Texas Instruments | PGA460-Q1 Automotive Ultrasonic Signal Processor and Transducer Driver (Rev. B) | Datasheet | Texas Instruments PGA460-Q1 Automotive Ultrasonic Signal Processor and Transducer Driver (Rev. B) Datasheet

Texas Instruments PGA460-Q1 Automotive Ultrasonic Signal Processor and Transducer Driver (Rev. B) Datasheet
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PGA460-Q1
SLASEC8B – FEBRUARY 2017 – REVISED JANUARY 2019
PGA460-Q1 Automotive Ultrasonic Signal Processor and Transducer Driver
1 Features
3 Description
•
•
The PGA460-Q1 device is a highly-integrated system
on-chip ultrasonic transducer driver and signal
conditioner with an advanced DSP core. The device
has a complimentary low-side driver pair that can
drive a transducer either in a transformer based
topology using a step-up transformer or in a directdrive topology using external high-side FETs. The
device can receive and condition the reflected echo
signal for reliable object detection. This feature is
accomplished using an analog front-end (AFE)
consisting of a low-noise amplifier followed by a
programmable time-varying gain stage feeding into
an ADC. The digitized signal is processed in the DSP
core for both near-field and far-field object detection
using time-varying thresholds.
1
•
•
•
•
•
•
•
•
•
•
•
•
Fully Integrated Solution for Ultrasonic Sensing
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Complimentary Low-Side Drivers With
Configurable Current Limit Supporting Both
Transformer Based and Direct Drive Topology for
Transducer Excitation
Single Transducer for Both Burst/Listen or a
Transducer Pair, One for Burst and the Other for
Listen Operation
Low-Noise Receiver With Programmable 6-Point
Time-Varying Gain (32 to 90 dB) With DSP (BPF,
Demodulation) for Echo Envelope Detection
Two Presets of 12-Point Time-Varying Threshold
for Object Detection
Timers to Measure Multiple Echo Distance and
Duration
Integrated Temperature Sensor
Record Time for Object Detection up to 11 m
128 Bytes of RAM for Echo Recording
42 Bytes of User EEPROM to Store Configuration
for Fast Initialization
One-Wire High-Voltage Time-Command Interface
or USART Asynchronous Interface
CMOS Level USART Interface
Sensor Diagnostics (Decay Frequency and Time,
Excitation Voltage), Supply, and Transceiver
Diagnostics.
2 Applications
•
•
•
•
•
•
•
•
•
Ultrasonic Radar
Automotive Park Assist
Lane-Departure and Collision Warning
Object distance and Position Sensing
Presence and Proximity Detection
Drone and Robotics Landing Assist and Obstacle
Detection
Automotive and Industrial Door-Opening Sensing
Automotive Motion Sensor for Intrusion Detection
Alarm
Occupancy and Motion Sensors
The main communication with an external controller is
achieved by either a time-command interface (TCI) or
a one-wire USART asynchronous interface on the IO
pin, or a CMOS-level USART interface on the RXD
and TXD pins. The PGA460-Q1 can be put in ultralow quiescent current low-power mode to reduce
power consumption when not in use and can be
woken up by commands on the communication
interfaces.
The PGA460-Q1 also includes on-chip system
diagnostics which monitor transducer voltage during
burst, frequency and decay time of transducer to
provide information about the integrity of the
excitation as well as supply-side and transceiver-side
diagnostics for overvoltage, undervoltage, overcurrent
and short-circuit scenarios.
Device Information(1)
PART NUMBER
PGA460-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram (Transformer Drive)
VIN
VPWR
OUTA
IO
OUTB
CT
100 nF
To ECU/
BCM
100 …F
TXD
To MCU
(optional)
RXD
INP
C(INP)
AVDD
IOREG
100 nF
INN
C(INN)
DECPL
100 nF
GND
GNDP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PGA460-Q1
SLASEC8B – FEBRUARY 2017 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
5
5
5
6
6
6
7
7
7
7
7
8
8
8
9
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Internal Supply Regulators Characteristics...............
Transducer Driver Characteristics ............................
Transducer Receiver Characteristics........................
Analog to Digital Converter Characteristics ..............
Digital Signal Processing Characteristics .................
Temperature Sensor Characteristics ......................
High-Voltage I/O Characteristics.............................
Digital I/O Characteristics .......................................
EEPROM Characteristics........................................
Timing Requirements ..............................................
Switching Characteristics ........................................
Typical Characteristics ............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
7.5
7.6
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
10
11
11
54
54
57
Application and Implementation ...................... 105
8.1 Application Information.......................................... 105
8.2 Typical Applications .............................................. 105
9 Power Supply Recommendations.................... 111
10 Layout................................................................. 112
10.1 Layout Guidelines ............................................... 112
10.2 Layout Example .................................................. 112
11 Device and Documentation Support ............... 113
11.1 Documentation Support ......................................
11.2 Receiving Notification of Documentation
Updates..................................................................
11.3 Community Resources........................................
11.4 Trademarks .........................................................
11.5 Electrostatic Discharge Caution ..........................
11.6 Glossary ..............................................................
113
113
113
113
113
113
12 Mechanical, Packaging, and Orderable
Information ......................................................... 113
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2017) to Revision B
Page
•
Changed Functional Block Diagram's GND and GNDP pin designators for correct grounding of the Output Driver. ......... 11
•
Updated tablenotes of Table 3 ............................................................................................................................................. 38
•
Added sentence: USART Synchronous Mode is identical to a Serial Peripheral Interface (SPI) without a chip-select
because the addressing is handled by the three-bit UART_ADDR value to enable up to eight devices on a single bus. .. 43
•
Added sentence: The temperature measurement's sample and conversion time requires at least 100 us after the
temperature measurement command is issued. Do not send other commands during this time to allow the
temperature value to properly update................................................................................................................................... 51
Changes from Original (February 2017) to Revision A
Page
•
Added zero padding information to the CONFIGURATION/STATUS Command section.................................................... 32
•
Changed UART interface parameter text from: 1 stop bit to: 2 stop bit .............................................................................. 34
•
Changed interfield wait time text from: optional to: required for 1 stop bit ........................................................................... 34
•
Added sentence: The sync field (0x55) is not included as part of the checksum calculation. ............................................. 37
•
Updated content and added tablenotes to Table 3 .............................................................................................................. 38
•
Added sentence: The diagnostic field is included in the slave generated checksum calculation. ...................................... 41
•
Added subsection Direct Data Burst Through USART Synchronous Mode......................................................................... 47
•
Added Equation 8 ................................................................................................................................................................. 52
•
Added sentence: This includes all threshold timing and level values. ................................................................................ 54
•
Updated UART and USART Communication Examples content ......................................................................................... 57
•
Updated content in Table 101 ........................................................................................................................................... 107
•
Added content to Application Curves ................................................................................................................................. 109
2
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•
Added content to Direct-Driven (Transformer-Less) Method and changed Figure 141 such that a GND node is
present at XDCRNegative and CINN ....................................................................................................................................... 110
•
Changed text from: TDK EPCOS B78416A2232A03 Transformer, muRata MA40H1S-R transducer to: Fairchild
FDC6506P p-channel MOSFET, muRata MA40H1S-R transducer ................................................................................... 111
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
GND
1
16
AVDD
INP
2
15
VPWR
INN
3
14
IOREG
GND
4
13
DECPL
OUTA
5
12
SCLK
GNDP
6
11
RXD
OUTB
7
10
TXD
IO
8
9
TEST
Not to scale
Pin Functions
PIN
NO.
1
NAME
TYPE (1)
DESCRIPTION
GND
P
Ground
2
INP
I
Positive transducer receive
3
INN
I
Negative transducer receive
4
GND
P
Ground
5
OUTA
O
Transducer driver output A
6
GNDP
P
Power ground
7
OUTB
O
Transducer driver output B
8
IO
I/O
Time-command interface data input and output
9
TEST
I/O
Test output pin
10
TXD
O
USART interface transmit
11
RXD
I
USART interface receive
12
SCLK
I
USART synchronous-mode clock input
13
DECPL
O
Decoupling transistor gate drive
14
IOREG
P
I/O buffer voltage regulator capacitor
15
VPWR
P
Power-supply voltage
16
AVDD
P
Analog voltage-regulator capacitor
(1)
4
I = input, O = output, I/O = input and output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VPWR
–0.3
30
IO
–0.3
30
INP, INN
–0.3
2
V
TEST, SCLK, RXD
–0.3
5.5
V
AVDD
–0.3
2
IOREG, DECPL, TEST, TXD
–0.3
5.5
OUTA, OUTB
–0.3
30
Ground voltage
GNDP, GND
–0.3
Sink current
OUTA, OUTB
Input voltage
Output voltage
V
V
0.3
V
500
mA
Operating junction temperature
–40
125
°C
Storage temperature, Tstg
–40
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
IEC 61000-4-2 contact discharge
(1)
UNIT
±2000
Corner Pins (1, 8, 9, 16)
±750
All Other Pins
±500
IO pin
±8000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
MAX
6
15
V
6
28
V
–0.1
VPWR
V
–0.1
0.9
V
RXD, TEST, SCLK
–0.1
VIOREG
V
GNDP, GND
–0.1
0.1
V
500
µA
VVPWR_XF
Supply input for transformer topology
VVPWR_DD
Supply input for direct drive topology
VIO
IO pin
IO
VINx
Transducer receive input
INP, INN
VDIG_IO
Digital I/O pins
VGND
Ground pins
ILPM
IBURST
VPWR Input current
Low Power Mode Enabled
During Ultrasonic Burst
UNIT
500
mA
TA
Operating free-air temperature
–40
105
°C
TJ
Operating junction temperature
–40
125
°C
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6.4 Thermal Information
PGA460-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
96.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.6
°C/W
RθJB
Junction-to-board thermal resistance
42
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
41.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Internal Supply Regulators Characteristics
PARAMETER
VAVDD
TEST CONDITIONS
Internal analog supply voltage
IAVDD = 5 mA
MIN
TYP
MAX
1.74
1.8
1.9
IVPWR_RX_ONL Supply current from VPWR pin during
listen only mode.
Y
VVPWR = 14 V; no bursting; Listen only
active
VIOREG_33
VTEST = 0 V during power-up ; IIOREG =
2 mA
2.95
3.3
3.65
VTEST ≥ 2 V during power-up ; IIOREG =
2 mA; VVPWR > 7.5 V
4.45
5
5.65
Digital IO supply voltage
VIOREG_50
ILIM_AVDD
AVDD current limit
AVDD short to GND
ILIM_IOREG
IOREG current limit
IOREG short to GND
VOV_AVDD
AVDD overvoltage threshold
VUV_AVDD
AVDD undervoltage threshold
VOV_IOREG_33
IOREG overvoltage threshold
VUV_IOREG_33
VUV_IOREG_50
VOV_VPWR
IOREG undervoltage threshold
VPWR overvoltage threshold
VUV_VPWR
VPWR undervoltage threshold
tON_REG
AVDD and IOREG power-up time
12
UNIT
V
mA
V
40
150
mA
10
50
mA
1.95
2.3
V
1.29
1.53
V
VTEST = 0 V during power-up
3.6
4.6
V
VTEST = 0 V during power-up
2.57
2.9
VTEST ≥ 2 V during power-up
3.8
4.5
VPWR_OV_TH = 0x0
11
12.3
15
VPWR_OV_TH = 0x1
16
17.7
21
VPWR_OV_TH = 0x2
21.5
22.8
27
VPWR_OV_TH = 0x3
27
28.3
31
5.25
VVPWR = 6 V
V
V
6
V
10
ms
6.6 Transducer Driver Characteristics
PARAMETER
VCLAMP_DRV
TEST CONDITIONS
MIN
Driver clamping voltage
Driver switched off
IPULSE_MAX_DRV
Maximum driver pulse current
VOUTA,VOUTB = 6 V:
FSW = 30 kHz; TA =
105°C
RDSONDRV
MOSFET on resistance
IDRAIN = 500 mA: TA =
105°C; DIS_CL=1
EDIS_BURST
Energy dissipated during burst
ILEAK_DRV
Leakage current
VOUTA,VOUTB=14 V
–1
ICLAMP_DRV_0
Current clamping range for minimum
code setting
VVPWR>7
V;CURR_LIM1 =
CURR_LIM2= 0
15
ICLAMP_DRV_63
VVPWR>7
Current clamping range from maximum
V;CURR_LIM1 =
code setting
CURR_LIM2= 63
ISTEP_SIZE_CLAMP_DRV
Step size (change in current from
value at previous step)
6
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TYP
MAX
30
UNIT
V
500
4.8
mA
8
Ω
6.4
mJ
1
µA
50
75
mA
450
500
570
mA
5.2
7.2
9.2
mA
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Transducer Driver Characteristics (continued)
PARAMETER
fSW_LOW
TEST CONDITIONS
Configurable switching frequency
fSW_HIGH
MIN
TYP
MAX
FREQ_SHIFT = 0
30
80
FREQ_SHIFT = 1
180
480
TEST CONDITIONS
MIN
UNIT
kHz
6.7 Transducer Receiver Characteristics
PARAMETER
Total receiver amplification gain
range
GAINRNG_TOT_RCV
GAINRNG_RCV
Receiver amplification gain
GAINNSTEP_RCV
Gain adjustment steps
GAINSTEP_SIZE_RCV
Gain adjustment step size
MAX
32
90
AFE_GAIN_RNG = 0x03
32
64
AFE_GAIN_RNG = 0x02
46
78
AFE_GAIN_RNG = 0x01
52
84
AFE_GAIN_RNG = 0x00
58
UNIT
dB
90
64
0.2
GAINTHRM_DRFT_RCV
Gain thermal drift
FSW = 30 kHz; TA = –40°C
to +105°C; Gain = 58.5
dB
ZINP_RCV
Input impedance
FSW < 80 kHz
Noise floor
FSW = 58 kHz; TA =
105°C; BW = 4 kHz
NRCV
TYP
FSW = FSW_LOW,FSW_HIGH;
TA = –40°C to +105°C
0.5
–3.5%
0.8
dB
3.5%
300
kΩ
7
nV/sqrt(Hz)
6.8 Analog to Digital Converter Characteristics
PARAMETER
VINP_ADC
Input voltage range
VREF_ADC
Voltage reference
NADC
Resolution
tCONV
Conversion time
TEST CONDITIONS
MIN
TYP
0
MAX
VAVDD
VAVDD
UNIT
V
12
Bits
1
µs
6.9 Digital Signal Processing Characteristics
PARAMETER
TEST CONDITIONS
MIN
Normalized to driver
frequency
TYP
FREQCENTER_BPF
Band-pass filter center frequency
BWBPF
Band-pass filter band width
NBPF
Band-pass filter adjustable steps
FREQSTEP_SIZE_BPF
Band-pass filter step size
FREQCUTOFF_LPF
Low-pass filter cutoff frequency
NLPF
Low-pass filter adjustable steps
4
FREQSTEP_SIZE_LPF
Low-pass filter step size
1
MAX
UNIT
8
kHz
1
2
4
2
1
kHz
4
kHz
kHz
6.10 Temperature Sensor Characteristics
PARAMETER
TRANGE_SENSE
TACC_SENSE
TEST CONDITIONS
Temperature sensor range
MIN
TYP
–40
VPWR=12
V;TEMP_GAIN = 0;
TEMP_OFF = 0
Range accuracy
MAX
UNIT
125
°C
5
°C
6.11 High-Voltage I/O Characteristics
PARAMETER
VIH_IO
High-voltage IO input high level
TEST CONDITIONS
IO pin
MIN
0.6 ×
VVPWR
TYP
MAX
UNIT
V
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High-Voltage I/O Characteristics (continued)
PARAMETER
TEST CONDITIONS
VIL_IO
High-voltage IO input low level
IO pin
VHYS_IO
High-voltage input hysteresis
IO pin
VOL_IO
High-voltage IO output low level
IO pin ; IIO = 10 mA
RPU_IO
High-voltage IO pullup resistance
IO pin
ILIM_IO
Current limit on high-voltage IO
Short to VPWR
MIN
TYP
0.05 ×
VPWR
4
MAX
UNIT
0.4 ×
VVPWR
V
0.175 ×
VPWR
V
10
40
2
V
16
kΩ
250
mA
MAX
UNIT
6.12 Digital I/O Characteristics
PARAMETER
TEST CONDITIONS
MIN
RX and SCLK pin;
VIOREG=VIOREG_33/VIOREG_50
TYP
0.7∗VIO
VIH_DIGIO
Digital input high level
VIL_DIGIO
Digital input low level
VHYS_DIGIO
Digital input hysteresis
RX and SCLK pin
VOH_DIGIO
Digital output high level
DECPL and TX pin; IDECPL/ITX = –2
mA; VIOREG=VIOREG_33/VIOREG_50
VOL_DIGIO
Digital output low level
DECPL and TX pin; IDECPL/ITX = 2mA
RPU_DIGIO_RX
Digital input pull-up resistance to
IOREG
RX pin
90
RPU_DIGIO_SC
Digital input pull-down resistance
SCLK pin
V
REG
RX and SCLK pin;
VIOREG=VIOREG_33/VIOREG_50
0.3∗VIO
V
REG
100
mV
VIOREG
– 0.2
V
0.2
V
100
160
kΩ
80
100
130
kΩ
MIN
TYP
MAX
LK
6.13 EEPROM Characteristics
PARAMETER
TEST CONDITIONS
BytesEE
EEPROM memory size
Application and Device Internal
tRET_EE
EEPROM data retention time
TA = 105°C
CyclBURN_EE
EEPROM burn cycles
tPROG_EE
EEPROM programming time
64
UNIT
Bytes
10
Years
1000
Cycles
600
ms
6.14 Timing Requirements
MIN
NOM
MAX
UNIT
TIME COMMAND INTERFACE
tBIT_TCI
Bit period
225
300
375
µs
tBIT0_TCI
Logical 0 bit length
150
200
250
µs
tBIT1_TCI
Logical 1 bit length
75
100
125
µs
tBLP1_TCI
BURST/LISTEN (Preset1) command period
328
400
472
µs
tBLP2_TCI
BURST/LISTEN (Preset2) command period
920
1010
1100
µs
tLP1_TCI
LISTEN only (Preset1) command period
697
780
863
µs
tLP2_TCI
LISTEN only (Preset2) command period
503
580
657
µs
tCFG_TCI
Device configuration command period
1170
1270
1370
µs
tTEMP_TCI
Temperature measurement command period
1440
1550
1660
µs
tNOISE_TCI
Noise level measurement command period
2070
2200
2340
µs
tDT_TCI
Command processing dead-time
75
100
125
µs
USART ASYNCHRONOUS INTERFACE
tBIT_UART
Logical bit length at 19.2 kbps
45.5
52.08
58.6
µs
tBITF_UART
Logical bit length at 115.2 kbps
7.6
8.68
9.76
µs
55
125
USART SYNCHRONOUS INTERFACE
tBIT_USART
8
Logical bit length at 8 Mbps
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6.15 Switching Characteristics
MIN
TYP
MAX
UNIT
fCORE_CLK
PARAMETER
Core frequency (1)
15.5
16
16.5
MHz
ACCCORE_CLK
Core frequency accuracy (2)
–4%
BaudUART
USART asynchronous interface baud
rate
BaudUSART
USART interface synchronous mode
baud rate
(1)
(2)
TEST CONDITIONS
2.4
4%
19.2
131.5
kbps
8
Mbps
At Room Temperature (25°C)
Across Operating Temperature Range (-40°C to 105°C)
6.16 Typical Characteristics
10 pulses, 400-mA current limit, 58.6-kHz driving frequency
90
100
OUTA Gate Driver
OUTB Gate Driver
70
Transducer Driving Voltage
60
50
40
Voltage (V)
Voltage (V)
30
10
-10
-30
20
0
-20
-40
-50
-60
-70
-90
-10
LNA Analog Output
Transducer Voltage
80
-80
10
30
50
70
90 110
Time (us)
130
150
170
190
-100
-100
400
D006
TDK EPCOS B78416A2232A003 transformer
muRata MA58MF14-7N transducer
OUTA/B Gate Driver is scaled up by 10 times
Figure 1. Driver Stage and Resulting Transducer Behavior
900
1400 1900 2400
Time (us)
2900
3400 3800
D007
TDK EPCOS B78416A2232A003 transformer
muRata MA58MF14-7N transducer
LNA analog output is scaled and shifted. Actual signal is 100 times
smaller and common mode is shifted up by 0.9 V
Figure 2. Receiver AFE Output Post-LNA
Object at 35 cm
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7 Detailed Description
7.1 Overview
The PGA460-Q1 device is a signal-conditioning and transducer-driver device for ultrasonic sensing for object or
distance sensing. The output driver consists of complimentary low-side drivers capable of driving a center-tap
transformer to generate large excitation voltages across an ultrasonic transducer and as a result create the
desired sound pressure level (SPL). The output driver can also be configured to be used in direct-drive mode
without a transformer using external FETs. The output driver implements configurable current limit for efficient
driving of the transformer and configurable bursting frequencies and burst length to be compatible with a large
number of transducers.
The analog front-end (AFE) can sense the received echo from the transducer and amplify it for correct object
detection. The AFE implements a low-noise amplifier followed by a time-varying gain amplifier that allows signals
from objects at a variable distance to be amplified correspondingly. This implementation allows for the maximum
dynamic range of the ADC to be used for both near-field and far-field objects in the same recording. An
embedded temperature sensor can be used to calibrate the signal conditioner for changes in temperature. The
digital signal processing path further filters the received echo and uses time-varying thresholds for accurate
detection of objects. Two presets for both bursting and thresholds are available which allow faster detection
cycles by saving time required to configure the device between multiple bursts. Most configuration parameters
are stored in nonvolatile memory for quick power up, which reduces initialization time.
The PGA460-Q1 device provides multiple IO protocols to communicate with the master controller. The device
provides a time-command interface and one-wire UART on the VPWR reference IO pin. It also provides both
synchronous and asynchronous USART on the TXD, RXD, and SCLK pins.
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7.2 Functional Block Diagram
VPWR
IOREG
AVDD
IO B uffer
Voltage
Regula tor
Ana log
Voltage
Regula tor
Control Logic
IO
TXD
OUTA
OUTB
Inte rface
RXD
SCLK
Bur st Freq uency
Pulse Gen erator
EEP RO M
Curren t Limit Sel ect
Gai n S elect
GND
Output Dri ver
Diagno stics
DECPL
TOF Capture
Temperature Sen se
TEST
Digital Signal Pro cessing
Ana log-to-Digital
Converter
(ADC)
INP
Mux
Low-Noise
Amplifier
INN
GNDP
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
7.3 Feature Description
7.3.1 Power-Supply Block
The PGA460-Q1 device uses multiple internal regulators as supplies for the internal circuits. The analog voltage
regulator (AVDD) requires an external capacitor of 100 nF. The power-supply block generates precision voltage
references, current bias, and an internal clock. An additional regulator (IOREG) generates the supply voltage for
the USART pins (RXD, TXD, and SCLK), DECPL pin, and TEST pin for their digital functionality. The AVDD and
IOREG regulators are not intended to support any external load. The external capacitors are recommended to be
placed as close as possible to the related pins (AVDD and IOREG). The PGA460-Q1 device starts to power up
when a voltage is applied to the VPWR pin. The internal power-on reset (POR) is released when all regulator
supplies are in regulation and the internal clock is running. During low-power mode, the IOREG regulator is
powered up while the other regulators shut down to conserve power.
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Feature Description (continued)
7.3.2 Burst Generation
The PGA460-Q1 device has a programmable frequency for the burst and number of pulse by configuring the
FREQ and P1_PULSE/P2_PULSE registers.
Use Equation 1 to calculate the frequency of burst for a range of 30 kHz to 80 kHz (FREQ_SHIFT bit set to 0).
f(DRV) 0.2 kHz u f 30 kHz
where
•
f is the frequency which can be from 0 to 200 as defined in the FREQUENCY register.
(1)
The actual driving frequency of the output stage is derived from the core clock frequency using Equation 1 and
Equation 2
f(CORE _ CLK)
n
f(DRV)
where
•
n is the ratio by which the main oscillator f(CORE_CLK) is divided.
(2)
The PULSE_P1 and PULSE_P2 registers can range from 0 to 31. When set to a value of M that is greater than
0, the M pulse pairs are generated on the OUTA and OUTB outputs.
7.3.2.1 Using Center-Tap Transformer
The PGA460-Q1 device provides efficient burst generation by exciting the primary side of a center-tap
transformer connected on the OUTA and OUTB pins through the complementary low-side FETs operating in a
current limiting mode. The frequency of the burst is from 30 kHz to 80 kHz with the current limit from 50 mA to
500 mA. The frequency of the burst, the current limit for transformer primary current, and the number of burst
pulses can be controlled by using the FREQUENCY, CURR_LIM_P1, CURR_LIM_P12, PULSE_P1, and
PULSE_P2 parameters, respectively.
Figure 3 shows the functional block diagram for echo generation.
12
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Feature Description (continued)
VBAT
6 V to 18 V
VPWR
Pulse Count
Frequency
OUTA
OUTB
Burst Control
Current Limit
Copyright © 2017, Texas Instruments Incorporated
Figure 3. Echo Generation Block Diagram
7.3.2.2 Direct Drive
The complementary low-side drivers can be used in conjunction with an external PMOS FET to provide singleended direct excitation to the transducer. In this configuration, the internal FETs can be used in a RDSON mode
by disabling current limiting feature by setting the DIS_CL bit in the CURR_LIM_P1 register.
An additional dead-time feature can be used in this mode to eliminate the shoot-through currents between the
external PMOS FET and internal low-side FETs by configuring the PULSE_DT bit. The burst cycle period of the
low-side FETs remains unchanged; however, the deactivation time is reduced by the dead-time programmed
value. Figure 4 shows this case.
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Feature Description (continued)
t=1/f
t/2
t/2
FET_A
DT
2
DT
2
DT
2
ON
DT
2
OFF
FET_B
DT
2
DT
2
ON
DT
2
OFF
Figure 4. Echo Generation Dead-Time Adjustment
7.3.2.3 Other Configurations
When any of the P1_PULSE or P2_PULSE bits are set to 0, only the OUTA output generates a pulse, while the
OUTB output remains in the high-impedance (High-Z) state during this period. This configuration is used to
reduce the output voltage when only short distances are required to be detected.
•
•
NOTE
For higher frequency support, the device has an option to shift up the burst frequency
range which occurs by setting the FREQ_SHIFT bit in the CURR_LIM_P1 register.
When this bit is set, the burst frequency is 6 times higher of the burst frequency
selected by the FREQUENCY register. With this bit set, the range of burst frequencies
is from 180 kHz to 480 kHz with a step of approximately 1.2 kHz.
The maximum dead time setting should be less than or equal to t / 8 where t is burst
period.
7.3.3 Analog Front-End
The analog front-end (AFE) in the PGA460-Q1 device, shown in Figure 5, receives the reflected echo from the
object, amplifies it, and feeds it into a digital signal processing (DSP) data path for echo detection. Because the
received echo signal can vary amplitude (in millivolts for near objects and in microvolts for far objects), the first
AFE stage is a very low-noise balanced amplifier with a predetermined fixed gain followed by a variable gainstage amplifier with configurable gain from 32 dB to 90 dB. The amplified echo signal is converted into a digital
signal by a 12-bit analog-to-digital converter (ADC) and fed to a DSP processing block for further evaluation and
time-of-flight measurement.
The PGA460-Q1 AFE implements system diagnostics for sensing element (transducer) monitoring during the
burst and decay stage of the echo recording process in a way of measuring the maximum achieved voltage at
the transducer node and the frequency of oscillation at the transducer node. For more information on these
diagnostics, see the System Diagnostics section.
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Feature Description (continued)
Analog Front-End
Voltage
Diagnostics
Frequency
Diagnostics
Low-Noise
Amplifier
INP
INN
PGA
Amplifier
+
+
±
±
To Digital
2:1
Mux
12-bit
ADC
Temperature Sense
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Analog Front-End
The variable gain amplifier in the AFE implements a time-varying gain feature which allows the user to set
different static gains and also specify a gain profile for the echo listening process (echo record time). This feature
allows for a uniform amplification of echo signals from objects at different distances without saturating the ADC.
As an example, for closer objects, gain can be programmed lower initially in time and then increased during the
recording time to detect farther objects which have a very small echo signal. This feature helps in attaining
sufficient SNR after ADC conversion for all distances for accurate time of flight measurement.
The time-varying gain parameters are stored in the EEPROM memory and characterized by:
• The initial fixed-gain parameter, GAIN_INIT.
• A time-varying gain start-time value stored in the TVGAIN0 register.
• An array of 5 gain-varying cross points placed in the TVGAIN0 to TVGAIN6 registers.
Figure 6 shows an example plot of the time-varying gain.
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Feature Description (continued)
AFE
GAIN
0.5 dB
TVG Start Time
(TVG_T0, GAIN_INIT)
TVG Point 1
(TVG_T1, TVG_G1)
End of Record Time
(P1_REC or P2_REC)
Initial Gain
(0, GAIN_INIT)
TVG Point 5
(TVG_T5, TVG_G5)
TVG Point 3
(TVG_T3, TVG_G3)
TVG Point 4
(TVG_T4, TVG_G4)
TVG Point 2
(TVG_T2, TVG_G2)
t
Figure 6. Time-Varying Gain Assignment Example
The time value, TVG start time, is expressed in terms of absolute time, and all following TVG point times
(TVG_Tx parameters) are expressed as a delta time between the current and previous point. All gain values are
expressed in an absolute gain value in dB and are unrelated from each other. The final gain setting of TVG Point
5 (TVG_G5) will be kept constant until the end of the echo record time. The time-varying gain assignment is the
same for both presets. A linear interpolation scheme is used to calculate gain between two TVG points. The AFE
gain resolution is 0.5 dB typical.
NOTE
The time-varying gain changes during the recording are applied only on the record cycle
that follows. If the TVGAIN[0:6] registers programmed to 0x00, the time-varying gain
function of the PGA460-Q1 device is disabled and a fixed gain defined by the INIT_GAIN
register is applied. In this case, changing the INIT_GAIN register changes the gain of AFE
during the recording.
The offset on the time-varying gain is controlled through the two AFE_GAIN_RNG bits in DECPL_TEMP register.
For each of the four settings as defined in the Register Maps section, the gain can be varied from 0 to 32 dB
added on top of the offset.
7.3.4 Digital Signal Processing
The DSP block of the PGA460-Q1 device processes the digital data from the ADC to extract the peak profile of
the echo after which the output of the DSP is compared against the programmed threshold to measure the time
of flight for object distance calculation.
Figure 7 shows the data path of the DSP. Also, the output of the comparator can be deglitched by the
THR_CMP_DEGLTCH[7:4] bits in the DEADTIME register.
16
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SAT_TH
±
To decay time
diagnostics
+
Memory
Preset 2
Threshold
Map
Digital Signal Processing (DSP)²Temperature
16-sample
Averager
Scaling
(gain, offset)
Preset 1
Threshold
Map
To temperature
diagnostic
Mux
8MSB
Memory
From ADC
De-mux
Digital Signal Processing (DSP)²Ultrasonic Echo
12
Band-Pass
Filter
Rectifier
Peak Hold
Nonlinear
Scaling
Low-Pass
Filter
Digital
Gain
+
To UART
Object Timer
±
To TCI-IO
Pin Control
Figure 7. DSP Data-Path
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7.3.4.1 Ultrasonic Echo—Band-Pass Filter
The ultrasonic echo signal is an amplitude-modulated signal with an underlying carrier frequency equal to the
drive frequency of the ultrasonic transducer. The DSP band-pass filter block allows the frequencies outside of the
observed frequency band to be filtered out and therefore reducing the amount of noise influencing the ultrasonic
echo signal.
The center frequency of the filter is automatically adjusted based on the driving frequency set by the FREQ bit
while the bandwidth of the filter can be adjusted from 2 kHz to 8 kHz in steps of 2 kHz by setting the BPF_BW bit
in the INIT_GAIN EEPROM register.
The band-pass filter is a second-order Butterworth IIR type filter. On power up, the PGA460-Q1 device calculates
the coefficients and places them in the BPF_A2_xSB, BPF_A3_xSB, and BPF_B1_xSB registers. These
registers can be overwritten by the user to reconfigure the filter. However, if the FREQ or BPF_BW bit is
changed, the coefficient calculation sequence is rerun and the device rewrites these registers. In case the
FREQ_SHIFT bit is set to 1 (80- to 480-kHz driving frequency range), the band-pass filter coefficients are not
calculated automatically by the PGA460-Q1 device. In this case the MCU is required to write these values
through the UART or USART interface.
7.3.4.2 Ultrasonic Echo–Rectifier, Peak Hold, Low-Pass Filter, and Data Selection
The rectifier, peak extractor, and low-pass filter DSP blocks demodulate the echo signal while outputting a baseband representation to be compared against the programmed thresholds. These blocks are defined as:
Rectifier
This block outputs the absolute value of the input signal since the input signal can be positive and
negative in amplitude.
Peak hold
This block holds the peak value of the rectified signal for a specific amount of time required for the
low-pass filter to detect the peak amplitude of the signal.
Low-pass filter (LPF) This block removes any noise artifacts from the echo signal. The LPF is realized as a
first-order IIR type filter. The user can set the cutoff frequency by setting the LPF_CO bit in
CURR_LIM_P2 register from 1 kHz to 4 kHz with a step of 1 kHz.
On power up the PGA460-Q1 device calculates the values of the filter coefficients and places them in the
LPF_A2_xSB and LPF_B1_xSB registers, respectively. The user can overwrite the values in these registers and
reconfigure the filter. In this case, the PGA460-Q1 device does not take any action. However, if the LPF_CO bit
is changed, the coefficient calculation sequence must be rerun and the device repopulates these registers.
7.3.4.3 Ultrasonic Echo—Nonlinear Scaling
The nonlinear scaling block in the DSP data path provides exponential scaling (digital nonlinear amplification) for
the echo signal to achieve a higher SNR. This feature is useful for detecting long distance object where the
amplitude of the echo signal is very attenuated and close to the noise floor.
The nonlinear scaling block performs the following algorithm:
if (t Time _ Offset)
Output Input;
else
Output
(Input Noise _ Level)Scale _ Exponent ;
where
•
•
•
•
t is the current record time.
Time_Offset is set by the SCALE_N parameter and is used to select one of the time points corresponding to
threshold points, TH9, TH10, TH11, or TH12 defined in the Ultrasonic Echo—Threshold Data Assignment
section.
Scale_Exponent is the nonlinear exponent (1.5 or 2) and defined by the SCALE_K bit.
Noise_Level is the user-set noise level between 0 and 31 in 1 LSB step and defined by the NOISE_LVL bit. (3)
The SCALE_N, SCALE_K, and NOISE_LVL bits are EEPROM parameters in the DSP_SCALE register.
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NOTE
The nonlinear scaling block can be applied to Preset1 and Preset2.
7.3.4.4 Ultrasonic Echo—Threshold Data Assignment
The PGA460-Q1 threshold assignments are organized in two presets: Preset1 and Preset2. Both of these
presets have an independent memory map for threshold segment allocation. The PGA460-Q1 device supports
up to 12 threshold segments for each preset defined by the threshold segment points (TSP) in the
P1_THR_[0:15] registers for Preset1 and P2_THR_[0:15]registers for Preset2.
Figure 8 shows an example of a threshold assignment.
III
(TH_Px_T11,
TH_Px_L11)
(TH_Px_T10,
TH_Px_L10)
(TH_Px_T9,
TH_Px_L9)
(TH_Px_T8,
TH_Px_L8)
End of Record Time
(Px_REC)
II
(TH_Px_T12,
TH_Px_L12)
I
(TH_Px_T7,
TH_Px_L7)
Initial
Segment
(TH_Px_T6,
TH_Px_L6)
(TH_Px_T5,
TH_Px_L5)
(TH_Px_T3,
TH_Px_L3)
(TH_Px_T2,
TH_Px_L2)
..........................
24
16
8
0
±8
(TH_Px_T1,
TH_Px_L1)
255
247
239
(TH_Px_T4,
TH_Px_L4)
Threshold
Level
+7
±8
Offset Adjustment Range (TH_Px_OFF)
t
Figure 8. Threshold Assignment Example
As shown in Figure 8, each TSP is described in the (time, level) format while Px is the preset number (P1 for
Preset1, P2 for Preset2). Additionally, only the initial segment time parameter (TH_Px_T1) value is expressed in
terms of absolute time, while all following TSP times (TH_Px_Tx parameters) are expressed as a delta time
between the absolute time value of the previous TSP and the absolute time value of the current TSP. The level
values of each TSP (TH_Px_Lx parameters) are all expressed in an absolute LSB-level value and are unrelated
from each other. The TSP level threshold value at any given time moment is determined by the PGA460-Q1
device as a linear interpolation function between the two neighboring threshold segment points
As shown in Figure 8, the initial segment has a constant threshold value determined by the TH_Px_L1 parameter
until reaching the start of the first segment and also the 12th segment will have a constant threshold value
determined by the TH_Px_L12 parameter until reaching the end of record time defined by the Px_REC
parameter.
The TH_Px_L1 through TH_Px_L8 threshold parameters are 5-bits wide and the TH_Px_L9 through TH_Px_L12
parameters are 8-bits wide. These sizes help save memory space and at the same time allow higher resolution
for long-range detection of weak echo signals in presence of noise while keeping the range constant across all
TSPs. Because the TH_Px_L1 through TH_Px_L8 resolution is an 8 LSB, a threshold offset is defined to allow
finer adjustment of the threshold map for short-range detection.
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•
•
•
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NOTE
All calculated values of TSP after adding offset, if negative, are clamped to 0 before
linear interpolation which causes the slope of threshold curve to deviate from expected
value.
Both Preset1 and Preset2 threshold map parameters are protected by a CRC
calculation algorithm (Equation 6).
At power up or wakeup from low power mode, all threshold registers (Px_THR_XX)
and threshold CRC register (THR_CRC) are not initialized to the default value which
causes a CRC error and sets THR_CRC_ERR bit to 1. This occurrence indicates to
the MCU that the configuration is not loaded properly. Writing to threshold registers
reruns CRC calculation and updates the error bit.
7.3.4.5 Digital Gain
A digital gain feature after the low-pass filtering is implemented to improve the SNR of the received echo without
lowering the threshold values. Because this gain is applied after the band-pass and low-pass filtering, the digital
gain does not amplify the out of band noise. This gain feature can help in suppressing false detection such as
ground reflection and detecting farther objects with more accuracy.
Two sets of digital gain ranges are available: short range (SR) and long range (LR). The SR and LR gain levels
are set using the Px_DIG_GAIN_SR and Px_DIG_GAIN_LR parameters, respectively, in the Px_GAIN_CTRL
register independently for Preset1 and Preset2. The LR gain is applied starting from the threshold level point set
by Px_DIG_GAIN_LR_ST parameter to the end of the record period. The SR gain is applied from time zero to
the start of the selected LR-threshold level point.
To prevent false detection of an echo at the point in time where the digital gain is applied, the defined thresholds
are also changed as shown in the example plot in Figure 9. Here, the LR gain is applied starting from the
threshold level point 9. If the LR gain is different than the SR gain at threshold level point 8, the threshold level 8
is multiplied by the ratio between the LR gain and SR gain (DIG_GAIN_LR/DIG_GAIN_SR) 1 µs after the end of
the SR threshold level 9 point. Although this creates a discontinuity in the threshold level, the object detection is
not affected (a false threshold crossing is prevented) because the echo signal is also scaled by the same gain
ratio. After this point, the threshold level is changed to the next set threshold level (point 9 in example below)
using a linear interpolation scheme. The threshold levels should be adjusted by taking the digital gain and the
ratio between the LR and SR gains into account.
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Threshold
Level
255
Short range threshold level map
Digital Gain = Px_DIG_GAIN_SR
Long range threshold level map
Digital Gain = Px_DIG_GAIN_LR
T1, L1
T2, L2
T8 + 1 µs,
L8 × gm
192
T3, L3
T9, L9
128
T4, L4
T5, L5
T6, L6
T10, L10
T7, L7
64
T11, L11
T8, L8
T12, L12
EOR
0
t
Figure 9. Example of DIG_GAIN_LR_ST = [00] TH9
7.3.5 System Diagnostics
The system diagnostics in the PGA460-Q1 device help characterize the transducer element during the burst itself
and determine the status of the overall system. By using the provided information the system should be able to
detect transducer failure, driver-circuit failure (transformer failure if used), environmental effects on the system
(such as ice, dirt, snow), objects compromising the transducer operation (such as pressure applied to the
transducer), and others.
Three implemented system diagnostics are available in the PGA460-Q1 device that provide information which
can be used in detecting system flaws. These diagnostics are described as follows:
Voltage diagnostic measurement The voltage diagnostic feature is obtained by monitoring the current flowing
through the INP pin only when a BURST/LISTEN run command is executed. The transducer
excitation voltage at the particular burst frequency results in a current at INP pin that is compared to
a reference current with a current comparator as shown in Figure 10. If the excitation current
exceeds the threshold level set using the FVOLT_ERR_TH in FVOLT_DEC register, the current
comparator output goes high which implies a normal burst with the desired level of excitation
voltage. The measurement starts approximately 50 µs after the burst stage is started and ends at
the end of the burst stage. The result of this diagnostic measurement is reported in the status
frames of the IO time-command or the UART interface as described in the Interface Description
section.
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VPWR
INP
ISNS
COMP_OUT
IREF
Figure 10. Block Diagram for Voltage Diagnostic
V(diag) # 3.25E
03
§
u FVOLT_ERR_TH[2:0] u ¨ R(INP)
¨
©
1
6.28 u f(burst)
·
¸
u C(INP) ¸¹
where
•
•
•
•
FVOLT_ERR_TH[2:0] corresponds to 1 for 000b to 8 for 111b.
fburst is the burst frequency in kilohertz.
CINP is the input capacitance on the INP pin.
RINPis an optional resistor (See Figure 136) used for EMI and ESD robustness.
(4)
NOTE
Prior to bursting, the comparator output is expected to be low. In the event that the
output is stuck high, the condition is detected and the diagnostic fail flag is set
Transducer frequency measurement During the decay stage of the record interval a frequency measurement
on the transducer node is performed to validate the performance and proper tuning of the
transformer and transducer matching.
To measure the transducer frequency, a start parameter, FDIAG_START, and a window
length parameter, FDIAG_LEN, are defined in EEPROM memory. The start parameter,
FDIAG_START, defines the time when the frequency measurement starts relative to the end
of the burst time. The diagnostic window length parameter, FDIAG_LEN, sets the time width
of the diagnostic window in terms of signal periods captured. A brief example of parameter
configuration can be explained:
1. Assume FDIAG_START = 2 and FDIAG_LEN = 1. Referring to the Register Maps
section, the start time of these EEPROM parameters is determined to be 200 µs after
the burst is completed and window length of 3 signal periods. Assuming an operating
frequency of 58 kHz, the signal period is 17.24 µs and therefore the diagnostic ends at
200 µs + 3 × 17.24 µs = 251.72 µs after the burst is complete.
2. The frequency information captured in the measurement window is averaged and
expressed as a 500-ns time based counter value. The signal frequency can be
calculated using Equation 5.
f = 1 / (FDIAG_VAL × 500e–09)
where
•
FDIAG_VAL is a value that can be extracted using any of the device interfaces.
(5)
3. If the specified number of objects are detected before a frequency diagnostic
measurement completes, no frequency measurement results are saved. This can be
managed by setting the previously defined diagnostic parameters and threshold settings
for near-object detection.
An additional frequency error feature is implemented in the PGA460-Q1 device to signify that
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the measured transducer frequency is outside of the limits set by the FDIAG_ERR_TH
threshold parameter. The result of this feature is reported in the status frames of the IO timecommand or the UART interface. For more information on reporting the transducer frequency
error, see the Interface Description section.
Decay-period time capture During the decay stage of the record interval a transducer decay time measurement
is performed to verify correct operation of the transducer. This diagnostic in combination with the
transducer frequency measurement are commonly used in ultrasonic systems to detect external
blockage of the ultrasonic transducer.
The decay period time is measured at the output of the digital data path. The measurement
starts at the same time when the burst stage is completed and the decay period is measured
as long as the echo level is higher than a saturation threshold level defined in the EEPROM
by the SAT_TH parameter. The provided result can be extracted by using any of the
PGA460-Q1 interfaces, while the value is expressed in 16-µs time increments. If the decay
time measured greater than 4 ms, the value extracted will read 0xFF.
Noise level measurement An additional system diagnostic implemented in the PGA460-Q1 device is the noiselevel measurement diagnostic. The purpose of this function is to evaluate the surrounding noise
generated by other ultrasonic systems nearby to determine disturbances and also evaluate the
noise floor level when far distance objects are being detected.
During the noise-level measurement, the PGA460-Q1 device executes the LISTEN ONLY
(Preset2) command (see the Interface Description section for details of the command) where
no burst is performed but only a record interval is started and lasts 8.192 ms. During this
record interval, the data collected at the output of the digital data path is averaged into two
groups each containing 4096 samples. The final noise level is measured by performing the
noise-level measurement function is the higher averaged value of the two groups. This value
is reported as the final noise-level measurement.
NOTE
The nonlinear scaling block is always disabled (scale factor EEPROM by setting the
SCALE_K bit 0 and the NOISE_LVL bit to 0) during the noise-level measurement
process.
Figure 11 shows the system diagnostics implemented in the PGA460-Q1 device as a full object-detection record
cycle example. The numbers 1, 2, and 3 in Figure 11 show voltage diagnostic, transducer frequency, and decayperiod measurement, respectively.
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OUTA
Digital Data-Path Output
Analog Front End Input (INP ± INN)
OUTB
BURST
ECHO DETECTION
DECAY
1
2
VPP
tr = 1 / fr
3
tdecay
SAT_TH
time
Figure 11. Systems Diagnostics Example
7.3.5.1 Device Internal Diagnostics
The PGA460-Q1 device also offers Internal diagnostics against overvoltage (OV), undervoltage (UV), overcurrent
(OC), and thermal shutdown.
The OV, UV, and thermal shutdown conditions are reported through the status bits in the DEV_STAT1 register.
The OC protection is implemented on the device integrated regulators; however, the effect of this protection is
not reported. For proper operation and to avoid false triggering, all electrical diagnostics are passed through a
25-µs deglitch while the thermal shutdown diagnostic is passed through a 50-µs deglitch before being reported.
The OV and UV protection thresholds for the internal regulators are listed in the Specifications section. When a
fault is detected, the corresponding status bit is set and it is cleared upon interface read (clear-on-read type).The
input device supply on the VPWR pin defines a fixed UV-threshold level and adjustable OV-threshold level
(VPWR_OV_TH) that keeps the device active while disabling the output driver. This feature allows control of
power dissipation at high voltage inputs without damaging the driver. When a VPWR_UV flag is detected, any
presently running TCI command finish and no new TCI commands are executed until the undervoltage condition
is removed. This feature is not applicable to USART communication irrespective of the pins (RXD, TXD, or IO)
The thermal shutdown protection diagnostic monitors the temperature of the FETs of the low-side driver. In case
of a thermal shutdown event, the PGA460-Q1 device disables the output drivers and re-enables them when the
thermal shutdown condition is removed. After thermal shutdown recovery, the thermal shutdown status bit is set
to notify the user of the action taken.
NOTE
If the voltage on the VPWR pin is less than 5 V, the performance of the device is not
ensured as the digital core might reset. Any settings stored in the volatile memory section
of the register map will be cleared.
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7.3.6 Interface Description
The PGA460-Q1 device is equipped with two communication interfaces, each with a designated pin. The timecommand interface is connected to the IO pin which is an open-drain output structure with an internal 10-kΩ
pullup resistor capable of communicating at battery level voltage. The asynchronous UART interface can
communicate on the IO pin and is also connected to the RXD and TXD pins. A third Interface option is to use the
synchronous USART interface which is available only at the RXD and TXD pins. This communication uses SCLK
pin for a serial clock input and is the fastest data-rate mode. USART communication on RXD and TXD pins is
available at a 3.3-V or 5-V CMOS level depending on the configured IOREG voltage as described in the TEST
Pin Functionality section.
NOTE
Because the system is unlikely to simultaneously use both the time-command interface
and the UART interface, the PGA460-Q1 device can disable the IO pin transceiver to
preserve power. To do so, the IO_IF_SEL bit must be 0, and the IO_DIS bit must be 1
which immediately disables the IO pin transceiver upon which communication is only
possible through the RXD and TXD pins. Setting the IO_DIS bit back to 0 does not reenable the IO interface. If the IO_DIS bit was set unintentionally, the device can recover
the IO interface (reset the IO_DIS bit to 0) upon power-cycle; however, when the value of
this bit is programmed in the EEPROM, the PGA460-Q1 device always follows the
EEPROM-programmed value on power up.
7.3.6.1 Time-Command Interface
The time-command interface is the communication interface connected on the IO pin. The default state for the IO
pin when the interface is idle is HIGH (pulled up to VPWR). The pin communication is bi-directional, where upon
receiving a command, the PGA460-Q1 device is actively driving the IO pin and providing a response by changing
the state of the IO pin. If the time-command interface remains stuck while transmitting a command or data for a
particular command that is either LOW or HIGH for more than 15 ms, then the PGA460-Q1 communication
resets and is expected to receive a new command transmission from the master device.
The time-command interface is specified by five time commands, where four are classified as run commands and
one CONFIGURATION/STATUS command. Logic 0 is transmitted by pulling the IO pin low for a time duration of
tBIT0_TCI and logic 1 is transmitted by pulling the IO pin low for time duration of tBIT1_TCI as defined in the
Specifications section. Figure 12 and Figure 13 receptively show the general timing diagram for device time
commands and for logic bit timing. The t(DT_TCI) dead-time is defined for the PGA460-Q1 device to process the
received command and change the IO pin state from input to output.
t(COMMAND_TCI)
tDT_TCI
Figure 12. Time-Command Interface Command Timing
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Logic 0
tBIT0_TCI
tBIT_TCI
Logic 1
tBIT1_TCI
tBIT_TCI
Figure 13. Time-Command Interface Bit Timing
7.3.6.1.1 RUN Commands
The run commands are used for device run-time operation and are most commonly used during the normal
operation cycle of the PGA460-Q1 device. These device commands are specified by pulling the IO pull low for a
specified period of time as defined in the Specifications section. The following are classified as run commands:
Burst/Listen (Preset1) The device sends an ultrasonic burst using the P1_PULSE number of pulses while using
the CURR_LIM1 current-limit setting and runs an object-detection record interval defined by the
value of the P1_REC time length. During the process of object detection, the P1_THR_xx threshold
map is used for signal comparison. The nonlinear scaling DSP function is available for use with this
command.
Burst/Listen (Preset2) The device sends an ultrasonic burst using the P2_PULSE number of pulses while using
the CURR_LIM2 current-limit setting and runs an object-detection record interval defined by the
value of the P2_REC time length. During the process of object detection, the P2_THR_xx threshold
map is used for signal comparison. The nonlinear scaling DSP function is available for use with this
command.
Listen Only (Preset1) The device does not send an ultrasonic burst, however, and only runs an object-detection
record interval defined by the value of the P1_REC time length. During the process of object
detection, the P1_THR_xx threshold map is used for signal comparison. The nonlinear scaling DSP
function is available for use with this command.
Listen Only (Preset2) The device does not send an ultrasonic burst, however, but only runs an object-detection
record interval defined by the value of the P2_REC time length. During the process of object
detection, the P2_THR_xx threshold map is used for signal comparison. The nonlinear scaling DSP
function is available for use with this command.
Figure 14 shows the process of the communication of the IO pin run command.
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IO (V)
tDT_TCI
tDT_TCI
tDT_TCI
tDT_TCI
End of Record Time
(Px_REC)
tCOMMAND_TCI
VPWR
IO
Master IO
0
HI-Z
(Bus Idle)
OUT-LOW
(Run Cmd)
HI-Z
(Bus Idle)
INPUT
(Run Cmd)
INPUT
(Data Capture)
IN/OUT
OUT
OUT
OUT OUT-LOW
(Stat 1) (Stat 2) (Stat 3)
(Burst)
OUT-HIGH
HI-Z
(Bus Idle)
OUT-LOW
(Object)
OUT-HIGH
HI-Z
(Bus Idle)
Status Feedback
Figure 14. Time-Command Interface RUN Command Execution
The status field of the PGA460-Q1 device is embedded in the run command and provided back to the master
controller by extending the dead-time on the IO bus. The dead-time can be further extended for up to 3 × t(DT_TCI)
which signifies three status bits, STAT[1:3]. Each status bit has an assigned diagnostic and a priority as listed in
Table 1.
Table 1. Time-Command Interface Status Bits Description
STATUS BIT
PRIORITY
STAT 1
1, low
STAT 2
2
STAT 3
3, high
DESCRIPTION
Threshold settings uninitialized error
Frequency diagnostics error
Voltage diagnostic error
Power-up auto EEPROM CRC error
User triggered EEPROM download CRC error
As listed in Table 1, the STAT3 bit has the highest priority. When a STAT3 error condition is present, then the
dead-time is further extended by 3 × t(DT_TCI). In this case, if any STAT2 or STAT1 error conditions are also
present, these conditions are overruled by the higher priority of STAT3 error conditions. In a similar way, a
STAT1 condition is overruled by a STAT2 error condition in which case the dead-time is further extended by 2 ×
t(DT_TCI). When all STAT3 and STAT2 error conditions have cleared, a STAT1 condition further extends the deadtime by an additional t(DT_TCI).
The functions of the status bits can be explained as follows:
STAT 1
STAT 2
•
•
STAT 3
This status bit is set to 1 when both preset threshold register groups are uninitialized. Any run
command received over the TCI communications channel is not executed until either preset
threshold register group is programmed.
This status bit is set to 1 when any of the following occurs:
If the measured frequency value as described in the System Diagnostics section for frequency
diagnostics is higher or lower than the delta value defined by the FDIAG_ERR_TH parameter in the
EEPROM memory (this is consider to be a frequency diagnostic error).
If the measured voltage value as described in the System Diagnostics section for transducer voltage
measurement is lower than the level provided by the FVOLT_ERR_TH parameter in EEPROM
memory.
Any run command received over the TCI communications channel is not executed until the EE
CRC error is fixed.
The user can write to any EEPROM-mapped register to clear the error.
The user must reprogram the EEPROM to prevent the error upon another automatically or
manually triggered EEPROM download operation.
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When the device receives a run command, the IO pin is actively driven by the PGA460-Q1 device depending on
the final DSP output to indicate object detection. If, at any time, the processed echo signal exceeds the threshold
at that time, the IO pin is pulled low (GND, strong pulldown) otherwise the IO pin is pulled up by the internal 10kΩ (weak pullup) resistor. When the record time reaches the end of the record defined by the Px_REC
parameters, the IO pin is released (pulled up as an input) and the device is ready for a next command. Figure 15
shows the object detection functionality of the IO pin. The device pulls the IO pin low during the burst and then
releases it to provide a reference for the recording time-frame for the MCU. Knowing the time of reference, the
duration of the programmed burst and following falling edges for each object detected, the master controller or
MCU can calculate the object distance.
Threshold Level
Echo Signal (DSP Output)
End of Record Time
(Px_REC)
ULTRASONIC
DECAY
.......................
...
• 300 µs
ULTRASONIC BURST
255
247
239
24
16
8
0
t
IO [V]
VPWR
0
t
Figure 15. IO-Pin Object-Detection Signaling With Burst/Listen Time Command
255
247
239
Threshold Level
.......................
End of Record Time
(Px_REC)
Echo Signal (DSP Output)
24
16
8
0
t
IO [V]
VPWR
300 µs
0
t
Figure 16. IO-Pin Object-Detection Signaling With Listen-Only Time Command
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The PGA460-Q1 device forces IO pin to go low after the t(DT_TCI) time passes after receiving a run command for a
minimum of 300 µs which indicates start of the record period. This process occurs to provide the master
controller a reference edge to start the time of flight measurement and also for PGA460-Q1 device to separate
the response of the status (STAT) bits from the record cycle information. In general, the duration of burst for
lower frequency range followed by ringing causes the AFE to saturate and pull the IO pin low for more than 300
µs. For higher frequency burst or for listen-only command, or in situations where the saturation caused by the
ultrasonic burst might not be a higher value than the assigned threshold, as shown in Figure 16, the minimum
pulse width is 300 µs. With a certain filter and deglitch setting, a fake object can be detected directly after this
300-µs period.
7.3.6.1.2 CONFIGURATION/STATUS Command
The CONFIGURATION/STATUS command is used for the following:
• PGA460-Q1 internal parameter configuration
• Time-varying gain and threshold setup
• EEPROM programing
• Diagnostics and temperature measurements
• Echo data-dump function
When the CONFIGURATION/STATUS command is issued, the remaining data is transferred by using bit-like
communication where a logical 1 and logical 0 are encoded as shown in Figure 13. Figure 17 and Figure 18
show a full-length CONFIGURATION/STATUS command.
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......
......
IO [V]
tCOMMAND_TCI
tDT_TCI
tBIT_TCI
tBIT_TCI
tBIT_TCI
W/R
INDX3
INDX2
tBIT_TCI
tBIT_TCI
tDT_TCI
tDT_TCI
VPWR
.....
INDX1
INDX0
DATA
N
DATA
N±1
DATA0 CHK_SUM7
.....
CHK_SUM0
ACK
IO
Master IO
0
HI-Z
(Bus Idle)
OUT
LOW
OUT
HIGH
HI-Z
(Bus Idle)
Write/Read
Bit
DATA OUTPUT
OUT/IN
INPUT IN/OUT
HI-Z
(Bus Idle)
INPUT
IN/OUT
DATA
OUT/IN
OUTPUT
HI-Z
(Bus Idle)
Subcommand Index
Field
Data
Frame Checksum
Acknowledge
Figure 17. Time-Command Interface CONFIGURATION/STATUS Command—Write
IO (V)
......
......
tCOMMAND_TCI
tDT_TCI
tBIT_TCI
tBIT_TCI
tBIT_TCI
tBIT_TCI
tBIT_TCI
W/R
INDX3
INDX2
INDX1
INDX0
tDT_TCI
tBIT_TCI
tBIT_TCI
tDT_TC
VPWR
.....
DATA
N
.....
DATA0 CHK_SUM7
DATA
N±1
CHK_SUM0
IO
Master IO
0
HI-Z
(Bus Idle)
OUT
LOW
OUT
HIGH
OUTPUT
HI-Z
(Bus Idle)
INPUT
Write/Read
Bit
OUT/IN
INPUT
IN/OU
IN/OUT
OUTPUT
OUT/
Subcommand Index
Field
Data
Frame Checksum
Figure 18. Time-Command Interface CONFIGURATION/STATUS Command—Read
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As indicated, each CONFIGURATION/STATUS command frame consists of three data segments: subcommand
field, data field, and frame checksum. The subcommands are defined and ordered by a 4-bit index field, where
each subcommand can have a different data length in the data segment of the frame. Table 2 lists all PGA460Q1 subcommands ordered according to their respective index.
Table 2. Time-Command Interface Subcommand Description (1)
INDEX
0
1
2
3
4
DATA LENGTH (BITS)
ACCESS
EE
8
R
N
R
N
R/W
Y
18
R/W
Y
8
R/W
Y
124
R/W
N
124
R/W
N
R/W
Y
Temperature value
Transducer frequency diagnostic value
8
Decay period time diagnostic value
8
Noise level diagnostic value
8
Driver frequency (FREQ)
24
8
Number of burst pulses for Preset1 (P1_PULSE)
5
Number of burst pulses for Preset2 (P2_PULSE)
5
Threshold comparator Deglitch (THR_CMP_DEG)
4
Burst pulses dead-time (PULSE_DT)
4
Record time length for Preset1 (P1_REC)
4
Record time length for Preset2 (P2_REC)
4
5
Threshold assignment for Preset1 (P1_THR_0 to P1_THR_15) (2)
6
(2)
7
(1)
(2)
DESCRIPTION
Threshold assignment for Preset2 (P2_THR_0 to P2_THR_15)
Band-pass filter bandwidth (BPF_BW)
2
Initial AFE gain (GAIN_INIT)
6
Low-pass filter cutoff frequency (LPF_CO)
2
Noninear scaling noise level (NOISE_LVL)
5
Nonlinear scaling exponent (SCALE_K)
1
Nonlinear scaling time offset (SCALE_N)
2
Temperature-scale gain (TEMP_GAIN)
4
Temperature-scale offset (TEMP_OFF)
4
P1 digital gain start threshold (P1_DIG_GAIN_LR_ST)
2
P1 digital long-range gain (P1_DIG_GAIN_LR)
3
P1 digital short-range gain (P1_DIG_GAIN_SR)
3
P2 digital gain start threshold (P2_DIG_GAIN_LR_ST)
2
P2 digital long-range gain (P2_DIG_GAIN_LR)
3
P2 digital short-range gain (P2_DIG_GAIN_SR)
3
42
8
Time-varying gain Assignment (TV_GAIN0 to TV_GAIN6)
56
R/W
Y
9
User-data memory (USER_1 to USER_20)
160
R/W
Y
The acronyms used in this table (for example, CURR_LIM1) are the same as those used in the Register Maps section.
Including the threshold level offset parameter (TH_Px_OFF).
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Table 2. Time-Command Interface Subcommand Description(1) (continued)
INDEX
10
11
(3)
(4)
DESCRIPTION
DATA LENGTH (BITS)
Frequency diagnostic window length (FDIAG_LEN)
4
Frequency diagnostic start time (FDIAG_START)
4
Frequency diagnostic error time threshold (FDIAG_ERR_TH)
3
Saturation diagnostic level (SAT_TH)
4
P1 nonlinear scaling (P1_NLS_EN)
1
P2 nonlinear scaling (P2_NLS_EN)
1
Supply overvoltage shutdown threshold (VPWR_OV_TH)
2
Sleep mode timer (LPM_TMR)
2
Voltage diagnostic threshold (FVOLT_ERR_TH)
3
AFE gain range (AFE_GAIN_RNG)
2
Low-power mode enable (LPM_EN)
1
Decouple time and temperature select (DECPL_TEMP_SEL)
1
Decouple time and temperature value (DECPL_T)
4
Disable current limit (DIS_CL)
1
Reserved
1
Driver current limit for Preset1 (CURR_LIM1)
6
Driver current limit for Preset2 (CURR_LIM2)
6
Echo data-dump enable (DATADUMP_EN)
1
EEPROM programming password (0xD)
4
EEPROM programming successful (EE_PRGM_OK)
1
Reload EEPROM (EE_RLOAD)
1
Program EEPROM (EE_PRGM)
1
ACCESS
EE
46
R/W
Y
8
R/W
N
12
Echo data-dump values (3)
1024
R
N
13
EEPROM user-bulk command (0x00 to 0x2B) (4)
352
R/W
Y
14
Reserved
15
EEPROM CRC value (EE_CRC)
THR_CRC value (THR_CC)
16
R
Y
Echo dump memory is an array of 128 samples, 8 bits/sample.
For index 13, byte 0x2B is read-only, when an index-13 write command is sent, the byte-2B data field will have no effect on the
EE_CRC value.
The frame checksum value is generated by both the master and slave devices, and is added after the data field,
while calculated as the inverted eight bit sum with carry-over on all bits in the frame. The checksum calculation
occurs byte-wise starting from the most-significant bit (MSB) which is the read-write (R/W) bit in the PGA460-Q1
write operation while for PGA460-Q1 read operation, this is the MSB of the data field. In cases where the number
of bits on which the checksum field is calculated is not a multiple of eight, then the checksum operation pads
trailing zeros until the closest multiple eight is achieved. Zero padding is only required for the checksum
calculation. The zero-padded bits should not actually be transmitted over the IO-TCI interface.
The following example, is one example of a frame checksum calculation showing the PGA460-Q1 write operation
of for subcommand Index 7 (42 data bits):
• Total number of bits for checksum generation: 1 R/W bit, 4 bits index value, 42 bits data values. The total
number of bits is 47.
• Because the checksum is calculated byte-wise, 1 trailing zero is added to achieve 6 full bytes.
• Figure 19 shows additional checksum calculation.
The following example, is a second example of a frame checksum calculation showing the PGA460-Q1 read
operation of for subcommand index 8:
• Total number of bits for checksum generation by the PGA460-Q1 device: 56 bits data values + 8 command
bits. The total number of bits is 64.
• The 8 command bits are equal to 4-zero bits + Index[3:0] = 8 command bits which is the first byte used in the
checksum calculation.
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•
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No trailing zeros added because the number of bits is already 56 or 7 bytes.
Figure 19 shows additional checksum calculation.
Byte_1[7:0]
Byte_2[7:0]
Carry 1
+
SUM_1[7:0]
+
Byte_3[7:0]
Carry 2
SUM_2[7:0]
+
Carry 3
data_4[7:0]
SUM_3[7:0]
+
Carry (N±1)
data_5[7:0]
SUM_(N±1)[7:0]
Carry (N)
+
Byte_N[7:0]
Checksum[7:0]
+
SUM_N[7:0]
Invert
Figure 19. Checksum Calculation
In addition, when a PGA460-Q1 write operation is issued, the PGA460-Q1 device implements an
acknowledgment bit response to signify a correct data transfer occurred. In this case, if the
CONFIGURATION/STATUS command time period is not detected properly, the PGA460-Q1 device does issue
an acknowledgment bit. If the CONFIGURATION/STATUS command-time period is detected properly but the
checksum of the transferred frame is not correct, then the PGA460-Q1 device transmits a logical 0
acknowledgment. If the CONFIGURATION/STATUS command-time period is detected properly and the
checksum value matches the correct checksum, then the PGA460-Q1 device transmits a logical 1
acknowledgment.
In the case of a bit-like communication (PGA460-Q1 actively serving CONFIGURATION/STATUS command)
when the bit stream is interrupted with another time command (either RUN or CONFIGURATION), the PGA460Q1 device decodes this event as a bit-timed event in which case the execution of the initial
CONFIGURATION/STATUS command continues until either a time-out error event is reached or, in the case of a
continuous data transfer, the PGA460-Q1 frame checksum invalidates the incorrectly transferred frame. In the
case where the bit-stream is valid but is longer than expected, the PGA460-Q1 executes on the correctly
transferred frame but ignores the rest of the bit-stream.
If, during PGA460-Q1 IDLE state, the time-command interface receives a time command with pulse duration
outside the limits of any of the commands, this condition is ignored and the PGA460-Q1 device remains in the
IDLE state until a valid time command is received. In this case, the PGA460-Q1 does not respond with a
negative acknowledgment.
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7.3.6.2 USART Interface
7.3.6.2.1 USART Asynchronous Mode
The PGA460-Q1 device includes a USART digital communication interface. The main function of the USART is
to enable writes to and reads from all addresses available for USART access. This function include access to
most EEPROM-register and RAM-register memory locations on the PGA460-Q1 device. The USART
asynchronous-mode (UART) digital communication is a master-slave communication link in which the PGA460Q1 is a slave device only. The master device controls when the data transmission begins and ends. The slave
device does not transmit data back to the master device until it is commanded to do so by the master device. A
logic 1 value on the UART interface is defined as a recessive value (weak pullup on the RXD pin). A logic 0
value on the UART interface is defined as a dominant value (strong pulldown on the RXD pin).
The UART asynchronous-mode interface in PGA460-Q1 is designed for data-rates from 2400-bps to 115200-bps
operation, where the data rate is automatically detected based on the sync field produced by the master
controller. Other parameters related to the operation of the UART interface include:
• Baud rate from 2400 bps to 115 200 bps, auto-detected (as previously described)
• 8 data bits
• 1 start bit
• 2 stop bit
• No parity bit
• No flow control
• Interfield wait time (required for 1 stop bit)
tBIT_UART
tBIT_UART
..........
Start
Bit
LSB
D0
MSB
D1
D2
D3
D4
D5
D7
D6
tBIT_UART
tBIT_UART
Stop
Bit
Inter-Byte
Space
Start
Bit
..........
Figure 20. USART Asynchronous Interface Bit Timing
Figure 20 shows the bit timing for USART asynchronous mode. Both data and control are in little endian format.
Data is transmitted through the UART interface in byte-sized packets. The first bit of the packet field is the start
bit (dominant). The next 8 bits of the field are data bits to be processed by the UART receiver. The final bit in the
field is the stop bit (recessive). The combined byte of information, and the start and stop bits make up an UART
field. Figure 21 shows the standard field structure for a UART interface field.
stop bit
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
start bit
Standard field
Figure 21. UART Interface Packet Field
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A group of fields makes up a transmission frame. A transmission frame is composed of the fields required to
complete one transmission operation on the UART interface. Figure 22 shows the structure of a data
transmission operation in a transmission frame.
Sync field
Command
Field
1st Data
Field
Nth Data
Field
Checksum
Field
cmd[0:7]
data-1[0:7]
data-N[0:7]
chksm[0:7]
Inter-Field
Wait Time
(Optional)
Figure 22. UART Interface Transmission Frame
Each transmission frame must have a synchronization field and command field followed by a number of data
fields. The sync field and command fields are always transmitted by the master device. The data fields can be
transmitted either by the master or the slave depending on the command given in the command field. The
command field determines the direction of travel of the data fields (master-to-slave or slave-to-master). The
number of data fields transmitted is also determined by the command in the command field. The interfield wait
time is 1-bit long and is required for the slave or the master to process data that has been received, or when data
must change direction after the command field is sent and the slave device must transmit data back to the
master device. Time must be allowed for the master and slave signal drivers to change direction. If the UART
interface remains idle in either the logic 0 or logic 1 state for more than 15 ms, then the PGA460-Q1
communication resets and expects to receive a sync field as the next data transmission from the master device.
7.3.6.2.1.1 Sync Field
The sync field is the first field in every frame that is transmitted by the master. The sync field is used by the
PGA460-Q1 device to confirm the correct baud rate of the frame that is send by the master device. This bit width
is used to accurately receive all subsequent fields transmitted by the master. The bit width is defined as the
number of internal oscillator clock periods that make up an entire bit of data transmitted by the master. This bit
width is measured by counting the number of slave oscillator clocks in the entire length of the sync field data,
and then dividing by 8. Figure 23 shows the format of the sync field.
Sync Field
stop bit
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
start bit
Measured time
Figure 23. UART Sync Field
Consecutive sync-field bits are measured, including the start and stop bits, and compared to determine if a valid
sync field is being transmitted to the PGA460-Q1 device is valid. If the difference in bit widths of any two
consecutive sync field bits is greater than ±25%, then the PGA460-Q1 device ignores the rest of the UART
frame; essentially, the PGA460-Q1 device does not respond to the UART message.
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7.3.6.2.1.2 Command Field
The command field is the second field in every frame sent by the master device. The command field contains
instructions about what to do with and where to send the data that is transmitted to a particular PGA460-Q1
device. The command field can also instruct the PGA460-Q1 device to send data back to the master device
during a read operation. The number of data fields to be transmitted is also determined by the command in the
command field. Figure 24 shows the format of the command field.
Address and Command Field
stop bit
addr[2]
addr[1]
addr[0]
cmd[4]
addr[0:2]
cmd[3]
cmd[2]
cmd[1]
cmd[0]
start bit
cmd[0:4]
Figure 24. UART Command Field
In the PGA460-Q1 device, the last 3-bits of the command field are reserved for UART address information. The
address information in the command field is compared to the UART_ADDR parameter in the EEPROM memory
where the UART address is programmed. Upon receiving the command field, the PGA460-Q1 device checks if
the self-address matches the received address and if it matches, the device executes on the received command.
If the address does not match, the device disregards the received frame. For improved communication efficiency,
common broadcast commands are defined where the PGA460-Q1 device executes regardless of the address in
the command field. For these commands and all UART commands, see Table 3.
NOTE
The factory preprogrammed address for the PGA460-Q1 device is 0.
7.3.6.2.1.3 Data Fields
After the master device has transmitted the command field in the transmission frame, zero or more data fields
are transmitted to the PGA460-Q1 device (write operation) or to the master (read operation). The data fields can
be raw memory data or a command related parameters. The format of the data is determined by the command in
the command field. Figure 25 shows the typical format of a data field.
Data Field
stop bit
data[7]
data[6]
data[5]
data[4]
data[3]
data[2]
data[1]
data[0]
start bit
data[0:7]
Figure 25. UART Data Field
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7.3.6.2.1.4 Checksum Field
A checksum field is transmitted as the last field of every UART frame. The checksum contains the value of the
inverted byte sum with carry operation over all data fields and the command field (command field for master
only). On a master-to-PGA460-Q1 transmission, the checksum field is calculated by the master device and
checked by the PGA460-Q1 device. On a PGA460-Q1-to-master transmission, the PGA460-Q1 device generates
the checksum and the master validates the integrity. The format of the checksum is identical to the data field and
the procedure for calculating the checksum is explained in the Time-Command Interface section. Because the
UART interface is a byte-based interface, no zero padding occurs in the process of calculating the checksum.
When the master device calculates the checksum field, the calculation occurs on the UART command field
followed by all UART data fields that are transmitted as a part of the current communication frame. When the
PGA460-Q1 device is calculating the checksum field, the calculation includes the diagnostic data field (see the
Diagnostic Field section) followed by all UART data fields in the current frame. The sync field (0x55) is not
included as part of the checksum calculation.
7.3.6.2.1.5 PGA460-Q1 UART Commands
Table 3 lists the PGA460-Q1 UART commands.
NOTE
In the case where any command is improperly received by the PGA460-Q1 device, for
example a wrong command, wrong number of bytes, or wrong data byte values, then the
PGA460-Q1 device does not execute on the received command or set the Error_Status[4]
bit described in the Diagnostic Field section.
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Table 3. UART Interface Command List
CMD[4:0]
COMMAND NAME
PGA460-Q1
RESPONSE
M-TO-S
DATA BYTES
MASTER-TO-SLAVE DATA
BYTES DESCRIPTION
S-TO-M
DATA BYTES
SLAVE-TO-MASTER DATA
BYTES DESCRIPTION
SINGLE ADDRESS
(1)
(2)
(3)
(4)
38
0
Burst and listen (Preset1)
No
1
1
Burst and listen (Preset2)
No
1
2
Listen only (Preset1)
No
1
3
Listen only (Preset2)
No
1
4
Temperature and noise-level
measurement
No
1
0
Byte1: N - Number of objects to be
detected (valid range is from 1 to 8)
0
0
0
Byte1: 0 - Temperature measurement
1 - Noise Measurement
2–255 - Not used
0
Byte1–Byte2: Object 1 time-of-flight (µs)
(MSB, LSB)
Byte3: Object 1 width
Byte4: Object 1 peak amplitude
.
.
Byte(3 × N – 3) – Byte(3 × N – 2): Object N
time-of-flight (µs) (MSB, LSB)
Byte(4 × N – 1): Object N width
Byte(4 × N): Object N peak amplitude
5
Ultrasonic measurement
result (1) (2)
Yes
0
4×N
6
Temperature and noise level result
Yes
0
2
7
Transducer echo data dump
Yes
0
128
8
System diagnostics (3)
Yes
0
2
Byte1: Transducer frequency
Byte2: Decay period time
9
Register read
Yes
1
Byte1: Register address
1
Byte1: Register data
No
2
Byte1: Register address
Byte2: Register data
0
Yes
0
(4)
10
Register write
11
EEPROM bulk read
43
Byte1: Temperature value
Byte2: Noise level value
Byte1–Byte128: Echo data dump (array of
128 samples)
Byte1: USER_DATA1 data
.
.
Byte43: P2_GAIN_CTRL data
If command 5 is executed while the echo data dump bit is enabled, the read out data will either be invalid or out-of-date. Only the echo data dump memory can be filled, or the threshold
comparator be utilized per burst-and-listen or listen-only command.
To convert the object's time-of-flight in microseconds to distance in meters: distance (m) = [vsound × (MSB<<8 + LSB) ÷ 2 × 1µs] . For improved burst-and-listen accuracy, add the
additional burst offset to the originally calculated distance: distanceburst_offset (m) = [vsound × (Pulses / Frequency) ÷ 2 ]. The speed of sound is typically assumed to be 343m/s at room
temperature. Adjust the speed of sound as a function of ambient temperature: vsound= 331m/s + (0.6m/s/°C × Temperature(°C)).
If command 8 is executed before a run command, read out data is invalid.
For commands 10 and 22: Wait 60 µs if INIT_GAIN, TVG, THR or P1_GAIN_CTRL or P2_GAIN_CTRL is written to before a read, otherwise wait 3.3 µs for other functions.
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Table 3. UART Interface Command List (continued)
CMD[4:0]
COMMAND NAME
12
EEPROM bulk write
13
14
15
16
PGA460-Q1
RESPONSE
(5)
M-TO-S
DATA BYTES
No
43
Time-varying-gain bulk read
Yes
0
Time-varying-gain bulk write (5)
No
7
Threshold bulk read
Yes
0
Threshold bulk write
(5)
No
32
MASTER-TO-SLAVE DATA
BYTES DESCRIPTION
Byte1: USER_DATA1 data
.
.
Byte43: P2_GAIN_CTRL data
S-TO-M
DATA BYTES
0
7
Byte1–Byte6: TVGAIN0 - TVGAIN6 data
Byte1–Byte6 : TVGAIN0 - TVGAIN6 data
0
32
Byte1–Byte28: 1_THR_0 - 2_THR_15
data
SLAVE-TO-MASTER DATA
BYTES DESCRIPTION
Byte1–Byte32: P1_THR_0 - P2_THR_15 data
0
BROADCAST
17
Burst and listen (Preset1)
No
1
18
Burst and listen (Preset2)
No
1
19
Listen only (Preset1)
No
1
20
Listen only (Preset2)
No
1
Byte1: N - Number of objects to be
detected (valid range is from 1 to 8)
0
0
0
21
Temperature and noise-level
measurement
No
1
Byte1: 0 - Temperature measurement
1 - Noise measurement
2–255 - Not used
22
Register write (4)
No
2
Byte1: Register address
Byte2: Register data
0
43
Byte1: USER_DATA1 data
.
.
Byte43: P2_GAIN_CTRL data
0
(5)
No
0
23
EEPROM bulk write
24
Time-varying-gain bulk write (5)
No
7
Byte1–Byte6: TVGAIN0 - TVGAIN6 data
0
25
Threshold bulk write
No
32
Byte1–Byte32: 1_THR_0 - 2_THR_15
0
RESERVED
No
26–31
(5)
0
For commands 12, 14 16, 23, 24, and 25: Wait 50 µs before issuing a read command.
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7.3.6.2.1.6 UART Operations
7.3.6.2.1.6.1 No-Response Operation
The no-response operation on the UART interface is fairly straightforward. The command field specifies the
address and command for the operation, where the subsequent data bytes, if any, are to be stored in the
PGA460-Q1 device. The number of data bytes to be sent is predetermined by the UART command. The last field
in the frame is the checksum field which is generated by the master. Figure 26 shows an example of memory
register write operation (command 10).
Command
Field
1st Data
Field
2nd Data
Field
Write_Cmd
Write_addr
Write Data
chksm[0:7]
(To Slave)
(To Slave)
(To Slave)
(To Slave)
Sync field
(To Slave)
Checksum
Field
Inter-Field
Wait Time
(Optional)
Figure 26. UART No-Response Example
NOTE
If a NO-RESPONSE command arrives on the UART interface while another NORESPONSE command is also served or if the PGA460-Q1 device is busy performing
functions, then the previous command is aborted and the new command is served
immediately. This process is particularly important when the PGA460-Q1 device is running
a record interval because of any of the Command0 through Command4 or Command17
through Command21 being previously received while another command is received on the
UART. In this case, the PGA460-Q1 device aborts the previous command and terminates
the current record interval after which it initiates a new command serving cycle.
7.3.6.2.1.6.2 Response Operation (All Except Register Read)
The response operation of the PGA460-Q1 UART interface is initiated with the master sending a response
request. After the response request is received by the PGA460-Q1 device, the UART responds with the proper
data of the command being requested. In a response operation, the master does not generate a checksum Field,
rather it is generated by the PGA460-Q1.
NOTE
Because the data direction changes (master device to PGA460-Q1 followed by PGA460Q1 to master device) and because of the amount of processing time required by the
PGA460-Q1 device to respond, a response delay time of 1-bit period occurs between the
response request and the PGA460-Q1 response on the UART.
Figure 27 shows an example of the PGA460-Q1 response operation.
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Data changes direction between
command field and first Data field.
(Variable based on command)
Command
Field
Diag Data
Field
1st Data
Field
Nth Data
Field
Checksum
Field
RESP_CMD
Diag Data
data-1[0:7]
data-N[0:7]
chksm[0:7]
(To Slave)
(To Master)
(To Master)
(To Master)
(To Master)
Sync field
(To Slave)
Inter-Field
Wait Time
(Optional)
Inter-field
Wait Time
(1-bit period)
Figure 27. UART Response Example
7.3.6.2.1.6.3 Response Operation (Register Read)
Because the REGISTER READ command requires the master device to specify a register address in the
PGA460-Q1 memory, an additional frame type is defined where the master issues the sync and command fields
followed by the memory register address as the only byte field in the master frame and a master checksum as
the last field. Following the master-to-slave transmission, the PGA460-Q1 device responds with a standard
PGA460-Q1 Response Operation frame. Figure 28 shows this operation.
Data changes direction between
command field and first Data field.
(1 bit period)
Sync field
(To Slave)
Command
Field
Cmd 9 Addr
1st Data
Field
Reg_addr
Checksum
Field
chksm[0:7]
Diag Data
Field
Diag Data
1st Data
Field
data-1[0:7]
Nth Data
Field
data-N[0:7]
Checksum
Field
chksm[0:7]
(To Slave)
(To Slave)
(To Slave)
(To Master)
(To Master)
(To Master)
(To Master)
Inter-field
Wait Time
(Optional)
Inter-field
Wait Time
(1 bit period)
Figure 28. UART Register Read Response Example
NOTE
If a RESPONSE command arrives on the UART interface while another NO-RESPONSE
command is also served or if the PGA460-Q1 device is busy performing functions, then
the PGA460-Q1 device responds with a diagnostic field (see the Diagnostic Field section)
having an error status of 0 which denotes that the device is busy serving functions. If the
PGA460-Q1 is currently serving a RESPONSE command while another RESPONSE
command arrives, then the PGA460-Q1 device ignores the new RESPONSE command
until it is done serving the previous RESPONSE command.
7.3.6.2.1.7 Diagnostic Field
As described in the Response Operation (Register Read) section, the PGA460-Q1 device begins the response
transmission with a diagnostic data field. This field contains UART communication error bits. If a particular bit is
set to 1 then the associated communication error has occurred sometime between the last response operation
and the current response operation. After a response operation is performed, the communication error bits are
cleared. The diagnostic field is included in the slave generated checksum calculation. Figure 29 shows the
diagnostic data field.
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Diagnostic Field
stop bit
error status[7]
error status[6]
error status[5]
error status[4]
error status[3]
error status[2]
error status[1]
error status[0]
start bit
Diagnostic error status[0:7]
Figure 29. UART Diagnostic Data Field
Table 4 lists the diagnostic data error status bits.
The error status[7:6] bits in the diagnostic field are set to 01b so that the bit time transmitted by the slave can be
easily measured. If more error status is required, these bit locations can be used to transmit the additional error
status.
Table 4. UART Diagnostic Data Description
BIT
UART_DIAG = 0
Error status [0]
UART_DIAG = 1
PGA460-Q1 Device Busy
Sync field bit rate too high (>115200 bps)
Error status [1]
Threshold settings CRC error
Sync field bit rate too low (>115200 bps)
Error status [2]
Consecutive sync field bit widths do not match
Frequency diagnostics error
Error status [3]
Invalid checksum received from master
(essentially a calculated slave checksum does
not match the checksum transmitted by the
master)
Voltage diagnostics error
Error status [4]
Invalid command sent from master
Logic 0
•
•
Error status [5]
•
•
•
•
•
General communication error:
SYNC filed stop bit too short
Command filed incorrect stop bit (dominant
when should be recessive)
Command filed stop bit too short
Data field incorrect stop bit (dominant when
should be recessive)
Data field stop bit too short
Data field PGA460-Q1 transmit value
overdriven to dominant value during stop bit
transmission
Data contention during PGA460-Q1 UART
transmit
EEPROM CRC error or TRM CRC error
Error status [6]
Logic 1
Error status [7]
Logic 0
7.3.6.2.1.8 USART Synchronous Mode
For fast (8 Mbps) communication between the master MCU and the PGA460-Q1 device, a fast USART
synchronous mode is implemented. This mode uses and is only available on the RXD and TXD pins and is also
using the SCLK pin as a clock input for communication to the device. In this mode the USART interface acts as a
serial-shift register with data set on the rising edge of the clock and sampled on the falling edge of the clock.
Differently than the USART asynchronous mode, the synchronous mode communication frame does not include
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a start, stop, nor interfield wait bit which means that as soon as the data in one frame has completed, the next
communication data frame follows immediately. USART Synchronous Mode is identical to a Serial Peripheral
Interface (SPI) without a chip-select because the addressing is handled by the three-bit UART_ADDR value to
enable up to eight devices on a single bus. Figure 30 shows the bit timing in synchronous mode and Figure 31
shows the data flow for USART synchronous mode.
tBIT_USART
CLK
..........
..........
DATA
..........
LSB
MSB
..........
D0
D1
D2
D3
D4
D5
D6
D7
Figure 30. USART Synchronous Interface Bit Timing
DATA FRAME 1
DATA FRAME 2
DATA FRAME 3
CLK
...
DATA
...
LSB
D0
MSB LSB
D1
D2
D3
D4
D5
D6
D7
D0
MSB LSB
D1
D2
D3
D4
D5
D6
D7
D0
MSB
D1
D2
D3
D4
D5
D6
D7
time
Figure 31. USART Synchronous Mode Data Flow
As shown in Figure 31, each data frame is 8-bits long with little endian format (least significant bit [LSB] first). All
other functionality of the USART synchronous mode aligns with the USART asynchronous mode. Muxing of the
IO pin of the USART synchronous mode is not possible and the IO pin transceiver is disabled when the device is
communicating through USART in the case when the IO_IF_SEL bit is set to 1.
The PGA460-Q1 device can communicate in USART synchronous mode immediately when a rising clock on the
SCLK pin is detected. No activation or deactivation of this mode is available.
If this communication mode is not used, the SCLK pin should be connected to GND to prevent noise triggering
the clock input.
7.3.6.2.2 One-Wire UART Interface
The PGA460-Q1 device implements an option to connect the UART interface on the IO pin. In this case, the
UART interface becomes a battery-voltage one-wire interface (OWI) because the IO pin is an open-drain type
and implements a 10-kΩ pullup to the VPWR pin. This feature is possible because the communication on the
UART interface is unidirectional at all times.
To enable the one-wire UART interface the IO_IF_SEL bit must be set to 1, in which case the internal
communication multiplexers connect the digital logic of the UART interface to the IO-pin transceiver. The RXD
and TXD pins are not changed and their operation is preserved.
Although UART communication through the IO pin, RXD pin, and TXD pin is allowed simultaneously, a possibility
can occur for data collision in the case when the master controller is communicating to the IO pin while another
master-controlled is trying to communicate through the UART transceiver on the RXD and TXD pins. Therefore,
in an application where the IO pin is used, the RXD pin must be connected to the Hi-Z state which would cause
the UART transceiver to disable when the PGA460-Q1 device has been enabled. For a detailed explanation, see
the Interface Description section.
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NOTE
When UART sync mode is selected while the IO_IF_SEL bit is set to 1 (IO pin to UART
interface) the IO transceiver is disabled.
7.3.6.2.3 Ultrasonic Object Detection Through UART Operations
The PGA460-Q1 UART interface has the capability to record up to 8 objects that would cut the assigned
threshold. The result is expressed as a 1-µs interval time value from the time when the burst stage is complete
and the echo signal drops below the assigned threshold to the moment when any of the detected objects cut the
assigned threshold again. Additionally, the width of the echo signal that cuts the threshold and the peak
amplitude of the object is also measured and reported. If the object is detected at the end of record time, then
object width is reported as 0xFF.The width of the echo that cuts the threshold is expressed as 4-µs interval-time
values. When a LISTEN ONLY command is used, the object detection starting point is at the start time of the
record interval. Figure 32 and Figure 33 show an example of two objects being detected with BURST/LISTEN
and LISTEN ONLY commands, respectively. Object detection cannot occur when the DATADUMP_EN bit is set
to 1.
255
247
239
ULTRASONIC
DECAY
Peak
Amplitude1
Peak
Amplitude2
24
16
8
0
End of Record Time
(Px_REC)
Echo Signal (DSP Output)
ignored
......................
ULTRASONIC BURST
Threshold Level
t
tOBJECT1 (MSB, LSB)
tWIDTH1
tWIDTH2
tOBJECT2 (MSB, LSB)
Figure 32. UART Object Detection Signaling With Burst and Listen Command
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255
247
239
Threshold Level
.......................
Peak
Amplitude2
24
16
8
0
End of Record Time
(Px_REC)
Echo Signal (DSP Output)
Peak
Amplitude1
t
tOBJECT1 (MSB, LSB)
tWIDTH1
tWIDTH2
tOBJECT2 (MSB, LSB)
Figure 33. UART Object Detection Signaling With LISTEN ONLY Command
The comparison is done between the assigned threshold and the amplitude of the signal at the output of the DSP
data path. If the threshold level is higher in value than the signal amplitude then no object is being detected. If
the signal amplitude is higher in value than the threshold level denoting an echo reflection then an object is
detected and the time-mark is captured. When the record time reaches the end of the record defined by the
Px_REC parameters and the number of objects to be detected is still not achieved, the record interval is
complete and the undetected object locations are assigned a value of 0xFF. At this point the device is ready for
the next command which should be USART command 5. In case the number of objects to be detected is fulfilled
before the end of record interval, the device interrupts the record cycle because the number of objects has
already been detected and the device is ready for command 5. Issuing command 5 before issuing command 0 to
4 provides unpredictable data.
The following example shows how to use the PGA460-Q1 UART commands for object detection:
1. On PGA460-Q1 power up, the master configures the following:
– EEPROM by using the EEPROM bulk write command
– Time-varying gain by using the time-varying gain bulk write command
– Threshold parameters by using the threshold bulk write command or by independently writing to a
particular parameter by using the register write command
2. When the PGA460-Q1 device has been configured, the master device issues a run command with any of the
following commands:
– BURST/LISTEN (Preset1)
– BURST/LISTEN (Preset2)
– LISTEN ONLY (Preset1)
– LISTEN ONLY (Preset2)
Following a successful receive of any of the these run commands the PGA460-Q1 device immediately runs
the requested action.
3. When the record interval has expired, the master device can issue the ultrasonic measurement result
command to collect the data from the PGA460-Q1 device.
7.3.6.3 In-System IO-Pin Interface Selection
The PGA460-Q1 device is factory programmed with the time-command interface enabled on the IO-pin. In a
system where the end user uses the IO-pin in a one-wire UART mode, two possible options of enabling the onewire UART interface on the IO-pin are available as follows:
• If access to the UART RXD and TXD pins is possible then the user can set the IO_IF_SEL bit to 1 in the
EEPROM memory space and then execute an EEPROM program command to store the configuration for
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future use.
If access to the RXD and TXD pins is not possible (assuming the end product has already been assembled)
then the device can be toggled between interfaces by using the pattern on the IO-pin shown in Figure 34.
•
260 µs
321 µs
208 µs
364 µs
156 µs
416 µs
bit[7]
1
1
1
1
1
1
Inter-Field Wait Time
bit[6]
1
bit[7]
bit[5]
0
stop bit
bit[4]
0
bit[6]
bit[3]
0
bit[5]
bit[2]
1
bit[4]
1
bit[3]
1
bit[2]
1
bit[1]
1
bit[0]
1
Inter-Field Wait Time
0
start bit
0
stop bit
0
bit[1]
0
bit[0]
1
Inter-Field Wait Time
1
start bit
1
bit[7]
1
stop bit
1
bit[6]
bit[2]
0
bit[5]
0
bit[4]
0
bit[3]
0
bit[1]
0
start bit
UART data
stream
bit[0]
Time-Based
Interface
tBIT = 52 µs
Figure 34. IO-Pin Interface Toggle Pattern
As show in Figure 34, the data format is selected in a specific way so that a time-command interface and a
UART interface can easily reproduce the pattern. The following two scenarios are possible:
IO-Pin in time-command interface while the master device is in UART interface In this case the master
device can send a UART frame with the following data: 0xF0 followed by 0xF8 followed by 0xFC
while the UART baud-rate is 19200 bps.
NOTE
In this case the master device does not generate a sync field.
IO-Pin in UART interface while the master deivce is in time-command interface In this case the master
device generates three time-command pulses with time durations as shown in Figure 34.
As soon as the data is received by the PGA460-Q1 device, the interface on the IO-pin is toggled. The pattern in
Figure 34 toggles the value of the IO_IF_SEL bit in the EEPROM memory; however, it does not program the
EEPROM. Therefore, as soon as the PGA460-Q1 Interface is set to the target interface, the master controller
must issue a command to program the EEPROM with the desired configuration.
NOTE
In case of toggling the selection pattern for the IO interface option, a STAT2 bit is
triggered to 1. Upon reading, the STAT2 bit is cleared.
7.3.7 Echo Data Dump
7.3.7.1 On-Board Memory Data Store
The PGA460-Q1 device offers a data-dump function where the data at the output of the digital data path can be
extracted in a raw digital format. This function is usually required for the ultrasonic system to be properly tuned
and to make correct time-varying gain and threshold adjustments. Additional uses can include system evaluation
and testing.
The echo data-dump function can be enabled for any of the four BURST/LISTEN or LISTEN ONLY commands
and is enabled by the DATADUMP_EN bit in the EE_CNTRL register. When enabled, and upon receiving a
BURST/LISTEN or a LISTEN ONLY command, the PGA460-Q1 device holds the IO pin low for the entire record
interval thus signaling the master MCU that data-dump cycle is in progress. When the data-dump cycle is
complete the data can be extracted by the data dump read command. For more information on the PGA460-Q1
device commands, see Table 2.
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The data-dump memory is composed of a 128-byte data memory array. Echo data is down sampled to allow
capturing of the complete recording interval. The down sampling amount depends on the record time-length
parameter for the preset of interest set by the P1_REC and P2_REC bits in the REC_LENGTH EEPROM
register. During the process of down-sampling, a peak hold function is performed and therefore only the highest
level values after down-sampling are stored in the data-dump memory. When the DATADUMP_EN bit is 1, object
detection and measurement is disabled.
The following is a brief example to present the data dump implementation:
1. The DATADUMP_EN bit is set to 1.
2. The P1_REC bit is set to 0x01, which selects a record time-length interval of 8192 µs. Because the output
rate of the digital data dath is 1 µs/sample, the total record interval has 8192 samples.
3. When any of BURST/LISTEN (Preset1) or LISTEN ONLY (Preset1) commands is executed, one sample
location in the data-dump memory is written with the highest (peak) value of 8192 / 128 = 64 samples.
Therefore the first data-dump value is the highest value of the 0–63 sample range while the last data-dump
value is the highest value 8127–8191 sample range.
7.3.7.2 Direct Data Burst Through USART Synchronous Mode
In the case where each 1-µs Data-Path sample is needed to be extracted for further analysis, the PGA460-Q1
device offers a Test Mode where the Raw Digital data can be extracted at different points in the Digital data path
as shown in Figure 35. Data burst is enabled when DP_MUX value is greater than 0 and less than 5, then the
object detection and measurement is disabled.
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Digital Signal Processing (DSP)²Temperature
Command
8MSB
From ADC
1
2
1:2
MUX
16-sample
Averager
Scaling
(gain, offset)
Data Split
Byte1 = [7:0]
Byte2 = [3:0] [11:8]
Digital Signal Processing (DSP)²Ultrasonic Echo
0x3
MUX
Band-Pass
Filter
Rectifier
Peak Hold
Nonlinear
Scaling
Low-Pass
Filter
0x1
Test
Mux
CLK
CLK
DATA
TXD
8/1
Serializer
Digital
Gain
0x2
SAMPLE_SEL
0x4
DP_MUX
This feature is only possible in USART Synchronous Mode.
Figure 35. Direct Data Burst
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To enable this mode, the Digital Data-Path Mux can select the source signal to be burst out of the device by
setting the DP_MUX parameter in the device memory. Once the DP_MUX parameter is enabled (set to a value
other than 0x00), and if any of the SEND/RECEIVE, Receive Only or TEMPERATURE READ commands are
issued using the standard UART command method, the selected source signal is passed through the Digital
Multiplexer and Serialized by the 8/1 Serializer block. This signal is immediately outputted on the UART TXD pin
that now acts as a data output pin, while the master sends clock pulses to the CLK pin.
It is important that after issuing any of these commands the master does not stop sending clock pulses on the
CLK pin until the Bus is idle. Once a Checksum received is verified and the bus is idle, that is considered the end
of the Burst data. This is needed for proper data synchronization in the PGA460-Q1 device. For further
explanation on the USART Synchronous communication mode, see the USART Synchronous Mode section.
Figure 36 shows the format of the order of the data stream coming out of the PGA460-Q1 device.
Diag Data
Field
1st Data
Field
Nth Data
Field
Checksum
Field
Diag Data
data-1[0:7]
data-N[0:7]
chksm[0:7]
(To Master)
(To Master)
Figure 36. Direct Data Burst Data Format
As shown in Figure 36, the output data-stream starts with a PGA460-Q1 diagnostic data field, followed by
number of data bytes and ends with a checksum field calculated on the diagnostic data byte and all data bytes.
The number of data bytes depends on the number of samples extracted from the PGA460-Q1 device, which
depends on the Recording Time Interval of the current command. The recording time Interval is determined by
the P1_REC and P2_REC parameters in the EEPROM memory while the sampling rate of the ADC and digital
signal path is 1 µs / Sample. From here it can be calculated that the number of samples is equivalent to the
recording time when expressed in microseconds.
The digital output offers two modes of operation based on the SAMPLE_SEL parameter:
When SAMPLE_SEL = 0 The output of the data path is selected by the Digital Data-Path Test Mux and the
data length is 8 bits/sample long. For the LPF output , we now use the active digital gain select to
determine which 8 bits are sent out. For all the others, if the active digital gain select = 0 then we
get the 8 MSB bits, else the PGA460-Q1 sends the 8 LSB bits. In this case, the sample rate is 1us,
meaning every sample that the ADC outputs will also be sent out of the PGA460-Q1 device.
When SAMPLE_SEL = 1 The output of the data path is selected by the digital data path test mux. However, the
full 12bits/sample data length is sent out of the PGA460-Q1 device. In this case, the sample rate is
2 µs, meaning every 2nd sample produced by the ADC will be sent out. The 12 bit data is split into
two bytes and sent in the order LS Byte followed by the MS Byte. The MS Byte is padded with a 4
bit sample counter so that the master controller can track the order of samples from the PGA460Q1 device.
NOTE
For both of the previously listed options, the nonlinear scaling block is only enabled if the
data is extracted from the Low-Pass filter (DP_MUX = 0x1). In all other cases, the
nonlinear scaling block is disabled.
7.3.8 Low-Power Mode
The PGA460-Q1 device implements a low-power mode where the current consumption is significantly reduced to
preserve system power. The low-power mode feature is enabled by setting the LPM_EN bit in the EEPROM. If
this bit is set, the PGA460-Q1 device goes into low-power mode after a certain period of inactivity as defined by
the LPM_TMR bits in the FVOLT_DEC EEPROM register. Inactivity is defined when no activity occurs on the
communication interfaces such as commands to BURST/LISTEN, LISTEN ONLY, or to configure the device. Any
command causes a reset of the timer. During the programming of the EEPROM, the timer remains in reset.
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In low-power mode the PGA460-Q1 device can wake up in two different ways based on the interface used for
communication: time-command interface and USART interface. These ways are described in the following
sections.
7.3.8.1 Time-Command Interface
The device wakes up immediately after a deglitched falling edge on the IO pin is detected. The master controller
must generate a wake-up signal defined as a dominant pulse (logic 0) on the time command interface with a
length of at least 300 µs. After the wake-up pulse is complete, at least one command processing dead-time must
be allowed before starting a time-command pulse which is shown in Figure 37.
t(D)
t(CMD)
....
t(WAKE) > 300 µs
t > t(D)
Figure 37. Time Command Interface Wake-Up Pulse
7.3.8.2 UART Interface
The master device must generate a wake-up signal defined as a dominant pulse (logic 0) on the UART interface
with a length of at least 300 µs. After the wake-up pulse is complete, at least one inter-byte space must be
allowed before starting a UART transmission. Figure 38 shows an example of a UART wakeup.
Sync
field
tb
....
t(WAKE) > 300 µs
t > tb
Figure 38. UART Wake-Up Pulse
7.3.9 Transducer Time and Temperature Decoupling
7.3.9.1 Time Decoupling
The PGA460-Q1 device has the option to decouple the transducer from the transformer and the rest of the
driving circuitry during the echo detection stage of the record interval. The transducer is less exposed to noise
generated by the driving circuit during this process and is less loaded, meaning the detected echo is capable of
producing a higher voltage swing to be detected by the PGA460-Q1 device. For this function, the DECPL pin on
the PGA460-Q1 device is used that drives the gate (or base) of an external transistor, QDECPL. During the burst
and decay stages of the record interval the DECPL pin is high (3.3 V or 5 V depending on the IOREG level) and
enables the external transistor which then connects the transformer driving circuit to GND and couples it to the
transducer. The time-decoupling function is selected when the DECPL_TEMP_SEL bit in the EEPROM is set to
0.
When the burst stage is complete, a timer is started which times to the value defined by the DECPL_T bit in the
EEPROM. When this time has elapsed, the state of the DECPL pin becomes low (GND) which means that the
external transistor, QDECPL, is disabled which disconnects the transformer secondary coil from the transducer.
Figure 39 shows the circuit implementation.
7.3.9.2 Temperature Decoupling
Similarly to time decoupling, a temperature-decoupling function has been implemented in the PGA460-Q1 device
that can connect and disconnect a temperature-compensation capacitor at a certain temperature point to
compensate for the temperature nonlinearity of the transducer. By using this function, the transducer frequency is
assumed to remain within limits across temperature. To enable this function, the DECPL_TEMP_SEL bit must be
set to 1.
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Upon receiving a run command, the PGA460-Q1 device executes the TEMPERATURE MEASUREMENT
command first and compares the result with the temperature setting defined by the DECPL_T bit in the
EEPROM. If the temperature measured is higher than the value based on the DECPL_T bit, then the DECPL pin
is low (GND) causing the QDECPL transistor to be disabled and the temperature compensation capacitor to
disconnect. If the measured temperature is less than the value based on the DECPL_T bit, the DECPL pin is
high (3.3 V or 5 V depending on the IOREG level), the QDECPL transistor is enabled and the temperature
compensation capacitor is connected to the circuit. Figure 40 shows the circuit implementation.
VPWR
VIN
OUTA
CT
VIN
100 nF
IO
IO
VPWR
OUTA
IO
OUTB
CT
100 nF
IO
OUTB
100 …F
100 …F
DECPL
DECPL
INP
INP
C(INP)
AVDD
IOREG
INN
100 nF
100 nF
GND
C(INP)
AVDD
IOREG
C(INN)
GNDP
INN
100 nF
QDECPL
Figure 39. Transducer Time Decoupling
100 nF
GND
GNDP
C(INN)
QDECPL
Figure 40. Transducer Temperature Decoupling
7.3.10 Memory CRC Calculation
The PGA460-Q1 implements a cyclic redundancy check (CRC) that is a self-contained algorithm to verify the
integrity of the EEPROM stored data and threshold settings. When an EEPROM program or EEPROM-reload
operation is executed, or when a threshold register is written, the CRC controller calculates the correct CRC
value and writes it to the corresponding registers: For EEPROM memory, this value is written to the EE_CRC
register. For threshold settings, this value is written to the THR_CRC register.
A CRC is performed at power-up when an EEPROM reload command is issued. The CRC algorithm for all
memory blocks is the same and is shown in Equation 6 with an initial seed value of 0xFF and uses MSB
ordering. This calculation is performed byte wise starting from the MSB to the LSB. The data is concatenated as
follows:
•
•
For EEPROM memory: Concatenation starts with MSB USER_DATA1 (0x00) to LSB P2_GAIN_CTRL (0x2A)
and calculated CRC is stored in the EE_CRC register (0x2B)
For threshold settings: Concatenation starts with MSB P1_THR_0 (0x5F) to LSB P2_THR_15 (0x7E) and
calculated CRC is stored in the THR_CRC register (0x7F)
X8 + X2 + X + 1 (ATM HEC)
(6)
The results of the CRC check are stored in the DEV_STAT0 register and can be directly read through the UART
interface, while the time-command interface reports these in Status Bit3 and Status Bit1. For more information on
the time-command interface status bits, see the Time-Command Interface section. For the default values, see
the Register Maps section.
7.3.11 Temperature Sensor and Temperature Data-Path
The PGA460-Q1 device has an on-chip temperature sensor and a dedicated temperature data path for accurate
temperature measurement. The output value is provided as an unsigned 8-bit number from –40°C to +125°C.
The temperature sensor measurement can be used to adjust the variation of the transducer performance as the
ambient temperature changes. The temperature measurement's sample and conversion time requires at least
100 us after the temperature measurement command is issued. Do not send other commands during this time to
allow the temperature value to properly update.
The output of the temperature digital data path can be read by using the time-command interface of the UART
interface. The value provided is related to the measured temperature as shown in Equation 7.
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T
T(VAL)
www.ti.com
64
1.5
T(VAL)
§ TEMP _ GAIN ·
ADCUNCOMP u ¨ 1
¸ TEMP _ OFF
128
©
¹
where
•
•
•
T(VAL)is value read from the device using TCI or UART commands.
T is the temperature.
TEMP_GAIN and TEMP_OFF are signed values in the limits from –8 to +7.
(7)
Because the output value of T(VAL) after the calculation can result in a decimal number, the value is rounded-up
to the closest integer value.
The temperature digital data path consists of a 16-sample averager and a scaling block as shown in Figure 41.
The 16-sample averaging block averages 16 temperature measurements arriving at a rate of 1 sample/µs into
one result to remove temperature measurement variations. The scaling block is used to adjust the Gain and the
offset parameter to better calibrate the temperature sensor. These two parameters are programmed using
TEMP_GAIN and TEMP_OFF bits in the TEMP_TRIM EEPROM register.
Digital Signal Processing (DSP) ± Temperature
From
Digital-MUX
TEMP_VAL
16-sample
Averager
Scaling
(gain, offset)
Figure 41. Temperature-Sensor Signal Path
Before compensation (TEMP_GAIN bit set to 0, TEMP_OFF bit set to 0), T(VAL) is same the value converted by
the ADC. As previously above, the user can compensate for variations in operating conditions (VPWR), board
design, and configuration of the device by performing a two-temperature measurement and trim. After
compensation, T(VAL) can be converted to an absolute temperature using Equation 7. As the VPWR is increased,
power dissipation increases and the internal die temperature can be different from the ambient temperature. The
temperature sensor always indicates the die temperature.
Without calibrating TEMP_GAIN and TEMP_OFF, the ambient temperature can be approximated from the die
temperature reading using Equation 8
TAmbient (°C) = TDie - [RθJA × (VPWR × IVPWR_RX_ONLY)]
where
•
•
•
52
RθJA(°C/W) is the Junction-to-ambient thermal resistance of 96.1°C/W.
VPWR (V) is the input voltage.
IVPWR_RX_ONLY(mA) is the supply current from VPWR pin during listen only mode of 12mA.
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7.3.12 TEST Pin Functionality
The PGA460-Q1 TEST pin serves multiple purposes including:
• Allows the user to extract internal signals from the PGA460-Q1 device.
• Selects the output voltage of the digital pins which enables a 3.3-V MCU or a 5-V MCU to be connected to
the device without using any external voltage translators. The RXD, TXD, SCLK, DECPL, and TEST pins are
affected by this selection.
Internal signals on the TEST pin can be extracted by selecting a predefined signal through the internal test mux.
The TEST_MUX register parameter is used to select this signal. Table 5 lists the possible PGA460-Q1 internal
signals that are output at the TEST pin.
Table 5. Internal Signals that can be Muxed out on the TEST Pin
TEST_MUX VALUE
SIGNAL NAME
0x00
Hi-Z (disabled)
0x01
ASC Output
0x02
Reserved
TYPE
The TEST pin is in the high impedance state
Analog
0x03
Reserved
0x04
8MHz Clock
0x05
ADC Sample Clock
0x06
Reserved
0x07
Reserved
DESCRIPTION
SAR ADC input after the ADC buffer
8-MHz clock output from PGA460-Q1
Digital
1-µs ADC sample Clock
When used as an analog test-mux output, the TEST pin output voltage can change from 0 V to 1.8 V while the
common mode voltage is set to 0.9 V.
The digital voltage-level selection performed by the TEST pin is executed at device power up. On power-up, the
device checks the level of the TEST pin. If the level is low, the digital output pins operate at 3.3 V. If the TEST
pin is tied high (3.3 V or 5 V are both considered high state), the digital output pins operate at a 5 V. This
condition is latched in the PGA460-Q1 device so that the test mux can further use the TEST pin as previously
described. If the application requires that a 5-V digital output is used and a test mux output must be extracted
from the PGA460-Q1 device, then a weak pullup resistor on the TEST pin can be connected as shown in
Figure 42.
5V
100 k
VCM
Analog
MUX
Digital
MUX
+
Analog
Buffer
±
< RPU < 500 k
TEST
Test Mux
Out
Digital
I/O buffer
800 k
To Digital
Copyright © 2017, Texas Instruments Incorporated
Figure 42. Test Pin Test Mux Output Application
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As shown in Figure 42, the resistor (RPU) is connected to a permanent power supply and a current path to
ground is generated through the RPU resistor and the 800-kΩ internal resistance. This configuration is no problem
for the system; however, it might cause a small quiescent-current increase in applications that require the use of
the PGA460-Q1 low-power mode to preserve energy. In this case, the TEST pin can be connected to a GPIO pin
on the external MCU that can output a logic low or high state on the TEST pin to select the voltage level at
device start-up and later disable the GPIO output to preserve energy or reconfigure the GPIO as an input in case
the MCU uses any of the PGA460-Q1 test output signals. The external pullup resistor is only required for CMOS
5-V UART communication and is not required for 3-V communication.
7.4 Device Functional Modes
The PGA460-Q1 device functional modes as defined as:
Active mode After the power-up sequence is complete, the device waits for a BURST/LISTEN or LISTEN ONLY
command to drive the transducer, and amplify and condition the received echo. In this mode, the
device can also be configured with various parameters, and data about the detected object can be
queried from the device. All these functions are achieved using commands defined in Interface
Description section.
Low-power mode The device can be configured to go to this mode after a defined period of inactivity as defined
in Low-Power Mode section. In this mode most of the blocks are turned off to dramatically reduce
current consumption. The device can come out of this mode with commands on the interface as
described in the Time-Command Interface and UART Interface section. In this mode, the device
cannot burst or listen for an echo. All configuration stored in volatile memory is also lost. This
includes all threshold timing and level values.
7.5 Programming
Figure 43 and Figure 44 are flow charts showing how the PGA460-Q1 device can be configured using the
USART or the TCI interfaces respectively.
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Programming (continued)
Idle
Wait for SYNC Field
SYNC
Received?
N
Y
Wait for
Command Field
Command
Received?
N
>15 ms?
N
Y
Y
Does the
address match
UART_ADDR?
N
Y
Set X Data Bytes Receive for
current command
Wait for X Number of Bytes
N
X Number
of Data
Bytes
Received?
N
Y
>15 ms?
Send Checksum
Y
Command
Requires
Checksum?
Y
Wait for Checksum field
Checksum
Received?
N
Send X Data Bytes according
to command
N
N
>15 ms?
Y
Y
Command
Correct?
Send
Diagnostic Field
N
Y
Y
Command
Must Send
Data
Back?
PGA460 Execute Command
N
Another
Command
has
Arrived?
Y
Is it a
No-Response
Command?
Y
N
Abort Execution of
current command
N
Load New Command
Figure 43. UART Communication Flow Chart
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Programming (continued)
Idle
Wait for Falling
Edge on IO pin
N
Switch IO
pin to Input
Switch to BitMode
Falling
Edge
Occurred?
Send 0
Acknowledgment
Wait for W/nR
bit
Send 1
Acknowledgment
Switch IO pin
to Output
Y
N
W/nR bit
Received?
Start Timer
N
>15 ms?
Y
Y
Wait for SubIndex Command
Field
Wait for
Rising Edge
on IO
N
N
Y
>15 ms?
N
Command
Received?
Rising
Edge
Occurred?
N
Y
PGA460 Execute
Command
if (echo > threshold)
IO_pin = low;
else
IO_pin = high;
Switch IO pin to
Output
Send Status
Feedback
(STAT bits)
Y
Send
Checksum
Check W/nR bit for
Data to be received
Restart Timer and
Capture Time
Command
Is it a Run
Command?
>15 ms?
Y
Y
Switch IO
pin to Input
N
N
Send X Data
Bytes according
to command
Expecting
Data and
Checksum
?
Y
Set X Data Bytes
Receive for
current command
Y
Command
Must Send
Data
Back?
Wait for X
Number of
Bytes
X Number
of Data
Bytes
Received?
Y
N
N
>15 ms?
Y
N
Check W/nR bit
for Data to be
sent
Switch IO pin
to Output
Wait for
Checksum field
PGA460 Execute
Command
N
Checksum
Received?
N
>15 ms?
Y
Y
Checksum
Correct?
N
Y
Figure 44. Time-Command Interface Communication Flow Chart
56
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Programming (continued)
7.5.1 UART and USART Communication Examples
The following are some examples of UART and USART communication:
Example1 – Read register 0x1B, where PGA460-Q1 address is 0x0:
Master to PGA460-Q1: 0x55, 0x09, 0x1B, 0xDB …
PGA460-Q1 to master: … 0xdiag, 0xdata, 0xchecksum
Example2 – Write register 0x40, data 0x80, where PGA460-Q1 address is 0x0:
Master to PGA460-Q1: 0x55, 0x0A, 0x40, 0x80, 0x35
PGA460-Q1 to master:No response, idle (0xFF)
Example3 – Execute command 0 (Burst/Listen Preset1) to detect 1 object, where PGA460-Q1 address is
0x0:
Master to PGA460-Q1: 0x55, 0x00, 0x01, 0xFE
PGA460-Q1 to master: No response, idle (0xFF)
Example4 – Execute command 5 (ultrasonic measurement result), where PGA460-Q1 address is 0x0,
assuming previous execution of Example3 where the master has commanded PGA460-Q1 to search for one
object:
Master to PGA460-Q1: 0x55, 0x05, 0xFA …
PGA460-Q1 to master: … 0xdiag , 0xtime_of_flight_in_us_[MSB],
0xtime_of_flight_in_us_[LSB], 0xtime_object_width_in_us, 0xpeak_amplidute_in_LSB, 0xchecksum
NOTE
A repeatable sequence of 0xFF signifies the idle bus state.
7.6 Register Maps
7.6.1 EEPROM Programming
To program the EEPROM, follow these steps:
1. Send an EEPROM program command using UART or TCI with a unique unlock pattern on 4-bits. The
program bit is set to 0 in register 0x40. The unlock passcode is 0x Dh.
2. Immediately send the same UART or TCI command with the program bit set to 1.
If any other command is issued after the unlock code (Step 1), the EEPROM program is initiated. Also, if the
unlock command in Step 1 is not correct, the EEPROM is not programmed. The EEPROM is locked again
automatically after each program command
NOTE
This EEPROM passcode is applicable by communication in the UART mode and for TCI
mode done through Config command 11.
7.6.2 Register Map Partitioning and Default Values
The register map in the Register Maps section is organized as follows:
• Address 0h-2Bh: EEPROM nonvolatile memory. Content in these registers is preserved during power cycle
and low-power mode.
• Address 40h-4Dh and address 5Fh-7Fh: Register-based volatile memory. Content in these registers is lost
during power cycle and low-power mode.
• Address 2Ch-3Fh and address 4Eh-5Eh are reserved for Texas Instruments internal use and are not
accessible to the user.
All registers are reset to the default values as shown in the Register Maps section. However, the PGA460-Q1
EEPROM is programmed to values as described in Table 6. These values are loaded into registers at power up,
overwriting the default reset values.
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Register Maps (continued)
Table 6. EEPROM Factory Default Values
EEPROM REGISTER
REGISTER ADDRESS
USER_DATA1-USER_DATA-20
0h-13h
Default Value
00h
TVGAIN0
14h
AFh
TVGAIN1
15h
FFh
TVGAIN2
16h
FFh
TVGAIN3
17h
2Dh
TVGAIN4
18h
68h
TVGAIN5
19h
36h
TVGAIN6
1Ah
FCh
INIT_GAIN
1Bh
C0h
FREQUENCY
1Ch
8Ch
DEADTIME
1Dh
00h
PULSE_P1
1Eh
01h
12h
PULSE_P2
1Fh
CURR_LIM_P1
20h
47h
CURR_LIM_P2
21h
FFh
REC_LENGTH
22h
1Ch
FREQ_DIAG
23h
00h
SAT_FDIAG_TH
24h
EEh
FVOLT_DEC
25h
7Ch
DECPL_TEMP
26h
0A
DSP_SCALE
27h
00h
TEMP_TRIM
28h
00h
P1_GAIN_CTRL
29h
00h
P2_GAIN_CTRL
2Ah
00h
2Bh
Auto calculated on EEPROM
burn
EE_CRC
7.6.3 REGMAP Registers
Table 7 lists the memory-mapped registers for the REGMAP. All register offset addresses not listed in Table 7
should be considered as reserved locations and the register contents should not be modified.
Table 7. REGMAP Registers
Offset
58
Acronym
Register Name
0h
USER_DATA1
User general purpose data register 1
Go
1h
USER_DATA2
User general purpose data register 2
Go
2h
USER_DATA3
User general purpose data register 3
Go
3h
USER_DATA4
User general purpose data register 4
Go
4h
USER_DATA5
User general purpose data register 5
Go
5h
USER_DATA6
User general purpose data register 6
Go
6h
USER_DATA7
User general purpose data register 7
Go
7h
USER_DATA8
User general purpose data register 8
Go
8h
USER_DATA9
User general purpose data register 9
Go
9h
USER_DATA10
User general purpose data register 10
Go
Ah
USER_DATA11
User general purpose data register 11
Go
Bh
USER_DATA12
User general purpose data register 12
Go
Ch
USER_DATA13
User general purpose data register 13
Go
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Table 7. REGMAP Registers (continued)
Offset
Acronym
Register Name
Dh
USER_DATA14
User general purpose data register 14
Section
Go
Eh
USER_DATA15
User general purpose data register 15
Go
Fh
USER_DATA16
User general purpose data register 16
Go
10h
USER_DATA17
User general purpose data register 17
Go
11h
USER_DATA18
User general purpose data register 18
Go
12h
USER_DATA19
User general purpose data register 19
Go
13h
USER_DATA20
User general purpose data register 20
Go
14h
TVGAIN0
Time-varying gain map segment configuration register 0
Go
15h
TVGAIN1
Time-varying gain map segment configuration register 1
Go
16h
TVGAIN2
Time-varying gain map segment configuration register 2
Go
17h
TVGAIN3
Time-varying gain map segment configuration register 3
Go
18h
TVGAIN4
Time-varying gain map segment configuration register 4
Go
19h
TVGAIN5
Time-varying gain map segment configuration register 5
Go
1Ah
TVGAIN6
Time-varying gain map segment configuration register 6
Go
1Bh
INIT_GAIN
AFE initial gain configuration register
Go
1Ch
FREQUENCY
Burst frequency configuration register
Go
1Dh
DEADTIME
Deadtime and threshold deglitch configuration
Go
1Eh
PULSE_P1
Preset1 pulse burst, IO control and UART diagnostic
configuration
Go
1Fh
PULSE_P2
Preset2 pulse burst, IO control and UART diagnostic
configuration
Go
20h
CURR_LIM_P1
Preset1 driver current limit configuration
Go
21h
CURR_LIM_P2
Preset2 current limit and low pass filter configuration
Go
22h
REC_LENGTH
Echo data record period configuration register
Go
23h
FREQ_DIAG
Frequency diagnostic configuration register
Go
24h
SAT_FDIAG_TH
Decay saturation, frequency diag error and Preset1 nonlinear control configuration
Go
25h
FVOLT_DEC
Voltage thresholds and Preset2 non-linear scaling
configuration
Go
26h
DECPL_TEMP
De-couple temp and AFE gain range configuration
Go
27h
DSP_SCALE
DSP path non-linear scaling and noise level
configuration
Go
28h
TEMP_TRIM
Temperature compensation values register
Go
29h
P1_GAIN_CTRL
Preset1 digital gain configuration register
Go
2Ah
P2_GAIN_CTRL
Preset2 digital gain confiuration register
Go
2Bh
EE_CRC
User EEPROM space CRC value register
Go
40h
EE_CNTRL
User EEPROM control register
Go
41h
BPF_A2_MSB
BPF A2 coefficient most-signifcant byte configuration
Go
42h
BPF_A2_LSB
BPF A2 coefficient least-signifcant byte configuration
Go
43h
BPF_A3_MSB
BPF A3 coefficient most-signifcant byte configuration
Go
44h
BPF_A3_LSB
BPF A3 coefficient least-signifcant byte configuration
Go
45h
BPF_B1_MSB
BPF B1 coefficient most-signifcant byte configuration
Go
46h
BPF_B1_LSB
BPF B1 coefficient least-signifcant byte configuration
Go
47h
LPF_A2_MSB
LPF A2 coefficient most-signifcant byte configuration
Go
48h
LPF_A2_LSB
LPF A2 coefficient least-signifcant byte configuration
Go
49h
LPF_B1_MSB
LPF B1 coefficient most-signifcant byte configuration
Go
4Ah
LPF_B1_LSB
LPF B1 coefficient least-signifcant byte configuration
Go
4Bh
TEST_MUX
Test multiplexer configuration register
Go
4Ch
DEV_STAT0
Device Status register 0
Go
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Table 7. REGMAP Registers (continued)
Offset
Acronym
Register Name
4Dh
DEV_STAT1
Device status register 1
Section
Go
5Fh
P1_THR_0
Preset1 threshold map segment configuration register 0
Go
60h
P1_THR_1
Preset1 threshold map segment configuration register 1
Go
61h
P1_THR_2
Preset1 threshold map segment configuration register 2
Go
62h
P1_THR_3
Preset1 threshold map segment configuration register 3
Go
63h
P1_THR_4
Preset1 threshold map segment configuration register 4
Go
64h
P1_THR_5
Preset1 threshold map segment configuration register 5
Go
65h
P1_THR_6
Preset1 threshold map segment configuration register 6
Go
66h
P1_THR_7
Preset1 threshold map segment configuration register 7
Go
67h
P1_THR_8
Preset1 threshold map segment configuration register 8
Go
68h
P1_THR_9
Preset1 threshold map segment configuration register 9
Go
69h
P1_THR_10
Preset1 threshold map segment configuration register 10
Go
6Ah
P1_THR_11
Preset1 threshold map segment configuration register 11
Go
6Bh
P1_THR_12
Preset1 threshold map segment configuration register 12
Go
6Ch
P1_THR_13
Preset1 threshold map segment configuration register 13
Go
6Dh
P1_THR_14
Preset1 threshold map segment configuration register 14
Go
6Eh
P1_THR_15
Preset1 threshold map segment configuration register 15
Go
6Fh
P2_THR_0
Preset2 threshold map segment configuration register 0
Go
70h
P2_THR_1
Preset2 threshold map segment configuration register 1
Go
71h
P2_THR_2
Preset2 threshold map segment configuration register 2
Go
72h
P2_THR_3
Preset2 threshold map segment configuration register 3
Go
73h
P2_THR_4
Preset2 threshold map segment configuration register 4
Go
74h
P2_THR_5
Preset2 threshold map segment configuration register 5
Go
75h
P2_THR_6
Preset2 threshold map segment configuration register 6
Go
76h
P2_THR_7
Preset2 threshold map segment configuration register 7
Go
77h
P2_THR_8
Preset2 threshold map segment configuration register 8
Go
78h
P2_THR_9
Preset2 threshold map segment configuration register 9
Go
79h
P2_THR_10
Preset2 threshold map segment configuration register 10
Go
7Ah
P2_THR_11
Preset2 threshold map segment configuration register 11
Go
7Bh
P2_THR_12
Preset2 threshold map segment configuration register 12
Go
7Ch
P2_THR_13
Preset2 threshold map segment configuration register 13
Go
7Dh
P2_THR_14
Preset2 threshold map segment configuration register 14
Go
7Eh
P2_THR_15
Preset2 threshold map segment configuration register 15
Go
7Fh
THR_CRC
Threshold map configuration registers data CRC register
Go
Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for
access types in this section.
Table 8. REGMAP Access Type Codes
Access Type
Code
Description
R
R
Read
RC
C
R
to Clear
Read
RH
H
R
Set or cleared by hardware
Read
W
Write
Read Type
Write Type
W
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Table 8. REGMAP Access Type Codes (continued)
Access Type
Code
Description
Reset or Default Value
-n
Value after reset or the default
value
7.6.3.1 USER_DATA1 Register (Address = 0h) [reset = 0h]
USER_DATA1 is shown in Figure 45 and described in Table 9.
Return to Summary Table.
User general purpose data register 1
Figure 45. USER_DATA1 Register
7
6
5
4
3
2
1
0
USER_1
R/W-0h
Table 9. USER_DATA1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_1
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.2 USER_DATA2 Register (Address = 1h) [reset = 0h]
USER_DATA2 is shown in Figure 46 and described in Table 10.
Return to Summary Table.
User general purpose data register 2
Figure 46. USER_DATA2 Register
7
6
5
4
3
2
1
0
USER_2
R/W-0h
Table 10. USER_DATA2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_2
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.3 USER_DATA3 Register (Address = 2h) [reset = 0h]
USER_DATA3 is shown in Figure 47 and described in Table 11.
Return to Summary Table.
User general purpose data register 3
Figure 47. USER_DATA3 Register
7
6
5
4
3
2
1
0
USER_3
R/W-0h
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Table 11. USER_DATA3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_3
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.4 USER_DATA4 Register (Address = 3h) [reset = 0h]
USER_DATA4 is shown in Figure 48 and described in Table 12.
Return to Summary Table.
User general purpose data register 4
Figure 48. USER_DATA4 Register
7
6
5
4
3
2
1
0
USER_4
R/W-0h
Table 12. USER_DATA4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_4
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.5 USER_DATA5 Register (Address = 4h) [reset = 0h]
USER_DATA5 is shown in Figure 49 and described in Table 13.
Return to Summary Table.
User general purpose data register 5
Figure 49. USER_DATA5 Register
7
6
5
4
3
2
1
0
USER_5
R/W-0h
Table 13. USER_DATA5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_5
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.6 USER_DATA6 Register (Address = 5h) [reset = 0h]
USER_DATA6 is shown in Figure 50 and described in Table 14.
Return to Summary Table.
User general purpose data register 6
Figure 50. USER_DATA6 Register
7
6
5
4
3
2
1
0
USER_6
R/W-0h
62
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Table 14. USER_DATA6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_6
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.7 USER_DATA7 Register (Address = 6h) [reset = 0h]
USER_DATA7 is shown in Figure 51 and described in Table 15.
Return to Summary Table.
User general purpose data register 7
Figure 51. USER_DATA7 Register
7
6
5
4
3
2
1
0
USER_7
R/W-0h
Table 15. USER_DATA7 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_7
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.8 USER_DATA8 Register (Address = 7h) [reset = 0h]
USER_DATA8 is shown in Figure 52 and described in Table 16.
Return to Summary Table.
User general purpose data register 8
Figure 52. USER_DATA8 Register
7
6
5
4
3
2
1
0
USER_8
R/W-0h
Table 16. USER_DATA8 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_8
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.9 USER_DATA9 Register (Address = 8h) [reset = 0h]
USER_DATA9 is shown in Figure 53 and described in Table 17.
Return to Summary Table.
User general purpose data register 9
Figure 53. USER_DATA9 Register
7
6
5
4
3
2
1
0
USER_9
R/W-0h
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Table 17. USER_DATA9 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_9
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.10 USER_DATA10 Register (Address = 9h) [reset = 0h]
USER_DATA10 is shown in Figure 54 and described in Table 18.
Return to Summary Table.
User general purpose data register 10
Figure 54. USER_DATA10 Register
7
6
5
4
3
2
1
0
USER_10
R/W-0h
Table 18. USER_DATA10 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_10
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.11 USER_DATA11 Register (Address = Ah) [reset = 0h]
USER_DATA11 is shown in Figure 55 and described in Table 19.
Return to Summary Table.
User general purpose data register 11
Figure 55. USER_DATA11 Register
7
6
5
4
3
2
1
0
USER_11
R/W-0h
Table 19. USER_DATA11 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_11
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.12 USER_DATA12 Register (Address = Bh) [reset = 0h]
USER_DATA12 is shown in Figure 56 and described in Table 20.
Return to Summary Table.
User general purpose data register 12
Figure 56. USER_DATA12 Register
7
6
5
4
3
2
1
0
USER_12
R/W-0h
64
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Table 20. USER_DATA12 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_12
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.13 USER_DATA13 Register (Address = Ch) [reset = 0h]
USER_DATA13 is shown in Figure 57 and described in Table 21.
Return to Summary Table.
User general purpose data register 13
Figure 57. USER_DATA13 Register
7
6
5
4
3
2
1
0
USER_13
R/W-0h
Table 21. USER_DATA13 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_13
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.14 USER_DATA14 Register (Address = Dh) [reset = 0h]
USER_DATA14 is shown in Figure 58 and described in Table 22.
Return to Summary Table.
User general purpose data register 14
Figure 58. USER_DATA14 Register
7
6
5
4
3
2
1
0
USER_14
R/W-0h
Table 22. USER_DATA14 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_14
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.15 USER_DATA15 Register (Address = Eh) [reset = 0h]
USER_DATA15 is shown in Figure 59 and described in Table 23.
Return to Summary Table.
User general purpose data register 15
Figure 59. USER_DATA15 Register
7
6
5
4
3
2
1
0
USER_15
R/W-0h
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Table 23. USER_DATA15 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_15
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.16 USER_DATA16 Register (Address = Fh) [reset = 0h]
USER_DATA16 is shown in Figure 60 and described in Table 24.
Return to Summary Table.
User general purpose data register 16
Figure 60. USER_DATA16 Register
7
6
5
4
3
2
1
0
USER_16
R/W-0h
Table 24. USER_DATA16 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_16
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.17 USER_DATA17 Register (Address = 10h) [reset = 0h]
USER_DATA17 is shown in Figure 61 and described in Table 25.
Return to Summary Table.
User general purpose data register 17
Figure 61. USER_DATA17 Register
7
6
5
4
3
2
1
0
USER_17
R/W-0h
Table 25. USER_DATA17 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_17
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.18 USER_DATA18 Register (Address = 11h) [reset = 0h]
USER_DATA18 is shown in Figure 62 and described in Table 26.
Return to Summary Table.
User general purpose data register 18
Figure 62. USER_DATA18 Register
7
6
5
4
3
2
1
0
USER_18
R/W-0h
66
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Table 26. USER_DATA18 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_18
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.19 USER_DATA19 Register (Address = 12h) [reset = 0h]
USER_DATA19 is shown in Figure 63 and described in Table 27.
Return to Summary Table.
User general purpose data register 19
Figure 63. USER_DATA19 Register
7
6
5
4
3
2
1
0
USER_19
R/W-0h
Table 27. USER_DATA19 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_19
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.20 USER_DATA20 Register (Address = 13h) [reset = 0h]
USER_DATA20 is shown in Figure 64 and described in Table 28.
Return to Summary Table.
User general purpose data register 20
Figure 64. USER_DATA20 Register
7
6
5
4
3
2
1
0
USER_20
R/W-0h
Table 28. USER_DATA20 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
USER_20
R/W
0h
This register has no internal functional use.
Register content is User defined solely for external use .
7.6.3.21 TVGAIN0 Register (Address = 14h) [reset = 0h]
TVGAIN0 is shown in Figure 65 and described in Table 29.
Return to Summary Table.
Time-varying gain map segment configuration register 0
Figure 65. TVGAIN0 Register
7
6
5
4
3
TVG_T0
R/W-0h
2
1
0
TVG_T1
R/W-0h
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Table 29. TVGAIN0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TVG_T0
R/W
0h
Time varying gain Start time parameter:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
3:0
TVG_T1
R/W
0h
Time Varying Gain T0/T1 Delta Time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
7.6.3.22 TVGAIN1 Register (Address = 15h) [reset = 0h]
TVGAIN1 is shown in Figure 66 and described in Table 30.
Return to Summary Table.
Time-varying gain map segment configuration register 1
Figure 66. TVGAIN1 Register
7
6
5
4
3
TVG_T2
R/W-0h
68
2
1
0
TVG_T3
R/W-0h
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Table 30. TVGAIN1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TVG_T2
R/W
0h
Time Varying Gain T1/T2 Delta Time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
3:0
TVG_T3
R/W
0h
Time Varying Gain T2/T3 Delta Time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
7.6.3.23 TVGAIN2 Register (Address = 16h) [reset = 0h]
TVGAIN2 is shown in Figure 67 and described in Table 31.
Return to Summary Table.
Time-varying gain map segment configuration register 2
Figure 67. TVGAIN2 Register
7
6
5
4
3
TVG_T4
R/W-0h
2
1
0
TVG_T5
R/W-0h
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Table 31. TVGAIN2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TVG_T4
R/W
0h
Time Varying Gain T3/T4 Delta Time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
3:0
TVG_T5
R/W
0h
Time Varying Gain T4/T5 Delta Time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
7.6.3.24 TVGAIN3 Register (Address = 17h) [reset = 0h]
TVGAIN3 is shown in Figure 68 and described in Table 32.
Return to Summary Table.
Time-varying gain map segment configuration register 3
Figure 68. TVGAIN3 Register
7
6
5
4
3
2
TVG_G1
R/W-0h
1
0
TVG_G2
R/W-0h
Table 32. TVGAIN3 Register Field Descriptions
70
Bit
Field
Type
Reset
Description
7:2
TVG_G1
R/W
0h
TVG Point 1 Gain Value:
Gain = 0.5 * (TVG_G1 +1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
1:0
TVG_G2
R/W
0h
TVG Point 2 Gain Value:
Gain = 0.5 * (TVG_G2 + 1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
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7.6.3.25 TVGAIN4 Register (Address = 18h) [reset = 0h]
TVGAIN4 is shown in Figure 69 and described in Table 33.
Return to Summary Table.
Time-varying gain map segment configuration register 4
Figure 69. TVGAIN4 Register
7
6
5
4
3
2
TVG_G2
R/W-0h
1
0
TVG_G3
R/W-0h
Table 33. TVGAIN4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TVG_G2
R/W
0h
TVG Point 2 Gain Value:
Gain = 0.5 * (TVG_G2 +1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
3:0
TVG_G3
R/W
0h
TVG Point 3 Gain Value:
Gain = 0.5 * (TVG_G3 + 1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
7.6.3.26 TVGAIN5 Register (Address = 19h) [reset = 0h]
TVGAIN5 is shown in Figure 70 and described in Table 34.
Return to Summary Table.
Time-varying gain map segment configuration register 5
Figure 70. TVGAIN5 Register
7
6
5
4
3
TVG_G3
R/W-0h
2
1
0
TVG_G4
R/W-0h
Table 34. TVGAIN5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
TVG_G3
R/W
0h
TVG Point 3 Gain Value:
Gain = 0.5 * (TVG_G3 +1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
5:0
TVG_G4
R/W
0h
TVG Point 4 Gain Value:
Gain = 0.5 * (TVG_G4 + 1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
7.6.3.27 TVGAIN6 Register (Address = 1Ah) [reset = 0h]
TVGAIN6 is shown in Figure 71 and described in Table 35.
Return to Summary Table.
Time-varying gain map segment configuration register 6
Figure 71. TVGAIN6 Register
7
6
5
4
3
TVG_G5
R/W-0h
2
1
RESERVED
R/W-0h
0
FREQ_SHIFT
R/W-0h
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Table 35. TVGAIN6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:2
TVG_G5
R/W
0h
TVG Point 5 Gain Value:
Gain = 0.5 * (TVG_G5 +1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
1
RESERVED
R/W
0h
Reserved
0
FREQ_SHIFT
R/W
0h
Burst Frequency Range Shift: 0b = Disabled
1b = Enabled, active freqency = 6 * frequency result from calculation
using equation given in the FREQUENCY register
7.6.3.28 INIT_GAIN Register (Address = 1Bh) [reset = 0h]
INIT_GAIN is shown in Figure 72 and described in Table 36.
Return to Summary Table.
AFE initial gain configuration register
Figure 72. INIT_GAIN Register
7
6
5
4
3
BPF_BW
R/W-0h
2
1
0
GAIN_INIT
R/W-0h
Table 36. INIT_GAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
BPF_BW
R/W
0h
Digital banpass filter bandwidth:
BandWidth = 2 * (BPF_BW + 1) [kHz]
5:0
GAIN_INIT
R/W
0h
Initial AFE Gain:
Init_Gain = 0.5 * (GAIN_INIT+1) + value(AFE_GAIN_RNG) [dB]
Where value(AFE_GAIN_RNG) is the corresponding value in dB for
bits set for AFE_GAIN_RNG in DECPL_TEMP register
7.6.3.29 FREQUENCY Register (Address = 1Ch) [reset = 0h]
FREQUENCY is shown in Figure 73 and described in Table 37.
Return to Summary Table.
Burst frequency configuration register
Figure 73. FREQUENCY Register
7
6
5
4
3
2
1
0
FREQ
R/W-0h
Table 37. FREQUENCY Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
FREQ
R/W
0h
Burst frequency equation parameter:
Frequency = 0.2 * FREQ + 30 [kHz]
The valid FREQ parameter value range is from 0 to 250 (00h to FAh)
7.6.3.30 DEADTIME Register (Address = 1Dh) [reset = 0h]
DEADTIME is shown in Figure 74 and described in Table 38.
Return to Summary Table.
Pulse deadtime and threshold deglitch configuration register
72
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Figure 74. DEADTIME Register
7
6
5
THR_CMP_DEGLTCH
R/W-0h
4
3
2
1
0
PULSE_DT
R/W-0h
Table 38. DEADTIME Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
THR_CMP_DEGLTCH
R/W
0h
Threshold level comparator deglitch period:
deglitch period = (THR_CMP_DEGLITCH * 8) [µs]
3:0
PULSE_DT
R/W
0h
Burst Pulse Dead-Time:
DeadTime = 0.0625 * PULSE_DT[µs]
7.6.3.31 PULSE_P1 Register (Address = 1Eh) [reset = 0h]
PULSE_P1 is shown in Figure 75 and described in Table 39.
Return to Summary Table.
Preset1 pulse burst number, IO pin control, and UART diagnostic configuration register
Figure 75. PULSE_P1 Register
7
IO_IF_SEL
R/W-0h
6
UART_DIAG
R/W-0h
5
IO_DIS
R/W-0h
4
3
2
P1_PULSE
R/W-0h
1
0
Table 39. PULSE_P1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
IO_IF_SEL
R/W
0h
Interface Selection on IO pin:
0b = Time-Based Interface
1b = One-Wire UART Interface
6
UART_DIAG
R/W
0h
UART Diagnostic Page Selection:
0b = Diagnostic bits related to UART interface
1b = Diagnostic bits related to System Diagnostics
5
IO_DIS
R/W
0h
Disable IO pin transceiver:
0b = IO transceiver enabled
1b = IO transceiver disabled Note: Available only if IO_IF_SEL = 0
P1_PULSE
R/W
0h
Number of burst pulses for Preset1
Note: 0h means one pulse is generated on OUTA only
4:0
7.6.3.32 PULSE_P2 Register (Address = 1Fh) [reset = 0h]
PULSE_P2 is shown in Figure 76 and described in Table 40.
Return to Summary Table.
Preset2 pulse burst number and UART address configuration register
Figure 76. PULSE_P2 Register
7
6
UART_ADDR
R/W-0h
5
4
3
2
P2_PULSE
R/W-0h
1
0
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Table 40. PULSE_P2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
UART_ADDR
R/W
0h
UART interface address
4:0
P2_PULSE
R/W
0h
Number of burst pulses for Preset2
Note: 0h means one pulse is generated on OUTA only
7.6.3.33 CURR_LIM_P1 Register (Address = 20h) [reset = 0h]
CURR_LIM_P1 is shown in Figure 77 and described in Table 41.
Return to Summary Table.
Preset1 driver current limit configuration register
Figure 77. CURR_LIM_P1 Register
7
DIS_CL
R/W-0h
6
5
4
3
2
1
0
CURR_LIM1
R/W-0h
Table 41. CURR_LIM_P1 Register Field Descriptions
Bit
7
5:0
Field
Type
Reset
Description
DIS_CL
R/W
0h
Disable Current Limit for Preset1 and Preset2
0b = current limit enabled
1b = current limit disabled
CURR_LIM1
R/W
0h
Driver Current Limit for Preset1
Current_Limit = 7 * CURR_LIM1 + 50 [mA]
7.6.3.34 CURR_LIM_P2 Register (Address = 21h) [reset = 0h]
CURR_LIM_P2 is shown in Figure 78 and described in Table 42.
Return to Summary Table.
Preset2 current limit and low pass filter configuration register
Figure 78. CURR_LIM_P2 Register
7
6
5
4
3
LPF_CO
R/W-0h
2
1
0
CURR_LIM2
R/W-0h
Table 42. CURR_LIM_P2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
LPF_CO
R/W
0h
Lowpass filter cutoff frequency:
Cut off frequency = LPF_CO + 1 [kHz]
5:0
CURR_LIM2
R/W
0h
Driver current limit for Preset2
Current limit = 7 * CURR_LIM2 + 50 [mA]
7.6.3.35 REC_LENGTH Register (Address = 22h) [reset = 0h]
REC_LENGTH is shown in Figure 79 and described in Table 43.
Return to Summary Table.
Echo data record period configuration register
74
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Figure 79. REC_LENGTH Register
7
6
5
4
3
2
P1_REC
R/W-0h
1
0
1
0
P2_REC
R/W-0h
Table 43. REC_LENGTH Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
P1_REC
R/W
0h
Preset1 record time length:
Record time = 4.096 * (P1_REC + 1) [ms]
3:0
P2_REC
R/W
0h
Preset2 record time length:
Record time = 4.096 * (P2_REC + 1) [ms]
7.6.3.36 FREQ_DIAG Register (Address = 23h) [reset = 0h]
FREQ_DIAG is shown in Figure 80 and described in Table 44.
Return to Summary Table.
Frequency diagnostic configuration register
Figure 80. FREQ_DIAG Register
7
6
5
4
3
2
FDIAG_LEN
R/W-0h
FDIAG_START
R/W-0h
Table 44. FREQ_DIAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
FDIAG_LEN
R/W
0h
Frequency diagnostic window length:
For value 0h, the diagnostic is disabled.
For values 0 to Fh, the window length is given by
3 * FDIAG_LEN [Signal Periods]
3:0
FDIAG_START
R/W
0h
Frequency diagnostic start time:
Start time = 100 * FDIAG_START [µs]
Note: this time is relative to the end-of-burst time
7.6.3.37 SAT_FDIAG_TH Register (Address = 24h) [reset = 0h]
SAT_FDIAG_TH is shown in Figure 81 and described in Table 45.
Return to Summary Table.
Decay saturation threshold, frequency diagnostic error threshold, and Preset1 non-linear enable control
configuration register
Figure 81. SAT_FDIAG_TH Register
7
6
FDIAG_ERR_TH
R/W-0h
5
4
3
2
1
SAT_TH
R/W-0h
0
P1_NLS_EN
R/W-0h
Table 45. SAT_FDIAG_TH Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
FDIAG_ERR_TH
R/W
0h
Frequency diagnostic asbolute error time threshold:
threshold = (FDIAG_ERR_TH + 1) [µs]
4:1
SAT_TH
R/W
0h
Saturation diagnostic threshold level.
P1_NLS_EN
R/W
0h
Set high to enable Preset1 non-linear scaling
0
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7.6.3.38 FVOLT_DEC Register (Address = 25h) [reset = 0h]
FVOLT_DEC is shown in Figure 82 and described in Table 46.
Return to Summary Table.
Voltage thresholds and Preset2 non-linear scaling enable configuration register
Figure 82. FVOLT_DEC Register
7
P2_NLS_EN
R/W-0h
6
5
4
VPWR_OV_TH
R/W-0h
3
2
1
FVOLT_ERR_TH
R/W-0h
LPM_TMR
R/W-0h
0
Table 46. FVOLT_DEC Register Field Descriptions
Bit
Field
Type
Reset
Description
P2_NLS_EN
R/W
0h
Set high to enable Preset2 non-linear scaling
6:5
VPWR_OV_TH
R/W
0h
VPWR over voltage threshold select:
00b = 12.3 V
01b = 17.7 V
10b = 22.8 V
11b = 28.3 V
4:3
LPM_TMR
R/W
0h
Low power mode enter time:
00b = 250 ms
01b = 500 ms
10b = 1 s
11b = 4s
2:0
FVOLT_ERR_TH
R/W
0h
See section on System Diagnostics for Voltage diagnostic
measurement:
000b = 1
001b = 2
010b = 3
011b = 4
100b = 5
101b = 6
110b = 7
111b = 8
7
7.6.3.39 DECPL_TEMP Register (Address = 26h) [reset = 0h]
DECPL_TEMP is shown in Figure 83 and described in Table 47.
Return to Summary Table.
De-couple temperature and AFE gain range configuration register
Figure 83. DECPL_TEMP Register
7
6
AFE_GAIN_RNG
5
LPM_EN
R/W-0h
R/W-0h
4
DECPL_TEMP
_SEL
R/W-0h
3
2
1
0
DECPL_T
R/W-0h
Table 47. DECPL_TEMP Register Field Descriptions
76
Bit
Field
Type
Reset
Description
7:6
AFE_GAIN_RNG
R/W
0h
AFE gain range selection codes:
00b = 58 to 90 dB
01b = 52 to 84 dB
10b = 46 to 78 dB
11b = 32 to 64 dB
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Table 47. DECPL_TEMP Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
LPM_EN
R/W
0h
PGA460 Low Power Mode Enable:
0b = Low power mode is disabled
1b = Low power mode is enabled
4
DECPL_TEMP_SEL
R/W
0h
Decouple Time / Temperature Select:
0b = Time Decouple
1b = Temperature Decouple
DECPL_T
R/W
0h
Secondary decouple time / temperature decouple
If DECPL_TEMP_SEL = 0 (Time Decouple)
Time = 4096 * (DECPL_T + 1) [µs]
If DECPL_TEMP_SEL = 1 (Temperature Decouple)
Temperature = 10 * DECPL_T - 40 [degC]
3:0
7.6.3.40 DSP_SCALE Register (Address = 27h) [reset = 0h]
DSP_SCALE is shown in Figure 84 and described in Table 48.
Return to Summary Table.
DSP non-linear scaling and noise level configuration register
Figure 84. DSP_SCALE Register
7
6
5
NOISE_LVL
R/W-0h
4
3
2
SCALE_K
R/W-0h
1
0
SCALE_N
R/W-0h
Table 48. DSP_SCALE Register Field Descriptions
Bit
Field
Type
Reset
Description
7:3
NOISE_LVL
R/W
0h
Value ranges from 0 to 31 with 1 LSB steps for digital gain values
(Px_DIG_GAIN_LR) less than 8
If digital gain (Px_DIG_GAIN_LR) is larger than 8, then multiply the
NOISE_LVL by Px_DIG_GAIN_LR/8
2
SCALE_K
R/W
0h
Non-Linear scaling exponent selection:
0b = 1.50
1b = 2.00
1:0
SCALE_N
R/W
0h
Selects the starting threshold level point from which the non-linear
gain (if enabled) is applied:
00b = TH9
01b = TH10
10b = TH11
11b = TH12
7.6.3.41 TEMP_TRIM Register (Address = 28h) [reset = 0h]
TEMP_TRIM is shown in Figure 85 and described in Table 49.
Return to Summary Table.
Temperature sensor compensation values register
Figure 85. TEMP_TRIM Register
7
6
5
4
3
TEMP_GAIN
R/W-0h
2
1
0
TEMP_OFF
R/W-0h
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Table 49. TEMP_TRIM Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TEMP_GAIN
R/W
0h
Temperature scaling gain:
signed value can range from -8 (1000b) to 7 (0111b) used for
measured temperature value compensation
3:0
TEMP_OFF
R/W
0h
Temperature Scaling Offset:
signed value can range from -8 (1000b) to 7 (0111b) used for
measured temperature value compensation
7.6.3.42 P1_GAIN_CTRL Register (Address = 29h) [reset = 0h]
P1_GAIN_CTRL is shown in Figure 86 and described in Table 50.
Return to Summary Table.
Preset1 digital gain configuration register
Figure 86. P1_GAIN_CTRL Register
7
6
P1_DIG_GAIN_LR_ST
R/W-0h
5
4
P1_DIG_GAIN_LR
R/W-0h
3
2
1
P1_DIG_GAIN_SR
R/W-0h
0
Table 50. P1_GAIN_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
P1_DIG_GAIN_LR_ST
R/W
0h
Selects the starting Preset1 threshold level point from which the long
range (LR) digital gain, P1_DIG_GAIN_LR, is applied
00b = TH9
01b = TH10
10b = TH11
11b = TH12
5:3
P1_DIG_GAIN_LR
R/W
0h
Preset1 Digital long range (LR) gain applied from the selected long
range threshold level point to the end of the record period Applied to
the thresholds set by P1_DIG_GAIN_LR_ST:
000b = multiplied by 1
001b = multiplied by 2
010b = multiplied by 4
011b = multiplied by 8
100b = multiplied by 16
101b = multiplied by 32
110b = invalid
111b = invalid
2:0
P1_DIG_GAIN_SR
R/W
0h
Preset1 Digital short range (SR) gain applied from time zero to the
start of the selected long range (LR) threshold level point:
000b = multiplied by 1
001b = multiplied by 2
010b = multiplied by 4
011b = multiplied by 8
100b = multiplied by 16
101b = multiplied by 32
110b = invalid
111b = invalid
7.6.3.43 P2_GAIN_CTRL Register (Address = 2Ah) [reset = 0h]
P2_GAIN_CTRL is shown in Figure 87 and described in Table 51.
Return to Summary Table.
Preset2 digital gain confiuration register
78
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Figure 87. P2_GAIN_CTRL Register
7
6
P2_DIG_GAIN_LR_ST
R/W-0h
5
4
P2_DIG_GAIN_LR
R/W-0h
3
2
1
P2_DIG_GAIN_SR
R/W-0h
0
Table 51. P2_GAIN_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
P2_DIG_GAIN_LR_ST
R/W
0h
Selects the starting Preset2 threshold level point from which the long
range (LR) digital gain, P2_DIG_GAIN_LR, is applied
00b = TH9
01b = TH10
10b = TH11
11b = TH12
5:3
P2_DIG_GAIN_LR
R/W
0h
Preset2 Digital long range (LR) gain applied from the selected long
range threshold level point to the end of the record period Applied to
the thresholds set by P2_DIG_GAIN_LR_ST:
000b = multiplied by 1
001b = multiplied by 2
010b = multiplied by 4
011b = multiplied by 8
100b = multiplied by 16
101b = multiplied by 32
110b = invalid
111b = invalid
2:0
P2_DIG_GAIN_SR
R/W
0h
Preset2 Digital short range (SR) gain applied from time zero to the
start of the selected long range (LR) threshold level point:
000b = multiplied by 1
001b = multiplied by 2
010b = multiplied by 4
011b = multiplied by 8
100b = multiplied by 16
101b = multiplied by 32
110b = invalid
111b = invalid
7.6.3.44 EE_CRC Register (Address = 2Bh) [reset = 0h]
EE_CRC is shown in Figure 88 and described in Table 52.
Return to Summary Table.
User EEPROM space data CRC register
Figure 88. EE_CRC Register
7
6
5
4
3
2
1
0
EE_CRC
R/W-0h
Table 52. EE_CRC Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
EE_CRC
R/W
0h
User EEPROM space data CRC value
7.6.3.45 EE_CNTRL Register (Address = 40h) [reset = 00h]
EE_CNTRL is shown in Figure 89 and described in Table 53.
Return to Summary Table.
User EEPROM control register
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Figure 89. EE_CNTRL Register
7
DATADUMP_E
N
RH/W-0h
6
5
EE_UNLCK
4
3
2
EE_PRGM_OK
1
EE_RLOAD
0
EE_PRGM
R/W-0h
R-0h
R/W-0h
R/W-0h
Table 53. EE_CNTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
DATADUMP_EN
RH/W
0h
Data Dump Enable bit: 0b = Disabled 1b = Enabled
EE_UNLCK
R/W
0h
EEPROM program enable unlock passcode register:
The valid passcode for enabling EEPROM programming is 0xD.
2
EE_PRGM_OK
R
0h
EEPROM programming status: 0b = EEPROM was not programmed
successfully 1b = EEPROM was programmed successfully
1
EE_RLOAD
R/W
0h
EEPROM Reload Trigger: 0b = Disabled 1b = Reload Data from
EEPROM
0
EE_PRGM
R/W
0h
EEPROM Program Trigger: 0b = Disabled 1b = Program Data to
EEPROM
7
6:3
7.6.3.46 BPF_A2_MSB Register (Address = 41h) [reset = 00h]
BPF_A2_MSB is shown in Figure 90 and described in Table 54.
Return to Summary Table.
BPF A2 coefficient most-signifcant byte configuration
Figure 90. BPF_A2_MSB Register
7
6
5
4
3
2
1
0
BPF_A2_MSB
R/W-0h
Table 54. BPF_A2_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
BPF_A2_MSB
R/W
0h
Bandpass filter A2 coefficient most-significant byte value
7.6.3.47 BPF_A2_LSB Register (Address = 42h) [reset = 00h]
BPF_A2_LSB is shown in Figure 91 and described in Table 55.
Return to Summary Table.
BPF A2 coefficient least-signifcant byte configuration
Figure 91. BPF_A2_LSB Register
7
6
5
4
3
2
1
0
BPF_A2_LSB
R/W-0h
Table 55. BPF_A2_LSB Register Field Descriptions
80
Bit
Field
Type
Reset
Description
7:0
BPF_A2_LSB
R/W
0h
Bandpass filter A2 coefficient least-signifcant byte value
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7.6.3.48 BPF_A3_MSB Register (Address = 43h) [reset = 00h]
BPF_A3_MSB is shown in Figure 92 and described in Table 56.
Return to Summary Table.
BPF A3 coefficient most-signifcant byte configuration
Figure 92. BPF_A3_MSB Register
7
6
5
4
3
2
1
0
BPF_A3_MSB
R/W-0h
Table 56. BPF_A3_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
BPF_A3_MSB
R/W
0h
Bandpass filter A3 coefficient most-signifcant byte value
7.6.3.49 BPF_A3_LSB Register (Address = 44h) [reset = 00h]
BPF_A3_LSB is shown in Figure 93 and described in Table 57.
Return to Summary Table.
BPF A3 coefficient least-signifcant byte configuration
Figure 93. BPF_A3_LSB Register
7
6
5
4
3
2
1
0
BPF_A3_LSB
R/W-0h
Table 57. BPF_A3_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
BPF_A3_LSB
R/W
0h
Bandpass filter A3 coefficient least-signifcant byte value
7.6.3.50 BPF_B1_MSB Register (Address = 45h) [reset = 00h]
BPF_B1_MSB is shown in Figure 94 and described in Table 58.
Return to Summary Table.
BPF B1 coefficient most-signifcant byte configuration
Figure 94. BPF_B1_MSB Register
7
6
5
4
3
2
1
0
BPF_B1_MSB
R/W-0h
Table 58. BPF_B1_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
BPF_B1_MSB
R/W
0h
Bandpass filter B1 coefficient most-signifcant byte value
7.6.3.51 BPF_B1_LSB Register (Address = 46h) [reset = 00h]
BPF_B1_LSB is shown in Figure 95 and described in Table 59.
Return to Summary Table.
BPF B1 coefficient least-signifcant byte configuration
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Figure 95. BPF_B1_LSB Register
7
6
5
4
3
2
1
0
BPF_B1_LSB
R/W-0h
Table 59. BPF_B1_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
BPF_B1_LSB
R/W
0h
Bandpass filter B1 coefficient least-signifcant byte value
7.6.3.52 LPF_A2_MSB Register (Address = 47h) [reset = 00h]
LPF_A2_MSB is shown in Figure 96 and described in Table 60.
Return to Summary Table.
LPF A2 coefficient most-signifcant byte configuration
Figure 96. LPF_A2_MSB Register
7
RESERVED
R-0h
6
5
4
3
LPF_A2_MSB
R/W-0h
2
1
0
Table 60. LPF_A2_MSB Register Field Descriptions
Bit
7
6:0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
LPF_A2_MSB
R/W
0h
Lowpass filter A2 coefficient most-signifcant byte value
7.6.3.53 LPF_A2_LSB Register (Address = 48h) [reset = 00h]
LPF_A2_LSB is shown in Figure 97 and described in Table 61.
Return to Summary Table.
LPF A2 coefficient least-signifcant byte configuration
Figure 97. LPF_A2_LSB Register
7
6
5
4
3
2
1
0
LPF_A2_LSB
R/W-0h
Table 61. LPF_A2_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
LPF_A2_LSB
R/W
0h
Lowpass filter A2 coefficient least-signifcant byte value
7.6.3.54 LPF_B1_MSB Register (Address = 49h) [reset = 00h]
LPF_B1_MSB is shown in Figure 98 and described in Table 62.
Return to Summary Table.
LPF B1 coefficient most-signifcant byte configuration
Figure 98. LPF_B1_MSB Register
7
RESERVED
R-0h
82
6
5
4
3
LPF_B1_MSB
R/W-0h
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1
0
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Table 62. LPF_B1_MSB Register Field Descriptions
Bit
7
6:0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
LPF_B1_MSB
R/W
0h
Lowpass filter B1 coefficient most-signifcant byte value
7.6.3.55 LPF_B1_LSB Register (Address = 4Ah) [reset = 00h]
LPF_B1_LSB is shown in Figure 99 and described in Table 63.
Return to Summary Table.
LPF B1 coefficient least-signifcant byte configuration
Figure 99. LPF_B1_LSB Register
7
6
5
4
3
2
1
0
LPF_B1_LSB
R/W-0h
Table 63. LPF_B1_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
LPF_B1_LSB
R/W
0h
Lowpass filter B1 coefficient least-signifcant byte value
7.6.3.56 TEST_MUX Register (Address = 4Bh) [reset = 00h]
TEST_MUX is shown in Figure 100 and described in Table 64.
Return to Summary Table.
Test multiplexers configuration register
Figure 100. TEST_MUX Register
7
6
TEST_MUX
R/W-0h
5
4
RESERVED
R-0h
3
SAMPLE_SEL
R/W-0h
2
1
DP_MUX
R/W-0h
0
Table 64. TEST_MUX Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
TEST_MUX
R/W
0h
Multiplexer output on the TEST Pin:
000b = GND ("Mux Off")
001b = Analog Front End output
010b = Reserved
011b = Reserved
100b = 8MHz clock
101b = ADC sample output clock
110b = Reserved
111b = Reserved
Note 1 000b through 011b are analog output signals
Note 2 100b through 111b are digital output signals
4
RESERVED
R
0h
Reserved
3
SAMPLE_SEL
R/W
0h
Data path sample select:
0b = 8 bit sample output at 1 µs per sample
1b = 12 bit sample output at 2 µs per sample
Note: For use with DP_MUX parameter values 001b to 100b
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Table 64. TEST_MUX Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2:0
DP_MUX
R/W
0h
Data path multiplexer source select codes:
000b = Disabled
001b = LPF output
010b = Rectifier output
011b = BPF output
100b = ADC output
101b = Not used
110b = Not used
111b = Not used
7.6.3.57 DEV_STAT0 Register (Address = 4Ch) [reset = 84h]
DEV_STAT0 is shown in Figure 101 and described in Table 65.
Return to Summary Table.
Device Status register 0
Figure 101. DEV_STAT0 Register
7
6
5
4
REV_ID
OPT_ID
R-2h
R-0h
3
CMW_WU_ER
R
R-0h
2
THR_CRC_ER
R
R-1h
1
0
EE_CRC_ERR TRIM_CRC_ER
R
R-0h
R-0h
Table 65. DEV_STAT0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
REV_ID
R
2h
Device Revision Identification
5:4
OPT_ID
R
0h
Device Option Identification
3
CMW_WU_ERR
R
0h
Wakeup Error indicator:
0 = no error
1 = user tried to send a command before the wake up sequence is
done
2
THR_CRC_ERR
R
1h
Threshold map configuration register data CRC error status:
0 = No error
1 = CRC error detected
This flag is asserted upon device power-up to indicate the uninitialized state of the threshold map configuration registers.
1
EE_CRC_ERR
R
0h
User EEPROM space data CRC error status:
0 = No error
1 = CRC error detected
0
TRIM_CRC_ERR
R
0h
Trim EEPROM space data CRC error status:
0 = No error
1 = CRC error detected
7.6.3.58 DEV_STAT1 Register (Address = 4Dh) [reset = 00h]
DEV_STAT1 is shown in Figure 102 and described in Table 66.
Return to Summary Table.
Device status register 1
Figure 102. DEV_STAT1 Register
7
RESERVED
R-0h
84
6
TSD_PROT
RC-0h
5
IOREG_OV
RC-0h
4
IOREG_UV
RC-0h
3
AVDD_OV
RC-0h
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2
AVDD_UV
RC-0h
1
VPWR_OV
RC-0h
0
VPWR_UV
RC-0h
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Table 66. DEV_STAT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6
TSD_PROT
RC
0h
Thermal shut-down protection status:
0 = No thermal shutdown has occured
1 = Thermal shutdown has occured
5
IOREG_OV
RC
0h
IOREG pin over voltage status:
0 = No error
1 = IOREG over voltage error
4
IOREG_UV
RC
0h
IOREG pin under voltage status:
0 = No error
1 = IOREG under voltage error
3
AVDD_OV
RC
0h
AVDD pin over voltage status:
0 = No error
1 = AVDD over voltage error
2
AVDD_UV
RC
0h
AVDD pin under voltage status:
0 = No Error
1 = AVDD Uuder voltage error
1
VPWR_OV
RC
0h
VPWR pin over voltage status:
0 = No error
1 = VPWR over voltage error
0
VPWR_UV
RC
0h
VPWR pin under voltage status:
0 = No error
1 = VPWR under voltage Error
7.6.3.59 P1_THR_0 Register (Address = 5Fh) [reset = X]
P1_THR_0 is shown in Figure 103 and described in Table 67.
Return to Summary Table.
Preset1 threshold map segment configuration register 0
Figure 103. P1_THR_0 Register
7
6
5
4
3
TH_P1_T1
R/W-X
2
1
0
TH_P1_T2
R/W-X
Table 67. P1_THR_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P1_T1
R/W
X
Preset1 Threshold T1 absolute time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
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Table 67. P1_THR_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
TH_P1_T2
R/W
X
Preset1 Threshold T2 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.60 P1_THR_1 Register (Address = 60h) [reset = X]
P1_THR_1 is shown in Figure 104 and described in Table 68.
Return to Summary Table.
Preset1 threshold map segment configuration register 1
Figure 104. P1_THR_1 Register
7
6
5
4
3
TH_P1_T3
R/W-X
2
1
0
TH_P1_T4
R/W-X
Table 68. P1_THR_1 Register Field Descriptions
86
Bit
Field
Type
Reset
Description
7:4
TH_P1_T3
R/W
X
Preset1 Threshold T3 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
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Table 68. P1_THR_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
TH_P1_T4
R/W
X
Preset1 Threshold T4 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.61 P1_THR_2 Register (Address = 61h) [reset = X]
P1_THR_2 is shown in Figure 105 and described in Table 69.
Return to Summary Table.
Preset1 threshold map segment configuration register 2
Figure 105. P1_THR_2 Register
7
6
5
4
3
TH_P1_T5
R/W-X
2
1
0
TH_P1_T6
R/W-X
Table 69. P1_THR_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P1_T5
R/W
X
Preset1 Threshold T5 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
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Table 69. P1_THR_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
TH_P1_T6
R/W
X
Preset1 Threshold T6 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.62 P1_THR_3 Register (Address = 62h) [reset = X]
P1_THR_3 is shown in Figure 106 and described in Table 70.
Return to Summary Table.
Preset1 threshold map segment configuration register 3
Figure 106. P1_THR_3 Register
7
6
5
4
3
TH_P1_T7
R/W-X
2
1
0
TH_P1_T8
R/W-X
Table 70. P1_THR_3 Register Field Descriptions
88
Bit
Field
Type
Reset
Description
7:4
TH_P1_T7
R/W
X
Preset1 Threshold T7 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
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Table 70. P1_THR_3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
TH_P1_T8
R/W
X
Preset1 Threshold T8 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.63 P1_THR_4 Register (Address = 63h) [reset = X]
P1_THR_4 is shown in Figure 107 and described in Table 71.
Return to Summary Table.
Preset1 threshold map segment configuration register 4
Figure 107. P1_THR_4 Register
7
6
5
4
3
TH_P1_T9
R/W-X
2
1
0
TH_P1_T10
R/W-X
Table 71. P1_THR_4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P1_T9
R/W
X
Preset1 Threshold T9 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
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Table 71. P1_THR_4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
TH_P1_T10
R/W
X
Preset1 Threshold T10 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.64 P1_THR_5 Register (Address = 64h) [reset = X]
P1_THR_5 is shown in Figure 108 and described in Table 72.
Return to Summary Table.
Preset1 threshold map segment configuration register 5
Figure 108. P1_THR_5 Register
7
6
5
4
3
TH_P1_T11
R/W-X
2
1
0
TH_P1_T12
R/W-X
Table 72. P1_THR_5 Register Field Descriptions
90
Bit
Field
Type
Reset
Description
7:4
TH_P1_T11
R/W
X
Preset1 Threshold T11 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
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Table 72. P1_THR_5 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
TH_P1_T12
R/W
X
Preset1 Threshold T12 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.65 P1_THR_6 Register (Address = 65h) [reset = X]
P1_THR_6 is shown in Figure 109 and described in Table 73.
Return to Summary Table.
Preset1 threshold map segment configuration register 6
Figure 109. P1_THR_6 Register
7
6
5
TH_P1_L1
R/W-X
4
3
2
1
TH_P1_L2
R/W-X
0
Table 73. P1_THR_6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:3
TH_P1_L1
R/W
X
Preset1 Threshold L1 level
This bit-field powers-up un-initialized.
2:0
TH_P1_L2
R/W
X
Preset1 Threshold L2 level bits (Bit4 to Bit2) This bit-field powers-up
un-initialized.
7.6.3.66 P1_THR_7 Register (Address = 66h) [reset = X]
P1_THR_7 is shown in Figure 110 and described in Table 74.
Return to Summary Table.
Preset1 threshold map segment configuration register 7
Figure 110. P1_THR_7 Register
7
6
5
4
TH_P1_L2
R/W-X
3
TH_P1_L3
R/W-X
2
1
0
TH_P1_L4
R/W-X
Table 74. P1_THR_7 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
TH_P1_L2
R/W
X
Preset1 Threshold L2 level (Bit1 to Bit0)
This bit-field powers-up un-initialized.
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Table 74. P1_THR_7 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5:1
TH_P1_L3
R/W
X
Preset1 Threshold L3 level
This bit-field powers-up un-initialized.
0
TH_P1_L4
R/W
X
Preset1 Threshold L4 level (Bit4) This bit-field powers-up uninitialized.
7.6.3.67 P1_THR_8 Register (Address = 67h) [reset = X]
P1_THR_8 is shown in Figure 111 and described in Table 75.
Return to Summary Table.
Preset1 threshold map segment configuration register 8
Figure 111. P1_THR_8 Register
7
6
5
4
3
2
TH_P1_L4
R/W-X
1
0
TH_P1_L5
R/W-X
Table 75. P1_THR_8 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P1_L4
R/W
X
Preset1 Threshold L4 level (Bits3 to Bit0)
This bit-field powers-up un-initialized.
3:0
TH_P1_L5
R/W
X
Preset1 Threshold L5 level (Bit4 to Bit1) This bit-field powers-up uninitialized.
7.6.3.68 P1_THR_9 Register (Address = 68h) [reset = X]
P1_THR_9 is shown in Figure 112 and described in Table 76.
Return to Summary Table.
Preset1 threshold map segment configuration register 9
Figure 112. P1_THR_9 Register
7
TH_P1_L5
R/W-X
6
5
4
TH_P1_L6
R/W-X
3
2
1
0
TH_P1_L7
R/W-X
Table 76. P1_THR_9 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TH_P1_L5
R/W
X
Preset1 Threshold L5 level (Bit0)
This bit-field powers-up un-initialized.
6:2
TH_P1_L6
R/W
X
Preset1 Threshold L6 level
This bit-field powers-up un-initialized.
1:0
TH_P1_L7
R/W
X
Preset1 Threshold L7 level (Bits4 to Bit3) This bit-field powers-up uninitialized.
7.6.3.69 P1_THR_10 Register (Address = 69h) [reset = X]
P1_THR_10 is shown in Figure 113 and described in Table 77.
Return to Summary Table.
Preset1 threshold map segment configuration register 10
92
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Figure 113. P1_THR_10 Register
7
6
TH_P1_L7
R/W-X
5
4
3
2
TH_P1_L8
R/W-X
1
0
Table 77. P1_THR_10 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
TH_P1_L7
R/W
X
Preset1 Threshold L7 Level (Bit2 to Bit0) This bit-field powers-up uninitialized.
4:0
TH_P1_L8
R/W
X
Preset1 Threshold L8 level
This bit-field powers-up un-initialized.
7.6.3.70 P1_THR_11 Register (Address = 6Ah) [reset = X]
P1_THR_11 is shown in Figure 114 and described in Table 78.
Return to Summary Table.
Preset1 threshold map segment configuration register 11
Figure 114. P1_THR_11 Register
7
6
5
4
3
2
1
0
1
0
TH_P1_L9
R/W-X
Table 78. P1_THR_11 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P1_L9
R/W
X
Threshold L9 level
This bit-field powers-up un-initialized.
7.6.3.71 P1_THR_12 Register (Address = 6Bh) [reset = X]
P1_THR_12 is shown in Figure 115 and described in Table 79.
Return to Summary Table.
Preset1 threshold map segment configuration register 12
Figure 115. P1_THR_12 Register
7
6
5
4
3
2
TH_P1_L10
R/W-X
Table 79. P1_THR_12 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P1_L10
R/W
X
Preset1 Threshold L10 Level
This bit-field powers-up un-initialized.
7.6.3.72 P1_THR_13 Register (Address = 6Ch) [reset = X]
P1_THR_13 is shown in Figure 116 and described in Table 80.
Return to Summary Table.
Preset1 threshold map segment configuration register 13
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Figure 116. P1_THR_13 Register
7
6
5
4
3
2
1
0
1
0
1
0
TH_P1_L11
R/W-X
Table 80. P1_THR_13 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P1_L11
R/W
X
Preset1 Threshold L11 Level
This bit-field powers-up un-initialized.
7.6.3.73 P1_THR_14 Register (Address = 6Dh) [reset = X]
P1_THR_14 is shown in Figure 117 and described in Table 81.
Return to Summary Table.
Preset1 threshold map segment configuration register 14
Figure 117. P1_THR_14 Register
7
6
5
4
3
2
TH_P1_L12
R/W-X
Table 81. P1_THR_14 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P1_L12
R/W
X
Preset1 Threshold L12 Level.
This bit-field powers-up un-initialized.
7.6.3.74 P1_THR_15 Register (Address = 6Eh) [reset = X]
P1_THR_15 is shown in Figure 118 and described in Table 82.
Return to Summary Table.
Preset1 threshold map segment configuration register 15
Figure 118. P1_THR_15 Register
7
6
5
4
3
RESERVED
R-X
2
TH_P1_OFF
R/W-X
Table 82. P1_THR_15 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
RESERVED
R
X
Reserved
3:0
TH_P1_OFF
R/W
X
Preset1 Threshold level Offset with values from 7 to -8 using signed
magnitude representation with MSB as the sign bit
This bit-field powers-up un-initialized.
7.6.3.75 P2_THR_0 Register (Address = 6Fh) [reset = X]
P2_THR_0 is shown in Figure 119 and described in Table 83.
Return to Summary Table.
Preset2 threshold map segment configuration register 0
94
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Figure 119. P2_THR_0 Register
7
6
5
4
3
2
TH_P2_T1
R/W-X
1
0
1
0
TH_P2_T2
R/W-X
Table 83. P2_THR_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_T1
R/W
X
Preset2 Threshold T1 absolute time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
3:0
TH_P2_T2
R/W
X
Preset2 Threshold T2 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.76 P2_THR_1 Register (Address = 70h) [reset = X]
P2_THR_1 is shown in Figure 120 and described in Table 84.
Return to Summary Table.
Preset2 threshold map segment configuration register 1
Figure 120. P2_THR_1 Register
7
6
5
4
3
TH_P2_T3
R/W-X
2
TH_P2_T4
R/W-X
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Table 84. P2_THR_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_T3
R/W
X
Preset2 Threshold T3 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
3:0
TH_P2_T4
R/W
X
Preset2 Threshold T4 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.77 P2_THR_2 Register (Address = 71h) [reset = X]
P2_THR_2 is shown in Figure 121 and described in Table 85.
Return to Summary Table.
Preset2 threshold map segment configuration register 2
Figure 121. P2_THR_2 Register
7
6
5
4
3
TH_P2_T5
R/W-X
96
2
1
0
TH_P2_T6
R/W-X
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Table 85. P2_THR_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_T5
R/W
X
Preset2 Threshold T5 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
3:0
TH_P2_T6
R/W
X
Preset2 Threshold T6 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.78 P2_THR_3 Register (Address = 72h) [reset = X]
P2_THR_3 is shown in Figure 122 and described in Table 86.
Return to Summary Table.
Preset2 threshold map segment configuration register 3
Figure 122. P2_THR_3 Register
7
6
5
4
3
TH_P2_T7
R/W-X
2
1
0
TH_P2_T8
R/W-X
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Table 86. P2_THR_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_T7
R/W
X
Preset2 Threshold T7 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
3:0
TH_P2_T8
R/W
X
Preset2 Threshold T8 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.79 P2_THR_4 Register (Address = 73h) [reset = X]
P2_THR_4 is shown in Figure 123 and described in Table 87.
Return to Summary Table.
Preset2 threshold map segment configuration register 4
Figure 123. P2_THR_4 Register
7
6
5
4
3
TH_P2_T9
R/W-X
98
2
1
0
TH_P2_T10
R/W-X
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Table 87. P2_THR_4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_T9
R/W
X
Preset2 Threshold T9 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
3:0
TH_P2_T10
R/W
X
Preset2 Threshold T10 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.80 P2_THR_5 Register (Address = 74h) [reset = X]
P2_THR_5 is shown in Figure 124 and described in Table 88.
Return to Summary Table.
Preset2 threshold map segment configuration register 5
Figure 124. P2_THR_5 Register
7
6
5
4
3
TH_P2_T11
R/W-X
2
1
0
TH_P2_T12
R/W-X
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Table 88. P2_THR_5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_T11
R/W
X
Preset2 Threshold T11 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
3:0
TH_P2_T12
R/W
X
Preset2 Threshold T12 delta time:
0000b = 100 µs
0001b = 200 µs
0010b = 300 µs
0011b = 400 µs
0100b = 600 µs
0101b = 800 µs
0110b = 1000 µs
0111b = 1200 µs
1000b = 1400 µs
1001b = 2000 µs
1010b = 2400 µs
1011b = 3200 µs
1100b = 4000 µs
1101b = 5200 µs
1110b = 6400 µs
1111b = 8000 µs
This bit-field powers-up un-initialized.
7.6.3.81 P2_THR_6 Register (Address = 75h) [reset = X]
P2_THR_6 is shown in Figure 125 and described in Table 89.
Return to Summary Table.
Preset2 threshold map segment configuration register 6
Figure 125. P2_THR_6 Register
7
6
5
TH_P2_L1
R/W-X
4
3
2
1
TH_P2_L2
R/W-X
0
Table 89. P2_THR_6 Register Field Descriptions
100
Bit
Field
Type
Reset
Description
7:3
TH_P2_L1
R/W
X
Preset2 Threshold L1 level
This bit-field powers-up un-initialized.
2:0
TH_P2_L2
R/W
X
Preset2 Threshold L2 level (Bit4 to Bit2) This bit-field powers-up uninitialized.
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7.6.3.82 P2_THR_7 Register (Address = 76h) [reset = X]
P2_THR_7 is shown in Figure 126 and described in Table 90.
Return to Summary Table.
Preset2 threshold map segment configuration register 7
Figure 126. P2_THR_7 Register
7
6
5
4
TH_P2_L2
R/W-X
3
TH_P2_L3
R/W-X
2
1
0
TH_P2_L4
R/W-X
Table 90. P2_THR_7 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
TH_P2_L2
R/W
X
Preset2 Threshold L2 level (Bit1 to Bit0) This bit-field powers-up uninitialized.
5:1
TH_P2_L3
R/W
X
Preset2 Threshold L3 level
This bit-field powers-up un-initialized.
0
TH_P2_L4
R/W
X
Preset2 Threshold L4 level (Bit4)
This bit-field powers-up un-initialized.
7.6.3.83 P2_THR_8 Register (Address = 77h) [reset = X]
P2_THR_8 is shown in Figure 127 and described in Table 91.
Return to Summary Table.
Preset2 threshold map segment configuration register 8
Figure 127. P2_THR_8 Register
7
6
5
4
3
2
TH_P2_L4
R/W-X
1
0
TH_P2_L5
R/W-X
Table 91. P2_THR_8 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
TH_P2_L4
R/W
X
Preset2 Threshold L4 level (Bit3 to Bit0)
This bit-field powers-up un-initialized.
3:0
TH_P2_L5
R/W
X
Preset2 Threshold L5 level (Bit4 to Bit1)
This bit-field powers-up un-initialized.
7.6.3.84 P2_THR_9 Register (Address = 78h) [reset = X]
P2_THR_9 is shown in Figure 128 and described in Table 92.
Return to Summary Table.
Preset2 threshold map segment configuration register 9
Figure 128. P2_THR_9 Register
7
TH_P2_L5
R/W-X
6
5
4
TH_P2_L6
R/W-X
3
2
1
0
TH_P2_L7
R/W-X
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Table 92. P2_THR_9 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TH_P2_L5
R/W
X
Preset2 Threshold L5 level (Bit0)
This bit-field powers-up un-initialized.
6:2
TH_P2_L6
R/W
X
Preset2 Threshold L6 level
This bit-field powers-up un-initialized.
1:0
TH_P2_L7
R/W
X
Preset2 Threshold L7 level (Bit4 to Bit3) This bit-field powers-up uninitialized.
7.6.3.85 P2_THR_10 Register (Address = 79h) [reset = X]
P2_THR_10 is shown in Figure 129 and described in Table 93.
Return to Summary Table.
Preset2 threshold map segment configuration register 10
Figure 129. P2_THR_10 Register
7
6
TH_P2_L7
R/W-X
5
4
3
2
TH_P2_L8
R/W-X
1
0
1
0
Table 93. P2_THR_10 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
TH_P2_L7
R/W
X
Preset2 Threshold L7 level (Bit2 to Bit0)
This bit-field powers-up un-initialized.
4:0
TH_P2_L8
R/W
X
Preset2 Threshold L8 level
This bit-field powers-up un-initialized.
7.6.3.86 P2_THR_11 Register (Address = 7Ah) [reset = X]
P2_THR_11 is shown in Figure 130 and described in Table 94.
Return to Summary Table.
Preset2 threshold map segment configuration register 11
Figure 130. P2_THR_11 Register
7
6
5
4
3
2
TH_P2_L9
R/W-X
Table 94. P2_THR_11 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P2_L9
R/W
X
Preset2 Threshold L9 level
This bit-field powers-up un-initialized.
7.6.3.87 P2_THR_12 Register (Address = 7Bh) [reset = X]
P2_THR_12 is shown in Figure 131 and described in Table 95.
Return to Summary Table.
Preset2 threshold map segment configuration register 12
102
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Figure 131. P2_THR_12 Register
7
6
5
4
3
2
1
0
1
0
1
0
TH_P2_L10
R/W-X
Table 95. P2_THR_12 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P2_L10
R/W
X
Preset2 Threshold L10 Level
This bit-field powers-up un-initialized.
7.6.3.88 P2_THR_13 Register (Address = 7Ch) [reset = X]
P2_THR_13 is shown in Figure 132 and described in Table 96.
Return to Summary Table.
Preset2 threshold map segment configuration register 13
Figure 132. P2_THR_13 Register
7
6
5
4
3
2
TH_P2_L11
R/W-X
Table 96. P2_THR_13 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P2_L11
R/W
X
Preset2 Threshold L11 Level
This bit-field powers-up un-initialized.
7.6.3.89 P2_THR_14 Register (Address = 7Dh) [reset = X]
P2_THR_14 is shown in Figure 133 and described in Table 97.
Return to Summary Table.
Preset2 threshold map segment configuration register 14
Figure 133. P2_THR_14 Register
7
6
5
4
3
2
TH_P2_L12
R/W-X
Table 97. P2_THR_14 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TH_P2_L12
R/W
X
Preset2 Threshold L12 Level
This bit-field powers-up un-initialized.
7.6.3.90 P2_THR_15 Register (Address = 7Eh) [reset = X]
P2_THR_15 is shown in Figure 134 and described in Table 98.
Return to Summary Table.
Preset2 threshold map segment configuration register 15
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Figure 134. P2_THR_15 Register
7
6
5
4
3
2
RESERVED
R-X
1
0
TH_P2_OFF
R/W-X
Table 98. P2_THR_15 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
RESERVED
R
X
Reserved
3:0
TH_P2_OFF
R/W
X
Preset2 Threshold level Offset with values from 7 to -8 using signed
magnitude representation with MSB as the sign bit
This bit-field powers-up un-initialized.
7.6.3.91 THR_CRC Register (Address = 7Fh) [reset = X]
THR_CRC is shown in Figure 135 and described in Table 99.
Return to Summary Table.
Threshold map configuration registers data CRC register
Figure 135. THR_CRC Register
7
6
5
4
3
2
1
0
THR_CRC
R/W-X
Table 99. THR_CRC Register Field Descriptions
104
Bit
Field
Type
Reset
Description
7:0
THR_CRC
R/W
X
Threshold map configuration registers data CRC value:
This read-only register is updated whenever a threshold map
configuration register gets updated
This bit-field powers-up un-initialized.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PGA460-Q1 device must be paired with an external transducer. The PGA460-Q1 device drives the
transducer, and then filters and processes the returned echo signal sensed by the transducer. The transducer
should be chosen based on the resonant frequency, input voltage requirements, sensitivity, beam pattern, and
decay time. The PGA460-Q1 device meets most transducer requirements by adjusting the driving frequency,
driving current limit, band-pass filtering coefficients, and low-pass filtering coefficients. The external transformer
or p-channel MOSFET should be chosen to meet the input voltage requirements of the transducer and have a
saturation current rated equal to or greater than the configured driving current limit of the PGA460-Q1 device.
The interface options include USART, TCI, and one-wire UART. After the burst-and-listen cycle is complete, the
PGA460-Q1 device can be called to return the distance, amplitude, and width of the echo through a
communication interface.
8.1.1 Transducer Types
The driver mode is dependant on the transducer type. Two types of transducers are available for open-air
ultrasonic measurements. Closed-top transducers are transducers which hermetically seal the piezoelectric
membrane from exposure to air or destructive particles. Closed-top transducer are favorable in applications that
are subject to harsh environmental conditions, such as exposure to outdoor elements, extreme temperature
changes, and debris. As a result of the additional protection offered by closed-top transducers, a transformerdriven method is typically required to maximize distance performance.
Open-top transducers are transducers with vents or slots that expose the piezoelectric membrane to the air.
Open-top transducers are favorable for controlled indoor applications to minimize the risk of the transducer
becoming damaged. Open-top transducers do not require as much driving voltage as closed-top transducers to
achieve maximum distance performance; therefore, a transformer is not necessary. For low-voltage driven
transducers, such as open-tops, a direct-drive (or bridge-drive) method can be used as an alternative to a
transformer. The direct-driven method can work on certain closed-top transducers, but the maximum achievable
distance will be reduced.
8.2 Typical Applications
In all typical applications, the PGA460-Q1 must be paired with at least one external transducer for generating an
ultrasonic echo to transmit through air and to detect the reflected echo returning from an object. The tasks of
transmitting and receiving the echo can be separated into independent transducers for improved performance. In
this case, the application must only detect ultrasonic echoes, no external driver components (transformer or pchannel MOSFET) are required.
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Typical Applications (continued)
8.2.1 Transformer-Driven Method
Figure 136 shows the transformer-driven method schematic for a single transducer.
R2
D1
R1
VIN
VPWR
D2
OUTA
+
100 nF
CT
XDCR
XFMR
+
TXD
UART
USART
SCLK
To MCU
(optional)
±
OUTB
100 …F
RXD
RINP
TCI/OWI UART
to ECU/BCM
INP
IO
L1
CINP
D3
C1
C2
INN
AVDD
CINN
100 nF
IOREG
QDECPL
DECPL
100 nF
Ferrite
Bead
GND
GNDP
PGA460-Q1
Copyright © 2017, Texas Instruments Incorporated
Figure 136. Transformer-Driven Method Schematic
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 100 as the input parameters.
Table 100. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
6 to 18 V
Input voltage recommended
7.4 V
Transformer turns ratio
(1-2) : (2-3) : (4-6) = 1:1:8.42
Transformer driving current rating
500 mA
Transformer main voltage (4-6) rating
200 VAC
Transducer driving voltage
120 VPP
Transducer frequency
58.5 kHz
Transducer pulse count
20
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Transducer
– Transducer driving voltage
– Transducer resonant frequency
– Transducer pulse count
• Driver
– Transformer turns ratio
– Transformer saturation current
– Transformer main voltage (4-6) rating
106
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Table 101 lists the recommended component values for typical applications.
Table 101. Recommended Component Values for Typical Applications
DESIGNATOR
VALUE
COMMENT
R1
10 Ω (1/2 Watt)
Optional (noise reduction)
R2
100 Ω(1/2 Watt)
Optional (limit in-rush current)
R(INP)
3 kΩ (1/4 Watt)
Optional (transformer drive only. For EMI/ESD robustness)
L1
100 nH
Optional (transient suppression)
C1
100 nF
Optional (Transient suppression)
C2
100 nF
Optional (transient suppression)
6
C(INP)
C(INP)
21.22 u 10
f(TRANSDUCER)
C(INN)
C(INN)
0.0024
f(TRANSDUCER)
CT
Value depends on transducer and transformer used
D1
1N4007 or equivalent
Schottky diode recommended
D2
VZ < 30 V
Optional (transient suppression)
D3
VBR < 30 V
Optional (transient suppression)
XDCR
Example devices for low-frequency range:
Closed top for transformer driven: muRata MA58MF14-7N,
SensComp 40KPT25
Open top for direct driven: muRata MA40H1S-R, SensComp
40LPT16, Kobitone 255-400PT160-ROX
XFMR
Example devices:
TDK EPCOS B78416A2232A003, muRata-Toko N1342DEA0008BQE=P3, Mitsumi K5-R4
QDECPL
Optional (time or temperature decoupling FET)
If no decoupling FET is used, ground the XFMR and CT
Q1
Can be FETs or BJTs as discrete implementation or transistor-array
package. Example devices:
Example devices: FDN358P Single FET, MUN5114 single BJT
Ferrite bead
BK215HS102-T or equivalent
Optional (noise reduction) ). Can be substituted with 0-Ω short.
8.2.1.2.1 Transducer Driving Voltage
When a voltage is applied to piezoelectric ceramics, mechanical distortion is generated according to the voltage
and frequency. The mechanical distortion is measured in units of sound pressure level (SPL) to indicate the
volume of sound, and can be derived from a free-field microphone voltage measurement using Equation 9.
§ V(MIC) ·
¨
¸
3.4 mV ¹
©
SPL (db) 20 u log
PO
where
•
•
V(MIC) is the measured sensor sound pressure (mVRMS).
PO is a referenced sound pressure of 20 μPa.
(9)
The SPL does not increase indefinitely with the driving voltage. After a particular driving voltage, the amount of
SPL that a transducer can generate becomes saturated. A transducer is given a maximum driving voltage
specification to indicate when the maximum SPL is generated. Driving the transducer beyond the maximum
driving voltage makes the ultrasonic module less power-efficient and can damage or decrease the life
expectancy of the transducer.
For the detailed procedure on measuring the SPL of a transducer, refer to PGA460 Ultrasonic Module Hardware
and Software Optimization.
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8.2.1.2.2 Transducer Driving Frequency
The strength of ultrasonic waves propagated into the air attenuate proportionally with distance. This attenuation
is caused by diffusion, diffraction, and absorption loss as the ultrasonic energy transmits through the medium of
air. As shown in Figure 137, the higher the frequency of the ultrasonic wave, the larger the attenuation rate and
the shorter the distance the wave reaches.
0
-10
-20
Attenuation (dB)
-30
-40
-50
-60
-70
-80
-90
-100
0.1
200 kHz
80 kHz
40 kHz
20 kHz
1
Distance (m)
10
D008
t = 20 °C
Figure 137. Attenuation Characteristics of Sound Pressure by Distance
An ultrasonic transducer has a fixed resonant center frequency with a typical tolerance of ±2%. The lower
frequency range of 30 to 80 kHz is the default operating range for common automotive and consumer
applications for a step resolution of 1 cm and typical range of 30 cm to 5m. The upper frequency range of 180 to
480 kHz is reserved for high-precision industrial applications with a step resolution of 1 mm and a typical range
of 5 cm to 1 m.
8.2.1.2.3 Transducer Pulse Count
The pulse count determines how many alternating periods are applied to the transducer by the complementary
low-side drivers and determines the total width of the ultrasonic ping that was transmitted. The larger the width of
the transmitted ping, the larger the width of the returned echo signature of the reflected surface and the more
resolution available to set a stable threshold. A disadvantage of a large pulse count is a large ringing-decay
period, which limits how detectable objects are at short distances.
Select a pulse count based on the minimum object distance requirement. If short-distance object detection is not
a priority, a high pulse count is not a concern. Certain transducers can be driven continuously while others have
a limit to the maximum driving-pulse count. Refer to the specification for the selected transducer to determine if
the pulse count must be limited.
8.2.1.2.4 Transformer Turns Ratio
A center-tap transformer is typically paired with the transducer to convert a DC voltage to a high-sinusoidal AC
voltage. The center tap is a contact made to a point halfway along the primary winding of the transformer. The
center tap is supplied with the DC voltage that is then multiplied on the secondary side based on the turns ratio
of the transformer. Figure 138 shows the typical pinout of a center-tap transformer where pin 2 is the center tap,
pins 1 and 3 are connected to OUTB and OUTA, pin 4 is connected to the positive terminal of the transducer,
and pin 6 is connected to ground.
108
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3
4
N1b
2
N2
N1a
1
6 (GND)
Figure 138. Typical Pinout of Center-Tap Transformer for Ultrasonic Transducers
Two modes to generate the transducer voltage using the center tap transformer are available. These modes are
defined as follows:
Push-pull
In this mode, the two internal low-side switches of the PGA460-Q1 device are used to turn current
on and off in two primary coils of the center-tap transformer.
The primary coils have the same number of turns. The rate of change of current in the
primary coil generates a voltage in the secondary coil of the transformer, which is connected
to the transducer. The direction of current in the primary coils generates voltages of opposite
polarity in the secondary coils which effectively doubles the peak-to-peak voltage in the
secondary coil.
Single-ended In this mode, one low-side switch is used to turn current on and off in the primary of the
transformer.
The rate of change of current in the primary coil generates a voltage in the secondary coil of
the transformer, which is connected to the transducer. The center tap of the transformer is
not required for this mode, and can be left floating. Instead, the reference voltage is
connected to an outermost primary-side terminal (pin 3) and either OUTA or OUTB is
connected to the other primary-side terminal (pin1).
8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
Leakage inductance is caused when magnetic flux is not completely coupled between windings in a transformer.
Magnetic saturation of a transformer core can be caused by excessive primary voltage, operation at too low of a
frequency, by the presence of a DC current in any of the windings, or a combination of these causes. The
PGA460-Q1 device can limit the primary-side driver current of the transformer internally from 50 to 500 mA. The
center-tap voltage is typically referenced to the VPWR voltage. However, if the VPWR voltage is too high of a
voltage on the center tap of the primary side, then the voltage must be down-regulated. If the VPWR is too low,
then the voltage must be up-regulated.
8.2.1.3 Application Curves
Components used: TDK EPCOS B78416A2232A003 Transformer, muRata MA58MF14-7N transducer. To
minimize the ranging of the TDK EPCOS B78416A2232A003 transformer and muRata MA58MF14-7N
transducer combination, place a 680pF tuning capacitor (CT) and 10kΩ damping resistor (RDamp) in parallel to the
transducer. This will enable sub-15cm ranging depending on the pulse count, center-tap voltage, and driver
current limit.
Data shown in Figure 139 and Figure 140 was recorded using the echo dump feature of the PGA460-Q1 device
(see the Echo Data Dump section)
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300
300
1m
2m
3m
4m
250
Echo Amplitude (8-bit)
250
Echo Amplitude (8-bit)
30 cm
40 cm
60 cm
80 cm
100 cm
5m
200
150
100
200
150
100
50
50
0
0
0
5
10
15
20
Time (ms)
25
30
35
0
1
2
3
D001
Figure 139. Long Range ISO-Pole Measurements Using
Transformer Drive
4
5
Time (ms)
6
7
8
9
D002
Figure 140. Short Range ISO-Pole Measurements Using
Transformer Drive
8.2.2 Direct-Driven (Transformer-Less) Method
The direct-driven method substitutes the traditional center-tap transformer with a bridge driver, and is suitable for
plastic-shelled open-top transducers. Any open or closed top transducer can be driven directly, but the maximum
amount of SPL may not be generated during transmission. The direct-driven configuration uses either a halfbridge or full-bridge gate driver to generate an alternating square wave to drive the transducer. By default, the
half-bridge driver configuration is enabled to allow the use of a single transducer to transmit and receive. The
PGA460-Q1 device cannot drive a single transducer in the full-bridge configuration without the addition of
external components (beyond the scope of this document).. Because the low-side drivers are integrated into the
PGA460-Q1 device, only one external high-side p-channel MOSFET is required. In the half-bridge configuration,
one OUTx channel is used to drive the p-channel MOSFET, while the other is used to directly excite the
transducer.. Figure 141 shows the direct-driven method schematic for a single transducer.
Q1
D1
R1
VIN
VPWR
D2
OUTA
+
100 nF
±
OUTB
XDCR
TXD
UART
To MCU
(optional)
USART
SCLK
RXD
TCI/OWI UART
to ECU/BCM
INP
IO
L1
C(INP)
D3
C1
C2
INN
AVDD
C(INN)
100 nF
IOREG
DECPL
100 nF
Ferrite
Bead
GND
GNDP
PGA460-Q1
Copyright © 2017, Texas Instruments Incorporated
Figure 141. Direct-Driven Method Schematic
110
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 102 as the input parameters.
Table 102. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
6 to 7.2 V
Input voltage recommended
7.2 V
Transducer driving voltage
7.2 VPP
Transducer frequency
40 kHz
Transducer pulse count
20
8.2.2.2 Detailed Design Procedure
For recommended component values in typical applications, see Table 101.
8.2.2.3 Application Curves
Components used: Fairchild FDC6506P p-channel MOSFET, muRata MA40H1S-R transducer
Data shown in Figure 139 and Figure 140 was recorded using the echo dump feature of the PGA460-Q1 device
(see the Echo Data Dump section)
300
300
1m
2m
3m
4m
5m
200
250
Echo Amplitude (8-bit)
Echo Amplitude (8-bit)
250
30 cm
40 cm
60 cm
150
100
80 cm
100 cm
200
150
100
50
50
0
0
0
5
10
15
20
Time (ms)
25
30
35
0
1
D003
Figure 142. Long Range ISO-Pole Measurements Using
Direct Drive
2
3
4
5
Time (ms)
6
7
8
9
D004
Figure 143. Short Range ISO-Pole Measurements Using
Direct Drive
9 Power Supply Recommendations
The PGA460-Q1 device is designed to operate from an input voltage supply range from 6 V to 28 V. In
automotive applications, the PGA460-Q1 device should only be connected directly to a car battery with proper
external component-safeguards (D1 and D2) to help protect the device from battery transients and reverse
battery currents. If the input supply is located more than a few inches from the PGA460-Q1 device, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
The electrolytic capacitor at the VPWR pin is intended to act as a fast discharge capacitor during the bursting
stage of the PGA460-Q1 device. The center-tap transformer can be supplied with a center-tap voltage that is
different than what is supplied to the VPWR pin, but must remain within specified maximum voltage rating of the
OUTA and OUTB outputs. No electrolytic capacitor is required for the direct-driven method, although it is
recommended for reference voltage stability, and can be less than 100 µF.
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PGA460-Q1
SLASEC8B – FEBRUARY 2017 – REVISED JANUARY 2019
www.ti.com
10 Layout
10.1 Layout Guidelines
A minimum of two layers is required to a accomplish a small-form factor ultrasonic module design. The layers
should be separated by analog and digital signals. The pin map of the device is routed such that the power and
digital signals are on the opposing side of the analog driver and receiver pins. Consider the following best
practices for PGA460-Q1 device layout in order of descending priority:
• Separating the grounding types is important to reduce noise at the AFE input of the PGA460-Q1. In particular,
the transducer sensor ground, supporting driver, and return-path circuitry should have a separate ground
before being connected to the main ground. Separating the sensor and main grounds through a ferrite bead
is best practice, but not required; a copper-trace or 0-Ω short is also acceptable when bridging grounds.
• The analog return path pins, INP and INN, are most susceptible to noise and therefore should be routed as
short and directly to the transducer as possible. Ensure the INN capacitor is close to the pin to reduce the
length of the ground wire.
• In applications where protection from an ESD strike on the case of the transducer is important, ground routing
of the capacitor on the INN pin should be separate from the device ground and connected directly with the
shortest possible trace to the connector ground.
• The analog drive pins can be high-current, high-voltage, or both and therefore the design limitation of the
OUTA and OUTB pins is based on the copper trace profile. The driver pins are recommended to be as short
and direct as possible when using a transformer, and driving the primary windings with a high-current limit
• The decoupling capacitors for the AVDD, IOREG, and VPWR pins should be placed as close to the pins as
possible
• Any digital communication should be routed away from the analog receiver pins. The IO, TXD, RXD, and
SCLK pins should be routed on the opposite side of the PCB, away from of the analog signals. When the IO
pin is referenced to a high-voltage VPWR, and operating at a high-speed baud rate, the trace to the
connector or master should be as direct as possible
10.2 Layout Example
Legend
To Power Source
Copper Trace - Top
Copper Trace - Bottom
Via
Vias to GND
GND 1
INP 2
14 IOREG
GND 4
13 DECPL
12 SCLK
To Master
GNDP 6
11 RXD
To Master
OUTB 7
10 TXD
To Master
IO 8
9 TEST
OUTA 5
Transformer
Sensor Ground
15 VPWR
INN 3
+
Transducer
16 AVDD
Charging
Capacitor
100 F
To Master
Figure 144. PGA460-Q1 Layout Example
112
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: PGA460-Q1
PGA460-Q1
www.ti.com
SLASEC8B – FEBRUARY 2017 – REVISED JANUARY 2019
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PGA460 Frequently Asked Questions (FAQ) and EVM Troubleshooting Guide (SLAA733)
• PGA460 Software Development Guide (SLAA730)
• PGA460 Ultrasonic Module Hardware and Software Optimization (SLAA732)
• PGA460-Q1 EVM Quick Start Guide (SLVUB17)
• PGA460-Q1 EVM User's Guide (SLAU659)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: PGA460-Q1
113
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PGA460TPWQ1
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
PGA460
PGA460TPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
PGA460
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jan-2019
OTHER QUALIFIED VERSIONS OF PGA460-Q1 :
• Catalog: PGA460
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PGA460TPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PGA460TPWRQ1
TSSOP
PW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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