Texas Instruments | IWR1443 Single-Chip 76- to 81-GHz mmWave Sensor (Rev. C) | Datasheet | Texas Instruments IWR1443 Single-Chip 76- to 81-GHz mmWave Sensor (Rev. C) Datasheet

Texas Instruments IWR1443 Single-Chip 76- to 81-GHz mmWave Sensor (Rev. C) Datasheet
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IWR1443
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
IWR1443 Single-Chip 76- to 81-GHz mmWave Sensor
1 Device Overview
1.1
Features
1
• FMCW Transceiver
– Integrated PLL, Transmitter, Receiver,
Baseband, and A2D
– 76- to 81-GHz Coverage With 4-GHz
Continuous Bandwidth
– Four Receive Channels
– Three Transmit Channels (Two Can be Used
Simultaneously)
– Ultra-Accurate Chirp Engine Based on
Fractional-N PLL
– TX Power: 12 dBm
– RX Noise Figure:
– 14 dB (76 to 77 GHz)
– 15 dB (77 to 81 GHz)
– Phase Noise at 1 MHz:
– –95 dBc/Hz (76 to 77 GHz)
– –93 dBc/Hz (77 to 81 GHz)
• Built-in Calibration and Self-Test
– ARM® Cortex®-R4F-Based Radio Control
System
– Built-in Firmware (ROM)
– Self-calibrating System Across Frequency and
Temperature
• On-Chip Programmable Core for Embedded User
Application
– Integrated Cortex®-R4F Microcontroller Clocked
at 200 MHz
– On-Chip Bootloader Supports Autonomous
Mode (Loading User Application From QSPI
Flash Memory)
– Integrated Peripherals
– Internal Memories With ECC
– Radar Hardware Accelerator (FFT, Logmagnitude Computations, and others)
– Integrated Timers (Watch Dog and up to Four
32-Bit or Two 64-Bit Timers)
1.2
•
•
•
•
•
•
•
•
•
•
•
– I2C (Master and Slave Modes Supported)
– Two SPI Ports
– CAN Port
– Up to Six General-Purpose ADC Ports
High-Speed Data Interface to Support Distributed
Applications
Host Interface
– Control Interface With External Processor Over
SPI
– Data Interface With External Processor Over
MIPI D-PHY and CSI2 V1.1
– Interrupts for Fault Reporting
IWR1443 Advanced Features
– Embedded Self-monitoring With No Host
Processor Involvement
– Complex Baseband Architecture
– Embedded Interference Detection Capability
Power Management
– Built-in LDO Network for Enhanced PSRR
– I/Os Support Dual Voltage 3.3 V/1.8 V
Clock Source
– Supports External Oscillator at 40 MHz
– Supports Externally Driven Clock (Square/Sine)
at 40 MHz
Easy Hardware Design
– 0.65-mm Pitch, 161-Pin 10.4 mm × 10.4 mm
Flip Chip BGA Package for Easy Assembly and
Low-Cost PCB Design
– Small Solution Size
Operating Conditions
– Junction Temp Range: –40°C to 105°C
Applications
Industrial Sensor for Measuring Range, Velocity,
and Angle
Tank Level Probing Radar
Displacement Sensing
Field Transmitters
•
•
•
•
•
Traffic Monitoring
Proximity and Position Sensing
Security and Surveillance
Factory Automation
Safety Guards
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
IWR1443
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
www.ti.com
Stored
Program
40 Mhz
Crystal
QSPI
Flash
Rx1
SPI
Control and Data
Communication
Interface
UART
Control and Data
Communication
Interface
CAN
Control and Data
Communication
Interface
CSI-2
LVDS
High Speed
Data Interface
LVDS or
CSI-2
Rx2
Rx3
Rx4
Radar
Front
End
R4F ARM
Control and Computation Processor
Hardware Accelerator, and Peripherals
Tx1
Tx2
Tx3
DC Power
and Power
Management
Figure 1-1. Autonomous Sensor For Industrial Applications
1.3
Description
The IWR1443 device is an integrated single-chip mmWave sensor based on FMCW radar technology
capable of operation in the 76- to 81-GHz band with up to 4 GHz continuous chirp. The device is built with
TI’s low-power 45-nm RFCMOS process, and this solution enables unprecedented levels of integration in
an extremely small form factor. The IWR1443 is an ideal solution for low-power, self-monitored, ultraaccurate radar systems in the industrial applications such as building automation, factory automation,
drones, material handling, traffic monitoring, and surveillance.
The IWR1443 device is a self-contained, single-chip solution that simplifies the implementation of
mmWave sensors in the band of 76 to 81 GHz. The IWR1443 includes a monolithic implementation of a
3TX, 4RX system with built-in PLL and A2D converters. The device includes fully configurable hardware
accelerator that supports complex FFT and CFAR detection. Additionally, the device includes two ARM
R4F-based processor subsystems: one processor subsystem is for master control, and additional
algorithms; a second processor subsystem is responsible for front-end configuration, control, and
calibration. Simple programming model changes can enable a wide variety of sensor implementation with
the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally, the device is
provided as a complete platform solution including reference hardware design, software drivers, sample
configurations, API guide, training, and user documentation.
Device Information (1)
PART NUMBER
IWR1443FQAGABLR (Tape and Reel)
IWR1443FQAGABL (Tray)
(1)
2
PACKAGE
BODY SIZE
FCBGA (161)
10.4 mm × 10.4 mm
For more information, see Section 9, Mechanical Packaging and Orderable Information.
Device Overview
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1.4
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Functional Block Diagram
Rx1
LNA
IF
ADC
Cortex R4F
@ 200MHz
Rx2
LNA
IF
ADC
Digital Frontend
(Decimation
filter chain)
Rx3
LNA
IF
ADC
LNA
IF
ADC
(User programmable)
Prog
RAM
Data
RAM (*)
Boot
ROM
Rx4
Tx1
Tx3
PA
BPM
PA
BPM
RF/Analog sub-system
x4
Synth
(20 GHz)
DMA
Ramp
Generator
Radar Data
Memory (*)
(L3)
Temp
6
GPADC
Master sub-system
(Customer programmed)
RF Control
BIST
Bus Matrix
Tx2
BPM
Bus Matrix
PA
QSPI Flash
interface
QSPI
Hardware
Accelerator
(**)
ADC Buffer
(**)
SPI
External MCU
interface
SPI / I2C
PMIC control
DCAN
Optional communication
interface
Debug
UARTs
Control UART,
And Debug UART
Test/
Debug
JTAG for debug/
development
LVDS/
CSI-2
High-speed Rx or
process
Data for recording or
External DSP
Mailbox
Osc.
(*) Total RAM available in Master subsystem is divided into ARM-Data RAM, Tightly Coupled Memory, Radar Data Memory, Patch Memory
(**) Shared Memory for ADC Buffer and Hardware Accelerator
Device Overview
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Table of Contents
1
2
3
Device Overview ......................................... 1
6.1
Overview
1.1
Features .............................................. 1
6.2
Functional Block Diagram ........................... 51
1.2
Applications ........................................... 1
6.3
External Interfaces .................................. 52
1.3
Description ............................................ 2
6.4
Subsystems
1.4
Functional Block Diagram ............................ 3
6.5
Accelerators and Coprocessors ..................... 57
Revision History ......................................... 5
Device Comparison ..................................... 7
6.6
Other Subsystems................................... 58
6.7
Identification ......................................... 62
Related Products ..................................... 8
6.8
Boot Modes.......................................... 62
3.1
4
Terminal Configuration and Functions .............. 9
.......................................... 9
4.2
Signal Descriptions .................................. 13
4.3
Pin Multiplexing ..................................... 16
Specifications ........................................... 21
5.1
Absolute Maximum Ratings ......................... 21
5.2
ESD Ratings ........................................ 21
5.3
Power-On Hours (POH) ............................. 21
5.4
Recommended Operating Conditions ............... 22
5.5
Power Supply Specifications ........................ 22
5.6
Power Consumption Summary...................... 23
5.7
RF Specification ..................................... 24
4.1
5
5.8
5.9
6
4
7
Pin Diagram
Thermal Resistance Characteristics for FCBGA
Package [ABL0161] ................................. 25
Timing and Switching Characteristics ............... 25
Detailed Description ................................... 51
8
.........................................
51
52
Applications, Implementation, and Layout........ 65
7.1
Application Information .............................. 65
7.2
Reference Schematic ............................... 65
7.3
Layout ............................................... 66
Device and Documentation Support ............... 67
8.1
Device Nomenclature ............................... 67
8.2
Tools and Software
8.3
Documentation Support ............................. 68
8.4
Community Resources .............................. 69
8.5
Trademarks.......................................... 69
8.6
Electrostatic Discharge Caution ..................... 69
8.7
Export Control Notice
8.8
9
............................................
.................................
...............................
Glossary .............................................
68
69
69
Mechanical, Packaging, and Orderable
Information .............................................. 70
9.1
Packaging Information
Table of Contents
..............................
70
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from February 20, 2018 to October 31, 2018 (from B Revision (February 2018) to C Revision)
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Updated RX Noise Figure from "15 dB (76 to 77 GHz)" to "14 dB (76 to 77 GHz)" ......................................... 1
Updated RX Noise Figure from "16 dB (77 to 81 GHz)" to "15 dB (77 to 81 GHz)" ......................................... 1
Updated Phase Noise at 1 MHz from "–94 dBc/Hz (76 to 77 GHz)" to "–95 dBc/Hz (76 to 77 GHz)" .................... 1
Updated Phase Noise at 1 MHz from "–91 dBc/Hz (77 to 81 GHz)" to "–93 dBc/Hz (77 to 81 GHz)" .................... 1
Removed "(Namely, Intermediate Data)" from "High-Speed Data Interface..." bullet ....................................... 1
Removed 50 MHz from Externally Driven Oscillator and Externally Driven Clock ........................................... 1
Updated Device Information ......................................................................................................... 2
Removed VMON block from Functional Block Diagram ......................................................................... 3
Added table note to "Number of transmitters" in Device Features Comparison .............................................. 7
Updated IWR1443 and IWR1642 Product status from AI to PD ............................................................... 7
Updated OSC_CLKOUT ........................................................................................................... 13
Updated P7 from "Open Drain" to "Pull Up' ...................................................................................... 13
Updated B10 DESCRIPTION ...................................................................................................... 14
Updated A10, A13, A2, and B2 DESCRIPTION ................................................................................ 14
Removed footnote from Flash programming and RS232 UART .............................................................. 15
Updated ESD Ratings .............................................................................................................. 21
Updated/Changed Power-On Hours (POH) ..................................................................................... 21
Updated VIOIN in Recommended Operating Conditions ...................................................................... 22
Updated VIL 1.8V MAX from "3*VIOIN" to "0.3*VIOIN" ......................................................................... 22
Updated VOH in Recommended Operating Conditions ......................................................................... 22
Updated VOH in Recommended Operating Conditions ......................................................................... 22
Updated Recommended Operating Conditions ................................................................................. 22
Added "VNWA" to 1.2 V Supply in Power Supply Rails Characteristics ..................................................... 22
Completely updated Ripple Specifications table ................................................................................ 23
Updated Receiver Noise figure values in RF Specification .................................................................... 24
Updated Receiver 1-dB compression point value from "–5" to "–8" .......................................................... 24
Updated "IQ gain mismatch" to "Image Rejection Ratio (IMRR)" ............................................................. 24
Removed IQ phase mismatch from RF Specification .......................................................................... 24
Updated RF Specification table ................................................................................................... 24
Updated footnote in RF Specification............................................................................................. 25
Removed 1v4 signal from Device Wakeup ..................................................................................... 26
Updated Device Wake-up Sequence ............................................................................................. 26
Updated Synchronized Frame Triggering text .................................................................................. 27
Added Synchronized Frame Triggering subsection............................................................................. 27
Removed TLag from Frame Trigger Timing table ............................................................................... 27
Updated Crystal Implementation note ............................................................................................ 28
Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40".......................................... 28
Completely updated External Clock Mode Specifications ..................................................................... 29
Updated SPI Slave Mode Timing Requirements ................................................................................ 35
Added LVDS Interface Configuration ............................................................................................. 38
Updated LVDS Interface Lane Config image .................................................................................... 38
Updated Timing Parameters ....................................................................................................... 38
Updated LVDS Electrical Characteristics ....................................................................................... 39
Updated Timing Requirements for QSPI Input (Read) Timings ............................................................... 44
Added Q12, Q13, Q14, and Q15 to QSPI Switching Characteristics ........................................................ 45
Updated Data bit rate from 900 Mbps to 600 Mbps ............................................................................ 48
Removed TCLK-SETTLE and THS-SETTLE ............................................................................................... 48
Updated Clock Subsystem diagram .............................................................................................. 53
Updated/Changed Transmit Subsystem (Per Channel) ........................................................................ 54
Removed Master System Memory Map .......................................................................................... 56
Updated Host Interface ............................................................................................................. 57
Updated text in "A2D Data Format Over CSI2 Interface" ...................................................................... 58
Updated text in ADC Channels (Service) for User Application ................................................................ 60
Completely updated GP-ADC Parameter table ................................................................................. 60
Revision History
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•
•
•
6
www.ti.com
Updated text in Functional Mode .................................................................................................. 64
Updated Application Information .................................................................................................. 65
Updated Device Nomenclature .................................................................................................... 68
Revision History
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3 Device Comparison
Table 3-1. Device Features Comparison
FUNCTION
IWR1443
IWR1642
Number of receivers
4
4
Number of transmitters
3
2
576KB
1.5MB
On-chip memory
Max I/F (Intermediate Frequency) (MHz)
15
5
Max real sampling rate (Msps)
37.5
12.5
Max complex sampling rate (Msps)
18.75
6.25
Yes
Yes
—
Yes
Processor
MCU (R4F)
DSP (C674x)
Peripherals
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
Inter-Integrated Circuit (I2C) interface
1
2
Yes
Yes
1
1
Yes
Yes
Trace
—
Yes
PWM
—
Yes
Hardware In Loop (HIL/DMM)
—
Yes
GPADC
Yes
Yes
LVDS/Debug
Yes
Yes
CSI2
Yes
—
Hardware accelerator
Yes
—
1-V bypass mode
Yes
Yes
Yes
Yes
PD (1)
PD (1)
Controller Area Network (DCAN) interface
JTAG
Product status
(1)
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Comparison
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3.1
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Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with
less power using the smallest footprint mmWave sensor portfolio for industrial applications.
mmWave IWR The Texas Instruments IWR1xxx family of mmWave Sensors are highly integrated and
built on RFCMOS technology operating in 76- to 81-GHz frequency band. The devices have
a closed-loop PLL for precise and linear chirp synthesis, includes a built-in radio processor
(BIST) for RF calibration and safety monitoring. The devices have a very small-form factor,
low power consumption, and are highly accurate. Industrial applications from long range to
ultra short range can be realized using these devices.
Companion Products for IWR1443 Review products that are frequently purchased or used in
conjunction with this product.
IWR1443 Reference Designs The IWR1443 TI Designs Reference Design Library is a robust reference
design library spanning analog, embedded processor and connectivity. Created by TI experts
to help you jump-start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Power Optimization for IWR1443 77GHz-Level Transmitter Reference Design
The
TIDEP-0091
highlights strategies for power optimization of a IWR1443 76- to 81-GHz mmWave sensor in
tank level-probing applications, displacement sensors, 4- to 20-mA sensors, and other lowpower applications for detecting range with high accuracy in minimal power envelope.
8
Device Comparison
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4 Terminal Configuration and Functions
4.1
Pin Diagram
Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4,
and Figure 4-5 show the same pins, but split into four quadrants.
1
2
3
A
VSSA
VOUT_PA
VSSA
B
RESERVED
VOUT_PA
VSSA
TX1
VSSA
TX2
VSSA
C
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
D
RESERVED
VIN
_13RF2
E
VSSA
VSSA
VSSA
VSS
RX4
VSSA
VIN_18BB
VSSA
VSSA
VIN
_13RF1
RX3
VSSA
VIN
_13RF1
VSSA
VSSA
VIN
_13RF1
RX2
VSSA
VIN_18BB
VSSA
VSSA
VSS
RX1
VSSA
VSSA
VSSA
F
G
VSSA
H
J
VSSA
K
L
VSSA
M
N
P
R
VSSA
4
6
7
VSSA
8
9
10
VSSA
VOUT
_14APLL
TX3
VSSA
VBGAP
VSSA
VSSA
VSSA
11
VIN
_18CLK
12
VIN
_18VCO
13
14
15
VOUT
_14SYNTH
OSC
_CLKOUT
VSSA
VSSA
VSSA
RESERVED
ANAMUX/
GPADC5
VSENSE/
GPADC6
VSSA
VIOIN
_18DIFF
GPIO[0]
Analog Test 1/ Analog Test 2/ Analog Test 3/
GPADC1
GPADC2
GPADC3
Reserved
Analog Test 4/
GPADC4
Reserved
VSSA
5
Reserved
RS232_RX
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RS232_TX
VDDIN
SPI_CS_1
VSSA
CLKP
VSS
VDDIN
CLKM
Reserved
CSI2
_TXM[0]
CSI2
_TXP[0]
TDI
CSI2
_TXM[1]
CSI2
_TXP[1]
TDO
CSI2_CLKM
CSI2_CLKP
VIOIN_18
CSI2
_TXM[2]
CSI2
_TXP[2]
TMS
CSI2
_TXM[3]
CSI2
_TXP[3]
TCK
HS_M
_Debug1
HS_P
_Debug1
VSS
VSS
VSS
VSS
GPIO[1]
VSS
VSS
VSS
VSS
MISO_1 SPI_HOST_INTR_1NERROR_IN
Reserved
VSS
VSS
VSS
VSS
NERROR_OUTMCU_CLK_OUT
RESERVED
VSSA
Sync_in
VDDIN
WARM
_RESET
GPIO[2]
HS_M
_Debug2
HS_P
_Debug2
QSPI_CS
QSPI[1]
QSPI[3]
Sync_out
NRESET
PMIC_CLK_OUT
VNWA
VDDIN
MOSI_1
SPI_CLK_1
QSPI_CLK
QSPI[0]
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
Figure 4-1. Pin Diagram
Terminal Configuration and Functions
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1
2
3
A
VSSA
VOUT_PA
VSSA
B
RESERVED
VOUT_PA
VSSA
TX1
VSSA
TX2
VSSA
TX3
C
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
D
RESERVED
VIN
_13RF2
E
VSSA
VSSA
VSSA
VSS
VSS
RX4
VSSA
VIN_18BB
VSSA
VSSA
VIN
_13RF1
F
G
VSSA
4
5
6
7
VSSA
8
VSSA
VSS
VSS
VSS
VSS
Not to scale
1
2
3
4
Figure 4-2. Top Left Quadrant
9
10
11
A
VSSA
VOUT
_14APLL
B
VSSA
VBGAP
C
VSSA
VIN
_18CLK
12
VIN
_18VCO
13
14
15
VOUT
_14SYNTH
OSC
_CLKOUT
VSSA
VSSA
VSSA
RESERVED
ANAMUX/
GPADC5
VSENSE/
GPADC6
VSSA
VIOIN
_18DIFF
D
E
VSS
F
VSS
G
VSS
RESERVED
VSS
VSSA
CLKP
VSS
VDDIN
CLKM
Reserved
CSI2
_TXM[0]
VSSA
CSI2
_TXP[0]
Not to scale
1
2
3
4
Figure 4-3. Top Right Quadrant
10
Terminal Configuration and Functions
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1
H
J
VSSA
K
L
VSSA
M
N
P
VSSA
2
3
4
RX3
VSSA
VIN
_13RF1
VSSA
VSSA
VIN
_13RF1
RX2
VSSA
VIN_18BB
VSSA
VSSA
VSS
VSS
RX1
VSSA
VSSA
VSSA
RS232_RX
RS232_TX
GPIO[0]
Analog Test 1/ Analog Test 2/ Analog Test 3/
GPADC1
GPADC2
GPADC3
Reserved
Analog Test 4/
GPADC4
Reserved
R
VSSA
Reserved
5
6
7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIO[1]
MISO_1 SPI_HOST_INTR_1NERROR_IN
Reserved
8
VDDIN
SPI_CS_1
NERROR_OUT
QSPI_CS
MOSI_1
Not to scale
1
2
3
4
Figure 4-4. Bottom Left Quadrant
Terminal Configuration and Functions
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9
H
10
11
VSS
12
VSS
J
VSS
K
VSS
VSS
L
VSS
VSS
M
13
14
15
TDI
CSI2
_TXM[1]
CSI2
_TXP[1]
TDO
CSI2_CLKM
CSI2_CLKP
VIOIN_18
CSI2
_TXM[2]
CSI2
_TXP[2]
TMS
CSI2
_TXM[3]
CSI2
_TXP[3]
TCK
HS_M
_Debug1
HS_P
_Debug1
N
MCU_CLK_OUT
Sync_in
VDDIN
WARM
_RESET
GPIO[2]
HS_M
_Debug2
HS_P
_Debug2
P
QSPI[1]
QSPI[3]
Sync_out
NRESET
PMIC_CLK_OUT
VNWA
VDDIN
R
SPI_CLK_1
QSPI_CLK
QSPI[0]
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
1
2
3
4
Figure 4-5. Bottom Right Quadrant
12
Terminal Configuration and Functions
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4.2
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Signal Descriptions
Table 4-1. Signal Descriptions
FUNCTION
Transmitters
Receivers
CSI2 TX/LVDS
TX
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS (1)
TX1
B4
O
—
Single-ended transmitter1 o/p
TX2
B6
O
—
Single-ended transmitter2 o/p
TX3
B8
O
—
Single-ended transmitter3 o/p
RX1
M2
I
—
Single-ended receiver1 i/p
RX2
K2
I
—
Single-ended receiver2 i/p
RX3
H2
I
—
Single-ended receiver3 i/p
RX4
F2
I
—
Single-ended receiver4 i/p
CSI2_TXP[0]
G15
O
—
CSI2_TXM[0]
G14
O
—
CSI2_CLKP
J15
O
—
CSI2_CLKM
J14
O
—
CSI2_TXP[1]
H15
O
—
CSI2_TXM[1]
H14
O
—
CSI2_TXP[2]
K15
O
—
CSI2_TXM[2]
K14
O
—
CSI2_TXP[3]
L15
O
—
CSI2_TXM[3]
L14
O
—
HS_DEBUG1_P
M15
O
—
HS_DEBUG1_M
M14
O
—
HS_DEBUG2_P
N15
O
—
HS_DEBUG2_M
N14
O
—
SIGNAL NAME
RESERVED
Reference clock OSC_CLKOUT
System
synchronization
SPI control
interface from
external MCU
(default slave
mode)
Differential clock Out
Differential data Out – Lane 1
Differential data Out – Lane 2
Differential data Out – Lane 3
Differential debug port 1
Differential debug port 2
—
Reference clock output from clocking subsystem
after cleanup PLL.
O
—
SYNC_OUT
P11
O
Pull Down
Low-frequency frame synchronization signal output.
Can be used by slave chip in multichip cascading
SYNC_IN
N10
I
Pull Down
Low-frequency frame synchronization signal input.
SPI_CS_1
R7
I
Pull Up
SPI_CLK_1
R9
I
Pull Down
MOSI_1
R8
I
Pull Up
SPI data input
MISO_1
P5
O
Pull Up
SPI data output
P6
O
Pull Down
RESERVED
R3, R4, R5,
P4
SPI chip select
SPI clock
SPI interrupt to host
—
NRESET
P12
I
Open Drain
Power on reset for chip. Active low
WARM_RESET
N12
IO
Open Drain
Open-drain fail-safe warm reset signal. Can be
driven from PMIC for diagnostic or can be used as
status signal that the device is going through reset.
NERROR_OUT
N8
O
Open Drain
Open-drain fail-safe output signal. Connected to
PMIC/Processor/MCU to indicate that some severe
criticality fault has happened. Recovery would be
through reset.
NERROR_IN
P7
I
Pull Up
Fail-safe input to the device. Error output from any
other device can be concentrated in the error
signaling monitor module inside the device and
appropriate action can be taken by firmware
Safety
(1)
Differential data Out – Lane 0
A14
SPI_HOST_INTR_1
Reset
B1, B15,
D1, D15
DESCRIPTION
Status of PULL structures associated with the IO after device POWER UP.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
FUNCTION
JTAG
Reference
oscillator
Band-gap
voltage
PIN
NUMBER
PIN
TYPE
TMS
L13
I
Pull Up
TCK
M13
I
Pull Down
TDI
H13
I
Pull Up
TDO
J13
O
—
CLKP
E14
I
—
CLKM
F14
O
—
VBGAP
B10
O
—
Internal voltage reference 0.9V
VDDIN
F13,N11,P1
5,R6
POW
—
1.2-V digital power supply
VIN_SRAM
R14
POW
—
1.2-V power rail for internal SRAM
VNWA
P14
POW
—
1.2-V power rail for SRAM array back bias
VIOIN
R13
POW
—
I/O supply (3.3-V or 1.8-V): All CMOS I/Os would
operate on this supply.
VIOIN_18
K13
POW
—
1.8-V supply for CMOS IO
VIN_18CLK
B11
POW
—
1.8-V supply for clock module
VIOIN_18DIFF
D13
POW
—
1.8-V supply for CSI2 port
Reserved
G13
POW
—
No connect
VIN_13RF1
G5,J5,H5
POW
—
VIN_13RF2
C2,D2
POW
—
1.3-V Analog and RF supply,VIN_13RF1 and
VIN_13RF2 could be shorted on the board
1.0-V Analog and RF supply input if RFLDO is
bypassed
VIN_18BB
K5,F5
POW
—
1.8-V Analog baseband power supply
SIGNAL NAME
VIN_18VCO
14
JTAG port for standard boundary scan
In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input
reference clock port (Output CLKM is grounded in
this case)
B12
POW
—
1.8-V RF VCO supply
VSS
GND
—
Digital ground
VSSA
A1,A3,A5,A
7,A9,A15,B
3,B5,B7,B9,
B13,B14,C1
,C3,C4,C5,
C6,C7,C8,C
9,C15,E1,E
2,E3,E13,E
15,F3,G1,G
2,G3,H3,J1,
J2,J3,K3,L1
,L2,L3,
M3,N1,N2,N
3,R1
GND
—
Analog ground
VOUT_14APLL
A10
O
—
1.4V internal regulator
VOUT_14SYNTH
A13
O
—
1.4V internal regulator
A2,B2
O
—
1.0V internal regulator
PMIC_CLK_OUT
P13
O
—
Dithered clock input to PMIC
MCU_CLK_OUT
N9
O
—
Programmable clock given out to external MCU or
the processor
VOUT_PA
External clock
out
DESCRIPTION
E5,E6,E8,E
10,E11,F9,F
11,G6,G7,G
8,G10,H7,H
9,H11,J6,J7
,J8,J10,K7,
K8,K9,K10,
K11,L5,L6,L
8,L10,R15
Power supply
Internal LDO
output/inputs
DEFAULT PULL
STATUS (1)
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
FUNCTION
Generalpurpose I/Os
QSPI for Serial
Flash
Flash
programming
and RS232
UART
Test and Debug
output for
preproduction
phase. Can be
pinned out on
production
hardware for
field debug
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS (1)
GPIO[0]
N4
IO
Pull Down
General-purpose IO
GPIO[1]
N7
IO
Pull Down
General-purpose IO
GPIO[2]
N13
IO
Pull Down
General-purpose IO
QSPI_CS
P8
O
Pull Up
QSPI_CLK
R10
O
Pull Down
Clock output from the device. Device is a master
connected to serial flash slave.
QSPI[0]
R11
IO
Pull Down
Data IN/OUT
QSPI[1]
P9
IO
Pull Down
Data IN/OUT
QSPI[2]
R12
IO
Pull Up
Data IN/OUT
QSPI[3]
P10
IO
Pull Up
Data IN/OUT
RS232_TX
N6
O
Pull Down
RS232_RX
N5
I
Pull Up
Analog Test1 /
GPADC1
P1
IO
—
GP ADC channel 1
Analog Test2 /
GPADC2
P2
IO
—
GP ADC channel 2
Analog Test3 /
GPADC3
P3
IO
—
GP ADC channel 3
Analog Test4 /
GPADC4
R2
IO
—
GP ADC channel 4
ANAMUX / GPADC5
C13
IO
—
GP ADC channel 5
VSENSE / GPADC6
C14
IO
—
GP ADC channel 6
SIGNAL NAME
DESCRIPTION
Chip-select output from the device. Device is a
master connected to serial flash slave.
UART pins for programming external flash in
preproduction/debug hardware.
Terminal Configuration and Functions
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Pin Multiplexing
Table 4-2. Pin Multiplexing
REGISTER
ADDRESS (1)
PIN NAME
EA00h
GPIO_12
EA04h
EA08h
EA0Ch
EA10h
EA14h
GPIO_0
GPIO_1
MOSI_1
MISO_1
SPI_CLK_1
PIN
P6
N4
N7
R8
P5
R9
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
SIGNAL NAME
SIGNAL DESCRIPTION
SPI_CS_1
R7
GPIO_12
General Purpose IO
IO
1
SPI_HOST1_INTR
General Purpose IO [IWR14xx]
O
0
GPIO_13
General Purpose IO
IO
1
GPIO_0
General Purpose IO
IO
2
PMIC_CLKOUT
Dithered Clock Output for PMIC
O
0
GPIO_16
General Purpose IO
IO
1
GPIO_1
General Purpose IO
IO
2
SYNC_OUT
Low Frequency Synchronization
Signal output
O
0
GPIO_19
General Purpose IO
IO
1
MOSI_1
SPI Channel#1 Data Input
IO
2
CAN_RX
CAN Interface
0
GPIO_20
General Purpose IO
IO
1
MISO_1
SPI Channel#1 Data Output
IO
2
CAN_TX
CAN Interface
O
0
GPIO_3
General Purpose IO
IO
1
SPI_CLK_1
SPI Channel#1 Clock
IO
EA20h
(1)
16
MOSI_2
MISO_2
R3
P4
STATE
INTERNAL WEAK
PULL STATE
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Up
Hi-Z
Weak Pull Up
Hi-Z
Weak Pull Up
Hi-Z
Weak Pull Up
I
O
0
GPIO_30
General Purpose IO
IO
1
SPI_CS_1
SPI Channel#1 Chip Select
IO
RCOSC_CLK
EA1Ch
SIGNAL TYPE
0
RCOSC_CLK
EA18h
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
O
0
GPIO_21
General Purpose IO
IO
1
MOSI_2
SPI Channel#2 Data Input
IO
2
I2C_SDA
I2C Data
IO
0
GPIO_22
General Purpose IO
IO
1
MISO_2
SPI Channel#2 Data Output
IO
2
I2C_SCL
I2C Clock
IO
Hi-Z
Hi-Z
Register addresses are of the form FFFF XXXXh, where XXXX is listed here.
Terminal Configuration and Functions
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Table 4-2. Pin Multiplexing (continued)
REGISTER
ADDRESS (1)
EA24h
EA28h
EA2Ch
EA30h
EA34h
EA38h
EA3Ch
EA40h
PIN NAME
SPI_CLK_2
SPI_CS_2
QSPI[0]
QSPI[1]
QSPI[2]
QSPI[3]
QSPI_CLK
QSPI_CS
PIN
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
R12
P10
R10
P8
SIGNAL DESCRIPTION
SIGNAL TYPE
GPIO_5
General Purpose IO
IO
1
SPI_CLK_2
SPI Channel#2 Clock
IO
MSS_UARTA_RX
STATE
INTERNAL WEAK
PULL STATE
Hi-Z
IO
6
MSS_UARTB_TX
Debug: Firmware Trace
7
BSS_UART_TX
Debug: Firmware Trace
O
0
GPIO_4
General Purpose IO
IO
1
SPI_CS_2
SPI Channel#2 Chip Select
IO
R4
P9
SIGNAL NAME
0
R5
R11
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
MSS_UARTA_TX
O
Hi-Z
IO
6
MSS_UARTB_TX
Debug: Firmware Trace
O
7
BSS_UART_TX
Debug: Firmware Trace
O
0
GPIO_8
General Purpose IO
IO
1
QSPI[0]
QSPI Data IN/OUT
IO
2
MISO_2
SPI Channel#1 Data Output
IO
0
GPIO_9
General Purpose IO
IO
1
QSPI[1]
QSPI Data IN/OUT
IO
2
MOSI_2
SPI Channel#2 Data Input
IO
0
GPIO_10
General Purpose IO
IO
1
QSPI[2]
QSPI Data IN/OUT
IO
0
GPIO_11
General Purpose IO
IO
1
QSPI[3]
QSPI Data IN/OUT
I
0
GPIO_7
General Purpose IO
IO
1
QSPI_CLK
QSPI Clock output from the device.
Device operates as a master with
the serial flash being a slave
O
2
SPI_CLK_2
SPI Channel#2 Clock
IO
0
GPIO_6
General Purpose IO
IO
1
QSPI_CS
QSPI Chip Select output from the
device.
Device operates as a master with
the serial flash being a slave
O
2
SPI_CS_2
SPI Channel#2 Chip Select
IO
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Up
Terminal Configuration and Functions
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Table 4-2. Pin Multiplexing (continued)
REGISTER
ADDRESS (1)
PIN NAME
NERROR_IN
WARM_RESET
NERROR_OUT
EA50h
EA54h
EA58h
TCK
TMS
TDI
PIN
SIGNAL TYPE
NERROR_IN
Failsafe input to the device. Nerror
output from any other device can be
concentrated in the error signaling
monitor module inside the device
and appropriate action can be taken
by Firmware
I
WARM_RESET
Open drain fail safe warm reset
signal. Can be driven from PMIC for
diagnostic or can be used as status
signal that the device is going
through reset.
IO
Hi-Z Input
Open Drain
NERROR_OUT
Open drain fail safe output signal.
Connected to PMIC/Processor/MCU
to indicate that some severe
criticality fault has happened.
Recovery would be through reset.
O
Hi-Z
Open Drain
0
GPIO_17
General Purpose IO
IO
Hi-Z
Weak Pull Down
1
TCK
JTAG Clock
I
2
MSS_UARTB_TX
Debug: Firmware Trace
O
6
BSS_UART_RX
Debug: Firmware Trace
0
GPIO_18
General Purpose IO
IO
Hi-Z
Weak Pull Up
1
TMS
JTAG Test Mode Select
IO
2
BSS_UART_TX
Debug: Firmware Trace
O
0
GPIO_23
General Purpose IO
IO
Hi-Z
Weak Pull Up
1
TDI
JTAG Test Data In
I
N12
N8
L13
H13
SIGNAL NAME
MSS_UARTA_RX
TDO
J13
GPIO_24
General Purpose IO
IO
1
TDO
JTAG Test Data Out
O
7
18
I
0
6
Hi-Z
IO
MSS_UARTA_TX
EA5Ch
STATE
INTERNAL WEAK
PULL STATE
SIGNAL DESCRIPTION
P7
M13
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
Hi-Z
IO
MSS_UARTB_TX
Debug: Firmware Trace
O
BSS_UART_TX
Debug: Firmware Trace
O
SOP0
Sense On Power [Reset] Line
Impacts boot mode
I
Terminal Configuration and Functions
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Table 4-2. Pin Multiplexing (continued)
REGISTER
ADDRESS (1)
PIN NAME
PIN
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
0
EA60h
EA64h
EA68h
MCU_CLKOUT
GPIO_2
PMIC_CLKOUT
N9
N13
P13
SYNC_IN
N10
EA74h
SYNC_OUT
RS232_RX
SIGNAL TYPE
IO
1
MCU_CLKOUT
Programmable clock given out to
external MCU or the processor
O
10
BSS_UART_RX
Debug: Firmware Trace
I
0
GPIO_26
General Purpose IO
IO
1
GPIO_2
General Purpose IO
IO
7
MSS_UARTB_TX
Debug: Firmware Trace
O
8
BSS_UART_TX
Debug: Firmware Trace
O
9
SYNC_OUT
Low frequency Synchronization
signal output
O
10
PMIC_CLKOUT
Dithered clock input to PMIC
O
0
GPIO_27
General Purpose IO
IO
1
PMIC_CLKOUT
Dithered Clock Output for PMIC
O
SOP2
Sense On Power [Reset] Line
Impacts boot mode
I
GPIO_28
General Purpose IO
1
SYNC_IN
Low frequency Synchronization
signal input
6
MSS_UARTB_RX
Debug: Firmware Trace
0
GPIO_29
General Purpose IO
IO
SYNC_OUT
Low frequency Synchronization
signal output
O
P11
N5
SIGNAL DESCRIPTION
General Purpose IO
1
EA70h
SIGNAL NAME
GPIO_25
0
EA6Ch
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
RCOSC_CLK
IO
STATE
INTERNAL WEAK
PULL STATE
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Down
Hi-Z
Weak Pull Up
I
I
O
SOP1
Sense On Power [Reset] Line
Impacts boot mode
0
GPIO_15
General Purpose IO
IO
1
RS232_RX
Debug: Firmware load to RAM
IO
2
MSS_UARTA_RX
FLASH Programming
Bootloader Controlled
I
6
BSS_UART_TX
Debug: Firmware Trace
O
7
MSS_UARTB_RX
Debug: Firmware Trace
I
I
Terminal Configuration and Functions
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Table 4-2. Pin Multiplexing (continued)
REGISTER
ADDRESS (1)
EA78h
20
PIN NAME
RS232_TX
PIN
N6
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
SIGNAL NAME
SIGNAL DESCRIPTION
SIGNAL TYPE
0
GPIO_14
General Purpose IO
IO
1
RS232_TX
Debug: Firmware load to RAM
IO
5
MSS_UARTA_TX
FLASH Programming
Bootloader Controlled
O
6
MSS_UARTB_TX
Debug: Firmware Trace
O
7
BSS_UART_TX
Debug: Firmware Trace
O
Terminal Configuration and Functions
STATE
INTERNAL WEAK
PULL STATE
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5 Specifications
Absolute Maximum Ratings (1) (2)
5.1
over operating Tj temperature range (unless otherwise noted)
MIN
MAX
VDDIN
1.2 V digital power supply
PARAMETERS
–0.5
1.4
V
VIN_SRAM
1.2 V power rail for internal SRAM
–0.5
1.4
V
VNWA
1.2 V power rail for SRAM array back bias
–0.5
1.4
V
VIOIN
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
–0.5
2
V
VIN_18CLK
1.8 V supply for clock module
–0.5
2
V
VIOIN_18DIFF
1.8 V supply for CSI2 port
–0.5
2
V
VIN_13RF1
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
–0.5
1.45
V
1-V Internal LDO bypass mode. Device supports mode where
external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
–0.5
1.4
V
VIN_18BB
1.8-V Analog baseband power supply
–0.5
2
V
VIN_18VCO supply
1.8-V RF VCO supply
–0.5
2
V
–0.3V
VIOIN + 0.3
VIN_13RF2
VIN_13RF1
VIN_13RF2
Input and output
voltage range
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
UNIT
V
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Input ports for reference crystal
–0.5
2
V
Clamp current
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
105
ºC
TSTG
Storage temperature range after soldered onto PC board
–55
150
ºC
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
(2)
5.2
ESD Ratings
VALUE
Human-body model (HBM)
V(ESD)
5.3
Electrostatic discharge
Charged-device model (CDM)
All other pins
±500
Corner pins
±750
V
Power-On Hours (POH) (1)
JUNCTION
TEMPERATURE (Tj)
OPERATING
CONDITION
NOMINAL CVDD VOLTAGE (V)
90% at 85ºC Tj
10% at 105ºC Tj
50% duty cycle
1.2
100% at 85ºC Tj
(1)
UNIT
±2000
POWER-ON HOURS [POH] (HOURS)
80,000
100,000
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
Specifications
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Recommended Operating Conditions
Tjunction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDDIN
1.2 V digital power supply
1.14
1.2
1.32
V
VIN_SRAM
1.2 V power rail for internal SRAM
1.14
1.2
1.32
V
VNWA
1.2 V power rail for SRAM array back bias
1.14
1.2
1.32
V
I/O supply (3.3 V)
3.15
3.3
3.45
I/O supply (1.8 V)
1.71
1.8
1.89
VIOIN_18
1.8 V supply for CMOS IO
1.71
1.8
1.9
V
VIN_18CLK
1.8 V supply for clock module
1.71
1.8
1.9
V
VIOIN_18DIFF
1.8 V supply for CSI2 port
1.71
1.8
1.9
V
VIN_13RF1
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In
this configuration, the internal LDO of the device would be
kept bypassed.
0.95
1
1.05
V
VIN18BB
1.8-V Analog baseband power supply
1.71
1.8
1.9
V
VIN_18VCO
1.8V RF VCO supply
1.71
1.8
1.9
V
Voltage Input High (1.8 V mode)
1.17
Voltage Input High (3.3 V mode)
2.25
VIOIN
VIN_13RF2
VIN_13RF1
(1-V Internal LDO
bypass mode)
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIH
VIL
VOH
VOL
NRESET
SOP[2:0]
0.3*VIOIN
Voltage Input Low (3.3 V mode)
0.62
85%*VIOIN
High-level output threshold (IOH = 6 mA) (3.3V)
VIOIN –
450mV
450
VIL (1.8V Mode)
0.2
VIH (1.8V Mode)
V
mV
Low-level output threshold (IOL = 6 mA)
0.96
VIL (3.3V Mode)
0.3
VIH (3.3V Mode)
5.5
V
Voltage Input Low (1.8 V mode)
High-level output threshold (IOH = 6 mA) (1.8V)
V
mV
V
1.57
Power Supply Specifications
Table 5-1 describes the four rails from an external power supply block of the IWR1443 device.
Table 5-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
1.8 V
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, LVDS
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal
LDO bypass mode)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM, VNWA
22
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The 1.3V (1.0V) and 1.8V power supply ripple specifications mentioned in Table 5-2 are defined to meet a
target spur level of –105dBc (RF Pin = –15dBm) at the RX. The spur and ripple levels have a dB to dB
relationship, for example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level. Values
quoted are rms levels for a sinusoidal input applied at the specified frequency.
Table 5-2. Ripple Specifications
RF RAIL
5.6
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
(µVRMS)
1.3 V (µVRMS)
1.8 V (µVRMS)
137.5
744
648
83
275
4
76
21
550
3
22
11
1100
2
4
6
2200
11
82
13
4400
13
93
19
6600
22
117
29
Power Consumption Summary
Table 5-3 and Table 5-4 summarize the power consumption at the power terminals.
Table 5-3. Maximum Current Ratings at Power Terminals
PARAMETER
Current consumption
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
VDDIN, VIN_SRAM, VNWA
Total current drawn by
all nodes driven by
1.2V rail
500
VIN_13RF1, VIN_13RF2
Total current drawn by
all nodes driven by
1.3V rail
2000
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by
all nodes driven by
1.8V rail
850
VIOIN
Total current drawn by
all nodes driven by
3.3V rail
50
UNIT
mA
Table 5-4. Average Power Consumption at Power Terminals
PARAMETER
Average power
consumption
CONDITION
DESCRIPTION
1.0-V internal
LDO bypass
mode
1TX, 4RX
1.3-V internal
LDO enabled
mode
1TX, 4RX
2TX, 4RX
2TX, 4RX
Sampling: 16.66 MSps complex
Transceiver, 40-ms frame time, 512
chirps, 512 samples/chirp, 8.5-μs
interchirp time (50% duty cycle)
Data Port: MIPI-CSI-2
MIN
TYP
MAX
1.73
1.88
1.92
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2.1
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UNIT
23
IWR1443
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5.7
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RF Specification
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
Noise figure
TYP
76 to 77 GHz
14
77 to 81 GHz
15
–8
dBm
48
dB
Gain range
24
dB
2
dB
30
dB
IF bandwidth
(2)
A2D sampling rate (real)
A2D sampling rate (complex)
A2D resolution
MHz
Msps
18.75
Msps
12
Bits
–10
dB
Gain mismatch variation (over temperature)
±0.5
dB
±3
°
In-band IIP2
RX gain = 30dB
IF = 1.5, 2 MHz at
–12 dBFS
16
dBm
Out-of-band IIP2
RX gain = 24dB
IF = 10 kHz at -10dBm,
1.9 MHz at -30 dBm
24
dBm
–90
dBFS
Idle Channel Spurs
Output power
12
Amplitude noise
76
dBc/Hz
81
Ramp rate
Phase noise at 1-MHz offset
dBm
–145
Frequency range
(1)
(2)
15
37.5
Return loss (S11)
Phase mismatch variation (over temperature)
Clock
subsystem
dB
Maximum gain
Image Rejection Ratio (IMRR)
Transmitter
UNIT
1-dB compression point (1)
Gain step size
Receiver
MAX
GHz
100 MHz/µs
76 to 77 GHz
–95
77 to 81 GHz
–93
dBc/Hz
1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone below the lowest HPF cut-off frequency (50 kHz).
The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of
available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
175, 235, 350, 700
HPF2
350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
• Less than ±0.5 dB pass-band ripple/droop, and
• Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
24
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NF (dB)
15.6
15.3
-20
NF (db)
IB P1db (dBm) -24
15
-28
14.7
-32
14.4
-36
14.1
-40
13.8
-44
13.5
24
26
28
30
32
34 36 38
RX Gain (dB)
40
42
44
46
IB P1dB (dBm)
Figure 5-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain
programmed.
-48
48
Figure 5-1. Noise Figure, In-band P1dB vs Receiver Gain
Thermal Resistance Characteristics for FCBGA Package [ABL0161] (1)
5.8
THERMAL METRICS (2)
°C/W (3)
RΘJC
Junction-to-case
4.92
RΘJB
Junction-to-board
6.57
RΘJA
Junction-to-free air
RΘJMA
Junction-to-moving air
PsiJT
Junction-to-package top
4.92
PsiJB
Junction-to-board
6.4
(1)
(2)
(3)
(4)
(4)
22.3
N/A (1)
N/A = not applicable
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 105ºC is assumed.
5.9
5.9.1
Timing and Switching Characteristics
Power Supply Sequencing and Reset Timing
The IWR1443 device expects all external voltage rails to be stable before reset is deasserted. Figure 5-2
describes the device wake-up sequence.
Specifications
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SOP
Setup
DC power
Time Stable before
DC
nRESET
Power
release
OK
www.ti.com
SOP
Hold time to
nRESET
MSS
BOOT
START
nRESET
ASSERT
tPGDEL
QSPI
READ
DC
Power
notOK
VDDIN,
VIN_SRAM
VNWA
VIOIN_18
VIN18_CLK
VIOIN_18DIFF
VIN18_BB
VIN_13RF1
VIN_13RF2
VIOIN
SOP[2.1.0]
nRESET
WARMRESET
OUTPUT
Warm reset
delay for crystal
or ext osc
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
MCUCLK
OUTPUT (1)
QSPI_CS
OUTPUT
(1)
7ms (XTAL Mode)
500 µs (REFCLK Mode)
MCU_CLK_OUT in autonomous mode, where IWR1443 application is booted from the serial flash, MCU_CLK_OUT is not enabled
by default by the device bootloader.
Figure 5-2. Device Wake-up Sequence
5.9.2
Synchronized Frame Triggering
The IWR1443 device supports a hardware based mechanism to trigger radar frames. An external host can
pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of the
external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional
programmable delay that the user can set to control the frame start time.
26
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Tactive_frame
SYNC_IN
(Hardware
Trigger)
Radar
Frames
Tpulse
Tlag
Frame-2
Frame-1
Figure 5-3. Sync In Hardware Trigger
Table 5-5. Frame Trigger Timing
PARAMETER
Tactive_frame
DESCRIPTION
Active frame duration
Tpulse
MIN
MAX
UNIT
User defined
25
< Tactive_frame
ns
Specifications
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5.9.3
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Input Clocks and Oscillators
5.9.3.1
Clock Specifications
An external crystal is connected to the device pins. Figure 5-4 shows the crystal implementation.
Cf1
XTALP
Cp
40 and 50 MHz
XTALM
Cf2
Figure 5-4. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-4, should be chosen such that Equation 1 is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic
capacitances due to PCB routing.
C f2
C L = C f1 ´
C f1 + C f 2
+CP
(1)
Table 5-6 lists the electrical characteristics of the clock crystal.
Table 5-6. Crystal Electrical Characteristics (Oscillator Mode)
NAME
DESCRIPTION
fP
Parallel resonance crystal frequency
CL
Crystal load capacitance
ESR
Crystal ESR
MIN
TYP
MAX
40
5
UNIT
MHz
8
12
pF
50
Ω
Temperature range Expected temperature range of operation
–40
105
ºC
Frequency
tolerance
–50
50
ppm
200
µW
Crystal frequency tolerance (1) (2) (3)
Drive level
(1)
(2)
(3)
28
50
The crystal manufacturer's specification must satisfy this requirement.
Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
Crystal tolerance affects radar sensor accuracy.
Specifications
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In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only;
CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally.
Table 5-7 lists the electrical characteristics of the external clock signal.
Table 5-7. External Clock Mode Specifications
SPECIFICATION
PARAMETER
MIN
Frequency
TYP
MAX
40
AC-Amplitude
Phase Noise
Input Clock:
External AC-coupled sine wave or DC- Phase Noise
coupled square wave
Phase Noise
Phase Noise referred to 40 MHz
Phase Noise
700
UNIT
MHz
1200
mV (pp)
at 1 kHz
–132
dBc/Hz
at 10 kHz
–143
dBc/Hz
at 100 kHz
–152
dBc/Hz
–153
dBc/Hz
at 1 MHz
Duty Cycle
35
65
%
Freq Tolerance
–50
50
ppm
Specifications
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Multibuffered / Standard Serial Peripheral Interface (MibSPI)
5.9.4.1
Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 8-bit baud clock generator
• SPICLK can be internally-generated (master mode) or received from an external clock source
(slave mode)
• Each word transferred can have a unique format.
• SPI I/Os not used in the communication can be used as digital input/output signals
5.9.4.2
MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
Table 5-9 to assume the operating conditions stated in Table 5-8.
Table 5-8. SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input rise time
1
3
ns
tF
Input fall time
1
3
ns
2
15
pF
Output Conditions
CLOAD
30
Output load capacitance
Specifications
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Table 5-9. SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
1
2 (4)
3 (4)
4 (4)
5 (4)
PARAMETER
tc(SPC)M
Cycle time, SPICLK (4)
tw(SPCH)M
MIN
6
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
td(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 3
td(SPCL-SIMO)M
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 3
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 10.5
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 10.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 1
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
CSHOLD = 0
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 1
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
0.5*tc(SPC)M +
(T2CDELAY + 1)
*tc(VCLK) – 7
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
Hold time, SPICLK high until CS inactive (clock polarity = 1)
0.5*tc(SPC)M +
(T2CDELAY + 1)
*tc(VCLK) – 7
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
tT2CDELAY
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
3
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
3
8 (4)
9
(1)
(2)
(3)
(4)
(5)
(4)
ns
ns
ns
ns
(C2TDELAY+2)*tc(VCLK
) – 7.5
tC2TDELAY
UNIT
ns
CSHOLD = 0
Setup time CS active until SPICLK low
(clock polarity = 1)
7 (5)
MAX
256tc(VCLK)
Setup time CS active until SPICLK high
(clock polarity = 0)
(5)
TYP
25
ns
ns
ns
ns
The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
1
3
SPICLK
(clock polarity = 1
5
4
Master Out Data Is Valid
SPISIMO
1
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-5. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
Master Out Data Is Valid
6
7
SPICSn
Figure 5-6. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
32
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Table 5-10. SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
1
2 (4)
3 (4)
4 (4)
5 (4)
PARAMETER
tc(SPC)M
Cycle time, SPICLK (4)
tw(SPCH)M
MIN
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
td(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 3
td(SPCL-SIMO)M
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 3
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 10.5
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 10.5
7
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
CSHOLD = 1
0.5*tc(SPC)M +
(C2TDELAY +
2)*tc(VCLK) – 7
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
CSHOLD = 0
0.5*tc(SPC)M +
(C2TDELAY+2)*tc(
VCLK) – 7
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
CSHOLD = 1
0.5*tc(SPC)M +
(C2TDELAY+3)*tc(
VCLK) – 7
0.5*tc(SPC)M +
(C2TDELAY+3) *
tc(VCLK) + 7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
8
9
(1)
(2)
(3)
(4)
(5)
tT2CDELAY
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
3
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
3
(4)
(4)
ns
ns
ns
ns
0.5*tc(SPC)M +
(C2TDELAY +
2)*tc(VCLK) – 7
tC2TDELAY
UNIT
ns
CSHOLD = 0
Setup time CS active until SPICLK low
(clock polarity = 1)
(5)
MAX
256tc(VCLK)
Setup time CS active until SPICLK high
(clock polarity = 0)
6 (5)
TYP
25
ns
ns
ns
ns
The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
Master Out Data Is Valid
SPISIMO
8
Data Valid
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-7. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
Master Out Data Is Valid
6
7
SPICSn
Figure 5-8. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
34
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5.9.4.3
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
SPI Slave Mode I/O Timings
Table 5-11. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output) (1) (2) (3)
NO.
1
2 (5)
3 (5)
4
5
6
7
(1)
(2)
(3)
(4)
(5)
PARAMETER
MIN
TYP
MAX
tc(SPC)S
Cycle time, SPICLK (4)
25
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
10
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
10
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
10
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
10
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
10
td(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
10
th(SPCH-SOMI)S
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
th(SPCL-SOMI)S
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
2
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock
polarity = 0; clock phase = 0) OR (clock polarity = 1;
clock phase = 1)
3
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock
polarity = 1; clock phase = 0) OR (clock polarity = 0;
clock phase = 1)
3
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
1
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
1
(5)
(5)
(5)
(5)
UNIT
ns
ns
ns
ns
ns
ns
ns
The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-9. SPI Slave Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO
SPISIMO Data
Must Be Valid
Figure 5-10. SPI Slave Mode External Timing (CLOCK PHASE = 1)
36
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5.9.4.4
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Typical Interface Protocol Diagram (Slave Mode)
1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI
clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 5-11 shows the SPI communication timing of the typical interface protocol.
2 SPI clocks
CS
CLK
0x1234
0x4321
CRC
0x5678
0x8765
MOSI
16 bytes
0xDCBA
0xABCD
CRC
MISO
IRQ
Figure 5-11. SPI Communication
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LVDS Interface Configuration
The IWR1443 supports seven differential LVDS IOs/Lanes. The lane configuration supported is four Data
lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane
(LVDS_FRCLKP/M), and one HS_DEBUG LVDS pair. The LVDS interface is used for debugging. The
LVDS interface supports the following data rates:
• 900 Mbps (450 MHz DDR Clock)
• 600 Mbps (300 MHz DDR Clock)
• 450 Mbps (225 MHz DDR Clock)
• 400 Mbps (200 MHz DDR Clock)
• 300 Mbps (150 MHz DDR Clock)
• 225 Mbps (112.5 MHz DDR Clock)
• 150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to
data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 5-12. LVDS Interface Lane Configuration And Relative Timings
5.9.5.1
LVDS Interface Timings
Trise
LVDS_CLK
LVDS_TXP/M
LVDS_FRCLKP/M
Clock Jitter = 6sigma
1100 ps
Figure 5-13. Timing Parameters
38
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Table 5-12. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
Duty Cycle Requirements
max 1 pF lumped capacitive load on
LVDS lanes
Output Differential Voltage
peak-to-peak single-ended with 100 Ω
resistive load between differential pairs
Output Offset Voltage
MIN
TYP
20%-80%, 900 Mbps
Jitter (pk-pk)
900 Mbps
UNIT
52%
250
450
mV
1275
mV
1125
Trise and Tfall
MAX
48%
500
ps
80
ps
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General-Purpose Input/Output
Table 5-13 lists the switching characteristics of output timing relative to load capacitance.
Table 5-13. Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (2)
PARAMETER
tr
TEST CONDITIONS
Max rise time
Slew control = 0
tf
tr
Max fall time
Max rise time
Slew control = 1
tf
(1)
(2)
40
Max fall time
VIOIN = 1.8V
VIOIN = 3.3V
CL = 20 pF
2.8
3.0
CL = 50 pF
6.4
6.9
CL = 75 pF
9.4
10.2
CL = 20 pF
2.8
2.8
CL = 50 pF
6.4
6.6
CL = 75 pF
9.4
9.8
CL = 20 pF
3.3
3.3
CL = 50 pF
6.7
7.2
CL = 75 pF
9.6
10.5
CL = 20 pF
3.1
3.1
CL = 50 pF
6.6
6.6
CL = 75 pF
9.6
9.6
UNIT
ns
ns
ns
ns
Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
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5.9.7
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Controller Area Network Interface (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments that require reliable
serial communication or multiplexed wiring.
The DCAN has the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbps
• Configurable Message objects
• Individual identifier masks for each message object
• Programmable FIFO mode for message objects
• Suspend mode for debug support
• Programmable loop-back modes for self-test operation
• Direct access to Message RAM in test mode
• Supports two interrupt lines - Level 0 and Level 1
• Automatic Message RAM initialization
Table 5-14. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
UNIT
td(CAN_tx)
Delay time, transmit shift register to CAN_tx pin (1)
15
ns
td(CAN_rx)
Delay time, CAN_rx pin to receive shift register (1)
10
ns
(1)
These values do not include rise/fall times of the output buffer.
describes the CSI-2 DPHY electrical specifications.
5.9.8
Serial Communication Interface (SCI)
The SCI has the following features:
• Standard universal asynchronous receiver-transmitter (UART) communication
• Standard non-return to zero (NRZ) format
• Double-buffered receive and transmit functions
• Asynchronous or iso-synchronous communication modes with no CLK pin
• Capability to use Direct Memory Access (DMA) for transmit and receive data
• Two external pins: RS232_RX and RS232_TX
Table 5-15. SCI Timing Requirements
MIN
f(baud)
Supported baud rate at 20 pF
TYP
921.6
MAX
UNIT
kHz
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Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface
between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by
an I2C-bus™. This module will support any slave or master I2C compatible device.
The I2C has the following features:
• Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multi-master transmitter/ slave receiver mode
– Multi-master receiver/ slave transmitter mode
– Combined master transmit/receive and receive/transmit mode
– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
• Free data format
• Two DMA events (transmit and receive)
• DMA event enable/disable capability
• Module enable/disable capability
• The SDA and SCL are optionally configurable as general purpose I/O
• Slew rate control of the outputs
• Open drain control of the outputs
• Programmable pullup/pulldown capability on the inputs
• Supports Ignore NACK mode
NOTE
This I2C module does not support:
• High-speed (HS) mode
• C-bus compatibility mode
• The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
42
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Table 5-16. I2C Timing Requirements (1)
STANDARD MODE
MIN
FAST MODE
MAX
MIN
MAX
UNIT
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low
(for a repeated START condition)
4.7
0.6
μs
th(SCLL-SDAL)
Hold time, SCL low after SDA low
(for a START and a repeated START condition)
4
0.6
μs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
μs
tw(SCLH)
Pulse duration, SCL high
4
0.6
μs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
th(SCLL-SDA)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high
(for STOP condition)
tw(SP)
Pulse duration, spike (must be suppressed)
Cb
(1)
(2)
(3)
(2) (3)
250
0
100
3.45 (1)
μs
0
0.9
μs
4.7
1.3
μs
4
0.6
μs
0
Capacitive load for each bus line
400
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SCLL)
tw(SP)
tsu(SCLH-SDAH)
tw(SCLH)
tr(SCL)
SCL
tc(SCL)
tf(SCL)
th(SCLL-SDAL)
th(SDA-SCLL)
tsu(SCLH-SDAL)
th(SCLL-SDAL)
Stop
Start
Repeated Start
Stop
Figure 5-14. I2C Timing Diagram
NOTE
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a
Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
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5.9.10 Quad Serial Peripheral Interface (QSPI)
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only. The QSPI in the device is primarily intended for fast
booting from quad-SPI flash memories.
The QSPI supports the following features:
• Programmable clock divider
• Six-pin interface
• Programmable length (from 1 to 128 bits) of the words transferred
• Programmable number (from 1 to 4096) of the words transferred
• Support for 3-, 4-, or 6-pin SPI interface
• Optional interrupt generation on word or frame (number of words) completion
• Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Table 5-18 and Table 5-19 assume the operating conditions stated in Table 5-17.
Table 5-17. QSPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input rise time
1
3
ns
tF
Input fall time
1
3
ns
2
15
pF
Output Conditions
CLOAD
Output load capacitance
Table 5-18. Timing Requirements for QSPI Input (Read) Timings (1) (2)
MIN
TYP
MAX
UNIT
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
th(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
tsu(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk edge
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk edge
1.5 + P (3)
ns
(1)
(2)
(3)
44
7.3
ns
1.5
ns
7.3 – P (3)
ns
Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although nonstandard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Mode 0.
P = SCLK period in ns.
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Table 5-19. QSPI Switching Characteristics
NO.
Q1
(1)
(2)
(3)
PARAMETER
tc(SCLK)
MIN
Cycle time, sclk
Q2
tw(SCLKL)
Pulse duration, sclk low
Q3
tw(SCLKH)
Pulse duration, sclk high
Y*P – 3
TYP
MAX
ns
(1) (2)
ns
Y*P – 3 (1)
Q4
td(CS-SCLK)
Delay time, sclk falling edge to cs active edge
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge
Q6
td(SCLK-D1)
Delay time, sclk falling edge to d[1] transition
UNIT
25
ns
(1) (3)
–M*P +
2.5 (1) (3)
ns
N*P – 1 (1) (3)
N*P +
2.5 (1) (3)
ns
–3.5
7
ns
(3)
(3)
ns
–M*P – 1
Q7
tena(CS-D1LZ)
Enable time, cs active edge to d[1] driven (lo-z)
–P – 4
Q8
tdis(CS-D1Z)
Disable time, cs active edge to d[1] tri-stated (hi-z)
–P – 4 (3)
–P +1 (3)
ns
Q9
td(SCLK-D1)
Delay time, sclk first falling edge to first d[1] transition
(for PHA = 0 only)
(3)
(3)
ns
Q12
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
7.3
ns
Q13
th(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
1.5
ns
Q14
tsu(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk
edge
7.3 — P (3)
ns
Q15
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk
edge
1.5 + P (3)
ns
–3.5 – P
–P +1
7–P
The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
P = SCLK period in ns.
M = QSPI_SPI_DC_REG.DDx + 1, N = 2
PHA=0
cs
Q5
Q4
Q1
Q2
POL=0
Q3
sclk
Q7
d[0]
Q6
Q9
Command Command
Bit n-1
Bit n-2
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 1
d[3:1]
Q12 Q13
Read Data
Bit 0
Q12 Q13
Read Data
Bit 0
SPRS85v_TIMING_OSPI1_02
Figure 5-15. QSPI Read (Clock Mode 0)
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PHA=0
cs
Q5
Q4
POL=0
Q1
Q2
Q3
sclk
Q7
d[0]
Q9
Q6
Command Command
Bit n-1
Bit n-2
Q6
Q8
Q6
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 5-16. QSPI Write (Clock Mode 0)
46
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5.9.11 JTAG Interface
Table 5-21 and Table 5-22 assume the operating conditions stated in Table 5-20.
Table 5-20. JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input rise time
1
3
ns
tF
Input fall time
1
3
ns
2
15
pF
MAX
UNIT
Output Conditions
CLOAD
Output load capacitance
Table 5-21. Timing Requirements for IEEE 1149.1 JTAG
NO.
MIN
TYP
1
tc(TCK)
Cycle time TCK
66.66
ns
1a
tw(TCKH)
Pulse duration TCK high (40% of tc)
26.67
ns
1b
tw(TCKL)
Pulse duration TCK low(40% of tc)
26.67
ns
tsu(TDI-TCK)
Input setup time TDI valid to TCK high
2.5
ns
tsu(TMS-TCK)
Input setup time TMS valid to TCK high
2.5
ns
th(TCK-TDI)
Input hold time TDI valid from TCK high
18
ns
th(TCK-TMS)
Input hold time TMS valid from TCK high
18
ns
3
4
Table 5-22. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
2
PARAMETER
td(TCKL-TDOV)
MIN
Delay time, TCK low to TDO valid
0
TYP
MAX
UNIT
25
ns
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 5-17. JTAG Timing
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5.9.12 Camera Serial Interface (CSI)
The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This
interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity
of each wire of a lane is also configurable. Table 5-23, Figure 5-18, Figure 5-19, and Figure 5-20 describe
the clock and data timing of the CSI.
Table 5-23. CSI Switching Characteristics
over operating Tj temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
HPTX
(1 or 2 data lane PHY)
150
600
(4 data lane PHY)
150
600
(1 or 2 data lane PHY)
75
450
(4 data lane PHY)
75
300
–50
50
HSTXDBR
Data bit rate
fCLK
DDR clock frequency
ΔVCMTX(LF)
Common-level variation from 75 to 450 MHz of CSI2 clock
frequency
tR and tF
20% to 80% rise time and fall time
150
Mbps
MHz
mVpeak
ns
0.3
UI
25
ns
105 +
12*UI
ns
LPTX DRIVER
tRLP and tFLP
15% to 85% rise time and fall time
tEOT (1)
Time from start of THS-TRAIL period to start of LP-11 state
δV/δtSR
(2) (3) (4)
CLOAD (2)
Slew rate. CLOAD = 0 to 5 pF
500
Slew rate. CLOAD = 5 to 20 pF
200
Slew rate. CLOAD = 20 to 70 pF
100
Load capacitance
0
70
Nominal Unit Interval (1, 2, or 3 data lane PHY)
1.11
13.33
Nominal Unit Interval (4 data lane PHY)
1.67
13.33
mV/ns
pF
DATA-CLOCK Timing Specification
UINOM
UIINST,MIN
TSKEW[TX]
Minimum instantaneous Unit Interval (1, 2, or 3 data lane PHY)
0.975*U
1.033 INOM –
0.05
Minimum instantaneous Unit Interval (4 data lane PHY)
1.131
Data to clock skew measured at transmitter
–0.15
ns
ns
0.15
UIINST,
MIN
CSI2 TIMING SPECIFICATION
TCLK-MISS
Time-out for receiver to detect absence of clock transitions and
disable the clock lane HS-RX.
TCLK-POST
Time that the transmitter continues to send HS clock after the
last associated data lane has transitioned to lp mode. Interval is
defined as the period from the end of THS-TRAIL to the beginning
of TCLK-TRAIL.
60 ns +
52*UI
ns
TCLK-PRE
Time that the HS clock shall be driven by the transmitter before
any associated data lane beginning the transition from LP to HS
mode.
8
ns
TCLK-PREPARE
Time that the transmitter drives the clock lane LP-00 line state
immediately before the HS-0 line state starting the HS
transmission.
TCLK-TERM-EN
Time for the clock lane receiver to enable the HS line
termination, starting from the time point when Dn crosses
VIL,MAX.
(1)
(2)
(3)
(4)
48
60
ns
38
95
ns
Time for Dn
to reach
VTERM-EN
38
ns
With an additional load capacitance CCM of 0 to 60 pF on the termination center tap at RX side of the lane
While driving CLOAD. Load capacitance includes 50 pF of transmission line capacitance, and 10 pF each for TX and RX.
When the output voltage is from 15% to 85% of the fully settled LP signal levels
Measured as average across any 50 mV segment of the output signal transition
Specifications
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Table 5-23. CSI Switching Characteristics (continued)
over operating Tj temperature range (unless otherwise noted)
PARAMETER
MIN
TCLK-TRAIL
Time that the transmitter drives the HS-0 state after the last
payload clock bit of a HS transmission burst.
TCLK-PREPARE + TCLK-ZERO
TCLK-PREPARE + time that the transmitter drives the HS-0 state
before starting the clock.
TD-TERM-EN
Time for the data lane receiver to enable the HS line
termination, starting from the time point when Dn crosses
VIL,MAX.
TEOT
Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL,
to the start of the LP-11 state following a HS burst.
THS-PREPARE
Time that the transmitter drives the data lane LP-00 line state
immediately before the HS-0 line state starting the HS
transmission
40 + 4*UI
THS-PREPARE + THS-ZERO
THS-PREPARE + time that the transmitter drives the HS-0 state
prior to transmitting the Sync sequence.
145 ns +
10*UI
THS-SKIP
Time interval during which the HS-RX should ignore any
transitions on the data lane, following a HS burst. The end point
of the interval is defined as the beginning of the LP-11 state
following the HS burst.
THS-EXIT
Time that the transmitter drives LP-11 following a HS burst.
THS-TRAIL
Time that the transmitter drives the flipped differential state after
last payload data bit of a HS transmission burst
TLPX
Transmitted length of any low-power state period
(5)
(6)
(7)
TYP
MAX
UNIT
60
ns
300
ns
Time for Dn
to reach
VTERM-EN
40
35 ns +
4*UI
ns
105 ns
+
n*12*UI
ns
85 +
6*UI
ns
ns
55 ns +
4*UI
ns
100
ns
max(n*8*UI,
60 ns +
n*4*UI) (5) (6)
ns
50 (7)
ns
If a > b then max(a, b) = a, otherwise max(a, b) = b.
Where n = 1 for Forward-direction HS mode and n = 4 for Reverse-direction HS mode
TLPX is an internal state machine timing reference. Externally measured values may differ slightly from the specified values due to
asymmetrical rise and fall times.
CSI2_CLK(P/M)
0.5UI + Tskew
CSI2_TX(P/M)
1 UI
Figure 5-18. Clock and Data Timing in HS Transmission
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Clock
Lane
Data Lane
Dp/Dn
TLPX
VOH
THS-ZERO
THS-SYNC
Disconnect
Terminator
THS-PREPARE
VIH(min)
VIL(max)
VOL
TREOT
Capture
1 Data Bit
TD-TERM-EN
LP-11
LP-01
THS-SKIP
st
LP-00
THS-SETTLE
LP-11
TEOT
THS-TRAIL
START OF
LOW-POWER TO
HS-ZERO TRANSMISSION
HIGH-SPEED
SEQUENCE
TRANSITION
HIGH-SPEED DATA
TRANSMISSION
THS-EXIT
HIGH-SPEED TO
HS-TRAIL LOW-POWER
TRANSITION
Figure 5-19. High-Speed Data Transmission Burst
Disconnect
Terminator
Clock Lane
Dp/Dn
TCLK-SETTLE
VIH(min)
VIL(max)
TLPX
TCLK-ZERO
TCLK-PRE
TCLK-PREPARE
Data Lane
Dp/Dn
THS-PREPARE
Disconnect
Terminator
TLPX
VIH(min)
VIL(max)
THS-SKIP
THS-SETTLE
(1)
The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
Figure 5-20. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
50
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6 Detailed Description
6.1
Overview
The IWR1443 device includes the entire Millimeter Wave blocks and analog baseband signal chain for
three transmitters (two usable at the same instance) and four receivers, as well as a customerprogrammable MCU with a hardware accelerator for radar signal processing. This device is applicable as
a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity and application
code size. These could be cost-sensitive industrial radar sensing applications. Examples are:
• Industrial level sensing
• Industrial automation sensor fusion with radar
• traffic intersection monitoring with radar
• Industrial radar-proximity monitoring.
In terms of scalability, the IWR1443 device could be paired with a low-end external MCU, to address more
complex applications that might require additional memory for larger application software footprint and
faster interfaces. Because the IWR1443 device also provides high speed data interfaces like MIPI-CSI2, it
is suitable for interfacing with more capable external processing blocks. Here system designers can
choose the IWR1443 to provide raw ADC data or use the on-chip Hardware Accelerator for partial
processing viz. first stage Fast Fourier Transform.
6.2
Functional Block Diagram
Rx1
LNA
IF
ADC
Cortex R4F
@ 200MHz
Rx2
LNA
IF
ADC
Digital Frontend
(Decimation
filter chain)
Rx3
LNA
IF
ADC
LNA
IF
ADC
(User programmable)
Prog
RAM
Data
RAM (*)
Boot
ROM
Rx4
Tx1
Tx3
PA
BPM
PA
BPM
RF/Analog sub-system
x4
Synth
(20 GHz)
DMA
Ramp
Generator
Radar Data
Memory (*)
(L3)
Temp
6
GPADC
Master sub-system
(Customer programmed)
RF Control
BIST
Bus Matrix
Tx2
BPM
Bus Matrix
PA
QSPI
Hardware
Accelerator
(**)
ADC Buffer
(**)
QSPI Flash
interface
SPI
External MCU
interface
SPI / I2C
PMIC control
DCAN
Optional communication
interface
Debug
UARTs
Control UART,
And Debug UART
Test/
Debug
JTAG for debug/
development
LVDS/
CSI-2
High-speed Rx or
process
Data for recording or
External DSP
Mailbox
Osc.
(*) Total RAM available in Master subsystem is divided into ARM-Data RAM, Tightly Coupled Memory, Radar Data Memory, Patch Memory
(**) Shared Memory for ADC Buffer and Hardware Accelerator
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6.3
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External Interfaces
The IWR1443 device provides the following external interfaces:
• Reference Clock – Reference clock available for Host Processor after device wakeup.
• Low speed control information
– Up to two 4-line standard SPI interface
– One I2C interface (Pin multiplexed with one of the SPI ports)
• One Controller Area Network (CAN) Port for Industrial Interfacing
• Data – High-Speed serial port following the MIPI CSI2 format. 4 data and 1 clock lane (all differential).
Data from different receive channels can be multiplexed on a single data lane in order to optimize
board routing. This is a unidirectional interface used for data transfer only.
• Reset – Active Low reset for device wakeup from host General Purpose IOs
• Error Signaling – Used for notifying the host in case the Radio Controller detects a fault
The IWR1443 device comprises of three main blocks – Radar (or the Millimeter Wave) System, Master (or
the Control) System and Processing System.
RADAR System
Radar Processing Inter-connect [128 Bit @ 200MHz]
L3
RAM
(384KB)
LVDS/
Mipi-CSI-2
FFT
ACCELERATOR
RF/Analog/Monitoring
ADC
BUFFERS
EDMA
MAILBOX
2x16KB
Master (Control) System Inter-connect [64 Bit @ 200MHz]
CRC
DMA
ROM
JTAG
Integrated MCU
®
®
ARM Cortex R4F
Program
RAM
Data
RAM
Peripheral Inter-connect
SPI
SPI
Timer
UART
QSPI
CAN
I2C
PWM
Figure 6-1. System Interconnect
6.4
6.4.1
Subsystems
RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA,
mixer, IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The
three transmit channels can be operated up to a maximum of two at a time (simultaneously) for transmit
beamforming purpose as required; whereas the four receive channels can all be operated simultaneously.
52
Detailed Description
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6.4.1.1
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Clock Subsystem
The IWR1443 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal or
external clock. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit.
The output of the RF synthesizer is then processed by an X4 multiplier to create the required frequency in
the 76 to 81 GHz spectrum. The RF synthesizer output is modulated by the timing engine block to create
the required waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring
the quality of the generated clock.
RF SYNTH
Self Test
ADCs
TX Phase Mod.
PA Envelope
Lock Detect
Figure 6-2 describes the clock subsystem.
Timing
Engine
CleanUp PLL
OSC_CLKOUT
XO/
Slicer
SYNCIN
TX LO
RX LO
x4
MULT
SYNC_OUT
Lock Detect
SoC Clock
CLK Detect
40 MHz
Figure 6-2. Clock Subsystem
Detailed Description
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6.4.1.2
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Transmit Subsystem
The IWR1443 transmit subsystem consists of three parallel transmit chains, each with independent phase
and amplitude control. A maximum of 2 transmit chains can be operational at the same time. However all
3 chains can be operated together in a time multiplexed fashion.The device supports binary phase
modulation for MIMO radar and interference mitigation.
Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit
chains also support programmable backoff for system optimization.
Figure 6-3 describes the transmit subsystem.
Loopback
Path
Chip
PCB
Package
Self Test
GSG
at 50 W
DF
LO
0 or 180°
(from Timing
Engine)
Figure 6-3. Transmit Subsystem (Per Channel)
6.4.1.3
Receive Subsystem
The IWR1443 receive subsystem consists of four parallel channels. A single receive channel consists of
an LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational
at the same time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the IWR1443 device supports a complex baseband architecture,
which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each
receiver channel. The IWR1443 is targeted for fast chirp systems. The band-pass IF chain has
configurable lower cutoff frequencies above 175 kHz and can support bandwidths up to 15 MHz.
Self Test
LO
Q
DSM
RSSI
ADC Buffer
I
50 W
GSG
I/Q Correction
Decimation
DSM
Image Rejection
Loopback
Path
Chip
PCB
Package
DAC
Saturation
Detect
Figure 6-4 describes the receive subsystem.
DAC
Figure 6-4. Receive Subsystem (Per Channel)
54
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SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Radio Processor Subsystem
The Radio Processor subsystem (also referred to as BIST Subsystem in this document) includes the
digital front-end, the ramp generator and an internal processor for control / configuration of the low-level
RF/analog and ramp generator registers. The Radar Processor also schedules periodic monitoring tasks.
User applications, running on
Master (Control) System, do not have direct access to Radar System; access is based on well-defined API
messages (over a hardware channel) from the master subsystem.
NOTE
This radio processor is programmed by TI and takes care of RF calibration and selftest/monitoring functions (BIST). This processor is not available directly for customer
use/application.
The digital front-end takes care of filtering and decimating the raw sigma-delta ADC output and provides
the final ADC data samples at a programmable sampling rate.
6.4.2
Master (Control) System
The Master (Control) System includes ARM’s Cortex-R4F processor clocked at 200 MHz, which is user
programmable. User applications executing on this processor control the overall operation of the device,
including Radar Control via well-defined API messages, radar signal processing (assisted by the radar
hardware accelerator) and peripherals for external interface.
The Master (Control) System plays a big role in enabling autonomous operation of IWR1443 as a radaron-a-chip sensor. The device includes a quad serial peripheral interface (QSPI) which can be used to
download customer code directly from a serial flash. A (classic) CAN interface is included that can be
used to communicate directly from the device to a CAN bus. An SPI/I2C interface is available for power
management IC (PMIC) control when the IWR1443 is used as an autonomous sensor.
For more complex applications, the device can operate under the control of an external MCU, which can
communicate with IWR1443 device over an SPI interface. In this case, it is possible to use the IWR14xx
as a radar sensor, providing raw detected objects to the external MCU. External MCU could reduce the
application code complexity residing in the device and makes more memory available for radar data cube
inside the IWR1443. This configuration also eliminates the need for a separate serial flash to be
connected to the IWR1443.
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The IWR1443 provides for several digital communications outputs; CSI-2 Clk, 4 data formats – can be
connected to a remote processor for additional processing. Note: CSI-2 data is from the digital front end or
accelerator. When the MSS is used for preprocessing / or another MCU is used in industrial settings the
Serial Tx/Rx or CAN bus can provide lower speed communication than CSI-2. The IWR1443 has
additional serial Tx/Rx for HART protocol for industrial sensors, or Modbus serial protocol. The SPI port
can also provide additional communications or IO control. Additional industrial IO can be Industrial
Ethernet or Wifi.
Note that although four interfaces – one CAN, one I2C and two SPI interfaces – are present in the
IWR1443 device for external communication and PMIC control, only two of these interfaces are usable at
any point in time.
The total memory (RAM) available in the master subsystem is 576 KB. This is partitioned between the
R4F program RAM, R4F data RAM and radar data memory. The maximum usable size for R4F is 448 KB
and this is partitioned between the R4F’s tightly coupled interfaces TCMA (320 KB) and TCMB (128 KB).
Although the complete 448 KB is unified memory and can be used for program or data, typical
applications use TCMA as program and TCMB as data memory.
The remaining memory, starting at a minimum of 128 KB, is available to be used as radar data memory
for storing the ‘radar data cube’. It is possible to increase the radar data memory size in 64 KB
increments, at the cost of corresponding reduction in R4F program or data RAM size. The maximum size
of radar data memory possible is 384 KB. A few example configurations supported are listed in Table 6-1.
Table 6-1. R4F RAM (1)
(1)
OPTION
R4F PROGRAM
RAM
R4F DATA
RAM
RADAR DATA
MEMORY
1
320KB
128KB
128KB
2
256KB
128KB
192KB
3
256KB
64KB
256KB
4
128KB
64KB
384KB
For IWR1443 ES1.0 and ES2.0, available RAM is 448 KB instead of
576KB.
The Master Subsystem Memory Map is shown in the Technical Reference Manual.
56
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6.4.3
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Host Interface
The IWR1443 device communicates with the host radar processor over the following main interfaces:
• Reference Clock – Reference clock available for host processor after device wakeup
• Control – 4-port standard SPI (slave) for host control. Control UART or CAN can be used as a control
interface
. All radio control commands (and response) flow through this interface.
• Data – High-speed serial port following the MIPI CSI2 format (LVDS format can also be used). Four
data and one clock lane (all differential). Data from different receive channels can be multiplexed on a
single data lane to optimize board routing. This is a unidirectional interface used for data transfer only.
• Reset – Active-low reset for device wakeup from host
• Out-of-band interrupt
• Error – Used for notifying the host in case the radio controller detects a fault
6.5
Accelerators and Coprocessors
The Processing System in the IWR1443 device is an accelerator for FFT operations. The Radar Hardware
Accelerator is an IP that enables off-loading the burden of certain frequently used computations in FMCW
radar signal processing from the main processor. It is well-known that FMCW radar signal processing
involves the use of FFT and Log-Magnitude computations in order to obtain a radar image across the
range, velocity and angle dimensions. Some of the frequently used functions in FMCW radar signal
processing can be done within the Radar Hardware Accelerator, while still retaining the flexibility of
implementing other proprietary algorithms in the Master System processor.
Key features of the Radar Processing Accelerator are:
• FFT computation, with programmable FFT sizes (powers of 2) up to 1024-pt complex FFT
• Internal FFT bit-width of 24 bits (each for I and Q) for good SQNR performance, with fully
programmable butterfly scaling at every radix-2 stage for user flexibility
• Built-in capabilities for simple pre-FFT processing – specifically, programmable windowing, basic
interference zeroing-out and basic BPM removal
• Magnitude (absolute value) and Log-Magnitude computation capability
• Flexible data flow and data sample arrangement to support efficient multi-dimensional FFT operations
and transpose accesses as required
• Chaining and Looping mechanism to sequence a set of accelerator operations one-after-another with
minimal intervention from the main processor
• CFAR-CA detector support (linear and logarithmic)
• Miscellaneous other capabilities of the accelerator
– Stitching two or four 1024-point FFTs to get the equivalent of 2048-point or 4096-point FFT for
industrial level sensing applications where large FFT sizes are required
– Slow DFT mode, with resolution equivalent to 16K size FFT, for FFT peak interpolation (eg. range
interpolation) purpose
– Complex Vector Multiplication and Dot product capability for vectors of size up to 512
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6.6
6.6.1
www.ti.com
Other Subsystems
A2D Data Format Over CSI2 Interface
The IWR1443 device uses MIPI D-PHY / CSI2-based format to transfer the raw A2D samples to the
external MCU. This is shown in Figure 6-5.
• Supports four data lanes
• CSI-2 data rate scalable from 150 Mbps to 600
Mbps per lane
• Virtual channel based
• CRC generation
Normal Mode
Frame Period
Acquisition Period
Frame
Ramp/Chirp
1
2
3
N
Data Ready
F
S
L
S
H
S
L
E
L
S
H
S
L
E
L
S
H
S
L
E
L
S
H
S
L
E
F
E
Short
Packet
ST SP ET
LPS
Short
Packet
ST SP ET
.5μs-.8μs
Long
Packet
LPS
ST
PH
Short
Packet
DATA
PF
ET
LPS
ST SP ET
LPS
Chirp 1 data
Data rate/Lane should be such that "Chirp + Interchirp" period
should be able to accommodate the data transfer
Copyright © 2017, Texas Instruments Incorporated
Frame Start – CSi2 VSYNC Start Short Packet
Line Start – CSI2 HSYNC Start Short Packet
Line End – CSI2 HSYNC End Short Packet
Frame End – CSi2 VSYNC End Short Packet
Figure 6-5. CSI-2 Transmission Format
58
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The data payload is constructed with the following three types of information:
• Chirp profile information
• The actual chirp number
• A2D data corresponding to chirps of all four channels
– Interleaved fashion
• Chirp quality data (configurable)
The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The
data packet packing format is shown in Figure 6-6
First
5
11
NU
CH Chirp
Profile
5
11
NU
CH Chirp
Profile
5
11
NU
CH Chirp
Profile
5
11
NU
CH Chirp
Profile
1
0
11
0
11
0
11
0
11
Channel
Number
1
Chirp Num
Channel
Number
1
0
0
0
0
11
0
11
0
11
0
11
0
11
0
11
0
11
Continues till the
last sample. Max 1023
0
CQ Data [47:36]
CQ Data [35:24]
CQ Data [59:48]
0
CQ Data [23:12]
CQ Data [11:0]
11
0
Channel 3 Sample 1 q
Channel 3 Sample 1 i
11
0
Channel 2 Sample 1 q
Channel 2 Sample 1 i
11
0
Channel 1 Sample 1 q
Channel 1 Sample 1 i
11
0
Channel 0 Sample 1 q
Channel 0 Sample 1 i
11
0
11
Channel 3 Sample 0 q
Channel 3 Sample 0 i
11
0
11
Channel 2 Sample 0 q
Channel 2 Sample 0 i
11
0
11
Channel 1 Sample 0 q
Channel 1 Sample 0 i
11
0
11
Channel 0 Sample 0 q
Channel 0 Sample 0 i
11
0
Chirp Num
0
11
0
Chirp Num
Channel
Number
11
0
Chirp Num
Channel
Number
1
0
NU
0
CQ Data [63:60]
Last
Figure 6-6. Data Packet Packing Format for 12-Bit Complex Configuration
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6.6.2
www.ti.com
ADC Channels (Service) for User Application
The IWR1443 device includes provision for an ADC service for user application, where the
GPADC engine present inside the device can be used to measure up to six external voltages. The
GPADC1, GPADC2, GPADC3, GPADC4, GPADC5, and GPADC6 pins are used for this purpose.
• ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for
customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST
subsystem. This API could be linked with the user application running on the Master R4.
• BIST subsystem firmware will internally schedule these measurements along with other RF and Analog
monitoring operations. The API allows configuring the settling time (number of ADC samples to skip)
and number of consecutive samples to take. At the end of a frame, the minimum, maximum and
average of the readings will be reported for each of the monitored voltages.
GPADC Specifications:
• 625 Ksps SAR ADC
• 0 to 1.8V input range
• 10-bit resolution
• For 5 out of the 6 inputs, an optional internal buffer (0.4-1.3V input range) is available. Without the
buffer, the ADC has a switched capacitor input load modeled with 5pF of sampling capacitance and
12pF parasitic capacitance (ADC channel mapped to C14, the internal buffer is not available).
ANALOG TEST 1-4,
ANAMUX
5
GPADC
5
VSENSE
Figure 6-7. ADC Path
Table 6-2. GP-ADC Parameter
PARAMETER
ADC supply
ADC unbuffered input voltage range
ADC buffered input voltage range
(1)
TYP
UNIT
1.8
V
0 – 1.8
V
0.4 – 1.3
V
ADC resolution
10
bits
ADC offset error
±5
LSB
ADC gain error
±5
LSB
ADC DNL
–1/+2.5
LSB
ADC INL
±2.5
LSB
ADC sample rate (2)
625
Ksps
ADC sampling time (2)
400
ns
ADC internal cap
10
pF
ADC buffer input capacitance
2
pF
(1)
(2)
60
Outside of given range, the buffer output will become nonlinear.
ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.
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Table 6-2. GP-ADC Parameter (continued)
PARAMETER
ADC input leakage current
TYP
UNIT
3
uA
Detailed Description
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Identification
The JTAG identification code is described in the IWR1443 Errata.
The JTAG interface provides the XDS emulator and boundary scan connectivity to the IWR1443.
Table 6-3. JTAG Interface
6.8
Signal
SoC Pin
Name
Type
Function
TCK
M13
Test Clock
Input
Free Running clock when used with emulators viz.
Spectrum Digital’s XDS200 or TI’s XDS110
TMS
L13
Test Mode Select
Input
Directs the next state of the JTAG state machine
TDI
H13
Test Data Input
Input
Scan Data Input to the device
TDO
J13
Test Data Output
Output
Scan Data Output of the device
Boot Modes
As soon as device reset is de-asserted, the R4F processor of the Master (Control) system starts executing
its bootloader from an on-chip ROM memory.
The bootloader of the Master system operates in two basic modes and these are specified on the user
hardware (Printed Circuit Board) by configuring what are termed as “Sense on Power” (SOP) pins. These
pins on the device boundary are scanned by the bootloader firmware and choice of mode for bootloader
operation is made.
Table 6-4 enumerates the relevant SOP combinations and how these map to bootloader operation.
Table 6-4. SOP Combinations
SOP2 (P13)
62
SOP1 (P11)
SOP0 (J13)
BOOTLOADER MODE AND OPERATION
0
0
1
Functional Mode
Device Bootloader loads user application from QSPI Serial Flash to
internal RAM and switches the control to it
1
0
1
Flashing Mode
Device Bootloader spins in loop to allow flashing of user application
(or device firmware patch – Supplied by TI) to the serial flash
0
1
1
Debug Mode
Bootloader is bypassed and R4F processor is halted. This allows
user to connect emulator at a known point
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Flashing Mode
In Flashing Mode, the Master System’s bootloader enables the UART driver and expects a data stream
comprising of User Application (Binary Image) and Device Firmware (referred to as Device Firmware
Patch or Service Pack) from an external flashing utility. Figure 6-8 shows the flashing utility executing on a
PC platform, but the protocol can be accomplished on an embedded platform as well.
Serial
FLASH
QSPI
SOP0
SOP1
SOP2
User Application
And device firmware
Flashing
x
x
x
ROM
Radar
Section
RAM
Program
RAM
UART
Integrated MCU
ARM Cortex-R4F
x
x
FLASHING
UTILITY
Data
RAM
Figure 6-8. Figure 5. Bootloader Flashing Mode
Detailed Description
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Functional Mode
In Functional Mode, the Master System’s bootloader looks for a valid image in the serial flash memory,
interfaced over the QSPI port. If a valid image is found, the bootloader transfers the same to Master
System’s memory subsystem. The image format contains the MSS application code and the radar
subsystem patch code.
If a valid image (or the QSPI Serial Flash is not found), the bootloader initializes the SPI port and awaits
for the image transfer. This operation comes handy for configurations where the IWR1443 is interfaced to
an external processor which has its own nonvolatile storage hence can store the user application and the
IWR1443 device’s firmware image.
User Application is Loaded
From FLASH to R4F RAM and
Device Patch to Radar Section
QSPI
SOP0
SOP1
SOP2
ROM
Radar
Section
RAM
Data
RAM
Serial
Flash
UART
Integrated MCU
ARM Cortex-R4F
Histogram
RAM
SPI
External
Processor
User Application is Loaded
From FLASH to R4F RAM and
Device Patch to Radar Section
Figure 6-9. Bootloader’s Functional Mode
64
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
Application Information
Application information can be found on IWR Application web page.
7.2
Reference Schematic
The reference schematic and power supply information can be found in the IWR1443 EVM
Documentation.
Applications, Implementation, and Layout
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7.3.1
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Layout
Layout Guidelines
General layout guidelines can be found in the IWR1443 EVM Documentation, IWR1443BOOST Layout
and Design Files, and IWR1443BOOST Schematics, Assembly Files, and BOM.
7.3.2
Layout Example
The IWR1443 EVM, RF layout can be found in the IWR1443BOOST Layout and Design Files and
IWR1443BOOST Schematics, Assembly Files, and BOM.
7.3.3
Stackup Details
Layout Stackup details can be found in the IWR1443BOOST Layout and Design Files and
IWR1443BOOST Schematics, Assembly Files, and BOM.
There are specific RF guidelines for the RF Tx and Rx. There are additional layout guidelines for other
sections in the IWR1443 Checklist for Schematic Review, Layout Review, Bringup/Wakeup.
66
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8 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions follow.
8.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, IWR1443). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ABL0161), the temperature range (for example, blank is the default
commercial temperature range). Figure 8-1 provides a legend for reading the complete device name for
any IWR1443 device.
For orderable part numbers of IWR1443 devices in the ABL0161 package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the IWR1443 Device
Errata.
Device and Documentation Support
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IWR
www.ti.com
1
4
43
F
__
__
Q
A
G
ABL
Prefix
IWR = Industrial
Generation
1 = 77 GHz Band
Variant
Increasing digital performance, generation based. Gen 1:
2 = FE
4 = FE + FFT + MCU
6 = FE + MCU + DSP
__
Tray or Tape & Reel
R = Tape & Reel
Blank = Tray
Package
ABL = BGA
Security
G = General
S = Secure
Num RX / TX Channels
RX = 1, 2, 3, 4
TX = 1, 2, 3
Silicon PG Revision
blank = Rev 2.0
F = Rev 3.0
Features
blank = baseline
Temperature (TJ)
A = -40C to 105C
Safety Level
Q = Quality Manage
Figure 8-1. Device Nomenclature
8.2
Tools and Software
Models
IWR1443 BSDL Model Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
IWR1443 IBIS Model IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
I\WR1443 Checklist for Schematic Review, Layout Review, Bringup/Wakeup A set of steps in
spreadsheet form to select system functions and pinmux options. Specific EVM schematic
and layout notes to apply to customer engineering. A bringup checklist is suggested for
customers.
8.3
Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (IWR1443). In the upper right corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral
follows.
Errata
IWR1443 Device Errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
68
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8.4
SWRS211C – MAY 2017 – REVISED OCTOBER 2018
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.5
Trademarks
E2E is a trademark of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
8.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
CAUTION
The following package information is subject to change without notice.
70
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
IWR1443FQAGABL
ACTIVE
FC/CSP
ABL
161
176
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 105
IWR1443
QG
964FC
C
ABL G1
964FC ABL
IWR1443FQAGABLR
ACTIVE
FC/CSP
ABL
161
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 105
IWR1443
QG
964FC
C
ABL G1
964FC ABL
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
ABL0161A
FCBGA - 1.17 mm max height
SCALE 1.400
PLASTIC BALL GRID ARRAY
10.5
10.3
A
B
BALL A1 CORNER
10.5
10.3
1.17 MAX
C
SEATING PLANE
BALL TYP
0.37
TYP
0.27
0.1 C
9.1 TYP
PKG
(0.65) TYP
R
P
(0.65) TYP
N
M
L
K
J
9.1
TYP
PKG
H
G
F
E
D
161X
C
B
0.45
0.35
0.15
0.08
C A B
C
A
0.65 TYP
BALL A1 CORNER
1 2
3
4 5
6 7 8
9 10 11 12 13 14 15
0.65 TYP
4222493/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ABL0161A
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
(0.65) TYP
B
C
D
E
F
G
PKG
H
J
K
L
M
N
P
R
PKG
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
0.05 MIN
( 0.32)
METAL
METAL UNDER
SOLDER MASK
( 0.32)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222493/B 10/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ABL0161A
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
(0.65) TYP
C
D
E
F
G
PKG
H
J
K
L
M
N
P
R
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4222493/B 10/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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