Texas Instruments | OPT3101 ToF-Based Long-Range Proximity and Distance Sensor AFE (Rev. A) | Datasheet | Texas Instruments OPT3101 ToF-Based Long-Range Proximity and Distance Sensor AFE (Rev. A) Datasheet

Texas Instruments OPT3101 ToF-Based Long-Range Proximity and Distance Sensor AFE (Rev. A) Datasheet
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OPT3101
SBAS883A – FEBRUARY 2018 – REVISED JUNE 2018
OPT3101 ToF-Based Long-Range Proximity and Distance Sensor AFE
1 Features
2 Applications
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1
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•
•
•
•
•
•
•
•
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Long-Range Distance Measurement, Obstacle
Detection and Avoidance
Flexibility to Customize Design With a Wide
Variety of Photodiodes and Emitters
Sample Rate up to 4 kHz
16-Bit Distance Output at 15-m Unambiguous
Range
De-Aliasing to Extend the Distance Range
Supports 3 Transmitter Channels for Multi-Zone
Operation
Excellent Ambient and Sunlight Rejection
200-nA Full-Scale Signal Current
88-dB Signal Phase Dynamic Range at 1 kHz
Supports DC Ambient up to 200 µA, 60-dB
Rejection for Ambient at 1 kHz
Distance Measurement Independent of Object
Reflectivity
Adaptive HDR to Save Power and Increase the
Dynamic Range
Configurable Event Detection and Interrupt Output
Mechanism
I2C Interface for Control and Data
Integrated Illumination Driver With Programmable
Current Control up to 173 mA
Integrated Temperature Sensor for Calibration
Single 3.3-V or 1.8-V and 3.3-V Supply Operation
Operating Ambient Temperature: –40 to 85°C
Application Block Diagram
•
Precise Long-Range Distance Measurement
– Background Suppression and Accurate Object
Counting in High-Speed Conveyor Belt
Systems
– Precise Displacement Sensing in Factory
Automation
– Non-Contact Distance and/or Level
Measurement in Harsh Environments (HighTemperature or Hazardous Conditions)
Obstacle Detection and Avoidance
– Precise Distance Measurement for Drone
Landing and Navigation
– Cliff and Edge Detection in Vacuum Cleaners
(No False Triggers From Dark Carpets)
– Perimeter Scan in Automatic Guided Vehicle
Like Lawnmowers, Robots
– Obstruction Sensing in Applications Such as
Smoke Detectors, Emergency Exits
3 Description
The OPT3101 device is a high-speed, high-resolution
AFE for continuous-wave, time-of-flight based
proximity sensing and range finding. The device
integrates the complete depth processing pipeline
that includes the ADC, timing sequencer, and the
digital processing engine. The device also has a builtin illumination driver that covers most of the target
applications.
Given the high ambient rejection ratio, the device can
support very high ambient conditions, including full
sunlight of 130 klx.
The timing sequencer is highly configurable to
provide for application-specific trade-offs of power
versus performance.
The device provides depth data that consists of
phase, amplitude, and ambient measurements. The
calibration subsystem supports phase-data calibration
for inaccuracies resulting from temperature and
crosstalk.
Device Information(1)
PART NUMBER
OPT3101
PACKAGE
VQFN (28)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPT3101
SBAS883A – FEBRUARY 2018 – REVISED JUNE 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Programming ..........................................................
Register Maps .........................................................
12
12
12
30
34
8
Application and Implementation ...................... 102
8.1 Application Information.......................................... 102
8.2 Typical Application ................................................ 102
8.3 Initialization Set Up .............................................. 106
9
Power Supply Recommendations.................... 107
9.1 System With Off-Chip 1.8-V Regulator ................ 107
9.2 System With On-Chip 1.8-V Regulator ................. 107
10 Layout................................................................. 108
10.1 Layout Guidelines ............................................... 108
10.2 Layout Example .................................................. 108
11 Device and Documentation Support ............... 111
11.1 Documentation Support .....................................
11.2 Receiving Notification of Documentation
Updates..................................................................
11.3 Community Resources........................................
11.4 Trademarks .........................................................
11.5 Electrostatic Discharge Caution ..........................
11.6 Glossary ..............................................................
111
111
111
111
111
111
12 Mechanical, Packaging, and Orderable
Information ......................................................... 111
4 Revision History
Changes from Original (February 2018) to Revision A
Page
•
Changged several items in the Features list ......................................................................................................................... 1
•
Changed the Application Block Diagram ............................................................................................................................... 1
•
Changed several items in the Applications section ............................................................................................................... 1
•
Changed all occurrences of "free-air temperature" in the data sheet to "junction temperature" ........................................... 5
•
Changed all occurrances of VCC in the data sheet to VCC .................................................................................................... 5
•
Added a row to the Absolute Maximum Ratings table for VO, Output voltage ...................................................................... 5
•
Added two rows to the Recommended Operating Conditions table for VI and VO ................................................................. 5
•
Changed subscripting of some parameter symbols in the Electrical Characteristics condition statement ............................ 6
•
Changed subscripting for tPU,Deepsleep and tPU,Standby ............................................................................................................... 6
•
Changed table rulings for VOH, VOL, and II ............................................................................................................................. 7
•
Changed Figure 15............................................................................................................................................................... 13
•
Changed Figure 16............................................................................................................................................................... 14
•
Changed the contents of numerous cells in the Table 29 table ........................................................................................... 34
•
Added the Table 30 table ..................................................................................................................................................... 40
•
Changed the content in most of the subsections of Register Descriptions.......................................................................... 40
2
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5 Pin Configuration and Functions
A0
AVSS
AVSS
INP
INM
AVSS
28
27
26
25
24
23
(RHF Package)
(28-Pin VQFN)
Top View
A1
1
22
NC
A2
2
21
AVDD
IOVSS
3
20
AVDD3
TX2
4
19
DVDD
18
REG_MODE
Thermal
TX1
5
VSSL
6
17
RST_MS
TX0
7
16
SDA_M
IOVSS
8
15
SCL_M
14
SDA_S
13
SCL_S
12
GP2
11
GP1
10
IOVDD
IOVDD
9
Pad
Not to scale
NC – No internal connection
Pin Functions
PIN
NAME
NO.
I/O
TYPE (1)
DESCRIPTION
A0
28
I
AVDD
I2C slave LSB0 address bit
A1
1
I
AVDD
I2C slave LSB1 address bit
A2
2
I
AVDD
I2C slave LSB2 address bit
AVDD
21
—
—
1.8-V analog supply
AVDD3
20
—
—
3.3-V analog supply
AVSS
23, 26, 27
—
—
Analog ground
DVDD
19
—
—
1.8-V digital supply
GP1
11
O
IOVDD
General-purpose output
GP2
12
I/O
IOVDD
General-purpose output, CLKREF input
INM
24
I
AVDD
AFE negative input. Connect photodiode equivalent capacitance. Connect the
other end of the capacitor to ground AVSS.
INP
25
I
AVDD
AFE positive input. Connect photodiode cathode. Connect the Anode of the
photodiode to ground AVSS.
IOVDD
9, 10
—
—
Supply for I/O and illumination driver
IOVSS
3, 8
—
—
Ground for digital and I/O
NC
22
—
—
No internal connection
REG_MODE
18
I
IOVDD
(1)
Mode to select internal regulator for 1.8-V supplies (AVDD, DVDD)
This column provides the I/O voltage domain of the input and output pins.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
TYPE (1)
DESCRIPTION
RST_MS
17
I
IOVDD
Active-low global reset, monoshot trigger. There is no internal pullup on this pin.
Connect this pin to the host controller or add a pullup resistor.
SCL_M
15
O
IOVDD
I2C master clock. Connect with a 10-kΩ resistor to a 3.3-V supply.
SCL_S
13
I
IOVDD
I2C slave clock. Connect with a 10-kΩ resistor to a 3.3-V supply.
SDA_M
16
I/O
IOVDD
I2C master data. Connect with a 10-kΩ resistor to a 3.3-V supply.
SDA_S
14
I/O
IOVDD
I2C slave data. Connect with a 10-kΩ resistor to a 3.3-V supply.
TX0
7
O
IOVDD
Illumination driver output. Connect to LED cathode. Anode should be connected
to a supply.
TX1
5
O
IOVDD
Illumination driver output. Connect to LED cathode. Anode should be connected
to a supply.
TX2
4
O
IOVDD
Illumination driver output. Connect to LED cathode. Anode should be connected
to a supply.
VSSL
6
—
—
Illumination driver ground.
Thermal pad
—
—
—
Thermal pad of the device. Connect thermal pad to AVSS PCB ground plane
using multiple vias for good thermal performance.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
IOVDD
Digital I/O supply
–0.3
4
V
AVDD3
Analog supply
–0.3
4
V
AVDD
Analog supply
–0.3
2.2
V
DVDD
Digital supply
–0.3
2.2
V
VI
Input voltage at input pins
–0.3
VCC + 0.3
(2)
VO
Output voltage at output pins
–0.3
VCC + 0.3
(2)
TJ
Junction temperature
–40
125
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
V
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VCC is equal to IOVDD or AVDD, based on the I/O voltage domain listed in the Pin Functions table.
6.2 ESD Ratings
VALUE
V (ESD)
(1)
(2)
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins
Electrostatic discharge
UNIT
±1000
(1)
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
1.7
1.8 to 3.3
3.6
V
Analog supply
3
3.3
3.6
V
AVDD
Analog supply
1.7
1.8
1.9
V
DVDD
Digital supply
1.7
1.8
1.9
V
VDRV
TX0, TX1, TX2 pin voltage
0.7
3.6
V
V
IOVDD
Digital I/O supply
AVDD3
UNIT
VI
Input voltage at input pins
–0.1
VCC + 0.3
VO
Output voltage at output pins
–0.1
VCC + 0.3
(1)
V
TA
Ambient temperature
–40
85
°C
(1)
(1)
VCC is equal to IOVDD or AVDD, based on the I/O voltage domain listed in the Pin Functions table.
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6.4 Thermal Information
OPT3101
THERMAL METRIC
(1)
RHF (QFN)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
32.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
21.6
°C/W
RθJB
Junction-to-board thermal resistance
10.8
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
10.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.6
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Electrical Characteristics
All specifications at TA = 25°C, VAVDD = 1.8 V, VAVDD3 = 3.3 V, VDVDD = 1.8 V, VIOVDD = 3.3 V, IambMax = 20 µA, photodiode with
a capacitance of 2 pF at AFE input unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AFE
Iref
Full-scale signal current at fmod
Inoise
AFE input-referred current noise
IambMax
Maximum ambient dc current at input
µ1000Hz
Ambient attenuation at 1000 Hz
VR
200
nA
1.5 (1)
pA/√Hz
(2)
µA
60
dB
Bias voltage at INM, INP
1
V
Cin
Maximum external photodiode
capacitance at input
6
pF
fmod
Modulation frequency
sps
Sample rate
tPU,Deepsleep
Deep sleep recovery time
tPU,Standby
Standby recovery time
AVDD3 = 3.3 V
200
10
MHz
4000
Monoshot mode only
(3)
Hz
1
ms
50
µs
173.6
mA
ILLUMINATION DRIVER
Maximum built-in illumination driver
current
IDRV
POWER (ACTIVE MODE AT MAXIMUM FRAME RATE)
IAVDD
1.8-V analog supply current
11.6
mA
IDVDD
1.8-V digital supply current
5.7
mA
IAVDD3
3.3-V analog supply current
0.5
mA
IIOVDD
3.3-V I/O supply current
0.7
mA
POWER (DEEP SLEEP MODE)
IAVDD
1.8-V analog supply current
1
µA
IDVDD
1.8-V digital supply current
3
µA
IAVDD3
3.3-V analog supply current
1
µA
IIOVDD
3.3-V I/O current
2
µA
POWER (ACTIVE MODE AT MAXIMUM FRAME RATE), INTERNAL LDO MODE
IAVDD3
3.3-V analog supply current
Internal LDO mode
17.9
mA
IIOVDD
3.3-V I/O supply current
Internal LDO mode
0.7
mA
POWER (DEEP SLEEP MODE), INTERNAL LDO MODE
IAVDD3
3.3-V analog supply current
Internal LDO mode
80
µA
IIOVDD
3.3-V I/O supply current
Internal LDO mode
2
µA
CMOS I/Os
(1)
(2)
(3)
6
Noise is higher by 20% with a photodiode capacitance of 6 pF at the AFE input.
IambMax is programmable through register setting IAMB_MAX_SEL.
Reference, oscillator, and ambient cancellation are not powered down.
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Electrical Characteristics (continued)
All specifications at TA = 25°C, VAVDD = 1.8 V, VAVDD3 = 3.3 V, VDVDD = 1.8 V, VIOVDD = 3.3 V, IambMax = 20 µA, photodiode with
a capacitance of 2 pF at AFE input unless otherwise noted.
PARAMETER
VIH
Input high-level threshold
VIL
Input low-level threshold
TEST CONDITIONS
MIN
MAX
UNIT
V
0.3 ×
VCC
IOH = –2 mA
VOH
TYP
0.7 ×
VCC
Output high level
IOH = –8 mA
VCC
(4)
–
0.45
VCC
(4)
V
V
–
0.5
IOL = 2 mA
0.35
IOL = 8 mA
0.65
Pins with pullup, pulldown resistor
±50
VOL
Output low level
II
Input pin leakage current
CI
Input capacitance
5
pF
IOH
Maximum output current high level
10
mA
IOL
Maximum output current low level
10
mA
(4)
Pins without pullup, pulldown resistor
V
µA
±10
VCC is equal to IOVDD or AVDD, based on the I/O voltage domain listed in the Pin Functions table.
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
RSTZ_MS Pin
tPWMonoShot Pulse duration of monoshot trigger
0.1
tPWReset
30
Reset pulse duration
1
µs
µs
2
I C Slave
fSCL
I 2 C slave SCL operating frequency
400
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6.7 Typical Characteristics
All specifications at TA = 25°C, VAVDD = 1.8 V, VAVDD3 = 3.3 V, VDVDD = 1.8 V, VIOVDD = 3.3 V, IambMax = 20 µA, photodiode with
a capacitance of 2 pF at INP and INM, unless otherwise noted.
Sample rate = 1000 Hz
Figure 1. Distance Standard Deviation vs AFE Input Signal
Figure 2. AFE Thermal Noise vs Maximum Ambient Current
Supported
Figure 3. Illumination Driver I-V Characteristics
8
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6.7.1 Continuous Mode
Duty Cycle =
(NUM_AVG_SUB_FRAMES + 1) / (NUM_SUB_FRAMES + 1)
Figure 4. Supply Current in Continuous Mode
Duty Cycle =
(NUM_AVG_SUB_FRAMES + 1) / (NUM_SUB_FRAMES + 1)
Figure 5. Supply Current in Continuous Mode with Internal
LDO
6.7.2 Monoshot Mode
Figure 6. AVDD Supply Current in Monoshot Mode
Figure 7. DVDD Supply Current in Monoshot Mode
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Monoshot Mode (continued)
Figure 8. AVDD3 Supply Current in Monoshot Mode
Figure 9. IOVDD Supply Current in Monoshot Mode
Figure 10. Illumination Supply Current in Monoshot Mode
10
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6.7.3 Monoshot Mode With Internal LDO
Figure 11. AVDD3 Supply Current in Monoshot Mode With
Internal LDO
Figure 12. IOVDD Supply Current in Monoshot Mode With
Internal LDO
Figure 13. Illumination Supply Current in Monoshot Mode With Internal LDO
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7 Detailed Description
7.1 Overview
The OPT3101 device is a fully integrated analog front end (AFE) based on the time-of-flight (ToF) principle using
active illumination. The OPT3101 AFE connects to an external illuminator (LED, VCSEL, or LASER) to transmit
modulated optical signals, and reflected signals are received by an external photodiode which connects to the
input of the AFE. The received signal is converted to amplitude and phase information by the AFE and depth
engine. This output is stored in registers, which can be read out through the device I2C interface.
The OPT3101 AFE has the following blocks:
• Timing generator: generates the sequencing signals for the sensor, illumination, and depth processor
• ToF receiver AFE
• Illumination driver
• Depth engine: calculates phase and amplitude
• I2C slave for configuration and output data interface of the device registers by the host processor
• I2C master for external temperature sensing, auto load registers from an external EEPROM
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Timing Generator
The timing generator (TG) generates the timing sequence for each frame. The TG has the following features:
• Frame rate control
• Sequencing
The following are various modes of operation:
• Continuous or monoshot mode
• Auto high-dynamic-range (HDR) mode or non-HDR mode
• Single-LED or multi-LED mode
12
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Feature Description (continued)
Different modes of operation are explained below.
Figure 14. Continuous and Monoshot Modes
7.3.1.1 Continuous Operating Mode
In this mode, the device runs continuously at the programmed sample rate. More details about the frame timing
are described in Non-HDR Mode and Auto HDR Mode.
7.3.1.2 Monoshot Mode
Monoshot mode is a low-power mode. In this mode, the device is in a deep sleep state and waits for an external
trigger. The sample can be initiated by an RST_MS pin (active-low) trigger or the register trigger
(MONOSHOT_BIT). On trigger, the device comes out of power down, waits for the programmed delay
(POWERUP_DELAY) to start a frame, captures the specified number of samples (MONOSHOT_NUMFRAME),
then goes into a deep sleep state to save power. A new interrupt is serviced only after completing the current
frame capture. Any interrupt during the capture of a frame is discarded. Figure 15 shows the timing diagram of
the monoshot mode with the RST_MS pin trigger. From the trigger, the frame start can be delayed by setting the
POWERUP_DELAY register. The delay between the trigger and the sample start (FR_VD signal in Figure 15) is
(64 × POWERUP_DELAY + 2) × tCLK. A minimum delay of 0.4 ms is required for the device to come out of the
deep sleep state. A maximum of 26.2 ms delay can be programmed. This mode can also be used for
synchronized capture from an external host.
The RST_MS pin is a dual-purpose pin used for reset and monoshot triggering. For reset, give a pulse duration
that is > 30 µs. For monoshot trigger, give a pulse duration that is < 1 µs and > 100 ns.
Figure 15. Timing for Pin-Triggered Monoshot Mode With RST_MS
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Feature Description (continued)
For register-triggered monoshot mode, the host writes 1 to the interrupt register (MONOSHOT_BIT) to initiate
sample capture. Once the data ready of the Nth sample is available, the device automatically clears the interrupt
register bit and goes into deep sleep state.
Figure 16. Timing for Register (MONOSHOT_BIT) Triggered Monoshot Mode
Table 1. Monoshot Mode Register Settings
PARAMETER
ADDRESS
DESCRIPTION
MONOSHOT_MODE
27h[1:0]
0: Continuous mode | 3: Monoshot mode | Other values: Not valid
MONOSHOT_NUMFRAME
27h[7:2]
Number of frames to be captured for every trigger.
POWERUP_DELAY
MONOSHOT_BIT
26h[23:10]
0h[23]
Register to program the delay from the external trigger to start of frame (FRAME_VD).
Delay = (64 × POWERUP_DELAY + 2) × tCLK, tCLK = 25 ns.
Monoshot trigger register.
Write 1 to start sample capture. The bit is auto cleared after capture completion.
7.3.1.3 Non-HDR Mode
In this mode a fixed LED current is used for the Illumination driver. Figure 17 shows the frame timing. Each
frame is divided into multiple sub-frames, which can be varied from 1 to 212. Each sub-frame is 10,000 clocks of
40 MHz, which is equal to a 4-kHz sub-frame rate. In each sub-frame, 8192 clocks is the photodiode signal
integration time and the remainder of the time is used for processing the signal and computing amplitude and
phase. The device can be operated at the highest frame rate of 4 kHz by setting the number of sub-frames to 1
(NUM_SUB_FRAMES = 0) in a frame.
4000
Sample Rate =
1 + NUM _ SUB _ FRAMES
(1)
Table 2. Sample-Rate Configuration Registers
PARAMETER
ADDRESS
DESCRIPTION
NUM_SUB_FRAMES
9Fh[11:0]
Total number of sub-frames in a frame. Each sub-frame is 0.25 ms.
Number of sub frames in a frame = NUM_SUB_FRAMES + 1.
This number must be equal or greater than NUM_AVG_SUB_FRAMES.
NUM_AVG_SUB_FRAMES
9Fh[23:12]
Specifies the number of sub-frames to be averaged in a frame. Number of averaged
sub-frames should be a power of 2
Averaging sub-frames = NUM_AVG_SUB_FRAMES + 1.
If the number of averaged sub-frames is not a power of 2, the output amplitude AMP_OUT scales according
Equation 2. This is only a digital scaling factor and does not affect the distance noise of the measurement. It is
recommended to use number of averaged sub-frames as a power of 2.
(2)
14
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(1)
N1 = 10,000; number of 40-MHz clocks in a sub-frame.
(2)
N2 = NUM_SUB_FRAMES + 1 is the number of sub-frames in a frame, programmable in the range of 1 to 212.
Figure 17. Frame Timing Diagram
7.3.1.4 Auto HDR Mode
In this mode, the sequencer switches between two illumination driver currents to extend the dynamic range,
depending on the signal saturation and lower amplitude threshold. The principle of operation is explained in
Figure 18. When the illumination driver current is high and the amplitude exceeds the saturation threshold,
HDR_THR_HIGH, the illumination driver is switched to the lower current. When the illumination driver current is
low and the measured amplitude is below the lower threshold, HDR_THR_LOW, the illumination driver is
switched to the higher current.
Figure 18. Auto HDR Mode: State Diagram
Figure 19 shows the frame timing diagram for HDR mode. In this mode, the first sub-frame information is used to
make a decision about the validity of the output. If the first sub-frame output is valid, the same illumination DAC
is used for the rest of the frame, otherwise the illumination driver is switched to the second illumination DAC
current.
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The illumination driver DAC switching is shown for a particular scenario.
Figure 19. Auto HDR Mode Frame Timing Diagram
Amplitude thresholds for the HDR mode should be chosen according to Equation 3. Choice of the two
illumination driver DAC currents depends on the end application.
HDR _ THR _ HIGH ILLUM _ DAC _ H
>
HDR _ THR _ LOW ILLUM _ DAC _ L
(3)
HDR_THR_HIGH is the saturation threshold for the HDR switching, and should be set slightly below the actual
saturation amplitude (HDR should trigger before the AFE analog path saturates). HDR_THR_LOW is the
accuracy threshold, the amplitude below which the distance accuracy is poor. Figure 20 shows an illustration of
the HDR operation with distance. At a distance close to the sensor, the lower illumination DAC current is used.
As the object moves away from the sensor, ILLUM_DAC switches to a higher value once the amplitude falls
below the lower threshold (HDR_THR_LOW). At the switching point, non-saturation is ensured by choosing the
DAC currents according to Equation 3. As the object moves towards the sensor, ILLUM_DAC switches to the
lower value once the amplitude reaches the saturation level (HDR_THR_HIGH). At this transition, the amplitude
with ILLUM_DAC_L is above HDR_THR_LOW.
Figure 20. HDR Mode Operation With Distance
16
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Table 3. HDR Mode Configuration Registers
PARAMETER
ADDRESS
DESCRIPTION
EN_ADAPTIVE_HDR
2Ah[15]
Enable adaptive HDR mode.
Minimum number of sub-frames in a frame in this mode is 2 (NUM_SUB_FRAMES =
1)
SEL_HDR_MODE
2Ah[16]
Chooses which current to use when EN_ADAPTIVE_HDR = 0.
0 – ILLUM_DAC_L | 1 – ILLUM_DAC_H
HDR_THR_HIGH
2Bh[15:0]
Saturation amplitude threshold of the auto HDR for high DAC current
(ILLUM_DAC_H)
Write a value of 27000
HDR_THR_LOW
2Ch[15:0]
Accuracy threshold of the auto HDR for low DAC current (ILLUM_DAC_L)
= HDR_THR_HIGH × (ILLUM_DAC_L / ILLUM_DAC_H) × (1 / 1.2)
ILLUM_DAC_L_TX0
29h[4:0]
ILLUM_DAC_L of TX0 channel
ILLUM_DAC_H_TX0
29h[9:5]
ILLUM_DAC_H of TX0 channel
ILLUM_DAC_L_TX1
29h[14:10]
ILLUM_DAC_L of TX1 channel
ILLUM_DAC_H_TX1
29h[19:15]
ILLUM_DAC_H of TX1 channel
ILLUM_DAC_L_TX2
29h[23:20],
2Ah[23]
ILLUM_DAC_L of TX2 channel
ILLUM_DAC_H_TX2
2Ah[22:18]
ILLUM_DAC_H of TX2 channel
7.3.1.5 Multi Channel Mode
The OPT3101 AFE supports up to three separate illumination channels. Only one illumination channel can be
activated at a given point of time. In multi channel mode, the illumination driver switches current between
different pins (TX0, TX1, and TX2) across samples. The sequence of switching is programmable
(TX_SEQ_REG). In single channel mode, the channel to be used can be selected through SEL_TX_CH. Each
illumination channel has separate current programmability, listed in Table 3. This mode can be combined with
continuous mode, monoshot mode, non-HDR mode, or auto HDR mode.
Table 4. Multi LED Configuration Registers
REGISTER
EN_TX_SWITCH
ADDRESS
2Ah[0]
DESCRIPTION
Enable switching between Illumination channels TX0, TX1, TX2.
SEL_TX_CH
2Ah[2:1]
Selects the ILLUM channels when switching is disabled.
TX_SEQ_REG
2Ah[14:3]
Stores the sequence of ILLUM channel switching in this register.
For example, register value: 2-1-0-2-1-0. The sequence will be 0-1-2-0-1-2
Separate calibration registers are provided for each illumination channel to support different currents for each
channel in the same system.
7.3.2 AFE
The diode current is capacitively coupled to the AFE as shown in Figure 21. The AFE processes the input signal
and produces digitized in-phase and quadrature-phase components of the input signal. The AFE has a full-scale
current of 200 nA peak-to-peak and supports a photodiode capacitance up to 6 pF.
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Figure 21. AFE, Photodiode Interface
The signal-to-noise ratio (SNR) for a given signal current and sample rate can be calculated from the following
equation.
SNR =
I SIG _ AFE
I noise ´ BW
=
I SIG _ AFE
94.8 pA / (NUM _ AVG _ SUB _ FRAMES + 1)
where
•
•
•
sphase
Isig_afe = signal current entering the AFE
Inoise = Input referred current noise floor of the AFE
= 1.5 pA/√Hz with IAMB_MAX=20 µA and CPD= 2pF (Figure 2)
BW = Signal measurement bandwidth
(4)
1
=
radians
SNR
where
•
•
σphase= Phase standard deviation in radians
SNR is calculated from Equation 4
sdis tance =
c / (2fMOD )
2p
(5)
1
´
meters
SNR
where
•
•
•
σdistance= Distance standard deviation in meters
c = Speed of light
fMOD = 10 MHz, modulation frequency
(6)
For example, with an AFE signal current of 20 nA peak-to-peak (–20 dBFS), frame rate of 125 Hz
(NUM_AVG_SUB_FRAMES = 31), SNR = 1193 = 61.5 dB. Depth noise standard deviation for this scenario is
σdistance = 15 m / (2π) / 1193 = 2 mm.
7.3.3 Ambient Cancellation
The ambient cancellation circuit provides the dc and low-frequency diode current while biasing the diode at 1 V.
Figure 22 shows the frequency response of the ambient cancellation circuit. A diode current with frequency
below fc2 has second-order rejection. The corner frequency fc2 is designed to be at 50 kHz for IAMB_MAX_SEL =
0 (20 µA ambient current support). Below frequency fc1 (approximately at 10 Hz), attenuation becomes first-order.
So for a frequency of 1 kHz, the rejection would be (50 kHz / 1 kHz) × 2 = 2500 = 68 dB.
18
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Figure 22. Ambient Cancellation Circuit Frequency Response
The maximum ambient current supported is programmable from 10 μA to 200 µA, listed in Table 5. Noise
contribution from the ambient cancellation block increases with increase in ambient current support, shown in
Figure 2. For low-ambient systems, the lower value of maximum ambient support should be used to reduce the
noise contribution from the ambient cancellation. Ambient current is also converted to digital using an ADC
(AMB_DATA) at the output of the ambient cancellation block. Ambient ADC resolution is 0.104 µA/LSB with 20µA support. Ambient ADC resolution scales linearly with maximum ambient current supported. Ambient current
can be calculated from the AMB_DATA using Equation 7.
AMB _ DATA - AMB _ CALIB
´ IAMB _ MAX
IAMB =
192
where
•
•
IAMB_MAX= Maximum ambient current supported. Listed in Table 5
AMB_CALIB = ambient ADC output in the dark. Typical value is 64, could vary by few codes from device to
device.
(7)
Table 5. Ambient Cancellation Register Settings
PARAMETER
IAMB_MAX_SEL
ADDRESS
72h[7:4]
DESCRIPTION
Selects the value of maximum ambient current support
0: 20 µA | 5: 10 µA | 10: 33 µA | 11: 50 µA | 12: 100 µA | 14: 200 μA | Other values:
Not valid
7.3.4 Oscillator
The system clock is generated using an on-chip oscillator with high stability across temperature. This oscillator is
trimmed to a nominal frequency of 80 MHz within ±3%. For accurate distance conversion, this frequency is
trimmed digitally to 10-bit accuracy. Additionally, the device can accept an external reference clock and correct
for the on-chip oscillator variations for continuous background frequency calibration.
7.3.5 CLKGEN
CLKGEN takes the clock from the oscillator and generates the clocks required for various blocks. CLKGEN
generates a 10-MHz clock for the illumination driver. The phase of the illumination CLK can be changed in 16
steps. This feature is useful for phase nonlinearity correction resulting from square wave modulation. Phase
nonlinearity from ideal square wave demodulation is approximately ±4 degrees. OPT3101 has a filter to reject the
higher-order harmonics of a square wave and the resulting nonlinearity is small, ±0.5 degrees. For de-aliasing,
CLKGEN also generates an additional frequency of 10 × (6 / 7) MHz or 10 × (6 / 5) MHz for the illumination
clock.
Table 6. Register Settings to Change the Phase of Illumination
PARAMETER
SHIFT_ILLUM_PHASE
ADDRESS
71h[6:3]
DESCRIPTION
Mode to generate different Illumination clock phases.
Illumination clock phase = SHIFT_ILLUM_PHASE × 22.5 degrees
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7.3.6 Illumination Driver
Figure 23 shows the illumination driver block diagram. The illumination driver supports three illumination
channels. The same current source is multiplexed onto three channels. Only one channel can be used at any
given time.
Figure 23. Illumination Driver Block Diagram
Illumination driver current can be programmed using a 5-bit DAC, listed in Table 7. Step size of the DAC can
also be scaled from 1.4 mA to 5.6 mA using ILLUM_SCALE. A dc bias-current option is also provided. DC bias is
useful if the system requires a very small switching illumination current. This dc bias can be programmed in the
range of 0.5 mA to 7.5 mA in steps of 0.5 mA using ILLUM_DC_CURR_DAC.
Table 7. Illumination Driver Register Settings
REGISTER
EN_LED_DRV
ADDRESS
79h[0]
DESCRIPTION
Enable the illumination driver
ILLUM_DAC_L_TX0
29h[4:0]
Illumination driver-current DAC register, ILLUM_DAC_L of TX0 channel. Illumination
current = ILLUM_DAC_L_TX0 × DAC step
ILLUM_DAC_H_TX0
29h[9:5]
Illumination driver current DAC register, ILLUM_DAC_H of TX0 channel. Illumination
current = ILLUM_DAC_L_TX0 × DAC step
ILLUM_SCALE_L_TX0
2Bh[18:16]
Scale the illumination current DAC step size for ILLUM_DAC_L_TX0
0: 5.6 mA | 1: 4.2 mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid.
ILLUM_SCALE_H_TX0
2Bh[21:19]
Scale the illumination current DAC step size for ILLUM_DAC_H_TX0
0: 5.6 mA | 1: 4.2 mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid.
ILLUM_DC_CURR_DAC
79h[11:8]
Program the illumination driver DC bias current
DC current = 0.5 mA × ILLUM_DC_CURR_DAC
7.3.7 Depth Engine
The depth engine computes the phase and amplitude from in-phase and quadrature-phase components of the
received signal. The depth engine also performs the following calibrations:
• Phase offset
• Phase correction with temperature
• Crosstalk
• Frequency
• Square wave nonlinearity
• Phase correction with ambient
For a detailed calibration procedure, see OPT3101 Distance Sensor System Calibration
Table 8. Phase Offset Correction Registers
PARAMETER
EN_PHASE_CORR
ADDRESS
43h [0]
DESCRIPTION
Enables phase offset correction
PHASE_OFFSET_HDR0_TX0
42h[15:0]
Phase offset for TX0 illumination channel with current of ILLUM_DAC_L_TX0
PHASE_OFFSET_HDR1_TX0
51h[15:0]
Phase offset for TX0 illumination channel with current of ILLUM_DAC_H_TX0
20
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Table 8. Phase Offset Correction Registers (continued)
PARAMETER
ADDRESS
DESCRIPTION
PHASE_OFFSET_HDR0_TX1
52h[15:0]
Phase offset for TX1 illumination channel with current of ILLUM_DAC_L_TX1
PHASE_OFFSET_HDR1_TX1
53h[15:0]
Phase offset for TX1 illumination channel with current of ILLUM_DAC_H_TX1
PHASE_OFFSET_HDR0_TX2
54h[15:0]
Phase offset for TX2 illumination channel with current of ILLUM_DAC_L_TX2
PHASE_OFFSET_HDR1_TX2
55h[15:0]
Phase offset for TX2 illumination channel with current of ILLUM_DAC_H_TX2
Table 9. Phase Temperature Coefficient Registers
PARAMETER
EN_TEMP_CORR
ADDRESS
43h[1]
DESCRIPTION
Enable temperature correction
SCALE_PHASE_TEMP_COEFF
43h[8:6]
Adjust scale factor for temperature coefficient
TMAIN_CALIB_HDR0_TX0
47h[11:0]
Calibration temperature for sensor offset for TX0 illumination channel with
current of ILLUM_DAC_L_TX0
TEMP_COEFF_MAIN_HDR0_TX0
45h[11:0]
Phase temperature coefficient for sensor temperature for TX0 illumination
channel with current of ILLUM_DAC_L_TX0
TMAIN_CALIB_HDR1_TX0
48h[11:0]
Calibration temperature for sensor offset for TX0 illumination channel with
current of ILLUM_DAC_H_TX0
TEMP_COEFF_MAIN_HDR1_TX0
2Dh[11:0]
Phase temperature coefficient for sensor temperature for TX0 illumination
channel with current of ILLUM_DAC_H_TX0
TMAIN_CALIB_HDR0_TX1
49h[11:0]
Calibration temperature for sensor offset for TX1 illumination channel with
current of ILLUM_DAC_L_TX1
TEMP_COEFF_MAIN_HDR0_TX1
2Dh[23:12]
Phase temperature coefficient for sensor temperature for TX1 illumination
channel with current of ILLUM_DAC_L_TX1
TMAIN_CALIB_HDR1_TX1
41h[23:12]
Calibration temperature for sensor offset for TX1 illumination channel with
current of ILLUM_DAC_H_TX1
TEMP_COEFF_MAIN_HDR1_TX1
2Fh[23:16],
30h[23:20]
Phase temperature coefficient for sensor temperature for TX1 illumination
channel with current of ILLUM_DAC_H_TX1
3Fh[11:0]
Calibration temperature for sensor offset for TX2 illumination channel with
current of ILLUM_DAC_L_TX2
TEMP_COEFF_MAIN_HDR0_TX2
31h[23:16],
32h[23:20]
Phase temperature coefficient for sensor temperature for TX2 illumination
channel with current of ILLUM_DAC_L_TX2
TMAIN_CALIB_HDR1_TX2
45h[23:12]
Calibration temperature for sensor offset for TX2 illumination channel with
current of ILLUM_DAC_H_TX2
TEMP_COEFF_MAIN_HDR1_TX2
33h[23:16],
34h[23:20]
Phase temperature coefficient for sensor temperature for TX2 illumination
channel with current of ILLUM_DAC_H_TX2
TMAIN_CALIB_HDR0_TX2
Table 10. Phase Temperature Coefficient Registers for External Temperature Sensor
PARAMETER
ADDRESS
DESCRIPTION
TILLUM_CALIB_HDR0_TX0
47h[23:12]
Calibration temperature of external temperature sensor
TEMP_COEFF_ILLUM_HDR0_TX0
46h[11:0]
Phase temperature coefficient for illumination using external temperature
sensor.
TILLUM_CALIB_HDR1_TX0
48h[23:12]
Calibration temperature of external temperature sensor
TEMP_COEFF_ILLUM_HDR1_TX0
51h[23:16],
52h[23:20]
Phase temperature coefficient for illumination using external temperature
sensor.
TILLUM_CALIB_HDR0_TX1
49h[23:12]
Calibration temperature of external temperature sensor
TEMP_COEFF_ILLUM_HDR0_TX1
53h[23:16],
54h[23:20]
Phase temperature coefficient for illumination using external temperature
sensor.
TILLUM_CALIB_HDR1_TX1
43h[23:12]
Calibration temperature of external temperature sensor
TEMP_COEFF_ILLUM_HDR1_TX1
55h[23:16],
56h[23:20]
Phase temperature coefficient for illumination using external temperature
sensor.
TILLUM_CALIB_HDR0_TX2
3Fh[23:12]
Calibration temperature of external temperature sensor
TEMP_COEFF_ILLUM_HDR0_TX2
57h[23:16],
58h[23:20]
Phase temperature coefficient for illumination using external temperature
sensor.
TILLUM_CALIB_HDR1_TX2
46h[23:12]
Calibration temperature of external temperature sensor
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Table 10. Phase Temperature Coefficient Registers for External Temperature Sensor (continued)
PARAMETER
ADDRESS
59h[23:16],
5Ah[23:20]
TEMP_COEFF_ILLUM_HDR1_TX2
DESCRIPTION
Phase temperature coefficient for illumination using external temperature
sensor.
Table 11. Ambient-Dependent Phase Correction Registers
REGISTER
ADDRESS
AMB_PHASE_CORR_PWL_X0
B8h[9:0]
AMB_PHASE_CORR_PWL_X1
B9h[19:10]
AMB_PHASE_CORR_PWL_X2
B9h[9:0]
DESCRIPTION
First knee point of PWL phase correction with ambient
Second knee point of PWL phase correction with ambient
Third knee point of PWL phase correction with ambient
AMB_PHASE_CORR_PWL_COEFF0
0Ch[23:16]
AMB_PHASE_CORR_PWL_COEFF1
B4h[7:0]
Slope of first segment for PWL phase correction with ambient
Slope of second segment for PWL phase correction with ambient
AMB_PHASE_CORR_PWL_COEFF2
B4h[15:8]
Slope of third segment for PWL phase correction with ambient
AMB_PHASE_CORR_PWL_COEFF3
B4h[23:16]
Slope of fourth segment for PWL phase correction with ambient
SCALE_AMB_PHASE_CORR_COEFF
B5h[2:0]
Scaling factor for ambient-based PWL phase correction.
Table 12. Internal Crosstalk Correction Registers
REGISTER
ADDRESS
INT_XTALK_CALIB
2Eh[4]
XTALK_FILT_TIME_CONST
DESCRIPTION
The device initializes the internal electrical crosstalk measurement upon
setting this bit.
Use the following sequence:
INT_XTALK_CALIB = 1
Delay (at least 5 × 2XTALK_FILT_TIME_CONST frames)
INT_XTALK_CALIB = 0
See OPT3101 Distance Sensor System Calibration.
2Eh[23:20]
Time constant for crosstalk filtering. Time constant τ = 2XTALK_FILT_TIME_CONST
frames. At least 5τ should be allowed for settling of crosstalk measurement.
USE_XTALK_FILT_INT
2Eh[5]
Select filter or direct sampling for internal crosstalk measurement.
0 – Direct sampling, 1 – Filter
USE_XTALK_REG_INT
2Eh[6]
Select register value or internally calibrated value for internal crosstalk
0 – Calibration value, 1 – Register value
IPHASE_XTALK_INT_REG
3D[15:0]
Register for in-phase component of internal crosstalk
QPHASE_XTALK_INT_REG
3E[15:0]
Register for quadrature-phase component of internal crosstalk
IPHASE_XTALK
3Bh[23:0]
Read-only register. In-phase component. Different values can be selected to
be read out with IQ_READ_DATA_SEL
QPHASE_XTALK
3Ch[23:0]
Read-only register. Quadrature-phase component. Different values can be
selected to be read out with IQ_READ_DATA_SEL
IQ_READ_DATA_SEL
2Eh[11:9]
Mux select for IPHASE_XTALK, QPHASE_XTALK
0 – Internal crosstalk | 1 – Illum crosstalk | 2 – Raw I, Q | 3 – 16-bit frame
counter
INT_XTALK_REG_SCALE
2E[16:14]
Scale factor for internal crosstalk register (IPHASE_XTALK_INT_REG,
QPHASE_XTALK_INT_REG). Scale = 2INT_XTALK_REG_SCALE
Table 13. Illumination Crosstalk Correction Registers
REGISTER
ADDRESS
DESCRIPTION
ILLUM_XTALK_CALIB
2Eh[12]
The device initializes the illumination crosstalk measurement upon setting this
bit. This measurement should be done with the photodiode masked such that
no modulated light is received.
Use following sequence:
ILLUM_XTALK_CALIB = 1
Delay (at least 5 × 2XTALK_FILT_TIME_CONST frames)
ILLUM_XTALK_CALIB = 0
See OPT3101 Distance Sensor System Calibration.
USE_XTALK_FILT_ILLUM
2Eh[7]
Select filter or direct sampling for illumination crosstalk measurement.
0 – Direct sampling, 1 – Filter
22
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Table 13. Illumination Crosstalk Correction Registers (continued)
REGISTER
ADDRESS
USE_XTALK_REG_ ILLUM
DESCRIPTION
Select register value or internally calibrated value for illumination crosstalk
correction.
0 – Calibration value, 1 – Register value
2Eh[8]
ILLUM_XTALK_REG_SCALE
2E[19-17]
Scale factor for Illumination crosstalk register
(IPHASE_XTALK_REG_HDR<i>_TX<j>,
QPHASE_XTALK_REG_HDR<i>_TX<j>, i = 0,1, j = 0,1,2). Scale =
2INT_XTALK_REG_SCALE
IPHASE_XTALK_REG_HDR0_TX0
2Fh[15:0]
Register for illumination crosstalk in-phase component for TX0 channel with
ILLUM_DAC_L_TX0 current
QPHASE_XTALK_REG_HDR0_TX0
30h[15:0]
Register for illumination crosstalk quadrature-phase component for TX0
channel with ILLUM_DAC_L_TX0 current
IPHASE_XTALK_REG_HDR1_TX0
31h[15:0]
Register for illumination crosstalk in-phase component for TX0 channel with
ILLUM_DAC_H_TX0 current
QPHASE_XTALK_REG_HDR1_TX0
32h[15:0]
Register for illumination crosstalk quadrature-phase component for TX0
channel with ILLUM_DAC_H_TX0 current
IPHASE_XTALK_REG_HDR0_TX1
33h[15:0]
Register for illumination crosstalk in-phase component for TX1 channel with
ILLUM_DAC_L_TX1 current
QPHASE_XTALK_REG_HDR0_TX1
34h[15:0]
Register for illumination crosstalk in quadrature-phase component for TX1
channel with ILLUM_DAC_L_TX1 current
IPHASE_XTALK_REG_HDR1_TX1
35h[15:0]
Register for illumination crosstalk in-phase component for TX1 channel with
ILLUM_DAC_H_TX1 current
QPHASE_XTALK_REG_HDR1_TX1
36h[15:0]
Register for illumination crosstalk quadrature-phase component for TX1
channel with ILLUM_DAC_H_TX1 current
IPHASE_XTALK_REG_HDR0_TX2
37h[15:0]
Register for illumination crosstalk in-phase component for TX2 channel with
ILLUM_DAC_L_TX2 current
QPHASE_XTALK_REG_HDR0_TX2
38h[15:0]
Register for illumination crosstalk quadrature-phase component for TX2
channel with ILLUM_DAC_L_TX2 current
IPHASE_XTALK_REG_HDR1_TX2
39h[15:0]
Register for illumination crosstalk in-phase component for TX2 channel with
ILLUM_DAC_H_TX2 current
QPHASE_XTALK_REG_HDR1_TX2
3Ah[15:0]
Register for illumination crosstalk quadrature-phase component for TX2
channel with ILLUM_DAC_H_TX2 current
Table 14. Frequency Correction Registers
REGISTER
ADDRESS
DESCRIPTION
EN_AUTO_FREQ_COUNT
0Fh[21]
Determines which value to be used for frequency correction
0 – Trimmed value
1 – Measured value from frequency calibration
EN_FLOOP
0Fh[22]
Enables the frequency calibration block.
EN_FREQ_CORR
0Fh[23]
Enables frequency correction for the phase output
REF_COUNT_LIMIT
0Fh[14:0]
This sets the limit for reference-clock count.
Write this register with value = (40 × 106 / 2SYS_CLK_DIVIDER) / fEXT
SYS_CLK_DIVIDER
0Fh[20:17]
Programs system clock divider for frequency calibration. This should be
adjusted to get it closer to the external reference frequency. The default is 10,
system clock = 40 MHz / 210 = 39.0625 kHz to bring close to 32.768 kHz.
EN_CONT_FCALIB
10h[15]
Enables continuous frequency calibration.
0 – Frequency is measured only when START_FREQ_CALIB = 1
1 – Frequency is continuously measured.
10h[14:0]
Read the register which holds the value of frequency calibration.
FREQ_COUNT_READ_REG
START_FREQ_CALIB
0Fh[16]
Starts the frequency calibration.
Table 15. Phase Nonlinearity Correction Registers
REGISTER
EN_NL_CORR
ADDRESS
4Ah[0]
DESCRIPTION
Enables square wave non-linearity correction
SCALE_NL_CORR_COEFF
4Ah[19:18]
Scaling factor for nonlinearity correction coefficients (A*_COEFF_HDR*_TX*)
A0_COEFF_HDR0_TX0
4Ah[17:2]
0th-order coefficient for square wave nonlinearity correction
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Table 15. Phase Nonlinearity Correction Registers (continued)
REGISTER
ADDRESS
DESCRIPTION
A1_COEFF_HDR0_TX0
4Bh[15:0]
1st-order coefficient for square wave nonlinearity correction
A2_COEFF_HDR0_TX0
4Ch[15:0]
2nd-order coefficient for square wave nonlinearity correction
A3_COEFF_HDR0_TX0
4D[15:0]
3rd-order coefficient for square wave nonlinearity correction
A4_COEFF_HDR0_TX0
4Eh[15:0]
4th-order coefficient for square wave nonlinearity correction
A0_COEFF_HDR1_TX0
A2[15:0]
0th-order coefficient for square wave nonlinearity correction
A1_COEFF_HDR1_TX0
A7[15:0]
1st-order coefficient for square wave nonlinearity correction
A2_COEFF_HDR1_TX0
AC[15:0]
2nd-order coefficient for square wave nonlinearity correction
A3_COEFF_HDR1_TX0
B1[15:0]
3rd-order coefficient for square wave nonlinearity correction
A4_COEFF_HDR1_TX0
AA[23:16],
AB[23:16]
4th-order coefficient for square wave nonlinearity correction
7.3.8 Output Data
Phase and amplitude information is stored in registers which can be read out using the I2C interface. The device
gives data ready after computation of the depth information on the general purpose I/O (GP1 or GP2) which can
be used trigger the host to read the data from the device. Distance can be calculated from the phase using
Equation 8. A single code of PHASE_OUT is 228.7µm.
PHASE _ OUT
c
Dis tance =
´
meters
16
2fMOD
2
where
•
•
c = Speed of light
fMOD = 10 MHz, modulation frequency
(8)
Along with phase and amplitude of the signal, ambient ADC output and temperature sensor output are also
stored in the registers. All the output data is stored in contiguous registers 8, 9, and 10.
AMB_OVL_FLAG
MOD_FREQ
FRAME_STATUS
REG 9
DEALIAS_BIN[3:0]
REG 10
24
18
TMAIN[11:4]
17
16
PHASE_OVER_FLOW
REG 8
19
HDR_MODE
20
FRAME_COUNT 1
21
TX_CHANNEL
22
SIG_O VL_FL AG
23
PHASE _OVER FLOW_ F2
REGIST
ER
FRAME_COUNT0
Table 16. Output Data Registers
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PHASE_OUT [15:8]
PHASE_OUT [7:0]
AMP_OUT[15:8]
AMP_OUT[7:0]
TMAIN[3:0]
AMB_DATA[9:6]
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1
0
FRAME_
COUNT
2
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Table 17. Output Data Registers Description
FIELD
BIT
PHASE_OUT
DESCRIPTION
08h[15:0]
PHASE_OVERFLOW
08h[16]
AMP_OUT
09h[15:0]
Final calibrated phase.
Phase overflow during frequency correction.
Amplitude of the signal.
SIG_OVL_FLAG
09h[18]
Overload flag to indicate signal saturation
AMB_OVL_FLAG
08h[22]
Overload flag to indicate ambient saturation
HDR_MODE
08h[17]
Indicates the illumination driver DAC current used. 0: ILLUM_DAC_L | 1:
ILLUM_DAC_H
TX_CHANNEL
08h[19:18]
Indicates which Illumination channel of TX0/TX1/TX2 is used.
FRAME_STATUS
08h[20]
0 = Invalid frame | 1= Valid frame. Frame can be invalid during crosstalk
measurement.
MOD_FREQ
08h[21]
Indicates the frequency used. 0: 10 MHz | 1: De-alias frequency (10 MHz × 6 / 7 or 10
MHz × 6 / 5)
FRAME_COUNT0
08h[23]
Frame counter LSB bit [0]
FRAME_COUNT1
09h[17:16]
FRAME_COUNT2
0Ah[1:0]
DEALIAS_BIN
09h[23:20]
PHASE_OVER_FLOW_F2
Frame counter bits [2:1]
Frame counter bits [4:3]. Frame counter = FRAME_COUNT2 × 8 + FRAME_COUNT1
× 2 + FRAME_COUNT0
Distance bin in de-alias mode
09h[19]
Phase overflow of second modulation frequency during frequency correction.
AMB_DATA
0Ah[11:2]
Ambient ADC output. Indicates the ambient light. In no ambient light condition
AMB_DATA is 64 typically.
TMAIN
0Ah[23:12]
Temperature sensor output
Temperature (°C) = (TMAIN / 8) – 256
7.3.9 General Purpose I/O
There are two general purpose I/Os which can be used to bring out various digital signals like DATA_RDY,
FRAME_VD, ILLUM CLK, ILLUM_EN. GP2 can also be used as an input pin for external clock reference for
device on-chip oscillator frequency calibration.
Table 18. GPIO Configuration Registers
REGISTER
ADDRESS
DESCRIPTION
GPO1_MUX_SEL
78h[8:6]
Select signal for the GP1 output multiplexer.
0: DVSS | 2: DIG_GPO_0 | 3: DIG_GPO_1 | 7: ILLUM_CLK | Other values: Not valid
GPIO1_OBUF_EN
78h[12]
Enable output buffer of GP1 pin
GPIO2_IBUF_EN
78h[16]
Enable input buffer of GP2 pin. External reference clock should be connected to this
pin for frequency calibration.
GPIO2_OBUF_EN
78h[15]
Enable output buffer of GP2 pin
GPO2_MUX_SEL
78h[11:9]
Select signal for the GP2 output multiplexer.
0: DVSS | 2: DIG_GPO_0 | 3: DIG_GPO_1 | 7: ILLUM_EN_TX0 | Other values: Not
valid
0Bh[3:0]
Mux selection bits for digital signal DIG_GPO_0, which can be brought out on GP1 or
GP2
0: FRAME_VD | 1: SUB_VD | 4: SEQUENCER_INTERRUPT
8: COMP_STATUS | 9: DATA_RDY | 10: FRAME_COUNTER_LSB | Other values:
Not valid
0Bh[7:4]
Mux selection bits for digital signal DIG_GPO_1 which can be brought out on GP1 or
GP2
0: FRAME_VD | 1: SUB-VD | 4: SEQUENCER_INTERRUPT
8: COMP_STATUS | 9: DATA_RDY | 10: FRAME_COUNTER_LSB | Other values:
Not valid
DIG_GPO_SEL0
DIG_GPO_SEL1
7.3.10 Temperature Sensor
The device has an internal temperature sensor to monitor the temperature of the sensor core. The temperature
sensor has a range of –25°C to 125°C. The output of this temperature sensor is accessible from register TMAIN.
It can be used for phase temperature compensation.
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7.3.11 On-Chip Regulator
AFE has an internal regulator for generating the 1.8-V supplies (AVDD, DVDD) from the AVDD3 supply. In this
mode, only one 3.3-V supply is sufficient for the device operation. Because the power is drawn from the 3.3-V
supply for AVDD, DVDD, power consumption is higher. The REG_MODE pin controls the regulator. Connect this
pin to IOVDD to enable regulator mode. In non-regulator mode, the REG_MODE pin should be connected to
IOVSS. Figure 177 show the block diagram of the regulator. A decoupling capacitor of 100 nF minimum should
be connected at the pins AVDD and DVDD. The decoupling capacitor on AVDD should be connected to AVSS,
and the decoupling capacitor on DVDD should be connected to IOVSS.
7.3.12 Sequencer
AFE has an on-chip sequencer which can be used to perform various operations. The sequencer commands are
tabulated in Table 19. Each instruction is 12 bits with the first four MSB bits as the opcode and next eight bit as
operand. The sequencer can perform a comparison of amplitude or phase with register thresholds
COMPARE_REG1, COMPARE_REG2 and generate a signal COMP_STATUS, which can be observed on GP1
with the DIG_GPO_SEL0 = 8 and gpo1_mux_sel = 2 settings. The comparison input type can be selected using
COMP_IN_SEL. The sequencer executes one command per sample. The sequencer interrupt to execute a
command can be positioned either at the beginning of the sample or at the end of the sample after data is ready
and before the next sample starts. The sequencer interrupt can be programmed with the TG_SEQ_INT_START,
TG_SEQ_INT_END,
TG_SEQ_INT_MASK_START,
and
TG_SEQ_INT_MASK_END
registers.
TG_SEQ_INT_START and TG_SEQ_INT_END define the position of the interrupt pulse within a sub-frame.
TG_SEQ_INT_MASK_START and TG_SEQ_INT_MASK_END define the sub-frame during which the pulse is
enabled.
Some of the use cases of the sequencer are:
• Switching of transmitter channels
• Generating an interrupt based on a phase or amplitude comparison with defined thresholds
• Generating an interrupt based on a phase or amplitude comparison with hysteresis
• Extending the dynamic range using four illumination driver currents
• Performing a de-alias operation to extend the distance range from 15 m to 75 m.
Table 19. Sequencer Commands
OPCODE
FUNCTION
DESCRIPTION
0000
NOP
The operand indicates the number of cycles for which NOP should be executed. 0 means 1
cycle, 1 means 2 cycle, and so on. For example 0000-0000 1111 indicates that for the next
16 cycles the sequencer does not do anything.
WRITE
This command writes the operand to the STATUS_OUT register. For example 00010110 0110 makes the value on the STATUS_OUT port 0110 01100. The STATUS_OUT
port is mapped to certain key registers listed in Table 20. STATUS_OUT values override the
register values only if EN_PROCESSOR_VALUES = 1.
GOTO
Program counter (PC) goes to the line indicated by the operand. This command is useful for
looping. The next command is executed on the next sequencer interrupt. For example,
0010-0000 0000 sets the PC to the first line of the program memory so that the instructions
are executed in a loop.
0011
DGOTO
In this command, the PC goes to the line indicated by the operand only if STATUS_IN_REG
bit is 1. If not, the PC stays in the same command until the STATUS_IN_REG register value
becomes 1. The next command is executed on the next frame VD. For example, 00110000 0000 suspends the program until the STATUS_IN_REG bit is set to 1. Once it is set,
the loop is restarted.
0100
DrGOTO
In this instruction, the PC goes to the line indicated by operand without any delay. This
executes next instruction as well. The next command is executed on the same frame VD.
0101
COMP0
In this command, the CPU compares COMP_IN and COMPARE_REG1. If COMP_IN ≤
COMPARE_REG1, the program counter stays where it is and the COMP_STATUS port is
0. If the comparison fails, the program counter moves to the line indicated by the operand,
and COMP_STATUS becomes 1.
0110
COMP0_INV
0111
COMP_WINDOW
0001
0010
26
Similar to COMP but the comparison used is: COMP_IN ≥ COMPARE_REG2
In this command, the PC stays at the same command forever. If (COMP_IN ≥
COMPARE_REG1) and (COMP_IN ≤ COMPARE_REG2) then COMP_STATUS becomes 1
else COMP_STATUS = 0.
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Table 19. Sequencer Commands (continued)
OPCODE
FUNCTION
DESCRIPTION
1000
COMP2
If (COMP_IN ≥ COMPARE_REG1) and (COMP_IN ≤ COMPARE_REG2) then
COMP_STATUS becomes 1 else COMP_STATUS = 0. If the condition is TRUE the
program counter stays at the same command else moves to the line indicated by the
operand.
1001
COMP3
Similar to COMP2. The difference is that regardless of the comparison result, the program
counter moves to the instruction pointed to by the operand. If comparison is met,
COMP_STATUS is set to 1, else to 0.
1010
COMP_HYST
In this command, the PC stays at the same command forever. There is hysteresis in the
comparison. If (COMP_IN ≤ COMPARE_REG1) then COMP_STATUS = 0, elsif (COMP_IN
≥ COMPARE_REG2) then COMP_STATUS = 1.
1011
COMP1
In this command, the CPU compares COMP_IN and COMPARE_REG1. If COMP_IN ≤
COMPARE_REG1, the program counter stays where it is and the COMP_STATUS port is
0. If the comparison fails the program counter moves to the line indicated by the operand
and COMP_STATUS becomes 1. Executes this command and moves to next command at
the same interrupt.
1100
COMP1_INV
Similar to COMP1 but the comparison used is COMP_IN ≥ COMPARE_REG2. Sequencer
executes the command and moves to next command at the same interrupt.
1101–1111
Not valid
Table 20. Sequencer STATUS_OUT Register Mapping
STATUS_OUT
REGISTER MAPPING
[0]
INT_XTALK_CALIB
[1]
EN_DEALIAS_MEAS
[2]
START_FREQ_CALIB
[4:3]
SEL_TX_CH
[5]
SEL_HDR_MODE
[7:6]
Invalid
Table 21. Sequencer Registers
REGISTER
ADDRESS
DESCRIPTION
COMP_IN_SEL
13h[2:0]
Select the value used for comp_in.
0: AMP_OUT | 1: DEALIAS_BIN | 2: Phase output in de-alias mode | 3:
PHASE_OUT
COMPARE_REG1
13h[18:3]
Sequencer comparison threshold1
COMPARE_REG2
14h[15:0]
Sequencer comparison threshold2
EN_SEQUENCER
14h[16]
Enable the sequencer.
EN_PROCESSOR_VALU
ES
14h[17]
Uses processor values instead of register values.
STATUS_IN_REG
14h[18]
The register is used to control the program flow in CPU
DIS_INTERRUPT
14h[19]
Disables the interrupt which triggers the sequencer.
COMMAND0 to
COMMAND19
15h[11:0] to 1Eh[23:12]
Sequencer command registers. A total of 20 command registers are available.
7.3.12.1 Interrupt Output
The sequencer supports various interrupt output modes using the comparison commands listed in Table 19. The
register settings to use the sequencer for generating interrupt output using COMP_WINDOW are listed in
Table 22, and the corresponding interrupt output is shown in Figure 24. To use a comparison with hysteresis
(COMP_HYST) use COMMAND0 = 0xA00 and the rest of the settings remain the same as when using
COMP_WINDOW.
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Figure 24. Interrupt Output Using Different Comparison Commands
Table 22. Register Settings to Use Sequencer for Generating Interrupt Output
PARAMETER
VALUE
DESCRIPTION
Sequencer Interrupt Signal
TG_SEQ_INT_START
TG_SEQ_INT_END
9850
9858
TG_SEQ_INT_MASK_START
NUM_AVG_SUB_FR
AMES
TG_SEQ_INT_MASK_END
NUM_AVG_SUB_FR
AMES
Set the sequencer interrupt at the end of the last averaged subframe after data ready is available
Sequencer Commands
COMMAND0
0x700
COMP_WINDOW.
COMP_STATUS = 1 when distance is between the lower
(COMPARE_REG1) and upper (COMPARE_REG2) limits else
COMP_STATUS = 0
Get COMP_STATUS on GP1
GPIO1_OBUF_EN
1
Enable GP1 output buffer.
GPO1_MUX_SEL
3
Select DIG_GPO_1 on GP1
GPO_SEL1
8
Select COMP_STATUS on DIG_GPO_1
1
Select amplitude PHASE_OUT for comparison input COMP_IN
Comparison Settings
COMP_IN_SEL
COMPARE_REG1
PHASE1
Phase corresponding to a lower distance (phase) threshold
COMPARE_REG2
PHASE2
Phase corresponding to an upper distance (phase) threshold
Sequencer Enable
EN_SEQUENCER
1
Enable the sequencer.
Sequencer enable should be only be changed while TG_EN = 0.
Before changing this register disable TG (TG_EN = 0), modify this
register and then enable TG (TG_EN = 1).
EN_PROCESSOR_VALUES
1
Enable processor values to control the STATUS_OUT register bits.
7.3.12.2 Super-HDR Mode Using Sequencer
The on-chip sequencer can be used to extend the dynamic range using four illumination currents. Figure 25
shows the state diagram of the super-HDR mode implemented using the sequencer. For this example, the
illumination driver currents should be programmed in the following order: IILLUM_H_TX1 > IILLUM_L_TX1 > IILLUM_H_TX0 >
IILLUM_L_TX0.Table 23 lists the register settings to operate the device in super HDR mode using the sequencer.
HDR_THR_LOW should be determined by the minimum of the two adaptive HDR settings listed below.
• HDR_THR_HIGH × ILLUM_DAC_L_TX0 / ILLUM_DAC_H_TX0
• HDR_THR_HIGH × ILLUM_DAC_L_TX1 / ILLUM_DAC_H_TX1
28
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Figure 25. Super-HDR Mode Using Sequencer: State Diagram
Table 23. Register Settings to Use Sequencer for Super HDR Mode
PARAMETER
VALUE
DESCRIPTION
Sequencer Interrupt Signal
TG_SEQ_INT_START
TG_SEQ_INT_END
9850
9858
TG_SEQ_INT_MASK_START
NUM_AVG_SUB_FR
AMES
TG_SEQ_INT_MASK_END
NUM_AVG_SUB_FR
AMES
Set the sequencer interrupt at the end of the last averaged subframe after data ready is available
Sequencer Commands
COMMAND0
0x108
Set illumination to channel TX1
COMMAND1
0xB02
COMP1 command.
If COMP_IN > COMPARE_REG1, move to COMMAND2.
COMMAND2
0x100
Set illumination to channel TX0
COMMAND3
0xC00
COMP1_INV command.
If COMP_IN < COMPARE_REG2, move to COMMAND0.
Comparison Settings
COMP_IN_SEL
0
Select amplitude AMP_OUT for COMP_IN
COMPARE_REG1
HDR_THR_HIGH +
500
Should be greater than the hdr High threshold: HDR_THR_HIGH
COMPARE_REG2
HDR_THR_LOW 500
Should be less than the hdr low threshold HDR_THR_LOW.
Sequencer Enable
EN_SEQUENCER
1
Enable the sequencer.
Sequencer enable should be only be changed while TG_EN = 0.
Before changing this register, disable TG (TG_EN = 0), modify this
register, and then enable TG (TG_EN = 1).
EN_PROCESSOR_VALUES
1
Enable processor values to control the STATUS_OUT register bits.
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7.4 Programming
The OPT3101 device supports the I2C interface for register read and write access. The device also has an I2C
host which can be used to interface with an external temperature sensor or external EEPROM.
7.4.1 I2C Slave
The I2C slave interface can be accessed with the SDA_S and SLC_S device pins. The I2C interface supports bus
speeds up to 400 kHz. The slave address for this device is 1011A2A1A0. Using the A0, A1, and A2 pins, the
address can be configured. By default A0, A1 and A2 are pulled to the AVDD supply and the default address is
1011 111. To change the address, connect these pins to either the AVDD or AVSS supply. The register access
can be single R/W or continuous R/W with auto-increment of register address.
Table 24. I2C Slave Configuration Registers
FIELD
I2C_CONT_RW
BIT
DESCRIPTION
00h[6]
Enable continuous read/write of registers using device I2C slave
The individual registers are 24-bit length in this device. However, the register read/write is in chunks of eight bits.
After every 8-bit transfer, the slave expects an acknowledgement from the master in the case of read or gives out
an acknowledgement in the case of write. Figure 26 shows the I2C timing for register write operation.
Figure 26. I2C Register Write Example
For example, to write 0x654321 to any register, the data should be split as three bytes and ordered as follows,
0x21, 0x43, 0x65. The same ordering is true for read mode. The first byte of data received corresponds to [7:0],
followed by [15:8] and then followed by [23:16]. Figure 27 shows the different read/write modes.
Figure 27. I2C Slave Interface R/W Modes
7.4.2 I2C Master
The OPT3101 device also has an I2C master, which is used to read the calibration and configuration registers
from an external memory with the I2C interface (EEPROM with I2C address of 1010 000) during power up. It can
also read temperature from an external temperature sensor with the I2C interface (default address of 1001 000).
Table 25 lists the register settings to configure the I2C Host.
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Table 25. I2C Master Register Settings
PARAMETER
BIT
DESCRIPTION
TSENS_SLAVE0
02h[6:0]
I2C slave address.
In multi-channel illumination operation, the temperature-sensor slave address is
selected based on the channel being used for reading the external temperature value
(TX0: TSENS_SLAVE0, TX1: TSENS_SLAVE1, TX2: TSENS_SLAVE2)
I2C_HOST_EN
01h[19]
Enable the I2C host
FRAME_VD_TRIG
01h[17]
Trigger I2C host operation every frame VD
I2C_TRIG_REG
01h[18]
Manual trigger the I2C host by writing to this register
I2C_NUM_TRAN
03h[17]
0: 1 transaction | 1: 2 transactions
I2C_RW
01h[21:20]
0: Write | 1: Read
LSB: First transaction
MSB: Second transaction
I2C_NUM_BYTES_TRAN1
07h[17:16]
0: 1 byte | 1: 2 bytes
I2C_NUM_BYTES_TRAN2
05h[23:22]
0: 1 byte | 1: 2 bytes
I2C_WRITE_DATA1
03h[16:9]
First byte of I2C write transaction
8-bit register address
I2C_WRITE_DATA2
07h[7:0]
Second byte of I2C write transaction
8-bit register data to be written
07h[19:18]
Selects the byte of read data.
0: 7:0 | 1: 15:8 | 2: 23:16 | 3: 31:24
I2C_SEL_READ_BYTES
I2C_READ_DATA
I2C host read data can be accessed through this register.
03h[7:0]
7.4.2.1 External Temperature Sensor
The temperature sensor address can be configured through internal registers (TSENS_SLAVE0,
TSENS_SLAVE1, TSENS_SLAVE2) . This sensor can be used for calibrating the system parameters with
temperature changes. An external temperature sensor is required if an external illumination driver is used.
Typically the on-die temperature sensor is sufficient if the internal illumination driver is used. The temperature
readings are refreshed every frame. The device supports up to three temperature sensors to associate with three
illumination channels. A single- or two-byte read operation is performed on each of the temperature sensors to
read the corresponding temperature. TI's TMP102 device, 12-bit temperature sensor is suggested if accurate
temperature correction with smaller jumps at the temperature code changes is required. The TMP103 8-bit
temperature sensor can be used if the temperature-correction accuracy requirement is less. For temperature
calibration of phase, the value read from the temperature sensor is assumed to be linear with the actual
temperature. Register settings to configure the external temperature sensor read using the I2C host are listed in
Table 26.
Table 26. Register Settings to Enable External Temperature Readout Using I2C
master
VALUE for
TMP102
VALUE for
TMP103A
0x48
0x70
EN_TILLUM_READ
1
1
Enable reading of the external temperature
sensor using the I2C master
TEMP_AVG_ILLUM
0
2
0: no averaging for TMP102, this is already
12-bit data. Further averaging not required.
2: 4 averages for TMP103A
I2C_HOST_EN
1
1
Enable I2C master
I2C_NUM_TRAN
0
0
One read transaction
I2C_RW
1
1
Read transaction
I2C_NUM_BYTES_TRAN1
1
0
1: Two-byte read for the TMP102 device
0: One-byte read for the TMP103A device
FRAME_VD_TRIG
1
1
Trigger temperature read for every frame
PARAMETER
TSENS_SLAVE0
DESCRIPTION
I2C slave address of the external
temperature sensor
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Table 26. Register Settings to Enable External Temperature Readout Using I2C
master (continued)
VALUE for
TMP102
VALUE for
TMP103A
CONFIG_TILLUM_MSB
8
0
Mode to select the correct 12 bits from the
read 16 bits in a two-byte read for the
TMP102 device
EN_TILLUM_12B
1
0
Enable the 12-bit mode to read 12-bit
temperature sensor data from an external
temperature sensor.
PARAMETER
DESCRIPTION
7.4.2.2 External EEPROM
The I2C host of the OPT3101 device automatically loads all of the registers (256 bytes) from an external 2KB
(256 × 8) EEPROM on device reset to configure the device. Of these 256 bytes, 64 bytes are register address,
and 192 bytes are data bytes. So from EEPROM, the device can auto load any of up to 64 device registers of 24
bits each (64 × 24). EEPROM data should be written in the following format. If only part of the memory is used,
the rest of the memory should be filled with all 0x00 or 0xFF.
Table 27. External EEPROM
Data Format
ADDRESS
DATA [7:0]
0
Register address i
1
Register data i[7:0]
2
Register data i[15:8]
3
Register data i[23:16]
4
Register address j
5
Register data j[7:0]
6
Register data j[15:8]
7
Register data j[23:16]
…
…
255
Register data k[23:16]
The EEPROM I2C slave address should be 0x50h. On device reset, I2C host initiates auto load from the external
EEPROM connected on the SDA_M, SCL_M bus. If there is an EEPROM device on the bus, this load operation
performs the 256-byte read operation. If there is no EEPROM on the host bus, the device terminates auto load
after the first transaction. During I2C host auto load, if an external host writes to the OPT3101 I2C slave, it
acknowledges but data transfer does not happen (write/read). Register address 0 of the OPT3101 device cannot
be loaded from the OPT3101 I2C host. Register address 0 is always reserved for I2C slave. By writing to register
bit 0[22] (FORCE_EN_SLAVE) of the OPT3101 device, I2C slave can take control of register access from host
auto load. If there are no pullup resistors connected on the I2C host bus SDA_M and SCL_M, then register bit
0[22] (FORCE_EN_SLAVE) = 1 should be written before any other I2C register writes, otherwise the device
register read/write does not happen. If the device is to be used in monoshot mode, I2C host power down disable
should be written first (DIS_GLB_PD_I2CHOST) before writing monoshot mode enable (MONOSHOT_MODE)
bit in the EEPROM.
7.4.2.3 External EEPROM Programming
To simplify the EEPROM programming in the end system, the OPT3101 device supports writing to EEPROM
through the device I2C slave. The device auto loads from EEPROM on reset. Before programming EEPROM, this
auto load might corrupt the registers. First erase the EEPROM and follow the flowchart shown in Figure 28. The
register settings to write to external EEPROM on the OPT3101 I2C host through the OPT3101 I2C slave are
listed in Table 28.
32
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Figure 28. EEPROM Programming Flow Chart
Table 28. Register Settings to Write to External EEPROM Using I2C Master
PARAMETER
VALUE
DESCRIPTION
TSENS_SLAVE0
50h
EEPROM I2C address. EEPROM with this I2C slave
address should be used.
I2C_HOST_EN
1
Enable device I2C host.
I2C_NUM_TRAN
0
Number of I2C master transactions = 1
I2C_RW
0
Write transaction
I2C_NUM_BYTES_TRAN1
1
2-byte transaction (register address, register data)
I2C_WRITE_DATA1
EEPROM register address
I2C_WRITE_DATA2
Data to be written
I2C_TRIG_REG
1→0
Trigger the I2C host write by writing 1 to this register
and make it 0
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7.5 Register Maps
7.5.1 Serial Interface Register Map
Table 29. Default Register Map
ADDRE
SS
(Hex)
D23
D22
D21
00h
MONO
SHOT_
BIT
FORCE
_EN_S
LAVE
FORCE
_EN_B
YPASS
0
0
D20
D19
0
I2C_RW
03h
TEMP_AVG_ILLU
M
EN_TIL
LUM_R
EAD
TEMP_AVG_MAI
N
0
04h
TILLUM
_UNSI
GNED
05h
I2C_NUM_BYTE
S_TRAN2
07h
08h
D10
D9
0
0
0
0
0
0
I2C_EN
I2C_TR
IG_RE
G
FRAME
_VD_T
RIG
0
0
0
0
0
0
0
0
0
0
0
0
MOD_F
REQ
1
0
0
I2C_SEL_READ_
BYTES
FRAME
_STAT
US
TX_CHANNEL
PHASE
_OVER
_FLOW
_F2
SIG_O
VL_FL
AG
0
0
0
0
D4
0
0
0
0
0
0
0
0
0
0
D3
0
D2
0
0
ADDR_SLAVE_EEPROM
D1
D0
0
SOFT
WARE_
RESET
SWAP_
READ_
DATA
EEPRO
M_REA
D_TRI
G
0
0
0
I2C_READ_DATA
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
I2C_WRITE_DATA2
0
PHASE_OUT
AMP_OUT
FRAME_COUNT
1
FRAME_COUNT
2
AMB_DATA
AMB_CALIB
EN_FR
EQ_CO
RR
0
D5
INIT_L
OAD_D
ONE
PHASE
_OVER
_FLOW
DIG_GPO_SEL2
AMB_PHASE_CORR_PWL_COEFF0
EN_TIL
LUM_1
2B
D6
I2C_C
ONT_R
W
TSENS_SLAVE0
I2C_WRITE_DATA1
I2C_NUM_BYTE
S_TRAN1
HDR_M
ODE
D7
TSENS_SLAVE1
I2C_NU
M_TRA
N
0
D8
TILLUM
0
0Bh
34
D11
TMAIN
0Ch
11h
D12
0
0
AMB_O
VL_FL
AG
D13
0
0Ah
10h
D14
0
0
09h
0Fh
D15
0
0
DEALIAS_BIN
0Dh
D16
TSENS_SLAVE2
CONFIG_TILLUM_MSB
FRAME
_COUN
T0
D17
0
01h
02h
D18
0
0
DIG_GPO_SEL1
AMB_XTALK_QPHASE_COEFF
DIG_GPO_SEL0
AMB_XTALK_IPHASE_COEFF
AMB_SAT_THR
0
0
0
EN_FL
OOP
EN_AU
TO_FR
EQ_CO
UNT
0
0
SYS_CLK_DIVIDER
0
0
START
_FREQ
_CALIB
0
0
0
0
0
0
REF_COUNT_LIMIT
0
AMPLITUDE_MIN_THR[15:8]
EN_CO
NT_FC
ALIB
AMPLITUDE_MIN_THR[7:0]
DIS_O
VL_GA
TING
FREQ_COUNT_READ_REG
FREQ_COUNT_REG
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Table 29. Default Register Map (continued)
ADDRE
SS
(Hex)
D23
D22
D21
D20
D19
13h
0
0
0
0
0
14h
0
0
0
0
DIS_IN
TERRU
PT
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
STATU
S_IN_R
EG
EN_PR
OCESS
OR_VA
LUES
EN_SE
QUEN
CER
COMMAND1
COMMAND0
COMMAND3
COMMAND2
17h
COMMAND5
COMMAND4
18h
COMMAND7
COMMAND6
19h
COMMAND9
COMMAND8
1Ah
COMMAND11
COMMAND10
1Bh
COMMAND13
COMMAND12
1Ch
COMMAND15
COMMAND14
1Dh
COMMAND17
COMMAND16
1Eh
COMMAND19
26h
0
0
0
2Bh
0
0
ILLUM_SCALE_H_TX0
ILLUM_SCALE_L_TX0
HDR_THR_HIGH
2Ch
0
0
ILLUM_SCALE_H_TX1
ILLUM_SCALE_L_TX1
HDR_THR_LOW
2Dh
ILLUM_XTALK_REG_SCAL
E
2Fh
31h
35h
0
ILLUM_
XTALK
_CALIB
IQ_READ_DATA_SEL
0
TEMP_COEFF_MAIN_HDR0_TX2[3:0
]
0
0
0
0
0
0
0
1
1
MONOSHOT_MO
DE
ILLUM_DAC_L_TX0
SEL_TX_CH
EN_TX
_SWIT
CH
USE_X
TALK_
REG_IL
LUM
USE_X
TALK_
FILT_IL
LUM
USE_X
TALK_
REG_I
NT
USE_X
TALK_
FILT_I
NT
INT_XT
ALK_C
ALIB
DIS_A
UTO_S
CALE
FORCE_SCALE_VAL
QPHASE_XTALK_REG_HDR0_TX0
0
IPHASE_XTALK_REG_HDR1_TX0
0
QPHASE_XTALK_REG_HDR1_TX0
0
TEMP_COEFF_MAIN_HDR1_TX2[11:4]
TEMP_COEFF_MAIN_HDR1_TX2[3:0
]
1
IPHASE_XTALK_REG_HDR0_TX0
TEMP_COEFF_MAIN_HDR0_TX2[11:4]
33h
34h
0
D0
TEMP_COEFF_MAIN_HDR1_TX0
TEMP_COEFF_MAIN_HDR1_TX1[11:4]
TEMP_COEFF_MAIN_HDR1_TX1[3:0
]
1
TX_SEQ_REG
INT_XTALK_REG_SCALE
2Eh
32h
EN_AD
APTIVE
_HDR
TEMP_COEFF_MAIN_HDR0_TX1
XTALK_FILT_TIME_CONST
0
ILLUM_DAC_H_TX0
2Ah
0
SEL_H
DR_M
ODE
0
MONOSHOT_NUMFRAME
ILLUM_DAC_L_TX1
ILLUM_
DAC_L
_TX2[0]
30h
0
MONOSHOT_FZ_CLKCNT
ILLUM_DAC_H_TX1
ILLUM_DAC_H_TX2
D1
COMMAND18
POWERUP_DELAY
27h
D2
COMPARE_REG2
16h
ILLUM_DAC_L_TX2[4:1]
D3
MUX_SEL_COMPIN
15h
29h
D4
COMPARE_REG1
IPHASE_XTALK_REG_HDR0_TX1
0
0
0
0
0
0
0
0
QPHASE_XTALK_REG_HDR0_TX1
IPHASE_XTALK_REG_HDR1_TX1
36h
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX0
QPHASE_XTALK_REG_HDR1_TX1
37h
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX0
IPHASE_XTALK_REG_HDR0_TX2
38h
TEMP_COEFF_XTALK_IPHASE_HDR0_TX0
QPHASE_XTALK_REG_HDR0_TX2
39h
TEMP_COEFF_XTALK_QPHASE_HDR0_TX0
IPHASE_XTALK_REG_HDR1_TX2
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Table 29. Default Register Map (continued)
ADDRE
SS
(Hex)
3Ah
D23
0
D22
D21
D20
SCALE_AMB_COEFF_XTA
LK
D19
D18
D17
SCALE_TEMP_COEFF_XT
ALK
D16
D15
D14
D13
D12
D11
D10
EN_TE
MP_XT
ALK_C
ORR
D9
D8
D7
D6
3Bh
IPHASE_XTALK
QPHASE_XTALK
3Dh
0
0
0
0
0
0
0
0
IPHASE_XTALK_INT_REG
3Eh
0
0
0
0
0
0
0
0
QPHASE_XTALK_INT_REG
NCR_C
ONFIG
0
EN_MU
LTI_FR
EQ_PH
ASE
0
0
0
40h
TILLUM_CALIB_HDR0_TX2
42h
ALPHA0_DEALIAS_SCALE
1
TMAIN_CALIB_HDR1_TX1
0
0
0
0
0
0
0
0
0
0
0
0
D1
D0
1
1
1
0
0
0
0
EN_DE
ALIAS_
MEAS
EN_TE
MP_CO
RR
EN_PH
ASE_C
ORR
0
EN_NL
_CORR
ALPHA1_DEALIAS_SCALE
PHASE_OFFSET_HDR0_TX0
TILLUM_CALIB_HDR1_TX1
0
D2
BETA1_DEALIAS_SCALE
0
43h
44h
D3
TMAIN_CALIB_HDR0_TX2
BETA0_DEALIAS_SCALE
41h
D4
QPHASE_XTALK_REG_HDR1_TX2
3Ch
3Fh
D5
0
0
SCALE_PHASE_TEMP_CO
EFF
0
0
TMAIN_CALIB_HDR1_TX2
TEMP_COEFF_MAIN_HDR0_TX0
46h
TILLUM_CALIB_HDR1_TX2
TEMP_COEFF_ILLUM_HDR0_TX0
47h
TILLUM_CALIB_HDR0_TX0
TMAIN_CALIB_HDR0_TX0
48h
TILLUM_CALIB_HDR1_TX0
TMAIN_CALIB_HDR1_TX0
49h
TILLUM_CALIB_HDR0_TX1
TMAIN_CALIB_HDR0_TX1
0
0
0
0
SCALE_NL_COR
R_COEFF
A0_COEFF_HDR0_TX0
4Bh
0
0
0
0
0
0
0
0
A1_COEFF_HDR0_TX0
4Ch
0
0
0
0
0
0
0
0
A2_COEFF_HDR0_TX0
4Dh
0
0
0
0
0
0
0
0
A3_COEFF_HDR0_TX0
4Eh
0
0
0
0
0
0
0
0
A4_COEFF_HDR0_TX0
1
0
OVERR
IDE_CL
KGEN_
REG
50h
51h
52h
53h
54h
55h
56h
57h
36
0
0
0
0
0
0
0
0
0
0
0
TEMP_COEFF_ILLUM_HDR1_TX0[11:4]
TEMP_COEFF_ILLUM_HDR1_TX0[3:
0]
0
0
0
0
0
0
0
1
0
0
0
0
CLIP_
MODE_
OFFSE
T
CLIP_
CLIP_
MODE_ MODE_
TEMP
NL
CLIP_
MODE_
FC
PHASE_OFFSET_HDR0_TX1
0
PHASE_OFFSET_HDR1_TX1
0
PHASE_OFFSET_HDR0_TX2
0
TEMP_COEFF_ILLUM_HDR1_TX1[11:4]
TEMP_COEFF_ILLUM_HDR1_TX1[3:
0]
0
PHASE_OFFSET_HDR1_TX0
TEMP_COEFF_ILLUM_HDR0_TX1[11:4]
TEMP_COEFF_ILLUM_HDR0_TX1[3:
0]
0
PHASE2_OFFSET_HDR0_TX0
45h
4Ah
0
PHASE_OFFSET_HDR1_TX2
0
PHASE2_OFFSET_HDR1_TX0
0
TEMP_COEFF_ILLUM_HDR0_TX2[11:4]
PHASE2_OFFSET_HDR0_TX1
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Table 29. Default Register Map (continued)
ADDRE
SS
(Hex)
58h
D23
D22
D21
59h
5Ah
D20
TEMP_COEFF_ILLUM_HDR0_TX2[3:
0]
D19
D18
D17
D16
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
0
D7
D6
D5
D4
D3
D2
D1
PHASE2_OFFSET_HDR0_TX2
0
0
PHASE2_OFFSET_HDR1_TX2
0
5Bh
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX1
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX1
5Ch
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX0
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX2
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX2
5Dh
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX2
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX1
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX1
5Eh
TEMP_COEFF_XTALK_IPHASE_HDR0_TX1
TEMP_COEFF_XTALK_IPHASE_HDR1_TX0
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX2
5Fh
TEMP_COEFF_XTALK_IPHASE_HDR1_TX2
TEMP_COEFF_XTALK_IPHASE_HDR0_TX2
TEMP_COEFF_XTALK_IPHASE_HDR1_TX1
60h
TEMP_COEFF_XTALK_QPHASE_HDR1_TX1
TEMP_COEFF_XTALK_QPHASE_HDR0_TX1
TEMP_COEFF_XTALK_QPHASE_HDR1_TX0
61h
64h
65h
6Eh
0
0
0
PROG_OVLDET_REFM
DIS_O
VLDET
0
0
0
71h
0
0
72h
0
0
0
0
0
0
0
PROG_OVLDET_REFP
77h
78h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMP_COEFF_XTALK_QPHASE_HDR1_TX2
0
0
0
SEL_G
P3_ON
_SDAM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
EN_TE
MP_CO
NV
0
0
0
0
0
0
0
0
0
0
EN_ILL
UM_CL
K_GPI
O
ILLUM_
CLK_G
PIO_M
ODE
0
0
DIS_IL
LUM_C
LK_TX
INVER
T_AFE
_CLK
0
INVER
T_TG_
CLK
SHUT_
CLOCK
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMP_COEFF_XTALK_QPHASE_HDR0_TX2
0
UNMA
SK_ILL
UMEN_
INTXTA
LK
0
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX0
0
0
0
0
0
0
0
0
PDN_IL
LUM_D
RV
79h
0
0
0
0
0
0
0
0
0
0
0
GPIO2
_IBUF_
EN
GPIO2
_OBUF
_EN
0
0
0
0
0
0
0
0
0
0
EN_DY
N_PD_I
2CHOS
T_OSC
0
0
0
0
GPIO1
_IBUF_
EN
GPIO1
_OBUF
_EN
0
PDN_IL
LUM_D
C_CUR
R
0
0
0
0
0
EN_DY
N_PD_
OSC
GPO2_MUX_SEL
0
0
0
RESER
VED
DIS_GL
B_PD_
AMB_D
AC
DIS_GL
DIS_GL
B_PD_
B_PD_
AFE_D
AFE
AC
DIS_GL DIS_GL
B_PD_I B_PD_
LLUM_ TEMP_
DRV
SENS
DIS_GL
B_PD_
REFSY
S
RESER
VED
EN_DY
N_PD_
AMB_A
DC
EN_DY
N_PD_
AMB_D
AC
EN_DY
N_PD_
AFE_D
AC
EN_DY
N_PD_I
LLUM_
DRV
EN_DY
N_PD_
REFSY
S
EN_DY
N_PD_
AFE
EN_DY
N_PD_
TEMP_
SENS
GPO1_MUX_SEL
0
0
0
0
DIS_GL
B_PD_
AMB_A
DC
0
0
0
0
EN_TX
_DC_C
URR_A
LL
SEL_IL
LUM_T
X0_ON
_TX1
ILLUM_DC_CURR_DAC
0
DEALIA
DEALIA
S_FRE
S_EN
Q
SHIFT_ILLUM_PHASE
IAMB_MAX_SEL
DIS_GL
DIS_GL
B_PD_I
B_PD_
2CHOS
OSC
T
PDN_G
LOBAL
76h
D0
PHASE2_OFFSET_HDR1_TX1
TEMP_COEFF_ILLUM_HDR1_TX2[11:4]
TEMP_COEFF_ILLUM_HDR1_TX2[3:
0]
D8
7Ah
0
0
0
0
0
0
0
0
0
0
0
0
0
80h
DIS_T
G_ACO
NF
0
0
0
83h
0
0
0
0
0
0
0
0
84h
0
0
0
0
0
0
0
0
TG_AFE_RST_END
85h
0
0
0
0
0
0
0
0
TG_SEQ_INT_START
0
0
TX0_PIN_CONFI
G
GPO3_MUX_SEL
EN_TX
_CLKZ
EN_TX
_CLKB
TX2_PIN_CONFI
G
TX1_PIN_CONFI
G
0
SUB_VD_CLK_CNT
TG_EN
TG_AFE_RST_START
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Table 29. Default Register Map (continued)
ADDRE
SS
(Hex)
D23
D22
D21
D20
D19
D18
D17
D16
86h
0
0
0
0
0
0
0
0
TG_SEQ_INT_END
87h
0
0
0
0
0
0
0
0
TG_CAPTURE_START
88h
0
0
0
0
0
0
0
0
TG_CAPTURE_END
89h
0
0
0
0
0
0
0
0
TG_OVL_WINDOW_START
8Ah
0
0
0
0
0
0
0
0
TG_OVL_WINDOW_END
8Fh
0
0
0
0
0
0
0
0
TG_ILLUMEN_START
90h
0
0
0
0
0
0
0
0
TG_ILLUMEN_END
91h
0
0
0
0
0
0
0
0
TG_CALC_START
92h
0
0
0
0
0
0
0
0
TG_CALC_END
93h
0
0
0
0
0
0
0
0
TG_DYNPDN_START
94h
0
0
0
0
0
0
0
0
TG_DYNPDN_END
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
97h
TG_SEQ_INT_MASK_END
TG_SEQ_INT_MASK_START
98h
TG_CAPTURE_MASK_END
TG_CAPTURE_MASK_START
99h
TG_OVL_WINDOW_MASK_END
TG_OVL_WINDOW_MASK_START
9Ch
TG_ILLUMEN_MASK_END
TG_ILLUMEN_MASK_START
9Dh
TG_CALC_MASK_END
TG_CALC_MASK_START
9Eh
TG_DYNPDN_MASK_END
TG_DYNPDN_MASK_START
9Fh
A0h
NUM_AVG_SUB_FRAMES
0
0
0
0
0
0
0
A3_COEFF_HDR0_TX1[15:8]
A0_COEFF_HDR1_TX0
A3_COEFF_HDR0_TX1[7:0]
A0_COEFF_HDR0_TX1
A4h
A3_COEFF_HDR1_TX1[15:8]
A0_COEFF_HDR1_TX1
A5h
A3_COEFF_HDR1_TX1[7:0]
A0_COEFF_HDR0_TX2
A6h
A3_COEFF_HDR0_TX2[15:8]
A0_COEFF_HDR1_TX2
A7h
A3_COEFF_HDR0_TX2[7:0]
A1_COEFF_HDR1_TX0
A8h
A3_COEFF_HDR1_TX2[15:8]
A1_COEFF_HDR0_TX1
A9h
A3_COEFF_HDR1_TX2[7:0]
A1_COEFF_HDR1_TX1
AAh
A4_COEFF_HDR1_TX0[15:8]
A1_COEFF_HDR0_TX2
ABh
A4_COEFF_HDR1_TX0[7:0]
A1_COEFF_HDR1_TX2
ACh
A4_COEFF_HDR0_TX1[15:8]
A2_COEFF_HDR1_TX0
ADh
A4_COEFF_HDR0_TX1[7:0]
A2_COEFF_HDR0_TX1
AEh
A4_COEFF_HDR1_TX1[15:8]
A2_COEFF_HDR1_TX1
AFh
A4_COEFF_HDR1_TX1[7:0]
A2_COEFF_HDR0_TX2
B0h
A4_COEFF_HDR0_TX2[15:8]
A2_COEFF_HDR1_TX2
B1h
A4_COEFF_HDR0_TX2[7:0]
0
B4h
B5h
38
0
0
0
0
0
0
0
D0
A3_COEFF_HDR1_TX0
0
0
0
A4_COEFF_HDR1_TX2
AMB_PHASE_CORR_PWL_COEFF3
0
D1
CAPTURE_CLK_CNT
A3h
0
D2
NUM_SUB_FRAMES
0
A2h
B2h
D3
0
AMB_PHASE_CORR_PWL_COEFF2
0
0
0
0
0
0
0
0
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AMB_PHASE_CORR_PWL_COEFF1
0
0
0
0
0
0
0
SCALE_AMB_PHASE_CO
RR_COEFF
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Table 29. Default Register Map (continued)
ADDRE
SS
(Hex)
B8h
B9h
D23
0
D22
0
D21
D20
0
GIVE_
DEALIA
S_DAT
A
ILLUM_SCALE_H_TX2
D19
D18
ILLUM_SCALE_L_TX2
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AMB_PHASE_CORR_PWL_X0
AMB_PHASE_CORR_PWL_X1
AMB_ADC_IN_T
X2
AMB_ADC_IN_T
X1
AMB_ADC_IN_T
X0
EN_TX
2_ON_
TX0
EN_TX
1_ON_
TX0
AMB_PHASE_CORR_PWL_X2
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7.5.1.1 Register Descriptions
Table 30. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
7.5.1.1.1 Register 0h (Address = 0h) [reset = 0h]
Figure 29. Register 0h
23
22
MONOSHOT_B FORCE_EN_S
IT
LAVE
R/W - 0h
R/W - 0h
15
14
7
0
R/W - 0h
21
20
FORCE_EN_B
YPASS
R/W - 0h
13
6
I2C_CONT_R
W
R/W - 0h
5
19
18
17
16
R/W - 0h
10
9
8
0
2
1
0
SOFTWARE_R
ESET
R/W - 0h
RESERVED
12
11
RESERVED
R/W - 0h
4
3
RESERVED
R/W - 0h
Table 31. Register 00 Field Descriptions
Bit
Field
Type
Reset
23
MONOSHOT_BIT
R/W
0h
Monoshot trigger register. Write a 1 to this bit to start sample capture in
monoshot mode. This bit is auto cleared after the sample capture
completion.
22
FORCE_EN_SLAVE
R/W
0h
Setting this bit to 1 enables I2C slave register access from the device I2C
host for any address. Set this bit to 1 when the SDA_M and SCL_M pins
are left floating.
21
FORCE_EN_BYPASS
R/W
0h
Setting this bit to 1 disables the device I2C host and shorts the I2C host bus
and I2C slave bus.
RESERVED
R/W
0h
Always read or write 0h.
I2C_CONT_RW
R/W
0h
Enable continuous read/write of the device I2C slave registers.
RESERVED
R/W
0h
Always read or write 0h.
SOFTWARE_RESET
R/W
0h
Generates a device reset on writing this bit and resets all the register
settings to default values, including this bit.
20:7
6
5:1
0
Description
7.5.1.1.2 Register 1h (Address = 1h) [reset = 120140h]
Figure 30. Register 1h
23
RESERVED
22
0
R/W - 0h
15
R/W - 0h
14
21
20
I2C_RW
R/W - 1h
13
12
RESERVED
19
I2C_EN
R/W - 0h
11
R/W - 0h
40
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18
I2C_TRIG_RE
G
R/W - 0h
10
17
FRAME_VD_T
RIG
R/W - 1h
9
16
RESERVED
R/W - 0h
8
ADDR_SLAVE
_EEPROM
R/W - 1h
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7
6
5
4
ADDR_SLAVE_EEPROM
3
2
1
SWAP_READ_
DATA
R/W - 0h
R/W - 10h
0
RESERVED
R/W - 0h
Table 32. Register 01 Field Descriptions
Bit
Field
Type
Reset
23
RESERVED
R/W
0h
Description
Always read or write 0h.
21:20
I2C_RW
R/W
1h
Chooses R/W for I2C host operation.
0: Write | 1: Read
LSB: first transaction, MSB: second transaction
19
I2C_EN
R/W
0h
Enables the I2C host.
18
I2C_TRIG_REG
R/W
0h
The trigger register for I2C transactions
17
FRAME_VD_TRIG
R/W
1h
When this bit is 1, the I2C host is triggered on every sample start. Else it is
triggered based on the setting of I2C_TRIG_REG.
16:9
RESERVED
R/W
0h
Always read or write 0h.
8:2
ADDR_SLAVE_EEPROM
R/W
50h
External EEPROM I2C slave address.
1
SWAP_READ_DATA
R/W
0h
Setting this bit to 1 reverses the data read by I2C host from [7:0] to [0:7].
0
RESERVED
R/W
0h
Always read or write 0h.
7.5.1.1.3 Register 2h (Address = 2h) [reset = 92A4C8h]
Figure 31. Register 2h
23
22
TEMP_AVG_ILLUM
R/W - 2h
15
14
TSENS_SLAVE2
R/W - 2h
7
6
TSENS_SLAVE
1
R/W - 1h
21
EN_TILLUM_R
EAD
R/W - 0h
13
20
5
4
19
18
TSENS_SLAVE2
R/W - 12h
11
10
TSENS_SLAVE1
R/W - 24h
3
2
TSENS_SLAVE0
12
17
16
9
8
1
0
R/W - 48h
Table 33. Register 02 Field Descriptions
Bit
23:22
Field
Type
Reset
Description
TEMP_AVG_ILLUM
R/W
2h
Average external temperature sensor reading.
0: No average | 1: 2-sample average | 2: 4-sample average | Other values:
Not valid
EN_TILLUM_READ
R/W
0h
Enable I2C read of appropriate external temperature sensor on I2C host
bus.
0: Disable external temperature sensor read | 1: Enable external
temperature sensor read
20:14
TSENS_SLAVE2
R/W
4Ah
Slave address of the external temperature sensor in proximity to the TX2
channel
13:7
TSENS_SLAVE1
R/W
49h
Slave address of the external temperature sensor in proximity to the TX1
channel
6:0
TSENS_SLAVE0
R/W
48h
Slave address of the external temperature sensor in proximity to the TX0
channel
21
7.5.1.1.4 Register 3h (Address = 3h) [reset = 800000h]
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Figure 32. Register 3h
23
22
TEMP_AVG_MAIN
21
20
19
18
11
10
17
I2C_NUM_TRA
N
R/W - 0h
9
2
1
RESERVED
R/W - 2h
15
14
13
7
6
5
R/W - 0h
12
I2C_WRITE_DATA1
R/W - 0h
4
3
I2C_READ_DATA
R - 0h
16
I2C_WRITE_D
ATA1
R/W - 0h
8
INIT_LOAD_D
ONE
R - 0h
0
Table 34. Register 03 Field Descriptions
Bit
Field
Type
Reset
23:22
TEMP_AVG_MAIN
R/W
0h
Average on-chip temperature sensor reading.
0: No average | 1: 2-sample average | 2: 4-sample average | 3: Not valid
21:18
RESERVED
R/W
0h
Always read or write 0h.
I2C_NUM_TRAN
R/W
0h
The number of I2C host transactions.
0: 1 transaction | 1: 2 transactions.
16:9
I2C_WRITE_DATA1
R/W
0h
The external I2C slave device register address connected to the OPT3101
I2C host bus where the read would start. Normally in a temperature-sensor
read this is not required to be programmed.
8
INIT_LOAD_DONE
R
0h
Can be used to check whether initial auto load from EEPROM is successful
or not.
0: Auto load from EEPROM is incomplete | 1: Auto load from EEPROM is
complete
7:0
I2C_READ_DATA
R
0h
The I2C host read data.
17
Description
7.5.1.1.5 Register 4h (Address = 4h) [reset = 17h]
Figure 33. Register 4h
23
TILLUM_UNSI
GNED
R/W - 0h
15
22
14
21
RESERVED
20
19
18
17
16
TILLUM
R/W - 0h
13
R - 0h
12
11
10
9
8
3
2
1
0
TILLUM
R - 0h
7
6
5
4
RESERVED
R/W - 17h
Table 35. Register 04 Field Descriptions
Bit
Field
Type
Reset
Description
23
TILLUM_UNSIGNED
R/W
0h
Set this bit to 1 when the temperature given by the external temperature
sensor is in unsigned format.
22:20
RESERVED
R/W
0h
Always read or write 0h.
19:8
TILLUM
R
0h
The temperature value of the external temperature sensor.
7:0
RESERVED
R/W
17h
Always read or write 17h.
7.5.1.1.6 Register 5h (Address = 5h) [reset = 80000h]
42
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Figure 34. Register 5h
23
22
I2C_NUM_BYTES_TRAN2
R/W-0h
15
14
7
21
20
R/W-0h
13
6
5
19
18
RESERVED
R/W-0h
R/W-1h
R/W-0h
12
11
10
RESERVED
R/W-0h
4
3
2
RESERVED
R/W-0h
17
16
R/W-0h
9
R/W-0h
8
1
0
Table 36. Register 05 Field Descriptions
Bit
Field
Type
Reset
Description
23:22
I2C_NUM_BYTES_TRAN2
R/W
0h
Number of bytes used in transaction 2 of the I2C host transaction.
0: 1 byte | 1: 2 bytes | Other values: Not valid
21:16
RESERVED
R/W
08h
Always read or write 08h.
15:0
RESERVED
R/W
0h
Always read or write 0h.
7.5.1.1.7 Register 7h (Address = 7h) [reset = 0h]
Figure 35. Register 7h
23
22
21
CONFIG_TILLUM_MSB
R/W-0h
14
13
15
7
6
20
19
18
I2C_SEL_READ_BYTES
R/W-0h
12
11
10
RESERVED
R/W-0h
4
3
2
I2C_WRITE_DATA2
R/W-0h
5
17
16
I2C_NUM_BYTES_TRAN1
R/W-0h
9
8
1
0
Table 37. Register 07 Field Descriptions
Bit
Field
Type
Reset
Description
23:20
CONFIG_TILLUM_MSB
R/W
0h
Configure the data read by the device I2C host from the external
temperature sensor
8: I2C host read data[15:4], to support 12-bit external temperature sensor |
Other values: Not valid.
Along with this register also set the EN_TILLUM_12B regsiter to 1.
19:18
I2C_SEL_READ_BYTES
R/W
0h
Chooses which byte of the I2C_READ register to be read on the
I2C_READ_DATA register
0: 7:0 | 1: 15:8 | 2: 23:16 | 3: 31:24
17:16
I2C_NUM_BYTES_TRAN1
R/W
0h
Number of bytes used in the transaction 1 of I2C host transaction.
0: 1 byte | 1: 2 bytes
15:8
RESERVED
R/W
0h
Always read or write 0h.
7:0
I2C_WRITE_DATA2
R/W
0h
Second byte of I2C write transaction. 8-bit register data to be written
7.5.1.1.8 Register 8h (Address = 8h) [reset = 0h]
Figure 36. Register 8h
23
22
FRAME_COUN AMB_OVL_FLA
T0
G
R-0h
R-0h
15
14
21
MOD_FREQ
R-0h
13
20
FRAME_STAT
US
R-0h
12
19
18
TX_CHANNEL
R-0h
11
10
17
HDR_MODE
R-0h
9
16
PHASE_OVER
_FLOW
R-0h
8
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PHASE_OUT
R-0h
7
6
5
4
3
2
1
0
PHASE_OUT
R-0h
Table 38. Register 08 Field Descriptions
Bit
Field
Type
Reset
23
FRAME_COUNT0
R
0h
Frame counter LSB bit.
22
AMB_OVL_FLAG
R
0h
Overload flag to indicate ambient saturation
0: No saturation | 1: Ambient saturation
21
MOD_FREQ
R
0h
Indicates the frequency used.
0: 10 MHz | 1: De-alias frequency (10 MHz × 6 / 7 or 10 MHz × 6 / 5)
20
FRAME_STATUS
R
0h
0: Invalid frame | 1: Valid frame. Frame is invalid during the internal
crosstalk calibration frame (INT_XTALK_CALIB = 1) or the illumination
crosstalk calibration frame (ILLUM_XTALK_CALIB = 1).
TX_CHANNEL
R
0h
Indicates which Illumination channel used.
0: TX0 | 1: TX1 | 2: TX2 | 3: Not valid
17
HDR_MODE
R
0h
Indicates the illumination driver DAC current used.
0: ILLUM_DAC_L | 1: ILLUM_DAC_H
16
PHASE_OVER_FLOW
R
0h
PHASE_OUT overflow bit during frequency correction
0: No overflow | 1: overflow
PHASE_OUT
R
0h
Final calibrated phase.
19:18
15:0
Description
7.5.1.1.9 Register 9h (Address = 9h) [reset = 0h]
Figure 37. Register 9h
23
22
21
20
19
PHASE_OVER
_FLOW_F2
R-0h
12
11
AMP_OUT
R-0h
4
3
AMP_OUT
R-0h
DEALIAS_BIN
R-0h
15
14
13
7
6
5
18
SIG_OVL_FLA
G
R-0h
10
2
17
16
FRAME_COUNT1
R-0h
9
8
1
0
Table 39. Register 09 Field Descriptions
Bit
Type
Reset
DEALIAS_BIN
R
0h
Distance bin in de-alias mode.
De-aliased distance = DEALIAS_BIN × 216 × FREQ_COUNT_READ_REG /
16384 + PHASE_OVER_FLOW × 216 + PHASE_OUT
19
PHASE_OVER_FLOW_F2
R
0h
Phase overflow of second modulation frequency used for de-alias operation
during frequency correction.
0: No overflow | 1: overflow
18
SIG_OVL_FLAG
R
0h
Overload flag to indicate signal saturation
0: No saturation | 1: Signal saturation
17:16
FRAME_COUNT1
R
0h
Frame counter bits [2:1]
15:0
AMP_OUT
R
0h
Amplitude of the received signal.
23:20
Field
Description
7.5.1.1.10 Register Ah (Address = Ah) [reset = 0h]
44
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Figure 38. Register Ah
23
22
21
20
19
18
11
10
17
16
9
8
TMAIN
R-0h
15
14
13
12
TMAIN
R-0h
7
6
AMB_DATA
R-0h
5
4
3
2
1
0
FRAME_COUNT2
R-0h
AMB_DATA
R-0h
Table 40. Register 0A Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TMAIN
R
0h
On-chip temperature sensor output
Temperature (°C) = TMAIN / 8 – 256
11:2
AMB_DATA
R
0h
Ambient ADC output. Indicates the ambient light.
1:0
FRAME_COUNT2
R
0h
Frame counter MSB bits [4:3].
7.5.1.1.11 Register Bh (Address = Bh) [reset = FC009h]
Figure 39. Register Bh
23
22
21
20
19
18
11
10
17
16
AMB_CALIB
R/W - 0Fh
15
14
13
12
AMB_CALIB
R/W - 3h
7
GPO_SEL2
R/W - 0h
6
5
DIG_GPO_SEL1
R/W - 0h
4
3
9
0
R/W - 0h
2
1
DIG_GPO_SEL0
R/W - 9h
8
0
R/W - 0h
0
Table 41. Register 0B Field Descriptions
Field
Type
Reset
23:14
Bit
AMB_CALIB
R/W
3Fh
13:10
DIG_GPO_SEL2
R/W
0h
Mux selection bits for digital signal DIG_GPO_2 which can be brought out
on GP3 (SDA_M)
0
R/W
0h
Always read or write 0h.
0h
Mux selection bits for digital signal DIG_GPO_1 which can be brought out
on GP1 or GP2
0: FRAME VD | 1: SUB-VD | 4: SEQUENCER INTERRUPT
8: COMP_STATUS | 9: DATA_RDY | 10: FRAME_COUNTER_LSB | Other
values: Not valid
9h
Mux selection bits for digital signal DIG_GPO_0 which can be brought out
on GP1 or GP2
0: FRAME VD | 1: SUB-VD | 4: SEQUENCER INTERRUPT
8: COMP_STATUS | 9: DATA_RDY | 10: FRAME_COUNTER_LSB | Other
values: Not valid
9:8
7:4
3:0
DIG_GPO_SEL1
DIG_GPO_SEL0
R/W
R/W
Description
The ambient ADC value at which device is calibrated for phase offset
7.5.1.1.12 Register Ch (Address = Ch) [reset = 0h]
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Figure 40. Register Ch
23
22
21
15
14
13
7
6
5
20
19
AMB_PHASE_CORR_PWL_COEFF0
R/W - 0h
12
11
AMB_XTALK_QPHASE_COEFF
R/W - 0h
4
3
AMB_XTALK_IPHASE_COEFF
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 42. Register 0C Field Descriptions
Bit
Field
Type
Reset
23:16
AMB_PHASE_CORR_PWL
_COEFF0
Description
R/W
0h
Coefficient 0 for piecewise linear (PWL) phase correction with ambient.
15:8
AMB_XTALK_QPHASE_C
OEFF
R/W
0h
Coefficient to correct for the crosstalk (quadrature component) change with
ambient.
7:0
AMB_XTALK_IPHASE_CO
EFF
R/W
0h
Coefficient to correct for the crosstalk (in-phase component) change with
ambient.
7.5.1.1.13 Register Dh (Address = Dh) [reset = 6000h]
Figure 41. Register Dh
23
EN_TILLUM_1
2B
R/W - 0h
15
22
21
14
13
7
AMB_SAT_TH
R
R/W - 0h
6
5
20
19
18
17
10
9
16
AMB_SAT_TH
R
R/W - 0h
8
2
1
0
RESERVED
R/W - 0h
12
11
AMB_SAT_THR
R/W - 60h
4
3
RESERVED
R/W - 0h
Table 43. Register 0D Field Descriptions
Bit
Field
Type
Reset
Description
EN_TILLUM_12B
R/W
0h
Enables support for an external temperature sensor with more than 8-bit
resolution on the I2C host bus. Preferred 12-bit temperature sensor:
TMP102.
0: 8-bit temperature read | 1: 12-bit temperature read
22:17
RESERVED
R/W
0h
Always read or write 0h.
16:7
AMB_SAT_THR
R/W
C0h
6:0
RESERVED
R/W
0h
23
Ambient threshold which is used to detect the ambient overload.
AMB_DATA – AMB_CALIB is compared against this threshold value and
AMB_OVL_FLAG is set to 1 if it exceeds the threshold.
Always read or write 0h.
7.5.1.1.14 Register Fh (Address = Fh) [reset = 144C4Bh]
Figure 42. Register Fh
23
EN_FREQ_CO
RR
R/W - 0h
15
46
22
EN_FLOOP
R/W - 0h
14
21
EN_AUTO_FR
EQ_COUNT
R/W - 0h
13
20
19
18
SYS_CLK_DIVIDER
12
11
17
R/W - Ah
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10
9
16
START_FREQ
_CALIB
R/W - 0h
8
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RESERVED
R/W - 0h
7
6
REF_COUNT_LIMIT
R/W - 4Ch
4
3
REF_COUNT_LIMIT
R/W - 4Bh
5
2
1
0
Table 44. Register 0F Field Descriptions
Bit
Field
Type
Reset
23
EN_FREQ_CORR
R/W
0h
Enable frequency correction for the phase output.
0: Frequency correction disabled | 1: Frequency correction enabled
22
EN_FLOOP
R/W
0h
Enables the frequency calibration block.
0: Disable frequency calibration block | 1: Enable frequency calibration
block
21
EN_AUTO_FREQ_COUNT
R/W
0h
Determines the value to be used for frequency correction.
0 – On-chip trimmed value | 1 – Measured value from frequency calibration
SYS_CLK_DIVIDER
R/W
Ah
Programs the system-clock divider for frequency calibration. This register
should be adjusted to get it closer to the external reference frequency
connected to GP2 pin.
SYS_CLK_DIVIDER = round(log2(40 × 106 / fEXT))
16
START_FREQ_CALIB
R/W
0h
Setting this bit to 1 starts the frequency calibration.
15
RESERVED
R/W
0h
Always read or write 0h.
REF_COUNT_LIMIT
R/W
4C4Bh
20:17
14:0
Description
This sets the limit for ref-clock count.
REF_COUNT_LIMIT = (40 × 106 / 2SYS_CLK_DIVIDER) / fEXT
7.5.1.1.15 Register 10h (Address = 10h) [reset = 4000h]
Figure 43. Register 10h
23
22
21
15
EN_CONT_FC
ALIB
R/W - 0h
7
14
13
6
5
20
19
18
AMPLITUDE_MIN_THR[15:8]
R/W - 0h
12
11
10
FREQ_COUNT_READ_REG
R/W - 40h
4
3
FREQ_COUNT_READ_REG
R/W - 0h
2
17
16
9
8
1
0
Table 45. Register 10 Field Descriptions
Bit
23:16
15
14:0
Field
Type
Reset
AMPLITUDE_MIN_THR[15:
8]
R/W
0h
MSB of minimum amplitude threshold below which phase is made FFFFh.
EN_CONT_FCALIB
R/W
0h
Enables continuous frequency calibration.
0: Frequency is measured only when START_FREQ_CALIB = 1 | 1:
Frequency is continuously measured.
R
4000h
FREQ_COUNT_READ_RE
G
Description
Read register which holds the value of frequency correction when frequency
calibration is enabled. This value is used for frequency correction when
EN_AUTO_FREQ_COUNT = 1.
7.5.1.1.16 Register 11h (Address = 11h) [reset = 0h]
Figure 44. Register 11h
23
22
21
15
14
13
20
19
AMPLITUDE_MIN_THR[7:0]
R/W - 0h
12
11
18
17
16
10
9
8
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DIS_OVL_GATI
NG
R/W - 0h
7
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FREQ_COUNT_REG
6
R
4
3
FREQ_COUNT_REG
R
5
2
1
0
Table 46. Register 11 Field Descriptions
Bit
23:16
15
14:0
Field
Type
Reset
AMPLITUDE_MIN_THR[7:0
]
R/W
0h
LSB of minimum amplitude threshold below which phase is made FFFFh.
DIS_OVL_GATING
R/W
0h
Disable gating of phase output when SIG_OVL_FLAG becomes 1.
0: PHASE_OUT is gated when SIG_OVL_FLAG = 1 | 1: PHASE_OUT is
not gated
FREQ_COUNT_REG
Description
Digital frequency correction trim value. This value will be used for frequency
correction when EN_AUTO_FREQ_COUNT = 0.
R
7.5.1.1.17 Register 13h (Address = 13h) [reset = 0h]
Figure 45. Register 13h
23
22
15
14
7
6
21
RESERVED
R/W - 0h
13
20
5
COMPARE_REG1
R/W - 0h
19
18
12
11
COMPARE_REG1
R/W - 0h
4
3
10
2
17
COMPARE_REG1
R/W - 0h
9
16
1
MUX_SEL_COMPIN
R/W - 0h
0
8
Table 47. Register 13 Field Descriptions
Field
Type
Reset
23:19
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
18:3
COMPARE_REG1
R/W
0h
Sequencer comparison threshold1 register
2:0
MUX_SEL_COMPIN
R/W
0h
Chooses the value used for comparator input register of sequencer.
0: AMP_OUT | 1: DEALIAS_BIN | 2: De-alias distance | 3: PHASE_OUT |
Other values: Not valid.
7.5.1.1.18 Register 14h (Address = 14h) [reset = 0h]
Figure 46. Register 14h
23
22
21
RESERVED
R/W - 0h
48
15
14
13
7
6
5
20
19
DIS_INTERRU
PT
R/W - 0h
12
11
COMPARE_REG2
R/W - 0h
4
3
COMPARE_REG2
R/W - 0h
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18
STATUS_IN_R
EG
R/W - 0h
10
17
EN_PROCESS
OR_VALUES
R/W - 0h
9
16
EN_SEQUENC
ER
R/W - 0h
8
2
1
0
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Table 48. Register 14 Field Descriptions
Bit
Field
Type
Reset
RESERVED
R/W
0h
Always read or write 0h.
19
DIS_INTERRUPT
R/W
0h
Disables the interrupt that triggers sequencer.
0: Sequencer interrupt enabled | 1: Sequencer interrupt disabled
18
STATUS_IN_REG
R/W
0h
This register is used to control the program flow in the sequencer
17
EN_PROCESSOR_VALUE
S
R/W
0h
Uses STATUS_OUT values instead of register values. STAUTS_OUT
register mapping is described in Table 20
16
EN_SEQUENCER
R/W
0h
Enable the sequencer.
0: Sequencer enabled | 1: Sequencer disabled
15:0
COMPARE_REG2
R/W
0h
Sequencer second comparison threshold register
23:20
Description
7.5.1.1.19 Register 15h (Address = 15h) [reset = 101063h]
Figure 47. Register 15h
23
22
21
20
19
18
11
10
17
16
9
8
1
0
17
16
9
8
1
0
COMMAND1
R/W - 10h
15
14
13
12
COMMAND1
R/W - 1h
7
6
COMMAND0
R/W - 0h
5
4
3
2
COMMAND0
R/W - 63h
Table 49. Register 15 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
COMMAND1
R/W
101h
Sequencer command 1.
11:0
COMMAND0
R/W
63h
Sequencer command 0.
7.5.1.1.20 Register 16h (Address = 16h) [reset = 400100h]
Figure 48. Register 16h
23
22
21
20
19
18
11
10
COMMAND3
R/W - 40h
15
14
13
12
COMMAND3
R/W - 0h
7
6
COMMAND2
R/W - 1h
5
4
3
2
COMMAND2
R/W - 00h
Table 50. Register 16 Field Descriptions
Field
Type
Reset
Description
23:12
Bit
COMMAND3
R/W
400h
Sequencer command 3.
11:0
COMMAND2
R/W
100h
Sequencer command 2.
7.5.1.1.21 Register 17h (Address = 17h) [reset = 0h]
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Figure 49. Register 17h
23
22
21
20
19
18
11
10
17
16
9
8
1
0
17
16
9
8
1
0
17
16
9
8
1
0
COMMAND5
R/W - 0h
15
14
13
12
COMMAND5
R/W - 0h
7
6
COMMAND4
R/W - 0h
5
4
3
2
COMMAND4
R/W - 0h
Table 51. Register 17 Field Descriptions
Field
Type
Reset
23:12
Bit
COMMAND5
R/W
0h
Description
Sequencer command 5.
11:0
COMMAND4
R/W
0h
Sequencer command 4.
7.5.1.1.22 Register 18h (Address = 18h) [reset = 0h]
Figure 50. Register 18h
23
22
21
20
19
18
11
10
COMMAND7
R/W - 0h
15
14
13
12
COMMAND7
R/W - 0h
7
6
COMMAND6
R/W - 0h
5
4
3
2
COMMAND6
R/W - 0h
Table 52. Register 18 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
COMMAND7
R/W
0h
Sequencer command 7.
11:0
COMMAND6
R/W
0h
Sequencer command 6.
7.5.1.1.23 Register 19h (Address = 19h) [reset = 0h]
Figure 51. Register 19h
23
22
21
20
19
18
11
10
COMMAND9
R/W - 0h
15
14
13
12
COMMAND9
R/W - 0h
7
6
COMMAND8
R/W - 0h
5
4
3
2
COMMAND8
R/W - 0h
Table 53. Register 19 Field Descriptions
Bit
50
Field
Type
Reset
23:12
COMMAND9
R/W
0h
Description
Sequencer command 9.
11:0
COMMAND8
R/W
0h
Sequencer command 8.
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7.5.1.1.24 Register 1Ah (Address = 1Ah) [reset = 0h]
Figure 52. Register 1Ah
23
22
21
20
19
18
11
10
17
16
9
8
1
0
17
16
9
8
1
0
17
16
9
8
1
0
COMMAND11
R/W - 0h
15
14
13
12
COMMAND11
R/W - 0h
7
6
COMMAND10
R/W - 0h
5
4
3
2
COMMAND10
R/W - 0h
Table 54. Register 1A Field Descriptions
Field
Type
Reset
23:12
Bit
COMMAND11
R/W
0h
Description
Sequencer command 11.
11:0
COMMAND10
R/W
0h
Sequencer command 10.
7.5.1.1.25 Register 1Bh (Address = 1Bh) [reset = 0h]
Figure 53. Register 1Bh
23
22
21
20
19
18
11
10
COMMAND13
R/W - 0h
15
14
13
12
COMMAND13
R/W - 0h
7
6
COMMAND12
R/W - 0h
5
4
3
2
COMMAND12
R/W - 0h
Table 55. Register 1B Field Descriptions
Bit
Field
Type
Reset
Description
23:12
COMMAND13
R/W
0h
Sequencer command 13.
11:0
COMMAND12
R/W
0h
Sequencer command 12.
7.5.1.1.26 Register 1Ch (Address = 1Ch) [reset = 0h]
Figure 54. Register 1Ch
23
22
21
20
19
18
11
10
COMMAND15
R/W - 0h
15
14
13
12
COMMAND15
R/W - 0h
7
6
COMMAND14
R/W - 0h
5
4
3
2
COMMAND14
R/W - 0h
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Table 56. Register 1C Field Descriptions
Field
Type
Reset
23:12
Bit
COMMAND15
R/W
0h
Description
Sequencer command 15.
11:0
COMMAND14
R/W
0h
Sequencer command 14.
7.5.1.1.27 Register 1Dh (Address = 1Dh) [reset = 0h]
Figure 55. Register 1Dh
23
22
21
20
19
18
17
16
11
10
9
8
1
0
17
16
9
8
1
0
18
17
16
10
9
0
R/W - 0h
1
8
0
R/W - 0h
0
COMMAND17
R/W - 0h
15
14
13
12
COMMAND17
R/W - 0h
7
6
COMMAND16
R/W - 0h
5
4
3
2
COMMAND16
R/W - 0h
Table 57. Register 1D Field Descriptions
Bit
Field
Type
Reset
Description
23:12
COMMAND17
R/W
0h
Sequencer command 17.
11:0
COMMAND16
R/W
0h
Sequencer command 16.
7.5.1.1.28 Register 1Eh (Address = 1Eh) [reset = 0h]
Figure 56. Register 1Eh
23
22
21
20
19
18
11
10
COMMAND19
R/W - 0h
15
14
13
12
COMMAND19
R/W - 0h
7
6
COMMAND18
R/W - 0h
5
4
3
2
COMMAND18
R/W - 0h
Table 58. Register 1E Field Descriptions
Field
Type
Reset
23:12
Bit
COMMAND19
R/W
0h
Description
Sequencer command 19.
11:0
COMMAND18
R/W
0h
Sequencer command 18.
7.5.1.1.29 Register 26h (Address = 26h) [reset = 4000Fh]
Figure 57. Register 26h
52
23
22
15
14
7
6
21
20
19
POWERUP_DELAY
R/W - 04h
13
12
11
POWERUP_DELAY
R/W - 00h
5
4
3
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0
R/W - 0h
0
R/W - 0h
0
R/W - 0h
0
R/W - 0h
1
R/W - 1h
1
R/W - 1h
1
R/W - 1h
1
R/W - 1h
Table 59. Register 26 Field Descriptions
Bit
23:10
9:0
Field
Type
Reset
Description
POWERUP_DELAY
R/W
100h
Register to program the delay from the monoshot trigger to start of frame
(FRAME_VD). Delay = (64 × POWERUP_DELAY + 2) × tCLK, tCLK = 25 ns.
RESERVED
R/W
Fh
Always read or write Fh.
7.5.1.1.30 Register 27h (Address = 27h) [reset = 26AC18h]
Figure 58. Register 27h
23
22
15
14
7
6
MONOSHOT_NUMFRAME
21
20
19
MONOSHOT_FZ_CLKCNT
R/W - 26h
13
12
11
MONOSHOT_FZ_CLKCNT
R/W - ACh
5
4
3
MONOSHOT_NUMFRAME
R/W - 6h
18
17
16
10
9
8
2
1
0
MONOSHOT_MODE
R/W - 0h
Table 60. Register 27 Field Descriptions
Bit
Field
Type
Reset
Description
23:8
MONOSHOT_FZ_CLKCNT
R/W
26ACh
The CLK count at which a monoshot operation freezes.
7:2
MONOSHOT_NUMFRAME
R/W
6h
The number of samples to be captured on every monoshot trigger event.
1:0
MONOSHOT_MODE
R/W
0h
Select monoshot mode.
0: Continuous mode | 3: Monoshot mode | Other values: Not valid
7.5.1.1.31 Register 29h (Address = 29h) [reset = 3F0FC3h]
Figure 59. Register 29h
23
22
21
ILLUM_DAC_L_TX2[4:1]
R/W - 3h
14
13
15
ILLUM_DAC_H
_TX1
R/W - 0h
7
6
ILLUM_DAC_H_TX0
R/W - 6h
20
19
12
ILLUM_DAC_L_TX1
11
R/W - 03h
4
5
18
17
16
ILLUM_DAC_H_TX1
R/W - Fh
10
9
8
ILLUM_DAC_H_TX0
R/W - 3h
3
2
ILLUM_DAC_L_TX0
R/W - 03h
1
0
Table 61. Register 29 Field Descriptions
Bit
Field
Type
Reset
Description
23:20
ILLUM_DAC_L_TX2[4:1]
R/W
3h
19:15
ILLUM_DAC_H_TX1
R/W
1Eh
Illumination driver current DAC register, ILLUM_DAC_H of TX1 channel
14:10
ILLUM_DAC_L_TX1
R/W
3h
Illumination driver current DAC register, ILLUM_DAC_L of TX1 channel
9:5
ILLUM_DAC_H_TX0
R/W
1Eh
Illumination driver current DAC register, ILLUM_DAC_H of TX0 channel
4:0
ILLUM_DAC_L_TX0
R/W
3h
Illumination driver current DAC register, ILLUM_DAC_L of TX0 channel
Illumination driver current DAC register, ILLUM_DAC_L[4:1] of TX2 channel
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7.5.1.1.32 Register 2Ah (Address = 2Ah) [reset = 784920h]
Figure 60. Register 2Ah
23
ILLUM_DAC_L
_TX2[0]
R/W - 0h
15
EN_ADAPTIVE
_HDR
R/W - 0h
7
22
21
20
ILLUM_DAC_H_TX2
14
13
6
5
TX_SEQ_REG
R/W - 1Eh
12
19
18
11
TX_SEQ_REG
10
R/W - 49h
3
4
17
RESERVED
R/W - 0h
9
2
1
SEL_TX_CH
R/W - 04h
16
SEL_HDR_MO
DE
R/W - 0h
8
R/W - 0h
0
EN_TX_SWITC
H
R/W - 0h
Table 62. Register 2A Field Descriptions
Bit
Field
Type
23
ILLUM_DAC_L_TX2[0]
R/W
1h
ILLUM_DAC_H_TX2
R/W
1Eh
17
RESERVED
R/W
0h
Always read or write 0h.
16
SEL_HDR_MODE
R/W
0h
Selects which current to use when EN_ADAPTIVE_HDR = 0
0: ILLUM_DAC_L | 1: ILLUM_DAC_H
15
EN_ADAPTIVE_HDR
R/W
0h
Enable adaptive HDR to switch between two illumination driver currents
(ILLUM_DAC_L and ILLUM_DAC_H) depending on the amplitude of the
received signal.
0: Disable adaptive HDR | 1: Enable adaptive HDR
14:3
TX_SEQ_REG
R/W
924h
Switching sequence of illumination channels. Up to a sequence of 6
channel configurations.
For example, for register value: 2-1-0-2-1-0, the illumination channel
sequence is 0-1-2-0-1-2
2:1
SEL_TX_CH
R/W
0h
Selects the illumination channel when channel switching is disabled.
0: TX0 | 1: TX1 | 2: TX2 | 3: Not valid
0h
Enable switching of illumination channels.
0: TX channel switching is disabled and the TX channel is determined by
SEL_TX_CH
1: TX channel switching is enabled. The TX channel switching is
programmed with TX_SEQ_REG.
22:18
0
EN_TX_SWITCH
R/W
Reset
Description
Illumination driver current DAC register, ILLUM_DAC_L[0] of TX2 channel
Illumination driver current DAC register, ILLUM_DAC_H of TX2 channel
7.5.1.1.33 Register 2Bh (Address = 2Bh) [reset = 6000h]
Figure 61. Register 2Bh
23
22
21
15
14
13
7
6
5
RESERVED
R/W - 0h
54
20
19
ILLUM_SCALE_H_TX0
R/W - 0h
12
11
HDR_THR_HIGH
R/W - 60h
4
3
HDR_THR_HIGH
R/W - 00h
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18
16
10
17
ILLUM_SCALE_L_TX0
R/W - 0h
9
2
1
0
8
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Table 63. Register 2B Field Descriptions
Field
Type
Reset
23:22
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
21:19
ILLUM_SCALE_H_TX0
R/W
0h
Illumination driver current scale register of TX0 channel with DAC_H
current.
0: 5.6 mA | 1: 4.2mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid
18:16
ILLUM_SCALE_L_TX0
R/W
0h
Illumination driver current scale register of TX0 channel with DAC_L current.
0: 5.6 mA | 1: 4.2mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid
15:0
HDR_THR_HIGH
R/W
6000h
High threshold for the HDR switching. Amplitude is compared against this
threshold when the illumination driver current is high (ILLUM_DAC_H) and it
switches to ILLUM_DAC_L if the amplitude exceeds this threshold value.
7.5.1.1.34 Register 2Ch (Address = 2Ch) [reset = 800h]
Figure 62. Register 2Ch
23
22
21
RESERVED
R/W - 0h
15
14
13
7
6
5
20
19
ILLUM_SCALE_H_TX1
R/W - 0h
12
11
HDR_THR_LOW
R/W - 08h
4
3
HDR_THR_LOW
R/W - 0h
18
17
16
10
ILLUM_SCALE_L_TX1
R/W - 0h
9
8
2
1
0
Table 64. Register 2C Field Descriptions
Bit
Field
Type
Reset
23:22
RESERVED
R/W
0h
Always read or write 0h.
21:19
ILLUM_SCALE_H_TX0
R/W
0h
Illumination driver current scale register of TX1 channel with DAC_H
current.
0: 5.6 mA | 1: 4.2 mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid
18:16
ILLUM_SCALE_L_TX0
R/W
0h
Illumination driver current scale register of TX1 channel with DAC_L current.
0: 5.6 mA | 1: 4.2 mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid
800h
Low threshold for the HDR switching. Amplitude is compared against this
threshold when the Illumination driver current is low (ILLUM_DAC_L) and it
switches to ILLUM_DAC_H if the amplitude is lower than this threshold
value.
15:0
HDR_THR_LOW
R/W
Description
7.5.1.1.35 Register 2Dh (Address = 2Dh) [reset = 0h]
Figure 63. Register 2Dh
23
15
7
22
21
14
13
TEMP_COEFF_MAIN_HDR0_TX1
R/W - 0h
6
5
20
19
TEMP_COEFF_MAIN_HDR0_TX1
R/W - 0h
12
11
4
3
TEMP_COEFF_MAIN_HDR1_TX0
R/W - 0h
18
17
10
9
TEMP_COEFF_MAIN_HDR1_TX0
R/W - 0h
2
1
16
8
0
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Table 65. Register 2D Field Descriptions
Bit
Field
Type
Reset
23:12
TEMP_COEFF_MAIN_HD
R0_TX1
Description
R/W
0h
Phase temperature coefficient for sensor temperature for TX1 illumination
channel with current of ILLUM_DAC_L_TX1
11:0
TEMP_COEFF_MAIN_HD
R1_TX0
R/W
0h
Phase temperature coefficient for sensor temperature for TX0 illumination
channel with current of ILLUM_DAC_H_TX0
7.5.1.1.36 Register 2Eh (Address = 2Eh) [reset = 8001A0h]
Figure 64. Register 2Eh
23
22
21
XTALK_FILT_TIME_CONST
R/W - 8h
15
14
INT_XTALK_REG_SCALE
13
0
R/W - 0h
R/W - 0h
7
6
5
USE_XTALK_F USE_XTALK_R USE_XTALK_F
ILT_ILLUM
EG_INT
ILT_INT
R/W - 1h
R/W - 0h
R/W - 1h
20
19
12
ILLUM_XTALK
_CALIB
R/W - 0h
4
INT_XTALK_C
ALIB
R/W - 0h
18
17
ILLUM_XTALK_REG_SCALE
16
INT_XTALK_R
EG_SCALE
R/W - 0h
R/W - 0h
11
10
9
8
IQ_READ_DATA_SEL
USE_XTALK_R
EG_ILLUM
R/W - 0h
R/W - 1h
3
2
1
0
DIS_AUTO_SC
FORCE_SCALE_VAL
ALE
R/W - 0h
R/W - 0h
Table 66. Register 2E Field Descriptions
Bit
Field
Type
Reset
23:20
XTALK_FILT_TIME_CONS
T
R/W
8h
Time constant for crosstalk filtering. Time constant τ =
2XTALK_FILT_TIME_CONST frames. At least 5τ should be allowed for settling the
crosstalk measurement.
19:17
ILLUM_XTALK_REG_SCA
LE
R/W
0h
Scale factor for illumination crosstalk register
(IPHASE_XTALK_REG_HDR<i>_TX<j>,
QPHASE_XTALK_REG_HDR<i>_TX<j>, i = 0, 1, j = 0, 1, 2).
Scale = 2ILLUM_XTALK_REG_SCALE
16:14
INT_XTALK_REG_SCALE
R/W
0h
Scale factor for internal crosstalk register (IPHASE_XTALK_INT_REG,
QPHASE_XTALK_INT_REG).
Scale = 2INT_XTALK_REG_SCALE
0
R/W
0h
Always read or write 0.
13
56
Description
12
ILLUM_XTALK_CALIB
R/W
0h
The device initializes the illumination crosstalk measurement upon setting
this bit. This measurement should be done with the photodiode masked
such that no modulated light is received.
Use the following sequence:
ILLUM_XTALK_CALIB = 1
Delay (at least 5 × 2XTALK_FILT_TIME_CONST frames)
ILLUM_XTALK_CALIB = 0
11:9
IQ_READ_DATA_SEL
R/W
0h
Mux selection for IPHASE_XTALK, QPHASE_XTALK registers
0: Internal crosstalk | 1: Illumination crosstalk | 2: Raw I, Q | 3: 16-bit frame
counter | Other values: Not valid
8
USE_XTALK_REG_ILLUM
R/W
1h
Select register value or internally calibrated value for illumination crosstalk
0: Calibration value | 1: Register value
7
USE_XTALK_FILT_ILLUM
R/W
1h
Select filter or direct sampling for Illumination crosstalk measurement.
0: Direct sampling | 1: Filter
6
USE_XTALK_REG_INT
R/W
0h
Select register value or internally calibrated value for internal crosstalk
0: Calibration value | 1: Register value
5
USE_XTALK_FILT_INT
R/W
1h
Select filter or direct sampling for internal crosstalk measurement.
0: Direct sampling | 1: Filter
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Table 66. Register 2E Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
INT_XTALK_CALIB
R/W
0h
The device initializes the internal electrical crosstalk measurement upon
setting this bit.
Use following sequence:
INT_XTALK_CALIB = 1
Delay (at least 5 × 2XTALK_FILT_TIME_CONST frames)
INT_XTALK_CALIB = 0
3
DIS_AUTO_SCALE
R/W
0h
Disable digital auto scale in the signal path.
0: Auto scale enabled | 1: Auto scale disabled.
FORCE_SCALE_VAL
R/W
0h
Digital scaling uses this register scale value if DIS_AUTO_SCALE = 1. This
scale value is also used during any crosstalk calibration even if
DIS_AUTO_SCALE = 0.
Scale = 2(6 – FORCE_SCALE_VAL)
2:0
7.5.1.1.37 Register 2Fh (Address = 2Fh) [reset = 0h]
Figure 65. Register 2Fh
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_MAIN_HDR1_TX1[11:4]
R/W - 0h
12
11
IPHASE_XTALK_REG_HDR0_TX0
R/W - 0h
4
3
IPHASE_XTALK_REG_HDR0_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 67. Register 2F Field Descriptions
Bit
Field
Type
Reset
Description
23:16
TEMP_COEFF_MAIN_HD
R1_TX1[11:4]
R/W
0h
MSB of phase temperature coefficient for sensor temperature for TX1
illumination channel with current of ILLUM_DAC_H_TX1
15:0
IPHASE_XTALK_REG_HD
R0_TX0
R/W
0h
Register for illumination crosstalk in-phase component for TX0 channel with
ILLUM_DAC_L_TX0 current
7.5.1.1.38 Register 30h (Address = 30h) [reset = 0h]
Figure 66. Register 30h
23
15
7
22
21
20
19
TEMP_COEFF_MAIN_HDR1_TX1[3:0]
R/W - 0h
14
13
12
11
QPHASE_XTALK_REG_HDR0_TX0
R/W - 0h
6
5
4
3
QPHASE_XTALK_REG_HDR0_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
Table 68. Register 30 Field Descriptions
Bit
Field
Type
Reset
23:20
TEMP_COEFF_MAIN_HD
R1_TX1[3:0]
Description
R/W
0h
LSB of phase temperature coefficient for sensor temperature for TX1
illumination channel with current of ILLUM_DAC_H_TX1
19:16
RESERVED
R/W
0h
Always read or write 0h.
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Table 68. Register 30 Field Descriptions (continued)
Bit
Field
Type
Reset
15:0
QPHASE_XTALK_REG_H
DR0_TX0
R/W
0h
Description
Quadrature component of the crosstalk for ILLUM_DAC_L of TX0
7.5.1.1.39 Register 31h (Address = 31h) [reset = 0h]
Figure 67. Register 31h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_MAIN_HDR0_TX2[11:4]
R/W - 0h
12
11
IPHASE_XTALK_REG_HDR1_TX0
R/W - 0h
4
3
IPHASE_XTALK_REG_HDR1_TX0
18
17
16
10
9
8
2
1
0
R/W - 0h
Table 69. Register 31 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_MAIN_HD
R0_TX2[11:4]
Description
R/W
0h
MSB of phase temperature coefficient for sensor temperature for TX2
illumination channel with current of ILLUM_DAC_L_TX2
15:0
IPHASE_XTALK_REG_HD
R1_TX0
R/W
0h
In-phase component of the crosstalk for ILLUM_DAC_H of TX0
7.5.1.1.40 Register 32h (Address = 32h) [reset = 0h]
Figure 68. Register 32h
23
15
7
22
21
20
19
TEMP_COEFF_MAIN_HDR0_TX2[3:0]
R/W - 0h
14
13
12
11
QPHASE_XTALK_REG_HDR1_TX0
R/W - 0h
6
5
4
3
QPHASE_XTALK_REG_HDR1_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
Table 70. Register 32 Field Descriptions
Bit
Field
Type
Reset
23:20
TEMP_COEFF_MAIN_HD
R0_TX2[3:0]
Description
R/W
0h
LSB of phase temperature coefficient for sensor temperature for TX2
illumination channel with current of ILLUM_DAC_L_TX2
19:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
QPHASE_XTALK_REG_H
DR1_TX0
R/W
0h
Register for illumination crosstalk quad phase component for TX0 channel
with ILLUM_DAC_H_TX0 current
7.5.1.1.41 Register 33h (Address = 33h) [reset = 0h]
58
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Figure 69. Register 33h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_MAIN_HDR1_TX2[11:4]
R/W - 0h
12
11
IPHASE_XTALK_REG_HDR0_TX1
R/W - 0h
4
3
IPHASE_XTALK_REG_HDR0_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 71. Register 33 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_MAIN_HD
R1_TX2[11:4]
Description
R/W
0h
MSB of phase temperature coefficient for sensor temperature for TX2
illumination channel with current of ILLUM_DAC_H_TX2
15:0
IPHASE_XTALK_REG_HD
R0_TX1
R/W
0h
Register for illumination crosstalk in-phase component for TX1 channel with
ILLUM_DAC_L_TX1 current
7.5.1.1.42 Register 34h (Address = 34h) [reset = 0h]
Figure 70. Register 34h
23
15
7
22
21
20
19
TEMP_COEFF_MAIN_HDR1_TX2[3:0]
R/W - 0h
14
13
12
11
QPHASE_XTALK_REG_HDR0_TX1
R/W - 0h
6
5
4
3
QPHASE_XTALK_REG_HDR0_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
Table 72. Register 34 Field Descriptions
Bit
Field
Type
Reset
23:20
TEMP_COEFF_MAIN_HD
R1_TX2[3:0]
Description
R/W
0h
LSB of phase temperature coefficient for sensor temperature for TX2
illumination channel with current of ILLUM_DAC_H_TX2
19:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
QPHASE_XTALK_REG_H
DR0_TX1
R/W
0h
Register for illumination crosstalk in quadrature-phase component for TX1
channel with ILLUM_DAC_L_TX1 current
7.5.1.1.43 Register 35h (Address = 35h) [reset = 0h]
Figure 71. Register 35h
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
IPHASE_XTALK_REG_HDR1_TX1
R/W - 0h
4
3
IPHASE_XTALK_REG_HDR1_TX1
R/W - 0h
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Table 73. Register 35 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
IPHASE_XTALK_REG_HD
R1_TX1
R/W
0h
Register for illumination crosstalk in-phase component for TX1 channel with
ILLUM_DAC_H_TX1 current
7.5.1.1.44 Register 36h (Address = 36h) [reset = 0h]
Figure 72. Register 36h
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX0
R/W - 0h
13
12
11
10
QPHASE_XTALK_REG_HDR1_TX1
R/W - 0h
5
4
3
2
QPHASE_XTALK_REG_HDR1_TX1
R/W - 0h
17
16
9
8
1
0
Table 74. Register 36 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_ILLUM_XT
ALK_IPHASE_HDR0_TX0
Description
R/W
0h
Temperature coefficient of crosstalk in-phase component with TILLUM for
TX0 channel with ILLUM_DAC_L_TX0 current.
15:0
QPHASE_XTALK_REG_H
DR1_TX1
R/W
0h
Register for illumination crosstalk quadrature-phase component for TX1
channel with ILLUM_DAC_H_TX1 current
7.5.1.1.45 Register 37h (Address = 37h) [reset = 0h]
Figure 73. Register 37h
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX0
R/W - 0h
13
12
11
10
IPHASE_XTALK_REG_HDR0_TX2
R/W - 0h
5
4
3
2
IPHASE_XTALK_REG_HDR0_TX2
R/W - 0h
17
16
9
8
1
0
Table 75. Register 37 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_ILLUM_XT
ALK_QPHASE_HDR0_TX0
Description
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TILLUM for TX0 channel with ILLUM_DAC_L_TX0 current.
15:0
IPHASE_XTALK_REG_HD
R0_TX2
R/W
0h
Register for illumination crosstalk in-phase component for TX2 channel with
ILLUM_DAC_L_TX2 current
7.5.1.1.46 Register 38h (Address = 38h) [reset = 0h]
60
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Figure 74. Register 38h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_XTALK_IPHASE_HDR0_TX0
R/W - 0h
12
11
QPHASE_XTALK_REG_HDR0_TX2
R/W - 0h
4
3
QPHASE_XTALK_REG_HDR0_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 76. Register 38 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_XTALK_IP
HASE_HDR0_TX0
Description
R/W
0h
Temperature coefficient of crosstalk in-phase component with TMAIN for
TX0 channel with ILLUM_DAC_L_TX0 current
15:0
QPHASE_XTALK_REG_H
DR0_TX2
R/W
0h
Register for illumination crosstalk quadrature-phase component for TX2
channel with ILLUM_DAC_L_TX2 current
7.5.1.1.47 Register 39h (Address = 39h) [reset = 0h]
Figure 75. Register 39h
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_XTALK_QPHASE_HDR0_TX0
R/W - 0h
13
12
11
10
IPHASE_XTALK_REG_HDR1_TX2
R/W - 0h
5
4
3
2
IPHASE_XTALK_REG_HDR1_TX2
R/W - 0h
17
16
9
8
1
0
Table 77. Register 39 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_XTALK_QP
HASE_HDR0_TX0
Description
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TMAIN for TX0 channel with ILLUM_DAC_L_TX0 current
15:0
IPHASE_XTALK_REG_HD
R1_TX2
R/W
0h
Register for illumination crosstalk in-phase component for TX2 channel with
ILLUM_DAC_H_TX2 current
7.5.1.1.48 Register 3Ah (Address = 3Ah) [reset = 0h]
Figure 76. Register 3Ah
23
RESERVED
22
21
20
SCALE_AMB_COEFF_XTALK
R/W - 0h
15
14
R/W - 4h
13
7
6
5
19
18
17
SCALE_TEMP_COEFF_XTALK
12
11
QPHASE_XTALK_REG_HDR1_TX2
R/W - 0h
4
3
QPHASE_XTALK_REG_HDR1_TX2
R/W - 0h
R/W - 5h
10
9
16
EN_TEMP_XT
ALK_CORR
R/W - 0h
8
2
1
0
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Table 78. Register 3A Field Descriptions
Bit
Field
Type
Reset
23
RESERVED
R/W
0h
Description
Always read or write 0h.
22:20
SCALE_AMB_COEFF_XTA
LK
R/W
4h
Scaling factor for ambient coefficient of crosstalk
(AMB_XTALK_IPHASE_COEFF, AMB_XTALK_QPHASE_COEFF)
19:17
SCALE_TEMP_COEFF_XT
ALK
R/W
5h
Scaling factor for temperature coefficient of crosstalk
(TEMP_COEFF_XTALK_IPHASE_HDR<i>_TX<j>,
TEMP_COEFF_XTALK_QPHASE_HDR<i>_TX<j>; i = 0, 1; j = 0, 1, 2).
16
EN_TEMP_XTALK_CORR
R/W
0h
Enable crosstalk correction with temperature.
15:0
QPHASE_XTALK_REG_H
DR1_TX2
R/W
0h
Register for illumination crosstalk quadrature-phase component for TX2
channel with ILLUM_DAC_H_TX2 current
7.5.1.1.49 Register 3Bh (Address = 3Bh) [reset = 0h]
Figure 77. Register 3Bh
23
22
21
15
14
13
7
6
5
20
19
IPHASE_XTALK
R - 0h
12
11
IPHASE_XTALK
R - 0h
4
3
IPHASE_XTALK
R - 0h
18
17
16
10
9
8
2
1
0
Table 79. Register 3B Field Descriptions
Bit
Field
23:0
IPHASE_XTALK
Type
Reset
R
0h
Description
Read-only register. In-phase component. Different values can be selected
to be read out with IQ_READ_DATA_SEL.
7.5.1.1.50 Register 3Ch (Address = 3Ch) [reset = 0h]
Figure 78. Register 3Ch
23
22
21
15
14
13
7
6
5
20
19
QPHASE_XTALK
R - 0h
12
11
QPHASE_XTALK
R - 0h
4
3
QPHASE_XTALK
R - 0h
18
17
16
10
9
8
2
1
0
Table 80. Register 3C Field Descriptions
Bit
Field
23:0
QPHASE_XTALK
Type
Reset
R
0h
Description
Read-only register. Quadrature-phase component. Different values can be
selected to be read out with IQ_READ_DATA_SEL.
7.5.1.1.51 Register 3Dh (Address = 3Dh) [reset = 0h]
62
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Figure 79. Register 3Dh
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R - 0h
15
14
13
7
6
5
12
11
IPHASE_XTALK_INT_REG
R/W - 0h
4
3
IPHASE_XTALK_INT_REG
R/W - 0h
Table 81. Register 3D Field Descriptions
Bit
Field
23:16
RESERVED
15:0
IPHASE_XTALK_INT_REG
Type
Reset
R
0h
R/W
0h
Description
Register for in-phase component of internal crosstalk
7.5.1.1.52 Register 3Eh (Address = 3Eh) [reset = 0h]
Figure 80. Register 3Eh
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R - 0h
15
14
13
7
6
5
12
11
QPHASE_XTALK_INT_REG
R/W - 0h
4
3
QPHASE_XTALK_INT_REG
R/W - 0h
Table 82. Register 3E Field Descriptions
Bit
Field
23:16
RESERVED
15:0
QPHASE_XTALK_INT_RE
G
Type
Reset
R
0h
R/W
0h
Description
Register for quadrature-phase component of internal crosstalk
7.5.1.1.53 Register 3Fh (Address = 3Fh) [reset = 0h]
Figure 81. Register 3Fh
23
22
15
21
14
13
TILLUM_CALIB_HDR0_TX2
R/W - 0h
6
5
7
20
19
TILLUM_CALIB_HDR0_TX2
R/W - 0h
12
11
4
3
TMAIN_CALIB_HDR0_TX2
R/W - 0h
18
17
10
9
TMAIN_CALIB_HDR0_TX2
R/W - 0h
2
1
16
8
0
Table 83. Register 3F Field Descriptions
Bit
23:12
Field
Type
Reset
TILLUM_CALIB_HDR0_TX
2
R/W
0h
Description
Calibration temperature of external temperature sensor (TILLUM) for TX2
illumination channel with current of ILLUM_DAC_L_TX2
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Table 83. Register 3F Field Descriptions (continued)
Bit
Field
Type
Reset
11:0
TMAIN_CALIB_HDR0_TX2
R/W
0h
Description
Calibration temperature of on-chip temperature sensor (TMAIN) for TX2
illumination channel with current of ILLUM_DAC_L_TX2
7.5.1.1.54 Register 40h (Address = 40h) [reset = 2021E0h]
Figure 82. Register 40h
23
RESERVED
R/W - 0h
15
BETA0_DEALI
AS_SCALE
R/W - 0h
7
22
EN_MULTI_FR
EQ_PHASE
R/W - 0h
14
21
NCR_CONFIG
6
5
R/W - 1h
13
20
19
18
BETA0_DEALIAS_SCALE
12
11
ALPHA0_DEALIAS_SCALE
17
16
R/W - 0h
10
9
8
RESERVED
2
1
R/W - 10h
4
3
RESERVED
R/W - 1h
0
EN_DEALIAS_
MEAS
R/W - 0h
R/W - 70h
Table 84. Register 40 Field Descriptions
Bit
Field
Type
Reset
23
RESERVED
R/W
0h
Description
Always read or write 0h.
22
EN_MULTI_FREQ_PHASE
R/W
0h
With this bit set to 1, along with EN_DEALIAS_MEAS = 1, the PHASE_OUT
register gives the phase measurement with two frequencies. The frequency
of the phase is indicated in MOD_FREQ status bit.
0: 10-MHz modulation | 1: 10-MHz and 10 × (6 / 7)-MHz or 10 × (6 / 5)-MHz
modulation.
21
NCR_CONFIG
R/W
1h
Select second frequency for de-alias operation.
0: 10 × (6 / 7) MHz | 1: 10 × (6 / 5) MHz.
20:15
BETA0_DEALIAS_SCALE
R/W
0h
Internal crosstalk scaling for de-alias frequency.
β = BETA0_DEALIAS_SCALE / 16.
14:9
ALPHA0_DEALIAS_SCALE
R/W
10h
Internal crosstalk scaling for de-alias frequency.
α = ALPHA0_DEALIAS_SCALE / 16.
8:1
RESERVED
R/W
F0h
Always read or write F0h.
EN_DEALIAS_MEAS
R/W
0h
0
Enables de-alias measurement.
0: Default operating mode | 1: De-alias operating mode
7.5.1.1.55 Register 41h (Address = 41h) [reset = 10h]
Figure 83. Register 41h
23
22
15
21
14
13
TMAIN_CALIB_HDR1_TX1
R/W - 0h
7
6
5
BETA1_DEALIAS_SCALE
R/W - 0h
64
20
19
TMAIN_CALIB_HDR1_TX1
R/W - 0h
12
11
4
18
17
10
9
BETA1_DEALIAS_SCALE
R/W - 0h
3
2
1
ALPHA1_DEALIAS_SCALE
R/W - 10h
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16
8
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Table 85. Register 41 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TMAIN_CALIB_HDR1_TX1
R/W
0h
Calibration temperature of on-chip temperature sensor (TMAIN) for TX1
illumination channel with current of ILLUM_DAC_H_TX1
11:6
BETA1_DEALIAS_SCALE
R/W
0h
Illumination crosstalk scaling for de-alias frequency.
β = BETA1_DEALIAS_SCALE / 16
5:0
ALPHA1_DEALIAS_SCALE
R/W
10h
Illumination crosstalk scaling for de-alias frequency.
α = ALPHA1_DEALIAS_SCALE / 16
7.5.1.1.56 Register 42h (Address = 42h) [reset = 0h]
Figure 84. Register 42h
23
22
21
20
19
18
17
16
11
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
7
6
13
12
PHASE_OFFSET_HDR0_TX0
R/W - 0h
4
3
PHASE_OFFSET_HDR0_TX0
R/W - 0h
5
Table 86. Register 42 Field Descriptions
Bit
Field
Type
Reset
Description
23:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
PHASE_OFFSET_HDR0_T
X0
R/W
0h
Phase offset for TX0 illumination channel with current of
ILLUM_DAC_L_TX0
7.5.1.1.57 Register 43h (Address = 43h) [reset = 81h]
Figure 85. Register 43h
23
15
22
21
14
13
TILLUM_CALIB_HDR1_TX1
R/W - 0h
7
6
SCALE_PHASE_TEMP_COEFF
20
19
TILLUM_CALIB_HDR1_TX1
R/W - 0h
12
11
0
5
4
R/W - 2h
R/W - 0h
3
RESERVED
18
17
10
0
9
0
R/W - 0h
2
R/W - 0h
1
EN_TEMP_CO
RR
R/W - 0h
R/W - 0h
16
8
SCALE_PHAS
E_TEMP_COE
FF
R/W - 0h
0
EN_PHASE_C
ORR
R/W - 1h
Table 87. Register 43 Field Descriptions
Bit
Field
Type
Reset
23:12
TILLUM_CALIB_HDR1_TX
1
R/W
0h
Calibration temperature of external temperature sensor (TILLUM) for TX1
illumination channel with current of ILLUM_DAC_H_TX1.
8:6
SCALE_PHASE_TEMP_C
OEFF
R/W
2h
Scaling factor for phase temperature coefficient.
5:2
RESERVED
R/W
0h
Always read or write 0h.
EN_TEMP_CORR
R/W
0h
Enables temperature correction for phase.
0: Phase temperature correction disabled | 0: Phase temperature correction
enabled
1
Description
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Table 87. Register 43 Field Descriptions (continued)
Bit
0
Field
Type
Reset
EN_PHASE_CORR
R/W
1h
Description
Enables phase offset correction.
0: Phase offset correction disabled | 0: Phase offset correction enabled
7.5.1.1.58 Register 44h (Address = 44h) [reset = 0h]
Figure 86. Register 44h
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
PHASE2_OFFSET_HDR0_TX0
R/W - 0h
4
3
PHASE2_OFFSET_HDR0_TX0
R/W - 0h
Table 88. Register 44 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
PHASE2_OFFSET_HDR0_
TX0
R/W
0h
De-alias frequency phase offset for TX0 illumination channel with current of
ILLUM_DAC_L_TX0.
7.5.1.1.59 Register 45h (Address = 45h) [reset = 0h]
Figure 87. Register 45h
23
22
15
21
14
13
TMAIN_CALIB_HDR1_TX2
R/W - 0h
6
5
7
20
19
TMAIN_CALIB_HDR1_TX2
R/W - 0h
12
11
4
3
18
17
10
9
TEMP_COEFF_MAIN_HDR0_TX0
R/W - 0h
2
1
16
8
0
TEMP_COEFF_MAIN_HDR0_TX0
R/W - 0h
Table 89. Register 45 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TMAIN_CALIB_HDR1_TX2
R/W
0h
Calibration temperature of on-chip temperature sensor (TMAIN) for TX2
illumination channel with current of ILLUM_DAC_H_TX2
11:0
TEMP_COEFF_MAIN_HD
R0_TX0
R/W
0h
Phase temperature coefficient of TX0 illumination channel with on-chip
temperature sensor (TMAIN) for a current of ILLUM_DAC_L_TX0
7.5.1.1.60 Register 46h (Address = 46h) [reset = 0h]
Figure 88. Register 46h
23
15
66
22
21
14
13
TILLUM_CALIB_HDR1_TX2
20
19
TILLUM_CALIB_HDR1_TX2
R/W - 0h
12
11
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18
17
10
9
TEMP_COEFF_ILLUM_HDR0_TX0
16
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R/W - 0h
7
6
R/W - 0h
5
4
3
TEMP_COEFF_ILLUM_HDR0_TX0
R/W - 0h
2
1
0
Table 90. Register 46 Field Descriptions
Bit
Field
Type
Reset
23:12
TILLUM_CALIB_HDR1_TX
2
Description
R/W
0h
Calibration temperature of external temperature sensor (TILLUM) for TX2
illumination channel with current of ILLUM_DAC_H_TX2
11:0
TEMP_COEFF_ILLUM_HD
R0_TX0
R/W
0h
Phase temperature coefficient of illumination source connected to TX0 pin
with external temperature sensor (TILLUM) for a current of
ILLUM_DAC_L_TX0.
7.5.1.1.61 Register 47h (Address = 47h) [reset = 800800h]
Figure 89. Register 47h
23
22
15
21
14
13
TILLUM_CALIB_HDR0_TX0
R/W - 0h
6
5
7
20
19
TILLUM_CALIB_HDR0_TX0
R/W - 80h
12
11
4
3
TMAIN_CALIB_HDR0_TX0
R/W - 0h
18
17
10
9
TMAIN_CALIB_HDR0_TX0
R/W - 8h
2
1
16
8
0
Table 91. Register 47 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TILLUM_CALIB_HDR0_TX
0
R/W
800h
Calibration temperature of external temperature sensor (TILLUM) for TX0
illumination channel with current of ILLUM_DAC_L_TX0
11:0
TMAIN_CALIB_HDR0_TX0
R/W
800h
Calibration temperature of on-chip temperature sensor (TMAIN) for TX0
illumination channel with current of ILLUM_DAC_L_TX0
7.5.1.1.62 Register 48h (Address = 48h) [reset = 0h]
Figure 90. Register 48h
23
22
15
21
14
13
TILLUM_CALIB_HDR1_TX0
R/W - 0h
6
5
7
20
19
TILLUM_CALIB_HDR1_TX0
R/W - 0h
12
11
4
3
TMAIN_CALIB_HDR1_TX0
R/W - 0h
18
17
10
9
TMAIN_CALIB_HDR1_TX0
R/W - 0h
2
1
16
8
0
Table 92. Register 48 Field Descriptions
Bit
Field
Type
Reset
23:12
TILLUM_CALIB_HDR1_TX
0
Description
R/W
0h
Calibration temperature of external temperature sensor (TILLUM) for TX0
illumination channel with current of ILLUM_DAC_H_TX0
11:0
TMAIN_CALIB_HDR1_TX0
R/W
0h
Calibration temperature of on-chip temperature sensor (TMAIN) for TX0
illumination channel with current of ILLUM_DAC_H_TX0
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7.5.1.1.63 Register 49h (Address = 49h) [reset = 0h]
Figure 91. Register 49h
23
22
15
21
14
13
TILLUM_CALIB_HDR0_TX1
R/W - 0h
6
5
7
20
19
TILLUM_CALIB_HDR0_TX1
R/W - 0h
12
11
4
3
TMAIN_CALIB_HDR0_TX1
R/W - 0h
18
17
10
9
TMAIN_CALIB_HDR0_TX1
R/W - 0h
2
1
16
8
0
Table 93. Register 49 Field Descriptions
Bit
Field
Type
Reset
23:12
TILLUM_CALIB_HDR0_TX
1
Description
R/W
0h
Calibration temperature of external temperature sensor (TILLUM) for TX1
illumination channel with current of ILLUM_DAC_L_TX1
11:0
TMAIN_CALIB_HDR0_TX1
R/W
0h
Calibration temperature of on-chip temperature sensor (TMAIN) for TX0
illumination channel with current of ILLUM_DAC_L_TX1
7.5.1.1.64 Register 4Ah (Address = 4Ah) [reset = 0h]
Figure 92. Register 4Ah
23
22
21
20
19
18
SCALE_NL_CORR_COEFF
R/W - 0h
13
12
11
10
A0_COEFF_HDR0_TX0
R/W - 0h
5
4
3
2
A0_COEFF_HDR0_TX0
R/W - 0h
RESERVED
R/W - 0h
15
14
7
6
17
16
A0_COEFF_HDR0_TX0
R/W - 0h
9
8
1
RESERVED
R/W - 0h
0
EN_NL_CORR
R/W - 0h
Table 94. Register 4A Field Descriptions
Field
Type
Reset
23:20
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
19:18
SCALE_NL_CORR_COEF
F
R/W
0h
Scaling factor for nonlinearity correction coefficients
(A*_COEFF_HDR<i>_TX<j>, i = 0,1; j = 0, 1, 2)
17:2
A0_COEFF_HDR0_TX0
R/W
0h
0th order coefficient for square wave nonlinearity correction
1
RESERVED
R/W
0h
Always read or write 0h.
0
EN_NL_CORR
R/W
0h
Enables square wave harmonic nonlinearity correction
7.5.1.1.65 Register 4Bh (Address = 4Bh) [reset = 407h]
Figure 93. Register 4Bh
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R - 0h
68
15
14
13
7
6
5
12
11
A1_COEFF_HDR0_TX0
R/W - 04h
4
3
A1_COEFF_HDR0_TX0
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R/W - 07h
Table 95. Register 4B Field Descriptions
Bit
Field
23:16
RESERVED
15:0
A1_COEFF_HDR0_TX0
Type
Reset
R
0h
R/W
407h
Description
Always read or write 0h.
First-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_L_TX0.
7.5.1.1.66 Register 4Ch (Address = 4Ch) [reset = F23Eh]
Figure 94. Register 4Ch
23
22
21
20
R/W - 0h
15
R/W - 0h
14
R/W - 0h
13
7
6
5
19
RESERVED 0
R - 0h
R/W - 0h
R/W - 0h
12
11
A2_COEFF_HDR0_TX0
R/W - F2h
4
3
A2_COEFF_HDR0_TX0
R/W - 3Eh
18
17
16
R/W - 0h
10
R/W - 0h
9
R/W - 0h
8
2
1
0
Table 96. Register 4C Field Descriptions
Bit
Field
23:16
RESERVED
15:0
A2_COEFF_HDR0_TX0
Type
Reset
R
0h
R/W
F23Eh
Description
Always read or write 0h.
Second-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_L_TX0.
7.5.1.1.67 Register 4Dh (Address = 4Dh) [reset = 1144h]
Figure 95. Register 4Dh
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R - 0h
15
14
13
7
6
5
12
11
A3_COEFF_HDR0_TX0
R/W - 11h
4
3
A3_COEFF_HDR0_TX0
R/W - 44h
Table 97. Register 4D Field Descriptions
Bit
Field
23:16
RESERVED
15:0
A3_COEFF_HDR0_TX0
Type
Reset
R
0h
R/W
1144h
Description
Third-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_L_TX0.
7.5.1.1.68 Register 4Eh (Address = 4Eh) [reset = F881h]
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Figure 96. Register 4Eh
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R - 0h
15
14
13
7
6
5
12
11
A4_COEFF_HDR0_TX0
R/W - F8h
4
3
A4_COEFF_HDR0_TX0
R/W - 81h
Table 98. Register 4E Field Descriptions
Bit
Field
23:16
RESERVED
15:0
A4_COEFF_HDR0_TX0
Type
Reset
R
0h
R/W
F881h
Description
Fourth-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_L_TX0
7.5.1.1.69 Register 50h (Address = 50h) [reset = 200100h]
Figure 97. Register 50h
23
0
21
1
20
0
R/W - 0h
15
0
R/W - 0h
7
0
22
OVERRIDE_CL
KGEN_REG
R/W - 0h
14
0
R/W - 0h
6
0
19
0
R/W - 1h
13
0
R/W - 0h
5
0
R/W - 0h
12
0
R/W - 0h
4
0
R/W - 0h
R/W - 0h
R/W - 0h
R/W - 0h
18
0
17
0
16
0
R/W - 0h
R/W - 0h
R/W - 0h
R/W - 0h
11
10
9
8
0
0
0
1
R/W - 0h
R/W - 0h
R/W - 0h
R/W - 1h
3
2
1
0
CLIP_MODE_O CLIP_MODE_T CLIP_MODE_N CLIP_MODE_F
FFSET
EMP
L
C
R/W - 0h
R/W - 0h
R/W - 0h
R/W - 0h
Table 99. Register 50 Field Descriptions
Bit
Field
Type
Reset
23
RESERVED
R/W
0h
Always read or write 0h.
22
OVERRIDE_CLKGEN_RE
G
R/W
0h
Setting this register to 1 allows user to independently control
DEALIAS_FREQ, DEALIAS_EN.
RESERVED
R/W
3
CLIP_MODE_OFFSET
R/W
0h
Chooses either clipping or wrap around when applying offset correction for
phase.
0: Wrap around | 1: Clip
2
CLIP_MODE_TEMP
R/W
0h
Chooses either clipping or wrap around when applying temperature
correction for phase.
0: Wrap around | 1: Clip
1
CLIP_MODE_NL
R/W
0h
Chooses either clipping or wrap around when applying nonlinearity
correction for phase.
0: Wrap around | 1: Clip
0
CLIP_MODE_FC
R/W
0h
Chooses clipping or wrap around when applying freq-correction for phase.
0: Wrap around | 1: Clip
21:4
Description
2 0010h Always read or write 2 0010h.
7.5.1.1.70 Register 51h (Address = 51h) [reset = 0h]
70
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Figure 98. Register 51h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_ILLUM_HDR1_TX0[11:4]
R/W - 0h
12
11
PHASE_OFFSET_HDR1_TX0
R/W - 0h
4
3
PHASE_OFFSET_HDR1_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 100. Register 51 Field Descriptions
Bit
Field
Type
Reset
Description
23:16
TEMP_COEFF_ILLUM_HD
R1_TX0[11:4]
R/W
0h
Phase temperature coefficient of illumination source connected to TX0 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_H_TX0.
15:0
PHASE_OFFSET_HDR1_T
X0
R/W
0h
Phase offset for TX0 illumination channel with current of
ILLUM_DAC_H_TX0
7.5.1.1.71 Register 52h (Address = 52h) [reset = 0h]
Figure 99. Register 52h
23
15
22
21
TEMP_COEFF_ILLUM_HDR1_TX0[3:0]
R/W - 0h
14
13
7
6
5
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
12
11
PHASE_OFFSET_HDR0_TX1
R/W - 0h
4
3
PHASE_OFFSET_HDR0_TX1
R/W - 0h
Table 101. Register 52 Field Descriptions
Bit
Field
Type
Reset
Description
23:20
TEMP_COEFF_ILLUM_HD
R1_TX0[3:0]
R/W
0h
Phase temperature coefficient of illumination source connected to TX0 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_H_TX0.
15:0
PHASE_OFFSET_HDR0_T
X1
R/W
0h
Phase offset for TX1 illumination channel with current of
ILLUM_DAC_L_TX1
7.5.1.1.72 Register 53h (Address = 53h) [reset = 0h]
Figure 100. Register 53h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_ILLUM_HDR0_TX1[11:4]
R/W - 0h
12
11
PHASE_OFFSET_HDR1_TX1
R/W - 0h
4
3
PHASE_OFFSET_HDR1_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
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Table 102. Register 53 Field Descriptions
Bit
Field
Type
Reset
Description
23:16
TEMP_COEFF_ILLUM_HD
R0_TX1[11:4]
R/W
0h
Phase temperature coefficient of illumination source connected to TX1 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_L_TX1.
15:0
PHASE_OFFSET_HDR1_T
X1
R/W
0h
Phase offset for TX1 illumination channel with current of
ILLUM_DAC_H_TX1
7.5.1.1.73 Register 54h (Address = 54h) [reset = 0h]
Figure 101. Register 54h
23
15
22
21
TEMP_COEFF_ILLUM_HDR0_TX1[3:0]
R/W - 0h
14
13
7
6
5
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
12
11
PHASE_OFFSET_HDR0_TX2
R/W - 0h
4
3
PHASE_OFFSET_HDR0_TX2
R/W - 0h
Table 103. Register 54 Field Descriptions
Bit
Field
Type
Reset
Description
23:20
TEMP_COEFF_ILLUM_HD
R0_TX1[3:0]
R/W
0h
Phase temperature coefficient of illumination source connected to TX1 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_L_TX1.
19:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
PHASE_OFFSET_HDR0_T
X2
R/W
0h
Phase offset for TX2 illumination channel with current of
ILLUM_DAC_L_TX2
7.5.1.1.74 Register 55h (Address = 55h) [reset = 0h]
Figure 102. Register 55h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_ILLUM_HDR1_TX1[11:4]
R/W - 0h
12
11
PHASE_OFFSET_HDR1_TX2
R/W - 0h
4
3
PHASE_OFFSET_HDR1_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 104. Register 55 Field Descriptions
Bit
72
Field
Type
Reset
Description
23:16
TEMP_COEFF_ILLUM_HD
R1_TX1[11:4]
R/W
0h
Phase temperature coefficient of illumination source connected to TX1 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_H_TX1.
15:0
PHASE_OFFSET_HDR1_T
X2
R/W
0h
Phase offset for TX2 illumination channel with current of
ILLUM_DAC_H_TX2
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7.5.1.1.75 Register 56h (Address = 56h) [reset = 0h]
Figure 103. Register 56h
23
22
21
TEMP_COEFF_ILLUM_HDR1_TX1[3:0]
15
14
13
7
6
5
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
12
11
PHASE2_OFFSET_HDR1_TX0
R/W - 0h
4
3
PHASE2_OFFSET_HDR1_TX0
R/W - 0h
Table 105. Register 56 Field Descriptions
Bit
Field
Type
Reset
Description
23:20
TEMP_COEFF_ILLUM_HD
R1_TX1[3:0]
R/W
0h
Phase temperature coefficient of illumination source connected to TX1 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_H_TX1.
19:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
PHASE2_OFFSET_HDR1_
TX0
R/W
0h
De-alias frequency phase offset for TX0 illumination channel with current of
ILLUM_DAC_H_TX0
7.5.1.1.76 Register 57h (Address = 57h) [reset = 0h]
Figure 104. Register 57h
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_ILLUM_HDR0_TX2[11:4]
R/W - 0h
12
11
PHASE2_OFFSET_HDR0_TX1
R/W - 0h
4
3
PHASE2_OFFSET_HDR0_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 106. Register 57 Field Descriptions
Bit
Field
Type
Reset
Description
23:16
TEMP_COEFF_ILLUM_HD
R0_TX2[11:4]
R/W
0h
Phase temperature coefficient of illumination source connected to TX2 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_L_TX2.
15:0
PHASE2_OFFSET_HDR0_
TX1
R/W
0h
De-alias frequency phase offset for TX1 illumination channel with current of
ILLUM_DAC_L_TX1
7.5.1.1.77 Register 58h (Address = 58h) [reset = 0h]
Figure 105. Register 58h
23
22
21
TEMP_COEFF_ILLUM_HDR0_TX2[3:0]
15
14
13
7
6
5
20
19
12
11
PHASE2_OFFSET_HDR1_TX1
4
3
PHASE2_OFFSET_HDR1_TX1
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
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Table 107. Register 58 Field Descriptions
Bit
Field
Type
Reset
Description
23:20
TEMP_COEFF_ILLUM_HD
R0_TX2[3:0]
R/W
0h
Phase temperature coefficient of illumination source connected to TX2 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_L_TX2.
19:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
PHASE2_OFFSET_HDR1_
TX1
R/W
0h
De-alias frequency phase offset for TX1 illumination channel with current of
ILLUM_DAC_H_TX1
7.5.1.1.78 Register 59h (Address = 59h) [reset = 0h]
Figure 106. Register 59h
23
22
21
15
14
13
7
6
20
19
TEMP_COEFF_ILLUM_HDR1_TX2[11:4]
R/W - 0h
12
11
PHASE2_OFFSET_HDR0_TX2
R/W - 0h
4
3
PHASE2_OFFSET_HDR0_TX2
R/W - 0h
5
18
17
16
10
9
8
2
1
0
Table 108. Register 59 Field Descriptions
Bit
Field
Type
Reset
Description
23:16
TEMP_COEFF_ILLUM_HD
R1_TX2[11:4]
R/W
0h
Phase temperature coefficient of illumination source connected to TX2 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_H_TX2.
15:0
PHASE2_OFFSET_HDR0_
TX2
R/W
0h
De-alias frequency phase offset for TX2 illumination channel with current of
ILLUM_DAC_L_TX2
7.5.1.1.79 Register 5Ah (Address = 5Ah) [reset = 0h]
Figure 107. Register 5Ah
23
22
21
TEMP_COEFF_ILLUM_HDR1_TX2[3:0]
15
14
13
7
6
5
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
12
11
PHASE2_OFFSET_HDR1_TX2
R/W - 0h
4
3
PHASE2_OFFSET_HDR1_TX2
R/W - 0h
Table 109. Register 5A Field Descriptions
Bit
74
Field
Type
Reset
Description
23:20
TEMP_COEFF_ILLUM_HD
R1_TX2[3:0]
R/W
0h
Phase temperature coefficient of illumination source connected to TX2 pin
with external temperature sensor (TILLUM) for current of
ILLUM_DAC_H_TX2.
19:16
RESERVED
R/W
0h
Always read or write 0h.
15:0
PHASE2_OFFSET_HDR1_
TX2
R/W
0h
De-alias frequency phase offset for TX2 illumination channel with current of
ILLUM_DAC_H_TX2
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7.5.1.1.80 Register 5Bh (Address = 5Bh) [reset = 0h]
Figure 108. Register 5Bh
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX1
R/W - 0h
13
12
11
10
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX1
R/W - 0h
5
4
3
2
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX0
R/W - 0h
17
16
9
8
1
0
Table 110. Register 5B Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_ILLUM_XT
ALK_IPHASE_HDR1_TX1
Description
R/W
0h
Temperature coefficient of crosstalk in-phase component with TILLUM for
TX1 channel with ILLUM_DAC_H_TX1 current.
15:8
TEMP_COEFF_ILLUM_XT
ALK_IPHASE_HDR0_TX1
R/W
0h
Temperature coefficient of crosstalk in-phase component with TILLUM for
TX1 channel with ILLUM_DAC_L_TX1 current.
7:0
TEMP_COEFF_ILLUM_XT
ALK_IPHASE_HDR1_TX0
R/W
0h
Temperature coefficient of crosstalk in-phase component with TILLUM for
TX0 channel with ILLUM_DAC_H_TX0 current.
7.5.1.1.81 Register 5Ch (Address = 5Ch) [reset = 0h]
Figure 109. Register 5Ch
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX0
R/W - 0h
13
12
11
10
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX2
R/W - 0h
5
4
3
2
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX2
R/W - 0h
17
16
9
8
1
0
Table 111. Register 5C Field Descriptions
Bit
Field
Type
Reset
Description
23:16
TEMP_COEFF_ILLUM_XT
ALK_QPHASE_HDR1_TX0
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TILLUM for TX0 channel with ILLUM_DAC_H_TX0 current.
15:8
TEMP_COEFF_ILLUM_XT
ALK_IPHASE_HDR1_TX2
R/W
0h
Temperature coefficient of crosstalk in-phase component with TILLUM for
TX2 channel with ILLUM_DAC_H_TX2 current.
7:0
TEMP_COEFF_ILLUM_XT
ALK_IPHASE_HDR0_TX2
R/W
0h
Temperature coefficient of crosstalk in-phase component with TILLUM for
TX2 channel with ILLUM_DAC_H_TX2 current.
7.5.1.1.82 Register 5Dh (Address = 5Dh) [reset = 0h]
Figure 110. Register 5Dh
23
22
15
14
21
20
19
18
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX2
R/W - 0h
13
12
11
10
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX1
R/W - 0h
17
16
9
8
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5
4
3
2
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX1
R/W - 0h
1
0
Table 112. Register 5D Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_ILLUM_XT
ALK_QPHASE_HDR0_TX2
Description
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TILLUM for TX2 channel with ILLUM_DAC_L_TX2 current.
15:8
TEMP_COEFF_ILLUM_XT
ALK_QPHASE_HDR1_TX1
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TILLUM for TX1 channel with ILLUM_DAC_H_TX1 current.
7:0
TEMP_COEFF_ILLUM_XT
ALK_QPHASE_HDR0_TX1
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TILLUM for TX1 channel with ILLUM_DAC_L_TX1 current.
7.5.1.1.83 Register 5Eh (Address = 5Eh) [reset = 0h]
Figure 111. Register 5Eh
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_XTALK_IPHASE_HDR0_TX1
R/W - 0h
13
12
11
10
TEMP_COEFF_XTALK_IPHASE_HDR1_TX0
R/W - 0h
5
4
3
2
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX2
R/W - 0h
17
16
9
8
1
0
Table 113. Register 5E Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_XTALK_IP
HASE_HDR0_TX1
Description
R/W
0h
Temperature coefficient of crosstalk in-phase component with TMAIN for
TX1 channel with ILLUM_DAC_L_TX1 current
15:8
TEMP_COEFF_XTALK_IP
HASE_HDR1_TX0
R/W
0h
Temperature coefficient of crosstalk in-phase component with TMAIN for
TX0 channel with ILLUM_DAC_H_TX0 current
7:0
TEMP_COEFF_ILLUM_XT
ALK_QPHASE_HDR1_TX2
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TILLUM for TX2 channel with ILLUM_DAC_H_TX2 current.
7.5.1.1.84 Register 5Fh (Address = 5Fh) [reset = 0h]
Figure 112. Register 5Fh
23
22
21
15
14
13
7
6
5
20
19
TEMP_COEFF_XTALK_IPHASE_HDR1_TX2
R/W - 0h
12
11
TEMP_COEFF_XTALK_IPHASE_HDR0_TX2
R/W - 0h
4
3
TEMP_COEFF_XTALK_IPHASE_HDR1_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 114. Register 5F Field Descriptions
Bit
76
Field
Type
Reset
Description
23:16
TEMP_COEFF_XTALK_IP
HASE_HDR1_TX2
R/W
0h
Temperature coefficient of crosstalk in-phase component with TMAIN for
TX2 channel with ILLUM_DAC_H_TX2 current
15:8
TEMP_COEFF_XTALK_IP
HASE_HDR0_TX2
R/W
0h
Temperature coefficient of crosstalk in-phase component with TMAIN for
TX2 channel with ILLUM_DAC_L_TX2 current
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Table 114. Register 5F Field Descriptions (continued)
Bit
Field
Type
Reset
7:0
TEMP_COEFF_XTALK_IP
HASE_HDR1_TX1
R/W
0h
Description
Temperature coefficient of crosstalk in-phase component with TMAIN for
TX1 channel with ILLUM_DAC_H_TX1 current
7.5.1.1.85 Register 60h (Address = 60h) [reset = 0h]
Figure 113. Register 60h
23
22
15
14
7
6
21
20
19
18
TEMP_COEFF_XTALK_QPHASE_HDR1_TX1
R/W - 0h
13
12
11
10
TEMP_COEFF_XTALK_QPHASE_HDR0_TX1
R/W - 0h
5
4
3
2
TEMP_COEFF_XTALK_QPHASE_HDR1_TX0
17
16
9
8
1
0
R/W - 0h
Table 115. Register 60 Field Descriptions
Bit
Field
Type
Reset
23:16
TEMP_COEFF_XTALK_QP
HASE_HDR1_TX1
Description
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TMAIN for TX1 channel with ILLUM_DAC_H_TX1 current
15:8
TEMP_COEFF_XTALK_QP
HASE_HDR0_TX1
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TMAIN for TX1 channel with ILLUM_DAC_L_TX1 current
7:0
TEMP_COEFF_XTALK_QP
HASE_HDR1_TX0
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TMAIN for TX0 channel with ILLUM_DAC_H_TX0 current
7.5.1.1.86 Register 61h (Address = 61h) [reset = 0h]
Figure 114. Register 61h
23
22
21
20
19
18
17
16
12
11
10
TEMP_COEFF_XTALK_QPHASE_HDR1_TX2
R/W - 0h
4
3
2
TEMP_COEFF_XTALK_QPHASE_HDR0_TX2
R/W - 0h
9
8
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
Table 116. Register 61 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:8
TEMP_COEFF_XTALK_QP
HASE_HDR1_TX2
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TMAIN for TX2 channel with ILLUM_DAC_H_TX2 current
7:0
TEMP_COEFF_XTALK_QP
HASE_HDR0_TX2
R/W
0h
Temperature coefficient of crosstalk quadrature-phase component with
TMAIN for TX2 channel with ILLUM_DAC_L_TX2 current
7.5.1.1.87 Register 64h (Address = 64h) [reset = 280C00h]
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Figure 115. Register 64h
23
21
15
22
PROG_OVLDET_REFM
R/W - 1h
14
7
6
5
20
19
PROG_OVLDET_REFP
R/W - 2h
12
11
RESERVED
R/W - 0Ch
4
3
RESERVED
R/W - 0h
13
18
17
16
RESERVED
R/W - 0h
10
9
8
2
1
0
Table 117. Register 64 Field Descriptions
Bit
Field
Type
Reset
Description
23:21
PROG_OVLDET_REFM
R/W
1h
Program overload comparator threshold
0: Default | 1: 100 mV | 2: 200 mV | Other values: Not valid
20:18
PROG_OVLDET_REFP
R/W
2h
Program overload comparator threshold
0: Default | 2: –100 mV | Other values: Not valid
17:0
RESERVED
R/W
0C00h
Always read or write 0C00h.
7.5.1.1.88 Register 65h (Address = 65h) [reset = 0h]
Figure 116. Register 65h
23
DIS_OVLDET
R/W - 0h
15
22
21
14
13
7
6
5
20
19
RESERVED
R/W - 0h
12
11
RESERVED
R/W - 0h
4
3
RESERVED
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 118. Register 65 Field Descriptions
Bit
Field
Type
Reset
23
DIS_OVLDET
R/W
0h
Disables AFE overload detection.
0: AFE overload detection is enabled. | 1: AFE overload detection is
disabled.
RESERVED
R/W
0h
Always read or write 0h.
22:0
Description
7.5.1.1.89 Register 6Eh (Address = 6Eh) [reset = 20000h]
Figure 117. Register 6Eh
23
22
21
RESERVED
R/W - 0h
78
15
14
13
7
6
5
20
19
EN_TEMP_CO
NV
R/W - 0h
12
11
RESERVED
R/W - 0h
4
3
RESERVED
R/W - 0h
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18
17
RESERVED
16
10
R/W - 2h
9
8
2
1
0
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Table 119. Register 6E Field Descriptions
Bit
23:20
19
18:0
Field
Type
Reset
RESERVED
R/W
0h
Description
Always read or write 0h.
EN_TEMP_CONV
R/W
0h
Enable temperature sensor conversion
0: Temperature conversion is disabled. | 1: Temperature conversion is
enabled.
RESERVED
R/W
2 0000h Always read or write 2 0000h.
7.5.1.1.90 Register 71h (Address = 71h) [reset = 0h]
Figure 118. Register 71h
23
22
21
20
19
18
17
UNMASK_ILLU
MEN_INTXTAL
K
R/W - 0h
16
EN_ILLUM_CL
K_GPIO
11
INVERT_AFE_
CLK
10
RESERVED
9
INVERT_TG_C
LK
R/W - 0h
1
DEALIAS_EN
8
SHUT_CLOCK
S
R/W - 0h
0
RESERVED
R/W - 0h
R/W - 0h
RESERVED
R/W - 0h
15
ILLUM_CLK_G
PIO_MODE
R/W - 0h
7
RESERVED
14
13
12
RESERVED
DIS_ILLUM_CL
K_TX
R/W - 0h
R/W - 0h
6
5
4
SHIFT_ILLUM_PHASE
R/W - 0h
3
R/W - 0h
R/W - 0h
2
DEALIAS_FRE
Q
R/W - 0h
R/W - 0h
Table 120. Register 71 Field Descriptions
Bit
Field
Type
Reset
RESERVED
R/W
0h
Always read or write 0h.
17
UNMASK_ILLUMEN_INTX
TALK
R/W
0h
Mask or unmask ILLUM_EN_TX0 going to GPIO with internal crosstalk
signal
0: ILLUM_EN_TX0 is masked with internal crosstalk correction signal
1: ILLUM_EN_TX0 is not masked with internal crosstalk correction signal
16
EN_ILLUM_CLK_GPIO
R/W
0h
Enable ILLUM CLK going to GPIO
0: Illumination clock to GPIO is disabled. | 1: Illumination clock to GPIO is
enabled.
15
ILLUM_CLK_GPIO_MODE
R/W
0h
Disable ILLUM_EN_TX0 gating ILLUM_CLK going to GPIO.
0: ILLUM_CLK comes on GPIO only when ILLUM_EN (TG signal) is high |
1: ILLUM_CLK alive always
RESERVED
R/W
0h
Always read or write 0h.
12
DIS_ILLUM_CLK_TX
R/W
0h
Disable ILLUM_CLK going to transmitter
0: Clock to illumination driver is enabled. | 1: Clock to illumination driver is
disabled
11
INVERT_AFE_CLK
R/W
0h
Invert CLK input to AFE.
0: AFE CLK is not inverted | 1: AFE CLK is inverted.
10
RESERVED
R/W
0h
Always read or write 0h.
9
INVERT_TG_CLK
R/W
0h
Invert CLK input to timing generation unit.
0: TG CLK is not inverted | 1: TG CLK is inverted.
8
SHUT_CLOCKS
R/W
0h
Shut down all CLK signals at modulation frequency.
0: Modulation clocks is alive | 1: Modulation clock is shut down.
7
RESERVED
R/W
0h
Always read or write 0h.
SHIFT_ILLUM_PHASE
R/W
0h
Shift the phase of ILLUM_CLK.
PHASE = SHIFT_ILLUM_PHASE × 22.5°.
2
DEALIAS_FREQ
R/W
0h
Select modulation frequency when DEALIAS_EN = 1. This register works
only when OVERRIDE_CLKGEN_REG = 1.
0: 10 × (6 / 7) MHz | 1: 10 × (6 / 5) MHz
1
DEALIAS_EN
R/W
0h
Change the modulation frequency. This register works only when
OVERRIDE_CLKGEN_REG = 1.
23:18
14:13
6:3
Description
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Table 120. Register 71 Field Descriptions (continued)
Bit
0
Field
Type
Reset
RESERVED
R/W
0h
Description
Always read or write 0h.
7.5.1.1.91 Register 72h (Address = 72h) [reset = C0h]
Figure 119. Register 72h
23
22
21
20
19
18
17
16
11
10
9
8
3
2
1
0
RESERVED
R/W - 0h
15
14
13
12
RESERVED
R/W - 0h
7
6
5
IAMB_MAX_SEL
R/W - Ch
4
RESERVED
R/W - 0h
Table 121. Register 72 Field Descriptions
Bit
Field
Type
Reset
23:8
RESERVED
R/W
0h
Description
Always read or write 0h.
7:4
IAMB_MAX_SEL
R/W
Ch
Selects the value of ambient cancellation DAC resistor
0: 20 µA | 5: 10 µA | 10: 33 µA | 11: 50 µA | 12: 100 µA | 14: 200 µA | Other
values: Not valid.
3:0
RESERVED
R/W
0h
Always read or write 0h.
7.5.1.1.92 Register 76h (Address = 76h) [reset = 0h]
Figure 120. Register 76h
23
22
21
20
19
18
11
PDN_GLOBAL
10
RESERVED
17
16
RESERVED
R/W - 0h
15
14
13
12
RESERVED
7
RESERVED
R/W - 0h
R/W - 0h
6
5
DIS_GLB_PD_ DIS_GLB_PD_
AMB_ADC
AMB_DAC
R/W - 0h
R/W - 0h
4
DIS_GLB_PD_
AFE_DAC
R/W - 0h
R/W - 0h
3
DIS_GLB_PD_
AFE
R/W - 0h
9
DIS_GLB_PD_I
2CHOST
R/W - 0h
R/W - 0h
2
1
DIS_GLB_PD_I DIS_GLB_PD_
LLUM_DRV
TEMP_SENS
R/W - 0h
R/W - 0h
8
DIS_GLB_PD_
OSC
R/W - 0h
0
DIS_GLB_PD_
REFSYS
R/W - 0h
Table 122. Register 76 Field Descriptions
Bit
Field
Type
Reset
RESERVED
R/W
0h
Always read or write 0h.
11
PDN_GLOBAL
R/W
0h
Global power down of all the blocks.
0: Acitve | 1: Power down
10
RESERVED
R/W
0h
Always read or write 0h.
9
DIS_GLB_PD_I2CHOST
R/W
0h
Disable global power down of I2C host.
0: Enable global power down | 1: Disable global power down.
8
DIS_GLB_PD_OSC
R/W
0h
Disable global power down of main oscillator.
0: Enable global power down | 1: Disable global power down.
7
RESERVED
R/W
0h
Always read or write 0h.
6
DIS_GLB_PD_AMB_ADC
R/W
0h
Disable global power down of ambient ADC.
0: Enable global power down | 1: Disable global power down.
23:12
80
Description
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Table 122. Register 76 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
DIS_GLB_PD_AMB_DAC
R/W
0h
Disable global power down of ambient cancellation.
0: Enable global power down | 1: Disable global power down.
4
DIS_GLB_PD_AFE_DAC
R/W
0h
Disable global power down of AFE DAC.
0: Enable global power down | 1: Disable global power down.
3
DIS_GLB_PD_AFE
R/W
0h
Disable global power down of AFE.
0: Enable global power down | 1: Disable global power down.
2
DIS_GLB_PD_ILLUM_DRV
R/W
0h
Disable global power down of illumination driver.
0: Enable global power down | 1: Disable global power down.
1
DIS_GLB_PD_TEMP_SEN
S
R/W
0h
Disable global power down of temperature sensor.
0: Enable global power down | 1: Disable global power down.
0
DIS_GLB_PD_REFSYS
R/W
0h
Disable global power down of reference.
0: Enable global power down | 1: Disable global power down.
7.5.1.1.93 Register 77h (Address = 77h) [reset = 0h]
Figure 121. Register 77h
23
22
21
20
19
18
17
16
11
10
3
EN_DYN_PD_
AFE
R/W - 0h
2
EN_DYN_PD_I
LLUM_DRV
R/W - 0h
9
EN_DYN_PD_I
2CHOST_OSC
R/W - 0h
1
EN_DYN_PD_
TEMP_SENS
R/W - 0h
8
EN_DYN_PD_
OSC
R/W - 0h
0
EN_DYN_PD_
REFSYS
R/W - 0h
RESERVED
R/W - 0h
15
14
13
12
RESERVED
7
RESERVED
R/W - 0h
6
EN_DYN_PD_
AMB_ADC
R/W - 0h
R/W - 0h
5
4
EN_DYN_PD_ EN_DYN_PD_
AMB_DAC
AFE_DAC
R/W - 0h
R/W - 0h
Table 123. Register 77 Field Descriptions
Bit
Field
Type
Reset
RESERVED
R/W
0h
Always read or write 0h.
9
EN_DYN_PD_I2CHOST_O
SC
R/W
0h
Enable dynamic power down of I2C host oscillator.
0: Disable dynamic power down | 1: Enable dynamic power down.
8
EN_DYN_PD_OSC
R/W
0h
Enable dynamic power down of main oscillator.
0: Disable dynamic power down | 1: Enable dynamic power down.
7
RESERVED
R/W
0h
Always read or write 0h.
6
EN_DYN_PD_AMB_ADC
R/W
0h
Enable dynamic power down of ambient ADC.
0: Disable dynamic power down | 1: Enable dynamic power down.
5
EN_DYN_PD_AMB_DAC
R/W
0h
Enable dynamic power down of ambient cancellation.
0: Disable dynamic power down | 1: Enable dynamic power down.
4
EN_DYN_PD_AFE_DAC
R/W
0h
Enable dynamic power down of AFE DAC.
0: Disable dynamic power down | 1: Enable dynamic power down.
3
EN_DYN_PD_AFE
R/W
0h
Enable dynamic power down of AFE.
0: Disable dynamic power down | 1: Enable dynamic power down.
2
EN_DYN_PD_ILLUM_DRV
R/W
0h
Enable dynamic power down of illumination driver.
0: Disable dynamic power down | 1: Enable dynamic power down.
1
EN_DYN_PD_TEMP_SEN
S
R/W
0h
Enable dynamic power down of temperature sensor.
0: Disable dynamic power down | 1: Enable dynamic power down.
0
EN_DYN_PD_REFSYS
R/W
0h
Enable dynamic power down of reference.
0: Disable dynamic power down | 1: Enable dynamic power down.
23:10
Description
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7.5.1.1.94 Register 78h (Address = 78h) [reset = 0h]
Figure 122. Register 78h
23
RESERVED
22
21
SEL_GP3_ON_
SDAM
R/W - 0h
R/W - 0h
15
14
13
GPIO2_OBUF_
RESERVED
EN
R/W - 0h
R/W - 0h
7
6
5
GPO1_MUX_SEL
R/W - 0h
20
19
RESERVED
12
GPIO1_OBUF_
EN
R/W - 0h
4
RESERVED
R/W - 0h
R/W - 0h
11
18
17
10
GPO2_MUX_SEL
9
3
R/W - 0h
2
1
GPO3_MUX_SEL
R/W - 0h
16
GPIO2_IBUF_E
N
R/W - 0h
8
GPO1_MUX_S
EL
R/W - 0h
0
Table 124. Register 78 Field Descriptions
Bit
Field
Type
Reset
23
RESERVED
R/W
0h
Always read or write 0h.
22
SEL_GP3_ON_SDAM
R/W
0h
Select GP3 on SDA_M pin. This feature can be used when I2C host is not
used in the system. Pull up need to be present on SDA_M pin. To save
power the signal on this pin are inverted (active low).
RESERVED
R/W
0h
Always read or write 0h.
16
GPIO2_IBUF_EN
R/W
0h
Enable input buffer on GP2 pin. Used for reference CLK input.
0: Disable input buffer | 1: Enable input buffer.
15
GPIO2_OBUF_EN
R/W
0h
Enable output buffer on GP2 pin.
0: Disable output buffer | 1: Enable output buffer.
RESERVED
R/W
0h
Always read or write 0h.
12
GPIO1_OBUF_EN
R/W
0h
Enable output buffer on GP1 pin.
0: Disable output buffer | 1: Enable output buffer.
11:9
GPO2_MUX_SEL
R/W
0h
Select signal for the GP2 output multiplexer.
0: DVSS | 2: DIG_GPO_0 | 3: DIG_GPO_1 | 7: ILLUM_EN_TX0 | Other
values: Not valid.
8:6
GPO1_MUX_SEL
R/W
0h
Select signal for the GP1 output multiplexer.
0: DVSS | 2: DIG_GPO_0 | 3: DIG_GPO_1 | 7: ILLUM_CLK | Other values:
Not valid.
5:3
RESERVED
R/W
0h
Always read or write 0h.
2:0
GPO3_MUX_SEL
R/W
0h
Select signal for the GP3 output multiplexer.
0: DVSS | 2: DIG_GPO_0 | 3: DIG_GPO_1 | 7: DIG_GPO_2 | Other values:
Not valid.
21:17
14:13
Description
7.5.1.1.95 Register 79h (Address = 79h) [reset = 1h]
Figure 123. Register 79h
23
22
21
20
12
PDN_ILLUM_D
C_CURR
R/W - 0h
4
EN_TX_DC_C
URR_ALL
R/W - 0h
RESERVED
15
R/W - 0h
14
RESERVED
13
7
R/W - 0h
6
RESERVED
5
R/W - 0h
82
19
PDN_ILLUM_D
RV
R/W - 0h
11
3
SEL_ILLUM_T
X0_ON_TX1
R/W - 0h
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18
17
RESERVED
R/W - 0h
10
9
ILLUM_DC_CURR_DAC
R/W - 0h
2
1
EN_TX_CLKZ
RESERVED
R/W - 0h
R/W - 0h
16
8
0
EN_TX_CLKB
R/W - 1h
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Table 125. Register 79 Field Descriptions
Bit
Field
Type
Reset
RESERVED
R/W
0h
Always read or write 0.
PDN_ILLUM_DRV
R/W
0h
Test-mode bit to power down the illumination driver.
0: Illumination driver is active | 1: Illumination driver is powered down.
RESERVED
R/W
0h
Always read or write 0.
12
PDN_ILLUM_DC_CURR
R/W
0h
Power down the dc bias current through the TX pins.
0: Illumination dc bias current is active | 1: Illumination dc bias current is
powered down.
11:8
ILLUM_DC_CURR_DAC
R/W
0h
DC current through TX pin = 0.5 mA × ILLUM_DC_CURR_DAC
7:5
RESERVED
R/W
0h
Always read or write 0.
4
EN_TX_DC_CURR_ALL
R/W
0h
Enable dc current of all TX channels when TX0 is selected.
3
SEL_ILLUM_TX0_ON_TX1
R/W
0h
Use ILLUM_EN_TX0 for TX1. This mode is required to enable static
current-drive mode.
0: TX1 is controlled by SEL_TX_CH | 0: TX1 is selected when TX0 is
active.
2
EN_TX_CLKZ
R/W
0h
Enable inverted modulation CLK.
0: Inverted modulation clock is disabled | 1: Inverted modulation clock is
enabled.
1
RESERVED
R/W
0h
Always read or write 0.
0
EN_TX_CLKB
R/W
1h
Enable modulation CLK.
0: Modulation clock is disabled | 1: Modulation clock is enabled.
23:20
19
18:14
Description
7.5.1.1.96 Register 7Ah (Address = 7Ah) [reset = 0h]
Figure 124. Register 7Ah
23
22
21
20
19
18
17
16
11
10
9
8
RESERVED
R/W - 0h
15
14
13
12
RESERVED
R/W - 0h
7
6
RESERVED
R/W - 0h
5
4
TX0_PIN_CONFIG
R/W - 0h
3
2
TX2_PIN_CONFIG
R/W - 0h
1
0
TX1_PIN_CONFIG
R/W - 0h
Table 126. Register 7A Field Descriptions
Bit
Field
Type
Reset
Description
23:6
RESERVED
R/W
0h
Always read or write 0.
5:4
TX0_PIN_CONFIG
R/W
0h
Configure TX0 pin. 0: CLKB | 2: CLKZ | 3: 1 | Other values: Not valid
3:2
TX2_PIN_CONFIG
R/W
0h
Configure TX2 pin. 0: CLKB | 2: CLKZ | 3: 1 | Other values: Not valid
1:0
TX1_PIN_CONFIG
R/W
0h
Configure TX1 pin. 0: CLKB | 2: CLKZ | 3: 1 | Other values: Not valid
7.5.1.1.97 Register 80h (Address = 80h) [reset = 4E1Eh]
Figure 125. Register 80h
23
DIS_TG_ACON
F
R/W - 0h
15
22
21
20
19
18
17
10
9
RESERVED
14
13
R/W - 0h
12
11
SUB_VD_CLK_CNT
R/W - 4Eh
16
SUB_VD_CLK_
CNT
R/W - 0h
8
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4
SUB_VD_CLK_CNT
R/W - 0Fh
3
2
1
0
TG_EN
R/W - 0h
Table 127. Register 80 Field Descriptions
Bit
Field
Type
Reset
Description
DIS_TG_ACONF
R/W
0h
Disable automatic configuration of TG registers: TG_CAPTURE_MASK_*,
TG_OVL_WINDOW_MSAK*, TG_ILLUMEN_MASK*, TG_CALC_MASK*,
TG_DYNPDN_MASK*. If these TG signals must be configured by the user,
DIS_TG_ACONF should be set 1 to override the default settings of the
above mentioned TG signal registers.
22:17
RESERVED
R/W
0h
Always read or write 0h.
16:1
SUB_VD_CLK_CNT
R/W
270Fh
TG_EN
R/W
0h
23
0
The number of TG clocks in a sub-frame.
Enable the timing generation unit.
0: TG is disabled | 1: TG is enabled.
7.5.1.1.98 Register 83h (Address = 83h) [reset = D0h]
Figure 126. Register 83h
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
TG_AFE_RST_START
R/W - 00h
4
3
TG_AFE_RST_START
R/W - D0h
Table 128. Register 83 Field Descriptions
Bit
Field
Type
Reset
23:16
RESERVED
R/W
0h
15:0
TG_AFE_RST_START
R/W
D0h
Description
Always read or write 0h.
This register defines the starting position of AFE data-path reset TG signal
in the number of TG CLKs (tCLK) in a sub-frame.
Pulse duration of this reset signal is (TG_AFE_RST_END –
TG_AFE_RST_START) × tCLK.
7.5.1.1.99 Register 84h (Address = 84h) [reset = D8h]
Figure 127. Register 84h
23
22
21
20
19
18
17
16
12
11
TG_AFE_RST_END
R/W - 00h
4
3
TG_AFE_RST_END
R/W - D8h
10
9
8
2
1
0
RESERVED
R/W - 0h
84
15
14
13
7
6
5
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Table 129. Register 84 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_AFE_RST_END
R/W
D8h
Description
Always read or write 0h.
This register defines the ending position of the AFE data-path reset TG
signal in the number of TG clocks (tCLK) in a sub-frame.
7.5.1.1.100 Register 85h (Address = 85h) [reset = 20h]
Figure 128. Register 85h
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
TG_SEQ_INT_START
R/W - 00h
4
3
TG_SEQ_INT_START
R/W - 20h
Table 130. Register 85 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
TG_SEQ_INT_START
R/W
20h
Starting position of the sequencer interrupt TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.101 Register 86h (Address = 86h) [reset = 28h]
Figure 129. Register 86h
23
22
21
20
19
18
17
16
12
11
TG_SEQ_INT_END
R/W - 00h
4
3
TG_SEQ_INT_END
R/W - 28h
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
Table 131. Register 86 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
TG_SEQ_INT_END
R/W
28h
Ending position of the sequencer interrupt TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.102 Register 87h (Address = 87h) [reset = 2454h]
Figure 130. Register 87h
23
22
21
20
19
18
17
16
11
10
9
8
RESERVED
R/W - 0h
15
14
13
12
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TG_CAPTURE_START
R/W - 24h
4
3
TG_CAPTURE_START
R/W - 54h
5
2
1
0
Table 132. Register 87 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_CAPTURE_START
R/W
2454h
Description
Always read or write 0h.
Starting position of the internal data capture TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.103 Register 88h (Address = 88h) [reset = 2648h]
Figure 131. Register 88h
23
22
21
20
19
18
17
16
12
11
TG_CAPTURE_END
R/W - 26h
4
3
TG_CAPTURE_END
R/W - 48h
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
Table 133. Register 88 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_CAPTURE_END
R/W
2648h
Description
Always read or write 0h.
Ending position of the internal data capture TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.104 Register 89h (Address = 89h) [reset = 3E8h]
Figure 132. Register 89h
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
TG_OVL_WINDOW_START
R/W - 03h
4
3
TG_OVL_WINDOW_START
R/W - E8h
Table 134. Register 89 Field Descriptions
Bit
86
Field
Type
Reset
23:16
RESERVED
R/W
0h
15:0
TG_OVL_WINDOW_STAR
T
R/W
3E8h
Description
Always read or write 0h.
Starting position of the AFE overload observation window TG signal in the
number of TG clocks (tCLK) in a sub-frame.
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7.5.1.1.105 Register 8Ah (Address = 8Ah) [reset = 1F40h]
Figure 133. Register 8Ah
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
TG_OVL_WINDOW_END
R/W - 1Fh
4
3
TG_OVL_WINDOW_END
R/W - 40h
Table 135. Register 8A Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_OVL_WINDOW_END
R/W
1F40h
Description
Always read or write 0h.
Ending position of the AFE overload observation window TG signal in the
number of TG clocks (tCLK) in a sub-frame.
7.5.1.1.106 Register 8Fh (Address = 8Fh) [reset = 0h]
Figure 134. Register 8Fh
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
TG_ILLUMEN_START
R/W - 0h
4
3
TG_ILLUMEN_START
R/W - 0h
Table 136. Register 8F Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
TG_ILLUMEN_START
R/W
0h
Starting position of the illumination enable TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.107 Register 90h (Address = 90h) [reset = 2134h]
Figure 135. Register 90h
23
22
21
20
19
18
17
16
12
11
TG_ILLUMEN_END
R/W - 21h
4
3
TG_ILLUMEN_END
R/W - 34h
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
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Table 137. Register 90 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_ILLUMEN_END
R/W
2134h
Description
Always read or write 0h.
Ending position of the illumination enable TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.108 Register 91h (Address = 91h) [reset = 2134h]
Figure 136. Register 91h
23
22
21
20
19
18
17
16
12
11
TG_CALC_START
R/W - 21h
4
3
TG_CALC_START
R/W - 34h
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
Table 138. Register 91 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_CALC_START
R/W
2134h
Description
Always read or write 0h.
Starting position of the calculation TG signal in the number of TG clocks
(tCLK) in a sub-frame.
7.5.1.1.109 Register 92h (Address = 92h) [reset = 2EE0h]
Figure 137. Register 92h
23
22
21
20
19
18
17
16
12
11
TG_CALC_END
R/W - 2Eh
4
3
TG_CALC_END
R/W - E0h
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
Table 139. Register 92 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_CALC_END
R/W
2EE0h
Description
Always read or write 0h.
Ending position of the calculation TG signal in the number of TG clocks
(tCLK) in a sub-frame.
7.5.1.1.110 Register 93h (Address = 93h) [reset = 0h]
Figure 138. Register 93h
23
22
21
20
19
18
17
16
11
10
9
8
RESERVED
R/W - 0h
15
88
14
13
12
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7
6
TG_DYNPDN_START
R/W - 0h
4
3
TG_DYNPDN_START
R/W - 0h
5
2
1
0
Table 140. Register 93 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
TG_DYNPDN_START
R/W
0h
Starting position of the dynamic power-down TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.111 Register 94h (Address = 94h) [reset = FFFFh]
Figure 139. Register 94h
23
22
21
20
19
18
17
16
12
11
TG_DYNPDN_END
R/W - FFh
4
3
TG_DYNPDN_END
R/W - FFh
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
Table 141. Register 94 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
TG_DYNPDN_END
R/W
FFFFh
Description
Always read or write 0h.
Ending position of the dynamic power-down TG signal in the number of TG
clocks (tCLK) in a sub-frame.
7.5.1.1.112 Register 97h (Address = 97h) [reset = 0h]
Figure 140. Register 97h
23
22
15
21
14
13
TG_SEQ_INT_MASK_END
R/W - 0h
6
5
7
20
19
TG_SEQ_INT_MASK_END
R/W - 0h
12
11
4
3
TG_SEQ_INT_MASK_START
R/W - 0h
18
17
10
9
TG_SEQ_INT_MASK_START
R/W - 0h
2
1
16
8
0
Table 142. Register 97 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TG_SEQ_INT_MASK_END
R/W
0h
Ending position of the sequencer interrupt TG signal mask in the number of
sub-frames in a frame.
11:0
TG_SEQ_INT_MASK_STA
RT
R/W
0h
Starting position of the sequencer interrupt TG signal mask in the number of
sub-frames in a frame. The TG signal exists between the START and END
sub-frames.
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7.5.1.1.113 Register 98h (Address = 98h) [reset = 0h]
Figure 141. Register 98h
23
22
15
21
14
13
TG_CAPTURE_MASK_END
R/W - 0h
6
5
7
20
19
TG_CAPTURE_MASK_END
R/W - 0h
12
11
4
3
TG_CAPTURE_MASK_START
R/W - 0h
18
17
10
9
TG_CAPTURE_MASK_START
R/W - 0h
2
1
16
8
0
Table 143. Register 98 Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TG_CAPTURE_MASK_EN
D
R/W
0h
Ending position of the internal data-capture TG signal mask in the number
of sub-frames in a frame. This register should be equal to
NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.
11:0
TG_CAPTURE_MASK_ST
ART
R/W
0h
Starting position of the internal data-capture TG signal mask in the number
of sub-frames in a frame. This register should be equal to
NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1. The TG signal
exists between the START and END sub-frames.
7.5.1.1.114 Register 99h (Address = 99h) [reset = 1h]
Figure 142. Register 99h
23
15
7
22
21
14
13
TG_OVL_WINDOW_MASK_END
R/W - 0h
6
5
20
19
TG_OVL_WINDOW_MASK_END
R/W - 0h
12
11
18
17
10
9
TG_OVL_WINDOW_MASK_START
R/W - 0h
4
3
2
1
TG_OVL_WINDOW_MASK_START
R/W - 0h
16
8
0
Table 144. Register 99 Field Descriptions
Bit
Field
Type
Reset
23:12
TG_OVL_WINDOW_MASK
_END
R/W
0h
Ending position of the AFE overload observation window TG signal mask in
the number of sub-frames in a frame. This register should be equal to
NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.
11:0
TG_OVL_WINDOW_MASK
_START
1h
Starting position of AFE overload observation window TG signal mask in the
number of sub-frames in a frame. The TG signal exists between the START
and END sub-frames. Write 0 to this register when DIS_TG_ACONF = 1
and EN_ADAPTIVE_HDR = 0, or 1 when DIS_TG_ACONF = 1 and
EN_ADAPTIVE_HDR = 1.
R/W
Description
7.5.1.1.115 Register 9Ch (Address = 9Ch) [reset = FFF000h]
Figure 143. Register 9Ch
23
15
90
22
21
14
13
TG_ILLUMEN_MASK_END
20
19
TG_ILLUMEN_MASK_END
R/W - FFh
12
11
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18
17
10
9
TG_ILLUMEN_MASK_START
16
8
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R/W - Fh
7
6
R/W - 0h
5
4
3
TG_ILLUMEN_MASK_START
R/W - 0h
2
1
0
Table 145. Register 9C Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TG_ILLUMEN_MASK_END
R/W
FFFh
Ending position of the illumination-enable TG signal mask in the number of
sub-frames in a frame. This register should be equal to
NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.
11:0
TG_ILLUMEN_MASK_STA
RT
R/W
0h
Starting position of the illumination-enable TG signal mask in the number of
sub-frames in a frame. The TG signal exists between the START and END
sub-frames.
7.5.1.1.116 Register 9Dh (Address = 9Dh) [reset = 0h]
Figure 144. Register 9Dh
23
22
15
21
14
13
TG_CALC_MASK_END
R/W - 0h
6
5
7
20
19
TG_CALC_MASK_END
R/W - 0h
12
11
4
3
TG_CALC_MASK_START
R/W - 0h
18
17
10
9
TG_CALC_MASK_START
R/W - 0h
2
1
16
8
0
Table 146. Register 9D Field Descriptions
Bit
Field
Type
Reset
Description
23:12
TG_CALC_MASK_END
R/W
0h
Ending position of the calculation TG signal mask in the number of subframes in a frame. This register should be equal to
NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.
11:0
TG_CALC_MASK_START
R/W
0h
Starting position of the calculation TG signal mask in the number of subframes in a frame. The TG signal exists between the START and END subframes. This register should be equal to NUM_AVG_SUB_FRAMES when
DIS_TG_ACONF = 1.
7.5.1.1.117 Register 9Eh (Address = 9Eh) [reset = 0h]
Figure 145. Register 9Eh
23
22
15
21
14
13
TG_DYNPDN_MASK_END
R/W - 0h
6
5
7
20
19
TG_DYNPDN_MASK_END
R/W - 0h
12
11
4
3
TG_DYNPDN_MASK_START
R/W - 0h
18
17
10
9
TG_DYNPDN_MASK_START
R/W - 0h
2
1
16
8
0
Table 147. Register 9E Field Descriptions
Bit
23:12
Field
Type
Reset
TG_DYNPDN_MASK_END
R/W
0h
Description
Ending position of the dynamic power-down TG signal mask in the number
of sub-frames in a frame. This register should be equal to
NUM_AVG_SUB_FRAMES when DIS_TG_ACONF = 1.
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Table 147. Register 9E Field Descriptions (continued)
Bit
Field
Type
Reset
11:0
TG_DYNPDN_MASK_STA
RT
R/W
0h
Description
Starting position of the dynamic power-down TG signal mask in the number
of sub-frames in a frame. The TG signal exists outside the
TG_DYNPDN_MASK_START and TG_DYNPDN_MASK_END sub-frames.
7.5.1.1.118 Register 9Fh (Address = 9Fh) [reset = 0h]
Figure 146. Register 9Fh
23
22
15
21
14
13
NUM_AVG_SUB_FRAMES
R/W - 0h
6
5
7
20
19
NUM_AVG_SUB_FRAMES
R/W - 0h
12
11
4
3
18
17
10
9
NUM_SUB_FRAMES
R/W - 0h
2
1
16
8
0
NUM_SUB_FRAMES
R/W - 0h
Table 148. Register 9F Field Descriptions
Bit
Field
Type
Reset
Description
23:12
NUM_AVG_SUB_FRAMES
R/W
0h
Specifies the number of sub-frames to be averaged in a frame.
Averaging sub-frames = NUM_AVG_SUB_FRAMES + 1.
11:0
NUM_SUB_FRAMES
R/W
0h
Total number of sub-frames in a frame. Each sub-frame is approximately
0.25 ms (SUB_VD_CLK_CNT × 25 ns)
Number of sub-frames in a frame = NUM_SUB_FRAMES + 1.
This number must be equal to or greater than NUM_AVG_SUB_FRAMES.
7.5.1.1.119 Register A0h (Address = A0h) [reset = 2198h]
Figure 147. Register A0h
23
22
21
20
19
18
17
16
11
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
7
6
13
12
CAPTURE_CLK_CNT
R/W - 21h
4
3
CAPTURE_CLK_CNT
R/W - 98h
5
Table 149. Register A0 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
15:0
CAPTURE_CLK_CNT
R/W
2198h
Description
Always read or write 0h.
Internal data capture position (number of TG clocks, tCLK) in a sub-frame.
7.5.1.1.120 Register A2h (Address = A2h) [reset = 0h]
92
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Figure 148. Register A2h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR0_TX1[15:8]
R/W - 0h
12
11
A0_COEFF_HDR1_TX0
R/W - 0h
4
3
A0_COEFF_HDR1_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 150. Register A2 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR0_TX1[15
:8]
Description
R/W
0h
MSB of third-order coefficient for square wave nonlinearity correction for
TX1 illumination channel with current of ILLUM_DAC_L_TX1.
15:0
A0_COEFF_HDR1_TX0
R/W
0h
Constant offset for square wave nonlinearity correction for TX0 illumination
channel with current of ILLUM_DAC_H_TX0.
7.5.1.1.121 Register A3h (Address = A3h) [reset = 0h]
Figure 149. Register A3h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR0_TX1[7:0]
R/W - 0h
12
11
A0_COEFF_HDR0_TX1
R/W - 0h
4
3
A0_COEFF_HDR0_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 151. Register A3 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR0_TX1[7:
0]
Description
R/W
0h
LSB of third-order coefficient for square wave nonlinearity correction for TX1
illumination channel with current of ILLUM_DAC_L_TX1.
15:0
A0_COEFF_HDR0_TX1
R/W
0h
Constant offset for square wave nonlinearity correction for TX1 illumination
channel with current of ILLUM_DAC_L_TX1.
7.5.1.1.122 Register A4h (Address = A4h) [reset = 0h]
Figure 150. Register A4h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR1_TX1[15:8]
R/W - 0h
12
11
A0_COEFF_HDR1_TX1
R/W - 0h
4
3
A0_COEFF_HDR1_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
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Table 152. Register A4 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR1_TX1[15
:8]
Description
R/W
0h
MSB of third order coefficient for square wave nonlinearity correction for
TX1 illumination channel with current of ILLUM_DAC_H_TX1.
15:0
A0_COEFF_HDR1_TX1
R/W
0h
Constant offset for square wave nonlinearity correction for TX1 illumination
channel with current of ILLUM_DAC_H_TX1.
7.5.1.1.123 Register A5h (Address = A5h) [reset = 0h]
Figure 151. Register A5h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR1_TX1[7:0]
R/W - 0h
12
11
A0_COEFF_HDR0_TX2
R/W - 0h
4
3
A0_COEFF_HDR0_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 153. Register A5 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR1_TX1[7:
0]
Description
R/W
0h
LSB of third-order coefficient for square wave nonlinearity correction for TX1
illumination channel with current of ILLUM_DAC_H_TX1.
15:0
A0_COEFF_HDR0_TX2
R/W
0h
Constant offset for square wave nonlinearity correction for TX2 illumination
channel with current of ILLUM_DAC_L_TX2.
7.5.1.1.124 Register A6h (Address = A6h) [reset = 0h]
Figure 152. Register A6h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR0_TX2[15:8]
R/W - 0h
12
11
A0_COEFF_HDR1_TX2
R/W - 0h
4
3
A0_COEFF_HDR1_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 154. Register A6 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR0_TX2[15
:8]
Description
R/W
0h
MSB of third-order coefficient for square wave nonlinearity correction for
TX2 illumination channel with current of ILLUM_DAC_L_TX2.
15:0
A0_COEFF_HDR1_TX2
R/W
0h
Constant offset for square wave nonlinearity correction for TX2 illumination
channel with current of ILLUM_DAC_H_TX2.
7.5.1.1.125 Register A7h (Address = A7h) [reset = 0h]
94
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Figure 153. Register A7h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR0_TX2[7:0]
R/W - 0h
12
11
A1_COEFF_HDR1_TX0
R/W - 0h
4
3
A1_COEFF_HDR1_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 155. Register A7 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR0_TX2[7:
0]
Description
R/W
0h
LSB of third-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_L_TX2.
15:0
A1_COEFF_HDR1_TX0
R/W
0h
First-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_H_TX0.
7.5.1.1.126 Register A8h (Address = A8h) [reset = 0h]
Figure 154. Register A8h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR1_TX2[15:8]
R/W - 0h
12
11
A1_COEFF_HDR0_TX1
R/W - 0h
4
3
A1_COEFF_HDR0_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 156. Register A8 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR1_TX2[15
:8]
Description
R/W
0h
MSB of third-order coefficient for square wave nonlinearity correction for
TX2 illumination channel with current of ILLUM_DAC_H_TX2.
15:0
A1_COEFF_HDR0_TX1
R/W
0h
First-order coefficient for square wave nonlinearity correction for TX1
illumination channel with current of ILLUM_DAC_L_TX1.
7.5.1.1.127 Register A9h (Address = A9h) [reset = 0h]
Figure 155. Register A9h
23
22
21
15
14
13
7
6
5
20
19
A3_COEFF_HDR1_TX2[7:0]
R/W - 0h
12
11
A1_COEFF_HDR1_TX1
R/W - 0h
4
3
A1_COEFF_HDR1_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
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Table 157. Register A9 Field Descriptions
Bit
Field
Type
Reset
23:16
A3_COEFF_HDR1_TX2[7:
0]
Description
R/W
0h
LSB of third-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_H_TX2.
15:0
A1_COEFF_HDR1_TX1
R/W
0h
First-order coefficient for square wave nonlinearity correction for TX1
illumination channel with current of ILLUM_DAC_H_TX1.
7.5.1.1.128 Register AAh (Address = AAh) [reset = 0h]
Figure 156. Register AAh
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR1_TX0[15:8]
R/W - 0h
12
11
A1_COEFF_HDR0_TX2
R/W - 0h
4
3
A1_COEFF_HDR0_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 158. Register AA Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR1_TX0[15
:8]
Description
R/W
0h
MSB of fourth-order coefficient for square wave nonlinearity correction for
TX0 illumination channel with current of ILLUM_DAC_H_TX0.
15:0
A1_COEFF_HDR0_TX2
R/W
0h
First-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_L_TX2.
7.5.1.1.129 Register ABh (Address = ABh) [reset = 0h]
Figure 157. Register ABh
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR1_TX0[7:0]
R/W - 0h
12
11
A1_COEFF_HDR1_TX2
R/W - 0h
4
3
A1_COEFF_HDR1_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 159. Register AB Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR1_TX0[7:
0]
Description
R/W
0h
LSB of fourth-order coefficient for square wave nonlinearity correction for
TX0 illumination channel with current of ILLUM_DAC_H_TX0.
15:0
A1_COEFF_HDR1_TX2
R/W
0h
First-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_H_TX2.
7.5.1.1.130 Register ACh (Address = ACh) [reset = 0h]
96
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Figure 158. Register ACh
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR0_TX1[15:8]
R/W - 0h
12
11
A2_COEFF_HDR1_TX0
R/W - 0h
4
3
A2_COEFF_HDR1_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 160. Register AC Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR0_TX1[15
:8]
Description
R/W
0h
MSB of fourth-order coefficient for square wave nonlinearity correction for
TX1 illumination channel with current of ILLUM_DAC_L_TX1.
15:0
A2_COEFF_HDR1_TX0
R/W
0h
Second-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_H_TX0.
7.5.1.1.131 Register ADh (Address = ADh) [reset = 0h]
Figure 159. Register ADh
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR0_TX1[7:0]
R/W - 0h
12
11
A2_COEFF_HDR0_TX1
R/W - 0h
4
3
A2_COEFF_HDR0_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 161. Register AD Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR0_TX1[7:
0]
Description
R/W
0h
LSB of fourth-order coefficient for square wave nonlinearity correction for
TX1 illumination channel with current of ILLUM_DAC_L_TX1.
15:0
A2_COEFF_HDR0_TX1
R/W
0h
Second-order coefficient for square wave nonlinearity correction for TX1
illumination channel with current of ILLUM_DAC_L_TX1.
7.5.1.1.132 Register AEh (Address = AEh) [reset = 0h]
Figure 160. Register AEh
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR1_TX1[15:8]
R/W - 0h
12
11
A2_COEFF_HDR1_TX1
R/W - 0h
4
3
A2_COEFF_HDR1_TX1
R/W - 0h
18
17
16
10
9
8
2
1
0
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Table 162. Register AE Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR1_TX1[15
:8]
Description
R/W
0h
MSB of fourth-order coefficient for square wave nonlinearity correction for
TX1 illumination channel with current of ILLUM_DAC_H_TX1.
15:0
A2_COEFF_HDR1_TX1
R/W
0h
Second-order coefficient for square wave nonlinearity correction for TX1
illumination channel with current of ILLUM_DAC_H_TX1.
7.5.1.1.133 Register AFh (Address = AFh) [reset = 0h]
Figure 161. Register AFh
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR1_TX1[7:0]
R/W - 0h
12
11
A2_COEFF_HDR0_TX2
R/W - 0h
4
3
A2_COEFF_HDR0_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 163. Register AF Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR1_TX1[7:
0]
Description
R/W
0h
LSB of fourth-order coefficient for square wave nonlinearity correction for
TX1 illumination channel with current of ILLUM_DAC_H_TX1.
15:0
A2_COEFF_HDR0_TX2
R/W
0h
Second-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_L_TX2.
7.5.1.1.134 Register B0h (Address = B0h) [reset = 0h]
Figure 162. Register B0h
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR0_TX2[15:8]
R/W - 0h
12
11
A2_COEFF_HDR1_TX2
R/W - 0h
4
3
A2_COEFF_HDR1_TX2
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 164. Register B0 Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR0_TX2[15
:8]
Description
R/W
0h
MSB of fourth-order coefficient for square wave nonlinearity correction for
TX2 illumination channel with current of ILLUM_DAC_L_TX2.
15:0
A2_COEFF_HDR1_TX2
R/W
0h
Second-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_H_TX2.
7.5.1.1.135 Register B1h (Address = B1h) [reset = 0h]
98
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Figure 163. Register B1h
23
22
21
15
14
13
7
6
5
20
19
A4_COEFF_HDR0_TX2[7:0]
R/W - 0h
12
11
A3_COEFF_HDR1_TX0
R/W - 0h
4
3
A3_COEFF_HDR1_TX0
R/W - 0h
18
17
16
10
9
8
2
1
0
Table 165. Register B1 Field Descriptions
Bit
Field
Type
Reset
23:16
A4_COEFF_HDR0_TX2[7:
0]
Description
R/W
0h
LSB byte of fourtt-order coefficient for square wave nonlinearity correction
for TX2 illumination channel with current of ILLUM_DAC_L_TX2.
15:0
A3_COEFF_HDR1_TX0
R/W
0h
Third-order coefficient for square wave nonlinearity correction for TX0
illumination channel with current of ILLUM_DAC_H_TX0.
7.5.1.1.136 Register B2h (Address = B2h) [reset = 0h]
Figure 164. Register B2h
23
22
21
20
19
18
17
16
10
9
8
2
1
0
RESERVED
R/W - 0h
15
14
13
7
6
5
12
11
A4_COEFF_HDR1_TX2
R/W - 0h
4
3
A4_COEFF_HDR1_TX2
R/W - 0h
Table 166. Register B2 Field Descriptions
Field
Type
Reset
23:16
Bit
RESERVED
R/W
0h
Description
Always read or write 0h.
15:0
A4_COEFF_HDR1_TX2
R/W
0h
Fourth-order coefficient for square wave nonlinearity correction for TX2
illumination channel with current of ILLUM_DAC_H_TX2.
7.5.1.1.137 Register B4h (Address = B4h) [reset = 0h]
Figure 165. Register B4h
23
22
21
15
14
13
7
6
5
20
19
AMB_PHASE_CORR_PWL_COEFF3
R/W - 0h
12
11
AMB_PHASE_CORR_PWL_COEFF2
R/W - 0h
4
3
AMB_PHASE_CORR_PWL_COEFF1
R/W - 0h
18
17
16
10
9
8
2
1
0
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Table 167. Register B4 Field Descriptions
Bit
Field
Type
Reset
23:16
AMB_PHASE_CORR_PWL
_COEFF3
Description
R/W
0h
Coefficient 3 for PWL phase correction with ambient.
15:8
AMB_PHASE_CORR_PWL
_COEFF2
R/W
0h
Coefficient 2 for PWL phase correction with ambient.
7:0
AMB_PHASE_CORR_PWL
_COEFF1
R/W
0h
Coefficient 1 for PWL phase correction with ambient.
7.5.1.1.138 Register B5h (Address = B5h) [reset = 0h]
Figure 166. Register B5h
23
22
21
20
19
18
17
16
11
10
9
8
3
2
1
0
SCALE_AMB_PHASE_CORR_COEFF
R/W - 0h
RESERVED
R/W - 0h
15
14
13
12
RESERVED
R/W - 0h
7
6
5
RESERVED
R/W - 0h
4
Table 168. Register B5 Field Descriptions
Bit
Field
Type
Reset
Description
23:3
RESERVED
R/W
0h
Always read or write 0h.
2:0
SCALE_AMB_PHASE_CO
RR_COEFF
R/W
0h
Scaling factor for ambient-based PWL phase correction.
7.5.1.1.139 Register B8h (Address = B8h) [reset = 7FDFFh]
Figure 167. Register B8h
23
22
RESERVED
15
R/W - 0h
14
7
6
21
20
19
GIVE_DEAL_D
ATA
R/W - 0h
13
12
11
AMB_PHASE_CORR_PWL_X1
R/W - 3Fh
5
4
3
AMB_PHASE_CORR_PWL_X0
R/W - FFh
18
17
AMB_PHASE_CORR_PWL_X1
16
R/W - 7h
10
2
9
8
AMB_PHASE_CORR_PWL_X0
R/W - 1h
1
0
Table 169. Register B8 Field Descriptions
Bit
Field
Type
Reset
RESERVED
R/W
0h
Always read or write 0h.
GIVE_DEALIAS_DATA
R/W
0h
When this register is set to 1, de-aliased phase is given out on
PHASE_OUT.
19:10
AMB_PHASE_CORR_PWL
_X1
R/W
1FFh
Second knee point of PWL phase correction with ambient.
9:0
AMB_PHASE_CORR_PWL
_X0
R/W
1FFh
First knee point of PWL phase correction with ambient.
23:21
20
100
Description
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7.5.1.1.140 Register B8h (Address = B9h) [reset = 1FFh]
Figure 168. Register B9h
23
22
ILLUM_SCALE_H_TX2
R/W - 0h
15
14
AMB_ADC_IN_TX1
R/W - 0h
7
6
21
20
19
18
ILLUM_SCALE_L_TX2
R/W - 0h
13
12
11
10
AMB_ADC_IN_TX0
EN_TX2_ON_T EN_TX1_ON_T
X0
X0
R/W - 0h
R/W - 0h
R/W - 0h
5
4
3
2
AMB_PHASE_CORR_PWL_X2
R/W - FFh
17
16
AMB_ADC_IN_TX2
R/W - 0h
9
8
AMB_PHASE_CORR_PWL_X2
R/W - 1h
1
0
Table 170. Register B9 Field Descriptions
Bit
Field
Type
Reset
Description
23:21
ILLUM_SCALE_H_TX2
R/W
0h
Current-scaling register for the illumination driver TX2 channel with DAC_H
current.
0: 5.6 mA | 1: 4.2 mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid
20:18
ILLUM_SCALE_L_TX2
R/W
0h
Current scaling register for the illumination driver TX2 channel with DAC_L
current.
0: 5.6 mA | 1: 4.2 mA | 2: 2.8 mA | 3: 1.4 mA | Other values: Not valid
17:16
AMB_ADC_IN_TX2
R/W
0h
Select ambient ADC input when TX2 channel is selected.
0: DACP - DACM | 1: DACP - REFP | 2: DACM - DACP | 3: DACM - REFM
15:14
AMB_ADC_IN_TX1
R/W
0h
Select ambient ADC input when TX1 channel is selected.
0: DACP - DACM | 1: DACP - REFP | 2: DACM - DACP | 3: DACM - REFM
13:12
AMB_ADC_IN_TX0
R/W
0h
Select ambient ADC input when TX0 channel is selected.
0: DACP - DACM | 1: DACP - REFP | 2: DACM - DACP | 3: DACM - REFM
11
EN_TX2_ON_TX0
R/W
0h
If this bit is 1 when TX2 is selected, the illumination driver current flows
through TX0.
10
EN_TX1_ON_TX0
R/W
0h
If this bit is 1 when TX1 is selected, the illumination driver current flows
through TX0.
9:0
AMB_PHASE_CORR_PWL
_X2
R/W
1FFh
Third knee point of PWL phase correction with ambient
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPT3101 AFE is a fully integrated analog front end with an integrated illumination driver for measuring
distance. The device interfaces an external photodiode and LED, VCSEL, or LASER. The device has an I2C
interface for the data output. An external MCU can read out the distance data from the device directly and no
computation is required on the external MCU. All the computation and corrections for crosstalk, phase offset,
temperature-dependent phase drift, and ambient-dependent phase drift are done on the chip. The device also
provides temperature output from the on-chip temperature sensor. It can operate up to a speed of 4000 sps in
non-HDR mode and 2000 sps in auto HDR mode.
8.2 Typical Application
Obstacle avoidance for autonomous vehicle navigation is a typical application which can be implemented using
this AFE. The system can be optimized to meet the application requirements by optimizing various parameters
like illumination current, sub-frame averaging, and auto HDR mode, which are explained in the following
sections. Figure 169 shows the interface between the OPT3101 device and an external MCU.
Figure 169. Typical Application Block Diagram
8.2.1 Design Requirements
Table 171 lists the application requirements for obstacle avoidance system.
Table 171. Application Specifications
SPECIFICATION
VALUE
UNITS
Minimum distance
0.3
m
Maximum distance
5
m
Distance accuracy
2
%
For an object with 18% reflectivity.
Sunlight condition
Ambient light
130
klx
Field of view
±3
degrees
Wavelength
850
nm
Sample rate
30
sps
Supply
3.3
V
102
COMMENTS
Infrared wavelength for illumination.
Single supply for the system
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8.2.2 Detailed Design Procedure
8.2.2.1 Sample Rate
The sample rate can be adjusted by programming the number of sub-frames in a frame. To meet the application
requirement of 30 sps, 128 sub-frame averaging can be used from Equation 1. Set the register
NUM_SUB_FRAME = 127 and NUM_AVG_SUB_FRAMES = 127, which gives a sample rate of 31.25 sps.
8.2.2.2 Photodiode and LED
OSRAM SFH4550 LED meets the required field of view specification and has peak spectral emission at
860 nm. Even though LED is specified for a half-angle of ±3 degrees, a significant amount of the optical power
will be outside the half-angle. Figure 170 shows the radiation characteristics of the LED. The photodiode should
have a field of view greater than the field of view of the LED to effectively collect all the optical power emitted
from the LED and reflected by the object. The photodiode should also have peak sensitivity matching the peak
spectral emission of the LED. Most of the photodiodes come in two variants;
• With a daylight filter, which has a very broad spectrum; example: SFH213
• Narrow-band IR spectrum; example: SFH213FA.
A photiode with a narrow-band IR filter should be selected as it collects a lower ambient signal. Photodiode
SFH213FA meets these requirements. This photodiode has a capacitance of 5.8 pF at 1-V reverse bias, which is
within the supported capacitance range of the AFE. Photodiode characterisitcs are shown in Figure 171 and
Figure 172
Figure 170. SFH4550 LED Radiation Characteristics
Figure 171. SFH213FA Photodiode Directional
Characteristics
Figure 172. SFH213FA Photodiode Reverse Bias
Capacitance
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8.2.2.3 Ambient Support
The photodiode has an IR filter centered at 900 nm as shown in Figure 173. The sunlight spectral irradiance
within the spectral bandwidth of the photodiode is also shown in the same figure. The total sunlight power with in
the spectral bandwidth of photodiode is 176 watts/m2. The ambient sunlight power received by the photodiode
can be calculated using Equation 9. Total ambient current for this photodiode is 49.2 µA. Accounting for
variations in reflectivity, the IAMB_MAX_SEL = 12 setting should be selected, which corresponds to 100-µA
ambient current support.
where
PAMB = Total ambient light power in the photodiode spectral bandwidth in W/m2
Ascene = Area covered by photodiode FoV
Ωlens = Solid angle from a point on target object to the photodiode lens
Ωsemi-sphere= 2π
•
•
•
•
(9)
where
•
φPD = Photodiode half-angle = 10° for SFH213FA
(10)
Figure 173. SFH213FA Photodiode Spectral Response and Sunlight Power Within Photodiode Spectral
Bandwidth
Table 172. Photodiode Specifications
PARAMETER
Photodiode current with 1 mW/cm
VALUE
2
Half-angle
UNIT
90
µA
±10
Degrees
COMMENTS
Photodiode specification
Total sunlight power in photodiode
spectral bandwidth falling on the object
175
W/m
Total power received at the photodiode
0.2736
mW/cm2
2
Photodiode specification
Calculated from sunlight spectra (see Figure 173)
Calculated using Equation 10
Ambient current
49.2
µA
Calculated from 0.2736 mW/cm2 × 90 µA/ (1
mW/cm2). An additional factor of 2 should be added to
account for the photodiode response outside the
specified half angle of ±10 degrees.
Reverse bias capacitance at VR = 1 V
5.8
pF
AFE supports a maximum capacitance of 6 pF.
104
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8.2.2.4 Distance Accuracy
For 30 sps operation, 128 sub-frames can be averaged to improve the noise performance by setting
NUM_SUB_FRAMES = 127 and NUM_AVG_SUB_FRAMES = 127. AFE noise with a 6-pF photodiode
capacitance and 100-µA ambient current support can be extracted from Figure 2 as 2.25 pA/√Hz. Total noise at
31.25 sps operation with the above settings is 12.6 pA. The minimum SNR required to meet the distance
accuracy of 2%, (10 cm at 5 m) can be calculated using Equation 6 as 23.8. So the minimum signal current
required is 12.6 pA × 23.8 = 300 pA. The photodiode current required to get a signal current of 300pA can be
calculated from Equation 11 as 720 pA. With a diode responsivity of 0.5 A/W, the optical power required is 720
pA / (0.5 A/W) = 1.44 nW. Illumination power required with an 18% reflective target can be calculated from
Equation 12 as 64 mW. The SFH4550 produces 70 mW of optical power for a current of 100 mA. From this, the
required illumination current can be calculated as 91.5 mA
where
•
•
•
IPD = Photodiode signal current.
ISIG_AFE = Signal current entering the AFE.
CPD = Photodiode capacitance at a reverse bias voltage of 1 V
(11)
Pr,sig = Signal power received by the photodiode
PLED = LED output power
R = Object reflectivity
Ωlens = Solid angle from a point on a target object to the photodiode lens
Ωsemi-sphere= 2π
(12)
Dlens = Diameter of the lens over the photodiode = 5 mm for SFH213FA
d = Object distance
(13)
where
•
•
•
•
•
where
•
•
Choose 100 mA as the illumination current for meeting the SNR requirement for the 18% reflective target at a 5m distance. With this illumination current, a 90% reflective object gives a signal current of 1.5 nA for an object at
5 m, and the AFE saturates for an object at a distance of 5 m / √(200 nA / 1.5nA) = 0.43 m. Because the
required minimum distance is lower than this, on-chip adaptive HDR should be used by setting
ENABLE_ADAPTIVE_HDR = 1, ILLUM_DAC_L_TX0 = 2 and ILLUM_DAC_H_TX0 = 20. HDR switching
thresholds can be set at HDR_THR_HIGH = 27 000 and HDR_THR_LOW = 27 000 / 10 / 1.2 = 2250.
8.2.2.5 Supply Voltage
Because the system must operate with a single supply, the OPT3101 device can be used in LDO mode, where
the required 1.8-V supplies AVDD and DVDD are generated by the device itself using an internal LDO. To
operate in this mode, connect the REG_MODE pin to the IOVDD supply (3.3 V).
8.2.3 Application Curves
Figure 174 and Figure 175 shows simulated received signal and distance standard deviation with object distance
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Figure 174. Received Signal vs Object Distance
Figure 175. Distance Standard Deviation vs Object
Distance
8.3 Initialization Set Up
After device power up, apply device reset by applying an active-low pulse of duration > 30 µs.
Write the following registers to set the device running in required condition.
• Write the NUM_SUB_FRAMES and NUM_AVG_SUB_FRAMES registers to set the device to operate at the
required sample rate.
• Select the maximum ambient current to be supported by writing IAMB_MAX_SEL.
• Enable adaptive HDR mode if required: EN_ADAPTIVE_HDR.
• Write illumination DAC currents ILLUM_DAC_L_TX0 and ILLUM_DAC_H_TX0.
• Program the adaptive HDR thresholds: HDR_THR_LOW and HDR_THR_HIGH.
• Load all the calibration settings: illumination crosstalk, phase offset, phase temperature coefficient, and phase
ambient coefficient.
• Enable frequency calibration if an external reference CLK is connected to GP2: EN_AUTO_FREQ_COUNT =
1, EN_FLOOP = 1, EN_FREQ_CORR = 1, SYS_CLK_DIVIDER = round(log2(40×106 / fEXT)),
REF_COUNT_LIMIT = 214 × (40×106 / 2SYS_CLK_DIV) / fEXT, EN_CONT_FCALIB = 1
• Enable on-chip temperature conversion: EN_TEMP_CONV = 1
• Write I2C host settings to read the external temperature sensor if it is present in the system. Register settings
are listed in Table 26.
• Enable the timing generator by setting TG_EN = 1
• Perform internal crosstalk correction by making INT_XTALK_CALIB = 1, followed by INT_XTALK_CALIB = 0.
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9 Power Supply Recommendations
The OPT3101 device requires 1.8-V and 3.3-V supplies. There are two 1.8-V supplies (AVDD and DVDD) and
two 3.3-V supplies (AVDD3 and IOVDD). AVDD and AVDD3 are analog supplies, DVDD and IOVDD are digital
and I/O supplies. VDD_LED is not a device pin, but the supply connecting to the anode of the LED (Illumination
source). The inimum voltage of the VDD_LED supply is 0.7 V (VDRV) + forward voltage drop of the LED at the
maximum illumination driver current (1.8-V typical for 850-nm LED with 100 mA) + IR drop across the series
elements (beads, PCB routing) in the supply (VDD_LED) – ground (VSSL) path. The transmitter and receiver of
the OPT3101 device operate at the same modulation frequency (10 MHz). Any coupling from the transmitter
switching to the AFE results in a crosstalk signal which affects the performance of the distance measurement.
Achieving the lowest possible crosstalk is critical for an accurate distance measurement system. Care should be
taken to isolate all analog and switching supplies. VDD_LED has the highest switching current at the modulation
frequency, fMOD. DVDD and IOVDD also have switching current at the modulation frequency, fMOD, but much
lower than VDD_LED. Use ferrite beads with the highest impedance at 10 MHz (> 500 Ω) in the series path of
the supplies and decoupling capacitors with low impedance at fMOD on the supplies very close to the device.
9.1 System With Off-Chip 1.8-V Regulator
Figure 176 shows the supply network with 1.8 V generated using an off-chip regulator. The REG_MODE pin of
the OPT3101 device should be connected to IOVSS in this mode. One external regulator can be used to
generate the 1.8-V supply and use beads to isolate AVDD and DVDD. The external regulator mode is useful only
when the on-chip regulator mode cannot meet the power-down-state current requirement. For example, in
systems where the sample rate is very low that are kept in the power-down state most of the time.
Figure 176. Power Supply Network in a System With External 1.8-V Regulator
9.2 System With On-Chip 1.8-V Regulator
Figure 177 shows the supply network with 1.8 V generated using the on-chip regulators. There are two
regulators, one each for AVDD and DVDD, with the input supply as AVDD3. Only decoupling capacitors need to
be placed on AVDD and DVDD supplies. All other supplies should have beads in the series path. The
REG_MODE pin of the OPT3101 device should be connected to IOVDD in this mode.
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System With On-Chip 1.8-V Regulator (continued)
Figure 177. Power Supply Network With On-Chip 1.8-V Regulator
10 Layout
10.1 Layout Guidelines
Reducing coupling between transmitter and receiver is very critical to achieve good system performance. The
area of the transmitter current-carrying loop through the LED supply decoupling capacitor, LED, and the AFE
pins TX* and VSSL should be minimized. Similarly, the receiver loop involving the photodiode, matching
capacitor, and the AFE pins INP and INM should be minimized.Figure 178 shows the transmitter and receiver
loops.
Figure 178. AFE Interface With Photodiode and LED
10.2 Layout Example
Layout of a system involving a 5-mm radial through-hole photodiode and LED is shown in Figure 179. The
following guidelines should be followed to keep the crosstalk between transmitter and receiver low.
• Use a four-layer board, so that all the analog and digital supplies can be well isolated from each other.
• Place the photodiode and LED oriented orthogonal to each other .
108
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Layout Example (continued)
•
•
•
•
•
•
•
•
Minimize the area of the transmitter current-carrying loop involving LED, VDD_LED-to-VSSL decoupling
capacitor, and AFE.
Minimize the area of the receiver loop involving the photodiode, matching capacitor, and AFE.
Shield the receiver loop using AVSS ground in the top and bottom PCB layers. Also place a shielding ring
around the photodiode and connect the shielding ring to AVSS. This shielding ring helps in reducing the
electrical and optical crosstalk.
Shield the transmitter loop using IOVSS ground in all the PCB layers. Also place a shielding ring around the
LED and connect the shielding ring to IOVSS.
LED terminals should not see the photodiode terminals directly. Any small amount of capacitive coupling
between photodiode and LED terminals results in huge crosstalk. Grounded metal rings around photodiode
and LED help in shielding.
Use vias around the transmitter and receiver loops in their respective ground planes to improve the shielding.
Connect the device thermal pad to AVSS.
Do not overlap different ground planes, keep them well isolated.
Figure 179. PCB Layout example
Figure 180. Ground Isolation Between AVSS and IOVSS in a Four-Layer PCB
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Layout Example (continued)
Figure 181. Photodiode and LED Placement on PCB
110
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• OPT3101 Distance Sensor System Calibration
• Introduction to Time-of-Flight Optical Proximity Sensor System Design
• OPT3101 Evaluation Module User's Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPT3101
111
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPT3101RHFR
ACTIVE
VQFN
RHF
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPT
3101
OPT3101RHFT
ACTIVE
VQFN
RHF
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPT
3101
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPT3101RHFR
VQFN
RHF
28
3000
330.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
OPT3101RHFT
VQFN
RHF
28
250
180.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPT3101RHFR
VQFN
RHF
28
3000
367.0
367.0
35.0
OPT3101RHFT
VQFN
RHF
28
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHF0028A
VQFN - 1.0 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
0.5
0.3
5.1
4.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2.55 0.1
2X 2.5
(0.2) TYP
9
EXPOSED
THERMAL PAD
14
24X 0.5
15
8
3.55 0.1
2X
3.5
29
SYMM
SEE TERMINAL
DETAIL
1
22
28X
PIN 1 ID
(OPTIONAL)
28
23
SYMM
28X
0.5
0.3
0.30
0.18
0.1
0.05
C A B
4220383/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHF0028A
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.55)
SYMM
28
23
28X (0.6)
22
1
28X (0.24)
(1.525)
(3.55)
24X (0.5)
29
SYMM
(4.8)
( 0.2) TYP
VIA
8
15
(R0.05)
TYP
9
14
(1.025)
(3.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220383/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHF0028A
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.13)
(0.665) TYP
23
28
28X (0.6)
22
1
28X (0.24)
(0.865)
TYP
24X (0.5)
SYMM
29
(4.8)
4X (1.53)
(R0.05) TYP
15
8
METAL
TYP
14
9
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 29
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4220383/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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