Texas Instruments | LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical Sensing Applications (Rev. B) | Datasheet | Texas Instruments LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical Sensing Applications (Rev. B) Datasheet

Texas Instruments LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical Sensing Applications (Rev. B) Datasheet
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LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical
Sensing Applications
1 Features
3 Description
•
•
•
•
•
The LMP91002 device is a programmable Analog
Front End (AFE) for use in micro-power
electrochemical-sensing applications. It provides a
complete signal path solution between a not biased
gas sensor and a microcontroller generating an
output voltage proportional to the cell current.
1
•
•
•
•
•
•
•
•
Typical Values, TA = 25°C
Supply Voltage 2.7 V to 3.6 V
Supply Current (Average Over Time) < 10 µA
Cell Conditioning Current Up to 10 mA
Reference Electrode Bias Current (85°C) 900-pA
(Maximum)
Output Drive Current 750 µA
Complete Potentiostat Circuit to Interface to Most
Not Biased Gas Sensors
Low Bias Voltage Drift
Programmable TIA Gain 2.75 kΩ to 350 kΩ
I2C-Compatible Digital Interface
Ambient Operating Temperature –40°C to 85°C
Package 14-pin WSON
Supported by Webench Sensor AFE Designer
The LMP91002’s programmability enables it support
not biased electro-chemical gas sensor with a single
design. The LMP91002 supports gas sensitivities
over a range of 0.5 nA/ppm to 9500 nA/ppm. It also
allows for an easy conversion of current ranges from
5 μA to 750 μA full scale. The LMP91002’s
transimpedance amplifier (TIA) gain is programmable
through the I2C interface. The I2C interface can also
be used for sensor diagnostics. The LMP91002 is
optimized for micro-power applications and operates
over a voltage range of 2.7 V to 3.6 V. The total
current consumption can be less than 10 μA. Further
power savings are possible by switching off the TIA
amplifier and shorting the reference electrode to the
working electrode with an internal switch.
2 Applications
•
•
•
Gas Detectors
Amperometric Applications
Electrochemical Blood Glucose Meters
Device Information(1)
PART NUMBER
LMP91002
PACKAGE
WSON (14)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VDD
VREF
SCL
LMP91002
3-Lead
Electrochemical
Cell
+
CE
A1
DIAGNOSTIC
VREF
DIVIDER
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MSP430
MENB
-
CE
RE
RE
DGND
WE
+
WE
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface ..............................................................
Timing Characteristics...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
7.5 Programming........................................................... 12
7.6 Register Maps ......................................................... 14
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 19
9
Power Supply Recommendations...................... 22
9.1 Power Consumption................................................ 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Original (March 2013) to Revision A
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
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5 Pin Configuration and Functions
NHL Package
14-Pin WSON
Top View
DGND 1
14 CE
MENB
RE
SCL
WE
SDA
VREF
DAP
NC
C1
VDD
C2
AGND 7
8
VOUT
Pin Functions (1)
PIN
I/O
DESCRIPTION
NO.
NAME
1
DGND
G
Connect to ground
2
MENB
D
Module Enable. Active Low
3
SCL
D
I2C Clock
4
SDA
D
I2C Data
5
NC
—
Do not connect. Not internally connected
6
VDD
P
Voltage supply
7
AGND
GND
8
VOUT
A
Analog voltage representing sensor output
9
C2
A
Optional External component node 2 for TIA (filter capacitor or gain resistor)
10
C1
A
Optional External component node 1 for TIA (filter capacitor or gain resistor)
11
VREF
A
External Reference voltage input
12
WE
A
Working Electrode of the sensor.
13
RE
A
Reference Electrode of the sensor.
14
CE
A
Counter Electrode of the sensor.
—
DAP
GND
(1)
Analog GND
Die attached pad. Connect to GND.
A = analog, D = digital, P = power, G = GND
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2) (3)
See
MAX
UNIT
Voltage between any two pins
MIN
6
V
Current through VDD or VSS
50
mA
Current sunk and sourced by CE pin
10
mA
Current out of other pins (4)
5
mA
150
°C
150
°C
Junction temperature
(5)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see SNOA549.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
All non-power pins of this device are protected against ESD by snapback devices. Voltage at such pins will rise beyond absmax if
current is forced into pin.
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
(1) (2)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±1000
Machine Model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
Supply voltage VS = (VDD - AGND)
2.7
3.6
V
Temperature (1)
–40
85
°C
(1)
UNIT
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LMP91002
THERMAL METRIC (1)
NHL (WSON)
UNIT
14 PINS
RθJA
(1)
(2)
4
Junction-to-ambient thermal resistance
(2)
44
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.
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6.5 Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF =
2.5 V, Internal Zero = 20% VREF. (1)
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
10
13.5
UNIT
POWER SUPPLY SPECIFICATION
3-lead amperometric cell
mode
MODECN = 0x03
IS
Supply current
Standby mode
MODECN = 0x02
Deep sleep mode
MODECN = 0x00
TA = 25ºC
At the temperature
extremes
15
TA = 25ºC
6.5
At the temperature
extremes
8
10
TA = 25ºC
0.6
At the temperature
extremes
µA
0.85
1
POTENTIOSTAT
VDD = 2.7 V;
Internal zero 50% VDD
IRE
Input bias current at RE pin
VDD = 3.6 V;
Internal zero 50% VDD
TA = 25ºC
At the temperature
extremes
TA = 25ºC
At the temperature
extremes
–90
90
–800
800
–90
90
–900
900
Minimum operating current
capability
Sink
750
Source
750
Minimum charging
capability (4)
Sink
10
Source
10
AOL_A1
Open-loop voltage gain of
control loop operational
amplifier (A1)
300 mV ≤ VCE ≤
Vs – 300 mV, –750 µA ≤
ICE ≤ 750 µA
en_RW
Low frequency integrated
noise between RE pin and
WE pin
0.1 Hz to 10 Hz (5)
ICE
VOS_RW
TcVOS_RW
(1)
(2)
(3)
(4)
(5)
(6)
WE voltage offset referred to
RE
WE voltage offset drift
referred to RE from –40°C to
85°C (6)
TA = 25ºC
At the temperature
extremes
pA
µA
mA
120
dB
104
3.4
µVpp
0% VREF, internal zero = 20% VREF,
at the temperature extremes
–550
550
0% VREF, internal zero = 50% VREF,
at the temperature extremes
–550
550
0% VREF, internal zero = 67% VREF,
at the temperature extremes
–550
550
0% VREF, internal zero = 20% VREF
–4
4
0% VREF, internal zero = 50% VREF
–4
4
0% VREF, internal zero = 67% VREF
–4
4
µV
µV/°C
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
At such currents no accuracy of the output voltage can be expected.
This parameter includes both A1 and TIA's noise contribution.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.Starting from the measured voltage offset at temperature T1 (VOS_RW(T1)), the voltage offset at temperature T2 (VOS_RW(T2)) is
calculated according the following formula: VOS_RW(T2)=VOS_RW(T1)+ABS(T2–T1)* TcVOS_RW.
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Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF =
2.5 V, Internal Zero = 20% VREF.(1)
PARAMETER
MIN (2)
TEST CONDITIONS
Transimpedance gain
accuracy
2.75
3.5
7
14
35
120
350
7 programmable gain resistors
Maximum external gain resistor
3 programmable percentages of VREF
3 programmable percentages of VDD
20%
50%
67%
Internal zero voltage
accuracy
±0.04%
Load resistor
Power supply rejection ratio
at RE pin
Ω
10
Load accuracy
PSRR
kΩ
350
20%
50%
67%
Internal zero voltage
RL
UNIT
±0.05%
TIA_GAIN
TIA_ZV
MAX (2)
5%
Linearity
Programmable TIA gains
TYP (3)
5%
2.7 V ≤ VDD ≤ 5.25 V
Internal zero 20% VREF
80
110
Internal zero 50% VREF
80
110
Internal zero 67% VREF
80
110
dB
EXTERNAL REFERENCE SPECIFICATION (7)
VREF
External voltage reference
range
1.5
VDD
Input impedance
(7)
10
V
MΩ
In case of external reference connected, the noise of the reference has to be added.
6.6 I2C Interface
Unless otherwise specified, all limits ensured for at TA = 25°C, VS= (VDD – AGND), 2.7 V <VS< 3.6 V and AGND = DGND = 0
V, VREF = 2.5 V. (1)
PARAMETER
TEST CONDITIONS
MIN (2)
0.7*VDD
VIH
Input High Voltage
At the temperature extremes
VIL
Input Low Voltage
At the temperature extremes
Output Low Voltage
IOUT = 3 mA, at the temperature
extremes
Hysteresis (4)
At the temperature extremes
Input Capacitance on all digital pins
At the temperature extremes
VOL
CIN
(1)
(2)
(3)
(4)
6
TYP (3)
MAX (2)
UNIT
V
0.1*VDD
0.3*VDD
V
0.4
V
V
0.5
pF
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design or characterization.
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6.7 Timing Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF
= 2.5 V, Internal Zero= 20% VREF. All limits apply at the temperature extremes. Refer to timing diagram in Figure 1 (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
kHz
fSCL
Clock Frequency
At the temperature extremes
10
tLOW
Clock Low Time
At the temperature extremes
4.7
µs
tHIGH
Clock High Time
At the temperature extremes
4
µs
tHD;STA
Data valid
After this period, the first clock pulse is
generated at the temperature extremes
4
µs
tSU;STA
Set-up time for a repeated START
condition
At the temperature extremes
4.7
µs
tHD;DAT
Data hold time
(2)
At the temperature extremes
0
ns
tSU;DAT
Data Set-up time
At the temperature extremes
250
ns
IL ≤ 3 mA, CL ≤ 400 pF,
at the temperature extremes
(3)
tf
SDA fall time
tSU;STO
Set-up time for STOP condition
At the temperature extremes
4
µs
tBUF
Bus free time between a STOP and
START condition
At the temperature extremes
4.7
µs
tVD;DAT
Data valid time
At the temperature extremes
3.45
µs
tVD;ACK
Data valid acknowledge time
At the temperature extremes
3.45
µs
tSP
Pulse width of spikes that must be
suppressed by the input filter (3)
At the temperature extremes
50
ns
t_timeout
SCL and SDA Timeout
At the temperature extremes
25
100
ms
2
250
ns
tEN;START
I C Interface Enabling
At the temperature extremes
600
ns
tEN;STOP
I2C Interface Disabling
At the temperature extremes
600
ns
tEN;HIGH
time between consecutive I2C
interface enabling and disabling
At the temperature extremes
600
ns
(1)
(2)
(3)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
This parameter is specified by design or characterization.
MENB
70%
30%
tEN;START
tEN;HIGH
tEN;STOP
70%
SDA
30%
tf
tVD;DAT
tLOW
tBUF
tHD;STA
tSP
SCL
70%
30%
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
1/fSCL
tSU;STO
tSU;DAT
tVD;ACK
REPEATED
START
STOP
START
Figure 1. I2C Interface Timing Diagram
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6.8 Typical Characteristics
Unless otherwise specified, TA = 25°C, VS= (VDD – AGND), 2.7 V <VS< 3.6 V and AGND = DGND = 0 V, VREF = 2.5 V.
-100
-120
85°C
25°C
-40°C
-120
-140
-140
-160
-160
VOS ( V)
VOS ( V)
-100
VDD = 2.7V
VDD = 3.3V
-180
-200
-220
-180
-200
-220
-240
-240
-260
-260
-280
-280
-300
-300
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
Figure 2. Input VOS_RW vs Temperature
Figure 3. Input VOS_RW vs VDD
140
1.0
VDD = 2.7V
VDD = 3.3V
0.9
SUPPLY CURRENT ( A)
PSRR (dB)
130
120
110
100
90
0.8
0.7
0.6
0.5
0.4
0.3
0.2
80
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
Figure 4. AC PSRR vs Frequency
SUPPLY CURRENT ( A)
0.9
7.50
85°C
25°C
-40°C
0.7
0.6
0.5
0.4
0.3
100
6.75
6.50
6.25
6.00
5.75
0.1
5.50
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
8
75
7.00
0.2
Figure 6. Supply Current vs VDD (Deep Sleep Mode)
0
25
50
TEMPERATURE (°C)
VDD = 2.7V
VDD = 3.3V
7.25
0.8
-25
Figure 5. Supply Current vs Temperature (Deep Sleep Mode)
SUPPLY CURRENT ( A)
1.0
-50
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
Figure 7. Supply Current vs Temperature (Standby Mode)
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, VS= (VDD – AGND), 2.7 V <VS< 3.6 V and AGND = DGND = 0 V, VREF = 2.5 V.
SUPPLY CURRENT ( A)
7.25
11.0
85°C
25°C
-40°C
7.00
6.75
6.50
6.25
6.00
10.6
10.4
10.2
10.0
9.8
9.6
9.4
5.75
9.2
5.50
9.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
Figure 8. Supply Current vs VDD (Standby Mode)
11.0
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
Figure 9. Supply Current vs Temperature (3-Lead
Amperometric Mode)
1.5
85°C
25°C
-40°C
1.0
10.6
10.4
EN_RW ( V)
SUPPLY CURRENT ( A)
10.8
VDD = 2.7V
VDD = 3.3V
VDD = 5V
10.8
SUPPLY CURRENT ( A)
7.50
10.2
10.0
9.8
9.6
9.4
0.5
0.0
-0.5
-1.0
9.2
9.0
-1.5
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
Figure 10. Supply Current vs VDD (3-Lead Amperometric
Mode)
0
1
2
3
4 5 6
TIME (s)
7
8
9 10
Figure 11. 0.1-Hz to 10-Hz Noise
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7 Detailed Description
7.1 Overview
The LMP91002 is a programmable AFE for use in micropower chemical sensing applications. The LMP91002 is
designed for 3-lead non-biased gas sensors and for 2 leads galvanic cell. This device provides all of the
functionality for detecting changes in gas concentration based on a delta current at the working electrode. The
LMP91002 generates an output voltage proportional to the cell current. Transimpedance gain is user
programmable through an I2C compatible interface from 2.75kΩ to 350kΩ making it easy to convert current
ranges from 5µA to 750µA full scale. Optimized for micro-power applications, the LMP91002 AFE works over a
voltage range of 2.7V to 3.6 V. The cell voltage is user selectable using the on board programmability. In
addition, it is possible to connect an external transimpedance gain resistor. Depending on the configuration, total
current consumption for the device can be less than 10µA. For power savings, the transimpedance amplifier can
be turned off and instead a load impedance equivalent to the TIA’s inputs impedance is switched in.
7.2 Functional Block Diagram
VDD
VREF
SCL
LMP91002
3-Lead
Electrochemical
Cell
+
CE
A1
DIAGNOSTIC
VREF
DIVIDER
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MENB
-
CE
RE
RE
DGND
WE
+
WE
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
7.3 Feature Description
7.3.1 Potentiostat Circuitry
The core of the LMP91002 is a potentiostat circuit. It consists of a differential input amplifier used to compare the
potential between the working and reference electrodes to a zero bias potential.. The error signal is amplified and
applied to the counter electrode (through the Control Amplifier - A1). Any changes in the impedance between
the working and reference electrodes will cause a change in the voltage applied to the counter electrode, in order
to maintain the constant voltage between working and reference electrodes. A Transimpedance Amplifier
connected to the working electrode, is used to provide an output voltage that is proportional to the cell current.
The working electrode is held at virtual ground (Internal ground) by the transimpedance amplifier. The
potentiostat will compare the reference voltage to the desired bias potential and adjust the voltage at the counter
electrode to maintain the proper working-to-reference voltage.
7.3.2 Transimpedance Amplifier
The transimpedance amplifier (TIA in Functional Block Diagram) has 7 programmable internal gain resistors. This
accommodates the full scale ranges of most existing sensors. Moreover an external gain resistor can be
connected to the LMP91002 between C1 and C2 pins. The gain is set through the I2C interface.
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Feature Description (continued)
7.3.3 Control Amplifier
The control amplifier (A1 op amp in Functional Block Diagram) provides initial charge to the sensor. A1 has the
capability to drive up to 10mA into the sensor in order to to provide a fast initial conditioning. A1 is able to sink
and source current according to the connected gas sensor (reducing or oxidizing gas sensor). It can be powered
down to reduce system power consumption. However powering down A1 is not recommended, as it may take a
long time for the sensor to recover from this situation.
7.3.4 Internal Zero
The internal Zero is the voltage at the non-inverting pin of the TIA. The internal zero can be programmed to be
either 67%, 50% or 20%, of the supply, or the external reference voltage. This provides both sufficient headroom
for the counter electrode of the sensor to swing, in case of sudden changes in the gas concentration, and best
use of the ADC’s full scale input range.
The Internal zero is provided through an internal voltage divider (Vref divider box in Functional Block Diagram).
The divider is programmed through the I2C interface.
7.3.5 2-Lead Galvanic Cell in Potentiostat Configuration
When the LMP91002 is interfaced to a galvanic cell (for instance to an Oxygen gas sensor) referred to a
reference, the Counter and the Reference pin of the LMP91002 are shorted together and connected to negative
electrode of the galvanic cell. The positive electrode of the galvanic cell is then connected to the Working pin of
the LMP91002.
The LMP91002 is then configured in 3-lead amperometric cell mode (as for amperometric cell). In this
configuration the Control Amplifier (A1) is ON and provides the internal zero voltage. The transimpedance
amplifier (TIA) is also ON, it converts the current generated by the gas sensor in a voltage, according to the
transimpedance gain:
Gain= RTIA
If different gains are required, an external resistor can be connected between the pins C1 and C2. In this case
the internal feedback resistor should be programmed to “external”.
VDD
VREF
SCL
LMP91002
2-Lead Sensor
such as Oxygen
CE
+
A1
VREF
DIVIDER
DIAGNOSTIC
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MENB
-
VERE
NC
DGND
VE+
WE
+
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
Figure 12. Two-Lead Sensor Connections
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7.4 Device Functional Modes
7.4.1 Timeout Feature
The timeout is a safety feature to avoid bus lockup situation. If SCL is stuck low for a time exceeding t_timeout,
the LMP91002 will automatically reset its I2C interface. Also, in the case the LMP91002 hangs the SDA for a time
exceeding t_timeout, the LMP91002’s I2C interface will be reset so that the SDA line will be released. Since the
SDA is an open-drain with an external resistor pull-up, this also avoids high power consumption when LMP91002
is driving the bus and the SCL is stopped.
7.5 Programming
7.5.1 I2C Interface
The I2C compatible interface operates in Standard mode (100kHz). Pull-up resistors or current sources are
required on the SCL and SDA pins to pull them high when they are not being driven low. A logic zero is
transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be
pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and
operating speed. The LMP91002 comes with a 7 bit bus fixed address: 1001 000.
7.5.2 Write and Read Operation
In order to start any read or write operation with the LMP91002, MENB needs to be set low during the whole
communication. Then the master generates a start condition by driving SDA from high to low while SCL is high.
The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have been
transmitted by the master, SDA is released by the master and the LMP91002 either ACKs or NACKs the
address. If the slave address matches, the LMP91002 ACKs the master. If the address doesn't match, the
LMP91002 NACKs the master. For a write operation, the master follows the ACK by sending the 8-bit register
address pointer. Then the LMP91002 ACKs the transfer by driving SDA low. Next, the master sends the 8-bit
data to the LMP91002. Then the LMP91002 ACKs the transfer by driving SDA low. At this point the master
should generate a stop condition and optionally set the MENB at logic high level (refer to Figure 15).
A read operation requires the LMP91002 address pointer to be set first, also in this case the master needs
setting at low logic level the MENB, then the master needs to write to the device and set the address pointer
before reading from the desired register. This type of read requires a start, the slave address, a write bit, the
address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 15).
Following this sequence, the LMP91002 sends out the 8-bit data of the register.
When just one LMP91002 is present on the I2C bus the MENB can be tied to ground (low logic level).
MENB
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
Start by
Master
Frame 1
Serial Bus Address Byte
from Master
MENB
(continued)
SCL
(continued)
1
SDA
(continued)
D7
D7
Ack
by
LMP91000
D6
D5
D4
D3
D2
D1
Frame 2
Internal Address Register
Byte from Master
D0
Ack
by
LMP91000
9
D6
D5
D4
D3
Frame 3
Data Byte
D2
D1
D0
Ack
Stop by
by
Master
LMP91000
Figure 13. (a) Register Write Transaction
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Programming (continued)
MENB
1
1
9
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
Start by
Master
Frame 1
Serial Bus Address Byte
from Master
D7
Ack
by
LMP91000
D6
D5
D4
D3
D2
D1
D0
Frame 2
Internal Address Register
Byte from Master
Ack
by
LMP91000
Stop by
Master
Figure 14. (b) Pointer Set Transaction
MENB
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
D7
Ack
by
LMP91000
Start by
Master
Frame 1
Serial Bus Address Byte
from Master
D6
D5
D4
D3
D2
D1
D0
No Ack
by
Master
Frame 2
Data Byte from
Slave
Stop
by
Master
(c) Register read transaction
Figure 15. READ and WRITE Transaction
7.5.3 Connection of More Than One LMP91002 to the I2C Bus
The LMP91002 comes out with a unique and fixed I2C slave address. It is still possible to connect more than one
LMP91002 to an I2C bus and select each device using the MENB pin. The MENB simply enables/disables the
I2C communication of the LMP91002. When the MENB is at logic level low all the I2C communication is enabled,
it is disabled when MENB is at high logic level.
In a system based on a μcontroller and more than one LMP91002 connected to the I2C bus, the I2C lines (SDA
and SCL) are shared, while the MENB of each LMP91002 is connected to a dedicate GPIO port of the
μcontroller.
The μcontroller starts communication asserting one out of N MENB signals where N is the total number of
LMP91002s connected to the I2C bus. Only the enabled device will acknowledge the I2C commands. After
finishing communicating with this particular LMP91002, the microcontroller de-asserts the corresponding MENB
and repeats the procedure for other LMP91002s. Figure 16 shows the typical connection when more than one
LMP91002 is connected to the I2C bus.
SCL
GPIO N
µC
SDA
LMP91000
MENB
SCL
GPIO 3
GPIO 2
SDA
MENB
LMP91000
SDA
SCL
LMP91000
MENB
SCL
GPIO 1
SDA
MENB
LMP91000
SCL
SDA
Figure 16. More than one LMP91002 on I2C bus
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7.6 Register Maps
The registers are used to configure the LMP91002.
If writing to a reserved bit, user must write only 0. Readback value is unspecified and should be discarded.
Table 1. Register Map
Offset
Name
Power on Default
Access (1)
Lockable?
Section
00h
STATUS
0x00
Read only
N
Go
0x01
R/W
N
Go
Y
Go
01h
LOCK
02h through 09h
RESERVED
10h
TIACN
0x03
R/W
11h
REFCN
0x20
R/W
Y
Go
12h
MODECN
0x00
R/W
N
Go
13h through FFh
RESERVED
(1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7.6.1 STATUS Register (Offset = 00h)
Status Register. The status bit is an indication of the LMP91002's power-on status. If its readback is “0”, the
LMP91002 is not ready to accept other I2C commands.
Figure 17. STATUS Register
7
6
5
4
Reserved
R
3
2
1
0
STATUS
R
Table 2. STATUS Register Field Descriptions
Bit
Name
Function
7-1
RESERVED
0
STATUS
Status of Device
0h = Not Ready (default)
1h = Ready
7.6.2 LOCK Register (Offset = 01h)
Protection Register. The lock bit enables and disables the writing of the TIACN and the REFCN registers. To
change the content of the TIACN and the REFCN registers, the lock bit must be set to “0”.
Figure 18. LOCK Register
7
6
5
4
Reserved
3
2
1
0
LOCK
R/W
Table 3. LOCK Register Field Descriptions
Bit
Name
7-1
RESERVED
0
LOCK
Function
Write protection
0h = Registers 0x10, 0x11 in write mode
1h = Registers 0x10, 0x11 in read only mode (default)
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7.6.3 TIACN Register (Offset = 10h)
TIA Control Register. The parameters in the TIA control register allow the configuration of the transimpedance
gain (RTIA).
Figure 19. TIACN Register
7
6
Reserved
5
4
3
TIA_GAIN
2
1
0
Reserved
Table 4. TIACN Register Field Descriptions
Bit
Name
Function
7-5
RESERVED
RESERVED
TIA feedback resistance selection
000h = External resistance (default)
001h = 2.75 kΩ
010h = 3.5 kΩ
4-2
TIA_GAIN
011h = 7 kΩ
100h = 14 kΩ
101h = 35 kΩ
110h = 120 kΩ
111h = 350 kΩ
1-0
RESERVED
RESERVED
7.6.4 REFCN Register (Offset = 11h)
Reference Control Register. The parameters in the Reference control register allow the configuration of the
Internal zero, and reference source. When the reference source is external, the reference is provided by a
reference voltage connected to the VREF pin. In this condition the internal zero is defined as a percentage of
VREF voltage instead of the supply voltage.
Figure 20. REFCN Register
7
REF_SOURCE
6
5
INT_Z
4
Reserved
3
2
1
0
DIAGNOSTIC
Table 5. REFCN Register Field Descriptions
BIT
NAME
7
REF_SOURCE
FUNCTION
Reference voltage source selection
0h = Internal (default)
1h = external
Internal zero selection (Percentage of the source reference)
6-5
INT_Z
00h = 20%
01h = 50% (default)
10h = 67%
4
RESERVED
3-0
DIAGNOSTIC
RESERVED
Diagnostic step (Percentage of the source reference)
0000h = 0% (default)
0001h = 1%
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7.6.5 MODECN Register (Offset = 12h)
Mode Control Register. The parameters in the mode register allow the configuration of the operation mode of the
LMP91002.
Figure 21. MODECN Register
7
FET_SHORT
6
5
4
3
2
Reserved
1
OP_MODE
0
Table 6. MODECN Register Field Descriptions
BIT
NAME
7
FET_SHORT
FUNCTION
Shorting FET feature
0h = Disabled (default)
1h = Enabled
6-3
RESERVED
RESERVED
Mode of Operation selection
2-0
OP_MODE
000h = Deep Sleep (default)
010h = Standby
011h = 3-lead amperometric cell
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Gas Sensor Interface
The LMP91002 supports both 3-lead and 2-lead gas sensors. Most of the toxic gas sensors are amperometric
cells with 3 leads (Counter, Worker and Reference). These leads should be connected to the LMP91002 in the
potentiostat topology.
8.1.1.1 3-Lead Amperometric Cell In Potentiostat Configuration
Most of the amperometric cell have 3 leads (Counter, Reference and Working electrodes). The interface of the 3lead gas sensor to the LMP91002 is straightforward. The leads of the gas sensor should be connected to the
LMP91002 pins which have the matching name
The LMP91002 is then configured in 3-lead amperometric cell mode; in this configuration the Control Amplifier
(A1) is ON and provides the internal zero voltage and bias in case of biased gas sensor. The transimpedance
amplifier (TIA) is ON, it converts the current generated by the gas sensor in a voltage, according to the
transimpedance gain:
Gain = RTIA
If different gains are required, an external resistor can be connected between the pins C1 and C2. In this case
the internal feedback resistor should be programmed to “external”. The RLoad together with the output
capacitance of the gas sensor acts as a low pass filter.
VDD
VREF
SCL
LMP91002
3-Lead
Electrochemical
Cell
+
CE
A1
DIAGNOSTIC
VREF
DIVIDER
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MENB
-
CE
RE
RE
DGND
WE
+
WE
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
Figure 22. 3-Lead Amperometric Cell
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Application Information (continued)
8.1.2 Sensor Test Procedure
The LMP91002 has all the hardware and programmability features to implement some test procedures. The
purpose of the test procedure is to:
a. test proper function of the sensor (status of health)
b. test proper connection of the sensor to the LMP91002
The test procedure is very easy. The diagnostic block is user programmable through the digital interface. A step
voltage can be applied by the end user to the positive input of A1. As a consequence a transient current will start
flowing into the sensor (to charge its internal capacitance) and it will be detected by the TIA. If the current
transient is not detected, either a sensor fault or a connection problem is present. The slope and the aspect of
the transient response can also be used to detect sensor aging (for example, a cell that is drying and no longer
efficiently conducts the current). After it is verified that the sensor is working properly, the LMP91002 needs to be
reset to its original configuration. It is not required to observe the full transient in order to contain the testing time.
All the needed information are included in the transient slopes (both edges). Figure 23 shows an example test
procedure, a Carbon Monoxide sensor is connected to the LMP91002, a 25-mVpp pulse is applied between
Reference and Working pin.
The following procedure shows how to implement the sensor test. Preliminary conditions:
The LMP91002 is unlocked and it is in 3-Lead Amperometric Cell Mode
1. Put in the [3:0] bit of the register REFCN (0x11) the 0001b value, leaving the other bit unchanged. This
operation will apply a potential (VRW) between RE and WE pin (VRE > VWE), VRW= 1% Source reference.
2. Put in the [3:0] bit of the register REFCN (0x11) the 0000b value, leaving the other bit unchanged. This
operation will remove the potential (VRW) between RE and WE pin (VRE > VWE), VRW= 0 V.
LMP91000 OUTPUT
TEST PULSE
INPUT PULSE (50mV/DIV)
OUTPUT VOLTTAGE (500mV/DIV)
The width of the pulse is simply the time between the two writing operation.
TIME (25ms/DIV)
Figure 23. Test Procedure Example
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8.2 Typical Application
VDD
VREF
SCL
LMP91002
3-Lead
Electrochemical
Cell
+
CE
A1
DIAGNOSTIC
VREF
DIVIDER
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MSP430
MENB
-
CE
RE
RE
DGND
WE
+
WE
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
Figure 24. AFE Gas Detector
8.2.1 Design Requirements
The primary design requirement is selecting the appropriate TIA gain for the expected range of current over the
operating range of the sensor. This gain should set the VOUT range to fall within the limits of the full-scale
voltage for the ADC that is sampling the signal. For example, assume the current output range of the sensor is 0
to 100,000 nA, and the full scale ADC input range is 0 to 1 V. Because Gain = RTIA, the appropriate relationship
is:
ISENSOR × Gain = RTIA × 10 – 4 A ≤ 1 V
(1)
4
Hence, RTIA < 10 Ω. In this case, the closest programmed gain value is 7 kΩ (see Table 4). However, if
optimization of the full-scale range is desired, then alternatively, RTIA can be programmed to 350 kΩ, and a 10kΩ resistor connected between pins C1 and C2. This will give an equivalent resistance of 9.7 kΩ.
8.2.2 Detailed Design Procedure
8.2.2.1 Smart Gas Sensor Analog Front End
The LMP91002 together with an external EEPROM represents the core of a SMART GAS SENSOR AFE. In the
EEPROM it is possible to store the information related to the GAS sensor type, calibration and LMP91002's
configuration (content of registers 10h, 11h, 12h). At startup the microcontroller reads the EEPROM's content
and configures the LMP91002. A typical smart gas sensor AFE is shown in Figure 25. The connection of MENB
to the hardware address pin A0 of the EEPROM allows the microcontroller to select the LMP91002 and its
corresponding EEPROM when more than one smart gas sensor AFE is present on the I2C bus.
NOTE
Only EEPROM I2C addresses with A0 = 0 should be used in this configuration.
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Typical Application (continued)
SCL
A0
SDA
SCL
MENB
MENB
SCL
SDA
I2C EEPROM
LMP91000
SDA
Figure 25. Smart Gas Sensor AFE
8.2.2.2 Smart Gas Sensor AFES on I2C Bus
The connection of Smart gas sensor AFEs on the I2C bus is the natural extension of the previous concepts. Also
in this case the microcontroller starts communication asserting 1 out of N MENB signals where N is the total
number of smart gas sensor AFE connected to the I2C bus. Only one of the devices (either LMP91002 or its
corresponding EEPROM) in the smart gas sensor AFE enabled will acknowledge the I2C commands. When the
communication with this particular module ends, the microcontroller de-asserts the corresponding MENB and
repeats the procedure for other modules. Figure 26 shows the typical connection when several smart gas sensor
AFEs are connected to the I2C bus.
SMART SENSOR AFE
SMART SENSOR AFE
SCL
SDA
A0
SCL
I2C EEPROM
SMART SENSOR AFE
GPIO 2
GPIO 1
SDA
LMP91000
MENB
SCL
SDA
I2C EEPROM
A0
SDA
SCL
LMP91000
MENB
SDA
A0
I2C EEPROM
SCL
SCL
SDA
MENB
LMP91000
GPIO N
µC
SCL
SDA
Figure 26. Smart Gas Sensor AFEs on I2C Bus
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Typical Application (continued)
NORMALIZED OUTPUT TIA (200mV/DIV)
2.75k
3.5k
7k
14k
35k
120k
350k
TIME (200 s/DIV)
Figure 27. IWE Step Current Response (Rise)
2.0
IWE
2.75k
3.5k
7k
14k
35k
120k
350k
IWE(50 A/DIV)
IWE
IWE(50 A/DIV)
NORMALIZED OUTPUT (200mV/DIV)
8.2.3 Application Curves
TIME (200 s/DIV)
Figure 28. IWE Step Current Response (Fall)
LMP91000
1.9
1.8
VOUT (V)
1.7
1.6
1.5
1.4
1.3
1.2
RTIA=35k ,
Rload=10 ,
1.1
1.0
0
25
50
75
100
TIME (s)
125
150
Figure 29. A VOUT Step Response 100 ppm to 400 ppm CO
(CO Gas Sensor Connected to LMP91002)
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9 Power Supply Recommendations
9.1 Power Consumption
The LMP91002 is intended for use in portable devices, so the power consumption is as low as possible in order
to ensure a long battery life. The total power consumption for the LMP91002 is below 10 µA at 3.3-V average
over time, (this excludes any current drawn from any pin). A typical usage of the LMP91002 is in a portable gas
detector and its power consumption is summarized in Table 7. This has the following assumptions:
• Power On only happens a few times over life, so its power consumption can be ignored
• Deep Sleep mode is not used
• The system is used about 8 hours a day, and 16 hours a day it is in Standby mode.
This results in an average power consumption of approximately 7.8 µA. This can potentially be further reduced,
by using the Standby mode between gas measurements. It may even be possible, depending on the sensor
used, to go into deep sleep for some time between measurements, further reducing the average power
consumption.
Table 7. Power Consumption Scenario
DEEP SLEEP
STANDBY
3-LEAD AMPEROMETRIC
CELL
Current consumption (µA) typical value
0.6
6.5
10
Time ON (%)
0
60
39
Average (µA)
0
3.9
3.9
A1
OFF
ON
ON
TIA
OFF
OFF
ON
ON
ON
ON
TOTAL
7.8
Notes
2
I C interface
10 Layout
10.1 Layout Guidelines
Figure 30 and Figure 31 show an example layout for the LMP91002. Figure 30 shows the top layer, and
Figure 31 shows the bottom layer. Figure 30 shows that the sensor electrodes may be arranged around the
LMP91002 so that the sensor sets directly over the LMP91002, creating a compact layout. There are very few
components needed for the LMP91002: one or more bypass capacitors attached to VDD, and one or two
optional external components attached to pins C1 or C2 of the TIA that can provide extra filtering or gain. In the
layout shown here, the VDD bypass capacitor is on the top layer, close to the LMP91002, while the optional
components for the TIA are placed on the bottom layer. However, these components may also be placed on the
top layer.
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10.2 Layout Example
CE
WE
LMP91002
RE
Figure 30. Layout Example – Top Layer
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Layout Example (continued)
CE
WE
Node C2
Node C1
RE
Optional external
components
Figure 31. Layout Example – Bottom Layer
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Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMP91002SD/NOPB
ACTIVE
WSON
NHL
14
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L91002
LMP91002SDE/NOPB
ACTIVE
WSON
NHL
14
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L91002
LMP91002SDX/NOPB
ACTIVE
WSON
NHL
14
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L91002
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMP91002SD/NOPB
WSON
NHL
14
LMP91002SDE/NOPB
WSON
NHL
LMP91002SDX/NOPB
WSON
NHL
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
14
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
14
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP91002SD/NOPB
WSON
NHL
14
1000
210.0
185.0
35.0
LMP91002SDE/NOPB
WSON
NHL
14
250
210.0
185.0
35.0
LMP91002SDX/NOPB
WSON
NHL
14
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NHL0014B
SDA14B (Rev A)
www.ti.com
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