Texas Instruments | Digital Temperature Sensor With a Two-Wire Interface (Rev. A) | Datasheet | Texas Instruments Digital Temperature Sensor With a Two-Wire Interface (Rev. A) Datasheet

Texas Instruments Digital Temperature Sensor With a Two-Wire Interface (Rev. A) Datasheet
TMP106
Chip-Scale
Package
SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
Digital Temperature Sensor
with Two-Wire Interface
FEATURES
D
D
D
D
DESCRIPTION
TWO ADDRESSES
DIGITAL OUTPUT: Two-Wire Serial Interface
RESOLUTION: 9- to 12-Bits, User-Selectable
ACCURACY:
±2.0°C (max) from −25°C to +85°C
±3.0°C (max) from −40°C to +125°C
D LOW QUIESCENT CURRENT:
50µA, 0.1µA Standby
D NO POWER-UP SEQUENCE REQUIRED, I2C
PULLUPS CAN BE ENABLED PRIOR TO V+
APPLICATIONS
D NOTEBOOK COMPUTERS
D COMPUTER PERIPHERAL THERMAL
PROTECTION
D
D
D
D
The TMP106 is a two-wire, serial output temperature
sensor available in a WCSP package. Requiring no
external components, the TMP106 is capable of reading
temperatures with a resolution of 0.0625°C.
The TMP106 features a Two-Wire interface that is
SMBus-compatible, with the TMP106 allowing up to two
devices on one bus. The TMP106 also features an SMBus
Alert function.
The TMP106 is ideal for extended temperature
measurement in a variety of communication, computer,
consumer, environmental, industrial, and instrumentation
applications.
The TMP106 is specified for operation over a temperature
range of −40°C to +125°C.
CELL PHONES
BATTERY MANAGEMENT
THERMOSTAT CONTROLS
ENVIRONMENTAL MONITORING AND HVAC
Temperature
YZC LEAD−FREE
2 X 3 ARRAY
(TOP VIEW)
1,65 mm
1,50 mm
SDA
SDA
A1
A2
GND
SCL
B1
B2
ALERT
V+
C1
C2
A0
SCL
V+
1,15 mm
1,00 mm
A1
B1
Diode
Temp.
Sensor
Control
Logic
∆Σ
A/D
Converter
Serial
Interface
OSC
Config.
and Temp.
Register
A2
B2
C1
C2
GND
ALERT
A0
(Bump Side Down)
TMP106
Note: Pin A1 is marked with a ‘0’ for Pb−free (YZC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2005−2006, Texas Instruments Incorporated
! ! www.ti.com
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ABSOLUTE MAXIMUM RATINGS(1)
Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +130°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating(3):
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V
Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . 500V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input voltage rating applies to all TMP106 input voltages.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
(3) ESD testing has been tested to TI specifications JEDEC
J−Std 020.
ORDERING INFORMATION(1)
PACKAGE
PART NUMBER
SYMBOL
Wafer chip-scale package (YZC)
TMP106YZC
F7
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
PIN ASSIGNMENTS
WCSP−6 PACKAGE
(TOP VIEW)
SDA
A1
A2
GND
SCL
B1
B2
ALERT
V+
C1
C2
A0
(Bump Side Down)
Note: Pin 1 is determined by orienting the package marking as indicated in the diagram.
2
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ELECTRICAL CHARACTERISTICS
At TA = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.
TMP106
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
TEMPERATURE INPUT
+125
°C
−25°C to +85°C
±0.5
±2.0
°C
−40°C to +125°C
±1.0
±3.0
°C
0.2
±0.5
°C/V
Range
−40
Accuracy (Temperature Error)
vs Supply
Resolution(1)
Selectable
0.0625
°C
3
pF
DIGITAL INPUT/OUTPUT
Input Capacitance
Input Logic Levels:
VIH
VIL
2.1
6.0
−0.5
0.8
V
1
µA
0V ≤ VIN ≤ 6V
Leakage Input Current, IIN
Input Voltage Hysteresis
SCL and SDA Pins
250
V
mV
Output Logic Levels:
VOL SDA
VOL ALERT
IOL = 3mA
IOL = 4mA
Resolution
Conversion Time
0
0.15
0.4
V
0
0.15
0.4
V
Selectable
9 to 12
9-Bit
27.5
37.5
ms
10-Bit
55
75
ms
11-Bit
110
150
ms
12-Bit
220
300
ms
54
74
ms
Timeout Time
25
Bits
POWER SUPPLY
Operating Range
Quiescent Current
Shutdown Current
2.7
IQ
ISD
Serial Bus Inactive
50
5.5
V
85
µA
µA
Serial Bus Active, SCL Freq = 400kHz
100
Serial Bus Active, SCL Freq = 3.4MHz
410
Serial Bus Inactive
0.1
Serial Bus Active, SCL Freq = 400kHz
60
µA
Serial Bus Active, SCL Freq = 3.4MHz
380
µA
µA
3
µA
TEMPERATURE RANGE
Specified Range
−40
+125
Operating Range
−55
+127
Thermal Resistance
qJA
240
°C
°C
°C/W
(1) Specified for 12-bit resolution.
3
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TYPICAL CHARACTERISTICS
At TA = +25°C and V+ = 5.0V, unless otherwise noted.
SHUTDOWN CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs TEMPERATURE
60
1.0
V+ = 2.8V
0.9
V+ = 5V
50
0.8
0.7
0.6
ISD (µA)
IQ (µA)
40
V+ = 2.7V
30
0.5
0.4
0.3
20
0.2
0.1
10
0.0
Serial Bus Inactive
−0.1
0
−50
−25
0
25
50
75
100
−55
125
−35
−15
5
25
45
65
85
105
125
Temperature (_ C)
Temperature (_ C)
TEMPERATURE ACCURACY vs TEMPERATURE
CONVERSION TIME vs TEMPERATURE
300
2.0
250
Temperature Error (_ C)
Conversion Time (ms)
1.5
V+ = 5V
200
V+ = 2.7V
150
1.0
0.5
0.0
−0.5
−1.0
−1.5
12−bit resolution.
100
−50
−25
0
25
50
75
100
−2.0
−55
125
3 typical units 12−bit resolution.
−35
−15
5
QUIESCENT CURRENT WITH
BUS ACTIVITY vs TEMPERATURE
500
Hs MODE
FAST MODE
450
400
I Q (µA)
350
300
250
200
125_C
150
25_ C
100
50
−55_C
0
1k
10k
100k
Frequency (Hz)
4
25
45
65
Temperature (_ C)
Temperature (_ C)
1M
10M
85
105
125
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APPLICATIONS INFORMATION
The TMP106 is a digital temperature sensor that is optimal
for thermal management and thermal protection
applications. The TMP106 is Two-Wire and SMBus
interface-compatible, and is specified over a temperature
range of −40°C to +125°C.
Pointer
Register
Temperature
Register
The TMP106 requires no external components for
operation except for pull-up resistors on SCL, SDA, and
ALERT, although a 0.1µF bypass capacitor is
recommended, as shown in Figure 1.
SCL
Configuration
Register
V+
I/O
Control
Interface
TLOW
Register
SDA
0.1µF
C1
To
Two−Wire
Controller
SCL
B1
SDA
A1
TMP106
THIGH
Register
C2
A0
B2
Figure 2. Internal Register Structure of the
TMP106
ALERT
(Output)
A2
GND
NOTE: SCL, SDA, and ALERT
pins require pull−up resistors.
P1
P0
0
0
Temperature Register (Read Only)
0
1
Configuration Register (Read/Write)
1
0
1
1
TLOW Register (Read/Write)
THIGH Register (Read/Write)
Figure 1. Typical Connections of the TMP106
The sensing device of the TMP106 is the chip itself.
Thermal paths run through the package leads. The lower
thermal resistance of metal causes the leads to provide the
primary thermal path.
To maintain accuracy in applications requiring air or
surface temperature measurement, care should be taken
to isolate the package and leads from ambient air
temperature.
POINTER REGISTER
Figure 2 shows the internal register structure of the
TMP106. The 8-bit Pointer Register of the device is used
to address a given data register. The Pointer Register uses
the two LSBs to identify which of the data registers should
respond to a read or write command. Table 1 identifies the
bits of the Pointer Register byte. Table 2 describes the
pointer address of the registers available in the TMP106.
Power-up reset value of P1/P0 is 00.
P7
P6
P5
P4
P3
P2
0
0
0
0
0
0
P1
P0
Register Bits
Table 1. Pointer Register Byte
REGISTER
Table 2. Pointer Addresses of the TMP106
TEMPERATURE REGISTER
The Temperature Register of the TMP106 is a 12-bit,
read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are
described in Table 3 and Table 4. Note that byte 1 is the
most significant byte; byte 2 is the least significant byte.
The first 12 bits are used to indicate temperature, with all
remaining bits equal to zero. The least significant byte
does not have to be read if that information is not needed.
Data format for temperature is summarized in Table 5.
Following power-up or reset, the Temperature Register will
read 0°C until the first conversion is complete.
D7
D6
D5
D4
D3
D2
D1
D0
T11
T10
T9
T8
T7
T6
T5
T4
Table 3. Byte 1 of Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T3
T2
T1
T0
0
0
0
0
Table 4. Byte 2 of Temperature Register
5
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POLARITY (POL)
TEMPERATURE
(°C)
DIGITAL OUTPUT
(BINARY)
HEX
128
0111 1111 1111
7FF
127.9375
0111 1111 1111
7FF
100
0110 0100 0000
640
80
0101 0000 0000
500
75
0100 1011 0000
4B0
50
0011 0010 0000
320
25
0001 1001 0000
190
0.25
0000 0000 0100
004
0
0000 0000 0000
000
−0.25
1111 1111 1100
FFC
−25
1110 0111 0000
E70
−55
1100 1001 0000
C90
The Polarity Bit of the TMP106 allows the user to adjust the
polarity of the ALERT pin output. If POL = 0, the ALERT pin
will be active LOW, as shown in Figure 3. For POL = 1, the
ALERT pin will be active HIGH, and the state of the ALERT
pin is inverted.
THIGH
Measured
Temperature
TLOW
Table 5. Temperature Data Format
TMP106 ALERT PIN
(Comparator Mode)
POL = 0
The user can obtain 9, 10, 11, or 12 bits of resolution by
addressing the Configuration Register and setting the
resolution bits accordingly. For 9-, 10-, or 11-bit resolution,
the most significant bits in the Temperature Register are
used with the unused LSBs set to zero.
TMP106 ALERT PIN
(Interrupt Mode)
POL = 0
TMP106 ALERT PIN
(Comparator Mode)
POL = 1
TMP106 ALERT PIN
(Interrupt Mode)
POL = 1
CONFIGURATION REGISTER
The Configuration Register is an 8-bit read/write register
used to store bits that control the operational modes of the
temperature sensor. Read/write operations are performed
MSB first. The format of the Configuration Register for the
TMP106 is shown in Table 6, followed by a breakdown of
the register bits. The power-up/reset value of the
Configuration Register is all bits equal to 0.
Read
Read
Read
Time
Figure 3. Output Transfer Function Diagrams
FAULT QUEUE (F1/F0)
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
OS
R1
R0
F1
F0
POL
TM
SD
Table 6. Configuration Register Format
SHUTDOWN MODE (SD)
The Shutdown Mode of the TMP106 allows the user to
save maximum power by shutting down all device circuitry
other than the serial interface, which reduces current
consumption to typically less than 0.1µA. Shutdown Mode
is enabled when the SD bit is 1; the device will shut down
once the current conversion is completed. When SD is
equal to 0, the device will maintain a continuous
conversion state.
THERMOSTAT MODE (TM)
The Thermostat Mode bit of the TMP106 indicates to the
device whether to operate in Comparator Mode (TM = 0)
or Interrupt Mode (TM = 1). For more information on
comparator and interrupt modes, see the High and Low
Limit Registers section.
6
A fault condition is defined as when the measured
temperature exceeds the user-defined limits set in the
THIGH and TLOW Registers. Additionally, the number of
fault conditions required to generate an alert may be
programmed using the fault queue. The fault queue is
provided to prevent a false alert as a result of
environmental noise. The fault queue requires
consecutive fault measurements in order to trigger the
alert function. Table 7 defines the number of measured
faults that may be programmed to trigger an alert condition
in the device. For THIGH and TLOW register format and byte
order, see the High and Low Limit Registers section.
F1
F0
CONSECUTIVE FAULTS
0
0
1
0
1
2
1
0
4
1
1
6
Table 7. Fault Settings of the TMP106
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CONVERTER RESOLUTION (R1/R0)
The Converter Resolution bits control the resolution of the
internal analog-to-digital (A/D) converter. This control
allows the user to maximize efficiency by programming for
higher resolution or faster conversion time. Table 8
identifies the resolution bits and the relationship between
resolution and conversion time.
R1
R0
RESOLUTION
CONVERSION TIME
(typical)
0
0
9 Bits (0.5°C)
27.5ms
0
1
10 Bits (0.25°C)
55ms
1
0
11 Bits (0.125°C)
110ms
1
1
12 Bits (0.0625°C)
220ms
Table 8. Resolution of the TMP106
ONE-SHOT (OS)
The TMP106 features a One-Shot Temperature
Measurement Mode. When the device is in Shutdown
Mode, writing a ‘1’ to the OS bit starts a single temperature
conversion. The device will return to the shutdown state at
the completion of the single conversion. This option is
useful to reduce power consumption in the TMP106 when
continuous temperature monitoring is not required. When
the Configuration Register is read, the OS always reads
zero.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT pin of the
TMP106 becomes active when the temperature equals or
exceeds the value in THIGH and generates a consecutive
number of faults according to fault bits F1 and F0. The
ALERT pin remains active until the temperature falls below
the indicated TLOW value for the same number of faults.
In Interrupt Mode (TM = 1), the ALERT pin becomes active
when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin
remains active until a read operation of any register
occurs, or until the device successfully responds to the
SMBus Alert Response address. The ALERT pin clears if
the device is placed in Shutdown Mode. Once the ALERT
pin is cleared, it will only become active again by the
temperature falling below TLOW. When the temperature
falls below TLOW, the ALERT pin becomes active and
remains active until cleared by a read operation of any
register or a successful response to the SMBus Alert
Response address. When the ALERT pin clears, the
above cycle will repeat, with the ALERT pin becoming
active when the temperature equals or exceeds THIGH.
The ALERT pin can also be cleared by resetting the device
with the General Call Reset command. This reset also
clears the state of the internal registers in the device,
returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 3.
Table 9 and Table 10 describe the format for the THIGH and
TLOW Registers. Note that the most significant byte is sent
first, followed by the least significant byte. Power-up reset
values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as
for the Temperature Register.
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
H11
H10
H9
H8
H7
H6
H5
H4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
H3
H2
H1
H0
0
0
0
0
Table 9. Bytes 1 and 2 of THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
L11
L10
L9
L8
L7
L6
L5
L4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
L3
L2
L1
L0
0
0
0
0
Table 10. Bytes 1 and 2 of TLOW Register
All 12 bits for the Temperature, THIGH, and TLOW Registers
are used in the comparisons for the ALERT function for all
converter resolutions. The three LSBs in THIGH and TLOW
can affect the ALERT output even if the converter is
configured for 9-bit resolution.
SERIAL INTERFACE
The TMP106 operates only as a slave device on the
Two-Wire bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The SDA
and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects of input spikes
and bus noise. The TMP106 supports the transmission
protocol for fast (1kHz to 400kHz) and high-speed (1kHz
to 3.4MHz) modes. All data bytes are transmitted MSB
first.
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SERIAL BUS ADDRESS
To communicate with the TMP106, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation.
The TMP106 features one address pin allowing up to two
devices to be connected per bus. Pin logic levels are
described in Table 11. The address pin of the TMP106 is
read after reset, at start of communication, or in response
to a Two-Wire address acquire request. Following the
reading of the pin state, the address is latched to minimize
power dissipation associated with detection.
A0
SLAVE ADDRESS
0
1001000
1
1001001
Table 11. Address Pin and Slave Addresses for
the TMP106
BUS OVERVIEW
The device that initiates the transfer is called a master, and
the devices controlled by the master are slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
8
Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as
any change in SDA while SCL is HIGH will be interpreted
as a control signal.
Once all data has been transferred, the master generates
a STOP condition, indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
WRITING/READING TO THE TMP106
Accessing a particular register on the TMP106 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W bit LOW. Every write operation to the TMP106
requires a value for the Pointer Register. (Refer to
Figure 5.)
When reading from the TMP106, the last value stored in
the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new
value must be written to the Pointer Register. This is
accomplished by issuing a slave address byte with the
R/W bit LOW, followed by the Pointer Register byte. No
additional data are required. The master can then
generate a START condition and send the slave address
byte with the R/W bit HIGH to initiate the read command.
See Figure 6 for details of this sequence. If repeated reads
from the same register are desired, it is not necessary to
continually send the Pointer Register byte, as the TMP106
remembers the Pointer Register value until it is changed
by the next write operation.
Note that register bytes are sent most-significant byte first,
followed by the least-significant byte.
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SLAVE MODE OPERATIONS
The TMP106 can operate as a slave receiver or slave
transmitter.
Slave Receiver Mode:
The first byte transmitted by the master is the slave
address, with the R/W bit LOW. The TMP106 then
acknowledges reception of a valid address. The next byte
transmitted by the master is the Pointer Register. The
TMP106 then acknowledges reception of the Pointer
Register byte. The next byte or bytes are written to the
register addressed by the Pointer Register. The TMP106
acknowledges reception of each data byte. The master
may terminate data transfer by generating a START or
STOP condition.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is
transmitted by the slave and is the most significant byte of
the register indicated by the Pointer Register. The master
acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The
master acknowledges reception of the data byte. The
master may terminate data transfer by generating a
Not-Acknowledge on reception of any data byte, or
generating a START or STOP condition.
SMBus ALERT FUNCTION
The TMP106 supports the SMBus Alert function. When
the TMP106 is operating in Interrupt Mode (TM = 1), the
ALERT pin of the TMP106 may be connected as an
SMBus Alert signal. When a master senses that an ALERT
condition is present on the ALERT line, the master sends
an SMBus Alert command (00011001) on the bus. If the
ALERT pin of the TMP106 is active, the devices will
acknowledge the SMBus Alert command and respond by
returning its slave address on the SDA line. The eighth bit
(LSB) of the slave address byte will indicate if the
temperature exceeding THIGH or falling below TLOW
caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to THIGH. This bit will
be LOW if the temperature is less than TLOW. Refer to
Figure 7 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert
command, arbitration during the slave address portion of
the SMBus Alert command will determine which device
will clear its ALERT status. If the TMP106 wins the
arbitration, its ALERT pin will become inactive at the
completion of the SMBus Alert command. If the TMP106
loses the arbitration, its ALERT pin will remain active.
GENERAL CALL
The TMP106 responds to a Two-Wire General Call
address (0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to
commands in the second byte. If the second byte is
00000100, the TMP106 will latch the status of the address
pin, but will not reset. If the second byte is 00000110, the
TMP106 will latch the status of the address pin and reset
the internal registers to their power-up values.
HIGH-SPEED MODE
In order for the Two-Wire bus to operate at frequencies
above 400kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START
condition to switch the bus to high-speed operation. The
TMP106 will not acknowledge this byte, but will switch its
input filters on SDA and SCL and its output filters on SDA
to operate in Hs-mode, allowing transfers at up to 3.4MHz.
After the Hs-mode master code has been issued, the
master will transmit a Two-Wire slave address to initiate a
data transfer operation. The bus will continue to operate in
Hs-mode until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP106 will switch the
input and output filters back to fast-mode operation.
TIMEOUT FUNCTION
The TMP106 will reset the serial interface if either SCL or
SDA are held LOW for 54ms (typ) between a START and
STOP condition. The TMP106 will release the bus if it is
pulled LOW and will wait for a START condition. To avoid
activating the timeout function, it is necessary to maintain
a communication speed of at least 1kHz for SCL operating
frequency.
9
"#$%
www.ti.com
SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
TIMING DIAGRAMS
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not limited and
is determined by the master device. The receiver
acknowledges the transfer of data.
The TMP106 is Two-Wire- and SMBus-compatible.
Figure 4 to Figure 7 describe the various operations on the
TMP106. Bus definitions are given below. Parameters for
Figure 4 are defined in Table 12.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line
is stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data
transfer can be signaled by the master generating a
Not-Acknowledge on the last byte that has been
transmitted by the slave.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer: A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
FAST MODE
PARAMETER
SCL Operating Frequency
Bus Free Time Between STOP and START Condition
Hold time after repeated START condition.
After this period, the first clock is generated.
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock LOW Period
SCL Clock HIGH Period
UNITS
MIN
MAX
MIN
MAX
f(SCL)
t(BUF)
0.001
0.4
0.001
3.4
600
160
ns
t(HDSTA)
100
100
ns
t(SUSTA)
t(SUSTO)
t(HDDAT)
100
100
ns
100
100
ns
0
0
ns
t(SUDAT)
t(LOW)
100
10
ns
1300
160
ns
600
60
t(HIGH)
tF
Clock/Data Fall Time
HIGH-SPEED MODE
Clock/Data Rise Time
for SCLK ≤ 100kHz
tR
MHz
ns
300
160
ns
300
1000
160
ns
ns
Table 12. Timing Diagram Definitions for the TMP106
TWO-WIRE TIMING DIAGRAMS
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BU F )
P
S
S
Figure 4. Two-Wire Timing Diagram
10
P
"#$%
www.ti.com
SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
1
9
1
9
…
SCL
1
SDA
0
0
1
0
0
A0
R/W
Start By
Master
0
0
0
0
0
0
P1
…
P0
ACK By
TMP106
ACK By
TMP106
Frame 2 Pointer Register Byte
Frame 1 Two−Wire Slave Address Byte
1
1
9
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D7
D0
D6
D5
D4
D3
D2
D1
D0
ACK By
TMP106
ACK By
TMP106
Stop By
Master
Frame 4 Data Byte 2
Frame 3 Data Byte 1
Figure 5. Two-Wire Timing Diagram for TMP106 Write Word Format
1
9
1
9
…
SCL
SDA
1
0
0
0
0
A0
R/W
Start By
Master
0
0
0
0
0
0
P1
…
P0
ACK By
TMP106
ACK By
TMP106
Frame 1 Two−Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
…
SCL
(Continued)
SDA
(Continued)
1
0
0
1
0
0
A0
D7
R/W
Start By
Master
ACK By
TMP106
Frame 3 Two−Wire Slave Address Byte
1
D6
D5
D4
D3
D2
D1
D0
From
TMP106
…
ACK By
Master
Frame 4 Data Byte 1 Read Register
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
TMP106
ACK By
Master
Stop By
Master
Frame 5 Data Byte 2 Read Register
Figure 6. Two-Wire Timing Diagram for Read Word Format
11
"#$%
www.ti.com
SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
ALERT
1
9
1
9
SCL
SDA
Start By
Master
0
0
0
1
1
0
0
R/W
1
0
0
1
0
ACK By
TMP106
Frame 1 SMBus ALERT Response Address Byte
A0
From
TMP106
Frame 2 Slave Address Byte
Figure 7. Timing Diagram for SMBus ALERT
12
0
Status
NACK By
Master
Stop By
Master
13
PACKAGE OPTION ADDENDUM
www.ti.com
9-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TMP106YZCR
ACTIVE
DSBGA
YZC
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
F7
TMP106YZCT
ACTIVE
DSBGA
YZC
6
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
F7
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Sep-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TMP106YZCR
DSBGA
YZC
6
3000
178.0
8.4
TMP106YZCT
DSBGA
YZC
6
250
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.24
1.7
0.76
4.0
8.0
Q1
1.24
1.7
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMP106YZCR
DSBGA
YZC
6
3000
220.0
220.0
35.0
TMP106YZCT
DSBGA
YZC
6
250
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZC0006
DSBGA - 0.625 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.35
0.15
BALL TYP
0.08 C
0.5 TYP
0.25 TYP
C
SYMM
1
TYP
B
0.5
TYP
A
6X
0.015
0.35
0.25
C A
1
2
SYMM
B
4219522/A 02/2015
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZC0006
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.265)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.265)
METAL
METAL
UNDER
SOLDER MASK
0.05 MIN
( 0.265)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219522/A 02/2015
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZC0006
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
2
1
(R0.05) TYP
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219522/A 02/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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