Texas Instruments | Precision Switched Integrator Transimpedance Amplifier | Datasheet | Texas Instruments Precision Switched Integrator Transimpedance Amplifier Datasheet

Texas Instruments Precision Switched Integrator Transimpedance Amplifier Datasheet
IVC102
®
PRECISION SWITCHED INTEGRATOR
TRANSIMPEDANCE AMPLIFIER
APPLICATIONS
DESCRIPTION
● PRECISION LOW CURRENT MEASUREMENT
The IVC102 is a precision integrating amplifier with
FET op amp, integrating capacitors, and low leakage
FET switches. It integrates low-level input current for
a user-determined period, storing the resulting voltage
on the integrating capacitor. The output voltage can be
held for accurate measurement. The IVC102 provides
a precision, lower noise alternative to conventional
transimpedance op amp circuits that require a very
high value feedback resistor.
● PHOTODIODE MEASUREMENTS
● IONIZATION CHAMBER MEASUREMENTS
● CURRENT/CHARGE-OUTPUT SENSORS
● LEAKAGE CURRENT MEASUREMENT
FEATURES
The IVC102 is ideal for amplifying low-level sensor
currents from photodiodes and ionization chambers.
The input signal current can be positive or negative.
● ON-CHIP INTEGRATING CAPACITORS
● GAIN PROGRAMMED BY TIMING
● LOW INPUT BIAS CURRENT: 750fA max
TTL/CMOS-compatible timing inputs control the integration period, hold and reset functions to set the
effective transimpedance gain and to reset (discharge)
the integrator capacitor.
● LOW NOISE
● LOW SWITCH CHARGE INJECTION
● FAST PULSE INTEGRATION
Package options include 14-Pin plastic DIP and SO-14
surface-mount packages. Both are specified for the
–40°C to 85°C industrial temperature range.
● LOW NONLINEARITY: 0.005% typ
● 14-PIN DIP, SO-14 SURFACE MOUNT
V+
C3
6
14
60pF
V
VB
C2
5
4
Ionization
Chamber
C1
=
∫
–1
I (t) dt
CINT IN
30pF
Positive or Negative
Signal Integration
10pF
S2
3
IIN
O
10
VO
2
0V
S1
Hold
1
9
Integrate
Hold
Reset
S1
Photodiode
Analog
Ground
11
S1
12
S2
Logic Low closes switches
13
V–
S2
Digital
Ground
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®
© 1996 Burr-Brown Corporation
SBFS009
1
PDS-1329A
IVC102
Printed in U.S.A. June, 1996
SPECIFICATIONS
At TA = +25°C, VS = ±15V, RL = 2kΩ, C INT = C1 + C2 + C3 , 1ms integration period(1), unless otherwise specified.
IVC102P, U
PARAMETER
CONDITIONS
TRANSFER FUNCTION
Gain Error
vs Temperature
Nonlinearity
Input Current Range
Offset Voltage(2)
vs Temperature
vs Power Supply
Droop Rate, Hold Mode
OP AMP
Input Bias Current
vs Temperature
Offset Voltage (Op Amp VOS)
vs Temperature
vs Power Supply
Noise Voltage
VO = ±10V
IIN = 0, CIN = 50pF
VS = +4.75/–10 to +18/–18V
DYNAMIC CHARACTERISTIC
Op Amp Gain-Bandwidth
Op Amp Slew Rate
Reset
Slew Rate
Settling Time, 0.01%
DIGITAL INPUTS
VIH (referred to digital ground)
VIL (referred to digital ground)
IIH
IIL
Switching Time
±5
mV
µV/°C
µV/V
nV/√Hz
80
100
±25
10
30
60
120
(V+)–3
(V–)+3
(V+)–1.3
(V–)+2.6
±20
500
See Typical Curve
V
V
mA
pF
2
3
MHz
V/µs
3
6
V/µs
µs
2
–0.5
100
+15
–15
4.1
–1.6
–0.2
–2.3
–40
–55
100
150
pF
ppm/°C
pF
pF
pF
5.5
0.8
V
V
µA
µA
ns
+18
–18
5.5
–2.2
V
V
mA
mA
mA
mA
85
125
°C
°C
2
0
100
+4.75
–10
TEMPERATURE RANGE
Operating Range
Storage
Thermal Resistance, θJA
DIP
SO-14
%
ppm/°C
%
µA
mV
µV/°C
µV/V
nV/µs
fA
10V Step
POWER SUPPLY
Voltage Range: Positive
Negative
Current: Positive
Negative
Analog Ground
Digital Ground
UNITS
±750
VS = +4.75/–10 to +18/–18V
f = 1kHz
(TTL/CMOS Compatible)
(Logic High)
(Logic Low)
VIH = 5V
VIL = 0V
MAX
–100
See Typical Curve
±0.5
±5
10
10
S1, S2 Open
RL = 2kΩ
RL = 2kΩ
TYP
VO = –(IIN )(TINT)/CINT
±5
+25/–17
±25
±0.005
±100
–5
±20
±30
150
750
–1
CINT = C1 + C2 + C3
INTEGRATION CAPACITORS
C1 + C2 + C3
vs Temperature
C1
C2
C3
OUTPUT
Voltage Range, Positive
Negative
Short-Circuit Current
Capacitive Load Drive
Noise Voltage
MIN
°C/W
°C/W
NOTES: (1) Standard test timing: 1ms integration, 200µs hold, 100µs reset. (2) Hold mode output voltage after 1ms integration of zero input current. Includes op
amp offset voltage, integration of input error current and switch charge injection effects.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
IVC102
2
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+ to V– .................................................................... 36V
Logic Input Voltage ...................................................................... V– to V+
Output Short Circuit to Ground ............................................... Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature ..................................................... –55°C to +125°C
Lead Temperature (soldering, 10s) ................................................. 300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PIN CONNECTIONS
Top View
14-Pin DIP/
SO-14 Surface Mount
Analog Ground
1
14 V+
IIN
2
13 Digital Ground
–In
3
12 S2
C1
4
11 S1
C2
5
10 VO
C3
6
9
V–
NC
7
8
NC
NC = No Internal Connection
Connect to Analog Ground for Lowest Noise
PACKAGE INFORMATION
PRODUCT
IVC102P
IVC102U
PACKAGE
PACKAGE DRAWING
NUMBER(1)
14-Pin DIP
SO-14 Surface Mount
010
235
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
®
3
IVC102
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, RL = 2kΩ, C INT = C1 + C2 + C3 , 1ms integration period, unless otherwise specified.
INPUT BIAS CURRENT vs TEMPERATURE
TOTAL OUTPUT NOISE vs CIN
100p
1000
rms Variation
of 100 Measurement
Cycles, TINT = 1ms.
Noise Voltage (µVrms)
Input Bias Current (A)
S1, S2 Open
10p
1p
100f
CINT = 10pF
CINT = 30pF
100
CINT = 100pF
CINT = 300pF
CINT = 1000pF
10
Reset Mode, S1 Open, S2 Closed.
10f
1
–50
–25
0
25
50
75
100
125
10
Temperature (°C)
1000
S1 CHARGE INJECTION vs INPUT CAPACITANCE
RESET TIME vs CINT
2.0
30
Charge Injection, ∆Q (pC)
0.01%
20
100pF
1.8
Time Required to
Reset from ±10V
to 0V.
25
Reset Time (µs)
100
CIN (pF)
15
10
1%
5
S1
1.6
1.4
CIN
1.2
∆VO =
1.0
∆Q
100pF
0.8
0.6
0.4
0.2
0
0
0
100
200 300 400 500 600 700
800 900 1000
10
CINT (pF)
S2 CHARGE INJECTION vs INPUT CAPACITANCE
1.0
Charge Injection, ∆Q (pC)
0.9
(V+) = +18V
0.8
0.7
(V+) = +15V
0.6
(V+) = +4.75V
0.5
S2
0.4
100pF
0.3
0.2
CIN
0.1
∆VO =
0
10
100
∆Q
100pF
1000
Input Capacitance, CIN (pF)
®
IVC102
100
Input Capacitance, CIN (pF)
4
1000
APPLICATION INFORMATION
BASIC RESET-AND-INTEGRATE MEASUREMENT
Figure 1 shows the circuit and timing for a simple reset-andintegrate measurement. The input current is connected directly to the inverting input of the IVC102, pin 3. Input
current is shown flowing out of pin 3, which produces a
positive-going ramp at VO. Current flowing into pin 3 would
produce a negative-going ramp.
Figure 1 shows the basic circuit connections to operate the
IVC102. Bypass capacitors are shown connected to the
power supply pins. Noisy power supplies should be avoided
or decoupled and carefully bypassed.
The Analog Ground terminal, pin 1, is shown internally
connected to the non-inverting input of the op amp. This
terminal connects to other internal circuitry and should be
connected to ground. Approximately 200µA flows out of
this terminal.
A measurement cycle starts by resetting the integrator output
voltage to 0V by closing S2 for 10µs. Integration of the input
current begins when S2 opens and the input current begins to
charge CINT. VO is measured with a sampling a/d converter
at the end of an integration period, just prior to the next reset
period. The ideal result is proportional to the average input
current (or total accumulated charge).
Digital Ground, pin 13, should be at the same voltage
potential as analog ground (within 100mV). Analog and
Digital grounds should be connected at some point in the
system, usually at the power supply connections to the
circuit board. A separate Digital Ground is provided so that
noisy logic signals can be referenced to separate circuit
board traces.
Switch S2 is again closed to reset the integrator output to 0V
before the next integration period.
This simple measurement arrangement is suited to many
applications. There are, however, limitations to this basic
approach. Input current continues to flow through S2 during
the reset period. This leaves a small voltage on C INT equal
to the input current times R S2, the on-resistance of S2,
approximately 1.5kΩ.
Integrator capacitors C1, C2 and C3 are shown connected in
parallel for a total CINT = 100pF. The IVC102 can be used
for a wide variety of integrating current measurements. The
input signal connections and control timing and CINT value
will depend on the sensor or signal type and other application details.
V+
+15V
0.1µF
C2
5
4
IIN
C1
14
60pF
C3
6
Figure 1a
30pF
10pF
S2
3
2
Photodiode
10
S1
1
Sampling
A/D
Converter
VO
9
Digital
Data
0.1µF
11
Analog
Ground
Logic
High
(+5V)
12
S2
See timing
signal below
13
–15V
V–
Digital
Ground
Charge Injection
of S2
0V
Figure 1b
Op Amp VOS
+
IIN • RS2
T2
T1
VO
Integrate
0V
S2
(S2 Open)
10µs
Reset
10µs
Reset
FIGURE 1. Reset-and Integrate Connections and Timing.
®
5
IVC102
measurement from the final sample at T2. Op amp offset
voltage, charge injection effects and I•RS2 offset voltage on
S2 are removed with this two-point measurement. The effective integration period is the time between the two measurements, T2-T1.
In addition, the offset voltage of the internal op amp and
charge injection of S2 contribute to the voltage on CINT at the
start of integration.
Performance of this basic approach can be improved by
sampling VO after the reset period at T1 and subtracting this
COMPARISON TO CONVENTIONAL TRANSIMPEDANCE AMPLIFIERS
VO is proportional to the integration time, TINT, and
inversely proportional to the feedback capacitor, CINT.
The effective transimpedance gain is TINT /CINT. Extremely high gain that would be impractical to achieve
with a conventional transimpedance amplifier can be
achieved with small integration capacitor values and/or
long integration times. For example the IVC102 with
CINT = 100pF and TINT = 100ms provides an effective
transimpedance of 1GΩ. A 10nA input current would
produce a 10V output after 100ms integration.
With the conventional transimpedance amplifier circuit
of Figure 2a, input current flows through the feedback
resistor, RF, to create a proportional output voltage.
VO = –IIN RF
The transimpedance gain is determined by RF. Very large
values of RF are required to measure very small signal
current. Feedback resistor values exceeding 100MΩ are
common.
The IVC102 (Figure 2b) provides a similar function,
converting an input current to an output voltage. The
input current flows through the feedback capacitor, CINT,
charging it at a rate that is proportional to the input
current. With a constant input current, the IVC102’s
output voltage is
The integrating behavior of the IVC102 reduces noise by
averaging the input noise of the sensor, amplifier, and
external sources.
VO = –IIN TINT / CINT
after an integration time of TINT.
Conventional Transimpedance Amplifier
Figure 2a
IIN
Integrating Transimpedance Amplifier
Figure 2b
IIN
RF
CINT
VO
VO
V
VO = –IIN RF
O
=
∫
–1
I (t) dt
CINT IN
for constant IIN, at the end of TINT
Provides time-continuous output
voltage proportional to IIN.
VO = –IIN
TINT
CINT
Output voltage after integration period is
proportional to average IIN throughout
the period.
FIGURE 2. Comparison to a Conventional Transimpedance Amplifier.
CURRENT-OUTPUT SENSORS
Figure 3 shows a model for many current-output sensors
such as photodiodes and ionization chambers. Sensor output
is a signal-dependent current with a very high source resistance. The output is generally loaded into a low impedance
so that the terminal voltage is kept very low. Typical sensor
capacitance values range from 10pF to over 100pF. This
capacitance plays a key role in operation of the switchedinput measurement technique (see next section).
®
IVC102
6
V+
+15V
0.1µF
3a
C3
6
C2
5
4
Photodiode
Sensor
C1
14
60pF
30pF
10pF
S2
3
2
I
R
C
10
S1
1
VO
9
A/D
Converter
Digital
Data
0.1µF
11
I: Signal - Dependent Current
R: Sensor Resistance
C: Sensor Capacitance
S1
12
S2
13
–15V
V–
See timing
signals below
Effective
Signal Integration
Period, TS
A
3b
0V
0V
VO waveform with
approx. half-scale input current.
Charge transferred
from sensor C
to CINT.
VO
(S1 Open)
S1
(S1 Closed)
(S2 Open)
S2
10µs
Hold
10µs
10µs
Reset Pre-Int.
Hold
+10mV
0V
10µs
Reset
Transfer Function
Offset Voltage
0V
A
Ramp due to
input bias current
(exaggerated).
∆Q
S1 Closing
VO
–10mV
10µs
Hold
VO waveform with
zero input current.
Op Amp
VOS
3c
B
∆Q
S1 Opening
∆Q
S2 Opening
B
FIGURE 3. Switched-Input Measurement Technique.
SWITCHED-INPUT MEASUREMENT TECHNIQUE
Input connections and timing are shown in Figure 3.
While the basic reset-and-integrate measurement arrangement in Figure 1 is satisfactory for many applications, the
switched-input timing technique shown in Figure 3 has
important advantages. This method can provide continuous
integration of the input signal. Furthermore, it can hold the
output voltage constant after integration for stable conversion (desirable for a/d converter without a sample/hold).
The timing diagram, Figure 3b, shows that S1 is closed only
when S 2 is open. During the short period that S1 is open
(30µs in this timing example), any signal current produced
by the sensor will charge the sensor’s source capacitance.
This charge is then transferred to CINT when S1 is closed. As
a result, no charge produced by the sensor is lost and the
input signal is continuously integrated. Even fast input
pulses are accurately integrated.
®
7
IVC102
OFFSET ERRORS
The input current, IIN, is shown as a conventional current
flowing into pin 2 in this diagram but the input current could
be bipolar (positive or negative). Current flowing out of pin
2 would produce a positive-ramping VO.
Figure 3c shows the effect on VO due to op amp input offset
voltage, input bias current and switch charge injection. It
assumes zero input current from the sensor. The various
offsets and charge injection (∆Q) jumps shown are typical of
that seen with a 50pF source capacitance. The specified
“transfer function offset voltage” is the voltage measured
during the hold period at B. Transfer function offset voltage
is dominated by the charge injection of S2 opening and op
amp VOS. The opening and closing charge injections of S1
are very nearly equal and opposite and are not significant
contributors.
The timing sequence proceeds as follows:
Reset Period
The integrator is reset by closing switch S2 with S1 open. A
10µs reset time is recommended to allow the op amp to slew
to 0V and settle to its final value.
Pre-Integration Hold
S2 is opened, holding VO constant for 10µs prior to integration. This pre-integration hold period assures that S2 is fully
open before S1 is closed so that no input signal is lost. A
minimum of 1µs is recommended to avoid switching overlap. The 10µs hold period shown in Figure 3b also allows an
a/d converter measurement to be made at point A. The
purpose of this measurement at A is discussed in the “Offset
Errors” section.
Note that using a two-point difference measurement at A
and B can dramatically reduce offset due to op amp VOS and
S2 charge injection. The remaining offset with this B-A
measurement is due to op amp input bias current charging
CINT. This error is usually very small and is exaggerated in
the figure.
Integration on CINT
Integration of the input current on CINT begins when S1 is
closed. An immediate step output voltage change occurs as
the charge that was stored on the input sensor capacitance is
transferred to CINT. Although this period of charging CINT
occurs only while S1 is closed, the charge transferred as S1
is closed causes the effective integration time to be equal to
the complete conversion period—see Figure 3b.
DIGITAL SWITCH INPUTS
The digital control inputs to S1 and S2 are compatible with
standard CMOS or TTL logic. Logic input pins 11 and 12
are high impedance and the threshold is approximately 1.4V
relative to Digital Ground, pin 13. A logic “low” closes the
switch.
Use care in routing these logic signals to their respective
input pins. Capacitive coupling of logic transitions to sensitive input nodes (pins 2 through 6) and to the positive power
supply (pin 14) will dramatically increase charge injection
and produce errors. Route these circuit board traces over a
ground plane (digital ground) and route digital ground traces
between logic traces and other critical traces for lowest
charge injection. See Figure 4.
The integration period could range from 100µs to many
minutes, depending on the input current and CINT value.
While S1 is closed, IIN charges CINT, producing a negativegoing ramp at the integrator output voltage, VO. The output
voltage at the end of integration is proportional to the
average input current throughout the complete conversion
cycle, including the integration period, reset and both hold
periods.
5V logic levels are generally satisfactory. Lower voltage
logic levels may help reduce charge injection errors, depending on circuit layout. Logic high voltages greater than
5.5V, or higher than the V+ supply are not recommended.
Hold Period
Opening S1 halts integration on CINT. Approximately 5µs
after S1 is opened, the output voltage is stable and can be
measured (at point B). The hold period is 10µs in this
example. CINT remains charged until a S2 is again closed, to
reset for the next conversion cycle.
Analog
Ground
Input trace guarded
all the way to sensor.
In this timing example, S1 is open for a total of 30µs. During
this time, signal current from the sensor charges the sensor
source capacitance. Care should be used to assure that the
voltage developed on the sensor does not exceed approximately 200mV during this time. The IIN terminal, pin 2, is
internally clamped with diodes. If these diodes forward bias,
signal current will flow to ground and will not be accurately
integrated.
1
•
Input nodes
guarded by
analog ground.
A maximum of 333nA signal current could be accurately
integrated on a 50pF sensor capacitance for 30µs before
200mV would be developed on the sensor.
7
I MAX = (50pF) (200mV) / 30µs = 333nA
V+
Switch logic inputs
guarded by digital
ground.
•
•
•
•
Digital
Ground
•
•
S2
•
•
S1
•
•
•
•
•
8
14
•
Pins 7 and 8 have no internal
connection but are connected to
ground for lowest noise pickup.
FIGURE 4. Circuit Board Layout Techniques.
®
IVC102
8
VO
V–
INPUT BIAS CURRENT ERRORS
CHOOSING CINT
Careful circuit board layout and assembly techniques are
required to achieve the very low input bias current capability
of the IVC102. The critical input connections are at ground
potential, so analog ground should be used as a circuit board
guard trace surrounding all critical nodes. These include
pins 2, 3, 4, 5 and 6. See Figure 4.
Internal capacitors C1, C2 and C3 are high quality metal/
oxide types with low leakage and excellent dielectric characteristics. Temperature stability is excellent—see typical
curve. They can be connected for C INT = 10pF, 30pF, 40pF,
60pF, 70pF, 90pF or 100pF. Connect unused internal capacitor pins to analog ground. Accuracy is ±20%, which
directly influences the gain of the transfer function.
Input bias current increases with temperature—see typical
performance curve Input Bias Current vs Temperature.
A larger value external CINT can be connected between pins
3 and 10 for slower/longer integration. Select a capacitor
type with low leakage and good temperature stability.
Teflon, polystyrene or polypropylene capacitors generally
provide excellent leakage, temperature drift and voltage
coefficient characteristics. Lower cost types such as NPO
ceramic, mica or glass may be adequate for many applications. Larger values for CINT require a longer reset time—see
typical curves.
HOLD MODE DROOP
Hold-mode droop is a slow change in output voltage primarily due to op amp input bias current. Droop is specified
using the internal CINT = 100pF and is based on a –100fA
typical input bias current. Current flows out of the inverting
input of the internal op amp.
Droop Rate =
–100fA
CINT
FREQUENCY RESPONSE
Integration of the input signal for a fixed period produces a
deep null (zero response) at the frequency 1/T INT and its
harmonics. An ac input current at this frequency (or its
harmonics) has zero average value and therefore produces
no output. This property can be used to position response
nulls at critical frequencies. For example, a 16.67ms integration period produces response nulls at 60Hz, 120Hz, 180Hz,
etc., which will reject ac line frequency noise and its harmonics. Response nulls can be positioned to reduce interference from system clocks or other periodic noise.
Response to all frequencies above f = 1/TINT falls at –20dB/
decade. The effective corner frequency of this single-pole
response is approximately 1/2.8TINT.
With CINT = 100pF, the droop rate is typically only
1nV/µs—slow enough that it rarely contributes significant
error at moderate temperatures.
Since the input bias current increases with temperature, the
droop rate will also increase with temperature. The droop
rate will approximately double for each 10°C increase in
junction temperature—see typical curves.
Droop rate is inversely proportional to CINT. If an external
integrator capacitor is used, a low leakage capacitor should
be selected to preserve the low droop performance of the
IVC102.
For the simple reset-and-integrate measurement technique,
TINT is equal to the to the time that S2 is open. The switchedinput technique, however, effectively integrates the input
signal throughout the full measurement cycle, including the
reset period and both hold periods. Using the timing shown
in Figure 3, the effective integration time is 1/Ts, where Ts
is the repetition rate of the sampling.
INPUT CURRENT RANGE
Extremely low input currents can be measured by integrating for long periods and/or using a small value for CINT.
Input bias current of the internal op amp is the primary
source of error.
Larger input currents can be measured by increasing the
value of CINT and/or using a shorter integration time. Input
currents greater than 200µA should not be applied to the pin
2 input, however. The approximately 1.5kΩ series resistance
of S1 will create an input voltage at pin 2 that will begin to
forward-bias internal protection clamp diodes. Any current
that flows through these protection diodes will not be accurately integrated. See “Input Impedance” section for more
information on input current-induced voltage.
INPUT IMPEDANCE
The input impedance of a perfect transimpedance circuit is
zero ohms. The input voltage ideally would be zero for any
input current. The actual input voltage when directly driving
the integrator input (pin 3) is proportional to the output slew
rate of the integrator. A 1V/µs slew rate produces approximately 100mV at pin 3. The input of the integrator can be
modeled as a resistance:
(2)
RIN = 10–7 /CINT
Input current greater than 200µA can, however, be connected directly to pin 3, using the simple reset-integrate
technique shown in Figure 1. Current applied at this input
can be externally switched to avoid excessive I•R voltage
across S2 during reset. Inputs up to 5mA at pin 3 can be
accurately integrated if CINT is made large enough to limit
slew rate to less than 1V/µs. A 5mA input current would
require CINT = 5nF to produce a 1V/µs slew rate. The input
current appears as load current to the internal op amp,
reducing its ability to drive an external load.
with RIN in Ω and CINT in Farads.
Using the internal CINT = C1 + C2 + C3 = 100pF
(3)
RIN = 10–7 /100pF = 1kΩ
Teflon E. I. Du Pont de Nemours & Co.
®
9
IVC102
Slew rate limit of the internal op amp is approximately
3V/µs. For most applications, the slew rate of VOUT should
be limited to 1V/µs or less. The rate of change is proportional to IIN and inversely proportional to CINT:
Frequency Response (dB)
0
–10
–20dB/decade
slope
Corner at
f = 0.32/TINT
Slew Rate =
–20
–3dB at
f = 0.44/TINT
–30
–40
This can be important in some applications since the slewinduced input voltage is applied to the sensor or signal
source. The slew-induced input voltage can be reduced by
increasing CINT, which reduces the output slew rate.
●●●
–50
1/10TINT
1/TINT
10/TINT
NONLINEARITY
Frequency
Careful nonlinearity measurements of the IVC102 yield
typical results of approximately ±0.005% using the internal
input capacitors (CINT = 100pF). Nonlinearity will be degraded by using an external integrator capacitor with poor
voltage coefficient. Performance with the internal capacitors
is typically equal or better than the sensors it is used to
measure. Actual application circuits with sensors such as a
photodiode may have other sources of nonlinearity.
FIGURE 5. Frequency Response of Integrating Converter.
The input resistance seen at pin 2 includes an additional
1.5kΩ, the on-resistance of S1. The total input resistance is
the sum of the switch resistance and RIN , or 2.5kΩ in this
example.
®
IVC102
I IN
C INT
10
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
IVC102U
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
IVC102U
IVC102U/2K5
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
IVC102U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
IVC102U/2K5
Package Package Pins
Type Drawing
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
9.0
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
IVC102U/2K5
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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