Texas Instruments | AWR1243 Bootloader Flow (Rev. A) | Application notes | Texas Instruments AWR1243 Bootloader Flow (Rev. A) Application notes

Texas Instruments AWR1243 Bootloader Flow (Rev. A) Application notes
Application Report
SWRA561A – May 2017 – Revised November 2018
AWR1243 Bootloader Flow
ABSTRACT
This application report describes the AWR1243 bootloader flow.
1
2
3
Contents
Introduction ................................................................................................................... 2
Basic Bootloader Flow ..................................................................................................... 5
Programming Serial Data Flash Over UART (Bootloader Service) .................................................. 10
1
Simplified Representation of AWR1243 Device ......................................................................... 2
2
Flashing Mode of Bootloader............................................................................................... 3
3
Execution Mode of Bootloader (image load from SFLASH)
List of Figures
4
5
6
7
8
9
10
........................................................... 4
Execution Mode of Bootloader (image load over SPI) .................................................................. 4
Basic Bootloader Flow Chart ............................................................................................... 5
Image Load Sequence ...................................................................................................... 6
ROM Assisted Image Download Sequence .............................................................................. 7
Bootmode - SPI .............................................................................................................. 9
HOST ↔ XWR Device UART Communication ......................................................................... 12
Flashing Sequence ......................................................................................................... 13
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AWR1243 Bootloader Flow
1
Introduction
1
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Introduction
AWR1243 Device could be broadly split as two sub-systems:
• Master Subsystem:
– Bootloader – Responsible for the device initialization, boot time tests, APLL open loop calibration,
loading of application images, downloading of images to SFLASH (device management mode,
SOP5).
– Functional firmware – Is responsible for the external host API communication, BSS API handshake,
data path (LVDS/CSI2) control, safety and monitoring of the entire device.
• Radar/Millimetre Wave Subsystem:
– Is responsible for configuring RF/analog and digital front-end in real-time, as well as to periodically
schedule calibration and functional safety monitoring. This enables the mm-Wave front-end to be
self-contained and capable of adapting itself to handle temperature and ageing effects, and to
enable significant ease-of-use from an external host perspective.
LNA
IF
ADC
LNA
IF
ADC
Digital
Front-end
(Decimation
filter chain)
IF
ADC
LNA
IF
ADC
PA
PA
PA
û-
ADC Buffer
û-
×4
Synth
(20 GHz)
Ramp
Generator
Data
RAM*
VMON
Temp
GPACD
(For RF Calbration
and Self-WHVW s 7,
Programeed)
Boot
ROM
VIM
QSPI
Serial Flash interface
DMA
SPI
External MCU interface
Mailbox
UART±
Flash Pgm.
RTI, WDT,
PMU
Debug
UARTs
For debug
ESM
Test/
Debug
JTAG for debug/
development
LVDS/
CSI2
High-speed ADC output
Interface (for processing)
ûRadio (BIST)
Processor
Osc
Prog
RAM*
Bus Matrix
LNA
Cortex R4F
at 200 MHz
Safety
(MPU,
STC,
PBIST)
Flash Programming
Prog RAM Data
and ROM RAM
eDMA
RF/Analog sub-system
Radio Processor
Sub-system
Master Sub-system
Figure 1. Simplified Representation of AWR1243 Device
2
AWR1243 Bootloader Flow
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Introduction
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•
•
•
Master subsystem is the first programmable block to get activated after AWR1243 device reset is deasserted. AWR1243 device’s bootloader is hosted in master subsystem’s read only memory (ROM)
and takes control immediately.
From this point onwards, the AWR1243 bootloader can operate in two modes: Flashing and Execution
modes.
Bootloader looks for the state of Sense On Power (SOP) I/Os (SOP lines – driven externally for
choosing the specific mode).
Table 1. Sense On Power (SOP) Lines and Boot Modes
SOP2
SOP1
SOP0
0
0
1
Bootloader mode & operation
Functional Mode
Primary deployment mode. After the patches are loaded (over SFLASH or SPI), the functional
firmware executes and the device is controlled by commands over SPI. The ADC data is available
on the high speed interface of choice (LVDS/CSI2).
1
0
1
Device Management Mode
Flash programming mode. The images (patches) are downloaded onto the SFLASH using a flashing
utility that transfers the images over the UART.
•
Device Management (Flashing) Mode of the bootloader allows an external entity to load the customer
application image to SerialDataFlash (SDF).
QSPI
SOP0
SOP1
SOP2
Serial
FLASH
User Application and
Device Firmware Flashing
x
AR1243
x
x
UART
x
x
ROM
Radar
Section
Progam
RAM
RAM
Data
RAM
Integrated
MCU
ARM* Cortex*
R4F
Flashing
Utility
Copyright © 2017, Texas Instruments Incorporated
Figure 2. Flashing Mode of Bootloader
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Introduction
•
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Execution (or Functional) Mode of the bootloader has two boot modes:
– Boot Mode – SFLASH (Development Phase)
If the presence of a Serial Flash is detected with a valid image, the bootloader relocates the image
stored in SDF to R4F and Radar section memory subsystems. Towards the end of this process,
bootloader would pass the control MSS Functional firmware.
The SFLASH is present only in development versions of the silicon where the functional firmware
(MSS and Radar section) does not execute from ROM, hence, it is a large image size.
QSPI
Serial
FLASH
SOP0
SOP1
SOP2
MSS Firmware Patch and Device
Patch to Radar Section, is loaded
from SFLASH to respective RAMS
AR1243
ROM
Radar
Section
Progam
RAM
RAM
Data
RAM
Integrated
MCU
ARM* Cortex*
R4F
Copyright © 2017, Texas Instruments Incorporated
Figure 3. Execution Mode of Bootloader (image load from SFLASH)
SOP0
SOP1
SOP2
– Boot Mode – SPI (Deployment Phase)
If the serial flash is not detected or a valid image is not detected in the serial flash, the bootloader
loads the images (patches) to the respective memories of the MSS R4F and Radar section
subsystems by receiving the data from an external host over SPI. Towards the end of this process,
the bootloader would pass the control MSS Functional firmware.
AR1243
x
ROM
Radar
Section
RAM
Progam
RAM
Data
RAM
Integrated
MCU
ARM* Cortex*
R4F
x
x
SPI
MiBSPI
x
x
Host IRQ
Programming
Utility
Copyright © 2017, Texas Instruments Incorporated
Figure 4. Execution Mode of Bootloader (image load over SPI)
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Basic Bootloader Flow
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2
Basic Bootloader Flow
A high level bootloader operation could be split into three phases:
• Device Initialization: bootloader uses “Built In Self Test” (BIST) Engines for hardware diagnostics (for
example, RAM tests)
• Sets up the root clock by starting the APLL
• Checks SOP lines to proceed with either the Flashing or Execution Modes
Flash Programming
Device Initialization
APLL open loop calibration
The below sequence
is on a per command
basis as the Mutlicore
image is parsed. The
flow is captured here
Flash program
Cmd over UART?
Functional Mode
Bootmode ± SPI
Generate MCU clock out
(at XTAL/2)
Flash programming
Over UART
SOP mode?
No
Flash present?
Bootmode - SFLASH
Setup SPI.
Generate a HostIRQ to indicate
bootup completion and await
commands.
Download MultiCore image (BSS
patch, MSS patch image) to SFLASH
Yes
Load BSS patch image from
SFLASH to program memory
Command over
SPI?
Load MSS patch image from
SFLASH to program memory
Wait Forever
Load BSS patch image over SPI to
BSS program memory
BootLoader
Execution
Load MSS patch image over SPI to
program memory
Functional Frimware Execution
Functional firmware execution
(Commands from Host over SPI)
Figure 5. Basic Bootloader Flow Chart
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AWR1243 Bootloader Flow
5
Basic Bootloader Flow
2.1
2.1.1
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Bootmode – SFLASH
Image Load Sequence
In functional mode, the bootloading of an image from the SDF is the first bootmode attempted by the
bootloader. This involves the following steps:
• Pinmux the QSPI pins of AR1243 device
– QSPI[0]: Ball R11
– QSPI[1]: Ball P9
– QSPI[2]: Ball R12
– QSPI[3]: Ball P10
– QSPI_CLK: Ball R10
– QSPI_CS_N: Ball P8
• QSPI is setup to operate at (System clock/5) = (200/5) = 40 MHz
• The SFLASH Discoverable Parameters (SFDP) command is issued to retrieve the JEDEC compliant
response that includes information regarding the SFLASH capabilities and command set. On
successful reception of the SFDP response, the information is used to communicate with the SDF and
further interpret the contents and load the images.
BootLoader
SFLASH
Read SFDP (SFLASH Discoverable Parameters)
SFDP Response
(Manuf. ID, Single/Dual/Quad, Read command, Write command)
Read MetaHeader (Loc, Size)
(Using the supported Read command)
loop
Load
Images
Read Images (Loc, Size)
(Using the supported Read command)
Figure 6. Image Load Sequence
Key Points:
• The ROM bootloader performs the read from the SDF based on the highest capability mode
(Quad/Dual/Single) as published by the SDF in response to the SFDP command.
• For SDF variants that support Quad mode, the Quad mode commands will be issued and in case the
Quad Enable (QE) bit is not set, the communication will fail. In such cases, the load flow expects that
the “Quad Enable (QE)” bit in the SDF is already set.
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AWR1243 Bootloader Flow
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Basic Bootloader Flow
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2.1.2
ROM Assisted Image Download Sequence
The ROM assisted image download sequence is entered by placing the device in flashing mode. Refer to
section 3, for further details on the handshake with an external host to receive the image. The
communication with the SDF is depicted in Figure 7.
BootLoader
SFLASH
Read SFDP (SFLASH Discoverable Parameters)
Supported SFLASH part variants
Spansion, Macronix
Note: Recommended to procure SFLASH parts
with quad mode set
SFDP Response
(Manuf. ID, Single/Dual/Quad, Read command, Write command)
If QUAD mode is supported and Quad Mode enable bit is not set,
Setup the Quad mode enable
loop
Get Image data
Over UART
Write Images (Loc, Size)
(Using the single mode Write command)
Figure 7. ROM Assisted Image Download Sequence
Key Points:
• The ROM assisted download should work with all flash variants that allow for “Memory mapped mode”
and “Page program command (0x2)” with 1 dummy byte and 24bit addressing.
• The setting of the “Quad Enable” bit varies from one SDF vendor to another. The ROM bootloader
supports setting the “Quad Enable” bit for Spansion and Macronix variants (certain specific part
variants only) in this flow.
In addition to a checksum based integrity check for every packet received over the UART, a CRC32based integrity check is performed over the complete image. The CRC32 is computed incrementally as
the packets are received and written to the SDF.
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Basic Bootloader Flow
2.2
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Bootmode – SPI
In functional mode, if no valid image header is found in the predefined SDF location, the bootloader will
enter the SPI based bootloading mode.
This involves the following steps:
• Pinmux the SPI pins - [SPI_MOSI: Ball R8, SPI_MISO: Ball P5, SPI_CLK: Ball R9, SPI_CS_N: Ball R7
and SPI_HOST_INTR: Ball P6 of AWR1243 device]
• Follows the “Communication Protocol” as defined in the Radar Interface Control document to
communicate with an external host to receive the images to be loaded as message packets over SPI.
• Once the load of all images is complete, the patches to the ROM get applied and then the functional
firmware begins execution that could then receive control API commands over SPI and send out the
data over the high speed interfaces (LVDS/CSI2).
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The handshake with the external host is as depicted in Figure 8.
XWR Device
External HOST
MSS ROM
Bootup completion
AR_AE_DEV_MSSPOWERUPDONE_SB
AR_DEV_FILE_DOWNLOAD_SB
(REM_CHUNKS (N-1), FILE_TYPE,
FILE_LENGTH and Image (1/N))
AR_ACK_MSG
AR_DEV_FILE_DOWNLOAD_SB
(REM_CHUNKS (N-2), Image (2/N))
AR_ACK_MSG
Image download over SPI
Bootloading
over SPI
AR_DEV_FILE_DOWNLOAD_SB
(REM_CHUNKS (0), Image (N/N))
AR_ACK_MSG/AR_NACK_MSG
AR_AE_MSS_BOOTERRORSTATUS_SB
(Indication of bootup status)
ROM FUNCTIONAL FIRMWARE
EXECUTION
Figure 8. Bootmode - SPI
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Programming Serial Data Flash Over UART (Bootloader Service)
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Programming Serial Data Flash Over UART (Bootloader Service)
TI’s AWR1243 device supports interfacing with an SDF to obtain the images to be loaded as a part of the
bootloading process. During the pre-production phase, the ROM is eclipsed and the majority of the
execution of the MasterSS and RadarSS firmware happens from the RAM. Hence, the image sizes being
considerably large, are loaded faster when present in the SDF with a QSPI interface.
The flash programmer connects to the device over UART. Specifics are as follows:
• MSS_UARTA [RX: Ball N5 and TX: Ball N6 of AWR1243 device]
• Baud Rate: 115200
• Maximum Data Chunk Size: 240 bytes
NOTE: Commands ‘Write File to SFLASH’ and ‘Write File to SRAM’ support a maximum data chunk
size of 240 bytes only.
The file is split into N commands where:
N = (file size/240) + ((file size%240) ? 1 : 0)
3.1
File to Download
One or more of the following binaries comprises of the files to be downloaded:
• RadarSS Image (Complete firmware (pre-production) Or Patch if any (production devices))
• MasterSS Image (Functional firmware (pre-production) Or Patch if any (production devices))
TI’s DeviceFirmwarePackage (DFP) for XWR12xx would include the necessary files to be downloaded to
both the MasterSS as well as RadarSS.
TI’s mmWaveSDK package for XWR14xx would include the “Image Creator” utility that would help
constructing the complete image with the above listed components for use with XWR14xx devices.
3.2
Flash Programming Sequence
1. Boot the device in SOP 5 mode (see Table 1)
2. Open the “UniFlash” tool. [As listed in mmWaveSDK]
3. Connect to the device over the UARTA com port. (the device expects a UART break signal – this is
generated by the UniFlash tool)
4. Flash the desired images <META_IMAGE1/ META_IMAGE2/ META_IMAGE3/ META_IMAGE4>
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3.3
Supported Commands and Format
Table 2. Supported Commands and Format
Command
Command Id
Description
PING
0x20
The device responds with ACK
OPEN FILE
0x21
Command that gives details about the type of file being
downloaded
Fields
File Size: Total File size being
downloaded.
File Type: META IMG1(4), META
IMG2(5),META IMG3(6), and META
IMG4(7)
Storage type: 2- SFLASH and 4- SRAM
WRITE FILE to
SFLASH
0x24
Command that gives the content of the file to write to
SFLASH
WRITE FILE to RAM
0x26
Command that gives the content of the file and the file
is directly written to RAM
CLOSE FILE
0x22
Command that indicates the end of file download
GET STATUS
0x23
Command that requests the status of the previous
command. The device responds with the status of the
previous command issued
ERASE DEVICE
0x28
Command to erase the contents of the SFALSH
GET VERSION
0x2F
Command that requests the version of the ROM. Device
responds with the version information
ACK response
0xCC
Response from the device.
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Storage type: 2- SFLASH and 4- SRAM
AWR1243 Bootloader Flow
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Programming Serial Data Flash Over UART (Bootloader Service)
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HOST COMMANDS TO XWR Device
GENERIC
COMMAND
STRUCTURE
OPEN
COMMAND
WRITE TO FLASH
COMMAND
CLOSE
COMMAND
PING
COMMAND
ERASE
COMMAND
GET STATUS
COMMAND
GET VERSION
COMMAND
(length -2) bytes
Max size: (243 ± 2) bytes
1 byte
2 bytes
1 byte
SYNC
(0xAA)
LENGTH
CHECK
SUM
1 byte
2 bytes
1 byte
1 byte
0xAA
0x13
CHECK
SUM
0x21
PAYLOAD
4 bytes
FILE SIZE
4 bytes
4 bytes
STORAGE TYPE
FILE TYPE
1 byte
2 bytes
1 byte
1 byte
(length -3) bytes
Max size: (243 ± 3) bytes
0xAA
LENGTH
CHECK
SUM
0x24
PAYLOAD
1 byte
2 bytes
1 byte
1 byte
0xAA
0x7
CHECK
SUM
0x22
1 byte
2 bytes
1 byte
1 byte
0xAA
0x3
0x20
0x20
1 byte
2 bytes
1 byte
1 byte
0xAA
0x3
0x28
0x28
1 byte
2 bytes
1 byte
1 byte
0xAA
0x3
0x23
0x23
1 byte
2 bytes
1 byte
1 byte
0xAA
0x3
0x2F
0x2F
4 bytes
RESERVED
4 bytes
STORAGE TYPE
XWR Device RESPONSE TO HOST
GENERIC RESPONSE
STRUCTURE
ACK RESPONSE
1 byte
LENGTH
CHEC
KSUM
2 bytes
1 byte
2 bytes
0xCC
0x00CC
0x4
2 bytes
STATUS RESPONSE
VERSION RESPONSE
(length -2) bytes
Max size: (256 ± 2) bytes
2 bytes
0x3
PAYLOAD
1 byte
1 byte
CHECK
STATUS
SUM
2 bytes
1 byte
4 bytes
8 bytes
0xE
0xCC
ROM VERSION INFORMATION
RESERVED
Figure 9. HOST ↔ XWR Device UART Communication
The 8-bit checksum in each UART command is a simple unsigned sum of the unsigned values of all the
bytes of the payload of the command, where only the least-significant 8 bits of the sum are kept. For
example, the pseudo-code to calculate the checksum would be:
checksum = 0
for each byte in the payload, checksum = (checksum + (unsigned) byte) AND (0xFF).
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The STATUS RESPONSE returned from the device is the bootloader error status based on the last
actionable command executed. Actionable commands include OPEN, WRITE TO FLASH, CLOSE, and
ERASE. Status commands like PING, GET STATUS, and GET VERSION do not affect the error status
reported in the STATUS RESPONSE. The possible returned STATUS values are as follows:
• 0x00 = INITIAL_STATUS (before any actionable commands are issued)
• 0x40 = SUCCESS
• 0x4B = ACCESS_IN_PROGRESS
• Any RESERVED fields in commands sent from the host should be set to 0x0
3.4
Flashing Sequence
Figure 10 shows the flash programming sequence. The initial handshake starts with a UART break issued
by the external host. This break is followed by the command sequence in Figure 10. The bootloader uses
a command-response protocol. So the host should wait after sending each command until an ACK
response is received from the device. Note that the GET STATUS command is unique in that it returns
only the STATUS RESPONSE message without sending an ACK response.
Figure 10. Flashing Sequence
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Key Points:
• The host processor needs to split the each file/image into smaller chunks and send each chunk in a
WRITE TO FLASH command. The LENGTH field of the command should be set to the total payload
size (which includes the image data chunk and 1 byte for the 0x24 opcode) + 2. The max chunk size
is243 - 3 = 240 bytes.
• The byte order for the words in the UART commands is big-endian (i.e. transmit most-significant byte
first). The BSS/MSS/Config images should be transmitted as bytes in the order they are in the binary
files.
• The ERASE command is not required but can be used to make sure the entire SDFLASH is cleared
before the new images are written.
• The GET STATUS command is not required but can be used to check status of device.
• The GET VERSION command not required but can be used by the host processor to allow it to
operate differently depending on the device silicon version.
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2017) to A Revision ........................................................................................................... Page
•
•
•
•
•
•
•
•
Updates were made in Section 2. ....................................................................................................... 5
Updates were made in Section 2.1.1. .................................................................................................. 6
New Section 2.1.2 was added . ......................................................................................................... 7
Updates were made in Section 3. ..................................................................................................... 10
Update was made in Section 3.1. ..................................................................................................... 10
Updates were made in Section 3.2. ................................................................................................... 10
Updates were made in Section 3.3. ................................................................................................... 11
Updates were made in Section 3.4. ................................................................................................... 13
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