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Texas Instruments MMWCAS-RF-EVM AWR1243 Cascaded Radar RF User guides
User's Guide
SWRU553 – September 2019
AWR1243 Cascaded Radar RF Evaluation Module
(MMWCAS-RF-EVM)
SWRU553 – September 2019
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AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
Copyright © 2019, Texas Instruments Incorporated
1
www.ti.com
1
2
3
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Contents
Getting Started ............................................................................................................... 4
1.1
Introduction .......................................................................................................... 4
1.2
Key Features ........................................................................................................ 5
1.3
What is Included .................................................................................................... 5
Hardware Description ...................................................................................................... 6
2.1
Block Diagram ....................................................................................................... 8
2.2
Attaching the MMWAVCAS-RF-EVM to the MMWAVCAS-DSP-EVM ...................................... 9
2.3
Power Status LED Indicators ................................................................................... 10
2.4
Reset LED Indicators ............................................................................................ 11
2.5
Connectors ......................................................................................................... 12
2.6
Antennas ........................................................................................................... 22
Design Files and Software Tools ......................................................................................... 36
3.1
Hardware Collateral .............................................................................................. 36
3.2
Software, Development Tools, and Example Codes for MMWCAS-RF-EVM ............................ 36
3.3
Critical AWR1243P Setup Notes ................................................................................ 37
PCB Dimensions and Mounting Information ........................................................................... 38
PCB Storage and Handling Recommendations ........................................................................ 40
Regulatory Information .................................................................................................... 40
List of Figures
Cascade RF EVM and companion TDA2x Host Processor Board Block Diagram
2
MMWAVCAS-RF-EVM Front View ........................................................................................ 6
3
MMWAVCAS-RF-EVM Back View ........................................................................................ 7
4
MMWAVCAS-RF-EVM System Block Diagram
5
MMWAVCAS-RF-EVM (top) attached to the MMWAVCAS-DSP-EVM (bottom)
6
7
8
9
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12
13
14
15
16
17
2
.................................
1
4
......................................................................... 8
................................... 9
MMWAVCAS-RF-EVM Power Status LED Indicators ................................................................ 10
MMWAVCAS-RF-EVM AWR1243P NRESET Status LED Indicators .............................................. 11
................................................................................................................................ 12
MMWCAS-RF-EVM (Bottom-View) Connector Placements and Callouts ......................................... 12
Host Board Connector #1 (J4), Schematic Excerpt ................................................................... 13
Host Board Connector #2 (J5), Schematic Excerpt ................................................................... 14
Antenna Axes Definition ................................................................................................... 22
PCB Antenna Arrays ...................................................................................................... 23
RX Antenna Array Dimensions .......................................................................................... 24
TX Antenna Array Dimensions .......................................................................................... 24
TX and RX Antenna Array Relative Dimensions ...................................................................... 25
Cascade RF Series-Fed, Microstrip Patch Array Antenna Element Dimensions .................................. 26
18
RX Array A Execerpt for Simulation (RX1 at the "top" of the image, RX8 at the "bottom" of the image.
RX1 highlighted in purple.) ................................................................................................ 27
19
RX Array A, RX1, 76 GHz Operation (Maximum E-plane (Phi = 90) and H-plane (Phi = 0) slices shown.
3dB beamwidths shown.) ................................................................................................. 28
20
RX Array A, RX4, 76 GHz Operation (Maximum E-plane (Phi = 90) and H-plane (Phi = 0) slices shown.
3dB beamwidths shown.) ................................................................................................. 29
21
RX Array A, RX8, 76 GHz Operation (Maximum E-plane (Phi = 90) and H-plane (Phi = 0) slices shown.
3dB beamwidths shown.) ................................................................................................. 30
22
RX Array A, RX4, 76 GHz Operation (3D Antenna Gain Pattern) ................................................... 31
23
RX Array A, RX4, 78.5 GHz Operation (3D Antenna Gain Pattern) ................................................. 32
24
TX array Excerpt for Simulation (TX1 at the "right" of the image and TX2 adjacent to TX1 to the left. TX1
highlighted in purple.) ..................................................................................................... 33
25
Combined TX Array TX1, TX2, 76 GHz, 78.5 GHz and 81 GHz Operation (Maximum E-plane (Phi = 90)
and H-plane (Phi = 0) slices shown. 3dB beamwidths shown.) ..................................................... 34
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
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27
28
29
..........................................................
LDO Bypass Enable Options in mmWave Studio .....................................................................
MMWCAS-RF-EVM Overall Mechanical Dimensions and Mounting Drill Dimensions ...........................
MMWCAS-RF-EVM PCB and Drill Stack-Up Table ...................................................................
TX Array, TX2, 78.5 GHz Operation (3D Antenna Pattern)
35
37
38
39
List of Tables
1
Key Features ................................................................................................................. 5
2
Host Board Connector #1 (J4) Connector Definition
3
4
5
6
7
.................................................................
Host Board Connector #2 (J5) Connector Definition .................................................................
Bench Power Connector (J6) ............................................................................................
RX Antenna Array Dimensions ..........................................................................................
TX Antenna Array Dimensions ..........................................................................................
Cascade RF Series-Fed, Microstrip Patch Array Antenna Element Dimensions ..................................
14
17
21
24
24
26
Trademarks
All trademarks are the property of their respective owners.
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Getting Started
1
Getting Started
1.1
Introduction
www.ti.com
The AWR1243P Cascaded Radar RF evaluation board is an AWR1243P based mmWave sensing
solution from TI implementing a 4-device, cascaded, array of AWR1243P mmWave devices. In this
cascaded radar configuration, a single master device distributes a 20 GHz LO signal betweeen all 4
devices, allowing these 4 devices to operate as a single RF transceiver. This enables support for up to 12
TX and 16 RX antenna elements. In TX beam-forming, beam-steering and MIMO/SIMO use-cases the
larger number of antenna elements allows for higher SNR and higher angular resolution compared to a
single-device system.
The Cascade Radar evalution board interfaces to a companion TI TDA2x based Host/Data Capture board
which is responsible for controlling the AWR1243P devices and receiving captured IF ADC samples. The
TI TDA2x Host/Data Capture board includes SSD storage for supporting longer term data capture
scenarios and 1Gigabit Ethernet connectivity for control and offloading captured data.
Figure 1. Cascade RF EVM and companion TDA2x Host Processor Board Block Diagram
The Cascade Radar evaluation board, when combined with a compatible host/data capture board,
contains everything needed to start evaluating a 2-device or 4-device cascaded radar solution.
4
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Getting Started
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1.2
Key Features
Table 1. Key Features
Cascade Radar RF Board
4x AWR1243P 76-81GHz Radar SoC
Integrated VCO, LO distribution, PA, LNA, ADC, 3 TX and 4 RX ARM MCU R4
Controller
AWR RF/LO Peripherals
12x TX, 16x RX Antennas
•
•
•
•
Embedded Antenna
• 4-element series-fed patch antenna, 12dBi
• ± 60 deg Azimuth 3dB
• ± 30 deg Elevation 3dB
20 GHz LO Star-Network Distribution
12 total transmitters across all 4 AWR1243 P devices
16 total receivers across all 4 AWR1243P devices
86 non-overlapping Azimuth virtual array (lambda/2)
4 minimum redundancy array (MRA) Elevation
2x Wilkinson power dividers fed by the Master AWR12x device LO output to
Master and Slave AWR1243P devices
AWR Digital Peripherals
CSI2.0 4-lane
600Mbps/Lane for 2.4 Gbps ADC IF data per device
QSPI Flash
16 Mbit QSPI flash for AWR firmware updates/deveopment
Serial Peripherals
SPI, I2C, UART, GPIO
System Temperature
TMP112 I2C Temperature Sensors
Power
Radar Power Management IC (PMIC) Solution
1.3
• 2x LP87524P Quad-Channel, Integrated FET, Buck Converters,
secondary LC filtering solution powering all 4 AWR devices
• TPS73733 LDO generating 3.3V system power
What is Included
1.3.1
Kit Hardware Contents
•
•
MMWAVCAS-RF-EVM PCB assembly
MMWAVCAS-RF-EVM mounting standoffs and screws
NOTE: The MMWAVCAS-RF-EVM is designed to be mounted to the companion TI TDA2x Cascade
Radar Host/Capture board MMWAVCAS-DSP-EVM. The combination MMWAVCAS-RF-EVM
and MMWAVCAS-RF-EVM kit is mastered through a host PC over Ethernet and USB and
the mmWave Studio software suite.
For more information on assembling, powering and configuring the full two-board system,
see the mmWave Studio and MMWAVCAS-DSP-EVM documentation. All necessary
mounting hardware and peripheral cables are expected to be provided by the host board
system.
1.3.2
mmWave Studio and Matlab Post Processing
TI
•
•
•
provides the following evalution software to get started with the Cascade Radar evaluation module
mmWave Studio GUI and Lua scriptable configuration environment
TDA2x ADC IF data capture application running on the MMWAVCAS-DSP-EVM
Matlab post processing sample codes for reading captured ADC IQ sample datasets and example
TDMA-MIMO and TX-Beamforming use modes
For details on getting started with these demos, see the mmWave Studio User's Guide. This is part of the
mmWave Studio 2.1 release (and later).
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Hardware Description
2
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Hardware Description
Figure 2 and Figure 3 show the front and rear views of the evaluation board, respectively. The front (top
layer) of the board primarily includes the AWR1243P devices and the embedded antenna arrays and 20
GHz LO splitters. The back (bottom layer) of the board primarily includes the host board connectors,
power supplies (PMIC), most other support IC and most passives.
Figure 2. MMWAVCAS-RF-EVM Front View
Front View Callouts:
1. AWR1243P #1 “Master” (U1_1)
2. AWR1243P #2 “Slave 1” (U1_2)
3. AWR1243P #3 “Slave 2” (U1_3)
4. AWR1243P #4 “Slave 3” (U1_4)
5. 20 GHz LO Wilkinson Power Divider #1 (FMCW_CLKOUT) AWR #1 and AWR #2
6. 20 GHz LO Wilkinson Power Divider #2 (FMCW_SYNCOUT) AWR #3 and AWR #4
7. LMK00804B (U4) AWR1243P 40 MHz clock distribution buffer
8. Receive antenna array
9. Transmit antenna array
10. AWR1243P reset LED indicators
11. System 5.0 V and 3.3 V power status indicators
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Figure 3. MMWAVCAS-RF-EVM Back View
Back View Callouts:
1. Host Board Connector #1 (J4) 5.0 V power, interfaces for AWR1243P #1, AWR1243P #2
2. Host Board Connector #2 (J5) 5.0 V power, interfaces forAWR1243P #3, AWR1243P #4
3. LP87524P PMIC #1 (U3) powers AWR1243P #1 and AWR1243P #4
4. LP87524P PMIC #2 (U4) powers AWR1243P #2 and AWR1243P #3
5. TPS73733 5.0V to 3.3 V LDO (U5) provides system 3.3 V power
6. Bench 5.0 V power connector (J6)
7. LMK00804B (U8) AWR1243 digital synchronization distribution buffer
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Hardware Description
2.1
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Block Diagram
The MMWAVCAS-RF-EVM consists of four AWR1243P mmWave SoC and their associated power,
clocking, synchronization, LO and RF TX and RX circuits. Each AWR1243P RF TX and RX port is routed
to an etched, series-fed, patch antenna element. Each AWR1243P on the RF board has a 4-port CSI2.0
transmitter which is used for sending radar IQ ADC data samples to an attached host processor CSI2.0
receiver set. All of the AWR1243P configuration, control and reset lines are made available on two host
interface connectors (J4 and J5) implemented with Hirose FX23-120 connectors.
Host Board
Connector #1
AWR1243P (Master1)
Master AWR Clock, LO and Trigger
Distribution
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
RX Antenna[4:1]
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
QSPI
Flash
TX[3:1]
AWR1243P (Slave2)
Resets
Resets
SOP
SOP
RX[4:1]
SPI
QSPI
Slave and Master
Slave
AWR1243
AWR1243
Slave AWR1243
Slave(Slave[1:3])
AWR1243
(Slave[3:1])
(Slave[1:3])
(Slave[1:3])
FMCW_SYNCIN1
FMCW_SYNCIN1
FMCW_SYNCIN1
FMCW_SYNCIN1
LMK00804B
1:4 Clock
Distribution
20GHz LO
20GHz LO
20GHz LO
1:2 Wilkinson
Power Divider
Wilkinson
[2:1]
Power Divider
1:2
AWR Host Board
Control and
Status
AWR Host Board
Control and
Status
UART
GPIO
GPIO
XTALP/N
AWR Radar
Data Path
AWR Radar
Data Path
TX[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
RX[4:1]
RX Antenna[4:1]
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
SPI
UART
CSI2
40MHz XTAL
Slave AWR1243
Slave AWR1243
Slave(Slave[3:1])
AWR1243
(Slave[1:3])
(Slave[1:3])
XTALP/N
FMCW_SYNCIN1
FMCW_SYNCIN1
Host Board
Connector #2
QSPI
CSI2
XTALP/N
OSC_CLKOUT
OSC_CLKOUT
MCU_CLKOUT
MCU_CLKOUT
20GHz LO
FMCW_CLKOUT
FMCW_CLKOUT
20GHz LO
FMCW_SYNCOUT
FMCW_SYNCOUT
20GHz LO
FMCW_SYNCIN1
FMCW_SYNCIN1
FMCW_SYNCIN2
FMCW_SYNCIN2
DIG_SYNCOUT
Slave AWR1243
Slave AWR1243
Slave(Slave[3:1])
AWR1243
(Slave[1:3])
(Slave[1:3])
DIG_SYNCIN
FMCW_SYNCIN1
FMCW_SYNCIN1
DIG_SYNCOUT
LMK040800B
1:4 Sync
Distribution
DIG_SYNCIN
QSPI
Flash
LMK00804B
1:4 Clock
Distribution
1:2 Wilkinson
Power Divider 2
LMK040800B
1:4 Sync
Distribution
DIG_SYNCIN
AWR1/4 1.2V
AWR1/4 1.8V
AWR2/3 1.2V
LP87524P Quad-Channel
Buck Converter PMIC 1
AWR1/4 1.0V
AWR 3.3V
5V, 8A
Host Board
Power
5V, 8A
Host Board
Power
LP87524P Quad-Channel
Buck Converter PMIC 2
AWR2/3 1.0V
TPS73733
AWR1243P (Slave4)
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
RX Antenna[4:1]
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
QSPI
Flash
LMK00804B
1:4 Clock
Distribution
AWR2/3 1.8V
TX[3:1]
AWR1243P (Slave3)
Resets
Resets
SOP
SOP
RX[4:1]
SPI
QSPI
AWR Host Board
Control and
Status
UART
GPIO
GPIO
AWR Radar
Data Path
AWR Radar
Data Path
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
RX[4:1]
RX Antenna[4:1]
TX Antenna[3:1]
TX Antenna[3:1]
TX Antenna[3:1]
SPI
UART
CSI2
XTALP/N
AWR Host Board
Control and
Status
TX[3:1]
QSPI
CSI2
XTALP/N
OSC_CLKOUT
OSC_CLKOUT
MCU_CLKOUT
MCU_CLKOUT
QSPI
Flash
LMK00804B
1:4 Clock
Distribution
FMCW_CLKOUT
FMCW_SYNCOUT
1:2 Wilkinson
Power Divider 1
LMK040800B
1:4 Sync
Distribution
FMCW_SYNCIN1
FMCW_SYNCIN1
FMCW_SYNCIN2
FMCW_SYNCIN2
DIG_SYNCOUT
DIG_SYNCOUT
DIG_SYNCIN
DIG_SYNCIN
1:2 Wilkinson
Power Divider 2
LMK040800B
1:4 Sync
Distribution
Figure 4. MMWAVCAS-RF-EVM System Block Diagram
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The AWR devices are separated into Master and Slave classes of devices. AWR1243P #1, the Master
device, utilizes the AWR1243P architecture built in VCO, LO distribution, clock distribution and frame
synchronization distribution to provide 40 MHz clock, 20 GHz LO and frame synchronization to the other
three Slave devices – AWR1243P #2, AWR1243P #3 and AWR1243P #4. This allows the system to
generate and receive synchronous FMCW chirps across the four device AWR1243P array of transmitters
and receivers.
The LO distribution follows the star-network configuration described in the AWR1243 Cascade Radar
Application Note, SWRA574A. The master AWR1243P feeds a network of two Wilkinson power dividers,
which in turn provide synchronous LO for the Master and Slave PA and mixer subsystems. All clock
distribution, synchronization distribution and LO distribution requirements are documented in this
referenced application note.
The Cascade RF board accepts 5V DC, 8A (max) power primarily through the host board connectors J4
and J5. A separate 6-pin power connector (J6) is available as an alternate power path. The primary 5V
system rail provided by the host board is converted into the various AWR1243P device rails by the
LP87524P quad-channel, monolithic, buck-converter.
2.2
Attaching the MMWAVCAS-RF-EVM to the MMWAVCAS-DSP-EVM
The MMWAVCAS-RF-EVM is designed to operate attached to the companion MMWAVCAS-DSP-EVM
host board. The MMWAVCAS-DSP-EVM host board provides 5.0V power and all necessary control
signals to reset, boot and load AWR1243P firmware.
The two boards are attached and aligned through the the Host Board Connector #1 (J4) and Host Board
Connector #2 (J5). These two connectors are keyed to prevent incorrect, 180 degree, opposite orientation.
Also, the 4 corner mounting holes and the overall board outlines match between the MMWAVCAS-RFEVM and MMWAVCAS-DSP-EVM host board. Simply depressing the J4 and J5 connectors into their
opposing connector pairs on the MMWAVCAS-DSP-EVM will connect the two EVM. Additional 25mm
mounting stand-offs and screws should be used to secure the two boards together into a single assembly.
Section 2.5.1 discusses the host board connectors.
Figure 5. MMWAVCAS-RF-EVM (top) attached to the MMWAVCAS-DSP-EVM (bottom)
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Hardware Description
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For additional information on the MMWAVCAS-DSP-EVM, see the MMWAVCAS-DSP-EVM User's Guide
on the associated technical documents collateral.
2.3
Power Status LED Indicators
The MMWAVCAS-RF-EVM board provides two LED for visually evaluating 5.0 V and 3.3 V system power
status. The 5.0 V LED will be enabled as soon as 5 V power is provided to the system through either the
primary host connectors (J4, J5) or through the bench power connector J6. The 3.3 V LED will be enabled
as soon as the TPS73733 LDO (U5) output is enabled. TPS73733 3.3 V power is enabled through the
GPIO2 output of LP87524P PMIC #1 (U3) as the last stage of the PMIC power on sequence.
Figure 6. MMWAVCAS-RF-EVM Power Status LED Indicators
Power Satus LED Callouts:
1. 5 V Power On LED (DS1) - Red LED active when 5 V power is available to MMWAVCAS-RF-EVM
board
2. 3.3 V Power On LED (DS3) - Amber LED active when TPS73733 LDO (U5) 3.3V output is enabled
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2.4
Reset LED Indicators
The MMWAVCAS-RF-EVM board provides four LED for visually evaluting AWR1243P NRESET status.
The NRESET is generated from a combination of PMIC #1 and PMIC #2 power good outputs and host
board NRESET signals. When powering on the MMWAVCAS-RF-EVM from the MMWAVCAS-DSP-EVM
the NRESET signals will be initially de-asserted. A full reset sequence will be driven later by the TDA2
host processor to initialize the AWR1243P devices.
Figure 7. MMWAVCAS-RF-EVM AWR1243P NRESET Status LED Indicators
Reset Status LED Callouts:
1. AWR1243P #1 NRESET
2. AWR1243P #2 NRESET
3. AWR1243P #3 NRESET
4. AWR1243P #4 NRESET
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LED
LED
LED
LED
(DS4)
(DS5)
(DS6)
(DS7)
-
Amber
Amber
Amber
Amber
LED active
LED active
LED active
LED active
when NRESET is de-asserted
when NRESET is de-asserted
when NRESET is de-asserted
when NRESET is de-asserted
(logic
(logic
(logic
(logic
high)
high)
high)
high)
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
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Hardware Description
2.5
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Connectors
To keep out of the field of view of the etched antenna array on the top layer (front) of the board, all
connectors are placed on the bottom layer (back) of the board.
Figure 8.
Figure 9. MMWCAS-RF-EVM (Bottom-View) Connector Placements and Callouts
Connector Callouts
• J6 - Auxillary Power Connector
• J4 - Host Board Connector (AWR #1, AWR #2)
• J5 - Host Board Connector (AWR #3, AWR #4)
• J3 - 20 GHz LO Debug Connecctor
• J2 - AWR OSC_CLKOUT Debug Header
• J1_1 - AWR #1 Debug Header
• J1_2 - AWR #2 Debug Header
• J1_3 - AWR #3 Debug Header
• J1_4 - AWR #4 Debug Header
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2.5.1
Host Board Connectors(J4, J5)
The primary connector set on the MMWAVCAS-RF-EVM is the host board connector #1 (J4) and host
board connector #2 (J5). These connectors are each implemeted with a Hirose FX23-120P-0.5SV15
Header. Connector #1 pinout containss all of the reset, boot, digital control and CSI2.0 data paths for
AWR1243P #1 and AWR1243P #2. Connector #2 pinout contains the same for AWR1243P #3 and
AWR1243P #4. Both connectors share a common 5.0V power and GND return path. Primary power to the
MMWCAS-RF-EVM is expected to be provided from a compatible host board through these connectors.
WARNING
It is required that any attached host board provide 5.0 V power
conditioning. No 5.0V power rail protection exists on the
MMWAVCAS-RF-EVM design itself. The attached host board is
expected to provide reverse polarity protectionand turn-on/off
transient suppression. This is especially import to note when
testing in an automotive alternator/battery powered system. The
MMWAVCAS-DSP-EVM host board includes an automotive 12V
input supply rail for this purpose.
Host Board Connector 1
J4
CONN_MONITOR_1
12XX_1_MCU_CLKOUT_CONN
TP32
12XX_1_MCU_CLKOUT
ClassName: 12XX_1_CSI_LVDS
12XX_1_LVDS_VALID_P
12XX_1_LVDS_VALID_N
12XX_1_LVDS_FRCLK_P
12XX_1_LVDS_FRCLK_N
12XX_1_CSI2_TX3_P
12XX_1_CSI2_TX3_N
12XX_1_CSI2_TX2_P
12XX_1_CSI2_TX2_N
12XX_1_CSI2_CLK_P
12XX_1_CSI2_CLK_N
12XX_1_LVDS_VALID_P
12XX_1_LVDS_VALID_N
12XX_1_LVDS_FRCLK_P
12XX_1_LVDS_FRCLK_N
12XX_1_CSI2_TX3_P
12XX_1_CSI2_TX3_N
12XX_1_CSI2_TX2_P
12XX_1_CSI2_TX2_N
12XX_1_CSI2_CLK_P
12XX_1_CSI2_CLK_N
TP12
XWR_CONN_TP1
ClassName: 12XX_1_CSI_LVDS
12XX_1_CSI2_TX1_P
12XX_1_CSI2_TX1_N
12XX_1_CSI2_TX0_P
12XX_1_CSI2_TX0_N
12XX_1_CSI2_TX1_P
12XX_1_CSI2_TX1_N
12XX_1_CSI2_TX0_P
12XX_1_CSI2_TX0_N
ClassName: 12XX_2_CSI_LVDS
12XX_2_LVDS_VALID_P
12XX_2_LVDS_VALID_N
12XX_2_LVDS_FRCLK_P
12XX_2_LVDS_FRCLK_N
12XX_2_CSI2_TX3_P
12XX_2_CSI2_TX3_N
12XX_2_CSI2_TX2_P
12XX_2_CSI2_TX2_N
12XX_2_CSI2_CLK_P
12XX_2_CSI2_CLK_N
12XX_2_LVDS_VALID_P
12XX_2_LVDS_VALID_N
12XX_2_LVDS_FRCLK_P
12XX_2_LVDS_FRCLK_N
12XX_2_CSI2_TX3_P
12XX_2_CSI2_TX3_N
12XX_2_CSI2_TX2_P
12XX_2_CSI2_TX2_N
12XX_2_CSI2_CLK_P
12XX_2_CSI2_CLK_N
TP15
XWR_CONN_TP2
ClassName: 12XX_2_CSI_LVDS
12XX_2_CSI2_TX1_P
12XX_2_CSI2_TX1_N
12XX_2_CSI2_TX0_P
12XX_2_CSI2_TX0_N
12XX_2_CSI2_TX1_P
12XX_2_CSI2_TX1_N
12XX_2_CSI2_TX0_P
12XX_2_CSI2_TX0_N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
P1
P2
P3
P4
MH1
12XX_1_GPIO_0
12XX_1_GPIO_1
12XX_1_GPIO_2
EXT_DIG_SYNC
12XX_1_SPI_MISO1
12XX_1_SPI_HOST_INTR1
12XX_1_SPI_CS1
12XX_1_SPI_MOSI1
12XX_1_SPI_CLK1
PMIC1_SCL
PMIC1_SDA
EXT_40MHZ_CLK_1V8
NERROR_OUT
12XX_1_UART_RX
12XX_1_UART_TX
12XX_1_MSS_LOGGER
12XX_1_BSS_LOGGER
12XX_1_SOP2_PMICCLKOUT
12XX_1_SOP1_SYNCOUT
12XX_1_SOP0_TDO
12XX_1_NRST
12XX_1_WARM_RST
12XX_1_TCK
12XX_1_TMS
12XX_1_TDO
12XX_1_TDI
12XX_1_SPI_MISO1
12XX_1_SPI_HOST_INTR1
12XX_1_SPI_CS1
12XX_1_SPI_MOSI1
12XX_1_SPI_CLK1
PMIC1_SCL
PMIC1_SDA
EXT_40MHZ_CLK_1V8
12XX_1_UART_RX
12XX_1_UART_TX
12XX_1_MSS_LOGGER
12XX_1_BSS_LOGGER
12XX_1_NRST
12XX_1_WARM_RST
12XX_1_TCK
12XX_1_TMS
12XX_1_TDI
12XX_2_SPI_MISO1
12XX_2_SPI_HOST_INTR1
12XX_2_SPI_CS1
12XX_2_SPI_MOSI1
12XX_2_SPI_CLK1
12XX_2_SPI_MISO1
12XX_2_SPI_HOST_INTR1
12XX_2_SPI_CS1
12XX_2_SPI_MOSI1
12XX_2_SPI_CLK1
12XX_2_UART_RX
12XX_2_UART_TX
12XX_2_MSS_LOGGER
12XX_2_BSS_LOGGER
12XX_2_GPIO_0
12XX_2_GPIO_1
12XX_2_GPIO_2
12XX_2_UART_RX
12XX_2_UART_TX
12XX_2_MSS_LOGGER
12XX_2_BSS_LOGGER
12XX_2_GPIO_0
12XX_2_GPIO_1
12XX_2_GPIO_2
12XX_2_NRST
12XX_2_WARM_RST
12XX_2_NRST
12XX_2_WARM_RST
12XX_2_SOP2_PMICCLKOUT
12XX_2_SOP1_SYNCOUT
12XX_2_SOP0_TDO
12XX_2_TCK
12XX_2_TMS
12XX_2_TDO
12XX_2_TDI
CONN_MONITOR_1
12XX_2_TCK
12XX_2_TMS
12XX_2_TDI
SYSTEM_5V0
MH2
FX23-120P-0.5SV15
GND
12XX_1_GPIO_0
12XX_1_GPIO_1
12XX_1_GPIO_2
EXT_DIG_SYNC
GND
C190
10V
47µF
GND
C191
10V
47µF
ClassName: SYSTEM_5V
GND
Figure 10. Host Board Connector #1 (J4), Schematic Excerpt
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Hardware Description
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Host Board Connector 2
J5
12XX_4_TDI
12XX_4_TDO
12XX_4_TMS
12XX_4_TCK
CONN_MONITOR_2
TP33
12XX_4_TDI
12XX_4_TDO
12XX_4_TMS
12XX_4_TCK
12XX_4_SOP0_TDO
12XX_4_SOP1_SYNCOUT
12XX_4_SOP2_PMICCLKOUT
12XX_4_WARM_RST
12XX_4_NRST
12XX_4_GPIO_2
12XX_4_GPIO_1
12XX_4_GPIO_0
12XX_4_BSS_LOGGER
12XX_4_MSS_LOGGER
12XX_4_UART_TX
12XX_4_UART_RX
12XX_4_SPI_CLK1
12XX_4_SPI_MOSI1
12XX_4_SPI_CS1
12XX_4_SPI_HOST_INTR1
12XX_4_SPI_MISO1
12XX_3_TDI
12XX_3_TMS
12XX_3_TCK
12XX_3_WARM_RST
12XX_3_NRST
12XX_3_BSS_LOGGER
12XX_3_MSS_LOGGER
12XX_3_UART_TX
12XX_3_UART_RX
12XX_4_WARM_RST
12XX_4_NRST
12XX_4_GPIO_2
12XX_4_GPIO_1
12XX_4_GPIO_0
12XX_4_BSS_LOGGER
12XX_4_MSS_LOGGER
12XX_4_UART_TX
12XX_4_UART_RX
12XX_4_SPI_CLK1
12XX_4_SPI_MOSI1
12XX_4_SPI_CS1
12XX_4_SPI_HOST_INTR1
12XX_4_SPI_MISO1
12XX_3_TDI
12XX_3_TDO
12XX_3_TMS
12XX_3_TCK
12XX_3_WARM_RST
12XX_3_NRST
12XX_3_SOP0_TDO
12XX_3_SOP1_SYNCOUT
12XX_3_SOP2_PMICCLKOUT
12XX_3_BSS_LOGGER
12XX_3_MSS_LOGGER
12XX_3_UART_TX
12XX_3_UART_RX
0 PMIC_BUCKEN_CONN
0 PMIC_NRST_CONN
PMIC2_TMPSNS_SDA
PMIC2_TMPSNS_SCL
PMIC_BUCKEN R145
R146
PMIC_NRST
PMIC_BUCKEN
PMIC_NRST
PMIC2_TMPSNS_SDA
PMIC2_TMPSNS_SCL
12XX_3_SPI_CLK1
12XX_3_SPI_MOSI1
12XX_3_SPI_CS1
12XX_3_SPI_HOST_INTR1
12XX_3_SPI_MISO1
TMPSNS_ALERT
12XX_3_GPIO_2
12XX_3_GPIO_1
12XX_3_GPIO_0
12XX_3_SPI_CLK1
12XX_3_SPI_MOSI1
12XX_3_SPI_CS1
12XX_3_SPI_HOST_INTR1
12XX_3_SPI_MISO1
TMPSNS_ALERT
12XX_3_GPIO_2
12XX_3_GPIO_1
12XX_3_GPIO_0
SYSTEM_5V0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
P1
P2
P3
P4
MH1
C192
10V
47µF
GND
12XX_4_CSI2_TX1_N
12XX_4_CSI2_TX1_P
XWR_CONN_TP3
12XX_4_CSI2_TX0_N
12XX_4_CSI2_TX0_P
12XX_4_CSI2_TX1_N
12XX_4_CSI2_TX1_P
TP8
ClassName: 12XX_4_CSI_LVDS
12XX_4_CSI2_CLK_N
12XX_4_CSI2_CLK_P
12XX_4_CSI2_TX2_N
12XX_4_CSI2_TX2_P
12XX_4_CSI2_TX3_N
12XX_4_CSI2_TX3_P
12XX_4_LVDS_FRCLK_N
12XX_4_LVDS_FRCLK_P
12XX_4_LVDS_VALID_N
12XX_4_LVDS_VALID_P
12XX_4_CSI2_CLK_N
12XX_4_CSI2_CLK_P
12XX_4_CSI2_TX2_N
12XX_4_CSI2_TX2_P
12XX_4_CSI2_TX3_N
12XX_4_CSI2_TX3_P
12XX_4_LVDS_FRCLK_N
12XX_4_LVDS_FRCLK_P
12XX_4_LVDS_VALID_N
12XX_4_LVDS_VALID_P
ClassName: 12XX_3_CSI_LVDS
12XX_3_CSI2_TX0_N
12XX_3_CSI2_TX0_P
12XX_3_CSI2_TX1_N
12XX_3_CSI2_TX1_P
XWR_CONN_TP4
12XX_3_CSI2_TX0_N
12XX_3_CSI2_TX0_P
12XX_3_CSI2_TX1_N
12XX_3_CSI2_TX1_P
TP13
ClassName: 12XX_3_CSI_LVDS
12XX_3_CSI2_CLK_N
12XX_3_CSI2_CLK_P
12XX_3_CSI2_TX2_N
12XX_3_CSI2_TX2_P
12XX_3_CSI2_TX3_N
12XX_3_CSI2_TX3_P
12XX_3_LVDS_FRCLK_N
12XX_3_LVDS_FRCLK_P
12XX_3_LVDS_VALID_N
12XX_3_LVDS_VALID_P
SYSTEM_PGOOD
CONN_MONITOR_2
12XX_3_CSI2_CLK_N
12XX_3_CSI2_CLK_P
12XX_3_CSI2_TX2_N
12XX_3_CSI2_TX2_P
12XX_3_CSI2_TX3_N
12XX_3_CSI2_TX3_P
12XX_3_LVDS_FRCLK_N
12XX_3_LVDS_FRCLK_P
12XX_3_LVDS_VALID_N
12XX_3_LVDS_VALID_P
SYSTEM_PGOOD
MH2
FX23-120P-0.5SV15
C193
10V
47µF
GND
ClassName: 12XX_4_CSI_LVDS
12XX_4_CSI2_TX0_N
12XX_4_CSI2_TX0_P
GND
GND
Figure 11. Host Board Connector #2 (J5), Schematic Excerpt
Table 2. Host Board Connector #1 (J4) Connector Definition
Pin
Number
14
Pin Name
Pin Type
(1)
Pin Description
1
CONN_MONITOR_1
Passive
Connection monitor - To be used
with pin 120
2
12XX_1_MCU_CLKOUT_CONN
Passive
AWR #1 MCU_CLKOUT
3
GND
Power
System ground return
4
12XX_1_LVDS_VALID_P
Output
AWR #1 LVDS
5
12XX_1_LVDS_VALID_N
Output
AWR #1 LVDS
6
GND
Power
System ground return
7
GND
Power
System ground return
8
12XX_1_LVDS_FRCLK_P
Output
AWR #1 LVDS
9
12XX_1_LVDS_FRCLK_N
Output
AWR #1 LVDS
10
GND
Power
System ground return
11
GND
Power
System ground return
12
12XX_1_CSI2_TX3_P
Output
AWR #1 CSI2 TX3
13
12XX_1_CSI2_TX3_P
Output
AWR #1 CSI2 TX3
14
GND
Power
System ground return
15
GND
Power
System ground return
16
12XX_1_CSI2_TX2_P
Output
AWR #1 CSI2 TX2
17
12XX_1_CSI2_TX2_N
Output
AWR #1 CSI2 TX2
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
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Hardware Description
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Table 2. Host Board Connector #1 (J4) Connector Definition (continued)
Pin
Number
Pin Name
Pin Type
(1)
Pin Description
18
GND
Power
System ground return
19
12XX_1_CSI2_CLK_P
Output
AWR #1 CSI2 Clock
20
12XX_1_CSI2_CLK_N
Output
AWR #1 CSI2 Clock
21
GND
Power
System ground return
22
XWR_CONN_TP1
23
GND
Power
System ground return
24
GND
Power
System ground return
25
12XX_1_CSI2_TX1_P
Output
AWR #1 CSI2 TX1
26
12XX_1_CSI2_TX1_N
Output
AWR #1 CSI2 TX1
27
GND
Power
System ground return
28
12XX_1_CSI2_TX0_P
Output
AWR #1 CSI2 TX0
29
12XX_1_CSI2_TX0_N
Output
AWR #1 CSI2 TX0
30
GND
Power
System ground return
31
GND
Power
System ground return
32
GND
Power
System ground return
33
12XX_2_LVDS_VALID_P
Output
AWR #2 LVDS
34
12XX_2_LVDS_VALID_N
Output
AWR #2 LVDS
35
GND
Power
System ground return
36
GND
Power
System ground return
37
12XX_2_LVDS_FRCLK_P
Output
AWR #2 LVDS
38
12XX_2_LVDS_FRCLK_N
Output
AWR #2 LVDS
39
GND
Power
System ground return
40
GND
Power
System ground return
41
12XX_2_CSI2_TX3_P
Output
AWR #2 CSI2 TX3
42
12XX_2_CSI2_TX3_N
Output
AWR #2 CSI2 TX3
43
GND
Power
System ground return
44
GND
Power
System ground return
45
12XX_2_CSI2_TX2_P
Output
AWR #2 CSI2 TX2
46
12XX_2_CSI2_TX2_N
Output
AWR #2 CSI2 TX2
47
GND
Power
System ground return
48
GND
Power
System ground return
49
12XX_2_CSI2_CLK_P
Output
AWR #2 CSI2 Clock
50
12XX_2_CSI2_CLK_N
Output
AWR #2 CSI2 Clock
51
GND
Power
System ground return
52
XWR_CONN_TP2
53
GND
Power
System ground return
54
GND
Power
System ground return
55
12XX_2_CSI2_TX1_P
Output
AWR #2 CSI2 TX1
56
12XX_2_CSI2_TX1_N
Output
AWR #2 CSI2 TX1
57
GND
Power
System ground return
58
12XX_2_CSI2_TX0_P
Output
AWR #2 CSI2 TX0
59
12XX_2_CSI2_TX0_P
Output
AWR #2 CSI2 TX0
60
GND
Power
System ground return
61
AWR1_GPIO0
Bidirectional
AWR #1 GPIO0
62
AWR1_GPIO1
Bidirectional
AWR #1 GPIO1
63
AWR1_GPIO2
Bidirectional
AWR #1 GPIO2
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Passive
Passive
Unused
Unused
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
Copyright © 2019, Texas Instruments Incorporated
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Hardware Description
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Table 2. Host Board Connector #1 (J4) Connector Definition (continued)
Pin
Number
16
Pin Name
Pin Type
(1)
Input
Pin Description
64
EXT_DIG_SYNC
65
GND
Power
System ground return
66
12XX_1_SPI_MISO1
Output
AWR#1 SPI Slave MISO
67
12XX_1_SPI_HOST_INTR1
Output
AWR#1 SPI Slave Interrupt
68
12XX_1_SPI_CS1
Input
AWR#1 SPI Slave CS0N
69
12XX_1_SPI_MOSI1
Input
AWR#1 SPI Slave MOSI
70
12XX_1_SPI_CLK1
Input
AWR#1 SPI Slave SCLK
71
GND
72
PMIC1_SCL
Input
LP8752 4P (U3) PMIC I2C
73
PMIC1_SDA
Bidirectional
LP8752 4P (U3) PMIC I2C
74
EXT_40MHZ_CLK_1V8
Input
Optional 40 MHz clock input for
AWR #1 (U1_1) CLKP.
75
NERROR_OUT
Input
Open-Drain Logic OR
ERROR_OUT from AWR#1, 2, 3
and 4
76
GND
77
12XX_1_UART_RX
Input
AWR#1 UART RX
78
12XX_1_UART_TX
Output
AWR#1 UART TX
79
12XX_1_MSS_LOGGER
Output
AWR #1 MSS debug log UART
output
80
12XX_1_BSS_LOGGER
Output
AWR #1 MSS debug log UART
output
81
GND
Power
System ground return
82
12XX_1_SOP2_PMICCLKOUT
Input
AWR#1 PMICCLKOUT/SOP2
83
12XX_1_SOP1_SYNCOUT
Input
AWR#1 SYNCOUT/SOP1 signal
84
12XX_1_SOP0_TDO
Input
AWR#1 TDO/SOP0 signal
85
12XX_1_NRST
Input
AWR#1 NRESET signal
86
12XX_1_WARM_RST
Input
AWR#1 WARM_RESET signal
87
GND
88
12XX_1_TCK
89
90
Power
Power
Power
Alternative input to AWRx digital
sync fanout buffer (U8)
System ground return
System ground return
System ground return
Input
AWR #1 JTAG
12XX_1_TMS
Input
AWR #1 JTAG
12XX_1_TDO
Output
AWR #1 JTAG
91
12XX_1_TDI
Input
AWR #1 JTAG
92
GND
Power
System ground return
93
12XX_2_SPI_MISO1
Output
AWR#2 SPI Slave MISO
94
12XX_2_SPI_HOST_INTR1
95
GND
96
97
Input
AWR#2 SPI Slave Interrupt
Power
System ground return
12XX_2_SPI_CS1
Input
AWR#2 SPI Slave CS
12XX_2_SPI_MOSI1
Input
AWR#2 SPI Slave MOSI
98
12XX_2_SPI_CLK1
Input
AWR#2 SPI Slave SCLK
99
GND
Power
System ground return
100
12XX_2_UART_RX
Output
AWR#2 UART RX - TDA2x TX to
AWR RX
101
12XX_2_UART_TX
Input
AWR#2 UART TX - AWR TX to
TDA2x RX
102
12XX_2_MSS_LOGGER
Output
AWR #1 MSS debug log UART
output
103
12XX_2_BSS_LOGGER
Output
AWR #1 BSS debug log UART
output
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
Copyright © 2019, Texas Instruments Incorporated
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Hardware Description
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Table 2. Host Board Connector #1 (J4) Connector Definition (continued)
Pin
Number
Pin Name
Pin Type
(1)
Power
Pin Description
104
GND
105
12XX_2_GPIO_0
Bidirectional
AWR #1 GPIO0
106
12XX_2_GPIO_1
Bidirectional
AWR #1 GPIO1
107
12XX_2_GPIO_2
Bidirectional
AWR #1 GPIO2
108
GND
Power
System ground return
109
12XX_2_NRST
Output
AWR#2 NRESET signal
110
12XX_2_WARM_RST
Output
AWR#2 WARM_RESET signal
111
GND
Power
System ground return
112
12XX_2_SOP2_PMICCLKOUT
Output
AWR#2 PMICCLKOUT/SOP2
113
12XX_2_SOP1_SYNCOUT
Output
AWR#2 SYNCOUT/SOP1 signal
114
12XX_2_SOP0_TDO
Output
AWR#2 TDO/SOP0 signal
115
GND
Power
System ground return
116
12XX_2_TCK
Input
AWR #2 JTAG
117
12XX_2_TMS
Input
AWR #2 JTAG
118
12XX_2_TDO
Output
AWR #2 JTAG
119
12XX_2_TDI
Input
AWR #2 JTAG
120
CONN_MONITOR_1
P1
GND
Power
Ground return
P2
GND
Power
Ground return
P3
EVM_5V0
Power
System 5.0V power
P4
Passive
System ground return
Connection monitor - To be used
with pin 1
EVM_5V0
Power
System 5.0V power
MH1
GND
Power
Plated mounting hole used for
additional ground return
MH2
GND
Power
Plated mounting hole used for
additional ground return
(1) Pin direction relative to the MMWAVCAS-RF-EVM. Output are signals generated by transmitters on the MMWCAS-RF-EVM.
Inputs are signal intended for receivers on the MMWCAS-RF-EVM.
Table 3. Host Board Connector #2 (J5) Connector Definition
Pin
Number
Pin Name
Pin Type
Pin Description
Passive
Connection monitor - To be used
with pin 120
1
CONN_MONITOR_2
2
12XX_4_TDI
Input
AWR #4 JTAG
3
12XX_4_TDO
Output
AWR #4 JTAG
4
12XX_4_TMS
Input
AWR #4 JTAG
5
12XX_4_TCK
Input
AWR #4 JTAG
6
GND
Power
Ground return
7
12XX_4_SOP0_TDO
Input
AWR#4 TDO/SOP0
8
12XX_4_SOP1_SYNCOUT
Input
AWR#4 SYNCOUT/SOP1
Input
AWR#4 PMICCLKOUT/SOP2
9
12XX_4_SOP2_PMICCLKOUT
10
GND
11
12XX_4_WARM_RST
Input
AWR#4 WARM_RESET signal
12
12XX_4_NRST
Input
AWR#4 NRESET signal
13
GND
14
12XX_4_GPIO_2
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Power
Power
Bidirectional
Ground return
Ground return
AWR #4 GPIO2
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
Copyright © 2019, Texas Instruments Incorporated
17
Hardware Description
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Table 3. Host Board Connector #2 (J5) Connector Definition (continued)
Pin
Number
18
Pin Name
Pin Type
Pin Description
15
12XX_4_GPIO_1
Bidirectional
AWR #4 GPIO1
16
12XX_4_GPIO_0
Bidirectional
AWR #4 GPIO0
17
GND
18
12XX_4_BSS_LOGGER
Passive
AWR #4 BSS debug log UART
output
19
12XX_4_MSS_LOGGER
Passive
AWR #4 MSS debug log UART
output
20
12XX_4_UART_TX
Output
AWR #4 UART TX
21
12XX_4_UART_RX
Input
AWR #4 UART RX
22
GND
Power
Ground return
23
12XX_4_SPI_CLK1
Output
AWR #4 SPI CLK
24
12XX_4_SPI_MOSI1
Output
AWR #4 SPI MOSI
25
12XX_4_SPI_CS1
Output
AWR #4 SPI CS
26
GND
Power
Ground return
27
12XX_4_SPI_HOST_INTR1
Input
AWR #4 SPI Host Interrupt
28
12XX_4_SPI_MISO1
Input
AWR #4 SPI MISO
29
GND
30
31
Power
Ground return
Power
Ground return
12XX_3_TDI
Input
AWR #3 JTAG
12XX_3_TDO
Output
AWR #3 JTAG
32
12XX_3_TMS
Input
AWR #3 JTAG
33
12XX_3_TCK
Input
AWR #3 JTAG
34
GND
Power
Ground return
35
12XX_3_WARM_RST
Input
AWR#4 WARM_RESET signal
36
12XX_3_NRST
Input
AWR#4 NRESET signal
37
12XX_3_SOP0_TDO
Input
AWR #3 TDO/SOP0
38
12XX_3_SOP1_SYNCOUT
Input
AWR #3 SYNCOUT/SOP1
39
12XX_3_SOP2_PMICCLKOUT
Input
AWR #3 MICCLKOUT /SOP2
40
GND
41
12XX_3_BSS_LOGGER
Passive
AWR #3 BSS debug log UART
output
42
12XX_3_MSS_LOGGER
Passive
AWR #3 MSS debug log UART
output
43
12XX_3_UART_TX
Input
AWR #3 UART TX
44
12XX_3_UART_RX
Output
AWR #3 UART RX
45
GND
Power
Ground return
46
PMIC_BUCKEN_CONN
47
PMIC_NRST_CONN
48
PMIC2_TMPSNS_SDA
Bidirectional
LP87524P (U4) and TMP112
(U9, U10) I2C
49
PMIC2_TMPSNS_SCL
Input
LP87524P (U4) and TMP112
(U9, U10) I2C
50
GND
51
12XX_3_SPI_CLK1
Input
AWR #3 SPI CLK
52
12XX_3_SPI_MOSI1
Input
AWR #3 SPI MOSI
53
12XX_3_SPI_CS1
Input
AWR #3 SPI CS
54
12XX_3_SPI_HOST_INTR1
Output
AWR #3 SPI Host Interupt
55
12XX_3_SPI_MISO1
Output
AWR #3 SPI MISO
Power
Ground return
PassInputive
LP87524P (U3) and (U4) power
enable input
Passive
LP87524P (U3) and (U4) reset
input
Power
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Table 3. Host Board Connector #2 (J5) Connector Definition (continued)
Pin
Number
Pin Name
Pin Type
Pin Description
56
GND
Power
Ground return
57
TMPSNS_ALERT
Output
TMP112 (U9, U10) I2C
temperature alert (3.3V opendrain)
58
12XX_3_GPIO_2
Bidirectional
AWR #3 GPIO2
59
12XX_3_GPIO_1
Bidirectional
AWR #3 GPIO1
60
12XX_3_GPIO_0
Bidirectional
AWR #3 GPIO0
61
GND
Power
Ground return
62
12XX_4_CSI2_TX0_N
Output
AWR #4 CSI2 TX0
63
12XX_4_CSI2_TX0_P
Output
AWR #4 CSI2 TX0
64
GND
Power
Ground return
65
12XX_4_CSI2_TX1_N
Output
AWR #4 CSI2 TX1
66
12XX_4_CSI2_TX1_P
Output
AWR #4 CSI2 TX1
67
GND
Power
Ground return
68
GND
Power
Ground return
69
XWR_CONN_TP3
70
GND
Power
Ground return
71
12XX_4_CSI2_CLK_N
Output
AWR #4 CSI2 Clock
72
12XX_4_CSI2_CLK_P
Output
AWR #4 CSI2 Clock
73
GND
Power
Ground return
74
GND
Power
Ground return
75
12XX_4_CSI2_TX2_N
Output
AWR #4 CSI2 TX2
76
12XX_4_CSI2_TX2_P
Output
AWR #4 CSI2 TX2
77
GND
Power
Ground return
78
GND
Power
Ground return
79
12XX_4_CSI2_TX3_P
Output
AWR #4 CSI2 TX3
80
12XX_4_CSI2_TX3_P
Output
AWR #4 CSI2 TX3
81
GND
Power
Ground return
82
GND
Power
Ground return
83
12XX_4_LVDS_FRCLK_N
Output
AWR #4 LVDS
84
12XX_4_LVDS_FRCLK_P
Output
AWR #4 LVDS
85
GND
Power
Ground return
86
GND
Power
Ground return
87
12XX_4_LVDS_VALID_N
Output
AWR #4 LVDS
88
12XX_4_LVDS_VALID_P
Output
AWR #4 LVDS
89
GND
Power
Ground return
90
GND
Power
Ground return
91
GND
Power
Ground return
92
12XX_3_CSI2_TX0_N
Output
AWR #3 CSI2 TX
93
12XX_3_CSI2_TX0_P
Output
AWR #3 CSI2 TX0
94
GND
Power
Ground return
95
12XX_3_CSI2_TX1_N
Output
AWR #3 CSI2 TX1
96
12XX_3_CSI2_TX1_P
Output
AWR #3 CSI2 TX1
97
GND
Power
Ground return
98
GND
Power
Ground return
99
XWR_CONN_TP4
100
GND
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Passive
Power
Unused
Unused
Ground return
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Table 3. Host Board Connector #2 (J5) Connector Definition (continued)
Pin
Number
20
Pin Name
Pin Type
Pin Description
101
12XX_3_CSI2_CLK_N
Output
AWR #3 CSI2 TX2
102
12XX_3_CSI2_CLK_P
Output
AWR #3 CSI2 TX2
103
GND
Power
Ground return
104
12XX_3_CSI2_TX2_N
105
12XX_3_CSI2_TX2_P
106
GND
Power
Ground return
107
GND
Power
Ground return
108
12XX_3_CSI2_TX3_N
Input
AWR #3 CSI2 TX3
109
12XX_3_CSI2_TX3_P
Input
AWR #3 CSI2 TX3
110
GND
111
GND
112
12XX_3_LVDS_FRCLK_N
113
12XX_3_LVDS_FRCLK_P
Passive
AWR #3 LVDS
114
GND
Power
Ground return
115
GND
Power
Ground return
116
12XX_3_LVDS_VALID_N
Passive
AWR #3 LVDS
117
12XX_3_LVDS_VALID_P
Passive
AWR #3 LVDS
118
GND
Power
Ground return
119
SYSTEM_PGOOD
Output
System power good. Wired logic
OR from LP87524P (U3, U4)
PMIC.
120
CONN_MONITOR_2
Passive
Connection monitor - To be used
with pin 1
P1
SYSTEM_5V0
Power
System 5.0V power
P2
SYSTEM_5V0
Power
System 5.0V power
P3
GND
Power
Ground return
P4
GND
Power
Ground return
MH1
GND
Power
Ground return
MH2
GND
Power
Ground return
Input
AWR #3 CSI2 TX2
Input
AWR #3 CSI2 TX2
Power
Ground return
Power
Ground return
Passive
AWR #3 LVDS
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2.5.2
Bench Power Connector(J6)
A separate, 6-pin, Molex Minifit Jr connector provides for the connection of bench 5.0 V power to the
MMWAVCAS-RF-EVM. 5.0 V power, GND return and a 5.0 V sense and GND sense path are also
provided for a 4-terminal, "Kelvin" connection.
NOTE: The Host Board Connectors, J4, and J5 are the primary 5.0 V power inputs to the
MMWCAS-RF-EVM. If this bench power connector, J6, is to be used, an attached host board
should ensure that either the J4, J5, 5.0 V nets are being supplied from the same supply
sourcing J6, or that the 5.0 V nets on J4 and J5 are open and not providing 5.0 V power to
the MMWCAS-RF-EVM.
The MMWCAS-DSP-EVM host board has no method of disconnecting these 5.0 V power
nets and therefore it is incompatible with this J6 bench power connector.
WARNING
It is required that any attached host board provide 5.0V power
conditioning. No 5.0 V rail protection exists on the MMWAVCASRF-EVM design itself. The attached host board is expected to
provide reverse polarity protection and turn-on/off transient
suppression. This is especially import to note when testing in an
automotive alternator/battery powered system.
Table 4. Bench Power Connector (J6)
Pin Number
2.5.3
Pin Name
Pin Type
Pin Description
1
GND_SENSE
Power
GND return sense path
2
GND
Power
GND return
3
GND
Power
GND return
4
SYSTEM_5V0_SENSE
Power
5.0V sense path
5
SYSTEM_5V0
Power
5.0V System Power
6
SYSTEM_5V0
Power
5.0V System Power
20 GHz LO Debug Connector (J3)
J3 is a footprint for a Rosenberger model 19S101-40ML5, 50-ohm, SMP connector capable of 26 GHz
operation with very low loss and reflection. This connector exposes the 12XX_3_FMCW_CLKOUT 20 GHz
local oscillator (LO) net from AWR #3. Depending on how the AWR #3 is configured, this connector allows
the user to sample an example AWR master-mode or slave-mode LO output signal. This connector is not
installed by default.
2.5.4
AWR OSC_CLKOUT Debug Header (J2)
A footprint for terminal strip of 25 mil square posts, 100 mil pitch, are provided to enable sampling of the
AWR #1, #2, #3 and #4 OSC_CLKOUT paths. These terminal strips are not installed by default.
2.5.5
AWR Debug Headers (J1_1, J1_2, J1_3, J1_4)
A footprint for terminal strip of 25 mil square posts, 100 mil pitch, are provided to enable sampling of the
AWR #1, #2, #3 and #4 GPADC debug headers. These terminal strips are not installed by default.
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2.6
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Antennas
Each of the 12 TX channels and 16 RX channels (across the 4 AWR1243P cascaded radar devices) is
routed to an etched antenna element. This antenna array allows for the creation of MIMO and TXBeamforming array generation, allowing for high angular resolution and longer range detection of targets
in a 3D space.
The antenna array axes are defined such that the azimuth axis is along the XZ-plane with azimuth boresight along the +Z-axis. Likewise, the elevation axis is along the YZ-plane with elevation bore-sight along
the +Z-axis. Antenna patterns presented are relative to these axes as well. The E-plane defined
polarization (Phi = 90 in spherical coordinates) being along the YZ-plane and the H-plane being (Phi = 0 in
spherical coordinates) along the XZ-plane.
+Y
+X
+Z
Figure 12. Antenna Axes Definition
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2.6.1
TX and RX Antenna Arrays
The following sections describe the TX and RX antenna array structures included on the board. The
element spacing information can be used to form the necessary processing models of the MIMO virtual
array and Beam-Forming phased array.
Figure 13. PCB Antenna Arrays
Reset Status LED Callouts:
1. RX Array A - 8, lambda/2, linear elements - azimuth displacement only
2. RX Array B – 4, lambda/2, linear elements - azimuth displacement only
3. RX Array C – 4, lambda/2, linear elements - azimuth displacement only
4. TX array – 9, lambda × 2, linear elements in azimuth. 4 minimum redundancy array (MRA) elements in
elevation.
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A2
A3
A1
A4
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
Lambda @ 77 GHz = 153.56 mil
A1 = lambda* 0.5 = 76.78 mil
A2 = 26.5 * lambda = 4069.34 mil
A3 = 4 * lambda = 614.24 mil
A4 =16 * lambda = 2456.96 mil
A5 = lambda * 7.759 = 1191.5 mil
A6 = lambda * 2 = 307.12 mil
B1 = lambda * 19.072 = 2928.84 mil
RX ARRAY B
RX ARRAY C
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
B2 = lambda * 0.5 = 76.78 mil
B3 = lambda * 1.5 = 230.36 mil
B4 = lambda * 1.0 = 153.56 mil
RX ARRAY A
Figure 14. RX Antenna Array Dimensions
Table 5. RX Antenna Array Dimensions
Dimension Label
Dimension (mils)
Dimension (78.5 GHz lambda)
A1
76.78
0.5
A2
4069.34
26.5
A3
614.24
4.0
A4
2456.96
16.0
A6
A6
A6
A6
A6
A6
A6
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
B4
B3
B2
A1
A1
A1
A1
Figure 15. TX Antenna Array Dimensions
Table 6. TX Antenna Array Dimensions
24
Dimension Label
Dimension (mils)
A1
76.78
0.5
A5
1191.5
7.759
A6
307.12
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Table 6. TX Antenna Array Dimensions (continued)
Dimension Label
Dimension (mils)
Dimension (77 GHz lambda)
B1
2928.84
19.072
B2
76.78
0.5
B3
230.36
1.5
B4
153.56
1.0
RX ARRAY B
RX ARRAY C
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
A2
RX ARRAY A
B1
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
TX/RX Signal
A5
TX ARRAY
Figure 16. TX and RX Antenna Array Relative Dimensions
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2.6.2
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PCB Antenna Element
Each TX/RX antenna element is implemented as a series-fed, Microstrip patch array. The following figures
and tables describe this antenna element. The element is implemted with a GCPW feed to Microstrip
transition, and then Microstrip stub matching into the first patch of the seried-fed array.
D1
F1
H
E2
D2
F3
GND
E1
E1
F2
TX/RX Signal
TX/RX Signal
GND
G
B1
A1
B2
A2
C1
B3
C2
B4
C2
C1
L1-L2 Ground Laser Micro-Via
5.9 mil drill diameter
13.77 mill pad diameter
Figure 17. Cascade RF Series-Fed, Microstrip Patch Array Antenna Element Dimensions
Table 7. Cascade RF Series-Fed, Microstrip Patch Array Antenna Element Dimensions
Dimension Label
Dimension (mils)
A1
27.568
A2
11.802
B1
47.24
B2
49.21
B3
45.27
B4
49.21
C1
42.52
C2
40.95
D1
16.722
D2
20.002
E1
39.38
E2
55.12
F1
8.4
F2
10.62
F3
G
3.94
(1)
> 78.7402
H
<= 20.67
(1) Dimension G is the is the minimum keepout from any structure adjacent to the antenna (vias, traces, copper pours, and so
forth).
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2.6.2.1
RX Antenna Element Performance
Simulated RX antenna performance from RX Array A is shown below. Three different RX antenna were
excerpted to show the overall performance across the array. These excerpted antenna are labeled RX1,
RX4 and RX8 shown. This selection is meant to highlight behavior of the RX antenna near the edge of the
RX antenna rrays and near the center of the arrays. Due to coupling between antenna, the performance
near the edge of the array changes from the performance near the center of the array.
Figure 18. RX Array A Execerpt for Simulation (RX1 at the "top" of the image, RX8 at the "bottom" of the
image. RX1 highlighted in purple.)
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Figure 19. RX Array A, RX1, 76 GHz Operation (Maximum E-plane (Phi = 90) and H-plane (Phi = 0) slices
shown. 3dB beamwidths shown.)
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Figure 20. RX Array A, RX4, 76 GHz Operation (Maximum E-plane (Phi = 90) and H-plane (Phi = 0) slices
shown. 3dB beamwidths shown.)
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Figure 21. RX Array A, RX8, 76 GHz Operation (Maximum E-plane (Phi = 90) and H-plane (Phi = 0) slices
shown. 3dB beamwidths shown.)
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Figure 22. RX Array A, RX4, 76 GHz Operation (3D Antenna Gain Pattern)
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Figure 23. RX Array A, RX4, 78.5 GHz Operation (3D Antenna Gain Pattern)
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2.6.2.2
TX Antenna Element Performance
Simulated TX antenna performance from center of the TX Array is shown below. Six different TX antenna
were excerpted to show the overall performance across the array. These excerpted antenna are labeled
TX1 and TX2. Like the RX antenna simulations, the TX selected here are meant to highlight the
differences in performance between the more widely separated antenna and the more closely placed
antenna.
Figure 24. TX array Excerpt for Simulation (TX1 at the "right" of the image and TX2 adjacent to TX1 to the
left. TX1 highlighted in purple.)
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Figure 25. Combined TX Array TX1, TX2, 76 GHz, 78.5 GHz and 81 GHz Operation (Maximum E-plane (Phi
= 90) and H-plane (Phi = 0) slices shown. 3dB beamwidths shown.)
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Figure 26. TX Array, TX2, 78.5 GHz Operation (3D Antenna Pattern)
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Design Files and Software Tools
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3
Design Files and Software Tools
3.1
Hardware Collateral
All PCB design documents for the MMWCAS-RF-EVM are available on ti.com enabling AWR1243P users
to fabricate, modify and extend the MMWCAS-RF-EVM to suite their own specific use-case requirements.
This design was created with Altium Designer 18.
MMWCAS-RF-EVM Rev C Design:
• MMWCAS-RF-EVM PCB Schematics, Layout, Assembly, and BOM Details
3.2
Software, Development Tools, and Example Codes for MMWCAS-RF-EVM
The Cascade Radar kit belongs to a larger TI ecosystem of hardware and software tools.
To enable immediate evaluation of the Cascade Radar kit TI provides the mmWave Studio RF evaluation
GUI and Lua scripting environment. This mmWave Studio tool interfaces to the MMWCAS-RF-EVM
through the MMWCAS-DSP-EVM host board and masters the TDA2Sx host processor, enabling
configuration, control and data capture of the AWR1243P devices on the MMWCAS-RF-EVM. mmWave
Studio includes example single-device, multi-device MIMO and multi-device TX-beamforming
configurations. Example capture Lua scripts are also included.
A Matlab code base for MIMO and TX-Beamforming post-processing and calibration has also been
developed and included in mmWave Studio. This post-processing code is designed to work on the raw
captured ADC samples and includes examples of basic 1D, 2D and 3D-FFT processing for creating
range-doppler and point-cloud datasets from the MIMO and TX-Beamforming data.
To enable development of an end application with single-device and cascaded AWR1243P, TI provides
the device firmware packages (DFP).
The DFP includes the MSS and BSS firmware, or firmware patches, as well as the mmWave Link
Framework and framework implementation examples. The mmWave Link Framework provides a C-source
implementation of the AWRx Interface Control Document (ICD) defined API.
Links:
• MMWCAS-DSP-EVM
• mmWave Studio (MMWAVE-STUDIO)
• AWR1243 DFP (MMWAVE-DFP)
• RTOS Processor SDK for Radar
• PROCESSOR-SDK-VISION
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3.3
Critical AWR1243P Setup Notes
This section covers critical details concerning setup of the AWR1243P devices on the Cascade RF board.
3.3.1
LDO Bypass Requirement
The MMWCAS-RF-EVM use a 1.0-V supply on the RF1 and RF2 power rails of each AWR1243P device.
To support simultaneous, 3 TX operation, the VOUT_PA output is shorted to the RF2 1.0 V power rail. For
best performance and to prevent damage to the device, the on-die 1.3 V to 1.0 V LDO must be bypassed.
This is done in a few different ways.
When using mmWave studio to configure the AWR1243P devices, select the 'RF LDO Bypass Enable'
and 'PA LDO I/P Disable' options in the Static Configuration tab prior to RF initialization.
Likewise, when issuing DFP API commands to the device, the RF LDO bypass can be configured using
the AWR_RF_LDO_BYPASS_SB API from the host processor. To enable the RF LDO Bypass and PA
LDO I/P Disable through the API, issue an ar1.RfLdoBypassConfig(0x3) command.
Figure 27. LDO Bypass Enable Options in mmWave Studio
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PCB Dimensions and Mounting Information
4
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PCB Dimensions and Mounting Information
The field of view of the radar sensor is orthogonal to the PCB top layer where the etched antenna are
placed. See the above antenna sections for more details on the antenna element gain patterns.
Mounting to the MMWCAS-DSP-EVM is accomplished through the 4, plated, through-holes in each corner
of the PCB. An optional pattern of 4, plated through-hole are provided in the same lateral area as the
AWR1243P devices and are meant to support a user-designed heat-sink plate across the AWR1243P
packages.
Figure 28. MMWCAS-RF-EVM Overall Mechanical Dimensions and Mounting Drill Dimensions
The MMWCAS-RF-EVM PCB is composed of an 8-layer, heterogenous, sequential lamination, stack-up.
Rogers RO3003 is used for the Layer 1 RF GCPW routing, etched antenna structtures and the 20 GHz
LO splitters. RO4450F prepreg and RO4835 LoPro are used to create Stripline routing on Layer 3 for 20
GHz LO distribution. The lower 4 core and prepreg layers are in Isola 370HR. These layers are dedicated
to power distribution and high-speed digital routing.
38
AWR1243 Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
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PCB Dimensions and Mounting Information
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Figure 29. MMWCAS-RF-EVM PCB and Drill Stack-Up Table
Three via types are utilized throughout the design:
• L1-L8, 12.2mil drill, 22.4 mil pad - primary via used throughout the design for power and high-speed
digital routing
• L1-L2, 5.9 mil drill, 13.77 mil pad (blind, micro-via) - L1 to L2 ground plane shorting for RF and LO
routing distribution
• L1-L3, 12 mil drill, 24 mil pad, (backdrilled up to L3) - 20 GHz LO distribution L1 GCPW to L3 Stripline
transition
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PCB Storage and Handling Recommendations
5
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PCB Storage and Handling Recommendations
All of the 77-81GHz RF and 20 GHz LO transmission-line and antenna structures on this design have
been left exposed on the top soldermask layer. An immersion silver finish is applied to these solder-mask
free regions to protect the underlying copper. The immersion silver finish provides the RF structures with a
more simple and controlled high-frequency finish compared to soldermask.
However, the immersion silver finish is also prone to oxidation in an open atmosphere environment. This
oxidation causes the surface around the antenna region to blacken or tarnish as a layer of silver-oxide
forms. To avoid this effect, store the PCB in an ESD cover and keep it at controlled room temperature with
low humidity conditions. It should be noted though that transmission lines and antenna which are
tarnished will not experiance RF performance degredation.
All ESD precautions must be taken while using and handling the EVM.
6
Regulatory Information
No additional regulatory information is available for the MMWCAS-RF-EVM.
40
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