Texas Instruments | IWR14xx/16xx/18xx/68xx Industrial Radar Family (Rev. D) | User Guides | Texas Instruments IWR14xx/16xx/18xx/68xx Industrial Radar Family (Rev. D) User guides

Texas Instruments IWR14xx/16xx/18xx/68xx Industrial Radar Family (Rev. D) User guides
IWR14xx/16xx/18xx/68xx Industrial Radar
Family
Technical Reference Manual
Literature Number: SWRU522D
May 2017 – Revised September 2019
Contents
Preface ..................................................................................................................................... 130
1
14xx ................................................................................................................................ 131
1.1
1.2
1.3
2
132
132
132
135
135
136
139
140
140
141
143
145
145
146
149
150
150
151
151
154
157
157
16xx/18xx ......................................................................................................................... 158
2.1
2.2
2.3
2
14xx Introduction ..........................................................................................................
1.1.1 14xx Overview....................................................................................................
1.1.2 14xx Description .................................................................................................
14xx Memory Map ........................................................................................................
1.2.1 System Interconnect .............................................................................................
1.2.2 Master Subsystem Cortex-R4F Memory Map................................................................
1.2.3 EDMA Memory Map .............................................................................................
14xx Integration ...........................................................................................................
1.3.1 Cortex-R4F Subsystem .........................................................................................
1.3.2 Clock Comparator ...............................................................................................
1.3.3 Direct Memory Access Controller (MSS_DMA) ..............................................................
1.3.4 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB) ................
1.3.5 General Purpose I/0 (MSS_GIO) ..............................................................................
1.3.6 Vectored Interrupt Manager (MSS_VIM) .....................................................................
1.3.7 Controller Area Network (MSS_DCAN) .......................................................................
1.3.8 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPIA) ......................................
1.3.9 Serial Peripheral Interface (MSS_SPIB) ......................................................................
1.3.10 Quad Serial Peripheral Interface (MSS_QSPI) .............................................................
1.3.11 Enhanced Direct Memory Access (EDMA) ..................................................................
1.3.12 Error Signaling Module (MSS_ESM) .........................................................................
1.3.13 High-Speed Interface (HSI)....................................................................................
1.3.14 Handshake RAM (HSRAM) ...................................................................................
16xx Introduction ..........................................................................................................
2.1.1 16xx Overview....................................................................................................
2.1.2 16xx Description .................................................................................................
16xx Memory Map ........................................................................................................
2.2.1 System Interconnect .............................................................................................
2.2.2 Master Subsystem Cortex-R4F Memory Map................................................................
2.2.3 DSP Subsystem Memory Map .................................................................................
2.2.4 EDMA Memory Map .............................................................................................
16xx Integration ...........................................................................................................
2.3.1 Cortex-R4F Subsystem .........................................................................................
2.3.2 Clock Comparator ...............................................................................................
2.3.3 C674x DSP Subsystem .........................................................................................
2.3.4 Direct Memory Access Controller (MSS_DMA) ..............................................................
2.3.5 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB) ................
2.3.6 General Purpose I/0 (MSS_GIO) ..............................................................................
2.3.7 Data Modification Module (MSS_DMM) ......................................................................
2.3.8 Enhanced Pulse Width Modulator (MSS_ETPWM) .........................................................
2.3.9 Vectored Interrupt Manager (MSS_VIM) .....................................................................
2.3.10 Controller Area Network (MSS_DCAN) ......................................................................
2.3.11 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPI).......................................
Contents
159
159
159
163
163
164
168
169
170
170
171
173
176
180
180
182
183
184
187
188
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
2.4
2.5
2.6
3
2.3.12 Quad Serial Peripheral Interface (MSS_QSPI) .............................................................
2.3.13 Enhanced Direct Memory Access (EDMA) ..................................................................
2.3.14 Error Signaling Module (MSS_ESM/DSS_ESM) ...........................................................
2.3.15 High-Speed Interface (HSI)....................................................................................
2.3.16 Handshake RAM (DSS_HSRAM1) ...........................................................................
18xx Introduction ..........................................................................................................
2.4.1 18xx Overview....................................................................................................
2.4.2 18xx Description .................................................................................................
18xx Memory Map ........................................................................................................
2.5.1 System Interconnect .............................................................................................
2.5.2 Master Subsystem Cortex-R4F Memory Map................................................................
2.5.3 DSP Subsystem Memory Map .................................................................................
2.5.4 EDMA Memory Map .............................................................................................
18xx Integration ...........................................................................................................
2.6.1 Cortex-R4F Subsystem .........................................................................................
2.6.2 Clock Comparator ...............................................................................................
2.6.3 C674x DSP Subsystem .........................................................................................
2.6.4 Direct Memory Access Controller (MSS_DMA) ..............................................................
2.6.5 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB) ................
2.6.6 General Purpose I/0 (MSS_GIO) ..............................................................................
2.6.7 Data Modification Module (MSS_DMM) ......................................................................
2.6.8 Enhanced Pulse Width Modulator (MSS_ETPWM) .........................................................
2.6.9 Vectored Interrupt Manager (MSS_VIM) .....................................................................
2.6.10 Controller Area Network (MSS_DCAN) ......................................................................
2.6.11 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPI).......................................
2.6.12 Quad Serial Peripheral Interface (MSS_QSPI) .............................................................
2.6.13 Enhanced Direct Memory Access (EDMA) ..................................................................
2.6.14 Error Signaling Module (MSS_ESM/DSS_ESM) ...........................................................
2.6.15 High-Speed Interface (HSI)....................................................................................
2.6.16 Handshake RAM (DSS_HSRAM1) ...........................................................................
189
189
196
200
200
200
200
201
204
204
205
210
211
212
212
213
215
218
222
222
224
225
226
229
230
231
231
238
242
242
68xx ................................................................................................................................ 243
3.1
3.2
3.3
68xx Introduction ..........................................................................................................
3.1.1 68xx Overview....................................................................................................
3.1.2 68xx Description .................................................................................................
68xx Memory Map ........................................................................................................
3.2.1 System Interconnect .............................................................................................
3.2.2 Master Subsystem Cortex-R4F Memory Map................................................................
3.2.3 DSP Subsystem Memory Map .................................................................................
3.2.4 EDMA Memory Map .............................................................................................
68xx Integration ...........................................................................................................
3.3.1 Cortex-R4F Subsystem .........................................................................................
3.3.2 Clock Comparator ...............................................................................................
3.3.3 C674x DSP Subsystem .........................................................................................
3.3.4 Direct Memory Access Controller (MSS_DMA) ..............................................................
3.3.5 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB) ................
3.3.6 General Purpose I/0 (MSS_GIO) ..............................................................................
3.3.7 Data Modification Module (MSS_DMM) ......................................................................
3.3.8 Enhanced Pulse Width Modulator (MSS_ETPWM) .........................................................
3.3.9 Vectored Interrupt Manager (MSS_VIM) .....................................................................
3.3.10 Module Controller Area Network (MSS_MCAN) ............................................................
3.3.11 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPI).......................................
3.3.12 Quad Serial Peripheral Interface (MSS_QSPI) .............................................................
3.3.13 Enhanced Direct Memory Access (EDMA) ..................................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
244
244
244
248
248
250
254
256
257
257
258
260
263
266
266
268
269
270
273
274
275
275
3
www.ti.com
3.3.14 Error Signaling Module (MSS_ESM/DSS_ESM) ........................................................... 282
3.3.15 High-Speed Interface (HSI).................................................................................... 286
3.3.16 Handshake RAM (DSS_HSRAM1) ........................................................................... 286
4
Power, Reset, Clock Management and Control Registers (IWR) .............................................. 287
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
RADAR Subsystem ......................................................................................................... 1374
5.1
6
Block
5.1.1
5.1.2
5.1.3
Diagram ...........................................................................................................
Clock Subsystem ...............................................................................................
Transmit Subsystem ...........................................................................................
Receive Subsystem ............................................................................................
Master Subsystem Cortex-R4F
6.1
4
PRCM Overview .......................................................................................................... 288
Digital Clock Domains .................................................................................................... 288
4.2.1 Clock Overview .................................................................................................. 288
4.2.2 Device Clock Sources (For Digital Logic)..................................................................... 289
4.2.3 Device Clock Domains .......................................................................................... 289
4.2.4 Clock Initialization Sequence ................................................................................... 290
4.2.5 PMIC Clock ....................................................................................................... 290
Resets ...................................................................................................................... 291
4.3.1 Reset Overview .................................................................................................. 291
4.3.2 Reset Types and Sources ...................................................................................... 292
4.3.3 Reset Domains ................................................................................................... 292
4.3.4 Reset Cause Registers ......................................................................................... 293
4.3.5 Module Resets ................................................................................................... 293
Power Domain............................................................................................................. 293
4.4.1 Available Device Power Domains ............................................................................. 293
4.4.2 Power Domain Control .......................................................................................... 294
Boot ......................................................................................................................... 297
4.5.1 Bootloader Modes ............................................................................................... 297
4.5.2 ROM Eclipsing ................................................................................................... 297
14xx Control Registers ................................................................................................... 298
4.6.1 MSS_TOPRCM Registers ...................................................................................... 299
4.6.2 MSS_RCM Registers............................................................................................ 339
4.6.3 MSS_GPCFG_REG Registers ................................................................................. 374
4.6.4 DSS_REG Registers ............................................................................................ 392
16xx Control Registers ................................................................................................... 484
4.7.1 MSS_TOPRCM Registers ...................................................................................... 485
4.7.2 MSS_RCM Registers............................................................................................ 529
4.7.3 MSS_GPCFG_REG Registers ................................................................................. 572
4.7.4 DSS_REG Registers ............................................................................................ 608
4.7.5 DSS_REG2 Registers ........................................................................................... 722
68xx Control Registers ................................................................................................... 781
4.8.1 MSS_TOPRCM Registers ...................................................................................... 782
4.8.2 MSS_RCM Registers............................................................................................ 826
4.8.3 MSS_GPCFG_REG Registers ................................................................................. 869
4.8.4 DSS_REG Registers ............................................................................................ 905
4.8.5 DSS_REG2 Registers ......................................................................................... 1019
18xx Control Registers ................................................................................................. 1077
4.9.1 MSS_TOPRCM Registers..................................................................................... 1078
4.9.2 MSS_RCM Registers .......................................................................................... 1122
4.9.3 MSS_GPCFG_REG Registers ............................................................................... 1165
4.9.4 DSS_REG Registers ........................................................................................... 1201
4.9.5 DSS_REG2 Registers ......................................................................................... 1315
1375
1376
1377
1378
......................................................................................... 1379
Introduction ............................................................................................................... 1380
Contents
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
6.2
7
1380
1380
1380
1380
Direct Memory Access Controller (DMA) ............................................................................ 1381
7.1
7.2
7.3
8
Cortex-R4F Subsystem .................................................................................................
6.2.1 Cortex-R4F Integration ........................................................................................
6.2.2 Tightly Coupled Memories ....................................................................................
6.2.3 Memory Module Hardware Initialization .....................................................................
Module Operation .......................................................................................................
7.1.1 Block Diagram ..................................................................................................
7.1.2 Memory Space..................................................................................................
7.1.3 DMA Data Access ..............................................................................................
7.1.4 Addressing Modes .............................................................................................
7.1.5 DMA Channel Control Packets ...............................................................................
7.1.6 Priority Queue ..................................................................................................
7.1.7 Data Packing and Unpacking .................................................................................
7.1.8 DMA Request ...................................................................................................
7.1.9 Auto-Initiation ...................................................................................................
7.1.10 Interrupts .......................................................................................................
7.1.11 Debugging ......................................................................................................
7.1.12 Power Management ..........................................................................................
7.1.13 FIFO Buffer.....................................................................................................
7.1.14 Channel Chaining .............................................................................................
7.1.15 Memory Protection ............................................................................................
7.1.16 Parity Checking ................................................................................................
7.1.17 Parity Testing ..................................................................................................
7.1.18 Initializing RAM with Parity ...................................................................................
Control Registers and Control Packets ...............................................................................
7.2.1 DMA Control Registers ........................................................................................
7.2.2 Channel Configuration .........................................................................................
DMA Request Map ......................................................................................................
1382
1382
1382
1382
1384
1384
1388
1390
1393
1394
1394
1396
1396
1396
1397
1398
1399
1400
1400
1401
1402
1482
1487
Vectored Interrupt Manager (VIM)...................................................................................... 1488
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Overview..................................................................................................................
Device Level Interrupt Management ..................................................................................
8.2.1 Interrupt Generation at the Peripheral .......................................................................
8.2.2 Interrupt Handling at the CPU ................................................................................
8.2.3 Software Interrupt Handling Options .........................................................................
Interrupt Handling Inside VIM ..........................................................................................
8.3.1 VIM Interrupt Channel Mapping ..............................................................................
8.3.2 VIM Input Channel Management .............................................................................
Interrupt Vector Table (VIM RAM) ....................................................................................
8.4.1 Interrupt Vector Table Operation .............................................................................
8.4.2 VIM ECC Syndrome ...........................................................................................
8.4.3 Interrupt Vector Table Initialization ...........................................................................
8.4.4 Interrupt Vector Table ECC Testing .........................................................................
VIM Wakeup Interrupt ..................................................................................................
Capture Event Sources .................................................................................................
Examples .................................................................................................................
8.7.1 Examples - Configure CPU To Receive Interrupts ........................................................
8.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling .....................................
VIM Control Registers ..................................................................................................
8.8.1 Interrupt Vector Table ECC Status Register (ECCSTAT).................................................
8.8.2 Interrupt Vector Table ECC Control Register (ECCCTL) .................................................
8.8.3 Uncorrectable Error Address Register (UERRADDR) .....................................................
8.8.4 Fallback Vector Address Register (FBVECADDR) ........................................................
8.8.5 Single Bit Error Address Register (SBERRADDR) ........................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
1489
1490
1490
1491
1492
1493
1494
1496
1497
1497
1498
1499
1499
1502
1503
1503
1503
1504
1506
1507
1508
1509
1509
1510
5
www.ti.com
8.9
9
9.3
9.4
9.5
10.2
10.3
12
6
Introduction ...............................................................................................................
TMS320C674x Megamodule ..........................................................................................
9.2.1 Internal Memory Controllers ..................................................................................
9.2.2 Internal Peripherals ............................................................................................
Memory Map .............................................................................................................
Advanced Event Triggering (AET) ....................................................................................
DSP Event Assignment ................................................................................................
1523
1524
1524
1524
1525
1525
1526
DSS_L3 Memory Organization .......................................................................................... 1527
10.1
11
1510
1511
1511
1512
1513
1514
1515
1516
1517
1518
1518
1519
1520
1521
DSP Subsystem C674x .................................................................................................... 1522
9.1
9.2
10
8.8.6 VIM Offset Vector Registers ..................................................................................
8.8.7 IRQ Index Offset Vector Register (IRQINDEX) ............................................................
8.8.8 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................
8.8.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3]) .......................................................
8.8.10 Pending Interrupt Read Location Registers (INTREQ[0:3]) .............................................
8.8.11 Interrupt Enable Set Registers (REQENASET[0:3]) ......................................................
8.8.12 Interrupt Enable Clear Registers (REQENACLR[0:3]) ...................................................
8.8.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])...................................................
8.8.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3]) ................................................
8.8.15 IRQ Interrupt Vector Register (IRQVECREG) .............................................................
8.8.16 FIQ Interrupt Vector Register (FIQVECREG) .............................................................
8.8.17 Capture Event Register (CAPEVT) .........................................................................
8.8.18 VIM Interrupt Control Registers (CHANCTRL[0:31]) .....................................................
Interrupt Request Assignments .......................................................................................
DSS_L3 Memory Organization for 14xx ..............................................................................
10.1.1 Functional Description ........................................................................................
10.1.2 Memory Auto Initialization ....................................................................................
10.1.3 Memory TAB Register ........................................................................................
DSS_L3 Memory Organization for 16xx/18xx .......................................................................
10.2.1 Functional Description ........................................................................................
10.2.2 Memory Auto-Initialization ....................................................................................
10.2.3 Memory TAB Register ........................................................................................
DSS_L3 Memory Organization for 68xx ..............................................................................
10.3.1 Functional Description ........................................................................................
10.3.2 Memory Auto-Initialization ....................................................................................
10.3.3 Memory TAB Register ........................................................................................
1528
1528
1529
1530
1530
1530
1531
1531
1531
1532
1532
1533
............................................................................................... 1534
Enhanced Direct Memory Access (EDMA) .......................................................................... 1535
12.1 EDMA Module Overview ............................................................................................... 1536
12.1.1 EDMA Features ............................................................................................... 1537
12.2 EDMA Controller Functional Description ............................................................................. 1538
12.2.1 Block Diagram ................................................................................................. 1538
12.2.2 Types of EDMA controller Transfers........................................................................ 1541
12.2.3 Parameter RAM (PaRAM) ................................................................................... 1543
12.2.4 Initiating a DMA Transfer ..................................................................................... 1555
12.2.5 Completion of a DMA Transfer .............................................................................. 1558
12.2.6 Event, Channel, and PaRAM Mapping ..................................................................... 1559
12.2.7 EDMA Channel Controller Regions ......................................................................... 1561
12.2.8 Chaining EDMA Channels ................................................................................... 1563
12.2.9 EDMA Interrupts ............................................................................................... 1565
12.2.10 Memory Protection .......................................................................................... 1573
12.2.11 Event Queue(s) .............................................................................................. 1578
12.2.12 EDMA Transfer Controller (EDMA_TPTC) ............................................................... 1580
Handshake RAM (HSRAM)
Contents
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
12.3
12.4
12.5
12.6
13
14.3
14.4
1825
1825
1827
1828
1828
Overview..................................................................................................................
CBUFF ....................................................................................................................
14.2.1 CBUFF Overview ..............................................................................................
14.2.2 CBUFF Sequencing ...........................................................................................
14.2.3 Sequence-Related CBUFF Configuration Fields ..........................................................
14.2.4 CBUFF Linklist Concept ......................................................................................
14.2.5 CBUFF Interrupts .............................................................................................
LVDS ......................................................................................................................
14.3.1 LVDS Overview ................................................................................................
14.3.2 LVDS Programming Sequence ..............................................................................
14.3.3 CBUFF and LVDS Registers ................................................................................
CSI2 .......................................................................................................................
14.4.1 CSI2 Overview .................................................................................................
14.4.2 CSI2 Protocol Engine and Phy ..............................................................................
14.4.3 CSI2 Programming Sequence ...............................................................................
14.4.4 CSI2_PROTOCOL_ENGINE Registers ....................................................................
14.4.5 CSI2_PHY Registers .........................................................................................
1831
1831
1831
1832
1834
1834
1837
1838
1838
1838
1840
1977
1977
1988
2000
2004
2074
Hardware Accelerator ...................................................................................................... 2092
15.1
15.2
16
Functional Description ..................................................................................................
13.1.1 DFE Data Write Operation ...................................................................................
13.1.2 Support for Hardware in Loop (HIL) ........................................................................
13.1.3 Test Pattern Generator Support .............................................................................
13.1.4 ADC Buffer Data Formats ....................................................................................
High-Speed Interface (HSI) ............................................................................................... 1830
14.1
14.2
15
1583
1583
1585
1586
1586
1588
1589
1591
1593
1593
1594
1594
1595
1595
ADC Buffer ..................................................................................................................... 1824
13.1
14
12.2.13 Event Dataflow ...............................................................................................
12.2.14 EDMA Controller Prioritization .............................................................................
12.2.15 Emulation Considerations ..................................................................................
EDMA Transfer Examples .............................................................................................
12.3.1 Block Move Example .........................................................................................
12.3.2 Subframe Extraction Example ...............................................................................
12.3.3 Data Sorting Example ........................................................................................
12.3.4 Setting Up an EDMA Transfer ...............................................................................
EDMA Debug Checklist and Programming Tips ....................................................................
12.4.1 EDMA Debug Checklist ......................................................................................
12.4.2 EDMA Programming Tips ....................................................................................
EDMA Request Map ....................................................................................................
EDMA Register Manual ................................................................................................
12.6.1 EDMA Registers ...............................................................................................
Introduction ............................................................................................................... 2093
Register Map ............................................................................................................. 2093
Real Time Interrupt (RTI) and RTI With Digital Watchdog Timer (WDT) .................................. 2094
16.1
16.2
16.3
Overview..................................................................................................................
16.1.1 Features ........................................................................................................
16.1.2 Industry Standard Compliance Statement .................................................................
Module Operation .......................................................................................................
16.2.1 Counter Operation ............................................................................................
16.2.2 Interrupt/DMA Requests ......................................................................................
16.2.3 Digital Watchdog (DWD) .....................................................................................
16.2.4 Halting Debug Mode Behaviour .............................................................................
RTI Control Registers ...................................................................................................
16.3.1 RTI Global Control Register (RTIGCTRL) .................................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
2095
2095
2095
2096
2096
2098
2099
2102
2103
2104
7
www.ti.com
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.3.7
16.3.8
16.3.9
16.3.10
16.3.11
16.3.12
16.3.13
16.3.14
16.3.15
16.3.16
16.3.17
16.3.18
16.3.19
16.3.20
16.3.21
16.3.22
16.3.23
16.3.24
16.3.25
16.3.26
16.3.27
16.3.28
16.3.29
16.3.30
16.3.31
16.3.32
16.3.33
16.3.34
16.3.35
16.3.36
16.3.37
16.3.38
16.3.39
17
2105
2106
2107
2108
2108
2109
2109
2110
2110
2111
2112
2113
2113
2114
2114
2115
2115
2116
2116
2117
2117
2118
2118
2119
2121
2123
2124
2125
2126
2127
2128
2128
2129
2130
2131
2131
2132
2132
General Purpose I/0 (GIO) ................................................................................................ 2133
17.1
17.2
17.3
17.4
17.5
8
RTI Timebase Control Register (RTITBCTRL) ............................................................
RTI Capture Control Register (RTICAPCTRL) ............................................................
RTI Compare Control Register (RTICOMPCTRL) ........................................................
RTI Free Running Counter 0 Register (RTIFRC0)........................................................
RTI Up Counter 0 Register (RTIUC0) ......................................................................
RTI Compare Up Counter 0 Register (RTICPUC0).......................................................
RTI Capture Free Running Counter 0 Register (RTICAFRC0) .........................................
RTI Capture Up Counter 0 Register (RTICAUC0) ........................................................
RTI Free Running Counter 1 Register (RTIFRC1) ......................................................
RTI Up Counter 1 Register (RTIUC1) .....................................................................
RTI Compare Up Counter 1 Register (RTICPUC1) .....................................................
RTI Capture Free Running Counter 1 Register (RTICAFRC1) ........................................
RTI Capture Up Counter 1 Register (RTICAUC1).......................................................
RTI Compare 0 Register (RTICOMP0) ...................................................................
RTI Update Compare 0 Register (RTIUDCP0) ..........................................................
RTI Compare 1 Register (RTICOMP1) ...................................................................
RTI Update Compare 1 Register (RTIUDCP1) ..........................................................
RTI Compare 2 Register (RTICOMP2) ...................................................................
RTI Update Compare 2 Register (RTIUDCP2) ..........................................................
RTI Compare 3 Register (RTICOMP3) ...................................................................
RTI Update Compare 3 Register (RTIUDCP3) ..........................................................
RTI Timebase Low Compare Register (RTITBLCOMP) ................................................
RTI Timebase High Compare Register (RTITBHCOMP) ...............................................
RTI Set Interrupt Enable Register (RTISETINTENA) ...................................................
RTI Clear Interrupt Enable Register (RTICLEARINTENA) .............................................
RTI Interrupt Flag Register (RTIINTFLAG) ...............................................................
Digital Watchdog Control Register (RTIDWDCTRL) ....................................................
Digital Watchdog Preload Register (RTIDWDPRLD) ...................................................
Watchdog Status Register (RTIWDSTATUS) ............................................................
RTI Watchdog Key Register (RTIWDKEY) ...............................................................
RTI Digital Watchdog Down Counter (RTIDWDCNTR) .................................................
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) ................................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) ..........................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) ...............................
RTI Compare 0 Clear Register (RTICMP0CLR) .........................................................
RTI Compare 1 Clear Register (RTICMP1CLR) .........................................................
RTI Compare 2 Clear Register (RTICMP2CLR) .........................................................
RTI Compare 3 Clear Register (RTICMP3CLR) .........................................................
Overview..................................................................................................................
Quick Start Guide .......................................................................................................
Functional Description of GIO Module................................................................................
17.3.1 I/O Functions...................................................................................................
17.3.2 Interrupt Function .............................................................................................
17.3.3 GIO Block Diagram ...........................................................................................
Device Modes of Operation ............................................................................................
17.4.1 Emulation Mode ...............................................................................................
17.4.2 Power-Down Mode (Low-Power Mode) ....................................................................
MSS_GIO Registers ....................................................................................................
17.5.1 GIOGCR Register (Offset = 0h) [reset = 0h] ..............................................................
17.5.2 GIOPWDN Register (Offset = 4h) [reset = 0h] ............................................................
17.5.3 GIOINTDET Register (Offset = 8h) [reset = 0h] ...........................................................
17.5.4 GIOPOL Register (Offset = Ch) [reset = 0h]...............................................................
Contents
2134
2134
2136
2136
2137
2137
2139
2139
2139
2140
2142
2143
2144
2145
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
17.5.5
17.5.6
17.5.7
17.5.8
17.5.9
17.5.10
17.5.11
17.5.12
17.5.13
17.5.14
17.5.15
17.5.16
17.5.17
17.5.18
17.5.19
17.5.20
17.5.21
17.5.22
17.5.23
17.5.24
17.5.25
17.5.26
17.5.27
17.5.28
17.5.29
17.5.30
17.5.31
17.5.32
17.5.33
17.5.34
17.5.35
17.5.36
17.5.37
17.5.38
17.5.39
17.5.40
17.5.41
17.5.42
17.5.43
17.5.44
17.5.45
17.5.46
17.5.47
17.5.48
17.5.49
17.5.50
17.5.51
17.5.52
17.5.53
17.5.54
17.5.55
17.5.56
17.5.57
GIOENASET Register (Offset = 10h) [reset = 0h] ........................................................
GIOENACLR Register (Offset = 14h) [reset = 0h] ........................................................
GIOLVLSET Register (Offset = 18h) [reset = 0h] .........................................................
GIOLVLCLR Register (Offset = 1Ch) [reset = 0h] ........................................................
GIOFLG Register (Offset = 20h) [reset = 0h] ..............................................................
GIOOFFA Register (Offset = 24h) [reset = 0h] ..........................................................
GIOOFFB Register (Offset = 28h) [reset = 0h] ..........................................................
GIOEMUA Register (Offset = 2Ch) [reset = 0h] .........................................................
GIOEMUB Register (Offset = 30h) [reset = 0h] ..........................................................
GIODIRA Register (Offset = 34h) [reset = 0h] ...........................................................
GIODINA Register (Offset = 38h) [reset = 0h] ...........................................................
GIODOUTA Register (Offset = 3Ch) [reset = 0h]........................................................
GIOSETA Register (Offset = 40h) [reset = 0h] ..........................................................
GIOCLRA Register (Offset = 44h) [reset = 0h] ..........................................................
GIOPDRA Register (Offset = 48h) [reset = 0h] ..........................................................
GIOPULDISA Register (Offset = 4Ch) [reset = 0h] .....................................................
GIOPSLA Register (Offset = 50h) [reset = 0h] ..........................................................
GIODIRB Register (Offset = 54h) [reset = 0h] ...........................................................
GIODINB Register (Offset = 58h) [reset = 0h] ...........................................................
GIODOUTB Register (Offset = 5Ch) [reset = 0h]........................................................
GIOSETB Register (Offset = 60h) [reset = 0h] ..........................................................
GIOCLRB Register (Offset = 64h) [reset = 0h] ..........................................................
GIOPDRB Register (Offset = 68h) [reset = 0h] ..........................................................
GIOPULDISB Register (Offset = 6Ch) [reset = 0h] .....................................................
GIOPSLB Register (Offset = 70h) [reset = 0h] ..........................................................
GIODIRC Register (Offset = 74h) [reset = 0h] ...........................................................
GIODINC Register (Offset = 78h) [reset = 0h] ...........................................................
GIODOUTC Register (Offset = 7Ch) [reset = 0h] .......................................................
GIOSETC Register (Offset = 80h) [reset = 0h] ..........................................................
GIOCLRC Register (Offset = 84h) [reset = 0h] ..........................................................
GIOPDRC Register (Offset = 88h) [reset = 0h] ..........................................................
GIOPULDISC Register (Offset = 8Ch) [reset = 0h] .....................................................
GIOPSLC Register (Offset = 90h) [reset = 0h] ..........................................................
GIODIRD Register (Offset = 94h) [reset = 0h] ...........................................................
GIODIND Register (Offset = 98h) [reset = 0h] ...........................................................
GIODOUTD Register (Offset = 9Ch) [reset = 0h] .......................................................
GIOSETD Register (Offset = A0h) [reset = 0h] ..........................................................
GIOCLRD Register (Offset = A4h) [reset = 0h] ..........................................................
GIOPDRD Register (Offset = A8h) [reset = 0h] .........................................................
GIOPULDISD Register (Offset = ACh) [reset = 0h] .....................................................
GIOPSLD Register (Offset = B0h) [reset = 0h] ..........................................................
GIODIRE Register (Offset = B4h) [reset = 0h] ...........................................................
GIODINE Register (Offset = B8h) [reset = 0h] ...........................................................
GIODOUTE Register (Offset = BCh) [reset = 0h] .......................................................
GIOSETE Register (Offset = C0h) [reset = 0h] ..........................................................
GIOCLRE Register (Offset = C4h) [reset = 0h] ..........................................................
GIOPDRE Register (Offset = C8h) [reset = 0h] .........................................................
GIOPULDISE Register (Offset = CCh) [reset = 0h] .....................................................
GIOPSLE Register (Offset = D0h) [reset = 0h] ..........................................................
GIODIRF Register (Offset = D4h) [reset = 0h] ...........................................................
GIODINF Register (Offset = D8h) [reset = 0h] ...........................................................
GIODOUTF Register (Offset = DCh) [reset = 0h] .......................................................
GIOSETF Register (Offset = E0h) [reset = 0h] ..........................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
9
www.ti.com
17.6
18
Maibox Message Scheme ..............................................................................................
Mailbox Registers .......................................................................................................
18.2.1 INT_MASK Register (Offset = 0h) [reset = 0h] ............................................................
18.2.2 INT_MASK_SET Register (Offset = 8h) [reset = 0h] .....................................................
18.2.3 INT_MASK_CLR Register (Offset = 10h) [reset = 0h] ...................................................
18.2.4 INT_STS_CLR Register (Offset = 18h) [reset = 0h] ......................................................
18.2.5 INT_ACK Register (Offset = 20h) [reset = 0h] ............................................................
18.2.6 INT_TRIG Register (Offset = 28h) [reset = 0h]............................................................
18.2.7 INT_STS_MASKED Register (Offset = 30h) [reset = 0h] ................................................
18.2.8 INT_STS_RAW Register (Offset = 38h) [reset = 0h] .....................................................
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
Data Modification Module (DMM)....................................................................................... 2239
19.1
19.2
19.3
10
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
Mailbox .......................................................................................................................... 2228
18.1
18.2
19
17.5.58 GIOCLRF Register (Offset = E4h) [reset = 0h] ..........................................................
17.5.59 GIOPDRF Register (Offset = E8h) [reset = 0h] ..........................................................
17.5.60 GIOPULDISF Register (Offset = ECh) [reset = 0h] .....................................................
17.5.61 GIOPSLF Register (Offset = F0h) [reset = 0h] ..........................................................
17.5.62 GIODIRG Register (Offset = F4h) [reset = 0h] ..........................................................
17.5.63 GIODING Register (Offset = F8h) [reset = 0h] ..........................................................
17.5.64 GIODOUTG Register (Offset = FCh) [reset = 0h] .......................................................
17.5.65 GIOSETG Register (Offset = 100h) [reset = 0h].........................................................
17.5.66 GIOCLRG Register (Offset = 104h) [reset = 0h] ........................................................
17.5.67 GIOPDRG Register (Offset = 108h) [reset = 0h] ........................................................
17.5.68 GIOPULDISG Register (Offset = 10Ch) [reset = 0h] ....................................................
17.5.69 GIOPSLG Register (Offset = 110h) [reset = 0h] .........................................................
17.5.70 GIODIRH Register (Offset = 114h) [reset = 0h] .........................................................
17.5.71 GIODINH Register (Offset = 118h) [reset = 0h] .........................................................
17.5.72 GIODOUTH Register (Offset = 11Ch) [reset = 0h] ......................................................
17.5.73 GIOSETH Register (Offset = 120h) [reset = 0h] .........................................................
17.5.74 GIOCLRH Register (Offset = 124h) [reset = 0h].........................................................
17.5.75 GIOPDRH Register (Offset = 128h) [reset = 0h] ........................................................
17.5.76 GIOPULDISH Register (Offset = 12Ch) [reset = 0h] ....................................................
17.5.77 GIOPSLH Register (Offset = 130h) [reset = 0h] .........................................................
17.5.78 GIOSRCA Register (Offset = 134h) [reset = 0h] ........................................................
17.5.79 GIOSRCB Register (Offset = 138h) [reset = 0h] ........................................................
17.5.80 GIOSRCC Register (Offset = 13Ch) [reset = 0h] ........................................................
17.5.81 GIOSRCD Register (Offset = 140h) [reset = 0h] ........................................................
17.5.82 GIOSRCE Register (Offset = 144h) [reset = 0h] ........................................................
17.5.83 GIOSRCF Register (Offset = 148h) [reset = 0h].........................................................
17.5.84 GIOSRCG Register (Offset = 14Ch) [reset = 0h] ........................................................
17.5.85 GIOSRCH Register (Offset = 150h) [reset = 0h] ........................................................
I/O Control Summary ...................................................................................................
Overview..................................................................................................................
19.1.1 Features ........................................................................................................
19.1.2 Block Diagram .................................................................................................
Module Operation .......................................................................................................
19.2.1 Data Format ....................................................................................................
19.2.2 Data Port .......................................................................................................
19.2.3 Error Handling .................................................................................................
19.2.4 Interrupts .......................................................................................................
Control Registers ........................................................................................................
19.3.1 DMM Global Control Register (DMMGLBCTRL) ..........................................................
19.3.2 DMM Interrupt Set Register (DMMINTSET) ...............................................................
19.3.3 DMM Interrupt Clear Register (DMMINTCLR) ............................................................
Contents
2240
2240
2240
2241
2241
2243
2244
2245
2246
2247
2249
2253
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.3.10
19.3.11
19.3.12
19.3.13
19.3.14
19.3.15
19.3.16
19.3.17
19.3.18
19.3.19
19.3.20
19.3.21
19.3.22
19.3.23
19.3.24
20
DMM Interrupt Level Register (DMMINTLVL) .............................................................
DMM Interrupt Flag Register (DMMINTFLG) ..............................................................
DMM Interrupt Offset 1 Register (DMMOFF1) ............................................................
DMM Interrupt Offset 2 Register (DMMOFF2) ............................................................
DMM Direct Data Mode Destination Register (DMMDDMDEST) .......................................
DMM Direct Data Mode Blocksize Register (DMMDDMBL) .............................................
DMM Direct Data Mode Pointer Register (DMMDDMPT) ..............................................
DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) .....................................
DMM Destination x Region 1 (DMMDESTxREG1) ......................................................
DMM Destination x Blocksize 1 (DMMDESTxBL1) .....................................................
DMM Destination x Region 2 (DMMDESTxREG2) ......................................................
DMM Destination x Blocksize 2 (DMMDESTxBL2) .....................................................
DMM Pin Control 0 (DMMPC0) ............................................................................
DMM Pin Control 1 (DMMPC1) ............................................................................
DMM Pin Control 2 (DMMPC2) ............................................................................
DMM Pin Control 3 (DMMPC3) ............................................................................
DMM Pin Control 4 (DMMPC4) ............................................................................
DMM Pin Control 5 (DMMPC5) ............................................................................
DMM Pin Control 6 (DMMPC6) ............................................................................
DMM Pin Control 7 (DMMPC7) ............................................................................
DMM Pin Control 8 (DMMPC8) ............................................................................
2258
2260
2264
2265
2266
2266
2267
2267
2268
2269
2270
2271
2272
2273
2275
2276
2277
2279
2280
2282
2283
Enhanced Pulse Width Modulator (ePWM) ......................................................................... 2285
20.1
20.2
20.3
20.4
Introduction ...............................................................................................................
20.1.1 Submodule Overview .........................................................................................
20.1.2 Register Mapping .............................................................................................
ePWM Submodules .....................................................................................................
20.2.1 Overview .......................................................................................................
20.2.2 Time-Base (TB) Submodule .................................................................................
20.2.3 Counter-Compare (CC) Submodule ........................................................................
20.2.4 Action-Qualifier (AQ) Submodule ...........................................................................
20.2.5 Dead-Band Generator (DB) Submodule ...................................................................
20.2.6 PWM-Chopper (PC) Submodule ............................................................................
20.2.7 Trip-Zone (TZ) Submodule ...................................................................................
20.2.8 Event-Trigger (ET) Submodule ..............................................................................
20.2.9 Digital Compare (DC) Submodule ..........................................................................
20.2.10 Proper Interrupt Initialization Procedure ..................................................................
Application Examples ...................................................................................................
20.3.1 Overview of Multiple Modules ..............................................................................
20.3.2 Key Configuration Capabilities ..............................................................................
20.3.3 Controlling Multiple Buck Converters With Independent Frequencies .................................
20.3.4 Controlling Multiple Buck Converters With Same Frequencies .........................................
20.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ....................................................
20.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) .......................................
20.3.7 Practical Applications Using Phase Control Between PWM Modules ..................................
MSS_ETPWM1 Registers ..............................................................................................
20.4.1 TBCTL_TBSTS Register (Offset = 0h) [reset = 0h] .......................................................
20.4.2 TBPHS Register (Offset = 4h) [reset = 0h] ................................................................
20.4.3 TBCTR_TBPRD Register (Offset = 8h) [reset = 0h] ......................................................
20.4.4 CMPCTL Register (Offset = Ch) [reset = 0h] ..............................................................
20.4.5 CMPA Register (Offset = 10h) [reset = 0h] ................................................................
20.4.6 CMPB_AQCTLA Register (Offset = 14h) [reset = 0h] ....................................................
20.4.7 AQCTLB_AQSFRC Register (Offset = 18h) [reset = 0h] ................................................
20.4.8 AQCSFRC_DBCTL Register (Offset = 1Ch) [reset = 0h] ................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
2286
2286
2289
2290
2290
2292
2300
2305
2318
2323
2327
2333
2338
2344
2345
2345
2345
2347
2350
2353
2355
2358
2360
2362
2364
2365
2366
2368
2369
2371
2373
11
www.ti.com
20.4.9
20.4.10
20.4.11
20.4.12
20.4.13
20.4.14
20.4.15
20.4.16
20.4.17
20.4.18
20.4.19
20.4.20
20.4.21
20.4.22
20.4.23
20.4.24
20.4.25
20.4.26
20.4.27
20.4.28
20.4.29
21
2375
2376
2378
2380
2382
2384
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2398
2399
2400
2401
Controller Area Network (DCAN) ....................................................................................... 2402
21.1
21.2
21.3
21.4
21.5
21.6
21.7
12
DBRED_DBFED Register (Offset = 20h) [reset = 0h] ....................................................
TZSEL_TZDCSEL Register (Offset = 24h) [reset = 0h] ................................................
TZCTL_TZEINT Register (Offset = 28h) [reset = 0h] ...................................................
TZFLG_TZCLR Register (Offset = 2Ch) [reset = 0h] ...................................................
TZFRC_ETSEL Register (Offset = 30h) [reset = 0h] ...................................................
ETPS_ETFLG Register (Offset = 34h) [reset = 0h] .....................................................
ETCLR_ETFRC Register (Offset = 38h) [reset = 0h] ...................................................
PCCTL Register (Offset = 3Ch) [reset = 0h] .............................................................
Reserved1 Register (Offset = 40h) [reset = 0h] .........................................................
Reserved2 Register (Offset = 44h) [reset = 0h] .........................................................
Reserved3 Register (Offset = 48h) [reset = 0h] .........................................................
Reserved4 Register (Offset = 4Ch) [reset = 0h] .........................................................
Reserved5 Register (Offset = 50h) [reset = 0h] .........................................................
Reserved6 Register (Offset = 54h) [reset = 0h] .........................................................
Reserved7 Register (Offset = 58h) [reset = 0h] .........................................................
Reserved8 Register (Offset = 5Ch) [reset = 0h] .........................................................
DCTRIPSEL_DCACTL Register (Offset = 60h) [reset = 0h] ...........................................
DCBCTL_DCFCTL Register (Offset = 64h) [reset = 0h] ...............................................
DCCAPCTL_DCFOFFSET Register (Offset = 68h) [reset = 0h] ......................................
DCFOFFSETCNT_DCFWINDOW Register (Offset = 6Ch) [reset = 0h] .............................
DCFWINDOWCNT_DCCAP Register (Offset = 70h) [reset = 0h] ....................................
Overview..................................................................................................................
21.1.1 Features ........................................................................................................
21.1.2 Functional Description ........................................................................................
CAN Blocks ..............................................................................................................
21.2.1 CAN Core ......................................................................................................
21.2.2 Message RAM .................................................................................................
21.2.3 Message Handler .............................................................................................
21.2.4 Message RAM Interface ......................................................................................
21.2.5 Register and Message Object Access .....................................................................
21.2.6 Dual Clock Source ............................................................................................
CAN Bit Timing ..........................................................................................................
21.3.1 Bit Time and Bit Rate .........................................................................................
21.3.2 DCAN Bit Timing Registers ..................................................................................
CAN Module Configuration.............................................................................................
21.4.1 DCAN RAM Initialization Through Hardware ..............................................................
21.4.2 CAN Module Initialization ....................................................................................
Message RAM ...........................................................................................................
21.5.1 Structure of Message Objects ...............................................................................
21.5.2 Addressing Message Objects in RAM ......................................................................
21.5.3 Message RAM Representation in Debug/Suspend Mode ...............................................
21.5.4 Message RAM Representation in Direct Access Mode ..................................................
21.5.5 ECC RAM ......................................................................................................
Message Interface Register Sets .....................................................................................
21.6.1 Message Interface Register Sets 1 and 2 .................................................................
21.6.2 Using Message Interface Register Sets 1 and 2 ..........................................................
21.6.3 Message Interface Register 3 ...............................................................................
Message Object Configurations .......................................................................................
21.7.1 Configuration of a Transmit Object for Data Frames .....................................................
21.7.2 Configuration of a Transmit Object for Remote Frames .................................................
21.7.3 Configuration of a Single Receive Object for Data Frames .............................................
21.7.4 Configuration of a Single Receive Object for Remote Frames ..........................................
Contents
2403
2403
2403
2404
2404
2404
2404
2405
2405
2405
2406
2406
2408
2410
2410
2410
2413
2413
2415
2416
2416
2417
2418
2418
2419
2420
2421
2421
2421
2421
2422
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
21.16
21.17
21.7.5 Configuration of a FIFO Buffer ..............................................................................
21.7.6 Reconfiguration of Message Objects for the Reception of Frames.....................................
21.7.7 Reconfiguration of Message Objects for the Reception of Frames.....................................
Message Handling ......................................................................................................
21.8.1 Message Handler Overview .................................................................................
21.8.2 Receive/Transmit Priority.....................................................................................
21.8.3 Transmission of Messages in Event Driven CAN Communication .....................................
21.8.4 Updating a Transmit Object ..................................................................................
21.8.5 Changing a Transmit Object .................................................................................
21.8.6 Acceptance Filtering of Received Messages ..............................................................
21.8.7 Reception of Data Frames ...................................................................................
21.8.8 Reception of Remote Frames ..............................................................................
21.8.9 Reading Received Messages ...............................................................................
21.8.10 Requesting New Data for a Receive Object .............................................................
21.8.11 Storing Received Messages in FIFO Buffers ............................................................
21.8.12 Reading from a FIFO Buffer ...............................................................................
CAN Message Transfer ................................................................................................
21.9.1 Automatic Retransmission ...................................................................................
21.9.2 Auto-Bus-On ...................................................................................................
Interrupt Functionality ..................................................................................................
21.10.1 Message Object Interrupts .................................................................................
21.10.2 Status Change Interrupts ...................................................................................
21.10.3 Error Interrupts ...............................................................................................
Global Power Down Mode .............................................................................................
21.11.1 Entering Global Power Down Mode .......................................................................
21.11.2 Wakeup From Global Power Down Mode ................................................................
Local Power Down Mode ..............................................................................................
21.12.1 Entering Local Power Down Mode ........................................................................
21.12.2 Wakeup From Local Power Down .........................................................................
GIO Support .............................................................................................................
Test Modes ..............................................................................................................
21.14.1 Silent Mode ...................................................................................................
21.14.2 Loop Back Mode .............................................................................................
21.14.3 External Loop Back Mode ..................................................................................
21.14.4 Loop Back Combined with Silent Mode...................................................................
21.14.5 Software Control of CAN_TX Pin ..........................................................................
SECDED Mechanism ...................................................................................................
21.15.1 Behavior on Single Bit Error ................................................................................
21.15.2 Behavior on Double Bit Error ...............................................................................
21.15.3 SECDED Testing ............................................................................................
Debug/Suspend Mode..................................................................................................
MSS_DCAN Registers .................................................................................................
21.17.1 CTL Register (Offset = 0h) [reset = 1401h] ..............................................................
21.17.2 ES Register (Offset = 4h) [reset = 7h] ....................................................................
21.17.3 ERRC Register (Offset = 8h) [reset = 0h] ................................................................
21.17.4 BTR Register (Offset = Ch) [reset = 2301h] .............................................................
21.17.5 INT Register (Offset = 10h) [reset = 0h] ..................................................................
21.17.6 TEST Register (Offset = 14h) [reset = 80h] ..............................................................
21.17.7 Reserved_1 Register (Offset = 18h) [reset = 0h] ........................................................
21.17.8 PERR Register (Offset = 1Ch) [reset = 0h] ..............................................................
21.17.9 DCAN_REV_ID Register (Offset = 20h) [reset = 0h] ...................................................
21.17.10 ECCDIAG Register (Offset = 24h) [reset = 0h].........................................................
21.17.11 ECCDIAG_STAT Register (Offset = 28h) [reset = 0h] ................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
2422
2422
2422
2423
2423
2423
2424
2424
2424
2425
2425
2425
2425
2426
2426
2426
2428
2428
2429
2429
2429
2430
2430
2431
2431
2431
2432
2432
2432
2432
2434
2434
2435
2436
2437
2437
2438
2438
2438
2438
2439
2440
2443
2446
2448
2449
2450
2451
2452
2453
2454
2455
2456
13
www.ti.com
21.17.12
21.17.13
21.17.14
21.17.15
21.17.16
21.17.17
21.17.18
21.17.19
21.17.20
21.17.21
21.17.22
21.17.23
21.17.24
21.17.25
21.17.26
21.17.27
21.17.28
21.17.29
21.17.30
21.17.31
21.17.32
21.17.33
21.17.34
21.17.35
21.17.36
21.17.37
21.17.38
21.17.39
21.17.40
21.17.41
21.17.42
21.17.43
21.17.44
21.17.45
21.17.46
21.17.47
21.17.48
21.17.49
21.17.50
21.17.51
21.17.52
21.17.53
21.17.54
21.17.55
21.17.56
21.17.57
21.17.58
21.17.59
21.17.60
21.17.61
21.17.62
21.17.63
21.17.64
14
Contents
ECC_CS Register (Offset = 2Ch) [reset = 0h] .........................................................
ECC_SERR Register (Offset = 30h) [reset = 0h] ......................................................
TTCAN1 Register (Offset = 34h) [reset = 0h] ..........................................................
TTCAN2 Register (Offset = 38h) [reset = 0h] ..........................................................
TTCAN3 Register (Offset = 3Ch) [reset = 0h] ..........................................................
TTCAN4 Register (Offset = 40h) [reset = 0h] ..........................................................
TTCAN5 Register (Offset = 44h) [reset = 0h] ..........................................................
TTCAN6 Register (Offset = 48h) [reset = 0h] ..........................................................
TTCAN7 Register (Offset = 4Ch) [reset = 0h] ..........................................................
TTCAN8 Register (Offset = 50h) [reset = 0h] ..........................................................
TTCAN9 Register (Offset = 54h) [reset = 0h] ..........................................................
TTCAN10 Register (Offset = 58h) [reset = 0h] .........................................................
TTCAN11 Register (Offset = 5Ch) [reset = 0h] ........................................................
TTCAN12 Register (Offset = 60h) [reset = 0h] .........................................................
TTCAN13 Register (Offset = 64h) [reset = 0h] .........................................................
TTCAN14 Register (Offset = 68h) [reset = 0h] .........................................................
TTCAN15 Register (Offset = 6Ch) [reset = 0h] ........................................................
TTCAN16 Register (Offset = 70h) [reset = 0h] .........................................................
TTCAN17 Register (Offset = 74h) [reset = 0h] .........................................................
TTCAN18 Register (Offset = 78h) [reset = 0h] .........................................................
TTCAN19 Register (Offset = 7Ch) [reset = 0h] ........................................................
ABOTR Register (Offset = 80h) [reset = 0h]............................................................
TXRQ_X Register (Offset = 84h) [reset = 0h] ..........................................................
TXRQ12 Register (Offset = 88h) [reset = 0h] ..........................................................
TXRQ34 Register (Offset = 8Ch) [reset = 0h] ..........................................................
TXRQ56 Register (Offset = 90h) [reset = 0h] ..........................................................
TXRQ78 Register (Offset = 94h) [reset = 0h] ..........................................................
NWDAT_X Register (Offset = 98h) [reset = 0h] ........................................................
NWDAT12 Register (Offset = 9Ch) [reset = 0h]........................................................
NWDAT34 Register (Offset = A0h) [reset = 0h] ........................................................
NWDAT56 Register (Offset = A4h) [reset = 0h] ........................................................
NWDAT78 Register (Offset = A8h) [reset = 0h] ........................................................
INTPND_X Register (Offset = ACh) [reset = 0h] .......................................................
INTPND12 Register (Offset = B0h) [reset = 0h] .......................................................
INTPND34 Register (Offset = B4h) [reset = 0h] .......................................................
INTPND56 Register (Offset = B8h) [reset = 0h] .......................................................
INTPND78 Register (Offset = BCh) [reset = 0h] .......................................................
MSGVAL_X Register (Offset = C0h) [reset = 0h] ......................................................
MSGVAL12 Register (Offset = C4h) [reset = 0h] ......................................................
MSGVAL34 Register (Offset = C8h) [reset = 0h] ......................................................
MSGVAL56 Register (Offset = CCh) [reset = 0h] ......................................................
MSGVAL78 Register (Offset = D0h) [reset = 0h] ......................................................
Reserved_2 Register (Offset = D4h) [reset = 0h] ......................................................
INTMUX12 Register (Offset = D8h) [reset = 0h] .......................................................
INTMUX34 Register (Offset = DCh) [reset = 0h] .......................................................
INTMUX56 Register (Offset = E0h) [reset = 0h] .......................................................
INTMUX78 Register (Offset = E4h) [reset = 0h] .......................................................
Reserved_3 Register (Offset = E8h) [reset = 0h] ......................................................
Reserved_4 Register (Offset = ECh) [reset = 0h]......................................................
Reserved_5 Register (Offset = F0h) [reset = 0h] ......................................................
Reserved_6 Register (Offset = F4h) [reset = 0h] ......................................................
Reserved_7 Register (Offset = F8h) [reset = 0h] ......................................................
Reserved_8 Register (Offset = FCh) [reset = 0h] ......................................................
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
21.17.65
21.17.66
21.17.67
21.17.68
21.17.69
21.17.70
21.17.71
21.17.72
21.17.73
21.17.74
21.17.75
21.17.76
21.17.77
21.17.78
21.17.79
21.17.80
21.17.81
21.17.82
21.17.83
21.17.84
21.17.85
21.17.86
21.17.87
21.17.88
21.17.89
21.17.90
21.17.91
21.17.92
21.17.93
21.17.94
21.17.95
21.17.96
21.17.97
21.17.98
21.17.99
21.17.100
21.17.101
21.17.102
21.17.103
21.17.104
21.17.105
21.17.106
21.17.107
21.17.108
21.17.109
21.17.110
21.17.111
21.17.112
21.17.113
21.17.114
21.17.115
21.17.116
21.17.117
IF1CMD Register (Offset = 100h) [reset = 1h] .........................................................
IF1MSK Register (Offset = 104h) [reset = FFFFFFFFh] ..............................................
IF1ARB Register (Offset = 108h) [reset = 0h] ..........................................................
IF1MCTL Register (Offset = 10Ch) [reset = 0h] ........................................................
IF1DATA Register (Offset = 110h) [reset = 0h] ........................................................
IF1DATB Register (Offset = 114h) [reset = 0h] ........................................................
Reserved_9 Register (Offset = 118h) [reset = 0h] .....................................................
Reserved_10 Register (Offset = 11Ch) [reset = 0h] ...................................................
IF2CMD Register (Offset = 120h) [reset = 1h] .........................................................
IF2MSK Register (Offset = 124h) [reset = FFFFFFFFh] ..............................................
IF2ARB Register (Offset = 128h) [reset = 0h] ..........................................................
IF2MCTL Register (Offset = 12Ch) [reset = 0h] ........................................................
IF2DATA Register (Offset = 130h) [reset = 0h] ........................................................
IF2DATB Register (Offset = 134h) [reset = 0h] ........................................................
Reserved_11 Register (Offset = 138h) [reset = 0h] ...................................................
Reserved_12 Register (Offset = 13Ch) [reset = 0h] ...................................................
IF3OBS Register (Offset = 140h) [reset = 0h] ..........................................................
IF3MSK Register (Offset = 144h) [reset = FFFFFFFFh] ..............................................
IF3ARB Register (Offset = 148h) [reset = 0h] ..........................................................
IF3MCTL Register (Offset = 14Ch) [reset = 0h] ........................................................
IF3DATA Register (Offset = 150h) [reset = 0h] ........................................................
IF3DATB Register (Offset = 154h) [reset = 0h] ........................................................
Reserved_13 Register (Offset = 158h) [reset = 0h] ...................................................
Reserved_14 Register (Offset = 15Ch) [reset = 0h] ...................................................
IF3UPD12 Register (Offset = 160h) [reset = 0h] .......................................................
IF3UPD34 Register (Offset = 164h) [reset = 0h] .......................................................
IF3UPD56 Register (Offset = 168h) [reset = 0h] .......................................................
IF3UPD78 Register (Offset = 16Ch) [reset = 0h] ......................................................
Reserved_15 Register (Offset = 170h) [reset = 0h] ...................................................
Reserved_16 Register (Offset = 174h) [reset = 0h] ...................................................
Reserved_17 Register (Offset = 178h) [reset = 0h] ...................................................
Reserved_18 Register (Offset = 17Ch) [reset = 0h] ...................................................
Reserved_19 Register (Offset = 180h) [reset = 0h] ...................................................
Reserved_20 Register (Offset = 184h) [reset = 0h] ...................................................
Reserved_21 Register (Offset = 188h) [reset = 0h] ...................................................
Reserved_22 Register (Offset = 18Ch) [reset = 0h] .................................................
Reserved_23 Register (Offset = 190h) [reset = 0h] ..................................................
Reserved_24 Register (Offset = 194h) [reset = 0h] ..................................................
Reserved_25 Register (Offset = 198h) [reset = 0h] ..................................................
Reserved_26 Register (Offset = 19Ch) [reset = 0h] .................................................
Reserved_27 Register (Offset = 1A0h) [reset = 0h] .................................................
Reserved_28 Register (Offset = 1A4h) [reset = 0h] .................................................
Reserved_29 Register (Offset = 1A8h) [reset = 0h] .................................................
Reserved_30 Register (Offset = 1ACh) [reset = 0h] .................................................
Reserved_31 Register (Offset = 1B0h) [reset = 0h] .................................................
Reserved_32 Register (Offset = 1B4h) [reset = 0h] .................................................
Reserved_33 Register (Offset = 1B8h) [reset = 0h] .................................................
Reserved_34 Register (Offset = 1BCh) [reset = 0h] .................................................
Reserved_35 Register (Offset = 1C0h) [reset = 0h] .................................................
Reserved_36 Register (Offset = 1C4h) [reset = 0h] .................................................
Reserved_37 Register (Offset = 1C8h) [reset = 0h] .................................................
Reserved_38 Register (Offset = 1CCh) [reset = 0h] .................................................
Reserved_39 Register (Offset = 1D0h) [reset = 0h] .................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
2510
2513
2514
2515
2517
2518
2519
2520
2521
2524
2525
2526
2528
2529
2530
2531
2532
2534
2535
2536
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
15
www.ti.com
21.17.118
21.17.119
21.17.120
21.17.121
21.17.122
22
22.2
23.2
23.3
23.4
23.5
23.6
2579
2579
2580
2613
2712
2712
2714
2747
.................................................. 2850
Overview..................................................................................................................
23.1.1 Features ........................................................................................................
23.1.2 Pin Configurations .............................................................................................
23.1.3 MibSPI /SPI Configurations ..................................................................................
Basic Operation..........................................................................................................
23.2.1 SPI Mode .......................................................................................................
23.2.2 MibSPI Mode ..................................................................................................
23.2.3 DMA Requests ................................................................................................
23.2.4 Interrupts .......................................................................................................
23.2.5 Physical Interface .............................................................................................
23.2.6 Advanced Module Configuration Options ..................................................................
23.2.7 General-Purpose I/O ..........................................................................................
23.2.8 Low-Power Mode ..............................................................................................
23.2.9 Safety Features................................................................................................
23.2.10 Test Features ................................................................................................
23.2.11 Module Configuration .......................................................................................
Control Registers ........................................................................................................
23.3.1 MSS_MIBSPIA Registers ....................................................................................
23.3.2 MSS_MIBSPIB Registers ....................................................................................
Multi-Buffer RAM ........................................................................................................
23.4.1 Multi-Buffer RAM Auto Initialization .........................................................................
23.4.2 Multi-Buffer RAM Register Summary .......................................................................
23.4.3 Multi-Buffer RAM Transmit Data Register .................................................................
23.4.4 Multi-buffer RAM Receive Buffer Register .................................................................
Parity\ECC Memory .....................................................................................................
23.5.1 Example of Parity Memory Organization ...................................................................
23.5.2 Example of ECC Memory Organization ....................................................................
MibSPI Pin Timing Parameters ........................................................................................
23.6.1 Master Mode Timings for SPI/MibSPI ......................................................................
23.6.2 Slave Mode Timings for SPI/MibSPI........................................................................
23.6.3 Master Mode Timing Parameter Details....................................................................
23.6.4 Slave Mode Timing Parameter Details .....................................................................
2851
2851
2852
2853
2853
2853
2855
2856
2858
2860
2864
2882
2882
2882
2884
2886
2888
2889
3005
3121
3122
3122
3123
3125
3127
3130
3131
3132
3132
3134
3135
3135
Quad Serial Peripheral Interface (QSPI) ............................................................................. 3136
24.1
24.2
16
MCAN (14xx,16xx,18xx) ................................................................................................
22.1.1 MCAN Overview ...............................................................................................
22.1.2 MCAN Functional Description ...............................................................................
22.1.3 MCAN Register Manual ......................................................................................
Modular Controller Area Network (68xx MCAN) ....................................................................
22.2.1 MCAN Overview ...............................................................................................
22.2.2 MCAN Functional Description ...............................................................................
22.2.3 MCAN Register Manual ......................................................................................
Multi-Buffered Serial Peripheral Interface Module (MibSPI)
23.1
24
2571
2572
2573
2574
2576
Modular Controller Area Network (MCAN) .......................................................................... 2578
22.1
23
Reserved_40 Register (Offset = 1D4h) [reset = 0h] .................................................
Reserved_41 Register (Offset = 1D8h) [reset = 0h] .................................................
Reserved_42 Register (Offset = 1DCh) [reset = 0h] .................................................
TIOC Register (Offset = 1E0h) [reset = 0h] ...........................................................
RIOC Register (Offset = 1E4h) [reset = 0h] ...........................................................
Quad Serial Peripheral Interface Overview ..........................................................................
QSPI Functional Description ...........................................................................................
24.2.1 QSPI Block Diagram ..........................................................................................
24.2.2 QSPI Clock Configuration ....................................................................................
24.2.3 QSPI Interrupt Requests .....................................................................................
Contents
3137
3138
3138
3143
3143
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
24.3
25
24.2.4 QSPI Memory Regions ....................................................................................... 3145
QSPI Register Manual .................................................................................................. 3146
24.3.1 MSS_QSPI Registers ......................................................................................... 3147
Inter-Integrated Circuit (I2C) ............................................................................................. 3169
25.1
25.2
25.3
25.4
25.5
25.6
Overview..................................................................................................................
25.1.1 Introduction to the I2C Module ..............................................................................
25.1.2 Functional Overview ..........................................................................................
25.1.3 Clock Generation ..............................................................................................
I2C Module Operation ..................................................................................................
25.2.1 Input and Output Voltage Levels ............................................................................
25.2.2 I2C Module Reset Conditions ...............................................................................
25.2.3 I2C Module Data Validity ....................................................................................
25.2.4 I2C Module Start and Stop Conditions .....................................................................
25.2.5 Serial Data Formats...........................................................................................
25.2.6 NACK Bit Generation .........................................................................................
I2C Operation Modes ...................................................................................................
25.3.1 Master Transmitter Mode ....................................................................................
25.3.2 Master Receiver Mode .......................................................................................
25.3.3 Slave Transmitter Mode ......................................................................................
25.3.4 Slave Receiver Mode ........................................................................................
25.3.5 Low Power Mode ..............................................................................................
25.3.6 Free Run Mode ................................................................................................
25.3.7 Ignore NACK Mode ..........................................................................................
I2C Module Integrity.....................................................................................................
25.4.1 Arbitration ......................................................................................................
25.4.2 I2C Clock Generation and Synchronization ...............................................................
25.4.3 Prescaler .......................................................................................................
25.4.4 Noise Filter .....................................................................................................
Operational Information.................................................................................................
25.5.1 I2C Module Interrupts .........................................................................................
25.5.2 DMA Controller Events .......................................................................................
25.5.3 I2C Enable/Disable............................................................................................
25.5.4 General Purpose I/O ..........................................................................................
25.5.5 Pull Up/Pull Down Function ..................................................................................
25.5.6 Open Drain Function ..........................................................................................
MSS_I2C Registers .....................................................................................................
25.6.1 ICOAR Register (Offset = 0h) [reset = 0h] .................................................................
25.6.2 ICIMR Register (Offset = 4h) [reset = 0h] ..................................................................
25.6.3 ICSTR Register (Offset = 8h) [reset = 0h] .................................................................
25.6.4 ICCLKL Register (Offset = Ch) [reset = 0h] ...............................................................
25.6.5 ICCLKH Register (Offset = 10h) [reset = 0h] ..............................................................
25.6.6 ICCNT Register (Offset = 14h) [reset = 0h] ................................................................
25.6.7 ICDRR Register (Offset = 18h) [reset = 0h] ...............................................................
25.6.8 ICSAR Register (Offset = 1Ch) [reset = 0h] ...............................................................
25.6.9 ICDXR Register (Offset = 20h) [reset = 0h] ...............................................................
25.6.10 ICMDR Register (Offset = 24h) [reset = 0h] .............................................................
25.6.11 ICIVR Register (Offset = 28h) [reset = 0h] ...............................................................
25.6.12 ICEMDR Register (Offset = 2Ch) [reset = 0h] ...........................................................
25.6.13 ICPSC Register (Offset = 30h) [reset = 0h] ..............................................................
25.6.14 ICPID1 Register (Offset = 34h) [reset = 0h] ..............................................................
25.6.15 ICPID2 Register (Offset = 38h) [reset = 0h] ..............................................................
25.6.16 ICDMAC Register (Offset = 3Ch) [reset = 0h] ...........................................................
25.6.17 ICPFUNC Register (Offset = 48h) [reset = 0h] ..........................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
3170
3170
3170
3173
3174
3174
3174
3174
3175
3175
3177
3178
3178
3178
3178
3178
3179
3179
3179
3180
3180
3181
3181
3181
3182
3182
3183
3183
3183
3184
3184
3185
3186
3187
3188
3190
3191
3192
3193
3194
3195
3196
3199
3200
3201
3202
3203
3204
3205
17
www.ti.com
25.7
26
3206
3207
3208
3209
3210
3211
3212
Serial Communication Interface (SCI) ................................................................................ 3213
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
18
25.6.18 ICPDIR Register (Offset = 4Ch) [reset = 0h] .............................................................
25.6.19 ICPDIN Register (Offset = 50h) [reset = 0h] .............................................................
25.6.20 ICPDOUT Register (Offset = 54h) [reset = 0h] ..........................................................
25.6.21 ICPDSET Register (Offset = 58h) [reset = 0h] ...........................................................
25.6.22 ICPDCLR Register (Offset = 5Ch) [reset = 0h] ..........................................................
25.6.23 ICPDRV Register (Offset = 60h) [reset = 0h] ............................................................
Sample Waveforms .....................................................................................................
Introduction ...............................................................................................................
26.1.1 SCI Features ...................................................................................................
26.1.2 Block Diagram .................................................................................................
SCI Communication Formats ..........................................................................................
26.2.1 SCI Frame Formats ...........................................................................................
26.2.2 SCI Timing Mode ..............................................................................................
26.2.3 SCI Baud Rate.................................................................................................
26.2.4 SCI Multiprocessor Communication Modes ...............................................................
SCI Interrupts ............................................................................................................
26.3.1 Transmit Interrupt .............................................................................................
26.3.2 Receive Interrupt ..............................................................................................
26.3.3 WakeUp Interrupt .............................................................................................
26.3.4 Error Interrupts ................................................................................................
SCI DMA Interface ......................................................................................................
26.4.1 Receive DMA Requests ......................................................................................
26.4.2 Transmit DMA Requests .....................................................................................
SCI Configurations ......................................................................................................
26.5.1 Receiving Data ................................................................................................
26.5.2 Transmitting Data .............................................................................................
SCI Low Power Mode ..................................................................................................
26.6.1 Sleep Mode for Multiprocessor Communication ..........................................................
SCI Control Registers ..................................................................................................
26.7.1 SCI Global Control Register 0 (SCIGCR0) ................................................................
26.7.2 SCI Global Control Register 1 (SCIGCR1) ................................................................
26.7.3 SCI Set Interrupt Register (SCISETINT) ..................................................................
26.7.4 SCI Clear Interrupt Register (SCICLEARINT) ............................................................
26.7.5 SCI Set Interrupt Level Register (SCISETINTLVL) ......................................................
26.7.6 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ................................................
26.7.7 SCI Flags Register (SCIFLR) ...............................................................................
26.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ...........................................................
26.7.9 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ...........................................................
26.7.10 SCI Format Control Register (SCIFORMAT) ............................................................
26.7.11 Baud Rate Selection Register (BRS) .....................................................................
26.7.12 SCI Data Buffers (SCIED, SCIRD, SCITD) ..............................................................
26.7.13 SCI Pin I/O Control Register 0 (SCIPIO0) ...............................................................
26.7.14 SCI Pin I/O Control Register 1 (SCIPIO1) ...............................................................
26.7.15 SCI Pin I/O Control Register 2 (SCIPIO2) ...............................................................
26.7.16 SCI Pin I/O Control Register 3 (SCIPIO3) ...............................................................
26.7.17 SCI Pin I/O Control Register 4 (SCIPIO4) ...............................................................
26.7.18 SCI Pin I/O Control Register 5 (SCIPIO5) ...............................................................
26.7.19 SCI Pin I/O Control Register 6 (SCIPIO6) ...............................................................
26.7.20 SCI Pin I/O Control Register 7 (SCIPIO7) ...............................................................
26.7.21 SCI Pin I/O Control Register 8 (SCIPIO8) ...............................................................
26.7.22 Input/Output Error Enable (IODFTCTRL) Register .....................................................
GPIO Functionality ......................................................................................................
Contents
3214
3214
3214
3216
3216
3216
3217
3218
3221
3222
3222
3222
3223
3224
3224
3225
3225
3226
3226
3227
3228
3229
3230
3231
3234
3236
3238
3239
3241
3245
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3256
3257
3259
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
26.8.1
26.8.2
26.8.3
26.8.4
26.8.5
27
Debug Subsystem ....................................................................................................... 3261
Triggering Subsystem .................................................................................................. 3262
27.2.1 Cross Trigger Input Tables................................................................................... 3263
Safety ............................................................................................................................ 3264
28.1
28.2
28.3
28.4
28.5
28.6
A
3259
3259
3260
3260
3260
Debug Architecture ......................................................................................................... 3261
27.1
27.2
28
GPIO Functionality ............................................................................................
Under Reset ...................................................................................................
Out of Reset ...................................................................................................
Open-Drain Feature Enabled on a Pin .....................................................................
Summary .......................................................................................................
Dual Clock Comparator (DCC) ........................................................................................
28.1.1 Introduction .....................................................................................................
28.1.2 Module Operation .............................................................................................
28.1.3 Clock Source Selection for Counter0 and Counter1 ......................................................
28.1.4 DCC Registers .................................................................................................
Error Signaling Module (ESM) .........................................................................................
28.2.1 Overview .......................................................................................................
28.2.2 Module Operation .............................................................................................
28.2.3 Recommended Programming Procedure ..................................................................
28.2.4 MSS_ESM Registers .........................................................................................
Cyclic Redundancy Check (CRC) .....................................................................................
28.3.1 Overview .......................................................................................................
28.3.2 Module Operation .............................................................................................
28.3.3 Example .......................................................................................................
28.3.4 DCC Registers .................................................................................................
Programmable Built-In Self-Test (PBIST) ............................................................................
28.4.1 Overview .......................................................................................................
28.4.2 RAM/ROM Grouping and Algorithm ........................................................................
28.4.3 PBIST Registers ...............................................................................................
Self-Test Controller (STC) .............................................................................................
28.5.1 Integration Spec ...............................................................................................
28.5.2 General Description ...........................................................................................
28.5.3 Block Diagram .................................................................................................
28.5.4 Module Description............................................................................................
28.5.5 STC Flow .......................................................................................................
28.5.6 ROM Organization ............................................................................................
28.5.7 STC Registers .................................................................................................
Core Clock Comparator (CCC) Module ..............................................................................
28.6.1 Description .....................................................................................................
28.6.2 Block Diagram .................................................................................................
28.6.3 Perform Clock Comparison ..................................................................................
28.6.4 Recommended Programmation .............................................................................
3265
3265
3266
3270
3271
3282
3282
3285
3288
3289
3319
3319
3321
3331
3335
3347
3347
3349
3351
3363
3363
3364
3365
3366
3368
3369
3376
3448
3448
3449
3449
3450
Glossary ........................................................................................................................ 3451
Revision History ...................................................................................................................... 3471
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Contents
19
www.ti.com
List of Figures
1-1.
14xx Block Diagram ...................................................................................................... 133
1-2.
System Interconnect ...................................................................................................... 136
1-3.
Integration of MSS_CCCA and MSS_CCCB Modules............................................................... 141
1-4.
MSS_DCCA/MSS_DCCB Integration Diagram ....................................................................... 142
1-5.
Integration of MSS_DMA Module ....................................................................................... 143
1-6.
Integration of MSS_RTIA and MSS_RTIB, Using the RTI Module ................................................. 145
1-7.
Integration Block Diagram for MSS_GIO .............................................................................. 146
1-8.
Integration Block Diagram for MSS_DCAN Module .................................................................. 149
1-9.
MSS_MIBSPIA Integration
1-10.
MSS_SPIB Integration Diagram ........................................................................................ 151
1-11.
EDMA Controller Integration
1-12.
14xx MSS_ESM Integration Diagram .................................................................................. 154
2-1.
16xx Block Diagram ...................................................................................................... 160
2-2.
System Interconnect ...................................................................................................... 164
2-3.
Integration of MSS_CCCA and MSS_CCCB Modules............................................................... 171
2-4.
MSS_CCCB Integration to MSS_WD .................................................................................. 172
2-5.
MSS_DCCA/MSS_DCCB Integration Diagram ....................................................................... 173
2-6.
Integration of MSS_DMA and MSS_DMA2 Module .................................................................. 177
2-7.
Integration of MSS_RTIA and MSS_RTIB, WDT Using the MSS_RTIB Module ................................. 180
2-8.
Integration Block Diagram for MSS_GIO .............................................................................. 181
2-9.
MSS_DMM Integration ................................................................................................... 182
2-10.
Multiple MSS_ETPWM Modules ........................................................................................ 183
2-11.
Integration Block Diagram for MSS_DCAN Module .................................................................. 187
2-12.
MSS_MIBSPIA Integration
188
2-13.
MSS_MIBSPIB Integration
189
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
3-1.
3-2.
3-3.
20
..............................................................................................
............................................................................................
..............................................................................................
..............................................................................................
EDMA Controller Integration (1 of 2) ...................................................................................
EDMA Controller Integration (2 of 2) ...................................................................................
16xx MSS_ESM/DSS_ESM Integration Diagram ....................................................................
18xx Block Diagram ......................................................................................................
System Interconnect ......................................................................................................
Integration of MSS_CCCA and MSS_CCCB Modules...............................................................
MSS_CCCB Integration to MSS_WD ..................................................................................
MSS_DCCA/MSS_DCCB Integration Diagram .......................................................................
Integration of MSS_DMA and MSS_DMA2 Module ..................................................................
Integration of MSS_RTIA and MSS_RTIB, WDT Using the MSS_RTIB Module .................................
Integration Block Diagram for MSS_GIO ..............................................................................
MSS_DMM Integration ...................................................................................................
Multiple MSS_ETPWM Modules ........................................................................................
Integration Block Diagram for MSS_DCAN Module ..................................................................
MSS_MIBSPIA Integration ..............................................................................................
MSS_MIBSPIB Integration ..............................................................................................
EDMA Controller Integration (1 of 2) ...................................................................................
EDMA Controller Integration (2 of 2) ...................................................................................
18xx MSS_ESM/DSS_ESM Integration Diagram ....................................................................
68xx Block Diagram ......................................................................................................
System Interconnect ......................................................................................................
Integration of MSS_CCCA and MSS_CCCB Modules...............................................................
List of Figures
150
152
191
192
196
201
205
213
214
215
219
222
223
224
225
229
230
231
233
234
238
245
249
258
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
3-4.
MSS_DCCA/MSS_DCCB Integration Diagram ....................................................................... 259
3-5.
Integration of MSS_DMA and MSS_DMA2 Module .................................................................. 263
3-6.
Integration of MSS_RTIA and MSS_RTIB, WDT Using the MSS_RTIB Module ................................. 266
3-7.
Integration Block Diagram for MSS_GIO .............................................................................. 267
3-8.
MSS_DMM Integration ................................................................................................... 268
3-9.
Multiple MSS_ETPWM Modules ........................................................................................ 269
3-10.
Integration Block Diagram for Module Controller Area Network (MSS_MCAN) .................................. 273
3-11.
MSS_MIBSPIA Integration
274
3-12.
MSS_MIBSPIB Integration
275
3-13.
3-14.
3-15.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
..............................................................................................
..............................................................................................
EDMA Controller Integration (1 of 2) ...................................................................................
EDMA Controller Integration (2 of 2) ...................................................................................
68xx MSS_ESM/DSS_ESM Integration Diagram ....................................................................
Clock Overview ...........................................................................................................
Reset Overview ...........................................................................................................
Power Domains ...........................................................................................................
Power Domain Controls ..................................................................................................
BSSCTL Register .........................................................................................................
EXTCLKDIV Register ....................................................................................................
EXTCLKSRCSEL Register ..............................................................................................
EXTCLKCTL Register ....................................................................................................
SOFTSYSRST Register .................................................................................................
WDRSTEN Register ......................................................................................................
SYSRSTCAUSE Register ...............................................................................................
SYSRSTCAUSECLR Register ..........................................................................................
MISCCAPT Register .....................................................................................................
DCDCCTL0 Register .....................................................................................................
DCDCCTL1 Register .....................................................................................................
MISCCTL Register........................................................................................................
USERMODEEN Register ................................................................................................
LVDSPADCTL0 Register ................................................................................................
LVDSPADCTL1 Register ................................................................................................
DFTREG0 Register .......................................................................................................
DFTREG1 Register .......................................................................................................
DFTREG2 Register .......................................................................................................
DFTREG3 Register .......................................................................................................
DFTREG4 Register .......................................................................................................
DFTREG5 Register .......................................................................................................
SHMEMINITADDR Register .............................................................................................
SHMEMINITECC Register...............................................................................................
DSSMEMBANKEN Register ............................................................................................
DSSMEMTAB0 Register .................................................................................................
DSSMEMTAB1 Register .................................................................................................
TCMAMEMBANK_EN Register .........................................................................................
TCMAMEMTAB0 Register ...............................................................................................
TCMAMEMTAB1 Register ...............................................................................................
TCMBMEMBANKEN Register ..........................................................................................
TCMBMEMTAB0 Register ...............................................................................................
TCMBMEM_TAB1 Register .............................................................................................
MEMINITSTART Register ...............................................................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
277
278
282
288
291
294
294
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
21
www.ti.com
4-38.
MEMINITDONE Register ................................................................................................ 334
4-39.
MSS_SIGNATURE Register
4-40.
MISCCTL1 Register ...................................................................................................... 336
4-41.
USERMODEEN2 Register............................................................................................... 337
4-42.
SYSTICK Register ........................................................................................................ 338
4-43.
SOFTRST2 Register
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
4-59.
4-60.
4-61.
4-62.
4-63.
4-64.
4-65.
4-66.
4-67.
4-68.
4-69.
4-70.
4-71.
4-72.
4-73.
4-74.
4-75.
4-76.
4-77.
4-78.
4-79.
4-80.
4-81.
4-82.
4-83.
4-84.
4-85.
4-86.
22
............................................................................................
.....................................................................................................
CLKDIVCTL0 Register ...................................................................................................
CLKSRCSEL0 Register ..................................................................................................
CR4CTL Register .........................................................................................................
CLKGATE Register .......................................................................................................
CLKSRCSEL1 Register ..................................................................................................
CURRCLKDIV0 Register ................................................................................................
MEMINITSTART Register ...............................................................................................
CURRCLKDIV1 Register ................................................................................................
MEMINITDONE Register ................................................................................................
USERMODEEN Register ................................................................................................
NSYSPERUSERMODEN Register .....................................................................................
ESMGATE0 Register .....................................................................................................
ESMGATE1 Register .....................................................................................................
ESMGATE2 Register .....................................................................................................
ESMGATE3 Register .....................................................................................................
ESMGATE4 Register .....................................................................................................
KEY Register ..............................................................................................................
SWIRQA Register ........................................................................................................
SWIRQB Register ........................................................................................................
MISCCTL0 Register ......................................................................................................
ATCMERRCAPTCTL Register ..........................................................................................
B0TCMERRCAPTCTL Register ........................................................................................
B1TCMERRCAPTCTL Register ........................................................................................
SOFTCORERST Register ...............................................................................................
RSTCAUSE Register .....................................................................................................
RSTCAUSECLR Register ...............................................................................................
SPITRIGSRC Register ...................................................................................................
CLKINUSE Register ......................................................................................................
ECCEN Register ..........................................................................................................
ECCCAPT Register.......................................................................................................
CLKDIVCTL2 Register ...................................................................................................
SWIRQC Register ........................................................................................................
GPCFG0 Register ........................................................................................................
GPCFG1 Register ........................................................................................................
GPCFG2 Register ........................................................................................................
GPCFG3 Register ........................................................................................................
GPCFG4 Register ........................................................................................................
CCCACFG0 Register.....................................................................................................
CCCACFG1 Register.....................................................................................................
CCCACFG2 Register.....................................................................................................
CCCACFG3 Register.....................................................................................................
CCCBCFG0 Register.....................................................................................................
CCCBCFG1 Register.....................................................................................................
List of Figures
335
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
375
376
377
378
379
380
381
382
383
384
385
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-87.
CCCBCFG2 Register..................................................................................................... 386
4-88.
CCCBCFG3 Register..................................................................................................... 387
4-89.
CCCACNTVAL Register ................................................................................................. 388
4-90.
CCCBCNTVAL Register ................................................................................................. 389
4-91.
CCCABERRSTAT Register
4-92.
USERMODEEN Register ................................................................................................ 391
4-93.
RTIEVENTCAPTURESEL Register .................................................................................... 395
4-94.
ADCBUFCFG1 Register ................................................................................................. 396
4-95.
ADCBUFCFG2 Register ................................................................................................. 397
4-96.
ADCBUFCFG3 Register ................................................................................................. 398
4-97.
ADCBUFCFG4 Register ................................................................................................. 399
4-98.
CQCFG1 Register ........................................................................................................ 400
4-99.
TPCCPARSTATCFG Register .......................................................................................... 401
.............................................................................................
390
4-100. CSI2TXPARSTATCFG Register ........................................................................................ 402
4-101. CSICFG1 Register ........................................................................................................ 403
4-102. TPTC0WRMPUSTADD0 Register ...................................................................................... 404
4-103. TPTC0WRMPUSTADD1 Register ...................................................................................... 405
4-104. TPTC0WRMPUSTADD2 Register ...................................................................................... 406
4-105. TPTC0WRMPUSTADD3 Register ...................................................................................... 407
4-106. TPTC0WRMPUSTADD4 Register ...................................................................................... 408
4-107. TPTC0WRMPUSTADD5 Register ...................................................................................... 409
4-108. TPTC0WRMPUSTADD6 Register ...................................................................................... 410
4-109. TPTC0WRMPUSTADD7 Register ...................................................................................... 411
...................................................................................
TPTC0WRMPUENDADD1 Register ...................................................................................
TPTC0WRMPUENDADD2 Register ...................................................................................
TPTC0WRMPUENDADD3 Register ...................................................................................
TPTC0WRMPUENDADD4 Register ...................................................................................
TPTC0WRMPUENDADD5 Register ...................................................................................
TPTC0WRMPUENDADD6 Register ...................................................................................
TPTC0WRMPUENDADD7 Register ...................................................................................
TPTC0WRMPUERRADD Register .....................................................................................
TPTC0RDMPUSTADD0 Register ......................................................................................
TPTC0RDMPUSTADD1 Register ......................................................................................
TPTC0RDMPUSTADD2 Register ......................................................................................
TPTC0RDMPUSTADD3 Register ......................................................................................
TPTC0RDMPUSTADD4 Register ......................................................................................
TPTC0RDMPUSTADD5 Register ......................................................................................
TPTC0RDMPUSTADD6 Register ......................................................................................
TPTC0RDMPUSTADD7 Register ......................................................................................
TPTC0RDMPUENDADD0 Register ....................................................................................
TPTC0RDMPUENDADD1 Register ....................................................................................
TPTC0RDMPUENDADD2 Register ....................................................................................
TPTC0RDMPUENDADD3 Register ....................................................................................
TPTC0RDMPUENDADD4 Register ....................................................................................
TPTC0RDMPUENDADD5 Register ....................................................................................
TPTC0RDMPUENDADD6 Register ....................................................................................
TPTC0RDMPUENDADD7 Register ....................................................................................
TPTC0RDMPUERRADD Register......................................................................................
4-110. TPTC0WRMPUENDADD0 Register
412
4-111.
413
4-112.
4-113.
4-114.
4-115.
4-116.
4-117.
4-118.
4-119.
4-120.
4-121.
4-122.
4-123.
4-124.
4-125.
4-126.
4-127.
4-128.
4-129.
4-130.
4-131.
4-132.
4-133.
4-134.
4-135.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
23
www.ti.com
4-136. TPTC1WRMPUSTADD0 Register ...................................................................................... 438
4-137. TPTC1WRMPUSTADD1 Register ...................................................................................... 439
4-138. TPTC1WRMPUSTADD2 Register ...................................................................................... 440
4-139. TPTC1WRMPUSTADD3 Register ...................................................................................... 441
4-140. TPTC1WRMPUSTADD4 Register ...................................................................................... 442
4-141. TPTC1WRMPUSTADD5 Register ...................................................................................... 443
4-142. TPTC1WRMPUSTADD6 Register ...................................................................................... 444
4-143. TPTC1WRMPUSTADD7 Register ...................................................................................... 445
446
4-145.
447
4-146.
4-147.
4-148.
4-149.
4-150.
4-151.
4-152.
4-153.
4-154.
4-155.
4-156.
4-157.
4-158.
4-159.
4-160.
4-161.
4-162.
4-163.
4-164.
4-165.
4-166.
4-167.
4-168.
4-169.
4-170.
4-171.
4-172.
4-173.
4-174.
4-175.
4-176.
4-177.
4-178.
4-179.
4-180.
4-181.
4-182.
4-183.
4-184.
24
...................................................................................
TPTC1WRMPUENDADD1 Register ...................................................................................
TPTC1WRMPUENDADD2 Register ...................................................................................
TPTC1WRMPUENDADD3 Register ...................................................................................
TPTC1WRMPUENDADD4 Register ...................................................................................
TPTC1WRMPUENDADD5 Register ...................................................................................
TPTC1WRMPUENDADD6 Register ...................................................................................
TPTC1WRMPUENDADD7 Register ...................................................................................
TPTC1WRMPUERRADD Register .....................................................................................
TPTC1RDMPUSTADD0 Register ......................................................................................
TPTC1RDMPUSTADD1 Register ......................................................................................
TPTC1RDMPUSTADD2 Register ......................................................................................
TPTC1RDMPUSTADD3 Register ......................................................................................
TPTC1RDMPUSTADD4 Register ......................................................................................
TPTC1RDMPUSTADD5 Register ......................................................................................
TPTC1RDMPUSTADD6 Register ......................................................................................
TPTC1RDMPUSTADD7 Register ......................................................................................
TPTC1RDMPUENDADD0 Register ....................................................................................
TPTC1RDMPUENDADD1 Register ....................................................................................
TPTC1RDMPUENDADD2 Register ....................................................................................
TPTC1RDMPUENDADD3 Register ....................................................................................
TPTC1RDMPUENDADD4 Register ....................................................................................
TPTC1RDMPUENDADD5 Register ....................................................................................
TPTC1RDMPUENDADD6 Register ....................................................................................
TPTC1RDMPUENDADD7 Register ....................................................................................
TPTC1RDMPUERRADD Register......................................................................................
TPTCMPUVALIDCFG Register .........................................................................................
TPTCMPUENCFG Register .............................................................................................
TESTPATTERNRX1ICFG Register ....................................................................................
TESTPATTERNRX2ICFG Register ....................................................................................
TESTPATTERNRX3ICFG Register ....................................................................................
TESTPATTERNRX4ICFG Register ....................................................................................
TESTPATTERNRX1QCFG Register ...................................................................................
TESTPATTERNRX2QCFG Register ...................................................................................
TESTPATTERNRX3QCFG Register ...................................................................................
TESTPATTERNRX4QCFG Register ...................................................................................
TESTPATTERNVLDCFG Register .....................................................................................
DSSMISC Register .......................................................................................................
DSSMISC2 Register ......................................................................................................
BSSCTL Register .........................................................................................................
DSSCTL Register .........................................................................................................
4-144. TPTC1WRMPUENDADD0 Register
List of Figures
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
487
488
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
....................................................................................................
EXTCLKSRCSEL Register ..............................................................................................
EXTCLKCTL Register ....................................................................................................
SOFTSYSRST Register .................................................................................................
WDRSTEN Register ......................................................................................................
SYSRSTCAUSE Register ...............................................................................................
SYSRSTCAUSECLR Register ..........................................................................................
MISCCAPT Register .....................................................................................................
DCDCCTL0 Register .....................................................................................................
DCDCCTL1 Register .....................................................................................................
USERMODEEN Register ................................................................................................
LVDSPADCTL0 Register ................................................................................................
LVDSPADCTL1 Register ................................................................................................
DFTREG0 Register .......................................................................................................
DFTREG1 Register .......................................................................................................
DFTREG5 Register .......................................................................................................
MEMINITDONE Register ................................................................................................
MSS_SIGNATURE Register ............................................................................................
GEMBOOTSTCEN Register ............................................................................................
MISCCTL1 Register ......................................................................................................
USERMODEEN2 Register...............................................................................................
SYSTICK Register ........................................................................................................
SECURECFGREG1 Register ...........................................................................................
SECURECFGREG2 Register ...........................................................................................
SECURECFGREG3 Register ...........................................................................................
SECURECFGREG4 Register ...........................................................................................
SECURERAMREG Register ............................................................................................
SPAREMULTIBIT Register ..............................................................................................
UID31TO0 Register.......................................................................................................
UID63TO32 Register .....................................................................................................
UID95TO64 Register .....................................................................................................
UID119TO96 Register....................................................................................................
MEMINITSTARTSHMEM Register .....................................................................................
MEMINITDONESHMEM Register ......................................................................................
DSSMEMTAB0 Register .................................................................................................
TCMAMEMTAB Register ................................................................................................
TCMBMEMTAB Register ................................................................................................
SHMEMBANKSEL3TO0 Register ......................................................................................
SHMEMBANKSEL7TO4 Register ......................................................................................
PBISTCLKCTL Register .................................................................................................
SOFTRST1 Register .....................................................................................................
SOFTRST2 Register .....................................................................................................
CLKDIVCTL0 Register ...................................................................................................
CLKSRCSEL0 Register ..................................................................................................
CR4CTL Register .........................................................................................................
CLKGATE Register .......................................................................................................
CLKSRCSEL1 Register ..................................................................................................
CURRCLKDIV0 Register ................................................................................................
RTICURRCLKDIV Register..............................................................................................
4-185. EXTCLKDIV Register
489
4-186.
490
4-187.
4-188.
4-189.
4-190.
4-191.
4-192.
4-193.
4-194.
4-195.
4-196.
4-197.
4-198.
4-199.
4-200.
4-201.
4-202.
4-203.
4-204.
4-205.
4-206.
4-207.
4-208.
4-209.
4-210.
4-211.
4-212.
4-213.
4-214.
4-215.
4-216.
4-217.
4-218.
4-219.
4-220.
4-221.
4-222.
4-223.
4-224.
4-225.
4-226.
4-227.
4-228.
4-229.
4-230.
4-231.
4-232.
4-233.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
531
532
533
534
535
536
537
538
539
25
www.ti.com
4-234. MEMINITSTART Register ............................................................................................... 540
4-235. CURRCLKDIV1 Register
................................................................................................
541
4-236. MEMINITDONE Register ................................................................................................ 542
4-237. ECCENMSSGEM Register .............................................................................................. 543
4-238. ECCCAPTMSSGEM Register........................................................................................... 544
545
4-240.
546
4-241.
4-242.
4-243.
4-244.
4-245.
4-246.
4-247.
4-248.
4-249.
4-250.
4-251.
4-252.
4-253.
4-254.
4-255.
4-256.
4-257.
4-258.
4-259.
4-260.
4-261.
4-262.
4-263.
4-264.
4-265.
4-266.
4-267.
4-268.
4-269.
4-270.
4-271.
4-272.
4-273.
4-274.
4-275.
4-276.
4-277.
4-278.
4-279.
4-280.
4-281.
4-282.
26
..............................................................................................
ECCCAPTBSSGEM Register ...........................................................................................
USERMODEEN Register ................................................................................................
NSYSPERUSERMODEN Register .....................................................................................
SECURERAMMMI Register .............................................................................................
SECURERAMECC Register ............................................................................................
ESMGATE0 Register .....................................................................................................
ESMGATE1 Register .....................................................................................................
ESMGATE2 Register .....................................................................................................
ESMGATE3 Register .....................................................................................................
ESMGATE4 Register .....................................................................................................
KEY Register ..............................................................................................................
SWIRQA Register ........................................................................................................
SWIRQB Register ........................................................................................................
MISCCTL0 Register ......................................................................................................
ATCMERRCAPTCTL Register ..........................................................................................
B0TCMERRCAPTCTL Register ........................................................................................
B1TCMERRCAPTCTL Register ........................................................................................
SOFTCORERST Register ...............................................................................................
RSTCAUSE Register .....................................................................................................
RSTCAUSECLR Register ...............................................................................................
SPITRIGSRC Register ...................................................................................................
CLKINUSE Register ......................................................................................................
ECCENMSSBSS Register ...............................................................................................
ECCCAPTMSSBSS Register ...........................................................................................
CLKDIVCTL2 Register ...................................................................................................
SWIRQC Register ........................................................................................................
GPCFG0 Register ........................................................................................................
GPCFG1 Register ........................................................................................................
GPCFG2 Register ........................................................................................................
GPCFG3 Register ........................................................................................................
GPCFG4 Register ........................................................................................................
GPCFG6 Register ........................................................................................................
GPCFG11 Register .......................................................................................................
CCCACFG0 Register.....................................................................................................
CCCACFG1 Register.....................................................................................................
CCCACFG2 Register.....................................................................................................
CCCACFG3 Register.....................................................................................................
CCCBCFG0 Register.....................................................................................................
CCCBCFG1 Register.....................................................................................................
CCCBCFG2 Register.....................................................................................................
CCCBCFG3 Register.....................................................................................................
CCCACNTVAL Register .................................................................................................
CCCBCNTVAL Register .................................................................................................
4-239. ECCENBSSGEM Register
List of Figures
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
.............................................................................................
USERMODEEN Register ................................................................................................
EPWMCFG Register .....................................................................................................
DMMSWINT0 Register ...................................................................................................
DMMSWINT1 Register ...................................................................................................
DMMSWINTSEL0 Register ..............................................................................................
DMMSWINTSEL1 Register ..............................................................................................
CCCBWDEN Register....................................................................................................
GPIOINTREDGESEL Register ..........................................................................................
PWMDMATRIGEN Register .............................................................................................
JTAGTXDATA Register ..................................................................................................
JTAGTXCONTROL Register ............................................................................................
JTAGRXDATA Register..................................................................................................
JTAGTXRXACK Register ................................................................................................
JTAGRXCONTROL Register............................................................................................
MSS2GEMSWIRQ Register .............................................................................................
CSETBFLUSH Register..................................................................................................
RTIEVENTCAPTURESEL Register ....................................................................................
CQCFG1 Register ........................................................................................................
TPCCPARSTATCFG Register ..........................................................................................
TPTC0WRMPUSTADD0 Register ......................................................................................
TPTC0WRMPUSTADD1 Register ......................................................................................
TPTC0WRMPUSTADD2 Register ......................................................................................
TPTC0WRMPUSTADD3 Register ......................................................................................
TPTC0WRMPUSTADD4 Register ......................................................................................
TPTC0WRMPUSTADD5 Register ......................................................................................
TPTC0WRMPUENDADD0 Register ...................................................................................
TPTC0WRMPUENDADD1 Register ...................................................................................
TPTC0WRMPUENDADD2 Register ...................................................................................
TPTC0WRMPUENDADD3 Register ...................................................................................
TPTC0WRMPUENDADD4 Register ...................................................................................
TPTC0WRMPUENDADD5 Register ...................................................................................
TPTC0WRMPUERRADD Register .....................................................................................
TPTC0RDMPUSTADD0 Register ......................................................................................
TPTC0RDMPUSTADD1 Register ......................................................................................
TPTC0RDMPUSTADD2 Register ......................................................................................
TPTC0RDMPUSTADD3 Register ......................................................................................
TPTC0RDMPUSTADD4 Register ......................................................................................
TPTC0RDMPUSTADD5 Register ......................................................................................
TPTC0RDMPUENDADD0 Register ....................................................................................
TPTC0RDMPUENDADD1 Register ....................................................................................
TPTC0RDMPUENDADD2 Register ....................................................................................
TPTC0RDMPUENDADD3 Register ....................................................................................
TPTC0RDMPUENDADD4 Register ....................................................................................
TPTC0RDMPUENDADD5 Register ....................................................................................
TPTC0RDMPUERRADD Register......................................................................................
TPTC1WRMPUSTADD0 Register ......................................................................................
TPTC1WRMPUSTADD1 Register ......................................................................................
TPTC1WRMPUSTADD2 Register ......................................................................................
4-283. CCCABERRSTAT Register
4-284.
4-285.
4-286.
4-287.
4-288.
4-289.
4-290.
4-291.
4-292.
4-293.
4-294.
4-295.
4-296.
4-297.
4-298.
4-299.
4-300.
4-301.
4-302.
4-303.
4-304.
4-305.
4-306.
4-307.
4-308.
4-309.
4-310.
4-311.
4-312.
4-313.
4-314.
4-315.
4-316.
4-317.
4-318.
4-319.
4-320.
4-321.
4-322.
4-323.
4-324.
4-325.
4-326.
4-327.
4-328.
4-329.
4-330.
4-331.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
27
www.ti.com
4-332. TPTC1WRMPUSTADD3 Register ...................................................................................... 643
4-333. TPTC1WRMPUSTADD4 Register ...................................................................................... 644
4-334. TPTC1WRMPUSTADD5 Register ...................................................................................... 645
646
4-336.
647
4-337.
4-338.
4-339.
4-340.
4-341.
4-342.
4-343.
4-344.
4-345.
4-346.
4-347.
4-348.
4-349.
4-350.
4-351.
4-352.
4-353.
4-354.
4-355.
4-356.
4-357.
4-358.
4-359.
4-360.
4-361.
4-362.
4-363.
4-364.
4-365.
4-366.
4-367.
4-368.
4-369.
4-370.
4-371.
4-372.
4-373.
4-374.
4-375.
4-376.
4-377.
4-378.
4-379.
4-380.
28
...................................................................................
TPTC1WRMPUENDADD1 Register ...................................................................................
TPTC1WRMPUENDADD2 Register ...................................................................................
TPTC1WRMPUENDADD3 Register ...................................................................................
TPTC1WRMPUENDADD4 Register ...................................................................................
TPTC1WRMPUENDADD5 Register ...................................................................................
TPTC1WRMPUERRADD Register .....................................................................................
TPTC1RDMPUSTADD0 Register ......................................................................................
TPTC1RDMPUSTADD1 Register ......................................................................................
TPTC1RDMPUSTADD2 Register ......................................................................................
TPTC1RDMPUSTADD3 Register ......................................................................................
TPTC1RDMPUSTADD4 Register ......................................................................................
TPTC1RDMPUSTADD5 Register ......................................................................................
TPTC1RDMPUENDADD0 Register ....................................................................................
TPTC1RDMPUENDADD1 Register ....................................................................................
TPTC1RDMPUENDADD2 Register ....................................................................................
TPTC1RDMPUENDADD3 Register ....................................................................................
TPTC1RDMPUENDADD4 Register ....................................................................................
TPTC1RDMPUENDADD5 Register ....................................................................................
TPTC1RDMPUERRADD Register......................................................................................
TPTCMPUVALIDCFG Register .........................................................................................
TPTCMPUENCFG Register .............................................................................................
TESTPATTERNRX1ICFG Register ....................................................................................
TESTPATTERNRX2ICFG Register ....................................................................................
TESTPATTERNRX3ICFG Register ....................................................................................
TESTPATTERNRX4ICFG Register ....................................................................................
TESTPATTERNRX1QCFG Register ...................................................................................
TESTPATTERNRX2QCFG Register ...................................................................................
TESTPATTERNRX3QCFG Register ...................................................................................
TESTPATTERNRX4QCFG Register ...................................................................................
TESTPATTERNVLDCFG Register .....................................................................................
TPCC1PARSTATCFG Register ........................................................................................
DMMSWINT1 Register ...................................................................................................
DSSINTRCFG Register ..................................................................................................
MPUMSTIDCFG1 Register ..............................................................................................
MPUMSTIDCFG2 Register ..............................................................................................
MPUMSTIDCFG3 Register ..............................................................................................
HSRAM1ECCCFG Register .............................................................................................
DATATRRAMECCCFG Register .......................................................................................
ADCBUFPINGECCCFG Register ......................................................................................
ADCBUFPONGECCCFG Register .....................................................................................
UMAP0PARITYCFG1 Register .........................................................................................
UMAP0PARITYCFG2 Register .........................................................................................
UMAP0PARITYCFG3 Register .........................................................................................
UMAP1PARITYCFG1 Register .........................................................................................
UMAP1PARITYCFG2 Register .........................................................................................
4-335. TPTC1WRMPUENDADD0 Register
List of Figures
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-381. UMAP1PARITYCFG3 Register ......................................................................................... 692
4-382. ESMGRP2MASKCFG Register ......................................................................................... 693
4-383. L2MEMINITCFG1 Register .............................................................................................. 694
4-384. L2MEMINITCFG2 Register .............................................................................................. 696
4-385. GEMRSTCAUSE Register............................................................................................... 697
4-386. GEMPWRSMCFG4 Register ............................................................................................ 698
4-387. PWRSMWAKEMASK0 Register ........................................................................................ 699
4-388. PWRSMWAKEMASK1 Register ........................................................................................ 700
4-389. PWRSMWAKEMASK2 Register ........................................................................................ 701
4-390. PWRSMMISEVTMASK0 Register ...................................................................................... 702
4-391. PWRSMMISEVTMASK1 Register ...................................................................................... 703
4-392. PWRSMMISEVTMASK2 Register ...................................................................................... 704
4-393. PWRSMWAKESRCSTAT0 Register ................................................................................... 705
4-394. PWRSMWAKESRCSTAT1 Register ................................................................................... 706
4-395. PWRSMWAKESRCSTAT2 Register ................................................................................... 707
4-396. PWRSMEVNTMONSTAT0 Register ................................................................................... 708
4-397. PWRSMEVNTMONSTAT1 Register ................................................................................... 709
4-398. PWRSMEVNTMONSTAT2 Register ................................................................................... 710
4-399. PWRSMWAKESRCSTATCLR0 Register .............................................................................. 711
4-400. PWRSMWAKESRCSTATCLR1 Register .............................................................................. 712
4-401. PWRSMWAKESRCSTATCLR2 Register .............................................................................. 713
4-402. ADCBUFCFG1 Register ................................................................................................. 714
4-403. ADCBUFCFG2 Register ................................................................................................. 715
4-404. ADCBUFCFG3 Register ................................................................................................. 716
4-405. ADCBUFCFG4 Register ................................................................................................. 717
4-406. STCPBISTSMCFG1 Register ........................................................................................... 718
4-407. STCPBISTSMCFG2 Register ........................................................................................... 719
4-408. RTI2EVENTCAPTURESEL Register................................................................................... 720
4-409. DSSMISC5 Register ...................................................................................................... 721
4-410. TPTC2WRMPUSTADD0 Register ...................................................................................... 724
4-411. TPTC2WRMPUSTADD1 Register ...................................................................................... 725
4-412. TPTC2WRMPUSTADD2 Register ...................................................................................... 726
4-413. TPTC2WRMPUSTADD3 Register ...................................................................................... 727
4-414. TPTC2WRMPUSTADD4 Register ...................................................................................... 728
4-415. TPTC2WRMPUSTADD5 Register ...................................................................................... 729
...................................................................................
TPTC2WRMPUENDADD1 Register ...................................................................................
TPTC2WRMPUENDADD2 Register ...................................................................................
TPTC2WRMPUENDADD3 Register ...................................................................................
TPTC2WRMPUENDADD4 Register ...................................................................................
TPTC2WRMPUENDADD5 Register ...................................................................................
TPTC2WRMPUERRADD Register .....................................................................................
TPTC2RDMPUSTADD0 Register ......................................................................................
TPTC2RDMPUSTADD1 Register ......................................................................................
TPTC2RDMPUSTADD2 Register ......................................................................................
TPTC2RDMPUSTADD3 Register ......................................................................................
TPTC2RDMPUSTADD4 Register ......................................................................................
TPTC2RDMPUSTADD5 Register ......................................................................................
TPTC2RDMPUENDADD0 Register ....................................................................................
4-416. TPTC2WRMPUENDADD0 Register
730
4-417.
731
4-418.
4-419.
4-420.
4-421.
4-422.
4-423.
4-424.
4-425.
4-426.
4-427.
4-428.
4-429.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
732
733
734
735
736
737
738
739
740
741
742
743
29
www.ti.com
4-430. TPTC2RDMPUENDADD1 Register .................................................................................... 744
4-431. TPTC2RDMPUENDADD2 Register .................................................................................... 745
4-432. TPTC2RDMPUENDADD3 Register .................................................................................... 746
4-433. TPTC2RDMPUENDADD4 Register .................................................................................... 747
4-434. TPTC2RDMPUENDADD5 Register .................................................................................... 748
4-435. TPTC2RDMPUERRADD Register...................................................................................... 749
4-436. TPTC3WRMPUSTADD0 Register ...................................................................................... 750
4-437. TPTC3WRMPUSTADD1 Register ...................................................................................... 751
4-438. TPTC3WRMPUSTADD2 Register ...................................................................................... 752
4-439. TPTC3WRMPUSTADD3 Register ...................................................................................... 753
4-440. TPTC3WRMPUSTADD4 Register ...................................................................................... 754
4-441. TPTC3WRMPUSTADD5 Register ...................................................................................... 755
756
4-443. TPTC3WRMPUENDADD1 Register
757
4-444.
758
4-445.
4-446.
4-447.
4-448.
4-449.
4-450.
4-451.
4-452.
4-453.
4-454.
4-455.
4-456.
4-457.
4-458.
4-459.
4-460.
4-461.
4-462.
4-463.
4-464.
4-465.
4-466.
4-467.
4-468.
4-469.
4-470.
4-471.
4-472.
4-473.
4-474.
4-475.
4-476.
4-477.
4-478.
30
...................................................................................
...................................................................................
TPTC3WRMPUENDADD2 Register ...................................................................................
TPTC3WRMPUENDADD3 Register ...................................................................................
TPTC3WRMPUENDADD4 Register ...................................................................................
TPTC3WRMPUENDADD5 Register ...................................................................................
TPTC3WRMPUERRADD Register .....................................................................................
TPTC3RDMPUSTADD0 Register ......................................................................................
TPTC3RDMPUSTADD1 Register ......................................................................................
TPTC3RDMPUSTADD2 Register ......................................................................................
TPTC3RDMPUSTADD3 Register ......................................................................................
TPTC3RDMPUSTADD4 Register ......................................................................................
TPTC3RDMPUSTADD5 Register ......................................................................................
TPTC3RDMPUENDADD0 Register ....................................................................................
TPTC3RDMPUENDADD1 Register ....................................................................................
TPTC3RDMPUENDADD2 Register ....................................................................................
TPTC3RDMPUENDADD3 Register ....................................................................................
TPTC3RDMPUENDADD4 Register ....................................................................................
TPTC3RDMPUENDADD5 Register ....................................................................................
TPTC3RDMPUERRADD Register......................................................................................
TPTCMPUVALIDCFG2 Register .......................................................................................
TPTCMPUENCFG2 Register ...........................................................................................
L3ECCCFG1 Register....................................................................................................
L3ECCCFG2 Register....................................................................................................
DSS2MSSSWIRQ Register .............................................................................................
BSSCTL Register .........................................................................................................
DSSCTL Register .........................................................................................................
EXTCLKDIV Register ....................................................................................................
EXTCLKSRCSEL Register ..............................................................................................
EXTCLKCTL Register ....................................................................................................
SOFTSYSRST Register .................................................................................................
WDRSTEN Register ......................................................................................................
SYSRSTCAUSE Register ...............................................................................................
SYSRSTCAUSECLR Register ..........................................................................................
MISCCAPT Register .....................................................................................................
DCDCCTL0 Register .....................................................................................................
DCDCCTL1 Register .....................................................................................................
4-442. TPTC3WRMPUENDADD0 Register
List of Figures
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
784
785
786
787
788
789
790
791
792
793
794
795
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-479. USERMODEEN Register ................................................................................................ 796
4-480. LVDSPADCTL0 Register ................................................................................................ 797
4-481. LVDSPADCTL1 Register ................................................................................................ 798
4-482. DFTREG0 Register ....................................................................................................... 799
4-483. DFTREG1 Register ....................................................................................................... 800
4-484. DFTREG5 Register ....................................................................................................... 801
4-485. MEMINITDONE Register ................................................................................................ 802
............................................................................................
............................................................................................
MISCCTL1 Register ......................................................................................................
USERMODEEN2 Register...............................................................................................
SYSTICK Register ........................................................................................................
SECURECFGREG1 Register ...........................................................................................
SECURECFGREG2 Register ...........................................................................................
SECURECFGREG3 Register ...........................................................................................
SECURECFGREG4 Register ...........................................................................................
SECURERAMREG Register ............................................................................................
SPAREMULTIBIT Register ..............................................................................................
UID31TO0 Register.......................................................................................................
UID63TO32 Register .....................................................................................................
UID95TO64 Register .....................................................................................................
UID119TO96 Register....................................................................................................
MEMINITSTARTSHMEM Register .....................................................................................
MEMINITDONESHMEM Register ......................................................................................
DSSMEMTAB0 Register .................................................................................................
TCMAMEMTAB Register ................................................................................................
TCMBMEMTAB Register ................................................................................................
SHMEMBANKSEL3TO0 Register ......................................................................................
SHMEMBANKSEL7TO4 Register ......................................................................................
PBISTCLKCTL Register .................................................................................................
SOFTRST1 Register .....................................................................................................
SOFTRST2 Register .....................................................................................................
CLKDIVCTL0 Register ...................................................................................................
CLKSRCSEL0 Register ..................................................................................................
CR4CTL Register .........................................................................................................
CLKGATE Register .......................................................................................................
CLKSRCSEL1 Register ..................................................................................................
CURRCLKDIV0 Register ................................................................................................
RTICURRCLKDIV Register..............................................................................................
MEMINITSTART Register ...............................................................................................
CURRCLKDIV1 Register ................................................................................................
MEMINITDONE Register ................................................................................................
ECCENMSSGEM Register ..............................................................................................
ECCCAPTMSSGEM Register...........................................................................................
ECCENBSSGEM Register ..............................................................................................
ECCCAPTBSSGEM Register ...........................................................................................
USERMODEEN Register ................................................................................................
NSYSPERUSERMODEN Register .....................................................................................
SECURERAMMMI Register .............................................................................................
4-486. MSS_SIGNATURE Register
803
4-487. GEMBOOTSTCEN Register
804
4-488.
4-489.
4-490.
4-491.
4-492.
4-493.
4-494.
4-495.
4-496.
4-497.
4-498.
4-499.
4-500.
4-501.
4-502.
4-503.
4-504.
4-505.
4-506.
4-507.
4-508.
4-509.
4-510.
4-511.
4-512.
4-513.
4-514.
4-515.
4-516.
4-517.
4-518.
4-519.
4-520.
4-521.
4-522.
4-523.
4-524.
4-525.
4-526.
4-527.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
31
www.ti.com
847
4-529.
848
4-530.
4-531.
4-532.
4-533.
4-534.
4-535.
4-536.
4-537.
4-538.
4-539.
4-540.
4-541.
4-542.
4-543.
4-544.
4-545.
4-546.
4-547.
4-548.
4-549.
4-550.
4-551.
4-552.
4-553.
4-554.
4-555.
4-556.
4-557.
4-558.
4-559.
4-560.
4-561.
4-562.
4-563.
4-564.
4-565.
4-566.
4-567.
4-568.
4-569.
4-570.
4-571.
4-572.
4-573.
4-574.
4-575.
4-576.
32
............................................................................................
ESMGATE0 Register .....................................................................................................
ESMGATE1 Register .....................................................................................................
ESMGATE2 Register .....................................................................................................
ESMGATE3 Register .....................................................................................................
ESMGATE4 Register .....................................................................................................
KEY Register ..............................................................................................................
SWIRQA Register ........................................................................................................
SWIRQB Register ........................................................................................................
MISCCTL0 Register ......................................................................................................
ATCMERRCAPTCTL Register ..........................................................................................
B0TCMERRCAPTCTL Register ........................................................................................
B1TCMERRCAPTCTL Register ........................................................................................
SOFTCORERST Register ...............................................................................................
RSTCAUSE Register .....................................................................................................
RSTCAUSECLR Register ...............................................................................................
SPITRIGSRC Register ...................................................................................................
CLKINUSE Register ......................................................................................................
ECCENMSSBSS Register ...............................................................................................
ECCCAPTMSSBSS Register ...........................................................................................
CLKDIVCTL2 Register ...................................................................................................
SWIRQC Register ........................................................................................................
GPCFG0 Register ........................................................................................................
GPCFG1 Register ........................................................................................................
GPCFG2 Register ........................................................................................................
GPCFG3 Register ........................................................................................................
GPCFG4 Register ........................................................................................................
GPCFG6 Register ........................................................................................................
GPCFG11 Register .......................................................................................................
CCCACFG0 Register.....................................................................................................
CCCACFG1 Register.....................................................................................................
CCCACFG2 Register.....................................................................................................
CCCACFG3 Register.....................................................................................................
CCCBCFG0 Register.....................................................................................................
CCCBCFG1 Register.....................................................................................................
CCCBCFG2 Register.....................................................................................................
CCCBCFG3 Register.....................................................................................................
CCCACNTVAL Register .................................................................................................
CCCBCNTVAL Register .................................................................................................
CCCABERRSTAT Register .............................................................................................
USERMODEEN Register ................................................................................................
EPWMCFG Register .....................................................................................................
DMMSWINT0 Register ...................................................................................................
DMMSWINT1 Register ...................................................................................................
DMMSWINTSEL0 Register ..............................................................................................
DMMSWINTSEL1 Register ..............................................................................................
CCCBWDEN Register....................................................................................................
GPIOINTREDGESEL Register ..........................................................................................
PWMDMATRIGEN Register .............................................................................................
4-528. SECURERAMECC Register
List of Figures
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-577. JTAGTXDATA Register .................................................................................................. 898
4-578. JTAGTXCONTROL Register ............................................................................................ 899
4-579. JTAGRXDATA Register.................................................................................................. 900
4-580. JTAGTXRXACK Register ................................................................................................ 901
4-581. JTAGRXCONTROL Register............................................................................................ 902
4-582. MSS2GEMSWIRQ Register ............................................................................................. 903
4-583. CSETBFLUSH Register.................................................................................................. 904
4-584. RTIEVENTCAPTURESEL Register .................................................................................... 908
4-585. CQCFG1 Register ........................................................................................................ 909
4-586. TPCCPARSTATCFG Register .......................................................................................... 910
4-587. TPTC0WRMPUSTADD0 Register ...................................................................................... 911
4-588. TPTC0WRMPUSTADD1 Register ...................................................................................... 912
4-589. TPTC0WRMPUSTADD2 Register ...................................................................................... 913
4-590. TPTC0WRMPUSTADD3 Register ...................................................................................... 914
4-591. TPTC0WRMPUSTADD4 Register ...................................................................................... 915
4-592. TPTC0WRMPUSTADD5 Register ...................................................................................... 916
...................................................................................
...................................................................................
TPTC0WRMPUENDADD2 Register ...................................................................................
TPTC0WRMPUENDADD3 Register ...................................................................................
TPTC0WRMPUENDADD4 Register ...................................................................................
TPTC0WRMPUENDADD5 Register ...................................................................................
TPTC0WRMPUERRADD Register .....................................................................................
TPTC0RDMPUSTADD0 Register ......................................................................................
TPTC0RDMPUSTADD1 Register ......................................................................................
TPTC0RDMPUSTADD2 Register ......................................................................................
TPTC0RDMPUSTADD3 Register ......................................................................................
TPTC0RDMPUSTADD4 Register ......................................................................................
TPTC0RDMPUSTADD5 Register ......................................................................................
TPTC0RDMPUENDADD0 Register ....................................................................................
TPTC0RDMPUENDADD1 Register ....................................................................................
TPTC0RDMPUENDADD2 Register ....................................................................................
TPTC0RDMPUENDADD3 Register ....................................................................................
TPTC0RDMPUENDADD4 Register ....................................................................................
TPTC0RDMPUENDADD5 Register ....................................................................................
TPTC0RDMPUERRADD Register......................................................................................
TPTC1WRMPUSTADD0 Register ......................................................................................
TPTC1WRMPUSTADD1 Register ......................................................................................
TPTC1WRMPUSTADD2 Register ......................................................................................
TPTC1WRMPUSTADD3 Register ......................................................................................
TPTC1WRMPUSTADD4 Register ......................................................................................
TPTC1WRMPUSTADD5 Register ......................................................................................
TPTC1WRMPUENDADD0 Register ...................................................................................
TPTC1WRMPUENDADD1 Register ...................................................................................
TPTC1WRMPUENDADD2 Register ...................................................................................
TPTC1WRMPUENDADD3 Register ...................................................................................
TPTC1WRMPUENDADD4 Register ...................................................................................
TPTC1WRMPUENDADD5 Register ...................................................................................
TPTC1WRMPUERRADD Register .....................................................................................
4-593. TPTC0WRMPUENDADD0 Register
917
4-594. TPTC0WRMPUENDADD1 Register
918
4-595.
919
4-596.
4-597.
4-598.
4-599.
4-600.
4-601.
4-602.
4-603.
4-604.
4-605.
4-606.
4-607.
4-608.
4-609.
4-610.
4-611.
4-612.
4-613.
4-614.
4-615.
4-616.
4-617.
4-618.
4-619.
4-620.
4-621.
4-622.
4-623.
4-624.
4-625.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
33
www.ti.com
950
4-627.
951
4-628.
4-629.
4-630.
4-631.
4-632.
4-633.
4-634.
4-635.
4-636.
4-637.
4-638.
4-639.
4-640.
4-641.
4-642.
4-643.
4-644.
4-645.
4-646.
4-647.
4-648.
4-649.
4-650.
4-651.
4-652.
4-653.
4-654.
4-655.
4-656.
4-657.
4-658.
4-659.
4-660.
4-661.
4-662.
4-663.
4-664.
4-665.
4-666.
4-667.
4-668.
4-669.
4-670.
4-671.
4-672.
4-673.
4-674.
34
......................................................................................
TPTC1RDMPUSTADD1 Register ......................................................................................
TPTC1RDMPUSTADD2 Register ......................................................................................
TPTC1RDMPUSTADD3 Register ......................................................................................
TPTC1RDMPUSTADD4 Register ......................................................................................
TPTC1RDMPUSTADD5 Register ......................................................................................
TPTC1RDMPUENDADD0 Register ....................................................................................
TPTC1RDMPUENDADD1 Register ....................................................................................
TPTC1RDMPUENDADD2 Register ....................................................................................
TPTC1RDMPUENDADD3 Register ....................................................................................
TPTC1RDMPUENDADD4 Register ....................................................................................
TPTC1RDMPUENDADD5 Register ....................................................................................
TPTC1RDMPUERRADD Register......................................................................................
TPTCMPUVALIDCFG Register .........................................................................................
TPTCMPUENCFG Register .............................................................................................
TESTPATTERNRX1ICFG Register ....................................................................................
TESTPATTERNRX2ICFG Register ....................................................................................
TESTPATTERNRX3ICFG Register ....................................................................................
TESTPATTERNRX4ICFG Register ....................................................................................
TESTPATTERNRX1QCFG Register ...................................................................................
TESTPATTERNRX2QCFG Register ...................................................................................
TESTPATTERNRX3QCFG Register ...................................................................................
TESTPATTERNRX4QCFG Register ...................................................................................
TESTPATTERNVLDCFG Register .....................................................................................
TPCC1PARSTATCFG Register ........................................................................................
DMMSWINT1 Register ...................................................................................................
DSSINTRCFG Register ..................................................................................................
MPUMSTIDCFG1 Register ..............................................................................................
MPUMSTIDCFG2 Register ..............................................................................................
MPUMSTIDCFG3 Register ..............................................................................................
HSRAM1ECCCFG Register .............................................................................................
DATATRRAMECCCFG Register .......................................................................................
ADCBUFPINGECCCFG Register ......................................................................................
ADCBUFPONGECCCFG Register .....................................................................................
UMAP0PARITYCFG1 Register .........................................................................................
UMAP0PARITYCFG2 Register .........................................................................................
UMAP0PARITYCFG3 Register .........................................................................................
UMAP1PARITYCFG1 Register .........................................................................................
UMAP1PARITYCFG2 Register .........................................................................................
UMAP1PARITYCFG3 Register .........................................................................................
ESMGRP2MASKCFG Register .........................................................................................
L2MEMINITCFG1 Register ..............................................................................................
L2MEMINITCFG2 Register ..............................................................................................
GEMRSTCAUSE Register...............................................................................................
GEMPWRSMCFG4 Register ............................................................................................
PWRSMWAKEMASK0 Register ........................................................................................
PWRSMWAKEMASK1 Register ........................................................................................
PWRSMWAKEMASK2 Register ........................................................................................
PWRSMMISEVTMASK0 Register ......................................................................................
4-626. TPTC1RDMPUSTADD0 Register
List of Figures
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
993
994
995
996
997
998
999
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
....................................................................................
PWRSMMISEVTMASK2 Register ....................................................................................
PWRSMWAKESRCSTAT0 Register..................................................................................
PWRSMWAKESRCSTAT1 Register..................................................................................
PWRSMWAKESRCSTAT2 Register..................................................................................
PWRSMEVNTMONSTAT0 Register ..................................................................................
PWRSMEVNTMONSTAT1 Register ..................................................................................
PWRSMEVNTMONSTAT2 Register ..................................................................................
PWRSMWAKESRCSTATCLR0 Register ............................................................................
PWRSMWAKESRCSTATCLR1 Register ............................................................................
PWRSMWAKESRCSTATCLR2 Register ............................................................................
ADCBUFCFG1 Register ................................................................................................
ADCBUFCFG2 Register ................................................................................................
ADCBUFCFG3 Register ................................................................................................
ADCBUFCFG4 Register ................................................................................................
STCPBISTSMCFG1 Register .........................................................................................
STCPBISTSMCFG2 Register .........................................................................................
RTI2EVENTCAPTURESEL Register .................................................................................
DSSMISC5 Register ....................................................................................................
TPTC2WRMPUSTADD0 Register ....................................................................................
TPTC2WRMPUSTADD1 Register ....................................................................................
TPTC2WRMPUSTADD2 Register ....................................................................................
TPTC2WRMPUSTADD3 Register ....................................................................................
TPTC2WRMPUSTADD4 Register ....................................................................................
TPTC2WRMPUSTADD5 Register ....................................................................................
TPTC2WRMPUENDADD0 Register ..................................................................................
TPTC2WRMPUENDADD1 Register ..................................................................................
TPTC2WRMPUENDADD2 Register ..................................................................................
TPTC2WRMPUENDADD3 Register ..................................................................................
TPTC2WRMPUENDADD4 Register ..................................................................................
TPTC2WRMPUENDADD5 Register ..................................................................................
TPTC2WRMPUERRADD Register ...................................................................................
TPTC2RDMPUSTADD0 Register .....................................................................................
TPTC2RDMPUSTADD1 Register .....................................................................................
TPTC2RDMPUSTADD2 Register .....................................................................................
TPTC2RDMPUSTADD3 Register .....................................................................................
TPTC2RDMPUSTADD4 Register .....................................................................................
TPTC2RDMPUSTADD5 Register .....................................................................................
TPTC2RDMPUENDADD0 Register...................................................................................
TPTC2RDMPUENDADD1 Register...................................................................................
TPTC2RDMPUENDADD2 Register...................................................................................
TPTC2RDMPUENDADD3 Register...................................................................................
TPTC2RDMPUENDADD4 Register...................................................................................
TPTC2RDMPUENDADD5 Register...................................................................................
TPTC2RDMPUERRADD Register ....................................................................................
TPTC3WRMPUSTADD0 Register ....................................................................................
TPTC3WRMPUSTADD1 Register ....................................................................................
TPTC3WRMPUSTADD2 Register ....................................................................................
TPTC3WRMPUSTADD3 Register ....................................................................................
4-675. PWRSMMISEVTMASK1 Register
1000
4-676.
1001
4-677.
4-678.
4-679.
4-680.
4-681.
4-682.
4-683.
4-684.
4-685.
4-686.
4-687.
4-688.
4-689.
4-690.
4-691.
4-692.
4-693.
4-694.
4-695.
4-696.
4-697.
4-698.
4-699.
4-700.
4-701.
4-702.
4-703.
4-704.
4-705.
4-706.
4-707.
4-708.
4-709.
4-710.
4-711.
4-712.
4-713.
4-714.
4-715.
4-716.
4-717.
4-718.
4-719.
4-720.
4-721.
4-722.
4-723.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
35
www.ti.com
4-724. TPTC3WRMPUSTADD4 Register .................................................................................... 1051
4-725. TPTC3WRMPUSTADD5 Register .................................................................................... 1052
4-726. TPTC3WRMPUENDADD0 Register .................................................................................. 1053
4-727. TPTC3WRMPUENDADD1 Register .................................................................................. 1054
4-728. TPTC3WRMPUENDADD2 Register .................................................................................. 1055
4-729. TPTC3WRMPUENDADD3 Register .................................................................................. 1056
4-730. TPTC3WRMPUENDADD4 Register .................................................................................. 1057
4-731. TPTC3WRMPUENDADD5 Register .................................................................................. 1058
1059
4-733.
1060
4-734.
4-735.
4-736.
4-737.
4-738.
4-739.
4-740.
4-741.
4-742.
4-743.
4-744.
4-745.
4-746.
4-747.
4-748.
4-749.
4-750.
4-751.
4-752.
4-753.
4-754.
4-755.
4-756.
4-757.
4-758.
4-759.
4-760.
4-761.
4-762.
4-763.
4-764.
4-765.
4-766.
4-767.
4-768.
4-769.
4-770.
4-771.
4-772.
36
...................................................................................
TPTC3RDMPUSTADD0 Register .....................................................................................
TPTC3RDMPUSTADD1 Register .....................................................................................
TPTC3RDMPUSTADD2 Register .....................................................................................
TPTC3RDMPUSTADD3 Register .....................................................................................
TPTC3RDMPUSTADD4 Register .....................................................................................
TPTC3RDMPUSTADD5 Register .....................................................................................
TPTC3RDMPUENDADD0 Register...................................................................................
TPTC3RDMPUENDADD1 Register...................................................................................
TPTC3RDMPUENDADD2 Register...................................................................................
TPTC3RDMPUENDADD3 Register...................................................................................
TPTC3RDMPUENDADD4 Register...................................................................................
TPTC3RDMPUENDADD5 Register...................................................................................
TPTC3RDMPUERRADD Register ....................................................................................
TPTCMPUVALIDCFG2 Register ......................................................................................
TPTCMPUENCFG2 Register ..........................................................................................
L3ECCCFG1 Register ..................................................................................................
L3ECCCFG2 Register ..................................................................................................
DSS2MSSSWIRQ Register ............................................................................................
BSSCTL Register .......................................................................................................
DSSCTL Register .......................................................................................................
EXTCLKDIV Register ...................................................................................................
EXTCLKSRCSEL Register .............................................................................................
EXTCLKCTL Register ..................................................................................................
SOFTSYSRST Register ................................................................................................
WDRSTEN Register ....................................................................................................
SYSRSTCAUSE Register ..............................................................................................
SYSRSTCAUSECLR Register ........................................................................................
MISCCAPT Register ....................................................................................................
DCDCCTL0 Register....................................................................................................
DCDCCTL1 Register....................................................................................................
USERMODEEN Register...............................................................................................
LVDSPADCTL0 Register ...............................................................................................
LVDSPADCTL1 Register ...............................................................................................
DFTREG0 Register .....................................................................................................
DFTREG1 Register .....................................................................................................
DFTREG5 Register .....................................................................................................
MEMINITDONE Register ...............................................................................................
MSS_SIGNATURE Register ...........................................................................................
GEMBOOTSTCEN Register ...........................................................................................
MISCCTL1 Register.....................................................................................................
4-732. TPTC3WRMPUERRADD Register
List of Figures
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-773. USERMODEEN2 Register ............................................................................................. 1102
4-774. SYSTICK Register
......................................................................................................
1103
4-775. SECURECFGREG1 Register .......................................................................................... 1104
4-776. SECURECFGREG2 Register .......................................................................................... 1105
4-777. SECURECFGREG3 Register .......................................................................................... 1106
4-778. SECURECFGREG4 Register .......................................................................................... 1107
4-779. SECURERAMREG Register ........................................................................................... 1108
4-780. SPAREMULTIBIT Register
............................................................................................
1109
4-781. UID31TO0 Register ..................................................................................................... 1110
4-782. UID63TO32 Register.................................................................................................... 1111
4-783. UID95TO64 Register.................................................................................................... 1112
4-784. UID119TO96 Register .................................................................................................. 1113
4-785. MEMINITSTARTSHMEM Register .................................................................................... 1114
4-786. MEMINITDONESHMEM Register ..................................................................................... 1115
4-787. DSSMEMTAB0 Register
...............................................................................................
1116
4-788. TCMAMEMTAB Register ............................................................................................... 1117
4-789. TCMBMEMTAB Register ............................................................................................... 1118
4-790. SHMEMBANKSEL3TO0 Register ..................................................................................... 1119
4-791. SHMEMBANKSEL7TO4 Register ..................................................................................... 1120
4-792. PBISTCLKCTL Register ................................................................................................ 1121
4-793. SOFTRST1 Register .................................................................................................... 1124
4-794. SOFTRST2 Register .................................................................................................... 1125
4-795. CLKDIVCTL0 Register.................................................................................................. 1126
................................................................................................
CR4CTL Register .......................................................................................................
CLKGATE Register .....................................................................................................
CLKSRCSEL1 Register ................................................................................................
CURRCLKDIV0 Register ...............................................................................................
RTICURRCLKDIV Register ............................................................................................
MEMINITSTART Register ..............................................................................................
CURRCLKDIV1 Register ...............................................................................................
MEMINITDONE Register ...............................................................................................
ECCENMSSGEM Register ............................................................................................
ECCCAPTMSSGEM Register .........................................................................................
ECCENBSSGEM Register .............................................................................................
ECCCAPTBSSGEM Register .........................................................................................
USERMODEEN Register...............................................................................................
NSYSPERUSERMODEN Register ...................................................................................
SECURERAMMMI Register ...........................................................................................
SECURERAMECC Register ...........................................................................................
ESMGATE0 Register ...................................................................................................
ESMGATE1 Register ...................................................................................................
ESMGATE2 Register ...................................................................................................
ESMGATE3 Register ...................................................................................................
ESMGATE4 Register ...................................................................................................
KEY Register.............................................................................................................
SWIRQA Register .......................................................................................................
SWIRQB Register .......................................................................................................
MISCCTL0 Register.....................................................................................................
4-796. CLKSRCSEL0 Register
1127
4-797.
1128
4-798.
4-799.
4-800.
4-801.
4-802.
4-803.
4-804.
4-805.
4-806.
4-807.
4-808.
4-809.
4-810.
4-811.
4-812.
4-813.
4-814.
4-815.
4-816.
4-817.
4-818.
4-819.
4-820.
4-821.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
37
www.ti.com
4-822. ATCMERRCAPTCTL Register ........................................................................................ 1153
4-823. B0TCMERRCAPTCTL Register ....................................................................................... 1154
4-824. B1TCMERRCAPTCTL Register ....................................................................................... 1155
4-825. SOFTCORERST Register.............................................................................................. 1156
4-826. RSTCAUSE Register ................................................................................................... 1157
4-827. RSTCAUSECLR Register .............................................................................................. 1158
1159
4-829. CLKINUSE Register
1160
4-830.
1161
4-831.
4-832.
4-833.
4-834.
4-835.
4-836.
4-837.
4-838.
4-839.
4-840.
4-841.
4-842.
4-843.
4-844.
4-845.
4-846.
4-847.
4-848.
4-849.
4-850.
4-851.
4-852.
4-853.
4-854.
4-855.
4-856.
4-857.
4-858.
4-859.
4-860.
4-861.
4-862.
4-863.
4-864.
4-865.
4-866.
4-867.
4-868.
4-869.
4-870.
38
.................................................................................................
....................................................................................................
ECCENMSSBSS Register .............................................................................................
ECCCAPTMSSBSS Register ..........................................................................................
CLKDIVCTL2 Register..................................................................................................
SWIRQC Register .......................................................................................................
GPCFG0 Register .......................................................................................................
GPCFG1 Register .......................................................................................................
GPCFG2 Register .......................................................................................................
GPCFG3 Register .......................................................................................................
GPCFG4 Register .......................................................................................................
GPCFG6 Register .......................................................................................................
GPCFG11 Register .....................................................................................................
CCCACFG0 Register ...................................................................................................
CCCACFG1 Register ...................................................................................................
CCCACFG2 Register ...................................................................................................
CCCACFG3 Register ...................................................................................................
CCCBCFG0 Register ...................................................................................................
CCCBCFG1 Register ...................................................................................................
CCCBCFG2 Register ...................................................................................................
CCCBCFG3 Register ...................................................................................................
CCCACNTVAL Register ................................................................................................
CCCBCNTVAL Register ................................................................................................
CCCABERRSTAT Register ............................................................................................
USERMODEEN Register...............................................................................................
EPWMCFG Register ....................................................................................................
DMMSWINT0 Register .................................................................................................
DMMSWINT1 Register .................................................................................................
DMMSWINTSEL0 Register ............................................................................................
DMMSWINTSEL1 Register ............................................................................................
CCCBWDEN Register ..................................................................................................
GPIOINTREDGESEL Register ........................................................................................
PWMDMATRIGEN Register ...........................................................................................
JTAGTXDATA Register ................................................................................................
JTAGTXCONTROL Register ..........................................................................................
JTAGRXDATA Register ................................................................................................
JTAGTXRXACK Register ..............................................................................................
JTAGRXCONTROL Register ..........................................................................................
MSS2GEMSWIRQ Register ...........................................................................................
CSETBFLUSH Register ................................................................................................
RTIEVENTCAPTURESEL Register...................................................................................
CQCFG1 Register .......................................................................................................
TPCCPARSTATCFG Register ........................................................................................
4-828. SPITRIGSRC Register
List of Figures
1162
1163
1164
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1204
1205
1206
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-871. TPTC0WRMPUSTADD0 Register .................................................................................... 1207
4-872. TPTC0WRMPUSTADD1 Register .................................................................................... 1208
4-873. TPTC0WRMPUSTADD2 Register .................................................................................... 1209
4-874. TPTC0WRMPUSTADD3 Register .................................................................................... 1210
4-875. TPTC0WRMPUSTADD4 Register .................................................................................... 1211
4-876. TPTC0WRMPUSTADD5 Register .................................................................................... 1212
4-877. TPTC0WRMPUENDADD0 Register .................................................................................. 1213
4-878. TPTC0WRMPUENDADD1 Register .................................................................................. 1214
4-879. TPTC0WRMPUENDADD2 Register .................................................................................. 1215
4-880. TPTC0WRMPUENDADD3 Register .................................................................................. 1216
4-881. TPTC0WRMPUENDADD4 Register .................................................................................. 1217
4-882. TPTC0WRMPUENDADD5 Register .................................................................................. 1218
4-883. TPTC0WRMPUERRADD Register
...................................................................................
1219
4-884. TPTC0RDMPUSTADD0 Register ..................................................................................... 1220
4-885. TPTC0RDMPUSTADD1 Register ..................................................................................... 1221
4-886. TPTC0RDMPUSTADD2 Register ..................................................................................... 1222
4-887. TPTC0RDMPUSTADD3 Register ..................................................................................... 1223
4-888. TPTC0RDMPUSTADD4 Register ..................................................................................... 1224
4-889. TPTC0RDMPUSTADD5 Register ..................................................................................... 1225
4-890. TPTC0RDMPUENDADD0 Register................................................................................... 1226
4-891. TPTC0RDMPUENDADD1 Register................................................................................... 1227
4-892. TPTC0RDMPUENDADD2 Register................................................................................... 1228
4-893. TPTC0RDMPUENDADD3 Register................................................................................... 1229
4-894. TPTC0RDMPUENDADD4 Register................................................................................... 1230
4-895. TPTC0RDMPUENDADD5 Register................................................................................... 1231
4-896. TPTC0RDMPUERRADD Register .................................................................................... 1232
4-897. TPTC1WRMPUSTADD0 Register .................................................................................... 1233
4-898. TPTC1WRMPUSTADD1 Register .................................................................................... 1234
4-899. TPTC1WRMPUSTADD2 Register .................................................................................... 1235
4-900. TPTC1WRMPUSTADD3 Register .................................................................................... 1236
4-901. TPTC1WRMPUSTADD4 Register .................................................................................... 1237
4-902. TPTC1WRMPUSTADD5 Register .................................................................................... 1238
4-903. TPTC1WRMPUENDADD0 Register .................................................................................. 1239
4-904. TPTC1WRMPUENDADD1 Register .................................................................................. 1240
4-905. TPTC1WRMPUENDADD2 Register .................................................................................. 1241
4-906. TPTC1WRMPUENDADD3 Register .................................................................................. 1242
4-907. TPTC1WRMPUENDADD4 Register .................................................................................. 1243
4-908. TPTC1WRMPUENDADD5 Register .................................................................................. 1244
...................................................................................
TPTC1RDMPUSTADD0 Register .....................................................................................
TPTC1RDMPUSTADD1 Register .....................................................................................
TPTC1RDMPUSTADD2 Register .....................................................................................
TPTC1RDMPUSTADD3 Register .....................................................................................
TPTC1RDMPUSTADD4 Register .....................................................................................
TPTC1RDMPUSTADD5 Register .....................................................................................
TPTC1RDMPUENDADD0 Register...................................................................................
TPTC1RDMPUENDADD1 Register...................................................................................
TPTC1RDMPUENDADD2 Register...................................................................................
TPTC1RDMPUENDADD3 Register...................................................................................
4-909. TPTC1WRMPUERRADD Register
1245
4-910.
1246
4-911.
4-912.
4-913.
4-914.
4-915.
4-916.
4-917.
4-918.
4-919.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1247
1248
1249
1250
1251
1252
1253
1254
1255
39
www.ti.com
4-920. TPTC1RDMPUENDADD4 Register................................................................................... 1256
4-921. TPTC1RDMPUENDADD5 Register................................................................................... 1257
4-922. TPTC1RDMPUERRADD Register .................................................................................... 1258
.......................................................................................
TPTCMPUENCFG Register ...........................................................................................
TESTPATTERNRX1ICFG Register ...................................................................................
TESTPATTERNRX2ICFG Register ...................................................................................
TESTPATTERNRX3ICFG Register ...................................................................................
TESTPATTERNRX4ICFG Register ...................................................................................
TESTPATTERNRX1QCFG Register .................................................................................
TESTPATTERNRX2QCFG Register .................................................................................
TESTPATTERNRX3QCFG Register .................................................................................
TESTPATTERNRX4QCFG Register .................................................................................
TESTPATTERNVLDCFG Register ...................................................................................
TPCC1PARSTATCFG Register .......................................................................................
DMMSWINT1 Register .................................................................................................
DSSINTRCFG Register ................................................................................................
MPUMSTIDCFG1 Register ............................................................................................
MPUMSTIDCFG2 Register ............................................................................................
MPUMSTIDCFG3 Register ............................................................................................
HSRAM1ECCCFG Register ...........................................................................................
DATATRRAMECCCFG Register ......................................................................................
ADCBUFPINGECCCFG Register .....................................................................................
ADCBUFPONGECCCFG Register ...................................................................................
UMAP0PARITYCFG1 Register ........................................................................................
UMAP0PARITYCFG2 Register ........................................................................................
UMAP0PARITYCFG3 Register ........................................................................................
UMAP1PARITYCFG1 Register ........................................................................................
UMAP1PARITYCFG2 Register ........................................................................................
UMAP1PARITYCFG3 Register ........................................................................................
ESMGRP2MASKCFG Register .......................................................................................
L2MEMINITCFG1 Register ............................................................................................
L2MEMINITCFG2 Register ............................................................................................
GEMRSTCAUSE Register .............................................................................................
GEMPWRSMCFG4 Register ..........................................................................................
PWRSMWAKEMASK0 Register ......................................................................................
PWRSMWAKEMASK1 Register ......................................................................................
PWRSMWAKEMASK2 Register ......................................................................................
PWRSMMISEVTMASK0 Register ....................................................................................
PWRSMMISEVTMASK1 Register ....................................................................................
PWRSMMISEVTMASK2 Register ....................................................................................
PWRSMWAKESRCSTAT0 Register..................................................................................
PWRSMWAKESRCSTAT1 Register..................................................................................
PWRSMWAKESRCSTAT2 Register..................................................................................
PWRSMEVNTMONSTAT0 Register ..................................................................................
PWRSMEVNTMONSTAT1 Register ..................................................................................
PWRSMEVNTMONSTAT2 Register ..................................................................................
PWRSMWAKESRCSTATCLR0 Register ............................................................................
PWRSMWAKESRCSTATCLR1 Register ............................................................................
4-923. TPTCMPUVALIDCFG Register
4-924.
4-925.
4-926.
4-927.
4-928.
4-929.
4-930.
4-931.
4-932.
4-933.
4-934.
4-935.
4-936.
4-937.
4-938.
4-939.
4-940.
4-941.
4-942.
4-943.
4-944.
4-945.
4-946.
4-947.
4-948.
4-949.
4-950.
4-951.
4-952.
4-953.
4-954.
4-955.
4-956.
4-957.
4-958.
4-959.
4-960.
4-961.
4-962.
4-963.
4-964.
4-965.
4-966.
4-967.
4-968.
40
List of Figures
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-969. PWRSMWAKESRCSTATCLR2 Register ............................................................................ 1306
4-970. ADCBUFCFG1 Register ................................................................................................ 1307
4-971. ADCBUFCFG2 Register ................................................................................................ 1308
4-972. ADCBUFCFG3 Register ................................................................................................ 1309
4-973. ADCBUFCFG4 Register ................................................................................................ 1310
.........................................................................................
4-975. STCPBISTSMCFG2 Register .........................................................................................
4-976. RTI2EVENTCAPTURESEL Register .................................................................................
4-977. DSSMISC5 Register ....................................................................................................
4-978. TPTC2WRMPUSTADD0 Register ....................................................................................
4-979. TPTC2WRMPUSTADD1 Register ....................................................................................
4-980. TPTC2WRMPUSTADD2 Register ....................................................................................
4-981. TPTC2WRMPUSTADD3 Register ....................................................................................
4-982. TPTC2WRMPUSTADD4 Register ....................................................................................
4-983. TPTC2WRMPUSTADD5 Register ....................................................................................
4-984. TPTC2WRMPUENDADD0 Register ..................................................................................
4-985. TPTC2WRMPUENDADD1 Register ..................................................................................
4-986. TPTC2WRMPUENDADD2 Register ..................................................................................
4-987. TPTC2WRMPUENDADD3 Register ..................................................................................
4-988. TPTC2WRMPUENDADD4 Register ..................................................................................
4-989. TPTC2WRMPUENDADD5 Register ..................................................................................
4-990. TPTC2WRMPUERRADD Register ...................................................................................
4-991. TPTC2RDMPUSTADD0 Register .....................................................................................
4-992. TPTC2RDMPUSTADD1 Register .....................................................................................
4-993. TPTC2RDMPUSTADD2 Register .....................................................................................
4-994. TPTC2RDMPUSTADD3 Register .....................................................................................
4-995. TPTC2RDMPUSTADD4 Register .....................................................................................
4-996. TPTC2RDMPUSTADD5 Register .....................................................................................
4-997. TPTC2RDMPUENDADD0 Register...................................................................................
4-998. TPTC2RDMPUENDADD1 Register...................................................................................
4-999. TPTC2RDMPUENDADD2 Register...................................................................................
4-1000. TPTC2RDMPUENDADD3 Register .................................................................................
4-1001. TPTC2RDMPUENDADD4 Register .................................................................................
4-1002. TPTC2RDMPUENDADD5 Register .................................................................................
4-1003. TPTC2RDMPUERRADD Register ...................................................................................
4-1004. TPTC3WRMPUSTADD0 Register ...................................................................................
4-1005. TPTC3WRMPUSTADD1 Register ...................................................................................
4-1006. TPTC3WRMPUSTADD2 Register ...................................................................................
4-1007. TPTC3WRMPUSTADD3 Register ...................................................................................
4-1008. TPTC3WRMPUSTADD4 Register ...................................................................................
4-1009. TPTC3WRMPUSTADD5 Register ...................................................................................
4-1010. TPTC3WRMPUENDADD0 Register .................................................................................
4-1011. TPTC3WRMPUENDADD1 Register .................................................................................
4-1012. TPTC3WRMPUENDADD2 Register .................................................................................
4-1013. TPTC3WRMPUENDADD3 Register .................................................................................
4-1014. TPTC3WRMPUENDADD4 Register .................................................................................
4-1015. TPTC3WRMPUENDADD5 Register .................................................................................
4-1016. TPTC3WRMPUERRADD Register ..................................................................................
4-1017. TPTC3RDMPUSTADD0 Register ...................................................................................
4-974. STCPBISTSMCFG1 Register
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1311
1312
1313
1314
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
41
www.ti.com
...................................................................................
4-1019. TPTC3RDMPUSTADD2 Register ...................................................................................
4-1020. TPTC3RDMPUSTADD3 Register ...................................................................................
4-1021. TPTC3RDMPUSTADD4 Register ...................................................................................
4-1022. TPTC3RDMPUSTADD5 Register ...................................................................................
4-1023. TPTC3RDMPUENDADD0 Register .................................................................................
4-1024. TPTC3RDMPUENDADD1 Register .................................................................................
4-1025. TPTC3RDMPUENDADD2 Register .................................................................................
4-1026. TPTC3RDMPUENDADD3 Register .................................................................................
4-1027. TPTC3RDMPUENDADD4 Register .................................................................................
4-1028. TPTC3RDMPUENDADD5 Register .................................................................................
4-1029. TPTC3RDMPUERRADD Register ...................................................................................
4-1030. TPTCMPUVALIDCFG2 Register.....................................................................................
4-1031. TPTCMPUENCFG2 Register.........................................................................................
4-1032. L3ECCCFG1 Register .................................................................................................
4-1033. L3ECCCFG2 Register .................................................................................................
4-1034. DSS2MSSSWIRQ Register ..........................................................................................
5-1.
RADAR Subsystem Block Diagram ...................................................................................
5-2.
Programming Model ....................................................................................................
5-3.
Clocking Subsystem ....................................................................................................
5-4.
Transmit Subsystem ....................................................................................................
5-5.
Receive Subsystem (Per Channel) ...................................................................................
6-1.
Cortex-R4F Integration .................................................................................................
7-1.
DMA Block Diagram ....................................................................................................
7-2.
Example of a DMA Transfer Using Frame Trigger Source ........................................................
7-3.
Example of a DMA Transfer Using Block Trigger Source .........................................................
7-4.
DMA Request Mapping and Control Packet Organization .........................................................
7-5.
Control Packet Organization and Memory Map .....................................................................
7-6.
DMA Transfer Example 1 ..............................................................................................
7-7.
DMA Indexing Example 1 ..............................................................................................
7-8.
DMA Indexing Example 2 ..............................................................................................
7-9.
Fixed Priority Scheme ..................................................................................................
7-10. Example of Priority Queues ............................................................................................
7-11. Example Channel Assignments .......................................................................................
7-12. Example of DMA Data Unpacking ....................................................................................
7-13. Example of DMA Data Packing .......................................................................................
7-14. DMA Interrupts...........................................................................................................
7-15. Detailed Interrupt Structure (Frame Transfer Complete Path) ....................................................
7-16. Example of Channel Chaining .........................................................................................
7-17. Example of Protection Mechanism ....................................................................................
7-18. GCTRL Register .........................................................................................................
7-19. PEND Register ..........................................................................................................
7-20. FBREG Register .........................................................................................................
7-21. DMASTAT Register .....................................................................................................
7-22. HWCHENAS Register ..................................................................................................
7-23. HWCHENAR Register ..................................................................................................
7-24. SWCHENAS Register ..................................................................................................
7-25. SWCHENAR Register ..................................................................................................
7-26. CHPRIOS Register ......................................................................................................
4-1018. TPTC3RDMPUSTADD1 Register
42
List of Figures
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1375
1376
1377
1378
1378
1380
1382
1383
1383
1385
1385
1387
1387
1388
1388
1389
1390
1391
1392
1395
1395
1398
1399
1404
1405
1406
1407
1408
1409
1410
1411
1412
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
.....................................................................................................
GCHIENAS Register ....................................................................................................
GCHIENAR Register ....................................................................................................
DREQASI0 Register ....................................................................................................
DREQASI1 Register ....................................................................................................
DREQASI2 Register ....................................................................................................
DREQASI3 Register ....................................................................................................
DREQASI4 Register ....................................................................................................
DREQASI5 Register ....................................................................................................
DREQASI6 Register ....................................................................................................
DREQASI7 Register ....................................................................................................
PAR0 Register ...........................................................................................................
PAR1 Register ...........................................................................................................
PAR2 Register ...........................................................................................................
PAR3 Register ...........................................................................................................
FTCMAP Register .......................................................................................................
LFSMAP Register .......................................................................................................
HBCMAP Register ......................................................................................................
BTCMAP Register .......................................................................................................
BERMAP Register.......................................................................................................
FTCINTENAS Register .................................................................................................
FTCINTENAR Register .................................................................................................
LFSINTENAS Register .................................................................................................
LFSINTENAR Register .................................................................................................
HBCINTENAS Register.................................................................................................
HBCINTENAR Register ................................................................................................
BTCINTENAS Register .................................................................................................
BTCINTENAR Register .................................................................................................
GINTFLAG Register ....................................................................................................
FTCFLAG Register ......................................................................................................
LFSFLAG Register ......................................................................................................
HBCFLAG Register .....................................................................................................
BTCFLAG Register .....................................................................................................
BERFLAG Register .....................................................................................................
FTCAOFFSET Register ................................................................................................
LFSAOFFSET Register.................................................................................................
HBCAOFFSET Register ................................................................................................
BTCAOFFSET Register ................................................................................................
BERAOFFSET Register ................................................................................................
FTCBOFFSET Register ................................................................................................
LFSBOFFSET Register.................................................................................................
HBCBOFFSET Register ................................................................................................
BTCBOFFSET Register ................................................................................................
BERBOFFSET Register ................................................................................................
PTCRL Register .........................................................................................................
RTCTRL Register .......................................................................................................
DCTRL Register .........................................................................................................
WPR Register ............................................................................................................
WMR Register ...........................................................................................................
CHPRIOR Register
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1459
1460
1461
1462
43
www.ti.com
7-76.
PAACSADDR Register ................................................................................................. 1463
7-77.
PAACDADDR Register ................................................................................................. 1464
7-78.
PAACTC Register ....................................................................................................... 1465
7-79.
PBACSADDR Register ................................................................................................. 1466
7-80.
PBACDADDR Register ................................................................................................. 1467
7-81.
PBACTC Register ....................................................................................................... 1468
7-82.
DMAPCR Register ...................................................................................................... 1469
7-83.
DMAPAR Register
7-84.
DMAMPCTRL Register ................................................................................................. 1471
7-85.
DMAMPST Register
7-86.
DMAMPR0S Register ................................................................................................... 1474
7-87.
DMAMPR0E Register ................................................................................................... 1475
7-88.
DMAMPR1S Register ................................................................................................... 1476
7-89.
DMAMPR1E Register ................................................................................................... 1477
7-90.
DMAMPR2S Register ................................................................................................... 1478
7-91.
DMAMPR2E Register ................................................................................................... 1479
7-92.
DMAMPR3S Register ................................................................................................... 1480
7-93.
DMAMPR3E Register ................................................................................................... 1481
7-94.
Initial Source Address (ISADDR) [offset = 00]....................................................................... 1482
7-95.
Initial Destination Address Register (IDADDR) [offset = 04h] ..................................................... 1482
7-96.
Initial Transfer Count Register (ITCOUNT) [offset = 08h].......................................................... 1483
7-97.
Channel Control Register (CHCTRL) [offset = 10h] ................................................................ 1483
7-98.
Element Index Offset Register (EIOFF) [offset = 14h]
7-99.
Frame Index Offset Register (FIOFF) [offset = 18h] ................................................................ 1485
......................................................................................................
....................................................................................................
.............................................................
1470
1473
1485
7-100. Current Source Address Register (CSADDR) [offset = 800h] ..................................................... 1486
7-101. Current Destination Address Register (CDADDR) [offset = 804h] ................................................ 1486
7-102. Current Transfer Count Register (CTCOUNT) [offset = 808h] .................................................... 1487
8-1.
Device Level Interrupt Block Diagram ................................................................................ 1490
8-2.
VIM Interrupt Handling Block Diagram ............................................................................... 1493
8-3.
VIM Channel Mapping .................................................................................................. 1494
8-4.
VIM in Default State ..................................................................................................... 1495
8-5.
VIM in a Programmed State ........................................................................................... 1495
8-6.
Interrupt Channel Management ....................................................................................... 1496
8-7.
VIM Interrupt Address Memory Map .................................................................................. 1497
8-8.
ECC Bits Mapping ....................................................................................................... 1501
8-9.
Detail of the IRQ Input .................................................................................................. 1502
8-10.
Capture Event Sources ................................................................................................. 1503
8-11.
Interrupt Vector Table ECC Status Register (ECCSTAT) [offset = ECh] ........................................ 1507
8-12.
Interrupt Vector Table ECC Control Register (ECCCTL) [offset = F0h].......................................... 1508
8-13.
Uncorrectable Error Address Register (UERRADDR) [offset = F4h] ............................................. 1509
8-14.
Fallback Vector Address Register (FBVECADDR) [offset = F8h]................................................. 1509
8-15.
Single Bit Error Address Register (SBERRADDR) [offset = FCh] ................................................ 1510
8-16.
IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h] ..................................................... 1511
8-17.
FIQ Index Offset Vector Register (FIQINDEX) [offset = F04h] .................................................... 1511
8-18.
FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h] .................................................. 1512
8-19.
FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = F14h]
8-20.
8-21.
8-22.
44
................................................
FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h] ..................................................
FIQ/IRQ Program Control Register 3 (FIRQPR3) [offset = 1Ch]..................................................
Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h] ..........................................
List of Figures
1512
1512
1512
1513
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
8-23.
Pending Interrupt Read Location Register 1 (INTREQ1) [offset = 24h] .......................................... 1513
8-24.
Pending Interrupt Read Location Register 2 (INTREQ2) [offset = 28h] .......................................... 1513
8-25.
Pending Interrupt Read Location Register 3 (INTREQ3) [offset = 2Ch] ......................................... 1513
8-26.
Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h] .................................................. 1514
8-27.
Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h] .................................................. 1514
8-28.
Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h] .................................................. 1514
8-29.
Interrupt Enable Set Register 3 (REQENASET3) [offset = 3Ch] .................................................. 1514
8-30.
Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h] ................................................ 1515
8-31.
Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h] ................................................ 1515
8-32.
Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h] ................................................ 1515
8-33.
Interrupt Enable Clear Register 3 (REQENACLR3) [offset = 4Ch] ............................................... 1515
8-34.
Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h] ............................................... 1516
8-35.
Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h] ............................................... 1516
8-36.
Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h] ............................................... 1516
8-37.
Wake-Up Enable Set Register 3 (WAKEENASET3) [offset = 5Ch]
8-38.
Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h] ............................................ 1517
8-39.
Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h] ............................................ 1517
8-40.
Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h] ............................................ 1517
8-41.
Wake-Up Enable Clear Register 3 (WAKEENACLR3) [offset = 6Ch] ............................................ 1517
8-42.
IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h] ...................................................... 1518
8-43.
IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h]....................................................... 1518
8-44.
Capture Event Register (CAPEVT) [offset = 78h] ................................................................... 1519
8-45.
Interrupt Control Registers (CHANCTRL[0:31]) [offset = 80h-FCh]
9-1.
TMS320C674x Megamodule Block Diagram ........................................................................ 1523
10-1.
DSS_L3 Memory Organization ........................................................................................ 1528
10-2.
DSS_L3 Memory Organization ........................................................................................ 1530
10-3.
DSS_L3 Memory Organization ........................................................................................ 1532
12-1.
EDMA Module Overview ............................................................................................... 1536
12-2.
EDMA Controller Block Diagram ...................................................................................... 1538
12-3.
EDMA Channel Controller Block Diagram ........................................................................... 1539
12-4.
TPTC Block Diagram ................................................................................................... 1540
12-5.
Definition of ACNT, BCNT, and CCNT
12-6.
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3).................................................... 1542
12-7.
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................. 1543
12-8.
PaRAM Set ............................................................................................................... 1545
12-9.
Linked Transfer .......................................................................................................... 1553
..............................................
..............................................
..............................................................................
1516
1520
1542
12-10. Link-to-Self Transfer .................................................................................................... 1554
12-11. DMA Channel and QDMA Channel to PaRAM Mapping........................................................... 1560
.................................................................................
Shadow Region Registers .............................................................................................
Interrupt Diagram ........................................................................................................
Error Interrupt Operation ...............................................................................................
PaRAM Set Content for Proxy Memory Protection Example ......................................................
Channel Options Parameter (OPT) Example ........................................................................
Proxy Memory Protection Example ...................................................................................
EDMA Prioritization .....................................................................................................
Block Move Example ...................................................................................................
Block Move Example PaRAM Configuration.........................................................................
Subframe Extraction Transfer .........................................................................................
12-12. QDMA Channel to PaRAM Mapping
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1561
1562
1568
1572
1577
1577
1578
1584
1586
1587
1588
45
www.ti.com
12-23. Subframe Extraction Example PaRAM Configuration .............................................................. 1588
1589
12-25. Data Sorting Example PaRAM Configuration
1590
12-26.
1599
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
12-42.
12-43.
12-44.
12-45.
12-46.
12-47.
12-48.
12-49.
12-50.
12-51.
12-52.
12-53.
12-54.
12-55.
12-56.
12-57.
12-58.
12-59.
12-60.
12-61.
12-62.
12-63.
12-64.
12-65.
12-66.
12-67.
12-68.
12-69.
12-70.
12-71.
46
..................................................................................................
.......................................................................
EDMA_TPCC_PID Register ...........................................................................................
EDMA_TPCC_CCCFG Register ......................................................................................
EDMA_TPCC_QCHMAPN Register ..................................................................................
EDMA_TPCC_DMAQNUMN Register................................................................................
EDMA_TPCC_QDMAQNUM Register ...............................................................................
EDMA_TPCC_QUETCMAP Register ................................................................................
EDMA_TPCC_QUEPRI Register .....................................................................................
EDMA_TPCC_EMR Register ..........................................................................................
EDMA_TPCC_EMRH Register ........................................................................................
EDMA_TPCC_EMCR Register ........................................................................................
EDMA_TPCC_EMCRH Register ......................................................................................
EDMA_TPCC_QEMR Register ........................................................................................
EDMA_TPCC_QEMCR Register ......................................................................................
EDMA_TPCC_CCERR Register ......................................................................................
EDMA_TPCC_CCERRCLR Register .................................................................................
EDMA_TPCC_EEVAL Register .......................................................................................
EDMA_TPCC_DRAEN Register ......................................................................................
EDMA_TPCC_DRAEM Register ......................................................................................
EDMA_TPCC_DRAEHM Register ....................................................................................
EDMA_TPCC_QRAEN Register ......................................................................................
EDMA_TPCC_QNEM Register ........................................................................................
EDMA_TPCC_QNE0 Register ........................................................................................
EDMA_TPCC_QNE1 Register ........................................................................................
EDMA_TPCC_QNE2 Register ........................................................................................
EDMA_TPCC_QNE3 Register ........................................................................................
EDMA_TPCC_QNE4 Register ........................................................................................
EDMA_TPCC_QNE5 Register ........................................................................................
EDMA_TPCC_QNE6 Register ........................................................................................
EDMA_TPCC_QNE7 Register ........................................................................................
EDMA_TPCC_QNE8 Register ........................................................................................
EDMA_TPCC_QNE9 Register ........................................................................................
EDMA_TPCC_QNE10 Register .......................................................................................
EDMA_TPCC_QNE11 Register .......................................................................................
EDMA_TPCC_QNE12 Register .......................................................................................
EDMA_TPCC_QNE13 Register .......................................................................................
EDMA_TPCC_QNE14 Register .......................................................................................
EDMA_TPCC_QNE15 Register .......................................................................................
EDMA_TPCC_QSTATN Register .....................................................................................
EDMA_TPCC_QWMTHRA Register..................................................................................
EDMA_TPCC_CCSTAT Register .....................................................................................
EDMA_TPCC_AETCTL Register .....................................................................................
EDMA_TPCC_AETSTAT Register ....................................................................................
EDMA_TPCC_AETCMD Register ....................................................................................
EDMA_TPCC_ER Register ............................................................................................
EDMA_TPCC_ERH Register ..........................................................................................
EDMA_TPCC_ECR Register ..........................................................................................
12-24. Data Sorting Example
List of Figures
1600
1602
1603
1604
1605
1606
1607
1609
1611
1613
1615
1616
1617
1619
1620
1621
1622
1624
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1648
1649
1650
1651
1653
1655
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
12-72. EDMA_TPCC_ECRH Register ........................................................................................ 1657
12-73. EDMA_TPCC_ESR Register .......................................................................................... 1659
12-74. EDMA_TPCC_ESRH Register ........................................................................................ 1661
12-75. EDMA_TPCC_CER Register .......................................................................................... 1663
12-76. EDMA_TPCC_CERH Register ........................................................................................ 1665
12-77. EDMA_TPCC_EER Register .......................................................................................... 1667
12-78. EDMA_TPCC_EERH Register ........................................................................................ 1669
12-79. EDMA_TPCC_EECR Register ........................................................................................ 1671
......................................................................................
12-81. EDMA_TPCC_EESR Register ........................................................................................
12-82. EDMA_TPCC_EESRH Register ......................................................................................
12-83. EDMA_TPCC_SER Register ..........................................................................................
12-84. EDMA_TPCC_SERH Register ........................................................................................
12-85. EDMA_TPCC_SECR Register ........................................................................................
12-86. EDMA_TPCC_SECRH Register ......................................................................................
12-87. EDMA_TPCC_IER Register ...........................................................................................
12-88. EDMA_TPCC_IERH Register .........................................................................................
12-89. EDMA_TPCC_IECR Register .........................................................................................
12-90. EDMA_TPCC_IECRH Register .......................................................................................
12-91. EDMA_TPCC_IESR Register .........................................................................................
12-92. EDMA_TPCC_IESRH Register........................................................................................
12-93. EDMA_TPCC_IPR Register ...........................................................................................
12-94. EDMA_TPCC_IPRH Register .........................................................................................
12-95. EDMA_TPCC_ICR Register ...........................................................................................
12-96. EDMA_TPCC_ICRH Register .........................................................................................
12-97. EDMA_TPCC_IEVAL Register ........................................................................................
12-98. EDMA_TPCC_QER Register ..........................................................................................
12-99. EDMA_TPCC_QEER Register ........................................................................................
12-100. EDMA_TPCC_QEECR Register .....................................................................................
12-101. EDMA_TPCC_QEESR Register .....................................................................................
12-102. EDMA_TPCC_QSER Register .......................................................................................
12-103. EDMA_TPCC_QSECR Register .....................................................................................
12-104. EDMA_TPCC_SHADOW_N Register ...............................................................................
12-105. EDMA_TPCC_ER_RN Register .....................................................................................
12-106. EDMA_TPCC_ERH_RN Register ...................................................................................
12-107. EDMA_TPCC_ECR_RN Register ...................................................................................
12-108. EDMA_TPCC_ECRH_RN Register .................................................................................
12-109. EDMA_TPCC_ESR_RN Register ...................................................................................
12-110. EDMA_TPCC_ESRH_RN Register..................................................................................
12-111. EDMA_TPCC_CER_RN Register ...................................................................................
12-112. EDMA_TPCC_CERH_RN Register .................................................................................
12-113. EDMA_TPCC_EER_RN Register ...................................................................................
12-114. EDMA_TPCC_EERH_RN Register..................................................................................
12-115. EDMA_TPCC_EECR_RN Register..................................................................................
12-116. EDMA_TPCC_EECRH_RN Register................................................................................
12-117. EDMA_TPCC_EESR_RN Register ..................................................................................
12-118. EDMA_TPCC_EESRH_RN Register ................................................................................
12-119. EDMA_TPCC_SER_RN Register ...................................................................................
12-120. EDMA_TPCC_SERH_RN Register..................................................................................
12-80. EDMA_TPCC_EECRH Register
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1673
1675
1677
1679
1681
1683
1685
1687
1689
1691
1693
1695
1697
1699
1701
1703
1705
1707
1708
1709
1710
1711
1712
1713
1714
1715
1717
1719
1721
1723
1725
1727
1729
1731
1733
1735
1737
1739
1741
1743
1745
47
www.ti.com
12-121. EDMA_TPCC_SECR_RN Register.................................................................................. 1747
12-122. EDMA_TPCC_SECRH_RN Register................................................................................ 1749
12-123. EDMA_TPCC_IER_RN Register..................................................................................... 1751
12-124. EDMA_TPCC_IERH_RN Register................................................................................... 1753
12-125. EDMA_TPCC_IECR_RN Register................................................................................... 1755
12-126. EDMA_TPCC_IECRH_RN Register ................................................................................. 1757
12-127. EDMA_TPCC_IESR_RN Register ................................................................................... 1759
12-128. EDMA_TPCC_IESRH_RN Register ................................................................................. 1761
12-129. EDMA_TPCC_IPR_RN Register..................................................................................... 1763
12-130. EDMA_TPCC_IPRH_RN Register................................................................................... 1765
1767
12-132.
1769
12-133.
12-134.
12-135.
12-136.
12-137.
12-138.
12-139.
12-140.
12-141.
12-142.
12-143.
12-144.
12-145.
12-146.
12-147.
12-148.
12-149.
12-150.
12-151.
12-152.
12-153.
12-154.
12-155.
12-156.
12-157.
12-158.
12-159.
12-160.
12-161.
12-162.
12-163.
12-164.
12-165.
12-166.
12-167.
12-168.
12-169.
48
....................................................................................
EDMA_TPCC_ICRH_RN Register ..................................................................................
EDMA_TPCC_IEVAL_RN Register .................................................................................
EDMA_TPCC_QER_RN Register ...................................................................................
EDMA_TPCC_QEER_RN Register .................................................................................
EDMA_TPCC_QEECR_RN Register ...............................................................................
EDMA_TPCC_QEESR_RN Register................................................................................
EDMA_TPCC_QSER_RN Register .................................................................................
EDMA_TPCC_QSECR_RN Register ...............................................................................
EDMA_TPCC_PARAMSET Register................................................................................
EDMA_TPCC_OPT Register .........................................................................................
EDMA_TPCC_SRC Register .........................................................................................
EDMA_TPCC_ABCNT Register .....................................................................................
EDMA_TPCC_DST Register .........................................................................................
EDMA_TPCC_BIDX Register ........................................................................................
EDMA_TPCC_LNK Register .........................................................................................
EDMA_TPCC_CIDX Register ........................................................................................
EDMA_TPCC_CCNT Register .......................................................................................
EDMA_TPTC_PID Register ..........................................................................................
EDMA_TPTC_TCCFG Register .....................................................................................
EDMA_TPTC_TCSTAT Register ....................................................................................
EDMA_TPTC_INTSTAT Register ...................................................................................
EDMA_TPTC_INTEN Register .......................................................................................
EDMA_TPTC_INTCLR Register .....................................................................................
EDMA_TPTC_INTCMD Register ....................................................................................
EDMA_TPTC_ERRSTAT Register ..................................................................................
EDMA_TPTC_ERREN Register .....................................................................................
EDMA_TPTC_ERRCLR Register ....................................................................................
EDMA_TPTC_ERRDET Register ....................................................................................
EDMA_TPTC_ERRCMD Register ...................................................................................
EDMA_TPTC_RDRATE Register ....................................................................................
EDMA_TPTC_POPT Register .......................................................................................
EDMA_TPTC_PSRC Register .......................................................................................
EDMA_TPTC_PCNT Register .......................................................................................
EDMA_TPTC_PDST Register .......................................................................................
EDMA_TPTC_PBIDX Register .......................................................................................
EDMA_TPTC_PMPPRXY Register..................................................................................
EDMA_TPTC_SAOPT Register......................................................................................
EDMA_TPTC_SASRC Register .....................................................................................
12-131. EDMA_TPCC_ICR_RN Register
List of Figures
1771
1772
1773
1774
1775
1776
1777
1778
1779
1781
1782
1783
1784
1785
1786
1787
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
12-170. EDMA_TPTC_SACNT Register...................................................................................... 1810
12-171. EDMA_TPTC_SABIDX Register ..................................................................................... 1811
12-172. EDMA_TPTC_SAMPPRXY Register ................................................................................ 1812
12-173. EDMA_TPTC_SACNTRLD Register ................................................................................ 1813
12-174. EDMA_TPTC_SASRCBREF Register .............................................................................. 1814
12-175. EDMA_TPTC_SADSTBREF Register............................................................................... 1815
12-176. EDMA_TPTC_DFCNTRLD Register ................................................................................ 1816
12-177. EDMA_TPTC_DFSRCBREF Register .............................................................................. 1817
12-178. EDMA_TPTC_DFOPT Register...................................................................................... 1818
12-179. EDMA_TPTC_DFSRC Register
.....................................................................................
1819
12-180. EDMA_TPTC_DFCNT Register...................................................................................... 1820
12-181. EDMA_TPTC_DFDST Register ...................................................................................... 1821
12-182. EDMA_TPTC_DFBIDX Register ..................................................................................... 1822
12-183. EDMA_TPTC_DFMPPRXY Register ................................................................................ 1823
13-1.
ADC Buffer Block Diagram for the 14xx .............................................................................. 1825
13-2.
ADC Buffer Block Diagram for the 16xx/18xx/68xx ................................................................. 1825
13-3.
Single-Chirp Mode
13-4.
Multi-Chirp Mode ........................................................................................................ 1827
14-1.
HSI Overview ............................................................................................................ 1831
14-2.
CBUFF Sequencing ..................................................................................................... 1833
14-3.
CBUFF Linklist Concept ................................................................................................ 1834
14-4.
Default Use Case........................................................................................................ 1836
14-5.
LVDS Interface Timings ................................................................................................ 1838
14-6.
CONFIG_REG_0 Register ............................................................................................. 1845
14-7.
CFG_SPHDR_ADDRESS Register ................................................................................... 1847
14-8.
CFG_CMD_HSVAL Register .......................................................................................... 1848
14-9.
CFG_CMD_HEVAL Register .......................................................................................... 1849
......................................................................................................
..........................................................................................
..........................................................................................
CFG_LPHDR_ADDRESS Register ...................................................................................
CFG_CHIRPS_PER_FRAME Register...............................................................................
CFG_FIFO_FREE_THRESHOLD Register ..........................................................................
CFG_LPPYLD_ADDRESS Register ..................................................................................
CFG_DATA_LL0 Register..............................................................................................
CFG_DATA_LL0_LPHDR_VAL Register ............................................................................
CFG_DATA_LL0_THRESHOLD Register ...........................................................................
CFG_DATA_LL1 Register..............................................................................................
CFG_DATA_LL1_LPHDR_VAL Register ............................................................................
CFG_DATA_LL1_THRESHOLD Register ...........................................................................
CFG_DATA_LL2 Register..............................................................................................
CFG_DATA_LL2_LPHDR_VAL Register ............................................................................
CFG_DATA_LL2_THRESHOLD Register ...........................................................................
CFG_DATA_LL3 Register..............................................................................................
CFG_DATA_LL3_LPHDR_VAL Register ............................................................................
CFG_DATA_LL3_THRESHOLD Register ...........................................................................
CFG_DATA_LL4 Register..............................................................................................
CFG_DATA_LL4_LPHDR_VAL Register ............................................................................
CFG_DATA_LL4_THRESHOLD Register ...........................................................................
CFG_DATA_LL5 Register..............................................................................................
1826
14-10. CFG_CMD_VSVAL Register
1850
14-11. CFG_CMD_VEVAL Register
1851
14-12.
1852
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
49
www.ti.com
14-32. CFG_DATA_LL5_LPHDR_VAL Register ............................................................................ 1872
14-33. CFG_DATA_LL5_THRESHOLD Register
...........................................................................
1873
14-34. CFG_DATA_LL6 Register.............................................................................................. 1874
14-35. CFG_DATA_LL6_LPHDR_VAL Register ............................................................................ 1875
14-36. CFG_DATA_LL6_THRESHOLD Register
...........................................................................
1876
14-37. CFG_DATA_LL7 Register.............................................................................................. 1877
14-38. CFG_DATA_LL7_LPHDR_VAL Register ............................................................................ 1878
14-39. CFG_DATA_LL7_THRESHOLD Register
...........................................................................
1879
14-40. CFG_DATA_LL8 Register.............................................................................................. 1880
14-41. CFG_DATA_LL8_LPHDR_VAL Register ............................................................................ 1881
1882
14-43.
1883
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
50
...........................................................................
CFG_DATA_LL9 Register..............................................................................................
CFG_DATA_LL9_LPHDR_VAL Register ............................................................................
CFG_DATA_LL9_THRESHOLD Register ...........................................................................
CFG_DATA_LL10 Register ............................................................................................
CFG_DATA_LL10_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL10_THRESHOLD Register ..........................................................................
CFG_DATA_LL11 Register ............................................................................................
CFG_DATA_LL11_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL11_THRESHOLD Register ..........................................................................
CFG_DATA_LL12 Register ............................................................................................
CFG_DATA_LL12_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL12_THRESHOLD Register ..........................................................................
CFG_DATA_LL13 Register ............................................................................................
CFG_DATA_LL13_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL13_THRESHOLD Register ..........................................................................
CFG_DATA_LL14 Register ............................................................................................
CFG_DATA_LL14_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL14_THRESHOLD Register ..........................................................................
CFG_DATA_LL15 Register ............................................................................................
CFG_DATA_LL15_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL15_THRESHOLD Register ..........................................................................
CFG_DATA_LL16 Register ............................................................................................
CFG_DATA_LL16_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL16_THRESHOLD Register ..........................................................................
CFG_DATA_LL17 Register ............................................................................................
CFG_DATA_LL17_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL17_THRESHOLD Register ..........................................................................
CFG_DATA_LL18 Register ............................................................................................
CFG_DATA_LL18_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL18_THRESHOLD Register ..........................................................................
CFG_DATA_LL19 Register ............................................................................................
CFG_DATA_LL19_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL19_THRESHOLD Register ..........................................................................
CFG_DATA_LL20 Register ............................................................................................
CFG_DATA_LL20_LPHDR_VAL Register ...........................................................................
CFG_DATA_LL20_THRESHOLD Register ..........................................................................
CFG_DATA_LL21 Register ............................................................................................
CFG_DATA_LL21_LPHDR_VAL Register ...........................................................................
14-42. CFG_DATA_LL8_THRESHOLD Register
List of Figures
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
14-81. CFG_DATA_LL21_THRESHOLD Register .......................................................................... 1921
14-82. CFG_DATA_LL22 Register ............................................................................................ 1922
14-83. CFG_DATA_LL22_LPHDR_VAL Register ........................................................................... 1923
14-84. CFG_DATA_LL22_THRESHOLD Register .......................................................................... 1924
14-85. CFG_DATA_LL23 Register ............................................................................................ 1925
14-86. CFG_DATA_LL23_LPHDR_VAL Register ........................................................................... 1926
14-87. CFG_DATA_LL23_THRESHOLD Register .......................................................................... 1927
14-88. CFG_DATA_LL24 Register ............................................................................................ 1928
14-89. CFG_DATA_LL24_LPHDR_VAL Register ........................................................................... 1929
14-90. CFG_DATA_LL24_THRESHOLD Register .......................................................................... 1930
14-91. CFG_DATA_LL25 Register ............................................................................................ 1931
14-92. CFG_DATA_LL25_LPHDR_VAL Register ........................................................................... 1932
14-93. CFG_DATA_LL25_THRESHOLD Register .......................................................................... 1933
14-94. CFG_DATA_LL26 Register ............................................................................................ 1934
14-95. CFG_DATA_LL26_LPHDR_VAL Register ........................................................................... 1935
14-96. CFG_DATA_LL26_THRESHOLD Register .......................................................................... 1936
14-97. CFG_DATA_LL27 Register ............................................................................................ 1937
14-98. CFG_DATA_LL27_LPHDR_VAL Register ........................................................................... 1938
14-99. CFG_DATA_LL27_THRESHOLD Register .......................................................................... 1939
14-100. CFG_DATA_LL28 Register ........................................................................................... 1940
.........................................................................
CFG_DATA_LL28_THRESHOLD Register.........................................................................
CFG_DATA_LL29 Register ...........................................................................................
CFG_DATA_LL29_LPHDR_VAL Register .........................................................................
CFG_DATA_LL29_THRESHOLD Register.........................................................................
CFG_DATA_LL30 Register ...........................................................................................
CFG_DATA_LL30_LPHDR_VAL Register .........................................................................
CFG_DATA_LL30_THRESHOLD Register.........................................................................
CFG_DATA_LL31 Register ...........................................................................................
CFG_DATA_LL31_LPHDR_VAL Register .........................................................................
CFG_DATA_LL31_THRESHOLD Register.........................................................................
CFG_LVDS_MAPPING_LANE0_FMT_0 Register ................................................................
CFG_LVDS_MAPPING_LANE1_FMT_0 Register ................................................................
CFG_LVDS_MAPPING_LANE2_FMT_0 Register ................................................................
CFG_LVDS_MAPPING_LANE3_FMT_0 Register ................................................................
CFG_LVDS_MAPPING_LANE0_FMT_1 Register ................................................................
CFG_LVDS_MAPPING_LANE1_FMT_1 Register ................................................................
CFG_LVDS_MAPPING_LANE2_FMT_1 Register ................................................................
CFG_LVDS_MAPPING_LANE3_FMT_1 Register ................................................................
CFG_LVDS_GEN_0 Register ........................................................................................
CFG_LVDS_GEN_1 Register ........................................................................................
CFG_LVDS_GEN_2 Register ........................................................................................
CFG_MASK_REG0 Register .........................................................................................
CFG_MASK_REG1 Register .........................................................................................
CFG_MASK_REG2 Register .........................................................................................
CFG_MASK_REG3 Register .........................................................................................
STAT_CBUFF_REG0 Register ......................................................................................
STAT_CBUFF_REG1 Register ......................................................................................
STAT_CBUFF_REG2 Register ......................................................................................
14-101. CFG_DATA_LL28_LPHDR_VAL Register
14-102.
14-103.
14-104.
14-105.
14-106.
14-107.
14-108.
14-109.
14-110.
14-111.
14-112.
14-113.
14-114.
14-115.
14-116.
14-117.
14-118.
14-119.
14-120.
14-121.
14-122.
14-123.
14-124.
14-125.
14-126.
14-127.
14-128.
14-129.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
51
www.ti.com
14-130. STAT_CBUFF_REG3 Register ...................................................................................... 1970
14-131. CLR_CBUFF_REG0 Register ........................................................................................ 1971
14-132. STAT_CBUFF_ECC_REG Register ................................................................................. 1972
14-133. MASK_CBUFF_ECC_REG Register ................................................................................ 1973
14-134. CLR_CBUFF_ECC_REG Register .................................................................................. 1974
14-135. STAT_SAFETY Register .............................................................................................. 1975
14-136. MASK_SAFETY Register ............................................................................................. 1976
14-137. CLR_SAFETY Register ............................................................................................... 1977
14-138. CSI2 Transmitter/Receiver Data Flow............................................................................... 1978
14-139. Low Level Protocol Packet Overview
...............................................................................
1980
14-140. Long Packet Structure................................................................................................. 1981
14-141. Short Packet Structure ................................................................................................ 1982
14-142. Data Identifier Byte .................................................................................................... 1982
1983
14-144.
1983
14-145.
14-146.
14-147.
14-148.
14-149.
14-150.
14-151.
14-152.
14-153.
14-154.
14-155.
14-156.
14-157.
14-158.
14-159.
14-160.
14-161.
14-162.
14-163.
14-164.
14-165.
14-166.
14-167.
14-168.
14-169.
14-170.
14-171.
14-172.
14-173.
14-174.
14-175.
14-176.
14-177.
14-178.
52
........................................................................
Interleaved Video Data Streams Examples ........................................................................
Four-Data Lane Configuration........................................................................................
Three-Data Lane Configuration ......................................................................................
Two-Data Lane Configuration ........................................................................................
One-Data Lane Configuration ........................................................................................
CSI2 Protocol Engine .................................................................................................
Interface Data Configuration..........................................................................................
LP to HS Timing........................................................................................................
HS to LP Timing........................................................................................................
64-Bit ECC Generation on TX Side .................................................................................
Checksum Transmission ..............................................................................................
16 Bit CRC Generation Using a Shift Register.....................................................................
Complex I/O Power FSM .............................................................................................
HS Clock Transmission ...............................................................................................
HS Data Transmission ................................................................................................
CSI2_REVISION Register ............................................................................................
CSI2_SYSCONFIG Register .........................................................................................
CSI2_SYSSTATUS Register .........................................................................................
CSI2_IRQSTATUS Register ..........................................................................................
CSI2_IRQENABLE Register ..........................................................................................
CSI2_CTRL Register ..................................................................................................
CSI2_GNQ Register ...................................................................................................
CSI2_COMPLEXIO_CFG1 Register ................................................................................
CSI2_COMPLEXIO_IRQSTATUS Register ........................................................................
CSI2_COMPLEXIO_IRQENABLE Register ........................................................................
CSI2_CLK_CTRL Register ...........................................................................................
CSI2_TIMING1 Register ..............................................................................................
CSI2_TIMING2 Register ..............................................................................................
CSI2_VM_TIMING1 Register.........................................................................................
CSI2_VM_TIMING2 Register.........................................................................................
CSI2_VM_TIMING3 Register.........................................................................................
CSI2_CLK_TIMING Register .........................................................................................
CSI2_TX_FIFO_VC_SIZE Register .................................................................................
CSI2_RX_FIFO_VC_SIZE Register .................................................................................
CSI2_COMPLEXIO_CFG2 Register ................................................................................
14-143. Logical Channel Block Diagram (Receiver)
List of Figures
1985
1986
1987
1987
1988
1989
1990
1992
1994
1995
1995
1996
1998
1999
2010
2011
2012
2013
2016
2018
2021
2023
2026
2030
2033
2035
2037
2039
2040
2041
2042
2043
2044
2045
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
14-179. CSI2_RX_FIFO_VC_FULLNESS Register ......................................................................... 2049
14-180. CSI2_VM_TIMING4 Register......................................................................................... 2050
14-181. CSI2_TX_FIFO_VC_EMPTINESS Register ........................................................................ 2051
14-182. CSI2_VM_TIMING5 Register......................................................................................... 2052
14-183. CSI2_VM_TIMING6 Register......................................................................................... 2053
14-184. CSI2_VM_TIMING7 Register......................................................................................... 2054
.................................................................................
................................................................................................
14-187. CSI2_VM_TIMING8 Register.........................................................................................
14-188. CSI2_TE_HSYNC_WIDTH_0 to CSI2_TE_HSYNC_WIDTH_1 Register ......................................
14-189. CSI2_TE_VSYNC_WIDTH_0 to CSI2_TE_VSYNC_WIDTH_1 Register.......................................
14-190. CSI2_TE_HSYNC_NUMBER_0 to CSI2_TE_HSYNC_NUMBER_1 Register.................................
14-191. CSI2_VC_CTRL_0 to CSI2_VC_CTRL_3 Register ...............................................................
14-192. CSI2_VC_TE_0 to CSI2_VC_TE_3 Register ......................................................................
14-193. CSI2_VC_LONG_PACKET_HEADER_0 to CSI2_VC_LONG_PACKET_HEADER_3 Register ............
14-194. CSI2_VC_LONG_PACKET_PAYLOAD_0 to CSI2_VC_LONG_PACKET_PAYLOAD_3 Register .........
14-195. CSI2_VC_SHORT_PACKET_HEADER_0 to CSI2_VC_SHORT_PACKET_HEADER_3 Register ........
14-196. CSI2_VC_IRQSTATUS_0 to CSI2_VC_IRQSTATUS_3 Register ..............................................
14-197. CSI2_VC_IRQENABLE_0 to CSI2_VC_IRQENABLE_3 Register ..............................................
14-198. REGISTER0 Register .................................................................................................
14-199. REGISTER1 Register .................................................................................................
14-200. REGISTER2 Register .................................................................................................
14-201. REGISTER3 Register .................................................................................................
14-202. REGISTER4 Register .................................................................................................
14-203. REGISTER5 Register .................................................................................................
14-204. REGISTER6 Register .................................................................................................
14-205. REGISTER7 Register .................................................................................................
14-206. REGISTER8 Register .................................................................................................
14-207. REGISTER9 Register .................................................................................................
14-208. REGISTER10 Register ................................................................................................
14-209. REGISTER11 Register ................................................................................................
14-210. REGISTER12 Register ................................................................................................
14-211. REGISTER13 Register ................................................................................................
14-212. REGISTER14 Register ................................................................................................
14-213. REGISTER15 Register ................................................................................................
16-1. RTI Block Diagram ......................................................................................................
16-2. Counter Block Diagram .................................................................................................
16-3. Compare Unit Block Diagram (shows only 1 of 4 blocks for simplification) .....................................
16-4. Digital Watchdog ........................................................................................................
16-5. DWD Operation ..........................................................................................................
16-6. Digital Windowed Watchdog Timing Example .......................................................................
16-7. Digital Windowed Watchdog Operation Example (25% Window).................................................
16-8. RTI Global Control Register (RTIGCTRL) [offset = 00] ............................................................
16-9. RTI Timebase Control Register (RTITBCTRL) [offset = 04h] .....................................................
16-10. RTI Capture Control Register (RTICAPCTRL) [offset = 08h]......................................................
16-11. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch] .................................................
16-12. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h] .................................................
16-13. RTI Up Counter 0 Register (RTIUC0) [offset = 14h] ................................................................
16-14. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h] ................................................
14-185. CSI2_STOPCLK_TIMING Register
2055
14-186. CSI2_CTRL2 Register
2056
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2058
2059
2060
2061
2062
2066
2067
2068
2069
2070
2072
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2086
2087
2088
2089
2090
2091
2096
2097
2099
2099
2100
2101
2101
2104
2105
2106
2107
2108
2108
2109
53
www.ti.com
16-15. RTI Capture Free Running Counter 0 Register (RTICAFRC0) [offset = 20h] ................................... 2109
16-16. RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24h]
.................................................
2110
16-17. RTI Free Running Counter 1 Register (RTIFRC1) [offset = 30h] ................................................. 2110
16-18. RTI Up Counter 1 Register (RTIUC1) [offset = 34h] ................................................................ 2111
16-19. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h] ................................................ 2112
16-20. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h] ................................... 2113
16-21. RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h]
.................................................
2113
16-22. RTI Compare 0 Register (RTICOMP0) [offset = 50h] .............................................................. 2114
16-23. RTI Update Compare 0 Register (RTIUDCP0) [offset = 54h] ..................................................... 2114
16-24. RTI Compare 1 Register (RTICOMP1) [offset = 58h] .............................................................. 2115
16-25. RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch] ..................................................... 2115
16-26. RTI Compare 2 Register (RTICOMP2) [offset = 60h] .............................................................. 2116
16-27. RTI Update Compare 2 Register (RTIUDCP2) [offset = 64h] ..................................................... 2116
16-28. RTI Compare 3 Register (RTICOMP3) [offset = 68h] .............................................................. 2117
16-29. RTI Update Compare 3 Register (RTIUDCP3) [offset = 6Ch] ..................................................... 2117
16-30. RTI Timebase Low Compare Register (RTITBLCOMP) [offset = 70h] ........................................... 2118
16-31. RTI Timebase High Compare Register (RTITBHCOMP) [offset = 74h] .......................................... 2118
16-32. RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h] .............................................. 2119
16-33. RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h]........................................ 2121
16-34. RTI Interrupt Flag Register (RTIINTFLAG) [offset = 88h] .......................................................... 2123
16-35. Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h] ............................................... 2124
16-36. Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h] .............................................. 2125
16-37. Watchdog Status Register (RTIWDSTATUS) [offset = 98h] ....................................................... 2126
16-38. RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch] ....................................................... 2127
16-39. RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h] ......................................... 2128
..........................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h] .....................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh] ..........................
RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h] ...................................................
RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h] ...................................................
RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h] ...................................................
RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh] ...................................................
I/O Function Quick Start Flow Chart ..................................................................................
Interrupt Generation Function Quick Start Flow Chart .............................................................
GIO Module Diagram ...................................................................................................
GIO Block Diagram .....................................................................................................
GIOGCR Register .......................................................................................................
GIOINTDET Register ...................................................................................................
GIOPOL Register........................................................................................................
GIOENASET Register ..................................................................................................
GIOENACLR Register ..................................................................................................
GIOLVLSET Register ...................................................................................................
GIOLVLCLR Register ...................................................................................................
GIOFLG Register ........................................................................................................
GIOOFFA Register ......................................................................................................
GIOOFFB Register ......................................................................................................
GIOEMUA Register .....................................................................................................
GIOEMUB Register .....................................................................................................
GIODIRA Register.......................................................................................................
16-40. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [offset = A4h]
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
54
List of Figures
2128
2129
2130
2131
2131
2132
2132
2134
2135
2136
2138
2142
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
17-18. GIODINA Register....................................................................................................... 2156
17-19. GIODOUTA Register.................................................................................................... 2157
17-20. GIOSETA Register ...................................................................................................... 2158
17-21. GIOCLRA Register ...................................................................................................... 2159
.....................................................................................................
.................................................................................................
GIOPSLA Register ......................................................................................................
GIODIRB Register.......................................................................................................
GIODINB Register.......................................................................................................
GIODOUTB Register....................................................................................................
GIOSETB Register ......................................................................................................
GIOCLRB Register ......................................................................................................
GIOPDRB Register .....................................................................................................
GIOPULDISB Register .................................................................................................
GIOPSLB Register ......................................................................................................
GIODIRC Register ......................................................................................................
GIODINC Register ......................................................................................................
GIODOUTC Register ...................................................................................................
GIOSETC Register ......................................................................................................
GIOCLRC Register ......................................................................................................
GIOPDRC Register .....................................................................................................
GIOPULDISC Register .................................................................................................
GIOPSLC Register ......................................................................................................
GIODIRD Register ......................................................................................................
GIODIND Register ......................................................................................................
GIODOUTD Register ...................................................................................................
GIOSETD Register ......................................................................................................
GIOCLRD Register ......................................................................................................
GIOPDRD Register .....................................................................................................
GIOPULDISD Register .................................................................................................
GIOPSLD Register ......................................................................................................
GIODIRE Register.......................................................................................................
GIODINE Register.......................................................................................................
GIODOUTE Register....................................................................................................
GIOSETE Register ......................................................................................................
GIOCLRE Register ......................................................................................................
GIOPDRE Register .....................................................................................................
GIOPULDISE Register .................................................................................................
GIOPSLE Register ......................................................................................................
GIODIRF Register .......................................................................................................
GIODINF Register .......................................................................................................
GIODOUTF Register ....................................................................................................
GIOSETF Register ......................................................................................................
GIOCLRF Register ......................................................................................................
GIOPDRF Register ......................................................................................................
GIOPULDISF Register..................................................................................................
GIOPSLF Register ......................................................................................................
GIODIRG Register ......................................................................................................
GIODING Register ......................................................................................................
17-22. GIOPDRA Register
2160
17-23. GIOPULDISA Register
2161
17-24.
2162
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
55
www.ti.com
17-67. GIODOUTG Register ................................................................................................... 2205
17-68. GIOSETG Register ...................................................................................................... 2206
17-69. GIOCLRG Register
.....................................................................................................
2207
17-70. GIOPDRG Register ..................................................................................................... 2208
17-71. GIOPULDISG Register ................................................................................................. 2209
17-72. GIOPSLG Register ...................................................................................................... 2210
2211
17-74. GIODINH Register
2212
17-75.
2213
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
17-88.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
56
......................................................................................................
......................................................................................................
GIODOUTH Register ...................................................................................................
GIOSETH Register ......................................................................................................
GIOCLRH Register ......................................................................................................
GIOPDRH Register .....................................................................................................
GIOPULDISH Register .................................................................................................
GIOPSLH Register ......................................................................................................
GIOSRCA Register .....................................................................................................
GIOSRCB Register .....................................................................................................
GIOSRCC Register .....................................................................................................
GIOSRCD Register .....................................................................................................
GIOSRCE Register .....................................................................................................
GIOSRCF Register ......................................................................................................
GIOSRCG Register .....................................................................................................
GIOSRCH Register .....................................................................................................
Mailbox Block Diagram .................................................................................................
INT_MASK Register ....................................................................................................
INT_MASK_SET Register ..............................................................................................
INT_MASK_CLR Register..............................................................................................
INT_STS_CLR Register ................................................................................................
INT_ACK Register.......................................................................................................
INT_TRIG Register ......................................................................................................
INT_STS_MASKED Register ..........................................................................................
INT_STS_RAW Register ...............................................................................................
DMM Block Diagram ....................................................................................................
Trace Mode Packet Format ............................................................................................
Direct Data Mode Packet Format .....................................................................................
Packet Sync Signal Example ..........................................................................................
Example Single Packet Transmission ................................................................................
Interrupt Structure .......................................................................................................
DMM Global Control Register (DMMGLBCTRL) [offset = 00h] ...................................................
DMM Interrupt Set Register (DMMINTSET) [offset = 04h].........................................................
DMM Interrupt Clear Register (DMMINTCLR) [offset = 08h] ......................................................
DMM Interrupt Level Register (DMMINTLVL) [offset = 0Ch] ......................................................
DMM Interrupt Flag Register (DMMINTFLG) [offset = 10h] .......................................................
DMM Interrupt Offset 1 Register (DMMOFF1) [offset = 14h] ......................................................
DMM Interrupt Offset 2 Register (DMMOFF2) [offset = 18h] ......................................................
DMM Direct Data Mode Destination Register (DMMDDMDEST) [offset = 1Ch] ................................
DMM Direct Data Mode Blocksize Register (DMMDDMBL) [offset = 20h] ......................................
DMM Direct Data Mode Pointer Register (DMMDDMPT) [offset = 24h] .........................................
DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) [offset = 28h] ................................
DMM Destination x Region 1 (DMMDESTxREG1) [offset = 2Ch, 3Ch, 4Ch, 5Ch] .............................
17-73. GIODIRH Register
List of Figures
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2228
2231
2232
2233
2234
2235
2236
2237
2238
2240
2242
2242
2244
2244
2245
2247
2249
2253
2258
2260
2264
2265
2266
2266
2267
2267
2268
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
19-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) [offset = 30h, 40h, 50h, 60h] .............................. 2269
19-20. DMM Destination x Region 2 (DMMDESTxREG2) [offset = 34h, 44h, 54h, 64h]
..............................
2270
19-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) [offset = 38h, 48h, 58h, 68h] .............................. 2271
......................................................................
DMM Pin Control 1 (DMMPC1) [offset = 70h] .......................................................................
DMM Pin Control 2 (DMMPC2) [offset = 74h] .......................................................................
DMM Pin Control 3 (DMMPC3) [offset = 78h] .......................................................................
DMM Pin Control 4 (DMMPC4) [offset = 7Ch] ......................................................................
DMM Pin Control 5 (DMMPC5) [offset = 80h] .......................................................................
DMM Pin Control 6 (DMMPC6) [offset = 84h] .......................................................................
DMM Pin Control 7 (DMMPC7) [offset = 88h] .......................................................................
DMM Pin Control 8 (DMMPC8) [offset = 8Ch] ......................................................................
ePWM Module ...........................................................................................................
Time-Base Submodule Block Diagram ...............................................................................
Time-Base Submodule Signals and Registers ......................................................................
Time-Base Frequency and Period ....................................................................................
Time-Base Counter Synchronization Scheme .......................................................................
Time-Base Up-Count Mode Waveforms .............................................................................
Time-Base Down-Count Mode Waveforms ..........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ...
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ......
Counter-Compare Submodule .........................................................................................
Detailed View of the Counter-Compare Submodule ................................................................
Counter-Compare Event Waveforms in Up-Count Mode ..........................................................
Counter-Compare Events in Down-Count Mode ....................................................................
19-22. DMM Pin Control 0 (DMMPC0) [offset = 6Ch]
2272
19-23.
2273
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
2275
2276
2277
2279
2280
2282
2283
2286
2292
2293
2295
2296
2298
2299
2299
2300
2300
2301
2303
2303
20-14. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................. 2304
20-15. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ..................................................................................................................... 2304
20-16. Action-Qualifier Submodule ............................................................................................ 2305
20-17. Action-Qualifier Submodule Inputs and Outputs .................................................................... 2306
20-18. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
.........................................
2307
20-19. Up-Down-Count Mode Symmetrical Waveform ..................................................................... 2310
20-20. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 2311
20-21. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 2312
20-22. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 2313
20-23. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 2315
20-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 2316
20-25. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 2317
20-26. Dead_Band Submodule ................................................................................................ 2318
20-27. Configuration Options for the Dead-Band Submodule ............................................................. 2319
20-28. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 2321
20-29. PWM-Chopper Submodule
............................................................................................
2323
20-30. PWM-Chopper Submodule Operational Details ..................................................................... 2324
20-31. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ............................... 2324
20-32. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 2325
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
57
www.ti.com
20-33. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 2326
20-34. Trip-Zone Submodule ................................................................................................... 2327
20-35. Trip-Zone Submodule Mode Control Logic .......................................................................... 2331
20-36. Trip-Zone Submodule Interrupt Logic................................................................................. 2332
20-37. Event-Trigger Submodule .............................................................................................. 2333
20-38. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion....................................... 2334
20-39. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 2335
20-40. Event-Trigger Interrupt Generator ..................................................................................... 2337
2337
20-42. Event-Trigger SOCB Pulse Generator
2338
20-43.
2338
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
58
...............................................................................
...............................................................................
Digital-Compare Submodule High-Level Block Diagram ...........................................................
DCAEVT1 Event Triggering ............................................................................................
DCAEVT2 Event Triggering ............................................................................................
DCBEVT1 Event Triggering ............................................................................................
DCBEVT2 Event Triggering ............................................................................................
Event Filtering ...........................................................................................................
Blanking Window Timing Diagram ....................................................................................
Simplified ePWM Module...............................................................................................
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .....................................
Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .......................................................
Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1) ............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1))...........................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1) ..........................................................
Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) ..........................................................
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control .............................
3-Phase Inverter Waveforms for (Only One Inverter Shown) .....................................................
Configuring Two PWM Modules for Phase Control .................................................................
Timing Waveforms Associated With Phase Control Between 2 Modules .......................................
TBCTL_TBSTS Register ...............................................................................................
TBPHS Register .........................................................................................................
TBCTR_TBPRD Register ..............................................................................................
CMPCTL Register .......................................................................................................
CMPA Register ..........................................................................................................
CMPB_AQCTLA Register ..............................................................................................
AQCTLB_AQSFRC Register ..........................................................................................
AQCSFRC_DBCTL Register ..........................................................................................
DBRED_DBFED Register ..............................................................................................
TZSEL_TZDCSEL Register ............................................................................................
TZCTL_TZEINT Register...............................................................................................
TZFLG_TZCLR Register ...............................................................................................
TZFRC_ETSEL Register ...............................................................................................
ETPS_ETFLG Register .................................................................................................
ETCLR_ETFRC Register...............................................................................................
PCCTL Register .........................................................................................................
Reserved1 Register .....................................................................................................
Reserved2 Register .....................................................................................................
Reserved3 Register .....................................................................................................
20-41. Event-Trigger SOCA Pulse Generator
List of Figures
2341
2341
2342
2342
2343
2344
2345
2346
2347
2348
2350
2351
2353
2354
2356
2357
2358
2359
2362
2364
2365
2366
2368
2369
2371
2373
2375
2376
2378
2380
2382
2384
2386
2387
2388
2389
2390
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
20-81. Reserved4 Register ..................................................................................................... 2391
20-82. Reserved5 Register ..................................................................................................... 2392
20-83. Reserved6 Register ..................................................................................................... 2393
20-84. Reserved7 Register ..................................................................................................... 2394
20-85. Reserved8 Register ..................................................................................................... 2395
......................................................................................
DCBCTL_DCFCTL Register ...........................................................................................
DCCAPCTL_DCFOFFSET Register ..................................................................................
DCFOFFSETCNT_DCFWINDOW Register .........................................................................
DCFWINDOWCNT_DCCAP Register ................................................................................
DCAN Block Diagram ...................................................................................................
Bit Timing .................................................................................................................
CAN Bit-timing Configuration ..........................................................................................
Structure of a Message Object ........................................................................................
Message RAM Representation in Debug/Suspend Mode .........................................................
Message RAM Representation in RAM Direct Access Mode .....................................................
ECC RAM Representation .............................................................................................
Data Transfer Between IF1 / IF2 Registers and Message RAM ..................................................
Initialization of a Transmit Object .....................................................................................
Initialization of a Single Receive Object for Data Frames .........................................................
Initialization of a Single Receive Object for Remote Frames ......................................................
CPU Handling of a FIFO Buffer (Interrupt Driven) ..................................................................
CAN Interrupt Topology 1 ..............................................................................................
CAN Interrupt Topology 2 ..............................................................................................
Local Power Down Mode Flow Diagram .............................................................................
CAN Core in Silent Mode ..............................................................................................
CAN Core in Loop Back Mode ........................................................................................
CAN Core in External Loop Back Mode ..............................................................................
CAN Core in Loop Back Combined with Silent Mode ..............................................................
CTL Register .............................................................................................................
ES Register ..............................................................................................................
ERRC Register ..........................................................................................................
BTR Register.............................................................................................................
INT Register..............................................................................................................
TEST Register ...........................................................................................................
Reserved_1 Register ...................................................................................................
PERR Register ..........................................................................................................
DCAN_REV_ID Register ...............................................................................................
ECCDIAG Register ......................................................................................................
ECCDIAG_STAT Register .............................................................................................
ECC_CS Register .......................................................................................................
ECC_SERR Register ...................................................................................................
TTCAN1 Register .......................................................................................................
TTCAN2 Register .......................................................................................................
TTCAN3 Register .......................................................................................................
TTCAN4 Register .......................................................................................................
TTCAN5 Register .......................................................................................................
TTCAN6 Register .......................................................................................................
TTCAN7 Register .......................................................................................................
20-86. DCTRIPSEL_DCACTL Register
2396
20-87.
2398
20-88.
20-89.
20-90.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2399
2400
2401
2404
2406
2411
2413
2416
2416
2417
2419
2421
2421
2422
2427
2430
2431
2433
2434
2435
2436
2437
2443
2446
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
59
www.ti.com
2466
21-41.
2467
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
21-61.
21-62.
21-63.
21-64.
21-65.
21-66.
21-67.
21-68.
21-69.
21-70.
21-71.
21-72.
21-73.
21-74.
21-75.
21-76.
21-77.
21-78.
21-79.
21-80.
21-81.
21-82.
21-83.
21-84.
21-85.
21-86.
21-87.
21-88.
60
.......................................................................................................
TTCAN9 Register .......................................................................................................
TTCAN10 Register ......................................................................................................
TTCAN11 Register ......................................................................................................
TTCAN12 Register ......................................................................................................
TTCAN13 Register ......................................................................................................
TTCAN14 Register ......................................................................................................
TTCAN15 Register ......................................................................................................
TTCAN16 Register ......................................................................................................
TTCAN17 Register ......................................................................................................
TTCAN18 Register ......................................................................................................
TTCAN19 Register ......................................................................................................
ABOTR Register .........................................................................................................
TXRQ_X Register .......................................................................................................
TXRQ12 Register .......................................................................................................
TXRQ34 Register .......................................................................................................
TXRQ56 Register .......................................................................................................
TXRQ78 Register .......................................................................................................
NWDAT_X Register .....................................................................................................
NWDAT12 Register .....................................................................................................
NWDAT34 Register .....................................................................................................
NWDAT56 Register .....................................................................................................
NWDAT78 Register .....................................................................................................
INTPND_X Register.....................................................................................................
INTPND12 Register .....................................................................................................
INTPND34 Register .....................................................................................................
INTPND56 Register .....................................................................................................
INTPND78 Register .....................................................................................................
MSGVAL_X Register ...................................................................................................
MSGVAL12 Register ....................................................................................................
MSGVAL34 Register ....................................................................................................
MSGVAL56 Register ....................................................................................................
MSGVAL78 Register ....................................................................................................
Reserved_2 Register ...................................................................................................
INTMUX12 Register.....................................................................................................
INTMUX34 Register.....................................................................................................
INTMUX56 Register.....................................................................................................
INTMUX78 Register.....................................................................................................
Reserved_3 Register ...................................................................................................
Reserved_4 Register ...................................................................................................
Reserved_5 Register ...................................................................................................
Reserved_6 Register ...................................................................................................
Reserved_7 Register ...................................................................................................
Reserved_8 Register ...................................................................................................
IF1CMD Register ........................................................................................................
IF1MSK Register ........................................................................................................
IF1ARB Register ........................................................................................................
IF1MCTL Register .......................................................................................................
IF1DATA Register .......................................................................................................
21-40. TTCAN8 Register
List of Figures
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2513
2514
2515
2517
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
21-89. IF1DATB Register ....................................................................................................... 2518
21-90. Reserved_9 Register
...................................................................................................
2519
21-91. Reserved_10 Register .................................................................................................. 2520
21-92. IF2CMD Register ........................................................................................................ 2521
21-93. IF2MSK Register ........................................................................................................ 2524
........................................................................................................
21-95. IF2MCTL Register .......................................................................................................
21-96. IF2DATA Register .......................................................................................................
21-97. IF2DATB Register .......................................................................................................
21-98. Reserved_11 Register ..................................................................................................
21-99. Reserved_12 Register ..................................................................................................
21-100. IF3OBS Register .......................................................................................................
21-101. IF3MSK Register .......................................................................................................
21-102. IF3ARB Register .......................................................................................................
21-103. IF3MCTL Register .....................................................................................................
21-104. IF3DATA Register .....................................................................................................
21-105. IF3DATB Register .....................................................................................................
21-106. Reserved_13 Register ................................................................................................
21-107. Reserved_14 Register ................................................................................................
21-108. IF3UPD12 Register ....................................................................................................
21-109. IF3UPD34 Register ....................................................................................................
21-110. IF3UPD56 Register ....................................................................................................
21-111. IF3UPD78 Register ....................................................................................................
21-112. Reserved_15 Register ................................................................................................
21-113. Reserved_16 Register ................................................................................................
21-114. Reserved_17 Register ................................................................................................
21-115. Reserved_18 Register ................................................................................................
21-116. Reserved_19 Register ................................................................................................
21-117. Reserved_20 Register ................................................................................................
21-118. Reserved_21 Register ................................................................................................
21-119. Reserved_22 Register ................................................................................................
21-120. Reserved_23 Register ................................................................................................
21-121. Reserved_24 Register ................................................................................................
21-122. Reserved_25 Register ................................................................................................
21-123. Reserved_26 Register ................................................................................................
21-124. Reserved_27 Register ................................................................................................
21-125. Reserved_28 Register ................................................................................................
21-126. Reserved_29 Register ................................................................................................
21-127. Reserved_30 Register ................................................................................................
21-128. Reserved_31 Register ................................................................................................
21-129. Reserved_32 Register ................................................................................................
21-130. Reserved_33 Register ................................................................................................
21-131. Reserved_34 Register ................................................................................................
21-132. Reserved_35 Register ................................................................................................
21-133. Reserved_36 Register ................................................................................................
21-134. Reserved_37 Register ................................................................................................
21-135. Reserved_38 Register ................................................................................................
21-136. Reserved_39 Register ................................................................................................
21-137. Reserved_40 Register ................................................................................................
21-94. IF2ARB Register
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2525
2526
2528
2529
2530
2531
2532
2534
2535
2536
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
61
www.ti.com
................................................................................................
21-139. Reserved_42 Register ................................................................................................
21-140. TIOC Register ..........................................................................................................
21-141. RIOC Register ..........................................................................................................
22-1. MCAN Block Diagram ..................................................................................................
22-2. CAN Bit Timing ..........................................................................................................
22-3. Transmitter Delay Measurement ......................................................................................
22-4. Connection of Signals in Bus Monitoring Mode .....................................................................
22-5. Internal Loop Back Mode ...............................................................................................
22-6. External Timestamp Counter Interrupt ...............................................................................
22-7. Standard Message ID Filter Path .....................................................................................
22-8. Extended Message ID Filter Path .....................................................................................
22-9. Rx FIFO Status ..........................................................................................................
22-10. Rx FIFO Overflow Handling ............................................................................................
22-11. Mixed Dedicated Tx Buffers / Tx FIFO (example) ..................................................................
22-12. Mixed Dedicated Tx Buffers / Tx Queue (example) ................................................................
22-13. Message RAM Configuration ..........................................................................................
22-14. Rx Buffer / Rx FIFO Element Structure ..............................................................................
22-15. Tx Buffer Element Structure ...........................................................................................
22-16. Tx Event FIFO Element Structure .....................................................................................
22-17. Standard Message ID Filter Element Structure .....................................................................
22-18. Extended Message ID Filter Element Structure .....................................................................
22-19. MCANSS_PID Register ................................................................................................
22-20. MCANSS_CTRL Register ..............................................................................................
22-21. MCANSS_STAT Register ..............................................................................................
22-22. MCANSS_ICS Register ................................................................................................
22-23. MCANSS_IRS Register ................................................................................................
22-24. MCANSS_IECS Register...............................................................................................
22-25. MCANSS_IE Register ..................................................................................................
22-26. MCANSS_IES Register.................................................................................................
22-27. MCANSS_EOI Register ................................................................................................
22-28. MCANSS_EXT_TS_PS Register......................................................................................
22-29. MCANSS_EXT_TS_USIC Register ...................................................................................
22-30. MCANSS_ECC_EOI Register .........................................................................................
22-31. MCAN_CREL Register .................................................................................................
22-32. MCAN_ENDN Register .................................................................................................
22-33. MCAN_CUST Register .................................................................................................
22-34. MCAN_DBTP Register .................................................................................................
22-35. MCAN_TEST Register..................................................................................................
22-36. MCAN_RWD Register ..................................................................................................
22-37. MCAN_CCCR Register .................................................................................................
22-38. MCAN_NBTP Register .................................................................................................
22-39. MCAN_TSCC Register .................................................................................................
22-40. MCAN_TSCV Register .................................................................................................
22-41. MCAN_TOCC Register .................................................................................................
22-42. MCAN_TOCV Register .................................................................................................
22-43. MCAN_RES00 Register ................................................................................................
22-44. MCAN_RES01 Register ................................................................................................
22-45. MCAN_RES02 Register ................................................................................................
21-138. Reserved_41 Register
62
List of Figures
2572
2573
2574
2576
2580
2584
2585
2586
2589
2590
2595
2596
2597
2598
2601
2602
2604
2604
2606
2608
2609
2611
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
22-46. MCAN_RES03 Register ................................................................................................ 2643
22-47. MCAN_ECR Register ................................................................................................... 2644
22-48. MCAN_PSR Register ................................................................................................... 2645
22-49. MCAN_TDCR Register ................................................................................................. 2646
22-50. MCAN_RES04 Register ................................................................................................ 2647
22-51. MCAN_IR Register ...................................................................................................... 2648
22-52. MCAN_IE Register ...................................................................................................... 2650
....................................................................................................
....................................................................................................
MCAN_RES05 Register ................................................................................................
MCAN_RES06 Register ................................................................................................
MCAN_RES07 Register ................................................................................................
MCAN_RES08 Register ................................................................................................
MCAN_RES09 Register ................................................................................................
MCAN_RES10 Register ................................................................................................
MCAN_RES11 Register ................................................................................................
MCAN_RES12 Register ................................................................................................
MCAN_GFC Register ...................................................................................................
MCAN_SIDFC Register ................................................................................................
MCAN_XIDFC Register ................................................................................................
MCAN_RES13 Register ................................................................................................
MCAN_XIDAM Register ................................................................................................
MCAN_HPMS Register .................................................................................................
MCAN_NDAT1 Register ................................................................................................
MCAN_NDAT2 Register ................................................................................................
MCAN_RXF0C Register ................................................................................................
MCAN_RXF0S Register ................................................................................................
MCAN_RXF0A Register ................................................................................................
MCAN_RXBC Register .................................................................................................
MCAN_RXF1C Register ................................................................................................
MCAN_RXF1S Register ................................................................................................
MCAN_RXF1A Register ................................................................................................
MCAN_RXESC Register ...............................................................................................
MCAN_TXBC Register .................................................................................................
MCAN_TXFQS Register ...............................................................................................
MCAN_TXESC Register ...............................................................................................
MCAN_TXBRP Register ...............................................................................................
MCAN_TXBAR Register ...............................................................................................
MCAN_TXBCR Register ...............................................................................................
MCAN_TXBTO Register ...............................................................................................
MCAN_TXBCF Register ................................................................................................
MCAN_TXBTIE Register ...............................................................................................
MCAN_TXBCIE Register ...............................................................................................
MCAN_RES14 Register ................................................................................................
MCAN_RES15 Register ................................................................................................
MCAN_TXEFC Register ................................................................................................
MCAN_TXEFS Register ................................................................................................
MCAN_TXEFA Register ................................................................................................
MCAN_RES16 Register ................................................................................................
22-53. MCAN_ILS Register
2652
22-54. MCAN_ILE Register
2654
22-55.
2655
22-56.
22-57.
22-58.
22-59.
22-60.
22-61.
22-62.
22-63.
22-64.
22-65.
22-66.
22-67.
22-68.
22-69.
22-70.
22-71.
22-72.
22-73.
22-74.
22-75.
22-76.
22-77.
22-78.
22-79.
22-80.
22-81.
22-82.
22-83.
22-84.
22-85.
22-86.
22-87.
22-88.
22-89.
22-90.
22-91.
22-92.
22-93.
22-94.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
63
www.ti.com
.......................................................................
22-96. MCANSS_ECC_VECTOR Register ..................................................................................
22-97. MCANSS_ECC_MISC_STATUS Register ...........................................................................
22-98. MCANSS_ECC_WRAP_REVISION Register .......................................................................
22-99. MCANSS_ECC_CONTROL Register ................................................................................
22-100. MCANSS_ECC_ERR_CTRL1 Register.............................................................................
22-101. MCANSS_ECC_ERR_CTRL2 Register.............................................................................
22-102. MCANSS_ECC_ERR_STAT1 Register .............................................................................
22-103. MCANSS_ECC_ERR_STAT2 Register .............................................................................
22-104. MCANSS_ECC_SEC_EOI_REG Register .........................................................................
22-105. MCANSS_ECC_SEC_STATUS_REG0 Register ..................................................................
22-106. MCANSS_ECC_SEC_ENABLE_SET_REG0 Register ...........................................................
22-107. MCANSS_ECC_SEC_ENABLE_CLR_REG0 Register ...........................................................
22-108. MCANSS_ECC_DED_EOI_REG Register .........................................................................
22-109. MCANSS_ECC_DED_STATUS_REG0 Register ..................................................................
22-110. MCANSS_ECC_DED_ENABLE_SET_REG0 Register ...........................................................
22-111. MCANSS_ECC_DED_ENABLE_CLR_REG0 Register ...........................................................
22-112. MCAN Block Diagram .................................................................................................
22-113. CAN Bit Timing .........................................................................................................
22-114. Transmitter Delay Measurement .....................................................................................
22-115. Connection of Signals in Bus Monitoring Mode ....................................................................
22-116. Internal Loop Back Mode .............................................................................................
22-117. External Timestamp Counter Interrupt ..............................................................................
22-118. Standard Message ID Filter Path ....................................................................................
22-119. Extended Message ID Filter Path....................................................................................
22-120. Rx FIFO Status .........................................................................................................
22-121. Rx FIFO Overflow Handling ..........................................................................................
22-122. Mixed Dedicated Tx Buffers / Tx FIFO (example) .................................................................
22-123. Mixed Dedicated Tx Buffers / Tx Queue (example) ...............................................................
22-124. Message RAM Configuration .........................................................................................
22-125. Rx Buffer / Rx FIFO Element Structure .............................................................................
22-126. Tx Buffer Element Structure ..........................................................................................
22-127. Tx Event FIFO Element Structure ...................................................................................
22-128. Standard Message ID Filter Element Structure ....................................................................
22-129. Extended Message ID Filter Element Structure ...................................................................
22-130. SS_PID Register .......................................................................................................
22-131. SS_CTRL Register ....................................................................................................
22-132. SS_STAT Register.....................................................................................................
22-133. SS_ICS Register .......................................................................................................
22-134. SS_IRS Register .......................................................................................................
22-135. SS_IECS Register .....................................................................................................
22-136. SS_IE Register .........................................................................................................
22-137. SS_IES Register .......................................................................................................
22-138. SS_EOI Register .......................................................................................................
22-139. SS_EXT_TS_PS Register ............................................................................................
22-140. SS_EXT_TS_USIC Register .........................................................................................
22-141. CREL Register .........................................................................................................
22-142. ENDN Register .........................................................................................................
22-143. CUST Register .........................................................................................................
22-95. MCANSS_ECC_AGGR_REVISION Register
64
List of Figures
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2714
2718
2719
2720
2723
2724
2729
2730
2731
2732
2735
2736
2738
2738
2740
2742
2743
2745
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
.........................................................................................................
TEST Register ..........................................................................................................
RWD Register ..........................................................................................................
CCCR Register .........................................................................................................
NBTP Register .........................................................................................................
TSCC Register .........................................................................................................
TSCV Register .........................................................................................................
TOCC Register .........................................................................................................
TOCV Register .........................................................................................................
RES00 Register ........................................................................................................
RES01 Register ........................................................................................................
RES02 Register ........................................................................................................
RES03 Register ........................................................................................................
ECR Register ...........................................................................................................
PSR Register ...........................................................................................................
TDCR Register .........................................................................................................
RES04 Register ........................................................................................................
IR Register ..............................................................................................................
IE Register ..............................................................................................................
ILS Register ............................................................................................................
ILE Register ............................................................................................................
RES05 Register ........................................................................................................
RES06 Register ........................................................................................................
RES07 Register ........................................................................................................
RES08 Register ........................................................................................................
RES09 Register ........................................................................................................
RES10 Register ........................................................................................................
RES11 Register ........................................................................................................
RES12 Register ........................................................................................................
GFC Register ...........................................................................................................
SIDFC Register ........................................................................................................
XIDFC Register ........................................................................................................
RES13 Register ........................................................................................................
XIDAM Register ........................................................................................................
HPMS Register .........................................................................................................
NDAT1 Register ........................................................................................................
NDAT2 Register ........................................................................................................
RXF0C Register ........................................................................................................
RXF0S Register ........................................................................................................
RXF0A Register ........................................................................................................
RXBC Register .........................................................................................................
RXF1C Register ........................................................................................................
RXF1S Register ........................................................................................................
RXF1A Register ........................................................................................................
RXESC Register .......................................................................................................
TXBC Register .........................................................................................................
TXFQS Register........................................................................................................
TXESC Register........................................................................................................
TXBRP Register........................................................................................................
22-144. DBTP Register
22-145.
22-146.
22-147.
22-148.
22-149.
22-150.
22-151.
22-152.
22-153.
22-154.
22-155.
22-156.
22-157.
22-158.
22-159.
22-160.
22-161.
22-162.
22-163.
22-164.
22-165.
22-166.
22-167.
22-168.
22-169.
22-170.
22-171.
22-172.
22-173.
22-174.
22-175.
22-176.
22-177.
22-178.
22-179.
22-180.
22-181.
22-182.
22-183.
22-184.
22-185.
22-186.
22-187.
22-188.
22-189.
22-190.
22-191.
22-192.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2783
2785
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
65
www.ti.com
22-193. TXBAR Register........................................................................................................ 2816
22-194. TXBCR Register
.......................................................................................................
2817
22-195. TXBTO Register........................................................................................................ 2818
22-196. TXBCF Register ........................................................................................................ 2819
22-197. TXBTIE Register ....................................................................................................... 2820
22-198. TXBCIE Register ....................................................................................................... 2821
22-199. RES14 Register ........................................................................................................ 2822
22-200. RES15 Register ........................................................................................................ 2823
22-201. TXEFC Register ........................................................................................................ 2824
22-202. TXEFS Register ........................................................................................................ 2825
22-203. TXEFA Register ........................................................................................................ 2826
22-204. RES16 Register ........................................................................................................ 2827
22-205. REV Register ........................................................................................................... 2829
22-206. VECTOR Register ..................................................................................................... 2830
22-207. STAT Register .......................................................................................................... 2831
.........................................................................................................
22-209. ERR_CTRL1 Register .................................................................................................
22-210. ERR_CTRL2 Register .................................................................................................
22-211. ERR_STAT1 Register .................................................................................................
22-212. ERR_STAT2 Register .................................................................................................
22-213. ERR_STAT3 Register .................................................................................................
22-214. SEC_EOI_REG Register .............................................................................................
22-215. SEC_STATUS_REG0 Register ......................................................................................
22-216. SEC_ENABLE_SET_REG0 Register ...............................................................................
22-217. SEC_ENABLE_CLR_REG0 Register ...............................................................................
22-218. DED_EOI_REG Register .............................................................................................
22-219. DED_STATUS_REG0 Register ......................................................................................
22-220. DED_ENABLE_SET_REG0 Register ...............................................................................
22-221. DED_ENABLE_CLR_REG0 Register ...............................................................................
22-222. AGGR_ENABLE_SET Register ......................................................................................
22-223. AGGR_ENABLE_CLR Register......................................................................................
22-224. AGGR_STATUS_SET Register ......................................................................................
22-225. AGGR_STATUS_CLR Register......................................................................................
23-1. SPI Functional Logic Diagram .........................................................................................
23-2. MibSPI Functional Logic Diagram.....................................................................................
23-3. DMA Channel and Request Line (Logical) Structure in Multi-buffer Mode ......................................
23-4. TG Interrupt Structure ..................................................................................................
23-5. SPIFLG Interrupt Structure.............................................................................................
23-6. SPI Three-Pin Operation ..............................................................................................
23-7. Operation with SPISCS .................................................................................................
23-8. Operation with SPIENA .................................................................................................
23-9. SPI Five-Pin Option with SPIENA and SPISCS .....................................................................
23-10. Format for Transmitting an 12-Bit Word ..............................................................................
23-11. Format for Receiving an 10-Bit Word .................................................................................
23-12. Clock Mode with Polarity = 0 and Phase = 0 ........................................................................
23-13. Clock Mode with Polarity = 0 and Phase = 1 ........................................................................
23-14. Clock Mode with Polarity = 1 and Phase = 0 ........................................................................
23-15. Clock Mode with Polarity = 1 and Phase = 1 ........................................................................
23-16. Five Bits per Character (5-Pin Option) ...............................................................................
22-208. CTRL Register
66
List of Figures
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2854
2855
2857
2859
2859
2860
2861
2862
2863
2864
2864
2865
2865
2866
2866
2867
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
= 8 VCLK Cycles ................................................................................... 2868
23-17. Example: t
C2TDELAY
23-18. Example: t
T2CDELAY
= 4 VCLK Cycles ................................................................................... 2869
23-19. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................. 2869
23-20. Chip-Select-Active-to-ENA-Signal-Active-Timeout .................................................................. 2870
23-21. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI) ...................................... 2871
23-22. Block Diagram Shift Register, MSB First ............................................................................. 2873
23-23. Block Diagram Shift Register, LSB First
.............................................................................
2873
23-24. 2-data Line Mode (Phase 0, Polarity 0) .............................................................................. 2876
23-25. Two-Pin Parallel Mode Timing Diagram (Phase 0, Polarity 0) .................................................... 2876
23-26. 4-Data Line Mode (Phase 0, Polarity 0) .............................................................................. 2877
23-27. 4 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0)....................................................... 2877
23-28. Eight-data Line Mode (Phase 0, Polarity 0).......................................................................... 2878
23-29. 8 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0)....................................................... 2879
23-30. Multi-buffer in Slave Mode ............................................................................................. 2880
23-31. I/O Paths During I/O Loopback Modes ............................................................................... 2885
23-32. SPIGCR0 Register ...................................................................................................... 2892
23-33. SPIGCR1 Register ...................................................................................................... 2893
23-34. SPIINT0 Register ........................................................................................................ 2895
23-35. SPILVL Register ......................................................................................................... 2897
........................................................................................................
........................................................................................................
SPIPC1 Register ........................................................................................................
SPIPC2 Register ........................................................................................................
SPIPC3 Register ........................................................................................................
SPIPC4 Register ........................................................................................................
SPIPC5 Register ........................................................................................................
SPIPC6 Register ........................................................................................................
SPIDAT0 Register .......................................................................................................
SPIDAT1 Register .......................................................................................................
SPIBUF Register ........................................................................................................
SPIEMU Register........................................................................................................
SPIDELAY Register .....................................................................................................
SPIDEF Register ........................................................................................................
SPIFMT0 Register.......................................................................................................
SPIFMT1 Register.......................................................................................................
SPIFMT2 Register.......................................................................................................
SPIFMT3 Register.......................................................................................................
TGINTVECT0 Register .................................................................................................
TGINTVECT1 Register .................................................................................................
SPIPC9 Register ........................................................................................................
SPIPMCTRL Register ..................................................................................................
MIBSPIE Register .......................................................................................................
TGITENST Register.....................................................................................................
TGITENCR Register ....................................................................................................
TGITLVST Register .....................................................................................................
TGITLVCR Register.....................................................................................................
TGINTFLAG Register ...................................................................................................
TICKCNT Register ......................................................................................................
LTGPEND Register .....................................................................................................
23-36. SPIFLG Register
2898
23-37. SPIPC0 Register
2901
23-38.
2903
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
23-45.
23-46.
23-47.
23-48.
23-49.
23-50.
23-51.
23-52.
23-53.
23-54.
23-55.
23-56.
23-57.
23-58.
23-59.
23-60.
23-61.
23-62.
23-63.
23-64.
23-65.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2905
2906
2908
2910
2912
2914
2915
2917
2920
2922
2924
2925
2927
2929
2931
2933
2935
2937
2938
2941
2943
2944
2945
2946
2947
2948
2949
67
www.ti.com
23-66. TG0CTRL Register ...................................................................................................... 2950
23-67. TG1CTRL Register ...................................................................................................... 2953
23-68. TG2CTRL Register ...................................................................................................... 2956
23-69. TG3CTRL Register ...................................................................................................... 2959
23-70. TG4CTRL Register ...................................................................................................... 2962
23-71. TG5CTRL Register ...................................................................................................... 2965
23-72. TG6CTRL Register ...................................................................................................... 2968
23-73. TG7CTRL Register ...................................................................................................... 2971
...................................................................................................
23-75. DMA1CTRL Register ...................................................................................................
23-76. DMA2CTRL Register ...................................................................................................
23-77. DMA3CTRL Register ...................................................................................................
23-78. DMA4CTRL Register ...................................................................................................
23-79. ICOUNT0 Register ......................................................................................................
23-80. ICOUNT1 Register ......................................................................................................
23-81. ICOUNT2 Register ......................................................................................................
23-82. ICOUNT3 Register ......................................................................................................
23-83. ICOUNT4 Register ......................................................................................................
23-84. DMACNTLEN Register .................................................................................................
23-85. PAR_ECC_CTRL Register .............................................................................................
23-86. PAR_ECC_STAT Register .............................................................................................
23-87. UERRADDR1 Register .................................................................................................
23-88. UERRADDR0 Register .................................................................................................
23-89. RXOVRN_BUF_ADDR Register ......................................................................................
23-90. IOLPBKTSTCR Register ...............................................................................................
23-91. EXTENDED_PRESCALE1 Register ..................................................................................
23-92. EXTENDED_PRESCALE2 Register ..................................................................................
23-93. ECCDIAG_CTRL Register .............................................................................................
23-94. ECCDIAG_STAT Register .............................................................................................
23-95. SBERRADDR1 Register ...............................................................................................
23-96. SBERRADDR0 Register ...............................................................................................
23-97. SPIREV Register ........................................................................................................
23-98. SPIGCR0 Register ......................................................................................................
23-99. SPIGCR1 Register ......................................................................................................
23-100. SPIINT0 Register ......................................................................................................
23-101. SPILVL Register .......................................................................................................
23-102. SPIFLG Register .......................................................................................................
23-103. SPIPC0 Register .......................................................................................................
23-104. SPIPC1 Register .......................................................................................................
23-105. SPIPC2 Register .......................................................................................................
23-106. SPIPC3 Register .......................................................................................................
23-107. SPIPC4 Register .......................................................................................................
23-108. SPIPC5 Register .......................................................................................................
23-109. SPIPC6 Register .......................................................................................................
23-110. SPIDAT0 Register .....................................................................................................
23-111. SPIDAT1 Register .....................................................................................................
23-112. SPIBUF Register .......................................................................................................
23-113. SPIEMU Register ......................................................................................................
23-114. SPIDELAY Register ...................................................................................................
23-74. DMA0CTRL Register
68
List of Figures
2974
2976
2978
2980
2982
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2997
2999
3000
3001
3002
3003
3004
3008
3009
3011
3013
3014
3017
3019
3021
3022
3024
3026
3028
3030
3031
3033
3036
3038
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
23-115. SPIDEF Register ....................................................................................................... 3040
23-116. SPIFMT0 Register ..................................................................................................... 3041
23-117. SPIFMT1 Register ..................................................................................................... 3043
23-118. SPIFMT2 Register ..................................................................................................... 3045
23-119. SPIFMT3 Register ..................................................................................................... 3047
23-120. TGINTVECT0 Register ................................................................................................ 3049
23-121. TGINTVECT1 Register ................................................................................................ 3051
23-122. SPIPC9 Register ....................................................................................................... 3053
23-123. SPIPMCTRL Register ................................................................................................. 3054
23-124. MIBSPIE Register...................................................................................................... 3057
23-125. TGITENST Register ................................................................................................... 3059
23-126. TGITENCR Register ................................................................................................... 3060
23-127. TGITLVST Register .................................................................................................... 3061
23-128. TGITLVCR Register ................................................................................................... 3062
23-129. TGINTFLAG Register
.................................................................................................
3063
23-130. TICKCNT Register ..................................................................................................... 3064
23-131. LTGPEND Register .................................................................................................... 3065
23-132. TG0CTRL Register .................................................................................................... 3066
23-133. TG1CTRL Register .................................................................................................... 3069
23-134. TG2CTRL Register .................................................................................................... 3072
23-135. TG3CTRL Register .................................................................................................... 3075
23-136. TG4CTRL Register .................................................................................................... 3078
23-137. TG5CTRL Register .................................................................................................... 3081
23-138. TG6CTRL Register .................................................................................................... 3084
23-139. TG7CTRL Register .................................................................................................... 3087
23-140. DMA0CTRL Register .................................................................................................. 3090
23-141. DMA1CTRL Register .................................................................................................. 3092
23-142. DMA2CTRL Register .................................................................................................. 3094
23-143. DMA3CTRL Register .................................................................................................. 3096
23-144. DMA4CTRL Register .................................................................................................. 3098
23-145. ICOUNT0 Register ..................................................................................................... 3100
23-146. ICOUNT1 Register ..................................................................................................... 3101
23-147. ICOUNT2 Register ..................................................................................................... 3102
23-148. ICOUNT3 Register ..................................................................................................... 3103
23-149. ICOUNT4 Register ..................................................................................................... 3104
23-150. DMACNTLEN Register ................................................................................................ 3105
23-151. PAR_ECC_CTRL Register ........................................................................................... 3106
23-152. PAR_ECC_STAT Register
...........................................................................................
3107
23-153. UERRADDR1 Register ................................................................................................ 3108
23-154. UERRADDR0 Register ................................................................................................ 3109
23-155. RXOVRN_BUF_ADDR Register ..................................................................................... 3110
23-156. IOLPBKTSTCR Register .............................................................................................. 3111
................................................................................
................................................................................
ECCDIAG_CTRL Register ............................................................................................
ECCDIAG_STAT Register ............................................................................................
SBERRADDR1 Register ..............................................................................................
SBERRADDR0 Register ..............................................................................................
SPIREV Register .......................................................................................................
23-157. EXTENDED_PRESCALE1 Register
3113
23-158. EXTENDED_PRESCALE2 Register
3115
23-159.
3116
23-160.
23-161.
23-162.
23-163.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
3117
3118
3119
3120
69
www.ti.com
23-164. Multi-Buffer RAM Configuration When Parity Check is Supported .............................................. 3121
23-165. Multi-Buffer RAM Configuration When ECC Check is Supported ............................................... 3121
23-166. Multi-Buffer RAM Transmit Data Register [offset = Base + 000-1FFh] ......................................... 3123
23-167. Multi-buffer RAM Receive Buffer Register [offset = RAM Base + 200-3FFh] .................................. 3125
23-168. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Disabled or the Feature is Not Implemented ........................................................................ 3128
23-169. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Enabled ................................................................................................................... 3129
23-170. Example of Memory-Mapped Parity Locations During Test Mode .............................................. 3130
23-171. Example of ECC Bit Locations During Test Mode ................................................................. 3131
23-172. SPI/MibSPI Pins During Master Mode 3-Pin Configuration ...................................................... 3132
23-173. SPI/MibSPI Pins During Master Mode 4-Pin with SPISCS Configuation ....................................... 3132
23-174. SPI/MibSPI Pins During Master Mode in 4-Pin with SPIENA Configuration ................................... 3133
23-175. SPI/MibSPI Pins During Master/Slave Mode with 5-Pin Configuration ......................................... 3133
23-176. SPI/MibSPI Pins During Slave Mode 3-Pin Configuration ........................................................ 3134
....................................
23-178. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single Slave) ...................................
23-179. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single/Multi-Slave) .............................
24-1. QSPI Overview ..........................................................................................................
24-2. QSPI Block Diagram ....................................................................................................
24-3. SPI_CLKGEN Block ....................................................................................................
24-4. SPI Clock Modes ........................................................................................................
24-5. Logical Representation of the QSPI Interrupt Generation Scheme...............................................
24-6. PID Register .............................................................................................................
24-7. SYSCONFIG Register ..................................................................................................
24-8. INTR_STATUS_RAW_SET Register .................................................................................
24-9. INTR_STATUS_ENABLED_CLEAR Register .......................................................................
24-10. INTR_ENABLE_SET Register .........................................................................................
24-11. INTR_ENABLE_CLEAR Register .....................................................................................
24-12. INTC_EOI Register .....................................................................................................
24-13. SPI_CLOCK_CNTRL Register ........................................................................................
24-14. SPI_DC Register ........................................................................................................
24-15. SPI_CMD Register ......................................................................................................
24-16. SPI_STATUS Register .................................................................................................
24-17. SPI_DATA Register .....................................................................................................
24-18. SPI_SETUP0 Register..................................................................................................
24-19. SPI_SETUP1 Register..................................................................................................
24-20. SPI_SETUP2 Register..................................................................................................
24-21. SPI_SETUP3 Register..................................................................................................
24-22. SPI_SWITCH Register .................................................................................................
24-23. SPI_DATA1 Register ...................................................................................................
24-24. SPI_DATA2 Register ...................................................................................................
24-25. SPI_DATA3 Register ...................................................................................................
25-1. Multiple I2C Modules Connection Diagram ..........................................................................
25-2. Simple I2C Block Diagram .............................................................................................
25-3. Clocking Diagram for the I2C Module ................................................................................
25-4. Bit Transfer on the I2C Bus ............................................................................................
25-5. I2C Module START and STOP Conditions ..........................................................................
25-6. I2C Module Data Transfer..............................................................................................
23-177. SPI/MibSPI Pins During Slave Mode in 4-Pin with SPIENA Configuration
70
List of Figures
3134
3134
3134
3137
3138
3142
3143
3144
3148
3149
3150
3151
3152
3153
3154
3155
3156
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3170
3172
3173
3174
3175
3175
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
25-7.
I2C Module 7-Bit Addressing Format ................................................................................. 3176
25-8.
I2C Module 10-bit Addressing Format ................................................................................ 3176
25-9.
I2C Module 7-Bit Addressing Format with Repeated START ..................................................... 3176
25-10. I2C Module in Free Data Format ...................................................................................... 3177
25-11. Arbitration Procedure Between Two Master Transmitters ......................................................... 3180
25-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................ 3181
25-13. ICOAR Register
.........................................................................................................
3186
25-14. ICIMR Register .......................................................................................................... 3187
25-15. ICSTR Register .......................................................................................................... 3188
25-16. ICCLKL Register
........................................................................................................
3190
25-17. ICCLKH Register ........................................................................................................ 3191
25-18. ICCNT Register .......................................................................................................... 3192
25-19. ICDRR Register
.........................................................................................................
3193
25-20. ICSAR Register .......................................................................................................... 3194
25-21. ICDXR Register.......................................................................................................... 3195
25-22. ICMDR Register ......................................................................................................... 3196
25-23. ICIVR Register ........................................................................................................... 3199
25-24. ICEMDR Register ....................................................................................................... 3200
25-25. ICPSC Register .......................................................................................................... 3201
25-26. ICPID1 Register ......................................................................................................... 3202
25-27. ICPID2 Register ......................................................................................................... 3203
25-28. ICDMAC Register ....................................................................................................... 3204
25-29. ICPFUNC Register ...................................................................................................... 3205
25-30. ICPDIR Register ......................................................................................................... 3206
25-31. ICPDIN Register ......................................................................................................... 3207
25-32. ICPDOUT Register ...................................................................................................... 3208
25-33. ICPDSET Register ...................................................................................................... 3209
25-34. ICPDCLR Register ...................................................................................................... 3210
25-35. ICPDRV Register ........................................................................................................ 3211
25-36. Difference between Normal Operation and Backward Compatibility Mode...................................... 3212
26-1.
Detailed SCI Block Diagram ........................................................................................... 3215
26-2.
Typical SCI Data Frame Formats ..................................................................................... 3216
26-3.
Asynchronous Communication Bit Timing ........................................................................... 3217
26-4.
Idle-Line Multiprocessor Communication Format ................................................................... 3219
26-5.
Address-Bit Multiprocessor Communication Format................................................................ 3220
26-6.
General Interrupt Scheme .............................................................................................. 3221
26-7.
Interrupt Generation for Given Flags
26-8.
SCI Global Control Register 0 (SCIGCR0) [offset = 00] ........................................................... 3230
26-9.
SCI Global Control Register 1 (SCIGCR1) [offset = 04h] .......................................................... 3231
.................................................................................
3222
26-10. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] ............................................................ 3234
26-11. SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] ...................................................... 3236
26-12. SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h]
................................................
3238
26-13. SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h] .......................................... 3239
26-14. SCI Flags Register (SCIFLR) [offset = 1Ch] ......................................................................... 3241
26-15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h] ...................................................... 3245
26-16. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h] ...................................................... 3245
26-17. SCI Format Control Register (SCIFORMAT) [offset = 28h]
.......................................................
3246
26-18. Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................ 3247
26-19. Receiver Emulation Data Buffer (SCIED) [offset = 30h]
...........................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
3248
71
www.ti.com
26-20. Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................ 3248
26-21. Transmit Data Buffer Register (SCITD) [offset = 38h] .............................................................. 3249
26-22. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch]
.........................................................
3249
26-23. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h] ........................................................... 3250
26-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h]
..........................................................
3251
26-25. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h] ........................................................... 3252
26-26. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch]
.........................................................
3253
26-27. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h] ........................................................... 3254
3255
26-29.
3256
26-30.
26-31.
26-32.
27-1.
27-2.
27-3.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
28-25.
28-26.
28-27.
28-28.
28-29.
28-30.
28-31.
28-32.
28-33.
72
..........................................................
SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h] ...........................................................
SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] .........................................................
Input/Output Error Enable Register (IODFTCTRL) [offset = 90h] .................................................
GPIO Functionality ......................................................................................................
Block Diagram of the 14xx Debug Subsystem Interconnect ......................................................
Block Diagram of the 16xx/18xx/68xx Debug Subsystem Interconnect..........................................
16xx/18xx/68xx Cross Trigger Subsystem ..........................................................................
DCC Operation ..........................................................................................................
Counter Relationship....................................................................................................
Clock1 Slower Than Clock0 - Results in an Error and Stops Counting ..........................................
Clock1 Faster Than Clock0 - Results in an Error and Stops Counting ..........................................
Clock1 Not Present - Results in an Error and Stops Counting ....................................................
Clock0 Not Present - Results in an Error and Stops Counting ....................................................
DCCGCTRL Register ...................................................................................................
DCCREV Register.......................................................................................................
DCCCNTSEED0 Register ..............................................................................................
DCCVALIDSEED0 Register ...........................................................................................
DCCCNTSEED1 Register ..............................................................................................
DCCSTAT Register .....................................................................................................
DCCCNT0 Register .....................................................................................................
DCCVALID0 Register ...................................................................................................
DCCCNT1 Register .....................................................................................................
DCCCLKSSRC1 Register ..............................................................................................
DCCCLKSSRC0 Register ..............................................................................................
Block Diagram ...........................................................................................................
Interrupt Response Handling ..........................................................................................
ERROR Pin Response Handling ......................................................................................
ERROR Pin Timing - Example 1 ......................................................................................
ERROR Pin Timing - Example 2 ......................................................................................
ERROR Pin Timing - Example 3 ......................................................................................
ERROR Pin Timing - Example 4 ......................................................................................
ERROR Pin Timing - Example 5 ......................................................................................
ERROR Pin Timing - Example 6 ......................................................................................
ESM Initialization ........................................................................................................
ESMIEPSR1 Register ..................................................................................................
ESMIEPCR1 Register ..................................................................................................
ESMIESR1 Register ....................................................................................................
ESMIECR1 Register ....................................................................................................
ESMILSR1 Register.....................................................................................................
ESMILCR1 Register ....................................................................................................
26-28. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h]
List of Figures
3256
3257
3259
3261
3262
3263
3265
3267
3267
3268
3268
3269
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3284
3286
3286
3286
3287
3287
3287
3288
3290
3291
3292
3293
3294
3295
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
28-34. ESMSR1 Register ....................................................................................................... 3296
28-35. ESMSR2 Register ....................................................................................................... 3297
28-36. ESMSR3 Register ....................................................................................................... 3298
28-37. ESMEPSR Register ..................................................................................................... 3299
28-38. ESMIOFFHR Register .................................................................................................. 3300
..................................................................................................
ESMLTCR Register .....................................................................................................
ESMLTCPR Register ...................................................................................................
ESMEKR Register.......................................................................................................
ESMSSR2 Register .....................................................................................................
ESMIEPSR4 Register ..................................................................................................
ESMIEPCR4 Register ..................................................................................................
ESMIESR4 Register ....................................................................................................
ESMIECR4 Register ....................................................................................................
ESMILSR4 Register.....................................................................................................
ESMILCR4 Register ....................................................................................................
ESMSR4 Register .......................................................................................................
ESMIEPSR7 Register ..................................................................................................
ESMIEPCR7 Register ..................................................................................................
ESMIESR7 Register ....................................................................................................
ESMIECR7 Register ....................................................................................................
ESMILSR7 Register.....................................................................................................
ESMILCR7 Register ....................................................................................................
ESMSR7 Register .......................................................................................................
CRC Controller Block Diagram For One Channel ..................................................................
Linear Feedback Shift Register (LFSR) ..............................................................................
AUTO Mode Using Hardware Timer Trigger ........................................................................
AUTO Mode With Software CPU Trigger ............................................................................
Semi-CPU Mode With Hardware Timer Trigger .....................................................................
Timeout Example 1 .....................................................................................................
Timeout Example 2 .....................................................................................................
Timeout Example 3 .....................................................................................................
DCCGCTRL Register ...................................................................................................
DCCREV Register.......................................................................................................
DCCCNTSEED0 Register ..............................................................................................
DCCVALIDSEED0 Register ...........................................................................................
DCCCNTSEED1 Register ..............................................................................................
DCCSTAT Register .....................................................................................................
DCCCNT0 Register .....................................................................................................
DCCVALID0 Register ...................................................................................................
DCCCNT1 Register .....................................................................................................
DCCCLKSSRC1 Register ..............................................................................................
DCCCLKSSRC0 Register ..............................................................................................
PBIST Block Diagram...................................................................................................
PBIST_DLR Register ...................................................................................................
PBIST_PACT Register .................................................................................................
PBIST_ID Register ......................................................................................................
PBIST_OVR Register ...................................................................................................
PBIST_FSFR0 Register ................................................................................................
28-39. ESMIOFFLR Register
3301
28-40.
3302
28-41.
28-42.
28-43.
28-44.
28-45.
28-46.
28-47.
28-48.
28-49.
28-50.
28-51.
28-52.
28-53.
28-54.
28-55.
28-56.
28-57.
28-58.
28-59.
28-60.
28-61.
28-62.
28-63.
28-64.
28-65.
28-66.
28-67.
28-68.
28-69.
28-70.
28-71.
28-72.
28-73.
28-74.
28-75.
28-76.
28-77.
28-78.
28-79.
28-80.
28-81.
28-82.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3322
3325
3325
3326
3328
3329
3329
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3348
3352
3353
3354
3355
3356
73
www.ti.com
28-83. PBIST_FSFR1 Register ................................................................................................ 3357
28-84. PBIST_FSRCR0 Register .............................................................................................. 3358
28-85. PBIST_FSRCR1 Register .............................................................................................. 3359
..................................................................................................
28-87. PBIST_ALGO Register .................................................................................................
28-88. PBIST_RINFOL Register ...............................................................................................
28-89. PBIST_RINFOU Register ..............................................................................................
28-90. OPMISR Conceptual Diagram .........................................................................................
28-91. Block Diagram for STC With Multiple Segments ....................................................................
28-92. STC Flow (1 of 2) .......................................................................................................
28-93. STC Flow (2 of 2) .......................................................................................................
28-94. STCGCR0 Register .....................................................................................................
28-95. STCGCR1 Register .....................................................................................................
28-96. STCTPR Register .......................................................................................................
28-97. STC_CADDR Register .................................................................................................
28-98. STCCICR Register ......................................................................................................
28-99. STCGSTAT Register....................................................................................................
28-100. STCFSTAT Register ...................................................................................................
28-101. STCSCSCR Register ..................................................................................................
28-102. STC_CADDR2 Register...............................................................................................
28-103. STC_CLKDIV Register ................................................................................................
28-104. STC_SEGPLR Register ...............................................................................................
28-105. SEG0_START_ADDR Register ......................................................................................
28-106. SEG1_START_ADDR Register ......................................................................................
28-107. SEG2_START_ADDR Register ......................................................................................
28-108. SEG3_START_ADDR Register ......................................................................................
28-109. CORE1_CURMISR_0 Register ......................................................................................
28-110. CORE1_CURMISR_1 Register ......................................................................................
28-111. CORE1_CURMISR_2 Register ......................................................................................
28-112. CORE1_CURMISR_3 Register ......................................................................................
28-113. CORE1_CURMISR_4 Register ......................................................................................
28-114. CORE1_CURMISR_5 Register ......................................................................................
28-115. CORE1_CURMISR_6 Register ......................................................................................
28-116. CORE1_CURMISR_7 Register ......................................................................................
28-117. CORE1_CURMISR_8 Register ......................................................................................
28-118. CORE1_CURMISR_9 Register ......................................................................................
28-119. CORE1_CURMISR_10 Register .....................................................................................
28-120. CORE1_CURMISR_11 Register .....................................................................................
28-121. CORE1_CURMISR_12 Register .....................................................................................
28-122. CORE1_CURMISR_13 Register .....................................................................................
28-123. CORE1_CURMISR_14 Register .....................................................................................
28-124. CORE1_CURMISR_15 Register .....................................................................................
28-125. CORE1_CURMISR_16 Register .....................................................................................
28-126. CORE1_CURMISR_17 Register .....................................................................................
28-127. CORE1_CURMISR_18 Register .....................................................................................
28-128. CORE1_CURMISR_19 Register .....................................................................................
28-129. CORE1_CURMISR_20 Register .....................................................................................
28-130. CORE1_CURMISR_21 Register .....................................................................................
28-131. CORE1_CURMISR_22 Register .....................................................................................
28-86. PBIST_ROM Register
74
List of Figures
3360
3361
3362
3363
3365
3366
3368
3369
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
28-132. CORE1_CURMISR_23 Register ..................................................................................... 3416
28-133. CORE1_CURMISR_24 Register ..................................................................................... 3417
28-134. CORE1_CURMISR_25 Register ..................................................................................... 3418
28-135. CORE1_CURMISR_26 Register ..................................................................................... 3419
28-136. CORE1_CURMISR_27 Register ..................................................................................... 3420
28-137. CORE2_CURMISR_0 Register ...................................................................................... 3421
28-138. CORE2_CURMISR_1 Register ...................................................................................... 3422
28-139. CORE2_CURMISR_2 Register ...................................................................................... 3423
28-140. CORE2_CURMISR_3 Register ...................................................................................... 3424
28-141. CORE2_CURMISR_4 Register ...................................................................................... 3425
28-142. CORE2_CURMISR_5 Register ...................................................................................... 3426
28-143. CORE2_CURMISR_6 Register ...................................................................................... 3427
28-144. CORE2_CURMISR_7 Register ...................................................................................... 3428
28-145. CORE2_CURMISR_8 Register ...................................................................................... 3429
28-146. CORE2_CURMISR_9 Register ...................................................................................... 3430
28-147. CORE2_CURMISR_10 Register ..................................................................................... 3431
28-148. CORE2_CURMISR_11 Register ..................................................................................... 3432
28-149. CORE2_CURMISR_12 Register ..................................................................................... 3433
28-150. CORE2_CURMISR_13 Register ..................................................................................... 3434
28-151. CORE2_CURMISR_14 Register ..................................................................................... 3435
28-152. CORE2_CURMISR_15 Register ..................................................................................... 3436
28-153. CORE2_CURMISR_16 Register ..................................................................................... 3437
28-154. CORE2_CURMISR_17 Register ..................................................................................... 3438
28-155. CORE2_CURMISR_18 Register ..................................................................................... 3439
28-156. CORE2_CURMISR_19 Register ..................................................................................... 3440
28-157. CORE2_CURMISR_20 Register ..................................................................................... 3441
28-158. CORE2_CURMISR_21 Register ..................................................................................... 3442
28-159. CORE2_CURMISR_22 Register ..................................................................................... 3443
28-160. CORE2_CURMISR_23 Register ..................................................................................... 3444
28-161. CORE2_CURMISR_24 Register ..................................................................................... 3445
28-162. CORE2_CURMISR_25 Register ..................................................................................... 3446
28-163. CORE2_CURMISR_26 Register ..................................................................................... 3447
28-164. CORE2_CURMISR_27 Register ..................................................................................... 3448
28-165. Core Clock Comparator Module ..................................................................................... 3448
28-166. Block Diagram .......................................................................................................... 3449
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
75
www.ti.com
List of Tables
1-1.
14xx Acronyms ............................................................................................................ 133
1-2.
Master Subsystem, Cortex-R4F Memory Map ........................................................................ 137
1-3.
EDMA-TPTC Memory Map .............................................................................................. 139
1-4.
Example Configurations.................................................................................................. 140
1-5.
MSS_CCCA and MSS_CCCB Integration Connections ............................................................. 141
1-6.
MSS_DCCA Clock Source Selection Table ........................................................................... 142
1-7.
MSS_DCCB Clock Source Selection Table ........................................................................... 142
1-8.
MSS_DMA Request Map ................................................................................................ 144
1-9.
Interrupt Request Assignments
1-10.
DSS_TPCC Configuration ............................................................................................... 151
1-11.
DSS_TPTC Configuration
1-12.
EDMA Request Map...................................................................................................... 153
1-13.
MSS_ESM Mapping ...................................................................................................... 154
1-14.
14xx High-Speed Interfaces ............................................................................................. 157
2-1.
16xx Acronyms ............................................................................................................ 160
2-2.
Master Subsystem, Cortex-R4F Memory Map ........................................................................ 164
2-3.
DSP C674x Memory Map................................................................................................ 168
2-4.
EDMA-TPTC Memory Map .............................................................................................. 169
2-5.
TCM and Shared Memory Available for Cortex R4F in Master Subsystem....................................... 170
2-6.
MSS_CCCA and MSS_CCCB Integration Connections ............................................................. 171
2-7.
MSS_DCCA Clock Source Selection Table ........................................................................... 173
2-8.
MSS_DCCB Clock Source Selection Table ........................................................................... 173
2-9.
DSP Event Assignment .................................................................................................. 173
2-10.
MSS_DMA Request Map ................................................................................................ 178
2-11.
Interrupt Request Assignments
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
76
........................................................................................
...............................................................................................
........................................................................................
DSS_TPCC Configuration ...............................................................................................
DSS_TPTC Configuration ...............................................................................................
EDMA Request Map......................................................................................................
MSS_ESM Mapping ......................................................................................................
DSS_ESM Mapping ......................................................................................................
16xx High-Speed Interfaces .............................................................................................
18xx Acronyms ............................................................................................................
Master Subsystem, Cortex-R4F Memory Map ........................................................................
DSP C674x Memory Map................................................................................................
EDMA-TPTC Memory Map ..............................................................................................
TCM and Shared Memory Available for Cortex R4F in Master Subsystem.......................................
MSS_CCCA and MSS_CCCB Integration Connections .............................................................
MSS_DCCA Clock Source Selection Table ...........................................................................
MSS_DCCB Clock Source Selection Table ...........................................................................
DSP Event Assignment ..................................................................................................
MSS_DMA Request Map ................................................................................................
Interrupt Request Assignments ........................................................................................
DSS_TPCC Configuration ...............................................................................................
DSS_TPTC Configuration ...............................................................................................
EDMA Request Map......................................................................................................
MSS_ESM Mapping ......................................................................................................
DSS_ESM Mapping ......................................................................................................
List of Tables
146
152
184
189
190
192
196
199
200
201
205
210
212
212
213
215
215
215
220
226
231
232
234
238
241
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
2-34.
18xx High-Speed Interfaces ............................................................................................. 242
3-1.
68xx Acronyms ............................................................................................................ 245
3-2.
Master Subsystem, Cortex-R4F Memory Map ........................................................................ 250
3-3.
DSP C674x Memory Map................................................................................................ 254
3-4.
EDMA-TPTC Memory Map .............................................................................................. 256
3-5.
TCM and Shared Memory Available for Cortex R4F in Master Subsystem....................................... 257
3-6.
MSS_CCCA and MSS_CCCB Integration Connections ............................................................. 258
3-7.
MSS_DCCA Clock Source Selection Table ........................................................................... 259
3-8.
MSS_DCCB Clock Source Selection Table ........................................................................... 259
3-9.
DSP Event Assignment .................................................................................................. 260
3-10.
MSS_DMA Request Map ................................................................................................ 264
3-11.
Interrupt Request Assignments ......................................................................................... 270
3-12.
DSS_TPCC Configuration ............................................................................................... 275
3-13.
DSS_TPTC Configuration
3-14.
3-15.
3-16.
3-17.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
...............................................................................................
EDMA Request Map......................................................................................................
MSS_ESM Mapping ......................................................................................................
DSS_ESM Mapping ......................................................................................................
68xx High-Speed Interfaces .............................................................................................
PRCM Overview ..........................................................................................................
Clock Sources .............................................................................................................
Clock Domains ............................................................................................................
PMIC Registers ...........................................................................................................
Reset Types and Sources ...............................................................................................
Reset Domains ............................................................................................................
Reset Cause Registers ..................................................................................................
Power Domain Status ....................................................................................................
SOP Table .................................................................................................................
Pre-Eclipse View of Master Subsystem Cortex-R4F .................................................................
Post-Eclipse View of Master Subsystem Cortex-R4F ................................................................
Enable ROM Eclipsing ...................................................................................................
MSS_TOPRCM Registers ...............................................................................................
MSS_TOPRCM Access Type Codes ..................................................................................
BSSCTL Register Field Descriptions ...................................................................................
EXTCLKDIV Register Field Descriptions ..............................................................................
EXTCLKSRCSEL Register Field Descriptions ........................................................................
EXTCLKCTL Register Field Descriptions..............................................................................
SOFTSYSRST Register Field Descriptions ...........................................................................
WDRSTEN Register Field Descriptions ...............................................................................
SYSRSTCAUSE Register Field Descriptions .........................................................................
SYSRSTCAUSECLR Register Field Descriptions ....................................................................
MISCCAPT Register Field Descriptions ...............................................................................
DCDCCTL0 Register Field Descriptions ...............................................................................
DCDCCTL1 Register Field Descriptions ...............................................................................
MISCCTL Register Field Descriptions .................................................................................
USERMODEEN Register Field Descriptions ..........................................................................
LVDSPADCTL0 Register Field Descriptions ..........................................................................
LVDSPADCTL1 Register Field Descriptions ..........................................................................
DFTREG0 Register Field Descriptions.................................................................................
DFTREG1 Register Field Descriptions.................................................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
276
278
282
285
286
288
289
290
291
292
292
293
296
297
297
298
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
77
www.ti.com
4-32.
DFTREG2 Register Field Descriptions................................................................................. 318
4-33.
DFTREG3 Register Field Descriptions................................................................................. 319
4-34.
DFTREG4 Register Field Descriptions................................................................................. 320
4-35.
DFTREG5 Register Field Descriptions................................................................................. 321
4-36.
SHMEMINITADDR Register Field Descriptions ...................................................................... 322
4-37.
SHMEMINITECC Register Field Descriptions ........................................................................ 323
4-38.
DSSMEMBANKEN Register Field Descriptions ...................................................................... 324
4-39.
DSSMEMTAB0 Register Field Descriptions........................................................................... 325
4-40.
DSSMEMTAB1 Register Field Descriptions........................................................................... 326
4-41.
TCMAMEMBANK_EN Register Field Descriptions................................................................... 327
4-42.
TCMAMEMTAB0 Register Field Descriptions
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
4-59.
4-60.
4-61.
4-62.
4-63.
4-64.
4-65.
4-66.
4-67.
4-68.
4-69.
4-70.
4-71.
4-72.
4-73.
4-74.
4-75.
4-76.
4-77.
4-78.
4-79.
4-80.
78
........................................................................
TCMAMEMTAB1 Register Field Descriptions ........................................................................
TCMBMEMBANKEN Register Field Descriptions ....................................................................
TCMBMEMTAB0 Register Field Descriptions ........................................................................
TCMBMEM_TAB1 Register Field Descriptions .......................................................................
MEMINITSTART Register Field Descriptions .........................................................................
MEMINITDONE Register Field Descriptions ..........................................................................
MSS_SIGNATURE Register Field Descriptions ......................................................................
MISCCTL1 Register Field Descriptions ................................................................................
USERMODEEN2 Register Field Descriptions ........................................................................
SYSTICK Register Field Descriptions..................................................................................
MSS_RCM Registers.....................................................................................................
MSS_RCM Access Type Codes ........................................................................................
SOFTRST2 Register Field Descriptions ...............................................................................
CLKDIVCTL0 Register Field Descriptions .............................................................................
CLKSRCSEL0 Register Field Descriptions............................................................................
CR4CTL Register Field Descriptions ...................................................................................
CLKGATE Register Field Descriptions.................................................................................
CLKSRCSEL1 Register Field Descriptions............................................................................
CURRCLKDIV0 Register Field Descriptions ..........................................................................
MEMINITSTART Register Field Descriptions .........................................................................
CURRCLKDIV1 Register Field Descriptions ..........................................................................
MEMINITDONE Register Field Descriptions ..........................................................................
USERMODEEN Register Field Descriptions ..........................................................................
NSYSPERUSERMODEN Register Field Descriptions ...............................................................
ESMGATE0 Register Field Descriptions ..............................................................................
ESMGATE1 Register Field Descriptions ..............................................................................
ESMGATE2 Register Field Descriptions ..............................................................................
ESMGATE3 Register Field Descriptions ..............................................................................
ESMGATE4 Register Field Descriptions ..............................................................................
KEY Register Field Descriptions ........................................................................................
SWIRQA Register Field Descriptions ..................................................................................
SWIRQB Register Field Descriptions ..................................................................................
MISCCTL0 Register Field Descriptions ................................................................................
ATCMERRCAPTCTL Register Field Descriptions ...................................................................
B0TCMERRCAPTCTL Register Field Descriptions ..................................................................
B1TCMERRCAPTCTL Register Field Descriptions ..................................................................
SOFTCORERST Register Field Descriptions .........................................................................
RSTCAUSE Register Field Descriptions ..............................................................................
List of Tables
328
329
330
331
332
333
334
335
336
337
338
339
339
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-81.
RSTCAUSECLR Register Field Descriptions ......................................................................... 367
4-82.
SPITRIGSRC Register Field Descriptions ............................................................................. 368
4-83.
CLKINUSE Register Field Descriptions ................................................................................ 369
4-84.
ECCEN Register Field Descriptions .................................................................................... 370
4-85.
ECCCAPT Register Field Descriptions ................................................................................ 371
4-86.
CLKDIVCTL2 Register Field Descriptions ............................................................................. 372
4-87.
SWIRQC Register Field Descriptions .................................................................................. 373
4-88.
MSS_GPCFG_REG Registers .......................................................................................... 374
4-89.
MSS_GPCFG_REG Access Type Codes ............................................................................. 374
4-90.
GPCFG0 Register Field Descriptions .................................................................................. 375
4-91.
GPCFG1 Register Field Descriptions .................................................................................. 376
4-92.
GPCFG2 Register Field Descriptions .................................................................................. 377
4-93.
GPCFG3 Register Field Descriptions .................................................................................. 378
4-94.
GPCFG4 Register Field Descriptions .................................................................................. 379
4-95.
CCCACFG0 Register Field Descriptions .............................................................................. 380
4-96.
CCCACFG1 Register Field Descriptions .............................................................................. 381
4-97.
CCCACFG2 Register Field Descriptions .............................................................................. 382
4-98.
CCCACFG3 Register Field Descriptions .............................................................................. 383
4-99.
CCCBCFG0 Register Field Descriptions .............................................................................. 384
4-100. CCCBCFG1 Register Field Descriptions .............................................................................. 385
4-101. CCCBCFG2 Register Field Descriptions .............................................................................. 386
4-102. CCCBCFG3 Register Field Descriptions .............................................................................. 387
4-103. CCCACNTVAL Register Field Descriptions ........................................................................... 388
4-104. CCCBCNTVAL Register Field Descriptions ........................................................................... 389
4-105. CCCABERRSTAT Register Field Descriptions ....................................................................... 390
4-106. USERMODEEN Register Field Descriptions .......................................................................... 391
4-107. DSS_REG Registers ..................................................................................................... 392
4-108. DSS_REG Access Type Codes
........................................................................................
394
4-109. RTIEVENTCAPTURESEL Register Field Descriptions .............................................................. 395
4-110. ADCBUFCFG1 Register Field Descriptions ........................................................................... 396
4-111. ADCBUFCFG2 Register Field Descriptions ........................................................................... 397
4-112. ADCBUFCFG3 Register Field Descriptions ........................................................................... 398
4-113. ADCBUFCFG4 Register Field Descriptions ........................................................................... 399
4-114. CQCFG1 Register Field Descriptions .................................................................................. 400
4-115. TPCCPARSTATCFG Register Field Descriptions .................................................................... 401
4-116. CSI2TXPARSTATCFG Register Field Descriptions.................................................................. 402
.................................................................................
...............................................................
TPTC0WRMPUSTADD1 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD6 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD7 Register Field Descriptions ...............................................................
TPTC0WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD3 Register Field Descriptions .............................................................
4-117. CSICFG1 Register Field Descriptions
403
4-118. TPTC0WRMPUSTADD0 Register Field Descriptions
404
4-119.
405
4-120.
4-121.
4-122.
4-123.
4-124.
4-125.
4-126.
4-127.
4-128.
4-129.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
406
407
408
409
410
411
412
413
414
415
79
www.ti.com
4-130. TPTC0WRMPUENDADD4 Register Field Descriptions ............................................................. 416
4-131. TPTC0WRMPUENDADD5 Register Field Descriptions ............................................................. 417
4-132. TPTC0WRMPUENDADD6 Register Field Descriptions ............................................................. 418
4-133. TPTC0WRMPUENDADD7 Register Field Descriptions ............................................................. 419
4-134. TPTC0WRMPUERRADD Register Field Descriptions ............................................................... 420
4-135. TPTC0RDMPUSTADD0 Register Field Descriptions ................................................................ 421
4-136. TPTC0RDMPUSTADD1 Register Field Descriptions ................................................................ 422
4-137. TPTC0RDMPUSTADD2 Register Field Descriptions ................................................................ 423
4-138. TPTC0RDMPUSTADD3 Register Field Descriptions ................................................................ 424
4-139. TPTC0RDMPUSTADD4 Register Field Descriptions ................................................................ 425
4-140. TPTC0RDMPUSTADD5 Register Field Descriptions ................................................................ 426
4-141. TPTC0RDMPUSTADD6 Register Field Descriptions ................................................................ 427
4-142. TPTC0RDMPUSTADD7 Register Field Descriptions ................................................................ 428
4-143. TPTC0RDMPUENDADD0 Register Field Descriptions .............................................................. 429
4-144. TPTC0RDMPUENDADD1 Register Field Descriptions .............................................................. 430
4-145. TPTC0RDMPUENDADD2 Register Field Descriptions .............................................................. 431
4-146. TPTC0RDMPUENDADD3 Register Field Descriptions .............................................................. 432
4-147. TPTC0RDMPUENDADD4 Register Field Descriptions .............................................................. 433
4-148. TPTC0RDMPUENDADD5 Register Field Descriptions .............................................................. 434
4-149. TPTC0RDMPUENDADD6 Register Field Descriptions .............................................................. 435
4-150. TPTC0RDMPUENDADD7 Register Field Descriptions .............................................................. 436
4-151. TPTC0RDMPUERRADD Register Field Descriptions ............................................................... 437
438
4-153. TPTC1WRMPUSTADD1 Register Field Descriptions
439
4-154.
440
4-155.
4-156.
4-157.
4-158.
4-159.
4-160.
4-161.
4-162.
4-163.
4-164.
4-165.
4-166.
4-167.
4-168.
4-169.
4-170.
4-171.
4-172.
4-173.
4-174.
4-175.
4-176.
4-177.
4-178.
80
...............................................................
...............................................................
TPTC1WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD6 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD7 Register Field Descriptions ...............................................................
TPTC1WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD4 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD5 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD6 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD7 Register Field Descriptions .............................................................
TPTC1WRMPUERRADD Register Field Descriptions ...............................................................
TPTC1RDMPUSTADD0 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD1 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD2 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD3 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD4 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD5 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD6 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD7 Register Field Descriptions ................................................................
TPTC1RDMPUENDADD0 Register Field Descriptions ..............................................................
TPTC1RDMPUENDADD1 Register Field Descriptions ..............................................................
4-152. TPTC1WRMPUSTADD0 Register Field Descriptions
List of Tables
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-179. TPTC1RDMPUENDADD2 Register Field Descriptions .............................................................. 465
4-180. TPTC1RDMPUENDADD3 Register Field Descriptions .............................................................. 466
4-181. TPTC1RDMPUENDADD4 Register Field Descriptions .............................................................. 467
4-182. TPTC1RDMPUENDADD5 Register Field Descriptions .............................................................. 468
4-183. TPTC1RDMPUENDADD6 Register Field Descriptions .............................................................. 469
4-184. TPTC1RDMPUENDADD7 Register Field Descriptions .............................................................. 470
4-185. TPTC1RDMPUERRADD Register Field Descriptions ............................................................... 471
4-186. TPTCMPUVALIDCFG Register Field Descriptions................................................................... 472
4-187. TPTCMPUENCFG Register Field Descriptions ....................................................................... 473
4-188. TESTPATTERNRX1ICFG Register Field Descriptions .............................................................. 474
4-189. TESTPATTERNRX2ICFG Register Field Descriptions .............................................................. 475
4-190. TESTPATTERNRX3ICFG Register Field Descriptions .............................................................. 476
4-191. TESTPATTERNRX4ICFG Register Field Descriptions .............................................................. 477
4-192. TESTPATTERNRX1QCFG Register Field Descriptions............................................................. 478
4-193. TESTPATTERNRX2QCFG Register Field Descriptions............................................................. 479
4-194. TESTPATTERNRX3QCFG Register Field Descriptions............................................................. 480
4-195. TESTPATTERNRX4QCFG Register Field Descriptions............................................................. 481
4-196. TESTPATTERNVLDCFG Register Field Descriptions ............................................................... 482
4-197. DSSMISC Register Field Descriptions ................................................................................. 483
4-198. DSSMISC2 Register Field Descriptions
...............................................................................
484
4-199. MSS_TOPRCM Registers ............................................................................................... 485
4-200. MSS_TOPRCM Access Type Codes
..................................................................................
486
4-201. BSSCTL Register Field Descriptions ................................................................................... 487
..................................................................................
EXTCLKDIV Register Field Descriptions ..............................................................................
EXTCLKSRCSEL Register Field Descriptions ........................................................................
EXTCLKCTL Register Field Descriptions..............................................................................
SOFTSYSRST Register Field Descriptions ...........................................................................
WDRSTEN Register Field Descriptions ...............................................................................
SYSRSTCAUSE Register Field Descriptions .........................................................................
SYSRSTCAUSECLR Register Field Descriptions ....................................................................
MISCCAPT Register Field Descriptions ...............................................................................
DCDCCTL0 Register Field Descriptions ...............................................................................
DCDCCTL1 Register Field Descriptions ...............................................................................
USERMODEEN Register Field Descriptions ..........................................................................
LVDSPADCTL0 Register Field Descriptions ..........................................................................
LVDSPADCTL1 Register Field Descriptions ..........................................................................
DFTREG0 Register Field Descriptions.................................................................................
DFTREG1 Register Field Descriptions.................................................................................
DFTREG5 Register Field Descriptions.................................................................................
MEMINITDONE Register Field Descriptions ..........................................................................
MSS_SIGNATURE Register Field Descriptions ......................................................................
GEMBOOTSTCEN Register Field Descriptions ......................................................................
MISCCTL1 Register Field Descriptions ................................................................................
USERMODEEN2 Register Field Descriptions ........................................................................
SYSTICK Register Field Descriptions..................................................................................
SECURECFGREG1 Register Field Descriptions .....................................................................
SECURECFGREG2 Register Field Descriptions .....................................................................
SECURECFGREG3 Register Field Descriptions .....................................................................
4-202. DSSCTL Register Field Descriptions
4-203.
4-204.
4-205.
4-206.
4-207.
4-208.
4-209.
4-210.
4-211.
4-212.
4-213.
4-214.
4-215.
4-216.
4-217.
4-218.
4-219.
4-220.
4-221.
4-222.
4-223.
4-224.
4-225.
4-226.
4-227.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
81
www.ti.com
4-228. SECURECFGREG4 Register Field Descriptions ..................................................................... 514
4-229. SECURERAMREG Register Field Descriptions ...................................................................... 515
4-230. SPAREMULTIBIT Register Field Descriptions ........................................................................ 516
4-231. UID31TO0 Register Field Descriptions ................................................................................ 517
4-232. UID63TO32 Register Field Descriptions ............................................................................... 518
4-233. UID95TO64 Register Field Descriptions ............................................................................... 519
4-234. UID119TO96 Register Field Descriptions ............................................................................. 520
4-235. MEMINITSTARTSHMEM Register Field Descriptions ............................................................... 521
4-236. MEMINITDONESHMEM Register Field Descriptions ................................................................ 522
4-237. DSSMEMTAB0 Register Field Descriptions........................................................................... 523
4-238. TCMAMEMTAB Register Field Descriptions .......................................................................... 524
4-239. TCMBMEMTAB Register Field Descriptions .......................................................................... 525
4-240. SHMEMBANKSEL3TO0 Register Field Descriptions ................................................................ 526
4-241. SHMEMBANKSEL7TO4 Register Field Descriptions ................................................................ 527
4-242. PBISTCLKCTL Register Field Descriptions ........................................................................... 528
4-243. MSS_RCM Registers..................................................................................................... 529
4-244. MSS_RCM Access Type Codes ........................................................................................ 530
4-245. SOFTRST1 Register Field Descriptions ............................................................................... 531
4-246. SOFTRST2 Register Field Descriptions ............................................................................... 532
4-247. CLKDIVCTL0 Register Field Descriptions ............................................................................. 533
4-248. CLKSRCSEL0 Register Field Descriptions............................................................................ 534
4-249. CR4CTL Register Field Descriptions ................................................................................... 535
4-250. CLKGATE Register Field Descriptions................................................................................. 536
4-251. CLKSRCSEL1 Register Field Descriptions............................................................................ 537
4-252. CURRCLKDIV0 Register Field Descriptions .......................................................................... 538
4-253. RTICURRCLKDIV Register Field Descriptions ....................................................................... 539
4-254. MEMINITSTART Register Field Descriptions ......................................................................... 540
4-255. CURRCLKDIV1 Register Field Descriptions .......................................................................... 541
4-256. MEMINITDONE Register Field Descriptions .......................................................................... 542
4-257. ECCENMSSGEM Register Field Descriptions ........................................................................ 543
4-258. ECCCAPTMSSGEM Register Field Descriptions .................................................................... 544
4-259. ECCENBSSGEM Register Field Descriptions ........................................................................ 545
4-260. ECCCAPTBSSGEM Register Field Descriptions ..................................................................... 546
4-261. USERMODEEN Register Field Descriptions .......................................................................... 547
4-262. NSYSPERUSERMODEN Register Field Descriptions ............................................................... 548
4-263. SECURERAMMMI Register Field Descriptions ....................................................................... 549
4-264. SECURERAMECC Register Field Descriptions ...................................................................... 550
551
4-266. ESMGATE1 Register Field Descriptions
552
4-267.
553
4-268.
4-269.
4-270.
4-271.
4-272.
4-273.
4-274.
4-275.
4-276.
82
..............................................................................
..............................................................................
ESMGATE2 Register Field Descriptions ..............................................................................
ESMGATE3 Register Field Descriptions ..............................................................................
ESMGATE4 Register Field Descriptions ..............................................................................
KEY Register Field Descriptions ........................................................................................
SWIRQA Register Field Descriptions ..................................................................................
SWIRQB Register Field Descriptions ..................................................................................
MISCCTL0 Register Field Descriptions ................................................................................
ATCMERRCAPTCTL Register Field Descriptions ...................................................................
B0TCMERRCAPTCTL Register Field Descriptions ..................................................................
B1TCMERRCAPTCTL Register Field Descriptions ..................................................................
4-265. ESMGATE0 Register Field Descriptions
List of Tables
554
555
556
557
558
559
560
561
562
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-277. SOFTCORERST Register Field Descriptions ......................................................................... 563
4-278. RSTCAUSE Register Field Descriptions
..............................................................................
564
4-279. RSTCAUSECLR Register Field Descriptions ......................................................................... 565
4-280. SPITRIGSRC Register Field Descriptions ............................................................................. 566
4-281. CLKINUSE Register Field Descriptions ................................................................................ 567
........................................................................
ECCCAPTMSSBSS Register Field Descriptions .....................................................................
CLKDIVCTL2 Register Field Descriptions .............................................................................
SWIRQC Register Field Descriptions ..................................................................................
MSS_GPCFG_REG Registers ..........................................................................................
MSS_GPCFG_REG Access Type Codes .............................................................................
GPCFG0 Register Field Descriptions ..................................................................................
GPCFG1 Register Field Descriptions ..................................................................................
GPCFG2 Register Field Descriptions ..................................................................................
GPCFG3 Register Field Descriptions ..................................................................................
GPCFG4 Register Field Descriptions ..................................................................................
GPCFG6 Register Field Descriptions ..................................................................................
GPCFG11 Register Field Descriptions.................................................................................
CCCACFG0 Register Field Descriptions ..............................................................................
CCCACFG1 Register Field Descriptions ..............................................................................
CCCACFG2 Register Field Descriptions ..............................................................................
CCCACFG3 Register Field Descriptions ..............................................................................
CCCBCFG0 Register Field Descriptions ..............................................................................
CCCBCFG1 Register Field Descriptions ..............................................................................
CCCBCFG2 Register Field Descriptions ..............................................................................
CCCBCFG3 Register Field Descriptions ..............................................................................
CCCACNTVAL Register Field Descriptions ...........................................................................
CCCBCNTVAL Register Field Descriptions ...........................................................................
CCCABERRSTAT Register Field Descriptions .......................................................................
USERMODEEN Register Field Descriptions ..........................................................................
EPWMCFG Register Field Descriptions ...............................................................................
DMMSWINT0 Register Field Descriptions ............................................................................
DMMSWINT1 Register Field Descriptions ............................................................................
DMMSWINTSEL0 Register Field Descriptions .......................................................................
DMMSWINTSEL1 Register Field Descriptions .......................................................................
CCCBWDEN Register Field Descriptions .............................................................................
GPIOINTREDGESEL Register Field Descriptions ...................................................................
PWMDMATRIGEN Register Field Descriptions ......................................................................
JTAGTXDATA Register Field Descriptions............................................................................
JTAGTXCONTROL Register Field Descriptions......................................................................
JTAGRXDATA Register Field Descriptions ...........................................................................
JTAGTXRXACK Register Field Descriptions .........................................................................
JTAGRXCONTROL Register Field Descriptions .....................................................................
MSS2GEMSWIRQ Register Field Descriptions ......................................................................
CSETBFLUSH Register Field Descriptions ...........................................................................
DSS_REG Registers .....................................................................................................
DSS_REG Access Type Codes ........................................................................................
RTIEVENTCAPTURESEL Register Field Descriptions ..............................................................
CQCFG1 Register Field Descriptions ..................................................................................
4-282. ECCENMSSBSS Register Field Descriptions
568
4-283.
569
4-284.
4-285.
4-286.
4-287.
4-288.
4-289.
4-290.
4-291.
4-292.
4-293.
4-294.
4-295.
4-296.
4-297.
4-298.
4-299.
4-300.
4-301.
4-302.
4-303.
4-304.
4-305.
4-306.
4-307.
4-308.
4-309.
4-310.
4-311.
4-312.
4-313.
4-314.
4-315.
4-316.
4-317.
4-318.
4-319.
4-320.
4-321.
4-322.
4-323.
4-324.
4-325.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
570
571
572
572
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
610
611
612
83
www.ti.com
4-326. TPCCPARSTATCFG Register Field Descriptions .................................................................... 613
614
4-328. TPTC0WRMPUSTADD1 Register Field Descriptions
615
4-329.
616
4-330.
4-331.
4-332.
4-333.
4-334.
4-335.
4-336.
4-337.
4-338.
4-339.
4-340.
4-341.
4-342.
4-343.
4-344.
4-345.
4-346.
4-347.
4-348.
4-349.
4-350.
4-351.
4-352.
4-353.
4-354.
4-355.
4-356.
4-357.
4-358.
4-359.
4-360.
4-361.
4-362.
4-363.
4-364.
4-365.
4-366.
4-367.
4-368.
4-369.
4-370.
4-371.
4-372.
4-373.
4-374.
84
...............................................................
...............................................................
TPTC0WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC0WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD4 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD5 Register Field Descriptions .............................................................
TPTC0WRMPUERRADD Register Field Descriptions ...............................................................
TPTC0RDMPUSTADD0 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD1 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD2 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD3 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD4 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD5 Register Field Descriptions ................................................................
TPTC0RDMPUENDADD0 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD1 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD2 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD3 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD4 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD5 Register Field Descriptions ..............................................................
TPTC0RDMPUERRADD Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD0 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD1 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC1WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD4 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD5 Register Field Descriptions .............................................................
TPTC1WRMPUERRADD Register Field Descriptions ...............................................................
TPTC1RDMPUSTADD0 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD1 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD2 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD3 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD4 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD5 Register Field Descriptions ................................................................
TPTC1RDMPUENDADD0 Register Field Descriptions ..............................................................
TPTC1RDMPUENDADD1 Register Field Descriptions ..............................................................
TPTC1RDMPUENDADD2 Register Field Descriptions ..............................................................
4-327. TPTC0WRMPUSTADD0 Register Field Descriptions
List of Tables
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-375. TPTC1RDMPUENDADD3 Register Field Descriptions .............................................................. 662
4-376. TPTC1RDMPUENDADD4 Register Field Descriptions .............................................................. 663
4-377. TPTC1RDMPUENDADD5 Register Field Descriptions .............................................................. 664
4-378. TPTC1RDMPUERRADD Register Field Descriptions ............................................................... 665
4-379. TPTCMPUVALIDCFG Register Field Descriptions................................................................... 666
4-380. TPTCMPUENCFG Register Field Descriptions ....................................................................... 667
4-381. TESTPATTERNRX1ICFG Register Field Descriptions .............................................................. 668
4-382. TESTPATTERNRX2ICFG Register Field Descriptions .............................................................. 669
4-383. TESTPATTERNRX3ICFG Register Field Descriptions .............................................................. 670
4-384. TESTPATTERNRX4ICFG Register Field Descriptions .............................................................. 671
4-385. TESTPATTERNRX1QCFG Register Field Descriptions............................................................. 672
4-386. TESTPATTERNRX2QCFG Register Field Descriptions............................................................. 673
4-387. TESTPATTERNRX3QCFG Register Field Descriptions............................................................. 674
4-388. TESTPATTERNRX4QCFG Register Field Descriptions............................................................. 675
4-389. TESTPATTERNVLDCFG Register Field Descriptions ............................................................... 676
4-390. TPCC1PARSTATCFG Register Field Descriptions .................................................................. 677
4-391. DMMSWINT1 Register Field Descriptions
............................................................................
678
4-392. DSSINTRCFG Register Field Descriptions............................................................................ 679
4-393. MPUMSTIDCFG1 Register Field Descriptions........................................................................ 680
4-394. MPUMSTIDCFG2 Register Field Descriptions........................................................................ 681
4-395. MPUMSTIDCFG3 Register Field Descriptions........................................................................ 682
4-396. HSRAM1ECCCFG Register Field Descriptions
......................................................................
683
4-397. DATATRRAMECCCFG Register Field Descriptions ................................................................. 684
4-398. ADCBUFPINGECCCFG Register Field Descriptions ................................................................ 685
4-399. ADCBUFPONGECCCFG Register Field Descriptions ............................................................... 686
4-400. UMAP0PARITYCFG1 Register Field Descriptions ................................................................... 687
4-401. UMAP0PARITYCFG2 Register Field Descriptions ................................................................... 688
4-402. UMAP0PARITYCFG3 Register Field Descriptions ................................................................... 689
4-403. UMAP1PARITYCFG1 Register Field Descriptions ................................................................... 690
4-404. UMAP1PARITYCFG2 Register Field Descriptions ................................................................... 691
4-405. UMAP1PARITYCFG3 Register Field Descriptions ................................................................... 692
4-406. ESMGRP2MASKCFG Register Field Descriptions................................................................... 693
4-407. L2MEMINITCFG1 Register Field Descriptions........................................................................ 694
4-408. L2MEMINITCFG2 Register Field Descriptions........................................................................ 696
4-409. GEMRSTCAUSE Register Field Descriptions ........................................................................ 697
.....................................................................
PWRSMWAKEMASK0 Register Field Descriptions ..................................................................
PWRSMWAKEMASK1 Register Field Descriptions ..................................................................
PWRSMWAKEMASK2 Register Field Descriptions ..................................................................
PWRSMMISEVTMASK0 Register Field Descriptions................................................................
PWRSMMISEVTMASK1 Register Field Descriptions................................................................
PWRSMMISEVTMASK2 Register Field Descriptions................................................................
PWRSMWAKESRCSTAT0 Register Field Descriptions .............................................................
PWRSMWAKESRCSTAT1 Register Field Descriptions .............................................................
PWRSMWAKESRCSTAT2 Register Field Descriptions .............................................................
PWRSMEVNTMONSTAT0 Register Field Descriptions .............................................................
PWRSMEVNTMONSTAT1 Register Field Descriptions .............................................................
PWRSMEVNTMONSTAT2 Register Field Descriptions .............................................................
PWRSMWAKESRCSTATCLR0 Register Field Descriptions .......................................................
4-410. GEMPWRSMCFG4 Register Field Descriptions
698
4-411.
699
4-412.
4-413.
4-414.
4-415.
4-416.
4-417.
4-418.
4-419.
4-420.
4-421.
4-422.
4-423.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
700
701
702
703
704
705
706
707
708
709
710
711
85
www.ti.com
4-424. PWRSMWAKESRCSTATCLR1 Register Field Descriptions ....................................................... 712
4-425. PWRSMWAKESRCSTATCLR2 Register Field Descriptions ....................................................... 713
4-426. ADCBUFCFG1 Register Field Descriptions ........................................................................... 714
4-427. ADCBUFCFG2 Register Field Descriptions ........................................................................... 715
4-428. ADCBUFCFG3 Register Field Descriptions ........................................................................... 716
4-429. ADCBUFCFG4 Register Field Descriptions ........................................................................... 717
4-430. STCPBISTSMCFG1 Register Field Descriptions ..................................................................... 718
4-431. STCPBISTSMCFG2 Register Field Descriptions ..................................................................... 719
4-432. RTI2EVENTCAPTURESEL Register Field Descriptions ............................................................ 720
4-433. DSSMISC5 Register Field Descriptions
...............................................................................
721
4-434. DSS_REG2 Registers .................................................................................................... 722
4-435. DSS_REG2 Access Type Codes ....................................................................................... 723
724
4-437. TPTC2WRMPUSTADD1 Register Field Descriptions
725
4-438.
726
4-439.
4-440.
4-441.
4-442.
4-443.
4-444.
4-445.
4-446.
4-447.
4-448.
4-449.
4-450.
4-451.
4-452.
4-453.
4-454.
4-455.
4-456.
4-457.
4-458.
4-459.
4-460.
4-461.
4-462.
4-463.
4-464.
4-465.
4-466.
4-467.
4-468.
4-469.
4-470.
4-471.
4-472.
86
...............................................................
...............................................................
TPTC2WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC2WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC2WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC2WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC2WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC2WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC2WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC2WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC2WRMPUENDADD4 Register Field Descriptions .............................................................
TPTC2WRMPUENDADD5 Register Field Descriptions .............................................................
TPTC2WRMPUERRADD Register Field Descriptions ...............................................................
TPTC2RDMPUSTADD0 Register Field Descriptions ................................................................
TPTC2RDMPUSTADD1 Register Field Descriptions ................................................................
TPTC2RDMPUSTADD2 Register Field Descriptions ................................................................
TPTC2RDMPUSTADD3 Register Field Descriptions ................................................................
TPTC2RDMPUSTADD4 Register Field Descriptions ................................................................
TPTC2RDMPUSTADD5 Register Field Descriptions ................................................................
TPTC2RDMPUENDADD0 Register Field Descriptions ..............................................................
TPTC2RDMPUENDADD1 Register Field Descriptions ..............................................................
TPTC2RDMPUENDADD2 Register Field Descriptions ..............................................................
TPTC2RDMPUENDADD3 Register Field Descriptions ..............................................................
TPTC2RDMPUENDADD4 Register Field Descriptions ..............................................................
TPTC2RDMPUENDADD5 Register Field Descriptions ..............................................................
TPTC2RDMPUERRADD Register Field Descriptions ...............................................................
TPTC3WRMPUSTADD0 Register Field Descriptions ...............................................................
TPTC3WRMPUSTADD1 Register Field Descriptions ...............................................................
TPTC3WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC3WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC3WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC3WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC3WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC3WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC3WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC3WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC3WRMPUENDADD4 Register Field Descriptions .............................................................
4-436. TPTC2WRMPUSTADD0 Register Field Descriptions
List of Tables
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-473. TPTC3WRMPUENDADD5 Register Field Descriptions ............................................................. 761
4-474. TPTC3WRMPUERRADD Register Field Descriptions ............................................................... 762
4-475. TPTC3RDMPUSTADD0 Register Field Descriptions ................................................................ 763
4-476. TPTC3RDMPUSTADD1 Register Field Descriptions ................................................................ 764
4-477. TPTC3RDMPUSTADD2 Register Field Descriptions ................................................................ 765
4-478. TPTC3RDMPUSTADD3 Register Field Descriptions ................................................................ 766
4-479. TPTC3RDMPUSTADD4 Register Field Descriptions ................................................................ 767
4-480. TPTC3RDMPUSTADD5 Register Field Descriptions ................................................................ 768
4-481. TPTC3RDMPUENDADD0 Register Field Descriptions .............................................................. 769
4-482. TPTC3RDMPUENDADD1 Register Field Descriptions .............................................................. 770
4-483. TPTC3RDMPUENDADD2 Register Field Descriptions .............................................................. 771
4-484. TPTC3RDMPUENDADD3 Register Field Descriptions .............................................................. 772
4-485. TPTC3RDMPUENDADD4 Register Field Descriptions .............................................................. 773
4-486. TPTC3RDMPUENDADD5 Register Field Descriptions .............................................................. 774
4-487. TPTC3RDMPUERRADD Register Field Descriptions ............................................................... 775
4-488. TPTCMPUVALIDCFG2 Register Field Descriptions ................................................................. 776
4-489. TPTCMPUENCFG2 Register Field Descriptions ..................................................................... 777
4-490. L3ECCCFG1 Register Field Descriptions ............................................................................. 778
4-491. L3ECCCFG2 Register Field Descriptions ............................................................................. 779
4-492. DSS2MSSSWIRQ Register Field Descriptions ....................................................................... 780
4-493. MSS_TOPRCM Registers ............................................................................................... 782
4-494. MSS_TOPRCM Access Type Codes
..................................................................................
783
4-495. BSSCTL Register Field Descriptions ................................................................................... 784
..................................................................................
EXTCLKDIV Register Field Descriptions ..............................................................................
EXTCLKSRCSEL Register Field Descriptions ........................................................................
EXTCLKCTL Register Field Descriptions..............................................................................
SOFTSYSRST Register Field Descriptions ...........................................................................
WDRSTEN Register Field Descriptions ...............................................................................
SYSRSTCAUSE Register Field Descriptions .........................................................................
SYSRSTCAUSECLR Register Field Descriptions ....................................................................
MISCCAPT Register Field Descriptions ...............................................................................
DCDCCTL0 Register Field Descriptions ...............................................................................
DCDCCTL1 Register Field Descriptions ...............................................................................
USERMODEEN Register Field Descriptions ..........................................................................
LVDSPADCTL0 Register Field Descriptions ..........................................................................
LVDSPADCTL1 Register Field Descriptions ..........................................................................
DFTREG0 Register Field Descriptions.................................................................................
DFTREG1 Register Field Descriptions.................................................................................
DFTREG5 Register Field Descriptions.................................................................................
MEMINITDONE Register Field Descriptions ..........................................................................
MSS_SIGNATURE Register Field Descriptions ......................................................................
GEMBOOTSTCEN Register Field Descriptions ......................................................................
MISCCTL1 Register Field Descriptions ................................................................................
USERMODEEN2 Register Field Descriptions ........................................................................
SYSTICK Register Field Descriptions..................................................................................
SECURECFGREG1 Register Field Descriptions .....................................................................
SECURECFGREG2 Register Field Descriptions .....................................................................
SECURECFGREG3 Register Field Descriptions .....................................................................
4-496. DSSCTL Register Field Descriptions
4-497.
4-498.
4-499.
4-500.
4-501.
4-502.
4-503.
4-504.
4-505.
4-506.
4-507.
4-508.
4-509.
4-510.
4-511.
4-512.
4-513.
4-514.
4-515.
4-516.
4-517.
4-518.
4-519.
4-520.
4-521.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
87
www.ti.com
4-522. SECURECFGREG4 Register Field Descriptions ..................................................................... 811
4-523. SECURERAMREG Register Field Descriptions ...................................................................... 812
4-524. SPAREMULTIBIT Register Field Descriptions ........................................................................ 813
4-525. UID31TO0 Register Field Descriptions ................................................................................ 814
4-526. UID63TO32 Register Field Descriptions ............................................................................... 815
4-527. UID95TO64 Register Field Descriptions ............................................................................... 816
4-528. UID119TO96 Register Field Descriptions ............................................................................. 817
4-529. MEMINITSTARTSHMEM Register Field Descriptions ............................................................... 818
4-530. MEMINITDONESHMEM Register Field Descriptions ................................................................ 819
4-531. DSSMEMTAB0 Register Field Descriptions........................................................................... 820
4-532. TCMAMEMTAB Register Field Descriptions .......................................................................... 821
4-533. TCMBMEMTAB Register Field Descriptions .......................................................................... 822
4-534. SHMEMBANKSEL3TO0 Register Field Descriptions ................................................................ 823
4-535. SHMEMBANKSEL7TO4 Register Field Descriptions ................................................................ 824
4-536. PBISTCLKCTL Register Field Descriptions ........................................................................... 825
4-537. MSS_RCM Registers..................................................................................................... 826
4-538. MSS_RCM Access Type Codes ........................................................................................ 827
4-539. SOFTRST1 Register Field Descriptions ............................................................................... 828
4-540. SOFTRST2 Register Field Descriptions ............................................................................... 829
4-541. CLKDIVCTL0 Register Field Descriptions ............................................................................. 830
4-542. CLKSRCSEL0 Register Field Descriptions............................................................................ 831
4-543. CR4CTL Register Field Descriptions ................................................................................... 832
4-544. CLKGATE Register Field Descriptions................................................................................. 833
4-545. CLKSRCSEL1 Register Field Descriptions............................................................................ 834
4-546. CURRCLKDIV0 Register Field Descriptions .......................................................................... 835
4-547. RTICURRCLKDIV Register Field Descriptions ....................................................................... 836
4-548. MEMINITSTART Register Field Descriptions ......................................................................... 837
4-549. CURRCLKDIV1 Register Field Descriptions .......................................................................... 838
4-550. MEMINITDONE Register Field Descriptions .......................................................................... 839
4-551. ECCENMSSGEM Register Field Descriptions ........................................................................ 840
4-552. ECCCAPTMSSGEM Register Field Descriptions .................................................................... 841
4-553. ECCENBSSGEM Register Field Descriptions ........................................................................ 842
4-554. ECCCAPTBSSGEM Register Field Descriptions ..................................................................... 843
4-555. USERMODEEN Register Field Descriptions .......................................................................... 844
4-556. NSYSPERUSERMODEN Register Field Descriptions ............................................................... 845
4-557. SECURERAMMMI Register Field Descriptions ....................................................................... 846
4-558. SECURERAMECC Register Field Descriptions ...................................................................... 847
848
4-560. ESMGATE1 Register Field Descriptions
849
4-561.
850
4-562.
4-563.
4-564.
4-565.
4-566.
4-567.
4-568.
4-569.
4-570.
88
..............................................................................
..............................................................................
ESMGATE2 Register Field Descriptions ..............................................................................
ESMGATE3 Register Field Descriptions ..............................................................................
ESMGATE4 Register Field Descriptions ..............................................................................
KEY Register Field Descriptions ........................................................................................
SWIRQA Register Field Descriptions ..................................................................................
SWIRQB Register Field Descriptions ..................................................................................
MISCCTL0 Register Field Descriptions ................................................................................
ATCMERRCAPTCTL Register Field Descriptions ...................................................................
B0TCMERRCAPTCTL Register Field Descriptions ..................................................................
B1TCMERRCAPTCTL Register Field Descriptions ..................................................................
4-559. ESMGATE0 Register Field Descriptions
List of Tables
851
852
853
854
855
856
857
858
859
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-571. SOFTCORERST Register Field Descriptions ......................................................................... 860
4-572. RSTCAUSE Register Field Descriptions
..............................................................................
861
4-573. RSTCAUSECLR Register Field Descriptions ......................................................................... 862
4-574. SPITRIGSRC Register Field Descriptions ............................................................................. 863
4-575. CLKINUSE Register Field Descriptions ................................................................................ 864
........................................................................
ECCCAPTMSSBSS Register Field Descriptions .....................................................................
CLKDIVCTL2 Register Field Descriptions .............................................................................
SWIRQC Register Field Descriptions ..................................................................................
MSS_GPCFG_REG Registers ..........................................................................................
MSS_GPCFG_REG Access Type Codes .............................................................................
GPCFG0 Register Field Descriptions ..................................................................................
GPCFG1 Register Field Descriptions ..................................................................................
GPCFG2 Register Field Descriptions ..................................................................................
GPCFG3 Register Field Descriptions ..................................................................................
GPCFG4 Register Field Descriptions ..................................................................................
GPCFG6 Register Field Descriptions ..................................................................................
GPCFG11 Register Field Descriptions.................................................................................
CCCACFG0 Register Field Descriptions ..............................................................................
CCCACFG1 Register Field Descriptions ..............................................................................
CCCACFG2 Register Field Descriptions ..............................................................................
CCCACFG3 Register Field Descriptions ..............................................................................
CCCBCFG0 Register Field Descriptions ..............................................................................
CCCBCFG1 Register Field Descriptions ..............................................................................
CCCBCFG2 Register Field Descriptions ..............................................................................
CCCBCFG3 Register Field Descriptions ..............................................................................
CCCACNTVAL Register Field Descriptions ...........................................................................
CCCBCNTVAL Register Field Descriptions ...........................................................................
CCCABERRSTAT Register Field Descriptions .......................................................................
USERMODEEN Register Field Descriptions ..........................................................................
EPWMCFG Register Field Descriptions ...............................................................................
DMMSWINT0 Register Field Descriptions ............................................................................
DMMSWINT1 Register Field Descriptions ............................................................................
DMMSWINTSEL0 Register Field Descriptions .......................................................................
DMMSWINTSEL1 Register Field Descriptions .......................................................................
CCCBWDEN Register Field Descriptions .............................................................................
GPIOINTREDGESEL Register Field Descriptions ...................................................................
PWMDMATRIGEN Register Field Descriptions ......................................................................
JTAGTXDATA Register Field Descriptions............................................................................
JTAGTXCONTROL Register Field Descriptions......................................................................
JTAGRXDATA Register Field Descriptions ...........................................................................
JTAGTXRXACK Register Field Descriptions .........................................................................
JTAGRXCONTROL Register Field Descriptions .....................................................................
MSS2GEMSWIRQ Register Field Descriptions ......................................................................
CSETBFLUSH Register Field Descriptions ...........................................................................
DSS_REG Registers .....................................................................................................
DSS_REG Access Type Codes ........................................................................................
RTIEVENTCAPTURESEL Register Field Descriptions ..............................................................
CQCFG1 Register Field Descriptions ..................................................................................
4-576. ECCENMSSBSS Register Field Descriptions
865
4-577.
866
4-578.
4-579.
4-580.
4-581.
4-582.
4-583.
4-584.
4-585.
4-586.
4-587.
4-588.
4-589.
4-590.
4-591.
4-592.
4-593.
4-594.
4-595.
4-596.
4-597.
4-598.
4-599.
4-600.
4-601.
4-602.
4-603.
4-604.
4-605.
4-606.
4-607.
4-608.
4-609.
4-610.
4-611.
4-612.
4-613.
4-614.
4-615.
4-616.
4-617.
4-618.
4-619.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
867
868
869
869
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
907
908
909
89
www.ti.com
4-620. TPCCPARSTATCFG Register Field Descriptions .................................................................... 910
911
4-622. TPTC0WRMPUSTADD1 Register Field Descriptions
912
4-623.
913
4-624.
4-625.
4-626.
4-627.
4-628.
4-629.
4-630.
4-631.
4-632.
4-633.
4-634.
4-635.
4-636.
4-637.
4-638.
4-639.
4-640.
4-641.
4-642.
4-643.
4-644.
4-645.
4-646.
4-647.
4-648.
4-649.
4-650.
4-651.
4-652.
4-653.
4-654.
4-655.
4-656.
4-657.
4-658.
4-659.
4-660.
4-661.
4-662.
4-663.
4-664.
4-665.
4-666.
4-667.
4-668.
90
...............................................................
...............................................................
TPTC0WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC0WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC0WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD4 Register Field Descriptions .............................................................
TPTC0WRMPUENDADD5 Register Field Descriptions .............................................................
TPTC0WRMPUERRADD Register Field Descriptions ...............................................................
TPTC0RDMPUSTADD0 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD1 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD2 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD3 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD4 Register Field Descriptions ................................................................
TPTC0RDMPUSTADD5 Register Field Descriptions ................................................................
TPTC0RDMPUENDADD0 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD1 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD2 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD3 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD4 Register Field Descriptions ..............................................................
TPTC0RDMPUENDADD5 Register Field Descriptions ..............................................................
TPTC0RDMPUERRADD Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD0 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD1 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD2 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD3 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD4 Register Field Descriptions ...............................................................
TPTC1WRMPUSTADD5 Register Field Descriptions ...............................................................
TPTC1WRMPUENDADD0 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD1 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD2 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD3 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD4 Register Field Descriptions .............................................................
TPTC1WRMPUENDADD5 Register Field Descriptions .............................................................
TPTC1WRMPUERRADD Register Field Descriptions ...............................................................
TPTC1RDMPUSTADD0 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD1 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD2 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD3 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD4 Register Field Descriptions ................................................................
TPTC1RDMPUSTADD5 Register Field Descriptions ................................................................
TPTC1RDMPUENDADD0 Register Field Descriptions ..............................................................
TPTC1RDMPUENDADD1 Register Field Descriptions ..............................................................
TPTC1RDMPUENDADD2 Register Field Descriptions ..............................................................
4-621. TPTC0WRMPUSTADD0 Register Field Descriptions
List of Tables
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-669. TPTC1RDMPUENDADD3 Register Field Descriptions .............................................................. 959
4-670. TPTC1RDMPUENDADD4 Register Field Descriptions .............................................................. 960
4-671. TPTC1RDMPUENDADD5 Register Field Descriptions .............................................................. 961
4-672. TPTC1RDMPUERRADD Register Field Descriptions ............................................................... 962
4-673. TPTCMPUVALIDCFG Register Field Descriptions................................................................... 963
4-674. TPTCMPUENCFG Register Field Descriptions ....................................................................... 964
4-675. TESTPATTERNRX1ICFG Register Field Descriptions .............................................................. 965
4-676. TESTPATTERNRX2ICFG Register Field Descriptions .............................................................. 966
4-677. TESTPATTERNRX3ICFG Register Field Descriptions .............................................................. 967
4-678. TESTPATTERNRX4ICFG Register Field Descriptions .............................................................. 968
4-679. TESTPATTERNRX1QCFG Register Field Descriptions............................................................. 969
4-680. TESTPATTERNRX2QCFG Register Field Descriptions............................................................. 970
4-681. TESTPATTERNRX3QCFG Register Field Descriptions............................................................. 971
4-682. TESTPATTERNRX4QCFG Register Field Descriptions............................................................. 972
4-683. TESTPATTERNVLDCFG Register Field Descriptions ............................................................... 973
4-684. TPCC1PARSTATCFG Register Field Descriptions .................................................................. 974
4-685. DMMSWINT1 Register Field Descriptions
............................................................................
975
4-686. DSSINTRCFG Register Field Descriptions............................................................................ 976
4-687. MPUMSTIDCFG1 Register Field Descriptions........................................................................ 977
4-688. MPUMSTIDCFG2 Register Field Descriptions........................................................................ 978
4-689. MPUMSTIDCFG3 Register Field Descriptions........................................................................ 979
4-690. HSRAM1ECCCFG Register Field Descriptions
......................................................................
980
4-691. DATATRRAMECCCFG Register Field Descriptions ................................................................. 981
4-692. ADCBUFPINGECCCFG Register Field Descriptions ................................................................ 982
4-693. ADCBUFPONGECCCFG Register Field Descriptions ............................................................... 983
4-694. UMAP0PARITYCFG1 Register Field Descriptions ................................................................... 984
4-695. UMAP0PARITYCFG2 Register Field Descriptions ................................................................... 985
4-696. UMAP0PARITYCFG3 Register Field Descriptions ................................................................... 986
4-697. UMAP1PARITYCFG1 Register Field Descriptions ................................................................... 987
4-698. UMAP1PARITYCFG2 Register Field Descriptions ................................................................... 988
4-699. UMAP1PARITYCFG3 Register Field Descriptions ................................................................... 989
4-700. ESMGRP2MASKCFG Register Field Descriptions................................................................... 990
4-701. L2MEMINITCFG1 Register Field Descriptions........................................................................ 991
4-702. L2MEMINITCFG2 Register Field Descriptions........................................................................ 993
4-703. GEMRSTCAUSE Register Field Descriptions ........................................................................ 994
..................................................................... 995
PWRSMWAKEMASK0 Register Field Descriptions .................................................................. 996
PWRSMWAKEMASK1 Register Field Descriptions .................................................................. 997
PWRSMWAKEMASK2 Register Field Descriptions .................................................................. 998
PWRSMMISEVTMASK0 Register Field Descriptions................................................................ 999
PWRSMMISEVTMASK1 Register Field Descriptions .............................................................. 1000
PWRSMMISEVTMASK2 Register Field Descriptions .............................................................. 1001
PWRSMWAKESRCSTAT0 Register Field Descriptions ........................................................... 1002
PWRSMWAKESRCSTAT1 Register Field Descriptions ........................................................... 1003
PWRSMWAKESRCSTAT2 Register Field Descriptions ........................................................... 1004
PWRSMEVNTMONSTAT0 Register Field Descriptions ........................................................... 1005
PWRSMEVNTMONSTAT1 Register Field Descriptions ........................................................... 1006
PWRSMEVNTMONSTAT2 Register Field Descriptions ........................................................... 1007
PWRSMWAKESRCSTATCLR0 Register Field Descriptions ...................................................... 1008
4-704. GEMPWRSMCFG4 Register Field Descriptions
4-705.
4-706.
4-707.
4-708.
4-709.
4-710.
4-711.
4-712.
4-713.
4-714.
4-715.
4-716.
4-717.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
91
www.ti.com
4-718. PWRSMWAKESRCSTATCLR1 Register Field Descriptions ...................................................... 1009
4-719. PWRSMWAKESRCSTATCLR2 Register Field Descriptions ...................................................... 1010
4-720. ADCBUFCFG1 Register Field Descriptions ......................................................................... 1011
4-721. ADCBUFCFG2 Register Field Descriptions ......................................................................... 1012
4-722. ADCBUFCFG3 Register Field Descriptions ......................................................................... 1013
4-723. ADCBUFCFG4 Register Field Descriptions ......................................................................... 1014
4-724. STCPBISTSMCFG1 Register Field Descriptions ................................................................... 1015
4-725. STCPBISTSMCFG2 Register Field Descriptions ................................................................... 1016
4-726. RTI2EVENTCAPTURESEL Register Field Descriptions ........................................................... 1017
4-727. DSSMISC5 Register Field Descriptions .............................................................................. 1018
4-728. DSS_REG2 Registers .................................................................................................. 1019
4-729. DSS_REG2 Access Type Codes
.....................................................................................
1020
4-730. TPTC2WRMPUSTADD0 Register Field Descriptions .............................................................. 1021
4-731. TPTC2WRMPUSTADD1 Register Field Descriptions .............................................................. 1022
4-732. TPTC2WRMPUSTADD2 Register Field Descriptions .............................................................. 1023
4-733. TPTC2WRMPUSTADD3 Register Field Descriptions .............................................................. 1024
4-734. TPTC2WRMPUSTADD4 Register Field Descriptions .............................................................. 1025
4-735. TPTC2WRMPUSTADD5 Register Field Descriptions .............................................................. 1026
4-736. TPTC2WRMPUENDADD0 Register Field Descriptions ............................................................ 1027
4-737. TPTC2WRMPUENDADD1 Register Field Descriptions ............................................................ 1028
4-738. TPTC2WRMPUENDADD2 Register Field Descriptions ............................................................ 1029
4-739. TPTC2WRMPUENDADD3 Register Field Descriptions ............................................................ 1030
4-740. TPTC2WRMPUENDADD4 Register Field Descriptions ............................................................ 1031
4-741. TPTC2WRMPUENDADD5 Register Field Descriptions ............................................................ 1032
4-742. TPTC2WRMPUERRADD Register Field Descriptions ............................................................. 1033
4-743. TPTC2RDMPUSTADD0 Register Field Descriptions............................................................... 1034
4-744. TPTC2RDMPUSTADD1 Register Field Descriptions............................................................... 1035
4-745. TPTC2RDMPUSTADD2 Register Field Descriptions............................................................... 1036
4-746. TPTC2RDMPUSTADD3 Register Field Descriptions............................................................... 1037
4-747. TPTC2RDMPUSTADD4 Register Field Descriptions............................................................... 1038
4-748. TPTC2RDMPUSTADD5 Register Field Descriptions............................................................... 1039
4-749. TPTC2RDMPUENDADD0 Register Field Descriptions ............................................................ 1040
4-750. TPTC2RDMPUENDADD1 Register Field Descriptions ............................................................ 1041
4-751. TPTC2RDMPUENDADD2 Register Field Descriptions ............................................................ 1042
4-752. TPTC2RDMPUENDADD3 Register Field Descriptions ............................................................ 1043
4-753. TPTC2RDMPUENDADD4 Register Field Descriptions ............................................................ 1044
4-754. TPTC2RDMPUENDADD5 Register Field Descriptions ............................................................ 1045
4-755. TPTC2RDMPUERRADD Register Field Descriptions .............................................................. 1046
4-756. TPTC3WRMPUSTADD0 Register Field Descriptions .............................................................. 1047
4-757. TPTC3WRMPUSTADD1 Register Field Descriptions .............................................................. 1048
4-758. TPTC3WRMPUSTADD2 Register Field Descriptions .............................................................. 1049
4-759. TPTC3WRMPUSTADD3 Register Field Descriptions .............................................................. 1050
4-760. TPTC3WRMPUSTADD4 Register Field Descriptions .............................................................. 1051
4-761. TPTC3WRMPUSTADD5 Register Field Descriptions .............................................................. 1052
4-762. TPTC3WRMPUENDADD0 Register Field Descriptions ............................................................ 1053
4-763. TPTC3WRMPUENDADD1 Register Field Descriptions ............................................................ 1054
4-764. TPTC3WRMPUENDADD2 Register Field Descriptions ............................................................ 1055
4-765. TPTC3WRMPUENDADD3 Register Field Descriptions ............................................................ 1056
4-766. TPTC3WRMPUENDADD4 Register Field Descriptions ............................................................ 1057
92
List of Tables
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-767. TPTC3WRMPUENDADD5 Register Field Descriptions ............................................................ 1058
4-768. TPTC3WRMPUERRADD Register Field Descriptions ............................................................. 1059
4-769. TPTC3RDMPUSTADD0 Register Field Descriptions............................................................... 1060
4-770. TPTC3RDMPUSTADD1 Register Field Descriptions............................................................... 1061
4-771. TPTC3RDMPUSTADD2 Register Field Descriptions............................................................... 1062
4-772. TPTC3RDMPUSTADD3 Register Field Descriptions............................................................... 1063
4-773. TPTC3RDMPUSTADD4 Register Field Descriptions............................................................... 1064
4-774. TPTC3RDMPUSTADD5 Register Field Descriptions............................................................... 1065
4-775. TPTC3RDMPUENDADD0 Register Field Descriptions ............................................................ 1066
4-776. TPTC3RDMPUENDADD1 Register Field Descriptions ............................................................ 1067
4-777. TPTC3RDMPUENDADD2 Register Field Descriptions ............................................................ 1068
4-778. TPTC3RDMPUENDADD3 Register Field Descriptions ............................................................ 1069
4-779. TPTC3RDMPUENDADD4 Register Field Descriptions ............................................................ 1070
4-780. TPTC3RDMPUENDADD5 Register Field Descriptions ............................................................ 1071
4-781. TPTC3RDMPUERRADD Register Field Descriptions .............................................................. 1072
4-782. TPTCMPUVALIDCFG2 Register Field Descriptions................................................................ 1073
4-783. TPTCMPUENCFG2 Register Field Descriptions .................................................................... 1074
4-784. L3ECCCFG1 Register Field Descriptions ............................................................................ 1075
4-785. L3ECCCFG2 Register Field Descriptions ............................................................................ 1076
4-786. DSS2MSSSWIRQ Register Field Descriptions...................................................................... 1077
4-787. MSS_TOPRCM Registers.............................................................................................. 1078
4-788. MSS_TOPRCM Access Type Codes ................................................................................. 1079
4-789. BSSCTL Register Field Descriptions ................................................................................. 1080
4-790. DSSCTL Register Field Descriptions ................................................................................. 1081
4-791. EXTCLKDIV Register Field Descriptions ............................................................................. 1082
4-792. EXTCLKSRCSEL Register Field Descriptions ...................................................................... 1083
4-793. EXTCLKCTL Register Field Descriptions ............................................................................ 1084
4-794. SOFTSYSRST Register Field Descriptions .......................................................................... 1085
4-795. WDRSTEN Register Field Descriptions .............................................................................. 1086
4-796. SYSRSTCAUSE Register Field Descriptions........................................................................ 1087
4-797. SYSRSTCAUSECLR Register Field Descriptions .................................................................. 1088
4-798. MISCCAPT Register Field Descriptions .............................................................................. 1089
4-799. DCDCCTL0 Register Field Descriptions ............................................................................. 1090
4-800. DCDCCTL1 Register Field Descriptions ............................................................................. 1091
4-801. USERMODEEN Register Field Descriptions ........................................................................ 1092
........................................................................
LVDSPADCTL1 Register Field Descriptions ........................................................................
DFTREG0 Register Field Descriptions ...............................................................................
DFTREG1 Register Field Descriptions ...............................................................................
DFTREG5 Register Field Descriptions ...............................................................................
MEMINITDONE Register Field Descriptions ........................................................................
MSS_SIGNATURE Register Field Descriptions.....................................................................
GEMBOOTSTCEN Register Field Descriptions .....................................................................
MISCCTL1 Register Field Descriptions ..............................................................................
USERMODEEN2 Register Field Descriptions .......................................................................
SYSTICK Register Field Descriptions ................................................................................
SECURECFGREG1 Register Field Descriptions ...................................................................
SECURECFGREG2 Register Field Descriptions ...................................................................
SECURECFGREG3 Register Field Descriptions ...................................................................
4-802. LVDSPADCTL0 Register Field Descriptions
1093
4-803.
1094
4-804.
4-805.
4-806.
4-807.
4-808.
4-809.
4-810.
4-811.
4-812.
4-813.
4-814.
4-815.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
93
www.ti.com
4-816. SECURECFGREG4 Register Field Descriptions ................................................................... 1107
4-817. SECURERAMREG Register Field Descriptions..................................................................... 1108
4-818. SPAREMULTIBIT Register Field Descriptions ...................................................................... 1109
4-819. UID31TO0 Register Field Descriptions ............................................................................... 1110
4-820. UID63TO32 Register Field Descriptions ............................................................................. 1111
4-821. UID95TO64 Register Field Descriptions ............................................................................. 1112
4-822. UID119TO96 Register Field Descriptions ............................................................................ 1113
4-823. MEMINITSTARTSHMEM Register Field Descriptions ............................................................. 1114
..............................................................
DSSMEMTAB0 Register Field Descriptions .........................................................................
TCMAMEMTAB Register Field Descriptions ........................................................................
TCMBMEMTAB Register Field Descriptions ........................................................................
SHMEMBANKSEL3TO0 Register Field Descriptions ..............................................................
SHMEMBANKSEL7TO4 Register Field Descriptions ..............................................................
PBISTCLKCTL Register Field Descriptions .........................................................................
MSS_RCM Registers ...................................................................................................
MSS_RCM Access Type Codes ......................................................................................
SOFTRST1 Register Field Descriptions..............................................................................
SOFTRST2 Register Field Descriptions..............................................................................
CLKDIVCTL0 Register Field Descriptions ...........................................................................
CLKSRCSEL0 Register Field Descriptions ..........................................................................
CR4CTL Register Field Descriptions .................................................................................
CLKGATE Register Field Descriptions ...............................................................................
CLKSRCSEL1 Register Field Descriptions ..........................................................................
CURRCLKDIV0 Register Field Descriptions.........................................................................
RTICURRCLKDIV Register Field Descriptions ......................................................................
MEMINITSTART Register Field Descriptions .......................................................................
CURRCLKDIV1 Register Field Descriptions.........................................................................
MEMINITDONE Register Field Descriptions ........................................................................
ECCENMSSGEM Register Field Descriptions ......................................................................
ECCCAPTMSSGEM Register Field Descriptions ...................................................................
ECCENBSSGEM Register Field Descriptions .......................................................................
ECCCAPTBSSGEM Register Field Descriptions ...................................................................
USERMODEEN Register Field Descriptions ........................................................................
NSYSPERUSERMODEN Register Field Descriptions .............................................................
SECURERAMMMI Register Field Descriptions .....................................................................
SECURERAMECC Register Field Descriptions .....................................................................
ESMGATE0 Register Field Descriptions .............................................................................
ESMGATE1 Register Field Descriptions .............................................................................
ESMGATE2 Register Field Descriptions .............................................................................
ESMGATE3 Register Field Descriptions .............................................................................
ESMGATE4 Register Field Descriptions .............................................................................
KEY Register Field Descriptions ......................................................................................
SWIRQA Register Field Descriptions .................................................................................
SWIRQB Register Field Descriptions .................................................................................
MISCCTL0 Register Field Descriptions ..............................................................................
ATCMERRCAPTCTL Register Field Descriptions ..................................................................
B0TCMERRCAPTCTL Register Field Descriptions ................................................................
B1TCMERRCAPTCTL Register Field Descriptions ................................................................
4-824. MEMINITDONESHMEM Register Field Descriptions
4-825.
4-826.
4-827.
4-828.
4-829.
4-830.
4-831.
4-832.
4-833.
4-834.
4-835.
4-836.
4-837.
4-838.
4-839.
4-840.
4-841.
4-842.
4-843.
4-844.
4-845.
4-846.
4-847.
4-848.
4-849.
4-850.
4-851.
4-852.
4-853.
4-854.
4-855.
4-856.
4-857.
4-858.
4-859.
4-860.
4-861.
4-862.
4-863.
4-864.
94
List of Tables
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-865. SOFTCORERST Register Field Descriptions ....................................................................... 1156
4-866. RSTCAUSE Register Field Descriptions ............................................................................. 1157
4-867. RSTCAUSECLR Register Field Descriptions........................................................................ 1158
4-868. SPITRIGSRC Register Field Descriptions ........................................................................... 1159
4-869. CLKINUSE Register Field Descriptions .............................................................................. 1160
4-870. ECCENMSSBSS Register Field Descriptions ....................................................................... 1161
4-871. ECCCAPTMSSBSS Register Field Descriptions
...................................................................
1162
4-872. CLKDIVCTL2 Register Field Descriptions ........................................................................... 1163
4-873. SWIRQC Register Field Descriptions................................................................................. 1164
4-874. MSS_GPCFG_REG Registers ........................................................................................ 1165
4-875. MSS_GPCFG_REG Access Type Codes............................................................................ 1165
4-876. GPCFG0 Register Field Descriptions................................................................................. 1167
4-877. GPCFG1 Register Field Descriptions................................................................................. 1168
4-878. GPCFG2 Register Field Descriptions................................................................................. 1169
4-879. GPCFG3 Register Field Descriptions................................................................................. 1170
4-880. GPCFG4 Register Field Descriptions................................................................................. 1171
4-881. GPCFG6 Register Field Descriptions................................................................................. 1172
4-882. GPCFG11 Register Field Descriptions ............................................................................... 1173
4-883. CCCACFG0 Register Field Descriptions ............................................................................. 1174
4-884. CCCACFG1 Register Field Descriptions ............................................................................. 1175
4-885. CCCACFG2 Register Field Descriptions ............................................................................. 1176
4-886. CCCACFG3 Register Field Descriptions ............................................................................. 1177
4-887. CCCBCFG0 Register Field Descriptions ............................................................................. 1178
4-888. CCCBCFG1 Register Field Descriptions ............................................................................. 1179
4-889. CCCBCFG2 Register Field Descriptions ............................................................................. 1180
4-890. CCCBCFG3 Register Field Descriptions ............................................................................. 1181
4-891. CCCACNTVAL Register Field Descriptions ......................................................................... 1182
4-892. CCCBCNTVAL Register Field Descriptions ......................................................................... 1183
4-893. CCCABERRSTAT Register Field Descriptions...................................................................... 1184
4-894. USERMODEEN Register Field Descriptions ........................................................................ 1185
4-895. EPWMCFG Register Field Descriptions.............................................................................. 1186
4-896. DMMSWINT0 Register Field Descriptions ........................................................................... 1187
4-897. DMMSWINT1 Register Field Descriptions ........................................................................... 1188
4-898. DMMSWINTSEL0 Register Field Descriptions ...................................................................... 1189
4-899. DMMSWINTSEL1 Register Field Descriptions ...................................................................... 1190
4-900. CCCBWDEN Register Field Descriptions ............................................................................ 1191
4-901. GPIOINTREDGESEL Register Field Descriptions .................................................................. 1192
4-902. PWMDMATRIGEN Register Field Descriptions ..................................................................... 1193
4-903. JTAGTXDATA Register Field Descriptions .......................................................................... 1194
4-904. JTAGTXCONTROL Register Field Descriptions .................................................................... 1195
4-905. JTAGRXDATA Register Field Descriptions .......................................................................... 1196
4-906. JTAGTXRXACK Register Field Descriptions ........................................................................ 1197
4-907. JTAGRXCONTROL Register Field Descriptions .................................................................... 1198
4-908. MSS2GEMSWIRQ Register Field Descriptions ..................................................................... 1199
4-909. CSETBFLUSH Register Field Descriptions .......................................................................... 1200
4-910. DSS_REG Registers .................................................................................................... 1201
4-911. DSS_REG Access Type Codes ....................................................................................... 1203
4-912. RTIEVENTCAPTURESEL Register Field Descriptions ............................................................ 1204
4-913. CQCFG1 Register Field Descriptions
................................................................................
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1205
95
www.ti.com
4-914. TPCCPARSTATCFG Register Field Descriptions .................................................................. 1206
4-915. TPTC0WRMPUSTADD0 Register Field Descriptions .............................................................. 1207
4-916. TPTC0WRMPUSTADD1 Register Field Descriptions .............................................................. 1208
4-917. TPTC0WRMPUSTADD2 Register Field Descriptions .............................................................. 1209
4-918. TPTC0WRMPUSTADD3 Register Field Descriptions .............................................................. 1210
4-919. TPTC0WRMPUSTADD4 Register Field Descriptions .............................................................. 1211
4-920. TPTC0WRMPUSTADD5 Register Field Descriptions .............................................................. 1212
4-921. TPTC0WRMPUENDADD0 Register Field Descriptions ............................................................ 1213
4-922. TPTC0WRMPUENDADD1 Register Field Descriptions ............................................................ 1214
4-923. TPTC0WRMPUENDADD2 Register Field Descriptions ............................................................ 1215
4-924. TPTC0WRMPUENDADD3 Register Field Descriptions ............................................................ 1216
4-925. TPTC0WRMPUENDADD4 Register Field Descriptions ............................................................ 1217
4-926. TPTC0WRMPUENDADD5 Register Field Descriptions ............................................................ 1218
4-927. TPTC0WRMPUERRADD Register Field Descriptions ............................................................. 1219
4-928. TPTC0RDMPUSTADD0 Register Field Descriptions............................................................... 1220
4-929. TPTC0RDMPUSTADD1 Register Field Descriptions............................................................... 1221
4-930. TPTC0RDMPUSTADD2 Register Field Descriptions............................................................... 1222
4-931. TPTC0RDMPUSTADD3 Register Field Descriptions............................................................... 1223
4-932. TPTC0RDMPUSTADD4 Register Field Descriptions............................................................... 1224
4-933. TPTC0RDMPUSTADD5 Register Field Descriptions............................................................... 1225
4-934. TPTC0RDMPUENDADD0 Register Field Descriptions ............................................................ 1226
4-935. TPTC0RDMPUENDADD1 Register Field Descriptions ............................................................ 1227
4-936. TPTC0RDMPUENDADD2 Register Field Descriptions ............................................................ 1228
4-937. TPTC0RDMPUENDADD3 Register Field Descriptions ............................................................ 1229
4-938. TPTC0RDMPUENDADD4 Register Field Descriptions ............................................................ 1230
4-939. TPTC0RDMPUENDADD5 Register Field Descriptions ............................................................ 1231
4-940. TPTC0RDMPUERRADD Register Field Descriptions .............................................................. 1232
4-941. TPTC1WRMPUSTADD0 Register Field Descriptions .............................................................. 1233
4-942. TPTC1WRMPUSTADD1 Register Field Descriptions .............................................................. 1234
4-943. TPTC1WRMPUSTADD2 Register Field Descriptions .............................................................. 1235
4-944. TPTC1WRMPUSTADD3 Register Field Descriptions .............................................................. 1236
4-945. TPTC1WRMPUSTADD4 Register Field Descriptions .............................................................. 1237
4-946. TPTC1WRMPUSTADD5 Register Field Descriptions .............................................................. 1238
4-947. TPTC1WRMPUENDADD0 Register Field Descriptions ............................................................ 1239
4-948. TPTC1WRMPUENDADD1 Register Field Descriptions ............................................................ 1240
4-949. TPTC1WRMPUENDADD2 Register Field Descriptions ............................................................ 1241
4-950. TPTC1WRMPUENDADD3 Register Field Descriptions ............................................................ 1242
4-951. TPTC1WRMPUENDADD4 Register Field Descriptions ............................................................ 1243
4-952. TPTC1WRMPUENDADD5 Register Field Descriptions ............................................................ 1244
4-953. TPTC1WRMPUERRADD Register Field Descriptions ............................................................. 1245
4-954. TPTC1RDMPUSTADD0 Register Field Descriptions............................................................... 1246
4-955. TPTC1RDMPUSTADD1 Register Field Descriptions............................................................... 1247
4-956. TPTC1RDMPUSTADD2 Register Field Descriptions............................................................... 1248
4-957. TPTC1RDMPUSTADD3 Register Field Descriptions............................................................... 1249
4-958. TPTC1RDMPUSTADD4 Register Field Descriptions............................................................... 1250
4-959. TPTC1RDMPUSTADD5 Register Field Descriptions............................................................... 1251
4-960. TPTC1RDMPUENDADD0 Register Field Descriptions ............................................................ 1252
4-961. TPTC1RDMPUENDADD1 Register Field Descriptions ............................................................ 1253
4-962. TPTC1RDMPUENDADD2 Register Field Descriptions ............................................................ 1254
96
List of Tables
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-963. TPTC1RDMPUENDADD3 Register Field Descriptions ............................................................ 1255
4-964. TPTC1RDMPUENDADD4 Register Field Descriptions ............................................................ 1256
4-965. TPTC1RDMPUENDADD5 Register Field Descriptions ............................................................ 1257
4-966. TPTC1RDMPUERRADD Register Field Descriptions .............................................................. 1258
4-967. TPTCMPUVALIDCFG Register Field Descriptions ................................................................. 1259
4-968. TPTCMPUENCFG Register Field Descriptions ..................................................................... 1260
............................................................
............................................................
4-971. TESTPATTERNRX3ICFG Register Field Descriptions ............................................................
4-972. TESTPATTERNRX4ICFG Register Field Descriptions ............................................................
4-973. TESTPATTERNRX1QCFG Register Field Descriptions ...........................................................
4-974. TESTPATTERNRX2QCFG Register Field Descriptions ...........................................................
4-975. TESTPATTERNRX3QCFG Register Field Descriptions ...........................................................
4-976. TESTPATTERNRX4QCFG Register Field Descriptions ...........................................................
4-977. TESTPATTERNVLDCFG Register Field Descriptions .............................................................
4-978. TPCC1PARSTATCFG Register Field Descriptions .................................................................
4-979. DMMSWINT1 Register Field Descriptions ...........................................................................
4-980. DSSINTRCFG Register Field Descriptions ..........................................................................
4-981. MPUMSTIDCFG1 Register Field Descriptions ......................................................................
4-982. MPUMSTIDCFG2 Register Field Descriptions ......................................................................
4-983. MPUMSTIDCFG3 Register Field Descriptions ......................................................................
4-984. HSRAM1ECCCFG Register Field Descriptions .....................................................................
4-985. DATATRRAMECCCFG Register Field Descriptions ...............................................................
4-986. ADCBUFPINGECCCFG Register Field Descriptions...............................................................
4-987. ADCBUFPONGECCCFG Register Field Descriptions .............................................................
4-988. UMAP0PARITYCFG1 Register Field Descriptions .................................................................
4-989. UMAP0PARITYCFG2 Register Field Descriptions .................................................................
4-990. UMAP0PARITYCFG3 Register Field Descriptions .................................................................
4-991. UMAP1PARITYCFG1 Register Field Descriptions .................................................................
4-992. UMAP1PARITYCFG2 Register Field Descriptions .................................................................
4-993. UMAP1PARITYCFG3 Register Field Descriptions .................................................................
4-994. ESMGRP2MASKCFG Register Field Descriptions .................................................................
4-995. L2MEMINITCFG1 Register Field Descriptions ......................................................................
4-996. L2MEMINITCFG2 Register Field Descriptions ......................................................................
4-997. GEMRSTCAUSE Register Field Descriptions .......................................................................
4-998. GEMPWRSMCFG4 Register Field Descriptions ....................................................................
4-999. PWRSMWAKEMASK0 Register Field Descriptions ................................................................
4-1000. PWRSMWAKEMASK1 Register Field Descriptions ...............................................................
4-1001. PWRSMWAKEMASK2 Register Field Descriptions ...............................................................
4-1002. PWRSMMISEVTMASK0 Register Field Descriptions .............................................................
4-1003. PWRSMMISEVTMASK1 Register Field Descriptions .............................................................
4-1004. PWRSMMISEVTMASK2 Register Field Descriptions .............................................................
4-1005. PWRSMWAKESRCSTAT0 Register Field Descriptions ..........................................................
4-1006. PWRSMWAKESRCSTAT1 Register Field Descriptions ..........................................................
4-1007. PWRSMWAKESRCSTAT2 Register Field Descriptions ..........................................................
4-1008. PWRSMEVNTMONSTAT0 Register Field Descriptions ..........................................................
4-1009. PWRSMEVNTMONSTAT1 Register Field Descriptions ..........................................................
4-1010. PWRSMEVNTMONSTAT2 Register Field Descriptions ..........................................................
4-1011. PWRSMWAKESRCSTATCLR0 Register Field Descriptions ....................................................
4-969. TESTPATTERNRX1ICFG Register Field Descriptions
1261
4-970. TESTPATTERNRX2ICFG Register Field Descriptions
1262
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
97
www.ti.com
....................................................
PWRSMWAKESRCSTATCLR2 Register Field Descriptions ....................................................
ADCBUFCFG1 Register Field Descriptions ........................................................................
ADCBUFCFG2 Register Field Descriptions ........................................................................
ADCBUFCFG3 Register Field Descriptions ........................................................................
ADCBUFCFG4 Register Field Descriptions ........................................................................
STCPBISTSMCFG1 Register Field Descriptions ..................................................................
STCPBISTSMCFG2 Register Field Descriptions ..................................................................
RTI2EVENTCAPTURESEL Register Field Descriptions .........................................................
DSSMISC5 Register Field Descriptions ............................................................................
DSS_REG2 Registers .................................................................................................
DSS_REG2 Access Type Codes ....................................................................................
TPTC2WRMPUSTADD0 Register Field Descriptions.............................................................
TPTC2WRMPUSTADD1 Register Field Descriptions.............................................................
TPTC2WRMPUSTADD2 Register Field Descriptions.............................................................
TPTC2WRMPUSTADD3 Register Field Descriptions.............................................................
TPTC2WRMPUSTADD4 Register Field Descriptions.............................................................
TPTC2WRMPUSTADD5 Register Field Descriptions.............................................................
TPTC2WRMPUENDADD0 Register Field Descriptions ..........................................................
TPTC2WRMPUENDADD1 Register Field Descriptions ..........................................................
TPTC2WRMPUENDADD2 Register Field Descriptions ..........................................................
TPTC2WRMPUENDADD3 Register Field Descriptions ..........................................................
TPTC2WRMPUENDADD4 Register Field Descriptions ..........................................................
TPTC2WRMPUENDADD5 Register Field Descriptions ..........................................................
TPTC2WRMPUERRADD Register Field Descriptions ............................................................
TPTC2RDMPUSTADD0 Register Field Descriptions .............................................................
TPTC2RDMPUSTADD1 Register Field Descriptions .............................................................
TPTC2RDMPUSTADD2 Register Field Descriptions .............................................................
TPTC2RDMPUSTADD3 Register Field Descriptions .............................................................
TPTC2RDMPUSTADD4 Register Field Descriptions .............................................................
TPTC2RDMPUSTADD5 Register Field Descriptions .............................................................
TPTC2RDMPUENDADD0 Register Field Descriptions ...........................................................
TPTC2RDMPUENDADD1 Register Field Descriptions ...........................................................
TPTC2RDMPUENDADD2 Register Field Descriptions ...........................................................
TPTC2RDMPUENDADD3 Register Field Descriptions ...........................................................
TPTC2RDMPUENDADD4 Register Field Descriptions ...........................................................
TPTC2RDMPUENDADD5 Register Field Descriptions ...........................................................
TPTC2RDMPUERRADD Register Field Descriptions ............................................................
TPTC3WRMPUSTADD0 Register Field Descriptions.............................................................
TPTC3WRMPUSTADD1 Register Field Descriptions.............................................................
TPTC3WRMPUSTADD2 Register Field Descriptions.............................................................
TPTC3WRMPUSTADD3 Register Field Descriptions.............................................................
TPTC3WRMPUSTADD4 Register Field Descriptions.............................................................
TPTC3WRMPUSTADD5 Register Field Descriptions.............................................................
TPTC3WRMPUENDADD0 Register Field Descriptions ..........................................................
TPTC3WRMPUENDADD1 Register Field Descriptions ..........................................................
TPTC3WRMPUENDADD2 Register Field Descriptions ..........................................................
TPTC3WRMPUENDADD3 Register Field Descriptions ..........................................................
TPTC3WRMPUENDADD4 Register Field Descriptions ..........................................................
4-1012. PWRSMWAKESRCSTATCLR1 Register Field Descriptions
4-1013.
4-1014.
4-1015.
4-1016.
4-1017.
4-1018.
4-1019.
4-1020.
4-1021.
4-1022.
4-1023.
4-1024.
4-1025.
4-1026.
4-1027.
4-1028.
4-1029.
4-1030.
4-1031.
4-1032.
4-1033.
4-1034.
4-1035.
4-1036.
4-1037.
4-1038.
4-1039.
4-1040.
4-1041.
4-1042.
4-1043.
4-1044.
4-1045.
4-1046.
4-1047.
4-1048.
4-1049.
4-1050.
4-1051.
4-1052.
4-1053.
4-1054.
4-1055.
4-1056.
4-1057.
4-1058.
4-1059.
4-1060.
98
List of Tables
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-1061. TPTC3WRMPUENDADD5 Register Field Descriptions .......................................................... 1354
4-1062. TPTC3WRMPUERRADD Register Field Descriptions ............................................................ 1355
4-1063. TPTC3RDMPUSTADD0 Register Field Descriptions ............................................................. 1356
4-1064. TPTC3RDMPUSTADD1 Register Field Descriptions ............................................................. 1357
4-1065. TPTC3RDMPUSTADD2 Register Field Descriptions ............................................................. 1358
4-1066. TPTC3RDMPUSTADD3 Register Field Descriptions ............................................................. 1359
4-1067. TPTC3RDMPUSTADD4 Register Field Descriptions ............................................................. 1360
4-1068. TPTC3RDMPUSTADD5 Register Field Descriptions ............................................................. 1361
4-1069. TPTC3RDMPUENDADD0 Register Field Descriptions ........................................................... 1362
4-1070. TPTC3RDMPUENDADD1 Register Field Descriptions ........................................................... 1363
4-1071. TPTC3RDMPUENDADD2 Register Field Descriptions ........................................................... 1364
4-1072. TPTC3RDMPUENDADD3 Register Field Descriptions ........................................................... 1365
4-1073. TPTC3RDMPUENDADD4 Register Field Descriptions ........................................................... 1366
4-1074. TPTC3RDMPUENDADD5 Register Field Descriptions ........................................................... 1367
4-1075. TPTC3RDMPUERRADD Register Field Descriptions
............................................................
1368
4-1076. TPTCMPUVALIDCFG2 Register Field Descriptions .............................................................. 1369
4-1077. TPTCMPUENCFG2 Register Field Descriptions .................................................................. 1370
..........................................................................
..........................................................................
4-1080. DSS2MSSSWIRQ Register Field Descriptions ....................................................................
7-1.
Arbitration According to Priority Queues and Priority Schemes...................................................
7-2.
Maximum Number of DMA Transactions per Channel in Non-Bypass Mode ...................................
7-3.
Maximum Number of DMA Transactions per Channel in Bypass Mode .........................................
7-4.
Control Packet RAM ....................................................................................................
7-5.
Control Packet RAM ....................................................................................................
7-6.
Parity RAM ...............................................................................................................
7-7.
DMA Control Registers .................................................................................................
7-8.
MSS_DMA_REG Access Type Codes ...............................................................................
7-9.
GCTRL Register Field Descriptions ..................................................................................
7-10. PEND Register Field Descriptions ....................................................................................
7-11. FBREG Register Field Descriptions ..................................................................................
7-12. DMASTAT Register Field Descriptions ...............................................................................
7-13. HWCHENAS Register Field Descriptions ............................................................................
7-14. HWCHENAR Register Field Descriptions ............................................................................
7-15. SWCHENAS Register Field Descriptions ............................................................................
7-16. SWCHENAR Register Field Descriptions ............................................................................
7-17. CHPRIOS Register Field Descriptions ...............................................................................
7-18. CHPRIOR Register Field Descriptions ...............................................................................
7-19. GCHIENAS Register Field Descriptions..............................................................................
7-20. GCHIENAR Register Field Descriptions .............................................................................
7-21. DREQASI0 Register Field Descriptions ..............................................................................
7-22. DREQASI1 Register Field Descriptions ..............................................................................
7-23. DREQASI2 Register Field Descriptions ..............................................................................
7-24. DREQASI3 Register Field Descriptions ..............................................................................
7-25. DREQASI4 Register Field Descriptions ..............................................................................
7-26. DREQASI5 Register Field Descriptions ..............................................................................
7-27. DREQASI6 Register Field Descriptions ..............................................................................
7-28. DREQASI7 Register Field Descriptions ..............................................................................
7-29. PAR0 Register Field Descriptions.....................................................................................
4-1078. L3ECCCFG1 Register Field Descriptions
1371
4-1079. L3ECCCFG2 Register Field Descriptions
1372
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1373
1389
1397
1397
1400
1400
1400
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
99
www.ti.com
7-30.
PAR1 Register Field Descriptions..................................................................................... 1425
7-31.
PAR2 Register Field Descriptions..................................................................................... 1426
7-32.
PAR3 Register Field Descriptions..................................................................................... 1427
7-33.
FTCMAP Register Field Descriptions................................................................................. 1428
7-34.
LFSMAP Register Field Descriptions ................................................................................. 1429
7-35.
HBCMAP Register Field Descriptions ................................................................................ 1430
7-36.
BTCMAP Register Field Descriptions
7-37.
BERMAP Register Field Descriptions ................................................................................ 1432
7-38.
FTCINTENAS Register Field Descriptions ........................................................................... 1433
7-39.
FTCINTENAR Register Field Descriptions........................................................................... 1434
7-40.
LFSINTENAS Register Field Descriptions ........................................................................... 1435
7-41.
LFSINTENAR Register Field Descriptions ........................................................................... 1436
7-42.
HBCINTENAS Register Field Descriptions .......................................................................... 1437
7-43.
HBCINTENAR Register Field Descriptions .......................................................................... 1438
7-44.
BTCINTENAS Register Field Descriptions........................................................................... 1439
7-45.
BTCINTENAR Register Field Descriptions
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
100
................................................................................
..........................................................................
GINTFLAG Register Field Descriptions ..............................................................................
FTCFLAG Register Field Descriptions ...............................................................................
LFSFLAG Register Field Descriptions ................................................................................
HBCFLAG Register Field Descriptions ...............................................................................
BTCFLAG Register Field Descriptions ...............................................................................
BERFLAG Register Field Descriptions ...............................................................................
FTCAOFFSET Register Field Descriptions ..........................................................................
LFSAOFFSET Register Field Descriptions ..........................................................................
HBCAOFFSET Register Field Descriptions .........................................................................
BTCAOFFSET Register Field Descriptions ..........................................................................
BERAOFFSET Register Field Descriptions ..........................................................................
FTCBOFFSET Register Field Descriptions ..........................................................................
LFSBOFFSET Register Field Descriptions ..........................................................................
HBCBOFFSET Register Field Descriptions .........................................................................
BTCBOFFSET Register Field Descriptions ..........................................................................
BERBOFFSET Register Field Descriptions ..........................................................................
PTCRL Register Field Descriptions ...................................................................................
RTCTRL Register Field Descriptions .................................................................................
DCTRL Register Field Descriptions ...................................................................................
WPR Register Field Descriptions .....................................................................................
WMR Register Field Descriptions .....................................................................................
PAACSADDR Register Field Descriptions ...........................................................................
PAACDADDR Register Field Descriptions ...........................................................................
PAACTC Register Field Descriptions .................................................................................
PBACSADDR Register Field Descriptions ...........................................................................
PBACDADDR Register Field Descriptions ...........................................................................
PBACTC Register Field Descriptions .................................................................................
DMAPCR Register Field Descriptions ................................................................................
DMAPAR Register Field Descriptions ................................................................................
DMAMPCTRL Register Field Descriptions...........................................................................
DMAMPST Register Field Descriptions ..............................................................................
DMAMPR0S Register Field Descriptions ............................................................................
DMAMPR0E Register Field Descriptions ............................................................................
List of Tables
1431
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1473
1474
1475
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
10-1.
10-2.
10-3.
10-4.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
............................................................................
DMAMPR1E Register Field Descriptions ............................................................................
DMAMPR2S Register Field Descriptions ............................................................................
DMAMPR2E Register Field Descriptions ............................................................................
DMAMPR3S Register Field Descriptions ............................................................................
DMAMPR3E Register Field Descriptions ............................................................................
Initial Source Address (ISADDR) Field Descriptions ...............................................................
Initial Destination Address Register (IDADDR) Field Descriptions ...............................................
Initial Transfer Count Register (ITCOUNT) Field Descriptions ....................................................
Channel Control Register (CHCTRL) Field Descriptions...........................................................
Element Index Offset Register (EIOFF) Field Descriptions .......................................................
Frame Index Offset Register (FIOFF) Field Descriptions ..........................................................
Current Source Address Register (CSADDR) Field Descriptions ................................................
Current Destination Address Register (CDADDR) Field Descriptions ...........................................
Current Transfer Count Register (CTCOUNT) Field Descriptions ................................................
ECC Syndrome Table ..................................................................................................
ECC Error Bits for Syndrome Decode ................................................................................
CPU Reads - Address Bit 10 Selects Between Normal Data and ECC Bits ....................................
CPU Writes - Address Bit 10 Selects Between Normal Data and ECC Bits ....................................
VIM Control Registers ..................................................................................................
Interrupt Vector Table ECC Status Register (ECCSTAT) Field Descriptions ...................................
Interrupt Vector Table ECC Control Register (ECCCTL) Field Descriptions ....................................
Uncorrectable Error Address Register (UERRADDR) Field Descriptions .......................................
Fallback Vector Address Register (FBVECADDR) Field Descriptions ...........................................
Single Bit Error Address Register (SBERRADDR) Field Descriptions ...........................................
Interrupt Dispatch .......................................................................................................
IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions ...............................................
FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions ................................................
FIQ/IRQ Program Control Registers (FIRQPR) Field Descriptions ..............................................
Pending Interrupt Read Location Registers (INTREQ) Field Descriptions ......................................
Interrupt Enable Set Registers (REQENASET) Field Descriptions ..............................................
Interrupt Enable Clear Registers (REQENACLR) Field Descriptions ............................................
Wake-Up Enable Set Registers (WAKEENASET) Field Descriptions ............................................
Wake-Up Enable Clear Registers (WAKEENACLR) Field Descriptions .........................................
IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions.................................................
FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions .................................................
Capture Event Register (CAPEVT) Field Descriptions .............................................................
Interrupt Control Registers Organization .............................................................................
Interrupt Control Registers (CHANCTRL[0:31]) Field Descriptions ...............................................
MSS_TOPRCM Registers..............................................................................................
MSS_TOPRCM Registers..............................................................................................
Register Programming ..................................................................................................
Register Programming ..................................................................................................
EDMA Parameter RAM Contents .....................................................................................
EDMA Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ...................................................................................
Parameter Updates in EDMA_TPCC (for Non-Null, Non-Dummy PaRAM Set) ................................
Expected Number of Transfers for Non-Null Transfer ..............................................................
Shadow Region Registers .............................................................................................
DMAMPR1S Register Field Descriptions
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1476
1477
1478
1479
1480
1481
1482
1482
1483
1484
1485
1485
1486
1486
1487
1498
1498
1499
1499
1506
1507
1508
1509
1509
1510
1510
1511
1511
1512
1513
1514
1515
1516
1517
1518
1518
1519
1520
1520
1529
1529
1531
1532
1544
1546
1550
1551
1558
1562
101
www.ti.com
12-7.
Chain Event Triggers ................................................................................................... 1565
12-8.
EDMA Transfer Completion Interrupts
12-9.
EDMA Error Interrupts .................................................................................................. 1565
............................................
Number of Interrupts ....................................................................................................
Allowed Accesses .......................................................................................................
MPPA Registers to Region Assignment ..............................................................................
Example Access Denied ...............................................................................................
Example Access Allowed...............................................................................................
Read/Write Command Optimization Rules...........................................................................
EDMA Transfer Controller Configurations ...........................................................................
Debug Checklist .........................................................................................................
EDMA_TPCC Registers ................................................................................................
EDMA_TPCC_PID Register Field Descriptions .....................................................................
EDMA_TPCC_CCCFG Register Field Descriptions ................................................................
EDMA_TPCC_QCHMAPN Register Field Descriptions ............................................................
EDMA_TPCC_DMAQNUMN Register Field Descriptions .........................................................
EDMA_TPCC_QDMAQNUM Register Field Descriptions .........................................................
EDMA_TPCC_QUETCMAP Register Field Descriptions ..........................................................
EDMA_TPCC_QUEPRI Register Field Descriptions ...............................................................
EDMA_TPCC_EMR Register Field Descriptions ...................................................................
EDMA_TPCC_EMRH Register Field Descriptions..................................................................
EDMA_TPCC_EMCR Register Field Descriptions..................................................................
EDMA_TPCC_EMCRH Register Field Descriptions................................................................
EDMA_TPCC_QEMR Register Field Descriptions .................................................................
EDMA_TPCC_QEMCR Register Field Descriptions ...............................................................
EDMA_TPCC_CCERR Register Field Descriptions ................................................................
EDMA_TPCC_CCERRCLR Register Field Descriptions ..........................................................
EDMA_TPCC_EEVAL Register Field Descriptions .................................................................
EDMA_TPCC_DRAEN Register Field Descriptions ................................................................
EDMA_TPCC_DRAEM Register Field Descriptions ................................................................
EDMA_TPCC_DRAEHM Register Field Descriptions ..............................................................
EDMA_TPCC_QRAEN Register Field Descriptions ................................................................
EDMA_TPCC_QNEM Register Field Descriptions .................................................................
EDMA_TPCC_QNE0 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE1 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE2 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE3 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE4 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE5 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE6 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE7 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE8 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE9 Register Field Descriptions ..................................................................
EDMA_TPCC_QNE10 Register Field Descriptions .................................................................
EDMA_TPCC_QNE11 Register Field Descriptions .................................................................
EDMA_TPCC_QNE12 Register Field Descriptions .................................................................
EDMA_TPCC_QNE13 Register Field Descriptions .................................................................
EDMA_TPCC_QNE14 Register Field Descriptions .................................................................
1565
12-10. Transfer Complete Code (TCC) to EDMA_TPCC Interrupt Mapping
1566
12-11.
1567
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
12-42.
12-43.
12-44.
12-45.
12-46.
12-47.
12-48.
12-49.
12-50.
12-51.
12-52.
12-53.
12-54.
12-55.
102
...............................................................................
List of Tables
1573
1573
1574
1576
1580
1582
1593
1596
1599
1600
1602
1603
1604
1605
1606
1607
1609
1611
1613
1615
1616
1617
1619
1620
1621
1622
1624
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
12-56. EDMA_TPCC_QNE15 Register Field Descriptions ................................................................. 1643
12-57. EDMA_TPCC_QSTATN Register Field Descriptions............................................................... 1644
12-58. EDMA_TPCC_QWMTHRA Register Field Descriptions ........................................................... 1645
12-59. EDMA_TPCC_CCSTAT Register Field Descriptions ............................................................... 1646
12-60. EDMA_TPCC_AETCTL Register Field Descriptions ............................................................... 1648
12-61. EDMA_TPCC_AETSTAT Register Field Descriptions ............................................................. 1649
12-62. EDMA_TPCC_AETCMD Register Field Descriptions .............................................................. 1650
12-63. EDMA_TPCC_ER Register Field Descriptions ...................................................................... 1651
12-64. EDMA_TPCC_ERH Register Field Descriptions .................................................................... 1653
12-65. EDMA_TPCC_ECR Register Field Descriptions .................................................................... 1655
12-66. EDMA_TPCC_ECRH Register Field Descriptions .................................................................. 1657
12-67. EDMA_TPCC_ESR Register Field Descriptions .................................................................... 1659
12-68. EDMA_TPCC_ESRH Register Field Descriptions .................................................................. 1661
12-69. EDMA_TPCC_CER Register Field Descriptions .................................................................... 1663
12-70. EDMA_TPCC_CERH Register Field Descriptions .................................................................. 1665
12-71. EDMA_TPCC_EER Register Field Descriptions .................................................................... 1667
12-72. EDMA_TPCC_EERH Register Field Descriptions .................................................................. 1669
12-73. EDMA_TPCC_EECR Register Field Descriptions .................................................................. 1671
12-74. EDMA_TPCC_EECRH Register Field Descriptions ................................................................ 1673
12-75. EDMA_TPCC_EESR Register Field Descriptions .................................................................. 1675
12-76. EDMA_TPCC_EESRH Register Field Descriptions ................................................................ 1677
12-77. EDMA_TPCC_SER Register Field Descriptions .................................................................... 1679
12-78. EDMA_TPCC_SERH Register Field Descriptions .................................................................. 1681
12-79. EDMA_TPCC_SECR Register Field Descriptions .................................................................. 1683
12-80. EDMA_TPCC_SECRH Register Field Descriptions ................................................................ 1685
12-81. EDMA_TPCC_IER Register Field Descriptions ..................................................................... 1687
12-82. EDMA_TPCC_IERH Register Field Descriptions ................................................................... 1689
12-83. EDMA_TPCC_IECR Register Field Descriptions ................................................................... 1691
12-84. EDMA_TPCC_IECRH Register Field Descriptions ................................................................. 1693
12-85. EDMA_TPCC_IESR Register Field Descriptions ................................................................... 1695
12-86. EDMA_TPCC_IESRH Register Field Descriptions ................................................................. 1697
12-87. EDMA_TPCC_IPR Register Field Descriptions ..................................................................... 1699
12-88. EDMA_TPCC_IPRH Register Field Descriptions ................................................................... 1701
12-89. EDMA_TPCC_ICR Register Field Descriptions ..................................................................... 1703
12-90. EDMA_TPCC_ICRH Register Field Descriptions ................................................................... 1705
12-91. EDMA_TPCC_IEVAL Register Field Descriptions .................................................................. 1707
12-92. EDMA_TPCC_QER Register Field Descriptions .................................................................... 1708
12-93. EDMA_TPCC_QEER Register Field Descriptions .................................................................. 1709
12-94. EDMA_TPCC_QEECR Register Field Descriptions ................................................................ 1710
12-95. EDMA_TPCC_QEESR Register Field Descriptions ................................................................ 1711
12-96. EDMA_TPCC_QSER Register Field Descriptions .................................................................. 1712
12-97. EDMA_TPCC_QSECR Register Field Descriptions ................................................................ 1713
12-98. EDMA_TPCC_SHADOW_N Register Field Descriptions .......................................................... 1714
12-99. EDMA_TPCC_ER_RN Register Field Descriptions ................................................................ 1715
12-100. EDMA_TPCC_ERH_RN Register Field Descriptions ............................................................. 1717
12-101. EDMA_TPCC_ECR_RN Register Field Descriptions ............................................................. 1719
12-102. EDMA_TPCC_ECRH_RN Register Field Descriptions ........................................................... 1721
12-103. EDMA_TPCC_ESR_RN Register Field Descriptions ............................................................. 1723
12-104. EDMA_TPCC_ESRH_RN Register Field Descriptions ........................................................... 1725
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
103
www.ti.com
12-105. EDMA_TPCC_CER_RN Register Field Descriptions ............................................................. 1727
12-106. EDMA_TPCC_CERH_RN Register Field Descriptions ........................................................... 1729
12-107. EDMA_TPCC_EER_RN Register Field Descriptions ............................................................. 1731
12-108. EDMA_TPCC_EERH_RN Register Field Descriptions ........................................................... 1733
12-109. EDMA_TPCC_EECR_RN Register Field Descriptions ........................................................... 1735
12-110. EDMA_TPCC_EECRH_RN Register Field Descriptions ......................................................... 1737
...........................................................
.........................................................
EDMA_TPCC_SER_RN Register Field Descriptions .............................................................
EDMA_TPCC_SERH_RN Register Field Descriptions ...........................................................
EDMA_TPCC_SECR_RN Register Field Descriptions ...........................................................
EDMA_TPCC_SECRH_RN Register Field Descriptions .........................................................
EDMA_TPCC_IER_RN Register Field Descriptions ..............................................................
EDMA_TPCC_IERH_RN Register Field Descriptions ............................................................
EDMA_TPCC_IECR_RN Register Field Descriptions ............................................................
EDMA_TPCC_IECRH_RN Register Field Descriptions ..........................................................
EDMA_TPCC_IESR_RN Register Field Descriptions ............................................................
EDMA_TPCC_IESRH_RN Register Field Descriptions ..........................................................
EDMA_TPCC_IPR_RN Register Field Descriptions ..............................................................
EDMA_TPCC_IPRH_RN Register Field Descriptions ............................................................
EDMA_TPCC_ICR_RN Register Field Descriptions ..............................................................
EDMA_TPCC_ICRH_RN Register Field Descriptions ............................................................
EDMA_TPCC_IEVAL_RN Register Field Descriptions ...........................................................
EDMA_TPCC_QER_RN Register Field Descriptions .............................................................
EDMA_TPCC_QEER_RN Register Field Descriptions ...........................................................
EDMA_TPCC_QEECR_RN Register Field Descriptions .........................................................
EDMA_TPCC_QEESR_RN Register Field Descriptions .........................................................
EDMA_TPCC_QSER_RN Register Field Descriptions ...........................................................
EDMA_TPCC_QSECR_RN Register Field Descriptions .........................................................
EDMA_TPCC_PARAMSET Register Field Descriptions .........................................................
EDMA_TPCC_OPT Register Field Descriptions...................................................................
EDMA_TPCC_SRC Register Field Descriptions ..................................................................
EDMA_TPCC_ABCNT Register Field Descriptions ...............................................................
EDMA_TPCC_DST Register Field Descriptions ...................................................................
EDMA_TPCC_BIDX Register Field Descriptions ..................................................................
EDMA_TPCC_LNK Register Field Descriptions ...................................................................
EDMA_TPCC_CIDX Register Field Descriptions ..................................................................
EDMA_TPCC_CCNT Register Field Descriptions .................................................................
EDMA_TPTC Registers ...............................................................................................
EDMA_TPTC_PID Register Field Descriptions ....................................................................
EDMA_TPTC_TCCFG Register Field Descriptions ...............................................................
EDMA_TPTC_TCSTAT Register Field Descriptions ..............................................................
EDMA_TPTC_INTSTAT Register Field Descriptions .............................................................
EDMA_TPTC_INTEN Register Field Descriptions ................................................................
EDMA_TPTC_INTCLR Register Field Descriptions ...............................................................
EDMA_TPTC_INTCMD Register Field Descriptions ..............................................................
EDMA_TPTC_ERRSTAT Register Field Descriptions ............................................................
EDMA_TPTC_ERREN Register Field Descriptions ...............................................................
EDMA_TPTC_ERRCLR Register Field Descriptions .............................................................
12-111. EDMA_TPCC_EESR_RN Register Field Descriptions
1741
12-113.
1743
12-114.
12-115.
12-116.
12-117.
12-118.
12-119.
12-120.
12-121.
12-122.
12-123.
12-124.
12-125.
12-126.
12-127.
12-128.
12-129.
12-130.
12-131.
12-132.
12-133.
12-134.
12-135.
12-136.
12-137.
12-138.
12-139.
12-140.
12-141.
12-142.
12-143.
12-144.
12-145.
12-146.
12-147.
12-148.
12-149.
12-150.
12-151.
12-152.
12-153.
104
1739
12-112. EDMA_TPCC_EESRH_RN Register Field Descriptions
List of Tables
1745
1747
1749
1751
1753
1755
1757
1759
1761
1763
1765
1767
1769
1771
1772
1773
1774
1775
1776
1777
1778
1779
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
12-154. EDMA_TPTC_ERRDET Register Field Descriptions ............................................................. 1799
12-155. EDMA_TPTC_ERRCMD Register Field Descriptions............................................................. 1800
12-156. EDMA_TPTC_RDRATE Register Field Descriptions ............................................................. 1801
12-157. EDMA_TPTC_POPT Register Field Descriptions ................................................................. 1802
12-158. EDMA_TPTC_PSRC Register Field Descriptions ................................................................. 1803
12-159. EDMA_TPTC_PCNT Register Field Descriptions ................................................................. 1804
12-160. EDMA_TPTC_PDST Register Field Descriptions ................................................................. 1805
12-161. EDMA_TPTC_PBIDX Register Field Descriptions ................................................................ 1806
12-162. EDMA_TPTC_PMPPRXY Register Field Descriptions ........................................................... 1807
12-163. EDMA_TPTC_SAOPT Register Field Descriptions ............................................................... 1808
12-164. EDMA_TPTC_SASRC Register Field Descriptions ............................................................... 1809
12-165. EDMA_TPTC_SACNT Register Field Descriptions ............................................................... 1810
..............................................................
.........................................................
12-168. EDMA_TPTC_SACNTRLD Register Field Descriptions ..........................................................
12-169. EDMA_TPTC_SASRCBREF Register Field Descriptions ........................................................
12-170. EDMA_TPTC_SADSTBREF Register Field Descriptions ........................................................
12-171. EDMA_TPTC_DFCNTRLD Register Field Descriptions ..........................................................
12-172. EDMA_TPTC_DFSRCBREF Register Field Descriptions ........................................................
12-173. EDMA_TPTC_DFOPT Register Field Descriptions ...............................................................
12-174. EDMA_TPTC_DFSRC Register Field Descriptions ...............................................................
12-175. EDMA_TPTC_DFCNT Register Field Descriptions ...............................................................
12-176. EDMA_TPTC_DFDST Register Field Descriptions ...............................................................
12-177. EDMA_TPTC_DFBIDX Register Field Descriptions ..............................................................
12-178. EDMA_TPTC_DFMPPRXY Register Field Descriptions .........................................................
13-1. ADC Buffer Single-Chirp and Multi-Chirp Mode Programming Sequence .......................................
13-2. ADC Buffer Continuous Mode Programming Sequence ...........................................................
13-3. Non-Interleaved Data Format ..........................................................................................
14-1. Main Sequence – PRCM and Global Configuration ................................................................
14-2. Main Sequence – CBUFF LVDS Static Configuration..............................................................
14-3. Main Sequence – CBUFF Linklist .....................................................................................
14-4. DSS_CBUFF Registers.................................................................................................
14-5. DSS_CBUFF Access Type Codes ....................................................................................
14-6. CONFIG_REG_0 Register Field Descriptions .......................................................................
14-7. CFG_SPHDR_ADDRESS Register Field Descriptions ............................................................
14-8. CFG_CMD_HSVAL Register Field Descriptions ....................................................................
14-9. CFG_CMD_HEVAL Register Field Descriptions ....................................................................
14-10. CFG_CMD_VSVAL Register Field Descriptions ....................................................................
14-11. CFG_CMD_VEVAL Register Field Descriptions ....................................................................
14-12. CFG_LPHDR_ADDRESS Register Field Descriptions .............................................................
14-13. CFG_CHIRPS_PER_FRAME Register Field Descriptions ........................................................
14-14. CFG_FIFO_FREE_THRESHOLD Register Field Descriptions ...................................................
14-15. CFG_LPPYLD_ADDRESS Register Field Descriptions............................................................
14-16. CFG_DATA_LL0 Register Field Descriptions .......................................................................
14-17. CFG_DATA_LL0_LPHDR_VAL Register Field Descriptions ......................................................
14-18. CFG_DATA_LL0_THRESHOLD Register Field Descriptions .....................................................
14-19. CFG_DATA_LL1 Register Field Descriptions .......................................................................
14-20. CFG_DATA_LL1_LPHDR_VAL Register Field Descriptions ......................................................
14-21. CFG_DATA_LL1_THRESHOLD Register Field Descriptions .....................................................
12-166. EDMA_TPTC_SABIDX Register Field Descriptions
1811
12-167. EDMA_TPTC_SAMPPRXY Register Field Descriptions
1812
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1826
1827
1829
1838
1839
1839
1841
1844
1845
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
105
www.ti.com
14-22. CFG_DATA_LL2 Register Field Descriptions ....................................................................... 1862
14-23. CFG_DATA_LL2_LPHDR_VAL Register Field Descriptions ...................................................... 1863
14-24. CFG_DATA_LL2_THRESHOLD Register Field Descriptions ..................................................... 1864
14-25. CFG_DATA_LL3 Register Field Descriptions ....................................................................... 1865
14-26. CFG_DATA_LL3_LPHDR_VAL Register Field Descriptions ...................................................... 1866
14-27. CFG_DATA_LL3_THRESHOLD Register Field Descriptions ..................................................... 1867
14-28. CFG_DATA_LL4 Register Field Descriptions ....................................................................... 1868
14-29. CFG_DATA_LL4_LPHDR_VAL Register Field Descriptions ...................................................... 1869
14-30. CFG_DATA_LL4_THRESHOLD Register Field Descriptions ..................................................... 1870
14-31. CFG_DATA_LL5 Register Field Descriptions ....................................................................... 1871
14-32. CFG_DATA_LL5_LPHDR_VAL Register Field Descriptions ...................................................... 1872
14-33. CFG_DATA_LL5_THRESHOLD Register Field Descriptions ..................................................... 1873
14-34. CFG_DATA_LL6 Register Field Descriptions ....................................................................... 1874
14-35. CFG_DATA_LL6_LPHDR_VAL Register Field Descriptions ...................................................... 1875
14-36. CFG_DATA_LL6_THRESHOLD Register Field Descriptions ..................................................... 1876
14-37. CFG_DATA_LL7 Register Field Descriptions ....................................................................... 1877
14-38. CFG_DATA_LL7_LPHDR_VAL Register Field Descriptions ...................................................... 1878
14-39. CFG_DATA_LL7_THRESHOLD Register Field Descriptions ..................................................... 1879
14-40. CFG_DATA_LL8 Register Field Descriptions ....................................................................... 1880
14-41. CFG_DATA_LL8_LPHDR_VAL Register Field Descriptions ...................................................... 1881
14-42. CFG_DATA_LL8_THRESHOLD Register Field Descriptions ..................................................... 1882
14-43. CFG_DATA_LL9 Register Field Descriptions ....................................................................... 1883
14-44. CFG_DATA_LL9_LPHDR_VAL Register Field Descriptions ...................................................... 1884
14-45. CFG_DATA_LL9_THRESHOLD Register Field Descriptions ..................................................... 1885
14-46. CFG_DATA_LL10 Register Field Descriptions ...................................................................... 1886
1887
14-48.
1888
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
106
....................................................
CFG_DATA_LL10_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL11 Register Field Descriptions ......................................................................
CFG_DATA_LL11_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL11_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL12 Register Field Descriptions ......................................................................
CFG_DATA_LL12_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL12_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL13 Register Field Descriptions ......................................................................
CFG_DATA_LL13_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL13_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL14 Register Field Descriptions ......................................................................
CFG_DATA_LL14_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL14_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL15 Register Field Descriptions ......................................................................
CFG_DATA_LL15_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL15_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL16 Register Field Descriptions ......................................................................
CFG_DATA_LL16_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL16_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL17 Register Field Descriptions ......................................................................
CFG_DATA_LL17_LPHDR_VAL Register Field Descriptions ....................................................
CFG_DATA_LL17_THRESHOLD Register Field Descriptions....................................................
CFG_DATA_LL18 Register Field Descriptions ......................................................................
14-47. CFG_DATA_LL10_LPHDR_VAL Register Field Descriptions
List of Tables
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
....................................................
14-72. CFG_DATA_LL18_THRESHOLD Register Field Descriptions....................................................
14-73. CFG_DATA_LL19 Register Field Descriptions ......................................................................
14-74. CFG_DATA_LL19_LPHDR_VAL Register Field Descriptions ....................................................
14-75. CFG_DATA_LL19_THRESHOLD Register Field Descriptions....................................................
14-76. CFG_DATA_LL20 Register Field Descriptions ......................................................................
14-77. CFG_DATA_LL20_LPHDR_VAL Register Field Descriptions ....................................................
14-78. CFG_DATA_LL20_THRESHOLD Register Field Descriptions....................................................
14-79. CFG_DATA_LL21 Register Field Descriptions ......................................................................
14-80. CFG_DATA_LL21_LPHDR_VAL Register Field Descriptions ....................................................
14-81. CFG_DATA_LL21_THRESHOLD Register Field Descriptions....................................................
14-82. CFG_DATA_LL22 Register Field Descriptions ......................................................................
14-83. CFG_DATA_LL22_LPHDR_VAL Register Field Descriptions ....................................................
14-84. CFG_DATA_LL22_THRESHOLD Register Field Descriptions....................................................
14-85. CFG_DATA_LL23 Register Field Descriptions ......................................................................
14-86. CFG_DATA_LL23_LPHDR_VAL Register Field Descriptions ....................................................
14-87. CFG_DATA_LL23_THRESHOLD Register Field Descriptions....................................................
14-88. CFG_DATA_LL24 Register Field Descriptions ......................................................................
14-89. CFG_DATA_LL24_LPHDR_VAL Register Field Descriptions ....................................................
14-90. CFG_DATA_LL24_THRESHOLD Register Field Descriptions....................................................
14-91. CFG_DATA_LL25 Register Field Descriptions ......................................................................
14-92. CFG_DATA_LL25_LPHDR_VAL Register Field Descriptions ....................................................
14-93. CFG_DATA_LL25_THRESHOLD Register Field Descriptions....................................................
14-94. CFG_DATA_LL26 Register Field Descriptions ......................................................................
14-95. CFG_DATA_LL26_LPHDR_VAL Register Field Descriptions ....................................................
14-96. CFG_DATA_LL26_THRESHOLD Register Field Descriptions....................................................
14-97. CFG_DATA_LL27 Register Field Descriptions ......................................................................
14-98. CFG_DATA_LL27_LPHDR_VAL Register Field Descriptions ....................................................
14-99. CFG_DATA_LL27_THRESHOLD Register Field Descriptions....................................................
14-100. CFG_DATA_LL28 Register Field Descriptions ....................................................................
14-101. CFG_DATA_LL28_LPHDR_VAL Register Field Descriptions ...................................................
14-102. CFG_DATA_LL28_THRESHOLD Register Field Descriptions ..................................................
14-103. CFG_DATA_LL29 Register Field Descriptions ....................................................................
14-104. CFG_DATA_LL29_LPHDR_VAL Register Field Descriptions ...................................................
14-105. CFG_DATA_LL29_THRESHOLD Register Field Descriptions ..................................................
14-106. CFG_DATA_LL30 Register Field Descriptions ....................................................................
14-107. CFG_DATA_LL30_LPHDR_VAL Register Field Descriptions ...................................................
14-108. CFG_DATA_LL30_THRESHOLD Register Field Descriptions ..................................................
14-109. CFG_DATA_LL31 Register Field Descriptions ....................................................................
14-110. CFG_DATA_LL31_LPHDR_VAL Register Field Descriptions ...................................................
14-111. CFG_DATA_LL31_THRESHOLD Register Field Descriptions ..................................................
14-112. CFG_LVDS_MAPPING_LANE0_FMT_0 Register Field Descriptions ..........................................
14-113. CFG_LVDS_MAPPING_LANE1_FMT_0 Register Field Descriptions ..........................................
14-114. CFG_LVDS_MAPPING_LANE2_FMT_0 Register Field Descriptions ..........................................
14-115. CFG_LVDS_MAPPING_LANE3_FMT_0 Register Field Descriptions ..........................................
14-116. CFG_LVDS_MAPPING_LANE0_FMT_1 Register Field Descriptions ..........................................
14-117. CFG_LVDS_MAPPING_LANE1_FMT_1 Register Field Descriptions ..........................................
14-118. CFG_LVDS_MAPPING_LANE2_FMT_1 Register Field Descriptions ..........................................
14-119. CFG_LVDS_MAPPING_LANE3_FMT_1 Register Field Descriptions ..........................................
14-71. CFG_DATA_LL18_LPHDR_VAL Register Field Descriptions
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
107
www.ti.com
14-120. CFG_LVDS_GEN_0 Register Field Descriptions .................................................................. 1960
14-121. CFG_LVDS_GEN_1 Register Field Descriptions .................................................................. 1961
14-122. CFG_LVDS_GEN_2 Register Field Descriptions .................................................................. 1962
14-123. CFG_MASK_REG0 Register Field Descriptions................................................................... 1963
14-124. CFG_MASK_REG1 Register Field Descriptions................................................................... 1964
14-125. CFG_MASK_REG2 Register Field Descriptions................................................................... 1965
14-126. CFG_MASK_REG3 Register Field Descriptions................................................................... 1966
14-127. STAT_CBUFF_REG0 Register Field Descriptions ................................................................ 1967
14-128. STAT_CBUFF_REG1 Register Field Descriptions ................................................................ 1968
14-129. STAT_CBUFF_REG2 Register Field Descriptions ................................................................ 1969
14-130. STAT_CBUFF_REG3 Register Field Descriptions ................................................................ 1970
14-131. CLR_CBUFF_REG0 Register Field Descriptions
.................................................................
1971
14-132. STAT_CBUFF_ECC_REG Register Field Descriptions .......................................................... 1972
14-133. MASK_CBUFF_ECC_REG Register Field Descriptions.......................................................... 1973
14-134. CLR_CBUFF_ECC_REG Register Field Descriptions ............................................................ 1974
1975
14-136.
1976
14-137.
14-138.
14-139.
14-140.
14-141.
14-142.
14-143.
14-144.
14-145.
14-146.
14-147.
14-148.
14-149.
14-150.
14-151.
14-152.
14-153.
14-154.
14-155.
14-156.
14-157.
14-158.
14-159.
14-160.
14-161.
14-162.
14-163.
14-164.
14-165.
14-166.
14-167.
14-168.
108
.......................................................................
MASK_SAFETY Register Field Descriptions.......................................................................
CLR_SAFETY Register Field Descriptions .........................................................................
I/O Description of CSI2 ................................................................................................
CSI2 Lane Configuration ..............................................................................................
Data Type Classes ....................................................................................................
Register Access Width Limitations ..................................................................................
LP to HS Timing Parameters .........................................................................................
LP to HS Timing Parameters Example for 400-MHz DDR Clock ................................................
HS to LP Timing Parameters .........................................................................................
HS to LP Timing Parameters Example for 400-MHz DDR Clock and Two Data Lanes ......................
Main Sequence – PRCM and Global Configuration ...............................................................
Main Sequence – Configure CSI2 Clock Configuration...........................................................
Main Sequence – Configure CSI2_PHY ............................................................................
Main Sequence – CSI2 Complex IO Configuration................................................................
Main Sequence – VC and OCP Configuration .....................................................................
Main Sequence – CBUFF CSI2 Static Configuration .............................................................
Main Sequence – CBUFF Linklist ...................................................................................
CSI2_PROTOCOL_ENGINE Registers .............................................................................
CSI2_PROTOCOL_ENGINE Access Type Codes ................................................................
CSI2_REVISION Register Field Descriptions ......................................................................
CSI2_SYSCONFIG Register Field Descriptions ...................................................................
CSI2_SYSSTATUS Register Field Descriptions ...................................................................
CSI2_IRQSTATUS Register Field Descriptions ...................................................................
CSI2_IRQENABLE Register Field Descriptions ...................................................................
CSI2_CTRL Register Field Descriptions ............................................................................
CSI2_GNQ Register Field Descriptions.............................................................................
CSI2_COMPLEXIO_CFG1 Register Field Descriptions ..........................................................
CSI2_COMPLEXIO_IRQSTATUS Register Field Descriptions ..................................................
CSI2_COMPLEXIO_IRQENABLE Register Field Descriptions ..................................................
CSI2_CLK_CTRL Register Field Descriptions .....................................................................
CSI2_TIMING1 Register Field Descriptions ........................................................................
CSI2_TIMING2 Register Field Descriptions ........................................................................
CSI2_VM_TIMING1 Register Field Descriptions ..................................................................
14-135. STAT_SAFETY Register Field Descriptions
List of Tables
1977
1978
1979
1984
1988
1991
1991
1993
1993
2000
2001
2001
2001
2002
2002
2003
2004
2009
2010
2011
2012
2013
2016
2018
2021
2023
2026
2030
2033
2035
2037
2039
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
14-169. CSI2_VM_TIMING2 Register Field Descriptions .................................................................. 2040
14-170. CSI2_VM_TIMING3 Register Field Descriptions .................................................................. 2041
14-171. CSI2_CLK_TIMING Register Field Descriptions................................................................... 2042
14-172. CSI2_TX_FIFO_VC_SIZE Register Field Descriptions ........................................................... 2043
14-173. CSI2_RX_FIFO_VC_SIZE Register Field Descriptions ........................................................... 2044
14-174. CSI2_COMPLEXIO_CFG2 Register Field Descriptions .......................................................... 2045
14-175. CSI2_RX_FIFO_VC_FULLNESS Register Field Descriptions ................................................... 2049
14-176. CSI2_VM_TIMING4 Register Field Descriptions .................................................................. 2050
14-177. CSI2_TX_FIFO_VC_EMPTINESS Register Field Descriptions ................................................. 2051
14-178. CSI2_VM_TIMING5 Register Field Descriptions .................................................................. 2052
14-179. CSI2_VM_TIMING6 Register Field Descriptions .................................................................. 2053
14-180. CSI2_VM_TIMING7 Register Field Descriptions .................................................................. 2054
14-181. CSI2_STOPCLK_TIMING Register Field Descriptions ........................................................... 2055
14-182. CSI2_CTRL2 Register Field Descriptions .......................................................................... 2056
14-183. CSI2_VM_TIMING8 Register Field Descriptions .................................................................. 2058
14-184. CSI2_TE_HSYNC_WIDTH_0 to CSI2_TE_HSYNC_WIDTH_1 Register Field Descriptions ................ 2059
14-185. CSI2_TE_VSYNC_WIDTH_0 to CSI2_TE_VSYNC_WIDTH_1 Register Field Descriptions ................ 2060
14-186. CSI2_TE_HSYNC_NUMBER_0 to CSI2_TE_HSYNC_NUMBER_1 Register Field Descriptions .......... 2061
14-187. CSI2_VC_CTRL_0 to CSI2_VC_CTRL_3 Register Field Descriptions ......................................... 2062
14-188. CSI2_VC_TE_0 to CSI2_VC_TE_3 Register Field Descriptions ................................................ 2066
14-189. CSI2_VC_LONG_PACKET_HEADER_0 to CSI2_VC_LONG_PACKET_HEADER_3 Register Field
Descriptions .............................................................................................................. 2067
14-190. CSI2_VC_LONG_PACKET_PAYLOAD_0 to CSI2_VC_LONG_PACKET_PAYLOAD_3 Register Field
Descriptions .............................................................................................................. 2068
14-191. CSI2_VC_SHORT_PACKET_HEADER_0 to CSI2_VC_SHORT_PACKET_HEADER_3 Register Field
Descriptions .............................................................................................................. 2069
14-192. CSI2_VC_IRQSTATUS_0 to CSI2_VC_IRQSTATUS_3 Register Field Descriptions ........................ 2070
14-193. CSI2_VC_IRQENABLE_0 to CSI2_VC_IRQENABLE_3 Register Field Descriptions ........................ 2072
14-194. CSI2_PHY Registers .................................................................................................. 2074
.....................................................................................
14-196. REGISTER0 Register Field Descriptions ...........................................................................
14-197. REGISTER1 Register Field Descriptions ...........................................................................
14-198. REGISTER2 Register Field Descriptions ...........................................................................
14-199. REGISTER3 Register Field Descriptions ...........................................................................
14-200. REGISTER4 Register Field Descriptions ...........................................................................
14-201. REGISTER5 Register Field Descriptions ...........................................................................
14-202. REGISTER6 Register Field Descriptions ...........................................................................
14-203. REGISTER7 Register Field Descriptions ...........................................................................
14-204. REGISTER8 Register Field Descriptions ...........................................................................
14-205. REGISTER9 Register Field Descriptions ...........................................................................
14-206. REGISTER10 Register Field Descriptions .........................................................................
14-207. REGISTER11 Register Field Descriptions .........................................................................
14-208. REGISTER12 Register Field Descriptions .........................................................................
14-209. REGISTER13 Register Field Descriptions .........................................................................
14-210. REGISTER14 Register Field Descriptions .........................................................................
14-211. REGISTER15 Register Field Descriptions .........................................................................
16-1. RTI Registers ............................................................................................................
16-2. RTI Global Control Register (RTIGCTRL) Field Descriptions .....................................................
16-3. RTI Timebase Control Register (RTITBCTRL) Field Descriptions ................................................
16-4. RTI Capture Control Register (RTICAPCTRL) Field Descriptions ................................................
14-195. CSI2_PHY Access Type Codes
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2086
2087
2088
2089
2090
2091
2103
2104
2105
2106
109
www.ti.com
16-5.
RTI Compare Control Register (RTICOMPCTRL) Field Descriptions ............................................ 2107
16-6.
RTI Free Running Counter 0 Register (RTIFRC0) Field Descriptions ........................................... 2108
16-7.
RTI Up Counter 0 Register (RTIUC0) Field Descriptions .......................................................... 2108
16-8.
RTI Compare Up Counter 0 Register (RTICPUC0) Field Descriptions .......................................... 2109
16-9.
RTI Capture Free Running Counter 0 Register (RTICAFRC0) Field Descriptions ............................. 2109
16-10. RTI Capture Up Counter 0 Register (RTICAUC0) Field Descriptions ............................................ 2110
16-11. RTI Free Running Counter 1 Register (RTIFRC1) Field Descriptions ........................................... 2110
16-12. RTI Up Counter 1 Register (RTIUC1) Field Descriptions .......................................................... 2111
16-13. RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions .......................................... 2112
16-14. RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions ............................. 2113
16-15. RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions ............................................ 2113
16-16. RTI Compare 0 Register (RTICOMP0) Field Descriptions......................................................... 2114
16-17. RTI Update Compare 0 Register (RTIUDCP0) Field Descriptions
...............................................
2114
16-18. RTI Compare 1 Register (RTICOMP1) Field Descriptions......................................................... 2115
16-19. RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions
...............................................
2115
16-20. RTI Compare 2 Register (RTICOMP2) Field Descriptions......................................................... 2116
16-21. RTI Update Compare 2 Register (RTIUDCP2) Field Descriptions
...............................................
2116
16-22. RTI Compare 3 Register (RTICOMP3) Field Descriptions......................................................... 2117
...............................................
RTI Timebase Low Compare Register (RTITBLCOMP) Field Descriptions .....................................
RTI Timebase High Compare Register (RTITBHCOMP) Field Descriptions ....................................
RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions ........................................
RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions ..................................
RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions ....................................................
Digital Watchdog Control Register (RTIDWDCTRL) Field Descriptions .........................................
Digital Watchdog Preload Register (RTIDWDPRLD) Field Descriptions ........................................
Watchdog Status Register (RTIWDSTATUS) Field Descriptions .................................................
RTI Watchdog Key Register (RTIDWDKEY) Field Descriptions ..................................................
Example of a WDKEY Sequence .....................................................................................
RTI Watchdog Down Counter Register (RTIDWDCNTR) Field Descriptions ...................................
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) Field Descriptions .....................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) Field Descriptions ................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) Field Descriptions .....................
RTI Compare 0 Clear Register (RTICMP0CLR) Field Descriptions ..............................................
RTI Compare 1 Clear Register (RTICMP1CLR) Field Descriptions ..............................................
RTI Compare 2 Clear Register (RTICMP2CLR) Field Descriptions ..............................................
RTI Compare 3 Clear Register (RTICMP3CLR) Field Descriptions ..............................................
MSS_GIO Registers ....................................................................................................
GIOGCR Register Field Descriptions .................................................................................
GIOPWDN Register Field Descriptions ..............................................................................
GIOINTDET Register Field Descriptions .............................................................................
GIOPOL Register Field Descriptions .................................................................................
GIOENASET Register Field Descriptions ............................................................................
GIOENACLR Register Field Descriptions ............................................................................
GIOLVLSET Register Field Descriptions .............................................................................
GIOLVLCLR Register Field Descriptions ............................................................................
GIOFLG Register Field Descriptions .................................................................................
GIOOFFA Register Field Descriptions ...............................................................................
GIOOFFB Register Field Descriptions ...............................................................................
16-23. RTI Update Compare 3 Register (RTIUDCP3) Field Descriptions
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
110
List of Tables
2117
2118
2118
2119
2121
2123
2124
2125
2126
2127
2127
2128
2128
2129
2130
2131
2131
2132
2132
2140
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
17-13. GIOEMUA Register Field Descriptions ............................................................................... 2153
17-14. GIOEMUB Register Field Descriptions ............................................................................... 2154
17-15. GIODIRA Register Field Descriptions ................................................................................ 2155
17-16. GIODINA Register Field Descriptions ................................................................................ 2156
17-17. GIODOUTA Register Field Descriptions ............................................................................. 2157
17-18. GIOSETA Register Field Descriptions ................................................................................ 2158
17-19. GIOCLRA Register Field Descriptions
...............................................................................
2159
17-20. GIOPDRA Register Field Descriptions ............................................................................... 2160
17-21. GIOPULDISA Register Field Descriptions ........................................................................... 2161
17-22. GIOPSLA Register Field Descriptions ................................................................................ 2162
17-23. GIODIRB Register Field Descriptions ................................................................................ 2163
17-24. GIODINB Register Field Descriptions ................................................................................ 2164
17-25. GIODOUTB Register Field Descriptions ............................................................................. 2165
17-26. GIOSETB Register Field Descriptions ................................................................................ 2166
17-27. GIOCLRB Register Field Descriptions
...............................................................................
2167
17-28. GIOPDRB Register Field Descriptions ............................................................................... 2168
17-29. GIOPULDISB Register Field Descriptions ........................................................................... 2169
17-30. GIOPSLB Register Field Descriptions ................................................................................ 2170
17-31. GIODIRC Register Field Descriptions ................................................................................ 2171
17-32. GIODINC Register Field Descriptions ................................................................................ 2172
17-33. GIODOUTC Register Field Descriptions ............................................................................. 2173
...............................................................................
...............................................................................
GIOPDRC Register Field Descriptions ...............................................................................
GIOPULDISC Register Field Descriptions ...........................................................................
GIOPSLC Register Field Descriptions ................................................................................
GIODIRD Register Field Descriptions ................................................................................
GIODIND Register Field Descriptions ................................................................................
GIODOUTD Register Field Descriptions .............................................................................
GIOSETD Register Field Descriptions ...............................................................................
GIOCLRD Register Field Descriptions ...............................................................................
GIOPDRD Register Field Descriptions ...............................................................................
GIOPULDISD Register Field Descriptions ...........................................................................
GIOPSLD Register Field Descriptions ................................................................................
GIODIRE Register Field Descriptions ................................................................................
GIODINE Register Field Descriptions ................................................................................
GIODOUTE Register Field Descriptions .............................................................................
GIOSETE Register Field Descriptions ................................................................................
GIOCLRE Register Field Descriptions ...............................................................................
GIOPDRE Register Field Descriptions ...............................................................................
GIOPULDISE Register Field Descriptions ...........................................................................
GIOPSLE Register Field Descriptions ................................................................................
GIODIRF Register Field Descriptions ................................................................................
GIODINF Register Field Descriptions ................................................................................
GIODOUTF Register Field Descriptions .............................................................................
GIOSETF Register Field Descriptions ................................................................................
GIOCLRF Register Field Descriptions ................................................................................
GIOPDRF Register Field Descriptions ...............................................................................
GIOPULDISF Register Field Descriptions ...........................................................................
17-34. GIOSETC Register Field Descriptions
2174
17-35. GIOCLRC Register Field Descriptions
2175
17-36.
2176
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
111
www.ti.com
17-62. GIOPSLF Register Field Descriptions ................................................................................ 2202
17-63. GIODIRG Register Field Descriptions ................................................................................ 2203
17-64. GIODING Register Field Descriptions ................................................................................ 2204
17-65. GIODOUTG Register Field Descriptions ............................................................................. 2205
17-66. GIOSETG Register Field Descriptions
...............................................................................
2206
17-67. GIOCLRG Register Field Descriptions ............................................................................... 2207
17-68. GIOPDRG Register Field Descriptions ............................................................................... 2208
17-69. GIOPULDISG Register Field Descriptions ........................................................................... 2209
2210
17-71.
2211
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
112
...............................................................................
GIODIRH Register Field Descriptions ................................................................................
GIODINH Register Field Descriptions ................................................................................
GIODOUTH Register Field Descriptions .............................................................................
GIOSETH Register Field Descriptions ...............................................................................
GIOCLRH Register Field Descriptions ...............................................................................
GIOPDRH Register Field Descriptions ...............................................................................
GIOPULDISH Register Field Descriptions ...........................................................................
GIOPSLH Register Field Descriptions ................................................................................
GIOSRCA Register Field Descriptions ...............................................................................
GIOSRCB Register Field Descriptions ...............................................................................
GIOSRCC Register Field Descriptions ...............................................................................
GIOSRCD Register Field Descriptions ...............................................................................
GIOSRCE Register Field Descriptions ...............................................................................
GIOSRCF Register Field Descriptions ...............................................................................
GIOSRCG Register Field Descriptions ...............................................................................
GIOSRCH Register Field Descriptions ...............................................................................
Output Buffer, and Pull Control Behavior for GIO Pins.............................................................
Mailbox Registers .......................................................................................................
Mailbox Access Type Codes...........................................................................................
INT_MASK Register Field Descriptions ..............................................................................
INT_MASK_SET Register Field Descriptions .......................................................................
INT_MASK_CLR Register Field Descriptions .......................................................................
INT_STS_CLR Register Field Descriptions ..........................................................................
INT_ACK Register Field Descriptions ................................................................................
INT_TRIG Register Field Descriptions ...............................................................................
INT_STS_MASKED Register Field Descriptions ....................................................................
INT_STS_RAW Register Field Descriptions .........................................................................
Encoding of Destination Bits in Trace Mode Packet Format ......................................................
Encoding of Status Bits in Trace Mode Packet Format ............................................................
Encoding of Write Size in Packet Format ............................................................................
Number of Clock Cycles per Packet ..................................................................................
Pins Used for Data Communication ..................................................................................
DMM Registers ..........................................................................................................
DMM Global Control Register (DMMGLBCTRL) Field Descriptions..............................................
DMM Interrupt Set Register (DMMINTSET) Field Descriptions ...................................................
DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions ................................................
DMM Interrupt Level Register (DMMINTLVL) Field Descriptions .................................................
DMM Interrupt Flag Register (DMMINTFLG) Field Descriptions ..................................................
DMM Interrupt Offset 1 Register (DMMOFF1) Field Descriptions ................................................
DMM Interrupt Offset 2 Register (DMMOFF1) Field Descriptions ................................................
17-70. GIOPSLG Register Field Descriptions
List of Tables
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2230
2230
2231
2232
2233
2234
2235
2236
2237
2238
2242
2242
2242
2243
2243
2246
2247
2249
2253
2258
2260
2264
2265
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
19-14. DMM Direct Data Mode Destination Register (DMMDDMDEST) Field Descriptions........................... 2266
19-15. DMM Direct Data Mode Blocksize Register (DMMDDMBL) Field Descriptions................................. 2266
19-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) Field Descriptions ................................... 2267
19-17. DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) Field Descriptions .......................... 2267
19-18. DMM Destination x Region 1 (DMMDESTxREG1) Field Descriptions ........................................... 2268
19-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) Field Descriptions ........................................... 2269
19-20. DMM Destination x Region 2 (DMMDESTxREG2) Field Descriptions ........................................... 2270
19-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) Field Descriptions ........................................... 2271
19-22. DMM Pin Control 0 (DMMPC0) Field Descriptions ................................................................. 2272
19-23. DMM Pin Control 1 (DMMPC1) Field Descriptions ................................................................. 2273
19-24. DMM Pin Control 2 (DMMPC2) Field Descriptions ................................................................. 2275
19-25. DMM Pin Control 3 (DMMPC3) Field Descriptions ................................................................. 2276
19-26. DMM Pin Control 4 (DMMPC4) Field Descriptions ................................................................. 2277
19-27. DMM Pin Control 5 (DMMPC5) Field Descriptions ................................................................. 2279
19-28. DMM Pin Control 6 (DMMPC6) Field Descriptions ................................................................. 2280
19-29. DMM Pin Control 7 (DMMPC7) Field Descriptions ................................................................. 2282
19-30. DMM Pin Control 8 (DMMPC8) Field Descriptions ................................................................. 2283
20-1.
ePWM Module Control and Status Register Set Grouped by Submodule ....................................... 2289
20-2.
Submodule Configuration Parameters................................................................................ 2290
20-3.
Time-Base Submodule Registers ..................................................................................... 2292
20-4.
Key Time-Base Signals ................................................................................................. 2293
20-5.
Counter-Compare Submodule Registers
20-6.
Counter-Compare Submodule Key Signals .......................................................................... 2302
20-7.
Action-Qualifier Submodule Registers ................................................................................ 2305
20-8.
Action-Qualifier Submodule Possible Input Events ................................................................. 2306
20-9.
Action-Qualifier Event Priority for Up-Down-Count Mode .......................................................... 2308
............................................................................
2301
20-10. Action-Qualifier Event Priority for Up-Count Mode.................................................................. 2308
20-11. Action-Qualifier Event Priority for Down-Count Mode .............................................................. 2308
20-12. Behavior if CMPA/CMPB is Greater than the Period ............................................................... 2308
20-13. Dead-Band Generator Submodule Registers........................................................................ 2318
.............................................................................
Dead-Band Delay Values in μS as a Function of DBFED and DBRED ..........................................
PWM-Chopper Submodule Registers ................................................................................
Possible Pulse Width Values for VCLK3 = 100 MHz ...............................................................
Trip-Zone Submodule Registers ......................................................................................
Possible Actions On a Trip Event .....................................................................................
Event-Trigger Submodule Registers .................................................................................
Digital Compare Submodule Registers ...............................................................................
MSS_ETPWM1 Registers ..............................................................................................
MSS_ETPWM1 Access Type Codes .................................................................................
TBCTL_TBSTS Register Field Descriptions .........................................................................
TBPHS Register Field Descriptions ...................................................................................
TBCTR_TBPRD Register Field Descriptions ........................................................................
CMPCTL Register Field Descriptions.................................................................................
CMPA Register Field Descriptions ....................................................................................
CMPB_AQCTLA Register Field Descriptions........................................................................
AQCTLB_AQSFRC Register Field Descriptions ....................................................................
AQCSFRC_DBCTL Register Field Descriptions ....................................................................
DBRED_DBFED Register Field Descriptions........................................................................
20-14. Classical Dead-Band Operating Modes
2320
20-15.
2322
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2323
2325
2328
2329
2335
2339
2360
2361
2362
2364
2365
2366
2368
2369
2371
2373
2375
113
www.ti.com
2376
20-34.
2378
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
114
.....................................................................
TZCTL_TZEINT Register Field Descriptions ........................................................................
TZFLG_TZCLR Register Field Descriptions .........................................................................
TZFRC_ETSEL Register Field Descriptions .........................................................................
ETPS_ETFLG Register Field Descriptions ..........................................................................
ETCLR_ETFRC Register Field Descriptions ........................................................................
PCCTL Register Field Descriptions ...................................................................................
Reserved1 Register Field Descriptions...............................................................................
Reserved2 Register Field Descriptions...............................................................................
Reserved3 Register Field Descriptions...............................................................................
Reserved4 Register Field Descriptions...............................................................................
Reserved5 Register Field Descriptions...............................................................................
Reserved6 Register Field Descriptions...............................................................................
Reserved7 Register Field Descriptions...............................................................................
Reserved8 Register Field Descriptions...............................................................................
DCTRIPSEL_DCACTL Register Field Descriptions ................................................................
DCBCTL_DCFCTL Register Field Descriptions .....................................................................
DCCAPCTL_DCFOFFSET Register Field Descriptions ...........................................................
DCFOFFSETCNT_DCFWINDOW Register Field Descriptions ...................................................
DCFWINDOWCNT_DCCAP Register Field Descriptions ..........................................................
Parameters of the CAN Bit Time ......................................................................................
Message Object Field Descriptions ...................................................................................
Message RAM Addressing in Debug/Suspend and RDA Mode ..................................................
Message Interface Register Sets 1 and 2 ...........................................................................
Message Interface Register 3 .........................................................................................
MSS_DCAN Registers..................................................................................................
MSS_DCAN Access Type Codes .....................................................................................
CTL Register Field Descriptions.......................................................................................
ES Register Field Descriptions ........................................................................................
ERRC Register Field Descriptions ....................................................................................
BTR Register Field Descriptions ......................................................................................
INT Register Field Descriptions .......................................................................................
TEST Register Field Descriptions .....................................................................................
Reserved_1 Register Field Descriptions .............................................................................
PERR Register Field Descriptions ....................................................................................
DCAN_REV_ID Register Field Descriptions .........................................................................
ECCDIAG Register Field Descriptions ...............................................................................
ECCDIAG_STAT Register Field Descriptions .......................................................................
ECC_CS Register Field Descriptions .................................................................................
ECC_SERR Register Field Descriptions .............................................................................
TTCAN1 Register Field Descriptions .................................................................................
TTCAN2 Register Field Descriptions .................................................................................
TTCAN3 Register Field Descriptions .................................................................................
TTCAN4 Register Field Descriptions .................................................................................
TTCAN5 Register Field Descriptions .................................................................................
TTCAN6 Register Field Descriptions .................................................................................
TTCAN7 Register Field Descriptions .................................................................................
TTCAN8 Register Field Descriptions .................................................................................
TTCAN9 Register Field Descriptions .................................................................................
20-33. TZSEL_TZDCSEL Register Field Descriptions
List of Tables
2380
2382
2384
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2398
2399
2400
2401
2406
2413
2415
2418
2420
2440
2442
2443
2446
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
21-30. TTCAN10 Register Field Descriptions ................................................................................ 2468
21-31. TTCAN11 Register Field Descriptions ................................................................................ 2469
21-32. TTCAN12 Register Field Descriptions ................................................................................ 2470
21-33. TTCAN13 Register Field Descriptions ................................................................................ 2471
21-34. TTCAN14 Register Field Descriptions ................................................................................ 2472
21-35. TTCAN15 Register Field Descriptions ................................................................................ 2473
21-36. TTCAN16 Register Field Descriptions ................................................................................ 2474
21-37. TTCAN17 Register Field Descriptions ................................................................................ 2475
21-38. TTCAN18 Register Field Descriptions ................................................................................ 2476
21-39. TTCAN19 Register Field Descriptions ................................................................................ 2477
..................................................................................
TXRQ_X Register Field Descriptions .................................................................................
TXRQ12 Register Field Descriptions .................................................................................
TXRQ34 Register Field Descriptions .................................................................................
TXRQ56 Register Field Descriptions .................................................................................
TXRQ78 Register Field Descriptions .................................................................................
NWDAT_X Register Field Descriptions ..............................................................................
NWDAT12 Register Field Descriptions ...............................................................................
NWDAT34 Register Field Descriptions ...............................................................................
NWDAT56 Register Field Descriptions ...............................................................................
NWDAT78 Register Field Descriptions ...............................................................................
INTPND_X Register Field Descriptions ..............................................................................
INTPND12 Register Field Descriptions...............................................................................
INTPND34 Register Field Descriptions...............................................................................
INTPND56 Register Field Descriptions...............................................................................
INTPND78 Register Field Descriptions...............................................................................
MSGVAL_X Register Field Descriptions .............................................................................
MSGVAL12 Register Field Descriptions .............................................................................
MSGVAL34 Register Field Descriptions .............................................................................
MSGVAL56 Register Field Descriptions .............................................................................
MSGVAL78 Register Field Descriptions .............................................................................
Reserved_2 Register Field Descriptions .............................................................................
INTMUX12 Register Field Descriptions ..............................................................................
INTMUX34 Register Field Descriptions ..............................................................................
INTMUX56 Register Field Descriptions ..............................................................................
INTMUX78 Register Field Descriptions ..............................................................................
Reserved_3 Register Field Descriptions .............................................................................
Reserved_4 Register Field Descriptions .............................................................................
Reserved_5 Register Field Descriptions .............................................................................
Reserved_6 Register Field Descriptions .............................................................................
Reserved_7 Register Field Descriptions .............................................................................
Reserved_8 Register Field Descriptions .............................................................................
IF1CMD Register Field Descriptions..................................................................................
IF1MSK Register Field Descriptions ..................................................................................
IF1ARB Register Field Descriptions ..................................................................................
IF1MCTL Register Field Descriptions ................................................................................
IF1DATA Register Field Descriptions.................................................................................
IF1DATB Register Field Descriptions.................................................................................
Reserved_9 Register Field Descriptions .............................................................................
21-40. ABOTR Register Field Descriptions
2478
21-41.
2479
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
21-61.
21-62.
21-63.
21-64.
21-65.
21-66.
21-67.
21-68.
21-69.
21-70.
21-71.
21-72.
21-73.
21-74.
21-75.
21-76.
21-77.
21-78.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2513
2514
2515
2517
2518
2519
115
www.ti.com
21-79. Reserved_10 Register Field Descriptions............................................................................ 2520
21-80. IF2CMD Register Field Descriptions.................................................................................. 2521
21-81. IF2MSK Register Field Descriptions .................................................................................. 2524
21-82. IF2ARB Register Field Descriptions .................................................................................. 2525
21-83. IF2MCTL Register Field Descriptions
................................................................................
2526
21-84. IF2DATA Register Field Descriptions................................................................................. 2528
21-85. IF2DATB Register Field Descriptions................................................................................. 2529
21-86. Reserved_11 Register Field Descriptions............................................................................ 2530
21-87. Reserved_12 Register Field Descriptions............................................................................ 2531
21-88. IF3OBS Register Field Descriptions .................................................................................. 2532
21-89. IF3MSK Register Field Descriptions .................................................................................. 2534
21-90. IF3ARB Register Field Descriptions .................................................................................. 2535
21-91. IF3MCTL Register Field Descriptions
................................................................................
2536
21-92. IF3DATA Register Field Descriptions................................................................................. 2538
21-93. IF3DATB Register Field Descriptions................................................................................. 2539
21-94. Reserved_13 Register Field Descriptions............................................................................ 2540
21-95. Reserved_14 Register Field Descriptions............................................................................ 2541
21-96. IF3UPD12 Register Field Descriptions ............................................................................... 2542
21-97. IF3UPD34 Register Field Descriptions ............................................................................... 2543
21-98. IF3UPD56 Register Field Descriptions ............................................................................... 2544
21-99. IF3UPD78 Register Field Descriptions ............................................................................... 2545
21-100. Reserved_15 Register Field Descriptions .......................................................................... 2546
21-101. Reserved_16 Register Field Descriptions .......................................................................... 2547
21-102. Reserved_17 Register Field Descriptions .......................................................................... 2548
21-103. Reserved_18 Register Field Descriptions .......................................................................... 2549
21-104. Reserved_19 Register Field Descriptions .......................................................................... 2550
21-105. Reserved_20 Register Field Descriptions .......................................................................... 2551
21-106. Reserved_21 Register Field Descriptions .......................................................................... 2552
21-107. Reserved_22 Register Field Descriptions .......................................................................... 2553
21-108. Reserved_23 Register Field Descriptions .......................................................................... 2554
21-109. Reserved_24 Register Field Descriptions .......................................................................... 2555
21-110. Reserved_25 Register Field Descriptions .......................................................................... 2556
21-111. Reserved_26 Register Field Descriptions .......................................................................... 2557
21-112. Reserved_27 Register Field Descriptions .......................................................................... 2558
21-113. Reserved_28 Register Field Descriptions .......................................................................... 2559
21-114. Reserved_29 Register Field Descriptions .......................................................................... 2560
21-115. Reserved_30 Register Field Descriptions .......................................................................... 2561
21-116. Reserved_31 Register Field Descriptions .......................................................................... 2562
21-117. Reserved_32 Register Field Descriptions .......................................................................... 2563
21-118. Reserved_33 Register Field Descriptions .......................................................................... 2564
21-119. Reserved_34 Register Field Descriptions .......................................................................... 2565
21-120. Reserved_35 Register Field Descriptions .......................................................................... 2566
21-121. Reserved_36 Register Field Descriptions .......................................................................... 2567
21-122. Reserved_37 Register Field Descriptions .......................................................................... 2568
21-123. Reserved_38 Register Field Descriptions .......................................................................... 2569
21-124. Reserved_39 Register Field Descriptions .......................................................................... 2570
21-125. Reserved_40 Register Field Descriptions .......................................................................... 2571
21-126. Reserved_41 Register Field Descriptions .......................................................................... 2572
21-127. Reserved_42 Register Field Descriptions .......................................................................... 2573
116
List of Tables
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
21-128. TIOC Register Field Descriptions .................................................................................... 2574
21-129. RIOC Register Field Descriptions
...................................................................................
2576
22-1.
DLC Coding in CAN FD ................................................................................................ 2584
22-2.
Rx Buffer / Rx FIFO Element Size .................................................................................... 2597
22-3.
Example Filter Configuration for Rx Buffers ......................................................................... 2598
22-4.
Possible Configurations for Message Transmission ................................................................ 2599
22-5.
Tx Buffer / Tx FIFO / Tx Queue Element Size
22-6.
Rx Buffer / Rx FIFO Element Field Descriptions .................................................................... 2605
22-7.
Tx Buffer Element Field Descriptions ................................................................................. 2607
22-8.
Tx Event FIFO Element Field Descriptions .......................................................................... 2608
22-9.
Standard Message ID Filter Element Field Descriptions ........................................................... 2610
......................................................................
2600
22-10. Extended Message ID Filter Element Field Descriptions .......................................................... 2611
22-11. MSS_MCAN_CFG Registers .......................................................................................... 2614
.............................................................................
MCANSS_PID Register Field Descriptions ..........................................................................
MCANSS_CTRL Register Field Descriptions........................................................................
MCANSS_STAT Register Field Descriptions ........................................................................
MCANSS_ICS Register Field Descriptions ..........................................................................
MCANSS_IRS Register Field Descriptions ..........................................................................
MCANSS_IECS Register Field Descriptions ........................................................................
MCANSS_IE Register Field Descriptions ............................................................................
MCANSS_IES Register Field Descriptions ..........................................................................
MCANSS_EOI Register Field Descriptions ..........................................................................
MCANSS_EXT_TS_PS Register Field Descriptions ...............................................................
MCANSS_EXT_TS_USIC Register Field Descriptions ............................................................
MCANSS_ECC_EOI Register Field Descriptions ...................................................................
MCAN_CREL Register Field Descriptions ...........................................................................
MCAN_ENDN Register Field Descriptions...........................................................................
MCAN_CUST Register Field Descriptions ...........................................................................
MCAN_DBTP Register Field Descriptions ...........................................................................
MCAN_TEST Register Field Descriptions ...........................................................................
MCAN_RWD Register Field Descriptions ............................................................................
MCAN_CCCR Register Field Descriptions ..........................................................................
MCAN_NBTP Register Field Descriptions ...........................................................................
MCAN_TSCC Register Field Descriptions ...........................................................................
MCAN_TSCV Register Field Descriptions ...........................................................................
MCAN_TOCC Register Field Descriptions...........................................................................
MCAN_TOCV Register Field Descriptions ...........................................................................
MCAN_RES00 Register Field Descriptions ..........................................................................
MCAN_RES01 Register Field Descriptions ..........................................................................
MCAN_RES02 Register Field Descriptions ..........................................................................
MCAN_RES03 Register Field Descriptions ..........................................................................
MCAN_ECR Register Field Descriptions ............................................................................
MCAN_PSR Register Field Descriptions .............................................................................
MCAN_TDCR Register Field Descriptions ...........................................................................
MCAN_RES04 Register Field Descriptions ..........................................................................
MCAN_IR Register Field Descriptions ...............................................................................
MCAN_IE Register Field Descriptions ................................................................................
MCAN_ILS Register Field Descriptions ..............................................................................
22-12. MSS_MCAN_CFG Access Type Codes
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2650
2652
117
www.ti.com
22-48. MCAN_ILE Register Field Descriptions .............................................................................. 2654
22-49. MCAN_RES05 Register Field Descriptions .......................................................................... 2655
22-50. MCAN_RES06 Register Field Descriptions .......................................................................... 2656
22-51. MCAN_RES07 Register Field Descriptions .......................................................................... 2657
22-52. MCAN_RES08 Register Field Descriptions .......................................................................... 2658
22-53. MCAN_RES09 Register Field Descriptions .......................................................................... 2659
22-54. MCAN_RES10 Register Field Descriptions .......................................................................... 2660
22-55. MCAN_RES11 Register Field Descriptions .......................................................................... 2661
22-56. MCAN_RES12 Register Field Descriptions .......................................................................... 2662
22-57. MCAN_GFC Register Field Descriptions
............................................................................
2663
22-58. MCAN_SIDFC Register Field Descriptions .......................................................................... 2664
22-59. MCAN_XIDFC Register Field Descriptions .......................................................................... 2665
22-60. MCAN_RES13 Register Field Descriptions .......................................................................... 2666
22-61. MCAN_XIDAM Register Field Descriptions .......................................................................... 2667
22-62. MCAN_HPMS Register Field Descriptions
..........................................................................
2668
22-63. MCAN_NDAT1 Register Field Descriptions ......................................................................... 2669
22-64. MCAN_NDAT2 Register Field Descriptions ......................................................................... 2670
22-65. MCAN_RXF0C Register Field Descriptions ......................................................................... 2671
2672
22-67.
2673
22-68.
22-69.
22-70.
22-71.
22-72.
22-73.
22-74.
22-75.
22-76.
22-77.
22-78.
22-79.
22-80.
22-81.
22-82.
22-83.
22-84.
22-85.
22-86.
22-87.
22-88.
22-89.
22-90.
22-91.
22-92.
22-93.
22-94.
22-95.
22-96.
118
.........................................................................
MCAN_RXF0A Register Field Descriptions .........................................................................
MCAN_RXBC Register Field Descriptions ...........................................................................
MCAN_RXF1C Register Field Descriptions .........................................................................
MCAN_RXF1S Register Field Descriptions .........................................................................
MCAN_RXF1A Register Field Descriptions .........................................................................
MCAN_RXESC Register Field Descriptions .........................................................................
MCAN_TXBC Register Field Descriptions ...........................................................................
MCAN_TXFQS Register Field Descriptions .........................................................................
MCAN_TXESC Register Field Descriptions .........................................................................
MCAN_TXBRP Register Field Descriptions .........................................................................
MCAN_TXBAR Register Field Descriptions .........................................................................
MCAN_TXBCR Register Field Descriptions .........................................................................
MCAN_TXBTO Register Field Descriptions .........................................................................
MCAN_TXBCF Register Field Descriptions .........................................................................
MCAN_TXBTIE Register Field Descriptions .........................................................................
MCAN_TXBCIE Register Field Descriptions ........................................................................
MCAN_RES14 Register Field Descriptions ..........................................................................
MCAN_RES15 Register Field Descriptions ..........................................................................
MCAN_TXEFC Register Field Descriptions .........................................................................
MCAN_TXEFS Register Field Descriptions .........................................................................
MCAN_TXEFA Register Field Descriptions .........................................................................
MCAN_RES16 Register Field Descriptions ..........................................................................
MSS_MCAN_ECC Registers ..........................................................................................
MSS_MCAN_ECC Access Type Codes .............................................................................
MCANSS_ECC_AGGR_REVISION Register Field Descriptions .................................................
MCANSS_ECC_VECTOR Register Field Descriptions ............................................................
MCANSS_ECC_MISC_STATUS Register Field Descriptions ....................................................
MCANSS_ECC_WRAP_REVISION Register Field Descriptions .................................................
MCANSS_ECC_CONTROL Register Field Descriptions ..........................................................
MCANSS_ECC_ERR_CTRL1 Register Field Descriptions ........................................................
22-66. MCAN_RXF0S Register Field Descriptions
List of Tables
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2695
2696
2697
2698
2699
2700
2701
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
22-97. MCANSS_ECC_ERR_CTRL2 Register Field Descriptions ........................................................ 2702
22-98. MCANSS_ECC_ERR_STAT1 Register Field Descriptions ........................................................ 2703
22-99. MCANSS_ECC_ERR_STAT2 Register Field Descriptions ........................................................ 2704
22-100. MCANSS_ECC_SEC_EOI_REG Register Field Descriptions ................................................... 2705
22-101. MCANSS_ECC_SEC_STATUS_REG0 Register Field Descriptions
...........................................
2706
22-102. MCANSS_ECC_SEC_ENABLE_SET_REG0 Register Field Descriptions ..................................... 2707
22-103. MCANSS_ECC_SEC_ENABLE_CLR_REG0 Register Field Descriptions..................................... 2708
22-104. MCANSS_ECC_DED_EOI_REG Register Field Descriptions ................................................... 2709
22-105. MCANSS_ECC_DED_STATUS_REG0 Register Field Descriptions ........................................... 2710
22-106. MCANSS_ECC_DED_ENABLE_SET_REG0 Register Field Descriptions..................................... 2711
....................................
DLC Coding in CAN FD ...............................................................................................
Rx Buffer / Rx FIFO Element Size ...................................................................................
Example Filter Configuration for Rx Buffers ........................................................................
Possible Configurations for Message Transmission ..............................................................
Tx Buffer / Tx FIFO / Tx Queue Element Size .....................................................................
Rx Buffer / Rx FIFO Element Field Descriptions ..................................................................
Tx Buffer Element Field Descriptions ...............................................................................
Tx Event FIFO Element Field Descriptions .........................................................................
Standard Message ID Filter Element Field Descriptions .........................................................
Extended Message ID Filter Element Field Descriptions .........................................................
MSS_MCAN_CFG Registers .........................................................................................
SS_PID Register Field Descriptions .................................................................................
SS_CTRL Register Field Descriptions ..............................................................................
SS_STAT Register Field Descriptions ..............................................................................
SS_ICS Register Field Descriptions .................................................................................
SS_IRS Register Field Descriptions .................................................................................
SS_IECS Register Field Descriptions ...............................................................................
SS_IE Register Field Descriptions...................................................................................
SS_IES Register Field Descriptions .................................................................................
SS_EOI Register Field Descriptions ................................................................................
SS_EXT_TS_PS Register Field Descriptions ......................................................................
SS_EXT_TS_USIC Register Field Descriptions ...................................................................
CREL Register Field Descriptions ...................................................................................
ENDN Register Field Descriptions...................................................................................
CUST Register Field Descriptions ...................................................................................
DBTP Register Field Descriptions ...................................................................................
TEST Register Field Descriptions ...................................................................................
RWD Register Field Descriptions ....................................................................................
CCCR Register Field Descriptions ..................................................................................
NBTP Register Field Descriptions ...................................................................................
TSCC Register Field Descriptions ...................................................................................
TSCV Register Field Descriptions ...................................................................................
TOCC Register Field Descriptions...................................................................................
TOCV Register Field Descriptions ...................................................................................
RES00 Register Field Descriptions ..................................................................................
RES01 Register Field Descriptions ..................................................................................
RES02 Register Field Descriptions ..................................................................................
RES03 Register Field Descriptions ..................................................................................
22-107. MCANSS_ECC_DED_ENABLE_CLR_REG0 Register Field Descriptions
22-108.
22-109.
22-110.
22-111.
22-112.
22-113.
22-114.
22-115.
22-116.
22-117.
22-118.
22-119.
22-120.
22-121.
22-122.
22-123.
22-124.
22-125.
22-126.
22-127.
22-128.
22-129.
22-130.
22-131.
22-132.
22-133.
22-134.
22-135.
22-136.
22-137.
22-138.
22-139.
22-140.
22-141.
22-142.
22-143.
22-144.
22-145.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2712
2718
2731
2732
2733
2734
2739
2741
2742
2744
2745
2748
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
119
www.ti.com
22-146. ECR Register Field Descriptions..................................................................................... 2777
22-147. PSR Register Field Descriptions ..................................................................................... 2778
22-148. TDCR Register Field Descriptions ................................................................................... 2779
22-149. RES04 Register Field Descriptions .................................................................................. 2780
22-150. IR Register Field Descriptions........................................................................................ 2781
22-151. IE Register Field Descriptions ........................................................................................ 2783
22-152. ILS Register Field Descriptions ...................................................................................... 2785
22-153. ILE Register Field Descriptions ...................................................................................... 2787
22-154. RES05 Register Field Descriptions .................................................................................. 2788
22-155. RES06 Register Field Descriptions .................................................................................. 2789
22-156. RES07 Register Field Descriptions .................................................................................. 2790
22-157. RES08 Register Field Descriptions .................................................................................. 2791
22-158. RES09 Register Field Descriptions .................................................................................. 2792
22-159. RES10 Register Field Descriptions .................................................................................. 2793
22-160. RES11 Register Field Descriptions .................................................................................. 2794
22-161. RES12 Register Field Descriptions .................................................................................. 2795
22-162. GFC Register Field Descriptions..................................................................................... 2796
22-163. SIDFC Register Field Descriptions .................................................................................. 2797
22-164. XIDFC Register Field Descriptions .................................................................................. 2798
22-165. RES13 Register Field Descriptions .................................................................................. 2799
22-166. XIDAM Register Field Descriptions .................................................................................. 2800
2801
22-168. NDAT1 Register Field Descriptions
2802
22-169.
2803
22-170.
22-171.
22-172.
22-173.
22-174.
22-175.
22-176.
22-177.
22-178.
22-179.
22-180.
22-181.
22-182.
22-183.
22-184.
22-185.
22-186.
22-187.
22-188.
22-189.
22-190.
22-191.
22-192.
22-193.
22-194.
120
..................................................................................
.................................................................................
NDAT2 Register Field Descriptions .................................................................................
RXF0C Register Field Descriptions .................................................................................
RXF0S Register Field Descriptions..................................................................................
RXF0A Register Field Descriptions..................................................................................
RXBC Register Field Descriptions ...................................................................................
RXF1C Register Field Descriptions .................................................................................
RXF1S Register Field Descriptions..................................................................................
RXF1A Register Field Descriptions..................................................................................
RXESC Register Field Descriptions .................................................................................
TXBC Register Field Descriptions ...................................................................................
TXFQS Register Field Descriptions .................................................................................
TXESC Register Field Descriptions .................................................................................
TXBRP Register Field Descriptions .................................................................................
TXBAR Register Field Descriptions .................................................................................
TXBCR Register Field Descriptions .................................................................................
TXBTO Register Field Descriptions .................................................................................
TXBCF Register Field Descriptions .................................................................................
TXBTIE Register Field Descriptions .................................................................................
TXBCIE Register Field Descriptions ................................................................................
RES14 Register Field Descriptions ..................................................................................
RES15 Register Field Descriptions ..................................................................................
TXEFC Register Field Descriptions .................................................................................
TXEFS Register Field Descriptions..................................................................................
TXEFA Register Field Descriptions..................................................................................
RES16 Register Field Descriptions ..................................................................................
MSS_MCAN_ECC Registers .........................................................................................
22-167. HPMS Register Field Descriptions
List of Tables
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
22-195. REV Register Field Descriptions ..................................................................................... 2829
22-196. VECTOR Register Field Descriptions ............................................................................... 2830
22-197. STAT Register Field Descriptions
...................................................................................
2831
22-198. CTRL Register Field Descriptions ................................................................................... 2832
..........................................................................
..........................................................................
22-201. ERR_STAT1 Register Field Descriptions ...........................................................................
22-202. ERR_STAT2 Register Field Descriptions ...........................................................................
22-203. ERR_STAT3 Register Field Descriptions ...........................................................................
22-204. SEC_EOI_REG Register Field Descriptions .......................................................................
22-205. SEC_STATUS_REG0 Register Field Descriptions ................................................................
22-206. SEC_ENABLE_SET_REG0 Register Field Descriptions .........................................................
22-207. SEC_ENABLE_CLR_REG0 Register Field Descriptions .........................................................
22-208. DED_EOI_REG Register Field Descriptions .......................................................................
22-209. DED_STATUS_REG0 Register Field Descriptions................................................................
22-210. DED_ENABLE_SET_REG0 Register Field Descriptions .........................................................
22-211. DED_ENABLE_CLR_REG0 Register Field Descriptions .........................................................
22-212. AGGR_ENABLE_SET Register Field Descriptions ...............................................................
22-213. AGGR_ENABLE_CLR Register Field Descriptions ...............................................................
22-214. AGGR_STATUS_SET Register Field Descriptions ...............................................................
22-215. AGGR_STATUS_CLR Register Field Descriptions ...............................................................
23-1. Register Control From MSS-RCM Configuration Space ...........................................................
23-2. Register Control From MSS-RCM Configuration Space ...........................................................
23-3. Pin Configurations .......................................................................................................
23-4. MibSPI/SPI Configurations .............................................................................................
23-5. Clocking Modes..........................................................................................................
23-6. Pin Mapping for SIMO Pin with MSB First ...........................................................................
23-7. Pin Mapping for SOMI Pin with MSB First ...........................................................................
23-8. Pin Mapping for SIMO Pin with LSB First ............................................................................
23-9. Pin Mapping for SOMI Pin with LSB First ............................................................................
23-10. MSS_MIBSPIA Registers ..............................................................................................
23-11. MSS_MIBSPIA Access Type Codes..................................................................................
23-12. SPIGCR0 Register Field Descriptions ................................................................................
23-13. SPIGCR1 Register Field Descriptions ................................................................................
23-14. SPIINT0 Register Field Descriptions .................................................................................
23-15. SPILVL Register Field Descriptions ..................................................................................
23-16. SPIFLG Register Field Descriptions ..................................................................................
23-17. SPIPC0 Register Field Descriptions ..................................................................................
23-18. SPIPC1 Register Field Descriptions ..................................................................................
23-19. SPIPC2 Register Field Descriptions ..................................................................................
23-20. SPIPC3 Register Field Descriptions ..................................................................................
23-21. SPIPC4 Register Field Descriptions ..................................................................................
23-22. SPIPC5 Register Field Descriptions ..................................................................................
23-23. SPIPC6 Register Field Descriptions ..................................................................................
23-24. SPIDAT0 Register Field Descriptions ................................................................................
23-25. SPIDAT1 Register Field Descriptions ................................................................................
23-26. SPIBUF Register Field Descriptions ..................................................................................
23-27. SPIEMU Register Field Descriptions .................................................................................
23-28. SPIDELAY Register Field Descriptions ..............................................................................
22-199. ERR_CTRL1 Register Field Descriptions
2833
22-200. ERR_CTRL2 Register Field Descriptions
2834
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2850
2852
2853
2865
2874
2874
2875
2875
2889
2891
2892
2893
2895
2897
2898
2901
2903
2905
2906
2908
2910
2912
2914
2915
2917
2920
2922
121
www.ti.com
23-29. SPIDEF Register Field Descriptions .................................................................................. 2924
23-30. SPIFMT0 Register Field Descriptions ................................................................................ 2925
23-31. SPIFMT1 Register Field Descriptions ................................................................................ 2927
23-32. SPIFMT2 Register Field Descriptions ................................................................................ 2929
23-33. SPIFMT3 Register Field Descriptions ................................................................................ 2931
23-34. TGINTVECT0 Register Field Descriptions ........................................................................... 2933
23-35. TGINTVECT1 Register Field Descriptions ........................................................................... 2935
23-36. SPIPC9 Register Field Descriptions .................................................................................. 2937
23-37. SPIPMCTRL Register Field Descriptions ............................................................................ 2938
23-38. MIBSPIE Register Field Descriptions ................................................................................. 2941
23-39. TGITENST Register Field Descriptions .............................................................................. 2943
23-40. TGITENCR Register Field Descriptions .............................................................................. 2944
23-41. TGITLVST Register Field Descriptions ............................................................................... 2945
23-42. TGITLVCR Register Field Descriptions .............................................................................. 2946
23-43. TGINTFLAG Register Field Descriptions
............................................................................
2947
23-44. TICKCNT Register Field Descriptions ................................................................................ 2948
23-45. LTGPEND Register Field Descriptions ............................................................................... 2949
2950
23-47. TG1CTRL Register Field Descriptions
2953
23-48.
2956
23-49.
23-50.
23-51.
23-52.
23-53.
23-54.
23-55.
23-56.
23-57.
23-58.
23-59.
23-60.
23-61.
23-62.
23-63.
23-64.
23-65.
23-66.
23-67.
23-68.
23-69.
23-70.
23-71.
23-72.
23-73.
23-74.
23-75.
23-76.
23-77.
122
...............................................................................
...............................................................................
TG2CTRL Register Field Descriptions ...............................................................................
TG3CTRL Register Field Descriptions ...............................................................................
TG4CTRL Register Field Descriptions ...............................................................................
TG5CTRL Register Field Descriptions ...............................................................................
TG6CTRL Register Field Descriptions ...............................................................................
TG7CTRL Register Field Descriptions ...............................................................................
DMA0CTRL Register Field Descriptions .............................................................................
DMA1CTRL Register Field Descriptions .............................................................................
DMA2CTRL Register Field Descriptions .............................................................................
DMA3CTRL Register Field Descriptions .............................................................................
DMA4CTRL Register Field Descriptions .............................................................................
ICOUNT0 Register Field Descriptions ................................................................................
ICOUNT1 Register Field Descriptions ................................................................................
ICOUNT2 Register Field Descriptions ................................................................................
ICOUNT3 Register Field Descriptions ................................................................................
ICOUNT4 Register Field Descriptions ................................................................................
DMACNTLEN Register Field Descriptions ...........................................................................
PAR_ECC_CTRL Register Field Descriptions ......................................................................
PAR_ECC_STAT Register Field Descriptions ......................................................................
UERRADDR1 Register Field Descriptions ...........................................................................
UERRADDR0 Register Field Descriptions ...........................................................................
RXOVRN_BUF_ADDR Register Field Descriptions ................................................................
IOLPBKTSTCR Register Field Descriptions .........................................................................
EXTENDED_PRESCALE1 Register Field Descriptions............................................................
EXTENDED_PRESCALE2 Register Field Descriptions............................................................
ECCDIAG_CTRL Register Field Descriptions .......................................................................
ECCDIAG_STAT Register Field Descriptions .......................................................................
SBERRADDR1 Register Field Descriptions .........................................................................
SBERRADDR0 Register Field Descriptions .........................................................................
SPIREV Register Field Descriptions ..................................................................................
23-46. TG0CTRL Register Field Descriptions
List of Tables
2959
2962
2965
2968
2971
2974
2976
2978
2980
2982
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2997
2999
3000
3001
3002
3003
3004
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
23-78. MSS_MIBSPIB Registers .............................................................................................. 3005
23-79. MSS_MIBSPIB Access Type Codes.................................................................................. 3007
23-80. SPIGCR0 Register Field Descriptions ................................................................................ 3008
23-81. SPIGCR1 Register Field Descriptions ................................................................................ 3009
.................................................................................
..................................................................................
23-84. SPIFLG Register Field Descriptions ..................................................................................
23-85. SPIPC0 Register Field Descriptions ..................................................................................
23-86. SPIPC1 Register Field Descriptions ..................................................................................
23-87. SPIPC2 Register Field Descriptions ..................................................................................
23-88. SPIPC3 Register Field Descriptions ..................................................................................
23-89. SPIPC4 Register Field Descriptions ..................................................................................
23-90. SPIPC5 Register Field Descriptions ..................................................................................
23-91. SPIPC6 Register Field Descriptions ..................................................................................
23-92. SPIDAT0 Register Field Descriptions ................................................................................
23-93. SPIDAT1 Register Field Descriptions ................................................................................
23-94. SPIBUF Register Field Descriptions ..................................................................................
23-95. SPIEMU Register Field Descriptions .................................................................................
23-96. SPIDELAY Register Field Descriptions ..............................................................................
23-97. SPIDEF Register Field Descriptions ..................................................................................
23-98. SPIFMT0 Register Field Descriptions ................................................................................
23-99. SPIFMT1 Register Field Descriptions ................................................................................
23-100. SPIFMT2 Register Field Descriptions ...............................................................................
23-101. SPIFMT3 Register Field Descriptions ...............................................................................
23-102. TGINTVECT0 Register Field Descriptions .........................................................................
23-103. TGINTVECT1 Register Field Descriptions .........................................................................
23-104. SPIPC9 Register Field Descriptions .................................................................................
23-105. SPIPMCTRL Register Field Descriptions ...........................................................................
23-106. MIBSPIE Register Field Descriptions ...............................................................................
23-107. TGITENST Register Field Descriptions .............................................................................
23-108. TGITENCR Register Field Descriptions ............................................................................
23-109. TGITLVST Register Field Descriptions .............................................................................
23-110. TGITLVCR Register Field Descriptions .............................................................................
23-111. TGINTFLAG Register Field Descriptions ...........................................................................
23-112. TICKCNT Register Field Descriptions...............................................................................
23-113. LTGPEND Register Field Descriptions .............................................................................
23-114. TG0CTRL Register Field Descriptions ..............................................................................
23-115. TG1CTRL Register Field Descriptions ..............................................................................
23-116. TG2CTRL Register Field Descriptions ..............................................................................
23-117. TG3CTRL Register Field Descriptions ..............................................................................
23-118. TG4CTRL Register Field Descriptions ..............................................................................
23-119. TG5CTRL Register Field Descriptions ..............................................................................
23-120. TG6CTRL Register Field Descriptions ..............................................................................
23-121. TG7CTRL Register Field Descriptions ..............................................................................
23-122. DMA0CTRL Register Field Descriptions ............................................................................
23-123. DMA1CTRL Register Field Descriptions ............................................................................
23-124. DMA2CTRL Register Field Descriptions ............................................................................
23-125. DMA3CTRL Register Field Descriptions ............................................................................
23-126. DMA4CTRL Register Field Descriptions ............................................................................
23-82. SPIINT0 Register Field Descriptions
3011
23-83. SPILVL Register Field Descriptions
3013
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
3014
3017
3019
3021
3022
3024
3026
3028
3030
3031
3033
3036
3038
3040
3041
3043
3045
3047
3049
3051
3053
3054
3057
3059
3060
3061
3062
3063
3064
3065
3066
3069
3072
3075
3078
3081
3084
3087
3090
3092
3094
3096
3098
123
www.ti.com
..............................................................................
23-128. ICOUNT1 Register Field Descriptions ..............................................................................
23-129. ICOUNT2 Register Field Descriptions ..............................................................................
23-130. ICOUNT3 Register Field Descriptions ..............................................................................
23-131. ICOUNT4 Register Field Descriptions ..............................................................................
23-132. DMACNTLEN Register Field Descriptions .........................................................................
23-133. PAR_ECC_CTRL Register Field Descriptions .....................................................................
23-134. PAR_ECC_STAT Register Field Descriptions .....................................................................
23-135. UERRADDR1 Register Field Descriptions .........................................................................
23-136. UERRADDR0 Register Field Descriptions .........................................................................
23-137. RXOVRN_BUF_ADDR Register Field Descriptions ...............................................................
23-138. IOLPBKTSTCR Register Field Descriptions .......................................................................
23-139. EXTENDED_PRESCALE1 Register Field Descriptions ..........................................................
23-140. EXTENDED_PRESCALE2 Register Field Descriptions ..........................................................
23-141. ECCDIAG_CTRL Register Field Descriptions .....................................................................
23-142. ECCDIAG_STAT Register Field Descriptions......................................................................
23-143. SBERRADDR1 Register Field Descriptions ........................................................................
23-144. SBERRADDR0 Register Field Descriptions ........................................................................
23-145. SPIREV Register Field Descriptions ................................................................................
23-146. Multi-Buffer RAM Register ............................................................................................
23-147. Multi-buffer RAM Transmit Data Register Field Descriptions ....................................................
23-148. Multi-buffer Receive Buffer Register Field Descriptions ..........................................................
24-1. SPI Clock Modes Definition ............................................................................................
24-2. QSPI Events .............................................................................................................
24-3. MSS_QSPI Registers ...................................................................................................
24-4. MSS_QSPI Access Type Codes ......................................................................................
24-5. PID Register Field Descriptions .......................................................................................
24-6. SYSCONFIG Register Field Descriptions ............................................................................
24-7. INTR_STATUS_RAW_SET Register Field Descriptions ...........................................................
24-8. INTR_STATUS_ENABLED_CLEAR Register Field Descriptions.................................................
24-9. INTR_ENABLE_SET Register Field Descriptions ..................................................................
24-10. INTR_ENABLE_CLEAR Register Field Descriptions ...............................................................
24-11. INTC_EOI Register Field Descriptions ...............................................................................
24-12. SPI_CLOCK_CNTRL Register Field Descriptions ..................................................................
24-13. SPI_DC Register Field Descriptions ..................................................................................
24-14. SPI_CMD Register Field Descriptions ................................................................................
24-15. SPI_STATUS Register Field Descriptions ...........................................................................
24-16. SPI_DATA Register Field Descriptions...............................................................................
24-17. SPI_SETUP0 Register Field Descriptions ...........................................................................
24-18. SPI_SETUP1 Register Field Descriptions ...........................................................................
24-19. SPI_SETUP2 Register Field Descriptions ...........................................................................
24-20. SPI_SETUP3 Register Field Descriptions ...........................................................................
24-21. SPI_SWITCH Register Field Descriptions ...........................................................................
24-22. SPI_DATA1 Register Field Descriptions .............................................................................
24-23. SPI_DATA2 Register Field Descriptions .............................................................................
24-24. SPI_DATA3 Register Field Descriptions .............................................................................
25-1. Ways to Generate a NACK Bit ........................................................................................
25-2. Interrupt Requests Generated by I2C Module .......................................................................
25-3. MSS_I2C Registers .....................................................................................................
23-127. ICOUNT0 Register Field Descriptions
124
List of Tables
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3113
3115
3116
3117
3118
3119
3120
3122
3123
3125
3142
3145
3147
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3177
3182
3185
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
25-4.
MSS_I2C Access Type Codes ........................................................................................ 3185
25-5.
ICOAR Register Field Descriptions ................................................................................... 3186
25-6.
ICIMR Register Field Descriptions .................................................................................... 3187
25-7.
ICSTR Register Field Descriptions.................................................................................... 3188
25-8.
ICCLKL Register Field Descriptions .................................................................................. 3190
25-9.
ICCLKH Register Field Descriptions .................................................................................. 3191
25-10. ICCNT Register Field Descriptions
...................................................................................
3192
25-11. ICDRR Register Field Descriptions ................................................................................... 3193
...................................................................................
ICDXR Register Field Descriptions ...................................................................................
ICMDR Register Field Descriptions ...................................................................................
ICIVR Register Field Descriptions ....................................................................................
ICEMDR Register Field Descriptions .................................................................................
ICPSC Register Field Descriptions ...................................................................................
ICPID1 Register Field Descriptions ...................................................................................
ICPID2 Register Field Descriptions ...................................................................................
ICDMAC Register Field Descriptions .................................................................................
ICPFUNC Register Field Descriptions ................................................................................
ICPDIR Register Field Descriptions ..................................................................................
ICPDIN Register Field Descriptions ..................................................................................
ICPDOUT Register Field Descriptions ...............................................................................
ICPDSET Register Field Descriptions ................................................................................
ICPDCLR Register Field Descriptions ................................................................................
ICPDRV Register Field Descriptions .................................................................................
SCI Interrupts ............................................................................................................
DMA and Interrupt Requests in Multiprocessor Modes ............................................................
SCI Control Registers Summary ......................................................................................
SCI Global Control Register 0 (SCIGCR0) Fied Descriptions .....................................................
SCI Global Control Register 1 (SCIGCR1) Field Descriptions ....................................................
SCI Set Interrupt Register (SCISETINT) Field Descriptions .......................................................
SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions.................................................
SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions ...........................................
SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions ....................................
SCI Flags Register (SCIFLR) Field Descriptions....................................................................
SCI Receiver Status Flags ............................................................................................
SCI Transmitter Status Flags .........................................................................................
SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................
SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................
SCI Format Control Register (SCIFORMAT) Field Descriptions ..................................................
Baud Rate Selection Register (BRS) Field Descriptions ..........................................................
Comparative Baud Values for Different P Values, Asynchronous Mode ........................................
Receiver Emulation Data Buffer (SCIED) Field Descriptions ......................................................
Receiver Data Buffer (SCIRD) Field Descriptions ..................................................................
Transmit Data Buffer Register (SCITD) Field Descriptions ........................................................
SCI Pin I/O Control Register 0 (SCIPIO0) Field Descriptions .....................................................
SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions .....................................................
SCITX Pin Control ......................................................................................................
SCIRX Pin Control .....................................................................................................
SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions ....................................................
25-12. ICSAR Register Field Descriptions
3194
25-13.
3195
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
26-25.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
3196
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3223
3224
3229
3230
3231
3234
3236
3238
3239
3241
3244
3244
3245
3245
3246
3247
3247
3248
3248
3249
3249
3250
3250
3250
3251
125
www.ti.com
3252
26-27.
3253
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
27-1.
27-2.
27-3.
27-4.
27-5.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
28-25.
28-26.
28-27.
28-28.
28-29.
28-30.
28-31.
28-32.
28-33.
28-34.
28-35.
28-36.
126
....................................................
SCI Pin I/O Control Register 4 (SCIPIO4) Field Descriptions ....................................................
SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions ....................................................
SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions .....................................................
SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions .....................................................
SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions ....................................................
Input/Output Error Enable Register (IODFTCTRL) Field Descriptions ...........................................
Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ...........................................
14xx Debug Subsystem Address Map ...............................................................................
16xx/18xx/68xx Debug Subsystem Address Map ..................................................................
MSS CTI Trigger Inputs ................................................................................................
MSS CTI Trigger Outputs ..............................................................................................
Debug SS CTI Trigger Inputs ..........................................................................................
DCC Registers ...........................................................................................................
DCC Access Type Codes ..............................................................................................
DCCGCTRL Register Field Descriptions .............................................................................
DCCREV Register Field Descriptions ................................................................................
DCCCNTSEED0 Register Field Descriptions .......................................................................
DCCVALIDSEED0 Register Field Descriptions .....................................................................
DCCCNTSEED1 Register Field Descriptions .......................................................................
DCCSTAT Register Field Descriptions ...............................................................................
DCCCNT0 Register Field Descriptions ...............................................................................
DCCVALID0 Register Field Descriptions ............................................................................
DCCCNT1 Register Field Descriptions ...............................................................................
DCCCLKSSRC1 Register Field Descriptions........................................................................
DCCCLKSSRC0 Register Field Descriptions........................................................................
ESM Interrupt and ERROR Pin Behavior ............................................................................
MSS_ESM Registers ...................................................................................................
MSS_ESM Access Type Codes .......................................................................................
ESMIEPSR1 Register Field Descriptions ............................................................................
ESMIEPCR1 Register Field Descriptions ............................................................................
ESMIESR1 Register Field Descriptions ..............................................................................
ESMIECR1 Register Field Descriptions ..............................................................................
ESMILSR1 Register Field Descriptions ..............................................................................
ESMILCR1 Register Field Descriptions ..............................................................................
ESMSR1 Register Field Descriptions.................................................................................
ESMSR2 Register Field Descriptions.................................................................................
ESMSR3 Register Field Descriptions.................................................................................
ESMEPSR Register Field Descriptions ..............................................................................
ESMIOFFHR Register Field Descriptions ............................................................................
ESMIOFFLR Register Field Descriptions ............................................................................
ESMLTCR Register Field Descriptions ...............................................................................
ESMLTCPR Register Field Descriptions .............................................................................
ESMEKR Register Field Descriptions ................................................................................
ESMSSR2 Register Field Descriptions ...............................................................................
ESMIEPSR4 Register Field Descriptions ............................................................................
ESMIEPCR4 Register Field Descriptions ............................................................................
ESMIESR4 Register Field Descriptions ..............................................................................
ESMIECR4 Register Field Descriptions ..............................................................................
26-26. SCI Pin I/O Control Register 3 (SCIPIO3) Field Descriptions
List of Tables
3254
3255
3256
3256
3257
3260
3262
3262
3263
3263
3263
3271
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3284
3289
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
28-37. ESMILSR4 Register Field Descriptions .............................................................................. 3310
28-38. ESMILCR4 Register Field Descriptions .............................................................................. 3311
28-39. ESMSR4 Register Field Descriptions................................................................................. 3312
28-40. ESMIEPSR7 Register Field Descriptions ............................................................................ 3313
28-41. ESMIEPCR7 Register Field Descriptions ............................................................................ 3314
28-42. ESMIESR7 Register Field Descriptions .............................................................................. 3315
28-43. ESMIECR7 Register Field Descriptions .............................................................................. 3316
28-44. ESMILSR7 Register Field Descriptions .............................................................................. 3317
28-45. ESMILCR7 Register Field Descriptions .............................................................................. 3318
28-46. ESMSR7 Register Field Descriptions................................................................................. 3319
28-47. CRC Modes in Which DMA Request and Counter Logic are Active or Inactive ................................ 3326
28-48. Modes in Which Interrupt Condition Can Occur ..................................................................... 3327
28-49. Interrupt Offset Mapping................................................................................................ 3330
28-50. DCC Registers ........................................................................................................... 3335
28-51. DCC Access Type Codes .............................................................................................. 3335
28-52. DCCGCTRL Register Field Descriptions ............................................................................. 3336
28-53. DCCREV Register Field Descriptions ................................................................................ 3337
28-54. DCCCNTSEED0 Register Field Descriptions
.......................................................................
3338
28-55. DCCVALIDSEED0 Register Field Descriptions ..................................................................... 3339
28-56. DCCCNTSEED1 Register Field Descriptions
.......................................................................
3340
28-57. DCCSTAT Register Field Descriptions ............................................................................... 3341
28-58. DCCCNT0 Register Field Descriptions ............................................................................... 3342
28-59. DCCVALID0 Register Field Descriptions
............................................................................
3343
28-60. DCCCNT1 Register Field Descriptions ............................................................................... 3344
28-61. DCCCLKSSRC1 Register Field Descriptions........................................................................ 3345
28-62. DCCCLKSSRC0 Register Field Descriptions........................................................................ 3346
28-63. Register Base Address (16xx/18xx) .................................................................................. 3347
28-64. Register Base Address (14xx) ......................................................................................... 3347
28-65. PBIST Registers ......................................................................................................... 3351
28-66. PBIST Access Type Codes ............................................................................................ 3351
28-67. PBIST_DLR Register Field Descriptions ............................................................................. 3352
28-68. PBIST_PACT Register Field Descriptions ........................................................................... 3353
28-69. PBIST_ID Register Field Descriptions ................................................................................ 3354
............................................................................
PBIST_FSFR0 Register Field Descriptions ..........................................................................
PBIST_FSFR1 Register Field Descriptions ..........................................................................
PBIST_FSRCR0 Register Field Descriptions........................................................................
PBIST_FSRCR1 Register Field Descriptions........................................................................
PBIST_ROM Register Field Descriptions ............................................................................
PBIST_ALGO Register Field Descriptions ...........................................................................
PBIST_RINFOL Register Field Descriptions ........................................................................
PBIST_RINFOU Register Field Descriptions ........................................................................
Memory Map for 16xx/18xx ............................................................................................
Memory Map for 14xx...................................................................................................
ROM Organization for 2 Intervals .....................................................................................
STC Registers ...........................................................................................................
STC Access Type Codes ..............................................................................................
STCGCR0 Register Field Descriptions ...............................................................................
STCGCR1 Register Field Descriptions ...............................................................................
28-70. PBIST_OVR Register Field Descriptions
3355
28-71.
3356
28-72.
28-73.
28-74.
28-75.
28-76.
28-77.
28-78.
28-79.
28-80.
28-81.
28-82.
28-83.
28-84.
28-85.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
3357
3358
3359
3360
3361
3362
3363
3363
3364
3369
3376
3377
3378
3379
127
www.ti.com
28-86. STCTPR Register Field Descriptions ................................................................................. 3380
28-87. STC_CADDR Register Field Descriptions ........................................................................... 3381
28-88. STCCICR Register Field Descriptions ................................................................................ 3382
28-89. STCGSTAT Register Field Descriptions ............................................................................. 3383
28-90. STCFSTAT Register Field Descriptions .............................................................................. 3384
28-91. STCSCSCR Register Field Descriptions ............................................................................. 3385
28-92. STC_CADDR2 Register Field Descriptions .......................................................................... 3386
28-93. STC_CLKDIV Register Field Descriptions ........................................................................... 3387
28-94. STC_SEGPLR Register Field Descriptions .......................................................................... 3388
28-95. SEG0_START_ADDR Register Field Descriptions ................................................................. 3389
28-96. SEG1_START_ADDR Register Field Descriptions ................................................................. 3390
28-97. SEG2_START_ADDR Register Field Descriptions ................................................................. 3391
28-98. SEG3_START_ADDR Register Field Descriptions ................................................................. 3392
28-99. CORE1_CURMISR_0 Register Field Descriptions ................................................................. 3393
28-100. CORE1_CURMISR_1 Register Field Descriptions ................................................................ 3394
28-101. CORE1_CURMISR_2 Register Field Descriptions ................................................................ 3395
28-102. CORE1_CURMISR_3 Register Field Descriptions ................................................................ 3396
28-103. CORE1_CURMISR_4 Register Field Descriptions ................................................................ 3397
28-104. CORE1_CURMISR_5 Register Field Descriptions ................................................................ 3398
28-105. CORE1_CURMISR_6 Register Field Descriptions ................................................................ 3399
28-106. CORE1_CURMISR_7 Register Field Descriptions ................................................................ 3400
28-107. CORE1_CURMISR_8 Register Field Descriptions ................................................................ 3401
28-108. CORE1_CURMISR_9 Register Field Descriptions ................................................................ 3402
3403
28-110.
3404
28-111.
28-112.
28-113.
28-114.
28-115.
28-116.
28-117.
28-118.
28-119.
28-120.
28-121.
28-122.
28-123.
28-124.
28-125.
28-126.
28-127.
28-128.
28-129.
28-130.
28-131.
28-132.
28-133.
28-134.
128
..............................................................
CORE1_CURMISR_11 Register Field Descriptions ..............................................................
CORE1_CURMISR_12 Register Field Descriptions ..............................................................
CORE1_CURMISR_13 Register Field Descriptions ..............................................................
CORE1_CURMISR_14 Register Field Descriptions ..............................................................
CORE1_CURMISR_15 Register Field Descriptions ..............................................................
CORE1_CURMISR_16 Register Field Descriptions ..............................................................
CORE1_CURMISR_17 Register Field Descriptions ..............................................................
CORE1_CURMISR_18 Register Field Descriptions ..............................................................
CORE1_CURMISR_19 Register Field Descriptions ..............................................................
CORE1_CURMISR_20 Register Field Descriptions ..............................................................
CORE1_CURMISR_21 Register Field Descriptions ..............................................................
CORE1_CURMISR_22 Register Field Descriptions ..............................................................
CORE1_CURMISR_23 Register Field Descriptions ..............................................................
CORE1_CURMISR_24 Register Field Descriptions ..............................................................
CORE1_CURMISR_25 Register Field Descriptions ..............................................................
CORE1_CURMISR_26 Register Field Descriptions ..............................................................
CORE1_CURMISR_27 Register Field Descriptions ..............................................................
CORE2_CURMISR_0 Register Field Descriptions ................................................................
CORE2_CURMISR_1 Register Field Descriptions ................................................................
CORE2_CURMISR_2 Register Field Descriptions ................................................................
CORE2_CURMISR_3 Register Field Descriptions ................................................................
CORE2_CURMISR_4 Register Field Descriptions ................................................................
CORE2_CURMISR_5 Register Field Descriptions ................................................................
CORE2_CURMISR_6 Register Field Descriptions ................................................................
CORE2_CURMISR_7 Register Field Descriptions ................................................................
28-109. CORE1_CURMISR_10 Register Field Descriptions
List of Tables
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
28-135. CORE2_CURMISR_8 Register Field Descriptions ................................................................ 3429
28-136. CORE2_CURMISR_9 Register Field Descriptions ................................................................ 3430
..............................................................
..............................................................
CORE2_CURMISR_12 Register Field Descriptions ..............................................................
CORE2_CURMISR_13 Register Field Descriptions ..............................................................
CORE2_CURMISR_14 Register Field Descriptions ..............................................................
CORE2_CURMISR_15 Register Field Descriptions ..............................................................
CORE2_CURMISR_16 Register Field Descriptions ..............................................................
CORE2_CURMISR_17 Register Field Descriptions ..............................................................
CORE2_CURMISR_18 Register Field Descriptions ..............................................................
CORE2_CURMISR_19 Register Field Descriptions ..............................................................
CORE2_CURMISR_20 Register Field Descriptions ..............................................................
CORE2_CURMISR_21 Register Field Descriptions ..............................................................
CORE2_CURMISR_22 Register Field Descriptions ..............................................................
CORE2_CURMISR_23 Register Field Descriptions ..............................................................
CORE2_CURMISR_24 Register Field Descriptions ..............................................................
CORE2_CURMISR_25 Register Field Descriptions ..............................................................
CORE2_CURMISR_26 Register Field Descriptions ..............................................................
CORE2_CURMISR_27 Register Field Descriptions ..............................................................
28-137. CORE2_CURMISR_10 Register Field Descriptions
3431
28-138. CORE2_CURMISR_11 Register Field Descriptions
3432
28-139.
3433
28-140.
28-141.
28-142.
28-143.
28-144.
28-145.
28-146.
28-147.
28-148.
28-149.
28-150.
28-151.
28-152.
28-153.
28-154.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
129
Preface
SWRU522D – May 2017 – Revised September 2019
Trademarks
ICEPick-D, TMS320C674x, TMS320C64x+, C64x+, TMS320C64x+, C64x+, TMS320C64x+, C64x+ are
trademarks of Texas Instruments.
JTAG is a registered trademark of JTAG Technologies B.V..
130
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Chapter 1
SWRU522D – May 2017 – Revised September 2019
14xx
Topic
1.1
1.2
1.3
...........................................................................................................................
Page
14xx Introduction.............................................................................................. 132
14xx Memory Map............................................................................................. 135
14xx Integration................................................................................................ 140
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
131
14xx Introduction
1.1
www.ti.com
14xx Introduction
1.1.1 14xx Overview
The 14xx is highly integrated single-chip RADAR device in TI’s 45-nm low-power RFCMOS technology, a
FCBGA 0.65-mm pitch automotive-grade package.
1.1.1.1 Features
• Frequency-Modulated Continuous Wave Radio Frequency Transceiver With 76-81-GHz Band
• Supports Three Transmitter Chains and Four Receiver Chains
• Chirp Profiles With Programmable Period and Slope
• 40-MHz XTAL/OSC Reference Input Clock
• 12, 14, and 16-bit Real/Complex ADC With Variable Baseband ADC Sampling Rates up to 18.75 MHz
at 12-bits Complex
• Cortex R4F at 200-MHz Application Processor for Control Functionality and Safety-Critical Algorithms
• Cortex R4F– Radio Processor at 200 MHz for Continuous Monitoring and Calibration of Analog/RF
Functionality
• High-Performance Data Transfer With Multiple DMA and EDMA-TPCC Engines
• CAN Support for ECU Interface
• QSPI Serial Flash Support
• MIBSPI, SPI, I2C, and UART Serial Interfaces Support
• Four Data, One Clock Lane Serial LVDS Interface Support
1.1.2 14xx Description
1.1.2.1
Block Diagram
Figure 1-1 shows the block diagram of the 14xx device.
132
14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Introduction
www.ti.com
Figure 1-1. 14xx Block Diagram
Cortex R4F
@ 200MHz
LNA
IF
ADC
LNA
IF
ADC
Digital
Front-end
LNA
IF
ADC
(Decimation
filter chain)
LNA
IF
ADC
(User programmable)
Prog RAM*
Radar Data
Memory*
Data RAM*
Boot
ROM
QSPI
SPI
PA
PA
Osc.
ADC
Buffer
ΔΦ
ΔΦ
x4
Synth
(20 GHz)
Ramp
Generator
Temp
RF/Analog sub-system
DCAN
PMIC control
Primary communication
interface (automotive)
DMA
Debug
UARTs
(For RF Calibration
& Self-test – TI
programmed)
Mailbox
Test/
Debug
JTAG for debug/
development
LVDS/
CSI2
High-speed ADC output
interface (for recording)
Prog RAM
& ROM
GPADC
(FFT, LogMag, etc.)
SPI / I2C
Optional External
MCU interface
Radio (BIST)
processor
ΔΦ
VMON
Radar
Hardware
Accelerator
Bus Matrix
PA
Serial Flash interface
Data
RAM
Radio processor
sub-system
Master sub-system
(TI programmed)
(Customer programmed)
For debug
* Total RAM available in Master sub-system is 576 KB (for Cortex R4F Program RAM, Data RAM and Radar Data Memory)
Table 1-1. 14xx Acronyms
ADC
Analog-to-Digital Convertor
CSI-2
Camera Serial Interface 2
DCAN
Controller Area Network
DMA
Direct Memory Access
GPADC
General Purpose Analog-to-Digital Convertor
I2C
Inter-Integrated Circuit
IF
Intermediate Frequency
LNA
Low-Noise Amplifier
LVDS
Low Voltage Differential Signaling
Osc
Oscillator
PA
Power Amplifier
QSPI
Quad Serial Peripheral Interface
SPI
Serial Peripheral Interface
UART
Univeral Asynchronous Receiver/Transmitter
VMON
Voltage Monitor
ΔΦ
Phase Modulator
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
133
14xx Introduction
1.1.2.2
www.ti.com
Radar Subsystem
The RADAR subsystem is responsible for the RF and analog functionality of the device. The subsystem
incorporates a built-in self-test processor for the continuous motoring and calibration of the analog and RF
modules. The subsystem consists of:
• FMCW transceiver
– Integrated PLL, transmitter, receiver, baseband, and A2D
– 76-81-GHz coverage with 4-GHz available bandwidth
– Four receive channels
– Two transmit channels
– Ultra-accurate chirp engine based on fractional-n PLL
– 12,14, or 16-bit complex analog to digital converter
• Radio processor for built-in calibration and self-test
– ARM Cortex R4F-based radio control system
– Built-in firmware (ROM)
– Self-calibrating system across frequency and temperature
This subsystem is TI-programmed with an API interface to the on-chip Cortex-R4F application processor.
1.1.2.3
Master Subsystem
The master subsystem consists of the following features:
• Dual Cortex-R4F core ARMv7-R, VFPv3-D16, and ARMv7 debug architecture
• Tightly-coupled memories
– 96 KB of ROM
– 128KB of program RAM with ECC
– 64KB of data RAM with ECC
• Hardware auto-initialization of the memories
• Vectored interrupt manager for prioritizing and controlling the interrupts for different sources
1.1.2.3.1 Serial Interfaces
• One DCAN controller supporting bit rates of up to 1 Mbit/s, and compliant to the controller area
network (CAN) 2.0B protocol specification
• One I2C controller module with rates up to 400 kbps
• Two high-speed synchronous serial input/output MIBSPI modules
• Two serial communication interface (SCI) modules implementing standard universal asynchronous
receiver-transmitter (UART)
• One quad SPI module support with maximum rate of 40 MHz
1.1.2.3.2
•
•
•
•
•
134
System Peripherals
Multiple general-purpose input/output (GPIO) modules
Direct memory access modules for high-performance data transfers
One watchdog timer and a general purpose timer implemented by the real-time interrupt (RTI) modules
Mailbox module for interprocessor communication
System reset and control module, which contains registers for the following functions:
– Status
– Efuse logic
– I/O configuration
– PAD configuration
– System boot decoding logic
14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Memory Map
www.ti.com
1.1.2.4
Functional Safety Deliverables
See the Device Safety Manual for supported features.
1.1.2.5
On-Chip Debug Support
The on-chip debug support has the following features:
• The following device cores can be debugged through Code Composer Studio (CCS):
– Cortex-R4F
• Target debugging using IEEE1149.1 (JTAG®) port
• The debug subsystem includes:
– IEEE1149.7 adapter
– Generic TAP for emulation and test control (ICEPick-D™)
– Debug access port (DAP)
– Embedded trace macro (ETM)
– Trace port interface Unit (TPIU)
– Embedded trace buffer (ETB)
1.2
14xx Memory Map
1.2.1 System Interconnect
The device implements a system interconnect based on TI’s common bus architecture, comprising of
VBUSM and VBUSP protocols. Figure 1-2 shows the interconnect diagram.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
135
14xx Memory Map
www.ti.com
Figure 1-2. System Interconnect
RADAR
Subsystem
MSS_MBOX4GEM
GEM_MBOX4MSS
MSS_MBOX4BSS
BSS_MBOX4MSS
MSS_DEBUGSS
MSS_DMA
Primary SCR(64bit)
PCR Bridge
MSS_CRC
MSS_QSPI
Master
Cortex-R4F
Subsystem
Bridge
Bridge
DSS_ADCBUF
DSS_L3RAM
LVDS TX
PRCM
MSS_ESM
MSS_VIM
MSS_IOMUX
MSS_RTIA
MSS_PBIST
MSS_RTIB
MSS_DCAN
SCR(128 bit)
PCR
Bridge
CSI2
E
D
M
A
DSS_CBUFF
DSS_TPCC
MSS_SCIA
MSS_I2C
MSS_SCIB
MSS_DCCA
MSS_MIBSPIA
MSS_DCCB
MSS_MIBSPIB
DSS_FFT_ACC_DMA1
DSS_FFT_ACC_DMA2
PCR 32-bit
eFuse logic
DSS_TPTC0
DSS_TPTC1
DSS_HW_ACC
MSS_GIO
PCR-2 32-bit
DSS_REG-1
BUS Master
Bus-Slave
The system interconnect is designed for the high-performance needs of the system. Its divided into
interconnect systems local to each subsystem: the RADAR subsystem and master subsystem. The
interconnection of all these subsystems is shown in .
In the master subsystem, the primary VBUSM SCR is responsible for managing the arbitration priority
between accesses from multiple masters to each of the slaves. The arbitration priority is always roundrobin.
The master subsystem has PCR interconnect that manages the accesses to the peripheral registers and
peripheral memories, and provides a global reset for all peripherals. It also supports the capability to
selectively enable or disable the clock for each peripheral individually. The PCR also manages the
accesses to the system module registers required to configure the device clocks, interrupts, and so forth.
The system module registers include status flags for indicating exception conditions – resets, aborts,
errors, and interrupts.
1.2.2 Master Subsystem Cortex-R4F Memory Map
Table 3-2 shows the master subsystem, Cortex-R4F memory map.
136
14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Memory Map
www.ti.com
Table 1-2. Master Subsystem, Cortex-R4F Memory Map
Module Name
Frame Address (Hex)
Size Used
Description
96KiB
MSS_TCMA_ROM (TCMA) Program ROM
(refer to ROM Eclipsing section)
Start
End
MSS_TCMA_ROM
0x0000_0000
0x0001_7FFF
Reserved
0x0001 8000
0x001F_FFFF
MSS_TCMA_RAM
0x0020_0000
0x07FF_FFFF
128KiB
MSS_TCMA_RAM (TCMA) size varies
based on device and DSS_L3 (L3) sharing
options configured (refer to ROM Eclipsing
section)
MSS_TCMB
0x0800_0000
0x0802_FFFF
64KiB
MSS_TCMB (TCMB) Data RAM
Reserved
0x0C20 0000
0x4FFF_FFFF
DSS_TPTC0
0x5000_0000
0x5000_03FF
1 KiB
DSS_TPTC0 (EDMA TPTC0) module
configuration space
DSS_REG
0x5000_0400
0x5000_07FF
584B
DSS_REG (DSPSS) control module
registers
DSS_TPTC1
0x5000_0800
0x5000_0BFF
1 KiB
DSS_TPTC1 (EDMA TPTC1) module
configuration space
Reserved
0x5000 0C00
0x5000_FFFF
DSS_TPCC
0x5001_0000
0x5001_FFFF
Reserved
0x5002 0000
0x5005_FFFF
CSI2
0x5006_0000
0x5006_03FF
512B
CSI2 (CSI2) configuration register space
(refer to HSI chapter)
CSI2 DHY
0x5006_0200
0x5006_05FF
64B
CSI2-DHY (CSI2) space (refer to HSI
chapter)
Reserved
0x5006_0600
0x5006_FFFF
DSS_CBUFF
(CSI/LVDS CBUF)
0x5007_0000
0x5007_FFFF
564B
DSS_CBUFF (CBUFF) module
configuration registers (refer to HSI
chapter)
DSS_HW_ACC_PARA
M
0x5008_0000
0x5008_07FF
512B
DSS_HW_ACC_PARAM (HWA) FFT
accelerator PARAM memory
DSS_HW_ACC_STATI
C
0x5008_0800
0x5008_0FFF
264B
DSS_HW_ACC_STATIC (HWA) FFT
accelerator configuration registers
DSS_HW_ACC_WIN
0x5008_1000
0x5008_FFFF
4KiB
DSS_HW_ACC_WIN (HWA) FFT
accelerator Window registers
Reserved
0x5009_0000
0x50FF_FFFF
DSS_L3RAM
0x5100_0000
0x51FF_FFFF
384KiB
DSS_L3RAM (L3) shared memory space
DSS_ADCBUF
0x5200_0000
0x5201_FFFF
16KiB
DSS_ADCBUF (ADC) buffer memory
space
DSS_CBUFF_FIFO
0x5202_0000
0x5202_7FFF
16KiB
DSS_CBUFF_FIFO (CBUFF) Common
buffer FIFO space (refer to HSI chapter)
Reserved
0x5202 8000
0x5202_FFFF
DSS_FFT_ACC_DMA1
0x5203_0000
0x5203_7FFF
32KiB
DSS_FFT_ACC_DMA1 (HWA DMA) FFT
accelerator Memory -1 space
DSS_FFT_ACC_DMA2
0x5203_8000
0x5206_FFFF
32KiB
DSS_FFT_ACC_DMA2 (HWA DMA) FFT
accelerator Memory -2 space
DSS_REG_VBUSM
0x5207_0000
0x5207_07FF
128B
DSS_REG_VBUSM 128-bit SCR
configuration port
DSS_DATA_TXFR_RA
M
0x5207_0800
0xBFFF_FFFF
8KiB
DSS_DATA_TXFR_RAM memory space
EXT_FLASH
0xC000_0000
0xC07F_FFFF
8MB
MSS_QSPI (QSPI) flash memory space
MSS_QSPI
0xC080_0000
0xC0FF_FFFF
116B
MSS_QSPI (QSPI) module configuration
registers
MSS_MBOX4BSS
0xF060_1000
0xF060_17FF
2KiB
MSS_MBOX4BSS mailbox memory space
BSS_MBOX4MSS
0xF060_2000
0xF060_27FF
2KiB
BSS_MBOX4MSS mailbox memory space
Reserved
0xF060_4000
0xF060_7FFF
Reserved (refer to ROM Eclipsing section)
Reserved
Reserved
64 KiB
DSS_TPCC (EDMA TPCC0) module
configuration space
Reserved
Reserved
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Reserved
14xx 137
14xx Memory Map
www.ti.com
Table 1-2. Master Subsystem, Cortex-R4F Memory Map (continued)
Module Name
Frame Address (Hex)
Start
Size Used
Description
188B
BSS_MBOX4MSS_REG mailbox
Configuration registers
End
BSS_MBOX4MSS_REG 0xF060_8000
0xF060_80FF
Reserved
0xF060_8100
0xF060_85FF
MSS_MBOX4BSS_REG 0xF060_8600
0xF060_86FF
Reserved
0xFCF7_8C00
0xFCFF_0FFF
MSS_PCR2
0xFCFF_1000
0xFCFF_17FF
Reserved
0xFCFF_F600
0xFDFF_FFFF
MSS_MCRC
0xFE00_0000
0xFEFF_FFFF
Reserved
Reserved
188B
MSS_MBOX4BSS_REG mailbox
Configuration registers
Reserved
1KiB
MSS_PCR2 (PCR_2) interconnect
configuration port
Reserved
16KiB
MSS_MCRC (CRC) module configuration
registers (refer to Safety chapter)
0xFF0C_0000
0xFF0D_FFFF
MSS_MIBSPIA_TXRAM 0xFF0E_0000
0xFF0E_01FF
0.5KB
MSS_MIBSPIA_TXRAM (MIBSPIA)
memory space
MSS_MIBSPIA_RXRAM 0xFF0E_0200
0xFF0E_03FF
0.5KB
MSS_MIBSPIA_RXRAM (MIBSPIA)
memory space
MSS_DCAN_MEM
0xFF1E_0000
0xFF1F_FFFF
128KB
MSS_DCAN_MEM (CAN) RAM memory
space
Reserved
0xFF50_0000
0xFF9F_FFFF
MSS_DEBUGSS
0xFFA0_0000
0xFFAF_FFFF
244KiB
MSS_DEBUGSS (Debug subsystem)
memory space and registers
MSS_PCR
0xFFF7_8000
0xFFF7_87FF
1KiB
MSS_PCR (PCR_1) interconnect
configuration port
Reserved
0xFFF7 A000
0xFFF7_BBFF
MSS_GIO
0xFFF7_BC00
0xFFF7_BDFF
Reserved
0xFFF7 C800
0xFFF7_D3FF
MSS_I2C
0xFFF7_D400
0xFFF7_D4FF
112B
MSS_I2C (I2C) module configuration
registers
MSS_DCAN
0xFFF7_DC00
0xFFF7_DDFF
512B
MSS_DCAN (CAN) module configuration
registers
MSS_SCIA (UART)
0xFFF7_E500
0xFFF7_E5FF
148B
MSS_SCIA (SCIA/UART) module
configuration registers
MSS_SCIB (UART)
0xFFF7_E700
0xFFF7_E7FF
148B
MSS_SCIB (SCIB/UART) module
configuration registers
MSS_MIBSPIA
0xFFF7_F400
0xFFF7_F5FF
512B
MSS_MIBSPIA (MIBSPIA) module
configuration registers
MSS_SPIB
0xFFF7_F600
0xFFF7_F7FF
512B
MSS_SPIB (SPIB) module configuration
registers
MSS_DMA_RAM
0xFFF8_0000
0xFFF8_0FFF
4KB
MSS_DMA_RAM (DMA1) RAM memory
space
MSS_VIM_MEM
0xFFF8_2000
0xFFF8_2FFF
2KB
MSS_VIM_MEM (VIM) RAM memory
space
Reserved
0xFFF8 C000
0xFFFF_E0FF
MSS_TOPRCM
0xFFFF_E100
0xFFFF_E2FF
756B
MSS_TOPRCM TOP Level Reset, Clock
management registers
MSS_PBIST
0xFFFF_E400
0xFFFF_E5FF
464B
MSS_PBIST (PBIST) module configuration
registers (refer to Safety chapter)
MSS_STC
0xFFFF_E600
0xFFFF_E7FF
284B
MSS_STC (STC) module configuration
registers (refer to Safety chapter)
MSS_IOMUX
0xFFFF_EA00
0xFFFF_EBFF
512KiB
MSS_IOMUX (IOMUX) module registers
MSS_DCCA
0xFFFF_EC00
0xFFFF_ECFF
44B
MSS_DCCA (DCCA) module configuration
registers (refer to Safety chapter)
138 14xx
Reserved
Reserved
Reserved
180B
MSS_GIO (GIO) module configuration
registers
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Memory Map
www.ti.com
Table 1-2. Master Subsystem, Cortex-R4F Memory Map (continued)
Module Name
Frame Address (Hex)
Start
1.2.2.1
Size Used
Description
End
MSS_RTIB (WDT/RTIB) 0xFFFF_EE00
0xFFFF_EEFF
192B
MSS_RTIB (WDT/RTIB) module register
space
MSS_DMA_REG
0xFFFF_F000
0xFFFF_F3FF
1KiB
MSS_DMA_REG (DMA1) module
configuration registers
MSS_DCCB
0xFFFF_F400
0xFFFF_F4FF
44B
MSS_DCCB (DCCB) module configuration
registers (refer to Safety chapter)
MSS_ESM
0xFFFF_F500
0xFFFF_F5FF
156B
MSS_ESM (ESM) module configuration
registers (refer to Safety chapter)
Reserved
0xFFFF_F600
0xFFFF_F7FF
MSS_GPCFG_REG
0xFFFF_F800
0xFFFF_FBFF
352B
MSS_GPCFG_REG (GPCFG) General
purpose control registers
MSS_RTIA
0xFFFF_FC00
0xFFFF_FCFF
192B
MSS_RTIA (RTIA) module
MSS_VIM
0xFFFF_FD00
0xFFFF_FEFF
512B
MSS_VIM (VIM) module configuration
registers
MSS_RCM
0xFFFF_FF00
0xFFFF_FFFF
256B
MSS_RCM (RCM) Reset, Clock
management registers
Reserved
Radar Subsystem Interface
The RADAR subsystem is accessible through a set of TI-implemented high-level API calls by the
application running on the master CR4F.
1.2.3 EDMA Memory Map
Table 1-3. EDMA-TPTC Memory Map
Module Name
Frame Address (Hex)
Size Used
Description
0x201F_FFFF
2MB
DSS_L3RAM (L3) shared memory space
0x2100_7FFC
32KiB
DSS_ADCBUF (ADC) memory space
0x2102_0000
0x2102_3FFC
16KiB
DSS_CBUFF_FIFO (CBUFF) memory
space
DSS_FFT_ACC_DMA1
0x2103 0000
0x2103_7FFF
32KiB
DSS_FFT_ACC_DMA1 (HWA DMA) FFT
accelerator memory-1 space
DSS_FFT_ACC_DMA2
0x2103 8000
0x401F_FFFF
32KiB
DSS_FFT_ACC_DMA2 (HWA DMA) FFT
accelerator memory-2 space
MSS_TCMA_RAM
0x4020_0000
0x4023_FFFF
256KiB
MSS_TCMA_RAM (TCMA) Data RAM
MSS_TCMB
0x4800_0000
0x4802_FFFF
192KiB
MSS_TCMB (TCMB) Data RAM
MSS_SW_BUFFER
0x4C20_0000
0x4C20_1FFF
8KiB
MSS_SW_BUFFER (SWBUFF)
Scratchpad memory
GEM_MBOX4MSS
0x5060_4000
0x5060_4000
2KiB
GEM_MBOX4MSS mailbox memory
space
MSS_MBOX4GEM
0x5060_5000
0x5060_5000
2KiB
MSS_MBOX4GEM mailbox memory
space
GEM_MBOX4BSS
0x5060_6000
0x5060_6000
2KiB
GEM_MBOX4BSS mailbox memory
space
BSS_MBOX4GEM
0x5060_7000
0x5060_7000
2KiB
BSS_MBOX4GEM mailbox memory
space
Start
End
DSS_L3RAM
0x2000_0000
DSS_ADCBUF
0x2100_0000
DSS_CBUFF_FIFO
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
139
14xx Integration
1.3
www.ti.com
14xx Integration
1.3.1 Cortex-R4F Subsystem
1.3.1.1
Tightly Coupled Memories
The total memory (RAM) available in the master subsystem is 576 KB. This is partitioned between the
R4F program RAM, R4F data RAM, and radar data memory. The maximum usable size for R4F is 448
KB, and this is partitioned between the R4F’s tightly coupled interfaces MSS_TCMA_RAM (320 KB) and
MSS_TCMB (128 KB). Although the complete 448 KB is unified memory and can be used for program or
data, typical applications use MSS_TCMA_RAM as program and MSS_TCMB as data memory.
The remaining memory, starting at a minimum of 128 KB, is available as radar data memory for storing
the ‘radar data cube’. The user can increase the radar data memory size in 64 KB increments, at the cost
of corresponding reduction in R4F program or data RAM size. The maximum size of radar data memory
possible is 384 KB. A few example configurations supported are listed in Table 1-4.
Table 1-4. Example Configurations
140
14xx
Option
R4F Program RAM (KB)
R4F Data RAM (KB)
Radar Data Memory (KB)
1
320
128
128
2
256
128
192
3
256
64
256
4
128
64
384
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
1.3.2 Clock Comparator
1.3.2.1
Core Clock Comparator (MSS_CCCA/MSS_CCCB)
Figure 1-3. Integration of MSS_CCCA and MSS_CCCB Modules
mss_vclk
async_rst_n
clock0_src[7:0]
clock1_src[7:0]
clock0_sel[7:0]
clock1_sel[7:0]
count0_expiry_val
MSS_GPCFG
counter_error
counter_done
To MSS_ESM Module
To MSS_VIM Module
MSS_CCCA
(CCCA)
count1_expected_val
disable_clk_output
enable_module
margin_count
count1_val_out
MSS_GPCFG
errstat
singleshot_mode
timeout_err_count
mss_vclk
async_rst_n
clock0_src[7:0]
clock1_src[7:0]
clock0_sel[7:0]
clock1_sel[7:0]
count0_expiry_val
MSS_GPCFG
counter_error
counter_done
To MSS_ESM Module
To MSS_VIM Module
MSS_CCCB
(CCCB)
count1_expected_val
disable_clk_output
count1_val_out
enable_module
margin_count
errstat
MSS_GPCFG
singleshot_mode
timeout_err_count
1.3.2.1.1 MSS_CCCA and MSS_CCCB Integration Connections
This device has two instances of CCC; MSS_CCCA (CCCA) and MSS_CCCB (CCCB). The clock
connectivity information for these two instances are provided in Table 1-5. Configuration and status of this
module is available through the MSS_GPCFG registers of the device.
Table 1-5. MSS_CCCA and MSS_CCCB Integration Connections
MSS_CCCA (CCCA)
MSS_CCCB (CCCB)
counter_error
ESM_GRP1[1]
ESM_GRP1[4]
counter_done
IRQ[80]
IRQ[81]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx 141
14xx Integration
www.ti.com
Table 1-5. MSS_CCCA and MSS_CCCB Integration Connections (continued)
MSS_CCCA (CCCA)
MSS_CCCB (CCCB)
clock0_src[0]
REFCLK
CR4_VCLK
clock0_src[1]
CPUCLK
Reserved
clock0_src[2]
RCCLK
BSSCLK
clock0_src[3]
RCCLK
QSPICLK
clock0_src[4]
RCCLK
Reserved
clock0_src[5]
RCCLK
REFCLK
clock0_src[6]
RCCLK
CPUCLK
clock0_src[7]
RCCLK
RCCLK
clock1_src[0]
REFCLK
PLLCLK_600
clock1_src[1]
Reserved
MSS_VCLK
clock1_src[2]
PLL 240Mhz
CPUCLK
clock1_src[3]
RCCLK
CR4_VCLK
clock1_src[4]
RCCLK
MSS_VCLK
clock1_src[5]
RCCLK
Reserved
clock1_src[6]
RCCLK
BSSCLK
clock1_src[7]
RCCLK
QSPICLK
1.3.2.2
Dual Clock Comparator (MSS_DCCA/MSS_DCCB)
Figure 1-4. MSS_DCCA/MSS_DCCB Integration Diagram
MSS_DCC
Clock Source Selection
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
MSS_DCCA/
MSS_DCCB
(DCCA/DCCB)
dcc_done_int
To MSS_VIM Module
dcc_error
To MSS_ESM Module
Table 1-6. MSS_DCCA Clock Source Selection Table
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
0x0 - REF_CLK
0x0 - REF_CLK
0xA - PLL_600
0x1 - CPU_CLK
0x5 - PLL_240
0x2 to 0x7 - RC_CLK
Table 1-7. MSS_DCCB Clock Source Selection Table
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
0x0 - PLL_600
0x0 - VCLK
0xA - VCLK
0x1 - DSS_CLK
0x5 - CPU_CLK
0x2 - BSS_CLK
0x3 - QSPI_CLK
0x4 - Reserved
0x5 - CPU_CLK
0x6 - REF_CLK
0x7 - RC_CLK
142 14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
NOTE: Any values not mentioned are not used.
1.3.3 Direct Memory Access Controller (MSS_DMA)
1.3.3.1
MSS_DMA Integration Diagram
The device has one instance of DMA module, MSS_DMA. Integration of the MSS_DMA blocks in the
device are shown in Figure 1-5.
Figure 1-5. Integration of MSS_DMA Module
From MSS_RCM
MSS_DMA
Request Source
VCLK
dma1_ftcint
RSTn
dma1_lfsint
MMI_START
dma1_hbcint
MMI_DONE
dma1_btcint
dma1_req[47:0]
MSS_DMA
(DMA1)
To MSS_VIM Module
dma1_berint
dma1_uerr
dma1_mpv
To MSS_ESM Module
dma1_wrerr_int_pls
Configuration Port
VBUS PCR
From BUS Matrix
VBUS_PCR
dma1_portb_vbusm
Master Port on
BUS Matrix
1.3.3.2 MSS_DMA Features
• 64-bit OCP protocol to perform bus master accesses
• INCR-4 64-bit burst accesses
• Multithreading architecture allowing data of two different channel transfers to be interleaved during
non-burst accesses
• 2-port configuration for parallel bus master
• Channels can be assigned to either high-priority queue or low-priority queue. Within each queue, fixed
or round-robin priorities can be serviced
• Built-in ECC generation and evaluation logic for internal RAM-storing channel transfer information
• Supports multiple interrupt outputs for mapping to multiple interrupt controllers in multicore systems
• 48 requests can be mapped to any 32 channels
• Supports LE endianness
• External ECC Gen/Eval block of MSS_DMA support ECC generation for data transactions, and parity
for address, and control signals (following Cortex-R5F standard)
• 8 MPU regions
• Channel-chaining capability
• Hardware and software MSS_DMA requests
• 8-, 16-, 32-, or 64-bit transactions supported
• Multiple addressing modes for source and destination (fixed, increment, offset)
• Auto-initiation
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
143
14xx Integration
1.3.3.3
www.ti.com
MSS_DMA Request Map
The MSS_DMA module has 32 channels and up to 42 hardware MSS_DMA requests. The module
contains DREQASIx registers to map the MSS_DMA requests to the MSS_DMA channels. By default,
channel 0 is mapped to request 0, channel 1 to request 1, and so forth.
Table 1-8. MSS_DMA Request Map
Module
DMA Request Sources
DMA Request
MSS_MIBSPIA
MSS_MIBSPIA Channel-1
DMAREQ[0]
MSS_MIBSPIA
MSS_MIBSPIA Channel-0
DMAREQ[1]
MSS_SPIB
MSS_SPIB Receive
DMAREQ[2]
MSS_SPIB
MSS_SPIB Transmit
DMAREQ[3]
MSS_QSPI
MSS_QSPI DMA request
DMAREQ[4]
MSS_MIBSPIA
MSS_MIBSPIA Channel-3
DMAREQ[5]
MSS_DCAN
MSS_DCAN IF2
DMAREQ[6]
DSS_CBUFF
DSS_CBUFF
DMAREQ[7]
MSS_DCAN
MSS_DCAN IF1
DMAREQ[8]
MSS_MIBSPIA
MSS_MIBSPIA Channel-5
DMAREQ[9]
MSS_I2C
MSS_I2C receive
DMAREQ[10]
MSS_I2C
MSS_I2C Transmit
DMAREQ[11]
MSS_RTIA
MSS_RTIA DMAREQ0
DMAREQ[12]
MSS_RTIA
MSS_RTIA DMAREQ1
DMAREQ[13]
Reserved
Reserved
DMAREQ[14]
Reserved
Reserved
DMAREQ[15]
MSS_DCAN
MSS_DCAN IF3
DMAREQ[16]
MSS_MIBSPIA
MSS_MIBSPIA Channel-9
DMAREQ[17]
MSS_RTIA
MSS_RTIA DMAREQ2
DMAREQ[18]
MSS_RTIA
MSS_RTIA DMAREQ3
DMAREQ[19]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ0
DMAREQ[20]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ1
DMAREQ[21]
MSS_MIBSPIA
MSS_MIBSPIA Channel-10
DMAREQ[22]
MSS_MIBSPIA
MSS_MIBSPIA Channel-11
DMAREQ[23]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ2
DMAREQ[24]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ3
DMAREQ[25]
MSS_MCRC
MSS_MCRC DMAREQ0
DMAREQ[26]
MSS_MCRC
MSS_MCRC DMAREQ1
DMAREQ[27]
MSS_SCIB (UART2)
MSS_SCIB (UART2) receive
DMAREQ[28]
MSS_SCIB (UART2)
MSS_SCIB (UART2) Transmit
DMAREQ[29]
MSS_SCI1 (UART1)
MSS_SCI1 (UART1) receive
DMAREQ[30]
MSS_SCI1 (UART1)
MSS_SCI1 (UART1) Transmit
DMAREQ[31]
MSS_GIO
MSS_GIO-0
DMAREQ[32]
MSS_GIO
MSS_GIO-1
DMAREQ[33]
MSS_GIO
MSS_GIO-2
DMAREQ[34]
Reserved
Reserved
DMAREQ[35]
MSS_MIBSPIA
MSS_MIBSPIA Channel-6
DMAREQ[36]
MSS_MIBSPIA
MSS_MIBSPIA Channel-7
DMAREQ[37]
MSS_MIBSPIA
MSS_MIBSPIA Channel-8
DMAREQ[38]
Reserved
Reserved
DMAREQ[39]
Reserved
Reserved
DMAREQ[40]
Reserved
Reserved
DMAREQ[41]
MSS_MIBSPIA
MSS_MIBSPIA Channel-12
DMAREQ[42]
144 14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
Table 1-8. MSS_DMA Request Map (continued)
Module
DMA Request Sources
DMA Request
MSS_MIBSPIA
MSS_MIBSPIA Channel-13
DMAREQ[43]
MSS_MIBSPIA
MSS_MIBSPIA Channel-14
DMAREQ[44]
MSS_MIBSPIA
MSS_MIBSPIA Channel-15
DMAREQ[45]
MSS_GIO
MSS_GIO-14
DMAREQ[46]
MSS_GIO
MSS_GIO-15
DMAREQ[47]
1.3.4 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB)
Figure 1-6. Integration of MSS_RTIA and MSS_RTIB, Using the RTI Module
From
MSS_RCM
rti_ovfl_req[1:0]
rti_cmp_int_req[3:0]
rti_tb_int_req
Vim_cap_evt[1:0]
rti_vclk
rti_sync
NTU[3:0]
Not used
RTI_PIN
MSS_RTIA
(RTIA)
rti_dma_req[3:0]
VBUS_PCR
wdt_rstn
Not used
NTU[3:0]
MSS_RTIB
(WDT/RTIB)
RTI_PIN
MSS_RTI Register Configuration
Port from Bus Matrix
wdt_nmi_req
To MSS_VIM
wdt_dma_req[3:0]
VBUS_PCR
To MSS_ESM
To MSS_DMA
wdt_ovl_req[1:0]
wdt_int_req[3:0]
wdt_tb_int_req
Vim_cap_evt[1:0]
wdt_vclk
wdt_sync
To/From
MSS_RCM
To/From MSS_VIM
To MSS_DMA
MSS_WDT RegisterConfiguration
Port from Bus Matrix
1.3.5 General Purpose I/0 (MSS_GIO)
NOTE: Emulation mode and power-down mode (low-power mode) are not supported in the 14xx
device.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
145
14xx Integration
www.ti.com
Figure 1-7. Integration Block Diagram for MSS_GIO
From
MSS_RCM
gio_vclk
gio_rstn
MSS_GIO
(GIO)
gio_pc
GIOA[7:0]
GIOB[7:0]
GIOC[7:0]
GIOD[6:0]
Device PCR Bus
To MSS_VIM
GIO_low_level_interrupt
GIO_high_level_interrupt
To MSS_DMA
GPIO_0_host_DMA
GPIO_1_host_DMA
GPIO_2_host_DMA Positive Edge to Pulse
GPIO_14_host_DMA
GPIO_15_host_DMA
To/from device pins
GPIO_0: GPIO_30
GPIO_0
GPIO_1
GPIO_2
GPIO_14
GPIO_15
From device pins
GPIO_0, GPIO_1, GPIO_2,
GPIO_14, GPIO_15
1.3.6 Vectored Interrupt Manager (MSS_VIM)
1.3.6.1
Interrupt Request Assignments
Table 1-9. Interrupt Request Assignments
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
MSS_ESM
MSS_ESM high-level interrupt(NMI)
0
Reserved
Reserved
1
MSS_RTIA
MSS_RTIA compare interrupt 0
2
MSS_RTIA
MSS_RTIA compare interrupt 1
3
MSS_RTIA
MSS_RTIA compare interrupt 2
4
MSS_RTIA
MSS_RTIA compare interrupt 3
5
MSS_RTIA
MSS_RTIA overflow interrupt 0
6
MSS_RTIA
MSS_RTIA overflow interrupt 1
7
MSS_RTIA
MSS_RTIA time-base
8
MSS_GIO
MSS_GIO high-level interrupt
9
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 0
10
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt1
11
MSS_MIBSPIA
MSS_MIBSPIA level 0 Interrupt
12
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) Interrupt 2
13
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) Interrupt 3
14
146 14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
Table 1-9. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) overflow interrupt 15
0
MSS_DCAN
MSS_DCAN level 0 interrupt
16
MSS_SPIB
MSS_SPIB level 0 Interrupt
17
Reserved
Reserved
18
MSS_MCRC
MSS_MCRC interrupt
19
MSS_ESM
MSS_ESM low-level interrupt
20
SYSTEM
Software-triggered interrupt 4
21
MSS Cortex R4F
MSS Cortex R4F interrupt PMU
22
MSS_GIO
MSS_GIO low-level interrupt
23
MSS_RTIB (WDT/RTIB)
WDT overflow interrupt 1
24
MSS_RTIB (WDT/RTIB)
WDT TB base interrupt
25
MSS_MIBSPIA
MSS_MIBSPIA level 0 interrupt
26
MSS_QSPI
MSS_QSPI interrupt
27
Reserved
Reserved
28
MSS_DCAN
MSS_DCAN level 1 interrupt
29
MSS_SPIB
MSS_SPIB level 1 interrupt
30
Reserved
Reserved
31
Reserved
Reserved
32
MSS_DMA
MSS_DMA frame transfer complete
interrupt
33
MSS_DMA
MSS_DMA last frame transfer start
interrupt
34
Reserved
Reserved
35
Reserved
Reserved
36
Reserved
Reserved
37
Reserved
Reserved
38
MSS_DMA
MSS_DMA half-block transfer complete
interrupt
39
MSS_DMA
MSS_DMA block transfer complete
interrupt
40
Reserved
Reserved
41
Reserved
Reserved
42
Reserved
Reserved
43
Reserved
Reserved
44
Reserved
Reserved
45
Reserved
Reserved
46
Reserved
Reserved
47
Reserved
Reserved
48
Reserved
Reserved
49
Reserved
Reserved
50
Reserved
Reserved
51
Reserved
Reserved
52
Reserved
Reserved
53
Reserved
Reserved
54
Reserved
Reserved
55
Reserved
Reserved
56
Reserved
Reserved
57
Reserved
Reserved
58
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Default VIM Interrupt Channel
14xx 147
14xx Integration
www.ti.com
Table 1-9. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
Reserved
Reserved
59
Reserved
Reserved
60
Reserved
Reserved
61
Reserved
Reserved
62
Reserved
Reserved
63
MSS_SCIA (UART1)
MSS_SCIA (UART1) level 0 interrupt
64
MSS_SCIB (UART2)
MSS_SCIB (UART2) level 0 interrupt
65
MSS_I2C
MSS_I2C interrupt
66
Reserved
Reserved
67
Reserved
Reserved
68
Reserved
Reserved
69
MSS_DMA
MSS_DMA bus error interrupt
70
Reserved
Reserved
71
Reserved
Reserved
72
Reserved
Reserved
73
MSS_SCIA (UART1)
MSS_SCIA (UART1) level 1 interrupt
74
MSS_SCIB (UART2)
MSS_SCIB (UART2) level 1 interrupt
75
SYSTEM
Software-triggered interrupt 0
76
SYSTEM
Software-triggered interrupt 1
77
SYSTEM
Software-triggered interrupt 2
78
SYSTEM
Software-triggered interrupt 3
79
Reserved
Reserved
80
Reserved
Reserved
81
MSS_DCCA
MSS_DCCA (dual clock compare) module 82
1-done interrupt
MSS_DCCB
MSS_DCCB (dual clock compare) module 83
2-done interrupt
SYSTEM
Software-triggered interrupt 5
84
MSS_PBIST
MSS_PBIST done interrupt
85
Reserved
Reserved
86
Reserved
Reserved
87
Reserved
Reserved
88
Reserved
Reserved
89
Reserved
Reserved
90
Reserved
Reserved
91
Reserved
Reserved
92
Reserved
Reserved
93
Reserved
Reserved
94
MAILBOX
RADARSS to MSS mailbox interrupt
95
MAILBOX
RADARSS mailbox read complete
interrupt sent from RADARASS to MSS
96
RADARSS
ADC valid fall interrupt
97
RADARSS
Frame start interrupt
98
RADARSS
Chirp start interrupt
99
RADARSS
Chirp end interrupt
100
RADARSS
Frame end interrupt
101
Reserved
Reserved
102
Reserved
Reserved
103
148 14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
Table 1-9. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
Reserved
Reserved
104
BSS_CR4_STC
BSS_CR4_STC interrupt
105
Reserved
Reserved
106
Reserved
Reserved
107
Reserved
Reserved
108
Reserved
Reserved
109
Reserved
Reserved
110
Reserved
Reserved
111
DSS_TPTC0 (EDMA TPTC0)
DSS_TPTC0 (EDMA TPTC0) interrupt
112
DSS_TPTC0 (EDMA TPTC0)
DSS_TPTC0 (EDMA TPTC0) error
interrupt
113
DSS_TPTC1 (EDMA TPTC1)
DSS_TPTC1 (EDMA TPTC1) interrupt
114
DSS_TPTC1 (EDMA TPTC1)
DSS_TPTC1 (EDMA TPTC1) error
interrupt
115
DSS_TPCC (EDMA TPCC0)
DSS_TPCC (EDMA TPCC0) interrupt
116
DSS_TPCC (EDMA TPCC0)
DSS_TPCC (EDMA TPCC0) error
interrupt
117
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) interrupt
118
DSS_ADCBUF
Falling edge of ADC valid interrupt
119
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) error
interrupt
120
Reserved
Reserved
121
Reserved
Reserved
122
DSS_ADCBUF
Chirp available interrupt
123
Reserved
Reserved
124
DSS_HW_ACC
DSS_HW_ACC FFT accelerator -param
done interrupt
125
DSS_HW_ACC
DSS_HW_ACC FFT accelerator - done
interrupt
126
DSS_HW_ACC
DSS_HW_ACC FFT accelerator –access
error interrupt
127
1.3.7 Controller Area Network (MSS_DCAN)
Figure 1-8. Integration Block Diagram for MSS_DCAN Module
From MSS_RCM
Vbusp_clk
Vbusp_rstn
dcan_clk
dcan_mmistart
dcan_mmidone
dcan_dma_req[2:0]
MSS_DCAN
(CAN)
Configuration Port VBUS_PCR
VBUS PCR
From BUS Matrix
To MSS_VIM
dcan_lvl_int[1:0]
dma_uerr
dma_serr
dcan_tx
dcan_rx
dcan_rx_oe_n
dcan_tx_oe_n
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
To MSS_DMA
To MSS_ESM
To/from device pins
14xx
149
14xx Integration
www.ti.com
1.3.8 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPIA)
Figure 1-9. MSS_MIBSPIA Integration
spia_cs_n_in[3:0]
spia_clk_in
spia_mosi_in
spia_miso_in
spia_nrst
spia_vclk
spia_mem_init
spia_mem_init_done
spia_trig_src[1:0]
From
MSS_RCM
spia_cs_n_ie[3:0]
spia_clk_ie
spia_mosi_ie
spia_miso_ie
spia_1sync_to_2sync_en
To MSS_VIM
To MSS_DMA
To MSS_ESM
Config
Port From
Bus-matrix
Register Control
from MSS_RCM
Configuration space
spia_int_req[1:0]
MSS_MIBSPIA
(MIBSPIA)
spia_dma_req[13:0]
spia_sberror
spia_uerror
spia_cs_n_out[3:0]
spia_clk_out
spia_mosi_out
spia_miso_out
To/from device pins
spia_cs_n_oe_n [3:0]
spia_clk_oe_n
spia_mosi_oe_n
spia_miso_oe_n
spia_pcr
1.3.9 Serial Peripheral Interface (MSS_SPIB)
MSS_SPIB module of the 14xx is equivalent in behavior and functionality to MSS_MIBSPIA module
configured in compatibility mode for SPI. Users cannot change the compatibility mode configuration of this
MSS_SPIB instance.
150
14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
Figure 1-10. MSS_SPIB Integration Diagram
spib_nrst
spib_vclk
spib_mem_init
spib_mem_init_done
spib_trig_src[5:0]
From
MSS_RCM
spib_cs_n_in[3:0]
spib_clk_in
spib_mosi_in
spib_miso_in
Register Control
from MSS_RCM
Configuration space
spib_1sync_to_2sync_en
To MSS_VIM
spib_int_req[1:0]
MSS_SPIB
(SPIB)
To MSS_DMA spib_dma_req[1:0]
To MSS_ESM
spib_sberror
spib_uerror
Config
Port From
Bus-matrix
spib_cs_n_ie[3:0]
spib_clk_ie
spib_mosi_ie
spib_miso_ie
spib_cs_n_out[3:0]
spib_clk_out
spib_mosi_out
spib_miso_out
To/from device pins
spib_cs_n_oe_n[3:0]
spib_clk_oe_n
spib_mosi_oe_n
spib_miso_oe_n
spib_pcr
1.3.10 Quad Serial Peripheral Interface (MSS_QSPI)
The QSPI module of the 14xx only supports one CS pin (qspi1_cs).
1.3.11 Enhanced Direct Memory Access (EDMA)
1.3.11.1 EDMA Controller Integration
The 14xx device has one EDMA channel controller (DSS_TPCC0) on the device:
• DSS_TPCC0 (EDMA TPCC0) has two transfer controllers: DSS_TPTC0 (EDMA TPTC0) and
DSS_TPTC1 (EDMA TPTC1)
Table 1-10. DSS_TPCC Configuration
DSS_TPCC0
Number of DMA channels
64
Number of PaRAM entires
128
Number of QDMA channels
8
Number of event queues
2
Memory protection existence
No
Channel mapping
No
Number of TCs (transfer controllers)
2
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
151
14xx Integration
www.ti.com
Table 1-11. DSS_TPTC Configuration
DSS_TPTC[0-1]
FIFO size
512 bytes
TR pipe depth
2
Bus width
16 bytes
This section describes the integration of the module in the device, including information about clocks,
resets, and hardware requests.
Figure 3-13 and Figure 3-14 show the EDMA controller integration.
Figure 1-11. EDMA Controller Integration
Peripherals
Enhanced DMA
Controller
DSS_TPTC1
Master Read
EDMA_TPCC_IRQ_ERR
To C674x-INTC
and
Master CR4F
TPCC_IRQ_Completion
Master Write
PCR 32 bit
CFG_Slave
128 bit
128 bit
Completion
Port
TPTC_GCLK
TPTC_RST
PCR 32bit
SCR 128bit
Transfer request
CFG_Slave
Device
modules
DSS_TPTC0
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Completion
Master Read
128 bit
Master Write
Completion
Port
TPTC_GCLK
TPTC_RST
128 bit
Transfer request
CFG_Slave
DSS_TPCC0
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Global_Completion
DMA requests
from Different
sources
EDMA_REQ[63:0]
DSPSS_CLK
PRCM
152
14xx
DSS_TPTC0
Transfer request
DSS_TPTC1
Master Interface
Reset_n
TPTC_GCLK
TPTC_RST
Completion
Port[6:0]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
1.3.11.2 EDMA Request Map
Table 1-12. EDMA Request Map
DSS_TPCC0 DMA Req No.
Hardware Event (14XX)
0
DSS_CBUFF_DMA_REQ_0
1
DSS_CBUFF_DMA_REQ_1
2
DSS_CBUFF_DMA_REQ_2
3
DSS_CBUFF_DMA_REQ_3
4
DSS_CBUFF_DMA_REQ_4
5
DSS_CBUFF_DMA_REQ_5
6
DSS_CBUFF_DMA_REQ_6
7
RESERVED
8
Frame Start
9
Chirp Available
10
CSI-2 DMA Req 0
11
CSI-2 DMA Req 1
12
CSI-2 DMA Req 2
13
CSI-2 DMA Req 3
14
VIN_FRAME_START
15
VIN_CHIRP_AVIALABLE
16
VIN_CHANNEL_AVAILABLE
17
DSS_FFT_ACC_CHANNEL_TRIGGER_0
18
DSS_FFT_ACC_CHANNEL_TRIGGER_1
19
DSS_FFT_ACC_CHANNEL_TRIGGER_2
20
DSS_FFT_ACC_CHANNEL_TRIGGER_3
21
DSS_FFT_ACC_CHANNEL_TRIGGER_4
22
DSS_FFT_ACC_CHANNEL_TRIGGER_5
23
DSS_FFT_ACC_CHANNEL_TRIGGER_6
24
DSS_FFT_ACC_CHANNEL_TRIGGER_7
25
DSS_FFT_ACC_CHANNEL_TRIGGER_8
26
DSS_FFT_ACC_CHANNEL_TRIGGER_9
27
DSS_FFT_ACC_CHANNEL_TRIGGER_10
28
DSS_FFT_ACC_CHANNEL_TRIGGER_11
29
DSS_FFT_ACC_CHANNEL_TRIGGER_12
30
DSS_FFT_ACC_CHANNEL_TRIGGER_13
31
DSS_FFT_ACC_CHANNEL_TRIGGER_14
32
DSS_FFT_ACC_CHANNEL_TRIGGER_15
33
RESERVED
34
RESERVED
35
FRC_EVENT_GEN_0
36
FRC_EVENT_GEN_1
37
FRC_EVENT_GEN_2
38
FRC_EVENT_GEN_3
39
RESERVED
40
LOGICAL_FRAME_START
41
ADC_DATA_VALID_FALL
42
RESERVED
43
RESERVED
44
RESERVED
45
RESERVED
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx 153
14xx Integration
www.ti.com
Table 1-12. EDMA Request Map (continued)
DSS_TPCC0 DMA Req No.
Hardware Event (14XX)
46
RESERVED
47
RESERVED
48
RESERVED
49
RESERVED
50
RESERVED
51
RESERVED
52
RESERVED
53
RESERVED
54
RESERVED
55
RESERVED
56
RESERVED
57
RESERVED
58
RESERVED
59
RESERVED
60
RESERVED
61
RESERVED
62
RESERVED
63
RESERVED
1.3.12 Error Signaling Module (MSS_ESM)
The 14xx device has one instance of the Error Signaling Module (MSS_ESM), shown in Figure 1-12.
Figure 1-12. 14xx MSS_ESM Integration Diagram
Table 1-13 shows the mapping on the input error inputs to the ESM module from various error sources
available for hardware diagnostics within the device.
Table 1-13. MSS_ESM Mapping
ESM Group 1
Channel Type
Description
63
ANA_LIMP_MODE
Error Signal
Error signal at device boot-up, if the CLK monitor finds the
REF CLK to be outside the permissible range of frequency
62
MSS_DCCB_ERR
Error Signal
MSS_DCCB frequency comparison error
61
BSS2MSS_MB_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_BSS2MSS
154 14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
Table 1-13. MSS_ESM Mapping (continued)
ESM Group 1
Channel Type
Description
60
BSS2MSS_MB_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_BSS2MSS
59
MSS2BSS_MB_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_MSS2BSS
58
MSS2BSS_MB_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_MSS2BSS
57
BSS_CRITICAL_ERR
Error Signal
BSS critical Error Indication.
Mask control to be configured in IRQ_CTL for individual
error signals.
56
Reserved
Reserved
Reserved
55
CLOCK_SUPPLY_ERR
Error Signal
Clock and Supply Errors from Analog.
Mask control to be configured in IRQ_CTL for individual
error signals
54
Reserved
53
NU
52
NU
51
NU
50
NU
49
NU
48
MSS_MCRC_ERR
47
NU
46
NU
45
NU
44
Reserved
43
NU
42
NU
41
NU
40
Reserved
Error Signal
MSS_MCRC Comparison Error
Reserved
Reserved
Reserved
Reserved
Reserved
39
Reserved
Reserved
38
DSS_CBUFF_SAFETY
Error Signal
CHIRP ERROR or CRC ERROR from DSS_CBUFF
37
NU
36
DSS_TPTC1_WR_MPU_ERR
Error Signal
DSS_TPTC1 write port MPU error
35
DSS_TPTC1_RD_MPU_ERR
Error Signal
DSS_TPTC1 read port MPU error
34
HVMODE_ERR
Error Signal
Error indication from IO Supply (Supply detector for dualvoltage IOs)
33
MSS_DCAN_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_DCAN Message
RAM (FRAM/SRAM)
32
MSS_TCMA_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for Cortex R4F MSS_TCMA
31
Reserved
Reserved
Reserved
30
MSS_DCCA_ERR
Error Signal
MSS_DCCA frequency comparison error
29
DSS_TPTC0_WR_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
28
MSS_TCMB1_REPAIR_ERR
Alert Signal
Single-bit error/reserved indication for MSS_TCMB1
27
MSS_STC_ERR
Error Signal
MSS_STC Error indication for MSS Cortex R4F
26
MSS_TCMB0_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_TCMB0
25
MSS_MIBSPIA_MEM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_MIBSPIA multibuffer (RXRAM/TXRAM)
24
NU
23
NU
22
FRC_COMPARE_ERR
Error Signal
Lockstep comparison error from Free running Counter (FRC)
in BSS
21
MSS_DCAN_RAM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_DCAN Message Memory
(FRAM/SRAM)
20
MSS_VIM_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_VIM_RAM
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx 155
14xx Integration
www.ti.com
Table 1-13. MSS_ESM Mapping (continued)
ESM Group 1
Channel Type
Description
DSS_TPTC0_RD_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
MSS_MIBSPIA_MEM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_MIBSPIA
(RXRAM/TXRAM)
Error Signal
Multi-bit uncorrectable error indication for MSS_VIM_RAM
DSS_CBUFF_ECC_FATAL
Error Signal
Multi-bit error indication from DSS_CBUFF FIFO
DSS_CBUFF_ECC_REPAIR
Alert Signal
Single-bit repair indication from DSS_CBUFF FIFO
7
DSS_TPCC_PARITY_ERR
Error Signal
Parity error from DSS_TPCC (EDMA Channel Controller)
6
DSS_CSI_PARITY_ERR
Error Signal
Parity error from DSS_SI
5
NU
4
MSS_CCCB_ERR
Error Signal
MSS_CCCB(Clock compare core) frequency comparison
error
3
MSS_DMA_MEM_PARITY_ERR
Error Signal
Parity Error for DMA1 memory
2
MSS_DMA_MPU_ERR
Error Signal
Error indication from MPU of MSS _DMA
1
MSS_CCCA_ERR
Error Signal
MSS_CCCA(Clock compare core) frequency comparison
error
0
NERROR_PAD_IN
Error Signal
Nerror from PAD looped in
19
Reserved
18
17
16
NU
15
MSS_VIM_RAM_FATAL_ERR
14
NU
13
Reserved
12
NU
11
NU
10
NU
9
8
ESM Group 2
31:26
NU
25
Reserved
Reserved
Reserved
24
MSS_RTIB_NMI
Error Signal
Watchdog Non-mask able interrupt
23:17
NU
16
MSS_CR4F_LIVELOCK_ERR
Error Signal
Cortex R4F Live lock error
15:9
NU
8
MSS_TCMB1_PARITY_ERR
Error Signal
Parity Error on Control signals for MSS_TCMB1
7
NU
6
MSS_TCMB0_PARITY_ERR
Error Signal
Parity Error on Control signals for MSS_TCMB0
5
NU
4
MSS_TCMA_PARITY_ERR
Error Signal
Parity Error on Control signals for MSS_TCMA
3
NU
2
Reserved
Reserved
Reserved
1:0
NU
Error Signal
Multi-bit error indication for MSS_TCMA
Error Signal
Multi -bit error indication for MSS_TCMB1
Error Signal
Multi-bit error indication for MSS_TCMB0
Error Signal
Efuse Auto-load error
ESM Group 3
156
31-8
NU
7
MSS_TCMA_FATAL_ERR
6
NU
5
MSS_TCMB1_FATAL_ERR
4
NU
3
MSS_TCMB0_FATAL_ERR
2
NU
1
EFC_AUTOLOAD_ERR
0
NU
14xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx Integration
www.ti.com
1.3.13 High-Speed Interface (HSI)
Table 1-14 lists the high-speed interfaces available for the 14xx device.
Table 1-14. 14xx High-Speed Interfaces
CSI2
4 lanes
LVDS
4 lanes
1.3.14 Handshake RAM (HSRAM)
On the 14xx, there is no HSRAM available.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
14xx
157
Chapter 2
SWRU522D – May 2017 – Revised September 2019
16xx/18xx
Topic
...........................................................................................................................
2.1
2.2
2.3
2.4
2.5
2.6
158
16xx/18xx
16xx
16xx
16xx
18xx
18xx
18xx
Introduction..............................................................................................
Memory Map.............................................................................................
Integration................................................................................................
Introduction..............................................................................................
Memory Map.............................................................................................
Integration................................................................................................
Page
159
163
170
200
204
212
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Introduction
www.ti.com
2.1
16xx Introduction
2.1.1 16xx Overview
The 16xx is highly integrated single-chip RADAR device in TI’s 45-nm low-power RFCMOS technology, a
FCBGA 0.65-mm pitch automotive-grade package.
2.1.1.1 Features
• Frequency-Modulated Continuous Wave Radio Frequency Transceiver With 76-81-GHz Band
• Supports Two Transmitter Chains and Four Receiver Chains
• Chirp Profiles With Programmable Period and Slope
• 40-MHz, 50-MHz, 80-MHz, and 100-MHz XTAL/OSC Reference Input Clock
• 12, 14, and 16-bit Real/Complex ADC With Variable Baseband ADC Sampling Rates up to 18.75 MHz
at 12-bits Complex
• Cortex R4F at 200-MHz Application Processor for Control Functionality and Safety-Critical Algorithms
• C674x DSP at up to 600 MHz for RADAR Data Processing
• Cortex R4F– Radio Processor at 200 MHz for Continuous Monitoring and Calibration of Analog/RF
Functionality
• On-Chip Multicore Debug Support
• Customer-Programmable Efuse Support
• Up to 768KB of L3 Shared Memory Support
• High-Performance Data Transfer With Multiple DMA and EDMA-TPCC Engines
• CAN Support for ECU Interface
• QSPI Serial Flash Support
• MIBSPI, SPI, I2C, and UART Serial Interfaces Support
• Hardware in Loop (HIL) Support
• Two-Lane Serial LVDS Interface Support
• AES, SHA, PKA, and TRNG Engines for Security
• I2C Serial Interface Support
• 3 EPWM (Three Enhanced Pulse Width Modulator)
2.1.2 16xx Description
2.1.2.1
Block Diagram
Figure 2-17 shows the block diagram of the 16xx device.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
159
16xx Introduction
www.ti.com
Figure 2-1. 16xx Block Diagram
RADAR Subsystem
Radio Processor
FMCW Transceiver 76-81GHz
Two Transmitters,
Four Receivers
Baseband
ADC
GPADC
Ramp Generator
B
U
S
DFE
M
A
T
R
I
X
Voltage Monitor
OSC
PLL
DSP Subsystem
Temp
Sensor
C674x DSP
Core
@
600MHz
@ 200MHz
(TI Programmed)
Prog RAM &
ROM
Analog/RF
Calibration
2 x EDMA
L1P-32KB
ARM Cortex R4F
L1D-32KB
EMC
UMC
Data
RAM
256 KB of L2 RAM
ESM
32KB ADC data
Buffer
32KB
HS-RAM
B
U
S
2xRTI
SCI
M
A
T
R
I
X
2 lane
Serial LVDS Interface
Upto 768KB shared
L3 memory
Master Subsystem
BUS Matrix
Safety
Cortex-R4F Subsystem
ARM Cortex R4F
VIM
@ 200MHz
ROM
12 8KB
256KB
ProgRAM
with ECC
System Peripherals
LBIST/STC
2xDCC
PBIST
ESM
CRC
2xCCC
Serial Interfaces and Connectivity
3xePWM
2xDMA
192KB
DataRAM
with ECC
2xRTI
GIO
DCAN
2xMIBSPI
QSPI
2xSCI
I2C
Mailbox
Security
2xDMM
AES
PKA
SHA
TRNG
PRCM
JTAG
S/W Buffer
Table 2-1. 16xx Acronyms
ADC
Analog-to-Digital Convertor
AES
Advanced Encryption Standard
CRC
Cyclic Redundancy Check
DCAN
Controller Area Network
DCC
Digital Clock Comparator
DFE
Digital Front End
DMA
Direct Memory Access
DMM
Data Modification Module
ECC
Error Correcting Code
EDMA
Enhanced Direct Memory Access
EMC
Extended Memory Controller
ePWM
Enhanced Pulse Width Modulator
ESM
Error Signaling Module
GIO
General Input/Output
GPADC
General Purpose Analog-to-Digital Convertor
HS-RAM
Handshake RAM
I2C
Inter-Integrated Circuit
JTAG
Joint Test Action Group
L1D
Level 1 Data Memory Controller
L1P
Level 1 Program Memory Controller
160 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Introduction
www.ti.com
Table 2-1. 16xx Acronyms (continued)
2.1.2.2
L2
Level 2
L3
Level 3
LBIST
Logic Built-In Self-Test
LVDS
Low Voltage Differential Signaling
MIBSPI
Multi-Buffered Serial Peripheral Interface Module
OSC
Oscillator
PBIST
Programmable Built-In Self-Test
PKA
Public Key Algorithm
PLL
Phase Locked Loops
PRCM
Power, Reset, Clock Management
QSPI
Quad Serial Peripheral Interface
RTI
Real Time Interrupt
S/W Buffer
Software Buffer
SCI
Serial Communication Interface
SHA
Secure Hash Algorithm
STC
Self-Test Controller
TRNG
True Random Number Generator
UMC
Unified Memory Controller
VIM
Vectored Interrupt Manager
Radar Subsystem
The RADAR subsystem is responsible for the RF and analog functionality of the device. The subsystem
incorporates a built-in self-test processor for the continuous motoring and calibration of the analog and RF
modules. The subsystem consists of:
• FMCW transceiver
– Integrated PLL, transmitter, receiver, baseband, and A2D
– 76-81-GHz coverage with 4-GHz available bandwidth
– Four receive channels
– Two transmit channels
– Ultra-accurate chirp engine based on fractional-n PLL
– 12,14, or 16-bit complex analog to digital converter
• Radio processor for built-in calibration and self-test
– ARM Cortex R4F-based radio control system
– Built-in firmware (ROM)
– Self-calibrating system across frequency and temperature
This subsystem is TI-programmed with an API interface to the on-chip Cortex-R4F application processor.
2.1.2.3
DSP Subsystem
The DSP subsystem consists of the following:
• The TMS320C674x™ VLIW DSP core from the generation, and the TMS320C64x+™ DSP architecture
for RADAR data processing. These are enhancements from TI’s C64x+™ DSP architecture, with
additional features.
• 32KB L1D and 32KB of L1P cache/RAM
• 256KB of L2 RAM
• On-chip L3 shared memory of 768KB, with 256KB dedicated to DSP and 512 KB of memory shared
between the DSP and master subsystems.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
161
16xx Introduction
•
•
•
•
•
•
•
2.1.2.4
www.ti.com
32KB of memory for storing ADC samples from the RADAR subsystem
Multiple Enhanced Direct Memory Access (EDMA) engines – TPCCs for high-performance data
transfers
2-lane LVDS interface with support of up to 900 Mbps per lane for the RADAR raw ADC data transfer
One watchdog timer and a general purpose timer implemented by the real time interrupt (RTI) modules
One serial communication Interface (SCI) module implementing standard universal asynchronous
receiver-transmitter (UART).
Emulation capabilities
Little Endian
Master Subsystem
The master subsystem consists of the following features:
• Cortex-R4F core supporting ARMv7-R, VFPv3-D16, and ARMv7 debug architecture
• Tightly-coupled memories
– 128 KB of ROM
– 256KB of program RAM with ECC
– 192KB of data RAM with ECC
• Hardware auto-initialization of the memories
• Vectored interrupt manager for prioritizing and controlling the interrupts for different sources
2.1.2.4.1 Serial Interfaces
• One DCAN controller supporting bit rates of up to 1 Mbit/s, and compliant to the controller area
network (CAN) 2.0B protocol specification
• One I2C controller module with rates up to 400 kbps
• Two MIBSPI modules
• Two serial communication interface (SCI) modules implementing standard universal asynchronous
receiver-transmitter (UART) with baud rates of up to 3.125 Mbps
• One quad SPI module support with maximum rate of 40 MHz
2.1.2.4.2
•
•
•
•
•
•
•
2.1.2.5
System Peripherals
Multiple general-purpose input/output (GPIO) modules
Direct memory access modules for high-performance data transfers
One watchdog timer and a general purpose timer implemented by the real-time interrupt (RTI) modules
Mailbox module for interprocessor communication
Two data modification modules (DMM) with up to 65 Mbit/s data rate per pin
Three enhanced pulse width (ePWM) modulator modules
System reset and control module, which contains registers for the following functions:
– Status
– Efuse logic
– I/O configuration
– PAD configuration
– System boot decoding logic
Functional Safety Deliverables
See the Device Safety Manual for supported features.
162
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Memory Map
www.ti.com
2.1.2.6
On-Chip Debug Support
The on-chip debug support has the following features:
• Multiprocessor debugging to let users control multiple cores embedded in the device, such as:
– Global starting and stopping of individual or multiple processors
– Each processor can generate triggers to alter the execution flow of other processors
– Interconnection of multiple devices
– Channel triggering
• The following device cores can be debugged through Code Composer Studio (CCS):
– Cortex-R4F
– DSP
• Target debugging using IEEE1149.1 (JTAG®) port
• The debug subsystem includes:
– IEEE1149.7 adapter
– Generic TAP for emulation and test control (ICEPick-D™)
– Debug access port (DAP)
– Embedded trace macro (ETM)
– Trace port interface Unit (TPIU)
– Embedded trace buffer (ETB)
2.2
16xx Memory Map
2.2.1 System Interconnect
The device implements a system interconnect based on TI’s common bus architecture, comprising of
VBUSM and VBUSP protocols. Figure 2-18 shows the interconnect diagram.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
163
16xx Memory Map
www.ti.com
Figure 2-2. System Interconnect
PCR-1 32-bit
MSS_DEBUGSS
MSS_DMM1
RADAR
Subsystem
MSS_DMM2
MSS_ETPWM1
MSS_MBOX4GEM
GEM_MBOX4MSS
MSS_MBOX4BSS
BSS_MBOX4MSS
MSS_DMA
MSS_DMA2
SCR-64bit
MSS_ETPWM2
MSS_ETPWM3
PCR-1 Bridge
Primary SCR(64bit)
PCR-2 Bridge
GEM_MBOX4BSS
BSS_MBOX4GEM
MSS_SW_BUFFER
MSS_CRC
MSS_QSPI
Master
Cortex-R4F
Subsystem
Bridge
C674x DSP
Subsystem
Bridge
DSS_ADCBUF
DSS_L3RAM
DSS_HSRAM1
PRCM
MSS_ESM
MSS_VIM
MSS_IOMUX
MSS_RTIA
MSS_PBIST
MSS_RTIB
MSS_DCAN
MSS_I2C
PCR-2 32-bit
eFuse logic
SCR(128 bit)
MSS_SCIA
MSS_SCIB
Bridge
DSS_TPCC
DSS_TPTC0
DSS_TPTC2
DSS_TPTC1
DSS_TPTC3
Bridge
PCR
Bridge
DSS_TPCC1
DSS_CBUFF
MSS_DCCA
MSS_MIBSPIA
MSS_DCCB
MSS_MIBSPIB
DSS_CRC
MSS_GIO
EDMA
PCR-3 32-bit
BUS Master
DSS_RTI
DSS_RTI2
DSS_REG
DSS_REG2
DSS_SCI
DSS_ESM
Bus-Slave
The system interconnect is designed for the high-performance needs of the system. Its divided into three
interconnect systems local to each of the three subsystems: the RADAR subsystem, DSP subsystem, and
master subsystem. The interconnection of all these subsystems is shown in Figure 3-2.
In the master subsystem, the primary VBUSM SCR is responsible for managing the arbitration priority
between accesses from multiple masters to each of the slaves. The arbitration priority is always roundrobin.
The master subsystem has PCR interconnect that manages the accesses to the peripheral registers and
peripheral memories, and provides a global reset for all peripherals. It also supports the capability to
selectively enable or disable the clock for each peripheral individually. The PCR also manages the
accesses to the system module registers required to configure the device clocks, interrupts, and so forth.
The system module registers include status flags for indicating exception conditions – resets, aborts,
errors, and interrupts.
Similarly, the 128-bit VBUSM SCR in the DSP subsystem manages the arbitration between accesses from
the multiple masters to the slaves. The DSP subsystem has a 32-bit VBUSP PCR for the system and nonsystem peripherals.
2.2.2 Master Subsystem Cortex-R4F Memory Map
Table 3-2 shows the master subsystem, Cortex-R4F memory map.
Table 2-2. Master Subsystem, Cortex-R4F Memory Map
ModuleName
Frame Address (Hex)
Start
End
MSS_TCMA_ROM
0x0000_0000
0x0001_7FFF
Reserved
0x0001_8000
0x001F_FFFF
164 16xx/18xx
Size
Used
Description
128KiB
MSS_TCMA_ROM (TCMA) Program ROM
(refer to ROM Eclipsing section)
Reserved (refer to ROM Eclipsing section)
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Memory Map
www.ti.com
Table 2-2. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size
Used
Description
0x07FF_FFFF
256KiB/
512KiB
MSS_TCMA_RAM (TCMA) size varies
based on device and DSS_L3 (L3) sharing
options configured (refer to ROM Eclipsing
section)
0x0800_0000
0x0C1F_FFFF
192KiB
MSS_TCMB (TCMB) Data RAM
0x0C20_0000
0x0C20_1FFF
8KiB
MSS_SW_BUFFER (SWBUFF)
Scratchpad memory
Reserved
0x0C20_2000
0x4FFF_FFFF
DSS_TPTC0
0x5000_0000
0x5000_03FF
792B
DSS_TPTC0 (EDMA TPTC0) module
configuration space
DSS_REG
0x5000_0400
0x5000_07FF
864B
DSS_REG (DSPSS) control module
registers
DSS_TPTC1
0x5000_0800
0x5000_0BFF
792B
DSS_TPTC1 (EDMA TPTC1) module
configuration space
DSS_REG2
0x5000_0C00
0x5000_FFFF
676B
DSS_REG2 (DSPSS) control module
registers
DSS_TPCC
0x5001_0000
0x5001_FFFF
16KiB
DSS_TPCC (EDMA TPCC0) module
configuration space
DSS_RTI
0x5002_0000
0x5002_FFFF
192B
DSS_RTI (WDT/RTI1) configuration space
DSS_SCI
0x5003_0000
0x5003_FFFF
148B
DSS_SCI (SCI) memory space
DSS_STC
0x5004_0000
0x5004_FFFF
284B
DSS_STC (STC) module configuration
space (refer to Safety chapter)
Reserved
0x5005_0000
0x5006_FFFF
DSS_CBUFF
0x5007_0000
0x5007_FFFF
Reserved
0x5008_0000
0x5008_FFFF
DSS_TPTC2
0x5009_0000
0x5009_03FF
792B
DSS_TPTC2 (EDMA TPTC2) module
configuration space
DSS_TPTC3
0x5009_0400
0x5009_FFFF
792B
DSS_TPTC3 (EDMA TPTC3) module
configuration space
DSS_TPCC1
0x500A_0000
0x500A_FFFF
16KiB
DSS_TPCC1 (EDMA TPCC1) module
configuration space
Reserved
0x500B_0000
0x500C_FFFF
DSS_ESM
0x500D_0000
0x500E_FFFF
1KiB
DSS_ESM (ESM) module configuration
registers (refer to Safety chapter)
DSS_RTI2
0x500F_0000
0x500F_FFFF
192B
DSS_RTI2 (RTI2) module configuration
registers
Reserved
0x5010_0000
0x50FF_FFFF
DSS_L3RAM
0x5100_0000
0x51FF_FFFF
2MB
DSS_L3RAM (L3) shared memory space
DSS_ADCBUF
0x5200_0000
0x5201_FFFF
32KiB
DSS_ADCBUF (ADC) buffer memory
space
DSS_CBUFF_FIFO
0x5202_0000
0x5202_7FFF
16KiB
DSS_CBUFF_FIFO (CBUFF) FIFO space
(refer to HSI chapter)
Reserved
0x5202_8000
0x5207_FFFF
DSS_HSRAM1
0x5208_0000
0x5208_FFFF
Reserved
0x5209_0000
0x577D_FFFF
DSS_DSP_L2_UMAP1
0x577E_0000
0x577F_FFFF
128KiB
DSS_DSP_L2_UMAP1 (L2) RAM space
DSS_DSP_L2_UMAP0
0x5780_0000
0x57DF_FFFF
128KiB
DSS_DSP_L2_UMAP0 (L2) RAM space
DSS_DSP_L1P
0x57E0_0000
0x57EF_FFFF
32KiB
DSS_DSP_L1P (L1) program memory
space
DSS_DSP_L1D
0x57F0_0000
0xBFFF_FFFF
32KiB
DSS_DSP_L1D (L1) data memory space
Start
End
MSS_TCMA_RAM
0x0020_0000
MSS_TCMB
MSS_SW_BUFFER
Reserved
Reserved
564B
DSS_CBUFF (CBUFF) module
configuration registers (refer to HSI
chapter)
Reserved
Reserved
Reserved
Reserved
32KiB
DSS_HSRAM1 (HSRAM) Handshake
memory space
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 165
16xx Memory Map
www.ti.com
Table 2-2. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size
Used
Description
0xC07F_FFFF
8MB
MSS_QSPI (QSPI) flash memory space
0xF060_0FFF
116B
MSS_QSPI (QSPI) module configuration
registers
0xF060_1000
0xF060_1FFF
2KiB
MSS_MBOX4BSS mailbox memory space
BSS_MBOX4MSS
0xF060_2000
0xF060_3FFF
2KiB
BSS_MBOX4MSS mailbox memory space
GEM_MBOX4MSS
0xF060_4000
0xF060_4FFF
2KiB
GEM_MBOX4MSS mailbox memory space
MSS_MBOX4GEM
0xF060_5000
0xF060_5FFF
2KiB
MSS_MBOX4GEM mailbox memory space
GEM_MBOX4BSS
0xF060_6000
0xF060_6FFF
2KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0xF060_7000
0xF060_7FFF
2KiB
BSS_MBOX4GEM mailbox memory space
BSS_MBOX4MSS_REG
0xF060_8000
0xF060_80FF
188B
BSS_MBOX4MSS_REG mailbox
Configuration registers
BSS_MBOX4GEM_REG
0xF060_8100
0xF060_81FF
188B
BSS_MBOX4GEM_REG mailbox
Configuration registers
GEM_MBOX4BSS_REG
0xF060_8200
0xF060_82FF
188B
GEM_MBOX4BSS_REG mailbox
Configuration registers
MSS_MBOX4GEM_REG
0xF060_8300
0xF060_83FF
188B
MSS_MBOX4GEM_REG mailbox
Configuration registers
GEM_MBOX4MSS_REG
0xF060_8400
0xF060_85FF
188B
GEM_MBOX4MSS_REG mailbox
Configuration registers
MSS_MBOX4BSS_REG
0xF060_8600
0xFCF7_8BFF
188B
MSS_MBOX4BSS_REG mailbox
Configuration registers
MSS_ETPWM1
0xFCF7_8C00
0xFCF7_8CFF
116B
MSS_ETPWM1 (ePWM1) configuration
registers
MSS_ETPWM2
0xFCF7_8D00
0xFCF7_8DFF
116B
MSS_ETPWM2 (ePWM2) configuration
registers
MSS_ETPWM3
0xFCF7_8E00
0xFCF8_0FFF
116B
MSS_ETPWM3 (ePWM3) configuration
registers
MSS_DMA2_RAM
0xFCF8_1000
0xFCFF_0FFF
4KiB
MSS_DMA2_RAM (DMA2) RAM memory
space
MSS_PCR2
0xFCFF_1000
0xFCFF_F5FF
1KiB
MSS_PCR2 (PCR_2) interconnect
configuration port
MSS_DMM2
0xFCFF_F600
0xFCFF_F6FF
472B
MSS_DMM2 (DMM2) module configuration
registers
MSS_DMM
0xFCFF_F700
0xFCFF_F7FF
472B
MSS_DMM (DMM1) module configuration
registers
MSS_DMA2_REG
0xFCFF_F800
0xFCFF_FFFF
1KiB
MSS_DMA2_REG (DMA2) module
configuration registers
MSS_DTHE
0xFD00_0000
0xFD00_3FFF
3KiB
MSS_DTHE (Crypto) module configuration
registers
Reserved
0xFD00_4000
0xFDFF_FFFF
MSS_MCRC
0xFE00_0000
0xFF0B_FFFF
16KiB
MSS_MCRC (CRC) module configuration
registers
MSS_MIBSPIB_TXRAM
0xFF0C_0000
0xFF0C_01FF
0.5KiB
MSS_MIBSPIB_TXRAM (MIBSPIB) TX
RAM memory space
MSS_MIBSPIB_RXRAM
0xFF0C_0200
0xFF0D_FFFF
0.5KiB
MSS_MIBSPIB_RXRAM (MIBSPIB) RX
RAM memory space
MSS_MIBSPIA_TXRAM
0xFF0E_0000
0xFF0E_01FF
0.5KiB
MSS_MIBSPIA_TXRAM (MIBSPIA ) TX
RAM memory space
MSS_MIBSPIA_RXRAM
0xFF0E_0200
0xFF1D_FFFF
0.5KiB
MSS_MIBSPIA_RXRAM (MIBSPIA ) RX
RAM memory space
MSS_DCAN_MEM
0xFF1E_0000
0xFF4F_FFFF
128KiB
MSS_DCAN_MEM (CAN) RAM memory
space
Reserved
0xFF50_0000
0xFF9F_FFFF
68KiB
Reserved
Start
End
EXT_FLASH
0xC000_0000
MSS_QSPI
0xC080_0000
MSS_MBOX4BSS
166 16xx/18xx
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Memory Map
www.ti.com
Table 2-2. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size
Used
Description
0xFFF7_7FFF
244KiB
MSS_DEBUGSS (Debug subsystem)
memory space and registers
0xFFF7_8000
0xFFF7_9FFF
1KiB
MSS_PCR (PCR_1) interconnect
configuration port
Reserved
0xFFF7_A000
0xFFF7_BBFF
452B
Reserved
MSS_GIO
0xFFF7_BC00
0xFFF7_C7FF
180B
MSS_GIO (GIO) module configuration
registers
Reserved
0xFFF7_C800
0xFFF7_D3FF
768B
Reserved
MSS_I2C
0xFFF7_D400
0xFFF7_DBFF
112B
MSS_I2C (I2C) module configuration
registers
MSS_DCAN
0xFFF7_DC00
0xFFF7_E4FF
512B
MSS_DCAN (CAN) module configuration
registers
MSS_SCIA
0xFFF7_E500
0xFFF7_E6FF
148B
MSS_SCIA (SCIA/UART) module
configuration registers
MSS_SCIB
0xFFF7_E700
0xFFF7_F3FF
148B
MSS_SCIB (SCIB/UART) module
configuration registers
MSS_MIBSPIA
0xFFF7_F400
0xFFF7_F5FF
512B
MSS_MIBSPIA (MIBSPIA) module
configuration registers
MSS_MIBSPIB
0xFFF7_F600
0xFFF7_FFFF
512B
MSS_MIBSPIB (MIBSPIB) module
configuration registers
MSS_DMA_RAM
0xFFF8_0000
0xFFF8_1FFF
4KiB
MSS_DMA_RAM (DMA1) RAM memory
space
MSS_VIM_MEM
0xFFF8_2000
0xFFF8_BFFF
2KB
MSS_VIM_MEM (VIM) RAM memory
space
Reserved
0xFFF8_C000
0xFFFF_E0FF
MSS_TOPRCM
0xFFFF_E100
0xFFFF_E3FF
756B
MSS_TOPRCM TOP Level Reset, Clock
management registers
MSS_PBIST
0xFFFF_E400
0xFFFF_E5FF
464B
MSS_PBIST (PBIST) module configuration
registers (refer to Safety chapter)
MSS_STC
0xFFFF_E600
0xFFFF_E9FF
284B
MSS_STC (STC) module configuration
registers (refer to Safety chapter)
MSS_IOMUX
0xFFFF_EA00
0xFFFF_EBFF
512B
MSS_IOMUX (IOMUX) module registers
MSS_DCCA
0xFFFF_EC00
0xFFFF_EDFF
44B
MSS_DCCA (DCCA) module configuration
registers
MSS_RTIB
0xFFFF_EE00
0xFFFF_EFFF
192B
MSS_RTIB (WDT/RTIB) module
configuration registers
MSS_DMA_REG
0xFFFF_F000
0xFFFF_F3FF
1KiB
MSS_DMA_REG (DMA1) module
configuration registers
MSS_DCCB
0xFFFF_F400
0xFFFF_F4FF
44B
MSS_DCCB (DCCB) module configuration
registers
MSS_ESM
0xFFFF_F500
0xFFFF_F5FF
156B
MSS_ESM (ESM) module configuration
registers (refer to Safety chapter)
Reserved
0xFFFF_F600
0xFFFF_F7FF
MSS_GPCFG_REG
0xFFFF_F800
0xFFFF_FBFF
352B
MSS_GPCFG_REG (GPCFG) General
purpose control registers
MSS_RTIA
0xFFFF_FC00
0xFFFF_FCFF
192B
MSS_RTIA (RTIA) module configuration
registers
MSS_VIM
0xFFFF_FD00
0xFFFF_FEFF
512B
MSS_VIM (VIM) module configuration
registers
MSS_RCM
0xFFFF_FF00
0xFFFF_FFFF
256B
MSS_RCM (RCM) Reset, Clock
management registers
Start
End
MSS_DEBUGSS
0xFFA0_0000
MSS_PCR
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
167
16xx Memory Map
2.2.2.1
www.ti.com
Radar Subsystem Interface
The RADAR subsystem is accessible through a set of TI-implemented high-level API calls by the
application running on the master CR4F. For more information on the 16xx RADAR subsystem interface,
see the 16xx Interface control document.
2.2.3 DSP Subsystem Memory Map
Table 3-3 shows the DSP C674x memory map.
Table 2-3. DSP C674x Memory Map
Module Name
Frame Address (Hex)
Size
Used
Description
0x007F_FFFF
128KiB
DSP_L2_UMAP1 (L2) RAM space
0x0081_FFFF
128KiB
DSP_L2_UMAP0 (L2) RAM space
0x00E0_0000
0x00E0_7FFF
32KiB
DSP_L1P (L1) program memory space
DSP_L1D
0x00F0_0000
0x00F0_7FFF
32KiB
DSP_L1D (L1) data memory space
DSS_TPTC0
0x0200_0000
0x0200_03FF
1KiB
DSS_TPTC0 (EDMA TPTC0) module configuration
space
DSS_REG
0x0200_0400
0x0200_07FF
864B
DSS_REG (DSPSS) control module registers
DSS_TPTC1
0x0200_0800
0x0200_0BFF
1KiB
DSS_TPTC1 (EDMA TPTC1) module configuration
space
DSS_REG2
0x0200_0C00
0x0200_0FFF
624B
DSS_REG2 (DSPSS) control module registers
DSS_TPCC
0x0201_0000
0x0201_3FFF
16KiB
DSS_TPCC (EDMA TPCC0) module configuration
space
DSS_RTI
0x0202_0000
0x0202_00FF
192B
DSS_RTI (WDT/RTI1) module configuration
registers
DSS_SCI
0x0203_0000
0x0203_00FF
148B
DSS_SCI (SCI/UART) module Configuration
registers
DSS_CBUFF
0x0207_0000
0x0207_03FF
564B
DSS_CBUFF (CBUFF) module Configuration
registers (refer to HSI chapter)
Reserved
0x0208_0000
0x0208_FFFF
DSS_TPTC2
0x0209_0000
0x0209_03FF
1KiB
DSS_TPTC2 (EDMA TPTC2) module configuration
space
DSS_TPTC3
0x0209_0400
0x0209_07FF
1KiB
DSS_TPTC3 (EDMA TPTC3) module configuration
space
DSS_TPCC1
0x020A_0000
0x020A_3FFF
16KiB
DSS_TPCC1 (EDMA TPCC1) module configuration
space
Reserved
0x020B_0000
0x020C_FFFF
DSS_ESM
0x020D_0000
0x020E_FFFF
92B
DSS_ESM (ESM) module Configuration registers
(refer to Safety chapter)
DSS_RTI2
0x020F_0000
0x020F_00FF
192B
DSS_RTI2 (RTI2) module configuration registers
Reserved
0x0210_0000
0x0460_7FFF
BSS_MBOX4MSS_REG
0x0460_8000
0x0460_80FF
188B
BSS_MBOX4MSS_REG mailbox Configuration
registers
BSS_MBOX4GEM_REG
0x0460_8100
0x0460_81FF
188B
BSS_MBOX4GEM_REG mailbox Configuration
registers
GEM_MBOX4BSS_REG
0x0460_8200
0x0460_82FF
188B
GEM_MBOX4BSS_REG mailbox Configuration
registers
MSS_MBOX4GEM_REG
0x0460_8300
0x0460_83FF
188B
MSS_MBOX4GEM_REG mailbox Configuration
registers
GEM_MBOX4MSS_REG
0x0460_8400
0x0460_84FF
188B
GEM_MBOX4MSS_REG mailbox Configuration
registers
MSS_MBOX4BSS_REG
0x0460_8600
0x0460_86FF
188B
MSS_MBOX4BSS_REG mailbox Configuration
registers
Reserved
0x050C_0000
0x1FFF_FFFF
DSS_L3RAM
0x2000_0000
0x201F_FFFF
Start
End
DSP_L2_UMAP1
0x007E_0000
DSP_L2_UMAP0
0x0080_0000
DSP_L1P
168 16xx/18xx
Reserved
Reserved
Reserved
Reserved
2MB
DSS_L3RAM (L3) shared memory space
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Memory Map
www.ti.com
Table 2-3. DSP C674x Memory Map (continued)
Module Name
Frame Address (Hex)
Size
Used
Description
0x2100_7FFC
32KiB
DSS_ADCBUF (ADC buffer) memory space
0x2102_3FFC
16KiB
DSS_CBUFF_FIFO (Common buffer) FIFO space
(Refer to HSI chapter)
Start
End
DSS_ADCBUF
0x2100_0000
DSS_CBUFF_FIFO
0x2102_0000
Reserved
0x2102_8000
0x2107_FFFF
DSS_HSRAM1
0x2108_0000
0x2108_7FFC
Reserved
0x2109_0000
0x21FF_FFFF
DSS_MCRC
0x2200_0000
0x2200_03FF
Reserved
0x2500_0000
0x5060_0FFF
MSS_MBOX4BSS
0x5060_1000
0x5060_17FF
2KiB
MSS_MBOX4BSS mailbox memory space
BSS_MBOX4MSS
0x5060_2000
0x5060_27FF
2KiB
BSS_MBOX4MSS mailbox memory space
GEM_MBOX4MSS
0x5060_4000
0x5060_47FF
2KiB
GEM_MBOX4MSS mailbox memory space
MSS_MBOX4GEM
0x5060_5000
0x5060_57FF
2KiB
MSS_MBOX4GEM mailbox memory space
GEM_MBOX4BSS
0x5060_6000
0x5060_67FF
2KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0x5060_7000
0x5060_57FF
2KiB
BSS_MBOX4GEM mailbox memory space
Reserved
0x5600_0000
0x5060_5FFF
GEM_MBOX4BSS
0x5060_6000
0x5060_67FF
2KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0x5060_7000
0x5060_7FFF
2KiB
BSS_MBOX4GEM mailbox memory space
Reserved
0x5600_0000
0xFFFF_FFFF
Reserved
32KiB
DSS_HSRAM1 (HSRAM) Handshake memory
space
Reserved
1KiB
DSS_MCRC (CRC) module Configuration registers
Reserved
Reserved
Reserved
2.2.4 EDMA Memory Map
Table 3-4 shows the EDMA-TPTC memory map.
Table 2-4. EDMA-TPTC Memory Map
Module Name
DSS_EDMA_SCI
Frame Address (Hex)
Start
End
Size
Used
Description
0x0603_0000
0x0603_00FF
148B
DSS_SCI memory space view from EDMA
DSS_DSP_L2_UMAP1 0x107E_0000
0x107F_FFFF
128KiB
DSP_L2_UMAP1 (L2) memory view from EDMA
DSS_DSP_L2_UMAP0 0x1080_0000
0x1081_FFFF
128KiB
DSP_L2_UMAP0 (L2) memory view from EDMA
DSS_DSP_L1P
0x10E0_0000
0x10E0_7FFF
32KiB
DSP_L1P (L1) program memory view from EDMA
DSS_DSP_L1D
0x10F0_0000
0x10F0_7FFF
32KiB
DSP_L1D (L1) data memory view from EDMA
DSS_L3RAM
0x2000_0000
0x201F_FFFF
2MB
DSS_L3RAM shared memory space
DSS_ADCBUF
0x2100_0000
0x2100_7FFC
32KiB
DSS_ADCBUF memory space
DSS_CBUFF_FIFO
0x2102_0000
0x2102_3FFC
16KiB
DSS_CBUFF_FIFO (Common buffer) memory
space (Refer to HSI chapter)
DSS_HSRAM1
0x2108_0000
0x2108_7FFC
32KiB
DSS_HSRAM1 (Handshake) memory
MSS_TCMA_RAM
0x4020_0000
0x4023_FFFF
256 KiB
MSS_TCMA_RAM (TCMA) Data RAM
MSS_TCMB
0x4800_0000
0x4802_FFFF
192 KiB
MSS_TCMB (TCMB) Data RAM
MSS_SW_BUFFER
0x4C20_0000
0x4C20_1FFF
8 KiB
MSS_SW_BUFFER S/W Scratchpad memory
GEM_MBOX4MSS
0x5060_4000
0x5060_4000
2 KiB
GEM_MBOX4MSS mailbox memory space
MSS_MBOX4GEM
0x5060_5000
0x5060_5000
2 KiB
MSS_MBOX4GEM mailbox memory space
GEM_MBOX4BSS
0x5060_6000
0x5060_6000
2 KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0x5060_7000
0x5060_7000
2 KiB
BSS_MBOX4GEM mailbox memory space
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
169
16xx Integration
2.3
www.ti.com
16xx Integration
2.3.1 Cortex-R4F Subsystem
2.3.1.1
Tightly Coupled Memories
Table 3-5 lists the dedicated MSS_TCMA_RAM and MSS_TCMB sizes for the Cortex R4F processor in
the master subsystem, and also mentions the total available L3 shared RAM in the device. A portion of
this L3 shared memory (DSS_L3RAM) can be allotted as TCM, to further increase the MSS_TCMA_RAM
and MSS_TCMB available for the Cortex R4F.
Table 2-5. TCM and Shared Memory Available for Cortex R4F in Master Subsystem
Cortex R4F
Shared
MSS_TCMA_RAM (Program RAM) (KB)
MSS_TCMB (Data RAM) (KB)
L3 Shared (KB)
256
192
768
See on how the L3 shared memory (DSS_L3RAM) can be assigned between the Cortex R4F of the
master subsystem and the DSP core.
170
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
2.3.2 Clock Comparator
2.3.2.1
Core Clock Comparator (MSS_CCCA/MSS_CCCB)
Figure 2-3. Integration of MSS_CCCA and MSS_CCCB Modules
mss_vclk
async_rst_n
clock0_src[7:0]
clock1_src[7:0]
clock0_sel[7:0]
clock1_sel[7:0]
count0_expiry_val
MSS_GPCFG
counter_error
counter_done
To MSS_ESM Module
To MSS_VIM Module
MSS_CCCA
(CCCA)
count1_expected_val
disable_clk_output
enable_module
margin_count
count1_val_out
MSS_GPCFG
errstat
singleshot_mode
timeout_err_count
mss_vclk
async_rst_n
clock0_src[7:0]
clock1_src[7:0]
clock0_sel[7:0]
clock1_sel[7:0]
count0_expiry_val
MSS_GPCFG
counter_error
counter_done
To MSS_ESM Module
To MSS_VIM Module
MSS_CCCB
(CCCB)
count1_expected_val
disable_clk_output
count1_val_out
enable_module
margin_count
errstat
MSS_GPCFG
singleshot_mode
timeout_err_count
2.3.2.1.1 MSS_CCCA and MSS_CCCB Integration Connections
This device has two instances of CCC: MSS_CCCA (CCCA) and MSS_CCCB (CCCB). The clock
connectivity information for these two instances is provided in Table 3-6. Configuration and status of this
module is available through the MSS_GPCFG registers of the device.
Table 2-6. MSS_CCCA and MSS_CCCB Integration Connections
MSS_CCCA (CCCA)
MSS_CCCB (CCCB)
counter_error
ESM_GRP1[1]
ESM_GRP1[4]
counter_done
IRQ[80]
IRQ[81]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 171
16xx Integration
www.ti.com
Table 2-6. MSS_CCCA and MSS_CCCB Integration Connections (continued)
MSS_CCCA (CCCA)
MSS_CCCB (CCCB)
clock0_src[0]
REFCLK
CR4_VCLK
clock0_src[1]
CPUCLK
DSSCLK
clock0_src[2]
RCCLK
BSSCLK
clock0_src[3]
RCCLK
QSPICLK
clock0_src[4]
RCCLK
N/A
clock0_src[5]
RCCLK
REFCLK
clock0_src[6]
RCCLK
CPUCLK
clock0_src[7]
RCCLK
RCCLK
clock1_src[0]
REFCLK
PLLCLK_600
clock1_src[1]
PLLCLK_600
MSS_VCLK
clock1_src[2]
PLL 240Mhz
CPUCLK
clock1_src[3]
RCCLK
CR4_VCLK
clock1_src[4]
RCCLK
MSS_VCLK
clock1_src[5]
RCCLK
DSSCLK
clock1_src[6]
RCCLK
BSSCLK
clock1_src[7]
RCCLK
QSPICLK
2.3.2.1.2 MSS_CCCB Integration to MSS_WD
As a safety requirement, WDT IP should work on an independent clock source instead of the clock used
by the MSS CR4. Because the WDT IP does not allow this flexibility, an additional monitoring logic is
added in the form of CCM (MSS_CCCB instance), coupled along with the watchdog. MSS_CCCB is used
to compare CR4_VCLK to an independent reference clock, such as XTAL. If the CR4 clock indicates a
deviation from the expected frequency, a WD reset or a WD NMI can be issued.
Figure 2-4. MSS_CCCB Integration to MSS_WD
MSS_WD_RST
(WARM_RESET generation)
RTI_RESETn
MSS_WDT
(MSS_RTIB)
RTI_WWD_NMI
counter_error
MSS_GPCFG.ENABLECCBERRRSTN
MSS_CCCB
MSS_WD_NMI
(to MSS_ESM)
MSS_GPCFG.ENABLECCBERRNMI
172
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
2.3.2.2
Dual Clock Comparator (MSS_DCCA/MSS_DCCB)
Figure 2-5. MSS_DCCA/MSS_DCCB Integration Diagram
MSS_DCC
Clock Source Selection
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
MSS_DCCA/
MSS_DCCB
(DCCA/DCCB)
dcc_done_int
To MSS_VIM Module
dcc_error
To MSS_ESM Module
Table 2-7. MSS_DCCA Clock Source Selection Table
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
0x0 - REF_CLK
0x0 - REF_CLK
0xA - PLL_600
0x1 - CPU_CLK
0x5 - PLL_240
0x2 to 0x7 - RC_CLK
Table 2-8. MSS_DCCB Clock Source Selection Table
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
0x0 - PLL_600
0x0 - VCLK
0xA - VCLK
0x1 - DSS_CLK
0x5 - CPU_CLK
0x2 - BSS_CLK
0x3 - QSPI_CLK
0x4 - Reserved
0x5 - CPU_CLK
0x6 - REF_CLK
0x7 - RC_CLK
NOTE: Any values not mentioned are not used.
2.3.3 C674x DSP Subsystem
2.3.3.1
DSP Event Assignment
Table 2-9. DSP Event Assignment
Event No.
Interrupt
Description
0
EVT0
Output of event combiner0, for events 1 through 31
1
EVT1
Output of event combiner0, for events 32 through 63
2
EVT2
Output of event combiner0, for events 64 through 95
3
EVT3
Output of event combiner0, for events 96 through 127
4
Reserved
Reserved
5
Reserved
Reserved
6
Reserved
Reserved
7
Reserved
Reserved
8
Reserved
Reserved
9
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 173
16xx Integration
www.ti.com
Table 2-9. DSP Event Assignment (continued)
Event No.
Interrupt
Description
10
Reserved
Reserved
11
Reserved
Reserved
12
Reserved
Reserved
13
IDMAINT0
From DSP EMC, IDMA Channel 0 Interrupt
14
IDMAINT1
From DSP EMC, IDMA Channel 1Interrupt
15
Reserved
Reserved
16
DSS_TPTC0_IRQ_DONE
DSS_TPTC0 (EDMA TPTC0) completion interrupt
17
DSS_TPTC0_IRQ_ERR
DSS_TPTC0 (EDMA TPTC0) Error Interrupt
18
DSS_TPTC1_IRQ_DONE
DSS_TPTC1 (EDMA TPTC1) completion interrupt
19
DSS_TPTC1_IRQ_ERR
DSS_TPTC1 (EDMA TPTC1) Error Interrupt
20
DSS_TPCC_IRQ_DONE
DSS_TPCC (EDMA TPCC0) Global completion Interrupt
21
DSS_TPCC_IRQ_ERR
DSS_TPCC (EDMA TPCC0) Error Interrupt
22
DSS_CBUFF_IRQ
DSS_CBUFF (COMMON BUFFER) Interrupt
23
Reserved
Reserved
24
DSS_CBUFF_ERR_INTR
DSS_CBUFF (COMMON BUFFER) Error Interrupt
25
Reserved
Reserved
26
DSS_FRAME_START_IRQ/DSS_DMMSW Mux of VIN Frame start or BSS DFE Frame start.
IN T0/DSS_DMMSWINT39
27
DSS_CHIRP_AVAIL_IRQ/DSS_DMMSWI
NT2 /DSS_DMMSWINT43
Mux of VIN Chirp Available or DFE chirp available..
28
Reserved
Reserved
29
Reserved
Reserved
30
Reserved
Reserved
31
Reserved
Reserved
32
DSS_ESM_LOW_PRIORITY
MSS_ESM_IRQ (Aggregate of MSS_ESM_GP1 errors)
33
DSS_MCRC_INT
MSS_MCRC (CRC) Interrupt
34
DSS_PROG_FILT_ERR
Error interrupt from Programmable filter indicating wrong
programming of filter length exceeding the allowed range.
35
GEM_WAKEUP_SOURCE_FROM_DFT
Wakeup source from DFT module.
36
DSS_STC_DONE
Done indication from DSS_STC
37
DSP_PBIST_DONE
DSP_PBIST done indication from GEM
38
Reserved
Reserved
39
Reserved
Reserved
40
Reserved
Reserved
41
Reserved
Reserved
42
Reserved
Reserved
43
Reserved
Reserved
44
Reserved
Reserved
45
Reserved
Reserved
46
DSS_DMMSWINT8
Interrupt from DSS_DMM configurable
47
DSS_DMMSWINT4
Interrupt from DSS_DMM configurable
48
Reserved
Reserved
49
Reserved
Reserved
50
Reserved
Reserved
51
Reserved
Reserved
52
Reserved
Reserved
53
Reserved
Reserved
54
Reserved
Reserved
174 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-9. DSP Event Assignment (continued)
Event No.
Interrupt
Description
55
Reserved
Reserved
56
Reserved
Reserved
57
Reserved
Reserved
58
DSS_MSS_SW0
DSS_MSS_SW interrupt
59
DSS_MSS_SW1
DSS_MSS_SW interrupt
60
DSS_DMMSWINT5
Interrupt from DSS_DMM configurable
61
DSS_DMMSWINT6
Interrupt from DSS_DMM configurable
62
DSS_BSS_SW1
Radar SS SW Interrupt 0
63
DSS_BSS_SW2
Radar SS SW Interrupt 1
64
DSS_TPTC2_IRQ_DONE
DSS_TPTC2 (EDMA TPTC2) completion interrupt
65
DSS_TPTC2_IRQ_ERR
DSS_TPTC2 (EDMA TPTC2) Error Interrupt
66
DSS_TPTC3_IRQ_DONE
DSS_TPTC3 (EDMA TPTC3) completion interrupt
67
DSS_TPTC3_IRQ_ERR
DSS_TPTC3 (EDMA TPTC3) Error Interrupt
68
DSS_TPCC1_IRQ_DONE
DSS_TPCC1 (EDMA TPCC1) Global completion Interrupt
69
DSS_TPCC1_IRQ_ERR
DSS_TPCC1 (EDMA TPCC1) Error Interrupt
70
DSS_ADC_DATA_VALID_FALL/DSS_DM
MS WINT3/DSS_DMMSWINT44
DSS_ADC Ping/Pong interrupt
71
DSS_UART_REQ0
DSS_SCI (UART) Req 0
72
DSS_UART_REQ1
DSS_SCI (UART) Req 1
73
DSS_RTI0_OVERFLOW_0
DSS_RTI Overflow 0
74
DSS_RTI0_OVERFLOW_1
DSS_RTI Overflow 1
75
DSS_RTI0_0
DSS_RTI Interrupt 0
76
DSS_RTI0_1
DSS_RTI Interrupt 1
77
DSS_RTI0_2
DSS_RTI Interrupt 2
78
DSS_RTI0_3
DSS_RTI Interrupt 3
79
DSS_RTI1_OVERFLOW_0
DSS_RTI2 Overflow 0
80
DSS_RTI1_OVERFLOW_1
DSS_RTI2 Overflow 1
81
DSS_RTI1_0
DSS_RTI2 Interrupt 0
82
DSS_RTI1_1
DSS_RTI2 Interrupt 1
83
DSS_RTI1_2
DSS_RTI2 Interrupt 2
84
DSS_RTI1_3
DSS_RTI2 Interrupt 3
85
DSS_BSS_MAILBOX_FULL
Interrupt indicating there is a message from MSS in the
Mailbox BSS-DSS
86
DSS_BSS_MAILBOX_EMPTY
Interrupt indicating the MSS has read/ack the message DSP
posted in the Mailbox DSS-BSS
87
GPIO_0_host_interrupt
MSS_GIO (GPIO) host Interrupt Controller
88
GPIO_1_host_interrupt
MSS_GIO (GPIO) host Interrupt Controller
89
GPIO_2_host_interrupt
MSS_GIO (GPIO) host Interrupt Controller
90
Reserved
Reserved
91
DSS_MSS_MAILBOX_FULL
Interrupt indicating there is a message from MSS in the
Mailbox MSS-DSS
92
DSS_MSS_MAILBOX_EMPTY
Interrupt indicating the MSS has read/ack the message DSP
posted in the Mailbox DSS-MSS
93
DSS_LOGICAL_FRAME_START/DSS_D
MM SWINT1/DSS_DMMSWINT40
Logical Frame start interrupt
94
DSS_DMMSWINT7
Interrupt from DSS_DMM configurable
95
Reserved
Reserved
96
INTERR
DSP dropped CPU interrupt event
97
IDMA_ERR
Invalid IDMA parameters
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 175
16xx Integration
www.ti.com
Table 2-9. DSP Event Assignment (continued)
Event No.
Interrupt
Description
98
Reserved
Reserved
99
Reserved
Reserved
100
Reserved
Reserved
101
Reserved
Reserved
102
Reserved
Reserved
103
Reserved
Reserved
104
Reserved
Reserved
105
Reserved
Reserved
106
Reserved
Reserved
107
Reserved
Reserved
108
Reserved
Reserved
109
Reserved
Reserved
110
Reserved
Reserved
111
Reserved
Reserved
112
Reserved
Reserved
113
DSP_PMC_ED
DSS_DSP_L1P parity error
114
Reserved
Reserved
115
Reserved
Reserved
116
DSP_UMC_ED1
DSS_DSP_L2 ECC single error correction
117
DSP_UMC_ED2
DSS_DSP_L2 ECC double error detection
118
DSP_PDC_INT
Power down sleep interrupt
119
DSP_SYS_CMPA
CPU memory protection fault
120
DSP_L1P_CMPA
DSS_DSP_L1P CPU memory protection fault
121
DSP_L1P_DMPA
DSS_DSP_L1P DMA memory protection fault
122
DSP_L1D_CMPA
DSS_DSP_L1D CPU memory protection fault
123
DSP_L1D_DMPA
DSS_DSP_L1D DMA memory protection fault
124
DSP_L2_CMPA
DSS_DSP_L2 CPU memory protection fault
125
DSP_L2_DMPA
DSS_DSP_L2 DMA memory protection fault
126
DSP_EMC_CMPA
From EMC, CPU memory protection fault
127
DSP_EMC_BUSSERR
From EMC, bus error interrupt
2.3.4 Direct Memory Access Controller (MSS_DMA)
2.3.4.1
MSS_DMA Integration Diagrams
The device has two instances of DMA module, MSS_DMA and MSS_DMA2. Integration of the two DMA
blocks in the device are shown in Figure 3-5 and .
176
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Figure 2-6. Integration of MSS_DMA and MSS_DMA2 Module
From MSS_RCM
VCLK
RSTn
MMI_START
MMI_DONE
MSS_DMA
dma1_req[63:0]
Request Source
Configuration Port
VBUS PCR
From BUS Matrix
From MSS_RCM
MSS_DMA
(DMA1)
VCLK
RSTn
MMI_START
MMI_DONE
Configuration Port
VBUS_PCR
VBUS PCR
From BUS Matrix
To MSS_VIM Module
dma1_uerr
dma1_mpv
dma1_wrerr_int_pls
dma1_portb_vbusm
VBUS_PCR
MSS_DMA
dma2_req[63:0]
Request Source
dma1_ftcint
dma1_lfsint
dma1_hbcint
dma1_btcint
dma1_berint
MSS_DMA2
(DMA2)
dma2_ftcint
dma2_lfsint
dma2_hbcint
dma2_btcint
dma2_berint
To MSS_ESM Module
Master Port on
BUS Matrix
To MSS_VIM Module
dma2_uerr
To MSS_ESM Module
dma2_mpv
dma2_wrerr_int_pls
dma2_portb_vbusm
Master Port on
BUS Matrix
2.3.4.2 MSS_DMA Features
• 64-bit OCP protocol to perform bus master accesses
• INCR-4 64-bit burst accesses
• Multithreading architecture allowing data of two different channel transfers to be interleaved during
non-burst accesses
• 2-port configuration for parallel bus master
• Channels can be assigned to either high-priority queue or low-priority queue. Within each queue, fixed
or round-robin priorities can be serviced
• Built-in ECC generation and evaluation logic for internal RAM-storing channel transfer information
• Supports multiple interrupt outputs for mapping to multiple interrupt controllers in multicore systems
• 48 requests can be mapped to any 32 channels
• Supports LE endianness
• External ECC Gen/Eval block of MSS_DMA support ECC generation for data transactions, and parity
for address, and control signals (following Cortex-R5F standard)
• 8 MPU regions
• Channel-chaining capability
• Hardware and software MSS_DMA requests
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
177
16xx Integration
•
•
•
2.3.4.3
www.ti.com
8-, 16-, 32-, or 64-bit transactions supported
Multiple addressing modes for source and destination (fixed, increment, offset)
Auto-initiation
MSS_DMA Request Map
Both instances of MSS_DMA have 64 lines of request and are connected to identical input triggers, as
shown in Table 3-10. This allows the two DMAs to trigger different types of transfers for the same request.
Table 2-10. MSS_DMA Request Map
Module
DMA Request Sources
DMA Request
MSS_MIBSPIA
MSS_MIBSPIA Channel-1
DMAREQ[0]
MSS_MIBSPIA
MSS_MIBSPIA Channel-0
DMAREQ[1]
MSS_MIBSPIB
MSS_MIBSPIB
DMAREQ[2]
MSS_MIBSPIB
MSS_MIBSPIB
DMAREQ[3]
MSS_QSPI
MSS_QSPI DMA request
DMAREQ[4]
MSS_MIBSPIA
MSS_MIBSPIA Channel-3
DMAREQ[5]
MSS_DCAN
MSS_DCAN IF2
DMAREQ[6]
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) DMAREQ
DMAREQ[7]
MSS_DCAN
MSS_DCAN IF1
DMAREQ[8]
MSS_MIBSPIA
MSS_MIBSPIA Channel-5
DMAREQ[9]
MSS_I2C
MSS_I2C receive
DMAREQ[10]
MSS_I2C
MSS_I2C transmit
DMAREQ[11]
MSS_RTIA
MSS_RTIA DMAREQ0
DMAREQ[12]
MSS_RTIA
MSS_RTIA DMAREQ1
DMAREQ[13]
Reserved
Reserved
DMAREQ[14]
Reserved
Reserved
DMAREQ[15]
MSS_DCAN
MSS_DCAN IF3
DMAREQ[16]
MSS_MIBSPIA
MSS_MIBSPIA Channel-2
DMAREQ[17]
MSS_RTIA
MSS_RTIA DMAREQ2
DMAREQ[18]
MSS_RTIA
MSS_RTIA DMAREQ3
DMAREQ[19]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ0
DMAREQ[20]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ1
DMAREQ[21]
MSS_MIBSPIA
MSS_MIBSPIA Channel-4
DMAREQ[22]
MSS_ETPWM3A
MSS_ETPWM3A DMAREQ
DMAREQ[23]
MSS_RTIB (WDT/RTIB)
WDT/RTIB DMAREQ2
DMAREQ[24]
MSS_RTIB (WDT/RTIB)
WDT/RTIB DMAREQ3
DMAREQ[25]
MSS_MCRC (CRC)
MSS_MCRC (CRC) DMAREQ0
DMAREQ[26]
MSS_MCRC (CRC)
MSS_MCRC (CRC) DMAREQ1
DMAREQ[27]
MSS_SCIB (UART2)
MSS_SCIB (UART2) receive
DMAREQ[28]
MSS_SCIB (UART2)
MSS_SCIB (UART2) transmit
DMAREQ[29]
MSS_SCIA (UART1)
MSS_SCIA (UART1) receive
DMAREQ[30]
MSS_SCIA (UART1)
MSS_SCIA (UART1) transmit
DMAREQ[31]
MSS_GIO
MSS_GIO-0
DMAREQ[32]
MSS_GIO
MSS_GIO-1
DMAREQ[33]
MSS_GIO
MSS_GIO-2
DMAREQ[34]
MSS_ETPWM1A
MSS_ETPWM1A DMAREQ
DMAREQ[35]
Reserved
Reserved
DMAREQ[36]
MSS_MIBSPIB
MSS_MIBSPIB Channel-2
DMAREQ[37]
MSS_MIBSPIB
MSS_MIBSPIB Channel-3
DMAREQ[38]
MSS_ETPWM1B
MSS_ETPWM1B DMAREQ
DMAREQ[39]
178 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-10. MSS_DMA Request Map (continued)
Module
DMA Request Sources
DMA Request
MSS_ETPWM2A
MSS_ETPWM2A DMAREQ
DMAREQ[40]
MSS_ETPWM2B
MSS_ETPWM2B DMAREQ
DMAREQ[41]
MSS_MIBSPIB
MSS_MIBSPIB Channel-4
DMAREQ[42]
MSS_MIBSPIB
MSS_MIBSPIB Channel-5
DMAREQ[43]
Reserved
Reserved
DMAREQ[44]
MSS_ETPWM3B
MSS_ETPWM3B DMAREQ
DMAREQ[45]
MSS_GIO
MSS_GIO-14
DMAREQ[46]
MSS_GIO
MSS_GIO-15
DMAREQ[47]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-0
DMAREQ[48]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-1
DMAREQ[49]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-2
DMAREQ[50]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-3
DMAREQ[51]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-4
DMAREQ[52]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-5
DMAREQ[53]
MSS_DTHE (Crypto/AES)
AES DMAREQ-0
DMAREQ[54]
MSS_DTHE (Crypto/AES)
AES DMAREQ-1
DMAREQ[55]
MSS_DTHE (Crypto/AES)
AES DMAREQ-2
DMAREQ[56]
MSS_DTHE (Crypto/AES)
AES DMAREQ-3
DMAREQ[57]
MSS_DTHE (Crypto/AES)
AES DMAREQ-4
DMAREQ[58]
MSS_DTHE (Crypto/AES)
AES DMAREQ-5
DMAREQ[59]
MSS_DTHE (Crypto/AES)
AES DMAREQ-6
DMAREQ[60]
MSS_DTHE (Crypto/AES)
AES DMAREQ-7
DMAREQ[61]
Reserved
Reserved
DMAREQ[62]
Reserved
Reserved
DMAREQ[63]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
179
16xx Integration
www.ti.com
2.3.5 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB)
Figure 2-7. Integration of MSS_RTIA and MSS_RTIB, WDT Using the MSS_RTIB Module
From
MSS_RCM
rti_ovf l_req[1:0]
rti_vclk
rti_ cmp_int_req[3:0]
rti_sync
Not used
RTI_PIN
To/From MSS_VIM
rti_tb_int_req
Vim_cap_evt[1:0]
NTU[3:0]
MSS_RTIA
(RTIA)
rti_dma_req[3:0]
To MSS_DMA/MSS_DMA2
VBUS_PCR
MSS_RTI Register Configuration
MSS_RTIC
MSS_RTID
wdt_ovl_req[1:0]
wdt_vclk
To/From
wdt_sync
MSS_RCM
wdt _rstn
Port from Bus Matrix
wdt_int_req[3:0]
To MSS_VIM
wdt_tb_int_req
Vim_cap_evt[1:0]
MSS_RTIB
NTU[3:0]
Not used
RTI_PIN
(WDT/RTIB)
wdt _dma_req[3 :0]
To MSS_DMA/MSS_DMA2
VBUS_PCR
MSS_WDT Register Configuration
wdt_nmi_req
Port from Bus Matrix
To MSS_ESM
2.3.6 General Purpose I/0 (MSS_GIO)
NOTE: Emulation mode and power-down mode (low-power mode) are not supported in the 16xx
device.
180
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Figure 2-8. Integration Block Diagram for MSS_GIO
gio_vclk
From
MSS_RCM
MSS_GIO
(GIO)
gio_rstn
GIOA[7:0]
GIOB[7:0]
gio_pc
Device
PCR Bus
GIOC[7:0]
To/from device pins
GPIO_0:GPIO_47
GIOD[7:0]
GIOE[7:0]
GIOF[7:0]
GIO_low_level_interrupt
To
MSS_VIM
GIO_high_level_interrupt
GIO G and F, is
included but not
supported
GIO_0_host_interrupt
To MSS_VIM &
DSP-Event
GPIO_0
GIO_1_host_interrupt
GIO_2_host_interrupt
GPIO Host
Interrupt Controller
(Specific to AR16)
GPIO_1
GPIO_2
From device pins
GPIO_0,GPIO_1,GPIO_2
GIO_0_host_DMA
To MSS_DMA
GIO_1_host_DMA
GIO_2_host_DMA
MSS_GPCFG_REG:
GPIOINTREDGESEL
GIO_14_host_DMA
GPIO_14
To MSS_DMA
Positive Edge to Pulse
GPIO_15
From device pins
GPIO_14, GPIO_15
GIO_15_host_DMA
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
181
16xx Integration
www.ti.com
2.3.7 Data Modification Module (MSS_DMM)
Figure 2-9. MSS_DMM Integration
From
MSS_RCM
dmm_vclk
dmm_rstn
Config
Port From
Bus-matrix
DMM1_PCR
dmm1_int_lvl0
dmm1_int_lvl1
ToMSS_VIM
MSS_DMM
(DMM1)
Not used
AHB2VBUSP
&
VBUSP2VBUSM
dmm_clk
To/from dmmsync_in
device dmmdata_in[15:0]
pins
dmmmux_in
DMM
SCR
64-Bit
MSS BUS MATRIX
AHB2VBUSP
&
VBUSP2VBUSM
Not used
From
MSS_RCM
Config
Port From
Bus-matrix
182
16xx/18xx
dmm_vclk
dmm_rstn
DMM2_PCR
MSS_DMM2
(DMM2)
dmm2_int_lvl0
dmm2_int_lvl1
ToMSS_VIM
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
2.3.8 Enhanced Pulse Width Modulator (MSS_ETPWM)
Figure 2-10. Multiple MSS_ETPWM Modules
Frame start
Rampgen
ePWM1_synci_in
From device pins
MSS_GPCFG_REG:
EPWMCFG
ePWM1_sync
ePWM1a_output
ePWM1b_output
ePWM1_vlk
From MSS_RCM ePWM1_rst
Device pins
MSS_ESM low-level int
DCC_1 done int
Not used
ePWM1a_dma_req
ePWM1b_dma_req
ePWM1_TZ[2:0]
ePWM1_TZ[3]
ePWM1_TZ[4]
ePWM1_TZ[5]
MSS_ETPWM1
(ePWM1)
ePWM1_adc_soc[1:0]
ePWM1_pcr
MSS_GPCFG_REG:
EPWMCFG
Frame start ePWM1_sync_out
Rampgen
MSS_GPCFG_REG:
PWMDMATRIGEN
To
MSS_DMA/
MSS_DMA2
Not used
ePWM1_int[1:0]
Device PCR Bus
To device pins
ToMSS_VIM
Todevice pins
ePWM2_sync
ePWM2a_output
ePWM2b_output
ePWM2_vlk
From MSS_RCM ePWM2_rst
Device pins
MSS_ESM low-level int
DCC_1 done int
Not used
ePWM2a_dma_req
ePWM2b_dma_req
ePWM2_TZ[2:0]
ePWM2_TZ[3 ]
ePWM2_TZ[4]
ePWM2_TZ[5]
Device PCR Bus
MSS_ETPWM2
(ePWM2)
MSS_GPCFG_REG:
EPWMCFG
ePWM2_int[1:0]
Frame start
Rampgen
ePWM2_sync_out
MSS_GPCFG_REG:
PWMDMATRIGEN
To
MSS_DMA/
MSS_DMA2
Not used
ePWM2_adc_soc[1:0]
ePWM2_pcr
To device pins
ToMSS_VIM
To device pins
ePWM3_sync
ePWM3a_output
ePWM3b_output
ePWM3_vlk
From MSS_RCM ePWM3_rst
Device pins
MSS_ESM low-level int
DCC_1 done int
Not used
ePWM3_TZ[2:0]
ePWM3_TZ[3]
ePWM3_TZ [4]
ePWM3_TZ[5]
Device PCR Bus
ePWM3a_dma_req
ePWM3b_dma_req
MSS_ETPWM3
(ePWM3)
ePWM3_adc_soc[1:0]
ePWM3_pcr
ePWM3_int[1:0]
ePWM3_sync_out
Note : Rampgen and Frame start
are from the RADAR Subsystem
To device pins
To
MSS_DMA/MSS_DMA2
Not used
To MSS_VIM
To device pins
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
183
16xx Integration
www.ti.com
2.3.9 Vectored Interrupt Manager (MSS_VIM)
2.3.9.1
Interrupt Request Assignments
Table 2-11. Interrupt Request Assignments
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
MSS_ESM
MSS_ESM high-level interrupt(NMI)
0
Reserved
Reserved
1
MSS_RTIA
MSS_RTIA compare interrupt 0
2
MSS_RTIA
MSS_RTIA compare interrupt 1
3
MSS_RTIA
MSS_RTIA compare interrupt 2
4
MSS_RTIA
MSS_RTIA compare interrupt 3
5
MSS_RTIA
MSS_RTIA overflow interrupt 0
6
MSS_RTIA
MSS_RTIA overflow interrupt 1
7
MSS_RTIA
MSS_RTIA time-base
8
MSS_GIO
MSS_GIO high-level interrupt
9
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 0
10
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt1
11
MSS_MIBSPIA
MSS_MIBSPIA level 0 interrupt
12
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 2
13
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 3
14
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) overflow interrupt 15
0
MSS_DCAN
MSS_DCAN level 0 interrupt
16
MSS_MIBSPIB
MSS_MIBSPIB level 0 Interrupt
17
MSS_GIO host interrupt module
MSS_GIO GPIO_0_host_interrupt
18
MSS_MCRC (CRC)
MSS_MCRC (CRC) interrupt
19
MSS_ESM
MSS_ESM low-level interrupt
20
SYSTEM
Software-triggered interrupt 4
21
MSS Cortex R4F
MSS Cortex R4F interrupt PMU
22
MSS_GIO
MSS_GIO low-level interrupt
23
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) overflow interrupt 24
1
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) TB base interrupt 25
MSS_MIBSPIA
MSS_MIBSPIA level 0 interrupt
26
MSS_QSPI
MSS_QSPI interrupt
27
MSS_DMM
MSS_DMM S/W interrupt 38
28
MSS_DCAN
MSS_DCAN level 1 interrupt
29
MSS_MIBSPIB
MSS_MIBSPIB level 1 interrupt
30
MSS_DTHE (Crypto/SHA)
MSS_DTHE (Crypto/SHA) SHA -S
interrupt
31
MSS_GIO host interrupt module
MSS_GIO GPIO_1_host_interrupt
32
MSS_DMA
MSS_DMA frame transfer complete
interrupt
33
MSS_DMA
MSS_DMA last frame transfer start
interrupt
34
Reserved
Reserved
35
MSS_DMM
MSS_DMM level -0 interrupt
36
MSS_DTHE (Crypto/SHA)
MSS_DTHE (Crypto/SHA) SHA -P
interrupt
37
MSS_DTHE (Crypto/TRNG)
MSS_DTHE (Crypto/TRNG) TRNG
interrupt
38
184 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-11. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
MSS_DMA
MSS_DMA half-block transfer complete
interrupt
39
MSS_DMA
MSS_DMA block transfer complete
interrupt
40
MSS_DMA2
MSS_DMA2 frame block transfer
complete interrupt
41
Reserved
Reserved
42
MSS_DMM
MSS_DMM level -1 interrupt
43
Reserved
Reserved
44
MSS_DMA2
MSS_DMA2 last frame complete interrupt
45
Reserved
Reserved
46
FPU
Floating point unit interrupt
47
MSS_GIO (GPIO host interrupt module)
MSS_GIO GPIO_2_host_interrupt
48
MSS_DMA2
MSS_DMA2 half-block transfer complete
interrupt
49
MSS_DMA2
MSS_DMA2 block transfer complete
interrupt
50
MSS_DMA2
MSS_DMA2 bus error interrupt
51
System
DSS to MSS software-triggered by
register
DSS_REG2:MSSSWIRQ:MSSSWIRQ1
52
MSS_DTHE (Crypto/PKA)
MSS_DTHE (Crypto/PKA) PKA module
interrupt
53
MSS_DTHE (Crypto/AES)
MSS_DTHE (Crypto/AES) AES-S module
interrupt
54
Reserved
Reserved
55
MSS_DTHE (Crypto/AES)
MSS_DTHE (Crypto/AES) AES-P module
interrupt
56
MSS_DMM2
MSS_DMM2 level -0 interrupt
57
MSS_DMM2
MSS_DMM2 level -1 interrupt
58
Mailbox
DSS to MSS mailbox full interrupt
59
Mailbox
DSS to MSS mailbox empty interrupt
60
System
DSS to MSS software-triggered by
register
DSS_REG2:MSSSWIRQ:MSSSWIRQ2
61
MSS_DEBUGSS (Debug subsystem)
MSS_DEBUGSS (Debug subsystem)
interrupt
62
DSPSS-MSS_STC
GEM MSS_STC done interrupt
63
MSS_SCIA (UART1)
MSS_SCIA (UART1) level 0 interrupt
64
MSS_SCIB (UART2)
MSS_SCIB (UART2) level 0 interrupt
65
MSS_I2C
MSS_I2C interrupt
66
MSS_DMM
MSS_DMM interrupt 34
67
MSS_DMM
MSS_DMM interrupt 35
68
MSS_DMM
MSS_DMM interrupt 36
69
MSS_DMA
MSS_DMA bus error interrupt
70
MSS_DMM/Radar subsystem
MSS_DMM interrupt 30 or Radar
subsystem logical Frame Start
71
Reserved
Reserved
72
MSS_DMM
MSS_DMM interrupt 33
73
MSS_SCIA (UART1)
MSS_SCIA (UART1) level 1 interrupt
74
MSS_SCIB (UART2)
MSS_SCIB (UART2) level 1 interrupt
75
SYSTEM
Software-triggered interrupt 0
76
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 185
16xx Integration
www.ti.com
Table 2-11. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
SYSTEM
Software-triggered interrupt 1
77
SYSTEM
Software-triggered interrupt 2
78
SYSTEM
Software-triggered interrupt 3
79
Reserved
Reserved
80
Reserved
Reserved
81
MSS_DCCA
MSS_DCCA (dual clock compare)
module1-done interrupt
82
MSS_DCCB
MSS_DCCB (dual clock compare)
module2-done interrupt
83
SYSTEM
Software-triggered interrupt 5
84
MSS_PBIST
MSS_PBIST interrupt
85
MSS_DMM/DSS
GEM IRQ-7/MSS_DMM interrupt 32
86
Reserved
Reserved
87
Reserved
Reserved
88
Reserved
Reserved
89
Reserved
Reserved
90
Reserved
Reserved
91
Reserved
Reserved
92
Reserved
Reserved
93
Reserved
Reserved
94
MAILBOX
RADARSS to MSS mailbox interrupt
95
MAILBOX
RADARSS mailbox read complete
interrupt sent from RADARSS to MSS
96
RADARSS
ADC valid fall interrupt
97
MSS_DMM/RADARSS
MSS_DMM interrupt 29/frame start
interrupt/
98
RADARSS
Chirp start interrupt
99
RADARSS
Chirp end Interrupt
100
RADARSS
Frame end Interrupt
101
Reserved
Reserved
102
Reserved
Reserved
103
MSS_ETPWM1
ePWM1 interrupt-1
104
RADARSS-MSS_STC
MSS_STC done Interrupt
105
RadarSS
All RadarSS interrupts combined
106
MSS_ETPWM1
ePWM1 interrupt-2
107
MSS_ETPWM2
ePWM2 interrupt-1
108
MSS_ETPWM2
ePWM2 interrupt-2
109
MSS_ETPWM3
ePWM3 interrupt-1
110
MSS_ETPWM3
ePWM3 interrupt-2
111
DSS_TPTC0 (EDMA TPTC0)
DSS_TPTC0 (EDMA TPTC0) interrupt
112
DSS_TPTC0 (EDMA TPTC0)
DSS_TPTC0 (EDMA TPTC0) error
interrupt
113
DSS_TPTC1 (EDMA TPTC1)
DSS_TPTC1 (EDMA TPTC1) interrupt
114
DSS_TPTC1 (EDMA TPTC1)
DSS_TPTC1 (EDMA TPTC1) error
interrupt
115
DSS_TPCC (EDMA TPCC0)
DSS_TPCC (EDMA TPCC0) interrupt
116
DSS_TPCC (EDMA TPCC0)
DSS_TPCC (EDMA TPCC0) error
interrupt
117
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) interrupt
118
186 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-11. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
Reserved
Reserved
119
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) error
interrupt
120
MSS_DMM
MSS_DMM interrupt 37
121
Reserved
Reserved
122
DSS_ADCBUF/MSS_DMM
Chirp available interrupt/MSS_DMM
interrupt 31
123
MSS_PBIST
MSS_PBIST: Gem MSS_STC done
124
Reserved
Reserved
125
Reserved
Reserved
126
Reserved
Reserved
127
2.3.10 Controller Area Network (MSS_DCAN)
Figure 2-11. Integration Block Diagram for MSS_DCAN Module
From MSS_RCM
Vbusp_clk
Vbusp_rstn
dcan_clk
dcan_mmistart
dcan_mmidone
MSS_DCAN
(CAN)
Configuration Port
VBUS PCR
From BUS Matrix
VBUS_PCR
To MSS_VIM
dcan_lvl_int[1:0]
dcan_IF1
dcan_IF2
dcan_IF3
dma_uerr
dma_serr
dcan_tx
dcan_rx
dcan_rx_oe_n
dcan_tx_oe_n
To MSS_DMA/MSS_DMA2
To MSS_ESM
To/from device pins
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
187
16xx Integration
www.ti.com
2.3.11 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPI)
Figure 2-12. MSS_MIBSPIA Integration
spia_cs_n_in[3:0]
spia_clk_in
spia_mosi_in
spia_miso_in
spia_nrst
spia_vclk
spia_mem_init
spia_mem_init_done
spia_trig_src[1:0]
From
MSS_RCM
spia_cs_n_ie[3:0]
spia_clk_ie
spia_mosi_ie
spia_miso_ie
spia_1sync_to_2sync_en
To MSS_VIM
spia_int_req[1:0]
To MSS_DMA/
MSS_DMA2
spia_dma_req[5:0]
To MSS_ESM
Config
Port From
Bus-matrix
188
16xx/18xx
MSS_MIBSPIA
(MIBSPIA)
spia_sberror
spia_uerror
Register Control
from MSS_RCM
Configuration space
spia_cs_n_out[3:0]
spia_clk_out
spia_mosi_out
spia_miso_out
To/from device pins
spia_cs_n_oe_n[3:0]
spia_clk_oe_n
spia_mosi_oe_n
spia_miso_oe_n
spia_pcr
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Figure 2-13. MSS_MIBSPIB Integration
From
MSS_RCM
spib_nrst
spib_vclk
spib_mem_init
spib_mem_init_done
spib_trig_src[1:0]
spib_cs_n_in[3:0]
spib_clk_in
spib_mosi_in
spib_miso_in
Register Control
from MSS_RCM
Configuration space
spib_1sync_to_2sync_en
To MSS_VIM
spib_int_req[1:0]
MSS_MIBSPIB
(MIBSPIB)
To MSS_DMA
spib_dma_req[5:0]
/MSS_DMA2
To MSS_ESM
spib_cs_n_out[3:0]
spib_clk_out
spib_mosi_out
spib_miso_out
To/from device pins
spib_cs_n_oe_n[3:0]
spib_clk_oe_n
spib_mosi_oe_n
spib_miso_oe_n
spib_sberror
spib_uerror
Config
Port From
Bus-matrix
spib_cs_n_ie[3:0]
spib_clk_ie
spib_mosi_ie
spib_miso_ie
spib_pcr
2.3.12 Quad Serial Peripheral Interface (MSS_QSPI)
The MSS_QSPI module of the 16xx only supports one CS pin, (qspi1_cs).
2.3.13 Enhanced Direct Memory Access (EDMA)
2.3.13.1 EDMA Controller Integration
The 16xx device has two EDMA channel controllers (DSS_TPCC0 and DSS_TPCC1) on the device:
• DSS_TPCC0 (EDMA TPCC0) has two transfer controllers: DSS_TPTC0 (EDMA TPTC0) and
DSS_TPTC1 (EDMA TPTC1)
• DSS_TPCC1 (EDMA TPCC1) has two transfer controllers: DSS_TPTC2 (EDMA TPTC2) and
DSS_TPTC3 (EDMA TPTC3)
NOTE: The 16xx device does not support the region interrupt feature of the EDMA peripheral. Only
the global interrupt feature of the EDMA module is supported.
Table 2-12. DSS_TPCC Configuration
DSS_TPCC0 (EDMA TPCC0)
DSS_TPCC1 (EDMA TPCC1)
Number of MSS_DMA channels
64
64
Number of PaRAM entires
128
256
Number of QDMA channels
8
8
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 189
16xx Integration
www.ti.com
Table 2-12. DSS_TPCC Configuration (continued)
DSS_TPCC0 (EDMA TPCC0)
DSS_TPCC1 (EDMA TPCC1)
Number of event queues
2
2
Memory protection existence
No
No
Channel mapping
No
No
Number of TCs (transfer controllers)
2
2
Table 2-13. DSS_TPTC Configuration
190
DSS_TPTC[0-1]
DSS_TPTC[2-3]
FIFO size
512 bytes
128 bytes
TR pipe depth
2
2
Bus width
16 bytes
16 bytes
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
This section describes the integration of the module in the device, including information about clocks,
resets, and hardware requests.
Figure 3-13 and Figure 3-14 show the EDMA controller integration.
Figure 2-14. EDMA Controller Integration (1 of 2)
Peripherals
Enhanced DMA
Controller
DSS_TPTC1
Master Read
EDMA_TPCC_IRQ_ERR
To C674x-INTC
and
Master CR4F
TPCC_IRQ_Completion
Master Write
PCR 32 bit
CFG_Slave
128 bit
128 bit
Completion
Port
TPTC_GCLK
TPTC_RST
PCR 32bit
SCR 128bit
Transfer request
CFG_Slave
Device
modules
DSS_TPTC0
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Completion
Master Read
128 bit
Master Write
Completion
Port
TPTC_GCLK
TPTC_RST
128 bit
Transfer request
CFG_Slave
DSS_TPCC0
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Global_Completion
DMA requests
from Different
sources
EDMA_REQ[63:0]
DSPSS_CLK
PRCM
DSS_TPTC0
Transfer request
DSS_TPTC1
Master Interface
Reset_n
TPTC_GCLK
TPTC_RST
Completion
Port[6:0]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
191
16xx Integration
www.ti.com
Figure 2-15. EDMA Controller Integration (2 of 2)
Peripherals
Enhanced DMA
Controller
DSS_TPTC3
Master Read
EDMA_TPCC_IRQ_ERR
To C674x-INTC
and
Master CR4F
TPCC_IRQ_Completion
Master Write
PCR 32 bit
CFG_Slave
128 bit
128 bit
Completion
Port
TPTC_GCLK
TPTC_RST
PCR 32bit
SCR 128bit
Transfer request
CFG_Slave
Device
modules
DSS_TPTC2
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Completion
Master Read
128 bit
Master Write
Completion
Port
TPTC_GCLK
TPTC_RST
128 bit
Transfer request
DSS_TPCC1
CFG_Slave
EDMA_TPCC_IRQ_ERR
DSS_TPTC2
Transfer request
DSS_TPTC3
Master Interface
TPCC_IRQ_Global_Completion
DMA requests
from Different
sources
EDMA_REQ[63:0]
DSPSS_CLK
PRCM
Reset_n
Completion
Port[6:0]
TPTC_GCLK
TPTC_RST
2.3.13.2 EDMA Request Map
Table 2-14. EDMA Request Map
Request Number
Hardware Event
DSS_TPCC0 (EDMA TPCC0) DMA
0
DSS_CBUFF_DMA_REQ_0
1
DSS_CBUFF_DMA_REQ_1
2
DSS_CBUFF_DMA_REQ_2
3
DSS_CBUFF_DMA_REQ_3
4
DSS_CBUFF_DMA_REQ_4
5
DSS_CBUFF_DMA_REQ_5
6
DSS_CBUFF_DMA_REQ_6
7
RESERVED
192 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-14. EDMA Request Map (continued)
Request Number
Hardware Event
8
Frame Start/DSS_DMMSWINT9/DSS_DMMSWINT39
9
Chirp Available/DSS_DMMSWINT11/DSS_DMMSWINT43
10
RESERVED
11
RESERVED
12
RESERVED
13
RESERVED
14
RESERVED
15
RESERVED
16
RESERVED
17
RESERVED
18
RESERVED
19
RESERVED
20
RESERVED
21
RESERVED
22
RESERVED
23
RESERVED
24
RESERVED
25
RESERVED
26
RESERVED
27
RESERVED
28
RESERVED
29
RESERVED
30
RESERVED
31
RESERVED
32
RESERVED
33
DSS_MCRC_DMA_REQ_0
34
DSS_MCRC_DMA_REQ_1
35
FRC_EVENT_GEN_0
36
FRC_EVENT_GEN_1
37
FRC_EVENT_GEN_2
38
FRC_EVENT_GEN_3
39
RESERVED
40
LOGICAL_FRAME_START/DSS_DMMSWINT10/DSS_DMMSWINT40
41
ADC_DATA_VALID_FALL/DSS_DMMSWINT12/DSS_DMMSWINT44
42
UART_DMA_REQ_0
43
UART_DMA_REQ_1
44
DMMSW_INT_13
45
DMMSW_INT_14
46
DMMSW_INT_15
47
DMMSW_INT_16
48
DMMSW_INT_17
49
GPIO_0_host_interrupt
50
GPIO_1_host_interrupt
51
GPIO_2_host_interrupt
52
RTI1_DMA_REQ_0
53
RTI1_DMA_REQ_1
54
RTI1_DMA_REQ_2
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 193
16xx Integration
www.ti.com
Table 2-14. EDMA Request Map (continued)
Request Number
Hardware Event
55
RTI1_DMA_REQ_3
56
RTI2_DMA_REQ_0
57
RTI2_DMA_REQ_1
58
RTI2_DMA_REQ_2
59
RTI2_DMA_REQ_3
60
RESERVED
61
RESERVED
62
RESERVED
63
DMMSW_INT_18
DSS_TPCC1 (EDMA TPCC1) MSS_DMA
0
DSS_CBUFF_DMA_REQ_0
1
DSS_CBUFF_DMA_REQ_1
2
DSS_CBUFF_DMA_REQ_2
3
DSS_CBUFF_DMA_REQ_3
4
DSS_CBUFF_DMA_REQ_4
5
DSS_CBUFF_DMA_REQ_5
6
DSS_CBUFF_DMA_REQ_6
7
RESERVED
8
FRAME_START/DSS_DMMSWINT19/DSS_DMMSWINT39
9
CHIRP_AVIALABLE/DSS_DMMSWINT21/DSS_DMMSWINT43
10
RESERVED
11
RESERVED
12
RESERVED
13
RESERVED
14
RESERVED
15
RESERVED
16
RESERVED
17
RESERVED
18
RESERVED
19
RESERVED
20
RESERVED
21
RESERVED
22
RESERVED
23
RESERVED
24
RESERVED
25
RESERVED
26
RESERVED
27
RESERVED
28
RESERVED
29
RESERVED
30
RESERVED
31
RESERVED
32
RESERVED
18
RESERVED
19
RESERVED
20
RESERVED
21
RESERVED
194 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-14. EDMA Request Map (continued)
Request Number
Hardware Event
22
RESERVED
23
RESERVED
24
RESERVED
25
RESERVED
26
RESERVED
27
RESERVED
28
RESERVED
29
RESERVED
30
RESERVED
31
RESERVED
32
RESERVED
33
DSS_MCRC_DMA_REQ_0
34
DSS_MCRC_DMA_REQ_1
35
FRC_EVENT_GEN_0
36
FRC_EVENT_GEN_1
37
FRC_EVENT_GEN_2
38
FRC_EVENT_GEN_3
39
RESERVED
40
LOGICAL_FRAME_START/DSS_DMMSWINT20/DSS_DMMSWINT40
41
ADC_DATA_VALID_FALL/DSS_DMMSWINT22/DSS_DMMSWINT44
42
UART_DMA_REQ_0
43
UART_DMA_REQ_1
44
DMMSW_INT_23
45
DMMSW_INT_24
46
DMMSW_INT_25
47
DMMSW_INT_26
48
DMMSW_INT_27
49
GPIO_0_host_interrupt
50
GPIO_1_host_interrupt
51
GPIO_2_host_interrupt
52
RTI1_DMA_REQ_0
53
RTI1_DMA_REQ_1
54
RTI1_DMA_REQ_2
55
RTI1_DMA_REQ_3
56
RTI2_DMA_REQ_0
57
RTI2_DMA_REQ_1
58
RTI2_DMA_REQ_2
59
RTI2_DMA_REQ_3
60
RESERVED
61
RESERVED
62
RESERVED
63
DMMSW_INT_28
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
195
16xx Integration
www.ti.com
2.3.14 Error Signaling Module (MSS_ESM/DSS_ESM)
The 16xx device has two instances of the Error Signaling Module (MSS_ESM/DSS_ESM), shown in
Figure 3-15.
Figure 2-16. 16xx MSS_ESM/DSS_ESM Integration Diagram
Table 3-15 shows the mapping on the input error inputs to the ESM module from various error sources
available for hardware diagnostics within the device.
Table 2-15. MSS_ESM Mapping
MSS_ESM Group 1
Channel Type
Description
63
ANA_LIMP_MODE
Error Signal
Error signal at device boot-up, if the CLK monitor finds the
REF CLK to be outside the permissible range of frequency
62
MSS_DCCB_ERR
Error Signal
MSS_DCCB frequency comparison error
61
MAILBOX_BSS2MSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_BSS2MSS
60
MAILBOX_BSS2MSS _REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_BSS2MSS
59
MAILBOX_MSS2BSS _FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_MSS2BSS
58
MAILBOX_MSS2BSS _REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_MSS2BSS
57
BSS_CRITICAL_ERR
Error Signal
BSS critical Error Indication.
Mask control to be configured in IRQ_CTL for individual error
signals.
56
Reserved
Reserved
Reserved
196 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-15. MSS_ESM Mapping (continued)
MSS_ESM Group 1
Channel Type
Description
55
CLOCK_SUPPLY_ERR
Error Signal
Clock and Supply Errors from Analog.
Mask control to be configured in IRQ_CTL for individual error
signals
54
Reserved
Reserved
Reserved
53
MAILBOX_DSS2MSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_DSS2MSS
52
MAILBOX_DSS2MSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_DSS2MSS
51
Reserved
Reserved
Reserved
50
Reserved
Reserved
Reserved
49
MSS_MIBSPIB_MEM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_MIBSPIB multi-buffer
(RXRAM/TXRAM)
48
MSS_MCRC_ERR
Error Signal
MSS_MCRC Comparison Error
47
Reserved
Reserved
Reserved
46
Reserved
Reserved
Reserved
45
MSS_MIBSPIB_MEM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_MIBSPIB multibuffer (RXRAM/TXRAM)
44
Reserved
Reserved
Reserved
43
MAILBOX_MSS2DSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_MSS2DSS
42
MAILBOX_MSS2DSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_MSS2DSS
41
DSS_ESM_GP1_ERR
Error Signal
DSS_ESM Low priority Interrupt
40:39
Reserved
Reserved
Reserved
38
DSS_CBUFF_SAFETY_ERR
Error Signal
CHIRP ERROR or CRC ERROR from DSS_CBUFF
37
DSS_ESM_GP2_ERR
Error Signal
DSS_ESM High priority Interrupt
36
DSS_TPTC1_WR_MPU_ERR
Error Signal
DSS_TPTC1 write port MPU error
35
DSS_TPTC1_RD_MPU_ERR
Error Signal
DSS_TPTC1 read port MPU error
34
HVMODE_ERR
Error Signal
Error indication from IO Supply (Supply detector for dualvoltage IOs)
33
MSS_DCAN_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_DCAN Message
RAM (FRAM/SRAM)
32
MSS_TCMA_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for Cortex R4F MSS_TCMA
31
Reserved
Reserved
Reserved
30
MSS_DCCA_ERR
Error Signal
MSS_DCCA frequency comparison error
29
DSS_TPTC0_WR_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
28
MSS_TCMB1_REPAIR_ERR
Alert Signal
Single-bit error/reserved indication for MSS_TCMB1
27
MSS_STC_ERR
Error Signal
MSS_STC Error indication for MSS Cortex R4F
26
MSS_TCMB0_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_TCMB0
25
MSS_MIBSPIA_MEM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_MIBSPIA multibuffer (RXRAM/TXRAM)
24
MSS_DMA2_MEM_PARITY_ERR
Error Signal
Parity Error for MSS_DMA2 memory
23
MSS_DMA2_MPU_ERR
Error Signal
Error indication from MPU of MSS_DMA2
22
FRC_COMPARE_ERR
Error Signal
Lockstep comparison error from Free running Counter (FRC)
in BSS
21
MSS_DCAN_RAM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_DCAN Message Memory
(FRAM/SRAM)
20
MSS_VIM_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_VIM_RAM
19
Reserved
Reserved
Reserved
18
DSS_TPTC0_RD_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
17
MSS_MIBSPIA_MEM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_MIBSPIA (RXRAM/TXRAM)
16
MSS_SECURE_RAM_FATAL_ERR
Error Signal
Multi-bit uncorrectable error indication for
MSS_DTHE/SECURE_RAM
15
MSS_VIM_RAM_FATAL_ERR
Error Signal
Multi-bit uncorrectable error indication for MSS_VIM_RAM
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 197
16xx Integration
www.ti.com
Table 2-15. MSS_ESM Mapping (continued)
MSS_ESM Group 1
Channel Type
Description
14
MSS_SECURE_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for
MSS_DTHE/SECURE_RAM
13
Reserved
Reserved
Reserved
12
MAILBOX_BSS2DSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_BSS2DSS
11
MAILBOX_BSS2DSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_BSS2DSS
10
MAILBOX_DSS2BSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_DSS2BSS
9
DSS_CBUFF_ECC_FATAL_ERR
Error Signal
Multi-bit error indication from DSS_CBUFF FIFO
8
DSS_CBUFF_ECC_REPAIR_ERR
Alert Signal
Single-bit repair indication from DSS_CBUFF FIFO
7
DSS_TPCC_PARITY_ERR
Error Signal
Parity error from DSS_TPCC (EDMA Channel Controller)
6
NU
Reserved
Reserved
5
MAILBOX_DSS2BSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_DSS2BSS
4
MSS_CCCB_ERR
Error Signal
MSS_CCCB(Clock compare core) frequency comparison
error
3
MSS_DMA_MEM_PARITY_ERR
Error Signal
Parity Error for DMA1 memory
2
MSS_DMA_MPU_ERR
Error Signal
Error indication from MPU of MSS _DMA
1
MSS_CCCA_ERR
Error Signal
MSS_CCCA(Clock compare core) frequency comparison
error
0
NERROR_PAD_IN
Error Signal
Nerror from PAD looped in
MSS_ESM Group 2
31:26
NU
25
Reserved
Reserved
Reserved
24
MSS_RTIB_NMI
Error Signal
Watchdog Non-mask able interrupt
23:17
NU
16
MSS_CR4F_LIVELOCK_ERR
Error Signal
Cortex R4F Live lock error
15:9
NU
8
MSS_TCMB1_PARITY_ERR
Error Signal
Parity Error on Control signals for MSS_TCMB1
7
NU
6
MSS_TCMB0_PARITY_ERR
Error Signal
Parity Error on Control signals for MSS_TCMB0
5
NU
4
MSS_TCMA_PARITY_ERR
Error Signal
Parity Error on Control signals for MSS_TCMA
3
NU
2
Reserved
Reserved
Reserved
1:0
NU
Error Signal
Multi-bit error indication for MSS_TCMA
Error Signal
Multi -bit error indication for MSS_TCMB1
Error Signal
Multi-bit error indication for MSS_TCMB0
Error Signal
Efuse Auto-load error
MSS_ESM Group 3
198
31-8
NU
7
MSS_TCMA_FATAL_ERR
6
NU
5
MSS_TCMB1_FATAL_ERR
4
NU
3
MSS_TCMB0_FATAL_ERR
2
NU
1
EFC_AUTOLOAD_ERR
0
NU
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx Integration
www.ti.com
Table 2-16. DSS_ESM Mapping
DSS_ESM Group 1
Channel Type
Description
63:57
Reserved
Reserved
Reserved
56
DSS_DSP_L1P_PARITY_ERR
Error Signal
DSS_DSP_L1P Parity Error
55
MAILBOX_MSS2DSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_MSS2DSS
54
MAILBOX_DSS2MSS_REPAIR_ERR
Error Signal
Single-bit error/repair indication from MAILBOX_DSS2MSS
53
MAILBOX_DSS2MSS_FATAL_ERR
Alert Signal
Multi-bit error indication from MAILBOX_DSS2MSS
52
MAILBOX_MSS2DSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_MSS2DSS
51
MAILBOX_BSS2DSS_REPAIR_ERR
Alert Signal
Single-bit repair indication from MAILBOX_BSS2DSS
50
MAILBOX_DSS2BSS_REPAIR_ERR
Alert Signal
Single-bit repair indication from MAILBOX_DSS2BSS
49
MAILBOX_BSS2DSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_BSS2DSS
48
MAILBOX_DSS2BSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_DSS2BSS
47:32
Reserved
Reserved
Reserved
31
DSS_CFG_MSTID_MPU_ERR
Error Signal
Error from Master ID based MPU on the
DSS_CFG_MSTID_MPU Configuration address space
30:29
Reserved
Reserved
Reserved
28
DSS_DATA_TXFR_RAM_ECC_FATAL Error Signal
_ERR
Multi-bit error indication from DSS_DATA_TXFR_RAM
27
DSS_DATA_TXFR_RAM_ECC
_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from DSS_DATA_TXFR_RAM
26
DSS_STC_ERR
Error Signal
Error from DSS_STC (Self-test Controller)
25
DSS_DSP_L2_UMAP_ECC_REPAIR
_ERR
Alert Signal
Single bit repair indication for DSS_DSP_L2_UMAP0 or
DSS_DSP_L2_UMAP1
24
DSS_HSRAM1_ECC_FATAL_ERR
Error Signal
Multi-bit error indication from DSS_HSRAM1
23
DSS_HSRAM1_ECC_REPAIR_ERR
Alert Signal
Single-bit repair indication from DSS_HSRAM1
22:19
Reserved
Reserved
Reserved
18
DSS_ADCBUF_PONG_FATAL_ERR
Error Signal
Multi-bit error indication from DSS_ADCBUF Pong Memory
17
DSS_ADCBUF_PONG_ECC_REPAIR
_ERR
Alert Signal
Single-bit error/repair indication from DSS_ADCBUF Pong
Memory
16
DSS_ADCBUF_PING_FATAL_ERR
Error Signal
Multi-bit error indication from DSS_ADCBUF Ping Memory
15
DSS_ADCBUF_PING_ECC_REPAIR
_ERR
Alert Signal
Single-bit error/repair indication from DSS_ADCBUF Ping
Memory
14
DSS_TPTC3_WR_MPU_ERR
Error Signal
DSS_TPTC3 write port MPU error
13
DSS_TPTC3_RD_MPU_ERR
Error Signal
DSS_TPTC3 read port MPU error
12
DSS_TPTC2_WR_MPU_ERR
Error Signal
DSS_TPTC2 write port MPU error
11
DSS_TPTC2_RD_MPU_ERR
Error Signal
DSS_TPTC2 read port MPU error
10
DSS_TPCC1_PARITY_ERR
Error Signal
Parity error from DSS_TPCC1 (EDMA Channel Controller)
9
DSS_CBUFF_SAFETY_ERR
Error Signal
CHIRP ERROR or CRC ERROR from DSS_CBUFF
8
DSS_TPTC1_WR_MPU_ERR
Error Signal
DSS_TPTC1 write port MPU error
7
DSS_TPTC1_RD_MPU_ERR
Error Signal
DSS_TPTC1 read port MPU error
6
DSS_TPTC0_WR_MPU_ERR
Error Signal
DSS_TPTC0 write port MPU error
5
DSS_TPTC0_RD_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
4
DSS_CBUFF_ECC_FATAL_ERR
Error Signal
Multi-bit error indication from DSS_CBUFF FIFO
3
DSS_CBUFF_ECC_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from DSS_CBUFF FIFO
2
DSS_TPCC_PARITY_ERR
Error Signal
Parity error from DSS_TPCC (EDMA Channel Controller)
1
DSS_L3RAM_ECC_FATAL_ERR
Error Signal
Multi-bit error indication from DSS_L3RAM Memory
0
DSS_L3RAM_ECC_REPAIR_ERR
Alert Signal
Single-bit repair indication from DSS_L3RAM Memory
DSS_ESM Group 2
31:6
Reserved
Reserved
Reserved
5
DSS_DSP_L2_UMAP_ECC_FATAL
_ERR
Error Signal
Multi-bit error indication for DSS_DSP_L2_UMAP0 or
DSS_DSP_L2_UMAP1
4
DSP_PBIST_ERR
Error Signal
DSP_PBIST (Memory Test) Fail Error
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 199
16xx Integration
www.ti.com
Table 2-16. DSS_ESM Mapping (continued)
DSS_ESM Group 1
Channel Type
Description
3
DSS_STC_ERR
Error Signal
Error from DSS_STC (Self-test Controller)
2
DSS_RTI_NMI
Error Signal
NMI from DSS_RTI (Watchdog)
1
DSS_DSP_L2_UMAP1_PARITY_ERR
Error Signal
Error from byte level parity comparison logic for
DSS_DSP_L2_UMAP1
0
DSS_DSP_L2_UMAP0_PARITY_ERR
Error Signal
Error from byte level parity comparison logic for
DSS_DSP_L2_UMAP0
2.3.15 High-Speed Interface (HSI)
Table 3-17 lists the high-speed interfaces available for the 16xx device.
Table 2-17. 16xx High-Speed Interfaces
CSI2
N/A
LVDS
2 lanes
2.3.16 Handshake RAM (DSS_HSRAM1)
The 16xx device has 32KB memory for HSRAM in the DSP subsystem.
2.4
18xx Introduction
2.4.1 18xx Overview
The 18xx is highly integrated single-chip RADAR device in TI’s 45-nm low-power RFCMOS technology, a
FCBGA 0.65-mm pitch automotive-grade package.
2.4.1.1 Features
• Frequency-Modulated Continuous Wave Radio Frequency Transceiver With 76-81-GHz Band
• Supports Three Transmitter Chains and Four Receiver Chains
• Chirp Profiles With Programmable Period and Slope
• 40-MHz, 50-MHz, 80-MHz, and 100-MHz XTAL/OSC Reference Input Clock
• 12, 14, and 16-bit Real/Complex ADC With Variable Baseband ADC Sampling Rates up to 18.75 MHz
at 12-bits Complex
• Cortex R4F at 200-MHz Application Processor for Control Functionality and Safety-Critical Algorithms
• C674x DSP at up to 600 MHz for RADAR Data Processing
• Cortex R4F– Radio Processor at 200 MHz for Continuous Monitoring and Calibration of Analog/RF
Functionality
• On-Chip Multicore Debug Support
• Customer-Programmable Efuse Support
• Up to 1024KB of L3 Shared Memory Support
• High-Performance Data Transfer With Multiple DMA and EDMA-TPCC Engines
• CAN Support for ECU Interface
• QSPI Serial Flash Support
• MIBSPI, SPI, I2C, and UART Serial Interfaces Support
• Hardware in Loop (HIL) Support
• Two-Lane Serial LVDS Interface Support
• AES, SHA, PKA, and TRNG Engines for Security
200
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Introduction
www.ti.com
•
•
3 EPWM (Three Enhanced Pulse Width Modulator)
Hardware Accelerator for FFT, Filtering, and CFAR Processing
2.4.2 18xx Description
2.4.2.1
Block Diagram
Figure 2-17 shows the block diagram of the 18xx device.
Figure 2-17. 18xx Block Diagram
RADAR Subsystem
Radio Processor
FMCW Transceiver 57-64 GHz
Three Transmitters,
Four Receivers
Baseband
ADC
GPADC
Ramp Generator
B
U
S
DFE
M
A
T
R
I
X
Voltage Monitor
OSC
PLL
DSP Subsystem
Temp
Sensor
C674x DSP
Core
@
600MHz
@ 200MHz
(TI Programmed)
Prog RAM &
ROM
Analog/RF
Calibration
2 x EDMA
L1P-32KB
ARM Cortex R4F
L1D-32KB
EMC
UMC
Data
RAM
256 KB of L2 RAM
ESM
32KB ADC data
Buffer
32KB
HS-RAM
B
U
S
2xRTI
SCI
M
A
T
R
I
X
2 lane
Serial LVDS Interface
Up to 1024KB
shared L3 memory
Master Subsystem
BUS Matrix
Safety
Cortex-R4F Subsystem
ARM Cortex R4F
VIM
512KB Prog
RAM with
ECC
LBIST/STC
2xDCC
PBIST
ESM
CRC
2xCCC
192KB Data
RAM with
ECC
Serial Interfaces and Connectivity
3xePWM
2xDMA
@ 200MHz
ROM
128KB
System Peripherals
2xRTI
GIO
DCAN
2xMIBSPI
QSPI
2xSCI
I2C
Mailbox
Security
2xDMM
AES
PKA
SHA
TRNG
PRCM
JTAG
S/W Buffer
Table 2-18. 18xx Acronyms
ADC
Analog-to-Digital Convertor
AES
Advanced Encryption Standard
CRC
Cyclic Redundancy Check
MCAN
Controller Area Network
DCC
Digital Clock Comparator
DFE
Digital Front End
DMA
Direct Memory Access
DMM
Data Modification Module
ECC
Error Correcting Code
EDMA
Enhanced Direct Memory Access
EMC
Extended Memory Controller
ePWM
Enhanced Pulse Width Modulator
ESM
Error Signaling Module
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 201
18xx Introduction
www.ti.com
Table 2-18. 18xx Acronyms (continued)
2.4.2.2
GIO
General Input/Output
GPADC
General Purpose Analog-to-Digital Convertor
HS-RAM
Handshake RAM
I2C
Inter-Integrated Circuit
JTAG
Joint Test Action Group
L1D
Level 1 Data Memory Controller
L1P
Level 1 Program Memory Controller
L2
Level 2
L3
Level 3
LBIST
Logic Built-In Self-Test
LVDS
Low Voltage Differential Signaling
MIBSPI
Multi-Buffered Serial Peripheral Interface Module
OSC
Oscillator
PBIST
Programmable Built-In Self-Test
PKA
Public Key Algorithm
PLL
Phase Locked Loops
PRCM
Power, Reset, Clock Management
QSPI
Quad Serial Peripheral Interface
RTI
Real Time Interrupt
S/W Buffer
Software Buffer
SCI
Serial Communication Interface
SHA
Secure Hash Algorithm
STC
Self-Test Controller
TRNG
True Random Number Generator
UMC
Unified Memory Controller
VIM
Vectored Interrupt Manager
Radar Subsystem
The RADAR subsystem is responsible for the RF and analog functionality of the device. The subsystem
incorporates a built-in self-test processor for the continuous motoring and calibration of the analog and RF
modules. The subsystem consists of:
• FMCW transceiver
– Integrated PLL, transmitter, receiver, baseband, and A2D
– 76-81-GHz coverage with 4-GHz available bandwidth
– Four receive channels
– Three transmit channels
– Ultra-accurate chirp engine based on fractional-n PLL
– 12,14, or 16-bit complex analog to digital converter
• Radio processor for built-in calibration and self-test
– ARM Cortex R4F-based radio control system
– Built-in firmware (ROM)
– Self-calibrating system across frequency and temperature
This subsystem is TI-programmed with an API interface to the on-chip Cortex-R4F application processor.
2.4.2.3
DSP Subsystem
The DSP subsystem consists of the following:
202
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Introduction
www.ti.com
•
•
•
•
•
•
•
•
•
•
•
2.4.2.4
The TMS320C674x™ VLIW DSP core from the generation, and the TMS320C64x+™ DSP architecture
for RADAR data processing. These are enhancements from TI’s C64x+™ DSP architecture, with
additional features.
32KB L1D and 32KB of L1P cache/RAM
256KB of L2 RAM
On-chip L3 shared memory of 1024KB, with 512KB dedicated to DSP and 512 KB of memory shared
between the DSP and master subsystems.
32KB of memory for storing ADC samples from the RADAR subsystem
Multiple Enhanced Direct Memory Access (EDMA) engines – TPCCs for high-performance data
transfers
2-lane LVDS interface with support of up to 900 Mbps per lane for the RADAR raw ADC data transfer
One watchdog timer and a general purpose timer implemented by the real time interrupt (RTI) modules
One serial communication Interface (SCI) module implementing standard universal asynchronous
receiver-transmitter (UART).
Emulation capabilities
Little Endian
Master Subsystem
The master subsystem consists of the following features:
• Cortex-R4F core supporting ARMv7-R, VFPv3-D16, and ARMv7 debug architecture
• Tightly-coupled memories
– 128 KB of ROM
– 512KB of program RAM with ECC
– 192KB of data RAM with ECC
• Hardware auto-initialization of the memories
• Vectored interrupt manager for prioritizing and controlling the interrupts for different sources
2.4.2.4.1 Serial Interfaces
• One MCAN controller supporting bit rates of up to 10 Mbit/s. compliant to the controller area network
(CAN) 2.0 part A, B protocol specification and ISO 11898-1, and CAN FD® V1.0 specification with up
to 64 data bytes support.
• One I2C controller module with rates up to 400 kbps
• Two MIBSPI modules
• Two serial communication interface (SCI) modules implementing standard universal asynchronous
receiver-transmitter (UART) with baud rates of up to 3.125 Mbps
• One quad SPI module support with maximum rate of 40 MHz
2.4.2.4.2
•
•
•
•
•
•
•
System Peripherals
Multiple general-purpose input/output (GPIO) modules
Direct memory access modules for high-performance data transfers
One watchdog timer and a general purpose timer implemented by the real-time interrupt (RTI) modules
Mailbox module for interprocessor communication
Two data modification modules (DMM) with up to 65 Mbit/s data rate per pin
Three enhanced pulse width (ePWM) modulator modules
System reset and control module, which contains registers for the following functions:
– Status
– Efuse logic
– I/O configuration
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
203
18xx Memory Map
www.ti.com
– PAD configuration
– System boot decoding logic
2.4.2.5
Functional Safety Deliverables
See the Device Safety Manual for supported features.
2.4.2.6
On-Chip Debug Support
The on-chip debug support has the following features:
• Multiprocessor debugging to let users control multiple cores embedded in the device, such as:
– Global starting and stopping of individual or multiple processors
– Each processor can generate triggers to alter the execution flow of other processors
– Interconnection of multiple devices
– Channel triggering
• The following device cores can be debugged through Code Composer Studio (CCS):
– Cortex-R4F
– DSP
• Target debugging using IEEE1149.1 (JTAG®) port
• The debug subsystem includes:
– IEEE1149.7 adapter
– Generic TAP for emulation and test control (ICEPick-D™)
– Debug access port (DAP)
– Embedded trace macro (ETM)
– Trace port interface Unit (TPIU)
– Embedded trace buffer (ETB)
2.5
18xx Memory Map
2.5.1 System Interconnect
The device implements a system interconnect based on TI’s common bus architecture, comprising of
VBUSM and VBUSP protocols. Figure 2-18 shows the interconnect diagram.
204
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Memory Map
www.ti.com
Figure 2-18. System Interconnect
PCR-1 32-bit
MSS_DEBUGSS
MSS_DMM1
RADAR
Subsystem
MSS_DMM2
MSS_ETPWM1
MSS_MBOX4GEM
GEM_MBOX4MSS
MSS_MBOX4BSS
BSS_MBOX4MSS
MSS_DMA
MSS_DMA2
SCR-64bit
MSS_ETPWM2
MSS_ETPWM3
PCR-1 Bridge
Primary SCR(64bit)
PCR-2 Bridge
GEM_MBOX4BSS
BSS_MBOX4GEM
MSS_SW_BUFFER
MSS_CRC
MSS_QSPI
Master
Cortex-R4F
Subsystem
Bridge
C674x DSP
Subsystem
Bridge
DSS_ADCBUF
DSS_L3RAM
DSS_HSRAM1
PRCM
MSS_ESM
MSS_VIM
MSS_IOMUX
MSS_RTIA
MSS_PBIST
MSS_RTIB
MSS_DCAN
MSS_I2C
PCR-2 32-bit
eFuse logic
SCR(128 bit)
MSS_SCIA
MSS_SCIB
Bridge
DSS_TPCC
DSS_TPTC0
DSS_TPTC2
DSS_TPTC1
DSS_TPTC3
Bridge
PCR
Bridge
DSS_TPCC1
DSS_CBUFF
MSS_DCCA
MSS_MIBSPIA
MSS_DCCB
MSS_MIBSPIB
MSS_MCAN
MSS_GIO
DSS_CRC
EDMA
PCR-3 32-bit
BUS Master
DSS_RTI
DSS_RTI2
DSS_REG
DSS_REG2
DSS_SCI
DSS_ESM
Bus-Slave
The system interconnect is designed for the high-performance needs of the system. Its divided into three
interconnect systems local to each of the three subsystems: the RADAR subsystem, DSP subsystem, and
master subsystem. The interconnection of all these subsystems is shown in Figure 3-2.
In the master subsystem, the primary VBUSM SCR is responsible for managing the arbitration priority
between accesses from multiple masters to each of the slaves. The arbitration priority is always roundrobin.
The master subsystem has PCR interconnect that manages the accesses to the peripheral registers and
peripheral memories, and provides a global reset for all peripherals. It also supports the capability to
selectively enable or disable the clock for each peripheral individually. The PCR also manages the
accesses to the system module registers required to configure the device clocks, interrupts, and so forth.
The system module registers include status flags for indicating exception conditions – resets, aborts,
errors, and interrupts.
Similarly, the 128-bit VBUSM SCR in the DSP subsystem manages the arbitration between accesses from
the multiple masters to the slaves. The DSP subsystem has a 32-bit VBUSP PCR for the system and nonsystem peripherals.
2.5.2 Master Subsystem Cortex-R4F Memory Map
Table 3-2 shows the master subsystem, Cortex-R4F memory map.
Table 2-19. Master Subsystem, Cortex-R4F Memory Map
ModuleName
MSS_TCMA_ROM
Frame Address (Hex)
Start
End
0x0000_0000
0x0001_7FFF
Size Used
Description
128KiB
MSS_TCMA_ROM (TCMA)
Program ROM (refer to
ROM Eclipsing section)
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 205
18xx Memory Map
www.ti.com
Table 2-19. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size Used
Description
Start
End
Reserved
0x0001_8000
0x001F_FFFF
MSS_TCMA_RAM
0x0020_0000
0x07FF_FFFF
512KiB
MSS_TCMA_RAM (TCMA)
size varies based on
device and DSS_L3 (L3)
sharing options configured
(refer to ROM Eclipsing
section)
MSS_TCMB
0x0800_0000
0x0C1F_FFFF
192KiB
MSS_TCMB (TCMB) Data
RAM
MSS_SW_BUFFER
0x0C20_0000
0x0C20_1FFF
8KiB
MSS_SW_BUFFER
(SWBUFF) Scratchpad
memory
Reserved
0x0C20_2000
0x4FFF_FFFF
DSS_TPTC0
0x5000_0000
0x5000_03FF
792B
DSS_TPTC0 (EDMA
TPTC0) module
configuration space
DSS_REG
0x5000_0400
0x5000_07FF
864B
DSS_REG (DSPSS)
control module registers
DSS_TPTC1
0x5000_0800
0x5000_0BFF
792B
DSS_TPTC1 (EDMA
TPTC1) module
configuration space
DSS_REG2
0x5000_0C00
0x5000_FFFF
676B
DSS_REG2 (DSPSS)
control module registers
DSS_TPCC
0x5001_0000
0x5001_FFFF
16KiB
DSS_TPCC (EDMA
TPCC0) module
configuration space
DSS_RTI
0x5002_0000
0x5002_FFFF
192B
DSS_RTI (WDT/RTI1)
configuration space
DSS_SCI
0x5003_0000
0x5003_FFFF
148B
DSS_SCI (SCI) memory
space
DSS_STC
0x5004_0000
0x5004_FFFF
284B
DSS_STC (STC) module
configuration space (refer
to Safety chapter)
Reserved
0x5005_0000
0x5006_FFFF
DSS_CBUFF
0x5007_0000
0x5007_FFFF
564B
DSS_CBUFF (CBUFF)
module configuration
registers (refer to HSI
chapter)
DSS_HW_ACC_PARAM
0x5008_0000
0x5008_07FF
512B
DSS_HW_ACC_PARAM
(HWA) FFT accelerator
PARAM memory
DSS_HW_ACC_STATIC
0x5008_0800
0x5008_0FFF
616B
DSS_HW_ACC_STATIC
(HWA) FFT accelerator
configuration registers
DSS_HW_ACC_WIN
0x5008_1000
0x5008_FFFF
4KiB
DSS_HW_ACC_WIN
(HWA) FFT accelerator
Window registers
DSS_TPTC2
0x5009_0000
0x5009_03FF
792B
DSS_TPTC2 (EDMA
TPTC2) module
configuration space
DSS_TPTC3
0x5009_0400
0x5009_FFFF
792B
DSS_TPTC3 (EDMA
TPTC3) module
configuration space
DSS_TPCC1
0x500A_0000
0x500A_FFFF
16KiB
DSS_TPCC1 (EDMA
TPCC1) module
configuration space
Reserved
0x500B_0000
0x500C_FFFF
206 16xx/18xx
Reserved (refer to ROM
Eclipsing section)
Reserved
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Memory Map
www.ti.com
Table 2-19. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size Used
Description
0x500E_FFFF
1KiB
DSS_ESM (ESM) module
configuration registers
(refer to Safety chapter)
0x500F_0000
0x500F_FFFF
192B
DSS_RTI2 (RTI2) module
configuration registers
Reserved
0x5010_0000
0x50FF_FFFF
DSS_L3RAM
0x5100_0000
0x51FF_FFFF
2MB
DSS_L3RAM (L3) shared
memory space
DSS_ADCBUF
0x5200_0000
0x5201_FFFF
32KiB
DSS_ADCBUF (ADC)
buffer memory space
DSS_CBUFF_FIFO
0x5202_0000
0x5202_7FFF
16KiB
DSS_CBUFF_FIFO
(CBUFF) FIFO space (refer
to HSI chapter)
Reserved
0x5202_8000
0x5202_FFFF
DSS_FFT_ACC_DMA1
0x5203_0000
0x5203_7FFF
32KiB
DSS_FFT_ACC_DMA1
(HWA DMA) FFT
accelerator Memory -1
space
DSS_FFT_ACC_DMA2
0x5203_8000
0x5206_FFFF
32KiB
DSS_FFT_ACC_DMA2
(HWA DMA) FFT
accelerator Memory -2
space
Reserved
0x5207_0000
0x5207_FFFF
DSS_HSRAM1
0x5208_0000
0x5208_FFFF
32KiB
DSS_HSRAM1 (HSRAM)
Handshake memory space
Reserved
0x5209_0000
0x577D_FFFF
DSS_DSP_L2_UMAP1
0x577E_0000
0x577F_FFFF
128KiB
DSS_DSP_L2_UMAP1
(L2) RAM space
DSS_DSP_L2_UMAP0
0x5780_0000
0x57DF_FFFF
128KiB
DSS_DSP_L2_UMAP0
(L2) RAM space
DSS_DSP_L1P
0x57E0_0000
0x57EF_FFFF
32KiB
DSS_DSP_L1P (L1)
program memory space
DSS_DSP_L1D
0x57F0_0000
0xBFFF_FFFF
32KiB
DSS_DSP_L1D (L1) data
memory space
EXT_FLASH
0xC000_0000
0xC07F_FFFF
8MB
MSS_QSPI (QSPI) flash
memory space
MSS_QSPI
0xC080_0000
0xF060_0FFF
116B
MSS_QSPI (QSPI) module
configuration registers
MSS_MBOX4BSS
0xF060_1000
0xF060_1FFF
2KiB
MSS_MBOX4BSS mailbox
memory space
BSS_MBOX4MSS
0xF060_2000
0xF060_3FFF
2KiB
BSS_MBOX4MSS mailbox
memory space
GEM_MBOX4MSS
0xF060_4000
0xF060_4FFF
2KiB
GEM_MBOX4MSS mailbox
memory space
MSS_MBOX4GEM
0xF060_5000
0xF060_5FFF
2KiB
MSS_MBOX4GEM mailbox
memory space
GEM_MBOX4BSS
0xF060_6000
0xF060_6FFF
2KiB
GEM_MBOX4BSS mailbox
memory space
BSS_MBOX4GEM
0xF060_7000
0xF060_7FFF
2KiB
BSS_MBOX4GEM mailbox
memory space
BSS_MBOX4MSS_REG
0xF060_8000
0xF060_80FF
188B
BSS_MBOX4MSS_REG
mailbox Configuration
registers
BSS_MBOX4GEM_REG
0xF060_8100
0xF060_81FF
188B
BSS_MBOX4GEM_REG
mailbox Configuration
registers
Start
End
DSS_ESM
0x500D_0000
DSS_RTI2
Reserved
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 207
18xx Memory Map
www.ti.com
Table 2-19. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size Used
Description
0xF060_82FF
188B
GEM_MBOX4BSS_REG
mailbox Configuration
registers
0xF060_8300
0xF060_83FF
188B
MSS_MBOX4GEM_REG
mailbox Configuration
registers
GEM_MBOX4MSS_REG
0xF060_8400
0xF060_85FF
188B
GEM_MBOX4MSS_REG
mailbox Configuration
registers
MSS_MBOX4BSS_REG
0xF060_8600
0xFCF7_8BFF
188B
MSS_MBOX4BSS_REG
mailbox Configuration
registers
MSS_ETPWM1
0xFCF7_8C00
0xFCF7_8CFF
116B
MSS_ETPWM1 (ePWM1)
configuration registers
MSS_ETPWM2
0xFCF7_8D00
0xFCF7_8DFF
116B
MSS_ETPWM2 (ePWM2)
configuration registers
MSS_ETPWM3
0xFCF7_8E00
0xFCF8_0FFF
116B
MSS_ETPWM3 (ePWM3)
configuration registers
MSS_DMA2_RAM
0xFCF8_1000
0xFCFF_0FFF
4KiB
MSS_DMA2_RAM (DMA2)
RAM memory space
MSS_PCR2
0xFCFF_1000
0xFCFF_F5FF
1KiB
MSS_PCR2 (PCR_2)
interconnect configuration
port
MSS_DMM2
0xFCFF_F600
0xFCFF_F6FF
472B
MSS_DMM2 (DMM2)
module configuration
registers
MSS_DMM
0xFCFF_F700
0xFCFF_F7FF
472B
MSS_DMM (DMM1)
module configuration
registers
MSS_DMA2_REG
0xFCFF_F800
0xFCFF_FFFF
1KiB
MSS_DMA2_REG (DMA2)
module configuration
registers
MSS_DTHE
0xFD00_0000
0xFD00_3FFF
3KiB
MSS_DTHE (Crypto)
module configuration
registers
Reserved
0xFD00_4000
0xFDFF_FFFF
MSS_MCRC
0xFE00_0000
0xFF0B_FFFF
16KiB
MSS_MCRC (CRC)
module configuration
registers
MSS_MIBSPIB_TXRAM
0xFF0C_0000
0xFF0C_01FF
0.5KiB
MSS_MIBSPIB_TXRAM
(MIBSPIB) TX RAM
memory space
MSS_MIBSPIB_RXRAM
0xFF0C_0200
0xFF0D_FFFF
0.5KiB
MSS_MIBSPIB_RXRAM
(MIBSPIB) RX RAM
memory space
MSS_MIBSPIA_TXRAM
0xFF0E_0000
0xFF0E_01FF
0.5KiB
MSS_MIBSPIA_TXRAM
(MIBSPIA ) TX RAM
memory space
MSS_MIBSPIA_RXRAM
0xFF0E_0200
0xFF1D_FFFF
0.5KiB
MSS_MIBSPIA_RXRAM
(MIBSPIA ) RX RAM
memory space
Reserved
0xFF1E_0000
0xFF4F_FFFF
MSS_MCAN_MSGMEM
0xFF50_0000
0xFF9F_FFFF
68KiB
MSS_MCAN_MSGMEM
(MCAN) RAM memory
space
MSS_DEBUGSS
0xFFA0_0000
0xFFF7_7FFF
244KiB
MSS_DEBUGSS (Debug
subsystem) memory space
and registers
Start
End
GEM_MBOX4BSS_REG
0xF060_8200
MSS_MBOX4GEM_REG
208 16xx/18xx
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Memory Map
www.ti.com
Table 2-19. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
Frame Address (Hex)
Size Used
Description
0xFFF7_9FFF
1KiB
MSS_PCR (PCR_1)
interconnect configuration
port
0xFFF7_A000
0xFFF7_BBFF
452B
MSS_MCAN_ECC (MCAN)
module registers
MSS_GIO
0xFFF7_BC00
0xFFF7_C7FF
180B
MSS_GIO (GIO) module
configuration registers
MSS_MCAN_CFG
0xFFF7_C800
0xFFF7_D3FF
768B
MSS_MCAN_CFG (MCAN)
module configuration
registers
MSS_I2C
0xFFF7_D400
0xFFF7_DBFF
112B
MSS_I2C (I2C) module
configuration registers
Reserved
0xFFF7_DC00
0xFFF7_E4FF
MSS_SCIA
0xFFF7_E500
0xFFF7_E6FF
148B
MSS_SCIA (SCIA/UART)
module configuration
registers
MSS_SCIB
0xFFF7_E700
0xFFF7_F3FF
148B
MSS_SCIB (SCIB/UART)
module configuration
registers
MSS_MIBSPIA
0xFFF7_F400
0xFFF7_F5FF
512B
MSS_MIBSPIA (MIBSPIA)
module configuration
registers
MSS_MIBSPIB
0xFFF7_F600
0xFFF7_FFFF
512B
MSS_MIBSPIB (MIBSPIB)
module configuration
registers
MSS_DMA_RAM
0xFFF8_0000
0xFFF8_1FFF
4KiB
MSS_DMA_RAM (DMA1)
RAM memory space
MSS_VIM_MEM
0xFFF8_2000
0xFFF8_BFFF
2KB
MSS_VIM_MEM (VIM)
RAM memory space
Reserved
0xFFF8_C000
0xFFFF_E0FF
MSS_TOPRCM
0xFFFF_E100
0xFFFF_E3FF
756B
MSS_TOPRCM TOP Level
Reset, Clock management
registers
MSS_PBIST
0xFFFF_E400
0xFFFF_E5FF
464B
MSS_PBIST (PBIST)
module configuration
registers (refer to Safety
chapter)
MSS_STC
0xFFFF_E600
0xFFFF_E9FF
284B
MSS_STC (STC) module
configuration registers
(refer to Safety chapter)
MSS_IOMUX
0xFFFF_EA00
0xFFFF_EBFF
512B
MSS_IOMUX (IOMUX)
module registers
MSS_DCCA
0xFFFF_EC00
0xFFFF_EDFF
44B
MSS_DCCA (DCCA)
module configuration
registers
MSS_RTIB
0xFFFF_EE00
0xFFFF_EFFF
192B
MSS_RTIB (WDT/RTIB)
module configuration
registers
MSS_DMA_REG
0xFFFF_F000
0xFFFF_F3FF
1KiB
MSS_DMA_REG (DMA1)
module configuration
registers
MSS_DCCB
0xFFFF_F400
0xFFFF_F4FF
44B
MSS_DCCB (DCCB)
module configuration
registers
MSS_ESM
0xFFFF_F500
0xFFFF_F5FF
156B
MSS_ESM (ESM) module
configuration registers
(refer to Safety chapter)
Start
End
MSS_PCR
0xFFF7_8000
MSS_MCAN_ECC
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 209
18xx Memory Map
www.ti.com
Table 2-19. Master Subsystem, Cortex-R4F Memory Map (continued)
ModuleName
2.5.2.1
Frame Address (Hex)
Size Used
Description
Start
End
Reserved
0xFFFF_F600
0xFFFF_F7FF
MSS_GPCFG_REG
0xFFFF_F800
0xFFFF_FBFF
352B
MSS_GPCFG_REG
(GPCFG) General purpose
control registers
MSS_RTIA
0xFFFF_FC00
0xFFFF_FCFF
192B
MSS_RTIA (RTIA) module
configuration registers
MSS_VIM
0xFFFF_FD00
0xFFFF_FEFF
512B
MSS_VIM (VIM) module
configuration registers
MSS_RCM
0xFFFF_FF00
0xFFFF_FFFF
256B
MSS_RCM (RCM) Reset,
Clock management
registers
Reserved
Radar Subsystem Interface
The RADAR subsystem is accessible through a set of TI-implemented high-level API calls by the
application running on the master CR4F. For more information on the 18xx RADAR subsystem interface,
see the 18xx Interface control document.
2.5.3 DSP Subsystem Memory Map
Table 3-3 shows the DSP C674x memory map.
Table 2-20. DSP C674x Memory Map
Module Name
Frame Address (Hex)
Size
Used
Description
0x007F_FFFF
128KiB
DSP_L2_UMAP1 (L2) RAM space
0x0080_0000
0x0081_FFFF
128KiB
DSP_L2_UMAP0 (L2) RAM space
0x00E0_0000
0x00E0_7FFF
32KiB
DSP_L1P (L1) program memory space
DSP_L1D
0x00F0_0000
0x00F0_7FFF
32KiB
DSP_L1D (L1) data memory space
DSS_TPTC0
0x0200_0000
0x0200_03FF
1KiB
DSS_TPTC0 (EDMA TPTC0) module configuration
space
DSS_REG
0x0200_0400
0x0200_07FF
864B
DSS_REG (DSPSS) control module registers
DSS_TPTC1
0x0200_0800
0x0200_0BFF
1KiB
DSS_TPTC1 (EDMA TPTC1) module configuration
space
DSS_REG2
0x0200_0C00
0x0200_0FFF
624B
DSS_REG2 (DSPSS) control module registers
DSS_TPCC
0x0201_0000
0x0201_3FFF
16KiB
DSS_TPCC (EDMA TPCC0) module configuration
space
DSS_RTI
0x0202_0000
0x0202_00FF
192B
DSS_RTI (WDT/RTI1) module configuration
registers
DSS_SCI
0x0203_0000
0x0203_00FF
148B
DSS_SCI (SCI/UART) module Configuration
registers
DSS_CBUFF
0x0207_0000
0x0207_03FF
564B
DSS_CBUFF (CBUFF) module Configuration
registers (refer to HSI chapter)
DSS_HW_ACC_PARAM
0x0208_0000
0x0208_07FF
512B
DSS_HW_ACC_PARAM (HWA) FFT accelerator
PARAM memory
DSS_HW_ACC_STATIC
0x0208_0800
0x0208_0FFF
616B
DSS_HW_ACC_STATIC (HWA) FFT accelerator
configuration registers
DSS_HW_ACC_WIN
0x0208_1000
0x0208_FFFF
4KiB
DSS_HW_ACC_WIN (HWA) FFT accelerator
Window registers
DSS_TPTC2
0x0209_0000
0x0209_03FF
1KiB
DSS_TPTC2 (EDMA TPTC2) module configuration
space
DSS_TPTC3
0x0209_0400
0x0209_07FF
1KiB
DSS_TPTC3 (EDMA TPTC3) module configuration
space
Start
End
DSP_L2_UMAP1
0x007E_0000
DSP_L2_UMAP0
DSP_L1P
210 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Memory Map
www.ti.com
Table 2-20. DSP C674x Memory Map (continued)
Module Name
Frame Address (Hex)
Size
Used
Description
16KiB
DSS_TPCC1 (EDMA TPCC1) module configuration
space
Start
End
DSS_TPCC1
0x020A_0000
0x020A_3FFF
Reserved
0x020B_0000
0x020C_FFFF
DSS_ESM
0x020D_0000
0x020E_FFFF
92B
DSS_ESM (ESM) module Configuration registers
(refer to Safety chapter)
DSS_RTI2
0x020F_0000
0x020F_00FF
192B
DSS_RTI2 (RTI2) module configuration registers
DSS_FFT_ACC_DMA1
0x2103_0000
0x2103_7FFF
32KiB
DSS_FFT_ACC_DMA1 (HWA DMA) FFT
accelerator Memory -1 space
DSS_FFT_ACC_DMA2
0x2103_8000
0x2103_FFFF
32KiB
DSS_FFT_ACC_DMA2 (HWA DMA) FFT
accelerator Memory -2 space
Reserved
0x0210_0000
0x0460_7FFF
BSS_MBOX4MSS_REG
0x0460_8000
0x0460_80FF
188B
BSS_MBOX4MSS_REG mailbox Configuration
registers
BSS_MBOX4GEM_REG
0x0460_8100
0x0460_81FF
188B
BSS_MBOX4GEM_REG mailbox Configuration
registers
GEM_MBOX4BSS_REG
0x0460_8200
0x0460_82FF
188B
GEM_MBOX4BSS_REG mailbox Configuration
registers
MSS_MBOX4GEM_REG
0x0460_8300
0x0460_83FF
188B
MSS_MBOX4GEM_REG mailbox Configuration
registers
GEM_MBOX4MSS_REG
0x0460_8400
0x0460_84FF
188B
GEM_MBOX4MSS_REG mailbox Configuration
registers
MSS_MBOX4BSS_REG
0x0460_8600
0x0460_86FF
188B
MSS_MBOX4BSS_REG mailbox Configuration
registers
Reserved
0x050C_0000
0x1FFF_FFFF
DSS_L3RAM
0x2000_0000
0x201F_FFFF
2MB
DSS_L3RAM (L3) shared memory space
DSS_ADCBUF
0x2100_0000
0x2100_7FFC
32KiB
DSS_ADCBUF (ADC buffer) memory space
DSS_CBUFF_FIFO
0x2102_0000
0x2102_3FFC
16KiB
DSS_CBUFF_FIFO (Common buffer) FIFO space
(Refer to HSI chapter)
Reserved
0x2102_8000
0x2107_FFFF
DSS_HSRAM1
0x2108_0000
0x2108_7FFC
Reserved
0x2109_0000
0x21FF_FFFF
DSS_MCRC
0x2200_0000
0x2200_03FF
Reserved
0x2500_0000
0x5060_0FFF
MSS_MBOX4BSS
0x5060_1000
0x5060_17FF
2KiB
MSS_MBOX4BSS mailbox memory space
BSS_MBOX4MSS
0x5060_2000
0x5060_27FF
2KiB
BSS_MBOX4MSS mailbox memory space
GEM_MBOX4MSS
0x5060_4000
0x5060_47FF
2KiB
GEM_MBOX4MSS mailbox memory space
MSS_MBOX4GEM
0x5060_5000
0x5060_57FF
2KiB
MSS_MBOX4GEM mailbox memory space
GEM_MBOX4BSS
0x5060_6000
0x5060_67FF
2KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0x5060_7000
0x5060_57FF
2KiB
BSS_MBOX4GEM mailbox memory space
Reserved
0x5600_0000
0x5060_5FFF
GEM_MBOX4BSS
0x5060_6000
0x5060_67FF
2KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0x5060_7000
0x5060_7FFF
2KiB
BSS_MBOX4GEM mailbox memory space
Reserved
0x5600_0000
0xFFFF_FFFF
Reserved
Reserved
Reserved
Reserved
32KiB
DSS_HSRAM1 (HSRAM) Handshake memory
space
Reserved
1KiB
DSS_MCRC (CRC) module Configuration registers
Reserved
Reserved
Reserved
2.5.4 EDMA Memory Map
Table 3-4 shows the EDMA-TPTC memory map.
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
211
18xx Integration
www.ti.com
Table 2-21. EDMA-TPTC Memory Map
Module Name
Frame Address (Hex)
Size
Used
Description
0x0603_00FF
148B
DSS_SCI memory space view from EDMA
DSS_DSP_L2_UMAP1 0x107E_0000
0x107F_FFFF
128KiB
DSP_L2_UMAP1 (L2) memory view from EDMA
DSS_DSP_L2_UMAP0 0x1080_0000
0x1081_FFFF
128KiB
DSP_L2_UMAP0 (L2) memory view from EDMA
DSS_DSP_L1P
0x10E0_0000
0x10E0_7FFF
32KiB
DSP_L1P (L1) program memory view from EDMA
DSS_DSP_L1D
0x10F0_0000
0x10F0_7FFF
32KiB
DSP_L1D (L1) data memory view from EDMA
DSS_L3RAM
0x2000_0000
0x201F_FFFF
2MB
DSS_L3RAM shared memory space
DSS_ADCBUF
0x2100_0000
0x2100_7FFC
32KiB
DSS_ADCBUF memory space
DSS_CBUFF_FIFO
0x2102_0000
0x2102_3FFC
16KiB
DSS_CBUFF_FIFO (Common buffer) memory
space (Refer to HSI chapter)
DSS_FFT_ACC_DMA1 0x2103 0000
0x2103_7FFF
32KiB
DSS_FFT_ACC_DMA1 (HWA DMA) FFT
accelerator memory-1 space
DSS_FFT_ACC_DMA2 0x2103 8000
0x2107_FFFF
32KiB
DSS_FFT_ACC_DMA2 (HWA DMA) FFT
accelerator memory-2 space
DSS_HSRAM1
0x2108_0000
0x2108_7FFC
32KiB
DSS_HSRAM1 (Handshake) memory
MSS_TCMA_RAM
0x4020_0000
0x4023_FFFF
256 KiB
MSS_TCMA_RAM (TCMA) Data RAM
MSS_TCMB
0x4800_0000
0x4802_FFFF
192 KiB
MSS_TCMB (TCMB) Data RAM
MSS_SW_BUFFER
0x4C20_0000
0x4C20_1FFF
8 KiB
MSS_SW_BUFFER S/W Scratchpad memory
GEM_MBOX4MSS
0x5060_4000
0x5060_4000
2 KiB
GEM_MBOX4MSS mailbox memory space
MSS_MBOX4GEM
0x5060_5000
0x5060_5000
2 KiB
MSS_MBOX4GEM mailbox memory space
GEM_MBOX4BSS
0x5060_6000
0x5060_6000
2 KiB
GEM_MBOX4BSS mailbox memory space
BSS_MBOX4GEM
0x5060_7000
0x5060_7000
2 KiB
BSS_MBOX4GEM mailbox memory space
DSS_EDMA_SCI
2.6
Start
End
0x0603_0000
18xx Integration
2.6.1 Cortex-R4F Subsystem
2.6.1.1
Tightly Coupled Memories
Table 3-5 lists the dedicated MSS_TCMA_RAM and MSS_TCMB sizes for the Cortex R4F processor in
the master subsystem, and also mentions the total available L3 shared RAM in the device. A portion of
this L3 shared memory (DSS_L3RAM) can be allotted as TCM, to further increase the MSS_TCMA_RAM
and MSS_TCMB available for the Cortex R4F.
Table 2-22. TCM and Shared Memory Available for Cortex R4F in Master Subsystem
Cortex R4F
Shared
MSS_TCMA_RAM (Program RAM) (KB)
MSS_TCMB (Data RAM) (KB)
L3 Shared (KB)
512
192
1024
See on how the L3 shared memory (DSS_L3RAM) can be assigned between the Cortex R4F of the
master subsystem and the DSP core.
212
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
2.6.2 Clock Comparator
2.6.2.1
Core Clock Comparator (MSS_CCCA/MSS_CCCB)
Figure 2-19. Integration of MSS_CCCA and MSS_CCCB Modules
mss_vclk
async_rst_n
clock0_src[7:0]
clock1_src[7:0]
clock0_sel[7:0]
clock1_sel[7:0]
count0_expiry_val
MSS_GPCFG
counter_error
counter_done
To MSS_ESM Module
To MSS_VIM Module
MSS_CCCA
(CCCA)
count1_expected_val
disable_clk_output
enable_module
margin_count
count1_val_out
MSS_GPCFG
errstat
singleshot_mode
timeout_err_count
mss_vclk
async_rst_n
clock0_src[7:0]
clock1_src[7:0]
clock0_sel[7:0]
clock1_sel[7:0]
count0_expiry_val
MSS_GPCFG
counter_error
counter_done
To MSS_ESM Module
To MSS_VIM Module
MSS_CCCB
(CCCB)
count1_expected_val
disable_clk_output
count1_val_out
enable_module
margin_count
errstat
MSS_GPCFG
singleshot_mode
timeout_err_count
2.6.2.1.1 MSS_CCCA and MSS_CCCB Integration Connections
This device has two instances of CCC: MSS_CCCA (CCCA) and MSS_CCCB (CCCB). The clock
connectivity information for these two instances is provided in Table 3-6. Configuration and status of this
module is available through the MSS_GPCFG registers of the device.
Table 2-23. MSS_CCCA and MSS_CCCB Integration Connections
MSS_CCCA (CCCA)
MSS_CCCB (CCCB)
counter_error
ESM_GRP1[1]
ESM_GRP1[4]
counter_done
IRQ[80]
IRQ[81]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 213
18xx Integration
www.ti.com
Table 2-23. MSS_CCCA and MSS_CCCB Integration Connections (continued)
MSS_CCCA (CCCA)
MSS_CCCB (CCCB)
clock0_src[0]
REFCLK
CR4_VCLK
clock0_src[1]
CPUCLK
DSSCLK
clock0_src[2]
RCCLK
BSSCLK
clock0_src[3]
RCCLK
QSPICLK
clock0_src[4]
RCCLK
N/A
clock0_src[5]
RCCLK
REFCLK
clock0_src[6]
RCCLK
CPUCLK
clock0_src[7]
RCCLK
RCCLK
clock1_src[0]
REFCLK
PLLCLK_600
clock1_src[1]
PLLCLK_600
MSS_VCLK
clock1_src[2]
PLL 240Mhz
CPUCLK
clock1_src[3]
RCCLK
CR4_VCLK
clock1_src[4]
RCCLK
MSS_VCLK
clock1_src[5]
RCCLK
DSSCLK
clock1_src[6]
RCCLK
BSSCLK
clock1_src[7]
RCCLK
QSPICLK
2.6.2.1.2 MSS_CCCB Integration to MSS_WD
As a safety requirement, WDT IP should work on an independent clock source instead of the clock used
by the MSS CR4. Because the WDT IP does not allow this flexibility, an additional monitoring logic is
added in the form of CCM (MSS_CCCB instance), coupled along with the watchdog. MSS_CCCB is used
to compare CR4_VCLK to an independent reference clock, such as XTAL. If the CR4 clock indicates a
deviation from the expected frequency, a WD reset or a WD NMI can be issued.
Figure 2-20. MSS_CCCB Integration to MSS_WD
MSS_WD_RST
(WARM_RESET generation)
RTI_RESETn
MSS_WDT
(MSS_RTIB)
RTI_WWD_NMI
counter_error
MSS_GPCFG.ENABLECCBERRRSTN
MSS_CCCB
MSS_WD_NMI
(to MSS_ESM)
MSS_GPCFG.ENABLECCBERRNMI
214
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
2.6.2.2
Dual Clock Comparator (MSS_DCCA/MSS_DCCB)
Figure 2-21. MSS_DCCA/MSS_DCCB Integration Diagram
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
MSS_DCC
Clock Source Selection
MSS_DCCA/
MSS_DCCB
(DCCA/DCCB)
dcc_done_int
To MSS_VIM Module
dcc_error
To MSS_ESM Module
Table 2-24. MSS_DCCA Clock Source Selection Table
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
0x0 - REF_CLK
0x0 - REF_CLK
0xA - PLL_600
0x1 - CPU_CLK
0x5 - PLL_240
0x2 to 0x7 - RC_CLK
Table 2-25. MSS_DCCB Clock Source Selection Table
DCCCLKSSRC0[3:0]
DCCCLKSSRC1[3:0]
0x0 - PLL_600
0x0 - VCLK
0xA - VCLK
0x1 - DSS_CLK
0x5 - CPU_CLK
0x2 - BSS_CLK
0x3 - QSPI_CLK
0x4 - Reserved
0x5 - CPU_CLK
0x6 - REF_CLK
0x7 - RC_CLK
NOTE: Any values not mentioned are not used.
2.6.3 C674x DSP Subsystem
2.6.3.1
DSP Event Assignment
Table 2-26. DSP Event Assignment
Event No.
Interrupt
Description
0
EVT0
Output of event combiner0, for events 1 through 31
1
EVT1
Output of event combiner0, for events 32 through 63
2
EVT2
Output of event combiner0, for events 64 through 95
3
EVT3
Output of event combiner0, for events 96 through 127
4
Reserved
Reserved
5
Reserved
Reserved
6
Reserved
Reserved
7
Reserved
Reserved
8
Reserved
Reserved
9
Reserved
Reserved
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 215
18xx Integration
www.ti.com
Table 2-26. DSP Event Assignment (continued)
Event No.
Interrupt
Description
10
Reserved
Reserved
11
Reserved
Reserved
12
Reserved
Reserved
13
IDMAINT0
From DSP EMC, IDMA Channel 0 Interrupt
14
IDMAINT1
From DSP EMC, IDMA Channel 1Interrupt
15
Reserved
Reserved
16
DSS_TPTC0_IRQ_DONE
DSS_TPTC0 (EDMA TPTC0) completion interrupt
17
DSS_TPTC0_IRQ_ERR
DSS_TPTC0 (EDMA TPTC0) Error Interrupt
18
DSS_TPTC1_IRQ_DONE
DSS_TPTC1 (EDMA TPTC1) completion interrupt
19
DSS_TPTC1_IRQ_ERR
DSS_TPTC1 (EDMA TPTC1) Error Interrupt
20
DSS_TPCC_IRQ_DONE
DSS_TPCC (EDMA TPCC0) Global completion Interrupt
21
DSS_TPCC_IRQ_ERR
DSS_TPCC (EDMA TPCC0) Error Interrupt
22
DSS_CBUFF_IRQ
DSS_CBUFF (COMMON BUFFER) Interrupt
23
Reserved
Reserved
24
DSS_CBUFF_ERR_INTR
DSS_CBUFF (COMMON BUFFER) Error Interrupt
25
Reserved
Reserved
26
DSS_FRAME_START_IRQ/DSS_DMMSW Mux of VIN Frame start or BSS DFE Frame start.
IN T0/DSS_DMMSWINT39
27
DSS_CHIRP_AVAIL_IRQ/DSS_DMMSWI
NT2 /DSS_DMMSWINT43
Mux of VIN Chirp Available or DFE chirp available..
28
Reserved
Reserved
29
FFT_ACC_PARAM_DONE_INTR
DSS_HW_ACC FFT accelerator - param done interrupt
30
FFT_ACC_DONE_INTR
DSS_HW_ACC FFT accelerator - done interrupt
31
FFT_ACC_ACCESS_ERR
DSS_HW_ACC FFT accelerator - access error interrupt
32
DSS_ESM_LOW_PRIORITY
MSS_ESM_IRQ (Aggregate of MSS_ESM_GP1 errors)
33
DSS_MCRC_INT
MSS_MCRC (CRC) Interrupt
34
DSS_PROG_FILT_ERR
Error interrupt from Programmable filter indicating wrong
programming of filter length exceeding the allowed range.
35
GEM_WAKEUP_SOURCE_FROM_DFT
Wakeup source from DFT module.
36
DSS_STC_DONE
Done indication from DSS_STC
37
DSP_PBIST_DONE
DSP_PBIST done indication from GEM
38
Reserved
Reserved
39
Reserved
Reserved
40
Reserved
Reserved
41
Reserved
Reserved
42
Reserved
Reserved
43
Reserved
Reserved
44
Reserved
Reserved
45
Reserved
Reserved
46
DSS_DMMSWINT8
Interrupt from DSS_DMM configurable
47
DSS_DMMSWINT4
Interrupt from DSS_DMM configurable
48
Reserved
Reserved
49
Reserved
Reserved
50
Reserved
Reserved
51
Reserved
Reserved
52
Reserved
Reserved
53
Reserved
Reserved
54
Reserved
Reserved
216 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-26. DSP Event Assignment (continued)
Event No.
Interrupt
Description
55
Reserved
Reserved
56
Reserved
Reserved
57
Reserved
Reserved
58
DSS_MSS_SW0
DSS_MSS_SW interrupt
59
DSS_MSS_SW1
DSS_MSS_SW interrupt
60
DSS_DMMSWINT5
Interrupt from DSS_DMM configurable
61
DSS_DMMSWINT6
Interrupt from DSS_DMM configurable
62
DSS_BSS_SW1
Radar SS SW Interrupt 0
63
DSS_BSS_SW2
Radar SS SW Interrupt 1
64
DSS_TPTC2_IRQ_DONE
DSS_TPTC2 (EDMA TPTC2) completion interrupt
65
DSS_TPTC2_IRQ_ERR
DSS_TPTC2 (EDMA TPTC2) Error Interrupt
66
DSS_TPTC3_IRQ_DONE
DSS_TPTC3 (EDMA TPTC3) completion interrupt
67
DSS_TPTC3_IRQ_ERR
DSS_TPTC3 (EDMA TPTC3) Error Interrupt
68
DSS_TPCC1_IRQ_DONE
DSS_TPCC1 (EDMA TPCC1) Global completion Interrupt
69
DSS_TPCC1_IRQ_ERR
DSS_TPCC1 (EDMA TPCC1) Error Interrupt
70
DSS_ADC_DATA_VALID_FALL/DSS_DM
MS WINT3/DSS_DMMSWINT44
DSS_ADC Ping/Pong interrupt
71
DSS_UART_REQ0
DSS_SCI (UART) Req 0
72
DSS_UART_REQ1
DSS_SCI (UART) Req 1
73
DSS_RTI0_OVERFLOW_0
DSS_RTI Overflow 0
74
DSS_RTI0_OVERFLOW_1
DSS_RTI Overflow 1
75
DSS_RTI0_0
DSS_RTI Interrupt 0
76
DSS_RTI0_1
DSS_RTI Interrupt 1
77
DSS_RTI0_2
DSS_RTI Interrupt 2
78
DSS_RTI0_3
DSS_RTI Interrupt 3
79
DSS_RTI1_OVERFLOW_0
DSS_RTI2 Overflow 0
80
DSS_RTI1_OVERFLOW_1
DSS_RTI2 Overflow 1
81
DSS_RTI1_0
DSS_RTI2 Interrupt 0
82
DSS_RTI1_1
DSS_RTI2 Interrupt 1
83
DSS_RTI1_2
DSS_RTI2 Interrupt 2
84
DSS_RTI1_3
DSS_RTI2 Interrupt 3
85
DSS_BSS_MAILBOX_FULL
Interrupt indicating there is a message from MSS in the
Mailbox BSS-DSS
86
DSS_BSS_MAILBOX_EMPTY
Interrupt indicating the MSS has read/ack the message DSP
posted in the Mailbox DSS-BSS
87
GPIO_0_host_interrupt
MSS_GIO (GPIO) host Interrupt Controller
88
GPIO_1_host_interrupt
MSS_GIO (GPIO) host Interrupt Controller
89
GPIO_2_host_interrupt
MSS_GIO (GPIO) host Interrupt Controller
90
Reserved
Reserved
91
DSS_MSS_MAILBOX_FULL
Interrupt indicating there is a message from MSS in the
Mailbox MSS-DSS
92
DSS_MSS_MAILBOX_EMPTY
Interrupt indicating the MSS has read/ack the message DSP
posted in the Mailbox DSS-MSS
93
DSS_LOGICAL_FRAME_START/DSS_D
MM SWINT1/DSS_DMMSWINT40
Logical Frame start interrupt
94
DSS_DMMSWINT7
Interrupt from DSS_DMM configurable
95
Reserved
Reserved
96
INTERR
DSP dropped CPU interrupt event
97
IDMA_ERR
Invalid IDMA parameters
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 217
18xx Integration
www.ti.com
Table 2-26. DSP Event Assignment (continued)
Event No.
Interrupt
Description
98
Reserved
Reserved
99
Reserved
Reserved
100
Reserved
Reserved
101
Reserved
Reserved
102
Reserved
Reserved
103
Reserved
Reserved
104
Reserved
Reserved
105
Reserved
Reserved
106
Reserved
Reserved
107
Reserved
Reserved
108
Reserved
Reserved
109
Reserved
Reserved
110
Reserved
Reserved
111
Reserved
Reserved
112
Reserved
Reserved
113
DSP_PMC_ED
DSS_DSP_L1P parity error
114
Reserved
Reserved
115
Reserved
Reserved
116
DSP_UMC_ED1
DSS_DSP_L2 ECC single error correction
117
DSP_UMC_ED2
DSS_DSP_L2 ECC double error detection
118
DSP_PDC_INT
Power down sleep interrupt
119
DSP_SYS_CMPA
CPU memory protection fault
120
DSP_L1P_CMPA
DSS_DSP_L1P CPU memory protection fault
121
DSP_L1P_DMPA
DSS_DSP_L1P DMA memory protection fault
122
DSP_L1D_CMPA
DSS_DSP_L1D CPU memory protection fault
123
DSP_L1D_DMPA
DSS_DSP_L1D DMA memory protection fault
124
DSP_L2_CMPA
DSS_DSP_L2 CPU memory protection fault
125
DSP_L2_DMPA
DSS_DSP_L2 DMA memory protection fault
126
DSP_EMC_CMPA
From EMC, CPU memory protection fault
127
DSP_EMC_BUSSERR
From EMC, bus error interrupt
2.6.4 Direct Memory Access Controller (MSS_DMA)
2.6.4.1
MSS_DMA Integration Diagrams
The device has two instances of DMA module, MSS_DMA and MSS_DMA2. Integration of the two DMA
blocks in the device are shown in Figure 3-5 and .
218
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Figure 2-22. Integration of MSS_DMA and MSS_DMA2 Module
From MSS_RCM
VCLK
RSTn
MMI_START
MMI_DONE
MSS_DMA
dma1_req[63:0]
Request Source
Configuration Port
VBUS PCR
From BUS Matrix
From MSS_RCM
MSS_DMA
(DMA1)
VCLK
RSTn
MMI_START
MMI_DONE
Configuration Port
VBUS_PCR
VBUS PCR
From BUS Matrix
To MSS_VIM Module
dma1_uerr
dma1_mpv
dma1_wrerr_int_pls
dma1_portb_vbusm
VBUS_PCR
MSS_DMA
dma2_req[63:0]
Request Source
dma1_ftcint
dma1_lfsint
dma1_hbcint
dma1_btcint
dma1_berint
MSS_DMA2
(DMA2)
dma2_ftcint
dma2_lfsint
dma2_hbcint
dma2_btcint
dma2_berint
To MSS_ESM Module
Master Port on
BUS Matrix
To MSS_VIM Module
dma2_uerr
To MSS_ESM Module
dma2_mpv
dma2_wrerr_int_pls
dma2_portb_vbusm
Master Port on
BUS Matrix
2.6.4.2 MSS_DMA Features
• 64-bit OCP protocol to perform bus master accesses
• INCR-4 64-bit burst accesses
• Multithreading architecture allowing data of two different channel transfers to be interleaved during
non-burst accesses
• 2-port configuration for parallel bus master
• Channels can be assigned to either high-priority queue or low-priority queue. Within each queue, fixed
or round-robin priorities can be serviced
• Built-in ECC generation and evaluation logic for internal RAM-storing channel transfer information
• Supports multiple interrupt outputs for mapping to multiple interrupt controllers in multicore systems
• 48 requests can be mapped to any 32 channels
• Supports LE endianness
• External ECC Gen/Eval block of MSS_DMA support ECC generation for data transactions, and parity
for address, and control signals (following Cortex-R5F standard)
• 8 MPU regions
• Channel-chaining capability
• Hardware and software MSS_DMA requests
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
219
18xx Integration
•
•
•
2.6.4.3
www.ti.com
8-, 16-, 32-, or 64-bit transactions supported
Multiple addressing modes for source and destination (fixed, increment, offset)
Auto-initiation
MSS_DMA Request Map
Both instances of MSS_DMA have 64 lines of request and are connected to identical input triggers, as
shown in Table 3-10. This allows the two DMAs to trigger different types of transfers for the same request.
Table 2-27. MSS_DMA Request Map
Module
DMA Request Sources
DMA Request
MSS_MIBSPIA
MSS_MIBSPIA Channel-1
DMAREQ[0]
MSS_MIBSPIA
MSS_MIBSPIA Channel-0
DMAREQ[1]
MSS_MIBSPIB
MSS_MIBSPIB
DMAREQ[2]
MSS_MIBSPIB
MSS_MIBSPIB
DMAREQ[3]
MSS_QSPI
MSS_QSPI DMA request
DMAREQ[4]
MSS_MIBSPIA
MSS_MIBSPIA Channel-3
DMAREQ[5]
MSS_DCAN
MSS_DCAN IF2
DMAREQ[6]
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) DMAREQ
DMAREQ[7]
MSS_DCAN
MSS_DCAN IF1
DMAREQ[8]
MSS_MIBSPIA
MSS_MIBSPIA Channel-5
DMAREQ[9]
MSS_I2C
MSS_I2C receive
DMAREQ[10]
MSS_I2C
MSS_I2C transmit
DMAREQ[11]
MSS_RTIA
MSS_RTIA DMAREQ0
DMAREQ[12]
MSS_RTIA
MSS_RTIA DMAREQ1
DMAREQ[13]
Reserved
Reserved
DMAREQ[14]
Reserved
Reserved
DMAREQ[15]
MSS_DCAN
MSS_DCAN IF3
DMAREQ[16]
MSS_MIBSPIA
MSS_MIBSPIA Channel-2
DMAREQ[17]
MSS_RTIA
MSS_RTIA DMAREQ2
DMAREQ[18]
MSS_RTIA
MSS_RTIA DMAREQ3
DMAREQ[19]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ0
DMAREQ[20]
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) DMAREQ1
DMAREQ[21]
MSS_MIBSPIA
MSS_MIBSPIA Channel-4
DMAREQ[22]
MSS_ETPWM3A
MSS_ETPWM3A DMAREQ
DMAREQ[23]
MSS_RTIB (WDT/RTIB)
WDT/RTIB DMAREQ2
DMAREQ[24]
MSS_RTIB (WDT/RTIB)
WDT/RTIB DMAREQ3
DMAREQ[25]
MSS_MCRC (CRC)
MSS_MCRC (CRC) DMAREQ0
DMAREQ[26]
MSS_MCRC (CRC)
MSS_MCRC (CRC) DMAREQ1
DMAREQ[27]
MSS_SCIB (UART2)
MSS_SCIB (UART2) receive
DMAREQ[28]
MSS_SCIB (UART2)
MSS_SCIB (UART2) transmit
DMAREQ[29]
MSS_SCIA (UART1)
MSS_SCIA (UART1) receive
DMAREQ[30]
MSS_SCIA (UART1)
MSS_SCIA (UART1) transmit
DMAREQ[31]
MSS_GIO
MSS_GIO-0
DMAREQ[32]
MSS_GIO
MSS_GIO-1
DMAREQ[33]
MSS_GIO
MSS_GIO-2
DMAREQ[34]
MSS_ETPWM1A
MSS_ETPWM1A DMAREQ
DMAREQ[35]
Reserved
Reserved
DMAREQ[36]
MSS_MIBSPIB
MSS_MIBSPIB Channel-2
DMAREQ[37]
MSS_MIBSPIB
MSS_MIBSPIB Channel-3
DMAREQ[38]
MSS_ETPWM1B
MSS_ETPWM1B DMAREQ
DMAREQ[39]
220 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-27. MSS_DMA Request Map (continued)
Module
DMA Request Sources
DMA Request
MSS_ETPWM2A
MSS_ETPWM2A DMAREQ
DMAREQ[40]
MSS_ETPWM2B
MSS_ETPWM2B DMAREQ
DMAREQ[41]
MSS_MIBSPIB
MSS_MIBSPIB Channel-4
DMAREQ[42]
MSS_MIBSPIB
MSS_MIBSPIB Channel-5
DMAREQ[43]
Reserved
Reserved
DMAREQ[44]
MSS_ETPWM3B
MSS_ETPWM3B DMAREQ
DMAREQ[45]
MSS_GIO
MSS_GIO-14
DMAREQ[46]
MSS_GIO
MSS_GIO-15
DMAREQ[47]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-0
DMAREQ[48]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-1
DMAREQ[49]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-2
DMAREQ[50]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-3
DMAREQ[51]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-4
DMAREQ[52]
MSS_DTHE (Crypto/SHA)
SHA DMAREQ-5
DMAREQ[53]
MSS_DTHE (Crypto/AES)
AES DMAREQ-0
DMAREQ[54]
MSS_DTHE (Crypto/AES)
AES DMAREQ-1
DMAREQ[55]
MSS_DTHE (Crypto/AES)
AES DMAREQ-2
DMAREQ[56]
MSS_DTHE (Crypto/AES)
AES DMAREQ-3
DMAREQ[57]
MSS_DTHE (Crypto/AES)
AES DMAREQ-4
DMAREQ[58]
MSS_DTHE (Crypto/AES)
AES DMAREQ-5
DMAREQ[59]
MSS_DTHE (Crypto/AES)
AES DMAREQ-6
DMAREQ[60]
MSS_DTHE (Crypto/AES)
AES DMAREQ-7
DMAREQ[61]
Reserved
Reserved
DMAREQ[62]
Reserved
Reserved
DMAREQ[63]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
221
18xx Integration
www.ti.com
2.6.5 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB)
Figure 2-23. Integration of MSS_RTIA and MSS_RTIB, WDT Using the MSS_RTIB Module
From
MSS_RCM
rti_ovf l_req[1:0]
rti_vclk
rti_ cmp_int_req[3:0]
rti_sync
Not used
RTI_PIN
To/From MSS_VIM
rti_tb_int_req
Vim_cap_evt[1:0]
NTU[3:0]
MSS_RTIA
(RTIA)
rti_dma_req[3:0]
To MSS_DMA/MSS_DMA2
VBUS_PCR
MSS_RTI Register Configuration
MSS_RTIC
MSS_RTID
wdt_ovl_req[1:0]
wdt_vclk
To/From
wdt_sync
MSS_RCM
wdt _rstn
Port from Bus Matrix
wdt_int_req[3:0]
To MSS_VIM
wdt_tb_int_req
Vim_cap_evt[1:0]
MSS_RTIB
NTU[3:0]
Not used
RTI_PIN
(WDT/RTIB)
wdt _dma_req[3 :0]
To MSS_DMA/MSS_DMA2
VBUS_PCR
MSS_WDT Register Configuration
wdt_nmi_req
Port from Bus Matrix
To MSS_ESM
2.6.6 General Purpose I/0 (MSS_GIO)
NOTE: Emulation mode and power-down mode (low-power mode) are not supported in the 18xx
device.
222
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Figure 2-24. Integration Block Diagram for MSS_GIO
gio_vclk
From
MSS_RCM
MSS_GIO
(GIO)
gio_rstn
GIOA[7:0]
GIOB[7:0]
gio_pc
Device
PCR Bus
GIOC[7:0]
To/from device pins
GPIO_0:GPIO_47
GIOD[7:0]
GIOE[7:0]
GIOF[7:0]
GIO_low_level_interrupt
To
MSS_VIM
GIO_high_level_interrupt
GIO G and F, is
included but not
supported
GIO_0_host_interrupt
To MSS_VIM &
DSP-Event
GPIO_0
GIO_1_host_interrupt
GIO_2_host_interrupt
GPIO Host
Interrupt Controller
(Specific to AR16)
GPIO_1
GPIO_2
From device pins
GPIO_0,GPIO_1,GPIO_2
GIO_0_host_DMA
To MSS_DMA
GIO_1_host_DMA
GIO_2_host_DMA
MSS_GPCFG_REG:
GPIOINTREDGESEL
GIO_14_host_DMA
GPIO_14
To MSS_DMA
Positive Edge to Pulse
GPIO_15
From device pins
GPIO_14, GPIO_15
GIO_15_host_DMA
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
223
18xx Integration
www.ti.com
2.6.7 Data Modification Module (MSS_DMM)
Figure 2-25. MSS_DMM Integration
From
MSS_RCM
dmm_vclk
dmm_rstn
Config
Port From
Bus-matrix
DMM1_PCR
dmm1_int_lvl0
dmm1_int_lvl1
ToMSS_VIM
MSS_DMM
(DMM1)
Not used
AHB2VBUSP
&
VBUSP2VBUSM
dmm_clk
To/from dmmsync_in
device dmmdata_in[15:0]
pins
dmmmux_in
DMM
SCR
64-Bit
MSS BUS MATRIX
AHB2VBUSP
&
VBUSP2VBUSM
Not used
From
MSS_RCM
Config
Port From
Bus-matrix
224
16xx/18xx
dmm_vclk
dmm_rstn
DMM2_PCR
MSS_DMM2
(DMM2)
dmm2_int_lvl0
dmm2_int_lvl1
ToMSS_VIM
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
2.6.8 Enhanced Pulse Width Modulator (MSS_ETPWM)
Figure 2-26. Multiple MSS_ETPWM Modules
Frame start
Rampgen
ePWM1_synci_in
From device pins
MSS_GPCFG_REG:
EPWMCFG
ePWM1_sync
ePWM1a_output
ePWM1b_output
ePWM1_vlk
From MSS_RCM ePWM1_rst
Device pins
MSS_ESM low-level int
DCC_1 done int
Not used
ePWM1a_dma_req
ePWM1b_dma_req
ePWM1_TZ[2:0]
ePWM1_TZ[3]
ePWM1_TZ[4]
ePWM1_TZ[5]
MSS_ETPWM1
(ePWM1)
ePWM1_adc_soc[1:0]
ePWM1_pcr
MSS_GPCFG_REG:
EPWMCFG
Frame start ePWM1_sync_out
Rampgen
MSS_GPCFG_REG:
PWMDMATRIGEN
To
MSS_DMA/
MSS_DMA2
Not used
ePWM1_int[1:0]
Device PCR Bus
To device pins
ToMSS_VIM
Todevice pins
ePWM2_sync
ePWM2a_output
ePWM2b_output
ePWM2_vlk
From MSS_RCM ePWM2_rst
Device pins
MSS_ESM low-level int
DCC_1 done int
Not used
ePWM2a_dma_req
ePWM2b_dma_req
ePWM2_TZ[2:0]
ePWM2_TZ[3 ]
ePWM2_TZ[4]
ePWM2_TZ[5]
Device PCR Bus
MSS_ETPWM2
(ePWM2)
MSS_GPCFG_REG:
EPWMCFG
ePWM2_int[1:0]
Frame start
Rampgen
ePWM2_sync_out
MSS_GPCFG_REG:
PWMDMATRIGEN
To
MSS_DMA/
MSS_DMA2
Not used
ePWM2_adc_soc[1:0]
ePWM2_pcr
To device pins
ToMSS_VIM
To device pins
ePWM3_sync
ePWM3a_output
ePWM3b_output
ePWM3_vlk
From MSS_RCM ePWM3_rst
Device pins
MSS_ESM low-level int
DCC_1 done int
Not used
ePWM3_TZ[2:0]
ePWM3_TZ[3]
ePWM3_TZ [4]
ePWM3_TZ[5]
Device PCR Bus
ePWM3a_dma_req
ePWM3b_dma_req
MSS_ETPWM3
(ePWM3)
ePWM3_adc_soc[1:0]
ePWM3_pcr
ePWM3_int[1:0]
ePWM3_sync_out
Note : Rampgen and Frame start
are from the RADAR Subsystem
To device pins
To
MSS_DMA/MSS_DMA2
Not used
To MSS_VIM
To device pins
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
225
18xx Integration
www.ti.com
2.6.9 Vectored Interrupt Manager (MSS_VIM)
2.6.9.1
Interrupt Request Assignments
Table 2-28. Interrupt Request Assignments
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
MSS_ESM
MSS_ESM high-level interrupt(NMI)
0
Reserved
Reserved
1
MSS_RTIA
MSS_RTIA compare interrupt 0
2
MSS_RTIA
MSS_RTIA compare interrupt 1
3
MSS_RTIA
MSS_RTIA compare interrupt 2
4
MSS_RTIA
MSS_RTIA compare interrupt 3
5
MSS_RTIA
MSS_RTIA overflow interrupt 0
6
MSS_RTIA
MSS_RTIA overflow interrupt 1
7
MSS_RTIA
MSS_RTIA time-base
8
MSS_GIO
MSS_GIO high-level interrupt
9
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 0
10
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt1
11
MSS_MIBSPIA
MSS_MIBSPIA level 0 interrupt
12
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 2
13
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) interrupt 3
14
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) overflow interrupt 15
0
MSS_DCAN
MSS_DCAN level 0 interrupt
16
MSS_MIBSPIB
MSS_MIBSPIB level 0 Interrupt
17
MSS_GIO host interrupt module
MSS_GIO GPIO_0_host_interrupt
18
MSS_MCRC (CRC)
MSS_MCRC (CRC) interrupt
19
MSS_ESM
MSS_ESM low-level interrupt
20
SYSTEM
Software-triggered interrupt 4
21
MSS Cortex R4F
MSS Cortex R4F interrupt PMU
22
MSS_GIO
MSS_GIO low-level interrupt
23
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) overflow interrupt 24
1
MSS_RTIB (WDT/RTIB)
MSS_RTIB (WDT/RTIB) TB base interrupt 25
MSS_MIBSPIA
MSS_MIBSPIA level 0 interrupt
26
MSS_QSPI
MSS_QSPI interrupt
27
MSS_DMM
MSS_DMM S/W interrupt 38
28
MSS_DCAN
MSS_DCAN level 1 interrupt
29
MSS_MIBSPIB
MSS_MIBSPIB level 1 interrupt
30
MSS_DTHE (Crypto/SHA)
MSS_DTHE (Crypto/SHA) SHA -S
interrupt
31
MSS_GIO host interrupt module
MSS_GIO GPIO_1_host_interrupt
32
MSS_DMA
MSS_DMA frame transfer complete
interrupt
33
MSS_DMA
MSS_DMA last frame transfer start
interrupt
34
Reserved
Reserved
35
MSS_DMM
MSS_DMM level -0 interrupt
36
MSS_DTHE (Crypto/SHA)
MSS_DTHE (Crypto/SHA) SHA -P
interrupt
37
MSS_DTHE (Crypto/TRNG)
MSS_DTHE (Crypto/TRNG) TRNG
interrupt
38
226 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-28. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
MSS_DMA
MSS_DMA half-block transfer complete
interrupt
39
MSS_DMA
MSS_DMA block transfer complete
interrupt
40
MSS_DMA2
MSS_DMA2 frame block transfer
complete interrupt
41
Reserved
Reserved
42
MSS_DMM
MSS_DMM level -1 interrupt
43
Reserved
Reserved
44
MSS_DMA2
MSS_DMA2 last frame complete interrupt
45
Reserved
Reserved
46
FPU
Floating point unit interrupt
47
MSS_GIO (GPIO host interrupt module)
MSS_GIO GPIO_2_host_interrupt
48
MSS_DMA2
MSS_DMA2 half-block transfer complete
interrupt
49
MSS_DMA2
MSS_DMA2 block transfer complete
interrupt
50
MSS_DMA2
MSS_DMA2 bus error interrupt
51
System
DSS to MSS software-triggered by
register
DSS_REG2:MSSSWIRQ:MSSSWIRQ1
52
MSS_DTHE (Crypto/PKA)
MSS_DTHE (Crypto/PKA) PKA module
interrupt
53
MSS_DTHE (Crypto/AES)
MSS_DTHE (Crypto/AES) AES-S module
interrupt
54
Reserved
Reserved
55
MSS_DTHE (Crypto/AES)
MSS_DTHE (Crypto/AES) AES-P module
interrupt
56
MSS_DMM2
MSS_DMM2 level -0 interrupt
57
MSS_DMM2
MSS_DMM2 level -1 interrupt
58
Mailbox
DSS to MSS mailbox full interrupt
59
Mailbox
DSS to MSS mailbox empty interrupt
60
System
DSS to MSS software-triggered by
register
DSS_REG2:MSSSWIRQ:MSSSWIRQ2
61
MSS_DEBUGSS (Debug subsystem)
MSS_DEBUGSS (Debug subsystem)
interrupt
62
DSPSS-MSS_STC
GEM MSS_STC done interrupt
63
MSS_SCIA (UART1)
MSS_SCIA (UART1) level 0 interrupt
64
MSS_SCIB (UART2)
MSS_SCIB (UART2) level 0 interrupt
65
MSS_I2C
MSS_I2C interrupt
66
MSS_DMM
MSS_DMM interrupt 34
67
MSS_DMM
MSS_DMM interrupt 35
68
MSS_DMM
MSS_DMM interrupt 36
69
MSS_DMA
MSS_DMA bus error interrupt
70
MSS_DMM/Radar subsystem
MSS_DMM interrupt 30 or Radar
subsystem logical Frame Start
71
Reserved
Reserved
72
MSS_DMM
MSS_DMM interrupt 33
73
MSS_SCIA (UART1)
MSS_SCIA (UART1) level 1 interrupt
74
MSS_SCIB (UART2)
MSS_SCIB (UART2) level 1 interrupt
75
SYSTEM
Software-triggered interrupt 0
76
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 227
18xx Integration
www.ti.com
Table 2-28. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
SYSTEM
Software-triggered interrupt 1
77
SYSTEM
Software-triggered interrupt 2
78
SYSTEM
Software-triggered interrupt 3
79
Reserved
Reserved
80
Reserved
Reserved
81
MSS_DCCA
MSS_DCCA (dual clock compare)
module1-done interrupt
82
MSS_DCCB
MSS_DCCB (dual clock compare)
module2-done interrupt
83
SYSTEM
Software-triggered interrupt 5
84
MSS_PBIST
MSS_PBIST interrupt
85
MSS_DMM/DSS
GEM IRQ-7/MSS_DMM interrupt 32
86
Reserved
Reserved
87
Reserved
Reserved
88
Reserved
Reserved
89
Reserved
Reserved
90
Reserved
Reserved
91
Reserved
Reserved
92
Reserved
Reserved
93
Reserved
Reserved
94
MAILBOX
RADARSS to MSS mailbox interrupt
95
MAILBOX
RADARSS mailbox read complete
interrupt sent from RADARSS to MSS
96
RADARSS
ADC valid fall interrupt
97
MSS_DMM/RADARSS
MSS_DMM interrupt 29/frame start
interrupt/
98
RADARSS
Chirp start interrupt
99
RADARSS
Chirp end Interrupt
100
RADARSS
Frame end Interrupt
101
Reserved
Reserved
102
Reserved
Reserved
103
MSS_ETPWM1
ePWM1 interrupt-1
104
RADARSS-MSS_STC
MSS_STC done Interrupt
105
RadarSS
All RadarSS interrupts combined
106
MSS_ETPWM1
ePWM1 interrupt-2
107
MSS_ETPWM2
ePWM2 interrupt-1
108
MSS_ETPWM2
ePWM2 interrupt-2
109
MSS_ETPWM3
ePWM3 interrupt-1
110
MSS_ETPWM3
ePWM3 interrupt-2
111
DSS_TPTC0 (EDMA TPTC0)
DSS_TPTC0 (EDMA TPTC0) interrupt
112
DSS_TPTC0 (EDMA TPTC0)
DSS_TPTC0 (EDMA TPTC0) error
interrupt
113
DSS_TPTC1 (EDMA TPTC1)
DSS_TPTC1 (EDMA TPTC1) interrupt
114
DSS_TPTC1 (EDMA TPTC1)
DSS_TPTC1 (EDMA TPTC1) error
interrupt
115
DSS_TPCC (EDMA TPCC0)
DSS_TPCC (EDMA TPCC0) interrupt
116
DSS_TPCC (EDMA TPCC0)
DSS_TPCC (EDMA TPCC0) error
interrupt
117
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) interrupt
118
228 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-28. Interrupt Request Assignments (continued)
Module
VIM Interrupt Sources
Default VIM Interrupt Channel
Reserved
Reserved
119
DSS_CBUFF (Common Buffer)
DSS_CBUFF (Common Buffer) error
interrupt
120
MSS_DMM
MSS_DMM interrupt 37
121
Reserved
Reserved
122
DSS_ADCBUF/MSS_DMM
Chirp available interrupt/MSS_DMM
interrupt 31
123
MSS_PBIST
MSS_PBIST: Gem MSS_STC done
124
DSS_HW_ACC
DSS_HW_ACC FFT accelerator -param
done interrupt
125
DSS_HW_ACC
DSS_HW_ACC FFT accelerator - done
interrupt
126
DSS_HW_ACC
DSS_HW_ACC FFT accelerator –access
error interrupt
127
2.6.10 Controller Area Network (MSS_DCAN)
Figure 2-27. Integration Block Diagram for MSS_DCAN Module
From MSS_RCM
Vbusp_clk
Vbusp_rstn
dcan_clk
dcan_mmistart
dcan_mmidone
MSS_DCAN
(CAN)
Configuration Port
VBUS PCR
From BUS Matrix
VBUS_PCR
To MSS_VIM
dcan_lvl_int[1:0]
dcan_IF1
dcan_IF2
dcan_IF3
dma_uerr
dma_serr
dcan_tx
dcan_rx
dcan_rx_oe_n
dcan_tx_oe_n
To MSS_DMA/MSS_DMA2
To MSS_ESM
To/from device pins
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
229
18xx Integration
www.ti.com
2.6.11 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPI)
Figure 2-28. MSS_MIBSPIA Integration
spia_cs_n_in[3:0]
spia_clk_in
spia_mosi_in
spia_miso_in
spia_nrst
spia_vclk
spia_mem_init
spia_mem_init_done
spia_trig_src[1:0]
From
MSS_RCM
spia_cs_n_ie[3:0]
spia_clk_ie
spia_mosi_ie
spia_miso_ie
spia_1sync_to_2sync_en
To MSS_VIM
spia_int_req[1:0]
To MSS_DMA/
MSS_DMA2
spia_dma_req[5:0]
To MSS_ESM
Config
Port From
Bus-matrix
230
16xx/18xx
MSS_MIBSPIA
(MIBSPIA)
spia_sberror
spia_uerror
Register Control
from MSS_RCM
Configuration space
spia_cs_n_out[3:0]
spia_clk_out
spia_mosi_out
spia_miso_out
To/from device pins
spia_cs_n_oe_n[3:0]
spia_clk_oe_n
spia_mosi_oe_n
spia_miso_oe_n
spia_pcr
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Figure 2-29. MSS_MIBSPIB Integration
From
MSS_RCM
spib_nrst
spib_vclk
spib_mem_init
spib_mem_init_done
spib_trig_src[1:0]
spib_cs_n_in[3:0]
spib_clk_in
spib_mosi_in
spib_miso_in
Register Control
from MSS_RCM
Configuration space
spib_1sync_to_2sync_en
To MSS_VIM
spib_int_req[1:0]
MSS_MIBSPIB
(MIBSPIB)
To MSS_DMA
spib_dma_req[5:0]
/MSS_DMA2
To MSS_ESM
spib_cs_n_out[3:0]
spib_clk_out
spib_mosi_out
spib_miso_out
To/from device pins
spib_cs_n_oe_n[3:0]
spib_clk_oe_n
spib_mosi_oe_n
spib_miso_oe_n
spib_sberror
spib_uerror
Config
Port From
Bus-matrix
spib_cs_n_ie[3:0]
spib_clk_ie
spib_mosi_ie
spib_miso_ie
spib_pcr
2.6.12 Quad Serial Peripheral Interface (MSS_QSPI)
The MSS_QSPI module of the 18xx only supports one CS pin, (qspi1_cs).
2.6.13 Enhanced Direct Memory Access (EDMA)
2.6.13.1 EDMA Controller Integration
The 18xx device has two EDMA channel controllers (DSS_TPCC0 and DSS_TPCC1) on the device:
• DSS_TPCC0 (EDMA TPCC0) has two transfer controllers: DSS_TPTC0 (EDMA TPTC0) and
DSS_TPTC1 (EDMA TPTC1)
• DSS_TPCC1 (EDMA TPCC1) has two transfer controllers: DSS_TPTC2 (EDMA TPTC2) and
DSS_TPTC3 (EDMA TPTC3)
NOTE: The 18xx device does not support the region interrupt feature of the EDMA peripheral. Only
the global interrupt feature of the EDMA module is supported.
Table 2-29. DSS_TPCC Configuration
DSS_TPCC0 (EDMA TPCC0)
DSS_TPCC1 (EDMA TPCC1)
Number of MSS_DMA channels
64
64
Number of PaRAM entires
128
256
Number of QDMA channels
8
8
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 231
18xx Integration
www.ti.com
Table 2-29. DSS_TPCC Configuration (continued)
DSS_TPCC0 (EDMA TPCC0)
DSS_TPCC1 (EDMA TPCC1)
Number of event queues
2
2
Memory protection existence
No
No
Channel mapping
No
No
Number of TCs (transfer controllers)
2
2
Table 2-30. DSS_TPTC Configuration
232
DSS_TPTC[0-1]
DSS_TPTC[2-3]
FIFO size
512 bytes
128 bytes
TR pipe depth
2
2
Bus width
16 bytes
16 bytes
16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
This section describes the integration of the module in the device, including information about clocks,
resets, and hardware requests.
Figure 3-13 and Figure 3-14 show the EDMA controller integration.
Figure 2-30. EDMA Controller Integration (1 of 2)
Peripherals
Enhanced DMA
Controller
DSS_TPTC1
Master Read
EDMA_TPCC_IRQ_ERR
To C674x-INTC
and
Master CR4F
TPCC_IRQ_Completion
Master Write
PCR 32 bit
CFG_Slave
128 bit
128 bit
Completion
Port
TPTC_GCLK
TPTC_RST
PCR 32bit
SCR 128bit
Transfer request
CFG_Slave
Device
modules
DSS_TPTC0
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Completion
Master Read
128 bit
Master Write
Completion
Port
TPTC_GCLK
TPTC_RST
128 bit
Transfer request
CFG_Slave
DSS_TPCC0
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Global_Completion
DMA requests
from Different
sources
EDMA_REQ[63:0]
DSPSS_CLK
PRCM
DSS_TPTC0
Transfer request
DSS_TPTC1
Master Interface
Reset_n
TPTC_GCLK
TPTC_RST
Completion
Port[6:0]
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
233
18xx Integration
www.ti.com
Figure 2-31. EDMA Controller Integration (2 of 2)
Peripherals
Enhanced DMA
Controller
DSS_TPTC3
Master Read
EDMA_TPCC_IRQ_ERR
To C674x-INTC
and
Master CR4F
TPCC_IRQ_Completion
Master Write
PCR 32 bit
CFG_Slave
128 bit
128 bit
Completion
Port
TPTC_GCLK
TPTC_RST
PCR 32bit
SCR 128bit
Transfer request
CFG_Slave
Device
modules
DSS_TPTC2
EDMA_TPCC_IRQ_ERR
TPCC_IRQ_Completion
Master Read
128 bit
Master Write
Completion
Port
TPTC_GCLK
TPTC_RST
128 bit
Transfer request
DSS_TPCC1
CFG_Slave
EDMA_TPCC_IRQ_ERR
DSS_TPTC2
Transfer request
DSS_TPTC3
Master Interface
TPCC_IRQ_Global_Completion
DMA requests
from Different
sources
EDMA_REQ[63:0]
DSPSS_CLK
PRCM
Reset_n
Completion
Port[6:0]
TPTC_GCLK
TPTC_RST
2.6.13.2 EDMA Request Map
Table 2-31. EDMA Request Map
Request Number
Hardware Event
DSS_TPCC0 (EDMA TPCC0) DMA
0
DSS_CBUFF_DMA_REQ_0
1
DSS_CBUFF_DMA_REQ_1
2
DSS_CBUFF_DMA_REQ_2
3
DSS_CBUFF_DMA_REQ_3
4
DSS_CBUFF_DMA_REQ_4
5
DSS_CBUFF_DMA_REQ_5
6
DSS_CBUFF_DMA_REQ_6
7
RESERVED
234 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-31. EDMA Request Map (continued)
Request Number
Hardware Event
8
Frame Start/DSS_DMMSWINT9/DSS_DMMSWINT39
9
Chirp Available/DSS_DMMSWINT11/DSS_DMMSWINT43
10
RESERVED
11
RESERVED
12
RESERVED
13
RESERVED
14
RESERVED
15
RESERVED
16
RESERVED
17
DSS_FFT_ACC_CHANNEL_TRIGGER_0
18
DSS_FFT_ACC_CHANNEL_TRIGGER_1
19
DSS_FFT_ACC_CHANNEL_TRIGGER_2
20
DSS_FFT_ACC_CHANNEL_TRIGGER_3
21
DSS_FFT_ACC_CHANNEL_TRIGGER_4
22
DSS_FFT_ACC_CHANNEL_TRIGGER_5
23
DSS_FFT_ACC_CHANNEL_TRIGGER_6
24
DSS_FFT_ACC_CHANNEL_TRIGGER_7
25
DSS_FFT_ACC_CHANNEL_TRIGGER_8
26
DSS_FFT_ACC_CHANNEL_TRIGGER_9
27
DSS_FFT_ACC_CHANNEL_TRIGGER_10
28
DSS_FFT_ACC_CHANNEL_TRIGGER_11
29
DSS_FFT_ACC_CHANNEL_TRIGGER_12
30
DSS_FFT_ACC_CHANNEL_TRIGGER_13
31
DSS_FFT_ACC_CHANNEL_TRIGGER_14
32
DSS_FFT_ACC_CHANNEL_TRIGGER_15
33
DSS_MCRC_DMA_REQ_0
34
DSS_MCRC_DMA_REQ_1
35
FRC_EVENT_GEN_0
36
FRC_EVENT_GEN_1
37
FRC_EVENT_GEN_2
38
FRC_EVENT_GEN_3
39
RESERVED
40
LOGICAL_FRAME_START/DSS_DMMSWINT10/DSS_DMMSWINT40
41
ADC_DATA_VALID_FALL/DSS_DMMSWINT12/DSS_DMMSWINT44
42
UART_DMA_REQ_0
43
UART_DMA_REQ_1
44
DMMSW_INT_13
45
DMMSW_INT_14
46
DMMSW_INT_15
47
DMMSW_INT_16
48
DMMSW_INT_17
49
GPIO_0_host_interrupt
50
GPIO_1_host_interrupt
51
GPIO_2_host_interrupt
52
RTI1_DMA_REQ_0
53
RTI1_DMA_REQ_1
54
RTI1_DMA_REQ_2
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx 235
18xx Integration
www.ti.com
Table 2-31. EDMA Request Map (continued)
Request Number
Hardware Event
55
RTI1_DMA_REQ_3
56
RTI2_DMA_REQ_0
57
RTI2_DMA_REQ_1
58
RTI2_DMA_REQ_2
59
RTI2_DMA_REQ_3
60
RESERVED
61
RESERVED
62
RESERVED
63
DMMSW_INT_18
DSS_TPCC1 (EDMA TPCC1) MSS_DMA
0
DSS_CBUFF_DMA_REQ_0
1
DSS_CBUFF_DMA_REQ_1
2
DSS_CBUFF_DMA_REQ_2
3
DSS_CBUFF_DMA_REQ_3
4
DSS_CBUFF_DMA_REQ_4
5
DSS_CBUFF_DMA_REQ_5
6
DSS_CBUFF_DMA_REQ_6
7
RESERVED
8
FRAME_START/DSS_DMMSWINT19/DSS_DMMSWINT39
9
CHIRP_AVIALABLE/DSS_DMMSWINT21/DSS_DMMSWINT43
10
RESERVED
11
RESERVED
12
RESERVED
13
RESERVED
14
RESERVED
15
RESERVED
16
RESERVED
17
DSS_FFT_ACC_CHANNEL_TRIGGER_0
18
DSS_FFT_ACC_CHANNEL_TRIGGER_1
19
DSS_FFT_ACC_CHANNEL_TRIGGER_2
20
DSS_FFT_ACC_CHANNEL_TRIGGER_3
21
DSS_FFT_ACC_CHANNEL_TRIGGER_4
22
DSS_FFT_ACC_CHANNEL_TRIGGER_5
23
DSS_FFT_ACC_CHANNEL_TRIGGER_6
24
DSS_FFT_ACC_CHANNEL_TRIGGER_7
25
DSS_FFT_ACC_CHANNEL_TRIGGER_8
26
DSS_FFT_ACC_CHANNEL_TRIGGER_9
27
DSS_FFT_ACC_CHANNEL_TRIGGER_10
28
DSS_FFT_ACC_CHANNEL_TRIGGER_11
29
DSS_FFT_ACC_CHANNEL_TRIGGER_12
30
DSS_FFT_ACC_CHANNEL_TRIGGER_13
31
DSS_FFT_ACC_CHANNEL_TRIGGER_14
32
DSS_FFT_ACC_CHANNEL_TRIGGER_15
18
RESERVED
19
RESERVED
20
RESERVED
21
RESERVED
236 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-31. EDMA Request Map (continued)
Request Number
Hardware Event
22
RESERVED
23
RESERVED
24
RESERVED
25
RESERVED
26
RESERVED
27
RESERVED
28
RESERVED
29
RESERVED
30
RESERVED
31
RESERVED
32
RESERVED
33
DSS_MCRC_DMA_REQ_0
34
DSS_MCRC_DMA_REQ_1
35
FRC_EVENT_GEN_0
36
FRC_EVENT_GEN_1
37
FRC_EVENT_GEN_2
38
FRC_EVENT_GEN_3
39
RESERVED
40
LOGICAL_FRAME_START/DSS_DMMSWINT20/DSS_DMMSWINT40
41
ADC_DATA_VALID_FALL/DSS_DMMSWINT22/DSS_DMMSWINT44
42
UART_DMA_REQ_0
43
UART_DMA_REQ_1
44
DMMSW_INT_23
45
DMMSW_INT_24
46
DMMSW_INT_25
47
DMMSW_INT_26
48
DMMSW_INT_27
49
GPIO_0_host_interrupt
50
GPIO_1_host_interrupt
51
GPIO_2_host_interrupt
52
RTI1_DMA_REQ_0
53
RTI1_DMA_REQ_1
54
RTI1_DMA_REQ_2
55
RTI1_DMA_REQ_3
56
RTI2_DMA_REQ_0
57
RTI2_DMA_REQ_1
58
RTI2_DMA_REQ_2
59
RTI2_DMA_REQ_3
60
RESERVED
61
RESERVED
62
RESERVED
63
DMMSW_INT_28
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
16xx/18xx
237
18xx Integration
www.ti.com
2.6.14 Error Signaling Module (MSS_ESM/DSS_ESM)
The 18xx device has two instances of the Error Signaling Module (MSS_ESM/DSS_ESM), shown in
Figure 3-15.
Figure 2-32. 18xx MSS_ESM/DSS_ESM Integration Diagram
Table 3-15 shows the mapping on the input error inputs to the ESM module from various error sources
available for hardware diagnostics within the device.
Table 2-32. MSS_ESM Mapping
MSS_ESM Group 1
Channel Type
Description
63
ANA_LIMP_MODE
Error Signal
Error signal at device boot-up, if the CLK monitor finds the
REF CLK to be outside the permissible range of frequency
62
MSS_DCCB_ERR
Error Signal
MSS_DCCB frequency comparison error
61
MAILBOX_BSS2MSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_BSS2MSS
60
MAILBOX_BSS2MSS _REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_BSS2MSS
59
MAILBOX_MSS2BSS _FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_MSS2BSS
58
MAILBOX_MSS2BSS _REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_MSS2BSS
57
BSS_CRITICAL_ERR
Error Signal
BSS critical Error Indication.
Mask control to be configured in IRQ_CTL for individual error
signals.
56
Reserved
Reserved
Reserved
238 16xx/18xx
SWRU522D – May 2017 – Revised September 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
18xx Integration
www.ti.com
Table 2-32. MSS_ESM Mapping (continued)
MSS_ESM Group 1
Channel Type
Description
55
CLOCK_SUPPLY_ERR
Error Signal
Clock and Supply Errors from Analog.
Mask control to be configured in IRQ_CTL for individual error
signals
54
Reserved
Reserved
Reserved
53
MAILBOX_DSS2MSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_DSS2MSS
52
MAILBOX_DSS2MSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_DSS2MSS
51
Reserved
Reserved
Reserved
50
Reserved
Reserved
Reserved
49
MSS_MIBSPIB_MEM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_MIBSPIB multi-buffer
(RXRAM/TXRAM)
48
MSS_MCRC_ERR
Error Signal
MSS_MCRC Comparison Error
47
Reserved
Reserved
Reserved
46
Reserved
Reserved
Reserved
45
MSS_MIBSPIB_MEM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_MIBSPIB multibuffer (RXRAM/TXRAM)
44
Reserved
Reserved
Reserved
43
MAILBOX_MSS2DSS_FATAL_ERR
Error Signal
Multi-bit error indication from MAILBOX_MSS2DSS
42
MAILBOX_MSS2DSS_REPAIR_ERR
Alert Signal
Single-bit error/repair indication from MAILBOX_MSS2DSS
41
DSS_ESM_GP1_ERR
Error Signal
DSS_ESM Low priority Interrupt
40:39
Reserved
Reserved
Reserved
38
DSS_CBUFF_SAFETY_ERR
Error Signal
CHIRP ERROR or CRC ERROR from DSS_CBUFF
37
DSS_ESM_GP2_ERR
Error Signal
DSS_ESM High priority Interrupt
36
DSS_TPTC1_WR_MPU_ERR
Error Signal
DSS_TPTC1 write port MPU error
35
DSS_TPTC1_RD_MPU_ERR
Error Signal
DSS_TPTC1 read port MPU error
34
HVMODE_ERR
Error Signal
Error indication from IO Supply (Supply detector for dualvoltage IOs)
33
MSS_DCAN_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_DCAN Message
RAM (FRAM/SRAM)
32
MSS_TCMA_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for Cortex R4F MSS_TCMA
31
Reserved
Reserved
Reserved
30
MSS_DCCA_ERR
Error Signal
MSS_DCCA frequency comparison error
29
DSS_TPTC0_WR_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
28
MSS_TCMB1_REPAIR_ERR
Alert Signal
Single-bit error/reserved indication for MSS_TCMB1
27
MSS_STC_ERR
Error Signal
MSS_STC Error indication for MSS Cortex R4F
26
MSS_TCMB0_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_TCMB0
25
MSS_MIBSPIA_MEM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_MIBSPIA multibuffer (RXRAM/TXRAM)
24
MSS_DMA2_MEM_PARITY_ERR
Error Signal
Parity Error for MSS_DMA2 memory
23
MSS_DMA2_MPU_ERR
Error Signal
Error indication from MPU of MSS_DMA2
22
FRC_COMPARE_ERR
Error Signal
Lockstep comparison error from Free running Counter (FRC)
in BSS
21
MSS_DCAN_RAM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_DCAN Message Memory
(FRAM/SRAM)
20
MSS_VIM_RAM_REPAIR_ERR
Alert Signal
Single-bit error/repair indication for MSS_VIM_RAM
19
Reserved
Reserved
Reserved
18
DSS_TPTC0_RD_MPU_ERR
Error Signal
DSS_TPTC0 read port MPU error
17
MSS_MIBSPIA_MEM_FATAL_ERR
Error Signal
Multi-bit error indication for MSS_MIBSPIA (RXRAM/TXRAM)
16
MSS_SECURE_RAM_FATAL_ERR
Error Signal
Multi-bit uncorrectable error indication for
MSS_DTHE/SECURE_RAM
15
MSS_VIM_RAM_FATAL_ERR
Error Signal
Multi-bit uncorrectable error indication for MSS_VIM_RAM
SWRU522D – May 2017 – Revised