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Texas Instruments PGA400-Q1 EVM (Rev. A) User guides
Preface
SLDU010A – March 2012 – Revised August 2014
Read This First
About This Manual
This user’s guide describes the characteristics, operation, and use of the PGA400-Q1EVM. An EVM
overview, graphical user-interface (GUI) description, interface requirements, and complete schematic are
included in this document.
How to Use This Manual
This document contains the following chapters:
1. Chapter 1: Power Supply Requirements and Connections
2. Chapter 2: Jumper Settings
3. Chapter 3: Sensor Inputs and Simulators
4. Chapter 4: PGA400-Q1 VOUT1 and VOUT2 Output Circuitry
5. Chapter 5: PGA400-Q1 Communication interfaces
6. Chapter 6: Controlling the PGA400-Q1 Memory Spaces with the GUI
7. Chapter 7: Controlling the PGA400-Q1 Functions with the GUI
8. Chapter 8: PGA400-Q1 EVM Schematics and Layout Drawings
EVM Overview
Features
The EVM includes the following features:
• Single 12-VDC power-supply input for basic operation
• Resistive and capacitive sensor simulators
• PC Control with a GUI and USB communications board
• One-wire-interface (OWI) activation and communication circuitry
• RS-232 transceiver for UART testing and debug
Introduction
The PGA400-Q1 device is a generic-sensor interface integrated circuit (IC) for resistive and capacitive
sensors. The device features a configurable analog front-end (AFE) with diagnostics, sigma-delta ADC,
8051 microcontroller, DACs, SPI, I2C, and a one-wire interface (OWI).
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1
Chapter 1
SLDU010A – March 2012 – Revised August 2014
Power Supply Requirements and Connections
The PGA400-Q1EVM has only one main 9-VDC to 12-VDC power connector that supplies power to the
entire board. The user is required to connect a power supply to the banana jacks, P1 VPWR and P3 GND
or use the screw terminal P2. Figure 1-1 shows an example using the banana jack connections.
Figure 1-1. Minimum Power Connections to the PGA400-Q1 EVM
Configure the power supply based on the following table:
CONNECTION
VOLTAGE
CURRENT LIMIT
VPWR
9 – 12 VDC
100 mA
When powered, the D30 LED should light up and the EVM should draw between 30 and 55 mA depending
on what state of operation the device is in.
2
Power Supply Requirements and Connections
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Controlling and Powering the R2D2 EVM through TI-GER USB Board
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1.1
Controlling and Powering the R2D2 EVM through TI-GER USB Board
The PGA400-Q1 EVM is shipped with a TI-GER USB communication board that provides a link from the
PC controlled GUI (see Chapter 6) to the EVM. The user must connect the TI-GER board to the PGA400Q1 by connecting the 15 × 2 100-mil female header on the TI-GER board to P6, the male 15 × 2 header
on the PGA400-Q1 EVM. The TI logo on the TI-GER board should face up when it is plugged in. Figure 12 shows the TI-GER board connected to the PGA400-Q1 EVM.
Figure 1-2. Connecting the TI-GER USB Communication Board to the PGA400-Q1 EVM
1.2
Power Supply LEDs
LEDs are installed in several places on the EVM to provide the user an indication that power-supplies are
connected correctly. The VDD and VP_OTP connections on the PGA400-Q1 device have LEDs to indicate
that power is applied. Also, two LEDS indicate that the USB power supplies on the TI-GER boards are
present.
Table 1-1. Power Supply LED Connections
LED
SUPPLY
D2
TI-GER 3.3 V
D3
TI-GER 5 V
D30
PGA400-Q1 VDD
D31
PGA400-Q1 VP_OTP
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3
Chapter 2
SLDU010A – March 2012 – Revised August 2014
Jumper Settings
Several jumpers are located on the board used to configure the connections to the PGA400-Q1 device
and the remaining part of the EVM. Although the jumpers are installed to default settings in the factory, TI
recommends that the user verify that the shunts are installed to the default settings before powering on
the EVM. Section 2.1 lists the default settings and effects.
2.1
Default Jumper Settings
Figure 2-1. Default Jumper Settings
4
Jumper Settings
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Table 2-1. Default Jumper Settings
REFERENCE
JUMPER POSITION
FUNCTION
JP1
Closed
The VDD power-supply input on the PGA400-Q1 device is supplied from the 5-V
regulator on the EVM.
JP2
Open
The VP_OTP power-supply input on the PGA400-Q1 device is not connected to
the 7.5-V regulator on the EVM.
JP3
Closed
The CS signal from the TI-GER board is connected to the PGA400-Q1 device in
the U1 socket and to the P4 header.
JP4
Closed
The MISO signal from the TI-GER board is connected to the PGA400-Q1 device in
the U1 socket and to the P4 header.
JP5
Closed
The MOSI signal from the TI-GER board is connected to the PGA400-Q1 device in
the U1 socket and to the P4 header.
JP6
Closed
The SCLK signal from the TI-GER board is connected to the PGA400-Q1 device in
the U1 socket and to the P4 header.
JP7
Closed
The TXD signal from the PGA400-Q1 device is connected to the U23 RS-232
transceiver.
JP8
Closed
The RXD signal from the PGA400-Q1 device is connected to the U23 RS-232
transceiver.
JP9
Closed
The VIN1P input filter is connected to the DAC MUX and variable resistive bridge.
JP10
Closed
The VIN1P signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
JP11
Closed
The VIN1N input filter is connected to the DAC MUX and variable resistive bridge.
JP12
1-2
The VIN1N signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
JP13
Closed
The TIP signal on the PGA400-Q1 device is connected to the DAC MUX.
JP14
Closed
The TIN signal on the PGA400-Q1 device is connected to the DAC MUX.
JP15
Closed
The VIN3 signal on the PGA400-Q1 device is connected to the DAC MUX.
JP16
Closed
The VIN2P input filter is connected to the DAC MUX and variable resistive bridge.
JP17
Closed
The VIN2P signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
JP18
Closed
The VIN2N input filter is connected to the DAC MUX and variable resistive bridge.
JP19
Closed
The VIN2N signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
JP22
Closed
The VOUT1 signal on the PGA400-Q1 device is connected to the DAC Output
MUX and to the P4 header.
JP23
Closed
The VOUT2 signal on the PGA400-Q1 device is connected to the DAC Output
MUX and to the P4 header.
JP26
1-2
The U23 RS-232 Transceiver TX signal is connected to the PGA400-Q1 device.
JP27
1-2
The U23 RS-232 Transceiver RX signal is connected to the PGA400-Q1 device.
JP28
Closed
The SCL signal from the TI-GER is connected to the GPIO_3 signal on the
PGA400-Q1 device.
JP29
Closed
The SDA signal from the TI-GER is connected to the GPIO_1 signal on the
PGA400-Q1 device.
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Jumper Settings
5
Default Jumper Settings
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2.1.1 Jumper Setting Options
Table 2-2 lists the function of each specific jumper setting on the EVM.
Table 2-2. Jumper Setting Options
REFERENCE
JUMPER SETTING (1)
JP1
FUNCTION
The VDD power-supply input on the PGA400-Q1 device is supplied from the 5-V
regulator on the EVM.
The VDD power-supply input on the PGA400-Q1 device is not supplied from the 5-V
regulator on the EVM and can be connected to an external 5-V power supply.
JP2
The VP_OTP power-supply input on the PGA400-Q1 device is connected to the 7.5-V
regulator on the EVM.
The VP_OTP power-supply input on the PGA400-Q1 device is not connected to the
7.5-V regulator on the EVM.
JP3
The CS signal from the TI-GER board is connected to the PGA400-Q1 device in the U1
socket and to the P4 header.
The CS signal from the TI-GER board is not connected to the PGA400-Q1 device in
the U1 socket and is only connected to the P4 header.
JP4
The MISO signal from the TI-GER board is connected to the PGA400-Q1 device in the
U1 socket and to the P4 header. The MISO signal from the TI-GER board is not
connected to the PGA400-Q1 device in the U1 socket and is only connected to the P4
header.
JP5
The MOSI signal from the TI-GER board is connected to the PGA400-Q1 device in the
U1 socket and to the P4 header.
The MOSI signal from the TI-GER board is not connected to the PGA400-Q1 device in
the U1 socket and is only connected to the P4 header.
JP6
The SCLK signal from the TI-GER board is connected to the PGA400-Q1 device in the
U1 socket and to the P4 header.
The SCLK signal from the TI-GER board is not connected to the PGA400-Q1 device in
the U1 socket and is only connected to the P4 header.
JP7
The TXD signal from the PGA400-Q1 device is connected to the U23 RS-232
transceiver.
The TXD signal from the PGA400-Q1 device is not connected to the U23 RS-232
transceiver.
JP8
The RXD signal from the PGA400-Q1 device is connected to the U23 RS-232
transceiver.
The RXD signal from the PGA400-Q1 device is not connected to the U23 RS-232
transceiver.
JP9
The VIN1P input filter is connected to the DAC MUX and variable resistive bridge.
The VIN1P input filter is not connected to the DAC MUX and variable resistive bridge.
An external stimulus voltage can be applied that passes through the input filter to the
PGA400-Q1 device.
JP10
JP11
R
C
The VIN1P signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
R
C
The VIN1P signal on the PGA400-Q1 device is connected to the capacitive sensor
simulator on the EVM.
R
C
The VIN1P signal on the PGA400-Q1 device is not connected to anything on the EVM.
The VIN1N input filter is connected to the DAC MUX and variable resistive bridge.
The VIN1N input filter is not connected to the DAC MUX and variable resistive bridge.
An external stimulus voltage can be applied that passes through the input filter to the
PGA400-Q1 device.
(1)
6
Indicates the corresponding pins that are shorted or closed.
Jumper Settings
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Table 2-2. Jumper Setting Options (continued)
REFERENCE
JP12
JUMPER SETTING (1)
FUNCTION
R
C
The VIN1N signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
R
C
The VIN1N signal on the PGA400-Q1 device is connected to the capacitive sensor
simulator on the EVM.
R
C
The VIN1P signal on the PGA400-Q1 device is not connected to anything on the EVM.
JP13
The TIP signal on the PGA400-Q1 device is connected to the DAC MUX and the P4
header.
The TIP signal on the PGA400-Q1 device is not connected to anything on the EVM.
The TIP signal on the P4 header is still connected to the DAC MUX.
JP14
The TIN signal on the PGA400-Q1 device is connected to the DAC MUX.
The TIN signal on the PGA400-Q1 device is not connected to anything on the EVM.
The TIN signal on the P4 header is still connected to the DAC MUX.
JP15
The VIN3 signal on the PGA400-Q1 device is connected to the DAC MUX.
The VIN3 signal on the PGA400-Q1 device is not connected to anything on the EVM.
JP16
The VIN2P input filter is connected to the DAC MUX and variable resistive bridge.
The VIN2P input filter is not connected to the DAC MUX and variable resistive bridge.
An external stimulus voltage can be applied that passes through the input filter to the
PGA400-Q1 device.
JP17
R
C
The VIN2P signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
R
C
The VIN2P signal on the PGA400-Q1 device is connected to the capacitive sensor
simulator on the EVM.
R
C
The VIN2P signal on the PGA400-Q1 device is not connected to anything on the EVM.
JP18
The VIN2N input filter is connected to the DAC MUX and variable resistive bridge.
The VIN2N input filter is not connected to the DAC MUX and variable resistive bridge.
An external stimulus voltage can be applied that passes through the input filter to the
PGA400-Q1 device.
JP19
R
C
The VIN2N signal on the PGA400-Q1 device is connected to the resistive bridge
sensor simulators and input filters on the EVM.
R
C
The VIN2N signal on the PGA400-Q1 device is connected to the capacitive sensor
simulator on the EVM.
R
C
The VIN2N signal on the PGA400-Q1 device is not connected to anything on the EVM.
JP22
The VOUT1 signal on the PGA400-Q1 device is connected to the DAC Output MUX ,
the OWI activation circuit, and the P4 header.
The VOUT1 signal on the PGA400-Q1 device is not connected to the DAC Output
MUX and the OWI activation circuit. The VOUT1 signal on the P4 header is still
connected to the DAC Output MUX.
JP23
The VOUT2 signal on the PGA400-Q1 device is connected to the DAC Output MUX ,
and the P4 header.
The VOUT2 signal on the PGA400-Q1 device is not connected to the DAC Output
MUX. The VOUT2 signal on the P4 header is still connected to the DAC Output MUX.
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Table 2-2. Jumper Setting Options (continued)
REFERENCE
JP26
JP27
JP28
JUMPER SETTING (1)
FUNCTION
1
3
The TXD signal on the PGA400-Q1 device is connected to the RS-232 transceiver.
1
3
The TXD input of the RS-232 transceiver is not connected to the PGA400-Q1 device
and is open so an external signal can be connected.
1
3
The RXD signal on the PGA400-Q1 device is connected to the RS-232 transceiver.
1
3
The RXD input of the RS-232 transceiver is not connected to the PGA400-Q1 device
and is open so an external signal can be connected.
The GPIO_3 signal on the PGA400-Q1 device is connected to the SCL signal on the
TI-GER board and also to the P4 header.
The GPIO_3 signal on the PGA400-Q1 device is not connected to the SCL signal on
the TI-GER board. The SCL signal from the TI-GER board is still connected to the P4
header.
JP29
The GPIO_1 signal on the PGA400-Q1 device is connected to the SDA signal on the
TI-GER board and also to the P4 header.
The GPIO_1 signal on the PGA400-Q1 device is not connected to the SDA signal on
the TI-GER board. The SDA signal from the TI-GER board is still connected to the P4
header.
8
Jumper Settings
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Chapter 3
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Sensor Inputs and Simulators
The PGA400-Q1 device has two main-sensor AFEs in the sensor-signal conditions. One sensor is
targeted towards resistive or voltage based sensors and the other sensor is targeted for capacitive
sensors. The PGA400-Q1 EVM is equipped with simple circuits to simulate the basic functionality of these
different sensors. Figure 3-1 shows a simplified block diagram of the sensor simulators on the PGA400Q1 EVM.
DAC1
M
U
X
x2
TIP
NC
Input
Filter
VIN1P
VBRG
ICAP1
M
U
X
ADC3
DAC2
x2
M
U
X
DAC3
x2
M
U
X
TIN
NC
VIN3
NC
Input
Filter
Input
Filter
VIN1N
VIN2P
VBRG
ICAP2
M
U
X
ADC4
DAC4
M
U
X
x2
NC
NC
Input
Filter
VIN2N
NC = No Connect
Red Text = Electrical Net
Figure 3-1. Simplified Block Diagram of PGA400-Q1 Input Circuitry
3.1
Resistive Bridge Sensors
A resistive bridge sensor on the PGA400-Q1 EVM can be simulated in two main ways. The first way is a
simple resistive bridge with two variable legs that can be used to adjust the voltage to the VIN1P and
VIN1N and the VIN2P and VIN2N inputs. The second uses 16-bit DACs and ADCs to set and measure
the voltage at the inputs. Either of these simulators can be fed through an input filter and then into the
PGA400-Q1 inputs.
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Resistive Bridge Sensors
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3.1.1 Variable Resistive Bridge
The EVM is equipped with a variable resistive bridge that can be used to adjust the voltage at the inputs
of the PGA400-Q1 device. The bridge is biased with the VBRG regulator from the PGA400-Q1 device.
The resistance of each leg of the bridge varies from 17.5 kΩ to 22 kΩ. Figure 3-2 shows the channel-1
resistive bridge that is used to vary the voltage to the VIN1P and VIN1N inputs. The channel 2 resistive
bridge is identical.
VBRG
R9
10k
R10
10k
VIN1P_MB
VIN1P_MB*
VIN1N_MB
R12
R13
0.0R
0.0R
RPotR14
5k
VIN1N_MB*
R15 RPot
5k
R17
7.5k
R18
7.5k
GND
Figure 3-2. Channel-1 Resistive Bridge Sensor Simulator
10
Sensor Inputs and Simulators
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3.1.2 Buffered DAC Outputs
The second way to excite the voltage inputs to the PGA400-Q1 device is to use the buffered DAC outputs
on the EVM. The DAC8574, a four-channel 16-bit DAC, is used to generate voltage signals that can be
used to excite the VIN1P, VIN1N, VIN2P, and VIN2N inputs. When the DAC MUX is set to the VIN1P,
VIN1N, VIN2P, and VIN2N sensor inputs, the DAC buffers over-drive the voltage that the resistive bridge
was previously producing. The buffered DAC voltage is measured with the ADS1100, 16-bit ADCs, and
then adjusted to serve out errors. The DACs are controlled with the GUI (see Chapter 6). Figure 3-3
shows the DACs and the DAC buffers.
C30
2.2nF,16V,X7R
1
2
R24
1k
R25
1k
8
V5
GND
2
V5
1
A
3
4
1
DAC1_1
U5A
OPA2335UA
2
C35
1uF,16V,X7R
DAC1_1_BUF
GND
C33
2.2nF,16V,X7R
1
2
GND
R32
C36
V5
0.1uF,16V,X7R
2
1
R31
1k
1k
8
V5
12
4
GND
6
GND V5
16
15
14
13
VREFH
SDA
SCL
VOUTA
VOUTB
VOUTC
VOUTD
A4
A2
A1
A0
GND
11
10
LDAC
VREFL
3
DAC1_4
DAC1_3
DAC1_2
DAC1_1
1
2
7
8
DAC1_2_BUF
U5B
OPA2335UA
GND
C38
2.2nF,16V,X7R
1
2
R36
1k
9
5
7
B
5
R35
1k
6
MB_SDA
MB_SCL
DAC1_2
4
U8
DAC8574
IOVDD
VDD
GND
8
V5
GND
GND
2
DAC1_3
1
A
3
1
4
V5
DAC1_3_BUF
U10A
OPA2335UA
C42
1uF,16V,X7R
2
GND
C41
2.2nF,16V,X7R
1
2
GND
R40
1k
R41
1k
V5
8
GND
6
5
7
B
4
DAC1_4
DAC1_4_BUF
U10B
OPA2335UA
GND
Figure 3-3. 4-Channel DAC8574 and OPA2335 Buffers
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3.1.3 Input Filters
2
Both the buffered DAC outputs and the resistive bridge outputs feed through the input filter on the EVM
before they connect to the inputs to the PGA400-Q1 device. The input filter is comprised of a commonmode and differential filter made from ferrite beads and capacitors. When the EVM is delivered to the
customer, the ferrite beads L1 through L4 are populated with 49-Ω resistors so that the filters work as
simple RC low-pass filters. If desired, the resistors can be replaced with ferrite beads that meet the
requirements of the final customer system. Similarly, the EVM has an unpopulated footprint for an X2Y
capacitor to replace the two common-mode and single differential capacitor. To use the X2Y capacitor,
uninstall the three populated filter capacitors on the desired channels and install a single X2Y capacitor.
Figure 3-4 shows the input filters on the EVM.
C24
1nF
GND
VIN1P_R
JP9
L1
JP10
1
VIN1P_MB
VIN1P_C
51R
2
C25
10nF - X2Y
DNI
1
C26
0.01uF
GND
GND
JP12
L2
VIN1N_C
2
VIN1N_R
VIN1N_MB
VIN1P
JP11
51R
C27
1nF
1
VIN1N
GND
2
51-Ω Resistors are Installed Instead of Ferrite Beads L1 to L4. Remove the 51-Ω resistors and replace with Ferrites if desired.
C28
1nF
GND
VIN2P_R
JP16
L3
JP17
1
VIN2P_MB
VIN2P_C
C29
10nF - X2Y
DNI
2
51R
1
C31
0.01uF
VIN2N_R
JP18
L4
GND
GND
JP19
VIN2N_C
2
VIN2N_MB
VIN2P
51R
C32
1nF
1
VIN2N
GND
Figure 3-4. Input Filtering and Selection on the PGA400-Q1 EVM
12
Sensor Inputs and Simulators
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3.2
Capacitive Sensors
The capacitive sensors on the PGA400-Q1 EVM can only be simulated in one way. This method uses a
fixed reference capacitor on one leg, and then a fixed capacitor in parallel with a variable trim capacitor on
the other leg. The reference leg capacitance is set to 56 pF, and the variable leg is adjustable from 35 to
80 pF. Figure 3-5 shows the circuit for the capacitive sensor simulator.
C18
7.0-50pF
Cap Var
C19
30pF
VIN2P_C
ICAP2
C20
56pF
VIN2N_C
C21
7.0-50pF
Cap Var
C22
30pF
VIN1P_C
ICAP1
C23
56pF
VIN1N_C
Figure 3-5. Capacitive Sensor Simulator
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13
Chapter 4
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PGA400-Q1 VOUT1 and VOUT2 Output Circuitry
The PGA400-Q1 device has two DAC outputs, VOUT1 and VOUT2, which serve as the main output for
the PGA400-Q1 device. Simple circuitry including output filtering and ADC monitoring of the DAC outputs
are present on the EVM. The VOUT1 output also has circuitry that is used for the OWI activation as well
as the OWI communication.
5V
200R
49.9 k
7.5 V
USB-TX
OWI
Activation
5V
49.9 k
5R
USB-RX
5V
49.9 k
M
U
X
VOUT1
NC
ADC1
100 pF
5V
49.9 k
M
U
X
VOUT1
ADC2
NC
100 pF
Figure 4-1. Simplified Block Diagram of PGA400-Q1 Output Circuitry
4.1
Output Filtering for VOUT1 and VOUT2
Both the VOUT1 and VOUT2 outputs on the PGA400-Q1 device have simple output filtering comprised of
a resistive pull-up and a capacitor to GND. The capacitor is used to form a low-pass filter with the output
impedance of the VOUT1 and VOUT2 DACs. The resistive pull-up is primarily used to fill the requirements
for an external pull-up in OWI mode. Figure 4-2 shows the output filters on the VOUT1 and VOUT2 pins.
14
PGA400-Q1 VOUT1 and VOUT2 Output Circuitry
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V5
R47
49k
VOUT1_MB
2
VOUT1
JP22
1
C44
100pF,50V,,X7R
GND
V5
R48
49k
VOUT2
VOUT2_MB
2
JP23
1
C47
100pF,50V,,X7R
GND
Figure 4-2. VOUT1 and VOUT2 (PSSC DAC) Output Filtering
4.2
ADC Measurement of VOUT1 and VOUT2 DAC Outputs
The EVM has two ADCs that are used to monitor and report the voltage at the VOUT1 and VOUT2
outputs back to the GUI. The EVM uses two ADS1100, 16-bit ADCs, to monitor the two outputs. The
ADCs are enabled by configuring the PGA400-Q1 DAC output MUX to route the VOUT1 and VOUT2
outputs into the ADCs. The PGA400-Q1 DAC output MUX and the ADCs are all configurable with the GUI.
4.3
OWI Activation Circuitry — VOUT1
The VOUT1 pin on the PGA400-Q1 device is shared between the DAC output and the OWI transceiver.
When the PGA400-Q1 device is running in MCU mode, the only way to signal to the IC that the device
must enter OWI mode is to use a pull-up to bring the VOUT1 pin of the device to 7.5 V for at least 10 ms
before the VOUT1 pin is released back to the previous value. The OWI activation circuitry is comprised of
a simple PMOS pull-up to 7.5 V that is activated with a GPIO from the TI-GER USB communication board.
The GUI ensures that the PGA400-Q1 DAC output MUX is open while the OWI activation pulse occurs so
that the 5-V tolerant circuitry for the ADCs and the OWI transceiver are not damaged with the 7.5-V pulse.
Figure 4-3 shows the OWI activation circuit.
V7p5_MB
R64
1k
DZ4
5.1V Zener
R66
Q3
SI2319DS-T1-E3
1
R69
49.9k
2
220k
Q4
2N2222
OWI_T
DNI
C59
330nF,16V,X7R
R68
5R
OWI_ACT
GND
GND
VOUT1_MB
GND
Figure 4-3. OWI Activation Circuit
SLDU010A – March 2012 – Revised August 2014
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15
OWI Transceiver — VOUT1
4.4
www.ti.com
OWI Transceiver — VOUT1
When the OWI transceiver in the PGA400-Q1 device has been activated either by the OWI activation
pulse, or by a direct SPI write, the TI-GER board must communicate with the PGA400-Q1 device with the
proper OWI signals. A simple circuit is used to convert the two-signal TI-GER USART (TX/RX) into the
single wire OWI signal. The circuit operates in a way that the receiver is constantly monitoring even while
transmitting so a loop-bak feature is always by the GUI uses to ensure the correct information was
transmitted out of the TI-GER board. When a read is requested from the PGA400-Q1 device, an OWI
message is transmitted from the VOUT1 pin, which is then received by the TI-GER. No issues of possible
bus contention occur and the OWI transceiver circuit ensures that only the RX line is affected by the data
transmitted out of the PGA400-Q1 device. Figure 4-4 shows OWI transceiver circuit.
V5
RX
RX
5
1
U12
SN74LVC1G07
4
R44
49k
NC
V5
2
R45
49k
R46
200R
5
1
NC
GND
U13
SN74LVC1G07
2
TX
TX
3
4
OWI_TX_RX
3
OWI
GND
Figure 4-4. OWI Transceiver
16
PGA400-Q1 VOUT1 and VOUT2 Output Circuitry
SLDU010A – March 2012 – Revised August 2014
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Chapter 5
SLDU010A – March 2012 – Revised August 2014
PGA400-Q1 Communication Interfaces
The PGA400-Q1 device has several communication options including: SPI, I2C, OWI, and UART. All of
these communication interfaces and related circuitry are present on the PGA400-Q1 EVM.
5.1
SPI
SPI is the main communication method on the PGA400-Q1 device and must be used to initially select one
of the other communication methods (with the exception of the OWI activation pulse). Because the SPI
and I2C pins are shared on the TI-GER communication board, a communication MUX is used to
differentiate between the SPI and I2C functions on the EVM. By default the EVM powers up with the SPI
communication interface selected. The user must change the setting on the communication MUX to
change to I2C. The SPI signals can be monitored on the H1 header on the EVM. Figure 5-1 the SPI and
I2C communication MUX.
V5
C68
0.1uF.16V,X7R
1
2
GND
U26
R76
49.9k
SPI/I2C
SCLK_MB
SCL
SCLK_T
MISO_MB
SDA
MISO_T
GND
1
2
3
4
5
6
7
8
S
1B1
1B2
1A
2B1
2B2
2A
GND
VCC
OE
4B1
4B2
4A
3B1
3B2
3A
SN74CBTLV3257
GND
16
15
14
13
12
11
10
9
COMM_EN
CS_MB
CS_T
MOSI_MB
R78
49.9k
R77
49.9k
MOSI_T
R79
49.9k
GND
GND
GND
2
Figure 5-1. SPI and I C Communication MUX
SLDU010A – March 2012 – Revised August 2014
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I2C
5.2
www.ti.com
I2C
The I2C is the second most common protocol for communicating with the PGA400-Q1 device. The I2C
communication method must be selected in the PGA400-Q1 device by sending the appropriate SPI
commands before the communication will work. If the GUI is used to change from SPI to I2C mode, the
GUI will configure the SPI and I2C MUX to send the I2C signals to the PGA400-Q1 device. The I2C is also
used as the main communication method for the DAC and ADC peripherals on the EVM. To avoid any
conflicts between I2C signals meant for the PGA400-Q1 device and I2C signals meant for the EVM
peripherals. A second MUX is installed that splits the I2C signals between the PGA400-Q1 device and the
rest of the EVM. Figure 5-2 shows the circuit of this MUX.
C69
V5 0.1uF.16V,X7R
1
2
U27
SDA_PSSC9
SDA 10
MB_SDA 2
SCL_PSSC7
SCL 6
MB_SCL 4
NC1
COM1
NO1
NC2
COM2
NO2
TS5A23159
V+
IN1
IN2
GND
8
GND
1
5
I2C_MB/PSSC
3
R80
49.9k
GND
GND
2
Figure 5-2. PGA400-Q1 EVM I C MUX
5.3
OWI
During final system calibration, the OWI communication method is preferred because it allows for a threepin sensor module (Power, GND, VOUT/OWI). The OWI communication method can be selected in the
PGA400-Q1 device by either sending the appropriate SPI commands to place the device in OWI mode, or
by issuing the OWI activation pulse and writing software in the 8051 MCU to switch to OWI mode when
the OWI activation pulse is detected. The GUI can be used to create the OWI activation signal as well as
performing the direct SPI writes to place the EVM into OWI mode. If the GUI is used to send the signals to
enter OWI mode, then the EVM is automatically configured to route the TX and RX lines from the TI-GER
board through the OWI transceiver to the VOUT1 pin.
18
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UART
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5.4
UART
An RS-232 transceiver (MAX3221) is present on the EVM that can be used as a debugging interface from
the 8051 MCU to a host PC. The circuit connects the TXD and RXD pins on the PGA400-Q1 to the
MAX3221. The ±15-V RS-232 signals are routed to a standard DB-9 connector on the EVM. Figure 5-3
shows the RS-232 circuit.
TXD_MB
U23
3
C60
0.1uF,50V,X7R
7
V+
T1IN
JP26
11
TTL RX
VR1OUT
9
TTL TX
2
GND
RXD_MB
C1+
T1OUT
C61 GND
0.1uF,50V,X7R
13
CPU_RX
8
CPU_TX
JP27
232 TX
4
C62
0.1uF,50V,X7R5
R1IN
14
C2EN
CPU_TX
232 RX
C2+
~INVALID
1
CPU_RX
CPU_TX
C1-
C63
0.1uF,50V,X7R
6
J1
CPU_RX
FORCEON
FORCEOFF
VCC
GND
MAX3221ECAE
10
R70
12
16
V5
1
6
2
7
3
8
4
9
5
11
10
Female
GND
10R
15
C64
0.1uF,50V,X7R
GND
GND
Figure 5-3. RS-232 Transceiver
SLDU010A – March 2012 – Revised August 2014
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19
Chapter 6
SLDU010A – March 2012 – Revised August 2014
Controlling the PGA400-Q1 Memory Spaces with the GUI
The PGA400-Q1 EVM is controlled by the user through a PC with the TI-GER USB communication board
and associated GUI. The PGA400-Q1 EVM GUI provides ways to manipulate all of the register spaces
present inside the PGA400-Q1 device (TEST, ESFR, EEPROM, IRAM, OTP). The following sections
describe how to manipulate the register spaces.
6.1
Using the Register Grids to Manipulate the Register Spaces
Most of the register spaces have register grids associated with them that provide a simple way to read,
write, or read and write the registers in the grid. Eight buttons are associated with the grid operations:
ZERO GRID, DESELECT GRID, SAVE GRID, RECALL GRID, READ SELECTED, WRITE SELECTED,
READ ALL, and WRITE ALL. These buttons perform operations on whichever register grid is currently
displayed. For example, when the GUI first loads, the TEST register tab is displayed. If any of the
previously listed buttons are pressed the buttons perform operations on the TEST register space. The
following sections describe each of the grid functions.
6.1.1 ZERO GRID
The ZERO GRID button replaces the contents of the entire grid with 0.
6.1.2 DESELECT GRID
The DESELECT GRID button removes any selections that have been made in the grid without performing
any operations on the registers that were selected.
6.1.3 SAVE GRID
The SAVE GRID button takes the contents of the register grid and save them to a .TXT file. The data is
saved in comma-separated-values format.
6.1.4 RECALL GRID
The RECALL GRID button opens a prompt that allows the user to select a .TXT file that was produced
during the SAVE GRID operation and then loads the grid with the contents from the .TXT file.
6.1.5 READ SELECTED
The READ SELECTED button performs a read operation on any registers in the grid that have been
selected by clicking the desired register number. Any selected registers are displayed in blue.
6.1.6 WRITE SELECTED
The WRITE SELECTED button performs a write operation on any registers in the grid that have been
selected by clicking the register number or modifying the register contents. Any selected registers are
displayed in blue and any modified registers are displayed in yellow. Any blue or yellow registers are
written to when the WRITE SELECTED button is pressed.
6.1.7 READ ALL
The READ ALL button performs a read operation on every register in the grid.
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Using the Register Grids to Manipulate the Register Spaces
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6.1.8 WRITE ALL
The WRITE ALL button performs a write operation on every register in the grid.
6.2
Test Registers
By default, the GUI opens with the TEST register-grid displayed. Aside from the functions associated
directly with the grid, the TEST tab includes two buttons related to the TEST registers.
6.2.1 IFSEL/uC_RST
The IFSEL/uC_RST button toggles bit 0 and bit 1 of register 0x0E. Press this button to select SPI and
shutdown the 8051 MCU before most other commands on the GUI will take affect is required.
6.2.2 Restricted Access
As described in the PGA400-Q1 data sheet (SLDS186), in order to access some of the features in the
TEST register map, a special unlock sequence must be sent to register 0xFF. The Restricted Access
button sends this sequence to the PGA400-Q1 device.
6.3
ESFR Registers
The ESFR register tab only contains a grid that can be used with the functions described before to directly
manipulate the ESFR register space. Most of the buttons on the right half of the GUI control bits in the
ESFR register tab. These buttons are described in Chapter 7.
6.4
EEPROM Registers
The EEPROM in the PGA400-Q1 device is comprised of six banks of EEPROM (BANK_0 to BANK_5)
and a shared cache. In the PGA400-Q1 GUI, each EEPROM BANK is given a grid even though all
operations are performed on the shared cache. As before, whichever BANK tab is displayed is the
EEPROM bank that is operated on which is achieved by updating the EEPROM bank select bits in the
TEST register space when the user selects a different EEPROM tab. By default, BANK_0 is selected. The
four buttons on the EEPROM tab are described in the following sections.
6.4.1 Auto Program EEPROM
The Auto Program EEPROM button uses the internal EEPROM charge pump and timer to enable and
then disable the EEPROM charge pump after the programming time has been met. This button should be
used if the user desires to burn the current EEPROM cache contents to the EEPROM bank.
6.4.2 PROG_ON
The PROG_ON button is used for a manual method of programming/testing the EEPROM. The
PROG_ON button turns on the EEPROM charge pump. Because no timer exists to automatically turn the
EEPROM charge pump back off, the user must press the PROG_OFF button to disable the charge-pump
6.4.3 PROG_OFF
The PROG_OFF button is used to complete a manual EEPROM programming by disabling the EEPROM
charge pump.
6.4.4 Reload CACHE
The Reload CACHE button uses the TEST register 0x0D to reload the CACHE with the contents of the
selected EEPROM bank and then performs a read-all to update the grid with the refreshed contents of the
EEPROM bank.
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IRAM
6.5
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IRAM
The IRAM tab is setup only for individual register read and writes without the use of the grid. When this
tab is displayed, the READ SELECTED / READ ALL and WRITE SELECTED / WRITE ALL buttons
perform the same operations respectively.
6.6
OTP
The OTP tab is setup only for individual register read/writes without the use of the grid. When this tab is
displayed, the READ SELECTED, READ ALL, WRITE SELECTED, and WRITE ALL buttons perform the
same operations respectively. The OTP tab also contains buttons used to load a .HEX 8051 program file
into the 8051 MCU in the PGA400-Q1 device.
6.6.1 Load .HEX File into GUI
The Load .HEX File into GUI button is used to load the contents of a .HEX file into the GUI RAM for use
with other operations. When the button is pressed, a second window opens that allows the user to locate
and open the desired .HEX file on the PC. Figure 6-1 shows an example of this operation.
Figure 6-1. Loading a .HEX File into the GUI
6.6.2 Program OTP Memory from .HEX File
If the Program OTP Memory from .HEX File check box was checked (default) when the .HEX file was
loaded into the GUI, the OTP memory is programmed with the contents of the .HEX file.
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OTP
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6.6.3 Verify OTP Programming
If the Verify OTP Programming button was also checked (default) then after the OTP memory is finished
programming, the GUI resets the MCU and then verifies that the contents of the OTP memory match the
.HEX file. If the OTP memory matches the contents of the .HEX file, the GUI displays the message OTP
Memory Verification Successful as shown in green text in Figure 6-2.
Figure 6-2. OTP Memory Successful Programming Verification
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23
Chapter 7
SLDU010A – March 2012 – Revised August 2014
Controlling the PGA400-Q1 Functions with the GUI
The previous section focused on the left side of the GUI which is primarily used for direct register
manipulation. The right side of the GUI is focused on providing a graphical method for controlling the
PGA400-Q1 device.
7.1
ADC Conversion Result Section of the GUI
The bottom-right corner of the GUI is dedicated for functions that support or directly read from the internal
ADC inside the PGA400-Q1 device. These buttons were not put inside a tab like the rest of the buttons
because reading the ADC registers that modify the AFE settings without switching tabs is useful. Figure 71 shows the ADC Conversion Result section of the GUI. The following sections include figures and
descriptions of the buttons found on this section.
Figure 7-1. ADC Conversion Result Section of GUI
7.1.1 ADC Update
The ADC Update button is used to load the contents of the ADC into the shadow register and then read
the contents into the GUI. The ADC Update button loads the output from the decimator that is selected
with the ADC Decimator Output Select combo-box. Results are displayed in both twos complement and
signed decimal.
7.1.2 ADC Decimator Output Select
The ADC Decimator Output Select combo-box is used to control with ADC decimator output is loaded
when the ADC Update button is pressed. The combo-box controls bits 2 to 0 in ESFR 0xB3.
7.1.3 ADC DC Level Shift
The ADC DC Level Shift button controls bit 5 in ESFR 0xA9.
7.1.4 Internal Temp Sensor
The Internal Temp Sensor button controls bit 4 in ESFR 0xA9.
7.2
AFE/Offset Tab
By default, the AFE/Offset tab is displayed in the right side of the GUI. This tab is divided into two parts.
The first part enables and controls either the resistive or capacitive AFEs. The second part manipulates
the shared offset DACs in the PGA400-Q1 device. The following sections describe the buttons on these
tabs.
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AFE/Offset Tab
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7.2.1 Resistive AFE Tab
The Resistive tab under the AFE/OFFSET tab is selected by default when the GUI loads. This tabe
corresponds to the default setting to have the resistive AFE selected on power-up. Figure 7-2 shows the
resistive AFE tab. The following sections describe the buttons on this tab.
Figure 7-2. Resistive AFE Tab
7.2.1.1
Activate Resistive Bridge AFE
The Activate Resistive Bride AFE button configures the PGA400-Q1 device for the resistive AFE by
controlling bit 7 in ESFR 0xA7.
7.2.1.2
Enable Bridge Drive Regulator
The Enable Bridge Drive Regulator button enables and disables the VBRG regulator by controlling bit 2 in
ESFR 0xA9.
7.2.1.3
Sensor Select
The Sensor Select combo-box controls which input signals are routed through the AFE by controlling bit 7
of ESFR 0xA9. The combo-box also controls which set of registers the rest of the resistive AFE GUI
controls. By default, Sensor 1 and all of the sensor specific buttons on the resistive tab are selected to
control the Sensor 1registers. The Offset section is also set to control the Sensor 1 registers. If the
combo-box is changed, the buttons will control the registers associated with the Sensor 2 inputs.
7.2.1.4
Invert Sensor
The Invert Sensor button controls the sign-bit MUX in the PGA400-Q1 device by controlling either bit 5 or
bit 6 in register 0xA9 depending on the state of the Sensor Select combo-box.
7.2.1.5
Stage 1 Gain Select
The Stage 1 Gain Select combo-box controls bits 5-7 of either register 0xA1 or 0xA2 depending on the
state of the Sensor Select combo-box
7.2.1.6
Stage 2 Gain Select
The Stage 2 Gain Select combo-box controls bits 0-4 of either register 0xA1 or 0xA2 depending on the
state of the Sensor Select combo-box
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AFE/Offset Tab
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7.2.2 Capacitive AFE Tab
The capacitive AFE tab is not activated by default when the GUI loads. The user can select the capacitive
tab and then enable the capacitive AFE to begin evaluating the capacitive signal chain on the PGA400-Q1
device. Figure 7-3 shows the capacitive AFE tab. The following sections describe the buttons found on
this tab.
Figure 7-3. Capacitive AFE Tab
7.2.2.1
Activate Capacitive AFE
The Activate Capacitive AFE button configures the PGA400-Q1 device for the resistive AFE by controlling
bit 7 in ESFR 0xA7.
7.2.2.2
Drive Voltage
The Drive Voltage selection boxes control the voltage on the clock generator comparator in the PGA400Q1 device by controlling bits 2 and 3 in ESFR 0xA7.
7.2.2.3
Drive Current Select
The Drive Current Select selection boxes control the current that is switched in and out of the ICAP pins
by controlling bits 4-6 in ESFR 0xA7.
7.2.2.4
Trans-Z
The Trans-Z selection boxes control the transimpedance resistance by controlling bits 0 and 1 in ESFR
0xA7.
7.2.3 ZTC and PTAT Offset Control
The ZTC and PTAT offset circuits are shared whether the user is using the PGA400-Q1 device in resistive
or capacitive mode, therefore theses circuits are displayed when either AFE tab is selected. Figure 7-4
shows offset control region of the GUI. The following sections describe the buttons on the offset control
region of the GUI.
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PSMON/AFE Diagnostics Tab
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Figure 7-4. ZTC and PTAT Offset Control
7.2.3.1
Offset ZTC Compenstation Read/Set
The Read and Set buttons in the Offset ZTC Compensation region can be used to directly enter in the
desired offset values. The buttons either read to or write from the ZTC offset bits in ESFRs 0xA3 and
0xA4 or 0xA5 and 0xA6 depending on the state of the Sensor Select combo-box.
7.2.3.2
Offset ZTC Compenstation Adjust Up/Down
The ↑ Coarse, ↓ Coarse, ↑ Fine, and↓ Fine buttons are used to adjust the value of the ZTC offset register
up or down in set increments. The buttons write to the ZTC offset bits in ESFRs 0xA3 and 0xA4 or 0xA5
and 0xA6 depending on the state of the Sensor Select combo-box. The fine adjustments move the ZTC
offset value by one, while the coarse adjustments move the ZTC offset value by 50.
7.2.3.3
Offset PTAT Compenstation Read/Set
The Read and Set buttons in the Offset PTAT Compensation region can be used to directly enter in the
desired offset values. The buttons either read to or write from the PTAT offset bits in ESFRs 0xA4 or 0xA6
depending on the state of the Sensor Select combo-box.
7.2.3.4
Offset PTAT Compenstation Adjust Up/Down
The ↑ Coarse, ↓ Coarse, ↑ Fine, and↓ Fine buttons are used to adjust the value of the PTAT offset register
up or down in set increments. The buttons write to the PTAT offset bits in ESFRs 0xA4 or 0xA6 depending
on the state of the Sensor Select combo-box. The fine adjustments move the PTAT offset value by one,
while the coarse adjustments move the PTAT offset value by 50.
7.3
PSMON/AFE Diagnostics Tab
The PSMON/AFE Diagnostics tab is the second tab in the right half tab control. The tab is setup so that
when activated, any flags that are currently set are displayed in red, while all of the bits that do not have
flags set are displayed in green. Figure 7-5 shows the PSMON/AFE Diagnostics tab the ADC_INPUT_OV
flag is set showing that the input to the ADC is out of range (over voltage). All of the power supplies are in
the correct range so none of the flags are set. The following sections describe the buttons on this tab.
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PSMON/AFE Diagnostics Tab
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Figure 7-5. PSMON/ AFE Diagnostics Tab
7.3.1 Update AFE Flags
The Update AFE Flags button reads from ESFR 0x93 and then updates the color of the flags in the GUI
accordingly.
7.3.2 Update PSMON Flags
The Update PSMON Flags button reads from ESFRs 0x91 and 0x92 and then updates the color of the
flags in the GUI accordingly.
7.4
Test MUX
The Test MUX tab can be used to activate and control the settings on the analog and digital test in and
out MUXs that are present inside the PGA400-Q1 device. The tab is divided into two tabs, one tabe for the
analog test MUXs and the other tab for the digital test MUXs.
7.4.1 Analog Test MUX Tab
The Analog Test MUX tab is used to control the settings for the analog test MUXs inside the PGA400-Q1
device. Before any changes on the Analog Test MUX tab go into effect, the user must activate Restricted
Access mode from the TEST tab. Figure 7-6 shows this tab. The following sections describe the controls
on this tab.
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Test MUX
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Figure 7-6. Analog Test MUX Tab
7.4.1.1
Activate Analog Test MUX
The Activate Analog Test MUX button disables the VOUT1 and VOUT2 DACs and activates the analog
test MUXs by controlling bits 3 and 4 of TEST register 0x10.
7.4.1.2
TIP_A and TIN_A Combo-Box
The TIP_A and TIN_A combo-box is used to select where the TIN and TIP signals get routed inside the
PGA400-Q1 device by controlling TEST register 0x08.
7.4.1.3
TOP_A and TON_A Combo-Box
The TOP_A and TON_A combo-box is used to select where the VOUT1 and VOUT2 signals get routed
inside the PGA400-Q1 device by controlling TEST register 0x06.
7.4.2 Digital Test MUX Tab
The Digital Test MUX tab is used to control the settings for the digital test MUXs inside the PGA400-Q1
device. Before any changes on the Digital Test MUX tab goes into effect, the user must activate Restricted
Access mode from the TEST tab. Figure 7-7 shows the Digital Test MUX tab. The following sections
describe the controls on this tab.
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DAC Output Tab
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Figure 7-7. Analog Test MUX Tab
7.4.2.1
Activate TIP_D
The Activate TIP_D button disables the digital test input signal by controlling bit 1 of TEST register 0x03.
7.4.2.2
Activate TOP_D
The Activate TOP_D button disables the activates the digital test output signal by controlling bits 2 and 3
of TEST register 0x03.
7.4.2.3
TIP_D and TIN_D Combo-Box
The TIP_D and TIN_D combo-box is used to select where the digital test input signals get routed inside
the PGA400-Q1 device by controlling TEST register 0x07.
7.4.2.4
TOP_D and TON_D Combo-Box
The TOP_A and TON_A combo-box is used to select where the VOUT1 and VOUT2 signals get routed
inside the PGA400-Q1 device by controlling TEST register 0x06.
7.5
DAC Output Tab
The DAC Output tab can be used to directly control the output of the VOUT1 and VOUT2 DACs on the
PGA400-Q1. Figure 7-8 shows the DAC Output tab. The following sections describe the buttons on this
tab.
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DAC Output Tab
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Figure 7-8. DAC Output Tab
7.5.1 DAC1 Output Read/Set
The Read and Set buttons in the DAC1 region can be used to directly enter in the desired DAC1 values.
The buttons either read to or write from the DAC1 ESFRs 0xB7/0xB9.
7.5.2 DAC1 Output Adjust Up/Down
The ↑ Coarse, ↓ Coarse, ↑ Fine, and↓ Fine buttons are used to adjust the value of the DAC1 output
register up or down in set increments. The buttons write to the DAC1 output bits in ESFRs 0xB7/0xB9.
The fine adjustments move the DAC1 output value by one, while the coarse adjustments move the DAC1
output value by 50.
7.5.3 DAC2 Output Read/Set
The Read and Set buttons in the DAC2 region can be used to directly enter in the desired DAC2 values.
The buttons either read to or write from the DAC2 ESFRs 0xBA/0xBB.
7.5.4 DAC2 Output Adjust Up/Down
The ↑ Coarse, ↓ Coarse, ↑ Fine, and↓ Fine buttons are used to adjust the value of the DAC2 output
register up or down in set increments. The buttons write to the DAC2 output bits in ESFRs 0xBA/0xBB.
The fine adjustments move the DAC2 output value by one, while the coarse adjustments move the DAC2
output value by 50.
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31
OWI Tab
7.6
www.ti.com
OWI Tab
The OWI tab in the GUI is used to initialize the OWI communication interface in the PGA400-Q1 device
along with perform direct OWI writes or reads. Figure 7-9 shows the OWI tab. The following sections
describe the buttons on this tab.
Figure 7-9. OWI GUI Tab
7.6.1 Activate OWI with Over-Voltage Drive
The Activate OWI with Over-Voltage Drive button on the GUI initializes the OWI activation circuit by
controlling the signal that drives the Q4 BJT. Pressing the button disables the PGA400-Q1 output MUX
and activates the 7.5-V pullup. The device waits about 200 ms and then releases the OWI pull-up. The
8051 MCU must be running and have code loaded into it that sends the signals to activate the OWI
transceiver.
7.6.2 Activate OWI with ESFRs
The Activate OWI with ESFRs button activates the OWI transceiver by directly writing to ESFR 0xD4. After
this button is pressed, the PGA400-Q1 device is in OWI mode and SPI commands will no longer work.
7.6.3 Activate TI-GER UART
The Activate TI-GER UART button initializes the UART hardware module in the TI-GER board in
preparation for OWI communication.
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OWI Tab
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7.6.4 Send Sync
The Send Sync button sends the required preliminary sync pulse to flush the contents of the OWI
transceiver shift buffer.
7.6.5 Write/Read Tab
The bottom portion of the main OWI tab is divided between performing simple OWI writes and reads and
performing OWI burst writes and reads. Figure 7-9 shows the Write/Read tab. The following sections
describe the buttons on this tab.
7.6.5.1
Memory Space Selection Box
The currently selected memory space in the Memory Space selection box is used to form the correct
packet when an OWI write or read is performed using the Write/Read buttons on the Write/Read tab.
7.6.5.2
Address Text Box
The Address text box is used to enter the address that the user desires to write or read from when using
the write and read buttons.
7.6.5.3
Data Text Box
The Data text box is used to enter the data that the user desires to write or read from when using the write
and read buttons.
7.6.5.4
Write OWI
The Write OWI button collects information from the Memory Space selection box, the Address text box,
and the Data text box and then form the appropriate packet to write the data into the selected address in
the correct memory space.
7.6.5.5
Send Read Init
The Send Read Init button collects information from the Memory Space selection box and the Address
and then form the appropriate packet to send in the Read Init command when reading from a selected
address in the correct memory space.
7.6.5.6
Send Read Response
The Send Read Response button sends the Read Response command to the PGA400-Q1 device that is
be followed by the data that was requested in the Read Init command.
7.6.5.7
Read USART
The Read USART button reads out the contents of the TI-GER USART buffer. Data is shifted out of the
FIFO buffer when the button is pressed and then displayed in the text box on the right side of the
Write/Read tab. Because the OWI always works in loop-back mode, the results of any OWI writes can be
seen by reading the USART after a write is performed.
7.6.6 EEPROM Burst Write/Read Tab
The second tab on the bottom portion of the OWI tab is the EEPROM Burst Write/Read tab. This tab is
used to perform the EEPROM burst write and read commands that the PGA400-Q1 device supports.
Figure 7-10 shows the EEPROM Burst Write/Read tab. The following sections describe the buttons on this
tab.
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33
OWI Tab
www.ti.com
Figure 7-10. EEPROM Burst Write/Read Tab
7.6.6.1
EEPROM Burst Write 1
The EEPROM BURST WRITE 1 button performs a burst write with the data that has been entered into the
text boxes under the Write Data label on the left side of the tab.
7.6.6.2
EEPROM Burst Read 1
The EEPROM BURST READ 1 button performs a burst read and then populate the data into the text
boxes under the Read Data with the data that has been entered into the text boxes under the Read Data
label on the left side of the tab.
7.6.6.3
EEPROM Burst Write 2
The EEPROM BURST WRITE 2 button performs a burst write with the data that has been entered into the
text boxes under the Write Data label on the right side of the tab.
7.6.6.4
EEPROM Burst Read 2
The EEPROM BURST READ 2 button performs a burst read and then populate the data into the text
boxes under the Read Data with the data that has been entered into the text boxes under the Read Data
label on the right side of the tab.
34
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IC/OC Tab
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7.7
IC/OC Tab
The IC/OC (input compare and output compare) tab on the GUI is used to read from and configure the
input and output compare registers on the PGA400-Q1 device. The tab is broken into five main regions:
Input Compare 1 (IC1), Input Compare 2 (IC2), Output Compare 1 (OC1), Output Compare 2 (OC2), and
Free Running Timer. Figure 7-11 shows the IC/OC tab. The following sections describe the buttons on this
tab.
Figure 7-11. IC/OC GUI Tab
7.7.1 Input Compare 1 Region
The Input Compare 1 region is used to activate and read from the Input Compare 1 peripheral in the
PGA400-Q1 device.
7.7.1.1
Activate IC1
The Activate IC1 button activates the Input Compare 1 function in the PGA400-Q1 device by controlling bit
0 of ESFR 0xC7.
7.7.1.2
Read IC1
The Read button in the IC1 region is used to update the text box with the contents of the input compare
registers by reading ESFRs 0xC1 and 0xC2.
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IC/OC Tab
7.7.1.3
www.ti.com
Falling/Rising Edge Selection Box
The Falling/Rising Edge selection box is used to change the polarity that the input compare peripheral
uses by controlling bit 1 of ESFR 0xC0.
7.7.2 Input Compare 2 Region
The Input Compare 2 region is used to activate and read from the Input Compare 2 peripheral in the
PGA400-Q1.
7.7.2.1
Activate IC2
The Activate IC2 button activates the Input Compare 2 function in the PGA400-Q1 device by controlling bit
1 of ESFR 0xC7.
7.7.2.2
Read IC2
The Read button in the IC2 region is used to update the text box with the contents of the input compare
registers by reading ESFRs 0xC3 and 0xC4.
7.7.2.3
Falling/Rising Edge Selection Box
The Falling/Rising Edge selection box is used to change the polarity that the input compare peripheral
uses by controlling bit 2 of ESFR 0xC0.
7.7.3 Output Compare 1 Region
The Output Compare 1 region is used to activate and set/read the Output Compare 1 peripheral in the
PGA400-Q1.
7.7.3.1
Activate OC1
The Activate OC1 button activates the Output Compare 1 function in the PGA400-Q1 device by controlling
bit 2 of ESFR 0xC7.
7.7.3.2
Read OC1
The Read button in the OC1 region is used to update the text box with the contents of the output compare
registers by reading ESFRs 0xC5 and 0xC6.
7.7.3.3
Set OC1
The Set button in the OC1 region is used to set the value in the Output Compare 1 register by writing to
ESFR 0xC5 and 0xC6.
7.7.4 Output Compare 2 Region
The Output Compare 2 region is used to activate and set and read the Output Compare 2 peripheral in the
PGA400-Q1.
7.7.4.1
Activate OC2
The Activate OC2 button activates the Output Compare 2 function in the PGA400-Q1 device by controlling
bit 3 of ESFR 0xC7.
7.7.4.2
Read OC2
The Read button in the OC2 region is used to update the text box with the contents of the output compare
registers by reading ESFRs 0xC9 and 0xCA.
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IC/OC Tab
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7.7.4.3
Set OC2
The Set button in the OC2 region is used to set the value in the Output Compare 2 register by writing to
ESFR 0xC9 and 0xCA.
7.7.5 No Change / Low Level / High Level Selection Box
The No Change / Low Level / High Level selection box is used to control the level that both the OC1 and
OC2 peripherals use for the output compare functions. This control is achieved by controlling bits 3 and 4
of ESFR 0xC0.
7.7.6 Free Running Timer Region
The Free Running Timer region of the IC/OC tab is used to monitor the Free Running Timer in the
PGA400-Q1.
7.7.6.1
Update Free Running Timer
The Update Free Running Timer button is used to populate the text box in the Free Running Timer region
with the contents of the PGA400-Q1 Free Running Timer.
7.7.6.2
10MHz / 20MHz Selection Box
The 10MHz / 20MHz selection box is used to select between a 10-MHz and 20-MHz Free Running Timer
inside the PGA400-Q1 device by controlling bit 0 of ESFR 0xC0.
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37
Chapter 8
SLDU010A – March 2012 – Revised August 2014
PGA400-Q1 EVM Schematics and Layout Drawings
1
2
1
JP1
C1
1uF,16V,X7R
2
VDD
VDD_MB
R930
510,0805,1/8W,5%
LED2
C2
D30
0.1uF,16V,X7R
U1
GND
VDD
GND
AVDD
DVDD
VDD
21
AVDD
DVDD
20
24
VBRG
ICAP1
ICAP2
9
11
14
PGA400 -Q1- QFN
H1
VDD
VP_OTP
AVDD
DVDD
SPI_CSN
SPI_SCK
SPI_MOSI
SPI_MISO
VBRG
ICAP1
ICAP2
C3
0.1uF,16V,X7R
VOUT2
VOUT1/DIO
VIN3
TIP
TIN
13
15
VIN3
16
TIP
TIN
7
8
VIN2P
VIN2N
VIN3
TIP
TIN
30
23
17
GND
VIN2P
VIN2N
GPIO_1/IIC_SDA
GPIO_2
GPIO_3/IIC_SCL
GPIO_4
GPIO_5/XTAL1
GPIO_6/XTAL2
+7.5V
V7P5_MB
DVSS
REF_GND
GND
GND
AVSS
VIN2P
VIN2N
C4
0.1uF,16V,X7R
VIN1P
VIN1N
PWRPAD
2
AVDD
10
12
0
VIN1P
VIN1N
VIN1P
VIN1N
RxD
TxD
VP_OTP
26
29
28
27
/CS
SCK
MOSI
MISO
6
VOUT2
4
VOUT1
2
1
36
35
34
33
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
32
31
RxD
TxD
CS_MB
MISO_MB
MOSI_MB
SCLK_MB
VP_OTP
/CS
SCK
MOSI
MISO
1
2
3
4
Header 4
VOUT2
H2
VOUT1
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
R1
0.0R
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5*
GPIO_6*
1
2
3
4
5
6
Header 6
RXD
TXD
R2
0.0R
GPIO6
22
18
5
25
19
GND
1
VBRG
ICAP1
ICAP2
NC
NC
NC
1
2
DVDD
3
2
VP_OTP
1
JP2
C5
LED2
D31
0.1uF,16V,X7R
R931
1.1k
GND
GND
GPIO_2
GND
R8D
GPIO_4
R8C
GPIO_5*
R8B
To use XTAL, remove R1 & R2 and install a 0 Ohm resistor or short R3 & R4
GPIO_5
GPIO_6*
GPIO_6
R3
0.0R
DNI
R5
1M
R8A
47k
R4
0.0R
DNI
GND
X1
2
ECS-400-20-30B-DU
40MHz - 20pF Load
GND
4
C6
36pF,50V,C0G
C7
36pF,50V,C0G
GND
PGA400-Q1 - Main
GND
Figure 8-1.
38
PGA400-Q1 EVM Schematics and Layout Drawings
SLDU010A – March 2012 – Revised August 2014
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9V - 12V Unregulated Input
7.5V Regulator
5V Regulator
V7p5_MB
D1
U2
2
GND
C17
0.1uF,50V,X7R
R7
1k
C14
22uF,16V,Tant
GND GND
C10
0.01uF,50V,X7R
VIN
GND
EN
VDD_MB
V5
VOUT
NR
5
4
1
R6
200R
TLV1117
1
2
3
REG102-5
C15
0.01uF,50V,X7R
C12
10uF,16V,Tant
2
ADJ/GND
U4
4
2
OUT
2
1
V7p5
OUT
1
P3 F
GND
DZ1
13V Zener
+5V
V7p5
IN
1
C9
0.1uF,50V,X7R
2 Pos Term Block
2
2
C8
0.1uF,16V,X7R
7R
2
V7p5
1
CBulk1
100uF,16V, AL
1
2
2
1
1
1
2
VPWR
3
P2
GND
Diode Schottky
VPWR
VPWR
1
P1 F
VPWR
GND
GND
GND
GND
GND
GND
MotherBoard - DaughterCard Connectors and Jumpers
TIP
TIN
VIN3
/CS
MISO
MOSI
SCK
TXD
RXD
P4
TIP_MB
JP13
JP14
JP15
JP3
JP4
JP5
JP6
JP7
VDD_MB
TIN_MB
TIN_MB
TIP_MB
VIN3_MB
CS_MB
VOUT2_MB
VOUT1_MB
MISO_MB
MOSI_MB
V7p5_MB
SCLK_MB
TXD_MB
TXD_MB
RXD_MB
RXD_MB
JP8
SCL_PSSC
SDA_PSSC
SCLK_MB
MOSI_MB
MISO_MB
CS_MB
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Header 20X2
GND
Power + Connectors
Figure 8-2.
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PGA400-Q1 EVM Schematics and Layout Drawings
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39
www.ti.com
4 Channel DAC and DAC Buffers
C30
2.2nF,16V,X7R
1
2
R24
1k
Cap Sensor
R25
1k
V5
C18
7.0-50pF
Cap Var
8
4 x 3PST MUX for Buffer Outputs
GND
C19
30pF
2
V5
A
3
4
1
DAC1_1
C35
1uF,16V,X7R
1
DAC1_1_BUF
Resistive Bridge
U5A
OPA2335UA
V5
2
VIN1P_MB*
TIP_MB
GND
C33
2.2nF,16V,X7R
1
2
R32
R33
49.9k
DAC1_1_BUF
1
2
3
7
NO1
NO2
NO3
COM
VCC
IN1
IN2
GND
8
6
5
4
1k
3PST_1
3PST_2
GND
V5
C37
0.1uF,16V,X7R
1
2
4
7
VIN1N_MB*
TIN_MB
DAC1_2_BUF
U5B
OPA2335UA
R34
49.9k
DAC1_2_BUF
1
2
3
7
NO1
NO2
NO3
COM
VCC
IN1
IN2
GND
8
6
5
4
3PST_1
3PST_2
C22
30pF
VIN1N_MB
R12
R13
0.0R
0.0R
RPotR14
5k
VIN1N_MB*
VIN1P_C
ICAP1
C23
56pF
GND
R17
7.5k
Input Filtering and Input Selection
R18
7.5k
TS5A3359
C24
1nF
GND
GND
VIN2P_MB*
VIN3_MB
8
R37
49.9k
DAC1_3_BUF
1
2
3
7
NO1
NO2
NO3
COM
VIN1P_MB
C39
0.1uF,16V,X7R
1
2
8
6
5
4
3PST_1
3PST_2
2
R20
10k
VIN1N_MB
4
1
VIN2P_MB
DAC1_3_BUF
GND
VIN2P_MB*
U10A
OPA2335UA
V5
C40
0.1uF,16V,X7R
1
2
1
2
GND
C41
2.2nF,16V,X7R
1
2
GND
R40
1k
VIN2N_MB* 1
2
3
DAC1_4_BUF7
R42
49.9k
R43
49.9k
R41
1k
NO1
NO2
NO3
COM
VCC
IN1
IN2
GND
JP12
VIN1N_C
8
6
5
4
R23
0.0R
0.0R
RPotR27
5k
3PST_1
3PST_2
TS5A3359
GND
51R
VIN2N_MB
R22
R28 RPot
5k
VIN2N_MB*
49.9k
R39
49.9k
GND
C27
1nF
R29
7.5k
51-Ω Resistors are Installed Instead of Ferrite Bead s: L1 - L4. Remove the 51-Ω resistors and replace with Ferrites if desired.
R30
7.5k
C28
1nF
GND
VIN2P_R
VIN2P_MB
JP16
GND
L3
VIN2P_C
2
GND
C31
0.01uF
1
V5
7
JP18
DAC1_4_BUF
L4
VIN2P
JP19
VIN2N_C
C32
1nF
U10B
OPA2335UA
GND
51R
1
B
4
5
GND
2
8
VIN2N_R
VIN2N_MB
6
DAC1_4
JP17
C29
10nF - X2Y
DNI
51R
GND
GND
VIN1N
GND
V5
R38
VIN1P
GND
L2
JP11
U11
C42
1uF,16V,X7R
VIN1N_R
GND
1
A
VIN1P_C
C26
0.01uF
R19
10k
GND
3
JP10
C25
10nF - X2Y
DNI
51R
GND
TS5A3359
2
DAC1_3
L1
VBRG
VCC
IN1
IN2
GND
GND
V5
VIN1P_R
JP9
U9
R35
1k
V5
GND
V5
1
R36
1k
9
5
GND
GND
2
GND
C38
2.2nF,16V,X7R
1
2
1
DAC1_4
DAC1_3
DAC1_2
DAC1_1
VIN1N_C
R15 RPot
5k
2
B
5
R10
10k
2
LDAC
VREFL
DAC1_2
3
1
2
7
8
VIN2N_C
C21
7.0-50pF
Cap Var
1
A4
A2
A1
A0
VOUTA
VOUTB
VOUTC
VOUTD
VIN1P_MB*
U7
12
4
IOVDD
VDD
16
15
14
13
SDA
SCL
R9
10k
VIN1P_MB
8
V5
6
GND V5
11
10
GND
MB_SDA
MB_SCL
VREFH
GND
GND
6
U8
DAC8574
VBRG
TS5A3359
R31
1k
GND
GND
VIN2P_C
C20
56pF
U6
GND
C36
V5
0.1uF,16V,X7R
2
1
C34
0.1uF,16V,X7R
1
2
ICAP2
VIN2N
GND
GND
DACs / Inputs
Figure 8-3.
40
PGA400-Q1 EVM Schematics and Layout Drawings
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PSSC DAC Outputs
OWI -> TX/RX
V5
4 x ADC
V5
RX
V5
R44
49k
R47
49k
2
100pF,50V,,X7R
6
R45
49k
OWI
V2.5
VIN+
VIN-
GND
4 MB_SDA
2
1
4
GND
2
V5
TX
GND
TX
V5
C45
0.1uF,50V,X7R
1
2
5
3
R46
200R
JP23
1
2
6
V2.5
VIN+
VIN-
C47
ADS1100A3
PSSC DAC Output MUX
VOUT1_MB 8
OWI_TX_RX 9
NO4
COM4
2.5V Reference for ADCs
NO1
COM1
VDD
NO2
COM2
IN1
IN2
IN3
IN4
NO3
COM3
11
10
NO4
COM4
14
1
GND
0.1uF,16V,X7R
GND
134SPST_1
5 4SPST_1
6 4SPST_2
124SPST_2
V5
U18
R50
49.9k
GND
ADC3
1
7
6
TS12A44514
R51
49.9k
4 MB_SDA
2
R49
49.9k
V2.5
+2.5V
GND
GND
VIN+
VIN-
GND
C49
0.1uF,50V,X7R
1
2
SCL
SDA
GND
3 MB_SCL
4 MB_SDA
2
ADS1100A4
V2.5
1
V5
SDA
GND
3 MB_SCL
5
VOUT1_MB 3
ADC1
4
SCL
V7p5_MB
C46
VOUT2_MB 1
2
ADC2
VDD
U15
GND
GND
100pF,50V,,X7R
GND
ADC2
2
GND
VOUT2_MB
VDD
U16
VOUT2
1
SDA
3 MB_SCL
5
U13
SN74LVC1G07
NC
GND
R48
49k
SCL
ADS1100A2
3
OWI_TX_RX
1
VDD
NC
ADC1
GND
1
4
5
U14
V5
JP22
C44
C43
0.1uF,50V,X7R
1
2
5
U12
SN74LVC1G07
VOUT1_MB
2
VOUT1
1
RX
C50
100pF,250V,C0G
1
2
GND
V5
ADC3 & ADC4 Input MUX
C51
0.1uF,50V,X7R
1
2
5
2
C52
1uF,16V,X7R
U19B
OPA2335UA
6
R53
4.99k
2
3
A
C53
1uF,16V,X7R
2
C54
0.1uF,50V,X7R
4
R55
4.99k
NC1
COM1
NO1
DAC1_2_BUF 7
ADC4
6
DAC1_4_BUF 4
NC2
COM2
NO2
V+
U20
ADC4
6
GND
IN1
IN2
GND
1
1
5
SPDT_1
SPDT_1
V2.5
VIN+
VIN-
VDD
DAC1_1_BUF 9
ADC3
10
DAC1_3_BUF 2
1
7
R54
200R
C48
V5 0.1uF,16V,X7R
1
2
8
SCL
SDA
GND
3 MB_SCL
4 MB_SDA
ADS1100A5
R52
49.9k
3
2
4
5
B
U19A
OPA2335UA
1
1
8
8
U17
GND
V5
V5
2
GND
GND
GND
TS5A23159
GND
GND
GND
GND
Outputs / Acquisition
Figure 8-4.
SLDU010A – March 2012 – Revised August 2014
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PGA400-Q1 EVM Schematics and Layout Drawings
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41
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V7p5_MB
R64
1k
DZ4
5.1V Zener
R66
Q3
SI2319DS-T1-E3
220k
2
Q4
2N2222
OWI_T
1
R69
49.9k
DNI
C59
330nF,16V,X7R
R68
5R
OWI_ACT
GND
GND
VOUT1_MB
GND
OWI_Activation
Figure 8-5.
TXD_MB
PSSC RXD/TXD -> RS-232
U23
3
C60
0.1uF,50V,X7R
7
V+
T1IN
JP26
11
TTL RX
VR1OUT
9
TTL TX
2
GND
RXD_MB
C1+
T1OUT
C61 GND
0.1uF,50V,X7R
13
CPU_RX
JP27
232 TX
4
C62
0.1uF,50V,X7R5
C1-
R1IN
14
C2EN
8
CPU_TX
CPU_TX
232 RX
C2+
~INVALID
1
CPU_RX
CPU_TX
C63
0.1uF,50V,X7R
6
J1
CPU_RX
FORCEON
FORCEOFF
GND
VCC
10
R70
12
16
V5
1
6
2
7
3
8
4
9
5
11
10
Female
GND
10R
15
MAX3221ECAE
C64
0.1uF,50V,X7R
GND
Communications
GND
Figure 8-6.
42
PGA400-Q1 EVM Schematics and Layout Drawings
SLDU010A – March 2012 – Revised August 2014
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Copyright © 2012–2014, Texas Instruments Incorporated
www.ti.com
TI-GER COMM MUX - SPI/I2C
MISO_T
SCLK_T
/CS_T
MOSI_T
SPI/I2C
OWI_T
I2C_MB/PSSC
3PST_2
SPDT_1
1
IO-MISO
3
IO-SCLK
5
IO-CS
7
IO-MOSI
9
IO-11
11
IO-0
13
IO-2
15
IO-4
17
IO-6
V_5.0_WORLD19
IO-OSC
21
V_3.3_WORLD23
25
V_DVM_1
27
V_DVM_2
29
V_DVM_3
MISO, SDA
GND
SCLK, SCL
GND
CS (SS)
GND
MOSI
GND
IO-11
IO-8, TX
IO-0
IO-1
IO-2
TIGER - A
IO-3
IO-4
IO-5
IO-6
IO-7
V_5.0V (OUT)
IO-9, RX
CHIP OSC (OUT) PWR-DWN
V_3.3V (OUT) IO-10 (PIC OSC)
DVM-1
IO-A
DVM-2
IO-B
DVM-3
IO-DAC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
GND
GND
GND
GND
IO-8__TX
TX
IO-1
4SPST_1
IO-3
4SPST_2
IO-5
3PST_1
IO-7
COMM_EN
IO-9__RX
RX
PWR-DWN
V3intD
IO-10 (SLOW OSC)
IO-A
IO-B
DAC_OUT
V5
C68
0.1uF.16V,X7R
1
2
GND
U26
R76
49.9k
SPI/I2C
SCLK_MB
SCL
SCLK_T
MISO_MB
SDA
MISO_T
GND
1
2
3
4
5
6
7
8
S
1B1
1B2
1A
2B1
2B2
2A
GND
VCC
OE
4B1
4B2
4A
3B1
3B2
3A
16
15
14
13
12
11
10
9
COMM_EN
CS_MB
CS_T
MOSI_MB
R77
49.9k
MOSI_T
SN74CBTLV3257
TIGER - A
R78
49.9k
R79
49.9k
GND
GND
GND
GND
I2C MUX - PSSC / EVM
IO-MOSI
MOSI_T
R75D
IO-CS
U25
CS_T
IO-SCLK
U27
SCLK_T
R75B
IO-MISO
MISO_T
R75A
100,0805,1/10W,5%
IO-0
OWI_T
SDA_PSSC9
SDA 10
MB_SDA 2
SCL_PSSC7
SCL 6
MB_SCL 4
4PST_EN 1
4SPST_1 2
3
C69
V5 0.1uF.16V,X7R
1
2
R75C
NC1
COM1
NO1
8
V+
5
4
4SPST_2
SN74LVC1G240
GND
IN1
IN2
NC2
COM2
NO2
V5
OE VCC
A
GND
Y
GND
1
5
I2C_MB/PSSC
3
R80
49.9k
GND
R81D
I2C_MB/PSSC
IO-1
TS5A23159
GND
R81C
IO-11
GND
SPI/I2C
R81B
TX
IO-8__TX
R81A
100,0805,1/10W,5%
3PST_1
IO-5
V5
V_3.3_WORLD
R87D
3PST_2
IO-4
LED2
D2
R87C
IO-3
4SPST_1
R89
R91
49.9k
49.9k
V_5.0_WORLD
SCL_PSSC
R87B
LED2
D3
4PST_EN
IO-2
R88
332, 0805,1/8W,5%
SDA_PSSC
R87A
100,0805,1/10W,5%
IO-10
GPIO_3
JP28
GND
R93
510,0805,1/8W,5%
GPIO_1
JP29
(SLOW OSC)
GND
R94D
IO-9__RX
RX
R94C
IO-7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
COMM_EN
R94B
IO-6
TI BUG
SPDT_1
R94A
100,0805,1/10W,5%
Digital Pins / TI - GER
Figure 8-7.
SLDU010A – March 2012 – Revised August 2014
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PGA400-Q1 EVM Schematics and Layout Drawings
Copyright © 2012–2014, Texas Instruments Incorporated
43
www.ti.com
Figure 8-8.
44
PGA400-Q1 EVM Schematics and Layout Drawings
SLDU010A – March 2012 – Revised August 2014
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Revision History
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Revision History
Changes from Original (March 2012) to A Revision ....................................................................................................... Page
•
Deleted Reference to the Chapter 8: Controlling the EVM peripherals with the GUI section ................................... 1
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SLDU010A – March 2012 – Revised August 2014
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45
ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR
EVALUATION MODULES
Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user
expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following:
1.
User agrees and acknowledges that EVMs are intended to be handled and used for feasibility evaluation only in laboratory and/or
development environments. Notwithstanding the foregoing, in certain instances, TI makes certain EVMs available to users that do not
handle and use EVMs solely for feasibility evaluation only in laboratory and/or development environments, but may use EVMs in a
hobbyist environment. All EVMs made available to hobbyist users are FCC certified, as applicable. Hobbyist users acknowledge, agree,
and shall comply with all applicable terms, conditions, warnings, and restrictions in this document and are subject to the disclaimer and
indemnity provisions included in this document.
2. Unless otherwise indicated, EVMs are not finished products and not intended for consumer use. EVMs are intended solely for use by
technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical
mechanical components, systems, and subsystems.
3. User agrees that EVMs shall not be used as, or incorporated into, all or any part of a finished product.
4. User agrees and acknowledges that certain EVMs may not be designed or manufactured by TI.
5. User must read the user's guide and all other documentation accompanying EVMs, including without limitation any warning or
restriction notices, prior to handling and/or using EVMs. Such notices contain important safety information related to, for example,
temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or
contact TI.
6. User assumes all responsibility, obligation, and any corresponding liability for proper and safe handling and use of EVMs.
7. Should any EVM not meet the specifications indicated in the user’s guide or other documentation accompanying such EVM, the EVM
may be returned to TI within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE
EXCLUSIVE WARRANTY MADE BY TI TO USER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR
STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. TI SHALL
NOT BE LIABLE TO USER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES RELATED TO THE
HANDLING OR USE OF ANY EVM.
8. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which EVMs might be or are used. TI currently deals with a variety of customers, and therefore TI’s arrangement with
the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services with respect to the handling or use of EVMs.
9. User assumes sole responsibility to determine whether EVMs may be subject to any applicable federal, state, or local laws and
regulatory requirements (including but not limited to U.S. Food and Drug Administration regulations, if applicable) related to its handling
and use of EVMs and, if applicable, compliance in all respects with such laws and regulations.
10. User has sole responsibility to ensure the safety of any activities to be conducted by it and its employees, affiliates, contractors or
designees, with respect to handling and using EVMs. Further, user is responsible to ensure that any interfaces (electronic and/or
mechanical) between EVMs and any human body are designed with suitable isolation and means to safely limit accessible leakage
currents to minimize the risk of electrical shock hazard.
11. User shall employ reasonable safeguards to ensure that user’s use of EVMs will not result in any property damage, injury or death,
even if EVMs should fail to perform as described or expected.
12. User shall be solely responsible for proper disposal and recycling of EVMs consistent with all applicable federal, state, and local
requirements.
Certain Instructions. User shall operate EVMs within TI’s recommended specifications and environmental considerations per the user’s
guide, accompanying documentation, and any other applicable requirements. Exceeding the specified ratings (including but not limited to
input and output voltage, current, power, and environmental ranges) for EVMs may cause property damage, personal injury or death. If
there are questions concerning these ratings, user should contact a TI field representative prior to connecting interface electronics including
input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate
operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the applicable EVM user's guide prior
to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During
normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained
at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors which can be identified using EVMs’ schematics located in the applicable EVM user's guide. When
placing measurement probes near EVMs during normal operation, please be aware that EVMs may become very warm. As with all
electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in
development environments should use EVMs.
Agreement to Defend, Indemnify and Hold Harmless. User agrees to defend, indemnify, and hold TI, its directors, officers, employees,
agents, representatives, affiliates, licensors and their representatives harmless from and against any and all claims, damages, losses,
expenses, costs and liabilities (collectively, "Claims") arising out of, or in connection with, any handling and/or use of EVMs. User’s
indemnity shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if EVMs fail to perform as
described or expected.
Safety-Critical or Life-Critical Applications. If user intends to use EVMs in evaluations of safety critical applications (such as life support),
and a failure of a TI product considered for purchase by user for use in user’s product would reasonably be expected to cause severe
personal injury or death such as devices which are classified as FDA Class III or similar classification, then user must specifically notify TI
of such intent and enter into a separate Assurance and Indemnity Agreement.
RADIO FREQUENCY REGULATORY COMPLIANCE INFORMATION FOR EVALUATION MODULES
Texas Instruments Incorporated (TI) evaluation boards, kits, and/or modules (EVMs) and/or accompanying hardware that is marketed, sold,
or loaned to users may or may not be subject to radio frequency regulations in specific countries.
General Statement for EVMs Not Including a Radio
For EVMs not including a radio and not subject to the U.S. Federal Communications Commission (FCC) or Industry Canada (IC)
regulations, TI intends EVMs to be used only for engineering development, demonstration, or evaluation purposes. EVMs are not finished
products typically fit for general consumer use. EVMs may nonetheless generate, use, or radiate radio frequency energy, but have not been
tested for compliance with the limits of computing devices pursuant to part 15 of FCC or the ICES-003 rules. Operation of such EVMs may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: For EVMs including a radio, the radio included in such EVMs is intended for development and/or
professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability in such EVMs
and their development application(s) must comply with local laws governing radio spectrum allocation and power limits for such EVMs. It is
the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations.
Any exceptions to this are strictly prohibited and unauthorized by TI unless user has obtained appropriate experimental and/or development
licenses from local regulatory authorities, which is the sole responsibility of the user, including its acceptable authorization.
U.S. Federal Communications Commission Compliance
For EVMs Annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications could void the user's authority to operate the equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at its own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
Industry Canada Compliance (English)
For EVMs Annotated as IC – INDUSTRY CANADA Compliant:
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs Including Radio Transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs Including Detachable Antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Canada Industry Canada Compliance (French)
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
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Important Notice for Users of EVMs Considered “Radio Frequency Products” in Japan
EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan.
If user uses EVMs in Japan, user is required by Radio Law of Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use EVMs only after user obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or
Use of EVMs only after user obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect
to EVMs. Also, do not transfer EVMs, unless user gives the same notice above to the transferee. Please note that if user does not
follow the instructions above, user will be subject to penalties of Radio Law of Japan.
http://www.tij.co.jp
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品の
ご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
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東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
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Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
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