Texas Instruments | CC1352R SimpleLink™ High-Performance Multi-Band Wireless MCU (Rev. F) | Datasheet | Texas Instruments CC1352R SimpleLink™ High-Performance Multi-Band Wireless MCU (Rev. F) Datasheet

Texas Instruments CC1352R SimpleLink™ High-Performance Multi-Band Wireless MCU (Rev. F) Datasheet
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CC1352R
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
CC1352R SimpleLink™ High-Performance Multi-Band Wireless MCU
1 Device Overview
1.1
Features
1
• Microcontroller
– Powerful 48-MHz Arm® Cortex®-M4F processor
– EEMBC CoreMark® score: 148
– 352KB of in-system Programmable Flash
– 256KB of ROM for protocols and library
functions
– 8KB of Cache SRAM (Alternatively available as
general-purpose RAM)
– 80KB of ultra-low leakage SRAM. The SRAM is
protected by parity to ensure high reliability of
operation.
– 2-Pin cJTAG and JTAG debugging
– Supports Over-the-Air upgrade (OTA)
• Ultra-low power sensor controller with 4KB of
SRAM
– Sample, store, and process sensor data
– Operation independent from system CPU
– Fast wake-up for low-power operation
• TI-RTOS, drivers, Bootloader, Bluetooth® 5 Low
Energy Controller, and IEEE 802.15.4 MAC in
ROM for optimized application size
• RoHS-compliant package
– 7-mm × 7-mm RGZ VQFN48 (28 GPIOs)
• Peripherals
– Digital peripherals can be routed to any GPIO
– 4× 32-bit or 8× 16-bit general-purpose timers
– 12-Bit ADC, 200 kSamples/s, 8 channels
– 2× comparators with internal reference DAC
(1× continuous time, 1× ultra-low power)
– Programmable current source
– 2× UART
– 2× SSI (SPI, MICROWIRE, TI)
– I2C
– I2S
– Real-Time Clock (RTC)
– AES 128- and 256-bit Crypto Accelerator
– ECC and RSA Public Key Hardware Accelerator
– SHA2 Accelerator (Full suite up to SHA-512)
– True Random Number Generator (TRNG)
– Capacitive sensing, up to 8 channels
– Integrated temperature and battery monitor
• External system
– On-chip Buck DC/DC converter
• Low power
– Wide supply voltage range: 1.8 V to 3.8 V
– Active-mode RX: 5.8 mA (3.6 V, 868 MHz),
6.9 mA (3.0 V, 2.4 GHz)
– Active-Mode TX 0 dBm: 8.0 mA (3.6 V,
868 MHz), 7.1 mA (3.0 V, 2.4 GHz)
– Active-Mode TX at +14 dBm: 24.9 mA
(868 MHz)
– Active-Mode MCU 48 MHz (CoreMark):
2.9 mA (60 μA/MHz)
– Sensor Controller, Low Power-Mode, 2 MHz,
running infinite loop: 30.8 μA
– Sensor Controller, Active-Mode, 24 MHz,
running infinite loop: 808 μA
– Standby: 0.85 µA (RTC on, 80KB RAM and
CPU retention)
– Shutdown: 150 nA (wakeup on external events)
• Radio section
– Multi-band sub-1 GHz and 2.4 GHz RF
transceiver compatible with Bluetooth 5 Low
Energy and IEEE 802.15.4 PHY and MAC
– Excellent receiver sensitivity:
–121 dBm for SimpleLink long-range mode
–110 dBm at 50 kbps, –105 dBm for Bluetooth
125-kbps (LE Coded PHY)
– Output power up to +14 dBm (Sub-1 GHz) and
+5 dBm (2.4 GHz) with temperature
compensation
– Suitable for systems targeting compliance with
worldwide radio frequency regulations
– ETSI EN 300 220 Receiver Category 1.5 and
2, EN 300 328, EN 303 131, EN 303 204
(Europe)
– EN 300 440 Category 2
– FCC CFR47 Part 15
– ARIB STD-T108 and STD-T66
– Wide standard support
• Wireless protocols
– Thread, Zigbee®, Bluetooth® 5 Low Energy,
IEEE 802.15.4g, IPv6-enabled smart objects
(6LoWPAN), Wireless M-Bus, Wi-SUN®,
KNX RF, proprietary systems, SimpleLink™ TI
15.4-Stack (Sub-1 GHz), and Dynamic
Multiprotocol Manager (DMM) driver.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC1352R
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
www.ti.com
• Development Tools and Software
– CC1352R LaunchPad™ Development Kit
– SimpleLink™ CC13x2 and CC26x2 Software
Development Kit (SDK)
1.2
•
•
Applications
433, 470 to 510, 868, 902 to 928, and
2400 to 2480 MHz ISM and SRD systems (1)
with down to 4 kHz of receive bandwidth
Building automation
– Building security systems – motion detector,
electronic smart lock, door and window sensor,
garage door system, gateway
– HVAC – thermostat, wireless environmental
sensor, HVAC system controller, gateway
– Fire safety system – smoke and heat detector,
fire alarm control panel (FACP)
– Video surveillance – IP network camera
– Elevators and escalators – elevator main
control panel for elevators and escalators
(1)
1.3
– SmartRF™ Studio for simple radio configuration
– Sensor Controller Studio for building low-power
sensing applications
•
•
•
•
•
Grid infrastructure
– Smart meters – water meter, gas meter,
electricity meter, and heat cost allocators
– Grid communications – wireless
communications – Long-range sensor
applications
– Other alternative energy – energy harvesting
Industrial transport – asset tracking
Factory automation and control
Medical
Electronic point of sale (EPOS) –Electronic Shelf
Label (ESL)
See RF Core for additional details on supported protocol
standards, modulation formats, and data rates.
Description
The CC1352R device is a multiprotocol and multi-band Sub-1 GHz and 2.4-GHz wireless microcontroller
(MCU) targeting Thread, Zigbee®, Bluetooth® 5 Low Energy, IEEE 802.15.4g, IPv6-enabled smart objects
(6LoWPAN), proprietary systems, including the SimpleLink™ TI 15.4-Stack (Sub-1 GHz and 2.4 GHz),
and concurrent multiprotocol through a Dynamic Multiprotocol Manager (DMM) driver. The device is
optimized for low-power wireless communication and advanced sensing in building security systems,
HVAC, smart meters, and medical markets. The highlighted features of this device include:
• Multi-band device supporting concurrent multiprotocol for both Sub-1 GHz and 2.4 GHz through a
DMM driver.
• Wide flexibility of protocol stack support in the SimpleLink™ CC13x2 and CC26x2 Software
Development Kit (SDK).
• Maximum transmit power of +14 dBm at Sub-1 GHz with 24.9 mA and +5 dBm at 2.4 GHz with 9.6 mA
current consumption.
• Longer battery life wireless applications with low standby current of 0.85 µA and full RAM retention.
• Industrial temperature ready with lowest standby current of 11 µA at 105 ⁰C.
• Advanced sensing with a programmable, autonomous ultra-low power Sensor Controller CPU with fast
wake-up capability. As an example, the sensor controller is capable of 1-Hz ADC sampling at 1 µA
system current.
• Low SER (Soft Error Rate) FIT (Failure-in-time) for long operation lifetime with no disruption for
industrial markets with always-on SRAM parity against corruption due to potential radiation events.
• Dedicated software controlled radio controller (Arm® Cortex®-M0) providing flexible low-power RF
transceiver capability to support multiple physical layers and RF standards.
• Excellent radio sensitivity (-121 dBm) and robustness (selectivity and blocking) performance for
SimpleLink™ long-range mode.
2
Device Overview
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SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
The CC1352R device is part of the SimpleLink™ microcontroller (MCU) platform, which consists of
Wi-Fi®, Bluetooth® Low Energy, Thread, Zigbee®, Sub-1 GHz MCUs, and host MCUs that all share a
common, easy-to-use development environment with a single core software development kit (SDK) and
rich tool set. A one-time integration of the SimpleLink™ platform enables you to add any combination of
the portfolio’s devices into your design, allowing 100 percent code reuse when your design requirements
change. For more information, visit SimpleLink™ MCU platform.
Device Information (1)
PART NUMBER
CC1352R1F3RGZ
(1)
PACKAGE
BODY SIZE (NOM)
VQFN (48)
7.00 mm × 7.00 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9,
or see the TI website.
Device Overview
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CC1352R
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
Functional Block Diagram
z
2.
4
Su
b-
CC1352R
G
H
1
G
H
z
1.4
www.ti.com
RF Core
cJTAG
Main CPU
256KB
ROM
ADC
ADC
Arm® Cortex®-M4F
Processor
48 MHz
60 µA/MHz (3.6 V)
Up to
352KB
Flash
with 8KB
Cache
Up to
80KB
SRAM
with Parity
Digital PLL
DSP Modem
Arm® Cortex®-M0
Processor
16KB
SRAM
ROM
General Hardware Peripherals and Modules
Sensor Interface
Sensor
Interface
I2C and I2S
4× 32-bit Timers
ULP Sensor Controller
ULP Sensor Controller
2× UART
2× SSI (SPI)
8-bit DAC
32 ch. µDMA
Watchdog Timer
12-bit ADC, 200 ks/s
12-bit ADC, 200 ks/s
28 GPIOs
TRNG
Low-Power Comparator
2x Low-Power Comparator
AES-256, SHA2-512
Temperature and
Battery Monitor
ECC, RSA
RTC
SPI-I2C Digital Sensor IF
SPI-I2C Digital Sensor IF
Constant Current Source
Capacitive Touch IF
Time-to-Digital Converter
Time-to-Digital Converter
LDO, Clocks, and References
Optional DC/DC Converter
4KB SRAM
4KB SRAM
Figure 1-1. CC1352R Block Diagram
4
Device Overview
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Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
5.18
Peripheral Characteristics ........................... 27
1.1
Features .............................................. 1
5.19
Typical Characteristics .............................. 35
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 4
6
Revision History ......................................... 5
Device Comparison ..................................... 6
Terminal Configuration and Functions .............. 7
4.1
Pin Diagram – RGZ Package (Top View) ............ 7
4.2
Signal Descriptions – RGZ Package ................. 8
4.3
Connections for Unused Pins and Modules .......... 9
Specifications ........................................... 10
5.1
Absolute Maximum Ratings ......................... 10
5.2
........................................
Recommended Operating Conditions ...............
Power Supply and Modules .........................
Power Consumption - Power Modes ...............
Power Consumption - Radio Modes ...............
Nonvolatile (Flash) Memory Characteristics ........
Thermal Resistance Characteristics ................
RF Frequency Bands ...............................
861 MHz to 1054 MHz - Receive (RX)..............
861 MHz to 1054 MHz - Transmit (TX) ............
861 MHz to 1054 MHz - PLL Phase Noise .........
Bluetooth Low Energy - Receive (RX) ..............
Bluetooth Low Energy - Transmit (TX) ..............
ESD Ratings
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
10
10
10
11
12
7
12
13
13
8
14
15
16
17
20
Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz
(OQPSK DSSS1:8, 250 kbps) - RX ................. 21
Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz
(OQPSK DSSS1:8, 250 kbps) - TX ................. 22
Timing and Switching Characteristics ............... 23
9
Detailed Description ................................... 59
............................................
........................................
6.3
Radio (RF Core) .....................................
6.4
Memory ..............................................
6.5
Sensor Controller ...................................
6.6
Cryptography ........................................
6.7
Timers ...............................................
6.8
Serial Peripherals and I/O...........................
6.9
Battery and Temperature Monitor ...................
6.10 µDMA ................................................
6.11 Debug ...............................................
6.12 Power Management .................................
6.13 Clock Systems ......................................
6.14 Network Processor ..................................
Application, Implementation, and Layout .........
7.1
Reference Designs ..................................
7.2
Junction Temperature Calculation ..................
Device and Documentation Support ...............
8.1
Tools and Software ..................................
8.2
Documentation Support .............................
8.3
Support Resources ..................................
8.4
Trademarks..........................................
8.5
Electrostatic Discharge Caution .....................
8.6
Glossary .............................................
6.1
Overview
59
6.2
System CPU
59
60
63
64
65
66
67
67
67
67
68
69
69
70
70
71
72
72
74
75
75
75
75
Mechanical, Packaging, and Orderable
Information .............................................. 75
9.1
Packaging Information
..............................
75
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2019) to Revision F
•
•
•
•
•
Page
Added Wireless protocols to Section 1.1 .......................................................................................... 1
Changed Section 1.2 ................................................................................................................. 2
Changed Section 1.3 ................................................................................................................. 2
Added Figure 5-29 ................................................................................................................. 50
Added Section 7.2 .................................................................................................................. 71
Revision History
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3 Device Comparison
Table 3-1. Device Family Overview
RADIO SUPPORT
FLASH
(KB)
RAM
(KB)
GPIO
PACKAGE SIZE
CC1312R
Sub-1 GHz
352
80
30
RGZ (7-mm × 7-mm VQFN48)
CC1352P
Multiprotocol
Sub-1 GHz
Bluetooth 5 Low Energy
Zigbee
Thread
2.4 GHz proprietary FSK-based formats
+20-dBm high-power amplifier
352
80
26
RGZ (7-mm × 7-mm VQFN48)
CC1352R
Multiprotocol
Sub-1 GHz
Bluetooth 5 Low Energy
Zigbee
Thread
2.4 GHz proprietary FSK-based formats
352
80
28
RGZ (7-mm × 7-mm VQFN48)
CC2642R
Bluetooth 5 Low Energy
2.4 GHz proprietary FSK-based formats
352
80
31
RGZ (7-mm × 7-mm VQFN48)
CC2652R
Multiprotocol
Bluetooth 5 Low Energy
Zigbee
Thread
2.4 GHz proprietary FSK-based formats
352
80
31
RGZ (7-mm × 7-mm VQFN48)
CC2652RB
Multiprotocol
Bluetooth 5 Low Energy
Zigbee
Thread
2.4 GHz proprietary FSK-based formats
352
80
31
RGZ (7-mm × 7-mm VQFN48)
CC2652P
Multiprotocol
Bluetooth 5 Low Energy
Zigbee
Thread
2.4 GHz proprietary FSK-based formats
+19.5-dBm high-power amplifier
352
80
26
RGZ (7-mm × 7-mm VQFN48)
CC1310
Sub-1 GHz
32–128
16–20
10–31
RGZ (7-mm × 7-mm VQFN48)
RHB (5-mm × 5-mm VQFN32)
RSM (4-mm × 4-mm VQFN32)
CC1350
Sub-1 GHz
Bluetooth 4.2 Low Energy
128
20
10–31
RGZ (7-mm × 7-mm VQFN48)
RHB (5-mm × 5-mm VQFN32)
RSM (4-mm × 4-mm VQFN32)
CC2640R2F
Bluetooth 5 Low Energy
2.4 GHz proprietary FSK-based formats
128
20
10–31
RGZ (7-mm × 7-mm VQFN48)
RHB (5-mm × 5-mm VQFN32)
RSM (4-mm × 4-mm VQFN32)
YFV (2.7-mm × 2.7-mm DSBGA34)
CC2640R2F-Q1
Bluetooth 5 Low Energy
2.4 GHz proprietary FSK-based formats
128
20
31
RGZ (7-mm × 7-mm VQFN48)
DEVICE
6
Device Comparison
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4 Terminal Configuration and Functions
38 DIO_25
37 DIO_24
40 DIO_27
39 DIO_26
42 DIO_29
41 DIO_28
44 VDDS
43 DIO_30
46 X48M_N
45 VDDR
Pin Diagram – RGZ Package (Top View)
48 VDDR_RF
47 X48M_P
RF_P_2_4GHZ
1
36 DIO_23
RF_N_2_4GHZ
2
35 RESET_N
RF_P_SUB_1GHZ
3
34 VDDS_DCDC
RF_N_SUB_1GHZ
4
33 DCDC_SW
RX_TX
5
32 DIO_22
X32K_Q1
6
31 DIO_21
X32K_Q2
7
30 DIO_20
DIO_3
8
29 DIO_19
DIO_4
25 JTAG_TCKC
JTAG_TMSC 24
26 DIO_16
DIO_7 12
VDDS3 22
DCOUPL 23
DIO_6 11
DIO_14 20
DIO_15 21
27 DIO_17
DIO_12 18
DIO_13 19
28 DIO_18
VDDS2 13
DIO_8 14
9
DIO_5 10
DIO_9 15
DIO_10 16
DIO_11 17
4.1
Figure 4-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in Figure 4-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in Figure 4-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30
Terminal Configuration and Functions
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4.2
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Signal Descriptions – RGZ Package
Table 4-1. Signal Descriptions – RGZ Package
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
DCDC_SW
33
—
Power
Output from internal DC/DC converter (1)
DCOUPL
23
—
Power
For decoupling of internal 1.27 V regulated digital-supply
DIO_3
8
I/O
Digital
GPIO
DIO_4
9
I/O
Digital
GPIO
DIO_5
10
I/O
Digital
GPIO, high-drive capability
DIO_6
11
I/O
Digital
GPIO, high-drive capability
DIO_7
12
I/O
Digital
GPIO, high-drive capability
DIO_8
14
I/O
Digital
GPIO
DIO_9
15
I/O
Digital
GPIO
DIO_10
16
I/O
Digital
GPIO
DIO_11
17
I/O
Digital
GPIO
DIO_12
18
I/O
Digital
GPIO
DIO_13
19
I/O
Digital
GPIO
DIO_14
20
I/O
Digital
GPIO
DIO_15
21
I/O
Digital
GPIO
DIO_16
26
I/O
Digital
GPIO, JTAG_TDO, high-drive capability
DIO_17
27
I/O
Digital
GPIO, JTAG_TDI, high-drive capability
DIO_18
28
I/O
Digital
GPIO
DIO_19
29
I/O
Digital
GPIO
DIO_20
30
I/O
Digital
GPIO
DIO_21
31
I/O
Digital
GPIO
DIO_22
32
I/O
Digital
GPIO
DIO_23
36
I/O
Digital or Analog
GPIO, analog capability
DIO_24
37
I/O
Digital or Analog
GPIO, analog capability
DIO_25
38
I/O
Digital or Analog
GPIO, analog capability
DIO_26
39
I/O
Digital or Analog
GPIO, analog capability
DIO_27
40
I/O
Digital or Analog
GPIO, analog capability
DIO_28
41
I/O
Digital or Analog
GPIO, analog capability
DIO_29
42
I/O
Digital or Analog
GPIO, analog capability
DIO_30
43
I/O
Digital or Analog
GPIO, analog capability
EGP
—
—
GND
Ground – exposed ground pad (3)
JTAG_TMSC
24
I/O
Digital
JTAG TMSC, high-drive capability
JTAG_TCKC
25
I
Digital
JTAG TCKC
RESET_N
35
I
Digital
Reset, active low. No internal pullup resistor
RF_P_2_4GHZ
1
—
RF
Positive 2.4-GHz RF input signal to LNA during RX
Positive 2.4-GHz RF output signal from PA during TX
RF_N_2_4GHZ
2
—
RF
Negative 2.4-GHz RF input signal to LNA during RX
Negative 2.4-GHz RF output signal from PA during TX
RF_P_SUB_1GHZ
3
—
RF
Positive Sub-1 GHz RF input signal to LNA during RX
Positive Sub-1 GHz RF output signal from PA during TX
RF_N_SUB_1GHZ
4
—
RF
Negative Sub-1 GHz RF input signal to LNA during RX
Negative Sub-1 GHz RF output signal from PA during TX
RX_TX
5
—
RF
Optional bias pin for the RF LNA
(1)
(2)
(3)
8
(2)
For more details, see technical reference manual listed in Section 8.2.
Do not supply external circuitry from this pin.
EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions – RGZ Package (continued)
PIN
I/O
TYPE
45
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO (4) (2) (5)
VDDR_RF
48
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO (6) (2) (5)
VDDS
44
—
Power
1.8-V to 3.8-V main chip supply (1)
VDDS2
13
—
Power
1.8-V to 3.8-V DIO supply (1)
VDDS3
22
—
Power
1.8-V to 3.8-V DIO supply (1)
VDDS_DCDC
34
—
Power
1.8-V to 3.8-V DC/DC converter supply
X48M_N
46
—
Analog
48-MHz crystal oscillator pin 1
X48M_P
47
—
Analog
48-MHz crystal oscillator pin 2
X32K_Q1
6
—
Analog
32-kHz crystal oscillator pin 1
X32K_Q2
7
—
Analog
32-kHz crystal oscillator pin 2
NAME
NO.
VDDR
(4)
(5)
(6)
DESCRIPTION
If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
Output from internal DC/DC and LDO is trimmed to 1.68 V.
If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
4.3
Connections for Unused Pins and Modules
Table 4-2. Connections for Unused Pins
FUNCTION
GPIO
32.768-kHz crystal
DC/DC converter (2)
(1)
(2)
SIGNAL NAME
DIO_n
PIN NUMBER
ACCEPTABLE
PRACTICE (1)
PREFERRED
PRACTICE (1)
8–12
14–21
26–32
36–43
NC or GND
NC
NC or GND
NC
X32K_Q1
6
X32K_Q2
7
DCDC_SW
33
NC
NC
VDDS_DCDC
34
VDDS
VDDS
NC = No connect
When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.
Terminal Configuration and Functions
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5 Specifications
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDDS (3)
Vin
(2)
MIN
MAX
Supply voltage
–0.3
4.1
V
Voltage on any digital pin (4)
–0.3
VDDS + 0.3, max 4.1
V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
–0.3
VDDR + 0.3, max 2.25
V
Voltage scaling enabled
–0.3
VDDS
Voltage scaling disabled, internal reference
–0.3
1.49
Voltage scaling disabled, VDDS as reference
–0.3
VDDS / 2.9
Voltage on ADC input
Input level, Sub-1 GHz RF pins
Input level, 2.4 GHz RF pins
Tstg
(1)
(2)
(3)
(4)
5.2
VESD
(1)
(2)
5.3
Storage temperature
–40
UNIT
V
10
dBm
5
dBm
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground, unless otherwise noted.
VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
Including analog capable DIOs.
ESD Ratings
Electrostatic
discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
All pins
±2000
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2)
All pins
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Operating junction temperature (1)
–40
105
°C
Operating supply voltage (VDDS)
1.8
3.8
V
2.1
3.8
V
Rising supply voltage slew rate
0
100
mV/µs
Falling supply voltage slew rate (2)
0
20
mV/µs
Operating supply voltage (VDDS), boost mode
(1)
(2)
5.4
VDDR = 1.95 V
+14 dBm RF output power
For thermal resistance characteristics refer to Section 5.8. For application considerations, refer to Section 7.2.
For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TYP
VDDS Power-on-Reset (POR) threshold
VDDS Brown-out Detector (BOD)
(1)
VDDS Brown-out Detector (BOD), before initial boot
VDDS Brown-out Detector (BOD)
(1)
(2)
10
(1)
(2)
UNIT
1.1 - 1.55
V
Rising threshold
1.77
V
Rising threshold
1.70
V
Falling threshold
1.75
V
For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V)
Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
Specifications
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5.5
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
Power Consumption - Power Modes
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled
unless otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold
150
Shutdown. No clocks running, no retention
150
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
0.85
µA
RTC running, CPU, 80KB RAM and (partial) register retention
XOSC_LF
0.99
µA
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
2.78
µA
RTC running, CPU, 80KB RAM and (partial) register retention.
XOSC_LF
2.92
µA
Idle
Supply Systems and RAM powered
RCOSC_HF
590
µA
Active
MCU running CoreMark at 48 MHz
RCOSC_HF
2.89
mA
Peripheral power
domain
Delta current with domain enabled
82.3
Serial power domain
Delta current with domain enabled
5.5
RF Core
Delta current with power domain enabled,
clock enabled, RF core idle
µDMA
Delta current with clock enabled, module is idle
53.6
Timers
Delta current with clock enabled, module is idle (1)
67.8
I2C
Delta current with clock enabled, module is idle
8.2
I2S
Delta current with clock enabled, module is idle
21.7
SSI
Delta current with clock enabled, module is idle (2)
69.4
UART
Delta current with clock enabled, module is idle (3)
140.8
CRYPTO (AES)
Delta current with clock enabled, module is idle
21.1
PKA
Delta current with clock enabled, module is idle
71.1
TRNG
Delta current with clock enabled, module is idle
29.7
Reset and Shutdown
Standby
without cache retention
Icore
Standby
with cache retention
nA
Peripheral Current Consumption
Iperi
178.9
µA
Sensor Controller Engine Consumption
ISCE
(1)
(2)
(3)
Active mode
24 MHz, infinite loop, VDDS = 3.0 V
808.5
Low-power mode
2 MHz, infinite loop, VDDS = 3.0 V
30.1
µA
Only one GPTimer running
Only one SSI running
Only one UART running
Specifications
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CC1352R
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
5.6
www.ti.com
Power Consumption - Radio Modes
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled
unless otherwise noted.
Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm
setting where this current is already included).
Relevant Icore and Iperi currents are included in below numbers.
PARAMETER
TEST CONDITIONS
TYP
UNIT
5.8
mA
VDDS = 3.0 V
6.9
mA
0 dBm output power setting
868 MHz
8.0
mA
+10 dBm output power setting
868 MHz
14.3
mA
+14 dBm output power setting
868 MHz
24.9
mA
0 dBm output power setting, VDDS = 3.0 V
7.1
mA
+5 dBm output power setting
2440 MHz, VDDS = 3.0 V
9.6
mA
Radio receive current, 868 MHz
Radio receive current, 2.44 GHz
(BLE)
Radio transmit current
Sub-1 GHz PA
Radio transmit current
Boost mode, Sub-1 GHz PA
Radio transmit current
2.4 GHz PA (BLE)
5.7
Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Flash sector size
TYP
MAX
8
UNIT
KB
Supported flash erase cycles before failure, full bank (1)
30
k Cycles
Supported flash erase cycles before failure, single sector (2)
60
k Cycles
Maximum number of write operations per row before sector
erase (3)
Flash retention
105 °C
Flash sector erase current
Flash sector erase time
83
Average delta current
10.7
Flash write current
Average delta current, 4 bytes at a time
Flash write time (4)
4 bytes at a time
(1)
(2)
(3)
(4)
12
Years at
105 °C
11.4
(4)
Write
Operations
mA
10
ms
6.2
mA
21.6
µs
A full bank erase is counted as a single erase cycle on each sector
Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per
write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number
of write operations per row is reached.
This number is dependent on Flash aging and increases over time and erase cycles
Specifications
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5.8
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
Thermal Resistance Characteristics
PACKAGE
THERMAL METRIC
RGZ
(VQFN)
(1)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
23.4
°C/W (2)
RθJC(top)
Junction-to-case (top) thermal resistance
13.3
°C/W (2)
RθJB
Junction-to-board thermal resistance
8.0
°C/W (2)
ψJT
Junction-to-top characterization parameter
0.1
°C/W (2)
ψJB
Junction-to-board characterization parameter
7.9
°C/W (2)
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W (2)
(1)
(2)
5.9
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
Frequency bands
TYP
MAX
2360
2500
1076
1315
861
1054
431
527
359
439
287
351
UNIT
Specifications
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13
CC1352R
SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
www.ti.com
5.10 861 MHz to 1054 MHz - Receive (RX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4000
kHz
General Parameters
Digital channel filter programmable receive
bandwidth
4
Data rate step size
1.5
bps
< -57
dBm
< -47
dBm
–110
dBm
10
dBm
Selectivity, ±200 kHz
BER = 10 , 868 MHz
(1)
44
dB
Selectivity, ±400 kHz
BER = 10–2, 868 MHz (1)
48
dB
Blocking, ±1 MHz
BER = 10–2, 868 MHz (1)
57
dB
Spurious emissions 25 MHz to 1 GHz
Spurious emissions 1 GHz to 13 GHz
868 MHz
Conducted emissions measured according to ETSI EN 300 220
802.15.4g Mandatory Mode (50 kbps, 2-GFSK, 100 kHz RX Bandwidth)
Sensitivity
BER = 10–2, 868 MHz
Saturation limit
BER = 10–2
–2
Blocking, ±2 MHz
–2
BER = 10 , 868 MHz
(1)
61
dB
Blocking, ±5 MHz
–2
BER = 10 , 868 MHz
(1)
67
dB
Blocking, ±10 MHz
BER = 10–2, 868 MHz (1)
76
dB
Image rejection (image compensation
enabled)
BER = 10–2, 868 MHz (1)
39
dB
RSSI dynamic range
Starting from the sensitivity limit
95
dB
RSSI accuracy
Starting from the sensitivity limit across the given dynamic range
±3
dB
SimpleLink™ Long Range 2.5 kbps or 5 kbps (20 ksym/s, 2-GFSK, 5 kHz Deviation, FEC (Half Rate), DSSS = 1:2 or 1:4, 34 kHz RX Bandwidth
Sensitivity
2.5 kbps, BER = 10–2, 868 MHz
-121
dBm
Sensitivity
5 kbps, BER = 10–2, 868 MHz
-120
dBm
Saturation limit
BER = 10–2
10
dBm
–2
(1)
49
dB
Selectivity, ±200 kHz
–2
2.5 kbps, BER = 10 , 868 MHz
(1)
50
dB
Selectivity, ±300 kHz
2.5 kbps, BER = 10–2, 868 MHz (1)
51
dB
Blocking, ±1 MHz
2.5 kbps, BER = 10–2, 868 MHz (1)
63
dB
Blocking, ±2 MHz
2.5 kbps, BER = 10 , 868 MHz
(1)
68
dB
Blocking, ±5 MHz
2.5 kbps, BER = 10–2, 868 MHz (1)
78
dB
Blocking, ±10 MHz
2.5 kbps, BER = 10–2, 868 MHz (1)
88
dB
45
dB
Selectivity, ±100 kHz
2.5 kbps, BER = 10 , 868 MHz
–2
Image rejection (image compensation
enabled)
RSSI dynamic range
Starting from the sensitivity limit
97
dB
RSSI accuracy
Starting from the sensitivity limit across the given dynamic range
±3
dB
(1)
14
Wanted signal 3 dB above usable sensitivity limit according to ETSI EN 300 220 v. 3.1.1.
Specifications
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SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
5.11 861 MHz to 1054 MHz - Transmit (TX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General parameters
Max output power, boost mode
Sub-1 GHz PA (2)
VDDR = 1.95 V
Minimum supply voltage (VDDS ) for boost
mode is 2.1 V
868 MHz and 915 MHz
14
dBm
Max output power,
Sub-1 GHz PA (2)
868 MHz and 915 MHz
12
dBm
Output power programmable range
Sub-1 GHz PA
868 MHz and 915 MHz
24
dB
Output power variation over temperature
Sub-1 GHz PA
+10 dBm setting
Over recommended temperature operating
range
±2
dB
Output power variation over temperature
Boost mode, Sub-1 GHz PA
+14 dBm setting
Over recommended temperature operating
range
±1.5
dB
+14 dBm setting
ETSI restricted bands
< -54
dBm
+14 dBm setting
ETSI outside restricted bands
< -36
dBm
1 GHz to 12.75 GHz
(outside ETSI restricted bands)
+14 dBm setting
measured in 1 MHz bandwidth (ETSI)
< -30
dBm
30 MHz to 88 MHz
(within FCC restricted bands)
+14 dBm setting
< -56
dBm
88 MHz to 216 MHz
(within FCC restricted bands)
+14 dBm setting
< -52
dBm
216 MHz to 960 MHz
(within FCC restricted bands)
+14 dBm setting
< -50
dBm
960 MHz to 2390 MHz and above
2483.5 MHz (within FCC restricted
band)
+14 dBm setting
<-42
dBm
1 GHz to 12.75 GHz
(outside FCC restricted bands)
+14 dBm setting
< -40
dBm
Below 710 MHz
(ARIB T-108)
+14 dBm setting
< -36
dBm
710 MHz to 900 MHz
(ARIB T-108)
+14 dBm setting
< -55
dBm
900 MHz to 915 MHz
(ARIB T-108)
+14 dBm setting
< -55
dBm
930 MHz to 1000 MHz
(ARIB T-108)
+14 dBm setting
< -55
dBm
1000 MHz to 1215 MHz
(ARIB T-108)
+14 dBm setting
< -45
dBm
Above 1215 MHz
(ARIB T-108)
+14 dBm setting
< -30
dBm
+14 dBm setting, 868 MHz
< -30
+14 dBm setting, 915 MHz
< -30
+14 dBm setting, 868 MHz
< -30
+14 dBm setting, 915 MHz
< -42
+14 dBm setting, 868 MHz
< -30
+14 dBm setting, 915 MHz
< -30
+14 dBm setting, 868 MHz
< -30
+14 dBm setting, 915 MHz
< -42
Spurious emissions and harmonics
Spurious emissions
(excluding harmonics)
Sub-1 GHz PA, 868
MHz (3)
Spurious emissions outof-band
Sub-1 GHz PA, 915
MHz (3)
Spurious emissions outof-band
Sub-1 GHz PA,
920.6/928 MHz (3)
30 MHz to 1 GHz
Second harmonic
Third harmonic
Harmonics
Sub-1 GHz PA
Fourth harmonic
Fifth harmonic
(1)
(2)
(3)
dBm
dBm
dBm
dBm
Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory
compliance. More details can be found in the device errata.
Output power is dependent on RF match. For dual-band devices in the CC13X2 platform, output power might be slightly reduced
depending on RF layout trade-offs.
Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
Specifications
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5.12 861 MHz to 1054 MHz - PLL Phase Noise
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
±10 kHz offset
Phase noise in the 868- and 915-MHz
bands (1)
(1)
16
TYP
MAX
UNIT
–74
dBc/Hz
±100 kHz offset
–97
dBc/Hz
±200 kHz offset
–107
dBc/Hz
±400 kHz offset
–113
dBc/Hz
±1000 kHz offset
–120
dBc/Hz
±2000 kHz offset
–127
dBc/Hz
±10000 kHz offset
–141
dBc/Hz
PLL settings for improved close-in phase noise for narrow-band operation will be added later.
Specifications
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SWRS196F – JANUARY 2018 – REVISED SEPTEMBER 2019
5.13 Bluetooth Low Energy - Receive (RX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125 kbps (LE Coded)
Receiver sensitivity
Differential mode. BER = 10–3
–105
dBm
Receiver saturation
–3
Differential mode. BER = 10
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–300 / 300)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–320 / 240)
ppm
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (255-byte packets)
> (–125 / 125)
ppm
Co-channel rejection (1)
Wanted signal at –79 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±1 MHz (1)
–1.5
dB
Wanted signal at –79 dBm, modulated interferer at ±1
MHz, BER = 10–3
8 / 4.5 (2)
dB
Selectivity, ±2 MHz (1)
Wanted signal at –79 dBm, modulated interferer at ±2
MHz, BER = 10–3
44 / 39 (2)
dB
Selectivity, ±3 MHz (1)
Wanted signal at –79 dBm, modulated interferer at ±3
MHz, BER = 10–3
46 / 44 (2)
dB
Selectivity, ±4 MHz (1)
Wanted signal at –79 dBm, modulated interferer at ±4
MHz, BER = 10–3
44 / 46 (2)
dB
Selectivity, ±6 MHz (1)
Wanted signal at –79 dBm, modulated interferer at ≥ ±6
MHz, BER = 10–3
48 / 44 (2)
dB
Selectivity, ±7 MHz
Wanted signal at –79 dBm, modulated interferer at ≥ ±7
MHz, BER = 10–3
51 / 45 (2)
dB
Selectivity, Image frequency (1)
Wanted signal at –79 dBm, modulated interferer at image
frequency, BER = 10–3
39
dB
Selectivity, Image frequency ±1
MHz (1)
Note that Image frequency + 1 MHz is the Co- channel –1
MHz. Wanted signal at –79 dBm, modulated interferer at
±1 MHz from image frequency, BER = 10–3
(2)
dB
4.5 / 44
500 kbps (LE Coded)
Receiver sensitivity
Differential mode. BER = 10–3
–100
dBm
Receiver saturation
Differential mode. BER = 10–3
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–300 / 300)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–450 / 450)
ppm
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (255-byte packets)
> (–175 / 175)
ppm
Co-channel rejection (1)
Wanted signal at –72 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±1 MHz (1)
–3.5
dB
Wanted signal at –72 dBm, modulated interferer at ±1
MHz, BER = 10–3
8 / 4 (2)
dB
Selectivity, ±2 MHz (1)
Wanted signal at –72 dBm, modulated interferer at ±2
MHz, BER = 10–3
44 / 37 (2)
dB
Selectivity, ±3 MHz (1)
Wanted signal at –72 dBm, modulated interferer at ±3
MHz, BER = 10–3
46 / 46 (2)
dB
Selectivity, ±4 MHz (1)
Wanted signal at –72 dBm, modulated interferer at ±4
MHz, BER = 10–3
45 / 47 (2)
dB
Selectivity, ±6 MHz (1)
Wanted signal at –72 dBm, modulated interferer at ≥ ±6
MHz, BER = 10–3
46 / 45 (2)
dB
Selectivity, ±7 MHz
Wanted signal at –72 dBm, modulated interferer at ≥ ±7
MHz, BER = 10–3
49 / 45 (2)
dB
(1)
(2)
Numbers given as I/C dB
X / Y, where X is +N MHz and Y is –N MHz
Specifications
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CC1352R
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www.ti.com
Bluetooth Low Energy - Receive (RX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
Selectivity, Image frequency
TEST CONDITIONS
(1)
Selectivity, Image frequency ±1
MHz (1)
MIN
TYP
MAX
UNIT
Wanted signal at –72 dBm, modulated interferer at image
frequency, BER = 10–3
37
dB
Note that Image frequency + 1 MHz is the Co- channel –1
MHz. Wanted signal at –72 dBm, modulated interferer at
±1 MHz from image frequency, BER = 10–3
4 / 46 (2)
dB
1 Mbps (LE 1M)
Receiver sensitivity
Differential mode. BER = 10–3
–97
dBm
Receiver saturation
Differential mode. BER = 10–3
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–350 / 350)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–750 / 750)
ppm
Co-channel rejection (1)
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±1 MHz (1)
–6
dB
Wanted signal at –67 dBm, modulated interferer at ±1
MHz, BER = 10–3
7 / 4 (2)
dB
Selectivity, ±2 MHz (1)
Wanted signal at –67 dBm, modulated interferer at ±2
MHz,BER = 10–3
40 / 33 (2)
dB
Selectivity, ±3 MHz (1)
Wanted signal at –67 dBm, modulated interferer at ±3
MHz, BER = 10–3
36 / 41 (2)
dB
Selectivity, ±4 MHz (1)
Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3
36 / 45 (2)
dB
Selectivity, ±5 MHz or more (1)
Wanted signal at –67 dBm, modulated interferer at ≥ ±5
MHz, BER = 10–3
40
dB
Selectivity, image frequency (1)
Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3
33
dB
Selectivity, image frequency
±1 MHz (1)
Note that Image frequency + 1 MHz is the Co- channel –1
MHz. Wanted signal at –67 dBm, modulated interferer at
±1 MHz from image frequency, BER = 10–3
4 / 41 (2)
dB
Out-of-band blocking (3)
30 MHz to 2000 MHz
–10
dBm
Out-of-band blocking
2003 MHz to 2399 MHz
–18
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
–12
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz
–2
dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers at
2405 and 2408 MHz respectively, at the given power
level
–42
dBm
Spurious emissions,
30 to 1000 MHz (4)
Measurement in a 50-Ω single-ended load.
< –59
dBm
Spurious emissions,
1 to 12.75 GHz (4)
Measurement in a 50 Ω single-ended load.
< –47
dBm
RSSI dynamic range
70
dB
RSSI accuracy
±4
dB
2 Mbps (LE 2M)
Receiver sensitivity
Differential mode. Measured at SMA connector, BER =
10–3
–92
dBm
Receiver saturation
Differential mode. Measured at SMA connector, BER =
10–3
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–500 / 500)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–700 / 750)
ppm
(3)
(4)
18
Excluding one exception at Fwanted / 2, per Bluetooth Specification
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Specifications
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Bluetooth Low Energy - Receive (RX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
Co-channel rejection
(1)
TEST CONDITIONS
Wanted signal at –67 dBm, modulated interferer in
channel,BER = 10–3
MIN
TYP
MAX
UNIT
–7
dB
Selectivity, ±2 MHz (1)
Wanted signal at –67 dBm, modulated interferer at ±2
MHz, Image frequency is at –2 MHz, BER = 10–3
8 / 4 (2)
dB
Selectivity, ±4 MHz (1)
Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3
36 / 36 (2)
dB
Selectivity, ±6 MHz (1)
Wanted signal at –67 dBm, modulated interferer at ±6
MHz, BER = 10–3
37 / 36 (2)
dB
Selectivity, image frequency (1)
Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3
4
dB
Selectivity, image frequency
±2 MHz (1)
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at ±2
MHz from image frequency, BER = 10–3
–7 / 36 (2)
dB
Out-of-band blocking (3)
30 MHz to 2000 MHz
–16
dBm
Out-of-band blocking
2003 MHz to 2399 MHz
–21
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
–15
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz
–12
dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers at
2405 and 2408 MHz respectively, at the given power
level
–38
dBm
Specifications
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5.14 Bluetooth Low Energy - Transmit (TX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Max output power, 2.4
Differential mode, delivered to a single-ended 50 Ω load through a balun
GHz PA
Output power
programmable range,
2.4 GHz PA
Differential mode, delivered to a single-ended 50 Ω load through a balun
5
dBm
26
dB
Spurious emissions and harmonics
Spurious emissions,
2.4 GHz PA (1)
f < 1 GHz, outside restricted bands
< –36
dBm
f < 1 GHz, restricted bands ETSI
< –54
dBm
f < 1 GHz, restricted bands FCC
< –55
dBm
< –42
dBm
Second harmonic
< –42
dBm
Third harmonic
< –42
dBm
f > 1 GHz, including harmonics
Harmonics,
2.4 GHz PA (1)
(1)
20
+5 dBm setting
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
Specifications
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5.15 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver sensitivity
PER = 1%
–100
dBm
Receiver saturation
PER = 1%
>5
dBm
Adjacent channel rejection
Wanted signal at –82 dBm, modulated interferer at ±5 MHz,
PER = 1%
36
dB
Alternate channel rejection
Wanted signal at –82 dBm, modulated interferer at ±10
MHz, PER = 1%
57
dB
Channel rejection, ±15 MHz or more
Wanted signal at –82 dBm, undesired signal is IEEE
802.15.4 modulated channel, stepped through all channels
2405 to 2480 MHz, PER = 1%
59
dB
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
57
dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
63
dB
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
63
dB
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
66
dB
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
60
dB
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
60
dB
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
63
dB
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
65
dB
Spurious emissions, 30 MHz to 1000
MHz
Measurement in a 50-Ω single-ended load
–66
dBm
Spurious emissions, 1 GHz to 12.75
GHz
Measurement in a 50-Ω single-ended load
–53
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and the
internally generated carrier frequency
> 350
ppm
Symbol rate error tolerance
Difference between incoming symbol rate and the internally
generated symbol rate
> 1000
ppm
RSSI dynamic range
95
dB
RSSI accuracy
±4
dB
Specifications
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5.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Max output power, 2.4
GHz PA
Differential mode, delivered to a single-ended 50-Ω load through a balun
5
dBm
Output power
programmable range,
2.4 GHz PA
Differential mode, delivered to a single-ended 50-Ω load through a balun
26
dB
Spurious emissions and harmonics
f < 1 GHz, outside restricted
bands
Spurious emissions,
2.4 GHz PA (1) (2)
Harmonics,
2.4 GHz PA (1)
< -36
dBm
< -47
dBm
< -55
dBm
f > 1 GHz, including harmonics
< –42
dBm
Second harmonic
< -42
dBm
Third harmonic
< -42
dBm
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
+5 dBm setting
IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)
Error vector magnitude,
2.4-GHz PA
(1)
(2)
22
+5 dBm setting
2
%
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than
100% duty cycle may be used when operating at 2480 MHz.
Specifications
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5.17 Timing and Switching Characteristics
Table 5-1. Reset Timing
PARAMETER
MIN
RESET_N low duration
TYP
MAX
UNIT
1
µs
Table 5-2. Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCU, Reset to Active (1)
850 - 3000
µs
MCU, Shutdown to Active (1)
850 - 3000
µs
MCU, Standby to Active
160
µs
MCU, Active to Standby
36
µs
MCU, Idle to Active
14
µs
(1)
The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has
been in Reset or Shutdown before starting up again.
Specifications
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5.17.1 Clock Specifications
Table 5-3. 48 MHz Crystal Oscillator (XOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. (1)
PARAMETER
MIN
TYP
Crystal frequency
48
ESR
Equivalent series resistance
6 pF < CL ≤ 9 pF
20
ESR
Equivalent series resistance
5 pF < CL ≤ 6 pF
LM
Motional inductance, relates to the load capacitance that is used for the crystal (CL
in Farads) (2)
CL
Crystal load capacitance
(3)
5
7
(4)
(5)
UNIT
MHz
60
Ω
80
Ω
< 3 × 10–24 / CL2
Start-up time (5)
(1)
(2)
(3)
MAX
H
(4)
9
200
pF
µs
Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
The crystal manufacturer's specification must satisfy this requirement for proper operation.
Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certaain regulations. See the device errata for further details.
On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
Table 5-4. 48 MHz RC Oscillator (RCOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Frequency
48
MHz
Uncalibrated frequency accuracy
±1
%
Calibrated frequency accuracy (1)
±0.25
%
5
µs
Start-up time
(1)
Accuracy relative to the calibration source (XOSC_HF)
Table 5-5. 2 MHz RC Oscillator (RCOSC_MF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Calibrated frequency
2
MHz
Start-up time
5
µs
Table 5-6. 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
Crystal frequency
ESR
Equivalent series resistance
CL
Crystal load capacitance
(1)
TYP
MAX
32.768
6
UNIT
kHz
30
100
kΩ
7 (1)
12
pF
Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
Table 5-7. 32 kHz RC Oscillator (RCOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
Calibrated frequency
Temperature coefficient
(1)
24
TYP
32.8
MAX
UNIT
(1)
kHz
50
ppm/°C
When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
Specifications
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5.17.2 Synchronous Serial Interface (SSI) Characteristics
Table 5-8. Synchronous Serial Interface (SSI) Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
NO.
PARAMETER
MIN
TYP
65024
UNIT
S1
tclk_per
SSIClk cycle time
S2 (2)
tclk_high
SSIClk high time
0.5
tclk_per
S3 (2)
tclk_low
SSIClk low time
0.5
tclk_per
(1)
(2)
12
MAX
System Clocks
(1)
When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
S1
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
Specifications
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S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
SSIRx
(Slave)
MSB
LSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
5.17.3 UART
Table 5-9. UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
UART rate
26
TYP
MAX
3
Specifications
UNIT
MBaud
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5.18 Peripheral Characteristics
5.18.1 ADC
Table 5-10. Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted. (1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
Input voltage range
TYP
0
Resolution
12
Sample Rate
V
Bits
200
ksps
Internal 4.3 V equivalent reference (2)
–0.24
LSB
Gain error
Internal 4.3 V equivalent reference (2)
7.14
LSB
>–1
LSB
±4
LSB
Differential nonlinearity
INL
Integral nonlinearity
THD
UNIT
Offset
DNL (3)
ENOB
MAX
VDDS
Effective number of bits
Total harmonic distortion
Internal 4.3 V equivalent reference (2), 200 kSamples/s,
9.6 kHz input tone
9.8
Internal 4.3 V equivalent reference (2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled
9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
10.1
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
11.1
Internal reference, voltage scaling disabled,
14-bit mode, 200 kSamples/s, 300 Hz input tone
(4)
11.3
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 300 Hz input tone
(4)
11.6
Internal 4.3 V equivalent reference (2), 200 kSamples/s,
9.6 kHz input tone
–65
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
–70
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
–72
Bits
Bits
(2)
SINAD,
SNDR
Signal-to-noise
and
distortion ratio
Internal 4.3 V equivalent reference , 200 kSamples/s,
9.6 kHz input tone
60
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
63
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
68
dB
(2)
Internal 4.3 V equivalent reference , 200 kSamples/s,
9.6 kHz input tone
SFDR
(1)
(2)
(3)
(4)
(5)
70
Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
73
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
75
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Current consumption
Internal 4.3 V equivalent reference (2)
Current consumption
VDDS as reference
Reference voltage
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the
gain/offset compensation factors stored in FCFG1
Reference voltage
Fixed internal reference (input voltage scaling disabled). For
best accuracy, the ADC conversion should be initiated through
the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage
VDDS as reference, input voltage scaling enabled
50
dB
Clock Cycles
0.42
mA
0.6
mA
4.3 (2) (5)
V
1.48
V
VDDS
V
Using IEEE Std 1241-2010 for terminology and test methods
Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
No missing codes
ADC_output = Σ(4n samples ) >> n, n = desired extra bits
Applied voltage must be within Absolute Maximum Ratings (see Section 5.1 ) at all times
Specifications
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Table 5-10. Analog-to-Digital Converter (ADC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
28
TEST CONDITIONS
MIN
Reference voltage
VDDS as reference, input voltage scaling disabled
Input impedance
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
Specifications
TYP
VDDS /
2.82 (5)
>1
MAX
UNIT
V
MΩ
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5.18.2 DAC
Table 5-11. Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Resolution
VDDS
FDAC
Supply voltage
Clock frequency
Voltage output settling time
8
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
1.8
3.8
External Load (1), any VREF, pre-charge OFF, DAC chargepump OFF
2.0
3.8
Any load, VREF = DCOUPL, pre-charge ON
2.6
3.8
Buffer ON (recommended for external load)
16
250
Buffer OFF (internal load)
16
1000
VREF = VDDS, buffer OFF, internal load
13
VREF = VDDS, buffer ON, external capacitive load = 20 pF (2)
20
External resistive load
200
10
kHz
pF
MΩ
Short circuit current
Max output impedance Vref
= VDDS, buffer ON, CLK
250 kHz
V
1 / FDAC
13.8
External capacitive load
ZMAX
Bits
400
VDDS = 3.8 V, DAC charge-pump OFF
50.8
VDDS = 3.0 V, DAC charge-pump ON
51.7
VDDS = 3.0 V, DAC charge-pump OFF
53.2
VDDS = 2.0 V, DAC charge-pump ON
48.7
VDDS = 2.0 V, DAC charge-pump OFF
70.2
VDDS = 1.8 V, DAC charge-pump ON
46.3
VDDS = 1.8 V, DAC charge-pump OFF
88.9
µA
kΩ
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
Differential nonlinearity
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 250 kHz
±1
Differential nonlinearity
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 16 kHz
±1.2
DNL
Offset error (4)
Load = Continuous Time
Comparator
Offset error (4)
Load = Low Power Clocked
Comparator
Max code output voltage
variation (4)
Load = Continuous Time
Comparator
(1)
(2)
(3)
(4)
LSB (3)
VREF = VDDS = 3.8 V
±0.64
VREF = VDDS = 3.0 V
±0.81
VREF = VDDS = 1.8 V
±1.27
VREF = DCOUPL, pre-charge ON
±3.43
VREF = DCOUPL, pre-charge OFF
±2.88
VREF = ADCREF
±2.37
VREF = VDDS = 3.8 V
±0.78
VREF = VDDS = 3.0 V
±0.77
VREF = VDDS = 1.8 V
±3.46
VREF = DCOUPL, pre-charge ON
±3.44
VREF = DCOUPL, pre-charge OFF
±4.70
VREF = ADCREF
±4.11
VREF = VDDS = 3.8 V
±1.53
VREF = VDDS = 3.0 V
±1.71
VREF = VDDS = 1.8 V
±2.10
VREF = DCOUPL, pre-charge ON
±6.00
VREF = DCOUPL, pre-charge OFF
±3.85
VREF = ADCREF
±5.84
LSB (3)
LSB (3)
LSB (3)
Keysight 34401A Multimeter
A load > 20 pF will increases the settling time
1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
Includes comparator offset
Specifications
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Table 5-11. Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Max code output voltage
variation (4)
Load = Low Power Clocked
Comparator
Output voltage range (4)
Load = Continuous Time
Comparator
Output voltage range (4)
Load = Low Power Clocked
Comparator
TEST CONDITIONS
MIN
TYP
VREF = VDDS = 3.8 V
±2.92
VREF =VDDS = 3.0 V
±3.06
VREF = VDDS = 1.8 V
±3.91
VREF = DCOUPL, pre-charge ON
±7.84
VREF = DCOUPL, pre-charge OFF
±4.06
VREF = ADCREF
±6.94
VREF = VDDS = 3.8 V, code 1
0.03
VREF = VDDS = 3.8 V, code 255
3.62
VREF = VDDS = 3.0 V, code 1
0.02
VREF = VDDS = 3.0 V, code 255
2.86
VREF = VDDS = 1.8 V, code 1
0.01
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.01
VREF = DCOUPL, pre-charge OFF, code 255
1.21
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
VREF = ADCREF, code 1
0.01
VREF = ADCREF, code 255
1.41
VREF = VDDS = 3.8 V, code 1
0.03
VREF = VDDS = 3.8 V, code 255
3.61
VREF = VDDS = 3.0 V, code 1
0.02
VREF = VDDS = 3.0 V, code 255
2.85
VREF = VDDS = 1.8 V, code 1
0.01
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.01
VREF = DCOUPL, pre-charge OFF, code 255
1.21
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
VREF = ADCREF, code 1
0.01
VREF = ADCREF, code 255
1.41
MAX
UNIT
LSB (3)
V
V
External Load (Keysight 34401A Multimeter)
INL
Integral nonlinearity
DNL
Differential nonlinearity
Offset error
Max code output voltage
variation
30
VREF = VDDS, FDAC = 250 kHz
±1
VREF = DCOUPL, FDAC = 250 kHz
±1
VREF = ADCREF, FDAC = 250 kHz
±1
VREF = VDDS, FDAC = 250 kHz
±1
VREF = VDDS = 3.8 V
±0.20
VREF = VDDS = 3.0 V
±0.25
VREF = VDDS = 1.8 V
±0.45
VREF = DCOUPL, pre-charge ON
±1.55
VREF = DCOUPL, pre-charge OFF
±1.30
VREF = ADCREF
±1.10
VREF = VDDS = 3.8 V
±0.60
VREF = VDDS = 3.0 V
±0.55
VREF = VDDS = 1.8 V
±0.60
VREF = DCOUPL, pre-charge ON
±3.45
VREF = DCOUPL, pre-charge OFF
±2.10
VREF = ADCREF
±1.90
Specifications
LSB (3)
LSB (3)
LSB (3)
LSB (3)
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Table 5-11. Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Output voltage range
Load = Low Power Clocked
Comparator
TEST CONDITIONS
MIN
TYP
VREF = VDDS = 3.8 V, code 1
0.03
VREF = VDDS = 3.8 V, code 255
3.61
VREF = VDDS = 3.0 V, code 1
0.02
VREF = VDDS = 3.0 V, code 255
2.85
VREF = VDDS = 1.8 V, code 1
0.02
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.02
VREF = DCOUPL, pre-charge OFF, code 255
1.20
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
VREF = ADCREF, code 1
0.02
VREF = ADCREF, code 255
1.42
MAX
UNIT
V
Specifications
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5.18.3 Temperature and Battery Monitor
Table 5-12. Temperature Sensor
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
2
°C
°C
Accuracy
-40 °C to 0 °C
±4.0
Accuracy
0 °C to 85 °C
±2.5
°C
3.6
°C/V
Supply voltage coefficient (1)
(1)
The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
Table 5-13. Battery Monitor
Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
Range
1.8
Integral nonlinearity (max)
Accuracy
MAX
25
mV
3.8
V
23
mV
22.5
mV
Offset error
-32
mV
Gain error
-1
%
32
VDDS = 3.0 V
UNIT
Specifications
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5.18.4 Comparators
Table 5-14. Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range (1)
TYP
0
Offset
Measured at VDDS / 2
Decision time
Step from –10 mV to 10 mV
Current consumption
Internal reference
(1)
MIN
MAX
UNIT
VDDS
V
±5
mV
0.78
µs
8.6
µA
The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC.
Table 5-15. Low-Power Clocked Comparator
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range
MIN
Clock frequency
MAX
UNIT
VDDS
V
SCLK_LF
Internal reference voltage (1)
Using internal DAC with VDDS as reference voltage,
DAC code = 0 - 255
Offset
Measured at VDDS / 2, includes error from internal DAC
Decision time
(1)
TYP
0
0.024 - 2.865
Step from –50 mV to 50 mV
V
±5
mV
1
Clock
Cycle
The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See Table 5-11.
5.18.5 Current Source
Table 5-16. Programmable Current Source
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Current source programmable output range (logarithmic
range)
Resolution
MIN
TYP
MAX
0.25 - 20
µA
0.25
µA
Specifications
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5.18.6 GPIO
Table 5-17. GPIO DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
1.56
V
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
0.24
V
GPIO VOH at 4 mA load
IOCURR = 1
1.59
V
GPIO VOL at 4 mA load
IOCURR = 1
0.21
V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
73
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
19
µA
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.08
V
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
0.73
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.35
V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
2.59
V
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
0.42
V
GPIO VOH at 4 mA load
IOCURR = 1
2.63
V
GPIO VOL at 4 mA load
IOCURR = 1
0.40
V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
282
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
110
µA
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.97
V
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
1.55
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.42
V
TA = 25 °C, VDDS = 3.0 V
TA = 25 °C, VDDS = 3.8 V
TA = 25 °C
VIH
Lowest GPIO input voltage reliably interpreted as a
High
VIL
Highest GPIO input voltage reliably interpreted as a
Low
34
Specifications
0.8*VDDS
V
0.2*VDDS
V
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5.19 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Recommended Operating Conditions, Section 5.3, for device limits. Values exceeding these limits are for
reference only.
5.19.1 MCU Current
Active Current vs. VDDS
Running CoreMark, SCLK_HF = 48 MHz RCOSC
6
5.5
Current [mA]
5
4.5
4
3.5
3
2.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Voltage [V]
3.6
3.8
D001
Figure 5-4. Active Mode (MCU) Current vs.
Supply Voltage (VDDS)
Specifications
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Standby Current vs. Temperature
80 kB RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz XOSC
12
Current [µA]
10
8
6
4
2
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
D006
Figure 5-5. Standby Mode (MCU) Current vs.
Temperature
Standby Current vs. Temperature
80 kB RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz XOSC VDDS = 3.6 V
12
Current [µA]
10
8
6
4
2
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
90
100
D007
Figure 5-6. Standby Mode (MCU) Current vs.
Temperature (VDDS = 3.6 V)
36
Specifications
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5.19.2 RX Current
RX Current vs. Temperature
50 kbps, 868.3 MHz
8
7.8
7.6
7.4
Current [mA]
7.2
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
D008
Figure 5-7. RX Current vs.
Temperature (50 kbps, 868.3 MHz)
RX Current vs. Temperature
50 kbps, 868.3 MHz, VDDS = 3.6 V
8
7.8
7.6
7.4
Current [mA]
7.2
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
100
D009
Figure 5-8. RX Current vs.
Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V)
Specifications
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RX Current vs. Temperature
Current [mA]
BLE 1 Mbps, 2.44 GHz
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6.6
6.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
100
D010
Figure 5-9. RX Current vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
RX Current vs. VDDS
50 kbps, 868.3 MHz
11.5
11
10.5
Current [mA]
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Voltage [V]
3.6
3.8
D012
Figure 5-10. RX Current vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
38
Specifications
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RX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz
11.5
11
10.5
Current [mA]
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Voltage [V]
3.6
3.8
D013
Figure 5-11. RX Current vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Specifications
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5.19.3 TX Current
TX Current vs. Temperature
Current [mA]
50 kbps, 868.3 MHz, +10 dBm
18
17.7
17.4
17.1
16.8
16.5
16.2
15.9
15.6
15.3
15
14.7
14.4
14.1
13.8
13.5
13.2
12.9
12.6
12.3
12
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
D014
Figure 5-12. TX Current vs.
Temperature (50 kbps, 868.3 MHz)
TX Current vs. Temperature
Current [mA]
50 kbps, 868.3 MHz, +10 dBm, VDDS = 3.6 V
18
17.7
17.4
17.1
16.8
16.5
16.2
15.9
15.6
15.3
15
14.7
14.4
14.1
13.8
13.5
13.2
12.9
12.6
12.3
12
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
90
100
D015
Figure 5-13. TX Current vs.
Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V)
40
Specifications
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TX Current vs. Temperature
Current [mA]
BLE 1 Mbps, 2.44 GHz, 0 dBm
9
8.85
8.7
8.55
8.4
8.25
8.1
7.95
7.8
7.65
7.5
7.35
7.2
7.05
6.9
6.75
6.6
6.45
6.3
6.15
6
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
90
100
D018
Figure 5-14. TX Current vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
TX Current vs. VDDS
50 kbps, 868.3 MHz, +10 dBm
26
25
24
23
Current [mA]
22
21
20
19
18
17
16
15
14
13
12
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
D022
Figure 5-15. TX Current vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
Specifications
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TX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz, 0 dBm
12
11.5
11
10.5
Current [mA]
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Voltage [V]
3.6
3.8
D024
Figure 5-16. TX Current vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
42
Specifications
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Table 5-18 and Table 5-19 show typical TX current and output power for different output power settings.
Table 5-18. Typical TX Current and Output Power (915 MHz, VDDS = 3.6 V)
CC1352R at 915 MHz, VDDS = 3.6 V (Measured on CC1352REM-XD7793-XD24)
txPower
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
0x013F
14
13.6
24.2
0xB224
12.5
12
17.6
0xA410
12
11.5
16.5
0x669A
11
10.5
14.9
0x3E92
10
9.4
13.5
0x3EDC
9
8.5
12.7
0x2CD8
8
7.7
11.9
0x26D4
7
6.5
11
0x20D1
6
5.4
10.2
0x1CCE
5
3.8
9.3
0x16CD
4
3.2
9
0x14CB
3
1.7
8.3
0x12CA
2
0.8
8
0x12C9
1
-0.3
7.6
0x10C8
0
-1.4
7.3
0x0AC4
-5
-8.6
5.8
0x0AC2
-10
-15.9
5.1
0x06C1
-15
-22.3
4.8
0x04C0
-20
-24.4
4.6
Table 5-19. Typical TX Current and Output Power (2.4 GHz, VDDS = 3.0 V)
CC1352R at 2.4 GHz, VDDS = 3.0 V (Measured on CC1352REM-XD7793-XD24)
txPower
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
0x7217
5
4.4
9.6
0x4E63
4
3.0
8.9
0x385D
3
1.8
8.3
0x3259
2
0.7
7.9
0x2856
1
-0.3
7.5
0x2853
0
-1.5
7.1
0x12D6
-5
-6.7
6.1
0x0ACF
-10
-11.5
5.5
0x06CA
-15
-16.7
5.1
0x04C6
-20
-22.7
4.8
Specifications
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5.19.4 RX Performance
Sensitivity vs. Frequency
50 kbps
-105
-106
Sensitivity [dBm ]
-107
-108
-109
-110
-111
-112
-113
-114
-115
863
864
865
866
867
868
869
870
Frequency [MHz]
D026
Figure 5-17. Sensitivity vs.
Frequency (50 kbps, 868 MHz)
Sensitivity vs. Frequency
50 kbps
-105
-106
Sensitivity [dBm ]
-107
-108
-109
-110
-111
-112
-113
-114
-115
900
903
906
909
912
915
918
921
Frequency [MHz]
924
927
930
D027
Figure 5-18. Sensitivity vs.
Frequency (50 kbps, 915 MHz)
44
Specifications
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Sensitivity vs. Frequency
BLE 1 Mbps, 2.44 GHz
-92
-93
Sensitivity [dBm]
-94
-95
-96
-97
-98
-99
-100
-101
-102
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
2.472
Frequency [GHz]
2.48
D028
Figure 5-19. Sensitivity vs.
Frequency (BLE 1 Mbps, 2.44 GHz)
Sensitivity vs. Frequency
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps)
-95
-96
Sensitivity [dBm ]
-97
-98
-99
-100
-101
-102
-103
-104
-105
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
Frequency [GHz]
2.464
2.472
2.48
D029
Figure 5-20. Sensitivity vs.
Frequency (250 kbps, 2.44 GHz)
Specifications
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Sensitivity vs. Temperature
50 kbps, 868.3 MHz
-105
-106
Sensitivity [dBm]
-107
-108
-109
-110
-111
-112
-113
-114
-115
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
D030
Figure 5-21. Sensitivity vs.
Temperature (50 kbps, 868.3 MHz)
Sensitivity vs. Temperature
BLE 1 Mbps, 2.44 GHz
-92
-93
Sensitivity [dBm]
-94
-95
-96
-97
-98
-99
-100
-101
-102
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Temperature [°C]
80
90
100
D031
Figure 5-22. Sensitivity vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
46
Specifications
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Sensitivity vs. Temperature
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-95
-96
Sensitivity [dBm]
-97
-98
-99
-100
-101
-102
-103
-104
-105
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
100
D032
Figure 5-23. Sensitivity vs.
Temperature (250 kbps, 2.44 GHz)
Sensitivity vs. VDDS
50 kbps, 868.3 MHz
-105
-106
Sensitivity [dBm ]
-107
-108
-109
-110
-111
-112
-113
-114
-115
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Voltage [V]
3.6
3.8
D033
Figure 5-24. Sensitivity vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
Specifications
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Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz
-92
-93
Sensitivity [dBm]
-94
-95
-96
-97
-98
-99
-100
-101
-102
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
3.8
D034
Figure 5-25. Sensitivity vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz, DCDC Off
-92
-93
Sensitivity [dBm]
-94
-95
-96
-97
-98
-99
-100
-101
-102
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
3.8
D035
Figure 5-26. Sensitivity vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, DCDC Off)
48
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Sensitivity vs. VDDS
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-95
-96
Sensitivity [dBm ]
-97
-98
-99
-100
-101
-102
-103
-104
-105
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
3.8
D036
Figure 5-27. Sensitivity vs.
Supply Voltage (VDDS) (250 kbps, 2.44 GHz)
Selectivity vs. Frequency Offset
50 kbps, 868.3 MHz
80
Selectivity [dB]
60
40
20
0
-20
-10
-8
-6
-4
-2
0
2
4
6
Frequency [MHz]
8
10
D038
Figure 5-28. Selectivity vs.
Frequency Offset (50 kbps, 868.3 MHz)
Specifications
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Packet error rate vs level and frequency offset for SLR 5 kbps.
0
100
90
-20
80
70
Level [dBm]
-40
60
-60
50
40
-80
30
-100
20
10
-120
0
-30
-20
-10
0
10
20
30
Offset frequency [ppm]
Figure 5-29. PER vs. Level vs.
Frequency (SimpleLink™ Long Range 5 kbps)
50
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5.19.5 TX Performance
Output Power vs. Temperature
50 kbps, 868.3 MHz, +14 dBm
14
13.8
Output Power [dBm]
13.6
13.4
13.2
13
12.8
12.6
12.4
12.2
12
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
D039
Figure 5-30. Output Power vs.
Temperature (50 kbps, 868.3 MHz)
Output Power vs. Temperature
Output Power [dBm]
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Temperature [°C]
80
90
100
D041
Figure 5-31. Output Power vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
Specifications
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Output Power vs. Temperature
Output Power [dBm]
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
90
100
D042
Figure 5-32. Output Power vs.
Temperature (BLE 1 Mbps, 2.44 GHz, +5 dBm)
Output Power vs. VDDS
Output Power [dBm]
50 kbps, 868.3 MHz, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
D044
Figure 5-33. Output Power vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
52
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Output Power vs. VDDS
Output Power [dBm]
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
3.8
D046
Figure 5-34. Output Power vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Output power vs. VDDS
Output Power [dBm]
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
3.8
D048
Figure 5-35. Output Power vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, +5 dBm)
Specifications
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Output Power vs. Frequency
Output Power [dBm]
50 kbps, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
863
864
865
866
867
868
869
870
Frequency [MHz]
D052
Figure 5-36. Output Power vs.
Frequency (50 kbps, 868 MHz)
Output Power vs. Frequency
Output Power [dBm]
50 kbps, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
902
904
906
908
910
912
914
916
918
920
Frequency [MHz]
922
924
926
928
D053
Figure 5-37. Output Power vs.
Frequency (50 kbps, 915 MHz)
54
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Output Power vs. Frequency
Output Power [dBm]
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
2.472
Frequency [GHz]
2.48
D058
Figure 5-38. Output Power vs.
Frequency (BLE 1 Mbps, 2.44 GHz)
Output Power vs. Frequency
Output Power [dBm]
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
Frequency [GHz]
2.472
2.48
D059
Figure 5-39. Output Power vs.
Frequency (BLE 1 Mbps, 2.44 GHz, +5 dBm)
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5.19.6 ADC Performance
ENOB vs. Input Frequency
11.4
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
11.1
ENOB [Bit]
10.8
10.5
10.2
9.9
9.6
0.2
0.3
0.5 0.7
1
2
3
4 5 6 7 8 10
20
30 40 50
Frequency [kHz]
70 100
D061
Figure 5-40. ENOB vs.
Input Frequency
ENOB vs. Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference,
Fin = Fs / 10
10.2
10.15
ENOB [Bit]
10.1
10.05
10
9.95
9.9
9.85
9.8
1
2
3
4 5 6 7 8 10
20
30 40 50
Frequency [kHz]
70
100
200
D062
Figure 5-41. ENOB vs.
Sampling Frequency
56
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INL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
1.5
1
INL [LSB]
0.5
0
-0.5
-1
-1.5
0
400
800
1200
1600
2000
2400
2800
3200
3600
ADC Code
4000
D064
Figure 5-42. INL vs.
ADC Code
DNL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
2.5
2
DNL [LSB]
1.5
1
0.5
0
-0.5
0
400
800
1200
1600
2000
2400
2800
ADC Code
3200
3600
4000
D065
Figure 5-43. DNL vs.
ADC Code
Specifications
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ADC Accuracy vs. Temperature
Vin = 1 V, Internal reference,
200 kSamples/s
1.01
1.009
1.008
Voltage [V]
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
100
D066
Figure 5-44. ADC Accuracy vs.
Temperature
ADC Accuracy vs. VDDS
Vin = 1 V, Internal reference,
200 kSamples/s
1.01
1.009
1.008
Voltage [V]
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.8
2
2.2
2.4
2.6
2.8
3
3.2
Voltage [V]
3.4
3.6
3.8
D067
Figure 5-45. ADC Accuracy vs.
Supply Voltage (VDDS)
58
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6 Detailed Description
6.1
Overview
Section 1.4 shows the core modules of the CC1352R device.
6.2
System CPU
The CC1352R SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system
requirements of minimal memory implementation, and low-power consumption, while delivering
outstanding computational performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
Arm core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Memory Protection Unit (MPU) for safety-critical applications
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption
and wait states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
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Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0
processor that interfaces the analog RF and base-band circuitry, handles data to and from the system
CPU side, and assembles the information bits in a given packet structure. The RF core offers a high level,
command-based API to the main CPU that configurations and data are passed through. The Arm CortexM0 processor is not programmable by customers and is interfaced through the TI-provided RF driver that
is included with the SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the
main CPU, which reduces power and leaves more resources for the user application. Several signals are
also available to control external circuitry such as RF switches or range extenders autonomously.
Dual-band and multiprotocol solutions are enabled through time-sliced access of the radio, handled
transparently for the application through the TI-provided RF driver and dual-mode manager.
The various physical layer radio formats are partly built as a software defined radio where the radio
behavior is either defined by radio ROM contents or by non-ROM radio formats delivered in form of
firmware patches with the SimpleLink SDKs. This allows the radio platform to be updated for support of
future versions of standards even with over-the-air (OTA) updates while still using the same silicon.
NOTE
Not all combinations of features, frequencies, data rates, and modulation formats described
in this chapter are supported. Over time, TI can enable new physical radio formats (PHYs)
for the device and provides performance numbers for selected PHYs in the data sheet.
Supported radio formats for a specific device, including optimized settings to use with the TI
RF driver, are included in the SmartRF Studio tool with performance numbers of selected
formats found in Section 5.
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Proprietary Radio Formats
The CC1352R radio can support a wide range of physical radio formats through a set of hardware
peripherals combined with firmware available in the device ROM, covering various customer needs for
optimizing towards parameters such as speed or sensitivity. This allows great flexibility in tuning the radio
both to work with legacy protocols as well as customizing the behavior for specific application needs.
Table 6-1 gives a simplified overview of features of the various radio formats available in ROM. Other
radio formats may be available in the form of radio firmware patches or programs through the Software
Development Kit (SDK) and may combine features in a different manner, as well as add other features.
Table 6-1. Feature Support
Feature
Main 2-(G)FSK Mode
High Data Rates
Low Data Rates
SimpleLink™ Long Range
Programmable preamble,
sync word and CRC
Yes
Yes
Yes
No
Programmable receive
bandwidth
Yes
Yes
Yes (down to 4 kHz)
Yes
20 to 1000 kbps
≤ 2 Msps
≤ 100 ksps
≤ 20 ksps
2-(G)FSK
2-(G)FSK
4-(G)FSK
2-(G)FSK
4-(G)FSK
2-(G)FSK
Yes
Yes
No
No
Yes
No
No
No
Preamble Detection (3)
Yes
Yes
Yes
No
Data Whitening
Yes
Yes
Yes
Yes
Digital RSSI
Yes
Yes
Yes
Yes
CRC filtering
Yes
Yes
Yes
Yes
Direct-sequence spread
spectrum (DSSS)
No
No
No
1:2
1:4
1:8
Forward error correction
(FEC)
No
No
No
Yes
Link Quality Indicator (LQI)
Yes
Yes
Yes
Yes
Data / Symbol rate (1)
Modulation format
Dual Sync Word
Carrier Sense
(1)
(2)
(3)
(2) (3)
Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a
smaller range might be supported.
Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance
with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API.
Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power.
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6.3.2
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Bluetooth 5 low energy
The RF Core offers full support for Bluetooth 5 low energy, including the high-sped 2-Mbps physical layer
and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5 stack
or through a high-level Bluetooth API. The Bluetooth 5 PHY and part of the controller are in radio and
system ROM, providing significant savings in memory usage and more space available for applications.
The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five
times the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this
mode offers significant improvements for energy efficiency and wireless coexistence with reduced radio
communication time.
Bluetooth 5 also enables unparalleled flexibility for adjustment of speed and range based on application
needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now
possible at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging
that were not previously an option using Bluetooth low energy. With high-speed mode, existing
applications deliver faster responses, richer engagement, and longer battery life. Bluetooth 5 enables fast,
reliable firmware updates.
6.3.3
802.15.4 (Thread, Zigbee, 6LoWPAN)
Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical
layer (2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread, Zigbee, and 6LoWPAN
protocols. The 802.15.4 PHY and MAC are in radio and system ROM. TI also provides royalty-free
protocol stacks for Thread and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end
solution.
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Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is insystem programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This
configuration is done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for
both storage of data and execution of code. Retention of SRAM contents in Standby power mode is
enabled by default and included in Standby mode power consumption numbers. Parity checking for
detection of bit errors in memory is built-in, which reduces chip-level soft errors and thereby increases
reliability. System SRAM is always initialized to zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4way nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the
system CPU. The cache can be used as a general-purpose RAM by enabling this feature in the Customer
Configuration Area (CCFG).
There is a 4-KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is
typically used for storing Sensor Controller programs, data and configuration parameters. This RAM is
also accessible by the system CPU. The Sensor Controller RAM is not cleared to zeroes between system
resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio
stacks, which frees up flash memory for the application. The ROM also contains a serial (SPI and UART)
bootloader that can be used for initial programming of the device.
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6.5
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Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power
modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a
proprietary power-optimized CPU. This CPU can read and monitor sensors or perform other tasks
autonomously; thereby significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has syntax
similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential
algorithms rather than static configuration of complex peripheral modules, timers, DMA, register
programmable state machines, or event routing.
The main advantages are:
• Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power
• 2 MHz low-power mode enables lowest possible handling of digital sensors
• Dynamic reuse of hardware resources
• 40-bit accumulator supporting multiplication, addition and shift
• Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool
produces C driver source code, which the System CPU application uses to control and exchange data
with the Sensor Controller. Typical use cases may be (but are not limited to) the following:
• Read analog sensors using integrated ADC or comparators
• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)
• Capacitive sensing
• Waveform generation
• Very low-power pulse counting (flow metering)
• Key scan
The peripherals in the Sensor Controller include the following:
• The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the
comparator. The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a timeto-digital converter, and a comparator. The continuous time comparator in this block can also be used
as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller takes
care of baseline tracking, hysteresis, filtering, and other related functions when these modules are
used for capacitive sensing.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC
can be triggered by many different sources including timers, I/O pins, software, and comparators.
• The analog modules can connect to up to eight different GPIOs
• Dedicated SPI master with up to 6 MHz clock speed
The peripherals in the Sensor Controller can also be controlled from the main application processor.
64
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Cryptography
The CC1352R device comes with a wide set of modern cryptography-related hardware accelerators,
drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit
of being lower power and improves availability and responsiveness of the system because the
cryptography operations runs in a background hardware thread.
Together with a large selection of open-source cryptography libraries provided with the Software
Development Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of
the platform. The hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for
the purpose of generating keys, initialization vectors (IVs), and other random number requirements.
The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinearcombinatorial circuit.
• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512
• Advanced Encryption Standard (AES) with 128 and 256 bit key lengths
• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic
curves up to 512 bits and RSA key pair generation up to 1024 bits.
Through use of these modules and the TI provided cryptography drivers, the following capabilities are
available for an application or stack:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P224, NIST-P256, NIST-P384, NIST-P521
• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
• secp256r1
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• SHA2 based MACs
– HMAC with SHA224, SHA256, SHA384, or SHA512
• Block cipher mode of operation
– AESCCM
– AESGCM
– AESECB
– AESCBC
– AESCBC-MAC
• True random number generation
Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such
as Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not
part of the TI SimpleLink SDK for the CC1352R device.
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Timers
A large selection of timers are available as part of the CC1352R device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to
compensate for frequency drift when using the LF RCOSC as the low frequency system clock. If an
external LF clock with frequency different from 32.768 kHz is used, the RTC tick speed can be
adjusted to compensate for this. When using TI-RTOS, the RTC is used as the base timer in the
operating system and should thus only be accessed through the kernel APIs such as the Clock
module. The real time clock can also be read by the Sensor Controller Engine to timestamp sensor
data and also has dedicated capture channels. By default, the RTC halts when a debugger halts the
device.
• General Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on
up to 48 MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or
periodic counting, pulse width modulation (PWM), time counting between edges and edge counting.
The inputs and outputs of the timer are connected to the device event fabric, which allows the timers to
interact with signals such as GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available
in Active and Idle power modes.
• Sensor Controller Timers
The Sensor Controller contains 3 timers:
AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on
each edge of a selected tick source. Both one-shot and periodical timer modes are available.
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor
Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot
or periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the
ADC, as well as for PWM output or waveform generation.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as
the network time. The radio timer is synchronized with the RTC by using a dedicated radio API when
the device radio is turned on or off. This ensures that for a network stack, the radio timer seems to
always be running when the radio is enabled. The radio timer is in most cases used indirectly through
the trigger time fields in the radio APIs and should only be used when running the accurate 48 MHz
high frequency crystal is the source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors.
It is typically used to generate an interrupt to and reset of the device for the case where periodic
monitoring of the system components and tasks fails to verify proper functionality. The watchdog timer
runs on a 1.5 MHz clock rate and cannot be stopped once enabled. The watchdog timer pauses to run
in Standby power mode and when a debugger halts the device.
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Serial Peripherals and I/O
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's
synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI
modules support configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible
baud-rate generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density
modulation microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C
interface can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of
peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up
capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative
or positive edge (configurable). When configured as an output, pins can function as either push-pull or
open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 4. All digital
peripherals can be connected to any digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLink™ Wireless MCU Technical Reference
Manual.
6.9
Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC1352R device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window
comparators to interrupt the system CPU when temperature or supply voltage go outside defined
windows. These events can also be used to wake up the device from Standby mode through the AlwaysOn (AON) event fabric.
6.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to
offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and
the available bus bandwidth. The µDMA controller can perform a transfer between memory and
peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be
programmed to automatically perform transfers between peripherals and memory when the peripheral is
ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
6.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
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6.12 Power Management
To minimize power consumption, the CC1352R supports a number of power modes and power
management features (see Table 6-2).
Table 6-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
ACTIVE
IDLE
STANDBY
SHUTDOWN
RESET PIN
HELD
CPU
Active
Off
Off
Off
Off
Flash
On
Available
Off
Off
Off
SRAM
On
On
Retention
Off
Off
Supply System
On
On
Duty Cycled
Off
Off
Register and CPU retention
Full
Full
Partial
No
No
SRAM retention
Full
Full
Full
No
No
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
2 MHz medium-speed clock
(SCLK_MF)
RCOSC_MF
RCOSC_MF
Available
Off
Off
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Off
Off
Peripherals
Available
Available
Off
Off
Off
Sensor Controller
Available
Available
Available
Off
Off
Wake-up on RTC
Available
Available
Available
Off
Off
Wake-up on pin edge
Available
Available
Available
Available
Off
Wake-up on reset pin
On
On
On
On
On
Brownout detector (BOD)
On
On
Duty Cycled
Off
Off
MODE
Power-on reset (POR)
On
On
On
Off
Off
Watchdog timer (WDT)
Available
Available
Paused
Off
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
any available clock source (see Table 6-2).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or
Sensor Controller event is required to bring the device back to active mode. MCU peripherals with
retention do not need to be reconfigured when waking up again, and the CPU continues execution from
where it went into standby mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller),
and the I/Os are latched with the value they had before entering shutdown mode. A change of state on
any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger.
The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset by reading
the reset status register. The only state retained in this mode is the latched I/O state and the flash memory
contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independently of the system CPU. This means that the system CPU does not have to wake up,
for example to perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and
wake-up time that would otherwise be wasted. The Sensor Controller Studio tool enables the user to
program the Sensor Controller, control its peripherals, and wake up the system CPU as needed. All
Sensor Controller peripherals can also be controlled by the system CPU.
NOTE
The power, RF and clock management for the CC1352R device require specific configuration
and handling by software for optimized performance. This configuration and handling is
implemented in the TI-provided drivers that are part of the CC1352R software development
kit (SDK). Therefore, TI highly recommends using this software framework for all application
development on the device. The complete SDK with TI-RTOS (optional), device drivers, and
examples are offered free of charge in source code.
6.13 Clock Systems
The CC1352R device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by
the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio
operation requires an external 48 MHz crystal.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for
internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC
Oscillator (RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller
for ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or
after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF),
a 32.768 kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to
other devices, thereby reducing the overall system cost.
6.14 Network Processor
Depending on the product configuration, the CC1352R device can function as a wireless network
processor (WNP - a device running the wireless protocol stack with the application running on a separate
host MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the system
CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second
case, the application must be written according to the application framework supplied with the wireless
protocol stack.
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7 Application, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
7.1
Reference Designs
The following reference designs should be followed closely when implementing designs using the
CC1352R device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator
components, as well as ground connections for all of these.
CC1352REM-XD7793-XD24 Design Files SPACER
The CC1352REM-XD7793-XD24 reference design provides schematic, layout and
production files for the characterization board used for deriving the performance number
found in this document.
LAUNCHXL-CC1352R1 Design Files SPACER
The CC1352R LaunchPad Design Files contain detailed schematics and layouts to build
application specific boards using the CC1352R device.
Sub-1 GHz and 2.4 GHz Antenna Kit for LaunchPad™ Development Kit and SensorTag SPACER
The antenna kit allows real-life testing to identify the optimal antenna for your application.
The antenna kit includes 16 antennas for frequencies from 169 MHz to 2.4 GHz, including:
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU LaunchPad
Development Kits and SensorTags.
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Junction Temperature Calculation
This section shows the different techniques for calculating the junction temperature under various
operating conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured
temperatures:
1. From package temperature:
(1)
2. From board temperature:
(2)
3. From ambient temperature:
(3)
P is the power dissipated from the device and can be calculated by multiplying current consumption with
supply voltage. Thermal resistance coefficients are found in Section 5.8.
Example:
Using Equation 3, the temperature difference between ambient temperature and junction temperature is
calculated. In this example, we assume a simple use case where the radio is transmitting continuously at
10 dBm output power. Let us assume the ambient temperature is 85 °C and the supply voltage is 3.6 V.
To calculate P, we need to look up the current consumption for Tx at 85 °C in Figure 5-13. From the plot,
we see that the current consumption is 14.4 mA. This means that P is 14.4 mA × 3.6 V = 51.8 mW.
The junction temperature is then calculated as:
(4)
As can be seen from the example, the junction temperature is 1.2 °C higher than the ambient temperature
when running continuous Tx at 85 °C and, thus, well within the recommended operating conditions.
For various application use cases current consumption for other modules may have to be added to
calculate the appropriate power dissipation. For example, the MCU may be running simultaneously as the
radio, peripheral modules may be enabled, etc. Typically, the easiest way to find the peak current
consumption, and thus the peak power dissipation in the device, is to measure as described in Measuring
CC13xx and CC26xx current consumption.
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8 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed as follows.
8.1
Tools and Software
The CC1352R device is supported by a variety of software and hardware development tools.
Development Kit
CC1352R LaunchPad™ Development Kit SPACER
The CC1352R LaunchPad™ Development Kit enables development of high-performance
wireless applications in the 863 - 930 MHz and 2.4 GHz frequency bands that benefit from
low-power operation. The kit features the CC1352R dual-band and multiprotocol SimpleLink
Wireless MCU. The kit works with the LaunchPad ecosystem, easily enabling additional
functionality like sensors, display, and more. The built-in EnergyTrace™ software is an
energy-based code analysis tool that measures and displays the application’s energy profile
and helps to optimize it for ultra-low-power consumption.
Software
SimpleLink™ CC13X2-CC26X2 SDK SPACER
The SimpleLink CC13X2-CC26X2 Software Development Kit (SDK) provides a complete
package for the development of wireless applications on the CC13X2 / CC26X2 family of
devices. The SDK includes a comprehensive software package for the CC1352R device,
including the following protocol stacks:
• Bluetooth Low Energy 4 and 5
• Thread (based on OpenThread)
• Zigbee 3.0
• TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and 2.4
GHz
• EasyLink - a large set of building blocks for building proprietary RF software stacks
• Multiprotocol support - concurrent operation between stacks using the Dynamic
Multiprotocol Manager (DMM)
The SimpleLink CC13X2-CC26X2 SDK is part of TI’s SimpleLink MCU platform, offering a
single development environment that delivers flexible hardware, software and tool options for
customers developing wired and wireless applications. For more information about the
SimpleLink MCU Platform, visit http://www.ti.com/simplelink.
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Development Tools
Code Composer Studio™ Integrated Development Environment (IDE) SPACER
Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse® software framework with advanced embedded debug capabilities from TI resulting
in a compelling feature-rich development environment for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling). A real-time object viewer plugin is available for
TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer Studio™ Cloud IDE SPACER
Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and
build CCS and Energia™ projects. After you have successfully built your project, you can
download and run on your connected LaunchPad. Basic debugging, including features like
setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded Workbench® for Arm® SPACER
IAR Embedded Workbench® is a set of development tools for building and debugging
embedded system applications using assembler, C and C++. It provides a completely
integrated development environment that includes a project manager, editor, and build tools.
IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™ and Segger J-Link™. A real-time object viewer plugin is
available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on
most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 KB size-limited version is available through iar.com.
SmartRF™ Studio SPACER
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of
RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing and
debugging of the RF system. SmartRF Studio can be used either as a standalone application
or together with applicable evaluation boards or debug probes for the RF device. Features of
the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
Sensor Controller Studio SPACER
Sensor Controller Studio is used to write, test and debug code for the Sensor Controller
peripheral. The tool generates a Sensor Controller Interface driver, which is a set of C
source files that are compiled into the System CPU application. These source files also
contain the Sensor Controller binary image and allow the System CPU application to control
and exchange data with the Sensor Controller. Features of the Sensor Controller Studio
include:
• Ready-to-use examples for several common use cases
• Full toolchain with built-in compiler and assembler for programming in a C-like
programming language
• Provides rapid development by using the integrated sensor controller task testing and
debugging functionality, including visualization of sensor data and verification of
algorithms
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CCS UniFlash SPACER
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.
UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free of
charge.
8.1.1
SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of
wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment.
Delivering flexible hardware, software and tool options for your IoT applications. Invest once in the
SimpleLink software development kit and use throughout your entire portfolio. Learn more on
ti.com/simplelink.
8.2
Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar,
navigate to the device product folder on ti.com/product/CC1352R. In the upper right corner, click on Alert
me to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is
listed as follows.
TI Resource Explorer
TI Resource Explorer SPACER
Software examples, libraries, executables, and documentation are available for your device
and development board.
Errata
CC1352R Silicon Errata SPACER
The silicon errata describes the known exceptions to the functional specifications for each
silicon revision of the device and description on how to recognize a device revision.
Application Reports
All application reports for the CC1352R device are found on the device product folder at:
ti.com/product/CC1352R/technicaldocuments.
Technical Reference Manual (TRM)
CC13x2, CC26x2 SimpleLink™ Wireless MCU TRM SPACER
The TRM provides a detailed description of all modules and peripherals available in the
device family.
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Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4
Trademarks
SimpleLink, SmartRF, LaunchPad, EnergyTrace, Code Composer Studio, E2E are trademarks of Texas
Instruments.
Arm, Cortex, Arm Thumb are registered trademarks of Arm Limited (or its subsidiaries).
Bluetooth is a registered trademark of Bluetooth SIG Inc.
Eclipse is a registered trademark of Eclipse Foundation.
CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium.
I-jet is a trademark of IAR Systems AB.
IAR Embedded Workbench is a registered trademark of IAR Systems AB.
Windows is a registered trademark of Microsoft Corporation.
J-Link is a trademark of SEGGER Microcontroller Systeme GmbH.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
Wi-SUN is a registered trademark of Wi-SUN Alliance Inc.
Zigbee is a registered trademark of Zigbee Alliance Inc.
All other trademarks are the property of their respective owners.
8.5
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018–2019, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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24-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC1352R1F3RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 105
CC1352
R1F3
CC1352R1F3RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 105
CC1352
R1F3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CC1352R1F3RGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
CC1352R1F3RGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC1352R1F3RGZR
VQFN
RGZ
48
2500
336.6
336.6
31.8
CC1352R1F3RGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
7 x 7, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
7.1
6.9
PIN 1 INDEX AREA
(0.1) TYP
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
5.15±0.1
(0.2) TYP
13
44X 0.5
24
12
25
SYMM
2X
5.5
1
PIN1 ID
(OPTIONAL)
SEE SIDE WALL
DETAIL
36
48
SYMM
37
48X 0.5
0.3
48X 0.30
0.18
0.1
0.05
C A B
C
4219044/B 08/2019
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
( 5.15)
SYMM
48X (0.6)
35
48
48X (0.24)
1
44X (0.5)
2X
(5.5)
34
SYMM
2X
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
23
12
21X (Ø0.2) VIA
TYP
13
22
2X (1.26)
2X (1.065)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
METAL UNDER
SOLDER MASK
4219044/B 08/2019
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
( 1.06)
48X (0.6)
48X (0.24)
44X (0.5)
2X
(5.5)
SYMM
2X
2X (6.8)
(0.63)
2X
(1.26)
(R0.05)
TYP
2X (0.63)
2X
(1.26)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/B 08/2019
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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