Texas Instruments | CC3135 SimpleLink™ Wi-Fi®, Dual-Band Network Processor, solution for MCU applications | Datasheet | Texas Instruments CC3135 SimpleLink™ Wi-Fi®, Dual-Band Network Processor, solution for MCU applications Datasheet

Texas Instruments CC3135 SimpleLink™ Wi-Fi®, Dual-Band Network Processor, solution for MCU applications Datasheet
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CC3135
SWAS037 – FEBRUARY 2019
CC3135 SimpleLink™ Wi-Fi®, Dual-Band Network Processor,
solution for MCU applications
1 Device Overview
1.1
Features
1
•
•
•
•
•
•
•
•
•
•
Integrated Dual-Band Wi-Fi® and internet protocols
802.11 a/b/g/n: 2.4 GHz and 5 GHz
FIPS 140-2 Level 1 Certification
Rich set of IoT security features helps developers
protect data
Low-Power Modes for battery powered application
Coexistence with 2.4 GHz Radios
Industrial temperature: –40°C to +85°C
Transferable Wi-Fi Alliance® Certification
Wi-Fi network processor subsystem:
– Wi-Fi core:
– 802.11 a/b/g/n 2.4 GHz and 5 GHz
– Modes:
– Access Point (AP)
– Station (STA)
– Wi-Fi Direct® (only supported on 2.4 GHz)
– Security:
– WEP
– WPA™/ WPA2™ PSK
– WPA2 Enterprise
– Internet and application protocols:
– HTTPs server, mDNS, DNS-SD, DHCP
– IPv4 and IPv6 TCP/IP stack
– 16 BSD sockets (fully secured TLS v1.2 and
SSL 3.0)
– Built-in power management subsystem:
– Configurable low-power profiles (always,
intermittent, tag)
– Advanced low-power modes
– Integrated DC/DC regulators
Multilayered security features:
– Separate execution environments
– Networking security
– Device identity and key
– Hardware accelerator cryptographic engines
•
•
•
•
•
•
•
(AES, DES, SHA/MD5, CRC)
– Application-level security (encryption,
authentication, access control)
– Initial secure programming
– Software tamper detection
– Secure boot
– Certificate signing request (CSR)
– Unique per device key pair
Application throughput:
– UDP: 16 Mbps, TCP: 13 Mbps
– Peak: 72 Mbps
Power-Management Subsystem:
– Integrated DC/DC converters support a wide
range of supply voltage:
– VBAT wide-voltage mode: 2.1 V to 3.6 V
– VIO is always tied with VBAT
– Advanced low-power modes:
– Shutdown: 1 µA, hibernate: 4 µA
– Low-power deep sleep (LPDS): 120 µA
– Idle connected (MCU in LPDS): 710 µA
– RX traffic (MCU active): 53 mA
– TX traffic (MCU active): 223 mA
Wi-Fi TX power:
– 2.4 GHz: 18.0 dBm at 1 DSSS
– 5 GHz: 18.1 dBm at 6 OFDM
Wi-Fi RX sensitivity:
– 2.4 GHz: –96 dBm at 1 DSSS
– 5 GHz: –92 dBm at 6 OFDM
Clock source:
– 40.0-MHz crystal with internal oscillator
– 32.768-kHz crystal or external RTC
RGK package
– 64-Pin, 9-mm × 9-mm very thin quad flat
nonleaded (VQFN) package, 0.5-mm pitch
Device supports SimpleLink™ MCU Platform
Developer's Ecosystem
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3135
SWAS037 – FEBRUARY 2019
1.2
•
www.ti.com
Applications
For Internet of Things applications, such as:
– Building and Home Automation:
• HVAC Systems & Thermostat
• Video Surveillance, Video Doorbells, and
Low-Power Camera
• Building Security Systems & E-locks
1.3
–
–
–
–
–
Appliances
Asset Tracking
Factory Automation
Medical and Healthcare
Grid Infrastructure
Description
Connect any microcontroller (MCU) to the Internet of Things (IoT) with the CC3135 device, a dual-band
wireless network processor from Texas Instruments™. The CC3135 Wi-Fi® Internet-on-a chip™ device
contains an Arm® Cortex®-M3 MCU dedicated to Wi-Fi® and internet protocols, in order to offload
networking activities from the host MCU. The subsystem includes a dual-band 802.11a/b/g/n radio,
baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit
encryption and a built in power management for best in class low power performance.
The Wi-Fi CERTIFIED® CC3135 device dramatically simplifies the implementation of low-power, with the
integrated Wi-Fi Alliance® IoT low power feature.
This generation introduces new capabilities that further simplify the connectivity of things to the Internet.
The main new features include:
• 802.11a (5 GHz) support
• BLE/2.4 GHz radio coexistence
• Antenna selection
• Enhanced security with FIPS 140-2 Level 1 certification and more. For exact status of FIPS
certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.
• Up to 16 concurrent secure sockets
• Certificate sign request (CSR)
• Online certificate status protocol (OCSP)
• Wi-Fi Alliance® certified for IoT applications with low-power capabilities and more
• Hostless mode for offloading template packet transmissions
• Improved fast scan
The CC3135 device is delivered with a slim and user-friendly host driver to simplify the integration and
development of networking applications. The host driver can easily be ported to most platforms and
operating systems (OS). The driver has a small memory footprint and can run on 8-bit, 16-bit, or 32-bit
microcontrollers with any clock speed (no performance or real-time dependency).
The CC3135 device is part of the SimpleLink™ MCU platform, a common, easy-to-use development
environment based on a single core software development kit (SDK), rich tool set, reference designs and
E2E™ community which supports Wi-Fi®, Bluetooth® low energy, Sub-1 GHz and host MCUs. For more
information, visit www.ti.com/simplelink.
Device Information (1)
PART NUMBER
CC3135RNMRGKR
(1)
2
PACKAGE
BODY SIZE
VQFN (64)
9.00 mm × 9.00 mm (nom)
For more information, see the Mechanical, Packaging, and Orderable Information section.
Device Overview
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Functional Block Diagram
Figure 1-1 shows the CC3135 device functional block diagram.
32.768 kHz
XTAL
VCC
(2.1 to 3.6V)
SPI
Flash
40 MHz
XTAL
Dual band Ant.
SSPI
A_TX
Wi-Fi
RF Switch
A_RX
5 GHz
BPF
SOP0
SOP1
Diplexer /
SPDT RF
Switch
32 kHz
RF_BG
MCU
nHIB
CC3135
BLE
DEVICE
HOST_INTR
Wi-Fi / BLE
RF Switch
2.4 GHz BPF
SPI/UART
HM_IOs
Dual band Ant.
COEX_IO
Output GPIOs
Note: The diplexer is used for the signal antenna solution. When using the antenna selection feature (dual antenna),
an SPDT switch and 2 GPIO lines are required after the diplexer.
Figure 1-1. Functional Block Diagram
Device Overview
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Figure 1-2 shows the CC3135 hardware overview.
External MCU
SimpleLink Driver APIs
SPI or UART Driver
SPI /
UART
Wi-Fi Network Processor
Host Interface
1 x SPI
1 x UART
Network Processor
POWER
Management
Wi-Fi Driver
TCP/IP Stack
Application
Protocols
Oscillators
(ARM CortexTM)
ROM
DC2DC
Baseband
MAC
Processor
Dual Band
Radio
Synthesizer
Crypto Engines
RAM
RTC
Figure 1-2. CC3135 Hardware Overview
4
Device Overview
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Figure 1-3 shows an overview of the CC3135 embedded software.
Customer Application
in external MCU
NetApp
BSD Socket
Wi-Fi
SimpleLink Driver APIs
Host Interface
Network
Apps
WLAN
Security &
Management
TCP/IP Stack
WLAN MAC & PHY
Figure 1-3. CC3135 Software Overview
Device Overview
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Table of Contents
1
Device Overview ......................................... 1
5.16
Thermal Resistance Characteristics for RGK
Package ............................................. 28
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
5.17
Timing and Switching Characteristics ............... 29
Description ............................................ 2
5.18
External Interfaces
1.3
Functional Block Diagram ............................ 3
1.4
6
..................................
39
Detailed Description ................................... 43
............................................
Revision History ......................................... 6
Device Comparison ..................................... 7
6.1
Overview
6.2
Device Features ..................................... 43
Related Products ..................................... 8
6.3
FIPS 140-2 Level 1 Certification .................... 48
4
Terminal Configuration and Functions .............. 9
6.4
Power-Management Subsystem .................... 48
6.5
Low-Power Operating Modes ....................... 49
6.6
Memory .............................................. 50
6.7
Restoring Factory Default Configuration ............ 51
6.8
Hostless Mode
5
.......................................... 9
4.2
Pin Attributes ........................................ 10
4.3
Signal Descriptions .................................. 14
4.4
Connections for Unused Pins ....................... 16
Specifications ........................................... 17
5.1
Absolute Maximum Ratings ......................... 17
5.2
ESD Ratings ........................................ 17
5.3
Power-On Hours (POH) ............................. 17
5.4
Recommended Operating Conditions ............... 17
2
3
3.1
4.1
Pin Diagram
7
8
......................................
43
52
Applications, Implementation, and Layout........ 53
7.1
Application Information .............................. 53
7.2
PCB Layout Guidelines
.............................
63
Device and Documentation Support ............... 67
....................
8.1
Third-Party Products Disclaimer
Tools and Software ................................ 67
67
Firmware Updates................................... 68
5.5
Current Consumption Summary: 2.4 GHz RF Band 18
8.2
5.6
Current Consumption Summary: 5 GHz RF Band .. 18
8.3
TX Power Control for 2.4 GHz Band ................ 19
8.4
Device Nomenclature ............................... 68
5.8
TX Power Control for 5 GHz ........................ 21
8.5
Documentation Support ........................... 69
5.9
.................
Electrical Characteristics for DIO Pins ..............
22
8.6
Community Resources .............................. 70
23
8.7
Trademarks.......................................... 70
Electrical Characteristics for Pin Internal Pullup and
Pulldown ............................................. 24
8.8
Electrostatic Discharge Caution ..................... 71
8.9
Export Control Notice
....................
WLAN Transmitter Characteristics ..................
WLAN Transmitter Out-of-Band Emissions .........
8.10
Glossary ............................................. 71
5.7
Brownout and Blackout Conditions
5.10
5.11
5.12
5.13
5.14
5.15
WLAN Receiver Characteristics
25
26
27
BLE/2.4 GHz Radio Coexistence and WLAN
Coexistence Requirements ......................... 28
9
...............................
71
Mechanical, Packaging, and Orderable
Information .............................................. 72
..............................
9.1
Packaging Information
9.1
Package Option Addendum ......................... 73
72
2 Revision History
6
DATE
REVISION
NOTES
February 2019
*
Initial Release
Revision History
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3 Device Comparison
Table 3-1 lists the features supported across different CC3x35 devices.
Table 3-1. Comparison of Device Features
DEVICE
FEATURE
CC3135
CC3235S
CC3235SF
Classification
Network processor
Wireless microcontroller
Wireless microcontroller
Standard
802.11a/b/g/n
802.11a/b/g/n
802.11a/b/g/n
TCP/IP stack
IPv4, IPv6
IPv4, IPv6
IPv4, IPv6
Sockets
16
16
16
Package
9-mm × 9-mm VQFN
9-mm × 9-mm VQFN
9-mm × 9-mm VQFN
ON-CHIP APPLICATION MEMORY
Flash
—
—
1MB
RAM
—
256KB
256KB
Frequency
2.4 GHz, 5 GHz
2.4 GHz, 5 GHz
2.4 GHz, 5 GHz
Coexistence with BLE Radio
Yes
Yes
Yes
RF FEATURES
SECURITY FEATURES
Additional networking security
Unique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol
(OCSP)
Certificate signing request (CSR)
Unique per-device key pair
Unique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol
(OCSP)
Certificate signing request (CSR)
Unique per-device key pair
Unique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol
(OCSP)
Certificate signing request (CSR)
Unique per-device key pair
Hardware acceleration
Hardware crypto engines
Hardware crypto engines
Hardware crypto engines
Secure boot
—
Yes
Yes
Enhanced application level security
—
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
FIPS 140-2 Level 1 Certification (1)
Yes
Yes
Yes
(1)
For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.
Device Comparison
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Related Products
For information about other devices in this family of products or related products see the links below.
The SimpleLink™ MCU Portfolio This portfolio offers a single development environment that delivers
flexible hardware, software, and tool options for customers developing wired and wireless
applications. With 100 percent code reuse across host MCUs, Wi-Fi®, Bluetooth® low
energy, Sub-1 GHz devices and more, choose the MCU or connectivity standard that fits
your design. A one-time investment with the SimpleLink™ software development kit (SDK)
allows you to reuse often, opening the door to create unlimited applications.
SimpleLink™ Wi-Fi® Family This device platform offers several Internet-on-a chip™ solutions, which
address the need of battery-operated, security-enabled products. Texas Instruments offers a
single-chip wireless microcontroller and a wireless network processor that can be paired with
any MCU, allowing developers to design new Wi-Fi® products or upgrade existing products
with Wi-Fi® capabilities.
MSP432™ Host MCU features the Arm® Cortex®-M4 processor offering ample processing capability with
floating point unit and memory footprint for advanced processing algorithm, communication
protocols as well as application needs, while incorporating a 14-bit 1-msps ADC14 that
provides a flexible and low-power analog with best-in-class performance to enable
developers to add differentiated sensing and measurement capabilities to their Wi-Fi
applications. For more information, visit www.ti.com/product/MSP432P401R.
Reference Designs for CC3135 Device TI Designs Reference Design Library is a robust reference
design library spanning analog, embedded processor and connectivity. Created by TI experts
to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
The SimpleLink™ Wi-Fi® SDK Plug-in The SDK contains drivers, sample applications for Wi-Fi features
and Internet, and documentation required to use the CC3135 solution.
8
Device Comparison
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4 Terminal Configuration and Functions
4.1
Pin Diagram
VDD_ANA1
VDD_ANA2
DCDC_ANA2_SW_N
DIO31
VIN_DCDC_DIG
DCDC_DIG_SW
DCDC_PA_OUT
DCDC_PA_SW_N
DCDC_PA_SW_P
VIN_DCDC_PA
DCDC_ANA_SW
VIN_DCDC_ANA
LDO_IN1
SOP0
SOP1
VDD_PA_IN
Figure 4-1 shows pin assignments for the 64-pin VQFN package.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DIO30
53
28
A_TX
VIN_IO2
54
27
A_RX
UART1_TX
55
26
NC
VDD_DIG2
56
25
LDO_IN2
UART1_RX
57
24
VDD_PLL
TEST_58
58
23
WLAN_XTAL_P
TEST_59
59
22
WLAN_XTAL_N
TEST_60
60
21
SOP2/TCXO_EN
UART1_nCTS
61
20
DIO29
TEST_62
62
19
RESERVED
DIO8
63
18
DIO28
DIO9
64
17
DIO24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIO23
GND
HOSTINTR
29
FLASH_SPI_CS
52
FLASH_SPI_MISO
RTC_XTAL_N
FLASH_SPI_MOSI
GND
FLASH_SPI_CLK
30
VIN_IO1
51
VDD_DIG1
RTC_XTAL_P
HOST_SPI_nCS
RF_BG
HOST_SPI_MISO
31
HOST_SPI_MOSI
50
HOST_SPI_CLK
UART1_nRTS
DIO13
nRESET
DIO12
32
nHIB
49
DIO10
VDD_RAM
Figure 4-1. Top View Pin Assignment for 64-Pin VQFN
Terminal Configuration and Functions
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Pin Attributes
Table 4-1 describes the CC3135 pins.
NOTE
Digital IOs on the CC3135 device refer to hostless mode, BLE/2.4 GHz coexistence, and
antenna select IOs, not general-purpose IOs.
If an external device drives a positive voltage to signal pads when the CC3135 device is not
powered, DC current is drawn from the other device. If the drive strength of the external
device is adequate, an unintentional wakeup and boot of the CC3135 device can occur. To
prevent current draw, TI recommends one of the following:
• All devices interfaced to the CC3135 device must be powered from the same power rail
as the CC3135 device.
• Use level shifters between the CC3135 device and any external devices fed from other
independent rails.
• The nRESET pin of the CC3135 device must be held low until the VBAT supply to the
device is driven and stable.
10
Terminal Configuration and Functions
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Table 4-1. Pin Description and Attributes
DIGITAL I/O
PIN
1
DEFAULT FUNCTION
DIO10
PAD_
CONFIG
HOSTLESS
MODE
10
Y
BLE COEX
CC_COEX_
OUT
CC_COEX_
IN
Y
Y
STATE AT
RESET AND
HIBERNATE
I/O TYPE (1)
–
I/O
DESCRIPTION
Digital input or output
2
nHIB
11
-
-
-
Hi-Z
I
Hibernate signal input to the NWP subsystem
(active low). This is connected to the MCU GPIO. If
the GPIO from the MCU can float while the MCU
enters low power, consider adding a pullup resistor
on the board to avoid floating.
3
DIO12
12
Y
Y
Y
–
O
Digital input or output
4
DIO13
13
Y
Y
Y
–
–
Digital input or output
5
HOST_SPI_CLK
14
-
-
-
Hi-Z
I
Host interface SPI clock
6
HOST_SPI_MOSI
15
-
-
-
Hi-Z
I
Host interface SPI data input
7
HOST_SPI_MISO
16
-
-
-
Hi-Z
O
Host interface SPI data output
8
HOST_SPI_nCS
17
-
-
-
Hi-Z
I
Host interface SPI chip select (active low)
9
VDD_DIG1
-
N/A
N/A
N/A
Hi-Z
Power
Digital core supply (1.2 V)
10
VIN_IO1
-
N/A
N/A
N/A
Hi-Z
Power
I/O supply
11
FLASH_SPI_CLK
-
N/A
N/A
N/A
Hi-Z
O
Serial Flash interface: SPI clock
12
FLASH_SPI_MOSI
-
N/A
N/A
N/A
Hi-Z
O
Serial Flash interface: SPI data out
13
FLASH _SPI_MISO
-
N/A
N/A
N/A
Hi-Z
I
Serial Flash interface: SPI data in (active high)
14
FLASH _SPI_CS
-
N/A
N/A
N/A
Hi-Z
O
Serial Flash interface: SPI chip select (active low)
15
HOST_INTR
22
-
-
-
Hi-Z
O
Interrupt output (active high)
16
DIO23
23
Y
Y
Y
Hi-Z
17
DIO24
24
Y
Y
Y
Hi-Z
18
DIO28
40
Y
Y
Y
–
–
Digital input or output
19
Reserved
28
-
-
-
Hi-Z
–
Connect a 100-kΩ pulldown resistor to ground.
20
DIO29
29
Y
Y
Y
Hi-Z
21
SOP2/TCXO_EN (2)
25
Y (3)
Y
-
Hi-Z
O
22
WLAN_XTAL_N
-
N/A
N/A
N/A
Hi-Z
Analog
(1)
(2)
(3)
Digital input or output
Digital input or output
Digital input or output
Controls restore to default mode. Enable signal for
external TCXO. Add a 10-kΩ pulldown resistor to
ground.
Connect the WLAN 40-MHz crystal here.
I = input
O = output
RF = radio frequency
I/O = bidirectional
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During
hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
Output Only
Terminal Configuration and Functions
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Table 4-1. Pin Description and Attributes (continued)
DIGITAL I/O
PIN
12
DEFAULT FUNCTION
PAD_
CONFIG
HOSTLESS
MODE
BLE COEX
CC_COEX_
OUT
CC_COEX_
IN
STATE AT
RESET AND
HIBERNATE
I/O TYPE (1)
DESCRIPTION
23
WLAN_XTAL_P
-
N/A
N/A
N/A
Hi-Z
Analog
Connect the WLAN 40-MHz crystal here.
24
VDD_PLL
-
N/A
N/A
N/A
Hi-Z
Power
Internal PLL power supply (1.4 V nominal)
25
LDO_IN2
-
N/A
N/A
N/A
Hi-Z
Power
Input to internal LDO
26
NC
-
N/A
N/A
N/A
–
–
27
A_RX
-
N/A
N/A
N/A
–
RF
5 GHz RF RX
28
A_TX
-
N/A
N/A
N/A
–
RF
5 GHz RF TX
29
GND
-
N/A
N/A
N/A
–
Power
GND
30
GND
-
N/A
N/A
N/A
–
Power
GND
31
RF_BG
-
N/A
N/A
N/A
Hi-Z
RF
32
nRESET
-
N/A
N/A
N/A
Hi-Z
I
33
VDD_PA_IN
-
N/A
N/A
N/A
Hi-Z
Power
34
SOP1
-
N/A
N/A
N/A
Hi-Z
–
SOP[2:0] used for factory restore. Add 100-kΩ
pulldown to ground. See Section 6.7. SOP1 used for
5 GHz switch control
35
SOP0
-
N/A
N/A
N/A
Hi-Z
–
SOP[2:0] used for factory restore. Add 100-kΩ
pulldown to ground. See Section 6.7. SOP0 used for
5GHz switch control
36
LDO_IN1
-
N/A
N/A
N/A
Hi-Z
Power
Input to internal LDO
37
VIN_DCDC_ANA
-
N/A
N/A
N/A
Hi-Z
Power
Power supply for the DC/DC converter for analog
section
38
DCDC_ANA_SW
-
N/A
N/A
N/A
Hi-Z
Power
Analog DC/DC converter switch output
39
VIN_DCDC_PA
-
N/A
N/A
N/A
Hi-Z
Power
PA DC/DC converter input supply
40
DCDC_PA_SW_P
-
N/A
N/A
N/A
Hi-Z
Power
PA DC/DC converter switch output +ve
41
DCDC_PA_SW_N
-
N/A
N/A
N/A
Hi-Z
Power
PA DC/DC converter switch output –ve
42
DCDC_PA_OUT
-
N/A
N/A
N/A
Hi-Z
Power
PA DC/DC converter output. Connect the output
capacitor for DC/DC here.
43
DCDC_DIG_SW
-
N/A
N/A
N/A
Hi-Z
Power
Digital DC/DC converter switch output
44
VIN_DCDC_DIG
-
N/A
N/A
N/A
Hi-Z
Power
Power supply input for the digital DC/DC converter
45
DIO31
31
Y
Y
Y
Hi-Z
–
46
DCDC_ANA2_SW_N
-
N/A
N/A
N/A
Hi-Z
Power
Analog2 DC/DC converter switch output –ve
47
VDD_ANA2
-
N/A
N/A
N/A
Hi-Z
Power
Analog2 power supply input
Terminal Configuration and Functions
No Connect
2.4 GHz RF TX, RX
RESET input for the device. Active low input. Use
RC circuit (100 kΩ || 0.01 µF) for power on reset
(POR).
Power supply for the RF power amplifier (PA)
Network Scripter I/O
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Table 4-1. Pin Description and Attributes (continued)
DIGITAL I/O
PIN
DEFAULT FUNCTION
PAD_
CONFIG
HOSTLESS
MODE
BLE COEX
CC_COEX_
OUT
CC_COEX_
IN
STATE AT
RESET AND
HIBERNATE
I/O TYPE (1)
DESCRIPTION
48
VDD_ANA1
-
N/A
N/A
N/A
Hi-Z
Power
Analog1 power supply input
49
VDD_RAM
-
N/A
N/A
N/A
Hi-Z
Power
Power supply for the internal RAM
50
UART1_nRTS
0
-
-
-
Hi-Z
O
51
RTC_XTAL_P
-
N/A
N/A
N/A
Hi-Z
Analog
32.768-kHz XTAL_P or external CMOS level clock
input
52
RTC_XTAL_N
32
Y
Y
Y
Hi-Z
Analog
32.768-kHz XTAL_N or 100-kΩ external pullup for
external clock
53
DIO30
30
54
VIN_IO2
55
UART1_TX
56
UART host interface (active low)
Y
Y
Y
Hi-Z
–
N/A
N/A
N/A
Hi-Z
Power
Network Scripter I/O
1
-
-
-
Hi-Z
O
VDD_DIG2
-
N/A
Hi-Z
Power
57
UART1_RX
2
-
-
-
Hi-Z
I
UART host interface; connect to test point on
prototype for Flash programming.
58
TEST_58
3
Y
Y
Y
Hi-Z
O
Test signal; connect to an external test point.
59
TEST_60
4
Y
Y
Y
Hi-Z
O
Test signal; connect to an external test point.
60
TEST_60
5
Y
Y
Y
Hi-Z
O
Test signal; connect to an external test point.
61
UART1_nCTS
6
-
-
-
Hi-Z
I
UART host interface (active low)
62
TEST_62
7
-
-
-
Hi-Z
O
Test signal; connect to an external test point.
63
DIO8
8
Y
Y
Y
Hi-Z
64
DIO9
9
Y
Y
Y
Hi-Z
–
65
GND
-
N/A
N/A
N/A
–
Power
I/O power supply. Same as battery voltage.
UART host interface. Connect to test point on
prototype for Flash programming.
Digital power supply (1.2 V)
Digital input or output
Digital input or output
Ground tab used as thermal and electrical ground
Terminal Configuration and Functions
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Signal Descriptions
Table 4-2. Signal Descriptions
FUNCTION
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
DIO10
1
I/O
O
DIO12
3
I/O
O
DIO13
4
I/O
O
DIO23
16
I/O
O
DIO24
17
I/O
O
SIGNAL NAME
DIO28
Antenna
selection
BLE/2.4 GHz
Radio
coexistence
Clock
(1)
14
18
(1)
DESCRIPTION
I/O
O
DIO29
20
I/O
O
DIO25
21
O
O
DIO31
45
(1)
I/O
O
DIO32
52 (1)
I/O
O
DIO30
53 (1)
I/O
O
DIO3
58
I/O
O
DIO4
59
I/O
O
DIO5
60
I/O
O
DIO8
63
I/O
O
DIO9
64
I/O
O
DIO10
1
I/O
I/O
DIO12
3
I/O
I/O
DIO13
4
I/O
I/O
DIO23
16
I/O
I/O
DIO24
17
I/O
I/O
DIO28
18 (1)
I/O
I/O
DIO29
20
I/O
I/O
DIO25
21
O
O
DIO31
45 (1)
I/O
I/O
DIO32
52 (1)
I/O
I/O
DIO30
53 (1)
I/O
I/O
DIO3
58
I/O
I/O
DIO4
59
I/O
I/O
DIO5
60
I/O
I/O
DIO8
63
I/O
I/O
DIO9
64
I/O
I/O
WLAN_XTAL_N
22
—
—
40-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P
23
—
—
40-MHz crystal or TCXO clock input
RTC_XTAL_P
51
—
—
Connect 32.768-kHz crystal or force external CMOS
level clock
RTC_XTAL_N
52
—
—
Connect 32.768-kHz crystal or connect 100-kΩ resistor
to supply voltage
Antenna selection control
Coexistence inputs and outputs
LPDS retention unavailable.
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
Hostless Mode
Power
HOST SPI
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
DIO10
1
I/O
I/O
DIO12
3
I/O
I/O
DIO13
4
I/O
I/O
DIO23
16
I/O
I/O
DIO24
17
I/O
I/O
DIO28
18 (1)
I/O
I/O
DIO29
20
I/O
I/O
SIGNAL NAME
DIO25
21
O
O
DIO31
45 (1)
I/O
I/O
DIO32
52 (1)
I/O
I/O
DIO30
(1)
53
DESCRIPTION
Hostless mode inputs and outputs
I/O
I/O
DIO3
58
I/O
I/O
DIO4
59
I/O
I/O
DIO5
60
I/O
I/O
DIO8
63
I/O
I/O
DIO9
64
I/O
I/O
VDD_DIG1
9
—
—
Internal digital core voltage
VIN_IO1
10
—
—
Device supply voltage (VBAT)
VDD_PLL
24
—
—
Internal analog voltage
LDO_IN2
25
—
—
Internal analog RF supply from analog DC/DC output
VDD_PA_IN
33
—
—
Internal PA supply voltage from PA DC/DC output
LDO_IN1
36
—
—
Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA
37
—
—
Analog DC/DC input (connected to device input supply
[VBAT])
DCDC_ANA_SW
38
—
—
Internal analog DC/DC switching node
VIN_DCDC_PA
39
—
—
PA DC/DC input (connected to device input supply
[VBAT])
DCDC_PA_SW_P
40
—
—
Internal PA DC/DC switching node
DCDC_PA_SW_N
41
—
—
Internal PA DC/DC switching node
DCDC_PA_OUT
42
—
—
Internal PA buck converter output
DCDC_DIG_SW
43
—
—
Internal digital DC/DC switching node
VIN_DCDC_DIG
44
—
—
Digital DC/DC input (connected to device input supply
[VBAT])
DCDC_ANA2_SW_P
45
—
—
Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N
46
—
—
Internal analog to DC/DC converter –ve switching node
VDD_ANA2
47
—
—
Internal analog to DC/DC output
VDD_ANA1
48
—
—
Internal analog supply fed by ANA2 DC/DC output
VDD_RAM
49
—
—
Internal SRAM LDO output
VIN_IO2
54
—
—
Device supply voltage (VBAT)
VDD_DIG2
56
—
—
Internal digital core voltage
HOST_SPI_CLK
5
I/O
I
Host SPI clock input
HOST_SPI_MOSI
6
I/O
I
Data from Host
HOST_SPI_MISO
8
I/O
O
Data to Host
HOST_SPI_nCS
7
I/O
I
Device select (active low)
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
FLASH_SPI_CLK
11
O
O
Clock to SPI serial flash (fixed default)
FLASH_SPI_DOUT
12
O
O
Data to SPI serial flash (fixed default)
FLASH_SPI_DIN
13
I
I
Data from SPI serial flash (fixed default)
FLASH_SPI_CS
14
O
O
Device select to SPI serial flash (fixed default)
UART1_nRTS
50
I/O
O
UART1 request-to-send (active low)
UART1_TX
55
I/O
I
UART TX data
UART1_RX
57
I/O
O
UART RX data
FUNCTION
FLASH SPI
UART
SIGNAL NAME
UART1_nCTS
Sense-OnPower
DESCRIPTION
61
I/O
I
UART1 clear-to-send (active low)
SOP2
21 (2)
O
I
Sense-on-power 2
SOP1
34
I
I
Configuration sense-on-power 1
SOP0
35
I
I
Configuration sense-on-power 0
Reset
nRESET
32
I
I
Global master device reset (active low)
nHIB
nHIB
2
I
I
Hibernate signal input to the NWP subsystem (active
low)
A_RX
27
I
I
WLAN analog A-band receive
A_TX
28
O
O
WLAN analog A-band transmit
RF_BG
31
I/O
I/O
WLAN analog RF 802.11 b/g bands
TEST_58
58
O
O
Test Signal
TEST_59
59
I
I
Test Signal
TEST_60
60
O
O
Test Signal
TEST_62
62
O
O
Test Signal
RF
Test Port
(2)
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
4.4
Connections for Unused Pins
All unused pin should be configured as stated in Table 4-3.
Table 4-3. Connections for Unused Pins
FUNCTION
SIGNAL DESCRIPTION
DIO
Digital input or output
No Connect
NC
SOP
Reset
ACCEPTABLE PRACTICE
PREFERRED PRACTICE
Wake up I/O source should not be
floating during hibernate.
All the I/O pins will float while in
Hibernate and Reset states. Ensure
pullup and pulldown resistors are
available on board to maintain the
state of the I/O.
Leave unused DIOs as NC
Unused pin, leave as NC.
Unused pin, leave as NC
Configuration sense-onpower
Ensure pulldown resistors are
available on unused SOP pins
69.8K Pull down resistor
on SOP0 and SOP1 used
as switch control pins,
100K pull down on SOP2
RESET input for the device
Never leave the reset pin floating
RTC_XTAL_N
When using an external oscillator,
add a 100-kΩ pullup resistor to VIO
WLAN_XTAL_N
When using an external oscillator,
connect to ground if unused
Clock
16
PIN
NUMBER
26
Terminal Configuration and Functions
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5 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
5.1
Absolute Maximum Ratings
All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process and
overvoltage unless otherwise indicated.
Over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage
VBAT and VIO
Pins: 37, 39, 44
VIO – VBAT (differential)
Pins: 10, 54
MIN
MAX
–0.5
3.8
UNIT
V
VBAT and VIO should be tied
together
V
Digital inputs
–0.5
VIO + 0.5
V
RF pins
–0.5
2.1
V
Analog pins, Crystal
–0.5
2.1
V
Operating temperature, TA
–40
85
°C
Storage temperature, Tstg
–55
125
°C
(1)
(2)
Pins: 22, 23, 51, 52
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
5.2
ESD Ratings
VALUE
VESD
(1)
(2)
5.3
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Power-On Hours (POH)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's
standard terms and conditions for TI semiconductor products.
POWER-ON HOURS [POH]
(hours)
OPERATING CONDITION
TA up to 85°C (1)
(1)
5.4
87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage
VBAT, VIO
(shorted to VBAT)
Pins: 10, 37, 39, 44, 54
Direct battery
connection (3)
Ambient thermal slew
(1)
(2)
(3)
(4)
MIN
TYP
MAX
2.1 (4)
3.3
3.6
V
20
°C/minute
–20
UNIT
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the transmission.
To ensure WLAN performance, ripple on the supply must be less than ±300 mV.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also
2.1 V, and care must be taken when operating at the minimum specified voltage.
Specifications
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Current Consumption Summary: 2.4 GHz RF Band
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS (1)
PARAMETER
1 DSSS
TX
6 OFDM
54 OFDM
RX (3)
(2)
MIN
TYP
TX power level = 0
272
TX power level = 4
188
TX power level = 0
248
TX power level = 4
179
TX power level = 0
223
TX power level = 4
160
1 DSSS
53
54 OFDM
53
MAX
UNIT
mA
mA
Idle connected (4)
690
µA
LPDS
115
µA
Hibernate
4
µA
Shutdown
1
µA
Peak calibration current (5) (3)
(1)
(2)
(3)
(4)
(5)
VBAT = 3.6 V
420
VBAT = 3.3 V
450
VBAT = 2.1 V
670
mA
TX power level = 0 implies maximum power (see Figure 5-1, Figure 5-2, and Figure 5-3). TX power level = 4 implies output power
backed off approximately 4 dB.
The CC3135 system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
The RX current is measured with a 1-Mbps throughput rate.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed
sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two
additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC31XX
CC32XX SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
5.6
Current Consumption Summary: 5 GHz RF Band
TA = 25°C, VBAT = 3.6 V
PARAMETER
TX
RX (3)
TEST CONDITIONS (1)
(2)
MIN
TYP
6 OFDM
318
54 OFDM
293
54 OFDM
MAX
UNIT
mA
61
mA
Idle connected (4)
690
µA
LPDS
115
µA
Hibernate
4
µA
Shutdown
1
µA
Peak calibration current (5) (3)
(1)
(2)
(3)
(4)
(5)
18
VBAT = 3.6 V
290
VBAT = 3.3 V
310
VBAT = 2.7 V
310
VBAT = 2.1 V
400
mA
TX power level = 0 implies maximum power (see Figure 5-1, Figure 5-2, and Figure 5-3). TX power level = 4 implies output power
backed off approximately 4 dB.
The CC3135 system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
The RX current is measured with a 1-Mbps throughput rate.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed
sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two
additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC31XX,
CC32XX SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
Specifications
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SWAS037 – FEBRUARY 2019
TX Power Control for 2.4 GHz Band
The CC3135 has several options for modifying the output power of the device when required. For the 2.4
GHz band it is possible to lower the overall output power at a global level using the global TX power level
setting. In addition, the 2.4 GHz band allows the user to enter additional back-offs (1), per channel, region
(2)
and modulation rates (3), via Image creator (see the UniFlash CC31xx, CC32xx SimpleLink™ Wi-Fi®
and Internet-on-a chip™ Solution ImageCreator and Programming Tool User's Guide for more details).
Figure 5-1, Figure 5-2, and Figure 5-3 show TX power and IBAT versus TX power level settings for the
CC3135 device at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively.
In Figure 5-1, the area enclosed in the circle represents a significant reduction in current during transition
from TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI
recommends using TX power level 4 to reduce the current.
1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
TX Power (dBm)
15.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 5-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
(1)
(2)
(3)
The back-off range is between -6 dB to +6 dB in 0.25 dB increments.
FCC/ISED, ETSI (Europe), and Japan are supported.
Back-off rates are grouped into 11b rates, high modulation rates (MCS7, 54 OFDM and 48 OFDM), and lower modulation rates (all other
rates).
Specifications
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6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 5-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 5-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
20
Specifications
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SWAS037 – FEBRUARY 2019
TX Power Control for 5 GHz
5 GHz power control is done via Image Creator where the maximum transmit power is provided (1). Within
Image Creator power control is possible per channel, region (2), and modulation rates (3). In addition, it is
possible to enter an additional back-off (4) factor per channel and modulation rate for further margin to
regulatory requirements.
Finally, it is also possible to set the TX and RX trace losses to the antenna per band (5). The peak antenna
gain (6) can also be provided, thus allowing further control. For a full description of options and capabilities
see the UniFlash CC31xx, CC32xx SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution ImageCreator
and Programming Tool User's Guide.
(1)
(2)
(3)
(4)
(5)
(6)
The maximum transmit power range is 18 dBm to 0.125 dBm in 0.125 dBm decrements.
FCC/ISED, ETSI (Europe), and Japan are supported.
Rates are grouped into high modulation rates (MCS7, 54 OFDM and 48 OFDM) and lower modulation rates (all other rates).
The back-off range is 0 dBm to 18 dBm in 0.125 dBm increments, with the maximum back-off not exceed that of the maximum transmit
power.
The range of losses if from 0 dBm to 7.75 dBm in 0.125 dBm increments.
The antenna gain has a range of -2 dBi to 5.75 dBi in 0.125 dBi increments.
Specifications
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Brownout and Blackout Conditions
The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 5-4 and
Figure 5-5). This condition must be considered during design of the power supply routing, especially when
operating from a battery. High-current operations, such as a TX packet or any external activity (not
necessarily related directly to networking) can cause a drop in the supply voltage, potentially triggering a
brownout condition. The resistance includes the internal resistance of the battery, the contact resistance of
the battery holder (four contacts for 2× AA batteries), and the wiring and PCB routing resistance.
NOTE
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect
during HIBERNATE state.
Supply
Voltage
Vbrownout
Vblackout
Chip in
Hibernate
Chip in
Hibernate
Brownout
is disabled
Brownout
is disabled
Chip in
Hibernate
Brownout
Brownout
is disabled
0V
Time
1
Software
Enters
Hibernate
2
Chip
Exits
Hibernate
3
4
Software
Enters
Hibernate
5
6
Chip
Exits
Hibernate
7
8
Software
Enters
Hibernate
Chip Gets
Fully Reset
In Blakcout
9
Chip Exits
Blackout Reset
& Boots
Figure 5-4. Brownout and Blackout Levels (1 of 2)
Supply
Voltage
Vbrownout
SLEEP
ACTIVE
SLEEP
SLEEP
Brownout
ACTIVE
LPDS
Brownout
Brownout
Vblackout
ACTIVE
LPDS
LPDS
0V
Time
1
2
3
4
5
6
7
Figure 5-5. Brownout and Blackout Levels (2 of 2)
22
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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the
Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The
blackout condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 5-1 lists the brownout and blackout voltage levels.
Table 5-1. Brownout and Blackout Voltage Levels
CONDITION
VOLTAGE LEVEL
UNIT
Vbrownout
2.1
V
Vblackout
1.67
V
5.10 Electrical Characteristics for DIO Pins
Table 5-2. Electrical Characteristics: DIO Pins Except 52 and 53
TA = 25°C, VBAT = 2.1 V to 3.3 V. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
CIN
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
V
VIL
Low-level input voltage
–0.5
0.35 × VDD
V
IIH
High-level input current
5
nA
IIL
Low-level input current
5
nA
VOH
VOL
IOH
IOL
(1)
High-level output
voltage
Low-level output
voltage
High-level
source
current
Low-level
sink
current
4
UNIT
pF
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
V
2-mA drive
2
4-mA drive
4
6-mA drive
6
2-mA drive
2
4-mA drive
4
6-mA drive
6
mA
mA
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of
interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
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Table 5-3. Electrical Characteristics: DIO Pins 52 and 53
TA = 25°C, VBAT = 2.1 V to 3.6 V. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
VIL
Low-level input voltage
–0.5
0.35 × VDD
IIH
High-level input current
50
nA
IIL
Low-level input current
50
nA
VOH
VOL
IOH
IOL
VIL
(1)
7
UNIT
CIN
High-level output voltage
Low-level output voltage
High-level
source current,
VOH = 2.4
Low-level sink
current
pF
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O
drive strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O
drive strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
V
V
V
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O
drive strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O
drive strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
V
2-mA
drive
1.5
4-mA
drive
2.5
6-mA
drive
3.5
2-mA
drive
1.5
4-mA
drive
2.5
6-mA
drive
3.5
mA
mA
nRESET
0.6
V
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of
interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
5.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
TA = 25°C, VBAT = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
IOH
Pullup current, VOH = 2.4 (VDD = 3.0 V)
5
IOL
Pulldown current, VOL = 0.4 (VDD = 3.0
V)
5
24
Specifications
TYP
MAX
10
UNIT
µA
µA
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5.12 WLAN Receiver Characteristics
Table 5-4. WLAN Receiver Characteristics: 2.4 GHz Band
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER
TEST CONDITIONS (Mbps)
TYP
–96.0
2 DSSS
–94.0
11 CCK
–88.0
6 OFDM
–90.5
9 OFDM
–90.0
18 OFDM
–86.5
36 OFDM
–80.5
54 OFDM
–74.5
MCS7 (GF) (2)
–71.5
Sensitivity
(8% PER for 11b rates, 10% PER for
11g/11n rates) (1)
Maximum input level
(10% PER)
(1)
(2)
MIN
1 DSSS
802.11b
–4.0
802.11g
–10.0
MAX
UNIT
dBm
dBm
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
Sensitivity for mixed mode is 1-dB worse.
Table 5-5. WLAN Receiver Characteristics: 5 GHz Band
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin are the average of channels 40, 56, 120, and 157.
PARAMETER
Sensitivity
(10% PER for 11g/11n rates)
TEST CONDITIONS (Mbps)
(1)
TYP
-92.0
9 OFDM
-91.0
18 OFDM
-88.0
36 OFDM
-81.5
54 OFDM
-75.0
MCS7 (GF)
Maximum input level
MIN
6 OFDM
(1)
802.11a
MAX
UNIT
dBm
-71.0
-20
dBm
Sensitivity for mixed mode is 1-dB worse.
Specifications
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5.13 WLAN Transmitter Characteristics
Table 5-6. WLAN Transmitter Characteristics: 2.4 GHz Band
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz). (1) (2)
PARAMETER
TEST CONDITIONS
Operating frequency range (3) (4)
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
MIN
1 DSSS
18.0
2 DSSS
18.0
11 CCK
18.3
6 OFDM
17.3
9 OFDM
17.3
18 OFDM
17.0
36 OFDM
16.0
54 OFDM
14.5
MCS7
Transmit center frequency accuracy
(1)
(2)
(3)
(4)
TYP
2412
MAX
UNIT
2472
MHz
dBm
13.0
–25
25
ppm
The OFDM and MCS7 edge channels (2412 and 2462 MHz) have reduced TX power to meet FCC emission limits.
Power of 802.11b rates are reduced to meet ETSI requirements in Europe.
Channels 1 (2142 MHz) through 11 (2462 MHz) are supported for FCC.
Channels 1 (2142 MHz) through 13 (2472MHz) are supported for Europe and Japan. Note that channel 14 is not supported for Japan.
Table 5-7. WLAN Transmitter Characteristics: 5 GHz Band
TA = 25°C, VBAT = 2.1 V to 3.6 V. (1) Parameters measured at SoC pin are the average of channels 40, 56, 120, and 157. (2)
PARAMETER
Operating frequency range
TEST CONDITIONS
(3) (4) (5)
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
26
TYP
5180
6 OFDM
18.1
9 OFDM
18.1
18 OFDM
18.1
36 OFDM
16.6
54 OFDM
15.0
MCS7
14.0
Transmit center frequency accuracy
(1)
(2)
(3)
(4)
(5)
MIN
-20
MAX
UNIT
5825
MHz
dBm
20
ppm
Transmit power will be reduced by 1.5dB for VBAT < 2.8V
FCC, Europe, and Japan channel power limits per modulation rates can be found in the Uniflash with Image Creator User Guide.
FCC band covers U-NII-1, U-NII-2A, U-NII-2C, and U-NII-3 20-MHz BW modulations.
Europe bands 1, 2 and 3, 20-MHz BW modulations are supported.
For Japan, W52, W53 and W56, 20-MHz BW modulations are supported.
Specifications
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5.14 WLAN Transmitter Out-of-Band Emissions
Both the 2.4 GHz and the 5 GHz RF paths require an external band-pass filter to meet the various
emission standards, including FCC. Table 5-8 and Table 5-9 presents the minimum attenuation
requirements for the 2.4 GHz and 5 GHz band-pass filter, respectively. TI recommends using the same
filter, switch, diplexer, and so on, used in the reference design to ease the process of certification.
Table 5-8. WLAN 2.4 GHz Filter Requirements
PARAMETER
FREQUENCY (MHz)
Return loss
2412 to 2484
Insertion loss (1)
2412 to 2484
Attenuation
Reference impendence
TYP
MAX
1
1.5
10
UNIT
dB
804 to 828
30
42
1608 to 1656
20
23
3216 to 3312
30
49
4020 to 4140
40
52
4824 to 4968
20
30
5628 to 5796
20
27
6432 to 6624
20
42
7200 to 7500
35
44
7500 to 10000
20
30
2412 to 2484
Filter type
(1)
MIN
dB
dB
50
Ω
Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
Table 5-9. WLAN 5 GHz Filter Requirements
PARAMETER
FREQUENCY (MHz)
Return loss
5150 to 5925
Insertion loss (1)
5150 to 5925
Attenuation
Reference impendence
Filter type
(1)
MIN
TYP
MAX
1
2
10
dB
600 to 2700
41
42
2950 to 3850
27
31
4400 to 4600
20
27
6600 to 6900
20
28
7000 to 7775
20
27
10300 to 11850
25
37
5150 to 5925
UNIT
50
dB
dB
Ω
Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
Specifications
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5.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
For proper BLE/2.4 GHz radio coexistence, the following requirements needs to met:
Table 5-10. COEX Isolation Requirement
PARAMETER
Port-to-port isolation
(1)
(2)
Band
MIN
Single antenna
20 (1)
Dual antenna Configuration
20 (2)
TYP
MAX
UNIT
dB
WLAN/BLE switch used must provide a minimum of 20 dB isolation between ports.
For dual antenna configuration antenna placement must be such that isolation between the BLE and WLAN ports is at least 20 dB.
5.16
Thermal Resistance Characteristics for RGK Package
THERMAL METRICS (1)
°C/W (2)
(3)
AIR FLOW (m/s) (4)
RΘJC
Junction-to-case
6.3
0.0051
RΘJB
Junction-to-board
2.4
0.0051
RΘJA
Junction-to-free air
23
0.0051
14.6
0.765
RΘJMA
Junction-to-moving air
12.4
1.275
10.8
2.55
0.2
0.0051
0.2
0.765
0.3
1.275
0.1
2.55
2.3
0.0051
2.3
0.765
2.2
1.275
2.4
2.55
PsiJT
PsiJB
(1)
(2)
(3)
(4)
28
Junction-to-package top
Junction-to-board
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
m/s = meters per second.
Specifications
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5.17 Timing and Switching Characteristics
5.17.1 Power Supply Sequencing
For proper operation of the CC3135 device, perform the recommended power-up sequencing as follows:
1. Tie the following pins together on the board:
– VBAT (pins 37, 39, and 44)
– VIO (pins 54 and 10)
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit
(100 K ||, 0.01 µF, RC = 1 ms).
3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see Section 5.17.3.
5.17.2 Device Reset
When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must
follow one of the following alternatives to ensure the reset is properly applied:
• A negative reset pulse (on pin 32) of at least 200-ms duration
• If the 200-ms pulse duration cannot be ensured, a pulldown resistor of 2 MΩ must be connected to pin
52 (RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used.
To ensure a proper reset sequence, the user must call the sl_stop function prior to toggling the reset.
When a reset is required, it is preferable to use the software reset instead of an external trigger.
5.17.3 Reset Timing
5.17.3.1 nRESET (32-kHz Crystal)
Figure 5-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal.
T2
T1
T3
VBAT
VIO
nRESET
nHIB
STATE POWER RESET
OFF
HW INIT
FW INIT
Device Ready to
serve API calls
32-kHz
XTAL
Figure 5-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)
Table 5-11 describes the timing requirements for the 32-kHz crystal first-time power-up and reset removal.
Table 5-11. First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
ITEM
NAME
T1
nReset time
T2
Hardware wake-up time
T3
Initialization time
DESCRIPTION
nReset timing after VBAT and VIO supply are
stable
32-kHz crystal settling plus firmware
initialization time plus radio calibration
MIN
TYP
MAX
1
ms
25
ms
1.35
s
Specifications
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5.17.3.2 nRESET (External 32-kHz Crystal)
Figure 5-7 shows the reset timing diagram for the external 32-kHz crystal first-time power-up and reset
removal.
T1
T2
T3
RESET
HW INIT
FW INIT
VBAT
VIO
nRESET
nHIB
STATE
POWER
OFF
Device Ready to
serve API calls
32-kHz
RTC CLK
Figure 5-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz Crystal)
Table 5-12 describes the timing requirements for the external first-time power-up and reset removal.
Table 5-12. First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Crystal)
ITEM
NAME
T1
nReset time
T2
Hardware wake-up time
T3
Initialization time
30
DESCRIPTION
nReset timing after VBAT and VIO supply are
stable
Firmware initialization time plus radio
calibration
Specifications
MIN
TYP
MAX
UNIT
1
ms
25
ms
250
ms
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5.17.4 Wakeup From HIBERNATE Mode
NOTE
The 32.768-kHz crystal is kept enabled by default when the chip goes into HIBERNATE
mode in response to nHIB being pulled low.
Figure 5-8 shows the timing diagram for wakeup from HIBERNATE mode.
Thib_min
Twake_from_hib
HIBERNATE
HW WAKEUP+FW INIT
VBAT
VIO
nRESET
nHIB
ACTIVE
ACTIVE
HIBERNATE
32-kHz
XTAL/CXO
Figure 5-8. nHIB Timing Diagram
Table 5-13 describes the timing requirements for nHIB.
Table 5-13. nHIB Timing Requirements
ITEM
NAME
DESCRIPTION
Thib_min
Minimum hibernate time
Minimum pulse width of nHIB being low (1)
Twake_from_hib
Hardware wakeup time plus
firmware initialization time
See (2)
(1)
(2)
MIN
TYP
MAX
10
UNIT
ms
50
ms
Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so
on).
If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.
Specifications
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5.17.5 Clock Specifications
The CC3135 device requires two separate clocks for its operation:
• A slow clock running at 32.768 kHz is used for the RTC.
• A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN
subsystem.
The device features internal oscillators that enable the use of less-expensive crystals rather than
dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing
clock on the system and to reduce overall cost.
5.17.5.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow
clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between
RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm
requirement.
Figure 5-9 shows the crystal connections for the slow clock.
51
RTC_XTAL_P
10 pF
GND
32.768 kHz
RTC_XTAL_N
52
10 pF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 5-9. RTC Crystal Connections
Table 5-14 lists the RTC crystal requirements.
Table 5-14. RTC Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
TYP
MAX
UNIT
±150
ppm
32.768
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
32.768 kHz
32
MIN
Specifications
kHz
70
kΩ
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5.17.5.2 Slow Clock Using an External Clock
When an RTC oscillator is present in the system, the CC3135 device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must
be a CMOS-level clock compatible with VIO fed to the device.
Figure 5-10 shows the external RTC input connection.
RTC_XTAL_P
32.768 kHz
VIO
Host system
100 KΩ
RTC_XTAL_N
Copyright © 2017, Texas Instruments Incorporated
Figure 5-10. External RTC Input
Table 5-15 lists the external RTC digital clock requirements.
Table 5-15. External RTC Digital Clock Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
Frequency accuracy
(Initial plus temperature plus aging)
tr, tf
Vil
Slow clock input voltage limits
Input impedance
MAX
UNIT
Hz
±150
ppm
Input transition time tr, tf
(10% to 90%)
100
Frequency input duty cycle
Vih
TYP
32768
20%
Square wave, DC coupled
Resistance
50%
ns
80%
0.65 × VIO
VIO
0
0.35 × VIO
V
Vpeak
1
Capacitance
MΩ
5
Specifications
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5.17.5.3 Fast Clock (Fref) Using an External Crystal
The CC3135 device also incorporates an internal crystal oscillator to support a crystal-based fast clock.
The crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable
loading capacitors.
Figure 5-11 shows the crystal connections for the fast clock.
23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
WLAN_XTAL_N
22
6.2 pF
GND
SWAS031-030
NOTE: The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx
Frequency Tuning for information on frequency tuning.
Figure 5-11. Fast Clock Crystal Connections
Table 5-16 lists the WLAN fast-clock crystal requirements.
Table 5-16. WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
TYP
MAX
40
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
40 MHz
34
MIN
Specifications
UNIT
MHz
±20
ppm
60
Ω
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5.17.5.4 Fast Clock (Fref) Using an External Oscillator
The CC3135 device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the
clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The
external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power
consumption of the system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using
the LDO improves noise on the TCXO power supply.
Figure 5-12 shows the connection.
Vcc
XO (40 MHz)
C
CC3135R
EN
TCXO_EN
82 pF
WLAN_XTAL_P
OUT
WLAN_XTAL_N
Figure 5-12. External TCXO Input
Table 5-17 lists the external Fref clock requirements.
Table 5-17. External Fref Clock Requirements (–40°C to +85°C)
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
Frequency accuracy
(Initial plus temperature plus aging)
45%
Sine or clipped sine wave,
AC coupled
Clock voltage limits
0.7
at 1 kHz
Phase noise at 40 MHz
Resistance
ppm
55%
1.2
Vpp
–125
at 10 kHz
–138.5
at 100 kHz
Input impedance
50%
UNIT
MHz
±20
Frequency input duty cycle
Vpp
MAX
40.00
dBc/Hz
–143
12
Capacitance
kΩ
7
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5.17.6 Interfaces
This section describes the interfaces that are supported by the CC3135 device:
• Host SPI
• Flash SPI
• Digital IO
5.17.6.1 Host SPI Interface Timing
Figure 5-13 shows the Host SPI interface timing diagram.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 5-13. Host SPI Interface Timing
Table 5-18 lists the Host SPI interface timing parameters.
Table 5-18. Host SPI Interface Timing Parameters
PARAMETER
NUMBER
(1)
(2)
36
DESCRIPTION
MIN
MAX
Clock frequency at VBAT = 3.3 V
20
Clock frequency at VBAT ≤ 2.1 V
12
UNIT
T1
F (1)
T2
tclk (1) (2)
Clock period
T3
tLP (1)
Clock low period
T4
tHT
(1)
T5
D (1)
Duty cycle
T6
tIS (1)
RX data setup time
4
T7
tIH
(1)
RX data hold time
4
T8
tOD (1)
TX data output delay
20
ns
T9
tOH (1)
TX data hold time
24
ns
50
Clock high period
45%
MHz
ns
25
ns
25
ns
55%
ns
ns
The timing parameter has a maximum load of 20 pF at 3.3 V.
Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge.
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5.17.6.2 Flash SPI Interface Timing
Figure 5-14 shows the Flash SPI interface timing diagram.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 5-14. Flash SPI Interface Timing
Table 5-19 lists the Flash SPI interface timing parameters.
Table 5-19. Flash SPI Interface Timing Parameters
PARAMETER
NUMBER
DESCRIPTION
MIN
MAX
UNIT
20
MHz
T1
F
Clock frequency
T2
tclk
Clock period
T3
tLP
Clock low period
25
ns
T4
tHT
Clock high period
25
ns
T5
D
Duty cycle
T6
tIS
RX data setup time
1
ns
T7
tIH
RX data hold time
2
ns
T8
tOD
TX data output delay
T9
tOH
TX data hold time
50
45%
ns
55%
8.5
ns
8
ns
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5.17.6.3 DIO Interface Timing
NOTE
Digital IOs on CC3135 refers to antenna select, hostless mode, and BLE/2.4 GHz
coexistence IOs not general purpose IOs
Figure 5-15 shows the DIO timing diagram.
VDD
80%
20%
tDIOF
tDIOR
SWAS037
Figure 5-15. DIO Timing Diagram
5.17.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3 V)
Table 5-20 lists the DIO output transition times for Vsupply = 3.3 V.
Table 5-20. DIO Output Transition Times (Vsupply = 3.3 V) (1)
DRIVE
STRENGTH
(mA)
DRIVE STRENGTH
CONTROL BITS
2MA_EN=1
2 (2)
4MA_EN=0
2MA_EN=0
4 (2)
4MA_EN=1
2MA_EN=1
6
(1)
(2)
4MA_EN=1
tr
tf
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
8.0
9.3
10.7
8.2
9.5
11.0
ns
6.6
7.1
7.6
4.7
5.2
5.8
ns
3.2
3.5
3.7
2.3
2.6
2.9
ns
Vsupply = 3.3 V, T = 25°C, total pin load = 30 pF
The 2-mA and 4-mA drive strength does not apply to the COEX I/O pins. Pins configured as COEX lines are invariably driven at 6 mA.
5.17.6.3.2 DIO Input Transition Time Parameters
Table 5-21 lists the input transition time parameters.
Table 5-21. DIO Input Transition Time Parameters
PARAMETERS
tr
tf
38
Input transition time (tr, tf), 10% to 90%
Specifications
MIN
MAX
1
3
UNIT
ns
1
3
ns
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5.18 External Interfaces
5.18.1 SPI Flash Interface
The external serial Flash stores the user profiles and firmware patch updates. The CC3135 device acts as
a master in this case; the SPI serial Flash acts as the slave device. This interface can work up to a speed
of 20 MHz.
Figure 5-16 shows the SPI Flash interface.
CC3135R (master)
Serial flash
FLASH_SPI_CLK
SPI_CLK
FLASH_SPI_CS
SPI_CS
FLASH_SPI_MISO
SPI_MISO
FLASH_SPI_MOSI
SPI_MOSI
Figure 5-16. SPI Flash Interface
Table 5-22 lists the SPI Flash interface pins.
Table 5-22. SPI Flash Interface
PIN NAME
DESCRIPTION
FLASH_SPI_CLK
Clock (up to 20 MHz) CC3135 device to serial Flash
FLASH_SPI_CS
CS signal from CC3135 device to serial Flash
FLASH_SPI_MISO
Data from serial Flash to CC3135 device
FLASH_SPI_MOSI
Data from CC3135 device to serial Flash
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5.18.2 SPI Host Interface
The device interfaces to an external host using the SPI interface. The CC3135 device can interrupt the
host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can
work up to a speed of 20 MHz.
Figure 5-17 shows the SPI host interface.
CC3135R (slave)
MCU
HOST_SPI_CLK
SPI_CLK
HOST_SPI_nCS
SPI_nCS
HOST_SPI_MISO
SPI_MISO
HOST_SPI_MOSI
SPI_MOSI
HOST_INTR
INTR
nHIB
GPIO
Figure 5-17. SPI Host Interface
Table 5-23 lists the SPI host interface pins.
Table 5-23. SPI Host Interface
PIN NAME
DESCRIPTION
HOST_SPI_CLK
Clock (up to 20 MHz) from MCU host to CC3135 device
HOST_SPI_nCS
CS (active low) signal from MCU host to CC3135 device
HOST_SPI_MOSI
Data from MCU host to CC3135 device
HOST_INTR
Interrupt from CC3135 device to MCU host
HOST_SPI_MISO
Data from CC3135 device to MCU host
nHIB
Active-low signal that commands the CC3135 device to enter hibernate mode (lowest power state)
40
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5.18.3 Host UART Interface
The SimpleLink device requires the UART configuration described in Table 5-24.
Table 5-24. SimpleLink™ UART Configuration
PROPERTY
SUPPORTED CC3135 CONFIGURATION
Baud rate
115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command
Data bits
8 bits
Flow control
CTS/RTS
Parity
None
Stop bits
1
Bit order
LSBit first
Host interrupt polarity
Active high
Host interrupt mode
Rising edge or level 1
Endianness
Little-endian only (1)
(1)
The SimpleLink device does not support automatic detection of the host length while using the UART interface.
5.18.3.1 5-Wire UART Topology
Figure 5-18 shows the typical 5-wire UART topology comprised of four standard UART lines plus one IRQ
line from the device to the host controller to allow efficient low-power mode.
This topology is recommended because the configuration offers the maximum communication reliability
and flexibility between the host and the SimpleLink device.
HOST MCU
UART
nRTS
nRTS
nCTS
nCTS
TX
TX
RX
RX
CC3135R SL
UART
HOST_INTR(IRQ)
HOST_INTR(IRQ)
Figure 5-18. 5-Wire UART Topology
5.18.3.2 4-Wire UART Topology
The 4-wire UART topology eliminates the host IRQ line (see Figure 5-19). Using this topology requires
meeting one of the following conditions:
• The host is always awake or active.
• The host goes to sleep, but the UART module has receiver start-edge detection for auto wakeup and
does not lose data.
HOST MCU
UART
nRTS
nRTS
nCTS
nCTS
TX
TX
RX
RX
H_IRQ
X
CC3135R SL
UART
H_IRQ
Figure 5-19. 4-Wire UART Configuration
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5.18.3.3 3-Wire UART Topology
The 3-wire UART topology requires only the following lines (see Figure 5-20):
• RX
• TX
• CTS
nRTS
nRTS
X
nCTS
nCTS
HOST MCU
UART
TX
TX
RX
RX
H_IRQ
X
CC3135R SL
UART
H_IRQ
Figure 5-20. 3-Wire UART Topology
Using this topology requires meeting one of the following conditions:
• The host always stays awake or active.
• The host goes to sleep but the UART module has receiver start-edge detection for auto-wake-up and
does not lose data.
• The host can always receive any amount of data transmitted by the SimpleLink™ device because
there is no flow control in this direction.
Because there is no full flow control, the host cannot stop the SimpleLink™ device to send its data; thus,
the following parameters must be carefully considered:
• Maximum baud rate
• RX character interrupt latency and low-level driver jitter buffer
• Time consumed by the user's application
42
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6 Detailed Description
6.1
Overview
Connect any microcontroller (MCU) to the Internet of Things (IoT) with the CC3135 device, a dual-band
wireless network processor from Texas Instruments™. The CC3135 Wi-Fi® Internet-on-a chip™ device
contains an Arm® Cortex®-M3 MCU dedicated to wi-fi and internet protocols, in order to offload networking
activities from the host MCU. The subsystem includes a dual band 802.11a/b/g/n radio, baseband, and
MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit encryption and a built
in power management for best in class low power performance. The CC3135 device supports station, AP,
and
Wi-Fi Direct® modes. The device also supports WPA2™ personal and enterprise security and WPS 2.0.
The Wi-Fi network processor includes an embedded IPv6 and IPv4 TCP/IP stack.
6.2
Device Features
6.2.1
WLAN
The WLAN features are as follows:
• 802.11a/b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station,
AP, Wi-Fi Direct® client, and group owner with CCK and OFDM rates in the 2.4 GHz ISM band
(channels 1 through 13), and the 5 GHz 20-MHz BW U-NII bands (U-NII-1, U-NII-2A, U-NII-2C, and UNII-3).
NOTE
802.11n is supported only in Wi-Fi® station and Wi-Fi Direct®.
•
•
•
•
•
•
•
The automatically calibrated radio with a single-ended 50-Ω interface enables easy connection to the
antenna without requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial flash allows
automatic fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x).
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the
provisioning decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point with HTTP server
– WPS - Wi-Fi Protected Setup, supporting both push button and pin code options.
– SmartConfig™ Technology: TI proprietary, easy to use, one-step, one-time process used to
connect a CC3135-enabled device to the home wireless network.
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket The
802.11 transceiver mode provides the option to select the working channel, rate, and transmitted
power. The receiver mode works with the filtering options.
Antenna selection for best connection
BLE/2.4 GHz radio coexistence mechanism to avoid interference
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Network Stack
The Network Stack features are as follows:
• Integrated IPv4, IPv6 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any
MCU, microprocessor, or ASIC
NOTE
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
Support of 16 simultaneous TCP, UDP, RAW, SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
Built-in network applications and utilities:
– HTTP/HTTPS
• Web page content stored on serial flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks
– Service discovery: Multicast DNS service discovery lets a client advertise its service without a
centralized server. After connecting to the access point, the CC3135 device provides critical
information, such as device name, IP, vendor, and port number.
– DHCP server
– Ping
Table 6-1 describes the NWP features.
44
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Table 6-1. NWP Features
Feature
Description
802.11a/b/g/n station
Wi-Fi standards
802.11a/b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
Wi-Fi channels
2.4 GHz ISM and 5 GHz U-NII Channels
Channel Bandwidth
20 MHz
Wi-Fi security
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x)
Wi-Fi provisioning
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server
IP protocols
IPv4/IPv6
IP addressing
Static IP, LLA, DHCPv4, DHCPv6 with DAD
Cross layer
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW
Ping
HTTP/HTTPS web server
Network applications and
utilities
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Security
Trusted root-certificate catalog
TI root-of-trust public key
Power management
Enhanced power policy management uses 802.11 power save and deep-sleep power modes
Transceiver
Other
Programmable RX filters with event-trigger mechanism
Rx Metrics for tracking the surrounding RF environment
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6.2.3
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Security
The SimpleLink Wi-Fi CC3135 Internet-on-a chip device enhances the security capabilities available for
development of IoT devices, while completely offloading these activities from the MCU to the networking
subsystem. The security capabilities include the following key features:
Code and Data Security:
• Secured network information: Network passwords and certificates are encrypted
• Secured and authenticated service pack: SP is signed based on TI certificate
Wi-Fi and Internet Security:
• Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK)
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0 MSCHAPv2
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
• Secure HTTP server (HTTPS)
• The Trusted root-certificate catalog verifies that the CA used by the application is trusted and known
secure content delivery
• The TI root-of-trust public key is a hardware-based mechanism that allows authenticating TI as the
genuine origin of a given content using asymmetric keys
• Secure content delivery allows file transfer to the system in a secure way on any unsecured tunnel
46
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•
6.2.4
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Secure sockets
– Protocol versions: SSL v3/TLS 1.0/TLS 1.1/TLS 1.2
– On-chip powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES
encryption for TLS and SSL connections
– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
– Socket upgrade to secure socket – STARTTLS
Host Interface and Driver
•
•
•
6.2.5
Interfaces over a 4-wire serial peripheral interface (SPI) with any MCU or a processor at a clock speed
of 20 MHz.
Interfaces over UART with any MCU with a baud rate up to 3 Mbps. A low footprint driver is provided
for TI MCUs and is easily ported to any processor or ASIC.
Simple APIs enable easy integration with any single-threaded or multithreaded application.
System
•
•
•
Works from a single preregulated power supply or connects directly to a battery
Ultra-low leakage when disabled (hibernate mode) with a current of less than 4 µA with the RTC
running
Integrated clock sources
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FIPS 140-2 Level 1 Certification
The Federal Information Processing Standard (FIPS) Publication 140-2 is a U.S. government computer
security standard. It is commonly referred to as FIPS 140-2 and is used to accredit the design and
implementation of cryptographic modules. A cryptographic module within a security system is necessary to
maintain the confidentiality and integrity of the information protected by the device.
The security engines of the CC3135 device is FIPS validated for FIPS 140-2 level 1 certification (1). This
certification involves testing the device for all areas related to the secure design and implementation of the
cryptographic modules and covers topics such as: cryptographic specifications, ports and interfaces, a
finite state model for the cryptographic module, the operational environment of the module, and how
cryptographic keys are managed.
6.4
Power-Management Subsystem
The CC3135 power-management subsystem contains DC/DC converters to accommodate the different
voltage or current requirements of the system.
• Digital DC/DC (Pin 44): Input: VBAT wide voltage (2.1 to 3.6 V)
• ANA1 DC/DC (Pin 38): Input: VBAT wide voltage (2.1 to 3.6 V)
• PA DC/DC (Pin 39): Input: VBAT wide voltage (2.1 to 3.6 V)
The CC3135 device is a single-chip WLAN radio solution used on an embedded system with a widevoltage supply range. The internal power management, including DC/DC converters and LDOs, generates
all of the voltages required for the device to operate from a wide variety of input sources. For maximum
flexibility, the device can operate in the modes described in Section 6.4.1.
6.4.1
VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the device is powered directly by the battery or preregulated 3.3-V
supply. All other voltages required to operate the device are generated internally by the DC/DC
converters. This scheme supports wide-voltage operation from 2.1 to 3.6 V and is thus the most common
mode for the device.
(1)
48
For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.
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Low-Power Operating Modes
This section describes the low-power modes supported by the device to optimize battery life.
6.5.1
Low-Power Deep Sleep
The low-power deep-sleep (LPDS) mode is an energy-efficient and transparent sleep mode that is entered
automatically during periods of inactivity based on internal power optimization algorithms. The device can
wake up in less than 3 ms from the internal timer or from any incoming host command. Typical battery
drain in this mode is 115 µA. During LPDS mode, the device retains the software state and certain
configuration information. The operation is transparent to the external host; thus, no additional handshake
is required to enter or exit LPDS mode. Advanced features of long sleep interval and IoT low power for
extending LPDS time for up to 22 seconds while maintaining Wi-Fi connection is also supported
6.5.2
Hibernate
The hibernate mode is the lowest power mode in which all of the digital logic is power-gated. Only a small
section of the logic powered directly by the main input supply is retained. The RTC is kept running and the
device wakes up once the nHIB line is asserted by the host driver. The wake-up time is longer than LPDS
mode at approximately 50 ms. The typical battery drain in this mode is 4.5 µA.
NOTE
Wake-up time can be extended depending on the service-pack size.
6.5.3
Shutdown
The shutdown mode is the lowest power-mode system-wise. All device logics are off, including the realtime clock (RTC). The wake-up time in this mode is longer than hibernate at approximately 1.1 s. The
typical battery drain in this mode is 1 µA.
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6.6
6.6.1
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Memory
External Memory Requirements
The CC3135 device maintains a proprietary file system on the sFLASH. The CC3135 file system stores
the service pack file, system files, configuration files, certificate files, web page files, and user files. By
using a format command through the API, users can provide the total size allocated for the file system.
The starting address of the file system cannot be set and is always at the beginning of the sFLASH. The
applications microcontroller must access the sFLASH memory area allocated to the file system directly
through the CC3135 file system. The applications microcontroller must not access the sFLASH memory
area directly.
The file system manages the allocation of sFLASH blocks for stored files according to download order,
which means that the location of a specific file is not fixed in all systems. Files are stored on sFLASH
using human-readable filenames rather than file IDs. The file system API works using plain text, and file
encryption and decryption is invisible to the user. Encrypted files can be accessed only through the file
system.
All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB
blocks and thus use a minimum of 4KB of Flash space. Fail-safe files require twice the original size and
use a minimum of 8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size
is 1MB.
Table 6-2 lists the minimum required memory consumption under the following assumptions:
• System files in use consume 64 blocks (256KB).
• Vendor files are not taken into account.
• Gang image:
– Storage for the gang image is rounded up to 32 blocks (meaning 128-KB resolution).
– Gang image size depends on the actual content size of all components. Additionally, the image
should be 128-KB aligned so unaligned memory is considered lost. Service pack, system files, and
the 128-KB aligned memory are assumed to occupy 256KB.
• All calculations consider that the restore-to-default is enabled.
Table 6-2. Recommended Flash Size
ITEM
CC3135 [KB]
File system allocation table
20
System and configuration files
256
Service Pack
264
Gang image size
256
Total
796
Minimal Flash size
8MBit
Recommended Flash size
16MBit
NOTE
The maximum supported serial flash size is 32MB (256Mb) (see Using Serial Flash on
CC3135/CC3235 SimpleLink™ Wi-Fi® and Internet-of-Things Devices).
50
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Restoring Factory Default Configuration
The device has an internal recovery mechanism that allows rolling back the file system to its predefined
factory image or restoring the factory default parameters of the device. The factory image is kept in a
separate sector on the sFLASH in a secure manner and cannot be accessed from the host processor. The
following restore modes are supported:
• None – no factory restore settings
• Enable restore of factory default parameters
• Enable restore of factory image and factory default parameters
The restore process is performed by pulling or forcing SOP[2:0] = 110 pins and toggling the nRESET pin
from low to high.
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial Flash vendor.
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6.8
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Hostless Mode
The SimpleLink™ Wi-Fi® CC3135 device incorporates a scripting ability that enables offloading of simple
tasks from the host processor. Using simple and conditional scripts, repetitive tasks can be handled
internally, which allows the host processor to remain in a low-power state. In some cases where the
scripter is being used to send packets, it reduces code footprint and memory consumption. The if-thisthen-that style conditioning can include anything from GPIO toggling to transmitting packets.
The conditional scripting abilities can be divided into conditions and actions. The conditions define when to
trigger actions. Only one action can be defined per condition, but multiple instances of the same condition
may be used, so in effect multiple actions can be defined for a single condition. In total, 16 condition and
action pairs can be defined. The conditions can be simple, or complex using sub-conditions (using a
combinatorial AND condition between them). The actions are divided into two types, those that can occur
during runtime and those that can occur only during the initialization phase.
The following actions can only be performed when triggered by the pre-initialization condition:
• Set roles AP, station, P2P, and Tag modes
• Delete all stored profiles
• Set connection policy
• Hardware GPIO indication allows an I/O to be driven directly from the WLAN core hardware to indicate
internal signaling
The following actions may be activated during runtime:
• Send transceiver packet
• Send UDP packet
• Send TCP packet
• Increment counter increments one of the user counters by 1
• Set counter allows setting a specific value to a counter
• Timer control
• Set GPIO allows GPIO output from the device using the internal networking core
• Enter Hibernate state
NOTE
Consider the following limitations:
• Timing cannot be ensured when using the network scripter because some variable
latency will apply depending on the utilization of the networking core.
• The scripter is limited to 16 pairs of conditions and reactions.
• Both timers and counters are limited to 8 instances each. Timers are limited to a
resolution of 1 second. Counters are 32 bits wide.
• Packet length is limited to the size of one packet and the number of possible packet
tokens is limited to 8.
52
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
7.1.1
Application Information
BLE/2.4 GHz Radio Coexistence
The CC3135 device is designed to support BLE/2.4 GHz radio coexistence. Because WLAN is inherently
more tolerant to time-domain disturbances, the coexistence mechanism gives priority to the Bluetooth® low
energy entity over the WLAN. Bluetooth® low energy operates in the 2.4 GHz band, therefore the
coexistence mechanism does not affect the 5 GHz band. The CC3135 device can operate normally on the
5 GHz band, while the Bluetooth® low energy works on the 2.4 GHz band without mutual interference.
The following coexistence modes can be configured by the user:
• Off mode or intrinsic mode
– No BLE/2.4 GHz radio coexistence, or no synchronization between WLAN and Bluetooth® low
energy—in case Bluetooth® low energy exists in this mode, collisions can randomly occur.
• Time Division Multiplexing (TDM, Single Antenna)
– 2.4 GHz Wi-Fi band (see Figure 7-1)
In this mode, the two entities share the antenna through an RF switch using two GPIOs (one input
and one output from the WLAN perspective).
– 5 GHz Wi-Fi band (see Figure 7-2)
In this mode, the WLAN operates on the 5 GHz band and Bluetooth® low energy operates on the
2.4 GHz band. A 2.4- or 5 GHz diplexer is required for sharing the single antenna.
• Time Division Multiplexing (TDM, Dual Antenna)
– 2.4 GHz Wi-Fi Band (see Figure 7-3)
In this mode, the two entities have separate antennas. No RF switch is required and only a single
GPIO (one input from the WLAN perspective).
– 5 GHz Wi-Fi band (see Figure 7-4)
In this mode, the WLAN operates on the 5 GHz band and Bluetooth® low energy operates on the
2.4 GHz band. No diplexer is required for the dual-antenna solution.
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BLE / 2.4 GHz Ant.
SPDT RF SWITCH
RF_BG
RF
WLAN
CC3135
BLE
CCxxxx
CC_COEX_SW_OUT
Coex IO
CC_COEX_BLE_IN
Figure 7-1. 2.4 GHz, Single-Antenna Coexistence Mode Block Diagram
Figure 7-2 shows the single antenna implementation of a complete Bluetooth® low energy and WLAN
coexistence network with the WLAN operating on either a 2.4- or a 5 GHz band. The SOP lines control the
5 GHz switch. The Coex switch is controlled by a GPIO signal from the BLE device and a GPIO signal
from the CC3135 device.
A_TX
5 GHz SPDT RF
SWITCH
Dual band Ant.
A_RX
SOP0
WLAN
CC3135
5 GHz
BPF
SOP1
RF_BG
2.4 / 5 GHz
Diplexer
CC_COEX_SW_OUT
CC_COEX_BLE_IN
Coex SPDT RF
SWITCH
Coex IO
BLE
CCxxxx
2.4 GHz
BPF
RF
Figure 7-2. Single Antenna Coexistence Solution with 5 GHz Wi-Fi ®
54
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Figure 7-3 shows the dual antenna implementation of a complete Bluetooth® low energy and WLAN
coexistence network with the WLAN operating on either a 2.4- or a 5 GHz band. Note in this
implementation no Coex switch is required and only a single GPIO from the BLE device to the CC3135
device is required.
2.4 GHz Ant.
BLE Ant.
RF_BG
RF
WLAN
CC3135
BLE
CCxxxx
Coex IO
CC_COEX_BLE_IN
Figure 7-3. Dual-Antenna Coexistence Mode Block Diagram
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Figure 7-4 shows the dual antenna implementation of a complete Bluetooth® low energy and WLAN
coexistence network with the WLAN operating on either a 2.4- or a 5 GHz band. In this case, the 2.4 GHz
and 5 GHz Wi-Fi share an antenna and the BLE has it's own dedicated antenna. The SOP lines control
the 5 GHz switch. Note in this implementation no Coex switch is required and only a single GPIO from the
BLE device to the CC3135 device is required.
A_TX
Dual Band Ant.
5 GHz SPDT RF
SWITCH
A_RX
5 GHz
BPF
SOP0
WLAN
CC3135
SOP1
2.4 / 5 GHz
Diplexer
RF_BG
2.4 GHz
BPF
CC_COEX_SW_OUT
CC_COEX_BLE_IN
Coex IO
BLE
CCxxxx
RF
BLE Ant.
Figure 7-4. Dual Antenna Coexistence Solution with 5 GHz Wi-Fi
56
Applications, Implementation, and Layout
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7.1.2
SWAS037 – FEBRUARY 2019
Antenna Selection
The CC3135 device is designed to also support antenna selection and is controlled from Image Creator.
When enabled, there are 3 options possible options:
•
ANT 1: When selected, the GPIOs that are defined for antenna selection with set the RF path for
antenna 1.
ANT 2: When selected, the GPIOs that are defined for antenna selection will set the RF path for
antenna 2.
Autoselect: When selected, during a scan and prior to connecting to an AP, CC3135 device will
determine the best RF path and select the appropriate antenna (1) (2). The result is the saved as port of
the profile.
•
•
Figure 7-5 shows the implementation of a complete Bluetooth® low energy and WLAN coexistence
network with the WLAN operating on either a 2.4- or a 5 GHz band with antenna selection. The SOP lines
control the 5 GHz switch. The Coex switch is controlled by a GPIO signal from the BLE device and a
GPIO signal from the CC3135 device. The Antenna switch is controlled by 2 GPIO lines from the CC3135
device.
A_TX
Dual Band Ant. 1
5 GHz SPDT RF
SWITCH
A_RX
5 GHz
BPF
SOP0
WLAN
CC3135
SOP1
2.4 / 5 GHz
Diplexer
RF_BG
CC_COEX_SW_OUT
CC_COEX_BLE_IN
ANT_SEL_1
Coex SPDT RF
SWITCH
Coex IO
BLE
CCxxxx
Antenna Selection
SPDT RF Switch
2.4 GHz
BPF
Dual Band Ant. 2
RF
ANT_SEL_2
Figure 7-5. Antenna Selection Solution with Coexistence Solution and 5 GHz Wi-Fi ®
(1)
(2)
When selecting Autoselect via the API, a reset is required in order for the CC3135 device to determine the best antenna for use.
Refer to the UniFlash CC31xx, CC32xx SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution ImageCreator and Programming Tool
User's Guide for more information.
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Figure 7-6 shows the antenna selection implementation for Wi-Fi®, with BLE operating on it's own
antenna. The SOP lines control the 5 GHz switch. Note in this implementation no Coex switch is required
and only a single GPIO from the BLE device to the CC3135 device is required. The Antenna switch is
controlled by 2 GPIO lines from the CC3135 device.
A_TX
5 GHz SPDT RF
SWITCH
Dual Band Ant. 1
A_RX
5 GHz
BPF
SOP0
WLAN
CC3135
SOP1
2.4 / 5 GHz
Diplexer
RF_BG
2.4 GHz
BPF
CC_COEX_SW_OUT
CC_COEX_BLE_IN
ANT_SEL_1
Antenna Selection
SPDT RF Switch
BLE
Coex IO CCxxxx
RF
Dual Band Ant. 2
ANT_SEL_2
BLE Ant.
Figure 7-6. Coexistence Solution with Wi-Fi Antenna Selection and Dedicated BLE Antenna
7.1.3
Typical Application
Figure 7-7 shows the schematic of the engine area for the CC3135 device in the wide-voltage mode of
operation, with the corresponding bill of materials show in Table 7-1. Figure 7-8 provides the schematic for
the RF implementation with and without BLE/2.4 GHz coexistence, with the corresponding bill of materials
shown in Table 7-2. For a full operation reference design, see the CC3135 SimpleLink™ WI-Fi®
BoosterPack™ Design Files.
58
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Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
RF_BG
VBAT_CC
VBAT_CC
See Figure 7.8 For
RF Configuration Options
VBAT_CC
A_RX
A_TX
C1
100µF
C2
100µF
VBAT_CC
R1
GND
C4
0.6pF
C3
4.7uF
C5
4.7uF
C6
4.7uF
C7
0.5pF
C8
0.1µF
GND
U2
GND
GND
GND
GND
VDD_ANA
C11
10uF
GND
GND
L1
2.2uH
C12
0.1µF
C13
0.2pF
C14
0.1uF
C15
0.6pF
L2
1uH
VDD_PA
GND
GND
GND
10
54
44
39
37
VIN_IO1
VIN_IO2
VIN_DCDC_DIG
VIN_DCDC_PA
VIN_DCDC_ANA
38
48
36
25
DCDC_ANA_SW
VDD_ANA1
LDO_IN1
LDO_IN2
40
41
42
33
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
VDD_PA_IN
43
9
56
DCDC_DIG_SW
VDD_DIG1
VDD_DIG2
47
49
24
VDD_ANA2
VDD_RAM
VDD_PLL
35
34
21
SOP0
SOP1
SOP2/TCXO_EN
L3
GND
2.2uH
VDD_DIG
C16
22uF
C17
22uF
C18
1µF
C19
10uF
VBAT_CC
GND
GND
C20
0.1µF
C21
0.1µF
GND
GND
GND
GND
C24
10uF
C22
0.1µF
GND
C23
0.1uF
GND
32
nRESET
52
RTC_XTAL_N
51
RTC_XTAL_P
GND
VBAT_CC
C25
0.6pF
23
WLAN_XTAL_P
22
WLAN_XTAL_N
26
46
NC
NC
VBAT_CC
GND
R9
69.8k
R10
69.8k
SOP0
SOP1
SOP2
R11
100k
2
CC_nRESET
J3
R17
69.8k
SFL_CLK
SFL_CS
SFL_MISO
SFL_MOSI
UART1_nCTS
UART1_nRTS
UART1_TX
UART1_RX
61
50
55
57
CC_UART1_CTS
CC_UART1_RTS
CC_UART1_TX
CC_UART1_RX
TEST_58
TEST_59
TEST_60
TEST_62
58
59
60
62
DIO10
DIO12
DIO13
DIO23
DIO24
DIO28
DIO29
DIO31
DIO30
DIO8
DIO9
1
3
4
16
17
18
20
45
53
63
64
HOST_SPI_CLK
HOST_SPI_nCS
HOST_SPI_MISO
HOST_SPI_MOSI
HOST_INTR
nHIB
5
8
7
6
15
2
Reserved
19
GND
GND
GND
29
30
65
VBAT_CC
GND
4
MX25R1635FM1IL0
R3
100k
GND
CC_WLRS232_TX
CC_WLRS232_RX
CC_WL_UART_TX
CC_NWP_UART_TX
R4
100k
GND
R5
100k
CC_UART1_CTS
CC_UART1_RTS
CC_UART1_TX
CC_UART1_RX
TP1
TP2
TP3
TP4
GND
CC_SPI_CLK
CC_SPI_CS
CC_SPI_DOUT
CC_SPI_DIN
CC_IRQ
CC_nHIB
R13
100k
Flash Programming /
Host Control
R7
100k R7 is needed only if
UART is used as the
host interface
P1_DIO_10
P3_DIO_12
P4_DIO_13
P16_DIO_23
P17_DIO_24
P18_DIO_28
P20_DIO_29
P45_DIO_31
P53_DIO_30
P63_DIO_8
P64_DIO_9
R12
100k
R6
100k
GND
CC_SPI_CLK
CC_SPI_CS
CC_SPI_DOUT
CC_SPI_DIN
CC_IRQ
CC_nHIB
HOST INTERFACE
(Ensure that nHIBline does
not float at any time.)
R14
100k
GND
GND
GND
1
3
C29
6.2pF
GND
Y2
40MHz
C30
6.2pF
GND
2
4
J2
R16
69.8k
11
14
13
12
CS
SCLK
SI/SIO0
SO/SIO1
WP/SIO2
RESET/SIO3
GND
GND
GND
J1
FLASH_SPI_CLK
FLASH _SPI_CS
FLASH _SPI_MISO
FLASH_SPI_MOSI
VCC
1
6
5
2
3
7
C28
10pF
GND
R15
100k
RF_BG
A_RX
A_TX
31
27
28
C10
0.1µF
8
CC3135RNM2RGKR
C27
10pF
3
2
1
3
2
1
1
32.768kHz
C26
0.01µF
3
2
1
Y1
G
G
R8
270
100k
R2
GND
GND
U1
10k
C9
0.1µF
GND
GND
GND
GND
Figure 7-7. CC3135 Engine Area
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Table 7-1. Bill of Materials for CC3135 Engine Area
Quantity
Designator
Value
Manufacturer
Part Number
Description
2
C1, C2
100 µF
Taiyo Yuden
LMK325ABJ107MMHT
CAP, CERM, 100 µF, 10 V,
+/- 20%, X5R, AEC-Q200 Grade 3,
1210
3
C3, C5, C6
4.7 µF
Taiyo Yuden
JMK105BC6475MV-F
CAP, CERM, 4.7 uF, 6.3 V,
+/- 20%, X6S, 0402
3
C4, C15, C25
0.6 pF
MuRata
GJM0335C1ER60BB01D
CAP, CERM, 0.6pF, 25 V,
+/- 16%, C0G/NP0, 0201
1
C7
0.5 pF
Murata
GJM0335C1ER50BB01D
CAP, CERM, 0.5 pF, 25 V,
+/- 20%, C0G/NP0, 0201
6
C8, C9, C10, C12,
C21, C22
0.1 µF
Walsin
CL05B104KO5NNNC
CAP, CERM, 0.1 µF, 16 V,
+/- 10%, X7R, 0402
1
C26
0.01 µF
Walsin
0402B103K500CT
CAP, CERM, 0.01 µF, 50 V,
+/- 10%, X7R, 0402
3
C11, C19, C24
10 µF
Taiyo Yuden
LMK107BC6106MA-T
CAP, CERM, 10 uF, 10 V,
+/- 20%, X6S, 0603
1
C13
0.2 pF
MuRata
GJM0335C1ER20BB01D
CAP, CERM, 0.2pF, 25 V,
+/- 50%, C0G/NP0, 0201
2
C14, C23
0.1 µF
Samsung ElectroMechanics
CL03A104KP3NNNC
CAP, CERM, 0.1 uF, 10 V,
+/- 10%, X5R, 0201
2
C16, C17
22 µF
MuRata
GRM188C80G226ME15J
CAP, CERM, 22 uF, 4 V,
+/- 20%, X6S, 0603
1
C18
1 µF
Walsin
CL05A105MP5NNNC
CAP, CERM, 1 µF, 10 V,
+/- 20%, X5R, 0402
2
C27, C28
10 pF
Walsin
0402N100J500CT
CAP, CERM, 10 pF, 50 V,
+/- 5%, C0G/NP0, 0402
2
C29, C30
6.2 pF
Walsin
0402N6R2C500CT
CAP, CERM, 6.2 pF, 50 V,
+/- 4%, C0G/NP0, 0402
3
J1, J2, J3
Wurth Elektronik
61300311121
Header, 2.54 mm, 3x1, Gold, TH
2
L1, L3
2.2 µH
MuRata
LQM2MPN2R2NG0
Inductor, Multilayer, Ferrite, 2.2 uH,
1.2 A, 0.11 ohm, SMD
1
L2
1 µH
MuRata
LQM2HPN1R0MG0L
Inductor, Multilayer, Ferrite, 1 uH,
1.6 A, 0.055 ohm, SMD
1
R1
Vishay-Dale
CRCW040210K0JNED
RES, 10 k, 5%, 0.063 W, AECQ200 Grade 0, 0402
10
R2, R3, R4, R5, R6,
R7, R11, R13, R14, 100k
R15
Vishay-Dale
CRCW0402100KJNED
RES, 100 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
1
R8
270
Vishay-Dale
CRCW0402270RJNED
RES, 270, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
1
R12
100k
Yageo America
RC0201JR-07100KL
RES, 100 k, 5%, 0.05 W, 0201
4
R9, R10, R16, R17
69.8k
Vishay-Dale
CRCW040269K8FKED
RES, 69.8 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
1
U1
Macronix International
Co., LTD
MX25R3235FM1IL0
Ultra low power, 32M-bit
[x 1/x 2/x 4] CMOS MXSMIO (serial
multi I/O) Flash memory, SOP-8
1
U2
Texas Instruments
CC3135RNMRGKR
SimpleLink Wi-Fi, Dual-Band
Network Processor, RGK0064B
(VQFN-64)
1
Y1
Abracon Corporation
ABS07-32.768KHZ-9-T
Crystal, 32.768 kHz, 9PF, SMD
1
Y2
TXC Corporation
8Y40072002
Crystal, 40 MHz, 8 pF, SMD
60
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Fine tuning of DC blocking capacitor
values for C31, C32, and C33 may be
required for optimal performance.
U3
68pF
1
RF1
VC1
6
3
RF2
VC2
4
2
GND
RFC
5
C33
RTC6608OSP
GND
R18
100k
68pF
Circuit configuration for BLE/2.4-GHz
COEX only. Iff eature is not being used
these components are not required.
GND
C34
100pF
GND
R19
100k
GND
C35
100pF
GND
A DC blocking capacitor is required. If
the antenna match contains a series
capacitor, this is suffi cient to meet the
requirement and thus C36 is not
required.
FL1
1
RF_BG
IN
OUT
3
GND
GND
2
4
U4
1
LBP
CP
5
3
HBP
GND
GND
GND
2
4
6
DEA202450BT-1294C1-H
GND
E1
Antenna match. Pi
network might be
required depending on
type of antenna.
C36
C37
8.2pF
2.2pF
3
2
1
68pF
5
4
C32
Feed 6
C31
RF_BLE
L4
3.9nH
DPX165950DT-8148A1
U5
A_RX
C41
A_TX
4.7pF
GND
RFC
5
3
RF2
VC2
4
RF1
VC1
6
1
4.7pF
FL2
C38
2
C40
1
1.6pF
C39
OUT
3
GND
2
GND
1.9pF
GND
GND
GND
L5
DEA165538BT-2236B1-H
2.7nH
GND
RTC6608OSP
GND
IN
GND
SOP0
SOP1
C42
100pF
GND
C43
100pF
GND
Figure 7-8. CC3135 RF Schematic Implementation With and Without Coexistence
NOTE
The Following guidelines are recommended for implementation of the RF design:
• Ensure an RF path is designed with an impedance of 50 Ω
• Tuning of the antenna impedance π matching network is recommended after manufacturing of the PCB to account for PCB parasitics
• π or L matching and tuning may be required between cascaded passive components on the RF path
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Table 7-2. Bill of Materials For CC3135 RF Section
Quantity
Designator
Value
Manufacturer
Part Number
Description
3
C31 (1), C32 (1),
C33 (1)
68 pF
Murata
GRM0335C1H680JA1D
CAP, CERM, 68 pF, 50 V, +/- 5%,
C0G/NP0, 0201
4
C34 (1), C35 (1), C42,
C43
100 pF
Yageo
CC0201JRNPO8BN101
CAP, CERM, 100 pF, 25 V, +/- 5%,
C0G/NP0, 0201
1
C36
8.2 pF
Walsin
0402N8R2C500CT
CAP, CERM, 8.2 pF, 50 V, +/- 3%,
C0G/NP0, 0402
1
C37
2.2 pF
MuRata
GJM1555C1H2R2BB01D
CAP, CERM, 2.2 pF, 50 V, +/- 4.5%,
C0G/NP0, 0402
1
C38
1.6 pF
MuRata
GRM0335C1H1R6BA01D
CAP, CERM, 1.6 pF, 50 V, +/- 7%,
C0G/NP0, 0201
1
C39
1.9 pF
MuRata
GJM1555C1H1R9WB01D
CAP, CERM, 1.9 pF, 50 V, +/- 2.6%,
C0G/NP0, 0402
2
C40, C41
4.7 pF
MuRata
GRM0335C1H4R7BA01D
CAP, CERM, 4.7 pF, 50 V, +/- 3%,
C0G/NP0, 0201
1
E1
Ethertronics
M830520
WLAN ANTENNA 802.11, SMD
1
FL1
TDK
DEA202450BT-1294C1-H
Multilayer Chip Band Pass Filter For
2.4GHz W-LAN/Bluetooth, SMD
1
FL2
TDK
DEA165538BT-2236B1-H
Multilayer Band Pass Filter For
5GHz W-LAN/LTE-U
1
L4
3.9 nH
MuRata
LQG15HS3N9S02D
Inductor, Multilayer, Air Core,
3.9 nH, 0.75 A, 0.14 ohm, SMD
1
L5
2.7 nH
MuRata
LQG15WH2N7C02D
Inductor, Multilayer, Air Core,
2.7 nH, 0.9 A, 0.07 ohm, AEC-Q200
Grade 1, SMD
2
R18 (1), R19 (1)
100k
Vishay-Dale
CRCW0402100KJNED
RES, 100 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
2
U3 (1), U5
Richwave
RTC6608OSP
0.03 GHz-6 GHz SPDT Switch
1
U4
TDK
DPX165950DT-8148A1
Multilayer Diplexer for 2.4 GHz
W-LAN & Bluetooth / 5 GHz W-LAN
(1)
62
If the BLE/2.4 GHz Coexistence features is not used, these components are not required.
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SWAS037 – FEBRUARY 2019
PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3135 VQFN device.
Follow these guidelines ensures that the design will minimize the risk with regulatory certifications
including FCC, ETSI, and CE. For more information, see CC3135 and CC3235 SimpleLink™ Wi-Fi® and
IoT Solution Layout Guidelines.
7.2.1
General PCB Guidelines
Use the following PCB guidelines:
• Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended
layers for signals and ground.
• Ensure that the VQFN PCB footprint follows the information in Section 9.
• Ensure that the VQFN PCB GND and solder paste follow the recommendations provided in CC3135
and CC3235 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.
• Decoupling capacitors must be as close as possible to the VQFN device.
7.2.2
Power Layout and Routing
Three critical DC/DC converters must be considered for the CC3135 device.
• Analog DC/DC converter
• PA DC/DC converter
• Digital DC/DC converter
Each converter requires an external inductor and capacitor that must be laid out with care. DC current
loops are formed when laying out the power components.
7.2.2.1
Design Considerations
The following design guidelines must be followed when laying out the CC3135 device:
• Ground returns of the input decoupling capacitors (C12, C14, and C21) should be routed on Layer 2
using thick traces to isolate the RF ground from the noisy supply ground. This step is also required to
meet the IEEE spectral mask specifications.
• Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power
amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).
• Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
• Place all decoupling capacitors as close to the respective pins as possible.
• Power budget—the CC3135 device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, for
24 ms during the calibration cycle.
• Ensure the power supply is designed to source this current without any issues. The complete
calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
• The CC3135 device contains many high-current input pins. Ensure the trace feeding these pins can
handle the following currents:
– VIN_DCDC_PA input (pin 39) maximum 1 A
– VIN_DCDC_ANA input (pin 37) maximum 600 mA
– VIN_DCDC_DIG input (pin 44) maximum 500 mA
– DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum 1 A
– DCDC_PA_OUT output node (pin 42) maximum 1 A
– DCDC_ANA_SW switching node (pin 38) maximum 600 mA
– DCDC_DIG_SW switching node (pin 43) maximum 500 mA
– VDD_PA_IN supply (pin 33) maximum 500 mA
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Figure 7-9 shows the ground routing for the input decoupling capacitors.
Figure 7-9. Ground Routing for Input Decoupling Capacitors
NOTE
The ground returns for the input capacitors are routed on layer two to reduce the EMI and
improve the spectral mask. This routing must be strictly followed because it is critical for the
overall performance of the device.
Pin 37
Ground
Traces
Pin 37
Pin 37
Figure 7-10. Ground Returns for Input Capacitors
64
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SWAS037 – FEBRUARY 2019
Clock Interface Guidelines
The following guidelines are for the slow clock:
• The 32.768-kHz crystal must be placed close to the VQFN package.
• Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance
within ±150 ppm.
• The ground plane on layer two is solid below the trace lanes, and there is ground around these traces
on the top layer.
The following guidelines are for the fast clock:
• The 40-MHz crystal must be placed close to the VQFN package.
• Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance
within ±10 ppm at room temperature. The total frequency across parts, temperature, and with aging
must be ±20 ppm to meet the WLAN specification.
• To avoid noise degradation, ensure that no high-frequency lines are routed close to the routing of the
crystal pins.
• Ensure that crystal tuning capacitors are close to the crystal pads.
• Both traces (XTAL_N and XTAL_P) should be as close as possible to parallel and approximately the
same length.
• The ground plane on layer two is solid below the trace lines, and there should be ground around these
traces on the top layer.
• For frequency tuning, see CC31xx & CC32xx Frequency Tuning.
7.2.4
Digital Input and Output Guidelines
The following guidelines are for the digital I/Os:
• Route SPI and UART lines away from any RF traces.
• Keep the length of the high-speed lines as short as possible to avoid transmission line effects.
• Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects (required
if the traces cannot be kept short). Place the resistor at the source end closer to the device that is
driving the signal.
• Add a series-terminating resistor for each high-speed line (for example, SPI_CLK or SPI_DATA) to
match the driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a
50-Ω line impedance.
• Route high-speed lines with a continuous ground reference plane below it to offer good impedance
throughout. This routing also helps shield the trace against EMI.
• Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple
locations, use a separate line driver for each line.
• If the lines are longer compared to the rise time, add series-terminating resistors near the driver for
each high-speed line to match the driver impedance to the line. Typical terminating-resistor values
range from 27 to 36 Ω for a 50-Ω line impedance.
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RF Interface Guidelines
The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific
antenna design guides (including placement of the antenna). Also see CC3135 and CC3235 SimpleLink™
Wi-Fi® and IoT Solution Layout Guidelines for general antenna guidelines.
• Ensure that the antenna is matched for 50-Ω. A π-matching network is recommended. Ensure that the
π pad is available for tuning the matching network after PCB manufacture.
• A DC blocking capacitor is required before the antenna. If the antenna matching network contains a
series capacitor, this is sufficient to meet the requirement.
• Ensure that the area underneath the BPFs pads have a solid plane on layer 2 and that the minimum
filter requirements are met.
• Ensure that the area underneath the RF switch pads have a solid plane on layer 2 and that the
minimum switch isolation requirements are met.
• Ensure that the area underneath the diplexer pads have a solid plane on layer 2 and that the minimum
diplexer requirements are met.
• Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.
• The RF trace bends must be made with gradual curves. Avoid 90-degree bends.
• The RF traces must not have sharp corners.
• There must be no traces or ground under the antenna section.
• The RF traces must have via stitching on the ground plane beside the RF trace on both sides.
• For optimal antenna performance, ensure adequate ground plane around the antenna on all layers.
• Ensure RF connectors for conducted testing are isolated from the top layer ground using vias.
• Maintain a controlled pad to trace shapes using filleted edges if necessary to avoid mismatch.
• Diplexers, switches, BPF, and other elements on the RF route should be isolated from the top layer
ground using vias.
66
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8 Device and Documentation Support
8.1
Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
8.2
Tools and Software
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed in this section.
For the most up-to-date list of development tools and software, see the CC3135 Tools & Software product
page. Users can also click the "Alert Me" button on the top right corner of the CC3135 Tools & Software
page to stay informed about updates related to the CC3135 device.
Development Tools
SimpleLink™ Wi-Fi® Starter Pro The supported devices are: CC3100, CC3200, CC3120R, CC3220x,
CC3135, and CC3235x.
The SimpleLink™ Wi-Fi® Starter Pro mobile App is a new mobile application for
SimpleLink™ provisioning. The app goes along with the embedded provisioning library and
example that runs on the device side (see SimpleLink™ Wi-Fi® SDK plugin and TI
SimpleLink™ CC32XX Software Development Kit (SDK)). The new provisioning release is a
TI recommendation for Wi-Fi provisioning using SimpleLink™ Wi-Fi® products. The
provisioning release implements advanced AP mode and SmartConfig™ technology
provisioning with feedback and fallback options to ensure successful process has been
accomplished. Customers can use both embedded library and the mobile library for
integration to their end products.
SimpleLink™ Wi-Fi® SDK plugin The CC3135 device is supported.
The CC3135 SDK contains drivers, many sample applications for Wi-Fi® features and
internet, and documentation needed to use the CC3135 Internet-on-a chip™ solution. This
SDK can be used with TI’s MSP432P401R LaunchPad™, or SimpleLink™ Studio, a PC tool
that allows MCU development with the CC3135 device. You can also use the SDK as
example code for any platform. All sample applications in the SDK are supported on TI’s
MSP432P401R ultra-low power MCUs with Code Composer Studio™ IDE and TI RTOS. In
addition, many of the applications support IAR.
SimpleLink™ Studio for CC31xx The CC31xx device is supported.
SimpleLink™ Studio for CC31xx is a Windows®-based software tool used to aid in the
development of embedded networking applications and software for microcontrollers. Using
SimpleLink™ Studio for CC31xx, embedded software developers can develop and test
applications using any desktop IDE, such as Visual Studio or Eclipse, and connect their
applications to the cloud using the CC31xx BoosterPack™ Plug-in Module. The application
can then be easily ported to any microcontroller. With the SimpleLink™ Wi-Fi® CC31xx
solution, customers now have the flexibility to add Wi-Fi® to any microcontroller (MCU). This
Internet-on-a-chip solution contains all you need to easily create IoT solutions: security, quick
connection, cloud support, and more. For more information on CC31xx devices, visit
SimpleLink™ Wi-Fi® solutions.
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SimpleLink™ Wi-Fi® Radio Testing Tool The supported devices are: CC3100, CC3200, CC3120R,
CC3220, CC3135 and CC3235x.
The SimpleLink™ Wi-Fi® Radio Testing Tool is a Windows-based software tool for RF
evaluation and testing of SimpleLink™ Wi-Fi® CC3x20 and CC3x35 designs during
development and certification. The tool enables low-level radio testing capabilities by
manually setting the radio into transmit or receive modes. Using the tool requires familiarity
and knowledge of radio circuit theory and radio test methods.
Created for the internet-of-things (IoT), the SimpleLink™ Wi-Fi® CC31xx and CC32xx family
of devices include on-chip Wi-Fi®, Internet, and robust security protocols with no prior Wi-Fi®
experience needed for faster development. For more information on these devices, visit
SimpleLink™ Wi-Fi® family, Internet-on-a chip™ solutions.
UniFlash Standalone Flash Tool for TI Microcontrollers (MCU), Sitara™ Processors and
SimpleLink™ Devices CCS UniFlash is a standalone tool used to program on-chip flash
memory on TI MCUs and on-board flash memory for Sitara™ processors. UniFlash has a
GUI, command line, and scripting interface. CCS UniFlash is available free of charge.
TI Designs and Reference Designs
The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jumpstart your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
8.3
Firmware Updates
TI updates features in the service pack for this module with no published schedule. Due to the ongoing
changes, TI recommends that the user has the latest service pack in their module for production.
To stay informed, click the SDK “Alert me” button the top right corner of the product page, or visit
SimpleLink™ Wi-Fi® SDK plugin.
8.4
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3135 device and support tools (see Figure 8-1).
X
CC
3
1
3
5
R
xx
xxx
x
PREFIX
X = Preproduction device
Null = Production device
PACKAGING
R = Large Reel
DEVICE FAMILY
CC = Wireless Connectivity
PACKAGE
RGK = 9 mm × 9 mm VQFN
SERIES NUMBER
3 = Wi-Fi Centric
MEMORY SIZE
NM = No Memory
MCU / HOST
1 = No MCU
2 = MCU
DEVICE GENERATION
0 = Gen 1
2 = Gen 2
3 = Gen 3
DEVICE VARIANTS
R = Default
FREQUENCY BAND
0 = 2.4 GHz only
5 = 2.4 GHz and 5 GHz supported
Figure 8-1. CC3135 Device Nomenclature
68
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SWAS037 – FEBRUARY 2019
Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (CC3135). In the upper right corner, click the "Alert me" button. This registers you to
receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document. The current documentation that describes the processor, related
peripherals, and other technical collateral follows.
The following documents provide support for the CC3135 device.
Application Reports
CC3135 and CC3235 SimpleLink™ Wi-Fi® Embedded Programming User Guide
CC3235 SimpleLink Wi-Fi Embedded Programming User Guide
CC3135
and
SimpleLink™ CC3135, CC3235 Wi-Fi® Internet-on-a chip™ Networking Sub-System Power
Management
This application report describes the best practices for power management and extended
battery life for embedded low-power Wi-Fi devices such as the SimpleLink Wi-Fi Internet-ona chip solution from Texas Instruments.
SimpleLink™ CC31xx, CC32xx Wi-Fi® Internet-on-a chip™ Solution Built-In Security Features The
SimpleLink Wi-Fi CC31xx and CC32xx Internet-on-a chip family of devices from Texas
Instruments offer a wide range of built-in security features to help developers address a
variety of security needs, which is achieved without any processing burden on the main
microcontroller (MCU). This document describes these security-related features and provides
recommendations for leveraging each in the context of practical system implementation.
SimpleLink™ CC3135, CC3235 Wi-Fi® and Internet-of-Things Over-the-Air Update This document
describes the OTA library for the SimpleLink Wi-Fi CC3x35 family of devices from Texas
Instruments and explains how to prepare a new cloud-ready update to be downloaded by the
OTA library.
SimpleLink™ CC3135, CC3235 Wi-Fi® Internet-on-a chip™ Solution Device Provisioning This guide
describes the provisioning process, which provides the SimpleLink Wi-Fi device with the
information (network name, password, and so forth) needed to connect to a wireless
network.
Transfer of TI's Wi-Fi® Alliance Certifications to Products Based on SimpleLink™ This document
explains how to employ the Wi-Fi® Alliance (WFA) derivative certification transfer policy to
transfer a WFA certification, already obtained by Texas Instruments, to a system you have
developed.
Using Serial Flash on SimpleLink™ CC3135 and CC3235 Wi-Fi® and Internet-of-Things Devices
This application note is divided into two parts. The first part provides important guidelines
and best- practice design techniques to consider when choosing and embedding a serial
Flash paired with the CC3135 and CC3235 (CC3x35) devices. The second part describes
the file system, along with guidelines and considerations for system designers working with
the CC3x35 devices.
Device and Documentation Support
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User's Guides
SimpleLink™ Wi-Fi® and Internet-of-Things CC31xx and CC32xx Network Processor This document
provides software (SW) programmers with all of the required knowledge for working with the
networking subsystem of the SimpleLink Wi-Fi devices. This guide provides basic guidelines
for writing robust, optimized networking host applications, and describes the capabilities of
the networking subsystem. The guide contains some example code snapshots, to give users
an idea of how to work with the host driver. More comprehensive code examples can be
found in the formal software development kit (SDK). This guide does not provide a detailed
description of the host driver APIs.
SimpleLink™ Wi-Fi® CC3135 and CC3235 and IoT Solution Layout Guidelines
This
document
provides the design guidelines of the 4-layer PCB used for the CC3135 and CC3235
SimpleLink Wi-Fi family of devices from Texas Instruments. The CC3135 and CC3235
devices are easy to lay out and are available in quad flat no-leads (QFNS) packages. When
designing the board, follow the suggestions in this document to optimize performance of the
board.
SimpleLink™ Wi-Fi® CC3135 BoosterPack™ Development Kit (BOOSTXL-CC3135) The SimpleLink
Wi-Fi CC3135 wireless network processor from Texas Instruments™ provides users the
flexibility to add Wi-Fi to any MCU. This user's guide explains the various configurations of
the CC3135 BoosterPack™ Plug-In Module.
SimpleLink™ Wi-Fi® and Internet-on-a chip™ CC3135 and CC3235 Solution Radio Tool The Radio
Tool serves as a control panel for direct access to the radio, and can be used for both the
radio frequency (RF) evaluation and for certification purposes. This guide describes how to
have the tool work seamlessly on Texas Instruments evaluation platforms such as the
BoosterPack plus FTDI emulation board for CC3235 devices, and the LaunchPad for
CC3235 devices.
SimpleLink™ Wi-Fi® CC3135 and CC3235 Provisioning for Mobile Applications This guide describes
TI’s SimpleLink Wi-Fi provisioning solution for mobile applications, specifically on the usage
of the Android™ and IOS® building blocks for UI requirements, networking, and provisioning
APIs required for building the mobile application.
More Literature
CC3x35 SimpleLink™ Wi-Fi® Hardware Design Checklist
CC3135 SimpleLink™ WI-Fi® BoosterPack™ Design Files
8.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7
Trademarks
Texas Instruments, SimpleLink, Internet-on-a chip, SmartConfig, LaunchPad, Code Composer Studio,
BoosterPack, Sitara, E2E are trademarks of Texas Instruments.
Arm, Cortex are registered trademarks of Arm Limited.
IOS is a registered trademark of Cisco.
Android is a trademark of Google LLC.
Windows is a registered trademark of Microsoft Inc.
WPA, WPA2 are trademarks of Wi-Fi Alliance.
Wi-Fi, Wi-Fi Alliance, Wi-Fi Direct are registered trademarks of Wi-Fi Alliance.
All other trademarks are the property of their respective owners.
70
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SWAS037 – FEBRUARY 2019
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
72
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9.1
Package Option Addendum
9.1.1
Packaging Information
Orderable Device
CC3135RNMRGKR
(1)
(2)
(3)
(4)
(5)
(6)
SWAS037 – FEBRUARY 2019
Status
(1)
ACTIVE
Packag
e Type
Package
Drawing
Pins
Package
Qty
VQFN
RGK
64
2500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/Ball Finish (3)
CU NIPDAU | CU
NIPDAUAG
MSL Peak Temp
(4)
Level-3-260C-168 HR
Op Temp (°C)
-40 to 85
Device Marking (5)
(6)
CC3135RNM
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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9.1.2
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Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
CC3135RNMRGKR
VQFN
RGK
64
2500
330.0
16.4
9.3
9.3
1.1
1.1 12.0
16.0
Q2
74
Mechanical, Packaging, and Orderable Information
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Product Folder Links: CC3135
Copyright © 2019, Texas Instruments Incorporated
CC3135
www.ti.com
SWAS037 – FEBRUARY 2019
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC3135RNMRGKR
VQFN
RGK
64
2500
367.0
367.0
38.0
Copyright © 2019, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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Product Folder Links: CC3135
75
PACKAGE OPTION ADDENDUM
www.ti.com
25-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
CC3135RNMRGKR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGK
64
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
CC3135R
NM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
RGK0064B
VQFN - 1 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
B
A
PIN 1 INDEX AREA
9.1
8.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 7.5
6.3 0.1
(0.2) TYP
SYMM
17
32
16
33
EXPOSED
THERMAL PAD
SYMM
65
2X 7.5
60X 0.5
PIN 1 ID
1
48
64
49
0.5
64X
0.3
64X
0.30
0.18
0.1
0.05
C A B
4222201/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGK0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 6.3)
SYMM
64X (0.6)
64
49
SEE SOLDER MASK
DETAIL
64X (0.24)
1
48
60X (0.5)
8X (1.1)
(R0.05) TYP
18X (1.2)
SYMM
(0.6) TYP
65
(8.8)
( 0.2) TYP
VIA
16
33
17
32
(0.6) TYP
8X
(1.1)
18X (1.2)
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4222201/B 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGK0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
64X (0.6)
(1.2) TYP
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.2) TYP
65
SYMM
(8.8)
16
METAL
TYP
33
17
32
SYMM
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4222201/B 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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