Texas Instruments | LMX9830 Bluetooth® Serial Port Module (Rev. C) | Datasheet | Texas Instruments LMX9830 Bluetooth® Serial Port Module (Rev. C) Datasheet

Texas Instruments LMX9830 Bluetooth® Serial Port Module (Rev. C) Datasheet
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LMX9830
SNOSAU0C – MAY 2008 – REVISED JUNE 2015
LMX9830 Bluetooth® Serial Port Module
1 Features
•
1
•
•
•
•
3 Description
®
Compliant With the Bluetooth 2.0 Core
Specification
– Qualified Design ID (PRD 2.0): B012364
Input Sensitivity Better than –80 dBm
Class 2 Operation
Low Power Consumption
High Integration:
– Implemented in 0.18-μm CMOS Technology
– RF Includes Antenna Filter and Switch OnChip
2 Applications
•
•
•
•
•
Personal Digital Assistants
POS Terminals
Data Logging Systems
Audio Gateway Applications
Telemedicine/Medical, Industrial and Scientific
The Texas Instruments LMX9830 Bluetooth Serial
Port module is a highly integrated Bluetooth 2.0
baseband controller and 2.4-GHz radio, combined to
form a complete small form factor (6.1 mm × 9.1 mm
× 1.2 mm) Bluetooth node.
All hardware and firmware is included to provide a
complete solution from antenna through the complete
lower and upper layers of the Bluetooth stack, up to
the application including the Generic Access Profile
(GAP), the Service Discovery Application Profile
(SDAP), and the Serial Port Profile (SPP). The
module includes a configurable service database to
fulfill service requests for additional profiles on the
host. Moreover, the LMX9830 is prequalified as a
Bluetooth Integrated Component. Conformance
testing through the Bluetooth qualification program.
The LMX9830 enables a short time to market after
system integration by ensuring a high probability of
compliance and interoperability.
Based on TI's CompactRISC 16-bit processor
architecture and Digital Smart Radio technology, the
LMX9830 is optimized to handle the data and link
management processing requirements of a Bluetooth
node.
Device Information(1)
PART NUMBER
LMX9830
PACKAGE
NFBGA (60)
BODY SIZE (NOM)
9.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMX9830
SNOSAU0C – MAY 2008 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Block Diagram........................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
5
5
5
6
6
6
7
7
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Supply Requirements ....................................
Digital DC Characteristics .........................................
RF Receiver Performance Characteristics................
RF Transmitter Performance Characteristics............
RF Synthesizer Performance Characteristics ...........
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
36
10 Application and Implementation........................ 41
10.1 Typical Application ................................................ 41
10.2 System Examples ................................................. 44
11 Power Supply Recommendations ..................... 47
11.1 Filtered Power Supply ........................................... 47
12 Device and Documentation Support ................. 50
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
50
50
13 Mechanical, Packaging, and Orderable
Information ........................................................... 50
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision A (April 2013) to Revision B
•
2
Page
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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6 Pin Configuration and Functions
NZB Package
60-Pin NFBGA
Top View
Pin Functions
PAD NAME
ANT
B_RESET_RA#
CTS#
(1)
ENV1#
GND
PAD LOCATION
TYPE
DEFAULT LAYOUT
D10
I/O
—
RF Antenna 50 Ω Nominal Impedance
DESCRIPTION
B6
O
NC
Buffered Reset Radio Output (active low)
C2
I
GND (if not used)
C6
I
NC
ENV1: Environment Select (active low) used for
manufacturing test only
Host Serial Port Clear To Send (active low)
B2,E2
—
—
Ground
GND_IF
D7
—
—
Ground
GND_RF
B9, C10, E10
—
—
Ground
E9
—
—
Ground
GND_VCO
MDODI
(2)
D1
I/O
—
SPI Master Out Slave In
A1,A2,A3
—
NC
Treat as no connect. Place pad for mechanical stability
D3
I
See Table 8 and
Table 9
OP3: Pin checked during Start-up Sequence for
configuration option
MWCS#: SPI Slave Select Input (active low)
D6
OP4: I
PG4: I/O
See Table 8 and
Table 9
OP4: Pin checked during Start-up Sequence for
configuration option
PG4: GPIO
F4
I/O
See Table 8 and
Table 9
OP5: Pin checked during Start-up Sequence for
configuration option
C1
OP6: I
SCL/MSK: I/O
See Table 8
OP6: Pin checked during Start-up Sequence for
configuration option
SCL: ACCESS.Bus Clock
MSK: SPI Shift
D4
OP7: I
SDA/MDIDO: I/O
See Table 8
OP7: Pin checked during Start-up Sequence for
configuration option
SDA: ACCESS.Bus Serial Data
MDIDO: SPI Master In Slave Out
PG6
A7
I/O
—
GPIO
PG7
D2
I/O
—
GPIO - Default setup RF traffic LED indication
NC
OP3/MWCS#
OP4/PG4
OP5
OP6/SCL/MSK
OP7/SDA/MDIDO
(1)
(2)
Connect to GND if CTS is not use.
Must use 1-kΩ pullup.
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Pin Functions (continued)
PAD LOCATION
TYPE
DEFAULT LAYOUT
RDY#
PAD NAME
A4
O
NC
DESCRIPTION
RESET_BB#
B7
I
RESET_RA#
B8
I
RTS# (3)
B1
O
NC (if not used)
RXD
B3
I
—
Host Serial Port Receive Data
SCLK
F1
I/O
—
Audio PCM Interface Clock
SFS
F2
I/O
—
Audio PCM Interface Frame Synchronization
JTAG Ready Output (active low)
Baseband Reset (active low)
Radio Reset (active low)
Host Serial Port Request To Send (active low)
SRD
F3
I
—
Audio PCM Interface Receive Data Input
STD
E3
O
—
Audio PCM Interface Transmit Data Output
TCK
B4
I
NC
JTAG Test Clock Input
TDI
B5
I
NC
JTAG Test Data Input
TDO
D5
O
NC
JTAG Test Data Output
TE
A9
I
GND
TMS
A5
I
NC
JTAG Test Mode Select Input
B10
I
NC
TST1: Test Mode. Leave not connected to permit use
with VTune automatic tuning algorithm
DIV2#: No longer supported
TST2
C7
I
GND
Test Mode, Connect to GND
TST3
C8
I
GND
Test Mode, Connect to GND
TST4
C9
I
GND
Test Mode, Connect to GND
TST5
D8
I
GND
Test Mode, Connect to GND
D9
I
VCO_OUT
TXD
C3
O
—
Host Serial Port Transmit Data
X1_CKI
E7
I
—
Crystal or External Clock 10-20 MHz
X1_CKO
F7
O
—
Crystal 10-20 MHz
F5
I
GND
(if not used)
32.768-kHz Crystal Oscillator
E5
O
NC
(if not used)
32.768-kHz Crystal Oscillator
A6
O
—
Clock Request. Toggles with X2 (LP0) crystal
enable/disable
TST1/DIV2#
TST6
X2_CKI
X2_CKO
XOSCEN
Test Enable - Used for manufacturing test only
Test Input,
Connect to VCO_OUT via 0-Ω resistor to permit use
with VTune automatic tuning algorithm
VCC
E1
I
—
Voltage Regulator Input
VCC_CORE
C5
O
—
1.8-V Voltage Regulator Output
VCC_IO
C4
I
—
Power Supply I/O
VCC_IOP
E4
I
—
Power Supply Audio Interface
VCC_PLL
F6
O
—
1.8-V Core Logic Power Supply Output
VCO_IN
F9
I
—
VCO Tuning Input, feedback from Loop filter
VCO_OUT
F8
O
—
Charge Pump Output, connect to Loop filter
VDD_IF
A8
I
—
Power Supply IF
VDD_IOR
E6
I
—
Power Supply I/O Radio/BB
VDD_RF
A10
I
—
Power Supply RF
VDD_VCO
F10
I
—
Power Supply VCO
VDD_X1
E8
I
—
Power Supply Crystal Oscillator
(3)
4
Treat as No Connect if RTS is not used. Pad required for mechanical stability.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
The following conditions are true unless otherwise stated in the tables: TA = -40°C to +85°C, VCC = 3.3 V, and RF system
performance specifications are ensured on Texas Instruments Mesa board rev 1.1 reference design platform.
MIN
MAX
VCC
Digital Voltage Regulator input
–0.2
4
UNIT
V
VI
Voltage on any pad with GND = 0 V
–0.2
VCC + 0.2
V
0.2
3.3
V
VDD_RF
VDD_IF
Supply Voltage Radio
VDD_X1
VDD_VCO
PINRF
RF Input Power
VANT
Applied Voltage to ANT pad
0
(2)
TL
Lead Temperature
TLNOPB
Lead Temperature NOPB (2) (3)(solder 40 sec.)
Tstg
Storage temperature
(1)
(2)
(3)
(solder 4 sec.)
–65
dBm
1.95
V
225
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Reference IPC/JDEC J-STD-20C spec.
NOPB = No Pb (No Lead)
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine model (MM)
±200 (3)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
A 200-V ESD rating applies to all pins except OP3, OP6, OP7, MDODI, SCLK, SFS, STD, TDO, and ANT pins = 150 V.
7.3 Recommended Operating Conditions
The following conditions are true unless otherwise stated in the tables: TA = –40°C to 85°C, VCC = 3.3 V, and RF system
performance specifications are ensured on Texas Instruments Mesa board rev 1.1 reference design platform.
VCC
Digital Voltage Regulator input
TR
Digital Voltage Regulator Rise Time
TA
Ambient Operating Temperature Range
MIN
TYP
MAX
2.5
2.75
3.6
UNIT
V
10
μs
–40
25
125
°C
1.6
3.3
3.6
V
Supply Voltage Radio
2.5
2.75
3
V
VDD_IOR
Supply Voltage Radio I/O
1.6
2.75
VDD_RF
V
VCC_IOP
Supply Voltage PCM Interface
1.6
3.3
3.6
V
VCC_CORE
Supply Voltage Output
VCC_COREMAX
Supply Voltage Output Max Load
VCC_CORESHORT
When used as Supply Input (VCC grounded)
Fully Functional Bluetooth Node
VCC_IO
Supply Voltage Digital I/O
VCC_PLL
Internally connected to VCC_Core
VDD_RF
VDD_IF
VDD_X1
VDD_VCO
1.8
V
5
1.6
1.8
mA
2
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7.4 Thermal Information
LMX9830
THERMAL METRIC (1)
NZB [NFBGA]
UNIT
60 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
51.0
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Power Supply Requirements (1) (2)
The following conditions are true unless otherwise stated in the tables: TA = –40°C to 85°C, VCC = 3.3 V, and RF system
performance specifications are ensured on Texas Instruments Mesa board rev 1.1 reference design platform.
PARAMETER
TYP (3)
MIN
MAX
UNIT
ICC-TX
Power supply current for continuous transmit
65
mA
ICC-RX
Power supply current for continuous receive
65
mA
IRXSL
Receive Data in SPP Link, Slave (4)
26
mA
IRXM
Receive Data in SPP Link, Master (4)
23
mA
ISnM
Sniff Mode, Sniff interval 1 second
(4)
5.6
mA
ISC-TLDIS
Scanning, No Active Link, TL Disabled (4)
0.43
mA
IIdle
Idle, Scanning Disabled, TL Disabled (4)
100
µA
(1)
(2)
(3)
(4)
Power supply requirements based on Class II output power.
Based on UART Baudrate 921.6 kbit/s.
VCC = 3.3 V, VCC_IO = 3.3 V, Ambient Temperature = 25°C.
Average values excluding IO.
7.6 Digital DC Characteristics
The following conditions are true unless otherwise stated in the tables: TA = –40°C to 85°C, VCC = 3.3 V, and RF system
performance specifications are ensured on Texas Instruments Mesa board rev 1.1 reference design platform.
MIN
MAX
VIH
Logical 1 Input Voltage high
(except oscillator I/O)
PARAMETER
1.6 V ≤ VCC_IO ≤ 3.0 V
3.0 V ≤ VCC_IO ≤ 3.6 V
TEST CONDITIONS
0.7 x VCC_IO
2
VCC_IO + 0.2
VCC_IO + 0.2
VIL
Logical 0 Input Voltage low
1.6 V ≤ VCC_IO ≤ 3.0 V
–0.2
0.25 x VCC_IO
(except oscillator I/O)
3.0 V ≤ VCC_IO ≤ 3.6 V
–0.2
0.8
UNIT
V
V
VHYS
Hysteresis Loop Width (1)
IOH
Logical 1 Output Current
VOH = 2.4 V, VCC_IO = 3.0 V
–10
mA
IOL
Logical 0 Output Current
VOH = 0.4 V, VCC_IO = 3.0 V
10
mA
(1)
6
0.1 x VCC_IO
V
Specified by design.
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7.7 RF Receiver Performance Characteristics
In the performance characteristics tables the following applies: All tests performed are based on Bluetooth Test Specification
revision 2.0. All tests are measured at antenna port unless otherwise specified. TA = –40°C to 85°C, VDD_RF = 2.8 V unless
otherwise specified. RF system performance specifications are ensured on Texas Instruments Mesa Board rev 1.1 reference
design platform.
PARAMETER
RXsense
Receive Sensitivity
PinRF
BER < 0.001
Return
Loss (3)
OOB
(1)
(2)
(3)
UNIT
2.402 GHz
–80
–76
dBm
2.441 GHz
–80
–76
dBm
2.480 GHz
–80
–76
dBm
F1= + 3 MHz,
F2= + 6 MHz,
PinRF = –64 dBm
Intermodulation Performance
ZRFIN (3)
MAX
Maximum Input Level
IMP (2) (3)
RSSI
TYP (1)
TEST CONDITIONS
RSSI Dynamic Range at LNA Input
MIN
–10
0
dBm
–38
–36
dBm
–72
–52
Single input impedance
Fin = 2.5 GHz
Input Impedance of RF Port (RF_inout)
Ω
32
Return Loss
–8
(2) (3)
Out Of Band Blocking Performance
dBm
dB
PinRF = –10 dBm,
30 MHz < FCWI < 2 GHz, BER < 0.001
–10
dBm
PinRF = –27 dBm,
2000 MHz < FCWI < 2399 MHz, BER <
0.001
–27
dBm
PinRF = –27 dBm,
2498 MHz < FCWI < 3000 MHz, BER <
0.001
–27
dBm
PinRF = –10 dBm,
3000 MHz < FCWI < 12.75 GHz, BER <
0.001
–10
dBm
Typical operating conditions are at 2.75 V operating voltage and 25°C ambient temperature.
The f0 = –64 dBm Bluetooth modulated signal, f1 = –39 dbm sine wave, f2 = –39 dBm Bluetooth modulated signal, f0 = 2f1 - f2, and |f2 f1| = n * 1 MHz, where n is 3, 4, or 5. For the typical case, n = 3.
Not tested in production.
7.8 RF Transmitter Performance Characteristics
In the performance characteristics tables the following applies: All tests performed are based on Bluetooth Test Specification
revision 2.0. All tests are measured at antenna port unless otherwise specified. TA = –40°C to 85°C, VDD_RF = 2.8 V unless
otherwise specified. RF system performance specifications are ensured on Texas Instruments Mesa Board rev 1.1 reference
design platform.
PARAMETER
MIN
TYP (1)
MAX
UNIT
2.402 GHz
−4
0
+3
dBm
2.441 GHz
−4
0
+3
dBm
TEST CONDITIONS
POUTRF
Transmit Output Power
−4
0
+3
dBm
MOD ΔF1AVG
Modulation Characteristics
Data = 00001111
140
165
175
kHz
MOD ΔF2MAX (2)
Modulation Characteristics
Data = 10101010
115
125
ΔF2AVG/DF1AVG (3)
Modulation Characteristics
2.480 GHz
kHz
20 dB Bandwidth
POUT2*fo (4)
ZRFOUT (5)
(1)
(2)
(3)
(4)
(5)
kHz
0.8
PA 2nd Harmonic Suppression
Maximum gain setting:
f0 = 2402 MHz,
Pout = 4804 MHz
RF Output Impedance/Input
Impedance of RF Port (RF_inout)
Pout @ 2.5 GHz
1000
kHz
-30
dBm
47
Ω
Typical operating conditions are at 2.75 V operating voltage and 25°C ambient temperature.
ΔF2max ≥ 115 kHz for at least 99.9% of all Δf2max.
Modulation index set between 0.28 and 0.35.
Out-of-Band spurs only exist at 2nd and 3rd harmonics of the CW frequency for each channel.
Not tested in production.
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7.9 RF Synthesizer Performance Characteristics
In the performance characteristics tables the following applies: All tests performed are based on Bluetooth Test Specification
revision 2.0. All tests are measured at antenna port unless otherwise specified. TA = –40°C to 85°C, VDD_RF = 2.8 V unless
otherwise specified. RF system performance specifications are ensured on Texas Instruments Mesa Board rev 1.1 reference
design platform.
PARAMETER
TEST CONDITIONS
MIN
TYP
2402
MAX
UNIT
2480
MHz
fVCO
VCO Frequency Range
tLOCK
Lock Time
f0 ± 20 kHz
Δf0offset (1)
Initial Carrier Frequency Tolerance
During preamble
-75
0
75
kHz
DH1 data packet
-25
0
25
kHz
DH3 data packet
-40
0
40
kHz
DH5 data packet
-40
0
40
kHz
Drift Rate
-20
0
20
kHz/50µs
Δf0drift (1)
Initial Carrier Frequency Drift
tD - TX
(1)
Transmitter Delay Time
From TX data to antenna
120
µs
4
µs
Frequency accuracy is dependent on crystal oscillator chosen. The crystal must have a cumulative accuracy of < ±20 ppm to meet
Bluetooth specifications.
7.10 Typical Characteristics
8
Figure 1. Modulation
Figure 2. Transmit Spectrum
Figure 3. Corresponding Eye Diagram
Figure 4. Synthesizer Phase Noise
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8 Parameter Measurement Information
Figure 5. Front-End Bandpass Filter Response
Figure 6. TX and RX Pin 50-Ω Impedance Characteristics
Figure 7. Transceiver Return Loss
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9 Detailed Description
9.1 Overview
LMX9830 is a highly compact Bluetooth 2.0 module solution, with integrated radio, controller, and processor. The
built-in Bluetooth stacks up to the application layer allows users to communicate directly with SPP commands,
and develop additional SPP-based Bluetooth profiles on Host through UART interface.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Feature Overview
The firmware supplied in the on-chip ROM memory offers a complete Bluetooth (v2.0) stack including profiles
and command interface. This firmware features point-to-point and point-to-multipoint link management supporting
data rates up to the theoretical maximum over RFComm of 704 kbps (Best in Class in the industry). The internal
memory supports up to 7 active Bluetooth data links and one active SCO link.
The on-chip Patch RAM provided for lowest cost and risk, allows the flexibility of a firmware upgrade.
The LMX9830 module is lead free and RoHS (Restriction of Hazardous Substances) compliant. For more
information
on
those
quality
standards,
visit
TI's
green
compliance
website
at
http://focus.ti.com/quality/docs/qualityhome.tsp
10
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Feature Description (continued)
9.3.1.1 Hardware
• Baseband and Link Management Processors
• CompactRISC Core
• Embedded ROM and Patch RAM Memory
• UART Command/Data Port:
– Support for up to 921.6 k Baud Rate
• Auxiliary Host Interface Ports:
– Link Status
– Transceiver Status (TX or RX)
– Three General Purpose I/Os, Available through the API
– Alternative IO Functions:
– Link Status
– Transport Layer Activity
• Advanced Power Management (APM) Features:
– Advanced Power Management functions
• Advanced Audio Interface for External PCM Codec
• ACCESS.Bus and SPI/Microwire for Interfacing with External Nonvolatile Memory
9.3.1.2 Firmware
• Complete Bluetooth Stack including:
– Baseband and Link Manager
– L2CAP, RFCOMM, SDP
– Profiles:
– GAP
– SDAP
– SPP
• Additional Profile support on Host, for example:
– Dial Up Networking (DUN)
– Facsimile Profile (FAX)
– File Transfer Protocol (FTP)
– Object Push Profile (OPP)
– Synchronization Profile (SYNC)
– Headset (HSP)
– Handsfree Profile (HFP)
– Basic Imaging Profile (BIP)
– Basic Printing Profile (BPP)
• On-Chip application including:
– Default connections
– Command Interface:
– Link setup and configuration (also Multipoint)
– Configuration of the module
– Service database modifications
– UART Transparent mode
– Optimized cable replacement :
– Automatic transparent mode
– Event filter
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Feature Description (continued)
9.3.1.3 Highly Integrated Digital Technology
• Accepts external clock or crystal input:
– 13 MHz Typical
– Supports 10 - 20 MHz
– Secondary 32.768-kHz oscillator for low-power modes
– 20 ppm cumulative clock error required for Bluetooth
• Synthesizer:
– Integrated VCO
– Provides all clocking for radio and baseband functions
• Antenna Port (50 Ω nominal impedance):
– Embedded front-end filter for enhanced out of band performance
• Integrated transmit/receive switch (full duplex operation via antenna port)
• Better than –80 dBm input sensitivity
• 0 dBm typical output power
9.3.1.4 Physical
• Compact size - 6.1 mm × 9.1 mm × 1.2 mm
• Complete system interface provided in Ball Grid Array on underside for surface mount assembly
9.3.2 Baseband and Link Management Processors
Baseband and Lower Link control functions are implemented using a combination of TI's CompactRISC 16-bit
processor and the Bluetooth Lower Link Controller. These processors operate from integrated ROM memory and
RAM and execute on-board firmware implementing all Bluetooth functions.
9.3.2.1 Bluetooth Lower Link Controller
The integrated Bluetooth Lower Link Controller (LLC) complies with the Bluetooth Specification version 2.0 and
implements the following functions:
• Adaptive Frequency Hopping
• Interlaced Scanning
• Fast Connect
• Support for 1, 3, and 5 slot packet types
• 79 Channel hop frequency generation circuitry
• Fast frequency hopping at 1600 hops per second
• Power management control
• Access code correlation and slot timing recovery
9.3.2.2 Bluetooth Upper Layer Stack
The integrated upper layer stack is prequalified and includes the following protocol layers:
• L2CAP
• RFComm
• SDP
9.3.2.3 Profile Support
The on-chip application of the LMX9830 allows full stand-alone operation, without any Bluetooth protocol layer
necessary outside the module. It supports the Generic Access Profile (GAP), the Service Discovery Application
Profile (SDAP), and the Serial Port Profile (SPP).
The on-chip profiles can be used as interfaces to additional profiles executed on the host. The LMX9830 includes
a configurable service database to answer requests with the profiles supported.
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Feature Description (continued)
9.3.2.4 Application With Command Interface
The module supports automatic slave operation eliminating the need for an external control unit. The
implemented transparent option enables the chip to handle incoming data raw, without the need for packaging in
a special format. The device uses a pin to block unallowed connections. This pincode can be fixed or
dynamically set.
Acting as master, the application offers a simple but versatile command interface for standard Bluetooth
operation-like inquiry, service discovery, or serial port connection. The firmware supports up to seven slaves.
Default Link Policy settings and a specific master mode allow optimized configuration for the application specific
requirements. See also Integrated Firmware.
9.3.2.5 Memory
The LMX9830 introduces 16 kB of combined system and Patch RAM memory that can be used for data and/or
code upgrades of the ROM based firmware. Due to the flexible start-up used for the LMX9830 operating
parameters like the Bluetooth Device Address (BD_ADDR) are defined during boot time. This allows reading out
the parameters of an external EEPROM or programming them directly over UART.
9.3.2.6 External Memory Interfaces
As the LMX9830 is a ROM based device with no on-chip non volatile storage, the operation parameters will be
lost after a power cycle or hardware reset. In order to prevent re initializing such parameters, patches or even
user data, the LMX9830 offers two interfaces to connect an external EEPROM to the device:
• μ-wire/SPI
• Access.bus (I2C compatible)
The selection of the interface is done during start-up based on the option pins. See Table 8 for the option pin
descriptions.
9.3.2.7 µ-wire/SPI Interface
In case the firmware is configured by the option pins to use a µ-wire/SPI EEPROM, the LMX9830 will activate
that interface and try to read out data from the EEPROM. The external memory must be compatible to the
reference listed in Table 1. The largest size EEPROM supported is limited by the addressing format of the
selected NVM.
The device must have a page size equal to N x 32 bytes.
The firmware requires that the EEPROM supports Page write. Clock must be HIGH when idle.
Table 1. M95640-S EEPROM 8k x 8
PARAMETER
VALUE
Supplier
ST Microelectronics
Supply Voltage (1)
1.8 - 3.6 V
Interface
SPI compatible (positive clock SPI Modes)
Memory Size
Clock Rate
(1)
Access
(1)
8k x 8, 64 kbit
2 MHz
Byte and Page Write (up to 32 bytes)
Parameter range reduced to requirements of TI reference design.
9.3.2.8 Access.bus Interface
In case the firmware is configured by the option pins to use an access.bus or I2C compatible EEPROM, the
LMX9830 will activate that interface and try to read out data from the EEPROM. The external memory must be
compatible to the reference listed in Table 2.
The largest size EEPROM supported is limited by the addressing format of the selected NVM. The device must
have a page size equal to N x 32 bytes.
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The device uses a 16 bit address format. The device address must be “000”.
Table 2. 24C64 EEPROM 8kx8
PARAMETER
VALUE
Supplier
Atmel
Supply Voltage (1)
2.7 - 5.5 V
Interface
2 wire serial interface
Memory Size
8K x 8, 64 kbit
Clock Rate (1)
100 kHz
Access
32 Byte Page Write Mode
(1)
Parameter range reduced to requirements of TI reference design.
9.3.3 Transport Port - UART
The LMX9830 provides one Universal Asynchronous Receiver Transmitter (UART). The UART interface consists
out of Receive (RX), Transmit (TX), Ready-to-Send (RTS) and Clear-to-Send signals. RTS and CTS are used for
hardware handshaking between the host and the LMX9830. Because the LMX9830 acts as gateway between the
Bluetooth and the UART interface, TI recommends to use the handshaking signals especially for transparent
operation. In case two signals are used CTS must be pulled to GND. Also see the LMX9830 Software User’s
Guide for detailed information on 2-wire operation.
The UART interface supports formats of 8-bit data with or without parity, with one or two stop bits. It can operate
at standard baud rates from 2400 bits/s up to a maximum baud rate of 921.6 kbits/s. DMA transfers are
supported to allow for fast processor independent receive and transmit operation.
The UART baudrate is configured during start-up by checking option pins OP3, OP4 and OP5 for reference clock
and baudrate. In case Auto baud rate detect is chosen, the firmware check the NVS area if a valid UART
baudrate has been stored in a previous session. In case, no useful value can be found the device will switch to
auto baud rate detection and wait for an incoming reference signal.
The UART offers wakeup from the power save modes via the multi-input wakeup module. When the LMX9830 is
in low power mode, RTS# and CTS# can function as Host_WakeUp and Bluetooth_WakeUp respectively.
Table 3 represents the operational modes supported by the firmware for implementing the transport via the
UART.
Table 3. UART Operation Modes
ITEM
Baud Rate
RANGE
DEFAULT AT POWER UP
WITH AUTO-DETECT
2.4 to 921.6 kbits/s
Either configured by option pins, NVS
parameter or auto baud rate detection
2.4 to 921.6 kbits/s
Flow Control
RTS#/CTS# or None
RTS#/CTS#
RTS#/CTS#
Parity
Odd, Even, None
None
None
Stop Bits
1,2
1
1
Data Bits
8
8
8
9.3.4 Audio Port
9.3.4.1 Advanced Audio Interface
The Advanced Audio Interface (AAI) is an advanced version of the Synchronous Serial Interface (SSI) that
provides a full-duplex communications port to a variety of industry-standard 13/14/15/16-bit linear or 8-bit log
PCM codecs, DSPs, and other serial audio devices.
The interface allows the support one codec or interface. The firmware selects the desired audio path and
interface configuration by a parameter that is located in RAM (imported from nonvolatile storage or programmed
during boot-up). The audio path options include the Motorola MC145483 codec, the OKI MSM7717 codec, the
Winbond W681360/W681310 codecs and the PCM slave through the AAI.
In case an external codec or DSP is used the LMX9830 audio interface generates the necessary bit and frame
clock driving the interface.
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Table 4 summarizes the audio path selection and the configuration of the audio interface at the specific modes.
The LMX9830 supports one SCO link.
Table 4. Audio Path Configuration
AUDIO SETTING
INTERFACE
FREQ
Advanced audio
interface
OKI MSM7717
Motorola MC145483 (2)
Advanced audio
interface
OKI MSM7717
Advanced audio
interface
ANY
(1)
13 MHz
FORMAT
AAI BIT
CLOCK
AAI FRAME
CLOCK
AAI FRAME
SYNC PULSE
LENGTH
8-bit log PCM
(a-law only)
480 kHz
8 kHz
14 Bits
13-bit linear
480 kHz
8 kHz
13 Bits
8-bit log PCM
(a-law only)
520 kHz
8 kHz
14 Bits
13-bit linear
520 kHz
8 kHz
13 Bits
Motorola MC145483 (2)
Advanced audio
interface
Winbond W681310
Advanced audio
interface
13 MHz
8 bit log PCM
A-law and μ-law
520 kHz
8 kHz
14 Bits
Winbond W681360
Advanced audio
interface
13 MHz
13-bit linear
520 kHz
8 kHz
13 Bits
PCM slave (3)
Advanced audio
interface
ANY (1)
8/16 bits
128 - 1024 kHz
8 kHz
8/16 Bits
(1)
(2)
(3)
For supported frequencies see Table 12.
Due to internal clock divider limitations the optimum of 512 kHz, 8 kHz can not be reached. The values are set to the best possible
values. The clock mismatch does not result in any discernible loss in audio quality.
In PCM slave mode, parameters are stored in NVS. Bit clock and frame clock must be generated by the host interface.
PCM slave configuration example: PCM slave uses the slot 0, 1 slot per frame, 16 bit linear mode, long frame
sync, normal frame sync. In this case, 0x03E0 should be stored in NVS. See “LMX9830 Software Users Guide”
for more details.
9.3.5 Auxiliary Ports
9.3.5.1 RESET#
There are two reset inputs: RESET_RA# for the radio and RESET_BB# for the baseband. Both are active low.
There is also a reset output, B_RESET_RA# (Buffered Radio Reset) active low. This output follows input
RESET_RA#.
When RESET_RA# is released, going high, B_RESET_RA# stays low until the clock has started.
See System Power-Up for details.
9.3.5.2 General Purpose I/Os
The LMX9830 offers 3 pins which either can be used as indication and configuration pins or can be used for
General Purpose functionality. The selection is made out of settings derived out of the power-up sequence.
In General Purpose configuration the pins are controlled hardware specific commands giving the ability to set the
direction, set them to high or low or enable a weak pullup.
In alternate function the pins have predefined indication functionality. See Table 5 for a description on the
alternate indication functionality.
Table 5. Alternate GPIO Pin Configuration
PIN
DESCRIPTION
OP4/PG4
Operation Mode pin to configure Transport Layer settings during boot-up
PG6
GPIO
PG7
RF Traffic indication
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9.3.6 System Power Up
In order to correctly power up the LMX9830, the following sequence is recommended to be performed:
Apply VCC_IO and VCC to the LMX9830.
The RESET_RA# should be driven high. Then RESET_BB# should be driven high at a recommended time of 1
ms after the LMX9830 voltage rails are high. The LMX9830 is properly reset.
See Figure 8.
ESR of the crystal also has impact on the start-up time of the crystal oscillator circuit of the LMX9830 (See
Table 6 and Table 7).
Figure 8. LMX9830 Power-On Reset Timing
Table 6. LMX9830 Power to Reset Timing
SYMBOL
tPTORRA
tPTORBB
(1)
(2)
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Power to Reset _RA#
VCC and VCC_IO at operating voltage
level to valid reset
<500 (1)
µs
Reset_RA# to Reset_BB#
VCC and VCC_IO at operating voltage
level to valid reset
1 (2)
ms
Rise time on power must switch on fast, rise time <500 µs.
Recommended value.
Table 7. ESR vs Start-up Time
(1)
(2)
16
ESR (Ω)
TYPICAL (1) (2)
UNIT
10
12
ms
25
13
ms
40
16
ms
50
24
ms
80
30
ms
Frequency, loading caps and ESR all must be considered for determining start-up time.
For reference only, must be tested on each system to accurately design POR and correctly start up system.
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9.3.7 Start-up Sequence
During start-up, the LMX9830 checks the options register pins OP3 to OP7 for configuration on operation mode,
external clock source, transport layer and available nonvolatile storage PROM.
The different options for start-up are described in Table 8.
9.3.7.1 Options Register
External pads in Table 8 are latched in this register at the end of Reset. The Options register can be read by
firmware at any time.
All pads are inputs with weak on-chip pullup/down resistors during Reset. Resistors are disconnected at the end
of RESET_BB#.
1 = Pullup resistor connected in application
0 = Pulldown resistor connected in application
x = Don’t care
9.3.7.2 Start-up With External PROM Available
To be able to read out information from an external PROM the option pins must be set according to Table 8.
Start-up sequence activities:
1. From the Options registers OP6 and OP7, the LMX9830 checks if a serial PROM is available to use
(ACCESS.bus or Microwire).
2. If serial PROM is available, the permanent parameter block, patch block, and nonvolatile storage (NVS) are
read from it. If the BD Address is not present, enter the BD address to be saved in the NVS. For more
information see Configuring the LMX9830 Through Transport Layer.
3. From the Options register OP3, OP4 and OP5, the LMX9830 checks for clocking information and transport
layer settings. If the NVS information are not sufficient, the LMX9830 will send the “Await Initialization” event
on the TL (Transport Layer) and wait for additional information (see Start-up Without External PROM
Available.)
4. The LMX9830 compensates the UART for new BBCLK information from the NVS.
5. The LMX9830 starts up the Bluetooth core.
9.3.7.3 Start-up Without External PROM Available
The following sequence will take place if OP6 and OP7 have been set to “No external memory” as described in
Table 8.
Start-up sequence activities:
1. From the Options registers OP6 and OP7, the LMX9830 checks if a serial PROM is available to use.
2. From the Options register OP3, OP4 and OP5, the LMX9830 checks for clocking mode and transport layer.
3. The LMX9830 sends the “Await Initialization” Event on the TL (Transport Layer) and waits for NVS
configuration commands. The configuration is finalized by sending the “Enter Bluetooth Mode” command.
4. The LMX9830 compensates the UART for new BBCLK information from the NVS.
5. The LMX9830 starts up the Bluetooth core.
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Table 8. Start-up Sequence Options (1)
PACKAGE PAD
(1)
(2)
(3)
COMMENT
OP3
OP4
OP5
OP6 (2)
OP7 (3)
ENV1#
PD
PD
PD
PD
PD
PU
x
x
x
Open (0)
Open (0)
Open (1)
BBCLK
No serial memory
x
x
x
1
Open (0)
Open (1)
BBCLK
Reserved
x
x
x
Open (0)
1
Open (1)
BBCLK
Microwire serial memory
x
x
x
1
1
Open (1)
BBCLK
ACCESS.bus serial memory
T_SCLK
x
x
T_RFDATA
T_RFCE
0 BBCLK
Test mode
PD = Internal Pulldown during Reset
PU = Internal Pullup during Reset
1/0 pullup/down resistor connected in application.
If OP6 is 1, must use 1-kΩ pullup, If OP6 is 0, must use 10-kΩ pulldown.
If OP7 is 1, must use 1-kΩ pullup.
Figure 9. Flow Diagram for the Start-Up Sequence
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Table 9. Fixed Frequencies
(1)
(2)
(3)
(4)
OSC FREQ.
(MHz)
BBCLK (MHz)
PLL (48 MHz)
OP3 (1)
OP4 (2)
OP5 (3)
12
12
OFF
0
0
0
UART speed read from NVS
10-20 (4)
10-20 (1)
ON
0
1
0
Clock and UART baudrate
detection
13
13
OFF
1
0
0
UART speed read from NVS
13
13
OFF
1
0
1
UART speed 9.6 kbps
13
13
OFF
1
1
0
UART speed 115.2 kbps
13
13
OFF
1
1
1
UART speed 921.6 kbps
FUNCTION
If OP3 is 1, must use 1-kΩ pullup.
If OP4 is 1, must use 1-kΩ pullup.
If OP5 is 1, must use 1-kΩ pullup.
Supported frequencies see Table 13.
9.3.7.4 Configuring the LMX9830 Through Transport Layer
As described in System Power-Up, the LMX9830 will check during start-up the Options Registers if an external
PROM is available. If the information on the PROM are incomplete or no PROM is installed the LMX9830 will
boot into the “initialization Mode”.
The mode is confirmed by the “Await Initialization” Event.
The following information are needed to enter Bluetooth Mode:
• Bluetooth Device Address (BD_Addr)
• External clock source (only if 10 - 20 MHz has been selected)
• UART Baudrate (only if Auto baudrate detection has been selected)
In general the following procedure will initialize the LMX9830:
1. Wait for “Await initialization” Event
– Event will only appear if transport layer speed is set or after successful baudrate detection.
2. Send “Set Clock and Baudrate” Command only if the clock speed is not known through hardware
configuration (i.e only if OP3, OP4, OP5 = 0 1 0).
3. Send “Write BD_Addr” to Configure Local Bluetooth Device Address.
4. Send “Enter Bluetooth Mode”
– LMX9830 will use configured clock and UART speed and start the command interface.
Note: In case no EEPROM is used, BDAddr, clock source and Baudrate are only valid until the next power-cycle
or hardware reset.
9.3.7.5 Auto Baud Rate Detection
The LMX9830 supports an Automatic Baudrate Detection in case the external clock is different to 12, 13 MHz or
the range 10-20 MHz or the baudrate is different to 9.6 kbps, 115.2 or 921.6 kbit/s.
The baudrate detection is based on the measurement of one character. The following issues need to be
considered:
• The flow control pin CTS must be low or else the host is in flow stop.
• The Auto Baudrate Detector measures the length of the 0x01 character from the positive edge of bit 0 to the
positive edge of stop bit.
• Therefore the very first received character must always be a 0x01.
• The host can restrict itself to send only a 0x01 character or also can send a command.
• The host must flush the TX buffer within 50-100 milliseconds depend on clock frequency on the host
controller.
• After 50-100 milliseconds the UART is about to be initialized and short after the host should receive a “Await
Initialization” Event or an “Command Status” Event.
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Figure 10. Auto Baudrate Detection Timing Diagram
9.3.8 Using an External EEPROM for Nonvolatile Data
The LMX9830 offers two interfaces to connect to external memory. Depending on the EEPROM used, the
interface is activated by setting the correct option pins during start-up. See Table 8 for the option pin settings.
The external memory is used to store mandatory parameters like the BD_Address as well as many optional
parameters like Link Keys or even User data.
The NVM is organized with fixed addresses for the parameters. Because of that the EEPROM can be
preprogrammed with default parameters in manufacturing. Refer to Table 36 for the organization of the NVS
map.
In case the external memory is empty on first start-up, the LMX9830 will behave as like no memory is connected.
(See Start-up Without External PROM Available). During the start-up process, parameters can be written directly
to the EEPROM to be available after next bootup. On first bootup, the EEPROM will be automatically
programmed to default values, including the UART speed of 9600 BPS. Patches supplied over the TL will be
stored automatically into the EEPROM.
9.3.9 Integrated Firmware
The LMX9830 includes the full Bluetooth stack up to RFComm to support the following profiles:
• GAP (Generic Access Profile)
• SDAP (Service Discovery Application Profile)
• SPP (Serial Port Profile)
Figure 11 shows the Bluetooth protocol stack with command interpreter interface. The command interpreter
offers a number of different commands to support the functionality given by the different profiles. Execution and
interface timing is handled by the control application.
The chip has an internal data area in RAM that includes the parameters shown in Table 36.
Figure 11. LMX9830 Software Implementation
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9.3.10 Digital Smart Radio
9.3.10.1 Functional Description
The integrated Digital Smart Radio uses a heterodyne receiver architecture with a low intermediate frequency (2
MHz) such that the intermediate frequency filters can be integrated on chip. The receiver consists of a low-noise
amplifier (LNA) followed by two mixers. The intermediate frequency signal processing blocks consist of a polyphase bandpass filter (BPF), two hard-limiters (LIM), a frequency discriminator (DET), and a post-detection filter
(PDF). The received signal level is detected by a received signal strength indicator (RSSI).
The received frequency equals the local oscillator frequency (fLO) plus the intermediate frequency (fIF):
fRF = fLO + fIF (supradyne).
The radio includes a synthesizer consisting of a phase detector, a charge pump, an (off-chip) loop-filter, an RFfrequency divider, and a voltage controlled oscillator (VCO).
The transmitter uses IQ-modulation with bit-stream data that is gaussian filtered. Other blocks included in the
transmitter are a VCO buffer and a power amplifier (PA).
9.3.10.2 Receiver Front-End
The receiver front-end consists of a low-noise amplifier (LNA) followed by two mixers and two low-pass filters for
the I- and Q-channels.
The intermediate frequency (IF) part of the receiver front-end consists of two IF amplifiers that receive input
signals from the mixers, delivering balanced I- and Q-signals to the poly-phase bandpass filter. The poly-phase
bandpass filter is directly followed by two hard-limiters that together generate an AD-converted RSSI signal.
9.3.10.2.1 Poly-Phase Bandpass Filter
The purpose of the IF bandpass filter is to reject noise and spurious (mainly adjacent channel) interference that
would otherwise enter the hard limiting stage. In addition, it takes care of the image rejection.
The bandpass filter uses both the I- and Q-signals from the mixers. The out-of-band suppression should be
higher than 40 dB (f<1 MHz, f>3 MHz). The bandpass filter is tuned over process spread and temperature
variations by the autotuner circuitry. A 5th order Butterworth filter is used.
9.3.10.2.2 Hard-Limiter and RSSI
The I- and Q-outputs of the bandpass filter are each followed by a hard-limiter. The hard-limiter has its own
reference current. The RSSI (Received Signal Strength Indicator) measures the level of the RF input signal.
The RSSI is generated by piece-wise linear approximation of the level of the RF signal. The RSSI has a mV/dB
scale, and an analog-to-digital converter for processing by the baseband circuit. The input RF power is converted
to a 5-bit value. The RSSI value is then proportional to the input power (in dBm).
The digital output from the ADC is sampled on the BPKTCTL signal low-to-high transition.
9.3.10.3 Receiver Back-End
The hard-limiters are followed by a two frequency discriminators. The I-frequency discriminator uses the 90×
phase-shifted signal from the Q-path, while the Q-discriminator uses the 90× phase-shifted signal from the I-path.
A poly-phase bandpass filter performs the required phase shifting. The output signals of the I- and Qdiscriminator are substracted and filtered by a low-pass filter. An equalizer is added to improve the eye-pattern
for 101010 patterns.
After equalization, a dynamic AFC (automatic frequency offset compensation) circuit and slicer extract the
RX_DATA from the analog data pattern. It is expected that the Eb/No of the demodulator is approximately 17 dB.
9.3.10.3.1 Frequency Discriminator
The frequency discriminator gets its input signals from the limiter. A defined signal level (independent of the
power supply voltage) is needed to obtain the input signal. Both inputs of the frequency discriminator have
limiting circuits to optimize performance. The bandpass filter in the frequency discriminator is tuned by the
autotuning circuitry.
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9.3.10.3.2 Post-Detection Filter and Equalizer
The output signals of the FM discriminator first go through a post-detection filter and then through an equalizer.
Both the post-detection filter and equalizer are tuned to the proper frequency by the autotuning circuitry. The
post-detection filter is a low-pass filter intended to suppress all remaining spurious signals, such as the second
harmonic (4 MHz) from the FM detector and noise generated after the limiter.
The post-detection filter also helps for attenuating the first adjacent channel signal. The equalizer improves the
eye-opening for 101010 patterns. The post-detection filter is a third order Butterworth filter.
9.3.10.4 Autotuning Circuitry
The autotuning circuitry is used for tuning the bandpass filter, the detector, the post-detection filter, the equalizer,
and the transmit filters for process and temperature variations. The circuit also includes an offset compensation
for the FM detector.
9.3.10.5 Synthesizer
The synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a programmable
frequency divider, a voltage-controlled oscillator (VCO), a delta-sigma modulator, and a lookup table.
The frequency divider consists of a divide-by-2 circuit (divides the 5 GHz signal from the VCO down to 2.5 GHz),
a divide-by-8-or-9 divider, and a digital modulus control. The delta-sigma modulator controls the division ratio and
also generates an input channel value to the lookup table.
9.3.10.5.1 Phase-Frequency Detector
The phase-frequency detector is a 5-state phase-detector. It responds only to transitions, hence phase-error is
independent of input waveform duty cycle or amplitude variations. Loop lockup occurs when all the negative
transitions on the inputs, F_REF and F_MOD, coincide. Both outputs (that is, Up and Down) then remain high.
This is equal to the zero error mode. The phase-frequency detector input frequency range operates at 12 MHz.
9.3.10.6 Transmitter Circuitry
The transmitter consists of ROM tables, two Digital to Analog (DA) converters, two low-pass filters, IQ mixers,
and a power amplifier (PA).
The ROM tables generate a digital IQ signal based on the transmit data. The output of the ROM tables is
inserted into IQ-DA converters and filtered through two low-pass filters. The two signal components are mixed up
to 2.5 GHz by the TX mixers and added together before being inserted into the transmit PA.
9.3.10.6.1 IQ-DA Converters and TX Mixers
The ROM output signals drive an I- and a Q-DA converter. Two Butterworth low-pass filters filter the DA output
signals. The 6-MHz clock for the DA converters and the logic circuitry around the ROM tables are derived from
the autotuner.
The TX mixers mix the balanced I- and Q-signals up to 2.4-2.5 GHz. The output signals of the I- and Q-mixers
are summed.
9.3.10.7 Crystal Requirements
The LMX9830 contains a crystal driver circuit. This circuit operates with an external crystal and capacitors to
form an oscillator. shows the recommended crystal circuit. Table 13 specifies system clock requirements.
The RF local oscillator and internal digital clocks for the LMX9830 is derived from the reference clock at the
CLK+ input. This reference may either come from an external clock or a dedicated crystal oscillator. The crystal
oscillator connections require an Xtal and two grounded capacitors.
It is also important to consider board and design dependant capacitance in tuning crystal circuit. Equations that
follow allow a close approximation of crystal tuning capacitance required, but actual values on board will vary
with capacitive properties of the board. As a result, some fine tuning of crystal circuit that must be done that
cannot be calculated; tuning must be done by testing different values of load capacitance.
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Many different crystals can be used with the LMX9830. Key requirements from Bluetooth specification is + 20
ppm. Additionally, ESR (Equivalent Series Resistance) must be carefully considered. LMX9830 can support
maximum of 230 Ω ESR, but it is recommended to stay <100 Ω ESR for best performance over voltage and
temperature. Reference Figure 17 for ESR as part of crystal circuit for more information.
9.3.10.7.1 Crystal
The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors. The
resonant frequency may be trimmed with the crystal load capacitance.
1. Load Capacitance: For resonance at the correct frequency, the crystal should be loaded with its specified
load capacitance, which is the value of capacitance used in conjunction with the crystal unit. Load
capacitance is a parameter specified by the crystal, typically expressed in pF. The crystal circuit shown in
Figure 13 is composed of:
– C1 (motional capacitance)
– R1 (motional resistance)
– L1 (motional inductance)
– C0 (static or shunt capacitance)
The LMX9830 provides some of the load with internal capacitors Cint. The remainder must come from the
external capacitors and tuning capacitors labeled Ct1 and Ct2 as shown in Figure 12. Ct1 and Ct2 should
have the same the value for best noise performance. The LMX9830 has an additional internal capacitance
CTUNE of 2.6 pF. Crystal load capacitance (CL) is calculated as the following:
CL = Cint + CTUNE + Ct1//Ct2
(1)
The CL above does not include the crystal internal self-capacitance C0 as shown in Figure 13, so the total
capacitance is:
Ctotal = CL + C0
(2)
Based on crystal spec and equation:
CL = Cint + CTUNE + Ct1//Ct2
CL = 8 pF + 2.6 pF + 6 pF = 16.6 pF
(3)
(4)
16.6 pF is very close to the TEW crystal requirement of 16 pF load capacitance. With the internal shunt
capacitance Ctotal:
Ctotal = 16.6 pF + 5 pF = 21.6 pF
(5)
2. Crystal Pullability: Pullability is another important parameter for a crystal, which is the change in frequency of
a crystal with units of ppm/pF, either from the natural resonant frequency to a load resonant frequency, or
from one load resonant frequency to another. The frequency can be pulled in a parallel resonant circuit by
changing the value of load capacitance. A decrease in load capacitance causes an increase in frequency,
and an increase in load capacitance causes a decrease in frequency.
3. Frequency Tuning: Frequency Tuning is achieved by adjusting the crystal load capacitance with external
capacitors. It is a Bluetooth requirement that the frequency is always within ±20 ppm. Crystal/oscillator must
have cumulative accuracy specifications of ±15 ppm to provide margin for frequency drift with aging and
temperature.
TEW Crystal: The LMX9830 has been tested with the TEW TAS-4025A crystal, reference Table 10 for
specification. Because the internal capacitance of the crystal circuit is 8 pF and the load capacitance is 16
pF, 12 pF is a good starting point for both Ct1 and Ct2. The 2480-MHz RF frequency offset is then tested.
Figure 14 shows the RF frequency offset test results.
Figure 14 shows the results are –20 kHz off the center frequency, which is –1 ppm. The pullability of the
crystal is 2 ppm/pF, so the load capacitance must be decreased by about 1.0 pF. By changing Ct1 or Ct2 to
10 pF, the total load capacitance is decreased by 1.0 pF. Figure 15 shows the frequency offset test results.
The frequency offset is now zero with Ct1 = 10 pF, Ct2 = 10 pF.
Reference Table 11 for crystal tuning values used on Mesa Development Board with TEW crystal.
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Figure 12. LMX9830 Crystal Recommended Circuit
Figure 13. Crystal Equivalent Circuit
Table 10. TEW TAS-4025A
SPECIFICATION
VALUE
Package
4.0 × 2.5 × 0.65 mm - 4 pads
Frequency
13.000 MHz
Mode
Fundamental
Stability
> ±15 ppm @ –40 to +85°C
CL Load Capacitance
16 pF
ESR
80 Ω max.
C0 Shunt Capacitance
5 pF
Drive Level
50 ±10 µV
Pullability
2 ppm/pF min
Storage Temperature
–40 to 85°C
Table 11. TEW on LMX9830 DONGLE
24
REFERENCE
LMX9830
Ct1
12 pF
Ct2
12 pF
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Figure 14. Frequency Offset with 12 pF//12 pF Capacitors
Figure 15. Frequency Offset with 10 pF//10 pF Capacitors
9.3.10.7.2 TCXO (Temperature Compensated Crystal Oscillator)
The LMX9830 also can operate with an external TCXO (Temperature Compensated Crystal Oscillator). The
TCXO signal is directly connected to the CLK+.
• Input Impedance: The LMX9830 CLK+ pin has in input impedance of 2 pF capacitance in parallel with >400
kW resistance.
9.3.10.7.3 Optional 32-kHz Oscillator
A second oscillator is provided (see Figure 16) that is tuned to provide optimum performance and low-power
consumption while operating with a 32.768-kHz crystal. An external crystal clock network is required between the
X2_CKI clock input and the X2_CKO clock output signals. The oscillator is built in a Pierce configuration and
uses two external capacitors. Table 12 provides the oscillator’s specifications.
In case the 32 kHz is not used, it is recommended to leave X2_CKO open and connect X2_CKI to GND.
Figure 16. 32.768-kHz Oscillator
Table 12. 32.768-kHz Oscillator Specifications
PARAMETER
VDD
Supply Voltage
IDDACT
Supply Current (Active)
f
Nominal Output Frequency
VPPOSC
Oscillating Amplitude
TEST CONDITIONS
MIN
TYP
MAX
1.62
1.8
1.98
40%
V
2
µA
32.768
kHz
1.8
Duty Cycle
UNIT
V
60%
—
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9.3.10.7.4 ESR (Equivalent Series Resistance)
LMX9830 can operate with a wide range of crystals with different ESR ratings. Reference Table 13 and
Figure 17 for more details.
Table 13. System Clock Requirements
MIN
TYP
MAX
UNIT
External Reference Clock Frequency (1)
PARAMETER
10
13
20
MHz
Frequency Tolerance (over full operating temperature and aging)
-20
±15
20
ppm
Crystal Serial Resistance
External Reference Clock Power Swing, pk to pk
100
200
Aging
(1)
230
Ω
400
mV
±1
ppm per year
Supported frequencies from external oscillator (in MHz): 10.00, 10.368, 12.00, 12.60, 12.80, 13.00, 13.824, 14.40, 15.36, 16.00, 16.20,
16.80, 19.20, 19.68, 19.80
Figure 17. ESR vs Load Capacitance for the Crystal Circuit
9.3.10.7.5 Antenna Matching and Front-End Filtering
Figure 18 shows the recommended component layout to be used between RF output and antenna input. Allows
for versatility in the design such that the match to the antenna maybe improved and/or the blocking margin
increased by addition of a LC filter. Refer to antenna application note for further details.
Figure 18. Front End Layout
26
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9.3.10.7.6 Loop Filter Design
The LMX9830 has an external loop filter which must be designed for best performance by the end customer.
This section therefore gives some foresight into its design. Refer also to Loop Filter application note and TI's
Webench on-line design tool for more information.
9.3.10.7.6.1 Component Calculations
The following parameters are required for component value calculation of a third order passive loop filter.
Φ
Phase Margin: Phase of the open loop transfer function
Fc
Loop Bandwidth
Fcomp
Comparison Frequency: Phase detector frequency
KVOC
VCO gain: Sensitivity of the VCO to control volts
KΦ
Charge Pump gain: Magnitude of the alternating current during lock
FOUT
Maximum RF output frequency
T31
Ratio of the poles T3 to T1 in a 3rd order filter
γ
Gamma optimization parameter
The third order loop filter being defined has the following topology. shown in Figure 19.
Figure 19. Third Order Loop Filter
N=
Fout
and ZC = 2SFC
Fcomp
(6)
Calculate the poles and zeros. Use exact method to solve for T1 using numerical methods,
I = tan
-1
J
§
· tan-1(ZC À T1)tan-1(ZC À T1 À T31)
©ZC À T1 À T1 + T31 ¹
T3 = T31 u T1
T2 =
(7)
J
ZC
2
À
(T1 + T3)
(8)
Calculate the loop filter coefficients,
2
KIÀ KVCO
A0 =
ZC
2
À
N
1 + ZC
À
(1 + ZC
2
À
À
2
T2
2
2
T1 )(1 + ZC
À
2
T3 )
|
A1 = A0 À (T1 + T3)
A2 = A0 À T1 À T3
(9)
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Summary:
SYMBOL
DESCRIPTION
n
UNIT
N counter value
None
Loop Bandwidth
rad/s
T1
Loop filter pole
S
T2
Loop filter zero
S
T3
Loop filter zero
S
A0
Total capacitance
nF
A1
First order loop filter coefficient
nFs
A2
Second order loop filter coefficient
nFs2
Components can then be calculated from loop filter coefficients
A2
2
T2
C1 =
C3 =
À
1 À T2
R2 =
§ T2 À A0 T2 À A1 ·
¸
A2
©
¹
1+¨
(1 +
2
À
T2
C2
(10)
2
C1 + T2 À A1 À C1 A2 À A0
2
T2 À C1 A2
R3 =
C2 = A0 C1 C3
(11)
A2
C1 À C3 À T2
(12)
Some typical values for the LMX9830 are:
Table 14. Typical Values
DESCRIPTION
VALUE
UNIT
Comparison Frequency
13
MHz
Phase Margin
48
Pl rad
Loop bandwidth
100
kHz
T3 over T1 ratio
40%
Gamma
1.0
VCO gain
120
MHz per V
Charge pump gain
0.6
mA
Fout
2441
MHz
Which give the following component values:
Table 15. Component Values
DESCRIPTION
VALUE
UNIT
C1
0.17
nF
C2
2.38
nF
C3
0.04
nF
R2
1737
Ω
R3
7025
Ω
9.3.10.7.6.2 Phase Noise and Lock-Time Calculations
Phase noise has three sources, the VCO, crystal oscillator and the rest of the PLL consisting of the phase
detector, dividers, charge pump and loop filter. Assuming the VCO and crystal are very low noise, it is possible to
put down approximate equations that govern the phase noise of the PLL.
Phase noise (in-band) = PN1Hz + 20Log[N] + 10Log[Fcomp]
where
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•
PH1Hz is the PLL normalized noise floor in 1 Hz resolution bandwidth
(13)
Further out from the carrier, the phase noise will be affected by the loop filter roll-off and hence its bandwidth.
As a rule-of-thumb;
ΔPhase noise = 40Log[ΔFc]
where
•
Fc is the relative change in loop BW expressed as a fraction
(14)
For example if the loop bandwidth is reduced from 100 kHz to 50 kHz or by one half, then the change in phase
noise will be -12dB. Loop BW in reality should be selected to meet the lower limit of the modulation deviation,
this will yield the best possible phase noise.
Even further out from the carrier, the phase noise will be mainly dominated by the VCO noise assuming the
crystal is relatively clean.
Lock-time is dependent on three factors, the loop bandwidth, the maximum frequency jump that the PLL must
make and the final tolerance to which the frequency must settle. As a rule-of-thumb it is given by:
LT =
400
(1 log10'F)
FC
Where 'F =
Frequency tolerance
Frequency jump
(15)
These equations are approximations of the ones used by Webench to calculate phase noise and lock-time.
9.3.10.7.6.3 Practical Optimization
In an example where frequency drift and drift rate can be improved though loop filter tweaks, consider the results
taken below. The drift rate is 26.1 kHz per 50 μs and the maximum drift is 25 kHz for DH1 packets, both of which
are exceeding or touching the Bluetooth pass limits. These measurements are taken with component values
shown in Table 15.
Table 16. Loop Filter Optimization Example – Before Optimization
TRM/CA/09/C (CARRIER DRIFT
HOPPONG ON- LOW CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs
26.1 kHz
N/A
−30.5 kHz
±20 kHz
Max Drift
25 kHz
N/A
36 kHz
DHI: ±25 kHz
Average Drift
−1 kHz
N/A
12 kHz
DH3: ±40 kHz
Packets Tested
10
N/A
10
D5I: ±40 kHz
Packets Failed
2
N/A
10
Overall Result
Failed
N/A
Failed
Results in Table 17 were taken on the same board with three loop filter values changed. C2 and R2 have been
increased in value and C1 has been reduced. The drift rate has improved by 13 kHz per 50 µs and the maximum
drift has improved by 10 kHz.
Table 17. Loop Filter Optimization Example – After Optimization
TRM/CA/09/C (CARRIER DRIFT
HOPPONG ON- LOW CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs
−13.6 kHz
N/A
−15.6 kHz
±20 kHz
Max Drift
15 kHz
N/A
21 kHz
DHI: ±25 kHz
Average Drift
3 kHz
N/A
1 kHz
DH3: ±40 kHz
Packets Tested
10
N/A
10
D5I: ±40 kHz
Packets Failed
0
N/A
0
Overall Result
Passed
N/A
Passed
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The effect of changing these three components is to reduce the loop bandwidth which reduces the phase noise.
The reduction in this noise level corresponds directly to the reduction of noise in the payload area where drift is
measured. This noise reduction comes at the expense of lock-time which can be increased to 120 µs without
suffering any ill effects, however if we continue to reduce the loop BW further the lock-time will increase such that
the PLL does not have time to lock before data transmission and the drift will again increase. Before the locktime goes out of spec, the modulation index will start to fall because it is being cut by the reducing loop BW.
Therefore, a compromise must be found between lock-time, phase noise and modulation, which yields best
performance.
Note: The values shown in the LMX9830 data sheet, are the best case optimized values that have been shown
to produce the best overall results and are recommended as a starting point for this design.
Another example of how the loop filter values can affect frequency drift rate, these results below show the DUT
with maximum drift on mid and high channels failing. Adjusting the loop bandwidth as shown provides the
improvement required to pass qualification.
Table 18. Original Results
HOPPONG ON- LOW CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs15.00
15.00 kHz
−28.10 kHz
−19.10 kHz
±20 kHz
Maximum Drift
19 kHz
−37 kHz
−20 kHz
DHI: ±25 kHz
Average Drift
11 kHz
−32 kHz
−10 kHz
DH3: ±40 kHz
Packets Tested
10
10
10
D5I: ±40 kHz
Packets Failed
0
1
0
Result
Pass
Fail
Pass
HOPPONG ON- MED CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs
15.00 kHz
−28.10 kHz
−19.10 kHz
±20 kHz
Max Drift
19 kHz
−37 kHz
−20kHz
DHI: ±25 kHz
Average Drift
11 kHz
−32 kHz
−10 kHz
DH3: ±40 kHz
Packets Tested
10
10
10
D5I: ±40 kHz
Packets Failed
0
1
0
Overall Result
Pass
Fail
Pass
HOPPONG ON- HIGH CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs
15.00 kHz
−28.10 kHz
−19.10 kHz
±20 kHz
Max Drift
19 kHz
−37 kHz
−20kHz
DHI: ±25 kHz
Average Drift
11 kHz
−32 kHz
−10 kHz
DH3: ±40 kHz
Packets Tested
10
10
10
D5I: ±40 kHz
Packets Failed
0
1
0
Overall Result
Pass
30
Fail
Pass
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Table 19. New Results
HOPPONG ON- LOW CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs
−12.00 kHz
−15.10 kHz
18.8 kHz
±20 kHz
Max Drift
−15 kHz
−35 kHz
−19 kHz
DHI: ±25 kHz
Average Drift
−6 kHz
−25 kHz
−9 kHz
DH3: ±40 kHz
Packets Tested
10
10
10
D5I: ±40 kHz
Packets Failed
0
0
0
Overall Result
Pass
Pass
Pass
HOPPONG ON- MED CHANNEL
DH1
DH3
DH5
LIMITS
Drift Rate/50 μs
−14.20 kHz
−16.10kHz
17.20 kHz
±20 kHz
Max Drift
−16 kHz
−354 kHz
−22 kHz
DHI: ±25 kHz
Average Drift
−11kHz
−27 kHz
−9 kHz
DH3: ±40 kHz
Packets Tested
10
10
10
D5I: ±40 kHz
Packets Failed
0
0
0
Overall Result
Pass
Pass
Pass
HOPPONG ON- HIGH CHANNEL
DH1
Drift Rate/50 μs
−12.70 kHz
Max Drift
−23 kHz
Average Drift
−12 kHz
Packets Tested
10
Packets Failed
0
Overall Result
Pass
DH3
DH5
−17.40 kHz
LIMITS
16.50 kHz
±20 kHz
−29 kHz
−25 kHz
DHI: ±25 kHz
−25 kHz
−16 kHz
DH3: ±40 kHz
10
10
D5I: ±40 kHz
0
0
Pass
Pass
9.3.10.7.6.4 Component Values for NSC Reference Designs
Table 20 shows a list of components for the loop filter values used on TI's reference design, (Serial Dongle) they
have been tweaked and optimized in each case to yield optimum performance for each case. The values differ
slightly from one platform to another due to board paracitics caused by layout differences.
Table 20. Components for Loop Filter Values
PLATFORM
C8
C7
C9
R23
R14
LMX9830 Dongle
220 pF
2200 pF
39 pF
3.3 k
10 k
9.3.11 Command Interface
The LMX9830 offers Bluetooth functionality in either a self contained slave functionality or over a simple
command interface. The interface is listening on the UART interface.
The following sections describe the protocol transported on the UART interface between the LMX9830 and the
host in command mode (see Figure 20). In Transparent mode, no data framing is necessary and the device does
not listen for commands.
9.3.11.1 Framing
The connection is considered “Error free”. But for packet recognition and synchronization, some framing is used.
All packets sent in both directions are constructed per the model shown in Table 21.
9.3.11.1.1 Start and End Delimiter
The “STX” char is used as start delimiter: STX = 0x02. ETX = 0x03 is used as end delimiter.
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9.3.11.1.2 Packet Type ID
This byte identifies the type of packet. See Table 22 for details.
9.3.11.1.3 Opcode
The opcode identifies the command to execute. The opcode values can be found within the “LMX9830 Software
User’s Guide” included within the LMX9830 Evaluation Board.
9.3.11.1.4 Data Length
Number of bytes in the Packet Data field. The maximum size is defined with 333 data bytes per packet.
9.3.11.1.5 Checksum:
This is a simple Block Check Character (BCC) checksum of the bytes “Packet type”, “Opcode” and “Data
Length”. The BCC checksum is calculated as low byte of the sum of all bytes (, if the sum of all bytes is 0x3724,
the checksum is 0x24).
Figure 20. Bluetooth Functionality
Table 21. Package Framing
START
DELIMITER
1 Byte
PACKET
TYPE ID
OPCODE
DATA LENGTH
CHECK SUM
PACKET DATA
END
DELIMITER
1 Byte
1 Byte
2 Bytes
1 Byte
<Data Length> Bytes
1 Byte
- - - - - - - - - - - - - Checksum - - - - - - - - - - - - -
Table 22. Packet Type Identification
ID
DIRECTION
DESCRIPTION
0x52
'R'
REQUEST
(REQ)
A request sent to the Bluetooth module.
All requests are answered by exactly one confirm.
0x43
'C'
Confirm
(CFM)
The Bluetooth modules confirm to a request.
All requests are answered by exactly one confirm.
0x69
'i'
Indication
(IND)
Information sent from the Bluetooth module that is not a direct confirm to a request.
Indicating status changes, incoming links, or unrequested events.
0x72
'r'
Response
(RES)
An optional response to an indication.
This is used to respond to some type of indication message.
9.3.11.2 Command Set Overview
The LMX9830 has a well defined command set to:
• Configure the device:
– Hardware settings
– Local Bluetooth parameters
– Service database
• Set up and handle links
Table 23 through Table 33 show the actual command set and the events coming back from the device. A full
documented description of the commands can be found in the “LMX9830 Software User’s Guide”.
Note: For standard Bluetooth operation only commands from Table 23 through Table 25 will be used. Most of the
remaining commands are for configuration purposes only.
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Table 23. Device Discovery
COMMAND
Inquiry
Remote Device Name
EVENT
DESCRIPTION
Inquiry Complete
Search for devices
Device Found
Lists BDADDR and class of device
Remote Device Name Confirm
Get name of remote device
Table 24. SDAP Client Commands
COMMAND
EVENT
DESCRIPTION
SDAP Connect
SDAP Connect Confirm
Create an SDP connection to remote device
SDAP Disconnect
SDAP Disconnect Confirm
Disconnect an active SDAP link
Connection Lost
Notification for lost SDAP link
SDAP Service Browse
Service Browse Confirm
Get the services of the remote device
SDAP Service Search
SDAP Service Search Confirm
Search a specific service on a remote device
SDAP Attribute Request
SDAP Attribute Request Confirm
Searches for services with specific attributes
Table 25. SPP Link Establishment
COMMAND
EVENT
Establish SPP Link
DESCRIPTION
Establishing SPP Link Confirm
Initiates link establishment to a remote device
Link Established
Link successfully established
Incoming Link
A remote device established a link to the local device
Set Link Timeout
Set Link Timeout Confirm
Confirms the Supervision Timeout for the existing Link
Get Link Timeout
Get Link Timeout Confirm
Get the Supervision Timeout for the existing Link
Release SPP Link
Release SPP Link Confirm
Initiate release of SPP link
SPP Send Data
SPP Send Data Confirm
Send data to specific SPP port
Incoming Data
Incoming data from remote device
Transparent Mode Confirm
Switch to Transparent mode on the UART
Transparent Mode
Table 26. Storing Default Connections
COMMAND
EVENT
DESCRIPTION
Connect Default Connection
Connect Default Connection Confirm
Connects to either one or all stored default connections
Store Default Connection
Store Default Connection Confirm
Store device as default connection
Get list of Default Connections
List of Default Devices
Delete Default Connections
Delete Default Connections Confirm
Table 27. Bluetooth Low Power Modes
COMMAND
Set Default Link Policy
EVENT
DESCRIPTION
Set Default Link Policy Confirm
Defines the link policy used for any incoming or outgoing
link
Get Default Link Policy
Get Default Link Policy Confirm
Returns the stored default link policy
Set Link Policy
Set Link Policy Confirm
Defines the modes allowed for a specific link
Get Link Policy
Get Link Policy Confirm
Returns the actual link policy for the link
Enter Sniff Mode
Enter Sniff Mode Confirm
Exit Sniff Mode
Exit Sniff Mode Confirm
Enter Hold Mode
Enter Hold Mode Confirm
Power Save Mode Changed
Remote device changed power save mode on the link
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Table 28. Audio Control Commands
COMMAND
Establish SCO Link
EVENT
DESCRIPTION
Establish SCO Link Confirm
Establish SCO Link on existing RFComm Link
SCO Link Established Indicator
A remote device has established a SCO link to the local
device
Release SCO Link Confirm
Release SCO Link Audio Control
SCO Link Released Indicator
SCO Link has been released
Change SCO Packet Type Confirm
Changes Packet Type for existing SCO link
SCO Packet Type changed indicator
SCO Packet Type has been changed
Set Audio Settings
Set Audio Settings Confirm
Set Audio Settings for existing Link
Get Audio Settings
Get Audio Settings Confirm
Get Audio Settings for existing Link
Set Volume
Set Volume Confirm
Configure the volume
Get Volume
Get Volume Confirm
Get current volume setting
Mute
Mute Confirm
Mutes the microphone input
Release SCO Link
Change SCO Packet Type
Table 29. Wakeup Functionality
COMMAND
Disable Transport Layer
EVENT
Transport Layer Enabled
DESCRIPTION
Disabling the UART Transport Layer and activates the
Hardware Wakeup function
Table 30. SPP Port Configuration and Status
COMMAND
EVENT
DESCRIPTION
Set Port Config
Set Port Config Confirm
Set port setting for the virtual serial port link over the air
Get Port Config
Get Port Config Confirm
Read the actual port settings for a virtual serial port
Port Config Changed
Notification if port settings were changed from remote
device
SPP Get Port Status
SPP Get Port Status Confirm
Returns status of DTR, RTS (for the active RFComm link)
SPP Port Set DTR
SPP Port Set DTR Confirm
Sets the DTR bit on the specified link
SPP Port Set RTS
SPP Port Set RTS Confirm
Sets the RTS bit on the specified link
SPP Port BREAK
SPP Port BREAK
Indicates that the host has detected a break
SPP Port Overrun Error
SPP Port Overrun Error Confirm
Used to indicate that the host has detected an overrun error
SPP Port Parity Error
SPP Port Parity Error Confirm
Host has detected a parity error
SPP Port Framing Error
SPP Port Framing Error Confirm
Host has detected a framing error
SPP Port Status Changed
Indicates that remote device has changed one of the port
status bits
Table 31. Local Bluetooth Settings
COMMAND
EVENT
DESCRIPTION
Read Local Name
Read Local Name Confirm
Read actual friendly name of the device
Write Local Name
Write Local Name Confirm
Set the friendly name of the device
Read Local BDADDR
Read Local BDADDR Confirm
Change Local BDADDR
Change Local BDADDR Confirm
Note: The BDADDR must be obtained from the IEEE
organization. See http://standarts.ieee.org/regauth/oui/
Store Class of Device
Store Class of Device Confirm
Set Scan Mode
Set Scan Mode Confirm
Change mode for discoverability and connectability
Set Scan Mode Indication
Reports end of Automatic limited discoverable mode
Get Fixed Pin
Get Fixed Pin Confirm
Reads current PinCode stored within the device
Set Fixed Pin
Set Fixed Pin Confirm
Set the local PinCode
PIN request
A PIN code is requested during authentication of an ACL
link
Get Security Mode Confirm
Get actual Security mode
Get Security Mode
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Table 31. Local Bluetooth Settings (continued)
COMMAND
EVENT
DESCRIPTION
Set Security Mode
Set Security Mode Confirm
Configure Security mode for local device (default 2)
Remove Pairing
Remove Pairing Confirm
Remove pairing with a remote device
List of Paired Devices
Get list of paired devices stored in the LMX9830 data
memory
Set Default Link Timeout
Set Default Link Timeout Confirm
Store default link supervision timeout
Get Default Link Timeout
Get Default Link Timeout Confirm
Get stored default link supervision timeout
Force Master Role Confirm
Enables/Disables the request for master role at incoming
connections
List Paired Devices
Force Master Role
Table 32. Local Service Database Configuration
COMMAND
EVENT
DESCRIPTION
Store generic SDP Record
Store SDP Record Confirm
Create a new service record within the service database
Enable SDP Record
Enable SDP Record Confirm
Enable or disable SDP records
Delete All SDP Records
Delete All SDP Records Confirm
Ports to Open
Ports to Open Confirmed
Specify the RFComm Ports to open on start-up
Table 33. Local Hardware Commands
COMMAND
Get Default Audio Settings
EVENT
DESCRIPTION
Get Default Audio Settings Confirm
Get stored Default Audio Settings
Set Default Audio Settings Confirm
Configure Default Settings for Audio Codec and Air Format,
stored in NVS
Set Event Filter
Set Event Filter Confirm
Configures the reporting level of the command interface
Get Event Filter
Get Event Filter Confirm
Get the status of the reporting level
Read RSSI
Read RSSI Confirm
Returns an indicator for the incoming signal strength
Change UART Speed
Change UART Speed Confirm
Set specific UART speed; needs proper ISEL pin setting
Change UART Settings
Change UART Settings Confirm
Change configuration for parity and stop bits
Test Mode
Test Mode Confirm
Enable Bluetooth, EMI test, or local loopback
Restore Factory Settings
Restore Factory Settings Confirm
Reset
Dongle Ready
Set Default Audio Settings
Soft reset
Firmware Upgrade
Stops the Bluetooth firmware and executes the In-systemprogramming code
Set Clock Frequency
Set Clock Frequency Confirm
Write Clock Frequency setting in the NVS
Get Clock Frequency
Get Clock Frequency Confirm
Read Clock Frequency setting from the NVS
Set PCM Slave Configuration
Set PCM Slave Configuration Confirm Write the PCM Slave Configuration in the NVS
Write ROM Patch
Write ROM Patch Confirm
Store ROM Patch in the SimplyBlue module
Read Memory
Read Memory Confirm
Read from the internal RAM
Write Memory
Write Memory Confirm
Write to the internal RAM
Read NVS
Read NVS Confirm
Read from the NVS (EEPROM)
Write NVS
Write NVS Confirm
Write to the NVS (EEPROM)
Table 34. Initialization Commands
COMMAND
EVENT
DESCRIPTION
Set Clock and Baudrate
Set Clock and Baudrate Confirm
Write Baseband frequency and Baudrate used
Enter Bluetooth Mode
Enter Bluetooth Mode Confirm
Request SimplyBlue module to enter BT mode
Set Clock and Baudrate
Set Clock and Baudrate Confirm
Write Baseband frequency and Baudrate used
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Table 35. GPIO Control Commands
COMMAND
EVENT
DESCRIPTION
Set GPIO WPU
Set GPIO WPU Confirm
Enable/Disable weak pullup resistor on GPIOs
Get GPIO Input State
Get GPIO Input States Confirm
Read the status of the GPIOs
Set GPIO Direction
Set GPIO Direction Confirm
Set the GPIOs direction (Input, Ouput)
Set GPIO Output High
Set GPIO Output High Confirm
Set GPIOs Output to logical High
Set GPIO Output Low
Set GPIO Output Low Confirm
Set GPIOs Output to logical Low
9.4 Device Functional Modes
9.4.1 Operation Modes
On boot-up, the application configures the module following the parameters in the data area.
9.4.1.1 Automatic Operation
9.4.1.1.1 No Default Connections Stored
In Automatic Operation the module is connectable and discoverable and automatically answers to service
requests. The command interpreter listens to commands and links can be set up. The full command list is
supported.
If connected by another device, the module sends an event back to the host, where the RFComm port has been
connected, and switches to transparent mode.
9.4.1.1.2 Default Connections Stored
If default connections were stored on a previous session, once the LMX9830 is reset, it will attempt to connect
each device stored within the data RAM three times. The host will be notified about the success of the link setup
via a link status event.
9.4.1.1.3 Nonautomatic Operation
In Nonautomatic Operation, the LMX9830 does not check the default connections section within the Data RAM. If
connected by another device, it will NOT switch to transparent mode and continue to interpret data sent on the
UART.
9.4.1.1.4 Transparent Mode
The LMX9830 supports transparent data communication from the UART interface to a Bluetooth link.
If activated, the module does not interpret the commands on the UART which normally are used to configure and
control the module. The packages don’t need to be formatted as described in Table 21. Instead all data are
directly passed through the firmware to the active Bluetooth link and the remote device.
Transparent mode can only be supported on a point-to-point connection. To leave Transparent mode, the host
must send a UART_BREAK signal to the module.
9.4.1.1.5 Force Master Mode
In Force Master mode tries to act like an Accesspoint for multiple connections. For this it will only accept the link
if a Master/slave role switch is accepted by the connecting device. After successful link establishment the
LMX9830 will be Master and available for additional incoming links. On the first incoming link the LMX9830 will
switch to transparent depending on the setting for automatic or command mode. Additional links will only be
possible if the device is not in transparent mode.
9.4.2 Default Connections
The LMX9830 supports the storage of up to 3 devices within its NVS. Those connections can either be
connected after reset or on demand using a specific command.
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Device Functional Modes (continued)
9.4.3 Event Filter
The LMX9830 uses events or indicators to notify the host about successful commands or changes at the
Bluetooth interface. Depending on the application the LMX9830 can be configured. The following levels are
defined:
• No Events:
– The LMX9830 is not reporting any events. Optimized for passive cable replacement solutions.
• Standard LMX9830 events:
– Only necessary events will be reported
• All events:
– Additional to the standard all changes at the physical layer will be reported.
9.4.4 Default Link Policy
Each Bluetooth Link can be configured to support M/S role switch, Hold Mode, Sniff Mode and Park Mode. The
default link policy defines the standard setting for incoming and outgoing connections.
9.4.5 Audio Support
The LMX9830 offers commands to establish and release synchronous connections (SCO) to support Headset or
Handsfree applications. The firmware supports one active link with all available package types (HV1, HV2, HV3),
routing the audio data between the Bluetooth link and the advanced audio interface. In order to provide the
analog data interface, an external audio codec is required. The LMX9830 includes a list of codecs which can be
used.
Table 36. Operation Parameters Stored in LMX9830
PARAMETER
DEFAULT VALUE
DESCRIPTION
BDADDR
(To be requested from IEEE)
Bluetooth device address
Local Name
Serial port device
Friendly Name
PinCode
0000
Bluetooth PinCode
Operation Mode
Automatic ON
Automatic mode ON or OFF
Default Connections
0
Up to seven default devices to connect to
SDP Database
1 SPP entry:
Name: COM1
Authentication and encryption enabled
Service discovery database, control for supported profiles
UART Speed
9600
Sets the speed of the physical UART interface to the host
UART Settings
1 Stop bit, parity disabled
Parity and stop bits on the hardware UART interface
Ports to Open
0000 0001
Defines the RFComm ports to open
Link Keys
No link keys
Link keys for paired devices
Security Mode
2
Security mode
Page Scan Mode
Connectable
Connectable/Not connectable for other devices
Discoverable
Discoverable/Not Discoverable/Limited Discoverable for other
devices
All modes allowed
Configures modes allowed for incoming or outgoing connections
(Role switch, Hold mode, Sniff mode...)
20 seconds
The Default Link Timeout configures the timeout, after which the link
is assumed lost, if no packages have been received from the remote
device.
Standard LMX9830 events reported
Defines the level of reporting on the UART
― no events
― standard events
― standard including ACL link events
Inquiry Scan Mode
Default Link Policy
Default Link Timeout
Event Filter
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Device Functional Modes (continued)
Table 36. Operation Parameters Stored in LMX9830 (continued)
PARAMETER
DEFAULT VALUE
Default Audio Settings
DESCRIPTION
Configures the settings for the external codec and the air format.
• Codecs:
Motorola MC145483 / Winbond W681360
OKI MSM7717 / Winbond W681310
PCM Slave
• Airformat:
CVSD
µ-Law
A-Law
non
9.4.6 Low Power Modes
The LMX9830 supports different Low Power Modes to reduce power in different operating situations. The
modular structure of the LMX9830 allows the firmware to power down unused modules.
The Low Power Modes have influence on:
• UART transport layer
– enabling or disabling the interface
• Bluetooth Baseband activity
– firmware disables LLC and Radio if possible
9.4.7 Power Modes
The following LMX9830 power modes, which depend on the activity level of the UART transport layer and the
radio activity are defined:
The radio activity level mainly depends on application requirements and is defined by standard Bluetooth
operations like inquiry/page scanning or an active link.
A remote device establishing or disconnecting a link may also indirectly change the radio activity level.
The UART transport layer by default is enabled on device power up. In order to disable the transport layer the
command “Disable Transport Layer” is used. Thus only the Host side command interface can disable the
transport layer. Enabling the transport layer is controlled by the HW Wakeup signalling. This can be done from
either the Host or the LMX9830. See also “LMX9830 Software User’s Guide” for detailed information on timing
and implementation requirements.
Table 37. Power Mode Activity
38
POWER MODE
UART ACTIVITY
RADIO ACTIVITY
PM0
OFF
OFF
none
PM1
ON
OFF
Main Clock
PM2
OFF
Scanning
Main Clock / 32.768 kHz
PM3
ON
Scanning
Main Clock
PM4
OFF
SPP Link
Main Clock
PM5
ON
SPP Link
Main Clock
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Figure 21. Transition Between Different Hardware Power Modes
9.4.8 Enabling and Disabling UART Transport
9.4.8.1 Hardware Wake-Up Functionality
In certain usage scenarios, the host can switch off the transport layer of the LMX9830 in order to reduce power
consumption. Afterwards both devices, host and LMX9830 are able to shut down their UART interfaces.
In order to save system connections the UART interface is reconfigured to hardware wake-up functionality. For a
detailed timing and command functionality, also see the LMX9830 Software User’s Guide.
The interface between host and LMX9830 is defined as described in Figure 22.
Figure 22. UART NULL Modem Connection
9.4.8.2 Disabling the UART Transport Layer
The Host can disable the UART transport layer by sending the “Disable Transport Layer” Command. The
LMX9830 will empty its buffers, send the confirmation event and disable its UART interface. Afterwards the
UART interface will be reconfigured to wake up on a falling edge of the CTS pin.
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9.4.8.3 LMX9830 Enabling the UART Interface
As the Transport Layer can be disabled in any situation the LMX9830 must first make sure the transport layer is
enabled before sending data to the host. Possible scenarios can be incoming data or incoming link indicators. If
the UART is not enabled the LMX9830 assumes that the Host is sleeping and waking it up by activating RTS. To
be able to react on that Wakeup, the host must monitor the CTS pin.
As soon as the host activates its RTS pin, the LMX9830 will first send a confirmation event and then start to
transmit the events.
9.4.8.4 Enabling the UART Transport Layer from the Host
If the host must send data or commands to the LMX9830 while the UART Transport Layer is disabled, it must
first assume that the LMX9830 is sleeping and wake it up using its RTS signal.
When the LMX9830 detects the Wake-Up signal it activates the UART HW and acknowledges the Wake-Up
signal by settings its RTS. Additionally the Wakeup will be confirmed by a confirmation event. When the Host has
received this “Transport Layer Enabled” event, the LMX9830 is ready to receive commands.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Typical Application
Figure 23. Reference Design
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Typical Application (continued)
10.1.1 Design Requirements
10.1.1.1 Evaluation Design
Recommended that a 4-component T-PI pad be used between RF out and antenna input. Allows for versatility in
the design such that the match to the antenna maybe improved and/or blocking margin increased by adding a LC
filter.
For a schematic including an RS232 communication with the host, see the LMX9830DONGLE designer guide,
SNOA518.
10.1.2 Detailed Design Procedure
10.1.2.1 Antenna Matching Network
The antenna matching network may or may not be required, depending upon the impedance of the antenna
chosen and the trace impedance on the PCB. A 6.8-pF blocking capacitor is recommended.
NOTE
Additional L network placement is recommended for tuning the trace impedance if needed.
10.1.2.2 Host Interface
To set the logic thresholds of the LMX9830 to match the host system, IOVCC (pin C4) must be connected to the
logic power supply of the host system. It is highly recommended that a 10-pF bypass capacitor be placed as
close as possible to the IOVCC pad on the LMX9830.
10.1.2.3 Frequency and Baud Rate Selections
OP3, OP4, OP5 can be strapped to the host logic 0 and 1 levels to set the host interface boot-up configuration.
Alternatively all OP3, OP4, OP5 can be hardwired over 1-kW pullup/pulldown resistors. See Table 10.
10.1.2.4 Start-Up Sequence Options
OP6, OP7, and Env1 can be left unconnected (both OP6 and OP7 are pulled low and ENV1 is pulled high
internally), These can be hardwired over 1-kW pullup/pulldown resistors. See Table 9.
10.1.2.5 Clock Input
The clock source must be placed as close as possible to the LMX9830. The quality of the radio performance is
directly related to the quality of the clock source connected to the oscillator port on the LMX9830. Careful
attention must be paid to the crystal/oscillator parameters or radio performance could be drastically reduced.
10.1.2.6 Soldering
The LMX9830 bumps are designed to melt as part of the Surface Mount Assembly (SMA) process. In order to
ensure reflow of all solder bumps and maximum solder joint reliability while minimizing damage to the package,
recommended reflow profiles should be used.
Table 38, Table 39 and Figure 24 provide the soldering details required to properly solder the LMX9830 to
standard PCBs. The illustration serves only as a guide and TI's is not liable if a selected profile does not work.
See IPC/JEDEC J-STD-020C, July 2004 for more information.
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Typical Application (continued)
Table 38. Soldering Details
PARAMETER
VALUE
PCB Land Pad Diameter
13 mil
PCB Solder Mask Opening
19 mil
PCB Finish (HASL details)
Defined by customer or manufacturing facility
Stencil Aperture
17 mil
Stencil Thickness
5 mil
Solder Paste Used
Defined by customer or manufacturing facility
Flux Cleaning Process
Defined by customer or manufacturing facility
Reflow Profiles
See Figure 24
Table 39. Classification Reflow Profiles (1) (2)
PROFILE FEATURE
NOPB ASSEMBLY
Average Ramp-Up Rate (TsMAX to Tp)
3°C/second maximum
Preheat:
Temperature Min (TsMIN)
Temperature Max (TsMAX)
Time (tsMIN to tsMAX)
150°C
200°C
60180 seconds
Time maintained above:
Temperature (TL)
Time (tL)
217°C
60150 seconds
Peak/Classification Temperature (Tp)
260 + 0°C
Time within 5°C of actual Peak Temperature (tp)
20 – 40 seconds
Ramp-Down Rate
6°C/second maximum
Time 25 °C to Peak Temperature
8 minutes maximum
Reflow Profiles
(1)
(2)
See Figure 24
See IPC/JEDEC J-STD-020C, July 2004.
All temperatures refer to the top side of the package, measured on the package body surface.
10.1.3 Application Curves
Figure 24. Typical Reflow Profiles
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10.2 System Examples
10.2.1 Usage Scenarios
10.2.1.1 Scenario 1: Point-to-Point Connection
LMX9830 acts only as slave, no further configuration is required.
Example: Sensor with LMX9830; hand-held device with standard Bluetooth option.
The SPP conformance of the LMX9830 allows any device using the SPP to connect to the LMX9830.
Because of switching to Transparent automatically, the controller has no need for an additional protocol layer;
data is sent raw to the other Bluetooth device.
On default, a PinCode is requested to block unallowed targeting.
Figure 25. Point-to-Point Connection
10.2.1.2 Scenario 2: Automatic Point-to-Point Connection
LMX9830 at both sides.
Example: Serial Cable Replacement.
Device #1 controls the link setup with a few commands as described.
If step 5 is executed, the stored default device is connected (step 4) after reset (in Automatic mode only) or by
sending the command “Connect to Default Device”. The command can be sent to the device at any time.
If step 6 is left out, the microcontroller must use the command “Send Data” instead of sending data directly to the
module.
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System Examples (continued)
Figure 26. Automatic Point-to-Point Connection
10.2.1.3 Scenario 3: Point-to-Multipoint Connection
LMX9830 acts as master for several slaves.
Example: Two sensors with LMX9830; one hand-held device with implemented LMX9830.
Serial Devices #2 and #3 establish the link automatically as soon as they are contacted by another device. No
controller interaction is necessary for setting up the Bluetooth link. Both switch automatically into Transparent
mode. The host sends raw data over the UART.
Serial Device #1 is acting as master for both devices. As the host must decide to or from which device data is
coming from, data must be sent using the “Send data command”. If the device receives data from the other
devices, it is packaged into an event called “Incoming data event”. The event includes the device related port
number.
If necessary, a link configuration can be stored as default in the master Serial Device #1 to enable the automatic
reconnect after reset, power up, or by sending the “connect default connection” command.
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System Examples (continued)
Figure 27. Automatic Point-to-Point Connection
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11 Power Supply Recommendations
11.1 Filtered Power Supply
It is important to provide the LMX9830 with adequate ground planes and a filtered power supply. TI highly
recommends placing a 0.1-µF and a 10-pF bypass capacitor as close as possible to VCC (pin E1) on the
LMX9830 for 2.5-V and 3.3-V operations.
NOTE
For 1.8-V operations, VCC filtering is not required and VCC should be tied directly to
ground.
Figure 28 represents a typical system functional schematic for the LMX9830 in its normal 3.0-V or 3.3-V system
interface operation.
Figure 29 represents a typical system functional schematic for the LMX9830 in its 1.8-V system interface
operation.
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Filtered Power Supply (continued)
Capacitor values, Ct1 and Ct2 may vary depending on board design crystal manufacturer specification.
Note: (CL = crystal capacitance load rating) of 12 pF or greater rating is required from the crystal vendor of choice to
best match module impedance and give a viable tuning range for the system.
For grounding, one ground plane is used for both RF and Digital Grounding.
For Antenna it is recommend that a 3 component L type pad with series 6.8pF blocker cap be used between RF
output and antenna matching L network. This allows for versatility in the design such that the match to the antenna
maybe improved and/or the blocking margin increased by use a LC filter.
Figure 28. 2.5-V to 3.3-V Example Functional System Schematic
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Filtered Power Supply (continued)
Capacitor values, Ct1 and Ct2 may vary depending on board design crystal manufacturer specification.
Note: (CL = crystal capacitance load rating) of 12 pF or greater rating is required from the crystal vendor of choice to
best match module impedance and give a viable tuning range for the system.
For grounding, one ground plane is used for both RF and Digital Grounding.
For Antenna, TI recommends that a 3-component L type pad with series 6.8-pF blocker cap be used between RF
output and antenna matching L network as shown above. This allows for versatility in the design such that the match
to the antenna maybe improved and/or the blocking margin increased by use a LC filter.
Figure 29. 1.8-V Example Functional System Schematic
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12 Device and Documentation Support
12.1 Device Support
LMX9830 Software User’s Guide, SNWC001
LMX9830DONGLE Evaluation Module, http://www.ti.com/tool/lmx9830dongle
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
AN-1810 LMX9830 Design Checklist, SNOA518
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc..
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMX9830SM/NOPB
ACTIVE
NFBGA
NZB
60
320
Green (RoHS
& no Sb/Br)
SNAGCU
Level-4-260C-72 HR
-40 to 125
9830SM
LMX9830SMX/NOPB
ACTIVE
NFBGA
NZB
60
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-4-260C-72 HR
-40 to 125
9830SM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Nov-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMX9830SMX/NOPB
Package Package Pins
Type Drawing
NFBGA
NZB
60
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
9.4
2.3
8.0
W
Pin1
(mm) Quadrant
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Nov-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMX9830SMX/NOPB
NFBGA
NZB
60
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NZB0060A
SLF60A (Rev A)
www.ti.com
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