Texas Instruments | CC1121 High-Performance Low-Power RF Transceiver (Rev. F) | Datasheet | Texas Instruments CC1121 High-Performance Low-Power RF Transceiver (Rev. F) Datasheet

Texas Instruments CC1121 High-Performance Low-Power RF Transceiver (Rev. F) Datasheet
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CC1121
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
CC1121 High-Performance Low-Power RF Transceiver
1 Device Overview
1.1
Features
1
• High-Performance, Single-Chip Transceiver
– Excellent Receiver Sensitivity:
• –120 dBm at 1.2 kbps
• –110 dBm at 50 kbps
– Blocking Performance: 86 dB at 10 MHz
– Adjacent Channel Selectivity: 60 dB
– Very Low Phase Noise: –111 dBc/Hz at
10-kHz Offset
• Separate 128-Byte RX and TX FIFOs
• WaveMatch: Advanced Digital Signal Processing
for Improved Sync Detect Performance
• Support for Seamless Integration With the CC1190
Device for Increased Range Giving up to 3-dB
Improvement in Sensitivity and up to +27-dBm
Output Power
• Power Supply
– Wide Supply Voltage Range (2.0 V to 3.6 V)
– Low Current Consumption:
• RX: 2 mA in RX Sniff Mode
• RX: 17-mA Peak Current in Low-Power
Mode
• RX: 22-mA Peak Current in HighPerformance Mode
• TX: 45 mA at +14 dBm
– Power Down: 0.12 μA (0.5 μA With eWOR
Timer Running)
• Programmable Output Power up to +16 dBm With
0.4-dB Step Size
1.2
•
•
•
• Automatic Output Power Ramping
• Configurable Data Rates: 1.2 to 200 kbps
• Supported Modulation Formats: 2-FSK,
2-GFSK, 4-FSK, 4-GFSK, MSK, OOK
• RoHS-Compliant 5-mm x 5-mm No-Lead QFN 32Pin Package (RHB)
• Regulations – Suitable for Systems Targeting
Compliance With
– Europe: ETSI EN 300 220, ETSI EN 54-25
– US: FCC CFR47 Part 15, FCC CFR47 Part 24
– Japan: ARIB STD-T108
• Peripherals and Support Functions
– Enhanced Wake-On-Radio Functionality for
Automatic Low-Power Receive Polling
– Includes Functions for Antenna Diversity
Support
– Support for Retransmissions
– Support for Auto-Acknowledge of Received
Packets
– TCXO Support and Control, also in Power
Modes
– Automatic Clear Channel Assessment (CCA) for
Listen-Before-Talk (LBT) Systems
– Built-in Coding Gain Support for Increased
Range and Robustness
– Digital RSSI Measurement
– Temperature Sensor
Applications
Ultra-Low Power Wireless Systems With Channel
Spacing Down to 50 kHz
169-, 315-, 433-, 868-, 915-, 920-, 950-MHz
ISM/SRD Band Systems
Wireless Metering and Wireless Smart Grid (AMR
and AMI)
•
•
•
•
•
•
IEEE 802.15.4g Systems
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
Wireless Healthcare Applications
Wireless Sensor Networks and Active RFID
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC1121
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
1.3
www.ti.com
Description
The CC1121 device is a fully integrated single-chip radio transceiver designed for high performance at
very low-power and low-voltage operation in cost-effective wireless systems. All filters are integrated, thus
removing the need for costly external SAW and IF filters. The device is mainly intended for the ISM
(Industrial, Scientific, and Medical) and SRD (Short Range Device) frequency bands at 274–320 MHz,
410–480 MHz, and 820–960 MHz.
The CC1121 device provides extensive hardware support for packet handling, data buffering, burst
transmissions, clear channel assessment, link quality indication, and Wake-On-Radio. The main operating
parameters of the CC1121 device can be controlled through an SPI interface. In a typical system, the
CC1121 device will be used with a microcontroller and only a few external passive components.
Device Information (1)
PART NUMBER
CC1121RHB
(1)
1.4
PACKAGE
BODY SIZE
VQFN (32)
5.00 mm x 5.00 mm
For more information, see Section 8, Mechanical Packaging and Orderable Information
Functional Diagram
Figure 1-1 shows the system block diagram of the CC1121 device.
CC112X
(optional 32kHz
clock intput)
Ultra low power 32kHz
auto-calibrated RC oscillator
4k byte
ROM
Power on reset
MARC
Main Radio Control Unit
Ultra low power 16 bit
MCU
CSn (chip select)
SPI
Serial configuration
and data interface
SI (serial input)
Interrupt and
IO handler
System bus
SO (serial output)
SCLK (serial clock)
eWOR
Enhanced ultra low power
Wake On Radio timer
Configuration and
status registers
Battery sensor /
temp sensor
256 byte
FIFO RAM
buffer
Packet handler
and FIFO control
(optional GPIO0-3)
RF and DSP frontend
Output power ramping and OOK / ASK modulation
I
Fully integrated Fractional-N
Frequency Synthesizer
Q
High linearity
LNA
LNA_N
(optional GPIO for
antenna diversity)
ifamp
XOSC
XOSC_Q2
90dB dynamic
range ADC
(optional bit clock)
Channel
filter
ifamp
LNA_P
XOSC_Q1
Data interface with
signal chain access
Cordic
14dBm high
efficiency PA
Modulator
PA
(optional autodetected
external XOSC / TCXO)
Highly flexible FSK / OOK
demodulator
(optional low jitter serial
data output for legacy
protocols)
90dB dynamic
range ADC
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Figure 1-1. Functional Block Diagram
2
Device Overview
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SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
Table of Contents
1
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 2
1.4
Functional Diagram ................................... 2
2
3
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
4
..........................................
3.2
Pin Configuration .....................................
Specifications ............................................
4.1
Absolute Maximum Ratings ..........................
4.2
Handling Ratings .....................................
3.1
4.3
4.4
Pin Diagram
6
7
7
7
Recommended Operating Conditions (General
Characteristics) ....................................... 7
Thermal Resistance Characteristics for RHB
Package .............................................. 7
RF Characteristics .................................... 8
4.6
................................ 9
Current Consumption, Static Modes ................. 9
Current Consumption, Transmit Modes .............. 9
Current Consumption, Receive Modes.............. 10
Receive Parameters................................. 11
Transmit Parameters ................................ 14
PLL Parameters ..................................... 15
Wake-up and Timing ................................ 16
32-MHz Crystal Oscillator ........................... 16
32-MHz Clock Input (TCXO) ....................... 16
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
5
5
4.5
4.7
4.16
Regulatory Standards
6
7
8
32-kHz Clock Input .................................. 17
...............................
.......................................
4.19 Temperature Sensor ................................
4.20 Typical Characteristics ..............................
Detailed Description ...................................
5.1
Block Diagram.......................................
5.2
Frequency Synthesizer ..............................
5.3
Receiver .............................................
5.4
Transmitter ..........................................
5.5
Radio Control and User Interface ...................
5.6
Enhanced Wake-On-Radio (eWOR) ................
5.7
Sniff Mode ...........................................
5.8
Antenna Diversity ...................................
5.9
Low-Power and High-Performance Mode...........
5.10 WaveMatch ..........................................
Typical Application Circuit ...........................
Device and Documentation Support ...............
7.1
Device Support ......................................
7.2
Documentation Support .............................
7.3
Community Resources ..............................
7.4
Trademarks..........................................
7.5
Electrostatic Discharge Caution .....................
7.6
Glossary .............................................
4.17
32-kHz RC Oscillator
17
4.18
I/O and Reset
17
17
18
20
20
20
21
21
21
21
22
22
22
23
24
25
25
26
26
26
26
26
Mechanical Packaging and Orderable
Information .............................................. 27
Table of Contents
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CC1121
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SWRS111E device-specific data
manual to make it an SWRS111F revision.
Changes from Revision E (July 2014) to Revision F
•
•
4
Page
Added Ambient to the temperature range condition and removed Tj from Temperature range ........................... 7
Added data to TCXO table ......................................................................................................... 16
Revision History
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SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
3 Terminal Configuration and Functions
3.1
Pin Diagram
25 AVDD_PFD_CHP
26 DCPL_PFD_CHP
27 AVDD_SYNTH2
28 AVDD_XOSC
DCPL_XOSC
29
30 XOSC_Q1
XOSC_Q2
31
32 EXT_XOSC
Figure 3-1 shows pin names and locations for the CC1121 device.
VDD_GUARD
1
24
LPF1
RESET_N
2
23
LPF0
GPIO3
3
22
AVDD_SYNTH1
GPIO2
4
21
DCPL_VCO
DVDD
5
20
LNA_N
DCPL
6
SI
7
SCLK
8
CC1121
19 LNA_P
GND
GROUND PAD
18
TRX_SW
17
PA
11
12
13
14
15
16
GPIO0
CSn
DVDD
AVDD_IF
RBIAS
AVDD_RF
N.C.
SO (GPIO1)
10
9
Figure 3-1. Package 5-mm × 5-mm QFN
Terminal Configuration and Functions
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SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
3.2
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Pin Configuration
The following table lists the pinout configuration for the CC1121 device.
PIN NO.
PIN NAME
TYPE / DIRECTION
DESCRIPTION
1
VDD_GUARD
Power
2.0–3.6 V VDD
2
RESET_N
Digital input
Asynchronous, active-low digital reset
3
GPIO3
Digital I/O
General-purpose I/O
4
GPIO2
Digital I/O
General-purpose I/O
5
DVDD
Power
2.0–3.6 V VDD to internal digital regulator
6
DCPL
Power
Digital regulator output to external decoupling capacitor
7
SI
Digital input
Serial data in
8
SCLK
Digital input
Serial data clock
9
SO(GPIO1)
Digital I/O
Serial data out (general-purpose I/O)
10
GPIO0
Digital I/O
General-purpose I/O
11
CSn
Digital Input
Active-low chip select
12
DVDD
Power
2.0–3.6 V VDD
13
AVDD_IF
Power
2.0–3.6 V VDD
14
RBIAS
Analog
External high-precision R
15
AVDD_RF
Power
2.0–3.6 V VDD
16
N.C.
17
PA
Analog
Single-ended TX output (requires DC path to VDD)
18
TRX_SW
Analog
TX and RX switch. Connected internally to GND in TX and floating (highimpedance) in RX.
19
LNA_P
Analog
Differential RX input (requires DC path to GND)
20
LNA_N
Analog
Differential RX input (requires DC path to GND)
21
DCPL_VCO
Power
Pin for external decoupling of VCO supply regulator
22
AVDD_SYNTH1
Power
2.0–3.6 V VDD
23
LPF0
Analog
External loop filter components
24
LPF1
25
AVDD_PFD_CHP
Power
2.0–3.6 V VDD
26
DCPL_PFD_CHP
Power
Pin for external decoupling of PFD and CHP regulator
27
AVDD_SYNTH2
Power
2.0–3.6 V VDD
28
AVDD_XOSC
Power
2.0–3.6 V VDD
29
DCPL_XOSC
Power
Pin for external decoupling of XOSC supply regulator
30
XOSC_Q1
Analog
Crystal oscillator pin 1 (must be grounded if a TCXO or other external clock
connected to EXT_XOSC is used)
31
XOSC_Q2
Analog
Crystal oscillator pin 2 (must be left floating if a TCXO or other external clock
connected to EXT_XOSC is used)
32
EXT_XOSC
Digital input
Pin for external XOSC input (must be grounded if a regular XOSC connected
to XOSC_Q1 and XOSC_Q2 is used)
–
GND
Ground pad
The ground pad must be connected to a solid ground plane.
6
Not connected
External loop filter components
Terminal Configuration and Functions
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4 Specifications
All measurements performed on CC1120EM_868_915
CC1120EM_420_470 rev.1.0.1, or CC1120EM_169 rev.1.2.
rev.1.0.1,
CC1120EM_955
rev.1.2.1,
Absolute Maximum Ratings (1) (2)
4.1
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
Supply voltage (VDD, AVDD_x)
–0.3
MAX
Input RF level
UNIT
3.9
V
+10
dBm
Voltage on any digital pin
–0.3
VDD+0.3
V
Voltage on analog pins
(including DCPL pins)
–0.3
2.0
V
(1)
(2)
All supply pins must have the same voltage
max 3.9 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under general characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
4.2
Handling Ratings
Tstg
Storage temperature range
Electrostatic discharge
(ESD) performance:
VESD
(1)
(2)
CONDITION
Human body model (HBM), per ANSI/ESDA/JEDEC JS001
Charged device model (CDM), per JESD22C101 (2)
(1)
All pins
MIN
MAX
UNIT
–40
125
°C
–2
2
kV
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.
4.3
Recommended Operating Conditions (General Characteristics)
PARAMETER
MIN
MAX
UNIT
Voltage supply range
2.0
3.6
V
0
VDD
V
–40
85
°C
Voltage on digital inputs
Temperature range
4.4
TYP
CONDITION
All supply pins must have the same voltage
Ambient
Thermal Resistance Characteristics for RHB Package
°C/W (1)
AIR FLOW (m/s) (2)
21.1
0.00
RθJC
Junction-to-case (top)
RθJB
Junction-to-board
5.3
0.00
RθJA
Junction-to-free air
31.3
0.00
PsiJT
Junction-to-package top
0.2
0.00
PsiJB
Junction-to-board
5.3
0.00
RθJC
Junction-to-case (bottom)
0.8
0.00
(1)
(2)
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 40 mW and an ambient temperature of 25ºC is assumed.
m/s = meters per second
Specifications
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4.5
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RF Characteristics
PARAMETER
MIN
MAX
UNIT
820
TYP
960
MHz
410
480
MHz
(273.3)
(320)
MHz
Frequency bands
164
192
MHz
(205)
(240)
MHz
(136.7)
(160)
MHz
Frequency resolution
Data rate step size
8
For more information, see application
note AN115, Using the
CC112x/CC1175 at 274 to 320 MHz.
Please contact TI for more information
about the use of these frequency
bands.
30
Hz
In 820- to 950-MHz band
15
Hz
In 410- to 480-MHz band
Hz
In 164- to 192-MHz band
6
Data rate
CONDITION
0
200
kbps
Packet mode
0
100
kbps
Transparent mode
1e-4
Specifications
bps
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4.6
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
Regulatory Standards
PERFORMANCE MODE
FREQUENCY BAND
ARIB T-108
ARIB T-96
ETSI EN 300 220, receiver category 2
ETSI EN 54-25
FCC PART 24 Submask D
FCC Part 15.247
FCC Part 15.249
Performance also suitable
for systems targeting
maximum allowed output
power in the respective
bands, using a range
extender such as the
CC1190 device
ETSI EN 300 220, category 2
Performance also suitable
for systems targeting
maximum allowed output
power in the respective
bands, using a range
extender
164–192 MHz
ETSI EN 300 220, category 2
Performance also suitable
for systems targeting
maximum allowed output
power in the respective
bands, using a range
extender
820–960 MHz
ETSI EN 300 220, category 2
FCC Part 15.247
FCC Part 15.249
410–480 MHz
ETSI EN 300 220, category 2
164–192 MHz
ETSI EN 300 220, category 2
820–960 MHz
High-performance mode
SUITABLE FOR COMPLIANCE WITH COMMENTS
410–480 MHz
Low-power mode
4.7
Current Consumption, Static Modes
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Power down with retention
TYP
MAX
UNIT
0.12
1
µA
CONDITION
0.5
µA
Low-power RC oscillator running
XOFF mode
170
µA
Crystal oscillator / TCXO disabled
IDLE mode
1.3
mA
Clock running, system waiting with no
radio activity
4.8
4.8.1
Current Consumption, Transmit Modes
950-MHz Band (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
TYP
MAX
UNIT
TX current consumption +10 dBm
37
mA
TX current consumption 0 dBm
26
mA
4.8.2
CONDITION
868-, 915-, and 920-MHz Bands (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
TYP
MAX
UNIT
TX current consumption +14 dBm
45
mA
TX current consumption +10 dBm
34
mA
CONDITION
Specifications
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434-MHz Band (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
TYP
MAX
UNIT
TX current consumption +15 dBm
50
mA
TX current consumption +14 dBm
45
mA
TX current consumption +10 dBm
34
mA
4.8.4
CONDITION
169-MHz Band (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
TYP
MAX
UNIT
TX current consumption +15 dBm
54
mA
TX current consumption +14 dBm
49
mA
TX current consumption +10 dBm
41
mA
4.8.5
CONDITION
Low-Power Mode
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
TX current consumption +10 dBm
4.9
TYP
MAX
32
UNIT
CONDITION
mA
Current Consumption, Receive Modes
4.9.1
High-Performance Mode
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
TYP
MAX
UNIT
CONDITION
2
mA
Using RX sniff mode, where the
receiver wakes up at regular
intervals to look for an incoming
packet
433-, 868-, 915-, 920-, and 950-MHz bands
22
mA
169-MHz band
23
mA
Peak current consumption during
packet reception at the sensitivity
threshold
Average current consumption
Check for data packet every 1 second
using Wake-on-Radio
15
µA
RX wait for sync
1.2 kbps, 4-byte preamble
RX peak current
4.9.2
50 kbps, 5-byte preamble, 40-kHz
RC oscillator used as sleep timer
Low-Power Mode
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
TYP
MAX
UNIT
RX peak current low-power RX mode
1.2 kbps
10
17
Specifications
mA
CONDITION
Peak current consumption during
packet reception at the sensitivity
level
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4.10 Receive Parameters
All RX measurements made at the antenna connector, to a bit error rate (BER) limit of 1%.
4.10.1 General Receive Parameters (High-Performance Mode)
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
TYP
Saturation
Digital channel filter programmable
bandwidth
MAX
UNIT
+10
CONDITION
dBm
41.7
200
kHz
IIP3, normal mode
–14
dBm
At maximum gain
IIP3, high linearity mode
–8
dBm
Using 6-dB gain reduction in front
end
±12
%
With carrier sense detection
enabled and assuming 4-byte
preamble
±0.2
%
With carrier sense detection
disabled
–56
dBm
< –57
dBm
Data rate offset tolerance
Spurious emissions
1–13 GHz (VCO leakage at 3.5 GHz)
30 MHz to 1 GHz
Radiated emissions measured
according to ETSI EN 300 220, fc =
869.5 MHz
Optimum source impedance
868-, 915-, and 920-MHz bands
60 + j60 / 30 + j30
Ω
433-MHz band
100 + j60 / 50+ j30
Ω
169-MHz band
140 + j40 / 70 + j20
Ω
(Differential or single-ended RX
configurations)
4.10.2 RX Performance in 950-MHz Band (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Sensitivity
Note: Sensitivity can be improved if the
TX and RX matching networks are
separated.
Blocking and selectivity
1.2-kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation,
50-kHz channel filter
Blocking and selectivity
50-kbps 2GFSK, 200-kHz channel
separation, 25-kHz deviation, 100-kHz
channel filter
(Same modulation format as 802.15.4g
Mandatory Mode)
Blocking and selectivity
200-kbps 4GFSK, 83-kHz deviation
(outer symbols),
200-kHz channel filter, zero IF
(1)
(2)
TYP
Max
UNIT
CONDITION
–114
dBm
1.2 kbps, DEV=20 kHz CHF=50 kHz (1)
–107
dBm
50 kbps 2GFSK, DEV=25 kHz, CHF=100 kHz (1)
–100
dBm
200 kbps, DEV=83 kHz (outer symbols), CHF=200 kHz,
4GFSK (2)
47
dB
± 50 kHz (adjacent channel)
48
dB
+ 100 kHz (alternate channel)
69
dB
± 1 MHz
71
dB
± 2 MHz
78
dB
± 10 MHz
43
dB
± 200 kHz (adjacent channel)
51
dB
± 400 kHz (alternate channel)
62
dB
± 1 MHz
65
dB
± 2 MHz
71
dB
± 10 MHz
37
dB
± 200 kHz (adjacent channel)
44
dB
± 400 kHz (alternate channel)
55
dB
± 1 MHz
58
dB
± 2 MHz
64
dB
± 10 MHz
DEV is short for deviation, CHF is short for Channel Filter Bandwidth
BT=0.5 is used in all GFSK measurements
Specifications
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4.10.3 RX Performance in 868-, 915-, and 920-MHz Bands (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Sensitivity
Blocking and selectivity
1.2-kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation, 50-kHz
channel filter
Blocking and selectivity
38.4-kbps 2GFSK, 100-kHz channel
separation, 20-kHz deviation, 100-kHz
channel filter
Blocking and selectivity
50-kbps 2GFSK, 200-kHz channel
separation, 25-kHz deviation, 100-kHz
channel filter
(Same modulation format as 802.15.4g
Mandatory Mode)
Blocking and selectivity
200-kbps 4GFSK, 83-kHz deviation
(outer symbols), 200-kHz channel filter,
zero IF
(1)
TYP
MAX
UNIT
CONDITION
–120
dBm
1.2 kbps, DEV=10 kHz CHF=41.7 kHz (1), using increased
RX filtering
–117
dBm
1.2 kbps, DEV=20 kHz CHF=50 kHz (1)
–114
dBm
4.8 kbps OOK
–110
dBm
38.4 kbps, DEV=20 kHz CHF=100 kHz (1)
–110
dBm
50 kbps 2GFSK, DEV=25 kHz, CHF=100 kHz (1)
–103
dBm
200 kbps, DEV=83 kHz (outer symbols), CHF=200
kHz (1), 4GFSK
48
dB
± 50 kHz (adjacent channel)
48
dB
± 100 kHz (alternate channel)
69
dB
± 1 MHz
74
dB
± 2 MHz
81
dB
± 10 MHz
42
dB
+ 100 kHz (adjacent channel)
43
dB
± 200 kHz (alternate channel)
62
dB
± 1 MHz
66
dB
± 2 MHz
74
dB
± 10 MHz
43
dB
± 200 kHz (adjacent channel)
50
dB
± 400 kHz (alternate channel)
61
dB
± 1 MHz
65
dB
± 2 MHz
74
dB
± 10 MHz
36
dB
± 200 kHz (adjacent channel)
44
dB
± 400 kHz (alternate channel)
55
dB
± 1 MHz
59
dB
± 2 MHz
67
dB
± 10 MHz
DEV is short for deviation, CHF is short for Channel Filter Bandwidth
4.10.4 RX Performance in 434-MHz Band (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
Sensitivity
Blocking and selectivity
1.2-kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation, 50-kHz
channel filter
Blocking and selectivity
38.4-kbps 2GFSK, 100-kHz channel
separation, 20-kHz deviation, 100-kHz
channel filter
(1)
12
MIN
UNIT
CONDITION
–109
TYP
MAX
dBm
50 kbps 2GFSK, DEV=25 kHz, CHF=100 kHz (1)
–116
dBm
1.2 kbps, DEV=20 kHz CHF=50 kHz (1)
54
dB
± 50 kHz (adjacent channel)
54
dB
+ 100 kHz (alternate channel)
74
dB
± 1 MHz
78
dB
± 2 MHz
86
dB
± 10 MHz
47
dB
+ 100 kHz (adjacent channel)
50
dB
± 200 kHz (alternate channel)
67
dB
± 1 MHz
71
dB
± 2 MHz
78
dB
± 10 MHz
DEV is short for deviation, CHF is short for Channel Filter Bandwidth
Specifications
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4.10.5 RX Performance in 169-MHz Band (High-Performance Mode)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Sensitivity
Blocking and selectivity
1.2-kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation, 50-kHz
channel filter
(1)
UNIT
CONDITION
–117
TYP
MAX
dBm
1.2 kbps, DEV=20 kHz CHF=50 kHz (1)
60
dB
± 50 kHz (adjacent channel)
60
dB
+ 100 kHz (alternate channel)
76
dB
± 1 MHz
77
dB
± 2 MHz
83
dB
± 10 MHz
DEV is short for deviation, CHF is short for Channel Filter Bandwidth
4.10.6 RX Performance in Low-Power Mode
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
Sensitivity
Blocking and selectivity
1.2-kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation, 50-kHz
channel filter
Blocking and selectivity
38.4-kbps 2GFSK, 100-kHz channel
separation, 20-kHz deviation, 100-kHz
channel filter
Blocking and selectivity
50-kbps 2GFSK, 200-kHz channel
separation, 25-kHz deviation, 100-kHz
channel filter
(Same modulation format as 802.15.4g
Mandatory Mode)
Saturation
(1)
TYP
MAX
UNIT
CONDITION
–99
dBm
38.4 kbps, DEV=50 kHz CHF=100 kHz (1)
–99
dBm
50 kbps 2GFSK, DEV=25 kHz, CHF=100 kHz (1)
43
dB
± 50 kHz (adjacent channel)
45
dB
+ 100 kHz (alternate channel)
71
dB
± 1 MHz
74
dB
± 2 MHz
75
dB
± 10 MHz
37
dB
+ 100 kHz (adjacent channel)
43
dB
+ 200 kHz (alternate channel)
58
dB
± 1 MHz
62
dB
± 2 MHz
64
dB
+ 10 MHz
43
dB
+ 200 kHz (adjacent channel)
52
dB
+ 400 kHz (alternate channel)
60
dB
± 1 MHz
64
dB
± 2 MHz
65
dB
± 10 MHz
+10
dBm
DEV is short for deviation, CHF is short for Channel Filter Bandwidth
Specifications
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4.11 Transmit Parameters
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
UNIT
CONDITION
+12
dBm
At 950 MHz
+14
dBm
At 915- and 920-MHz
+15
dBm
At 915- and 920-MHz with VDD = 3.6 V
+15
dBm
At 868 MHz
+16
dBm
At 868 MHz with VDD = 3.6 V
+15
dBm
At 433 MHz
+16
dBm
At 433 MHz with VDD = 3.6 V
+15
dBm
At 169 MHz
+16
dBm
At 169 MHz with VDD = 3.6 V
–11
dBm
Within fine step size range
–40
dBm
Within coarse step size range
0.4
dB
Within fine step size range
–75
dBc
4-GFSK 9.6 kbps in 12.5-kHz channel, measured in 100-Hz
bandwidth at 434 MHz (FCC Part 90 Mask D compliant)
–58
dBc
4-GFSK 9.6 kbps in 12.5-kHz channel, measured in 8.75-kHz
bandwidth (ETSI 300 220 compliant)
–61
dBc
2-GFSK 2.4 kbps in 12.5-kHz channel, 1.2-kHz deviation
<–60
dBm
Second Harm, 169 MHz
–39
dBm
Third Harm, 169 MHz
–58
dBm
Second Harm, 433 MHz
–56
dBm
Third Harm, 433 MHz
–51
dBm
Second Harm, 450 MHz
–60
dBm
Third Harm, 450 MHz
–45
dBm
Second Harm, 868 MHz
–40
dBm
Third Harm, 868 MHz
–42
dBm
Second Harm, 915 MHz
56
dBuV/m
Third Harm, 915 MHz
52
dBuV/m
Fourth Harm, 915 MHz
60
dBuV/m
Second Harm, 950 MHz
–58
dBm
Third Harm, 950 MHz
–42
dBm
Max output power
Min output power
Output power step size
Adjacent channel power
Spurious emissions
(not including harmonics)
MIN
TYP
MAX
Harmonics
Transmission at +14 dBm (or maximum allowed in applicable
band where this is less than +14 dBm) using TI reference
design.
Emissions measured according to ARIB T-96 in 950-MHz
band, ETSI EN 300 220 in 169-, 433-, and 868-MHz bands
and FCC Part 15.247 in 450- and 915-MHz band
Fourth harmonic in 915-MHz band will require extra filtering to
meet FCC requirements if transmitting for long intervals (>50ms periods).
Optimum load
Impedance 868-, 915-, and 920MHz bands
35 + j35
Ω
433-MHz band
55 + j25
Ω
169-MHz band
80 + j0
Ω
14
Specifications
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4.12 PLL Parameters
4.12.1 High-Performance Mode
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
Phase noise in 950-MHz band
Phase noise in 868-, 915-, and 920-MHz
bands
Phase noise in 433-MHz band
Phase noise in 169-MHz band
TYP
MAX
UNIT
CONDITION
–99
dBc/Hz
± 10 kHz offset
–99
dBc/Hz
± 100 kHz offset
–123
dBc/Hz
± 1 MHz offset
–99
dBc/Hz
± 10 kHz offset
–100
dBc/Hz
± 100 kHz offset
–122
dBc/Hz
± 1 MHz offset
–106
dBc/Hz
± 10 kHz offset
–107
dBc/Hz
± 100 kHz offset
–127
dBc/Hz
± 1 MHz offset
–111
dBc/Hz
± 10 kHz offset
–116
dBc/Hz
± 100 kHz offset
–135
dBc/Hz
± 1 MHz offset
UNIT
CONDITION
4.12.2 Low-Power Mode
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
Phase noise in 950-MHz band
Phase noise in 868- and 915-MHz bands
Phase noise in 433-MHz band
Phase noise in 169-MHz band
MIN
TYP
MAX
–90
dBc/Hz
± 10 kHz offset
–92
dBc/Hz
± 100 kHz offset
–124
dBc/Hz
± 1 MHz offset
–95
dBc/Hz
± 10 kHz offset
–95
dBc/Hz
± 100 kHz offset
–124
dBc/Hz
± 1 MHz offset
–98
dBc/Hz
± 10 kHz offset
–102
dBc/Hz
± 100 kHz offset
–129
dBc/Hz
± 1 MHz offset
–106
dBc/Hz
± 10 kHz offset
–110
dBc/Hz
± 100 kHz offset
–136
dBc/Hz
± 1 MHz offset
Specifications
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4.13 Wake-up and Timing
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
MIN
TYP
Powerdown to IDLE
IDLE to RX/TX
RX/TX turnaround
RX/TX to IDLE time
MAX
UNIT
CONDITION
0.4
ms
Depends on crystal
166
µs
Calibration disabled
461
µs
Calibration enabled
50
µs
296
µs
Calibrate when leaving RX/TX enabled
0
µs
Calibrate when leaving RX/TX disabled
Frequency synthesizer calibration
391
µs
When using SCAL strobe
Minimum required number of preamble
bytes
0.5
bytes
Time from start RX until valid RSSI
Including gain settling (function of channel
bandwidth).
Programmable for trade-off between speed
and accuracy
0.3
ms
200-kHz channels
UNIT
CONDITION
MHz
It is expected that there will be
degraded sensitivity at multiples of
XOSC/2 in RX, and an increase in
spurious emissions when the RF
channel is close to multiples of XOSC
in TX. We recommend that the RF
channel is kept RX_BW/2 away from
XOSC/2 in RX, and that the level of
spurious emissions be evaluated if the
RF channel is closer than 1 MHz to
multiples of XOSC in TX.
Required for RF front-end gain settling
only. Digital demodulation does not
require preamble for settling.
4.14 32-MHz Crystal Oscillator
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
Crystal frequency
MIN
TYP
32
MAX
33.6
Load capacitance (CL)
10
ESR
pF
60
Start-up time
0.4
Ω
Simulated over operating conditions
ms
Depends on crystal
CONDITION
4.15 32-MHz Clock Input (TCXO)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MAX
UNIT
32
33.6
MHz
High input voltage
1.4
VDD
V
Low input voltage
0
0.6
V
2
ns
1.5
V
Clock frequency
MIN
TYP
TCXO with CMOS output
Rise / Fall time
Clipped sine output
Clock input amplitude (peak-to-peak)
16
0.8
Specifications
TCXO with CMOS output directly
coupled to pin EXT_OSC
TCXO clipped sine output connected
to pin EXT_OSC through series
capacitor
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4.16 32-kHz Clock Input
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Clock frequency
32-kHz clock input pin input high voltage
TYP
MAX
32
UNIT
CONDITION
kHz
0.8×VDD
V
32-kHz clock input pin input low voltage
0.2×VDD
V
MAX
UNIT
4.17 32-kHz RC Oscillator
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Frequency
TYP
32
kHz
Frequency accuracy after calibration
±0.1
%
Initial calibration time
1.6
ms
CONDITION
After calibration
Relative to frequency reference (that
is, 32-MHz crystal or TCXO)
4.18 I/O and Reset
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
Logic input high voltage
MIN
TYP
0.2×VDD
0.8×VDD
CONDITION
V
V
Logic output low voltage
0.2×VDD
Power-on reset threshold
UNIT
V
Logic input low voltage
Logic output high voltage
MAX
0.8×VDD
1.3
V
V
At 4-mA output load or less
Voltage on DVDD pin
4.19 Temperature Sensor
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Temperature sensor range
–40
TYP
MAX
UNIT
85
°C
Temperature coefficient
2.66
mV / °C
Typical output voltage
794
mV
VDD coefficient
1.17
mV / V
CONDITION
Change in sensor output voltage
versus change in temperature
Typical sensor output voltage at TA =
25°C, VDD = 3.0 V
Change in sensor output voltage
versus change in VDD
The CC1121 device can be configured to provide a voltage proportional to temperature on GPIO1. The
temperature can be estimated by measuring this voltage (See Section 4.19, Temperature Sensor). For more
information, see the temperature sensor design note (SWRA415).
Specifications
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4.20 Typical Characteristics
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated.
All measurements performed on CC1120EM_868_915 rev.1.0.1, CC1120EM_955 rev.1.2.1, CC1120EM_420_470 rev.1.0.1
or CC1120EM_169 rev.1.2.
Figure 4-6 was measured at the 50-Ω antenna connector.
60
17
Output Power (dBm)
40
30
20
10
0
16.5
16
15.5
-40
43
47
4B
53
4F
57
5B
63
5F
67
6B
73
6F
77
7B
7F
15
PA power setting
18
20
16
10
Output Power (dBm)
14
80
12
10
8
0
-10
-20
-30
-40
Supply Voltage (V)
Figure 4-3. Output Power vs Voltage
Max Setting, 170 MHz
200 kbps, DEV = 83 kHz (Outer Symbols), 4GFSK
Figure 4-5. Eye Diagram
47
43
4B
53
4F
57
5B
3.5
63
5F
3
67
2.5
6B
2
73
6F
-50
6
7F
7B
Output Power (dBm)
40
Temperature (ºC)
Figure 4-2. Output Power vs Temperature
Max Setting, 170 MHz, 3.6 V
Figure 4-1. TX Current at 868 MHz
vs PA Power Setting
18
0
77
TX Current (mA)
50
PA power setting
Figure 4-4. Output Power at 868 MHz
vs PA Power Setting
Figure 4-6. Output Power vs Load Impedance (+14-dBm Setting)
Specifications
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Typical Characteristics (continued)
Figure 4-8. Phase Noise in 868-MHz Band
3.1
GPIO Output Low Voltage (mV)
GPIO Output High Voltage (V)
9.6 kbps in 12.5-kHz Channel
Figure 4-7. FCC Part 90 Mask D
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
0
5
10
15
20
25
30
35
1400
1200
1000
800
600
400
200
0
0
5
10
15
20
25
30
35
Current (mA)
Current (mA)
Figure 4-9. GPIO Output High Voltage vs Current Being Sourced
Figure 4-10. GPIO Output Low Voltage vs Current Being Sinked
Specifications
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5 Detailed Description
5.1
Block Diagram
Figure 5-1 shows the system block diagram of the CC1121 device.
CC112X
(optional 32kHz
clock intput)
Ultra low power 32kHz
auto-calibrated RC oscillator
4k byte
ROM
Power on reset
MARC
Main Radio Control Unit
Ultra low power 16 bit
MCU
CSn (chip select)
SPI
Serial configuration
and data interface
SI (serial input)
Interrupt and
IO handler
System bus
SO (serial output)
SCLK (serial clock)
eWOR
Enhanced ultra low power
Wake On Radio timer
Configuration and
status registers
Battery sensor /
temp sensor
256 byte
FIFO RAM
buffer
Packet handler
and FIFO control
(optional GPIO0-3)
RF and DSP frontend
Output power ramping and OOK / ASK modulation
I
Fully integrated Fractional-N
Frequency Synthesizer
Q
(optional GPIO for
antenna diversity)
ifamp
XOSC
XOSC_Q2
90dB dynamic
range ADC
(optional bit clock)
Cordic
High linearity
LNA
LNA_N
Data interface with
signal chain access
Channel
filter
ifamp
LNA_P
XOSC_Q1
Modulator
14dBm high
efficiency PA
PA
(optional autodetected
external XOSC / TCXO)
Highly flexible FSK / OOK
demodulator
(optional low jitter serial
data output for legacy
protocols)
90dB dynamic
range ADC
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Figure 5-1. System Block Diagram
5.2
Frequency Synthesizer
At the center of the CC1121 device there is a fully integrated, fractional-N, ultra-high-performance
frequency synthesizer. The frequency synthesizer is designed for excellent phase noise performance,
providing very high selectivity and blocking performance. The system is designed to comply with the most
stringent regulatory spectral masks at maximum transmit power.
Either a crystal can be connected to XOSC_Q1 and XOSC_Q2, or a TCXO can be connected to the
EXT_XOSC input. The oscillator generates the reference frequency for the synthesizer, as well as clocks
for the analog-to-digital converter (ADC) and the digital part. To reduce system cost, CC1121 device has
high-accuracy frequency estimation and compensation registers to measure and compensate for crystal
inaccuracies. This compensation enables the use of lower cost crystals. If a TCXO is used, the CC1121
device automatically turns on and off the TCXO when needed to support low-power modes and Wake-OnRadio operation.
20
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5.3
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
Receiver
The CC1121 device features a highly flexible receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and is down-converted in quadrature (I/Q) to the intermediate frequency (IF). At IF,
the I/Q signals are digitized by the high dynamic-range ADCs.
An advanced automatic gain control (AGC) unit adjusts the front-end gain, and enables the CC1121
device to receive strong and weak signals, even in the presence of strong interferers. High-attenuation
channels and data filtering enable reception with strong neighbor channel interferers. The I/Q signal is
converted to a phase and magnitude signal to support both FSK and OOK modulation schemes.
NOTE
A unique I/Q compensation algorithm removes any problem of I/Q mismatch, thus avoiding
time consuming and costly I/Q image calibration steps.
5.4
Transmitter
The CC1121 transmitter is based on direct synthesis of the RF frequency (in-loop modulation). To use the
spectrum effectively, the CC1121 device has extensive data filtering and shaping in TX mode to support
high throughput data communication in narrowband channels. The modulator also controls power ramping
to remove issues such as spectral splattering when driving external high-power RF amplifiers.
5.5
Radio Control and User Interface
The CC1121 digital control system is built around the main radio control (MARC), which is implemented
using an internal high-performance, 16-bit ultra-low-power processor. MARC handles power modes, radio
sequencing and protocol timing.
A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband
includes support for channel configuration, packet handling, and data buffering. The host MCU can stay in
power-down mode until a valid RF packet is received. This greatly reduces power consumption. When the
host MCU receives a valid RF packet, it burst-reads the data. This reduces the required computing power.
The CC1121 radio control and user interface are based on the widely used the CC1101 transceiver. This
relationship enables an easy transition between the two platforms. The command strobes and the main
radio states are the same for the two platforms.
For legacy formats, the CC1121 device also supports two serial modes:
• Synchronous serial mode: The CC1121 device performs bit synchronization and provides the MCU
with a bit clock with associated data.
• Transparent mode: The CC1121 outputs the digital baseband signal using a digital interpolation filter to
eliminate jitter introduced by digital filtering and demodulation.
5.6
Enhanced Wake-On-Radio (eWOR)
eWOR, using a flexible integrated sleep timer, enables automatic receiver polling with no intervention from
the MCU. The CC1121 device enters RX mode, it listens and then returns to sleep if a valid RF packet is
not received. The sleep interval and duty cycle can be configured to make a trade-off between network
latency and power consumption. Incoming messages are time-stamped to simplify timer resynchronization.
The eWOR timer runs off an ultra-low-power 32-kHz RC oscillator. To improve timing accuracy, the RC
oscillator can be automatically calibrated to the RF crystal in configurable intervals.
Detailed Description
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5.7
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Sniff Mode
The CC1121 device supports very quick start up times, and requires very few preamble bits. Sniff mode
uses these conditions to dramatically reduce the current consumption while the receiver is waiting for
data.
Because the CC1121 can wake up and settle much faster than the duration of most preambles, it is not
required to be in RX mode continuously while waiting for a packet to arrive. Instead, the enhanced WakeOn-Radio feature can be used to put the device into sleep periodically. By setting an appropriate sleep
time, the CC1121 device can wake up and receive the packet when it arrives with no performance loss.
This sequence removes the need for accurate timing synchronization between transmitter and receiver,
and lets the user to trade off current consumption between the transmitter and receiver.
For more information, see the sniff mode design note (SWRA428).
5.8
Antenna Diversity
Antenna diversity can increase performance in a multipath environment. An external antenna switch is
required. The CC1121 device uses one of the GPIO pins to automatically control the switch. The device
also supports differential output control signals typically used in RF switches.
If antenna diversity is enabled, the GPIO alternates between high and low states until a valid RF input
signal is detected. An optional acknowledge packet can be transmitted without changing the state of the
GPIO.
An incoming RF signal can be validated by received signal strength or by using the automatic preamble
detector. Using the automatic preamble detector ensures a more robust system and avoids the need to
set a defined signal strength threshold (such a threshold sets the sensitivity limit of the system).
5.9
Low-Power and High-Performance Mode
The CC1121 device is highly configurable, enabling trade-offs between power and performance based on
the needs of the application. This data sheet describes two modes: low-power mode and highperformance mode. These modes represent configurations where the device is optimized for either power
or performance.
22
Detailed Description
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5.10 WaveMatch
Advanced capture logic locks onto the synchronization word and does not require preamble settling bytes.
Therefore, receiver settling time is reduced to the settling time of the AGC, typically 4 bits.
The WaveMatch feature also greatly reduces false sync triggering on noise, further reducing the power
consumption and improving sensitivity and reliability. The same logic can also be used as a highperformance preamble detector to reliably detect a valid preamble in the channel.
See SWRC046 for more information.
Figure 5-2. Receiver Configurator in SmartRF™ Studio
Detailed Description
Copyright © 2011–2014, Texas Instruments Incorporated
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23
CC1121
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
www.ti.com
6 Typical Application Circuit
NOTE
This section is intended only as an introduction.
Very few external components are required for the operation of the CC1121 device. Figure 6-1 shows a
typical application circuit. The board layout will greatly influence the RF performance of the CC1121
device. Figure 6-1 does not show decoupling capacitors for power pins.
Optional
vdd
25
AVDD_PFD_CHP
vdd
VDD_GUARD
DCPL_PFD_CHP 26
vdd
AVDD_SYNTH2 27
1
AVDD_XOSC 28
2 RESET_N
vdd
LPF1 24
LPF0 23
3 GPIO3
AVDD_SYNTH1 22
4 GPIO2
DCPL_VCO 21
CC1121
5 DVDD
vdd
LNA_N 20
6 DCPL
LNA_P 19
7 SI
TRX_SW 18
8 SCLK
N.C.
16
AVDD_RF
15
vdd
13 AVDD_IF
vdd
14 RBIAS
12 DVDD
vdd
CSn
11
10 GPIO0
9 SO (GPIO1)
PA 17
vdd
vdd
DCPL_XOSC 29
(optional control pin
from CC1121)
XOSC_Q1 30
EXT_XOSC 32
XOSC/
TCXO
XOSC_Q2 31
32 MHz
crystal
MCU connection
SPI interface and
optional gpio pins
Figure 6-1. Typical Application Circuit
For more information, see the reference designs available for the CC1121 device in Section 7.2,
Documentation Support.
24
Typical Application Circuit
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: CC1121
CC1121
www.ti.com
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
7 Device and Documentation Support
7.1
Device Support
7.1.1
Development Support
7.1.1.1
Configuration Software
The CC1121 device can be configured using the SmartRF Studio software (SWRC046). The SmartRF
Studio software is highly recommended for obtaining optimum register settings, and for evaluating
performance and functionality.
7.1.2
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, CC1121). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RHB) and the temperature range (for example, blank is the default commercial
temperature range) provides a legend for reading the complete device name for any CC1121 device.
For orderable part numbers of CC1121 devices in the QFN package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
Device and Documentation Support
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1121
25
CC1121
SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
7.2
www.ti.com
Documentation Support
The following documents supplement the CC1121 processor. Copies of these documents are available on
the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
7.3
SWRR106
CC112x IPC 868- and 915-MHz 2-layer Reference Design
SWRR107
CC112x IPC 868- and 915-MHz 4-layer Reference Design
SWRC221
CC1120EM 420- to 470-MHz Reference Design
SWRC224
CC1121EM 868- to 915-MHz Reference Design
SWRC223
CC1120EM 955-MHz Reference Design
SWRC046
SmartRF Studio Software
SWRA428
CC112x/CC120x Sniff Mode Application Note
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.4
Trademarks
SmartRF, E2E are trademarks of Texas Instruments.
7.5
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.6
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
Device and Documentation Support
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: CC1121
CC1121
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SWRS111F – JUNE 2011 – REVISED OCTOBER 2014
8 Mechanical Packaging and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2014, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: CC1121
27
PACKAGE OPTION ADDENDUM
www.ti.com
30-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC1121RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC1121
CC1121RHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC1121
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-May-2018
Addendum-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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