Texas Instruments | CC2544 System-on-Chip for 2.4-GHz USB Applications (Rev. D) | Datasheet | Texas Instruments CC2544 System-on-Chip for 2.4-GHz USB Applications (Rev. D) Datasheet

Texas Instruments CC2544 System-on-Chip for 2.4-GHz USB Applications (Rev. D) Datasheet
CC2544
www.ti.com
SWRS103D – JUNE 2011 – REVISED MAY 2012
System-on-Chip for 2.4-GHz USB Applications
FEATURES
1
•
•
•
RF section
– Single-Chip 2.4-GHz RF Transceiver and
MCU
– Data Rates and Modulation Formats:
– 2-Mbps GFSK, 320-kHz Deviation
– 2-Mbps GFSK, 500-kHz Deviation
– 1-Mbps GFSK, 160-kHz Deviation
– 1-Mbps GFSK, 250-kHz Deviation
– 500-kbps MSK
– 250-kbps GFSK, 160-kHz Deviation
– 250-kbps MSK
– Excellent Link Budget, Enabling Long
Range Without External Front-Ends
– Programmable Output Power up to 4 dBm
– Excellent Receiver Sensitivity (–88 dBm at
2 Mbps)
– Suitable for Systems Targeting Compliance
With Worldwide Radio Frequency
Regulations: ETSI EN 300 328 and EN 300
440 Category 2 (Europe), FCC CFR47 Part
15 (US), and ARIB STD-T66 (Japan)
– Accurate RSSI Function
Layout
– Few External Components
– Reference Designs Available
– 32-pin 5-mm × 5-mm QFN (8 General I/O
Pins) Package
Low Power
– Active Mode RX: 22.5 mA
– Active Mode TX (0 dBm): 27 mA
– Power Mode 1 (4-µs Wake-Up): 1 mA
– Wide Supply-Voltage Range
– 3.3V LDO Output
– Supply Range: 2 V–3.6 V
– USB 5-V Regulator: 4 V–5.45 V
•
•
Microcontroller
– High-Performance and Low-Power 8051
Microcontroller Core With Code Prefetch
– 32-KB Flash Program Memory
– 2 KB SRAM
– Hardware Debug Support
– Extensive Baseband Automation, Including
Auto-Acknowledgement and Address
Decoding
Peripherals
– Full Speed USB 2.0
– 6 Endpoints (Endpoint 0 and 5 IN/OUT
Endpoints)
– Internal Pullup for D+
– 5-V to 3.3-V Regulator
– Powerful Two-Channel DMA
– General-Purpose Timers (One 16-Bit, Two
8-Bit)
– Radio Timer, 40-Bit
– IR Generation Circuitry
– Several Oscillators:
– 32-MHz XOSC
– 16-MHz RCOSC
– 32-kHz RCOSC
– 32-kHz Sleep Timer With Capture
– AES Security Coprocessor
– UART/SPI Serial Interface
– 8 General-Purpose I/O pins (6 × 4-mA and 2
× 20-mA Drive Strength)
– Watchdog Timer
– True Random-Number Generator
APPLICATIONS
•
•
•
Proprietary 2.4-GHz Systems
Human Interface Devices (USB Dongle)
Consumer Electronics
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
CC2544
SWRS103D – JUNE 2011 – REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CC2544 is an optimized system-on-chip (SoC) solution for USB applications with datarates upto 2Mbps built
with low bill-of-material cost. The CC2544 combines the excellent performance of a leading RF transceiver with a
single-cycle 8051 compliant CPU, 32-KB in-system programmable flash memory, up to 2-KB RAM, and many
other powerful features.
The CC2544 is compatible with the CC2541/CC2543/CC2545. It comes in a 5-mm × 5-mm QFN32 package, with
SPI/UART/USB interface. The CC2544 comes complete with reference designs from Texas Instruments.
The devices target wireless consumer and HID applications. The CC2544 is ideal for USB dongle applications.
For block diagram, see Figure 7
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Supply voltage VBUS
Supply voltage VDD
All supply pins must have the same voltage
Voltage on any digital pin
MIN
MAX
UNIT
–0.3
5.5
V
–0.3
≤3.9
V
–0.3
≤3.9
V
10
dBm
125
°C
2
kV
750
V
Input RF level
Storage temperature range
ESD
(1)
(2)
–40
All pins, according to human-body model, JEDEC STD 22,
method A114 (HBM)
(2)
According to charged-device model, JEDEC STD 22, method
C101 (CDM)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CAUTION: ESD sensitive device. Precautions should be used when handing the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
TEST CONDITIONS
Operating ambient temperature range, TA
MIN
MAX
UNIT
–40
85
°C
Operating supply voltage VBUS
Optional to use this regulator
4
5.45
V
Operating supply voltage VDD
All supply pins must have same voltage
2
3.6
V
2
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SWRS103D – JUNE 2011 – REVISED MAY 2012
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2544EM reference design with TA = 25°C and VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER
RX mode, no peripherals active, low MCU activity
I core– Core current
consumption
22.5
mA
TX mode, 0-dBm output power, no peripherals active, low MCU
activity
27
mA
TX mode, 4-dBm output power, no peripherals active, low MCU
activity
30
mA
Active mode, 16-MHz RCOSC, Low MCU activity
4
mA
Active mode, 32-MHz clock frequency, low MCU activity
7
mA
Power mode 0, CPU clock halted, all peripherals on, no clock
division, 32-MHz crystal selected
6
mA
3.5
mA
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.753-kHz RCOSC, POR, BOD,
and sleep timer active; RAM and register retention
1
mA
Timer 1 (16-bit). Timer running, 32-MHz XOSC used
90
µA
Radio timer(40 bit). Timer running, 32-MHz XOSC used
90
µA
Timer 3 (8-bit). Timer running, 32-MHz XOSC used
60
µA
Timer 4 (8-bit). Timer running, 32-MHz XOSC used
70
µA
Sleep timer. Including 32.753-kHz RCOSC
0.6
µA
Power mode 0, CPU clock halted, all peripherals on, clock
division at max. (Limits max. speed in peripherals except
radio), 32-MHz crystal selected
I peri– Peripheral
current consumption
(Adds to core
current Icore for each
peripheral unit
activated)
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2544EM reference design with TA = 25°C and VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Power mode 1 → Active
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC.
Active → TX or RX
4
µs
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with
32-MHz XOSC OFF.
410
µs
With 32-MHz XOSC initially on.
160
µs
130
µs
RX/TX turnaround
RADIO PART
RF frequency range
Programmable in 1-MHz steps
Data rates and modulation
formats
2 Mbps, GFSK 320-kHz deviation
2-Mbps, GFSK 500 kHz deviation
1-Mbps, GFSK 160 kHz deviation
1-Mbps, GFSK 250 kHz deviation
500 kbps, MSK
250 kbps, GFSK 160 kHz deviation
250 kbps, MSK
2380
2495
MHz
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SWRS103D – JUNE 2011 – REVISED MAY 2012
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RF RECEIVE SECTION
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, and fC = 2440
MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER
Receiver sensitivity
–84
dBm
0
dBm
Wanted signal at -67 dBm
–15
dB
±2-MHz offset, wanted signal –67 dBm
–5
±4-MHz offset, wanted signal –67 dBm
30
±6-MHz offset, wanted signal –67 dBm
40
>12-MHz offset, wanted signal –67 dBm
42
1-MHz resolution. Wanted signal –67 dBm, f < 2 GHz
Two exception frequencies with poorer performance
–35
1-MHz resolution. Wanted signal –67 dBm, 2 GHz > f < 3
GHz
Two exception frequencies with poorer performance
–36
1-MHz resolution. Wanted signal –67 dBm, f > 3GHz
Two exception frequencies with poorer performance
–12
Intermodulation
Wanted signal –64 dBm, 1st interferer is CW, 2nd interferer
is GFSK-modulated signal. Offsets of interferers are:
6 and 12 MHz
8 and 16 MHz
10 and 20 MHz
–43
Frequency error
tolerance (2)
Including both initial tolerance and drift. Limit set to
minimum sensitivity of –70dBm, 250K byte payload
–300
300
kHz
Symbol rate error
tolerance (3)
Limit set to minimum sensitivity of –70 dBm, 250K byte
payload
–120
120
ppm
Saturation (1)
Co-channel rejection
In-band blocking rejection
Out-of-band blocking
rejection
dB
dBm
dBm
2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Receiver sensitivity
Saturation
(1)
Co-channel rejection
In-band blocking rejection
–88
dBm
3
dBm
Wanted signal at -67 dBm
-9
dB
±2-MHz offset, wanted signal –67 dBm
-3
±4-MHz offset, wanted signal –67 dBm
33
±6-MHz offset, wanted signal –67 dBm
49
>12-MHz offset, wanted signal –67 dBm
40
dB
Frequency error
tolerance (2)
Including both initial tolerance and drift. Sensitivity better
than –70 dBm. 250-byte payload
–300
300
kHz
Symbol-rate error
tolerance (3)
Sensitivity better than –70 dBm. 250-byte payload
–120
120
ppm
1 Mbps, GFSK, 250-kHz Deviation, 0.1% BER
Receiver sensitivity
-91
dBm
5
dBm
Wanted signal at –67 dBm
-6
dB
±2-MHz offset, wanted signal –67 dBm
28
±4-MHz offset, wanted signal –67 dBm
31
±6-MHz offset, wanted signal –67 dBm
40
>12-MHz offset, wanted signal –67 dBm
49
Saturation (1)
Co-channel rejection
In-band blocking rejection
dB
Frequency error
tolerance (2)
Including both initial tolerance and drift. Sensitivity better
than –70 dBm. 250-byte payload
–250
250
kHz
Symbol-rate error
tolerance (3)
Sensitivity better than –70 dBm. 250-byte payload
–80
80
ppm
(1)
(2)
(3)
4
AGC enabled
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
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SWRS103D – JUNE 2011 – REVISED MAY 2012
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, and fC = 2440
MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1 Mbps, GFSK, 160-kHz Deviation, 0.1% BER
Receiver sensitivity
-87
dBm
5
dBm
Wanted signal at -67 dBm
-9
dB
±2-MHz offset, wanted signal –67 dBm
26
±4-MHz offset, wanted signal –67 dBm
30
±6-MHz offset, wanted signal –67 dBm
40
>12-MHz offset, wanted signal –67 dBm
46
Saturation (1)
Co-channel rejection
In-band blocking rejection
dB
Frequency error
tolerance (2)
Including both initial tolerance and drift. Sensitivity better
than –70 dBm. 250-byte payload
–250
250
kHz
Symbol-rate error
tolerance (3)
Sensitivity better than –70 dBm. 250-byte payload
–80
80
ppm
500 kbps, MSK, 0.1% BER
Receiver sensitivity
-96
dBm
5
dBm
Wanted signal at -67 dBm
-5
dB
±2-MHz offset, wanted signal –67 dBm
31
±4-MHz offset, wanted signal –67 dBm
31
±6-MHz offset, wanted signal –67 dBm
45
>12-MHz offset, wanted signal –67 dBm
54
Saturation (4)
Co-channel rejection
In-band blocking rejection
dB
Frequency error
tolerance (5)
Including both initial tolerance and drift. Sensitivity better
than –70 dBm. 250-byte payload
–150
150
kHz
Symbol-rate error
tolerance (6)
Sensitivity better than –70 dBm. 250-byte payload
–60
60
ppm
(4)
(5)
(6)
AGC enabled
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
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RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, and fC = 2440
MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250 kbps, GFSK, 160-kHz Deviation, 0.1% BER
Receiver sensitivity
-95
dBm
5
dBm
Wanted signal at –67 dBm
-9
dB
±2-MHz offset, wanted signal –67 dBm
31
±4-MHz offset, wanted signal –67 dBm
31
±6-MHz offset, wanted signal –67 dBm
55
>12-MHz offset, wanted signal –67 dBm
53
Saturation (7)
Co-channel rejection
In-band blocking rejection
dB
Frequency error
tolerance (8)
Including both initial tolerance and drift. Sensitivity better
than –70 dBm. 250-byte payload
–150
150
kHz
Symbol-rate error
tolerance (9)
Sensitivity better than –70 dBm. 250-byte payload
–60
60
ppm
250 kbps, MSK, 0.1% BER
Receiver sensitivity
–95
dBm
5
dBm
Wanted signal at –67 dBm
–5
dB
±2-MHz offset, wanted signal –67 dBm
31
±4-MHz offset, wanted signal –67 dBm
31
±6-MHz offset, wanted signal –67 dBm
45
>12-MHz offset, wanted signal –67 dBm
54
Saturation (7)
Co-channel rejection
In-band blocking rejection
dB
Frequency error
tolerance (8)
Including both initial tolerance and drift. Sensitivity better
than –70 dBm. 250-byte payload
–150
150
kHz
Symbol-rate error
tolerance (9)
Sensitivity better than –70 dBm. 250-byte payload
–60
60
ppm
ALL RATES/FORMATS
Spurious emission in RX.
Conducted measurement
f < 1 GHz
–67
dBm
Spurious emission in RX.
Conducted measurement
f > 1 GHz
–57
dBm
(7)
(8)
(9)
AGC enabled
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
RF TRANSMIT SECTION
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, and fC = 2440
MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output power, maximum
setting
Delivered to a single-ended 50-Ω load through a balun
using maximum recommended output power setting.
4
dBm
Output power, minimum
setting
Delivered to a single-ended 50-Ω load through a balun
using minimum recommended output power setting.
–20
dBm
Programmable output power
range
Delivered to a single-ended 50-Ω load through a balun.
24
dB
Spurious emission in TX.
Conducted measurement.
f < 1 GHz
–46
dBm
Spurious emission in TX.
Conducted measurement.
f > 1 GHz
–44
dBm
Optimum load impedance
Differential impedance as seen from the RF port (RF_P
and RF_N) toward the antenna
70 + j30
Ω
6
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SWRS103D – JUNE 2011 – REVISED MAY 2012
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Crystal frequency
MAX
32
Crystal frequency accuracy
requirement
2-Mbps data rate
UNIT
MHz
–60
60
ppm
Equivalent series resistance
6
60
Ω
Crystal shunt capacitance
1
7
pF
Crystal load capacitance
10
16
Start-up time
pF
0.25
The crystal oscillator must be in power down for a guard
time before it is used again. This requirement is valid for
all modes of operation. The need for power-down guard
time can vary with crystal type and load.
Power-down guard time
ms
3
ms
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
Calibrated frequency
TEST CONDITIONS
MIN
TYP
(1)
kHz
±0.2%
Temperature coefficient (2)
(3)
Calibration time (4)
(1)
(2)
(3)
(4)
UNIT
32.753
Frequency accuracy after calibration
Supply-voltage coefficient
MAX
0.4
%/ºC
3
%/V
2
ms
The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
Frequency drift when temperature changes after calibration
Frequency drift when supply voltage changes after calibration
The 32-kHz RC oscillator is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator is performed, while
SLEEPCMD.OSC32K_CALDIS is set to 0.
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Calibrated frequency
TYP
16
Uncalibrated frequency accuracy
±18%
Frequency accuracy after calibration (1)
±0.6%
MAX
UNIT
MHz
Start-up time
10
µs
Initial calibration time
50
µs
(1)
The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
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RSSI CHARACTERISTICS
Measured on Texas Instruments CC2544 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
RSSI range (1)
60
dB
RSSI offset (1)
97
dBm
Absolute uncalibrated accuracy (1)
±6
dB
1
dB
RSSI range (1)
60
dB
(1)
101
dBm
±3
dB
1
dB
Step size (LSB value)
All Other Rates/Formats
RSSI offset
Absolute uncalibrated accuracy (1)
Step size (LSB value)
(1)
Assuming CC2544 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
Phase noise, unmodulated carrier
TEST CONDITIONS
MIN
TYP
At ±1 MHz from carrier
–112
At ±2 MHz from carrier
–119
At ±5 MHz from carrier
–124
MAX
UNIT
dBc/Hz
USB BUS 5-V to 3.3-V REGULATOR
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage, typical minimum
4
Input voltage, typical maximum
5.45
V
Current limit
100
mA
Start-up time
0.8
ms
Output voltage
3.3
V
8
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SWRS103D – JUNE 2011 – REVISED MAY 2012
DC CHARACTERISTICS
Measured on Texas Instruments CC2544EM reference design with TA = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
V
50
nA
Logic-0 input voltage
Logic-1 input voltage
2.5
Logic-0 input current
–50
Logic-1 input current
–50
V
50
I/O pin pullup and pulldown resistors
nA
20
Logic-0 output voltage 4-mA pins
Output load 4 mA
Logic-1 output voltage 4-mA pins
Output load 4 mA
Logic-0 output voltage 20-mA pins
Output load 20 mA
Logic-1 output voltage, 20-A pins
Outpu load 20 mA
kΩ
0.5
V
2.4
V
0.5
V
2.4
V
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
RESET_N low duration
See item 1, Figure 1. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
1
µs
Interrupt pulse duration
See item 2, Figure 1.This is the shortest pulse that is recognized as
an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
t1
SCK period
TEST CONDITIONS
MIN
Master, RX and TX
250
Slave, RX and TX
250
TYP MAX
UNIT
ns
SCK duty cycle
Master
t2
SSN low to SCK,
Figure 2 and Figure 3
Master
63
50%
Slave
63
t3
SCK to SSN high
Master
63
Slave
63
t4
MOSI early out
Master, load = 10 pF
t5
MOSI late out
Master, load = 10 pF
t6
MISO setup
Master
90
ns
t7
MISO hold
Master
10
ns
ns
ns
7
ns
10
ns
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SPI AC CHARACTERISTICS (continued)
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
SCK duty cycle
Slave
t10
MOSI setup
Slave
35
t11
MOSI hold
Slave
10
t8
MISO early out
Slave, load = 10 pF
0
ns
t9
MISO late out
Slave, load = 10 pF
95
ns
Operating frequency
50%
UNIT
ns
ns
ns
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
X
t6
MISO
t5
D1
t7
D0
X
X
T0478-01
Figure 2. SPI Master AC Characteristics
SCK
t2
t3
SSN
t8
D0
MISO
X
t10
MOSI
X
t9
D1
t11
D0
X
T0479-01
Figure 3. SPI Slave AC Characteristics
10
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DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
fclk_dbg
Debug clock frequency (see Figure 4)
t1
Allowed high pulse on clock (see Figure 4)
35
ns
t2
Allowed low pulse on clock (see Figure 4)
35
ns
t3
EXT_RESET_N low to first falling edge on debug
clock (see Figure 5)
167
ns
t4
Falling edge on clock to EXT_RESET_N high (see
Figure 5)
83
ns
t5
EXT_RESET_N high to first debug command (see
Figure 5)
83
ns
t6
Debug data setup (see Figure 6)
2
ns
t7
Debug data hold (see Figure 6)
4
ns
t8
Clock-to-data delay (see Figure 6)
Load = 10 pF
30
ns
Time
DE BUG_ CLK
P1_2
t1
t2
1/fclk_dbg
T0436-44
Figure 4. Debug Clock – Basic Timing
Ti me
DE BUG_ CLK
P1_2
RESET_ N
t3
t4
t5
T0437-44
Figure 5. Debug Enable Timing
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Time
DEBUG_ CLK
P1_2
DEBUG_DATA
(to CC2544)
P1_3
DEBUG_DATA
(from CC2544)
P1_3
t6
t8
t7
T0438-03
Figure 6. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
12
TEST CONDITIONS
MIN
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
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1.5
TYP
MAX
UNIT
tSYSCLK
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DEVICE INFORMATION
PIN DESCRIPTIONS
VDD
P1_3
P1_2
VSS
VDD
32
31
30
29
28
27
26
RBIAS
VSS
DCPL1
CC2544
RHB Package
(Top View)
25
24
VDD
2
23
VDD
VDD
3
22
VDD
DCPL2
4
21
RF_N
VBUS
5
20
RF_P
P1_0
6
19
VDD
P1_1
7
18
XOSC2
VDD
8
17
16
XOSC1
10
11
12 13
14
15
P0_2
P0_3
RESET_N
VDD
9
VDD
VSS
Thermal Pad
VSS
USB_N
P0_1
1
P0_0
USB_P
P0048-19
NOTE: The exposed ground pad must be connected to a solid ground plane; this is the main ground connection for the chip.
Table 1. Pin Description Table
NAME
PIN
DESCRIPTION
DCPL1
31
1.8-V reg. decouple
DCPL2
4
3.3-V reg. decouple
P0_0
9
GPIO
P0_1
10
GPIO
P0_2
13
GPIO
P0_3
14
GPIO
P1_0
6
GPIO/20 mA
P1_1
7
GPIO/20 mA
P1_2
28
GPIO/debug clock
P1_3
29
GPIO/debug data
RBIAS
25
External precision bias resistor for reference current
RESET_N
15
Reset, active-low
RF_N
21
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
20
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
USB_P
1
USB module
USB_N
2
USB module
VBUS
5
5-V power
VDD
3
AVDD
VDD
8, 12
IOVDD
VDD
16, 19, 22, 23, 24 AVDD
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Table 1. Pin Description Table (continued)
NAME
VDD
PIN
DESCRIPTION
26
AVDD_GUARD
VDD
30
IOVDD
VSS
11, 27
VSS
32
VSS
Ground pad
Optional IOVSS
USB ground
Must be connected to solid ground as this is the main ground connection for the chip.
XOSC1
17
32-MHz crystal oscillator pin 1or external-clock input
XOSC2
18
32-MHz crystal oscillator pin 2
14
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BLOCK DIAGRAM
A block diagram of the CC2544 is shown in Figure 7. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given. For more details, see the
CC2543/44/45 User’s Guide (SWRU283).
WATCHDOG
TIMER
RESET
XOSC_Q2
32-MHz
CRYSTAL OSC
XOSC_Q1
CLOCK MUX
and
CALIBRATION
HIGHSPEED
RC-OSC
DEBUG
INTERFACE
ON-CHIP VOLTAGE
REGULATOR
VDD (2 V–3.6 V)
POWER ON RESET
BROWN OUT
5 V to 3.3 V
VOLTAGE REGULATOR
SFR Bus
RESET_N
DCOUPL
VBUS (4 V –5.45 V)
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
PDATA
XRAM
8051 CPU
CORE
IRAM
SFR
RAM
SRAM
FLASH
FLASH
MEMORY
ARBITRATOR
P1_3
P1_2
DMA
P1_1
UNIFIED
P1_0
IRQ CTRL
FLASH CTRL
1 KB SRAM
FIFOCTRL
RADIO Arbiter
PSEUDO-RANDOM
NUMBER
GENERATOR
P0_2
RADIO REGISTERS
Link Layer Engine
AES
ENCRYPTION
AND
DECRYPTION
SFR Bus
P0_0
I/O CONTROLLER
P0_1
DEMODULATOR
SYNTH
P0_3
MODULATOR
USB_N
USB
RECEIVE
USART 0
FREQUENCY
SYNTHESIZER
USB_P
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(RADIO TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
DIGITAL
ANALOG
TIMER 4 (8-Bit)
MIXED
B0301-09
Figure 7. CC2544 Block Diagram
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BLOCK DESCRIPTIONS
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 15-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 7 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 2-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.
The 32-KB flash block provides in-circuit programmable non-volatile program memory for the device, and maps
into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile two-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USART, timers, etc.)
can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or
XREG address and flash/SRAM.
The interrupt controller services a total of 15 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (when
in sleep mode, the device is in low-power mode PM1).
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between several different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that uses an internal 32.753-kHz RC oscillator. The sleep timer runs
continuously in all operating modes. Typical applications of this timer are as a real-time counter or as a wake-up
timer to get out of power mode 1.
A built-in watchdog timer allows the CC2544 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
16
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Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit
overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture
register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the
exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflowcompare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and
TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has
its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured
as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling
scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
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TYPICAL CHARACTERISTICS
RX CURRENT
vs
TEMPERATURE
TX CURRENT
vs
TEMPERATURE
23.5
31.0
22.5
Current (mA)
Current (mA)
23.0
31.5
3.3-V Supply
−70 dBm Input
22.0
21.5
21.0
20.5
−40
3.3-V Supply
TXPOWER = 4 dBm
30.5
30.0
29.5
29.0
−20
0
20
40
Temperature (°C)
60
80
28.5
−40
−20
0
20
40
Temperature (°C)
Figure 8.
Figure 9.
RX SENSITIVITY
vs
TEMPERATURE
TX POWER
vs
TEMPERATURE
−80
5
−82
4
Level (dBm)
Sensitivity (dBm)
−81
−83
−84
2
−85
1
−20
0
20
40
Temperature (°C)
60
80
3.3-V Supply
TXPOWER = 4 dBm
3
0
−40
Figure 10.
18
80
6
3.3-V Supply
−86
−40
60
−20
0
20
40
Temperature (°C)
60
80
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
RX CURRENT
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
23.0
22.8
30.5
T = 25°C
−70 dBm Input
T = 25°C
TXPOWER = 4 dBm
22.6
30.0
Current (mA)
Current (mA)
22.4
22.2
22.0
21.8
29.5
21.6
29.0
21.4
21.2
21.0
2.0
2.2
2.4
2.6
2.8
3.0
Supply Voltage (V)
3.2
3.4
3.6
28.5
2.0
2.2
2.4
2.6
2.8
3.0
Supply Voltage (V)
Figure 12.
Figure 13.
RX SENSITIVITY
vs
SUPPLY VOLTAGE
TX POWER
vs
SUPPLY VOLTAGE
−82
3.6
T = 25°C
TXPOWER = 4 dBm
5
Level (dBm)
−83
Sensitivity (dBm)
3.4
6
T = 25°C
−84
−85
−86
2.0
3.2
4
3
2.2
2.4
2.6
2.8
3.0
Supply Voltage (V)
3.2
3.4
3.6
2
2.0
Figure 14.
2.2
2.4
2.6
2.8
3.0
Supply Voltage (V)
3.2
3.4
3.6
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
vs
FREQUENCY
TX POWER
vs
FREQUENCY
−82
6
3.3-V Supply
T = 25°C
3.3-V Supply
T = 25°C
TXPOWER = 4 dBm
5
Level (dBm)
Sensitivity (dBm)
−83
−84
−85
−86
2400
4
3
2420
2440
2460
Frequency (MHz)
2
2400
2480
2420
2440
2460
Frequency (MHz)
Figure 16.
2480
Figure 17.
RX INTERFERER REJECTION (SELECTIVITY)
vs
INTERFERER FREQUENCY
85
75
Rejection (dB)
55
3.3-V Supply
T = 25°C
Wanted signal at 2426 MHz
35
15
−5
−25
Wanted signal 3 dB above sensitivity limit
Wanted signal 10 dB above sensitivity limit
Wanted signal 30 dB above sensitivity limit
Wanted signal 50 dB above sensitivity limit
−45
−65
−15
−10
−5
0
5
Frequency Offset (MHz)
10
15
Figure 18.
20
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2544. A typical application circuit is shown in
Figure 19. For suggestions of component values other than those listed in Table 2, see reference design
CC2544EM. The performance stated in this data sheet is only valid for the CC2544EM reference design. To
obtain similar performance, the reference design should be copied as closely as possible.
C311
D+
D–
R21
C21
RBIAS 25
VSS 27
VDD 26
P1_2 28
VDD 30
P1_3 29
VSS 32
C11
Antenna
(50 W)
1
USB_P
VDD 24
2
USB_N
VDD 23
3
VDD
VDD 22
4
DCPL2
RF_N 21
CC2544
VBUS
6
P1_0
7
P1_1
XOSC2 18
8
VDD
XOSC1 17
16 VDD
VDD 19
15 RESET_N
14 P0_3
13 P0_2
9
11 VSS
DIE ATTACH PAD
P0_0
C41
RF_P 20
5
12 VDD
4-V to 5.45-V
Power Supply
10 P0_1
R11
DCPL1 31
R251
C171
C181
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
S0383-06
Figure 19. CC2544 Application Circuit
Table 2. Overview of External Components (Excluding Balun, Crystal and Supply Decoupling Capacitors)
Component
Description
Value
C11
USB D+ decoupling
47 pF
C21
USB D– decoupling
47 pF
C41
Decoupling capacitor for the internal 5V-3.3V digital voltage
regulator
1 µF
C311
Decoupling capacitor for the internal 1.8V digital voltage
regulator
1 µF
R11
USB D+ series resistor
33 Ω
R21
USB D– series resistor
33 Ω
R251
Precision resistor ±1%, used for internal biasing
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2544EM,
for recommended balun.
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Crystal
An external 32-MHz crystal with two loading capacitors is used for the 32-MHz crystal oscillator. The load
capacitance seen by the 32-MHz crystal is given by:
1
CL =
+ Cparasitic
1
1
+
C171 C181
(1)
A series resistor may be used to comply with ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C311) for stable operation.
On-Chip 5-V to 3.3-V USB Voltage Regulator Decoupling
The 5-V to 3.3-V on-chip voltage regulator supplies the 1.8-V on-chip voltage regulator. This regulator requires a
decoupling capacitor (C41) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
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REVISION HISTORY
Changes from Original (June 2011) to Revision A
•
Page
Changes to the Product Preview data sheet ........................................................................................................................ 1
Changes from Revision A (March 2012) to Revision B
•
Page
Changed From: (–84 dBm at 2 Mbps) To: (–88 dBm at 2 Mbps) ......................................................................................... 1
Changes from Revision B (April 2012) to Revision C
•
Page
Changed the device From: Preview To: Production ............................................................................................................. 1
Changes from Revision C (April 2012) to Revision D
•
Page
Added the Description .......................................................................................................................................................... 2
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PACKAGE OPTION ADDENDUM
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9-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC2544RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2544
CC2544RHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2544
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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9-Mar-2018
Addendum-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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