Texas Instruments | Low-Cost Low-Power 2.4 GHz RF Transceiver (Rev. C) | Datasheet | Texas Instruments Low-Cost Low-Power 2.4 GHz RF Transceiver (Rev. C) Datasheet

Texas Instruments Low-Cost Low-Power 2.4 GHz RF Transceiver (Rev. C) Datasheet
CC2500
CC2500
Low-Cost Low-Power 2.4 GHz RF Transceiver
Applications
 2400-2483.5 MHz ISM/SRD band systems
 Consumer electronics
 Wireless game controllers
 Wireless audio
 Wireless keyboard and mouse
 RF enabled remote controls
Product Description
19
18
17
16
8
9
10
CC2500 provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication, and wake-on-radio.
20
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data rate up to 500 kBaud.
7
controlled via an SPI interface. In a typical
system, the CC2500 will be used together with
a microcontroller and a few additional passive
components.
6
The CC2500 is a low-cost 2.4 GHz transceiver
designed for very low-power wireless applications. The circuit is intended for the 24002483.5 MHz ISM (Industrial, Scientific and
Medical) and SRD (Short Range Device)
frequency band.
The main operating parameters and the 64byte transmit/receive FIFOs of CC2500 can be
Key Features
RF Performance






High sensitivity (–104 dBm at 2.4 kBaud,
1% packet error rate)
Low current consumption (13.3 mA in RX,
250 kBaud, input well above sensitivity
limit)
Programmable output power up to +1 dBm
Excellent receiver selectivity and blocking
performance
Programmable data rate from 1.2 to 500
kBaud
Frequency range: 2400 – 2483.5 MHz


Digital Features

Analog Features






OOK, 2-FSK, GFSK, and MSK supported
Suitable for frequency hopping and multichannel systems due to a fast settling
SWRS040C
frequency synthesizer with 90 us settling
time
Automatic
Frequency
Compensation
(AFC) can be used to align the frequency
synthesizer to the received centre
frequency
Integrated analog temperature sensor
Flexible support for packet oriented
systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling
Efficient SPI interface: All registers can be
programmed with one “burst” transfer
Digital RSSI output
Programmable channel filter bandwidth
Programmable
Carrier
Sense
(CS)
indicator
Page 1 of 89
CC2500




Programmable Preamble Quality Indicator
(PQI) for improved protection against false
sync word detection in random noise
Support for automatic Clear Channel
Assessment (CCA) before transmitting (for
listen-before-talk systems)
Support for per-package Link Quality
Indication (LQI)
Optional automatic whitening and dewhitening of data
General




Low-Power Features




400 nA SLEEP mode current consumption
Fast startup time: 240 us from SLEEP to
RX or TX mode (measured on EM design)
Wake-on-radio functionality for automatic
low-power RX polling
Separate 64-byte RX and TX data FIFOs
(enables burst mode data transmission)
SWRS040C

Few external components: Complete onchip frequency synthesizer, no external
filters or RF switch needed
Green package: RoHS compliant and no
antimony or bromine
Small size (QLP 4x4 mm package, 20
pins)
Suited for systems compliant with EN 300
328 and EN 300 440 class 2 (Europe),
FCC CFR47 Part 15 (US), and ARIB STDT66 (Japan)
Support
for
asynchronous
and
synchronous serial receive/transmit mode
for backwards compatibility with existing
radio communication protocols
Page 2 of 89
CC2500
Abbreviations
Abbreviations used in this data sheet are described below.
ACP
ADC
AFC
AGC
AMR
ARIB
BER
BT
CCA
CFR
CRC
CS
CW
DC
DVGA
ESR
FCC
FEC
FIFO
FHSS
2-FSK
GFSK
IF
I/Q
ISM
LBT
LC
LNA
LO
LQI
LSB
MCU
Adjacent Channel Power
Analog to Digital Converter
Automatic Frequency Offset Compensation
Automatic Gain Control
Automatic Meter Reading
Association of Radio Industries and Businesses
Bit Error Rate
Bandwidth-Time product
Clear Channel Assessment
Code of Federal Regulations
Cyclic Redundancy Check
Carrier Sense
Continuous Wave (Unmodulated Carrier)
Direct Current
Digital Variable Gain Amplifier
Equivalent Series Resistance
Federal Communications Commission
Forward Error Correction
First-In-First-Out
Frequency Hopping Spread Spectrum
Frequency Shift Keying
Gaussian shaped Frequency Shift Keying
Intermediate Frequency
In-Phase/Quadrature
Industrial, Scientific and Medical
Listen Before Transmit
Inductor-Capacitor
Low Noise Amplifier
Local Oscillator
Link Quality Indicator
Least Significant Bit
Microcontroller Unit
SWRS040C
MSB
MSK
NA
NRZ
OOK
PA
PCB
PD
PER
PLL
POR
PQI
PQT
RCOSC
QPSK
QLP
RC
RF
RSSI
RX
SMD
SNR
SPI
SRD
T/R
TX
VCO
WLAN
WOR
XOSC
XTAL
Most Significant Bit
Minimum Shift Keying
Not Applicable
Non Return to Zero (Coding)
On Off Keying
Power Amplifier
Printed Circuit Board
Power Down
Packet Error Rate
Phase Locked Loop
Power-on Reset
Preamble Quality Indicator
Preamble Quality Threshold
RC Oscillator
Quadrature Phase Shift Keying
Quad Leadless Package
Resistor-Capacitor
Radio Frequency
Received Signal Strength Indicator
Receive, Receive Mode
Surface Mount Device
Signal to Noise Ratio
Serial Peripheral Interface
Short Range Device
Transmit/Receive
Transmit, Transmit Mode
Voltage Controlled Oscillator
Wireless Local Area Networks
Wake on Radio, Low power polling
Crystal Oscillator
Crystal
Page 3 of 89
CC2500
Table of Contents
APPLICATIONS ...........................................................................................................................................1
PRODUCT DESCRIPTION.........................................................................................................................1
KEY FEATURES ..........................................................................................................................................1
RF PERFORMANCE ...........................................................................................................................................1
ANALOG FEATURES ..........................................................................................................................................1
DIGITAL FEATURES ..........................................................................................................................................1
LOW-POWER FEATURES ...................................................................................................................................2
GENERAL..........................................................................................................................................................2
ABBREVIATIONS........................................................................................................................................3
TABLE OF CONTENTS ..............................................................................................................................4
1
ABSOLUTE MAXIMUM RATINGS ...........................................................................................................6
2
OPERATING CONDITIONS ......................................................................................................................6
3
GENERAL CHARACTERISTICS ...............................................................................................................6
4
ELECTRICAL SPECIFICATIONS ...............................................................................................................7
4.1
CURRENT CONSUMPTION .....................................................................................................................7
4.2
RF RECEIVE SECTION ...........................................................................................................................9
4.3
RF TRANSMIT SECTION ......................................................................................................................11
4.4
CRYSTAL OSCILLATOR .......................................................................................................................12
4.5
LOW POWER RC OSCILLATOR ............................................................................................................12
4.6
FREQUENCY SYNTHESIZER CHARACTERISTICS ...................................................................................13
4.7
ANALOG TEMPERATURE SENSOR .......................................................................................................14
4.8
DC CHARACTERISTICS .......................................................................................................................14
4.9
POWER-ON RESET ..............................................................................................................................14
5
PIN CONFIGURATION ..........................................................................................................................15
6
CIRCUIT DESCRIPTION ........................................................................................................................17
7
APPLICATION CIRCUIT ........................................................................................................................17
8
CONFIGURATION OVERVIEW ..............................................................................................................19
9
CONFIGURATION SOFTWARE ..............................................................................................................20
10
4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ...................................................................21
10.1 CHIP STATUS BYTE ............................................................................................................................22
10.2 REGISTER ACCESS ..............................................................................................................................23
10.3 SPI READ ...........................................................................................................................................23
10.4 COMMAND STROBES ..........................................................................................................................24
10.5 FIFO ACCESS .....................................................................................................................................24
10.6 PATABLE ACCESS .............................................................................................................................24
11
MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ...............................................................25
11.1 CONFIGURATION INTERFACE ..............................................................................................................25
11.2 GENERAL CONTROL AND STATUS PINS ..............................................................................................25
11.3 OPTIONAL RADIO CONTROL FEATURE ...............................................................................................26
12
DATA RATE PROGRAMMING ...............................................................................................................26
13
RECEIVER CHANNEL FILTER BANDWIDTH ..........................................................................................27
14
DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION .......................................................27
14.1 FREQUENCY OFFSET COMPENSATION.................................................................................................27
14.2 BIT SYNCHRONIZATION ......................................................................................................................27
14.3 BYTE SYNCHRONIZATION ...................................................................................................................28
15
PACKET HANDLING HARDWARE SUPPORT .........................................................................................28
15.1 DATA WHITENING ..............................................................................................................................29
15.2 PACKET FORMAT ................................................................................................................................29
15.3 PACKET FILTERING IN RECEIVE MODE ...............................................................................................31
15.4 CRC CHECK .......................................................................................................................................31
15.5 PACKET HANDLING IN TRANSMIT MODE ............................................................................................32
15.6 PACKET HANDLING IN RECEIVE MODE ..............................................................................................32
15.7 PACKET HANDLING IN FIRMWARE ......................................................................................................33
16
MODULATION FORMATS.....................................................................................................................33
16.1 FREQUENCY SHIFT KEYING ................................................................................................................33
16.2 MINIMUM SHIFT KEYING....................................................................................................................33
SWRS040C
Page 4 of 89
CC2500
16.3
17
17.1
17.2
17.3
17.4
17.5
17.6
18
18.1
18.2
19
19.1
19.2
19.3
19.4
19.5
19.6
19.7
20
21
22
22.1
23
24
25
26
26.1
27
28
29
30
30.1
30.2
31
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.8
31.9
31.10
32
32.1
32.2
32.3
33
33.1
33.2
34
35
36
36.1
AMPLITUDE MODULATION .................................................................................................................34
RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ...................................................34
SYNC WORD QUALIFIER .....................................................................................................................34
PREAMBLE QUALITY THRESHOLD (PQT) ...........................................................................................34
RSSI...................................................................................................................................................34
CARRIER SENSE (CS)..........................................................................................................................35
CLEAR CHANNEL ASSESSMENT (CCA) ..............................................................................................37
LINK QUALITY INDICATOR (LQI) .......................................................................................................37
FORWARD ERROR CORRECTION WITH INTERLEAVING ........................................................................37
FORWARD ERROR CORRECTION (FEC)...............................................................................................37
INTERLEAVING ...................................................................................................................................37
RADIO CONTROL ................................................................................................................................39
POWER-ON START-UP SEQUENCE ......................................................................................................39
CRYSTAL CONTROL ............................................................................................................................40
VOLTAGE REGULATOR CONTROL.......................................................................................................40
ACTIVE MODES ..................................................................................................................................41
WAKE ON RADIO (WOR)...................................................................................................................41
TIMING ...............................................................................................................................................42
RX TERMINATION TIMER ...................................................................................................................43
DATA FIFO ........................................................................................................................................43
FREQUENCY PROGRAMMING ..............................................................................................................44
VCO...................................................................................................................................................45
VCO AND PLL SELF-CALIBRATION ...................................................................................................45
VOLTAGE REGULATORS .....................................................................................................................46
OUTPUT POWER PROGRAMMING ........................................................................................................46
SELECTIVITY ......................................................................................................................................48
CRYSTAL OSCILLATOR .......................................................................................................................50
REFERENCE SIGNAL ...........................................................................................................................50
EXTERNAL RF MATCH .......................................................................................................................50
PCB LAYOUT RECOMMENDATIONS ....................................................................................................51
GENERAL PURPOSE / TEST OUTPUT CONTROL PINS ...........................................................................52
ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION ................................................................54
ASYNCHRONOUS OPERATION .............................................................................................................54
SYNCHRONOUS SERIAL OPERATION ...................................................................................................54
SYSTEM CONSIDERATIONS AND GUIDELINES .....................................................................................54
SRD REGULATIONS ............................................................................................................................54
FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS .....................................................................55
WIDEBAND MODULATION NOT USING SPREAD SPECTRUM ................................................................55
DATA BURST TRANSMISSIONS............................................................................................................55
CONTINUOUS TRANSMISSIONS ...........................................................................................................55
CRYSTAL DRIFT COMPENSATION .......................................................................................................56
SPECTRUM EFFICIENT MODULATION ..................................................................................................56
LOW COST SYSTEMS ..........................................................................................................................56
BATTERY OPERATED SYSTEMS ..........................................................................................................56
INCREASING OUTPUT POWER .........................................................................................................56
CONFIGURATION REGISTERS ..............................................................................................................57
CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ......61
CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOSE PROGRAMMING IN SLEEP STATE .....80
STATUS REGISTER DETAILS................................................................................................................81
PACKAGE DESCRIPTION (QFN 20) .....................................................................................................85
RECOMMENDED PCB LAYOUT FOR PACKAGE (QFN 20)....................................................................85
SOLDERING INFORMATION .................................................................................................................85
ORDERING INFORMATION ...................................................................................................................86
REFERENCES.......................................................................................................................................86
GENERAL INFORMATION ....................................................................................................................88
DOCUMENT HISTORY .........................................................................................................................88
SWRS040C
Page 5 of 89
CC2500
1
Absolute Maximum Ratings
Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress
exceeding one or more of the limiting values may cause permanent damage to the device.
Caution!
ESD
sensitive
device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
Parameter
Min
Max
Unit
Supply voltage
–0.3
3.9
V
Voltage on any digital pin
–0.3
VDD+0.3,
max 3.9
V
Voltage on the pins RF_P, RF_N
and DCOUPL
–0.3
2.0
V
Voltage ramp-up rate
120
kV/µs
Input RF level
+10
dBm
150
C
Solder reflow temperature
260
C
According to IPC/JEDEC J-STD-020D
ESD
<500
V
According to JEDEC STD 22, method A114,
Human Body Model
Storage temperature range
–50
Condition/Note
All supply pins must have the same voltage
Table 1: Absolute Maximum Ratings
2
Operating Conditions
The CC2500 operating conditions are listed in Table 2 below.
Parameter
Min
Max
Unit
Operating temperature
–40
85
C
Operating supply voltage
1.8
3.6
V
Condition/Note
All supply pins must have the same voltage
Table 2: Operating Conditions
3
General Characteristics
Parameter
Min
Frequency range
Data rate
Typ
Max
Unit
Condition/Note
2400
2483.5
MHz
There will be spurious signals at n/2·crystal oscillator
frequency (n is an integer number). RF frequencies at
n/2·crystal oscillator frequency should therefore be
avoided (e.g. 2405, 2418, 2431, 2444, 2457, 2470 and
2483 MHz when using a 26 MHz crystal).
1.2
500
kBaud
2-FSK
1.2
250
kBaud
GFSK and OOK
26
500
kBaud
(Shaped) MSK (also known as differential offset
QPSK)
Optional Manchester encoding (the data rate in kbps
will be half the baud rate).
Table 3: General Characteristics
SWRS040C
Page 6 of 89
CC2500
4
4.1
Electrical Specifications
Current Consumption
Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design
([4]).
Parameter
Current consumption in
power down modes
Current consumption
Current consumption,
RX states
Min
Typ
Max
Unit
Condition/Note
400
nA
Voltage regulator to digital part off, register values retained
(SLEEP state). All GDO pins programmed to 0x2F (HW to 0)
900
nA
Voltage regulator to digital part off, register values retained, lowpower RC oscillator running (SLEEP state with WOR enabled)
92
A
Voltage regulator to digital part off, register values retained,
XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)
160
A
Voltage regulator to digital part on, all other modules in power
down (XOFF state)
8.1
A
Automatic RX polling once each second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate,
PLL calibration every 4th wakeup. Average current with signal in
channel below carrier sense level (MCSM2.RX_TIME_RSSI=1).
35
A
Same as above, but with signal in channel above carrier sense
level, 1.95 ms RX timeout, and no preamble/sync word found.
1.4
A
Automatic RX polling every 15th second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate,
PLL calibration every 4th wakeup. Average current with signal in
channel below carrier sense level (MCSM2.RX_TIME_RSSI=1).
34
A
Same as above, but with signal in channel above carrier sense
level, 29.3 ms RX timeout, and no preamble/sync word found.
1.5
mA
Only voltage regulator to digital part and crystal oscillator running
(IDLE state)
7.4
mA
Only the frequency synthesizer is running (FSTXON state). This
current consumption is also representative for the other
intermediate states when going from IDLE to RX or TX, including
the calibration state.
17.0
mA
Receive mode, 2.4 kBaud, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
14.5
mA
Receive mode, 2.4 kBaud, input well above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
17.3
mA
Receive mode, 10 kBaud, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
14.9
mA
Receive mode, 10 kBaud, input well above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
18.8
mA
Receive mode, 250 kBaud, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
15.7
mA
Receive mode, 250 kBaud, input well above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
16.6
mA
Receive mode, 250 kBaud current optimized, input at sensitivity
limit, MDMCFG2.DEM_DCFILT_OFF=1
13.3
mA
Receive mode, 250 kBaud current optimized, input well above
sensitivity limit, MDMCFG2.DEM_DCFILT_OFF=1
19.6
mA
Receive mode, 500 kBaud, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
17.0
mA
Receive mode, 500 kBaud, input well above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF=0
SWRS040C
Page 7 of 89
CC2500
Current consumption,
TX states
11.1
mA
Transmit mode, –12 dBm output power
15.0
mA
Transmit mode, -6 dBm output power
21.2
mA
Transmit mode, 0 dBm output power
21.5
mA
Transmit mode, +1 dBm output power
Table 4: Current Consumption
SWRS040C
Page 8 of 89
CC2500
4.2
RF Receive Section
Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design
([4]).
Parameter
Min
Digital channel filter
bandwidth
58
Typ
Max
Unit
Condition/Note
812
kHz
User programmable. The bandwidth limits are
proportional to crystal frequency (given values assume
a 26.0 MHz crystal).
2.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth)
Receiver sensitivity
–104
dBm
The RX current consumption can be reduced by
approximately 1.7 mA by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity
is then -102 dBm and the temperature range is from 0oC
to +85oC.
The sensitivity can be improved to typically –106 dBm
with MDMCFG2.DEM_DCFILT_OFF=0 by programming
registers TEST2 and TEST1 (see page 82). The
temperature range is then from 0oC to +85oC.
Saturation
–13
dBm
Adjacent channel
rejection
23
dB
Desired channel 3 dB above the sensitivity limit. 250
kHz channel spacing
Alternate channel
rejection
31
dB
Desired channel 3 dB above the sensitivity limit. 250
kHz channel spacing
See Figure 22 for plot of selectivity versus frequency
offset
Blocking
Wanted signal 3 dB above sensitivity level.
±10 MHz offset
64
dBm
±20 MHz offset
70
dBm
±50 MHz offset
71
dBm
Compliant with ETSI EN 300 440 class 2 receiver
requirements.
10 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(2-FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth)
Receiver sensitivity
–99
dBm
The RX current consumption can be reduced by
approximately 1.7 mA by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity
is then -97 dBm
The sensitivity can be improved to typically –101 dBm
with MDMCFG2.DEM_DCFILT_OFF=0 by programming
registers TEST2 and TEST1 (see page 82). The
temperature range is then from 0oC to +85oC.
Saturation
–9
dBm
Adjacent channel
rejection
18
dB
Desired channel 3 dB above the sensitivity limit. 250
kHz channel spacing
Alternate channel
rejection
25
dB
Desired channel 3 dB above the sensitivity limit. 250
kHz channel spacing
See Figure 23 for plot of selectivity versus frequency
offset
Blocking
Wanted signal 3 dB above sensitivity level.
±10 MHz offset
59
dB
±20 MHz offset
65
dB
±50 MHz offset
66
dB
Compliant with ETSI EN 300 440 class 2 receiver
requirements.
SWRS040C
Page 9 of 89
CC2500
Parameter
Min
Typ
Max
Unit
Condition/Note
250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity
–89
dBm
Saturation
–13
dBm
Adjacent channel rejection
21
dB
Desired channel 3 dB above the sensitivity limit. 750
kHz channel spacing
Alternate channel rejection
30
dB
Desired channel 3 dB above the sensitivity limit. 750
kHz channel spacing
See Figure 24 for plot of selectivity versus frequency
offset
Blocking
Wanted signal 3 dB above sensitivity level.
±10 MHz offset
46
dB
±20 MHz offset
53
dB
±50 MHz offset
55
dB
Compliant with ETSI EN 300 440 class 2 receiver
requirements.
250 kBaud data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF=1
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity
–87
dBm
Saturation
–12
dBm
Adjacent channel rejection
21
dB
Desired channel 3 dB above the sensitivity limit. 750
kHz channel spacing
Alternate channel rejection
30
dB
Desired channel 3 dB above the sensitivity limit. 750
kHz channel spacing
See Figure 25 for plot of selectivity versus frequency
offset
Blocking
Wanted signal 3 dB above sensitivity level.
±10 MHz offset
46
dB
±20 MHz offset
52
dB
±50 MHz offset
55
dB
Compliant with ETSI EN 300 440 class 2 receiver
requirements.
500 kBaud data rate, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates
>250 kBaud)
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity
–83
dBm
Saturation
–18
dBm
Adjacent channel rejection
14
dB
Desired channel 3 dB above the sensitivity limit. 1 MHz
channel spacing
Alternate channel rejection
25
dB
Desired channel 3 dB above the sensitivity limit. 1 MHz
channel spacing
See Figure 26 for plot of selectivity versus frequency
offset
Blocking
Wanted signal 3 dB above sensitivity level.
±10 MHz offset
40
dB
±20 MHz offset
48
dB
±50 MHz offset
50
dB
Compliant with ETSI EN 300 440 class 2 receiver
requirements.
General
Spurious emissions
25 MHz – 1 GHz
–57
dBm
Above 1 GHz
–47
dBm
RX latency
9
bit
Serial operation. Time from start of reception until data
is available on the receiver data output pin is equal to 9
bit.
Table 5: RF Receive Section
SWRS040C
Page 10 of 89
CC2500
4.3
RF Transmit Section
Tc = 25C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2500EM reference
design ([4]).
Parameter
Min
Typ
Max
Unit
Differential load
impedance
80 + j74

Output power,
highest setting
+1
dBm
Condition/Note
Differential impedance as seen from the RF-port (RF_P and
RF_N) towards the antenna. Follow the CC2500EM
reference design ([4]) available from the TI website.
Output power is programmable and full range is available
across the entire frequency band.
Delivered to a 50  single-ended load via CC2500EM
reference design ([4]) RF matching network.
Output power,
lowest setting
–30
dBm
Output power is programmable and full range is available
across the entire frequency band.
Delivered to a 50  single-ended load via CC2500EM
reference design ([4]) RF matching network.
It is possible to program less than -30 dBm output power,
but this is not recommended due to large variation in output
power across operating conditions and processing corners
for these settings.
Occupied bandwidth
(99%)
Adjacent channel
power (ACP)
91
kHz
2.4 kBaud, 38.2 kHz deviation, 2-FSK
117
kHz
10 kBaud, 38.2 kHz deviation, 2-FSK
296
kHz
250 kBaud, MSK
489
kHz
500 kBaud, MSK
-28
dBc
2.4 kBaud, 38.2 kHz deviation, 2-FSK, 250 kHz channel
spacing
-27
dBc
10 kBaud, 38.2 kHz deviation, 2-FSK, 250 kHz channel
spacing
-22
dBc
250 kBaud, MSK, 750 kHz channel spacing
-21
dBc
500 kBaud, MSK, 1 MHz channel spacing
Spurious emissions
25 MHz – 1 GHz
–36
dBm
47-74, 87.5-118, 174230, 470-862 MHz
–54
dBm
1800-1900 MHz
–47
dBm
Restricted band in Europe
At 2∙RF and 3∙RF
–41
dBm
Restricted bands in USA
Otherwise above 1
GHz
–30
dBm
TX latency
8
bit
Serial operation. Time from sampling the data on the
transmitter data input pin until it is observed on the RF
output ports.
Table 6: RF Transmit Section
SWRS040C
Page 11 of 89
CC2500
4.4
Crystal Oscillator
Tc = 25C, VDD = 3.0 V if nothing else stated.
Parameter
Crystal frequency
Min
Typ
Max
Unit
26
26
27
MHz
Tolerance
±40
ppm
Condition/Note
This is the total tolerance including a) initial tolerance, b) crystal
loading, c) aging, and d) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.
ESR

100
Start-up time
150
µs
Measured on CC2500EM reference design ([4]) using crystal
AT-41CD2 from NDK.
This parameter is to a large degree crystal dependent.
Table 7: Crystal Oscillator Parameters
4.5
Low Power RC Oscillator
Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design
([4]).
Parameter
Min
Typ
Max
Unit
Condition/Note
Calibrated frequency
34.7
34.7
36
kHz
Calibrated RC oscillator frequency is XTAL
frequency divided by 750
-1 /
+10
%
Frequency accuracy after
calibration
The RC oscillator contains an error in the
calibration routine that statistically occurs in
17.3% of all calibrations performed. The given
maximum accuracy figures account for the
calibration error. Refer also to the CC2500
Errata Notes.
+0.4
% / C
Frequency drift when temperature changes
after calibration
Supply voltage coefficient
+3
%/V
Frequency drift when supply voltage changes
after calibration
Initial calibration time
2
ms
Temperature coefficient
When the RC oscillator is enabled, calibration
is continuously done in the background as long
as the crystal oscillator is running.
Table 8: RC Oscillator Parameters
SWRS040C
Page 12 of 89
CC2500
4.6
Frequency Synthesizer Characteristics
Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design
([4]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal.
Parameter
Min
Typ
Max
Unit
Programmed
frequency resolution
397
FXOSC/
216
412
Hz
Condition/Note
26-27 MHz crystal.
Synthesizer frequency
tolerance
±40
ppm
Given by crystal used. Required accuracy (including
temperature and aging) depends on frequency band and
channel bandwidth / spacing.
RF carrier phase noise
–78
dBc/Hz
@ 50 kHz offset from carrier
–78
dBc/Hz
@ 100 kHz offset from carrier
–81
dBc/Hz
@ 200 kHz offset from carrier
–90
dBc/Hz
@ 500 kHz offset from carrier
–100
dBc/Hz
@ 1 MHz offset from carrier
–108
dBc/Hz
@ 2 MHz offset from carrier
–114
dBc/Hz
@ 5 MHz offset from carrier
–118
dBc/Hz
@ 10 MHz offset from carrier
PLL turn-on / hop time
85.1
88.4
88.4
s
Time from leaving the IDLE state until arriving in the RX,
FSTXON or TX state, when not performing calibration.
Crystal oscillator running.
PLL RX/TX settling
time
9.3
9.6
9.6
s
Settling time for the 1·IF frequency step from RX to TX
PLL TX/RX settling
time
20.7
21.5
21.5
s
Settling time for the 1·IF frequency step from TX to RX
PLL calibration time
694
721
721
s
Calibration can be initiated manually or automatically
before entering or after leaving RX/TX.
Table 9: Frequency Synthesizer Parameters
SWRS040C
Page 13 of 89
CC2500
4.7
Analog Temperature Sensor
The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table
10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog
temperature sensor in the IDLE state.
Parameter
Min
Typ
Max
Unit
Output voltage at –40C
0.654
V
Output voltage at 0C
0.750
V
Output voltage at +40C
0.848
V
Output voltage at +80C
0.946
V
Temperature coefficient
2.43
-2
Error in calculated
temperature, calibrated
*
0
2
*
Condition/Note
mV/C
Fitted from –20C to +80C
C
From –20C to +80C when using 2.43 mV / C,
after 1-point calibration at room temperature
*
The indicated minimum and maximum error with 1point calibration is based on measured values for
typical process parameters
Current consumption
increase when enabled
0.3
mA
Table 10: Analog Temperature Sensor Parameters
4.8
DC Characteristics
Tc = 25C if nothing else stated.
Digital Inputs/Outputs
Min
Max
Unit
Condition/Note
Logic "0" input voltage
0
0.7
V
Logic "1" input voltage
VDD-0.7
VDD
V
Logic "0" output voltage
0
0.5
V
For up to 4 mA output current
Logic "1" output voltage
VDD-0.3
VDD
V
For up to 4 mA output current
Logic "0" input current
N/A
–50
nA
Input equals 0 V
Logic "1" input current
N/A
50
nA
Input equals VDD
Table 11: DC Characteristics
4.9
Power-On Reset
When the power supply complies with the requirements in Table 12 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state
until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 39 for further
details.
Parameter
Min
Power ramp-up time
Power off time
1
Typ
Max
Unit
Condition/Note
5
ms
From 0 V until reaching 1.8 V
ms
Minimum time between power-on and power-off
Table 12: Power-on Reset Requirements
SWRS040C
Page 14 of 89
CC2500
GND
RBIAS
DGUARD
GND
Pin Configuration
SI
5
20 19 18 17 16
SCLK 1
15 AVDD
SO (GDO1) 2
14 AVDD
GDO2 3
13 RF_N
DVDD 4
12 RF_P
DCOUPL 5
11 AVDD
9 10
AVDD
XOSC_Q2
8
XOSC_Q1
GDO0 (ATEST)
7
CSn
6
GND
Exposed die
attach pad
Figure 1: Pinout Top View
Note: The exposed die attach pad must be connected to a solid ground plane as this is the main
ground connection for the chip.
SWRS040C
Page 15 of 89
CC2500
Pin #
Pin Name
Pin Type
Description
1
SCLK
Digital Input
Serial configuration interface, clock input
2
SO (GDO1)
Digital Output
Serial configuration interface, data output.
Optional general output pin when CSn is high
3
GDO2
Digital Output
Digital output pin for general use:
 Test signals
 FIFO status signals
 Clear Channel Indicator
 Clock output, down-divided from XOSC
 Serial output RX data
4
DVDD
Power (Digital)
1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core
voltage regulator
5
DCOUPL
Power (Digital)
1.6 - 2.0 V digital power supply output for decoupling.
NOTE: This pin is intended for use with the CC2500 only. It can not be
used to provide supply voltage to other devices.
6
GDO0
Digital I/O
Digital output pin for general use:
 Test signals
(ATEST)
 FIFO status signals
 Clear Channel Indicator
 Clock output, down-divided from XOSC
 Serial output RX data
 Serial input TX data
Also used as analog test I/O for prototype/production testing
7
CSn
Digital Input
Serial configuration interface, chip select
8
XOSC_Q1
Analog I/O
Crystal oscillator pin 1, or external clock input
9
AVDD
Power (Analog)
1.8 - 3.6 V analog power supply connection
10
XOSC_Q2
Analog I/O
Crystal oscillator pin 2
11
AVDD
Power (Analog)
1.8 - 3.6 V analog power supply connection
12
RF_P
RF I/O
Positive RF input signal to LNA in receive mode
Positive RF output signal from PA in transmit mode
13
RF_N
RF I/O
Negative RF input signal to LNA in receive mode
14
AVDD
Power (Analog)
1.8 - 3.6 V analog power supply connection
15
AVDD
Power (Analog)
1.8 - 3.6 V analog power supply connection
16
GND
Ground (Analog)
Analog ground connection
17
RBIAS
Analog I/O
External bias resistor for reference current
18
DGUARD
Power (Digital)
Power supply connection for digital noise isolation
19
GND
Ground (Digital)
Ground connection for digital noise isolation
20
SI
Digital Input
Serial configuration interface, data input
Negative RF output signal from PA in transmit mode
Table 13: Pinout Overview
SWRS040C
Page 16 of 89
CC2500
6
Circuit Description
FREQ
SYNTH
0
RF_N
90
MODULATOR
RF_P
PA
RC OSC
BIAS
RBIAS
XOSC
XOSC_Q1
RXFIFO
DIGITAL INTERFACE TO MCU
ADC
TXFIFO
LNA
PACKET HANDLER
ADC
FEC / INTERLEAVER
DEMODULATOR
RADIO CONTROL
SCLK
SO (GDO1)
SI
CSn
GDO0 (ATEST)
GDO2
XOSC_Q2
Figure 2: CC2500 Simplified Block Diagram
A simplified block diagram of CC2500 is shown
in Figure 2.
signals to the down-conversion mixers in
receive mode.
CC2500
features a low-IF receiver. The
received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in
quadrature (I and Q) to the intermediate
frequency (IF). At IF, the I/Q signals are
digitised by the ADCs. Automatic gain control
(AGC), fine channel filtering, demodulation
bit/packet synchronization are performed
digitally.
A crystal is to be connected to XOSC_Q1 and
XOSC_Q2. The crystal oscillator generates the
reference frequency for the synthesizer, as
well as clocks for the ADC and the digital part.
The transmitter part of CC2500 is based on
direct synthesis of the RF frequency.
A 4-wire SPI serial interface is used for
configuration and data buffer access.
The digital baseband includes support for
channel configuration, packet handling, and
data buffering.
The frequency synthesizer includes a
completely on-chip LC VCO and a 90 degrees
phase shifter for generating the I and Q LO
7
Application Circuit
Only a few external components are required
for using the CC2500. The recommended
application circuit is shown in Figure 3. The
external components are described in Table
14, and typical values are given in Table 15.
Bias Resistor
The bias resistor R171 is used to set an
accurate bias current.
Balun and RF Matching
The components between the RF_N/RF_P pins
and the point where the two signals are joined
together (C122, C132, L121, and L131) form a
SWRS040C
Page 17 of 89
CC2500
Crystal
balun that converts the differential RF signal
on CC2500 to a single-ended RF signal. C121
and C131 are needed for DC blocking.
Together with an appropriate LC network, the
balun components also transform the
impedance to match a 50  antenna (or
cable). Suggested values are listed in Table
15.
The crystal oscillator uses an external crystal
with two loading capacitors (C81 and C101).
See Section 26 on page 50 for details.
Power Supply Decoupling
The power supply must be properly decoupled
close to the supply pins. Note that decoupling
capacitors are not shown in the application
circuit. The placement and the size of the
decoupling capacitors are very important to
achieve the optimum performance. The
CC2500EM reference design ([4]) should be
followed closely.
The balun and LC filter component values and
their placement are important to keep the
performance
optimized.
It
is
highly
recommended to follow the CC2500EM
reference design ([4]).
Component
Description
C51
Decoupling capacitor for on-chip voltage regulator to digital part
C81/C101
Crystal loading capacitors, see Section 26 on page 50 for details
C121/C131
RF balun DC blocking capacitors
C122/C132
RF balun/matching capacitors
C123/C124
RF LC filter/matching capacitors
L121/L131
RF balun/matching inductors (inexpensive multi-layer type)
L122
RF LC filter inductor (inexpensive multi-layer type)
R171
Resistor for internal bias current reference
XTAL
26-27 MHz crystal, see Section 26 on page 50 for details
Table 14: Overview of External Components (excluding supply decoupling capacitors)
1.8V-3.6V power supply
R171
RBIAS 17
GND 16
L131
AVDD 14
RF_N 13
DIE ATTACH PAD:
RF_P 12
7 CSn
5 DCOUPL
10 XOSC_Q2
CC2500
9 AVDD
3 GDO2
Antenna
(50 Ohm)
AVDD 15
2 SO (GDO1)
4 DVDD
C51
DGUARD 18
1 SCLK
8 XOSC_Q1
SO
(GDO1)
GDO2
(optional)
6 GDO0
Digital Inteface
SCLK
GND 19
SI 20
SI
AVDD 11
C132
C121
L121
C122
L122
C123
C124
Alternative:
Folded dipole PCB
antenna (no external
components needed)
GDO0
(optional)
CSn
XTAL
C81
C131
C101
Figure 3: Typical Application and Evaluation Circuit (excluding supply decoupling capacitors)
SWRS040C
Page 18 of 89
CC2500
Component
Value
Manufacturer
C51
100 nF ±10%, 0402 X5R
Murata GRM15 series
C81
27 pF ±5%, 0402 NP0
Murata GRM15 series
C101
27 pF ±5%, 0402 NP0
Murata GRM15 series
C121
100 pF ±5%, 0402 NP0
Murata GRM15 series
C122
1.0 pF ±0.25 pF, 0402 NP0
Murata GRM15 series
C123
1.8 pF ±0.25 pF, 0402 NP0
Murata GRM15 series
C124
1.5 pF ±0.25 pF, 0402 NP0
Murata GRM15 series
C131
100 pF ±5%, 0402 NP0
Murata GRM15 series
C132
1.0 pF ±0.25 pF, 0402 NP0
Murata GRM15 series
L121
1.2 nH ±0.3 nH, 0402 monolithic
Murata LQG15HS series
L122
1.2 nH ±0.3 nH, 0402 monolithic
Murata LQG15HS series
L131
1.2 nH ±0.3 nH, 0402 monolithic
Murata LQG15HS series
R171
56 kΩ ±1%, 0402
Koa RK73 series
XTAL
26.0 MHz surface mount crystal
NDK, AT-41CD2
Table 15: Bill Of Materials for the Application Circuit
Measurements have been performed with
multi-layer inductors from other manufacturers
(e.g. Würth) and the measurement results
were the same as when using the Murata part.
The Gerber files for the CC2500EM reference
design ([4]) are available from the TI website.
Figure 4: CC2500EM Reference Design ([4])
8
Configuration Overview
CC2500 can be configured to achieve optimum
performance for many different applications.
Configuration is done using the SPI interface.
The following key parameters can be
programmed:









Power-down / power up mode
Crystal oscillator power-up / power-down
Receive / transmit mode
RF channel selection
Data rate
Modulation format
RX channel filter bandwidth
RF output power
Data buffering with separate 64-byte
receive and transmit FIFOs
SWRS040C




Packet radio hardware support
Forward Error Correction (FEC)
interleaving
Data Whitening
Wake-On-Radio (WOR)
with
Details of each configuration register can be
found in Section 32, starting on page 57.
Figure 5 shows a simplified state diagram that
explains the main CC2500 states, together with
typical usage and current consumption. For
detailed information on controlling the CC2500
state machine, and a complete state diagram,
see Section 19, starting on page 39.
Page 19 of 89
CC2500
Sleep
SPWD or wake-on-radio (WOR)
SIDLE
Default state when the radio is not
receiving or transmitting. Typ.
current consumption: 1.5mA.
Lowest power mode. Most
register values are retained.
Typ. current consumption
400nA, or 900nA when
wake-on-radio (WOR) is
enabled.
CSn=0
Idle
SXOFF
SCAL
Used for calibrating frequency
synthesizer upfront (entering
CSn=0
receive or transmit mode can
Manual freq.
then be done quicker).
synth. calibration SRX or STX or SFSTXON or wake-on-radio (WOR)
Transitional state. Typ. current
consumption: 7.4mA.
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the
STX command strobe.Typ.
current consumption: 7.4mA.
SFSTXON
Frequency
synthesizer startup,
optional calibration,
settling
Crystal
oscillator off
All register values are
retained. Typ. current
consumption; 0.16mA.
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state. Typ. current consumption: 7.4mA.
Frequency
synthesizer on
STX
SRX or wake-on-radio (WOR)
STX
TXOFF_MODE=01
SFSTXON or RXOFF_MODE=01
Typ. current consumption:
11.1mA at -12dBm output,
15.1mA at -6dBm output,
21.2mA at 0dBm output.
STX or RXOFF_MODE=10
Transmit mode
TXOFF_MODE=00
In FIFO-based modes,
transmission is turned off
and this state entered if the
TX FIFO becomes empty in
the middle of a packet. Typ.
current consumption: 1.5mA.
Receive mode
SRX or TXOFF_MODE=11
RXOFF_MODE=00
Optional transitional state. Typ.
current consumption: 7.4mA.
TX FIFO
underflow
Typ. current
consumption:
from 13.3mA (strong
input signal) to 16.6mA
(weak input signal).
Optional freq.
synth. calibration
SFTX
RX FIFO
overflow
In FIFO-based modes,
reception is turned off and
this state entered if the RX
FIFO overflows. Typ.
current consumption:
1.5mA.
SFRX
Idle
Figure 5: Simplified State Diagram with Typical Usage and Current Consumption at 250 kBaud
Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized)
9
Configuration Software
CC2500 can be configured using the SmartRF
Studio software [5]. The SmartRF Studio
software is highly recommended for obtaining
optimum register settings, and for evaluating
performance and functionality. A screenshot of
the SmartRF Studio user interface for CC2500
is shown in Figure 6.
SWRS040C
After chip reset, all the registers have default
values as shown in the tables in Section 32.
The optimum register setting might differ from
the default value. After a reset all registers that
shall be different from the default value
therefore needs to be programmed through
the SPI interface.
Page 20 of 89
CC2500
Figure 6: SmartRF Studio [5] User Interface
10 4-wire Serial Configuration and Data Interface
CC2500 is configured via a simple 4-wire SPIcompatible interface (SI, SO, SCLK and CSn)
where CC2500 is the slave. This interface is
also used to read and write buffered data. All
transfers on the SPI interface are done most
significant bit first.
All transactions on the SPI interface start with
a header byte containing a R/W bit, a burst
access bit (B), and a 6-bit address (A5 – A0).
The CSn pin must be kept low during transfers
on the SPI bus. If CSn goes high during the
SWRS040C
transfer of a header byte or during read/write
from/to a register,
the transfer will be
cancelled. The timing for the address and data
transfer on the SPI interface is shown in
Figure 7 with reference to Table 16.
When CSn is pulled low, the MCU must wait
until CC2500 SO pin goes low before starting to
transfer the header byte. This indicates that
the crystal is running. Unless the chip was in
the SLEEP or XOFF states, the SO pin will
always go low immediately after taking CSn
low.
Page 21 of 89
CC2500
Figure 7: Configuration Register Write and Read Operations
Parameter
Description
fSCLK
SCLK frequency
Min
Max
Units
-
10
MHz
9
MHz
6.5
MHz
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
SCLK frequency, single access
No delay between address and data byte
SCLK frequency, burst access
No delay between address and data byte, or between data bytes
tsp,pd
CSn low to positive edge on SCLK, in power-down mode
150
tsp
CSn low to positive edge on SCLK, in active mode
20
-
ns
tch
Clock high
50
-
ns
tcl
Clock low
50
-
ns
trise
Clock rise time
-
5
ns
tfall
Clock fall time
-
5
ns
tsd
Setup data (negative SCLK edge) to
positive edge on SCLK
Single access
55
-
ns
Burst access
76
-
ns
(tsd applies between address and data bytes, and
between data bytes)
µs
thd
Hold data after positive edge on SCLK
20
-
ns
tns
Negative edge on SCLK to CSn high
20
-
ns
Table 16: SPI Interface Timing Requirements
Note: The minimum tsp,pd figure in Table 16 can be used in cases where the user does not read the
CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down
depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator
start-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK.
10.1
Chip Status Byte
When the header byte, data byte or, command
strobe is sent on the SPI interface, the chip
status byte is sent by the CC2500 on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
the CHIP_RDYn signal; this signal must go low
SWRS040C
before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is
running.
Bits 6, 5, and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core is on in
the IDLE state, but all other modules are in
power down. The frequency and channel
Page 22 of 89
CC2500
configuration should only be updated when the
chip is in this state. The RX state will be active
when the chip is in receive mode. Likewise, TX
is active when the chip is transmitting.
The last four bits (3:0) in the status byte
contains FIFO_BYTES_AVAILABLE. For read
operations (the R/W bit in the header byte is
set to 1), the FIFO_BYTES_AVAILABLE field
contains the number of bytes available for
Bits
reading from the RX FIFO. For write
operations (the R/W bit in the header byte is
set to 0), the FIFO_BYTES_AVAILABLE field
contains the number of bytes that can be
written
to
the
TX
FIFO.
When
FIFO_BYTES_AVAILABLE=15, 15 or more
bytes are available/free.
Table 17 gives a status byte summary.
Name
Description
7
CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
6:4
STATE[2:0]
Indicates the current main state machine mode
3:0
FIFO_BYTES_AVAILABLE[3:0]
Value
State
Description
000
IDLE
Idle state
(Also reported for some transitional states
instead of SETTLING or CALIBRATE)
001
RX
Receive mode
010
TX
Transmit mode
011
FSTXON
Frequency synthesizer is on, ready to start
transmitting
100
CALIBRATE
Frequency synthesizer calibration is running
101
SETTLING
PLL is settling
110
RXFIFO_OVERFLOW
RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX
111
TXFIFO_UNDERFLOW
TX FIFO has underflowed. Acknowledge with
SFTX
The number of bytes available in the RX FIFO or free bytes in the TX FIFO
Table 17: Status Byte Summary
10.2
Register Access
The configuration registers of the CC2500 are
located on SPI addresses from 0x00 to 0x2E.
Table 35 on page 58 lists all configuration
registers. It is highly recommended to use
®
SmartRF Studio [5] to generate optimum
register settings. The detailed description of
each register is found in Section 32.1, starting
on page 61. All configuration registers can be
both written to and read. The R/W bit controls
if the register should be written to or read.
When writing to registers, the status byte is
sent on the SO pin each time a header byte or
data byte is transmitted on the SI pin. When
reading from registers, the status byte is sent
on the SO pin each time a header byte is
transmitted on the SI pin.
Registers with consecutive addresses can be
accessed in an efficient way by setting the
SWRS040C
burst bit (B) in the header byte. The address
bits (A5 – A0) set the start address in an
internal address counter. This counter is
incremented by one each new byte (every 8
clock pulses). The burst access is either a
read or a write access and must be terminated
by setting CSn high.
For register addresses in the range 0x300x3D, the burst bit is used to select between
status registers, burst bit is one, and command
strobes, burst bit is zero (see Section 10.4
below). Because of this, burst access is not
available for status registers and they must be
accessed one at a time. The status registers
can only be read.
10.3
SPI Read
When reading register fields over the SPI
interface while the register fields are updated
Page 23 of 89
CC2500
by the radio hardware (e.g. MARCSTATE or
TXBYTES), there is a small, but finite,
probability that a single read from the register
is being corrupt. As an example, the
probability of any single read from TXBYTES
being corrupt, assuming the maximum data
rate is used, is approximately 80 ppm. Refer to
the CC2500 Errata Notes [1] for more details.
10.4
Command Strobes
Command strobes may be viewed as single
byte instructions to CC2500. By addressing a
command strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 13
command strobes are listed in Table 34 on
page 57.
The command strobe registers are accessed
by transferring a single header byte (no data is
being transferred). That is, only the R/W bit,
the burst access bit (set to 0), and the six
address bits (in the range 0x30 through 0x3D)
are written. The R/W bit can be either one or
zero
and
will
determine
how
the
FIFO_BYTES_AVAILABLE field in the status
byte should be interpreted.
When writing command strobes, the status
byte is sent on the SO pin.
A command strobe may be followed by any
other SPI access without pulling CSn high.
However, if an SRES strobe is being issued,
one will have to wait for SO to go low again
before the next header byte can be issued as
shown in Figure 8. The command strobes are
executed immediately, with the exception of
the SPWD and the SXOFF strobes that are
executed when CSn goes high.
The TX FIFO is write-only, while the RX FIFO
is read-only.
The burst bit is used to determine if the FIFO
access is a single byte access or a burst
access. The single byte access method
expects a header byte with the burst bit set to
zero and one data byte. After the data byte a
new header byte is expected; hence, CSn can
remain low. The burst access method expects
one header byte and then consecutive data
bytes until terminating the access by setting
CSn high.
The following header bytes access the FIFOs:

0x3F: Single byte access to TX FIFO

0x7F: Burst access to TX FIFO

0xBF: Single byte access to RX FIFO

0xFF: Burst access to RX FIFO
When writing to the TX FIFO, the status byte
(see Section 10.1) is output for each new data
byte on SO, as shown in Figure 7. This status
byte can be used to detect TX FIFO underflow
while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
free before writing the byte in progress to the
TX FIFO. When the last byte that fits in the TX
FIFO is transmitted on SI, the status byte
received concurrently on SO will indicate that
one byte is free in the TX FIFO.
The TX FIFO may be flushed by issuing a
SFTX command strobe. Similarly, a SFRX
command strobe will flush the RX FIFO. A
SFTX or SFRX command strobe can only be
issued in the IDLE, TXFIFO_UNDERLOW or
RXFIFO_OVERFLOW states. Both FIFOs are
flushed when going to the SLEEP state.
Figure 9 gives a brief overview of different
register access types possible.
10.6
Figure 8: SRES Command Strobe
10.5
FIFO Access
The 64-byte TX FIFO and the 64-byte RX
FIFO are accessed through the 0x3F address.
When the R/W bit is zero, the TX FIFO is
accessed, and the RX FIFO is accessed when
the R/W bit is one.
SWRS040C
PATABLE Access
The 0x3E address is used to access the
PATABLE, which is used for selecting PA
power control settings. The PATABLE is an 8byte table, but not all entries into this table are
used. The entries to use are selected by the 3bit value FREND0.PA_POWER.

When using 2-FSK, GFSK, or MSK
modulation only the first entry into this
table is used (index 0).
Page 24 of 89
CC2500

When using OOK modulation the first two
entries into this table are used (index 0
and index 1).
Since the PATABLE is an 8-byte table, the
table is written and read from the lowest
setting (0) to the highest (7), one byte at a
time. An index counter is used to control the
access to the table. This counter is
incremented each time a byte is read or
written to the table, and set to the lowest index
when CSn is high. When the highest value is
reached the counter restarts at 0.
access is a write access (R/W=0) or a read
access (R/W=1).
If one byte is written to the PATABLE and this
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
Note that the content of the PATABLE is lost
when entering the SLEEP state, except for the
first byte (index 0).
See Section 24 on page 46 for output power
programming details.
The access to the PATABLE is either single
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The R/W bit controls whether the
Figure 9: Register Access Types
11 Microcontroller Interface and Pin Configuration
In a typical system, CC2500 will interface to a
microcontroller. This microcontroller must be
able to:
 Program CC2500 into different modes
 Read and write buffered data
 Read back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLK and CSn)
11.1
Configuration Interface
The microcontroller uses four I/O pins for the
SPI configuration interface (SI, SO, SCLK and
CSn). The SPI is described in Section 10 on
page 21.
SWRS040C
11.2
General Control and Status Pins
The CC2500 has two dedicated configurable
pins (GDO0 and GDO2) and one shared pin
(GDO1) that can output internal status
information useful for control software. These
pins can be used to generate interrupts on the
MCU. See Section 28 on page 51 for more
details on the signals that can be programmed.
GDO1 is shared with the SO pin in the SPI
interface. The default setting for GDO1/SO is 3state output. By selecting any other of the
programming options the GDO1/SO pin will
become a generic pin. When CSn is low, the
pin will always function as a normal SO pin.
In the synchronous and asynchronous serial
modes, the GDO0 pin is used as a serial TX
data input pin while in transmit mode.
Page 25 of 89
CC2500
The GDO0 pin can also be used for an on-chip
analog temperature sensor. By measuring the
voltage on the GDO0 pin with an external ADC,
the
temperature
can
be
calculated.
Specifications for the temperature sensor are
found in Section 4.7 on page 14.
With default PTEST register setting (0x7F) the
temperature sensor output is only available
when the frequency synthesizer is enabled
(e.g. the MANCAL, FSTXON, RX and TX
states). It is necessary to write 0xBF to the
PTEST register to use the analog temperature
sensor in the IDLE state. Before leaving the
IDLE state, the PTEST register should be
restored to its default value (0x7F).
11.3
Optional Radio Control Feature
The CC2500 has an optional way of controlling
the radio, by reusing SI, SCLK and CSn from
the SPI interface. This feature allows for a
simple three-pin control of the major states of
the radio: SLEEP, IDLE, RX and TX.
This optional functionality is enabled with the
MCSM0.PIN_CTRL_EN configuration bit.
State changes are commanded as follows:
When CSn is high the SI and SCLK is set to
the desired state according to Table 18. When
CSn goes low the state of SI and SCLK is
latched and a command strobe is generated
internally according to the control coding. It is
only possible to change state with this
functionality. That means that for instance RX
will not be restarted if SI and SCLK are set to
RX and CSn toggles. When CSn is low the SI
and SCLK has normal SPI functionality.
All pin control command strobes are executed
immediately, except the SPWD strobe, which is
delayed until CSn goes high.
CSn
SCLK
SI
1
X
X
Chip unaffected by SCLK/SI

0
0
Generates SPWD strobe

0
1
Generates STX strobe

1
0
Generates SIDLE strobe

1
SPI
mode
1
SPI
mode
Generates SRX strobe
SPI mode (wakes up into
IDLE if in SLEEP/XOFF)
0
Function
Table 18: Optional Pin Control Coding
12 Data Rate Programming
The data rate used when transmitting, or the
data rate expected in receive is programmed
by
the
MDMCFG3.DRATE_M
and
the
MDMCFG4.DRATE_E configuration registers.
The data rate is given by the formula below.
As the formula shows, the programmed data
rate depends on the crystal frequency.
RDATA 
256  DRATE _ M   2
2 28
DRATE _ E
 f XOSC
The following approach can be used to find
suitable values for a given data rate:

R
 2 20 

DRATE _ E  log 2  DATA

 f XOSC 
RDATA  2 28
DRATE _ M 
 256
f XOSC  2 DRATE _ E
If DRATE_M is rounded to the nearest integer
and becomes 256, increment DRATE_E and
use DRATE_M=0.
The data rate can be set from 1.2 kBaud to
500 kBaud with the minimum step size of:
Min Data
Rate
[kBaud]
Typical
Data Rate
[kBaud]
Max Data
Rate
[kBaud]
Data Rate
Step Size
[kBaud]
0.8
1.2/2.4
3.17
0.0062
3.17
4.8
6.35
0.0124
6.35
9.6
12.7
0.0248
12.7
19.6
25.4
0.0496
25.4
38.4
50.8
0.0992
50.8
76.8
101.6
0.1984
101.6
153.6
203.1
0.3967
203.1
250
406.3
0.7935
406.3
500
500
1.5869
Table 19: Data Rate Step Size
SWRS040C
Page 26 of 89
CC2500
13 Receiver Channel Filter Bandwidth
In order to meet different channel width
requirements, the receiver channel filter is
programmable. The MDMCFG4.CHANBW_E and
MDMCFG4.CHANBW_M configuration registers
control the receiver channel filter bandwidth,
which scales with the crystal oscillator
frequency. The following formula gives the
relation between the register settings and the
channel filter bandwidth:
BWchannel
kHz, which is 480 kHz. Assuming 2.44 GHz
frequency and ±20 ppm frequency uncertainty
for both the transmitting device and the
receiving device, the
total frequency
uncertainty is ±40 ppm of 2.44 GHz, which is
±98 kHz. If the whole transmitted signal
bandwidth is to be received within 480 kHz,
the transmitted signal bandwidth should be
maximum 480 kHz – 2·98 kHz, which is 284
kHz.
The CC2500 supports the following channel
filter bandwidths:
f XOSC

8  ( 4  CHANBW _ M )·2CHANBW _ E
MDMCFG4.
For best performance, the channel filter
bandwidth should be selected so that the
signal bandwidth occupies at most 80% of the
channel filter bandwidth. The channel centre
tolerance due to crystal accuracy should also
be subtracted from the signal bandwidth. The
following example illustrates this:
With the channel filter bandwidth set to 600
kHz, the signal should stay within 80% of 600
MDMCFG4.CHANBW_E
CHANBW_M
00
01
10
11
00
812
406
203
102
01
650
325
162
81
10
541
270
135
68
11
464
232
116
58
Table 20: Channel Filter Bandwidths [kHz]
(assuming a 26 MHz crystal)
14 Demodulator, Symbol Synchronizer and Data Decision
CC2500 contains an advanced and highly
configurable demodulator. Channel filtering
and frequency offset compensation is
performed digitally. To generate the RSSI level
(see Section 17.3 for more information) the
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
14.1
Frequency Offset Compensation
When using 2-FSK, GFSK, or MSK
modulation, the demodulator will compensate
for the offset between the transmitter and
receiver frequency, within certain limits, by
estimating the centre of the received data.
This value is available in the FREQEST status
register. Writing the value from FREQEST into
FSCTRL0.FREQOFF
the
frequency
synthesizer
is
automatically
adjusted
according to the estimated frequency offset.
The tracking range of the algorithm is
selectable as fractions of the channel
bandwidth with the FOCCFG.FOC_LIMIT
configuration register.
SWRS040C
If the FOCCFG.FOC_BS_CS_GATE bit is set,
the offset compensator will freeze until carrier
sense asserts. This may be useful when the
radio is in RX for long periods with no traffic,
since the algorithm may drift to the boundaries
when trying to track noise.
The tracking loop has two gain factors, which
affects the settling time and noise sensitivity of
the algorithm. FOCCFG.FOC_PRE_K sets the
gain before the sync word is detected, and
FOCCFG.FOC_POST_K selects the gain after
the sync word has been found.
Note that frequency offset compensation is not
supported for OOK modulation.
14.2
Bit Synchronization
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 12 on
page 26. Re-synchronization is performed
continuously to adjust for error in the incoming
symbol rate.
Page 27 of 89
CC2500
14.3
Byte Synchronization
Byte synchronization is achieved by a
continuous sync word search. The sync word
is a 16 bit configurable field (can be repeated
to get a 32 bit) that is automatically inserted at
the start of the packet by the modulator in
transmit mode. The demodulator uses this
field to find the byte boundaries in the stream
of bits. The sync word will also function as a
system identifier, since only packets with the
correct predefined sync word will be received if
the sync word detection in RX is enabled in
register MDMCFG2 (see Section 17.1). The
sync word detector correlates against the
user-configured 16 or 32 bit sync word. The
correlation threshold can be set to 15/16,
16/16, or 30/32 bits match. The sync word can
be further qualified using the preamble quality
indicator mechanism described below and/or a
carrier sense condition. The sync word is
configured through the SYNC1 and SYNC0
registers.
In order to make false detections of sync
words less likely, a mechanism called
preamble quality indication (PQI) can be used
to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
order for a detected sync word to be accepted.
See Section 17.2 on page 34 for more details.
15 Packet Handling Hardware Support
The CC2500 has built-in hardware support for
packet oriented radio protocols.


In transmit mode, the packet handler can be
configured to add the following elements to the
packet stored in the TX FIFO:





A programmable number of preamble
bytes
A two byte synchronization (sync) word.
Can be duplicated to give a 4-byte sync
word (recommended). It is not possible to
only insert preamble or only insert a sync
word.
A CRC checksum computed over the data
field
Optionally, two status bytes (see Table 21 and
Table 22) with RSSI value, Link Quality
Indication, and CRC status can be appended
in the RX FIFO.
Bit
Field Name
Description
7:0
RSSI
RSSI value
Table 21: Received Packet Status Byte 1
(first byte appended after the data)
The recommended setting is 4-byte preamble
and 4-byte sync word, except for 500 kBaud
data rate where the recommended preamble
length is 8 bytes.
In addition, the following can be implemented
on the data field and the optional 2-byte CRC
checksum:


Whitening of the data with a PN9
sequence.
Forward error correction by the use of
interleaving and coding of the data
(convolutional coding).
In receive mode, the packet handling support
will de-construct the data packet by
implementing the following (if enabled):



One byte address check
Packet length check (length byte checked
against a programmable maximum length)
De-whitening
De-interleaving and decoding
Bit
Field Name
Description
7
CRC_OK
1: CRC for received data OK (or
CRC disabled)
0: CRC error in received data
6:0
LQI
The Link Quality Indicator
estimates how easily a received
signal can be demodulated
Table 22: Received Packet Status Byte 2
(second byte appended after the data)
Note that register fields that control the packet
handling features should only be altered when
CC2500 is in the IDLE state.
Preamble detection
Sync word detection
CRC computation and CRC check
SWRS040C
Page 28 of 89
CC2500
15.1
Data Whitening
From a radio perspective, the ideal over the air
data are random and DC free. This results in
the smoothest power distribution over the
occupied bandwidth. This also gives the
regulation loops in the receiver uniform
operation conditions (no data dependencies).
Real world data often contain long sequences
of zeros and ones. Performance can then be
improved by whitening the data before
transmitting, and de-whitening the data in the
receiver. With CC2500, this can be done
automatically
by
setting
PKTCTRL0.WHITE_DATA=1. All data, except
the preamble and the sync word, are then
XOR-ed with a 9-bit pseudo-random (PN9)
sequence before being transmitted as shown
in Figure 10. At the receiver end, the data are
XOR-ed with the same pseudo-random
sequence. This way, the whitening is reversed,
and the original data appear in the receiver.
The PN9 sequence is reset to all 1’s.
Data whitening can only be used when
PKTCTRL0.CC2400_EN=0 (default).
Figure 10: Data Whitening in TX Mode
15.2

Packet Format
The format of the data packet can be
configured and consists of the following items
(see Figure 11):
Preamble
Synchronization word
8 x n bits
Data field
16/32 bits
8
bits
8
bits
8 x n bits
Legend:
Inserted automatically in TX,
processed and removed in RX.
CRC-16
Address field
Preamble bits
(1010...1010)
Length field
Optional data whitening
Optionally FEC encoded/decoded
Optional CRC-16 calculation
Sync word





Length byte or constant programmable
packet length
Optional address byte
Payload
Optional 2 byte CRC
Optional user-provided fields processed in TX,
processed but not removed in RX.
Unprocessed user data (apart from FEC
and/or whitening)
16 bits
Figure 11: Packet Format
SWRS040C
Page 29 of 89
CC2500
The preamble pattern is an alternating
sequence of ones and zeros (101010101…).
The minimum length of the preamble is
programmable. When enabling TX, the
modulator will start transmitting the preamble.
When the programmed number of preamble
bytes has been transmitted, the modulator will
send the sync word and then data from the TX
FIFO if data is available. If the TX FIFO is
empty, the modulator will continue to send
preamble bytes until the first byte is written to
the TX FIFO. The modulator will then send the
sync word and then the data bytes. The
number of preamble bytes is programmed with
the MDMCFG1.NUM_PREAMBLE value.
The synchronization word is a two-byte value
set in the SYNC1 and SYNC0 registers. The
sync word provides byte synchronization of the
incoming packet. A one-byte sync word can be
emulated by setting the SYNC1 value to the
preamble pattern. It is also possible to emulate
a
32
bit
sync
word
by
using
MDMCFG2.SYNC_MODE=3 or 7. The sync word
will then be repeated twice.
CC2500 supports both fixed packet length
protocols and variable packet length protocols.
Variable or fixed packet length mode can be
used for packets up to 255 bytes. For longer
packets, infinite packet length mode must be
used.
Fixed packet length mode is selected by
setting PKTCTRL0.LENGTH_CONFIG=0. The
desired packet length is set by the PKTLEN
register.
In
variable
packet
length
mode,
PKTCTRL0.LENGTH_CONFIG=1, the packet
length is configured by the first byte after the
sync word. The packet length is defined as the
payload data, excluding the length byte and
the optional CRC. The PKTLEN register is
used to set the maximum packet length
allowed in RX. Any packet received with a
length byte with a value greater than PKTLEN
will be discarded.
With PKTCTRL0.LENGTH_CONFIG=2, the
packet length is set to infinite and transmission
and reception will continue until turned off
manually. As described in the next section, this
can be used to support packet formats with
different length configuration than natively
supported by CC2500. One should make sure
that TX mode is not turned off during the
transmission of the first half of any byte. Refer
SWRS040C
to the CC2500
details.
Errata Notes [1] for more
Note that the minimum packet length
supported (excluding the optional length byte
and CRC) is one byte of payload data.
15.2.1 Arbitrary Length Field Configuration
The packet length register, PKTLEN, can be
reprogrammed during receive and transmit. In
combination with fixed packet length mode
(PKTCTRL0.LENGTH_CONFIG=0) this opens
the possibility to have a different length field
configuration than supported for variable
length packets (in variable packet length mode
the length byte is the first byte after the sync
word). At the start of reception, the packet
length is set to a large value. The MCU reads
out enough bytes to interpret the length field in
the packet. Then the PKTLEN value is set
according to this value. The end of packet will
occur when the byte counter in the packet
handler is equal to the PKTLEN register. Thus,
the MCU must be able to program the correct
length, before the internal counter reaches the
packet length.
15.2.2 Packet Length > 256 bytes
Also the packet automation control register,
PKTCTRL0, can be reprogrammed during TX
and RX. This opens the possibility to transmit
and receive packets that are longer than 256
bytes and still be able to use the packet
handling hardware support. At the start of the
packet, the infinite packet length mode
(PKTCTRL0.LENGTH_CONFIG=2) must be
active. On the TX side, the PKTLEN register is
set to mod(length,256). On the RX side the
MCU reads out enough bytes to interpret the
length field in the packet and sets the PKTLEN
register to mod(length,256). When less than
256 bytes remains of the packet the MCU
disables infinite packet length mode and
activates fixed packet length mode. When the
internal byte counter reaches the PKTLEN
value, the transmission or reception ends (the
radio enters the state determined by
TXOFF_MODE or RXOFF_MODE). Automatic
CRC appending/checking can also be used
(by setting PKTCTRL0.CRC_EN=1).
When for example a 600-byte packet is to be
transmitted, the MCU should do the following
(see also Figure 12):

Set PKTCTRL0.LENGTH_CONFIG=2.
Page 30 of 89
CC2500

Pre-program the PKTLEN
mod(600,256)=88.

Transmit at least 345 bytes, for example
by filling the 64-byte TX FIFO six times
(384 bytes transmitted).
register
to

Set PKTCTRL0.LENGTH_CONFIG=0.

The transmission ends when the packet
counter reaches 88. A total of 600 bytes
are transmitted.
Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again
0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................
Infinite packet length enabled
600 bytes transmitted and
received
Fixed packet length
enabled when less than
256 bytes remains of
packet
Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88
Figure 12: Packet Length > 256
15.3
Packet Filtering in Receive Mode
CC2500 supports three different types of
packet-filtering: address filtering, maximum
length filtering and CRC filtering.
15.3.1 Address Filtering
Setting PKTCTRL1.ADR_CHK to any other
value than zero enables the packet address
filter. The packet handler engine will compare
the destination address byte in the packet with
the programmed node address in the ADDR
register and the 0x00 broadcast address when
PKTCTRL1.ADR_CHK=10b or both 0x00 and
0xFF
broadcast
addresses
when
PKTCTRL1.ADR_CHK=11b. If the received
address matches a valid address, the packet is
received and written into the RX FIFO. If the
address match fails, the packet is discarded
and receive mode restarted (regardless of the
MCSM1.RXOFF_MODE setting).
If the received address matches a valid
address when using infinite packet length
mode and address filtering is enabled, 0xFF
will be written into the RX FIFO followed by the
address byte and then the payload data.
15.3.2 Maximum Length Filtering
In
variable
packet
length
mode,
PKTCTRL0.LENGTH_CONFIG=1,
the
PKTLEN.PACKET_LENGTH register value is
used to set the maximum allowed packet
length. If the received length byte has a larger
value than this, the packet is discarded and
SWRS040C
receive mode restarted (regardless of the
MCSM1.RXOFF_MODE setting).
15.3.3 CRC Filtering
The filtering of a packet when CRC check fails
is
enabled
by
setting
PKTCTRL1.CRC_AUTOFLUSH=1. The CRC
auto flush function will flush the entire RX
FIFO if the CRC check fails. After auto flushing
the RX FIFO, the next state depends on the
MCSM1.RXOFF_MODE
setting.
PKTCTRL0.CC2400_EN must be 0 (default)
for the CRC auto flush function to work
correctly.
When using the auto flush function, the
maximum packet length is 63 bytes in variable
packet length mode and 64 bytes in fixed
packet length mode. Note that the maximum
allowed packet length is reduced by two bytes
when
PKTCTRL1.APPEND_STATUS
is
enabled, to make room in the RX FIFO for the
two status bytes appended at the end of the
packet. Since the entire RX FIFO is flushed
when the CRC check fails, the previously
received packet must be read out of the FIFO
before receiving the current packet. The MCU
must not read from the current packet until the
CRC has been checked as OK.
15.4
CRC Check
There are two different CRC implementations.
PKTCTRL0.CC2400_EN selects between the
2 options. The CRC check is different for the 2
Page 31 of 89
CC2500
options. Refer also to the CC2500 Errata Notes
[1].
15.4.1 PKTCTRL0.CC2400_EN=0
If PKTCTRL0.CC2400_EN=0 it is possible to
read back the CRC status in 2 different ways:
1) Set PKTCTRL1.APPEND_STATUS=1 and
read the CRC_OK flag in the MSB of the
second byte appended to the RX FIFO after
the packet data. This requires double buffering
of the packet, i.e. the entire packet content of
the RX FIFO must be completely read out
before it is possible to check whether the CRC
indication is OK or not.
2) To avoid reading the entire RX FIFO,
another
solution
is
to
use
the
PKTCTRL1.CRC_AUTOFLUSH feature. If this
feature is enabled, the entire RX FIFO will be
flushed if the CRC check fails. If
GDOx_CFG=0x06 the GDOx pin will be asserted
when a sync word is found. The GDOx pin will
be de-asserted at the end of the packet. When
the latter occurs the MCU should read the
number of bytes in the RX FIFO from the
RXBYTES.NUM_RXBYTES status register. If
RXBYTES.NUM_RXBYTES=0 the CRC check
failed and the FIFO is flushed. If
RXBYTES.NUM_RXBYTES>0 the CRC check
was OK and data can be read out of the FIFO.
15.4.2 PKTCTRL0.CC2400_EN=1
If PKTCTRL0.CC2400_EN=1 the CRC can be
checked as outlined in 1) in Section 15.4.1 as
well as by reading the CRC_OK flag available
in the PKTSTATUS[7] register, in the LQI[7]
status register or from one of the GDO pins if
GDOx_CFG is 0x07 or 0x15.
The PKTCTRL1.CRC_AUTOFLUSH or data
whitening
cannot
be
used
when
PKTCTRL0.CC2400_EN=1.
15.5
Packet Handling in Transmit Mode
The payload that is to be transmitted must be
written into the TX FIFO. The first byte written
must be the length byte when variable packet
length is enabled. The length byte has a value
equal to the payload of the packet (including
the optional address byte). If address
recognition is enabled on the receiver, the
second byte written to the TX FIFO must be
the address byte. If fixed packet length is
enabled, then the first byte written to the TX
FIFO should be the address (if the receiver
uses address recognition).
SWRS040C
The modulator will first send the programmed
number of preamble bytes. If data is available
in the TX FIFO, the modulator will send the
two-byte (optionally 4-byte) sync word and
then the payload in the TX FIFO. If CRC is
enabled, the checksum is calculated over all
the data pulled from the TX FIFO and the
result is sent as two extra bytes following the
payload data. If the TX FIFO runs empty
before the complete packet has been
transmitted,
the
radio
will
enter
TXFIFO_UNDERFLOW state. The only way to
exit this state is by issuing an SFTX strobe.
Writing to the TX FIFO after it has underflowed
will not restart TX mode.
If whitening is enabled, everything following
the sync words will be whitened. This is done
before the optional FEC/Interleaver stage.
Whitening
is
enabled
by
setting
PKTCTRL0.WHITE_DATA=1.
If FEC/Interleaving is enabled, everything
following the sync words will be scrambled by
the interleaver and FEC encoded before being
modulated. FEC is enabled by setting
MDMCFG1.FEC_EN=1.
15.6
Packet Handling in Receive Mode
In receive mode, the demodulator and packet
handler will search for a valid preamble and
the sync word. When found, the demodulator
has obtained both bit and byte synchronism
and will receive the first payload byte.
If FEC/Interleaving is enabled, the FEC
decoder will start to decode the first payload
byte. The interleaver will de-scramble the bits
before any other processing is done to the
data.
If whitening is enabled, the data will be dewhitened at this stage.
When variable packet length mode is enabled,
the first byte is the length byte. The packet
handler stores this value as the packet length
and receives the number of bytes indicated by
the length byte. If fixed packet length mode is
used, the packet handler will accept the
programmed number of bytes.
Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is
enabled, the packet handler computes CRC
and matches it with the appended CRC
checksum.
At the end of the payload, the packet handler
will optionally write two extra packet status
Page 32 of 89
CC2500
bytes that contain CRC status, link quality
indication and RSSI value.
information on how many bytes are in the RX
FIFO and TX FIFO respectively. See Table 33.
b) SPI polling
15.7
Packet Handling in Firmware
When implementing a packet oriented radio
protocol in firmware, the MCU needs to know
when a packet has been received/transmitted.
Additionally, for packets longer than 64 bytes
the RX FIFO needs to be read while in RX and
the TX FIFO needs to be refilled while in TX.
This means that the MCU needs to know the
number of bytes that can be read from or
written to the RX FIFO and TX FIFO
respectively. There are two possible solutions
to get the necessary status information:
a) Interrupt driven solution
In both RX and TX one can use one of the GDO
pins to give an interrupt when a sync word has
been received/transmitted and/or when a
complete
packet
has
been
received/transmitted
(IOCFGx=0x06).
In
addition, there are two configurations for the
IOCFGx register that are associated with the
RX FIFO (IOCFGx=0x00 and IOCFGx=0x01)
and two that are associated with the TX FIFO
(IOCFGx=0x02 and IOCFG=0x03) that can be
used as interrupt sources to provide
The PKTSTATUS register can be polled at a
given rate to get information about the current
GDO2 and GDO0 values respectively. The
RXBYTES and TXBYTES registers can be
polled at a given rate to get information about
the number of bytes in the RX FIFO and TX
FIFO respectively. Alternatively, the number of
bytes in the RX FIFO and TX FIFO can be
read from the chip status byte returned on the
MISO line each time a header byte, data byte,
or command strobe is sent on the SPI bus.
It is recommended to employ an interrupt
driven solution as high rate SPI polling will
reduce the RX sensitivity. Furthermore, as
explained in Section 10.3 and the CC2500
Errata Notes [1], when using SPI polling there
is a small, but finite, probability that a single
read from registers PKTSTATUS, RXBYTES and
TXBYTES is being corrupt. The same is the
case when reading the chip status byte.
Refer to the TI website for SW examples ([6]
and [7]).
16 Modulation Formats
CC2500 supports amplitude, frequency and
phase shift modulation formats. The desired
modulation
format
is
set
in
the
MDMCFG2.MOD_FORMAT register.
Optionally, the data stream can be Manchester
coded by the modulator and decoded by the
demodulator. This option is enabled by setting
MDMCFG2.MANCHESTER_EN=1.
Manchester
encoding is not supported at the same time as
using the FEC/Interleaver option.
16.1
f dev 
f xosc
 (8  DEVIATION _ M )  2 DEVIATION _ E
17
2
The symbol encoding is shown in Table 23.
Format
Symbol
Coding
2-FSK/GFSK
‘0’
– Deviation
‘1’
+ Deviation
Table 23: Symbol Encoding for 2-FSK/GFSK
Modulation
Frequency Shift Keying
2-FSK can optionally be shaped by a
Gaussian filter with BT=1, producing a GFSK
modulated signal.
The frequency deviation is programmed with
the DEVIATION_M and DEVIATION_E values
in the DEVIATN register. The value has an
exponent/mantissa form, and the resultant
deviation is given by:
16.2
Minimum Shift Keying
1
When using MSK , the complete transmission
(preamble, sync word and payload) will be
MSK modulated.
Phase shifts are performed with a constant
transition time.
1
Identical to offset QPSK with half-sine
shaping (data coding may differ)
SWRS040C
Page 33 of 89
CC2500
The fraction of a symbol period used to
change the phase can be modified with the
DEVIATN.DEVIATION_M setting. This is
equivalent to changing the shaping of the
symbol.
16.3
Amplitude Modulation
The supported amplitude modulation On-Off
Keying (OOK) simply turns on or off the PA to
modulate 1 and 0 respectively.
The MSK modulation format implemented in
CC2500
inverts the sync word and data
compared to e.g. signal generators.
17 Received Signal Qualifiers and Link Quality Information
CC2500 has several qualifiers that can be used
to increase the likelihood that a valid sync
word is detected.
17.1
Sync Word Qualifier
If sync word detection in RX is enabled in
register MDMCFG2 the CC2500 will not start
filling the RX FIFO and perform the packet
filtering described in Section 15.3 before a
valid sync word has been detected. The sync
word
qualifier
mode
is
set
by
MDMCFG2.SYNC_MODE and is summarized in
Table 24. Carrier sense in Table 24 is
described in Section 17.4.
MDMCFG2.
SYNC_MODE
Sync Word Qualifier Mode
000
No preamble/sync
001
15/16 sync word bits detected
010
16/16 sync word bits detected
011
30/32 sync word bits detected
100
No preamble/sync, carrier sense
above threshold
101
15/16 + carrier sense above threshold
110
16/16 + carrier sense above threshold
111
30/32 + carrier sense above threshold
A “Preamble Quality Reached” signal can be
observed on one of the GDO pins by setting
IOCFGx.GDOx_CFG=8. It is also possible to
determine if preamble quality is reached by
checking the PQT_REACHED bit in the
PKTSTATUS register. This signal / bit asserts
when the received signal exceeds the PQT.
17.3
RSSI
The RSSI value is an estimate of the signal
level in the chosen channel. This value is
based on the current gain setting in the RX
chain and the measured signal level in the
channel.
Table 24: Sync Word Qualifier Mode
17.2
The preamble quality estimator increases an
internal counter by one each time a bit is
received that is different from the previous bit,
and decreases the counter by 8 each time a
bit is received that is the same as the last bit.
The threshold is configured with the register
field PKTCTRL1.PQT. A threshold of 4∙PQT for
this counter is used to gate sync word
detection. By setting the value to zero, the
preamble quality qualifier of the sync word is
disabled.
Preamble Quality Threshold (PQT)
The Preamble Quality Threshold (PQT) syncword qualifier adds the requirement that the
received sync word must be preceded with a
preamble with a quality above a programmed
threshold.
Another use of the preamble quality threshold
is as a qualifier for the optional RX termination
timer. See Section 19.7 on page 43 for details.
SWRS040C
In RX mode, the RSSI value can be read
continuously from the RSSI status register
until the demodulator detects a sync word
(when sync word detection is enabled). At that
point the RSSI readout value is frozen until the
next time the chip enters the RX state. The
RSSI value is in dBm with ½dB resolution. The
RSSI update rate, fRSSI, depends on the
receiver filter bandwidth (BW channel defined in
Section 13) and AGCCTRL0.FILTER_LENGTH.
f RSSI 
2  BWchannel
8  2 FILTER _ LENGTH
If PKTCTRL1.APPEND_STATUS is enabled the
RSSI value at sync word detection is
Page 34 of 89
CC2500
automatically added to the first byte appended
after the data payload.
Table 25 provides typical values for the
RSSI_offset.
The RSSI value read from the RSSI status
register is a 2’s complement number. The
following procedure can be used to convert the
RSSI reading to an absolute power level
(RSSI_dBm).
Figure 13 shows typical plots of RSSI readings
as a function of input power level for different
data rates.
1) Read the RSSI status register
Data Rate [kBaud]
RSSI_offset [dB]
2.4
71
10
69
250
72
500
72
2) Convert the reading from a hexadecimal
number to a decimal number (RSSI_dec)
3) If RSSI_dec ≥ 128 then RSSI_dBm =
(RSSI_dec - 256)/2 – RSSI_offset
4) Else if RSSI_dec < 128 then RSSI_dBm =
(RSSI_dec)/2 – RSSI_offset
Table 25: Typical RSSI_offset Values
0,0
-10,0
-20,0
RSSI readout [dBm]
-30,0
-40,0
-50,0
-60,0
-70,0
-80,0
-90,0
-100,0
-110,0
-120,0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input power [dBm]
2.4 kBaud
10 kBaud
250 kBaud
250 kBaud, reduced current
500 kBaud
Figure 13: Typical RSSI Value vs. Input Power Level for Some Typical Data Rates
17.4
Carrier Sense (CS)
The Carrier Sense (CS) flag is used as a sync
word qualifier and for CCA. The CS flag can
be set based on two conditions, which can be
individually adjusted:


CS is asserted when the RSSI is above a
programmable absolute threshold, and deasserted when RSSI is below the same
threshold (with hysteresis).
CS is asserted when the RSSI has
increased with a programmable number of
dB from one RSSI sample to the next, and
SWRS040C
de-asserted when RSSI has decreased
with the same number of dB. This setting
is not dependent on the absolute signal
level and is thus useful to detect signals in
environments with a time varying noise
floor.
Carrier Sense can be used as a sync word
qualifier that requires the signal level to be
higher than the threshold for a sync word
search to be performed. The signal can also
be observed on one of the GDO pins by setting
Page 35 of 89
CC2500
IOCFGx.GDOx_CFG=14 and in the status
register bit PKTSTATUS.CS.
CS can be used to avoid interference from e.g.
WLAN.
17.4.1 CS Absolute Threshold
MAX_LNA_GAIN[2:0]
Other uses of Carrier Sense include the TX-ifCCA function (see Section 17.5 on page 37)
and the optional fast RX termination (see
Section 19.7 on page 43).
MAX_DVGA_GAIN[1:0]
The absolute threshold related to the RSSI
value depends on the following register fields:

AGCCTRL2.MAX_LNA_GAIN

AGCCTRL2.MAX_DVGA_GAIN

AGCCTRL1.CARRIER_SENSE_ABS_THR

AGCCTRL2.MAGN_TARGET
00
01
10
11
000
-99
-93
-87
-81.5
001
-97
-90.5
-85
-78.5
010
-93.5
-87
-82
-76
011
-91.5
-86
-80
-74
100
-90.5
-84
-78
-72.5
101
-88
-82.5
-76
-70
110
-84.5
-78.5
-73
-67
111
-82.5
-76
-70
-64
Table 26: Typical RSSI Value in dBm at CS
Threshold with Default MAGN_TARGET at 2.4
kBaud
The MAGN_TARGET setting is a compromise
between blocker tolerance/selectivity and
sensitivity. The value sets the desired signal
level in the channel into the demodulator.
Increasing this value reduces the headroom
for blockers, and therefore close-in selectivity.
®
It is strongly recommended to use SmartRF
Studio
[5]
to
generate
the
correct
MAGN_TARGET setting.
Table 26 and Table 27 show the typical RSSI
readout values at the CS threshold at 2.4
kBaud and 250 kBaud data rate respectively.
The default CARRIER_SENSE_ABS_THR=0 (0
dB) and MAGN_TARGET=3 (33 dB) have been
used.
For other data rates the user must generate
similar tables to find the CS absolute
threshold.
MAX_LNA_GAIN[2:0]
For a given AGCCTRL2.MAX_LNA_GAIN and
AGCCTRL2.MAX_DVGA_GAIN
setting the
absolute threshold can be adjusted ±7 dB in
steps
of
1
dB
using
CARRIER_SENSE_ABS_THR.
MAX_DVGA_GAIN[1:0]
00
01
10
11
000
-96
-90
-84
-78.5
001
-94.5
-89
-83
-77.5
010
-92.5
-87
-81
-75
011
-91
-85
-78.5
-73
100
-87.5
-82
-76
-70
101
-85
-79.5
-73.5
-67.5
110
-83
-76.5
-70.5
-65
111
-78
-72
-66
-60
Table 27: Typical RSSI Value in dBm at CS
Threshold with Default MAGN_TARGET at 250
kBaud
If the threshold is set high, i.e. only strong
signals are wanted, the threshold should be
adjusted upwards by first reducing the
MAX_LNA_GAIN
value
and
then
the
MAX_DVGA_GAIN value. This will reduce
power consumption in the receiver front end,
since the highest gain settings are avoided.
17.4.2 CS Relative Threshold
The relative threshold detects sudden changes
in the measured signal level. This setting is not
dependent on the absolute signal level and is
thus useful to detect signals in environments
with a time varying noise floor. The register
field AGCCTRL1.CARRIER_SENSE_REL_THR
is used to enable/disable relative CS, and to
select threshold of 6 dB, 10 dB or 14 dB RSSI
change
SWRS040C
Page 36 of 89
CC2500
17.5
Clear Channel Assessment (CCA)
The Clear Channel Assessment CCA) is used
to indicate if the current channel is free or
busy. The current CCA state is viewable on
any of the GDO pins by setting IOCFGx.GDOx_
CFG=0x09.
MCSM1.CCA_MODE selects the mode to use
when determining CCA.
When the STX or SFSTXON command strobe is
given while CC2500 is in the RX state, the TX
or FSTXON state is only entered if the clear
channel requirements are fulfilled. The chip
will otherwise remain in RX (if the channel
becomes available, the radio will not enter TX
or FSTXON state before a new strobe
command is sent on the SPI interface). This
feature is called TX-if-CCA. Four CCA
requirements can be programmed: Four CCA
requirements can be programmed:

Always (CCA disabled, always goes to TX)

If RSSI is below threshold

Unless currently receiving a packet

Both the above (RSSI below threshold and
not currently receiving a packet)
17.6
Link Quality Indicator (LQI)
The Link Quality Indicator is a metric of the
current quality of the received signal. If
PKTCTRL1.APPEND_STATUS is enabled, the
value is automatically added to the last byte
appended after the payload. The value can
also be read from the LQI status register. The
LQI gives an estimate of how easily a received
signal can be demodulated by accumulating
the magnitude of the error between ideal
constellations and the received signal over the
64 symbols immediately following the sync
word. LQI is best used as a relative
measurement of the link quality (a high value
indicates a better link than what a low value
does), since the value is dependent on the
modulation format.
18 Forward Error Correction with Interleaving
18.1
Forward Error Correction (FEC)
CC2500 has built in support for Forward Error
Correction (FEC). To enable this option, set
MDMCFG1.FEC_EN to 1. FEC is only supported
in
fixed
packet
length
mode
(PKTCTRL0.LENGTH_CONFIG=0). FEC is
employed on the data field and CRC word in
order to reduce the gross bit error rate when
operating
near
the
sensitivity
limit.
Redundancy is added to the transmitted data
in such a way that the receiver can restore the
original data in the presence of some bit
errors.
The use of FEC allows correct reception at a
lower SNR, thus extending communication
range. Alternatively, for a given SNR, using
FEC decreases the bit error rate (BER). As the
packet error rate (PER) is related to BER by:
PER  1  (1  BER) packet _ length
a lower BER can be used to allow longer
packets, or a higher percentage of packets of
a given length, to be transmitted successfully.
Finally, in realistic ISM radio environments,
transient and time-varying phenomena will
SWRS040C
produce occasional errors even in otherwise
good reception conditions. FEC will mask such
errors and, combined with interleaving of the
coded data, even correct relatively long
periods of faulty reception (burst errors).
The FEC scheme adopted for CC2500 is
convolutional coding, in which n bits are
generated based on k input bits and the m
most recent input bits, forming a code stream
able to withstand a certain number of bit errors
between each coding state (the m-bit window).
The convolutional coder is a rate 1/2 code with
a constraint length of m=4. The coder codes
one input bit and produces two output bits;
hence, the effective data rate is halved. I.e. to
transmit at the same effective data rate when
using FEC, it is necessary to use twice as high
over-the-air data rate. This will require a higher
receiver bandwidth, and thus reduce
sensitivity. In other words, the improved
reception by using FEC and the degraded
sensitivity from a higher receiver bandwidth
will be counteracting factors.
18.2
Interleaving
Data received through radio channels will
often experience burst errors due to
Page 37 of 89
CC2500
interference and time-varying signal strengths.
In order to increase the robustness to errors
spanning multiple bits, interleaving is used
when FEC is enabled. After de-interleaving, a
continuous span of errors in the received
stream will become single errors spread apart.
When FEC and interleaving is used at least
one extra byte is required for trellis
termination. In addition, the amount of data
transmitted over the air must be a multiple of
the size of the interleaver buffer (two bytes).
The packet control hardware therefore
automatically inserts one or two extra bytes at
the end of the packet, so that the total length
of the data to be interleaved is an even
number. Note that these extra bytes are
invisible to the user, as they are removed
before the received packet enters the RX
FIFO.
CC2500 employs matrix interleaving, which is
illustrated in Figure 14. The on-chip
interleaving and de-interleaving buffers are 4 x
4 matrices. In the transmitter, the data bits
from the rate ½ convolutional coder are written
into the rows of the matrix, whereas the bit
sequence to be transmitted is read from the
columns of the matrix. Conversely, in the
receiver, the received symbols are written into
the rows of the matrix, whereas the data
passed onto the convolutional decoder is read
from the columns of the matrix.
When FEC and interleaving is used the
minimum data payload is 2 bytes.
Interleaver
Write buffer
Packet
Engine
Interleaver
Read buffer
FEC
Encoder
Modulator
Interleaver
Write buffer
Interleaver
Read buffer
FEC
Decoder
Demodulator
Packet
Engine
Figure 14: General Principle of Matrix Interleaving
SWRS040C
Page 38 of 89
CC2500
19 Radio Control
SIDLE
SPWD | SWOR
SLEEP
0
CAL_ COMPLETE
MANCAL
3,4,5
IDLE
1
CSn = 0 | WOR
SXOFF
SCAL
CSn = 0
XOFF
2
SRX | STX | SFSTXON | WOR
FS_ WAKEUP
6,7
FS_ AUTOCAL= 01
&
SRX | STX | SFSTXON | WOR
FS_ AUTOCAL= 00 | 10 | 11
&
SRX | STX | SFSTXON | WOR
SETTLING
9,10,11
SFSTXON
CALIBRATE
8
CAL_ COMPLETE
FSTXON
18
STX
STX
SRX | WOR
SFSTXON | RXOFF_ MODE = 01
TXOFF_ MODE=01
SRX
STX | RXOFF_ MODE = 10
TXOFF_ MODE = 10
RXTX_ SETTLING
21
TX
19,20
SRX | TXOFF_ MODE = 11
TXOFF_ MODE = 00
&
FS_ AUTOCAL= 00 | 01
RX
13,14,15
RXOFF_ MODE = 11
TXRX_ SETTLING
16
RXOFF_ MODE= 00
&
FS_ AUTOCAL= 10 | 11
TXOFF_ MODE = 00
&
FS_ AUTOCAL= 10 | 11
TXFIFO_ UNDERFLOW
( STX | SFSTXON) & CCA
|
RXOFF_ MODE= 01 | 10
CALIBRATE
12
RXOFF_ MODE = 00
&
FS_ AUTOCAL= 00 | 01
TXFIFO_UNDERFLOW
22
SFTX
RXFIFO_ OVERFLOW
RXFIFO_OVERFLOW
17
SFRX
IDLE
1
Figure 15: Complete Radio Control State Diagram
CC2500 has a built-in state machine that is
used to switch between different operation
states (modes). The change of state is done
either by using command strobes or by
internal events such as TX FIFO underflow.
readable in the MARCSTATE status register.
This register is primarily for test purposes.
A simplified state diagram, together with
typical usage and current consumption, is
shown in Figure 5 on page 15. The complete
radio control state diagram is shown in Figure
15. The numbers refer to the state number
When the power supply is turned on, the
system must be reset. One of the following two
sequences must be followed: Automatic
power-on reset (POR) or manual reset.
SWRS040C
19.1
Power-On Start-Up Sequence
Page 39 of 89
CC2500
19.1.1 Automatic POR
XOSC and voltage regulator switched on
A power-on reset circuit is included in the
CC2500. The minimum requirements stated in
Section 4.9 must be followed for the power-on
reset to function properly. The internal powerup sequence is completed when CHIP_RDYn
goes low. CHIP_RDYn is observed on the SO
pin after CSn is pulled low. See Section 10.1
for more details on CHIP_RDYn.
When the CC2500 reset is completed the chip
will be in the IDLE state and the crystal
oscillator will be running. If the chip has had
sufficient time for the crystal oscillator to
stabilize after the power-on-reset, the SO pin
will go low immediately after taking CSn low. If
CSn is taken low before reset is completed the
SO pin will first go high, indicating that the
crystal oscillator is not stabilized, before going
low as shown in Figure 16.
40 us
CSn
SO
XOSC Stable
SI
SRES
Figure 17: Power-On Reset with SRES
Note that the above reset procedure is only
required just after the power supply is first
turned on. If the user wants to reset the
CC2500 after this, it is only necessary to issue
an SRES command strobe.
19.2
Crystal Control
The crystal oscillator (XOSC) is either
automatically controlled or always on, if
MCSM0.XOSC_FORCE_ON is set.
Figure 16: Power-On Reset
19.1.2 Manual Reset
The other global reset possibility on CC2500 is
the SRES command strobe. By issuing this
strobe, all internal registers and states are set
to the default, IDLE state. The manual powerup sequence is as follows (see Figure 17):

Set SCLK=1 and SI=0, to avoid potential
problems with pin control mode (see
Section 11.3 on page 26).

Strobe CSn low / high.

Hold CSn high for at least 40 µs relative to
pulling CSn low

Pull CSn low and wait for SO to go low
(CHIP_RDYn).

Issue the SRES strobe on the SI line.

When SO goes low again, reset is
complete and the chip is in the IDLE state.
SWRS040C
In the automatic mode, the XOSC will be
turned off if the SXOFF or SPWD command
strobes are issued; the state machine then
goes to XOFF or SLEEP respectively. This
can only be done from the IDLE state. The
XOSC will be turned off when CSn is released
(goes high). The XOSC will be automatically
turned on again when CSn goes low. The state
machine will then go to the IDLE state. The SO
pin on the SPI interface must be pulled low
before the SPI interface is ready to be used;
as described in Section 10.1 on page 22.
If the XOSC is forced on, the crystal will
always stay on even in the SLEEP state.
Crystal oscillator start-up time depends on
crystal ESR and load capacitances. The
electrical specification for the crystal oscillator
can be found in Section 4.4 on page 12.
19.3
Voltage Regulator Control
The voltage regulator to the digital core is
controlled by the radio controller. When the
chip enters the SLEEP state, which is the state
with the lowest current consumption, the
voltage regulator is disabled. This occurs after
CSn is released when a SPWD command
strobe has been sent on the SPI interface. The
chip is now in the SLEEP state. Setting CSn
low again will turn on the regulator and crystal
Page 40 of 89
CC2500
oscillator and make the chip enter the IDLE
state.
When wake on radio is enabled, the WOR
module will control the voltage regulator as
described in Section 19.5.
19.4
Active Modes
CC2500 has two active modes: receive and
transmit. These modes are activated directly
by the MCU by using the SRX and STX
command strobes, or automatically by Wake
on Radio.
The frequency synthesizer must be calibrated
regularly. CC2500 has one manual calibration
option (using the SCAL strobe), and three
automatic calibration options, controlled by the
MCSM0.FS_AUTOCAL setting:
has been successfully transmitted. Then the
state will change as indicated by the
MCSM1.TXOFF_MODE setting. The possible
destinations are the same as for RX.
The MCU can manually change the state from
RX to TX and vice versa by using the
command strobes. If the radio controller is
currently in transmit and the SRX strobe is
used, the current transmission will be ended
and the transition to RX will be done.
If the radio controller is in RX when the STX or
SFSTXON command strobes are used, the TXif-CCA function will be used. If the channel is
not clear, the chip will remain in RX. The
MCSM1.CCA_MODE
setting
controls
the
conditions for clear channel assessment. See
Section 17.5 on page 37 for details.

Calibrate when going from IDLE to either
RX or TX (or FSTXON)
The SIDLE command strobe can always be
used to force the radio controller to go to the
IDLE state.

Calibrate when going from either RX or TX
to IDLE automatically
19.5

Calibrate every fourth time when going
from either RX or TX to IDLE automatically
If the radio goes from TX or RX to IDLE by
issuing an SIDLE strobe, calibration will not be
performed. The calibration takes a constant
number of XOSC cycles (see Table 28 for
timing details).
When RX is activated, the chip will remain in
receive mode until a packet is successfully
received or the RX termination timer expires
(see Section 19.7). Note: the probability that a
false sync word is detected can be reduced by
using PQT, CS, maximum sync word length
and sync word qualifier mode as describe in
Section 17. After a packet is successfully
received the radio controller will then go to the
state indicated by the MCSM1.RXOFF_MODE
setting. The possible destinations are:

IDLE

FSTXON: Frequency synthesizer on and
ready at the TX frequency. Activate TX
with STX.

TX: Start sending preambles

RX: Start search for a new packet
Similarly, when TX is active the chip will
remain in the TX state until the current packet
SWRS040C
Wake On Radio (WOR)
The optional Wake on Radio (WOR)
functionality enables CC2500 to periodically
wake up from SLEEP and listen for incoming
packets without MCU interaction.
When the SWOR strobe command is sent on
the SPI interface, the CC2500 will go to the
SLEEP state when CSn is released. The RC
oscillator must be enabled before the WOR
strobe can be used, as it is the clock source
for the WOR timer. The on-chip timer will set
CC2500 into the IDLE state and then the RX
state. After a programmable time in RX, the
chip goes back to the SLEEP state, unless a
packet is received. See Figure 18 and Section
19.7 for details on how the timeout works.
Set the CC2500 into the IDLE state to exit
WOR mode.
CC2500 can be set up to signal the MCU that a
packet has been received by using the GDO
pins. If a packet is received, the
MCSM1.RXOFF_MODE
will determine the
behaviour at the end of the received packet.
When the MCU has read the packet, it can put
the chip back into SLEEP with the SWOR strobe
from the IDLE state. The FIFO will lose its
contents in the SLEEP state.
The WOR timer has two events, Event 0 and
Event 1. In the SLEEP state with WOR
activated, reaching Event 0 will turn on the
digital regulator and start the crystal oscillator.
Page 41 of 89
CC2500
Event 1 follows Event 0 after a programmed
timeout.
The time between two consecutive Event 0 is
programmed with a mantissa value given by
WOREVT1.EVENT0 and WOREVT0.EVENT0,
and
an
exponent
value
set
by
WORCTRL.WOR_RES. The equation is:
t Event 0 
750
 EVENT 0  2 5WOR _ RES
f XOSC
The Event 1 timeout is programmed with
WORCTRL.EVENT1. Figure 18 shows the
timing relationship between Event 0 timeout
and Event 1 timeout.
clock. When the chip goes to the SLEEP state,
the RC oscillator will use the last valid
calibration result. The frequency of the RC
oscillator is locked to the main crystal
frequency divided by 750.
In applications where the radio wakes up very
often, typically several times every second, it
is possible to do the RC oscillator calibration
once
and
then
turn
off
calibration
(WORCTRL.RC_CAL=0) to reduce the current
consumption. This requires that RC oscillator
calibration values are read from registers
RCCTRL0_STATUS and RCCTRL1_STATUS
and written back to RCCTRL0 and RCCTRL0
respectively. If the RC oscillator calibration is
turned off it will have to be manually turned on
again if temperature and supply voltage
changes.
Refer to Application Note AN047 [3] for further
details.
19.6
Figure 18: Event 0 and Event 1 Relationship
The time from the CC2500 enters SLEEP state
until the next Event 0 is programmed to
appear (tSLEEP in Figure 18) should be larger
than 11.08 ms when using a 26 MHz crystal
and 10.67 ms when a 27 MHz crystal is used.
If tSLEEP is less than 11.08 (10.67) ms there is a
chance that the consecutive Event 0 will occur
750
 128 seconds
f XOSC
too early. Application Note AN047 [3] explains
in detail the theory of operation and the
different registers involved when using WOR,
as well as highlighting important aspects when
using WOR mode.
19.5.1 RC Oscillator and Timing
The frequency of the low-power RC oscillator
used for the WOR functionality varies with
temperature and supply voltage. In order to
keep the frequency as accurate as possible,
the RC oscillator will be calibrated whenever
possible, which is when the XOSC is running
and the chip is not in the SLEEP state. When
the power and XOSC is enabled, the clock
used by the WOR timer is a divided XOSC
SWRS040C
Timing
The radio controller controls most timing in
CC2500, such as synthesizer calibration, PLL
lock time and RX/TX turnaround times. Timing
from IDLE to RX and IDLE to TX is constant,
dependent on the auto calibration setting.
RX/TX and TX/RX turnaround times are
constant. The calibration time is constant
18739 clock periods. Table 28 shows timing in
crystal clock cycles for key state transitions.
Power on time and XOSC start-up times are
variable, but within the limits stated in Table 7.
Note that in a frequency hopping spread
spectrum or a multi-channel protocol the
calibration time can be reduced from 721 µs to
approximately 150 µs. This is explained in
Section 31.2.
Description
XOSC
Periods
26 MHz
Crystal
IDLE to RX, no calibration
2298
88.4 μs
IDLE to RX, with calibration
~21037
809 μs
IDLE to TX/FSTXON, no calibration
2298
88.4 μs
IDLE to TX/FSTXON, with calibration
~21037
809 μs
TX to RX switch
560
21.5 μs
RX to TX switch
250
9.6 μs
RX or TX to IDLE, no calibration
2
0.1 μs
RX or TX to IDLE, with calibration
~18739
721 μs
Manual calibration
~18739
721 μs
Table 28: State Transition Timing
Page 42 of 89
CC2500
19.7
RX Termination Timer
CC2500 has optional functions for automatic
termination of RX after a programmable time.
The main use for this functionality is wake-onradio (WOR), but it may be useful for other
applications. The termination timer starts when
in RX state. The timeout is programmable with
the MCSM2.RX_TIME setting. When the timer
expires, the radio controller will check the
condition for staying in RX; if the condition is
not met, RX will terminate.
The programmable conditions are:

MCSM2.RX_TIME_QUAL=0:
Continue
receive if sync word has been found

MCSM2.RX_TIME_QUAL=1:
Continue
receive if sync word has been found or
preamble quality is above threshold (PQT)
If the system can expect the transmission to
have started when enabling the receiver, the
MCSM2.RX_TIME_RSSI function can be used.
The radio controller will then terminate RX if
the first valid carrier sense sample indicates
no carrier (RSSI below threshold). See Section
17.4 on page 35 for details on Carrier Sense.
For OOK modulation, lack of carrier sense is
only considered valid after eight symbol
periods. Thus, the MCSM2.RX_TIME_RSSI
function can be used in OOK mode when the
distance between “1” symbols is 8 or less.
If RX terminates due to no carrier sense when
the MCSM2.RX_TIME_RSSI function is used,
or if no sync word was found when using the
MCSM2.RX_TIME timeout function, the chip
will always go back to IDLE if WOR is disabled
and back to SLEEP if WOR is enabled.
Otherwise, the MCSM1.RXOFF_MODE setting
determines the state to go to when RX ends.
This means that the chip will not automatically
go back to SLEEP once a sync word has been
received. It is therefore recommended to
always wake up the microcontroller on sync
word detection when using WOR mode. This
can be done by selecting output signal 6 (see
Table 33 on page 53) on one of the
programmable GDO output
pins, and
programming the microcontroller to wake up
on an edge-triggered interrupt from this GDO
pin.
20 Data FIFO
The CC2500 contains two 64 byte FIFOs, one
for received data and one for data to be
transmitted. The SPI interface is used to read
from the RX FIFO and write to the TX FIFO.
Section 10.5 contains details on the SPI FIFO
access. The FIFO controller will detect
overflow in the RX FIFO and underflow in the
TX FIFO.
When writing to the TX FIFO it is the
responsibility of the MCU to avoid TX FIFO
overflow. A TX FIFO overflow will result in an
error in the TX FIFO content.
Likewise, when reading the RX FIFO the MCU
must avoid reading the RX FIFO past its
empty value, since an RX FIFO underflow will
result in an error in the data read out of the RX
FIFO.
The chip status byte that is available on the SO
pin while transferring the SPI header contains
the fill grade of the RX FIFO if the access is a
read operation and the fill grade of the TX
FIFO if the access is a write operation. Section
10.1 on page 22 contains more details on this.
SWRS040C
The number of bytes in the RX FIFO and TX
FIFO can also be read from the status
registers
RXBYTES.NUM_RXBYTES
and
TXBYTES.NUM_TXBYTES respectively. If a
received data byte is written to the RX FIFO at
the exact same time as the last byte in the RX
FIFO is read over the SPI interface, the RX
FIFO pointer is not properly updated and the
last read byte is duplicated. To avoid this
problem one should never empty the RX FIFO
before the last byte of the packet is received.
For packet lengths less than 64 bytes it is
recommended to wait until the complete
packet has been received before reading it out
of the RX FIFO.
If the packet length is larger than 64 bytes the
MCU must determine how many bytes can be
read
from
the
RX
FIFO
(RXBYTES.NUM_RXBYTES-1) and the following
software routine can be used:
Page 43 of 89
CC2500
1. Read
RXBYTES.NUM_RXBYTES
repeatedly at a rate guaranteed to be at
least twice that of which RF bytes are
received until the same value is returned
twice; store value in n.
FIFO_THR
Bytes in TX FIFO
Bytes in RX FIFO
0 (0000)
61
4
1 (0001)
57
8
2 (0010)
53
12
2. If n < # of bytes remaining in packet, read
n-1 bytes from the RX FIFO.
3 (0011)
49
16
4 (0100)
45
20
3. Repeat steps 1 and 2 until n = # of bytes
remaining in the packet.
5 (0101)
41
24
6 (0110)
37
28
7 (0111)
33
32
8 (1000)
29
36
9 (1001)
25
40
10 (1010)
21
44
11 (1011)
17
48
12 (1100)
13
52
13 (1101)
9
56
14 (1110)
5
60
15 (1111)
1
64
4. Read the remaining bytes from the RX
FIFO.
The 4-bit FIFOTHR.FIFO_THR setting is used
to program threshold points in the FIFOs.
Table 29 lists the 16 FIFO_THR settings and
the corresponding thresholds for the RX and
TX FIFOs. The threshold value is coded in
opposite directions for the RX FIFO and TX
FIFO. This gives equal margin to the overflow
and underflow conditions when the threshold
is reached.
Table 29: FIFO_THR Settings and the
Corresponding FIFO Thresholds
A signal will assert when the number of bytes
in the FIFO is equal to or higher than the
programmed threshold. The signal can be
viewed on the GDO pins (see Section 28 on
page 51).
Figure 20 shows the number of bytes in both
the RX FIFO and TX FIFO when the threshold
flag toggles, in the case of FIFO_THR=13.
Figure 19 shows the signal as the respective
FIFO is filled above the threshold, and then
drained below.
NUM_RXBYTES
Overflow
margin
FIFO_THR=13
56 bytes
53 54 55 56 57 56 55 54 53
FIFO_THR=13
GDO
Underflow
margin
NUM_TXBYTES
6
7
8
9 10 9
8
7
6
RXFIFO
8 bytes
TXFIFO
GDO
Figure 20: Example of FIFOs at Threshold
Figure 19: FIFO_THR=13 vs. Number of
Bytes in FIFO (GDOx_CFG=0x00 in RX and
GDOx_CFG=0x02 in TX)
21 Frequency Programming
The frequency programming in CC2500 is
designed to minimize the programming
needed in a channel-oriented system.
MDMCFG1.CHANSPC_E registers. The channel
spacing registers are mantissa and exponent
respectively.
To set up a system with channel numbers, the
desired channel spacing is programmed with
the
MDMCFG0.CHANSPC_M
and
The base or start frequency is set by the 24 bit
frequency word located in the FREQ2, FREQ1
and FREQ0 registers. This word will typically
SWRS040C
Page 44 of 89
CC2500
be set to the centre of the lowest channel
frequency that is to be used.
The desired channel number is programmed
with the 8-bit channel number register,
f carrier 


f XOSC
 FREQ  CHAN  256  CHANSPC _ M   2 CHANSPC _ E 2
216
With a 26 MHz crystal the maximum channel
spacing is 405 kHz. To get e.g. 1 MHz channel
spacing one solution is to use 333 kHz
channel spacing and select each third channel
in CHANNR.CHAN.
The preferred IF frequency is programmed
with the FSCTRL1.FREQ_IF register. The IF
frequency is given by:
f IF 
CHANNR.CHAN, which is multiplied by the
channel offset. The resultant carrier frequency
is given by:
f XOSC
 FREQ _ IF
210

®
Note that the SmartRF Studio software [5]
automatically
calculates
the
optimum
FSCTRL1.FREQ_IF register setting based on
channel spacing and channel filter bandwidth.
If any frequency programming register is
altered when the frequency synthesizer is
running, the synthesizer may give an
undesired response. Hence, the frequency
programming should only be updated when
the radio is in the IDLE state.
22 VCO
The VCO is completely integrated on-chip.
22.1
VCO and PLL Self-Calibration
The VCO characteristics will vary with
temperature and supply voltage changes, as
well as the desired operating frequency. In
order to ensure reliable operation, CC2500
includes frequency synthesizer self-calibration
circuitry. This calibration should be done
regularly, and must be performed after turning
on power and before using a new frequency
(or channel). The number of XOSC cycles for
completing the PLL calibration is given in
Table 28 on page 42.
The calibration can be initiated automatically
or manually. The synthesizer can be
automatically calibrated each time the
synthesizer is turned on, or each time the
synthesizer is turned off automatically. This is
configured with the MCSM0.FS_AUTOCAL
register setting. In manual mode, the
calibration is initiated when the SCAL
command strobe is activated in the IDLE
mode.
SWRS040C
Note that the calibration values are maintained
in SLEEP mode, so the calibration is still valid
after waking up from SLEEP mode (unless
supply voltage or temperature has changed
significantly).
To check that the PLL is in lock the user can
program register IOCFGx.GDOx_CFG to 0x0A
and use the lock detector output available on
the GDOx pin as an interrupt for the MCU (x =
0,1 or 2). A positive transition on the GDOx pin
means that the PLL is in lock. As an alternative
the user can read register FSCAL1. The PLL is
in lock if the register content is different from
0x3F. Refer also to the CC2500 Errata Notes
[1]. For more robust operation the source code
could include a check so that the PLL is recalibrated until PLL lock is achieved if the PLL
does not lock the first time.
Page 45 of 89
CC2500
23 Voltage Regulators
CC2500 contains several on-chip linear voltage
regulators, which generate the supply voltage
needed by low-voltage modules. These
voltage regulators are invisible to the user, and
can be viewed as integral parts of the various
modules. The user must however make sure
that the absolute maximum ratings and
required pin voltages in Table 1 and Table 13
are not exceeded. The voltage regulator for
the digital core requires one external
decoupling capacitor.
If the chip is programmed to enter power-down
mode, (SPWD strobe issued), the power will be
turned off after CSn goes high. The power and
crystal oscillator will be turned on again when
CSn goes low.
The voltage regulator output should only be
used for driving the CC2500.
Setting the CSn pin low turns on the voltage
regulator to the digital core and starts the
crystal oscillator. The SO pin on the SPI
interface must go low before the first positive
edge of SCLK (setup time is given in Table
16).
24 Output Power Programming
The RF output power level from the device has
two levels of programmability, as illustrated in
Figure 21.
The RF output power level from the device is
programmed through the PATABLE register.


If 2-FSK, GFSK or MSK modulation is
used the desired output power is
programmed to index 0 in the PATABLE
register (PATABLE(0)[7:0]). The 3-bit
FREND0.PA_POWER value shall be set to 0
(reset default value).
If OOK modulation is used the desired
output power for the logic 0 and logic 1
power levels are programmed to index 0
and index 1 in the PATABLE register
respectively (PATABLE(0)[7:0] and
PATABLE(1)[7:0]).
The
3-bit
SWRS040C
FREND0.PA_POWER value shall be set to
1.
Table 31 contains recommended PATABLE
settings for various output levels and
frequency bands. See Section 10.6 on page
24 for PATABLE programming details. The
SmartRF Studio software [5] should be used
to obtain optimum PATABLE settings for
various output powers.
PATABLE must be programmed in burst mode
if writing to other entries than PATABLE(0)
(OOK modulation). Note that all content of the
PATABLE, except for the first byte (index 0) is
lost when entering the SLEEP state.
Page 46 of 89
CC2500
Figure 21: PA_POWER and PATABLE
Default power setting
Output power,
typical [dBm]
Current consumption,
typical [mA]
0xC6
-12
11.1
Table 30: Output Power and Current Consumption for Default PATABLE Setting
Output Power,
Typical, +25°C, 3.0 V [dBm]
PATABLE
Value
Current Consumption,
Typical [mA]
(–55 or less)
0x00
8.4
–30
0x50
9.9
–28
0x44
9.7
–26
0xC0
10.2
–24
0x84
10.1
–22
0x81
10.0
–20
0x46
10.1
–18
0x93
11.7
–16
0x55
10.8
–14
0x8D
12.2
–12
0xC6
11.1
–10
0x97
12.2
–8
0x6E
14.1
–6
0x7F
15.0
–4
0xA9
16.2
–2
0xBB
17.7
0
0xFE
21.2
+1
0xFF
21.5
Table 31: Optimum PATABLE Settings for Various Output Power Levels
SWRS040C
Page 47 of 89
CC2500
25 Selectivity
Figure 22 to Figure 26 show the typical selectivity performance (adjacent and alternate rejection).
50
40
Selectivity [dB]
30
20
10
0
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-10
Frequency offset [MHz]
Figure 22: Typical Selectivity at 2.4 kBaud. IF Frequency is 273.9 kHz.
MDMCFG2.DEM_DCFILT_OFF=1
40
35
30
Selectivity [dB]
25
20
15
10
5
0
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-5
-10
Fre que ncy offse t [M Hz]
Figure 23: Typical Selectivity at 10 kBaud. IF Frequency is 273.9 kHz.
MDMCFG2.DEM_DCFILT_OFF=1
SWRS040C
Page 48 of 89
CC2500
50
40
Selectivity [dB]
30
20
10
0
-3
-2
-1
0
1
2
3
-10
-20
Frequency offset [MHz]
Figure 24: Typical Selectivity at 250 kBaud. IF Frequency is 177.7 kHz.
MDMCFG2.DEM_DCFILT_OFF=0
50
40
Selectivity [dB]
30
20
10
0
-3
-2
-1
0
1
2
3
-10
-20
Frequency offset [MHz]
Figure 25: Typical Selectivity at 250 kBaud. IF Frequency is 457 kHz.
MDMCFG2.DEM_DCFILT_OFF=1
35
30
25
20
Selectivity [dB]
15
10
5
0
-3
-2
-1
0
1
2
3
-5
-10
-15
-20
Frequency offse t [MHz]
Figure 26: Typical Selectivity at 500 kBaud. IF Frequency is 304.7 kHz.
MDMCFG2.DEM_DCFILT_OFF=0
SWRS040C
Page 49 of 89
CC2500
26 Crystal Oscillator
A crystal in the frequency range 26-27 MHz
must be connected between the XOSC_Q1 and
XOSC_Q2 pins. The oscillator is designed for
parallel mode operation of the crystal. In
addition, loading capacitors (C81 and C101)
for the crystal are required. The loading
capacitor values depend on the total load
capacitance, CL, specified for the crystal. The
total load capacitance seen between the
crystal terminals should equal CL for the
crystal to oscillate at the specified frequency.
CL 
The crystal oscillator circuit is shown in Figure
27. Typical component values for different
values of CL are given in Table 32.
The crystal oscillator is amplitude regulated.
This means that a high current is used to start
up the oscillations. When the amplitude builds
up, the current is reduced to what is necessary
to maintain approximately 0.4 Vpp signal
swing. This ensures a fast start-up, and keeps
the drive level to a minimum. The ESR of the
crystal should be within the specification in
order to ensure a reliable start-up (see Section
4.4 on page 12).
1
 C parasitic
1
1

C81 C101
XOSC_Q1
XOSC_Q2
XTAL
The parasitic capacitance is constituted by pin
input capacitance and PCB stray capacitance.
Total parasitic capacitance is typically 2.5 pF.
C81
C101
Figure 27: Crystal Oscillator Circuit
Component
CL= 10 pF
CL=13 Pf
CL=16 pF
C81
15 pF
22 pF
27 pF
C101
15 pF
22 pF
27 pF
Table 32: Crystal Oscillator Component Values
26.1
Reference Signal
The chip can alternatively be operated with a
reference signal from 26 to 27 MHz instead of
a crystal. This input clock can either be a fullswing digital signal (0 V to VDD) or a sine
wave of maximum 1 V peak-peak amplitude.
The reference signal must be connected to the
XOSC_Q1 input. The sine wave must be
connected to XOSC_Q1 using a serial
capacitor. When using a full-swing digital
signal this capacitor can be omitted. The
XOSC_Q2 line must be left un-connected. C81
and C101 can be omitted when using a
reference signal.
27 External RF Match
The balanced RF input and output of CC2500
share two common pins and are designed for
a simple, low-cost matching and balun network
on the printed circuit board. The receive- and
transmit switching at the CC2500 front-end is
controlled by a dedicated on-chip function,
eliminating the need for an external RX/TXswitch.
A few passive external components combined
with the internal RX/TX switch/termination
SWRS040C
circuitry ensures match in both RX and TX
mode.
Although CC2500 has a balanced RF
input/output, the chip can be connected to a
single-ended antenna with few external low
cost capacitors and inductors.
The
passive
matching/filtering
network
connected to CC2500 should have the following
differential impedance as seen from the RFport (RF_P and RF_N) towards the antenna:
Page 50 of 89
CC2500
Zout = 80 + j74 Ω
To ensure optimal matching of the CC2500
differential output it is highly recommended to
follow the CC2500EM reference designs [4] as
closely as possible. Gerber files for the
reference designs are available for download
from the TI website.
28 PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be filled
with metallization connected to ground using
several vias.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias for good thermal
performance and sufficiently low inductance to
ground. In the CC2500EM reference designs
[4] 5 vias are placed inside the exposed die
attached pad. These vias should be “tented”
(covered with solder mask) on the component
side of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%.
See Figure 28 for top solder resist and top
paste masks. See Figure 30 for recommended
PCB layout for QLP 20 package.
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed to decouple. Each decoupling
capacitor should be connected to the power
line by separate vias. The best routing is from
the power line to the decoupling capacitor and
then to the CC2500 supply pin. Supply power
filtering is very important.
Each decoupling capacitor ground pad should
be connected to the ground plane using a
separate via. Direct connections between
neighboring power pins will increase noise
coupling and should be avoided unless
absolutely necessary.
The external components should ideally be as
small as possible (0402 is recommended) and
surface
mount
devices
are
highly
recommended. Please note that components
smaller than those specified may have
differing characteristics.
Precaution should be used when placing the
microcontroller in order to avoid noise
interfering with the RF circuitry.
A CC2500/2550DK Development Kit with a
fully assembled CC2500EM Evaluation
Module is available. It is strongly advised that
this reference layout is followed very closely in
order to get the best performance. The
schematic, BOM and layout Gerber files are all
available from the TI website [4].
Figure 28: Left: Top Solder Resist Mask (negative). Right: Top Paste Mask. Circles are Vias.
SWRS040C
Page 51 of 89
CC2500
29 General Purpose / Test Output Control Pins
The three digital output pins GDO0, GDO1 and
GDO2 are general control pins configured with
IOCFG0.GDO0_CFG,
IOCFG1.GDO1_CFG
and IOCFG2.GDO2_CFG respectively. Table
33 shows the different signals that can be
monitored on the GDO pins. These signals can
be used as inputs to the MCU. GDO1 is the
same pin as the SO pin on the SPI interface,
thus the output programmed on this pin will
only be valid when CSn is high. The default
value for GDO1 is 3-stated, which is useful
when the SPI interface is shared with other
devices.
The default value for GDO0 is a 135-141 kHz
clock output (XOSC frequency divided by 192).
Since the XOSC is turned on at power-onreset, this can be used to clock the MCU in
systems with only one crystal. When the MCU
is up and running, it can change the clock
frequency by writing to IOCFG0.GDO0_CFG.
IOCFG0.GDO0_CFG register. The voltage on
the GDO0 pin is then proportional to
temperature. See Section 4.7 on page 14 for
temperature sensor specifications.
If the IOCFGx.GDO0_CFG setting is less than
0x20 and IOCFGx_GDOx_INV is 0 (1), the
GDO0 and GDO2 pins will be hardwired to 0 (1)
and the GDO1 pin will be hardwired to 1 (0) in
the SLEEP state. These signals will be
hardwired until the CHIP_RDYn signal goes
low.
If the IOCFGx.GDO0_CFG setting is 0x20 or
higher the GDO pins will work as programmed
also in SLEEP state. As an example, GDO1 is
high
impedance
in
all
states
if
IOCFG1.GDO0_CFG=0x2E.
An on-chip analog temperature sensor is
enabled by writing the value 128 (0x80) to the
SWRS040C
Page 52 of 89
CC2500
GDOx_CFG[5:0]]
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
to
21 (0x15)
22 (0x16)
23 (0x17)
24 (0x18)
25 (0x19)
26 (0x1A)
27 (0x1B)
28 (0x1C)
29 (0x1D)
30 (0x1E)
to
35 (0x23)
36 (0x24)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29)
42 (0x2A)
43 (0x2B)
44 (0x2C)
45 (0x2D)
46 (0x2E)
47 (0x2F)
48 (0x30)
49 (0x31)
50 (0x32)
51 (0x33)
52 (0x34)
53 (0x35)
54 (0x36)
55 (0x37)
56 (0x38)
57 (0x39)
58 (0x3A)
59 (0x3B)
60 (0x3C)
61 (0x3D)
62 (0x3E)
63 (0x3F)
Description
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX
FIFO is drained below the same threshold.
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is
reached. De-asserts when the RX FIFO is empty.
Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the
TX FIFO is below the same threshold.
Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO
threshold.
Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert
when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.
Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO. Only
valid if PKTCTRL0.CC2400_EN=1.
Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.
Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting)
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To
check for PLL lock the lock detector output should be used as an interrupt for the MCU.
Serial Clock. Synchronous to the data in synchronous serial mode.
In RX mode, data is set up on the falling edge by CC2500 when GDOx_INV=0.
In TX mode, data is sampled by CC2500 on the rising edge of the serial clock when GDOx_INV=0.
Serial Synchronous Data Output (DO). Used for synchronous serial mode.
Serial Data Output. Used for asynchronous serial mode.
Carrier sense. High if RSSI level is above threshold.
CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. Only valid if
PKTCTRL0.CC2400_EN=1.
Reserved – used for test.
RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX
switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX
switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output.
Reserved – used for test.
WOR_EVNT0
WOR_EVNT1
Reserved – used for test.
CLK_32k
Reserved – used for test.
CHIP_RDYn
Reserved – used for test.
XOSC_STABLE
Reserved – used for test.
GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
High impedance (3-state)
HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch.
CLK_XOSC/1
CLK_XOSC/1.5
CLK_XOSC/2
CLK_XOSC/3
CLK_XOSC/4
CLK_XOSC/6
CLK_XOSC/8
Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any
CLK_XOSC/12
time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must
be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
CLK_XOSC/16
CLK_XOSC/24
CLK_XOSC/32
CLK_XOSC/48
CLK_XOSC/64
CLK_XOSC/96
CLK_XOSC/128
CLK_XOSC/192
Table 33: GDOx Signal Selection (x = 0, 1 or 2)
SWRS040C
Page 53 of 89
CC2500
30 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have
been included in the CC2500 to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller and
simplify software development.
30.1
Asynchronous Operation
For backward compatibility with systems
already using the asynchronous data transfer
from other Chipcon products, asynchronous
transfer is also included in CC2500. When
asynchronous transfer is enabled, several of
the support mechanisms for the MCU that are
included in CC2500 will be disabled, such as
packet handling hardware, buffering in the
FIFO and so on. The asynchronous transfer
mode does not allow the use of the data
whitener, interleaver, and FEC, and it is not
possible to use Manchester encoding.
Note that MSK is
asynchronous transfer.
not
supported
Setting
PKTCTRL0.PKT_FORMAT
enables asynchronous serial mode.
to
for
3
In TX, the GDO0 pin is used for data input (TX
data). Data output can be on GDO0, GDO1 or
GDO2. This is set by the IOCFG0.GDO0_CFG,
IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG
fields.
30.2
Synchronous Serial Operation
Setting
PKTCTRL0.PKT_FORMAT
to
1
enables synchronous serial mode. In the
synchronous serial mode, data is transferred
on a two wire serial interface. The CC2500
provides a clock that is used to set up new
data on the data input line or sample data on
the data output line. Data input (TX data) is the
GDO0 pin. This pin will automatically be
configured as an input when TX is active. The
data output pin can be any of the GDO pins;
this is set by the IOCFG0.GDO0_CFG,
IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG
fields.
Preamble and sync word insertion/detection
may or may not be active, dependent on the
sync mode set by the MDMCFG2.SYNC_MODE.
If preamble and sync word is disabled, all
other packet handler features and FEC should
also be disabled. The MCU must then handle
preamble and sync word insertion and
detection in software. If preamble and sync
word insertion/detection is left on, all packet
handling features and FEC can be used. One
exception is that the address filtering feature is
unavailable in synchronous serial mode.
When using the packet handling features in
synchronous serial mode, the CC2500 will
insert and detect the preamble and sync word
and the MCU will only provide/get the data
payload.
This
is
equivalent
to
the
recommended FIFO operation mode.
The CC2500 modulator samples the level of the
asynchronous input 8 times faster than the
programmed data rate. The timing requirement
for the asynchronous stream is that the error in
the bit period must be less than one eighth of
the programmed data rate.
31 System Considerations and Guidelines
31.1
SRD Regulations
International regulations and national laws
regulate the use of radio receivers and
transmitters. The most important regulations
for the 2.4 GHz band are EN 300 440 and EN
300 328 (Europe), FCC CFR47 part 15.247
and 15.249 (USA), and ARIB STD-T66
(Japan). A summary of the most important
SWRS040C
aspects of these regulations can be found in
Application Note AN032 [2].
Please note that compliance with regulations
is
dependent
on
complete
system
performance. It is the customer’s responsibility
to ensure that the system complies with
regulations.
Page 54 of 89
CC2500
31.2
Frequency Hopping
Channel Systems
and
Multi-
The 2.400 – 2.4835 GHz band is shared by
many systems both in industrial, office and
home
environments.
It
is
therefore
recommended to use frequency hopping
spread spectrum (FHSS) or a multi-channel
protocol because the frequency diversity
makes the system more robust with respect to
interference from other systems operating in
the same frequency band. FHSS also combats
multipath fading.
CC2500 is highly suited for FHSS or multichannel systems due to its agile frequency
synthesizer and effective communication
interface. Using the packet handling support
and data buffering is also beneficial in such
systems as these features will significantly
offload the host controller.
Charge pump current, VCO current and VCO
capacitance array calibration data is required
for each frequency when implementing
frequency hopping for CC2500. There are 3
ways of obtaining the calibration data from the
chip:
1) Frequency hopping with calibration for each
hop. The PLL calibration time is approximately
720 µs. The blanking interval between each
frequency hop is then approximately 810 us.
2) Fast frequency hopping without calibration
for each hop can be done by calibrating each
frequency at startup and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values
in MCU memory. Between each frequency
hop, the calibration process can then be
replaced by writing the FSCAL3, FSCAL2 and
FSCAL1 register values corresponding to the
next RF frequency. The PLL turn on time is
approximately 90 µs. The blanking interval
between each frequency hop is then
approximately 90 us. The VCO current
calibration result is available in FSCAL2 and is
not dependent on the RF frequency. Neither is
the charge pump current calibration result
available in FSCAL3. The same value can
therefore be used for all frequencies.
3) Run calibration on a single frequency at
startup. Next write 0 to FSCAL3[5:4] to
disable the charge pump calibration. After
writing to FSCAL3[5:4] strobe SRX (or STX)
with MCSM0.FS_AUTOCAL=1 for each new
frequency hop. That is, VCO current and VCO
capacitance calibration is done but not charge
pump current calibration. When charge pump
current calibration is disabled the calibration
SWRS040C
time is reduced from approximately 720 µs to
approximately 150 µs. The blanking interval
between each frequency hop is then
approximately 240 us
There is a trade off between blanking time and
memory space needed for storing calibration
data in non-volatile memory. Solution 2) above
gives the shortest blanking interval, but
requires more memory space to store
calibration
values.
Solution
3)
gives
approximately 570 µs smaller blanking interval
than solution 1).
31.3
Wideband Modulation not Using
Spread Spectrum
Digital modulation systems under FCC part
15.247 includes 2-FSK and GFSK modulation.
A maximum peak output power of 1 W (+30
dBm) is allowed if the 6 dB bandwidth of the
modulated signal exceeds 500 kHz. In
addition, the peak power spectral density
conducted to the antenna shall not be greater
than +8 dBm in any 3 kHz band.
Operating at high data rates and high
frequency separation, the CC2500 is suited for
systems targeting compliance with digital
modulation systems as defined by FCC part
15.247. An external power amplifier is needed
to increase the output above +1 dBm.
31.4
Data Burst Transmissions
The high maximum data rate of CC2500 opens
up for burst transmissions. A low average data
rate link (e.g. 10 kBaud), can be realized using
a higher over-the-air data rate. Buffering the
data and transmitting in bursts at high data
rate (e.g. 500 kBaud) will reduce the time in
active mode, and hence also reduce the
average current consumption significantly.
Reducing the time in active mode will reduce
the likelihood of collisions with other systems,
e.g. WLAN.
31.5
Continuous Transmissions
In data streaming applications the CC2500
opens up for continuous transmissions at 500
kBaud effective data rate. As the modulation is
done with a closed loop PLL, there is no
limitation in the length of a transmission.
(Open loop modulation used in some
transceivers often prevents this kind of
continuous data streaming and reduces the
effective data rate.)
Page 55 of 89
CC2500
31.6
Crystal Drift Compensation
3. The CC25XX Folded Dipole reference
design [8] contains schematics and layout files
for a CC2500EM with a folded dipole PCB
antenna. Please see DN004 [9] for more
details on this design.
The CC2500 has a very fine frequency
resolution (see Table 9). This feature can be
used to compensate for frequency offset and
drift.
A HC-49 type SMD crystal is used in the
CC2500EM reference design [4]. Note that the
crystal package strongly influences the price.
In a size constrained PCB design a smaller,
but more expensive, crystal may be used.
The frequency offset between an ‘external’
transmitter and the receiver is measured in the
CC2500 and can be read back from the
FREQEST status register as described in
Section 14.1. The measured frequency offset
can be used to calibrate the frequency using
the ‘external’ transmitter as the reference. That
is, the received signal of the device will match
the receiver’s channel filter better. In the same
way the centre frequency of the transmitted
signal will match the ‘external’ transmitter’s
signal.
31.7
31.9
In low power applications, the SLEEP state
with the crystal oscillator core switched off
should be used when the CC2500 is not active.
It is possible to leave the crystal oscillator core
running in the SLEEP state if start-up time is
critical.
Spectrum Efficient Modulation
The WOR functionality should be used in low
power applications.
CC2500 also has the possibility to use
Gaussian shaped 2-FSK (GFSK). This
spectrum-shaping feature improves adjacent
channel
power
(ACP)
and
occupied
bandwidth. In ‘true’ 2-FSK systems with abrupt
frequency shifting, the spectrum is inherently
broad. By making the frequency shift ‘softer’,
the spectrum can be made significantly
narrower. Thus, higher data rates can be
transmitted in the same bandwidth using
GFSK.
31.8
Battery Operated Systems
31.10
Increasing Output Power
In some applications it may be necessary to
extend the link range. Adding an external
power amplifier is the most effective way of
doing this.
The power amplifier should be inserted
between the antenna and the balun, and two
T/R switches are needed to disconnect the PA
in RX mode. See Figure 29.
Low Cost Systems
A differential antenna will eliminate the need
for a balun, and the DC biasing can be
achieved in the antenna topology, see Figure
Antenna
Filter
PA
Balun
T/R switch
CC2500
T/R switch
Figure 29. Block Diagram of CC2500 Usage with External Power Amplifier
SWRS040C
Page 56 of 89
CC2500
32 Configuration Registers
The configuration of CC2500 is done by
programming 8-bit registers. The optimum
configuration data based on selected system
parameters are most easily found by using the
SmartRF Studio software [5]. Complete
descriptions of the registers are given in the
following tables. After chip reset, all the
registers have default values as shown in the
tables. The optimum register setting might
differ from the default value. After a reset all
registers that shall be different from the default
value therefore needs to be programmed
through the SPI interface.
There are also 12 status registers, which are
listed in Table 36. These registers, which are
read-only, contain information about the status
of CC2500.
There are 13 command strobe registers, listed
in Table 34. Accessing these registers will
initiate the change of an internal state or
mode. There are 47 normal 8-bit configuration
registers, listed in Table 35. Many of these
registers are for test purposes only, and need
not be written for normal operation of CC2500.
Table 37 summarizes the SPI address space.
The address to use is given by adding the
base address to the left and the burst and R/W
bits on the top. Note that the burst bit has
different meaning for base addresses above
and below 0x2F.
The two FIFOs are accessed through one 8-bit
register. Write operations write to the TX FIFO,
while read operations read from the RX FIFO.
During the header byte transfer and while
writing data to a register or the TX FIFO, a
status byte is returned on the SO line. This
status byte is described in Table 17 on page
23.
Address
Strobe
Name
Description
0x30
SRES
Reset chip.
0x31
SFSTXON
0x32
SXOFF
0x33
SCAL
Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without
setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
0x34
SRX
Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.
0x35
STX
In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
If in RX state and CCA is enabled: Only go to TX if channel is clear.
0x36
SIDLE
Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
0x38
SWOR
Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if
WORCTRL.RC_PD=0.
0x39
SPWD
Enter power down mode when CSn goes high.
0x3A
SFRX
Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states.
0x3B
SFTX
Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
0x3C
SWORRST
0x3D
SNOP
Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
Turn off crystal oscillator.
Reset real time clock to Event1 value.
No operation. May be used to get access to the chip status byte.
Table 34: Command Strobes
SWRS040C
Page 57 of 89
CC2500
Preserved in
SLEEP State
Details on
Page Number
GDO2 output pin configuration
Yes
61
IOCFG1
GDO1 output pin configuration
Yes
61
IOCFG0
GDO0 output pin configuration
Yes
61
0x03
FIFOTHR
RX FIFO and TX FIFO thresholds
Yes
62
0x04
SYNC1
Sync word, high byte
Yes
62
0x05
SYNC0
Sync word, low byte
Yes
62
0x06
PKTLEN
Packet length
Yes
62
0x07
PKTCTRL1
Packet automation control
Yes
63
0x08
PKTCTRL0
Packet automation control
Yes
64
Address
Register
Description
0x00
IOCFG2
0x01
0x02
0x09
ADDR
Device address
Yes
64
0x0A
CHANNR
Channel number
Yes
64
0x0B
FSCTRL1
Frequency synthesizer control
Yes
65
0x0C
FSCTRL0
Frequency synthesizer control
Yes
65
0x0D
FREQ2
Frequency control word, high byte
Yes
65
0x0E
FREQ1
Frequency control word, middle byte
Yes
65
0x0F
FREQ0
Frequency control word, low byte
Yes
65
0x10
MDMCFG4
Modem configuration
Yes
66
0x11
MDMCFG3
Modem configuration
Yes
66
0x12
MDMCFG2
Modem configuration
Yes
67
0x13
MDMCFG1
Modem configuration
Yes
68
0x14
MDMCFG0
Modem configuration
Yes
68
0x15
DEVIATN
Modem deviation setting
Yes
69
0x16
MCSM2
Main Radio Control State Machine configuration
Yes
70
0x17
MCSM1
Main Radio Control State Machine configuration
Yes
71
0x18
MCSM0
Main Radio Control State Machine configuration
Yes
72
0x19
FOCCFG
Frequency Offset Compensation configuration
Yes
73
0x1A
BSCFG
Bit Synchronization configuration
Yes
74
0x1B
AGCTRL2
AGC control
Yes
75
0x1C
AGCTRL1
AGC control
Yes
76
0x1D
AGCTRL0
AGC control
Yes
77
0x1E
WOREVT1
High byte Event 0 timeout
Yes
77
0x1F
WOREVT0
Low byte Event 0 timeout
Yes
78
0x20
WORCTRL
Wake On Radio control
Yes
78
0x21
FREND1
Front end RX configuration
Yes
78
0x22
FREND0
Front end TX configuration
Yes
79
0x23
FSCAL3
Frequency synthesizer calibration
Yes
79
0x24
FSCAL2
Frequency synthesizer calibration
Yes
79
0x25
FSCAL1
Frequency synthesizer calibration
Yes
80
0x26
FSCAL0
Frequency synthesizer calibration
Yes
80
0x27
RCCTRL1
RC oscillator configuration
Yes
80
0x28
RCCTRL0
RC oscillator configuration
Yes
80
0x29
FSTEST
Frequency synthesizer calibration control
No
80
0x2A
PTEST
Production test
No
80
0x2B
AGCTEST
AGC test
No
81
0x2C
TEST2
Various test settings
No
81
0x2D
TEST1
Various test settings
No
81
0x2E
TEST0
Various test settings
No
81
Table 35: Configuration Registers Overview
SWRS040C
Page 58 of 89
CC2500
Description
Details on
Page Number
Address
Register
0x30 (0xF0)
PARTNUM
CC2500 part number
81
0x31 (0xF1)
VERSION
Current version number
81
0x32 (0xF2)
FREQEST
Frequency offset estimate
81
0x33 (0xF3)
LQI
Demodulator estimate for Link Quality
82
0x34 (0xF4)
RSSI
Received signal strength indication
82
0x35 (0xF5)
MARCSTATE
Control state machine state
82
0x36 (0xF6)
WORTIME1
High byte of WOR timer
83
0x37 (0xF7)
WORTIME0
Low byte of WOR timer
83
0x38 (0xF8)
PKTSTATUS
Current GDOx status and packet status
83
0x39 (0xF9)
VCO_VC_DAC
Current setting from PLL calibration module
83
0x3A (0xFA)
TXBYTES
Underflow and number of bytes in the TX FIFO
83
0x3B (0xFB)
RXBYTES
Overflow and number of bytes in the RX FIFO
84
0x3C (0xFC)
RCCTRL1_STATUS
Last RC oscillator calibration result
84
0x3D (0xFD)
RCCTRL0_STATUS
Last RC oscillator calibration result
84
Table 36: Status Registers Overview
SWRS040C
Page 59 of 89
CC2500
Single byte
+0x80
Burst
+0xC0
IOCFG2
IOCFG1
IOCFG0
FIFOTHR
SYNC1
SYNC0
PKTLEN
PKTCTRL1
PKTCTRL0
ADDR
CHANNR
FSCTRL1
FSCTRL0
FREQ2
FREQ1
FREQ0
MDMCFG4
MDMCFG3
MDMCFG2
MDMCFG1
MDMCFG0
DEVIATN
MCSM2
MCSM1
MCSM0
FOCCFG
BSCFG
AGCCTRL2
AGCCTRL1
AGCCTRL0
WOREVT1
WOREVT0
WORCTRL
FREND1
FREND0
FSCAL3
FSCAL2
FSCAL1
FSCAL0
RCCTRL1
RCCTRL0
FSTEST
PTEST
AGCTEST
TEST2
TEST1
TEST0
SRES
SFSTXON
SXOFF
SCAL
SRX
STX
SIDLE
SRES
SFSTXON
SXOFF
SCAL
SRX
STX
SIDLE
SWOR
SPWD
SFRX
SFTX
SWORRST
SNOP
PATABLE
TX FIFO
SWOR
SPWD
SFRX
SFTX
SWORRST
SNOP
PATABLE
RX FIFO
PATABLE
TX FIFO
R/W configuration registers, burst access possible
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Read
Burst
+0x40
PARTNUM
VERSION
FREQEST
LQI
RSSI
MARCSTATE
WORTIME1
WORTIME0
PKTSTATUS
VCO_VC_DAC
TXBYTES
RXBYTES
RCCTRL1_STATUS
RCCTRL0_STATUS
PATABLE
RX FIFO
Command strobes, status registers (read only)
and multi byte registers
Write
Single byte
+0x00
Table 37: SPI Address Space
SWRS040C
Page 60 of 89
CC2500
32.1
Configuration Register Details – Registers with Preserved Values in SLEEP State
0x00: IOCFG2 – GDO2 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
Reserved
6
GDO2_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO2_CFG[5:0]
41 (0x29)
R/W
Default is CHIP_RDYn (see Table 33 on page 53).
R0
0x01: IOCFG1 – GDO1 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
GDO_DS
0
R/W
Set high (1) or low (0) output drive strength on the
GDO pins.
6
GDO1_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO1_CFG[5:0]
46 (0x2E)
R/W
Default is 3-state (see Table 33 on page 53)
0x02: IOCFG0 – GDO0 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
TEMP_SENSOR_ENABLE
0
R/W
Enable analog temperature sensor. Write 0 in all other
register bits when using temperature sensor.
6
GDO0_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO0_CFG[5:0]
63 (0x3F)
R/W
Default is CLK_XOSC/192 (see Table 33 on page 53).
SWRS040C
Page 61 of 89
CC2500
0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds
Bit
Field Name
Reset
R/W
Description
7:4
Reserved
0
R0
Write 0 for compatibility with possible future extensions
3:0
FIFO_THR[3:0]
7 (0111)
R/W
Set the threshold for the TX FIFO and RX FIFO. The threshold
is exceeded when the number of bytes in the FIFO is equal to
or higher than the threshold value.
Setting
Bytes in TX FIFO
Bytes in RX FIFO
0 (0000)
61
4
1 (0001)
57
8
2 (0010)
53
12
3 (0011)
49
16
4 (0100)
45
20
5 (0101)
41
24
6 (0110)
37
28
7 (0111)
33
32
8 (1000)
29
36
9 (1001)
25
40
10 (1010)
21
44
11 (1011)
17
48
12 (1100)
13
52
13 (1101)
9
56
14 (1110)
5
60
15 (1111)
1
64
0x04: SYNC1 – Sync Word, High Byte
Bit
Field Name
Reset
R/W
Description
7:0
SYNC[15:8]
211 (0xD3)
R/W
8 MSB of 16-bit sync word
0x05: SYNC0 – Sync Word, Low Byte
Bit
Field Name
Reset
R/W
Description
7:0
SYNC[7:0]
145 (0x91)
R/W
8 LSB of 16-bit sync word
0x06: PKTLEN – Packet Length
Bit
Field Name
Reset
R/W
Description
7:0
PACKET_LENGTH
255 (0xFF)
R/W
Indicates the packet length when fixed packet length is
enabled. If variable length packets are used, this value
indicates the maximum length packets allowed.
SWRS040C
Page 62 of 89
CC2500
0x07: PKTCTRL1 – Packet Automation Control
Bit
Field Name
Reset
R/W
Description
7:5
PQT[2:0]
0 (000)
R/W
Preamble quality estimator threshold. The preamble quality
estimator increases an internal counter by one each time a bit is
received that is different from the previous bit, and decreases the
counter by 8 each time a bit is received that is the same as the
last bit.
A threshold of 4∙PQT for this counter is used to gate sync word
detection. When PQT=0 a sync word is always accepted.
4
Reserved
0
R0
3
CRC_AUTOFLUSH
0
R/W
Enable automatic flush of RX FIFO when CRC is not OK. This
requires that only one packet is in the RX FIFO and that packet
length is limited to the RX FIFO size.
PKTCTRL0.CC2400_EN must be 0 (default) for the CRC
autoflush function to work correctly.
2
APPEND_STATUS
1
R/W
When enabled, two status bytes will be appended to the payload
of the packet. The status bytes contain RSSI and LQI values, as
well as the CRC OK flag.
1:0
ADR_CHK[1:0]
0 (00)
R/W
Controls address check configuration of received packages.
Setting
Address check configuration
0 (00)
No address check
1 (01)
Address check, no broadcast
2 (10)
Address check and 0 (0x00) broadcast
3 (11)
Address check and 0 (0x00) and 255 (0xFF)
broadcast
SWRS040C
Page 63 of 89
CC2500
0x08: PKTCTRL0 – Packet Automation Control
Bit
Field Name
7
Reserved
6
WHITE_DATA
Reset
R/W
Description
R0
1
R/W
Turn data whitening on / off
0: Whitening off
1: Whitening on
Data whitening can only be used when
PKTCTRL0.CC2400_EN=0 (default).
5:4
3
PKT_FORMAT[1:0]
CC2400_EN
0 (00)
0
R/W
Format of RX and TX data
R/W
Setting
Packet format
0 (00)
Normal mode, use FIFOs for RX and TX
1 (01)
Synchronous serial mode, used for backwards
compatibility. Data in on GDO0
2 (10)
Random TX mode; sends random data using PN9
generator. Used for test.
Works as normal mode, setting 0 (00), in RX.
3 (11)
Asynchronous serial mode. Data in on GDO0 and
data out on either of the GDO0 pins
Enable CC2400 support. Use same CRC implementation as
CC2400.
PKTCTRL1.CRC_AUTOFLUSH must be 0 if
PKTCTRL0.CC2400_EN=1.
PKTCTRL0.WHITE_DATA must be 0 if
PKTCTRL0.CC2400_EN=1.
2
CRC_EN
1
R/W
1: CRC calculation in TX and CRC check in RX enabled
0: CRC disabled for TX and RX
1:0
LENGTH_CONFIG[1:0]
1 (01)
R/W
Configure the packet length
Setting
Packet length configuration
0 (00)
Fixed packet length mode. Length configured in
PKTLEN register
1 (01)
Variable packet length mode. Packet length
configured by the first byte after sync word
2 (10)
Infinite packet length mode
3 (11)
Reserved
0x09: ADDR – Device Address
Bit
Field Name
Reset
R/W
Description
7:0
DEVICE_ADDR[7:0]
0 (0x00)
R/W
Address used for packet filtration. Optional broadcast
addresses are 0 (0x00) and 255 (0xFF).
0x0A: CHANNR – Channel Number
Bit
Field Name
Reset
R/W
Description
7:0
CHAN[7:0]
0 (0x00)
R/W
The 8-bit unsigned channel number, which is multiplied by the
channel spacing setting and added to the base frequency.
SWRS040C
Page 64 of 89
CC2500
0x0B: FSCTRL1 – Frequency Synthesizer Control
Bit
Field Name
7:5
Reserved
4:0
FREQ_IF[4:0]
Reset
R/W
Description
R0
15 (0x0F)
R/W
The desired IF frequency to employ in RX. Subtracted from FS
base frequency in RX and controls the digital complex mixer in
the demodulator.
f IF 
f XOSC
 FREQ _ IF
210
The default value gives an IF frequency of 381 kHz, assuming
a 26.0 MHz crystal.
0x0C: FSCTRL0 – Frequency Synthesizer Control
Bit
Field Name
Reset
R/W
Description
7:0
FREQOFF[7:0]
0 (0x00)
R/W
Frequency offset added to the base frequency before being
used by the FS. (2’s complement).
Resolution is FXTAL/214 (1.59 - 1.65 kHz); range is ±202 kHz to
±210 kHz, dependent of XTAL frequency.
0x0D: FREQ2 – Frequency Control Word, High Byte
Bit
Field Name
Reset
R/W
Description
7:6
FREQ[23:22]
1 (01)
R
FREQ[23:22] is always binary 01 (the FREQ2 register is in the range 85 to
95 with 26-27 MHz crystal)
5:0
FREQ[21:16]
30
(0x1E)
R/W
FREQ[23:0] is the base frequency for the frequency synthesiser in
increments of FXOSC/216.
f carrier 
f XOSC
 FREQ 23 : 0 
216
0x0E: FREQ1 – Frequency Control Word, Middle Byte
Bit
Field Name
Reset
R/W
Description
7:0
FREQ[15:8]
196 (0xC4)
R/W
Ref. FREQ2 register
0x0F: FREQ0 – Frequency Control Word, Low Byte
Bit
Field Name
Reset
R/W
Description
7:0
FREQ[7:0]
236 (0xEC)
R/W
Ref. FREQ2 register
SWRS040C
Page 65 of 89
CC2500
0x10: MDMCFG4 – Modem Configuration
Bit
Field Name
Reset
R/W
7:6
CHANBW_E[1:0]
2 (10)
R/W
5:4
CHANBW_M[1:0]
0 (00)
R/W
Description
Sets the decimation ratio for the delta-sigma ADC input stream
and thus the channel bandwidth.
BWchannel 
f XOSC
8  (4  CHANBW _ M )·2CHANBW _ E
The default values give 203 kHz channel filter bandwidth,
assuming a 26.0 MHz crystal.
3:0
DRATE_E[3:0]
12 (1100)
R/W
The exponent of the user specified symbol rate
0x11: MDMCFG3 – Modem Configuration
Bit
Field Name
Reset
R/W
Description
7:0
DRATE_M[7:0]
34 (0x22)
R/W
The mantissa of the user specified symbol rate. The symbol
rate is configured using an unsigned, floating-point number
with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden
‘1’. The resulting data rate is:
RDATA 
256  DRATE _ M   2 DRATE _ E  f
2 28
XOSC
The default values give a data rate of 115.051 kBaud (closest
setting to 115.2 kBaud), assuming a 26.0 MHz crystal.
SWRS040C
Page 66 of 89
CC2500
0x12: MDMCFG2 – Modem Configuration
Bit
Field Name
Reset
R/W
Description
7
DEM_DCFILT_OFF
0
R/W
Disable digital DC blocking filter before demodulator.
0 = Enable (better sensitivity)
1 = Disable (current optimized). Only for data rates
≤ 250 kBaud
The recommended IF frequency changes when the DC
blocking is disabled. Please use SmartRF Studio [5] to
calculate correct register setting.
6:4
3
MOD_FORMAT[2:0]
MANCHESTER_EN
0 (000)
0
R/W
R/W
The modulation format of the radio signal
Setting
Modulation format
0 (000)
2-FSK
1 (001)
GFSK
2 (010)
-
3 (011)
OOK
4 (100)
-
5 (101)
-
6 (110)
-
7 (111)
MSK
Enables Manchester encoding/decoding.
0 = Disable
1 = Enable
2:0
SYNC_MODE[2:0]
2 (010)
R/W
Combined sync-word qualifier mode.
The values 0 (000) and 4 (100) disables preamble and
sync word transmission in TX and preamble and sync
word detection in RX.
The values 1 (001), 2 (010), 5 (101) and 6 (110)
enables 16-bit sync word transmission in TX and 16bits sync word detection in RX. Only 15 of 16 bits need
to match in RX when using setting 1 (001) or 5 (101).
The values 3 (011) and 7 (111) enables repeated sync
word transmission in TX and 32-bits sync word
detection in RX (only 30 of 32 bits need to match).
SWRS040C
Setting
Sync-word qualifier mode
0 (000)
No preamble/sync
1 (001)
15/16 sync word bits detected
2 (010)
16/16 sync word bits detected
3 (011)
30/32 sync word bits detected
4 (100)
No preamble/sync, carrier-sense
above threshold
5 (101)
15/16 + carrier-sense above threshold
6 (110)
16/16 + carrier-sense above threshold
7 (111)
30/32 + carrier-sense above threshold
Page 67 of 89
CC2500
0x13: MDMCFG1 – Modem Configuration
Bit
Field Name
Reset
R/W
Description
7
FEC_EN
0
R/W
Enable Forward Error Correction (FEC) with interleaving for
packet payload
0 = Disable
1 = Enable (Only supported for fixed packet length mode, i.e.
PKTCTRL0.LENGTH_CONFIG=0)
6:4
NUM_PREAMBLE[2:0]
3:2
Reserved
1:0
CHANSPC_E[1:0]
2 (010)
R/W
Sets the minimum number of preamble bytes to be transmitted
Setting
Number of preamble bytes
0 (000)
2
1 (001)
3
2 (010)
4
3 (011)
6
4 (100)
8
5 (101)
12
6 (110)
16
7 (111)
24
R0
2 (10)
R/W
2 bit exponent of channel spacing
0x14: MDMCFG0 – Modem Configuration
Bit
Field Name
Reset
R/W
Description
7:0
CHANSPC_M[7:0]
248 (0xF8)
R/W
8-bit mantissa of channel spacing. The channel spacing is
multiplied by the channel number CHAN and added to the base
frequency. It is unsigned and has the format:
f CHANNEL 
f XOSC
 256  CHANSPC _ M   2 CHANSPC _ E
218
The default values give 199.951 kHz channel spacing (the closest
setting to 200 kHz), assuming 26.0 MHz crystal frequency.
SWRS040C
Page 68 of 89
CC2500
0x15: DEVIATN – Modem Deviation Setting
Bit
Field Name
7
Reserved
6:4
DEVIATION_E[2:0]
3
Reserved
2:0
DEVIATION_M[2:0]
Reset
R/W
Description
R0
4 (100)
R/W
Deviation exponent
R0
7 (111)
R/W
When MSK modulation is enabled:
Sets fraction of symbol period used for phase change. Refer to
the SmartRF Studio software [5] for correct DEVIATN setting
when using MSK.
When 2-FSK/GFSK modulation is enabled:
Deviation mantissa, interpreted as a 4-bit value with MSB implicit
1. The resulting deviation is given by:
f dev 
f xosc
 (8  DEVIATION _ M )  2 DEVIATION _ E
217
The default values give ±47.607 kHz deviation, assuming 26.0
MHz crystal frequency.
SWRS040C
Page 69 of 89
CC2500
0x16: MCSM2 – Main Radio Control State Machine Configuration
Bit
Field Name
7:5
Reserved
4
RX_TIME_RSSI
3
2:0
Reset
R/W
Description
R0
Reserved
0
R/W
Direct RX termination based on RSSI measurement (carrier
sense).
RX_TIME_QUAL
0
R/W
When the RX_TIME timer expires the chip stays in RX mode if
sync word is found when RX_TIME_QUAL=0, or either sync
word is found or PQT is set when RX_TIME_QUAL=1.
RX_TIME[2:0]
7 (111)
R/W
Timeout for sync word search in RX for both WOR mode and
normal RX operation. The timeout is relative to the
programmed EVENT0 timeout.
The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and
X is the crystal oscillator frequency in MHz:
RX_TIME[2:0]
WOR_RES = 0
WOR_RES = 1
WOR_RES = 2
WOR_RES = 3
0 (000)
3.6058
18.0288
32.4519
46.8750
1 (001)
1.8029
9.0144
16.2260
23.4375
2 (010)
0.9014
4.5072
8.1130
11.7188
3 (011)
0.4507
2.2536
4.0565
5.8594
4 (100)
0.2254
1.1268
2.0282
2.9297
5 (101)
0.1127
0.5634
1.0141
1.4648
6 (110)
0.0563
0.2817
0.5071
0.7324
7 (111)
Until end of packet
As an example, EVENT0=34666, WOR_RES=0 and RX_TIME=6 corresponds to 1.95 ms RX timeout, 1 s polling
interval and 0.195% duty cycle. Note that WOR_RES should be 0 or 1 when using WOR because using
WOR_RES > 1 will give a very low duty cycle. In applications where WOR is not used all settings of WOR_RES
can be used.
The duty cycle using WOR is approximated by:
RX_TIME[2:0]
WOR_RES = 0
WOR_RES = 1
0 (000)
12.50%
1.95%
1 (001)
6.250%
9765 ppm
2 (010)
3.125%
4883 ppm
3 (011)
1.563%
2441 ppm
4 (100)
0.781%
NA
5 (101)
0.391%
NA
6 (110)
0.195%
NA
7 (111)
NA
Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator
periods. WOR mode does not need to be enabled.
The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0,
decreasing to the 7 MSBs of EVENT0 with RX_TIME=6.
SWRS040C
Page 70 of 89
CC2500
0x17: MCSM1 – Main Radio Control State Machine Configuration
Bit
Field Name
7:6
Reserved
5:4
CCA_MODE[1:0]
3:2
RXOFF_MODE[1:0]
Reset
R/W
Description
R0
3 (11)
0 (00)
R/W
R/W
Selects CCA_MODE; Reflected in CCA signal
Setting
Clear channel indication
0 (00)
Always
1 (01)
If RSSI below threshold
2 (10)
Unless currently receiving a packet
3 (11)
If RSSI below threshold unless currently
receiving a packet
Select what should happen when a packet has been received
Setting
Next state after finishing packet reception
0 (00)
IDLE
1 (01)
FSTXON
2 (10)
TX
3 (11)
Stay in RX
It is not possible to set RXOFF_MODE to be TX or FSTXON
and at the same time use CCA.
1:0
TXOFF_MODE[1:0]
0 (00)
R/W
Select what should happen when a packet has been sent (TX)
Setting
Next state after finishing packet transmission
0 (00)
IDLE
1 (01)
FSTXON
2 (10)
Stay in TX (start sending preamble)
3 (11)
RX
SWRS040C
Page 71 of 89
CC2500
0x18: MCSM0 – Main Radio Control State Machine Configuration
Bit
Field Name
7:6
Reserved
5:4
FS_AUTOCAL[1:0]
Reset
R/W
Description
R0
0 (00)
R/W
Automatically calibrate when going to RX or TX, or back to IDLE
Setting
When to perform automatic calibration
0 (00)
Never (manually calibrate using SCAL strobe)
1 (01)
When going from IDLE to RX or TX (or FSTXON)
2 (10)
When going from RX or TX back to IDLE
automatically
3 (11)
Every 4th time when going from RX or TX to IDLE
automatically
In some automatic wake-on-radio (WOR) applications, using
setting 3 (11) can significantly reduce current consumption.
3:2
PO_TIMEOUT
1 (01)
R/W
Programs the number of times the six-bit ripple counter must
expire after XOSC has stabilized before CHP_RDYn goes low.
If XOSC is on (stable) during power-down, PO_TIMEOUT
should be set so that the regulated digital supply voltage has
time to stabilize before CHP_RDYn goes low (PO_TIMEOUT=2
recommended). Typical start-up time for the voltage regulator is
50 us.
If XOSC is off during power-down and the regulated digital
supply voltage has sufficient time to stabilize while waiting for
the crystal to be stable, PO_TIMEOUT can be set to 0. For
robust operation it is recommended to use PO_TIMEOUT=2.
Setting
Expire count
Timeout after XOSC start
0 (00)
1
Approx. 2.3 – 2.4 μs
1 (01)
16
Approx. 37 – 39 μs
2 (10)
64
Approx. 149 – 155 μs
3 (11)
256
Approx. 597 – 620 μs
Exact timeout depends on crystal frequency.
1
PIN_CTRL_EN
0
R/W
Enables the pin radio control option
0
XOSC_FORCE_ON
0
R/W
Force the XOSC to stay on in the SLEEP state.
SWRS040C
Page 72 of 89
CC2500
0x19: FOCCFG – Frequency Offset Compensation Configuration
Bit
Field Name
7:6
Reserved
5
FOC_BS_CS_GATE
1
R/W
If set, the demodulator freezes the frequency offset
compensation and clock recovery feedback loops until the
CARRIER_SENSE signal goes high.
4:3
FOC_PRE_K[1:0]
2 (10)
R/W
The frequency compensation loop gain to be used before a sync
word is detected.
2
1:0
FOC_POST_K
FOC_LIMIT[1:0]
Reset
R/W
Description
R0
1
2 (10)
R/W
R/W
Setting
Freq. compensation loop gain before sync word
0 (00)
K
1 (01)
2K
2 (10)
3K
3 (11)
4K
The frequency compensation loop gain to be used after a sync
word is detected.
Setting
Freq. compensation loop gain after sync word
0
Same as FOC_PRE_K
1
K/2
The saturation point for the frequency offset compensation
algorithm:
Setting
Saturation point (max compensated offset)
0 (00)
±0 (no frequency offset compensation)
1 (01)
±BWCHAN/8
2 (10)
±BWCHAN/4
3 (11)
±BWCHAN/2
Frequency offset compensation is not supported for OOK;
Always use FOC_LIMIT=0 with this modulation format.
SWRS040C
Page 73 of 89
CC2500
0x1A: BSCFG – Bit Synchronization Configuration
Bit
Field Name
Reset
R/W
Description
7:6
BS_PRE_KI[1:0]
1 (01)
R/W
The clock recovery feedback loop integral gain to be used before a
sync word is detected (used to correct offsets in data rate):
5:4
3
2
1:0
BS_PRE_KP[1:0]
BS_POST_KI
BS_POST_KP
BS_LIMIT[1:0]
2 (10)
1
1
0 (00)
R/W
R/W
R/W
R/W
Setting
Clock recovery loop integral gain before sync word
0 (00)
KI
1 (01)
2KI
2 (10)
3KI
3 (11)
4KI
The clock recovery feedback loop proportional gain to be used
before a sync word is detected.
Setting
Clock recovery loop proportional gain before sync word
0 (00)
KP
1 (01)
2KP
2 (10)
3KP
3 (11)
4KP
The clock recovery feedback loop integral gain to be used after a
sync word is detected.
Setting
Clock recovery loop integral gain after sync word
0
Same as BS_PRE_KI
1
KI /2
The clock recovery feedback loop proportional gain to be used after
a sync word is detected.
Setting
Clock recovery loop proportional gain after sync word
0
Same as BS_PRE_KP
1
KP
The saturation point for the data rate offset compensation algorithm:
Setting
Data rate offset saturation (max data rate difference)
0 (00)
±0 (No data rate offset compensation performed)
1 (01)
±3.125% data rate offset
2 (10)
±6.25% data rate offset
3 (11)
±12.5% data rate offset
SWRS040C
Page 74 of 89
CC2500
0x1B: AGCCTRL2 – AGC Control
Bit
Field Name
Reset
R/W
Description
7:6
MAX_DVGA_GAIN[1:0]
0 (00)
R/W
Reduces the maximum allowable DVGA gain.
5:3
2:0
MAX_LNA_GAIN[2:0]
MAGN_TARGET[2:0]
0 (000)
3 (011)
R/W
R/W
Setting
Allowable DVGA settings
0 (00)
All gain settings can be used
1 (01)
The highest gain setting can not be used
2 (10)
The 2 highest gain settings can not be used
3 (11)
The 3 highest gain settings can not be used
Sets the maximum allowable LNA + LNA 2 gain relative to the
maximum possible gain.
Setting
Maximum allowable LNA + LNA 2 gain
0 (000)
Maximum possible LNA + LNA 2 gain
1 (001)
Approx. 2.6 dB below maximum possible gain
2 (010)
Approx. 6.1 dB below maximum possible gain
3 (011)
Approx. 7.4 dB below maximum possible gain
4 (100)
Approx. 9.2 dB below maximum possible gain
5 (101)
Approx. 11.5 dB below maximum possible gain
6 (110)
Approx. 14.6 dB below maximum possible gain
7 (111)
Approx. 17.1 dB below maximum possible gain
These bits set the target value for the averaged amplitude from
the digital channel filter (1 LSB = 0 dB).
Setting
Target amplitude from channel filter
0 (000)
24 dB
1 (001)
27 dB
2 (010)
30 dB
3 (011)
33 dB
4 (100)
36 dB
5 (101)
38 dB
6 (110)
40 dB
7 (111)
42 dB
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CC2500
0x1C: AGCCTRL1 – AGC Control
Bit
Field Name
7
Reserved
6
AGC_LNA_PRIORITY
1
R/W
Selects between two different strategies for LNA and LNA2
gain adjustment. When 1, the LNA gain is decreased first.
When 0, the LNA2 gain is decreased to minimum before
decreasing LNA gain.
5:4
CARRIER_SENSE_REL_THR[1:0]
0 (00)
R/W
Sets the relative change threshold for asserting carrier
sense.
3:0
CARRIER_SENSE_ABS_THR[3:0]
Reset
R/W
Description
R0
0
(0000)
R/W
Setting
Carrier sense relative threshold
0 (00)
Relative carrier sense threshold disabled
1 (01)
6 dB increase in RSSI value
2 (10)
10 dB increase in RSSI value
3 (11)
14 dB increase in RSSI value
Sets the absolute RSSI threshold for asserting carrier
sense. The 2’s complement signed threshold is programmed
in steps of 1 dB and is relative to the MAGN_TARGET
setting.
Setting
Carrier sense absolute threshold
(Equal to channel filter amplitude when AGC
has not decreased gain)
-8 (1000)
Absolute carrier sense threshold disabled
-7 (1001)
7 dB below MAGN_TARGET setting
…
…
-1 (1111)
1 dB below MAGN_TARGET setting
0 (0000)
At MAGN_TARGET setting
1 (0001)
1 dB above MAGN_TARGET setting
…
…
7 (0111)
7 dB above MAGN_TARGET setting
SWRS040C
Page 76 of 89
CC2500
0x1D: AGCCTRL0 – AGC Control
Bit
Field Name
Reset
R/W
Description
7:6
HYST_LEVEL[1:0]
2 (10)
R/W
Sets the level of hysteresis on the magnitude deviation
(internal AGC signal that determines gain changes).
5:4
3:2
1:0
WAIT_TIME[1:0]
AGC_FREEZE[1:0]
FILTER_LENGTH[1:0]
1 (01)
0 (00)
1 (01)
R/W
R/W
R/W
Setting
Description
0 (00)
No hysteresis, small symmetric dead zone,
high gain
1 (01)
Low hysteresis, small asymmetric dead zone,
medium gain
2 (10)
Medium hysteresis, medium asymmetric dead
zone, medium gain
3 (11)
Large hysteresis, large asymmetric dead
zone, low gain
Sets the number of channel filter samples from a gain
adjustment has been made until the AGC algorithm starts
accumulating new samples.
Setting
Channel filter samples
0 (00)
8
1 (01)
16
2 (10)
24
3 (11)
32
Controls when the AGC gain should be frozen.
Setting
Function
0 (00)
Normal operation. Always adjust gain when
required.
1 (01)
The gain setting is frozen when a sync word has
been found.
2 (10)
Manually freezes the analog gain setting and
continue to adjust the digital gain.
3 (11)
Manually freezes both the analog and the digital
gain settings. Used for manually overriding the
gain.
Sets the averaging length for the amplitude from the channel
filter. Sets the OOK decision boundary for OOK reception.
Setting
Channel filter samples
OOK decision
0 (00)
8
4 dB
1 (01)
16
8 dB
2 (10)
32
12 dB
3 (11)
64
16 dB
0x1E: WOREVT1 – High Byte Event0 Timeout
Bit
Field Name
Reset
R/W
Description
7:0
EVENT0[15:8]
135 (0x87)
R/W
High byte of Event 0 timeout register
t Event 0 
SWRS040C
750
 EVENT 0  2 5WOR _ RES
f XOSC
Page 77 of 89
CC2500
0x1F: WOREVT0 – Low Byte Event0 Timeout
Bit
Field Name
Reset
R/W
Description
7:0
EVENT0[7:0]
107 (0x6B)
R/W
Low byte of Event 0 timeout register.
The default Event 0 value gives 1.0 s timeout, assuming a
26.0 MHz crystal.
0x20: WORCTRL – Wake On Radio Control
Bit
Field Name
Reset
R/W
Description
7
RC_PD
1
R/W
Power down signal to RC oscillator. When written to 0, automatic
initial calibration will be performed
6:4
EVENT1[2:0]
7 (111)
R/W
Timeout setting from register block. Decoded to Event 1 timeout.
RC oscillator clock frequency equals FXOSC/750, which is 34.7-36
kHz, depending on crystal frequency. The table below lists the
number of clock periods after Event 0 before Event 1 times out.
3
RC_CAL
2
Reserved
1:0
WOR_RES[1:0]
1
R/W
Setting
t_event1
0 (000)
4 (0.111 – 0.115 ms)
1 (001)
6 (0.167 – 0.173 ms)
2 (010)
8 (0.222 – 0.230 ms)
3 (011)
12 (0.333 – 0.346 ms)
4 (100)
16 (0.444 – 0.462 ms)
5 (101)
24 (0.667 – 0.692 ms)
6 (110)
32 (0.889 – 0.923 ms)
7 (111)
48 (1.333 – 1.385 ms)
Enables (1) or disables (0) the RC oscillator calibration.
R0
0 (00)
R/W
Controls the Event 0 resolution as well as maximum timeout of the
WOR module and maximum timeout under normal RX operation:
Setting
Resolution (1 LSB)
Max timeout
0 (00)
1 period (28 – 29 μs)
1.8 – 1.9 seconds
1 (01)
2 (10)
3 (11)
5
58 – 61 seconds
10
31 – 32 minutes
15
16.5 – 17.2 hours
2 periods (0.89 – 0.92 ms)
2 periods (28 – 30 ms)
2 periods (0.91 – 0.94 s)
Note that WOR_RES should be 0 or 1 when using WOR because
WOR_RES > 1 will give a very low duty cycle.
In normal RX operation all settings of WOR_RES can be used.
0x21: FREND1 – Front End RX Configuration
Bit
Field Name
Reset
R/W
Description
7:6
LNA_CURRENT[1:0]
1 (01)
R/W
Adjusts front-end LNA PTAT current output
5:4
LNA2MIX_CURRENT[1:0]
1 (01)
R/W
Adjusts front-end PTAT outputs
3:2
LODIV_BUF_CURRENT_RX[1:0]
1 (01)
R/W
Adjusts current in RX LO buffer (LO input to mixer)
1:0
MIX_CURRENT[1:0]
2 (10)
R/W
Adjusts current in mixer
SWRS040C
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CC2500
0x22: FREND0 – Front End TX configuration
Bit
Field Name
Reset
7:6
Reserved
5:4
LODIV_BUF_CURRENT_TX[1:0]
3
Reserved
2:0
PA_POWER[2:0]
R/W
Description
R0
1 (01)
R/W
Adjusts current TX LO buffer (input to PA). The value to use in
this field is given by the SmartRF Studio software [5].
R0
0 (000)
R/W
Selects PA power setting. This value is an index to the
PATABLE. In OOK mode, this selects the PATABLE index to
use when transmitting a ‘1’. PATABLE index zero is used in
OOK when transmitting a ‘0’.
0x23: FSCAL3 – Frequency Synthesizer Calibration
Bit
Field Name
Reset
R/W
Description
7:6
FSCAL3[7:6]
2 (10)
R/W
Frequency synthesizer calibration configuration. The value to write in
this register before calibration is given by the SmartRF Studio
software [5].
5:4
CHP_CURR_CAL_EN[1:0]
2 (10)
R/W
Disable charge pump calibration stage when 0
3:0
FSCAL3[3:0]
9
(1001)
R/W
Frequency synthesizer calibration result register. Digital bit vector
defining the charge pump output current, on an exponential scale:
IOUT=I0·2FSCAL3[3:0]/4
Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.
0x24: FSCAL2 – Frequency Synthesizer Calibration
Bit
Field Name
Reset
R/W
Description
7:6
Reserved
5
VCO_CORE_H_EN
0
R/W
Choose high (1) / low (0) VCO
4:0
FSCAL2[4:0]
10
(0x0A)
R/W
Frequency synthesizer calibration result register. VCO current
calibration result and override value
Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.
R0
SWRS040C
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CC2500
0x25: FSCAL1 – Frequency Synthesizer Calibration
Bit
Field Name
7:6
Reserved
5:0
FSCAL1[5:0]
Reset
R/W
Description
R0
32
(0x20)
R/W
Frequency synthesizer calibration result register. Capacitor array
setting for VCO coarse tuning.
Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.
0x26: FSCAL0 – Frequency Synthesizer Calibration
Bit
Field Name
7
Reserved
6:0
FSCAL0[6:0]
Reset
R/W
Description
R0
13 (0x0D)
R/W
Frequency synthesizer calibration control. The value to use in
this register is given by the SmartRF Studio software [5].
0x27: RCCTRL1 – RC Oscillator Configuration
Bit
Field Name
Reset
R/W
7
Reserved
0
R0
6:0
RCCTRL1[6:0]
65
(0x41)
R/W
Description
RC oscillator configuration.
0x28: RCCTRL0 – RC Oscillator Configuration
Bit
Field Name
Reset
R/W
7
Reserved
0
R0
6:0
RCCTRL0[6:0]
0
(0x00)
R/W
32.2
Description
RC oscillator configuration.
Configuration Register Details – Registers that Lose Programming in SLEEP State
0x29: FSTEST – Frequency Synthesizer Calibration Control
Bit
Field Name
Reset
R/W
Description
7:0
FSTEST[7:0]
89
(0x59)
R/W
For test only. Do not write to this register.
0x2A: PTEST – Production Test
Bit
Field Name
Reset
R/W
Description
7:0
PTEST[7:0]
127
(0x7F)
R/W
Writing 0xBF to this register makes the on-chip temperature sensor
available in the IDLE state. The default 0x7F value should then be
written back before leaving the IDLE state.
Other use of this register is for test only.
SWRS040C
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CC2500
0x2B: AGCTEST – AGC Test
Bit
Field Name
Reset
R/W
Description
7:0
AGCTEST[7:0]
63
(0x3F)
R/W
For test only. Do not write to this register.
0x2C: TEST2 – Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:0
TEST2[7:0]
136 (0x88)
R/W
Set to 0x81 for improved sensitivity at data rates ≤100 kBaud. The
temperature range is then from 0oC to +85oC.
0x2D: TEST1 – Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:0
TEST1[7:0]
49 (0x31)
R/W
Set to 0x35 for improved sensitivity at data rates ≤100 kBaud. The
temperature range is then from 0oC to +85oC.
0x2E: TEST0 – Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:2
TEST0[7:2]
2 (0x02)
R/W
The value to use in this register is given by the SmartRF Studio
software [5].
1
VCO_SEL_CAL_EN
1
R/W
Enable VCO selection calibration stage when 1
0
TEST0[0]
1
R/W
The value to use in this register is given by the SmartRF Studio
software [5].
32.3
Status Register Details
0x30 (0xF0): PARTNUM – Chip ID
Bit
Field Name
Reset
R/W
Description
7:0
PARTNUM[7:0]
128 (0x80)
R
Chip part number
0x31 (0xF1): VERSION – Chip ID
Bit
Field Name
Reset
R/W
Description
7:0
VERSION[7:0]
3 (0x03)
R
Chip version number.
0x32 (0xF2): FREQEST – Frequency Offset Estimate from Demodulator
Bit
Field Name
7:0
FREQOFF_EST
Reset
R/W
Description
R
The estimated frequency offset (2’s complement) of the carrier.
Resolution is FXTAL/214 (1.59 - 1.65 kHz); range is ±202 kHz to
±210 kHz, dependent of XTAL frequency.
Frequency offset compensation is only supported for 2-FSK;
GFSK and MSK modulation. This register will read 0 when
using OOK modulation.
SWRS040C
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CC2500
0x33 (0xF3): LQI – Demodulator Estimate for Link Quality
Bit
Field Name
7
6:0
Reset
R/W
Description
CRC_OK
R
The last CRC comparison matched. Cleared when
entering/restarting RX mode. Only valid if
PKTCTRL0.CC2400_EN=1.
LQI_EST[6:0]
R
The Link Quality Indicator estimates how easily a received signal
can be demodulated. Calculated over the 64 symbols following
the sync word.
0x34 (0xF4): RSSI – Received Signal Strength Indication
Bit
Field Name
7:0
RSSI
Reset
R/W
Description
R
Received signal strength indicator
0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State
Bit
Field Name
Reset
R/W
7:5
Reserved
R0
4:0
MARC_STATE[4:0]
R
Description
Main Radio Control FSM State
Value
State name
State (Figure 15, page 39)
0 (0x00)
SLEEP
SLEEP
1 (0x01)
IDLE
IDLE
2 (0x02)
XOFF
XOFF
3 (0x03)
VCOON_MC
MANCAL
4 (0x04)
REGON_MC
MANCAL
5 (0x05)
MANCAL
MANCAL
6 (0x06)
VCOON
FS_WAKEUP
7 (0x07)
REGON
FS_WAKEUP
8 (0x08)
STARTCAL
CALIBRATE
9 (0x09)
BWBOOST
SETTLING
10 (0x0A)
FS_LOCK
SETTLING
11 (0x0B)
IFADCON
SETTLING
12 (0x0C)
ENDCAL
CALIBRATE
13 (0x0D)
RX
RX
14 (0x0E)
RX_END
RX
15 (0x0F)
RX_RST
RX
16 (0x10)
TXRX_SWITCH
TXRX_SETTLING
17 (0x11)
RXFIFO_OVERFLOW
RXFIFO_OVERFLOW
18 (0x12)
FSTXON
FSTXON
19 (0x13)
TX
TX
20 (0x14)
TX_END
TX
21 (0x15)
RXTX_SWITCH
RXTX_SETTLING
22 (0x16)
TXFIFO_UNDERFLOW
TXFIFO_UNDERFLOW
Note: it is not possible to read back the SLEEP or XOFF state numbers
because setting CSn low will make the chip enter the IDLE mode from
the SLEEP or XOFF states.
SWRS040C
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CC2500
0x36 (0xF6): WORTIME1 – High Byte of WOR Time
Bit
Field Name
7:0
TIME[15:8]
Reset
R/W
Description
R
High byte of timer value in WOR module
0x37 (0xF7): WORTIME0 – Low Byte of WOR Time
Bit
Field Name
7:0
TIME[7:0]
Reset
R/W
Description
R
Low byte of timer value in WOR module
0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status
Bit
Field Name
7
Reset
R/W
Description
CRC_OK
R
The last CRC comparison matched. Cleared when
entering/restarting RX mode. Only valid if
PKTCTRL0.CC2400_EN=1.
6
CS
R
Carrier sense
5
PQT_REACHED
R
Preamble Quality reached
4
CCA
R
Channel is clear
3
SFD
R
Sync word found
2
GDO2
R
Current GDO2 value. Note: the reading gives the non-inverted
value irrespective what IOCFG2.GDO2_INV is programmed to.
It is not recommended to check for PLL lock by reading
PKTSTATUS[2] with GDO2_CFG=0x0A.
1
Reserved
R0
0
GDO0
R
Current GDO0 value. Note: the reading gives the non-inverted
value irrespective what IOCFG0.GDO0_INV is programmed to.
It is not recommended to check for PLL lock by reading
PKTSTATUS[0] with GDO0_CFG=0x0A.
0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module
Bit
Field Name
Reset
7:0
VCO_VC_DAC[7:0]
R/W
Description
R
Status register for test only
0x3A (0xFA): TXBYTES – Underflow and Number of Bytes
Bit
Field Name
Reset
R/W
7
TXFIFO_UNDERFLOW
R
6:0
NUM_TXBYTES
R
Description
Number of bytes in TX FIFO
SWRS040C
Page 83 of 89
CC2500
0x3B (0xFB): RXBYTES – Underflow and Number of Bytes
Bit
Field Name
Reset
R/W
7
RXFIFO_OVERFLOW
R
6:0
NUM_RXBYTES
R
Description
Number of bytes in RX FIFO
0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result
Bit
Field Name
Reset
R/W
7
Reserved
R0
6:0
RCCTRL1_STATUS[6:0]
R
Description
Contains the value from the last run of the RC oscillator
calibration routine.
For usage description refer to AN047 [3].
0x3D (0xFC): RCCTRL0_STATUS – Last RC Oscillator Calibration Result
Bit
Field Name
Reset
R/W
7
Reserved
R0
6:0
RCCTRL0_STATUS[6:0]
R
Description
Contains the value from the last run of the RC oscillator
calibration routine.
For usage description refer to AN047 [3].
SWRS040C
Page 84 of 89
CC2500
33 Package Description (QFN 20)
33.1
Recommended PCB Layout for Package (QFN 20)
Figure 30: Recommended PCB Layout for QFN 20 Package
Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes
distributed symmetrically in the ground pad under the package. See also the CC2500EM
reference design [4].
33.2
Soldering Information
The recommendations for lead-free reflow in IPC/JEDE J-STD-020D should be followed.
SWRS040C
Page 85 of 89
CC2500
34 Ordering Information
Orderable
Device
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan (2)
Lead
Finish
MSL
Peak
Temp (3)
CC2500RTKR
Active
QFN
RTK
20
3000
Green (RoHS &
no Sb/Br)
Cu NiPdAu
LEVEL3-260C
Green (RoHS &
no Sb/Br)
Cu NiPdAu
CC2500RTK
Active
QFN
RTK
20
92
1 YEAR
LEVEL3-260C
1 YEAR
Orderable Evaluation Module
Description
Minimum Order Quantity
CC2500-CC2550DK
CC2500_CC2550 Development Kit
1
CC2500EMK
CC1101 Development Kit
1
Figure 31: Ordering Information
35 References
[1] CC2500 Errata Notes (swrz002.pdf)
[2] AN032 2.4 GHz Regulations (swra060.pdf)
[3] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf)
[4] CC2500EM Reference Design 1.0 (swrr016.zip)
SWRS040C
Page 86 of 89
CC2500
®
[5] SmartRF Studio (swrc046.zip)
[6] CC1100 CC2500 Examples Libraries (swrc021.zip)
[7] CC1100/CC1150DK & CC2500/CC2550DK Development Kit Examples & Libraries User
Manual (swru109.pdf)
[8] CC25XX Folded Dipole Reference Design (swrc065.zip)
[9] DN004 Folded Dipole Antenna for CCC25xx (swra118.pdf)
SWRS040C
Page 87 of 89
CC2500
36 General Information
36.1
Document History
Revision
Date
Description/Changes
SWRS040C
2008-05-04
Updated package and ordering information.
SWRS040B
2007-05-09
kbps replaced by kBaud throughout the document.
Some of the sections have been re-written to be easier to read without having any new info added.
Absolute maximum supply voltage rating increased from 3.6 V to 3.9 V.
FSK changed to 2-FSK throughout the document.
Updates to the Abbreviation table.
Updates to the Electrical Specifications section. Added ACP, OBW and blocking performance.
Maximum output power changed from 0 dBm to +1 dBm.
Added information about reduced link performance at n/2∙crystal frequency.
Added info about RX and TX latency in serial mode.
Changes to the maximum RC oscillator frequency accuracy after calibration.
Added info about default values after reset versus optimum register settings in the Configuration
Software section.
Changes to the SPI Interface Timing Requirements. Info added about tsp,pd
The following figures have been changed: Configuration Registers Write and Read Operations,
SRES Command Strobe, and Register Access Types.
In the Register Access section, the address range is changed.
Changes to PATABLE Access section.
In the Packet Format section, preamble pattern is changed to 10101010 and info about bug related
to turning off the transmitter in infinite packet length mode is added.
Added info to the Frequency Offset Compensation section.
Added info about the initial value of the PN9 sequence in the Data Whitening section.
Added info about TX FIFO underflow state in the Packet Handling in Transmit Mode section.
Added section Packet Handling in Firmware.
In the PQT section a change is made as to how much the counter decreases.
The RSSI value is in dBm and not dB.
The whole CS Absolute Threshold section has been re-written and the equation calculating the
threshold has been removed.
Added info in the CCA section on what happens if the channel is not clear.
Added info to the LQI section for better understanding.
Removed all references to the voltage regulator in relation with the CHP_RDYn signal, as this
signal is only related to the crystal.
Removed references to the voltage regulator in the figures: Power-On Reset and Power-On Reset
with SRES. Changes to the SI line in the Power-On Reset with SRES figure.
Added info on the three automatic calibration options.
Added info about minimum sleep time and references to App. Note 047 together with info about
calibration of the RC oscillator.
The figure Event 0 and Event 1 Relationship is changed for better readability.
Info added to the RC Oscillator and Timing section related to reduced calibration time.
The Output Power Programming section has been changed. Only 1 PATABLE entry used for 2FSK/GFSK/MSK and 2 PATABLE entries used for OOK. Added info about PATABLE when
entering SLEEP mode. New PA_POWER and PATABLE figure.
Added section on PCB Layout Recommendations.
In section General Purpose / Test Output Control Pins: Added info on GDO pins in SLEEP state.
Asynchronous transparent mode is called asynchronous serial mode throughout the document.
Removed comments about having to use NRZ coding in synchronous serial mode.
Added info that Manchester encoding cannot be used in asynchronous serial mode.
Changed number of commands strobes from 14 to 13.
Added two new registers; RCCTRL1_STATUS and RCCTRL0_STATUS
Changed field name and/or description of the following registers:
MCSM2, MCSM0, WORCTRL, FSCAL3, FSCAL2, FSCAL1, TEST2, TEST1 and TEST0.
Added references.
SWRS040C
Page 88 of 89
CC2500
Revision
Date
Description/Changes
2006-06-28
Added figures to table on SPI interface timing requirements.
Added information about SPI read.
Updates to text and included new figure in section on arbitrary length configuration.
Updates to section on CRC check. Added information about CRC check when
PKTCTRL0.CC2400_EN=1.
Added information on RSSI update rate in section RSSI.
Updates to text and included new figures in section on power-on start-up sequence.
Changes to wake-on-radio current consumption figures under electrical specifications.
Updates to text in section on data FIFO.
Added information about how to check for PLL lock in section on VCO.
Better explanation of some of the signals in table of GDO signal selection. Also added some more
signals.
Added section on wideband modulation not using spread spectrum under section on system
considerations and guidelines.
Changes to timeout for sync word search in RX in register MCSM2.
Changes to wake-on-radio control register WORCTRL. WOR_RES[1:0] settings 10 b and 11b
changed to Not Applicable (NA).
Added more detailed information on PO_TIMEOUT in register MCSM0.
Added description of programming bits in registers FOCCFG, BSCFG, AGCCTRL0, FREND1.
Changes to ordering information.
1.1
2005-10-20
MDMCFG2[7] used. 26-27 MHz crystal range. Chapter 15: description of the 2 optional append
bytes. Added matching information. Added information about using a reference signal instead of a
crystal. CRC can only be checked by append bytes or CRC_AUTOFLUSH. Added equation for
calculating RSSI in dBm. Selectivity performance graphs added.
1.0
2005-01-24
First preliminary release.
1.2
SWRS040A
Table 38: Document History
SWRS040C
Page 89 of 89
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC2500RGP
ACTIVE
QFN
RGP
20
92
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC2500
CC2500RGPR
ACTIVE
QFN
RGP
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC2500
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CC2500RGPR
Package Package Pins
Type Drawing
QFN
RGP
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
4.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2500RGPR
QFN
RGP
20
3000
350.0
350.0
43.0
Pack Materials-Page 2
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