Texas Instruments | Using the SPI Interface with TRF7960 (Rev. B) | Application notes | Texas Instruments Using the SPI Interface with TRF7960 (Rev. B) Application notes

Texas Instruments Using the SPI Interface with TRF7960 (Rev. B) Application notes
Application Report
SLOA140B – April 2009 – Revised November 2018
Using the SPI Interface With TRF7960
ShreHarsha Rao
ABSTRACT
One of the microcontroller interfacing options available for the TRF7960 is the SPI with SS*. This is also
known as 4-wire hardware SPI mode. The TRF7960 device acts as the slave device and the
microcontroller or DSP is the master in this configuration.
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Contents
TRF7960 - SPI With SS* Mode Errata ....................................................................................
1.1
SCLK Polarity Switch ...............................................................................................
1.2
IRQ Status Register Read .........................................................................................
1.3
Direct Command Processing ......................................................................................
1.4
Initialization of Derivative Registers ..............................................................................
1.5
Transmitting One Byte Through the FIFO .......................................................................
1.6
Extra Dummy Bytes on RX ........................................................................................
1.7
Timing Conditions for MOSI With Respect to S_CLK .........................................................
2
3
4
5
7
7
8
9
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All other trademarks are the property of their respective owners.
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TRF7960 - SPI With SS* Mode Errata
It is important to note that there are some nonstandard conditions when the TRF7960 is operated in the
SPI mode. Table 1 lists these conditions and the software patches to work around them.
Table 1. Nonstandard Conditions
Condition
Software Fix
SCLK clock polarity switch needed when read operation
(single or continuous) is executed.
Firmware fix to switch clock polarity between writes and reads (see
Section 1.1).
IRQ Status register is not automatically cleared after reading.
Dummy read is needed to clear the contents of IRQ status register
and hence drive the IRQ pin low (see Section 1.2).
All stand-alone (single-byte) direct commands need additional All direct command functions need to have this additional SW fix.
clock cycle to work. An example is the slot markers (EOF) for Direct commands like “Transmit Next Slot” needs to have additional
ISO 15693 do not work in SPI mode.
SCLK cycle before SS* goes high (see Section 1.3).
Some of the registers (RX wait time, RX no response wait
Manually program these defaults again in the initialization routine
time) do not take default values when the appropriate protocol
(see Section 1.4).
is chosen in the ISO control register.
Transmitting one byte through the FIFO.
Split the command (See Section 1.5).
The serial interface is in reset while the SS* signal is high. Serial Data-In (MOSI) changes on the falling
edge, and are validated in the reader on the rising edge (see Figure 1). Communication is terminated
when SS* signal goes inactive (high). All words must be 8 bits long with the MSB transmitted first.
WRITE OPERATION
SCLK
MOSI
B7
B6
B5
B4
B3
B2
B1
B0
SS*
Figure 1. Serial - SPI Interface Communication (Write Mode)
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1.1
SCLK Polarity Switch
The SPI read operation is shown in Figure 2 below.
Write Mode
CKPH – 1 CKPL -0 (MSP430)
Data Transition – SCLK Falling Edge
MOSI Valid – SCLK Rising Edge
Read Mode
CKPH – 0 CKPL -0 (MSP430)
Data Transition – SCLK Rising Edge
MISO Valid – SCLK Falling Edge
Switch
SCLK
Polarity
SINGLE READ OPERATION
Write address byte
Read data byte
SCLK
MOSI
B7
B6
B5
B4
B3
B2
B1
B0
No Data Transitions (All High/Low)
MISO
Don’t Care
B7
B6
B5
B3
B4
B2
B1
B0
SS*
Figure 2. Serial - SPI Interface Communication (Read Mode)
The read command is sent out on the MOSI pin, MSB first in the first 8 clock cycles. MOSI data changes
on the falling edge, and is validated in the reader on the rising edge (see Figure 2). During the write cycle
the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the 8th rising
edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling edge of
SCLK. It takes 8 clock edges to read out the full byte (MSB first).
NOTE: When using the hardware SPI (for example, a MSP430 hardware SPI) to implement the
above feature, care must be taken to switch the SCLK polarity after write phase for proper
read operation. The example clock polarity for the MSP430-specific environment is shown in
the box above. Refer to the USARTSPI chapter for any specific microcontroller family for
further information on the setting the appropriate clock polarity.
This clock polarity switch NEEDS to be done for all read (single, continuous) operations.
The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also,
the SS* should be low during the whole write and read operation.
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The clock polarity switch is illustrated by the following pseudo code. This code refers specifically to the
MSP430 platform. See the data sheet of the relevant microcontroller for your design.
*pbuf = (0x40 | *pbuf);
// address, read, single
*pbuf = (0x5f &*pbuf);
// register address
while (!(IFG2 & UCB0TXIFG));
// USCI_B0 TX buffer ready?
UCB0TXBUF = *pbuf;
// Previous data to TX, RX
//while (!(IFG2 & UCB0RXIFG));
temp=UCB0RXBUF;
UCB0CTL1 |= UCSWRST;
UCB0CTL0 &= ~UCCKPH;
// switch clock polarity for read
UCB0CTL1 &= ~UCSWRST;
SPIStartCondition();
P3SEL |= BIT3;
while (!(IFG2 & UCB0TXIFG));
UCB0TXBUF = 0x00;
// SCLK High/Low to complete the cycle
// USCI_B0 TX buffer ready?
// Receive initiated by a dummy TX write???
while (!(IFG2 & UCB0RXIFG));
_NOP();
_NOP();
*pbuf = UCB0RXBUF;
pbuf++;
lenght--;
UCB0CTL0 |= UCCKPH;
// revert to original clock polarity
Figure 3 shows the continuous read operation.
Continuous Read Operation
Write Address
byte
Read Data
Byte n
Read Data
Byte 1
SCLK
MOSI
B7 B6 B5 B4 B3 B2 B1 B0
MISO
Don’t Care
No transitions (High/Low)
No transitions (High/Low)
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
SS*
Figure 3. SPI Interface Communication (Continuous Read Mode)
1.2
IRQ Status Register Read
NOTE: Special steps are needed when you read the TRF796x IRQ status register (register address
0x0C) in SPI mode. The status of the bits in this register are cleared after a “dummy read”.
The following steps need to be followed when reading the IRQ status register.
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1. Write in command 0x6C: read 'IRQ status' register in continuous mode (8 clocks).
2. Read out the data in register 0x0C (8 clocks).
3. Generate another 8 clocks (as you were reading the data in register 0x0D) but ignore the MISO data
line.
This is shown in Figure 4.
Special Case – IRQ Status Register Read
Write Address
byte (0x6C)
Read Data in
IRQ Status
Register
Dummy Read
No Transitions (High/Low)
No Transitions (High/Low)
SCLK
MOSI
B7 B6 B5 B4 B3 B2 B1 B0
MISO
Don’t Care
B7 B6 B5 B4 B3 B2 B1 B0
Ignore
SS*
Figure 4. SPI Interface Communication (IRQ Status Register Read)
1.3
Direct Command Processing
Table 2 lists the direct commands supported by the TRF7960 and TRF7961.
Table 2. Command Codes
Command Code (hex)
Command
00
Idle
Comments
03
Software initialization
0F
Reset FIFO
10
Transmission without CRC
11
Transmission wtih CRC
12
Delayed transmission without CRC
EPC
13
Delayed transmission with CRC
EPC
14
Transmit next time slot
ISO15693, Tag-it™
16
Block receiver
17
Enable receiver
18
Test internal RF (RSSI at RX input with TX off)
19
Test internal RF (RSSI at RX input with TX on)
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Software initialization, same as power on reset
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Table 3 lists the direct commands that need the software fix when using SPI with SS* mode. These are
the direct commands that are executed stand-alone (direct commands with just one byte).
Table 3. Direct Commands
Direct Command
Command Code
Need Dummy Clock
Idle
0x03
Yes
Software initialization
0x00
Yes
Reset FIFO
0x0F
Yes
Transmit next time slot
0x14
Yes
Block receiver
0x16
Yes
Enable receiver
0x17
Yes
Test internal RF
0x18
Yes
Test external RF
0x19
Yes
Transmit without CRC
0x10
No
Transmit with CRC
0x11
No
Delayed transmit without CRC
0x12
No
Delayed transmit with CRC
0x13
No
It is recommended to have this software fix written as part of a direct command function. An example of a
direct command is the slot markers (EOF) for ISO 15693. This will not work in SPI mode.
This is solved by a software fix by implementing the direct command (for example transmit next slot” ) in
one of two ways:
1. Have an additional SCLK cycle (low/high) before SS* goes high.
or
2. Send a dummy TX write (8 SCLK cycles) before SS* goes high.
This is shown in the diagram below.
Any one of the three dummy clock options work.
0x8F FIFO Reset
DATA
CLK
1
2
3
The pseudo code shown below in the DirectCommand function implements a SCLK low/high/low
transition.
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SlaveSelectLOW; //Start SPI Mode
*pbuf = (0x80 | *pbuf); /* command */
*pbuf = (0x9f &*pbuf);
/* command code */
while (!(IFG2 & UCB0TXIFG));
// USCI_B0 TX buffer ready?
UCB0TXBUF = *pbuf;
// Previous data to TX, RX
// while (!(IFG2 & UCB0RXIFG));
temp=UCB0RXBUF;
SPIStartCondition(); //SCLK Low/High cycle implemented
SlaveSelectHIGH; //Stop SPI Mode
P3SEL |=
1.4
BIT3;
//Revert Back
Initialization of Derivative Registers
Some of the registers (RX wait time, RX no response wait time) do not take default values when the Tagit™ protocol is chosen in the ISO control register. This is solved by manually programming the timing
related registers in the Initialization routine as shown in the pseudo code of the TIInventoryRequest
function below.
//added code
buf[0] = RXNoResponseWaitTime;
buf[1] = 0x14;
buf[2] = ModulatorControl;
buf[3] = 0x21;
WriteSingle(buf, 4);
//end added code
It is also recommended that the modulator and system clock register (register 0x09) be re-initialized when
the inventory request (15693) or REQB (14443B) or REQA (14443A) is issued.
1.5
Transmitting One Byte Through the FIFO
When transmitting one byte to the TRF7960 using SPI with SS* mode, a special firmware fix is needed.
This method involves splitting the writes into two operations as shown in the pseudo code below.
buf[0] = 0x8f;
buf[1] = 0x91;
buf[2] = 0x3d;
buf[3] = 0x00;
buf[4] = 0x10;
RAWwrite(&buf[0], 5);
buf[5] = 0x3F;
buf[6] = "one byte data to be transmitted";
buf[7] = 0x00;
RAWwrite(&buf[5], 3);
Each RAW Write function takes the SS low and high. Please refer to the TRF7960 firmware for definition
of RAWwrite function. (file name parallel.c)
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1.6
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Extra Dummy Bytes on RX
A specific condition can cause the TRF7960 to output two additional dummy bytes of data when reading
the FIFO after an RX operation. This occurs when the MOSI line is left high after issuing the direct
command to continuous read from the TRF7960 FIFO. The MOSI line can left high due to not properly
resetting the SPI module while changing the SCLK polarity for the read operation. Figure 5 shows the root
cause of this output.
Figure 5. Screenshot With Root Cause
To fix this, ensure the SPI module is properly reset in the MCU when toggling the SCLK polarity between
read and write operations. This should force the MOSI line back low and resolve the issue. Figure 6
shows the updated firmware, and Figure 7 shows the signals after correction.
Figure 6. Screenshot of Adjusted Firmware
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Figure 7. Screenshot With Issue Fixed
1.7
Timing Conditions for MOSI With Respect to S_CLK
When in SPI mode, MOSI should be able to rise or fall independent of S_CLK as long as SPI timing
requirements are met. However, while in SPI mode, if MOSI has a falling edge before the end of a high
period of S_CLK, then the device treats it as a parallel mode stop condition and does not register the data.
This behavior occurs only when S_CLK and MOSI are high and the state of MOSI changes from logic high
to logic low before the state of S_CLK change from logic high to logic low (see Figure 8).
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Issue occurs
Communication is terminated by the parallel mode Stop condition
when MOSI data changes during a high SCLK period.
SCLK
Falling edge
Issue does not occur
Issue does not occur
SCLK
SCLK
Falling edge
MOSI
MOSI
Falling edge
Figure 8. Parallel Mode Stop Condition
In use cases where SPI is not naturally synchronized, the workaround is to add software guards to prevent
MOSI from changing state before S_CLK.
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from May 31, 2017 to November 27, 2018 ........................................................................................................ Page
•
Added Section 1.7, Timing Conditions for MOSI With Respect to S_CLK
........................................................
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