Texas Instruments | DN113 CC111xFx CC243xFx CC251xFx CC253xFx SPI Interface (Rev. A) | Application notes | Texas Instruments DN113 CC111xFx CC243xFx CC251xFx CC253xFx SPI Interface (Rev. A) Application notes

Texas Instruments DN113 CC111xFx CC243xFx CC251xFx CC253xFx SPI Interface (Rev. A) Application notes
Design Note DN113
CC111xFx, CC243xFx,CC251xFx and CC253xFx SPI
By Siri Johnsrud and Torgeir Sundet
Keywords






1






SPI
USART
Master
Slave
CC1110Fx
CC1111Fx
CC2430Fx
CC2431Fx
CC2510Fx
CC2511Fx
CC2530Fx
CC2531Fx
Introduction
The purpose of this design note is to
describe how to operate the two USARTs
in synchronous SPI mode, both as a
master and as a slave.
In the following sections, an x in the
register name represents the USART
number 0 or 1 if nothing else is stated. All
code examples use USART1.
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Design Note DN113
Table of Contents
KEYWORDS.............................................................................................................................. 1
1
INTRODUCTION ............................................................................................................. 1
ABBREVIATIONS........................................................................................................... 2
2
CONFIGURING THE USART FOR SPI MODE.............................................................. 3
3
I/O PINS .................................................................................................................... 3
3.1
3.2
BAUD RATE ............................................................................................................... 4
3.3
MODE OF OPERATION ................................................................................................ 4
3.4
POLARITY, CLOCK PHASE, AND BIT ORDER ................................................................. 4
4
IMPLEMENTING THE CODE ......................................................................................... 6
MASTER TO SLAVE ..................................................................................................... 8
4.1
4.1.1
Polling of Status Bits ........................................................................................................8
Interrupt Driven Solution ...............................................................................................10
4.1.2
DMA ...............................................................................................................................11
4.1.3
SLAVE TO MASTER ................................................................................................... 14
4.2
4.2.1
Polling of Status Bits ......................................................................................................14
REFERENCES .............................................................................................................. 16
5
GENERAL INFORMATION .......................................................................................... 17
6
DOCUMENT HISTORY................................................................................................ 17
6.1
2
Abbreviations
GPIO
IC
I/O
ISR
LSB
MISO
MOSI
MSB
RX
SoC
SPI
TX
USART
General Purpose Input/Output
Integrated Circuit
Input/Output
Interrupt Service Routine
Least Significant Bit
Master In Slave Out
Master Out Slave In
Most Significant Bit
Receive. Used in this document to reference SPI receive.
System on Chip. A collective term used to refer to Texas Instruments
ICs with on-chip MCU and RF transceiver. Used in this document to
reference the CC1110Fx, CC1111Fx, CC2430Fx, CC2431Fx,
CC2510Fx, CC2511Fx, CC2530Fx and CC2531Fx.
Serial Peripheral Interface
Transmit. Used in this document to reference SPI transmit
Universal Synchronous/Asynchronous Receiver/Transmitter
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Design Note DN113
3
Configuring the USART for SPI Mode
There are several things that need to be set up correctly before the USART can be used in
SPI mode, and these things are described in the following sections.
3.1
I/O Pins
When used in SPI mode, both USARTs can choose between two alternative locations for its
I/O pins (see Table 1).
USART0
Alternative 1
Alternative 2
USART1
Pin
Signal
Setting
Pin
Signal
Setting
P0_4
SSN
PERCFG.U0CFG = 0
P0_2
SSN
PERCFG.U1CFG = 0
P0_5
SCK
P0_3
SCK
P0_3
MOSI
P0_4
MOSI
P0_2
MISO
P0_5
MISO
P1_2
SSN
P1_4
SSN
P1_3
SCK
P1_5
SCK
P1_5
MOSI
P1_6
MOSI
P1_4
MISO
P1_7
MISO
PERCFG.U0CFG = 1
PERCFG.U1CFG = 1
Table 1. I/O Location
Next one needs to configure the I/O pins on the selected location (alternative 1 or 2) to be
peripheral I/O pins. This is done through the PxSEL registers, by setting PxSEL.SELPx_n =
1 (x = 0, 1, or 2 and indicates the port number, while n = 0, 1, 2, .., 7 and indicates the pin
number).
Note: In SPI master mode, only the MOSI, MISO, and SCK should be configured as
peripheral I/Os. If the external slave requires a slave select signal (SSN) then a GPIO should
be configured as output on the Master to control the SSN.
The code below shows how both a master and a slave unit are configured to map USART1 to
its alternative 2 location.
// Master Mode
PERCFG |= 0x02;
P1SEL |= 0xE0;
P1SEL &= ~0x10;
P1DIR |= 0x10;
//
//
//
//
PERCFG.U1CFG = 1
P1_7, P1_6, and P1_5 are peripherals
P1_4 is GPIO (SSN)
SSN is set as output
// Slave Mode
PERCFG |= 0x02;
// PERCFG.U1CFG = 1
P1SEL |= 0xF0;
// P1_7, P1_6, P1_5, and P1_4 are peripherals
/*-------------------------------------------------------------------------------Master
Slave
------------------------|
|
|
|
|P1_4
SSN |--------->|SSN
P1_4|
|
|
|
|
|P1_5
SCK |--------->|SCK
P1_5|
|
|
|
|
|P1_6
MOSI|--------->|MOSI
P1_6|
|
|
|
|
|P1_7
MISO|<---------|MISO
P1_7|
|
|
|
|
--------------------------------------------------------------------------------------------------------*/
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Design Note DN113
3.2
Baud Rate
The SPI master clock frequency is set up by an internal baud rate generator, meaning that
Timer 1, Timer 2, Timer 3, and Timer 4, can be used for other purposes. The SCK frequency
is given by Equation 1, where F is the system clock frequency and BAUD_M and BAUD_E can
be found in UxBAUD and Ux0GCR respectively.

256  BAUD _ M   2 BAUD _ E

F
f SCK
228
Equation 1. SCK Frequency
The maximum baud rate and thus SCK frequency is F/8.
Note: If the SPI master does not need to receive data, the maximum baud rate can be
increased to F/2.
Maximum baud rate (F/8) can be achieved by setting BAUD_M = 0 and BAUD_E = 17.
// Set baud rate
// Assuming a 26
// max baud rate
U1BAUD = 0x00;
U1GCR |= 0x11;
to max (system clock frequency / 8)
MHz crystal (CC1110Fx/CC2510Fx),
= 26 MHz / 8 = 3.25 MHz.
// BAUD_M = 0
// BAUD_E = 17
Note: The baud rate must never be changed during a transfer (i.e when UxCSR.ACTIVE is
asserted).
3.3
Mode of Operation
To configure USARTx to operate in SPI mode, UxCSR.MODE must be set to 0. UxCSR.SLAVE
should be 0 for master mode and 1 for slave mode.
// SPI Slave Mode
U1CSR &= ~0x80;
U1CSR |= 0x20;
// SPI Master Mode
U1CSR &= ~0xA0;
3.4
Polarity, Clock Phase, and Bit Order
The phase and polarity of SCK is configured through UxGCR.CPHA and UxGCR.CPOL (see
Table 2).
Register
UxGCR.CPOL
UxGCR.CPHA
Setting
Comment
0
1
0
1
SCK low when idle
SCK high when idle
Data centered on first edge of SCK period
Data centered on second edge of SCK period
Table 2. SCK Phase and Polarity
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Design Note DN113
The transfer bit order is configured by setting UxGCR.ORDER = 0 for LSB first and
UxGCR.ORDER = 1 for MSB first. Figure 1 shows the SCK signal for the different phase and
polarity configurations in addition to MOSI and MISO, for both UxGCR.ORDER = 0 and
UxGCR.ORDER = 1.
Figure 1. Phase, Polarity, and Bit Order
The code example below show how the SPI should be configured for negative clock polarity,
data centered on second edge of SCK, and transferring MSB first.
// Configure phase, polarity, and bit order
U1GCR &= ~0xC0;
// CPOL = CPHA = 0
U1GCR |= 0x20;
// ORDER = 1
/*-----------------------------------------------------------------------------------------------------------| |
| |
| |
| |
| |
| |
| |
| |
| |
---------------------------------------------------------------------------------------------------------| MSB
|
|
|
|
|
|
|
| LSB |
------------------------------------------------------------------------------------------------------------------------------------------------------------*/
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Design Note DN113
4
Implementing the Code
In this section, different methods of sending data from master to slave and from slave to
master will be discussed and code examples will be shown. In all the following examples, the
data to be transferred are shown in Figure 2. Assume that both slave and master have one
buffer for data to be transmitted and one for data to be received. These buffers are called
rxBufferSlave, txBufferSlave, rxBufferMaster, and txBufferMaster and are all 10 bytes wide. It
is also assumed that USART1 has been initialized as shown in the previous code examples.
Four different software flags are also implemented in the code; mDataTransmitted,
mDataReceived, sDataTransmitted, and sDataReceived.
Figure 2. Data to be Transferred between Master and Slave
Note:
SPI communication means that the slave is clocked by the master. An important
implication of this is that the slave must complete its access (write/read) to the data buffer
(for the SoC this means UxDBUF) within the frame/byte gap of the master. Otherwise the
slave risks loosing data in RX or re-transmitting data in TX. For example, assuming a
slave to master transmission, if the slave then fails to update (write) UxDBUF in time before
the master starts clocking the next frame/byte, then the “old” slave UxDBUF contents will
be clocked out on the MISO line. This particular concern must be carefully reviewed when
choosing implementation of slave RX/TX method, that is; polling of SPI status bits, SPI
ISR, or DMA.
For an SoC slave it is recommended to use a designated DMA channel to handle SPI
RX/TX, as this guarantees fastest possible transfer of data between the SoC memory and
UxDBUF. Using SPI ISR implies that the SoC CPU must jump to the SPI ISR upon each
enabled SPI interrupt request. This adds SPI processing time on the slave, and
consequently the slave needs the master to adjust the frame/byte gap accordingly. The
same limitation applies on the slave for polling-based SPI RX/TX. However, since polling it
self does not execute jump instructions, this method typically allows somewhat shorter
byte/frame gaps than for SPI ISR method. In general, if nothing interrupts the SPI
ISR/polling method, then it is possible to determine/estimate the required byte/frame gap
which should be applied by the master.
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Design Note DN113
Sections 4.1, 4.1.2, and 4.1.3 will show how data are written by the master and read by the
slave. The following defines are included in the code:
// Define basic data types:
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned char UINT8;
// Define data structure for DMA descriptor:
typedef struct {
unsigned char SRCADDRH;
// High byte of the source address
unsigned char SRCADDRL;
// Low byte of the source address
unsigned char DESTADDRH;
// High byte of the destination address
unsigned char DESTADDRL;
// Low byte of the destination address
unsigned char VLEN
: 3; // Length configuration
unsigned char LENH
: 5; // High byte of fixed length
unsigned char LENL
: 8; // Low byte of fixed length
unsigned char WORDSIZE : 1; // Number of bytes per transfer element
unsigned char TMODE
: 2; // DMA trigger mode (e.g. single or repeated)
unsigned char TRIG
: 5; // DMA trigger; SPI RX/TX
unsigned char SRCINC
: 2; // Number of source address increments
unsigned char DESTINC
: 2; // Number of destination address increments
unsigned char IRQMASK
: 1; // DMA interrupt mask
unsigned char M8
: 1; // Number of desired bit transfers in byte mode
unsigned char PRIORITY : 2; // The DMA memory access priority
} DMA_DESC;
// Define masks, fixed values, etc.
#define DMAIF0
0x01 // Bit mask for DMA channel 0 interrupt flag (DMAIRQ)
#define DMAARM0
0x01 // Bit mask for DMA arm channel 0 bit (DMAARM)
#define ABORT
0x80 // Bit mask for DMA abort bit (DMAARM)
#define UTX1IF
0x40 // Bit mask for USART1 TX interrupt flag (IRCON2)
#define URX1IF
0x80 // Bit mask for USART1 RX interrupt flag (TCON)
#define SSN
P1_4
#define LOW
0
#define HIGH
1
#define N
9
// Length byte
#define TRUE
1
#define FALSE
0
// Define macro for splitting 16 bits in 2 x 8 bits:
#define HIBYTE(a) (BYTE) ((WORD)(a) >> 8)
#define LOBYTE(a) (BYTE) (WORD)(a)
#define SET_WORD(regH, regL, word) \
do {
\
(regH) = HIBYTE( word );
\
(regL) = LOBYTE( word );
\
} while(0)
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Design Note DN113
4.1
Master to Slave
Master is going to transmit (write) 10 bytes to the slave.
4.1.1
Polling of Status Bits
4.1.1.1
UxCSR.UxTX_BYTE and UxCSR.UxRX_BYTE
In master mode, the assertion of the UxCSR.TX_BYTE bit can be used as an indication on
when new data can be written to UxDBUF. In slave mode, the assertion of UxCSR.RX_BYTE
indicates that UxDBUF can be read.
// SPI Master (SSN is only necessary if the slave requires a slave select signal)
// Method 1; SSN kept low during the transfer of all 10 bytes
SSN = LOW;
for (i = 0; i <= N; i++)
{
U1DBUF = txBufferMaster[i];
while (!U1TX_BYTE);
U1TX_BYTE = 0;
}
SSN = HIGH;
mDataTransmitted = TRUE;
// or
// Method 2; SSN pulled high between every single byte
for (i = 0; i <= N; i++)
{
SSN = LOW;
U1DBUF = txBufferMaster[i];
while (!U1TX_BYTE);
SSN = HIGH;
U1TX_BYTE = 0;
}
mDataTransmitted = TRUE;
// SPI Slave
for (i = 0; i <= N; i++)
{
while (!U1RX_BYTE);
U1RX_BYTE = 0;
rxBufferSlave[i] = U1DBUF;
}
sDataReceived = TRUE;
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Design Note DN113
4.1.1.2
UxCSR.ACTIVE
In master mode, UxCSR.ACTIVE is asserted when a byte transfer is initiated (i.e. when the
UxDBUF register is written) and de-asserted when it ends. In slave mode, the UxCSR.ACTIVE
bit is asserted when SSN is pulled low and de-asserted when it is pulled high again. This
means that if polling of the UxCSR.ACTIVE bit should be used in slave mode, the master
must pull SSN high in between every byte transferred.
// SPI Master (SSN is only necessary if the slave requires a slave select signal)
// Method 1; SSN kept low during the transfer of all 10 bytes
SSN = LOW;
for (i = 0; i <= N; i++)
{
U1DBUF = txBufferMaster[i];
// U1ACTIVE is asserted
while (U1ACTIVE);
// Wait for U1ACTIVE to be de-asserted
}
SSN = HIGH;
mDataTransmitted = TRUE;
// or
// Method 2; SSN pulled high between every single byte
for (i = 0; i <= N; i++)
{
SSN = LOW;
U1DBUF = txBufferMaster[i];
// U1ACTIVE is asserted
while (U1ACTIVE);
// Wait for U1ACTIVE to be de-asserted
SSN = HIGH;
}
mDataTransmitted = TRUE;
// SPI Slave (For this approach to work, SSN must be pulled high in between every
// byte that is transferred)
for (i = 0; i <= N; i++)
{
while (!U1ACTIVE);
// Wait for U1ACTIVE to be asserted (SSN pulled low)
while (U1ACTIVE);
// Wait for U1ACTIVE to be de-asserted (SSN pulled high)
rxBufferSlave[i] = U1DBUF;
}
sDataReceived = TRUE;
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Design Note DN113
4.1.2
Interrupt Driven Solution
It is not possible to use an interrupt based solution in master mode, as there are some issues
related to the USARTx TX complete CPU interrupt flag (IRCON2.UTXxIF). Please see the
data sheets for more details ([1], [2], [3] and [4]). In slave mode, the USARTx RX complete
CPU interrupt flag, TCON.URXxIF, is asserted when the received data byte is available in
UxDBUF.
Note: The interval between data bytes sent from the master to the slave must be long enough
for the slave’s ISR to complete before a new interrupt request is being generated.
//--------------------------------------------------------------------------------// 1. Clear interrupt flags
// For pulsed or edge shaped interrupt sources one should clear the CPU interrupt
// flag prior to clearing the module interrupt flag
TCON &= ~URX1IF;
// 2. Set individual interrupt enable bit in the peripherals SFR, if any
// 3. Set the corresponding individual, interrupt enable bit in the IEN0, IEN1, or
// IEN2 registers to 1
URX1IE = 1;
// 4. Enable global interrupt
EA = 1;
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------#pragma vector=URX1_VECTOR
__interrupt void urx1_IRQ(void)
{
static UINT8 bufferIndex = 0;
TCON &= ~URX1IF;
// Clear the CPU URX1IF interrupt flag
rxBufferSlave[bufferIndex++] = U1DBUF;
if (bufferIndex == (N + 1))
{
bufferIndex = 0;
sDataReceived = TRUE;
}
}
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------while (condition)
{
if (sDataReceived)
{
// All 10 bytes are received
sDataReceived = FALSE;
}
// Implement code to execute while waiting for the 10 bytes to be received
// .
// .
// .
}
//---------------------------------------------------------------------------------
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Design Note DN113
4.1.3
DMA
It is also possible to use the DMA to move data to and from UxDBUF and this is the only
method which allow for back-to-back transfers. There are two DMA triggers associated with
each USART (URX0, UTX0, URX1, and UTX1). The DMA triggers are activated by the same
events that might generate USART interrupt requests. Even though there is an issue related
to the USARTx TX complete CPU interrupt flag, the only limitation related to using the URX0
and URX1 is that the UxGDR.CPHA bit must be set to zero.
If IRQMASK = 1, the CPU interrupt flag IRCON.DMAIF will be asserted when the transfer
count is reached and an interrupt request will be generated if the corresponding CPU
interrupt mask bit, IEN1.DMAIE, is 1.
The first UTXx DMA trigger event does not occur before a byte is written to UxDBUF. Since
the DMA does not write to UxDBUF before it gets a trigger event, it is necessary to manually
trigger the DMA by setting DMAREQ.DMAREQn = 1 after the DMA has been armed by setting
DMAARM.DMAARMn = 1 (n is the DMA channel number). The remaing 9 trigger events will be
generated automatically by the USART when UxDBUF is ready to be loaded with new data.
Note: When the transfer count is reached (in the code below that will be when all 10 bytes
have been written to UxDBUF), the transfer of byte number 10 is not yet completed. It is
therefore necessary to wait for UxCSR.ACTIVE to be de-asserted before pulling SSN high.
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Design Note DN113
// SPI Master
//--------------------------------------------------------------------------------DMA_DESC __xdata dmaConfigTx;
SET_WORD(dmaConfigTx.SRCADDRH, dmaConfigTx.SRCADDRL, txBufferMaster);
SET_WORD(dmaConfigTx.DESTADDRH, dmaConfigTx.DESTADDRL, &X_U1DBUF);
dmaConfigTx.VLEN
= 1; // Transfer number of bytes commanded by n, + 1
SET_WORD(dmaConfigTx.LENH, dmaConfigTx.LENL, N + 1); //LEN = nmax + 1
dmaConfigTx.WORDSIZE = 0; // Each transfer is 8 bits
dmaConfigTx.TRIG
= 17; // Use UTX1 trigger
dmaConfigTx.TMODE
= 0; // One byte transferred per trigger event
dmaConfigTx.SRCINC
= 1; // Increase source addr. by 1 between transfers
dmaConfigTx.DESTINC
= 0; // Keep the same dest. addr. for all transfers
dmaConfigTx.IRQMASK
= 1; // Allow IRCON.DMAIF to be asserted when the transfer
// count is reached
dmaConfigTx.M8
= 0; // Use all 8 bits of first byte in source data to
// determine the transfer count
dmaConfigTx.PRIORITY = 2; // DMA memory access has high priority
// Save pointer to the DMA config. struct into DMA ch. 0 config. registers
SET_WORD(DMA0CFGH, DMA0CFGL, &dmaConfigTx);
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------// 1. Clear interrupt flags
// For pulsed or edge shaped interrupt sources one should clear the CPU interrupt
// flag prior to clearing the module interrupt flag
DMAIF = 0;
DMAIRQ &= ~DMAIF0;
// 2. Set individual interrupt enable bit in the peripherals SFR, if any
// No flag for the DMA (Set in the DMA struct (IRQMASK = 1))
// 3. Set the corresponding individual, interrupt enable bit in the IEN0, IEN1, or
// IEN2 registers to 1
DMAIE = 1;
// 4. Enable global interrupt
EA = 1;
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------#pragma vector=DMA_VECTOR
__interrupt void dma_IRQ(void)
{
DMAIF = 0;
// Clear the CPU DMA interrupt flag
DMAIRQ &= ~DMAIF0;
// DMA channel 0 module interrupt flag
while (U1ACTIVE);
// Wait for the transfer to complete (the last byte
// transfer is not complete even if transfer count is
// reached)
mDataTransmitted = TRUE; // All 10 bytes are transmitted
}
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------DMAARM = DMAARM0;
// Arm DMA channel 0
SSN = LOW;
DMAREQ = 0x01;
while (condition)
{
if (mDataTransmitted)
{
SSN = HIGH; // All 10 bytes are sent so SSN is pulled high again
mDataTransmitted = FALSE;
}
// Implement code to execute while waiting for the 10 bytes to be transmitted
// .
// .
// .
}
//---------------------------------------------------------------------------------
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Design Note DN113
// SPI Slave
//--------------------------------------------------------------------------------DMA_DESC __xdata dmaConfigRx;
SET_WORD(dmaConfigRx.SRCADDRH, dmaConfigRx.SRCADDRL, &X_U1DBUF);
SET_WORD(dmaConfigRx.DESTADDRH, dmaConfigRx.DESTADDRL, rxBufferSlave);
dmaConfigRx.VLEN
= 1; // Transfer number of bytes commanded by n, + 1
SET_WORD(dmaConfigRx.LENH, dmaConfigRx.LENL, N + 1); //LEN = nmax + 1
dmaConfigRx.WORDSIZE = 0; // Each transfer is 8 bits
dmaConfigRx.TRIG
= 16; // Use URX1 trigger
dmaConfigRx.TMODE
= 0; // One byte transferred per trigger event
dmaConfigRx.SRCINC
= 0; // Keep the same source addr. for all transfers
dmaConfigRx.DESTINC
= 1; // Increase dest. addr. by 1 between transfers
dmaConfigRx.IRQMASK
= 1; // Allow IRCON.DMAIF to be asserted when the transfer
// count is reached
dmaConfigRx.M8
= 0; // Use all 8 bits of first byte in source data to
// determine the transfer count
dmaConfigRx.PRIORITY = 2; // DMA memory access has high priority
// Save pointer to the DMA config. struct into DMA ch. 0 config. registers
SET_WORD(DMA0CFGH, DMA0CFGL, &dmaConfigRx);
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------// 1. Clear interrupt flags
// For pulsed or edge shaped interrupt sources one should clear the CPU interrupt
// flag prior to clearing the module interrupt flag
DMAIF = 0;
DMAIRQ &= ~DMAIF0;
// 2. Set individual interrupt enable bit in the peripherals SFR, if any
// No flag for the DMA (Set in the DMA struct (IRQMASK = 1))
// 3. Set the corresponding individual, interrupt enable bit in the IEN0, IEN1, or
// IEN2 registers to 1
DMAIE = 1;
// 4. Enable global interrupt
EA = 1;
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------#pragma vector=DMA_VECTOR
__interrupt void dma_IRQ(void)
{
DMAIF = 0;
// Clear the CPU DMA interrupt flag
DMAIRQ &= ~DMAIF0;
// DMA channel 0 module interrupt flag
sDataReceived = TRUE;
// All 10 bytes are received
}
//--------------------------------------------------------------------------------//--------------------------------------------------------------------------------DMAARM = DMAARM0;
// Arm DMA channel 0
while (condition)
{
if (sDataReceived)
sDataReceived = FALSE; // All 10 bytes are received
//
//
//
//
Implement code to execute while waiting for the 10 bytes to be received
.
.
.
}
Since the SSN signal must be asserted and de-asserted by the application and is not handled
by the USART (master mode), it does only make sense to use the DMA in master mode in
cases where several bytes shall be transferred in a row without pulling SSN high between
every byte transfer.
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Design Note DN113
4.2
Slave to Master
Master is going to receive (read) 10 bytes from the slave.
4.2.1
Polling of Status Bits
4.2.1.1
UxCSR.UxTX_BYTE and UxCSR.UxRX_BYTE
In master mode, the assertion of the UxCSR.TX_BYTE bit can be used as an indication on
when data can be read from UxDBUF. In slave mode, the assertion of UxCSR.RX_BYTE
indicates that a new byte can be written to UxDBUF.
// SPI Master (SSN is only necessary if the slave requires a slave select signal)
// Method 1; SSN kept low during the transfer of all 10 bytes
SSN = LOW;
for (i = 0; i <= N; i++)
{
U1DBUF = dummyByte;
while (!U1TX_BYTE);
rxBufferMaster[i] = U1DBUF;
U1TX_BYTE = 0;
}
SSN = HIGH;
mDataReceived = TRUE;
// or
// Method 2; SSN pulled high between every single byte
for (i = 0; i <= N; i++)
{
SSN = LOW;
U1DBUF = dummyByte;
while (!U1TX_BYTE);
rxBufferMaster[i] = U1DBUF;
SSN = HIGH;
U1TX_BYTE = 0;
}
mDataReceived = TRUE;
// SPI Slave
for (i = 0; i <= N; i++)
{
U1DBUF = txBufferSlave[i];
while (!U1RX_BYTE);
U1RX_BYTE = 0;
}
sDataTransmitted = TRUE;
4.2.1.2
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Design Note DN113
UxCSR.ACTIVE
In master mode, UxCSR.ACTIVE is asserted when a byte transfer is initiated (i.e. when the
UxDBUF register is written) and de-asserted when it ends. In slave mode, the UxCSR.ACTIVE
bit is asserted when SSN is pulled low and de-asserted when it is pulled high again. When
the slave is going to write a byte to the master, the data must be written to UxDBUF before
SSN is pulled low. One should therefore think that it would be possible to implement the
following code to write 10 bytes from slave to master, but that is not the case.
for (i = 0; i <= N; i++)
{
U1DBUF = txBufferSlave[i];
while (!U1ACTIVE);
// Wait for U1ACTIVE to be asserted (SSN pulled low)
while (U1ACTIVE);
// Wait for U1ACTIVE to be de-asserted (SSN pulled high)
}
sDataTransmitted = TRUE;
Due to the double buffering of UxDBUF and the way the content of this register is moved to an
internal shift register, one might risk transmitting the same byte twice. The ACIVE bit should
therefore not be used in slave mode to determine when a new byte can be written to UxDBUF.
The code for how the ACTIVE bit can be used in master mode when reading a byte from the
slave is shown below.
// SPI Master (SSN is only necessary if the slave requires a slave select signal)
// Method 1; SSN kept low during the transfer of all 10 bytes
SSN = LOW;
for (i = 0; i <= N; i++)
{
U1DBUF = dummyByte; // U1ACTIVE is asserted
while (U1ACTIVE);
// Wait for U1ACTIVE to be de-asserted (U1DBUF can be read)
rxBufferMaster[i] = U1DBUF;
}
SSN = HIGH;
mDataReceived = TRUE;
// or
// Method 2; SSN pulled high between every single byte
for (i = 0; i <= N; i++)
{
SSN = LOW;
U1DBUF = dummyByte; // U1ACTIVE is asserted
while (U1ACTIVE);
// Wait for U1ACTIVE to be de-asserted (U1DBUF can be read)
rxBufferMaster[i] = U1DBUF;
SSN = HIGH;
}
mDataReceived = TRUE;
SWRA223A
Page 15 of 17
Design Note DN113
5
References
[1] CC1110Fx/CC1111Fx Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1
GHz RF Transceiver, and USB Controller (cc1110f32.pdf)
[2] CC2510Fx/CC2511Fx Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz
RF Transceiver, and USB Controller (cc2510f32.pdf)
[3] CC2430 A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee®
(cc2430.pdf)
[4] CC2530 A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee
Applications (cc2530.pdf)
SWRA223A
Page 16 of 17
Design Note DN113
6
6.1
General Information
Document History
Revision
SWRA223A
SWRA223
Date
2009.06.30
2008.08.16
Description/Changes
Updated for CC2530 and CC2531.
Initial release.
SWRA223A
Page 17 of 17
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