Texas Instruments | DN116 -- Clearing Module Interrupt Flags in LPW SoC Devices | Application notes | Texas Instruments DN116 -- Clearing Module Interrupt Flags in LPW SoC Devices Application notes

Texas Instruments DN116 -- Clearing Module Interrupt Flags in LPW SoC Devices Application notes
Design Note DN116
August 2009
Clearing Module Interrupt Flags in LPW SoC Devices
By Kristoffer Flores
Keywords
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Lost module interrupt flags
Write-0 register bits
Read-Modify-Write
Interrupt Handling
CC1110Fx
CC1111Fx
CC2510Fx
CC2511Fx
CC2430
CC2431
CC2530
Introduction
The traditional software method for
clearing module interrupt flags in TI’s
8051-based low power wireless Systemon-Chip (LPW SoC) devices can
unintentionally mask other interrupt flags.
Depending on the peripheral and the
application, these masked or missing
module interrupts can lead to unexpected
system behavior. For example, in the
Direct Memory Access (DMA) controller, a
missing interrupt flag can freeze a channel
until a system restart reinitializes the
controller.
Lost interrupts can result from readmodify-write (RMW) operations to clear
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older interrupt flags in the same module
flag register. Examples of these traditional
RMW operations to clear interrupt flags
can be found in datasheets and sample
code. This design note describes how
module interrupt flags can be lost when
using these operations and recommends
alternative code that takes advantage of
the Write-0 design of the module interrupt
flag bits.
Although this note assumes a working
knowledge of interrupt programming, a
brief overview of interrupt flags prefaces
the issue of lost module interrupt flags and
its avoidance.
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Design Note DN116
August 2009
Table of Contents
KEYWORDS.............................................................................................................................. 1
1
INTRODUCTION............................................................................................................. 1
2
ABBREVIATIONS........................................................................................................... 2
3
CPU AND MODULE INTERRUPT FLAGS .................................................................... 3
4
READ-MODIFY-WRITE OPERATIONS AND LOST MODULE INTERRUPT FLAGS.. 3
5
WRITE-0 REGISTERS.................................................................................................... 5
6
SUMMARY...................................................................................................................... 6
7
REFERENCES................................................................................................................ 7
8
GENERAL INFORMATION ............................................................................................ 8
8.1
DOCUMENT HISTORY.................................................................................................. 8
2
Abbreviations
CPU
DMA
ISR
RMW
SoC
Central Processing Unit
Direct Memory Access
Interrupt Service Routine
Read Modify Write
System On Chip
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Design Note DN116
August 2009
3
CPU and Module Interrupt Flags
For most modules found in TI’s LPW SoC devices, the hardware asserts, or sets to 1, two
flags when an interrupt condition occurs: a CPU interrupt flag and a more descriptive flag in a
module-specific register. The CPU interrupt flag tells the CPU which module has an interrupt
to service while the flag in the module register gives an indication of what event occurred.
For example, when using the DMA controller and a DMA channel reaches its transfer count,
both the DMAIF bit in the IRCON CPU flag register and a bit in the DMAIRQ register are
asserted. DMAIF tells the CPU to call the DMA’s interrupt service routine (ISR). The bit
asserted in DMAIRQ corresponds to the channel that triggered the transfer complete
interrupt, i.e. channel 0’s flag is 0x01, channel 1’s flag is 0x02, and so on. The ISR reads the
value of DMAIRQ to determine which DMA channel reached its transfer count. The SoC
datasheets ([1], [2], [3], and [4]) each contain a list of all the CPU interrupt flags as well as the
module-specific interrupt flags and their descriptions.
Unless the flags are cleared by hardware, both the CPU interrupt flag and the flag in the
module interrupt register must be cleared, or set to 0, during a module’s ISR. If an ISR
completes without clearing the CPU interrupt flag, the CPU will call the ISR again after
returning to the interrupted process, which is usually the main program loop. Clearing a
module interrupt flag prevents the ISR from interpreting old flags as new interrupts on the
next ISR call.
4
Read-modify-write Operations and Lost Module Interrupt Flags
Depending on the code used to clear a module interrupt flag, it is possible to accidentally
mask an incoming interrupt. Consider the C code below for a typical DMA ISR for a system
using two DMA channels for single block transfers. The ISR uses DMAIRQ to determine
which channel has an interrupt, clears the flag in DMAIRQ, and rearms the channel:
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#pragma vector = DMA_VECTOR
__interrupt void dma_irq (void)
{
EA = 0;
// Disable all other interrupts
DMAIF = 0;
// Clear the main CPU DMA interrupt flag
if (DMAIRQ & 0x01)
{
DMAIRQ &= ~0x01;
// Check if DMA ch. 0 transfer complete
// Clear channel 0 interrupt flag
// Any other desired actions before rearming the channel.
// e.g. increment counter, toggle LED, set case variable
// for program loop
DMAARM |= 0x01;
// Rearm the channel so it can be
// triggered again
}
else if (DMAIRQ & 0x02) // Check if ch. 1 transfer complete
{
DMAIRQ &= ~0x02;
// Clear channel 1 interrupt flag
// Any other desired actions before rearming the channel.
// e.g. increment counter, toggle LED, set case variable
// for program loop
DMAARM |= 0x02;
}
}
EA = 1;
// Rearm the channel so it can be
// triggered again
// Re-enable interrupts
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Design Note DN116
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The line DMAIF = 0 performs a bit-clear on the DMA controller’s CPU interrupt flag in the
IRCON register. A bit-clear has no effect on the other bits in the same register. This bit-clear
operation is possible because IRCON is bit-addressable. In the 8051-based LPW SoC’s, all
of the CPU interrupt flag registers are bit-addressable except for the S1CON register. S1CON
contains two identical copies of the general RF interrupt flag RFIF, and the other bits of the
register are unused.
DMAIRQ, as with most module registers, is not bit-addressable. The lines DMAIRQ &=
~0x01 and DMAIRQ &= ~0x02 are the statements to clear the module interrupt flags. A
general form of these statements is RegisterName &= ~FlagBit, an instruction intended
to clear FlagBit while leaving the remaining bits in RegisterName unaffected. The 8051 CPU
executes this instruction as a bit-wise AND between a direct data register, RegisterName,
and an immediate data byte, ~FlagBit, and stores the result back into RegisterName. The
compiler-generated assembly instruction for the statement is ANL RegisterName,
#(~FlagBit) and requires 4 clock cycles.
The possibility of losing interrupt flags arises because this instruction requires a read-modifywrite operation. The CPU reads the value from RegisterName, the necessary operations are
performed with the read value, and the computed value is written back to RegisterName.
Suppose DMAIRQ is initially 0x01 due to a channel 0 interrupt and the example DMA ISR has
been called. The ISR finds the channel 0 flag in DMAIRQ and executes DMAIRQ &= ~0x01
to clear the flag. In executing this instruction, the CPU first reads the value of DMAIRQ, or
0x01. A bit-wise AND is then performed between this read value and 0xFE (i.e. ~0x01),
resulting in 0x00. Finally, the CPU writes 0x00 back to the DMAIRQ register.
Suppose another channel, DMA channel 1, reaches its transfer count in the time between the
read and write in the RMW operation above. DMAIF is reasserted and the channel 1 interrupt
bit in DMAIRQ is asserted by hardware so that the physical value of DMAIRQ is 0x03.
However, the CPU is performing operations on the previously read value of DMAIRQ, 0x01.
The CPU calculates 0x01 & 0xFE = 0x00, and writes 0x00 to DMAIRQ, clearing the
interrupt flag for DMA channel 1. The ISR continues and completes with no apparent errors.
Figure 1 illustrates this sequence by showing the operations of the CPU and the physical
contents of the register.
Time
CPU
Physical Contents
of DMAIRQ
Read: DMAIRQ register = 0x01
Modify: 0x01 & 0xFE = 0x00
Write: 0x00 to DMAIRQ register
0x01
0x01
0x01
0x01
0x03 Å DMA Ch. 1 interrupt flag set
0x03
0x03
0x03
0x03
0x03
0x00 Å Ch. 1 flag cleared
0x00
0x00
Figure 1. Timing diagram showing a missed interrupt flag on DMA channel 1 due to the
instruction, DMAIRQ &= ~0x01, to clear the DMA channel 0 interrupt flag.
Continuing the above scenario, the CPU calls the DMA ISR again (since DMAIF = 1)
immediately after the previous ISR execution completes. This time, DMAIRQ is 0x00 and both
if-statements fail. DMA channel 1 is not rearmed and will not process new transfers when
triggered. If channel 1 is not rearmed anywhere else in the program code, the channel
remains idle until the DMA initialization code (which arms the channels) executes again due
to a system reset or fresh power-up. In single transfer modes, a DMA channel must be
rearmed after each completed transfer count before it can be triggered again to execute other
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Design Note DN116
August 2009
transfers. Refer to the “DMA Controller” section in the SoC datasheets ([1], [2], [3], and [4]) for
more detailed information about the DMA controller.
Imagine another application that relies on Port 0 input interrupts: five logic-level signals from
sensors and a power supply. Like the DMA, Port 0 has a CPU interrupt flag, P0IF, and a
module flag register, P0IFG, where each bit of P0IFG corresponds to an interrupt flag for a
pin. While P0IF is a flag bit in the bit-addressable IRCON register, the module register P0IFG
is not bit-addressable. If the timing between interrupt-triggering edges on the port pins fall just
right, clearing an interrupt flag bit using P0IFG &= ~FlagBit can lead to lost interrupts and
erroneous system operation.
5
Write-0 Registers
Fortunately, a quick modification to existing code can prevent missing interrupt flags. In TI’s
8051-based LPW SoC devices, all module interrupt flags are Write-0 bits, or W0 as listed in
the datasheets. Write-0 bits cannot be set to 1 by software; that is, writing a 1 into a Write-0
bit has no effect on the bit’s value. However, a Write-0 bit that has been set to 1 by hardware
due to an interrupt can be cleared by writing a 0 to the bit. Figure 2 shows a simplified model
of a Write-0 bit consisting of a D flip-flop with a feedback AND gate between the data to be
written and the current bit value, Q. An interrupt event changes the bit value to 1 via the flipflop’s Preset pin. Writing a 0 to the input AND gate will clear the bit value to 0. Writing a 1 to
the input AND gate will maintain whatever value is already in the flip-flop.
Figure 2. Simplified Write-0 Bit Model
The solution to prevent missing interrupts takes advantage of the Write-0 bit behavior. For the
DMA example, instead of using DMAIRQ &= ~0x01 and DMAIRQ &= ~0x02, the ISR should
use DMAIRQ = ~0x01 and DMAIRQ = ~0x02, respectively. These instructions will clear the
desired bit with a 0 and write 1s to the other bits to preserve the physical register values. In a
general form, for a module interrupt flag register with all Write-0 bits, replace RegisterName
&= ~FlagBit with RegisterName = ~FlagBit.
The compiler-generated assembly instruction for the new statement is a memory move
operation: MOV RegisterName, #(~FlagBit). Though the operation still requires 3 clock
cycles, it carries no risk of inadvertently clearing new interrupt flag bits.
Some Write-0 interrupt flag bits share a register with non-Write-0 bits. For example, the upper
four bits of the T1CTL register are Write-0 interrupt flags for Timer 1 while the lower four bits
of the register control the timer settings. To clear a flag, use the following code:
T1CTL = (~FlagBit & 0xF0) | (T1CTL & 0x0F);
This will preserve the values for the lower four bits, write a 0 to the flag bit to be cleared, and
write 1s to the remaining flag bits. Again, the 1s written to the other Write-0 flag bits pass the
existing values in the T1CTL register. This is a safer approach than using T1CTL &=
~FlagBit.
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Design Note DN116
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6
Summary
To avoid losing module interrupt flags, take advantage of the Write-0 design of the module
interrupt flag bits. Replace instructions that require read-modify-write operations with
instructions that write 1s to the flags not being cleared. Often, this is as simple as removing a
single symbol, &, to change the read-modify-write operation RegisterName &= ~FlagBit
to RegisterName = ~FlagBit.
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Design Note DN116
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7
References
[1]
CC1110Fx/CC1111Fx Datasheet (SWRS033)
[2]
CC2510Fx/CC2511Fx Datasheet (SWRS055)
[3]
CC2430 Datasheet (SWRS036)
[4]
CC253x User Guide (SWRU191)
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Design Note DN116
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8
8.1
General Information
Document History
Revision
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Date
2009.08.04
Description/Changes
Initial release.
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