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Texas Instruments CC430 Family (Rev. E) User guides
ECCN 5E002 TSPA - Technology / Software Publicly Available.
CC430 Family
User's Guide
Literature Number: SLAU259E
May 2009 – Revised January 2013
ECCN 5E002 TSPA - Technology / Software Publicly Available.
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Contents
...................................................................................................................................... 33
System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ...................... 35
1.1
System Control Module (SYS) Introduction ............................................................................ 36
1.2
System Reset and Initialization .......................................................................................... 36
1.2.1 Device Initial Conditions After System Reset ................................................................. 38
1.3
Interrupts .................................................................................................................... 38
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 39
1.3.2 SNMI Timing ...................................................................................................... 40
1.3.3 Maskable Interrupts .............................................................................................. 41
1.3.4 Interrupt Processing .............................................................................................. 41
1.3.5 Interrupt Nesting .................................................................................................. 42
1.3.6 Interrupt Vectors .................................................................................................. 42
1.3.7 SYS Interrupt Vector Generators ............................................................................... 43
1.4
Operating Modes .......................................................................................................... 44
1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4 ............................................ 47
1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 47
1.4.3 Extended Time in Low-Power Modes .......................................................................... 48
1.5
Principles for Low-Power Applications .................................................................................. 50
1.6
Connection of Unused Pins .............................................................................................. 50
1.7
Reset Pin (RST/NMI) Configuration ..................................................................................... 51
1.8
Configuring JTAG pins .................................................................................................... 51
1.9
Boot Code .................................................................................................................. 51
1.10 Bootstrap Loader (BSL) .................................................................................................. 51
1.11 Memory Map – Uses and Abilities ...................................................................................... 53
1.11.1 Vacant Memory Space ......................................................................................... 53
1.11.2 JTAG Lock Mechanism via the Electronic Fuse ............................................................. 53
1.12 JTAG Mailbox (JMB) System ............................................................................................ 54
1.12.1 JMB Configuration ............................................................................................... 54
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox ................................................................ 54
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox ...................................................................... 54
1.12.4 JMB NMI Usage ................................................................................................. 55
1.13 Device Descriptor Table .................................................................................................. 55
1.13.1 Identifying Device Type ......................................................................................... 56
1.13.2 TLV Descriptors ................................................................................................. 57
1.13.3 Peripheral Discovery Descriptor ............................................................................... 58
1.13.4 CRC Computation ............................................................................................... 62
1.13.5 Calibration Values ............................................................................................... 63
1.14 SFR Registers ............................................................................................................. 65
1.14.1 SFRIE1 Register ................................................................................................. 66
1.14.2 SFRIFG1 Register ............................................................................................... 67
1.14.3 SFRRPCR Register ............................................................................................. 69
1.15 SYS Registers ............................................................................................................. 70
1.15.1 SYSCTL Register ................................................................................................ 71
1.15.2 SYSBSLC Register .............................................................................................. 72
1.15.3 SYSJMBC Register ............................................................................................. 73
Preface
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1.15.4
1.15.5
1.15.6
1.15.7
1.15.8
1.15.9
1.15.10
1.15.11
2
2.3
Power Management Module (PMM) Introduction ..................................................................... 81
PMM Operation ............................................................................................................ 83
2.2.1 VCORE and the Regulator ......................................................................................... 83
2.2.2 Supply Voltage Supervisor and Monitor ....................................................................... 83
2.2.3 Supply Voltage Supervisor and Monitor - Power-Up ........................................................ 89
2.2.4 Increasing VCORE to Support Higher MCLK Frequencies ..................................................... 89
2.2.5 Decreasing VCORE for Power Optimization ..................................................................... 91
2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................. 91
2.2.7 LPM3.5 and LPM4.5 ............................................................................................. 91
2.2.8 Brownout Reset (BOR), Software BOR, Software POR ..................................................... 91
2.2.9 SVS and SVM Performance Modes and Wakeup Times ................................................... 92
2.2.10 PMM Interrupts .................................................................................................. 95
2.2.11 Port I/O Control .................................................................................................. 95
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional) ...................................................... 95
PMM Registers ............................................................................................................ 96
2.3.1 PMMCTL0 Register .............................................................................................. 97
2.3.2 PMMCTL1 Register .............................................................................................. 98
2.3.3 SVSMHCTL Register ............................................................................................ 99
2.3.4 SVSMLCTL Register ........................................................................................... 100
2.3.5 SVSMIO Register ............................................................................................... 101
2.3.6 PMMIFG Register ............................................................................................... 102
2.3.7 PMMRIE Register ............................................................................................... 104
2.3.8 PM5CTL0 Register ............................................................................................. 105
Unified Clock System (UCS)
3.1
3.2
3.3
3.4
4
74
74
75
75
76
77
78
79
Power Management Module and Supply Voltage Supervisor ................................................... 80
2.1
2.2
3
SYSJMBI0 Register .............................................................................................
SYSJMBI1 Register .............................................................................................
SYSJMBO0 Register ............................................................................................
SYSJMBO1 Register ............................................................................................
SYSUNIV Register ..............................................................................................
SYSSNIV Register ..............................................................................................
SYSRSTIV Register ...........................................................................................
SYSBERRIV Register .........................................................................................
.............................................................................................. 106
Unified Clock System (UCS) Introduction ............................................................................
UCS Operation ...........................................................................................................
3.2.1 UCS Module Features for Low-Power Applications ........................................................
3.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ...............................................
3.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) .........................................
3.2.4 XT1 Oscillator ...................................................................................................
3.2.5 RF XT2 Oscillator ...............................................................................................
3.2.6 Digitally-Controlled Oscillator (DCO) .........................................................................
3.2.7 Frequency Locked Loop (FLL) ................................................................................
3.2.8 DCO Modulator ..................................................................................................
3.2.9 Disabling FLL Hardware and Modulator .....................................................................
3.2.10 FLL Operation From Low-Power Modes ....................................................................
3.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules ...............................
3.2.12 UCS Module Fail-Safe Operation ............................................................................
3.2.13 Synchronization of Clock Signals ............................................................................
Module Oscillator (MODOSC) ..........................................................................................
3.3.1 MODOSC Operation ............................................................................................
UCS Module Registers ..................................................................................................
3.4.1 UCSCTL0 Register .............................................................................................
3.4.2 UCSCTL1 Register .............................................................................................
Contents
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109
109
110
110
111
111
111
112
113
113
113
115
118
119
119
120
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3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
4
4.4
4.5
4.6
MSP430X CPU (CPUX) Introduction ..................................................................................
Interrupts ..................................................................................................................
CPU Registers ............................................................................................................
4.3.1 Program Counter (PC) .........................................................................................
4.3.2 Stack Pointer (SP) ..............................................................................................
4.3.3 Status Register (SR) ............................................................................................
4.3.4 Constant Generator Registers (CG1 and CG2) .............................................................
4.3.5 General-Purpose Registers (R4 –R15) ......................................................................
Addressing Modes .......................................................................................................
4.4.1 Register Mode ...................................................................................................
4.4.2 Indexed Mode ...................................................................................................
4.4.3 Symbolic Mode ..................................................................................................
4.4.4 Absolute Mode ..................................................................................................
4.4.5 Indirect Register Mode .........................................................................................
4.4.6 Indirect Autoincrement Mode ..................................................................................
4.4.7 Immediate Mode ................................................................................................
MSP430 and MSP430X Instructions ..................................................................................
4.5.1 MSP430 Instructions ............................................................................................
4.5.2 MSP430X Extended Instructions ..............................................................................
Instruction Set Description ..............................................................................................
4.6.1 Extended Instruction Binary Descriptions ....................................................................
4.6.2 MSP430 Instructions ............................................................................................
4.6.3 Extended Instructions ..........................................................................................
4.6.4 Address Instructions ............................................................................................
Flash Memory Controller
5.1
5.2
5.3
5.4
6
123
124
125
126
128
129
130
131
CPUX .............................................................................................................................. 132
4.1
4.2
4.3
5
UCSCTL2 Register .............................................................................................
UCSCTL3 Register .............................................................................................
UCSCTL4 Register .............................................................................................
UCSCTL5 Register .............................................................................................
UCSCTL6 Register .............................................................................................
UCSCTL7 Register .............................................................................................
UCSCTL8 Register .............................................................................................
UCSCTL9 Register ............................................................................................
.................................................................................................. 288
Flash Memory Introduction .............................................................................................
Flash Memory Segmentation ...........................................................................................
5.2.1 Segment A .......................................................................................................
Flash Memory Operation ................................................................................................
5.3.1 Erasing Flash Memory .........................................................................................
5.3.2 Writing Flash Memory ..........................................................................................
5.3.3 Flash Memory Access During Write or Erase ...............................................................
5.3.4 Stopping Write or Erase Cycle ................................................................................
5.3.5 Checking Flash Memory .......................................................................................
5.3.6 Configuring and Accessing the Flash Memory Controller .................................................
5.3.7 Flash Memory Controller Interrupts ...........................................................................
5.3.8 Programming Flash Memory Devices ........................................................................
FCTL Registers ...........................................................................................................
5.4.1 FCTL1 Register .................................................................................................
5.4.2 FCTL3 Register .................................................................................................
5.4.3 FCTL4 Register .................................................................................................
5.4.4 SFRIE1 Register ................................................................................................
RAM Controller (RAMCTL)
6.1
133
135
136
136
136
138
139
140
142
143
144
148
153
155
156
157
159
159
164
175
176
178
230
273
289
290
291
292
292
296
303
304
304
305
305
306
307
308
309
310
311
................................................................................................ 312
.............................................................................. 313
RAM Controller (RAMCTL) Introduction
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6.2
6.3
7
Direct Memory Access (DMA) Controller Module
7.1
7.2
7.3
8
................................................................. 316
Direct Memory Access (DMA) Introduction ...........................................................................
DMA Operation ...........................................................................................................
7.2.1 DMA Addressing Modes .......................................................................................
7.2.2 DMA Transfer Modes ...........................................................................................
7.2.3 Initiating DMA Transfers .......................................................................................
7.2.4 Halting Executing Instructions for DMA Transfers ..........................................................
7.2.5 Stopping DMA Transfers .......................................................................................
7.2.6 DMA Channel Priorities ........................................................................................
7.2.7 DMA Transfer Cycle Time .....................................................................................
7.2.8 Using DMA With System Interrupts ...........................................................................
7.2.9 DMA Controller Interrupts ......................................................................................
7.2.10 Using the USCI_B I2C Module With the DMA Controller .................................................
7.2.11 Using ADC12 With the DMA Controller .....................................................................
7.2.12 Using DAC12 With the DMA Controller .....................................................................
DMA Registers ...........................................................................................................
7.3.1 DMACTL0 Register .............................................................................................
7.3.2 DMACTL1 Register .............................................................................................
7.3.3 DMACTL2 Register .............................................................................................
7.3.4 DMACTL3 Register .............................................................................................
7.3.5 DMACTL4 Register .............................................................................................
7.3.6 DMAxCTL Register .............................................................................................
7.3.7 DMAxSA Register ...............................................................................................
7.3.8 DMAxDA Register ...............................................................................................
7.3.9 DMAxSZ Register ...............................................................................................
7.3.10 DMAIV Register ................................................................................................
317
319
319
319
325
325
326
326
327
327
327
329
329
329
330
332
333
334
335
336
337
339
340
341
342
............................................................................................................ 343
Digital I/O Introduction ................................................................................................... 344
Digital I/O Operation ..................................................................................................... 345
8.2.1 Input Registers (PxIN) .......................................................................................... 345
8.2.2 Output Registers (PxOUT) ..................................................................................... 345
8.2.3 Direction Registers (PxDIR) ................................................................................... 345
8.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 345
8.2.5 Output Drive Strength Registers (PxDS) ..................................................................... 346
8.2.6 Function Select Registers (PxSEL) ........................................................................... 346
8.2.7 Port Interrupts ................................................................................................... 346
8.2.8 Configuring Unused Port Pins ................................................................................. 348
I/O Configuration and LPMx.5 Low-Power Modes ................................................................... 348
Digital I/O Registers ..................................................................................................... 350
8.4.1 P1IV Register .................................................................................................... 356
8.4.2 P2IV Register .................................................................................................... 357
8.4.3 P1IES Register .................................................................................................. 358
8.4.4 P1IE Register .................................................................................................... 358
8.4.5 P1IFG Register .................................................................................................. 358
8.4.6 P2IES Register .................................................................................................. 359
8.4.7 P2IE Register .................................................................................................... 359
8.4.8 P2IFG Register .................................................................................................. 359
8.4.9 PxIN Register .................................................................................................... 360
8.4.10 PxOUT Register ................................................................................................ 360
8.4.11 PxDIR Register ................................................................................................. 360
Digital I/O Module
8.1
8.2
8.3
8.4
6
RAMCTL Operation ...................................................................................................... 313
RAMCTL Registers ...................................................................................................... 314
6.3.1 RCCTL0 Register ............................................................................................... 315
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8.4.12 PxREN Register ................................................................................................ 361
8.4.13 PxDS Register .................................................................................................. 361
8.4.14 PxSEL Register ................................................................................................ 361
9
Port Mapping Controller
9.1
9.2
9.3
10
Cyclic Redundancy Check (CRC) Module
10.1
10.2
10.3
10.4
11
11.3
12.3
368
368
369
369
370
372
373
373
374
374
.............................................................................................................. 375
AES Accelerator Introduction ...........................................................................................
AES Accelerator Operation .............................................................................................
11.2.1 Encryption .......................................................................................................
11.2.2 Decryption ......................................................................................................
11.2.3 Decryption Key Generation ...................................................................................
11.2.4 Using the AES Accelerator With Low-Power Modes ......................................................
11.2.5 AES Accelerator Interrupts ...................................................................................
11.2.6 Implementing Block Cipher Modes ..........................................................................
AES_ACCEL Registers .................................................................................................
11.3.1 AESACTL0 Register ...........................................................................................
11.3.2 AESACTL1 Register ...........................................................................................
11.3.3 AESASTAT Register ..........................................................................................
11.3.4 AESAKEY Register ............................................................................................
11.3.5 AESADIN Register .............................................................................................
11.3.6 AESADOUT Register ..........................................................................................
11.3.7 AESAXDIN Register ...........................................................................................
11.3.8 AESAXIN Register .............................................................................................
Watchdog Timer (WDT_A)
12.1
12.2
363
363
363
363
365
366
366
366
........................................................................... 367
Cyclic Redundancy Check (CRC) Module Introduction .............................................................
CRC Standard and Bit Order ...........................................................................................
CRC Checksum Generation ............................................................................................
10.3.1 CRC Implementation ..........................................................................................
10.3.2 Assembler Examples ..........................................................................................
CRC Registers ...........................................................................................................
10.4.1 CRCDI Register ................................................................................................
10.4.2 CRCDIRB Register ............................................................................................
10.4.3 CRCINIRES Register ..........................................................................................
10.4.4 CRCRESR Register ...........................................................................................
AES Accelerator
11.1
11.2
12
................................................................................................... 362
Port Mapping Controller Introduction ..................................................................................
Port Mapping Controller Operation ....................................................................................
9.2.1 Access ............................................................................................................
9.2.2 Mapping ..........................................................................................................
Port Mapping Controller Registers .....................................................................................
9.3.1 PMAPKEYID Register ..........................................................................................
9.3.2 PMAPCTL Register .............................................................................................
9.3.3 PxMAPy Register ...............................................................................................
376
377
378
379
380
381
381
381
382
383
384
385
386
387
387
388
388
................................................................................................. 389
WDT_A Introduction .....................................................................................................
WDT_A Operation .......................................................................................................
12.2.1 Watchdog Timer Counter (WDTCNT) .......................................................................
12.2.2 Watchdog Mode ................................................................................................
12.2.3 Interval Timer Mode ...........................................................................................
12.2.4 Watchdog Timer Interrupts ...................................................................................
12.2.5 Clock Fail-Safe Feature .......................................................................................
12.2.6 Operation in Low-Power Modes .............................................................................
12.2.7 Software Examples ............................................................................................
WDT_A Registers ........................................................................................................
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............................................................................................. 395
Timer_A .......................................................................................................................... 396
13.1 Timer_A Introduction .................................................................................................... 397
13.2 Timer_A Operation ....................................................................................................... 399
13.2.1 16-Bit Timer Counter .......................................................................................... 399
13.2.2 Starting the Timer .............................................................................................. 399
13.2.3 Timer Mode Control ........................................................................................... 400
13.2.4 Capture/Compare Blocks ..................................................................................... 403
13.2.5 Output Unit ...................................................................................................... 405
13.2.6 Timer_A Interrupts ............................................................................................. 409
13.3 Timer_A Registers ....................................................................................................... 411
13.3.1 TAxCTL Register ............................................................................................... 412
13.3.2 TAxR Register .................................................................................................. 413
13.3.3 TAxCCTLn Register ........................................................................................... 414
13.3.4 TAxCCRn Register ............................................................................................ 416
13.3.5 TAxIV Register ................................................................................................. 416
13.3.6 TAxEX0 Register ............................................................................................... 417
Real-Time Clock (RTC) Overview ....................................................................................... 418
14.1 RTC Overview ............................................................................................................ 418
Real-Time Clock (RTC_A) .................................................................................................. 419
15.1 RTC_A Introduction ...................................................................................................... 420
15.2 RTC_A Operation ........................................................................................................ 422
15.2.1 Counter Mode .................................................................................................. 422
15.2.2 Calendar Mode ................................................................................................. 422
15.2.3 Real-Time Clock Interrupts ................................................................................... 424
15.2.4 Real-Time Clock Calibration .................................................................................. 426
15.3 RTC_A Registers ........................................................................................................ 428
15.3.1 RTCCTL0 Register ............................................................................................ 430
15.3.2 RTCCTL1 Register ............................................................................................ 431
15.3.3 RTCCTL2 Register ............................................................................................ 432
15.3.4 RTCCTL3 Register ............................................................................................ 432
15.3.5 RTCNT1 Register .............................................................................................. 433
15.3.6 RTCNT2 Register .............................................................................................. 433
15.3.7 RTCNT3 Register .............................................................................................. 433
15.3.8 RTCNT4 Register .............................................................................................. 433
15.3.9 RTCSEC Register – Calendar Mode With Hexadecimal Format ........................................ 434
15.3.10 RTCSEC Register – Calendar Mode With BCD Format ................................................ 434
15.3.11 RTCMIN Register – Calendar Mode With Hexadecimal Format ....................................... 435
15.3.12 RTCMIN Register – Calendar Mode With BCD Format ................................................. 435
15.3.13 RTCHOUR Register – Calendar Mode With Hexadecimal Format .................................... 436
15.3.14 RTCHOUR Register – Calendar Mode With BCD Format .............................................. 436
15.3.15 RTCDOW Register – Calendar Mode ..................................................................... 437
15.3.16 RTCDAY Register – Calendar Mode With Hexadecimal Format ...................................... 437
15.3.17 RTCDAY Register – Calendar Mode With BCD Format ................................................ 437
15.3.18 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 438
15.3.19 RTCMON Register – Calendar Mode With BCD Format ................................................ 438
15.3.20 RTCYEARL Register – Calendar Mode With Hexadecimal Format ................................... 439
15.3.21 RTCYEARL Register – Calendar Mode With BCD Format ............................................. 439
15.3.22 RTCYEARH Register – Calendar Mode With Hexadecimal Format ................................... 440
15.3.23 RTCYEARH Register – Calendar Mode With BCD Format ............................................. 440
15.3.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format ..................................... 441
15.3.25 RTCAMIN Register – Calendar Mode With BCD Format ............................................... 441
15.3.26 RTCAHOUR Register – Calendar Mode With Hexadecimal Format .................................. 442
12.3.1 WDTCTL Register
13
14
15
8
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15.3.27
15.3.28
15.3.29
15.3.30
15.3.31
15.3.32
15.3.33
15.3.34
15.3.35
16
RTCAHOUR Register – Calendar Mode With BCD Format ............................................
RTCADOW Register .........................................................................................
RTCADAY Register – Calendar Mode With Hexadecimal Format .....................................
RTCADAY Register – Calendar Mode With BCD Format ..............................................
RTCPS0CTL Register .......................................................................................
RTCPS1CTL Register .......................................................................................
RT0PS Register ..............................................................................................
RT1PS Register ..............................................................................................
RTCIV Register ...............................................................................................
442
443
443
443
444
445
446
446
446
Real-Time Clock D (RTC_D) ............................................................................................... 447
16.1
16.2
16.3
Real-Time Clock RTC_D Introduction .................................................................................
RTC_D Operation ........................................................................................................
16.2.1 Counter Mode ..................................................................................................
16.2.2 Calendar Mode .................................................................................................
16.2.3 Real-Time Clock Interrupts ...................................................................................
16.2.4 Real-Time Clock Calibration ..................................................................................
16.2.5 Real-Time Clock Operation in LPMx.5 Low-Power Mode ................................................
RTC_D Registers ........................................................................................................
16.3.1 RTCCTL0 Register ............................................................................................
16.3.2 RTCCTL1 Register ............................................................................................
16.3.3 RTCCTL2 Register ............................................................................................
16.3.4 RTCCTL3 Register ............................................................................................
16.3.5 RTCNT1 Register ..............................................................................................
16.3.6 RTCNT2 Register ..............................................................................................
16.3.7 RTCNT3 Register ..............................................................................................
16.3.8 RTCNT4 Register ..............................................................................................
16.3.9 RTCSEC Register – Hexadecimal Format .................................................................
16.3.10 RTCSEC Register – BCD Format ..........................................................................
16.3.11 RTCMIN Register – Hexadecimal Format ................................................................
16.3.12 RTCMIN Register – BCD Format ..........................................................................
16.3.13 RTCHOUR Register – Hexadecimal Format .............................................................
16.3.14 RTCHOUR Register – BCD Format .......................................................................
16.3.15 RTCDOW Register – Calendar Mode .....................................................................
16.3.16 RTCDAY Register – Hexadecimal Format ................................................................
16.3.17 RTCDAY Register – BCD Format ..........................................................................
16.3.18 RTCMON Register – Hexadecimal Format ...............................................................
16.3.19 RTCMON Register – BCD Format .........................................................................
16.3.20 RTCYEAR Register – Calendar Mode With Hexadecimal Format .....................................
16.3.21 RTCYEAR Register – Calendar Mode With BCD Format ..............................................
16.3.22 RTCAMIN Register – Hexadecimal Format ...............................................................
16.3.23 RTCAMIN Register – BCD Format .........................................................................
16.3.24 RTCAHOUR Register – Hexadecimal Format ............................................................
16.3.25 RTCAHOUR Register – BCD Format ......................................................................
16.3.26 RTCADOW Register .........................................................................................
16.3.27 RTCADAY Register – Hexadecimal Format ..............................................................
16.3.28 RTCADAY Register – BCD Format ........................................................................
16.3.29 RTCPS0CTL Register .......................................................................................
16.3.30 RTCPS1CTL Register .......................................................................................
16.3.31 RTCPS0 Register ............................................................................................
16.3.32 RTCPS1 Register ............................................................................................
16.3.33 RTCIV Register ...............................................................................................
16.3.34 BIN2BCD Register ...........................................................................................
16.3.35 BCD2BIN Register ...........................................................................................
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17
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10
....................................................................................
17.1 32-Bit Hardware Multiplier (MPY32) Introduction ....................................................................
17.2 MPY32 Operation ........................................................................................................
17.2.1 Operand Registers .............................................................................................
17.2.2 Result Registers ................................................................................................
17.2.3 Software Examples ............................................................................................
17.2.4 Fractional Numbers ............................................................................................
17.2.5 Putting It All Together .........................................................................................
17.2.6 Indirect Addressing of Result Registers .....................................................................
17.2.7 Using Interrupts ................................................................................................
17.2.8 Using DMA ......................................................................................................
17.3 MPY32 Registers ........................................................................................................
17.3.1 MPY32CTL0 Register .........................................................................................
REF ................................................................................................................................
18.1 REF Introduction .........................................................................................................
18.2 Principle of Operation ...................................................................................................
18.2.1 Low-Power Operation .........................................................................................
18.2.2 REFCTL .........................................................................................................
18.2.3 Reference System Requests .................................................................................
18.3 REF Registers ............................................................................................................
18.3.1 REFCTL0 Register (offset = 00h) [reset = 0080h] .........................................................
ADC10_A ........................................................................................................................
19.1 ADC10_A Introduction ...................................................................................................
19.2 ADC10_A Operation .....................................................................................................
19.2.1 10-Bit ADC Core ...............................................................................................
19.2.2 ADC10_A Inputs and Multiplexer ............................................................................
19.2.3 Voltage Reference Generator ................................................................................
19.2.4 Auto Power Down ..............................................................................................
19.2.5 Sample and Conversion Timing ..............................................................................
19.2.6 Conversion Result .............................................................................................
19.2.7 ADC10_A Conversion Modes ................................................................................
19.2.8 Window Comparator ...........................................................................................
19.2.9 Using the Integrated Temperature Sensor .................................................................
19.2.10 ADC10_A Grounding and Noise Considerations .........................................................
19.2.11 ADC10_A Interrupts ..........................................................................................
19.3 ADC10_A Registers .....................................................................................................
19.3.1 ADC10CTL0 Register .........................................................................................
19.3.2 ADC10CTL1 Register .........................................................................................
19.3.3 ADC10CTL2 Register .........................................................................................
19.3.4 ADC10MEM0 Register ........................................................................................
19.3.5 ADC10MEM0 Register, 2s-Complement Format ..........................................................
19.3.6 ADC10MCTL0 Register .......................................................................................
19.3.7 ADC10HI Register .............................................................................................
19.3.8 ADC10HI Register, 2s-Complement Format ...............................................................
19.3.9 ADC10LO Register ............................................................................................
19.3.10 ADC10LO Register, 2s-Complement Format .............................................................
19.3.11 ADC10IE Register ............................................................................................
19.3.12 ADC10IFG Register ..........................................................................................
19.3.13 ADC10IV Register ............................................................................................
ADC12_A ........................................................................................................................
20.1 ADC12_A Introduction ...................................................................................................
20.2 ADC12_A Operation .....................................................................................................
20.2.1 12-Bit ADC Core ...............................................................................................
32-Bit Hardware Multiplier (MPY32)
Contents
477
478
480
481
482
483
484
487
490
490
491
492
494
495
496
498
498
499
500
502
503
505
506
508
508
508
509
509
509
511
511
516
517
518
518
520
521
522
524
525
525
526
527
527
528
528
529
530
531
532
533
536
536
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20.3
21
22
20.2.2 ADC12_A Inputs and Multiplexer ............................................................................
20.2.3 Voltage Reference Generator ................................................................................
20.2.4 Auto Power Down ..............................................................................................
20.2.5 Sample and Conversion Timing ..............................................................................
20.2.6 Conversion Memory ...........................................................................................
20.2.7 ADC12_A Conversion Modes ................................................................................
20.2.8 Using the Integrated Temperature Sensor .................................................................
20.2.9 ADC12_A Grounding and Noise Considerations ..........................................................
20.2.10 ADC12_A Interrupts ..........................................................................................
ADC12_A Registers .....................................................................................................
20.3.1 ADC12CTL0 Register .........................................................................................
20.3.2 ADC12CTL1 Register .........................................................................................
20.3.3 ADC12CTL2 Register .........................................................................................
20.3.4 ADC12MEMx Register ........................................................................................
20.3.5 ADC12MCTLx Register .......................................................................................
20.3.6 ADC12IE Register .............................................................................................
20.3.7 ADC12IFG Register ...........................................................................................
20.3.8 ADC12IV Register .............................................................................................
536
537
538
538
540
540
546
547
548
550
552
554
555
556
557
558
560
562
.......................................................................................................................... 563
21.1 Comp_B Introduction .................................................................................................... 564
21.2 Comp_B Operation ...................................................................................................... 565
21.2.1 Comparator ..................................................................................................... 565
21.2.2 Analog Input Switches ......................................................................................... 565
21.2.3 Port Logic ....................................................................................................... 565
21.2.4 Input Short Switch ............................................................................................. 565
21.2.5 Output Filter .................................................................................................... 566
21.2.6 Reference Voltage Generator ................................................................................ 567
21.2.7 Comp_B, Port Disable Register CBPD ..................................................................... 568
21.2.8 Comp_B Interrupts ............................................................................................. 568
21.2.9 Comp_B Used to Measure Resistive Elements ............................................................ 568
21.3 Comp_B Registers ....................................................................................................... 570
21.3.1 CBCTL0 Register .............................................................................................. 571
21.3.2 CBCTL1 Register .............................................................................................. 572
21.3.3 CBCTL2 Register .............................................................................................. 574
21.3.4 CBCTL3 Register .............................................................................................. 575
21.3.5 CBINT Register ................................................................................................ 577
21.3.6 CBIV Register .................................................................................................. 578
Universal Serial Communication Interface – UART Mode ...................................................... 579
22.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 580
22.2 USCI Introduction – UART Mode ...................................................................................... 581
22.3 USCI Operation – UART Mode ........................................................................................ 583
22.3.1 USCI Initialization and Reset ................................................................................. 583
22.3.2 Character Format .............................................................................................. 583
22.3.3 Asynchronous Communication Format ..................................................................... 583
22.3.4 Automatic Baud-Rate Detection ............................................................................. 586
22.3.5 IrDA Encoding and Decoding ................................................................................ 587
22.3.6 Automatic Error Detection .................................................................................... 588
22.3.7 USCI Receive Enable ......................................................................................... 589
22.3.8 USCI Transmit Enable ........................................................................................ 589
22.3.9 UART Baud-Rate Generation ................................................................................ 590
22.3.10 Setting a Baud Rate .......................................................................................... 592
22.3.11 Transmit Bit Timing ........................................................................................... 592
22.3.12 Receive Bit Timing ........................................................................................... 593
Comp_B
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22.4
23
594
597
597
599
600
601
602
602
602
603
604
604
605
605
606
607
607
608
......................................................... 609
Universal Serial Communication Interface (USCI) Overview ....................................................... 610
USCI Introduction – SPI Mode ......................................................................................... 611
USCI Operation – SPI Mode ........................................................................................... 613
23.3.1 USCI Initialization and Reset ................................................................................. 613
23.3.2 Character Format .............................................................................................. 613
23.3.3 Master Mode .................................................................................................... 614
23.3.4 Slave Mode ..................................................................................................... 615
23.3.5 SPI Enable ...................................................................................................... 615
23.3.6 Serial Clock Control ........................................................................................... 616
23.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 616
23.3.8 SPI Interrupts ................................................................................................... 617
USCI_A SPI Mode Registers ........................................................................................... 618
23.4.1 UCAxCTL0 Register ........................................................................................... 619
23.4.2 UCAxCTL1 Register ........................................................................................... 620
23.4.3 UCAxBR0 Register ............................................................................................ 621
23.4.4 UCAxBR1 Register ............................................................................................ 621
23.4.5 UCAxMCTL Register .......................................................................................... 621
23.4.6 UCAxSTAT Register ........................................................................................... 622
23.4.7 UCAxRXBUF Register ........................................................................................ 623
23.4.8 UCAxTXBUF Register ......................................................................................... 623
23.4.9 UCAxIE Register ............................................................................................... 624
23.4.10 UCAxIFG Register ........................................................................................... 624
23.4.11 UCAxIV Register ............................................................................................. 625
USCI_B SPI Mode Registers ........................................................................................... 626
23.5.1 UCBxCTL0 Register ........................................................................................... 627
23.5.2 UCBxCTL1 Register ........................................................................................... 628
23.5.3 UCBxBR0 Register ............................................................................................ 629
23.5.4 UCBxBR1 Register ............................................................................................ 629
23.5.5 UCBxMCTL Register .......................................................................................... 629
23.5.6 UCBxSTAT Register ........................................................................................... 630
23.5.7 UCBxRXBUF Register ........................................................................................ 631
23.5.8 UCBxTXBUF Register ......................................................................................... 631
23.5.9 UCBxIE Register ............................................................................................... 632
23.5.10 UCBxIFG Register ........................................................................................... 632
Universal Serial Communication Interface – SPI Mode
23.1
23.2
23.3
23.4
23.5
12
22.3.13 Typical Baud Rates and Errors .............................................................................
22.3.14 Using the USCI Module in UART Mode With Low-Power Modes .....................................
22.3.15 USCI Interrupts ...............................................................................................
USCI_A UART Mode Registers ........................................................................................
22.4.1 UCAxCTL0 Register ...........................................................................................
22.4.2 UCAxCTL1 Register ...........................................................................................
22.4.3 UCAxBR0 Register ............................................................................................
22.4.4 UCAxBR1 Register ............................................................................................
22.4.5 UCAxMCTL Register ..........................................................................................
22.4.6 UCAxSTAT Register ...........................................................................................
22.4.7 UCAxRXBUF Register ........................................................................................
22.4.8 UCAxTXBUF Register .........................................................................................
22.4.9 UCAxIRTCTL Register ........................................................................................
22.4.10 UCAxIRRCTL Register ......................................................................................
22.4.11 UCAxABCTL Register .......................................................................................
22.4.12 UCAxIE Register .............................................................................................
22.4.13 UCAxIFG Register ...........................................................................................
22.4.14 UCAxIV Register .............................................................................................
Contents
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............................................................................................. 633
Universal Serial Communication Interface – I2C Mode .......................................................... 634
24.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 635
24.2 USCI Introduction – I2C Mode .......................................................................................... 636
24.3 USCI Operation – I2C Mode ............................................................................................ 637
24.3.1 USCI Initialization and Reset ................................................................................. 638
24.3.2 I2C Serial Data .................................................................................................. 638
24.3.3 I2C Addressing Modes ......................................................................................... 640
24.3.4 I2C Module Operating Modes ................................................................................. 641
24.3.5 I2C Clock Generation and Synchronization ................................................................. 652
24.3.6 Using the USCI Module in I2C Mode With Low-Power Modes ........................................... 653
24.3.7 USCI Interrupts in I2C Mode .................................................................................. 653
24.4 USCI_B I2C Mode Registers ........................................................................................... 656
24.4.1 UCBxCTL0 Register ........................................................................................... 657
24.4.2 UCBxCTL1 Register ........................................................................................... 658
24.4.3 UCBxBR0 Register ............................................................................................ 659
24.4.4 UCBxBR1 Register ............................................................................................ 659
24.4.5 UCBxSTAT Register ........................................................................................... 660
24.4.6 UCBxRXBUF Register ........................................................................................ 661
24.4.7 UCBxTXBUF Register ......................................................................................... 661
24.4.8 UCBxI2COA Register ......................................................................................... 662
24.4.9 UCBxI2CSA Register .......................................................................................... 662
24.4.10 UCBxIE Register ............................................................................................. 663
24.4.11 UCBxIFG Register ........................................................................................... 664
24.4.12 UCBxIV Register ............................................................................................. 665
CC1101-Based Radio Module (RF1A) .................................................................................. 666
25.1 Radio Module Introduction .............................................................................................. 667
25.2 Radio Interface Operation .............................................................................................. 668
25.2.1 Radio Interface ................................................................................................. 668
25.2.2 Radio Interface Interrupts ..................................................................................... 674
25.2.3 Radio Core Interrupts ......................................................................................... 674
25.2.4 Using Radio With Low-Power Modes ....................................................................... 675
25.2.5 Radio Interrupt Handling ...................................................................................... 675
25.2.6 Software Considerations ...................................................................................... 678
25.3 CC1101-Based Radio Core ............................................................................................. 680
25.3.1 Differences From CC1101 .................................................................................... 680
25.3.2 Instruction Set for CC1101-Based Radio Core ............................................................ 681
25.3.3 Radio-Core Operation ......................................................................................... 684
25.3.4 System Considerations and Guidelines ..................................................................... 705
25.3.5 Radio Core Registers ......................................................................................... 709
25.4 RF1A Registers .......................................................................................................... 732
25.4.1 RF1AIFCTL0 Register ......................................................................................... 734
25.4.2 RF1AIFCTL1 Register ......................................................................................... 735
25.4.3 RF1AIFERR Register .......................................................................................... 736
25.4.4 RF1AIFERRV Register ........................................................................................ 737
25.4.5 RF1AIFIV Register ............................................................................................. 737
25.4.6 RF1AIN Register ............................................................................................... 738
25.4.7 RF1AIFG Register ............................................................................................. 738
25.4.8 RF1AIES Register ............................................................................................. 739
25.4.9 RF1AIE Register ............................................................................................... 739
25.4.10 RF1AIV Register .............................................................................................. 740
LCD_B Controller ............................................................................................................. 741
26.1 LCD_B Controller Introduction ......................................................................................... 742
23.5.11 UCBxIV Register
24
25
26
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26.2
26.3
27
LCD_B Controller Operation ............................................................................................
26.2.1 LCD Memory ...................................................................................................
26.2.2 LCD Timing Generation .......................................................................................
26.2.3 Blanking the LCD ..............................................................................................
26.2.4 LCD Blinking ....................................................................................................
26.2.5 LCD_B Voltage And Bias Generation .......................................................................
26.2.6 LCD Outputs ....................................................................................................
26.2.7 LCD_B Interrupts ..............................................................................................
26.2.8 Static Mode .....................................................................................................
26.2.9 2-Mux Mode ....................................................................................................
26.2.10 3-Mux Mode ...................................................................................................
26.2.11 4-Mux Mode ...................................................................................................
LCD_B Registers .........................................................................................................
26.3.1 LCDBCTL0 Register ...........................................................................................
26.3.2 LCDBCTL1 Register ...........................................................................................
26.3.3 LCDBBLKCTL Register .......................................................................................
26.3.4 LCDBMEMCTL Register ......................................................................................
26.3.5 LCDBVCTL Register ..........................................................................................
26.3.6 LCDBPCTL0 Register .........................................................................................
26.3.7 LCDBPCTL1 Register .........................................................................................
26.3.8 LCDBPCTL2 Register .........................................................................................
26.3.9 LCDBPCTL3 Register .........................................................................................
26.3.10 LCDBCPCTL Register .......................................................................................
26.3.11 LCDBIV Register .............................................................................................
Embedded Emulation Module (EEM)
27.1
27.2
27.3
14
.................................................................................. 775
Embedded Emulation Module (EEM) Introduction ...................................................................
EEM Building Blocks ....................................................................................................
27.2.1 Triggers .........................................................................................................
27.2.2 Trigger Sequencer .............................................................................................
27.2.3 State Storage (Internal Trace Buffer) ........................................................................
27.2.4 Cycle Counter ..................................................................................................
27.2.5 Clock Control ...................................................................................................
EEM Configurations .....................................................................................................
Revision History
Contents
744
744
744
745
745
746
748
748
750
753
756
759
762
765
766
767
768
769
771
771
772
772
773
774
776
778
778
778
778
778
779
779
....................................................................................................................... 780
SLAU259E – May 2009 – Revised January 2013
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List of Figures
1-1.
BOR/POR/PUC Reset Circuit ............................................................................................ 37
1-2.
Interrupt Priority ............................................................................................................ 39
1-3.
NMIs With Reentrance Protection ....................................................................................... 40
1-4.
Interrupt Processing ....................................................................................................... 41
1-5.
Return From Interrupt ..................................................................................................... 42
1-6.
Operation Modes .......................................................................................................... 45
1-7.
Devices Descriptor Table ................................................................................................. 56
1-8.
SFRIE1 Register ........................................................................................................... 66
1-9.
SFRIFG1 Register ......................................................................................................... 67
1-10.
SFRRPCR Register ....................................................................................................... 69
1-11.
SYSCTL Register .......................................................................................................... 71
1-12.
SYSBSLC Register ........................................................................................................ 72
1-13.
SYSJMBC Register
1-14.
SYSJMBI0 Register ....................................................................................................... 74
1-15.
SYSJMBI1 Register ....................................................................................................... 74
1-16.
SYSJMBO0 Register ...................................................................................................... 75
1-17.
SYSJMBO1 Register ...................................................................................................... 75
1-18.
SYSUNIV Register ........................................................................................................ 76
1-19.
SYSSNIV Register
1-20.
SYSRSTIV Register ....................................................................................................... 78
1-21.
SYSBERRIV Register ..................................................................................................... 79
2-1.
System Frequency, Supply Voltage, and Core Voltage – See Device-Specific Data Sheet .................... 81
2-2.
PMM Block Diagram ...................................................................................................... 82
2-3.
Available SVMH Settings Versus VCORE Settings.................................................................... 85
2-4.
High-Side and Low-Side Voltage Failure and Resulting PMM Actions ............................................. 86
2-5.
High-Side SVS and SVM ................................................................................................. 87
2-6.
Low-Side SVS and SVM.................................................................................................. 88
2-7.
PMM Action at Device Power-Up
2-8.
Changing VCORE and SVML and SVSL Levels ........................................................................... 90
2-9.
PMMCTL0 Register ....................................................................................................... 97
2-10.
PMMCTL1 Register ....................................................................................................... 98
2-11.
SVSMHCTL Register
2-12.
2-13.
2-14.
2-15.
2-16.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
.......................................................................................................
........................................................................................................
.......................................................................................
.....................................................................................................
SVSMLCTL Register ....................................................................................................
SVSMIO Register ........................................................................................................
PMMIFG Register ........................................................................................................
PMMRIE Register ........................................................................................................
PM5CTL0 Register ......................................................................................................
UCS Block Diagram .....................................................................................................
Modulator Patterns .......................................................................................................
Module Request Clock System ........................................................................................
Oscillator Fault Logic ....................................................................................................
Switch MCLK from DCOCLK to XT1CLK .............................................................................
UCSCTL0 Register ......................................................................................................
UCSCTL1 Register ......................................................................................................
UCSCTL2 Register ......................................................................................................
UCSCTL3 Register ......................................................................................................
UCSCTL4 Register ......................................................................................................
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List of Figures
73
77
89
99
100
101
102
104
105
108
112
114
117
118
121
122
123
124
125
15
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3-11.
3-12.
3-13.
3-14.
3-15.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
4-39.
4-40.
4-41.
4-42.
4-43.
4-44.
16
......................................................................................................
UCSCTL6 Register ......................................................................................................
UCSCTL7 Register ......................................................................................................
UCSCTL8 Register ......................................................................................................
UCSCTL9 Register ......................................................................................................
MSP430X CPU Block Diagram ........................................................................................
PC Storage on the Stack for Interrupts ...............................................................................
Program Counter .........................................................................................................
PC Storage on the Stack for CALLA ..................................................................................
Stack Pointer .............................................................................................................
Stack Usage ..............................................................................................................
PUSHX.A Format on the Stack ........................................................................................
PUSH SP, POP SP Sequence .........................................................................................
SR Bits ....................................................................................................................
Register-Byte and Byte-Register Operation ..........................................................................
Register-Word Operation ...............................................................................................
Word-Register Operation ...............................................................................................
Register – Address-Word Operation ..................................................................................
Address-Word – Register Operation ..................................................................................
Indexed Mode in Lower 64 KB .........................................................................................
Indexed Mode in Upper Memory .......................................................................................
Overflow and Underflow for Indexed Mode ...........................................................................
Example for Indexed Mode .............................................................................................
Symbolic Mode Running in Lower 64 KB .............................................................................
Symbolic Mode Running in Upper Memory ..........................................................................
Overflow and Underflow for Symbolic Mode .........................................................................
MSP430 Double-Operand Instruction Format ........................................................................
MSP430 Single-Operand Instructions .................................................................................
Format of Conditional Jump Instructions..............................................................................
Extension Word for Register Modes ...................................................................................
Extension Word for Non-Register Modes .............................................................................
Example for Extended Register or Register Instruction .............................................................
Example for Extended Immediate or Indexed Instruction...........................................................
Extended Format I Instruction Formats ...............................................................................
20-Bit Addresses in Memory ...........................................................................................
Extended Format II Instruction Format ................................................................................
PUSHM and POPM Instruction Format ...............................................................................
RRCM, RRAM, RRUM, and RLAM Instruction Format .............................................................
BRA Instruction Format .................................................................................................
CALLA Instruction Format ..............................................................................................
Decrement Overlap ......................................................................................................
Stack After a RET Instruction ..........................................................................................
Destination Operand—Arithmetic Shift Left ..........................................................................
Destination Operand—Carry Left Shift ................................................................................
Rotate Right Arithmetically RRA.B and RRA.W .....................................................................
Rotate Right Through Carry RRC.B and RRC.W ....................................................................
Swap Bytes in Memory ..................................................................................................
Swap Bytes in a Register ...............................................................................................
Rotate Left Arithmetically—RLAM[.W] and RLAM.A ................................................................
UCSCTL5 Register
List of Figures
126
128
129
130
131
134
135
136
136
137
137
137
137
138
140
140
141
141
142
144
145
146
147
149
150
151
159
160
161
164
164
165
166
167
167
168
169
169
169
169
195
214
216
217
218
219
226
226
253
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4-45.
Destination Operand-Arithmetic Shift Left ............................................................................ 254
4-46.
Destination Operand-Carry Left Shift .................................................................................. 255
4-47.
Rotate Right Arithmetically RRAM[.W] and RRAM.A
4-48.
Rotate Right Arithmetically RRAX(.B,.A) – Register Mode ......................................................... 258
4-49.
Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode ................................................... 258
4-50.
Rotate Right Through Carry RRCM[.W] and RRCM.A .............................................................. 260
4-51.
Rotate Right Through Carry RRCX(.B,.A) – Register Mode
4-52.
Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
4-59.
4-60.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
6-1.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
...............................................................
.......................................................
.................................................
Rotate Right Unsigned RRUM[.W] and RRUM.A ....................................................................
Rotate Right Unsigned RRUX(.B,.A) – Register Mode .............................................................
Swap Bytes SWPBX.A Register Mode ................................................................................
Swap Bytes SWPBX.A In Memory ....................................................................................
Swap Bytes SWPBX[.W] Register Mode .............................................................................
Swap Bytes SWPBX[.W] In Memory ..................................................................................
Sign Extend SXTX.A ....................................................................................................
Sign Extend SXTX[.W] ..................................................................................................
Flash Memory Module Block Diagram ................................................................................
256-KB Flash Memory Segments Example ..........................................................................
Erase Cycle Timing ......................................................................................................
Erase Cycle From Flash ................................................................................................
Erase Cycle From RAM .................................................................................................
Byte, Word, and Long-Word Write Timing ............................................................................
Initiating a Byte or Word Write From Flash ...........................................................................
Initiating a Byte or Word Write From RAM ...........................................................................
Initiating Long-Word Write From Flash ................................................................................
Initiating Long-Word Write from RAM .................................................................................
Block-Write Cycle Timing ...............................................................................................
Block Write Flow .........................................................................................................
User-Developed Programming Solution ..............................................................................
FCTL1 Register ..........................................................................................................
FCTL3 Register ..........................................................................................................
FCTL4 Register ..........................................................................................................
SFRIE1 Register .........................................................................................................
RCCTL0 Register ........................................................................................................
DMA Controller Block Diagram.........................................................................................
DMA Addressing Modes ................................................................................................
DMA Single Transfer State Diagram ..................................................................................
DMA Block Transfer State Diagram ...................................................................................
DMA Burst-Block Transfer State Diagram ............................................................................
DMACTL0 Register ......................................................................................................
DMACTL1 Register ......................................................................................................
DMACTL2 Register ......................................................................................................
DMACTL3 Register ......................................................................................................
DMACTL4 Register ......................................................................................................
DMAxCTL Register ......................................................................................................
DMAxSA Register ........................................................................................................
DMAxDA Register........................................................................................................
DMAxSZ Register ........................................................................................................
DMAIV Register ..........................................................................................................
SLAU259E – May 2009 – Revised January 2013
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List of Figures
256
262
262
263
264
268
268
269
269
270
270
289
290
293
294
295
296
297
298
299
300
301
302
306
308
309
310
311
315
318
319
321
322
324
332
333
334
335
336
337
339
340
341
342
17
ECCN 5E002 TSPA - Technology / Software Publicly Available.
www.ti.com
8-1.
P1IV Register ............................................................................................................. 356
8-2.
P2IV Register ............................................................................................................. 357
8-3.
P1IES Register ........................................................................................................... 358
8-4.
P1IE Register ............................................................................................................. 358
8-5.
P1IFG Register ........................................................................................................... 358
8-6.
P2IES Register ........................................................................................................... 359
8-7.
P2IE Register ............................................................................................................. 359
8-8.
P2IFG Register ........................................................................................................... 359
8-9.
PxIN Register ............................................................................................................. 360
8-10.
PxOUT Register .......................................................................................................... 360
8-11.
PxDIR Register ........................................................................................................... 360
8-12.
PxREN Register .......................................................................................................... 361
8-13.
PxDS Register ............................................................................................................ 361
8-14.
PxSEL Register
9-1.
9-2.
9-3.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
11-12.
11-13.
12-1.
12-2.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
18
..........................................................................................................
PMAPKEYID Register ...................................................................................................
PMAPCTL Register ......................................................................................................
PxMAPy Register ........................................................................................................
LFSR Implementation of CRC-CCITT Standard, Bit 0 is the MSB of the Result ................................
Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers ..................................
CRCDI Register ..........................................................................................................
CRCDIRB Register ......................................................................................................
CRCINIRES Register ....................................................................................................
CRCRESR Register .....................................................................................................
AES Accelerator Block Diagram .......................................................................................
AES State Array Input and Output .....................................................................................
AES-128 Encryption Process...........................................................................................
AES-128 Decryption Process using AESOPx = 01 .................................................................
AES-128 Decryption Process using AESOPx = 10 and 11 ........................................................
AESACTL0 Register .....................................................................................................
AESACTL1 Register .....................................................................................................
AESASTAT Register.....................................................................................................
AESAKEY Register ......................................................................................................
AESADIN Register .......................................................................................................
AESADOUT Register ....................................................................................................
AESAXDIN Register .....................................................................................................
AESAXIN Register .......................................................................................................
Watchdog Timer Block Diagram .......................................................................................
WDTCTL Register .......................................................................................................
Timer_A Block Diagram .................................................................................................
Up Mode ..................................................................................................................
Up Mode Flag Setting ...................................................................................................
Continuous Mode ........................................................................................................
Continuous Mode Flag Setting .........................................................................................
Continuous Mode Time Intervals ......................................................................................
Up/Down Mode ...........................................................................................................
Up/Down Mode Flag Setting............................................................................................
Output Unit in Up/Down Mode .........................................................................................
Capture Signal (SCS = 1) ...............................................................................................
Capture Cycle ............................................................................................................
List of Figures
361
366
366
366
368
370
373
373
374
374
376
377
378
379
380
383
384
385
386
387
387
388
388
391
395
398
400
400
401
401
401
402
402
403
404
404
SLAU259E – May 2009 – Revised January 2013
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.................................................................................
Output Example – Timer in Continuous Mode .......................................................................
Output Example – Timer in Up/Down Mode ..........................................................................
Capture/Compare TAxCCR0 Interrupt Flag ..........................................................................
TAxCTL Register .........................................................................................................
TAxR Register ............................................................................................................
TAxCCTLn Register .....................................................................................................
TAxCCRn Register ......................................................................................................
TAxIV Register ...........................................................................................................
TAxEX0 Register .........................................................................................................
RTC_A .....................................................................................................................
RTCCTL0 Register ......................................................................................................
RTCCTL1 Register ......................................................................................................
RTCCTL2 Register ......................................................................................................
RTCCTL3 Register ......................................................................................................
RTCNT1 Register ........................................................................................................
RTCNT2 Register ........................................................................................................
RTCNT3 Register ........................................................................................................
RTCNT4 Register ........................................................................................................
RTCSEC Register........................................................................................................
RTCSEC Register........................................................................................................
RTCMIN Register ........................................................................................................
RTCMIN Register ........................................................................................................
RTCHOUR Register .....................................................................................................
RTCHOUR Register .....................................................................................................
RTCDOW Register ......................................................................................................
RTCDAY Register........................................................................................................
RTCDAY Register........................................................................................................
RTCMON Register .......................................................................................................
RTCMON Register .......................................................................................................
RTCYEARL Register ....................................................................................................
RTCYEARL Register ....................................................................................................
RTCYEARH Register ....................................................................................................
RTCYEARH Register ....................................................................................................
RTCAMIN Register ......................................................................................................
RTCAMIN Register ......................................................................................................
RTCAHOUR Register ...................................................................................................
RTCAHOUR Register ...................................................................................................
RTCADOW Register .....................................................................................................
RTCADAY Register ......................................................................................................
RTCADAY Register ......................................................................................................
RTCPS0CTL Register ...................................................................................................
RTCPS1CTL Register ...................................................................................................
RT0PS Register ..........................................................................................................
RTPS1 Register ..........................................................................................................
RTCIV Register...........................................................................................................
RTC_D Block Diagram ..................................................................................................
RTCCTL0 Register ......................................................................................................
RTCCTL1 Register ......................................................................................................
13-12. Output Example – Timer in Up Mode
406
13-13.
407
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
16-1.
16-2.
16-3.
SLAU259E – May 2009 – Revised January 2013
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List of Figures
408
409
412
413
414
416
416
417
421
430
431
432
432
433
433
433
433
434
434
435
435
436
436
437
437
437
438
438
439
439
440
440
441
441
442
442
443
443
443
444
445
446
446
446
449
459
460
19
ECCN 5E002 TSPA - Technology / Software Publicly Available.
www.ti.com
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
18-1.
18-2.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
20
......................................................................................................
RTCCTL3 Register ......................................................................................................
RTCNT1 Register ........................................................................................................
RTCNT2 Register ........................................................................................................
RTCNT3 Register ........................................................................................................
RTCNT4 Register ........................................................................................................
RTCSEC Register........................................................................................................
RTCSEC Register........................................................................................................
RTCMIN Register ........................................................................................................
RTCMIN Register ........................................................................................................
RTCHOUR Register .....................................................................................................
RTCHOUR Register .....................................................................................................
RTCDOW Register ......................................................................................................
RTCDAY Register........................................................................................................
RTCDAY Register........................................................................................................
RTCMON Register .......................................................................................................
RTCMON Register .......................................................................................................
RTCYEAR Register ......................................................................................................
RTCYEAR Register ......................................................................................................
RTCAMIN Register ......................................................................................................
RTCAMIN Register ......................................................................................................
RTCAHOUR Register ...................................................................................................
RTCAHOUR Register ...................................................................................................
RTCADOW Register .....................................................................................................
RTCADAY Register ......................................................................................................
RTCADAY Register ......................................................................................................
RTCPS0CTL Register ...................................................................................................
RTCPS1CTL Register ...................................................................................................
RTCPS0 Register ........................................................................................................
RTCPS1 Register ........................................................................................................
RTCIV Register...........................................................................................................
BIN2BCD Register .......................................................................................................
BCD2BIN Register .......................................................................................................
MPY32 Block Diagram ..................................................................................................
Q15 Format Representation ............................................................................................
Q14 Format Representation ............................................................................................
Saturation Flow Chart ...................................................................................................
Multiplication Flow Chart ................................................................................................
MPY32CTL0 Register ...................................................................................................
REF Block Diagram ......................................................................................................
REFCTL0 Register .......................................................................................................
ADC10_A Block Diagram ...............................................................................................
Analog Multiplexer .......................................................................................................
Extended Sample Mode.................................................................................................
Pulse Sample Mode .....................................................................................................
Analog Input Equivalent Circuit ........................................................................................
Single-Channel Single-Conversion Mode .............................................................................
Sequence-of-Channels Mode ..........................................................................................
Repeat-Single-Channel Mode ..........................................................................................
RTCCTL2 Register
List of Figures
461
461
462
462
462
462
463
463
464
464
465
465
466
466
466
467
467
468
468
469
469
470
470
471
471
471
472
473
474
474
475
476
476
479
484
484
486
488
494
497
503
507
508
510
510
511
512
513
514
SLAU259E – May 2009 – Revised January 2013
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19-9.
Repeat-Sequence-of-Channels Mode ................................................................................. 515
19-10. Typical Temperature Sensor Transfer Function ..................................................................... 517
19-11. ADC10_A Grounding and Noise Considerations .................................................................... 518
...................................................................................................
ADC10CTL1 Register ...................................................................................................
ADC10CTL2 Register ...................................................................................................
ADC10MEM0 Register ..................................................................................................
ADC10MEM0 Register ..................................................................................................
ADC10MCTL0 Register .................................................................................................
ADC10HI Register .......................................................................................................
ADC10HI Register .......................................................................................................
ADC10LO Register ......................................................................................................
ADC10LO Register ......................................................................................................
ADC10IE Register .......................................................................................................
ADC10IFG Register .....................................................................................................
ADC10IV Register .......................................................................................................
ADC12_A Block Diagram (Devices With REF Module) .............................................................
ADC12_A MSP430F54xx (non-A) Block Diagram ...................................................................
Analog Multiplexer .......................................................................................................
Extended Sample Mode.................................................................................................
Pulse Sample Mode .....................................................................................................
Analog Input Equivalent Circuit ........................................................................................
Single-Channel Single-Conversion Mode .............................................................................
Sequence-of-Channels Mode ..........................................................................................
Repeat-Single-Channel Mode ..........................................................................................
Repeat-Sequence-of-Channels Mode .................................................................................
Typical Temperature Sensor Transfer Function .....................................................................
ADC12_A Grounding and Noise Considerations ....................................................................
ADC12CTL0 Register ...................................................................................................
ADC12CTL1 Register ...................................................................................................
ADC12CTL2 Register ...................................................................................................
ADC12MEMx Register ..................................................................................................
ADC12MCTLx Register .................................................................................................
ADC12IE Register .......................................................................................................
ADC12IFG Register .....................................................................................................
ADC12IV Register .......................................................................................................
Comp_B Block Diagram.................................................................................................
Comp_B Sample-And-Hold .............................................................................................
RC-Filter Response at the Output of the Comparator...............................................................
Reference Generator Block Diagram ..................................................................................
Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer ......................................
Temperature Measurement System ...................................................................................
Timing for Temperature Measurement Systems .....................................................................
CBCTL0 Register ........................................................................................................
CBCTL1 Register ........................................................................................................
CBCTL2 Register ........................................................................................................
CBCTL3 Register ........................................................................................................
CBINT Register...........................................................................................................
CBIV Register ............................................................................................................
19-12. ADC10CTL0 Register
521
19-13.
522
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
SLAU259E – May 2009 – Revised January 2013
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List of Figures
524
525
525
526
527
527
528
528
529
530
531
534
535
536
538
539
539
541
542
543
544
546
547
552
554
555
556
557
558
560
562
564
566
567
567
568
568
569
571
572
574
575
577
578
21
ECCN 5E002 TSPA - Technology / Software Publicly Available.
www.ti.com
22-1.
USCI_Ax Block Diagram – UART Mode (UCSYNC = 0) ........................................................... 582
22-2.
Character Format ........................................................................................................ 583
22-3.
Idle-Line Format .......................................................................................................... 584
22-4.
Address-Bit Multiprocessor Format .................................................................................... 585
22-5.
Auto Baud-Rate Detection – Break/Synch Sequence ............................................................... 586
22-6.
Auto Baud-Rate Detection – Synch Field ............................................................................. 586
22-7.
UART vs IrDA Data Format............................................................................................. 587
22-8.
Glitch Suppression, USCI Receive Not Started ...................................................................... 589
22-9.
Glitch Suppression, USCI Activated ................................................................................... 589
22-10. BITCLK Baud-Rate Timing With UCOS16 = 0 ....................................................................... 590
22-11. Receive Error ............................................................................................................. 593
22-12. UCAxCTL0 Register ..................................................................................................... 600
22-13. UCAxCTL1 Register ..................................................................................................... 601
602
22-15.
602
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
22
......................................................................................................
UCAxBR1 Register ......................................................................................................
UCAxMCTL Register ....................................................................................................
UCAxSTAT Register .....................................................................................................
UCAxRXBUF Register ..................................................................................................
UCAxTXBUF Register ...................................................................................................
UCAxIRTCTL Register ..................................................................................................
UCAxIRRCTL Register ..................................................................................................
UCAxABCTL Register ...................................................................................................
UCAxIE Register .........................................................................................................
UCAxIFG Register .......................................................................................................
UCAxIV Register .........................................................................................................
USCI Block Diagram – SPI Mode......................................................................................
USCI Master and External Slave ......................................................................................
USCI Slave and External Master ......................................................................................
USCI SPI Timing With UCMSB = 1 ...................................................................................
UCAxCTL0 Register .....................................................................................................
UCAxCTL1 Register .....................................................................................................
UCAxBR0 Register ......................................................................................................
UCAxBR1 Register ......................................................................................................
UCAxMCTL Register ....................................................................................................
UCAxSTAT Register .....................................................................................................
UCAxRXBUF Register ..................................................................................................
UCAxTXBUF Register ...................................................................................................
UCAxIE Register .........................................................................................................
UCAxIFG Register .......................................................................................................
UCAxIV Register .........................................................................................................
UCBxCTL0 Register .....................................................................................................
UCBxCTL1 Register .....................................................................................................
UCBxBR0 Register ......................................................................................................
UCBxBR1 Register ......................................................................................................
UCBxMCTL Register ....................................................................................................
UCBxSTAT Register .....................................................................................................
UCBxRXBUF Register ..................................................................................................
UCBxTXBUF Register ...................................................................................................
UCBxIE Register .........................................................................................................
22-14. UCAxBR0 Register
List of Figures
602
603
604
604
605
605
606
607
607
608
612
614
615
616
619
620
621
621
621
622
623
623
624
624
625
627
628
629
629
629
630
631
631
632
SLAU259E – May 2009 – Revised January 2013
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23-25. UCBxIFG Register ....................................................................................................... 632
23-26. UCBxIV Register ......................................................................................................... 633
......................................................................................
24-1.
USCI Block Diagram – I2C Mode
24-2.
I2C Bus Connection Diagram ........................................................................................... 638
24-3.
I2C Module Data Transfer ............................................................................................... 639
24-4.
Bit Transfer on I2C Bus .................................................................................................. 639
24-5.
I2C Module 7-Bit Addressing Format .................................................................................. 640
24-6.
I2C Module 10-Bit Addressing Format ................................................................................. 640
24-7.
I2C Module Addressing Format With Repeated START Condition ................................................ 640
24-8.
I2C Time-Line Legend ................................................................................................... 641
24-9.
I2C Slave Transmitter Mode
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
............................................................................................
I C Slave Receiver Mode ...............................................................................................
I2C Slave 10-Bit Addressing Mode .....................................................................................
I2C Master Transmitter Mode ...........................................................................................
I2C Master Receiver Mode ..............................................................................................
I2C Master 10-Bit Addressing Mode ...................................................................................
Arbitration Procedure Between Two Master Transmitters ..........................................................
Synchronization of Two I2C Clock Generators During Arbitration .................................................
UCBxCTL0 Register .....................................................................................................
UCBxCTL1 Register .....................................................................................................
UCBxBR0 Register ......................................................................................................
UCBxBR1 Register ......................................................................................................
UCBxSTAT Register .....................................................................................................
UCBxRXBUF Register ..................................................................................................
UCBxTXBUF Register ...................................................................................................
UCBxI2COA Register ...................................................................................................
UCBxI2CSA Register ....................................................................................................
UCBxIE Register .........................................................................................................
UCBxIFG Register .......................................................................................................
UCBxIV Register .........................................................................................................
Simplified Block Diagram of the CC1101-Based Radio Module ...................................................
Radio Interface Overview ...............................................................................................
Logical Channels Between Radio Interface and Radio Core ......................................................
Data Whitening in TX Mode ............................................................................................
Packet Format ............................................................................................................
Packet Length Greater Than 255 ......................................................................................
Complete Radio-Control State Diagram ..............................................................................
Event 0 and Event 1 Relationship .....................................................................................
2
637
642
644
645
647
649
650
651
652
657
658
659
659
660
661
661
662
662
663
664
665
667
668
669
688
688
690
697
699
FIFO_THR = 13 vs Number of Bytes in FIFO (GDOx_CFG = 0x00 in RX and GDOx_CFG = 0x02 in
TX) ......................................................................................................................... 702
25-10. Example of FIFOs at Threshold ........................................................................................ 702
25-11. PA_POWER and PATABLE ............................................................................................ 704
25-12. Shaping of ASK Signal .................................................................................................. 704
25-13. Block Diagram of CC1101-based Radio With External Power Amplifier ......................................... 708
25-14. RF1AIFCTL0 Register ................................................................................................... 734
25-15. RF1AIFCTL1 Register ................................................................................................... 735
25-16. RF1AIFERR Register .................................................................................................... 736
25-17. RF1AIFERRV Register .................................................................................................. 737
25-18. RF1AIFIV Register ....................................................................................................... 737
SLAU259E – May 2009 – Revised January 2013
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List of Figures
23
ECCN 5E002 TSPA - Technology / Software Publicly Available.
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25-19. RF1AIN Register ......................................................................................................... 738
25-20. RF1AIFG Register ....................................................................................................... 738
25-21. RF1AIES Register
.......................................................................................................
739
25-22. RF1AIE Register ......................................................................................................... 739
25-23. RF1AIV Register ......................................................................................................... 740
26-1.
LCD_B Controller Block Diagram ...................................................................................... 743
26-2.
LCD Memory - Example for 160 Segments Maximum .............................................................. 744
26-3.
Bias Generation .......................................................................................................... 747
26-4.
Example Static Waveforms ............................................................................................. 750
26-5.
Static LCD Example (MAB addresses need to be replaced with LCDMx) ....................................... 751
26-6.
Example 2-Mux Waveforms ............................................................................................ 753
26-7.
2-Mux LCD Example (MAB addresses need to be replaced with LCDMx)....................................... 754
26-8.
Example 3-Mux Waveforms ............................................................................................ 756
26-9.
3-Mux LCD Example (MAB addresses need to be replaced with LCDMx)....................................... 757
26-10. Example 4-Mux Waveforms ............................................................................................ 759
26-11. 4-Mux LCD Example (MAB addresses need to be replaced with LCDMx)....................................... 760
26-12. LCDBCTL0 Register ..................................................................................................... 765
26-13. LCDBCTL1 Register ..................................................................................................... 766
26-14. LCDBBLKCTL Register ................................................................................................. 767
26-15. LCDBMEMCTL Register ................................................................................................ 768
26-16. LCDBVCTL Register..................................................................................................... 769
26-17. LCDBPCTL0 Register ................................................................................................... 771
26-18. LCDBPCTL1 Register ................................................................................................... 771
26-19. LCDBPCTL2 Register ................................................................................................... 772
26-20. LCDBPCTL3 Register ................................................................................................... 772
26-21. LCDBCPCTL Register................................................................................................... 773
26-22. LCDBIV Register ......................................................................................................... 774
27-1.
24
Large Implementation of EEM .......................................................................................... 777
List of Figures
SLAU259E – May 2009 – Revised January 2013
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List of Tables
1-1.
Interrupt Sources, Flags, and Vectors .................................................................................. 42
1-2.
Operation Modes .......................................................................................................... 46
1-3.
Connection of Unused Pins .............................................................................................. 50
1-4.
Tag Values ................................................................................................................. 57
1-5.
Peripheral Discovery Descriptor ......................................................................................... 58
1-6.
Values for Memory Entry ................................................................................................. 58
1-7.
Values for Peripheral Entry............................................................................................... 59
1-8.
Peripheral IDs
1-9.
Sample Peripheral Discovery Descriptor ............................................................................... 61
1-10.
SFR Base Address ........................................................................................................ 65
1-11.
SFR Registers
1-12.
SFRIE1 Register Description
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
1-19.
1-20.
1-21.
1-22.
1-23.
1-24.
1-25.
1-26.
1-27.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
.............................................................................................................
59
............................................................................................................. 65
............................................................................................ 66
SFRIFG1 Register Description .......................................................................................... 67
SFRRPCR Register Description ......................................................................................... 69
SYS Base Address ........................................................................................................ 70
SYS Registers ............................................................................................................. 70
SYSCTL Register Description ........................................................................................... 71
SYSBSLC Register Description ......................................................................................... 72
SYSJMBC Register Description ......................................................................................... 73
SYSJMBI0 Register Description ......................................................................................... 74
SYSJMBI1 Register Description ......................................................................................... 74
SYSJMBO0 Register Description ....................................................................................... 75
SYSJMBO1 Register Description ....................................................................................... 75
SYSUNIV Register Description .......................................................................................... 76
SYSSNIV Register Description .......................................................................................... 77
SYSRSTIV Register Description ........................................................................................ 78
SYSBERRIV Register Description ...................................................................................... 79
SVS and SVM Thresholds ............................................................................................... 84
Recommended SVSL Settings ........................................................................................... 84
Recommended SVSH Settings ........................................................................................... 84
Available SVSH and SVMH Settings Versus VCORE Settings .......................................................... 85
SVSL and SVML Control Mode Selection ............................................................................... 93
SVSL Automatic Performance Control .................................................................................. 93
SVSL Manual Performance Modes ...................................................................................... 93
SVML Automatic Performance Control .................................................................................. 93
SVML Manual Performance Modes ..................................................................................... 93
SVSH and SVMH Control Mode Selection .............................................................................. 94
SVSH Automatic Performance Control .................................................................................. 94
SVSH Manual Performance Modes ...................................................................................... 94
SVMH Automatic Performance Control ................................................................................. 94
SVMH Manual Performance Modes ..................................................................................... 94
PMM Registers ............................................................................................................ 96
PMMCTL0 Register Description ......................................................................................... 97
PMMCTL1 Register Description ......................................................................................... 98
SVSMHCTL Register Description ....................................................................................... 99
SVSMLCTL Register Description ...................................................................................... 100
SVSMIO Register Description .......................................................................................... 101
SLAU259E – May 2009 – Revised January 2013
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List of Tables
25
ECCN 5E002 TSPA - Technology / Software Publicly Available.
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2-21.
PMMIFG Register Description.......................................................................................... 102
2-22.
PMMRIE Register Description.......................................................................................... 104
2-23.
PM5CTL0 Register Description ........................................................................................ 105
3-1.
Clock Request System and Power Modes
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
6-1.
6-2.
7-1.
7-2.
7-3.
26
...........................................................................
UCS Registers............................................................................................................
UCSCTL0 Register Description ........................................................................................
UCSCTL1 Register Description ........................................................................................
UCSCTL2 Register Description ........................................................................................
UCSCTL3 Register Description ........................................................................................
UCSCTL4 Register Description ........................................................................................
UCSCTL5 Register Description ........................................................................................
UCSCTL6 Register Description ........................................................................................
UCSCTL7 Register Description ........................................................................................
UCSCTL8 Register Description ........................................................................................
UCSCTL9 Register Description ........................................................................................
SR Bit Description .......................................................................................................
Values of Constant Generators CG1, CG2 ...........................................................................
Source and Destination Addressing ...................................................................................
MSP430 Double-Operand Instructions ................................................................................
MSP430 Single-Operand Instructions .................................................................................
Conditional Jump Instructions ..........................................................................................
Emulated Instructions ...................................................................................................
Interrupt, Return, and Reset Cycles and Length.....................................................................
MSP430 Format II Instruction Cycles and Length ...................................................................
MSP430 Format I Instructions Cycles and Length ..................................................................
Description of the Extension Word Bits for Register Mode .........................................................
Description of Extension Word Bits for Non-Register Modes ......................................................
Extended Double-Operand Instructions ...............................................................................
Extended Single-Operand Instructions ................................................................................
Extended Emulated Instructions .......................................................................................
Address Instructions, Operate on 20-Bit Register Data .............................................................
MSP430X Format II Instruction Cycles and Length .................................................................
MSP430X Format I Instruction Cycles and Length ..................................................................
Address Instruction Cycles and Length ...............................................................................
Instruction Map of MSP430X ...........................................................................................
Supported Simultaneous Code Execution and Flash Operations .................................................
Erase Modes..............................................................................................................
Write Modes ..............................................................................................................
Flash Access While Flash is Busy (BUSY = 1) ......................................................................
FCTL Registers...........................................................................................................
FCTL1 Register Description ............................................................................................
FCTL3 Register Description ............................................................................................
FCTL4 Register Description ............................................................................................
SFRIE1 Register Description ...........................................................................................
RAMCTL Registers ......................................................................................................
RCCTL0 Register Description ..........................................................................................
DMA Transfer Modes ....................................................................................................
DMA Trigger Operation .................................................................................................
Maximum Single-Transfer DMA Cycle Time .........................................................................
List of Tables
114
120
121
122
123
124
125
126
128
129
130
131
138
139
142
160
160
161
161
162
162
163
164
165
166
168
170
171
172
173
174
175
292
292
296
303
307
308
309
310
311
314
315
320
326
327
SLAU259E – May 2009 – Revised January 2013
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7-4.
DMA Registers ........................................................................................................... 330
7-5.
DMACTL0 Register Description ........................................................................................ 332
7-6.
DMACTL1 Register Description ........................................................................................ 333
7-7.
DMACTL2 Register Description ........................................................................................ 334
7-8.
DMACTL3 Register Description ........................................................................................ 335
7-9.
DMACTL4 Register Description ........................................................................................ 336
7-10.
DMAxCTL Register Description ........................................................................................ 337
7-11.
DMAxSA Register Description
7-12.
DMAxDA Register Description ......................................................................................... 340
7-13.
DMAxSZ Register Description.......................................................................................... 341
7-14.
DMAIV Register Description ............................................................................................ 342
8-1.
I/O Configuration ......................................................................................................... 345
8-2.
Digital I/O Registers
350
8-3.
P1IV Register Description
356
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
10-1.
10-2.
10-3.
10-4.
10-5.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
12-1.
.........................................................................................
.....................................................................................................
..............................................................................................
P2IV Register Description ..............................................................................................
P1IES Register Description .............................................................................................
P1IE Register Description ..............................................................................................
P1IFG Register Description.............................................................................................
P2IES Register Description .............................................................................................
P2IE Register Description ..............................................................................................
P2IFG Register Description.............................................................................................
PxIN Register Description ..............................................................................................
PxOUT Register Description ...........................................................................................
PxDIR Register Description.............................................................................................
PxREN Register Description ...........................................................................................
PxDS Register Description .............................................................................................
PxSEL Register Description ............................................................................................
Examples for Port Mapping Mnemonics and Functions ............................................................
Port Mapping Control Registers ........................................................................................
Port Mapping Registers for Port Px – Byte Access .................................................................
Port Mapping Registers for Port Px – Word Access ................................................................
PMAPKEYID Register Description.....................................................................................
PMAPCTL Register Description........................................................................................
PxMAPy Register Description ..........................................................................................
CRC Registers ...........................................................................................................
CRCDI Register Description ............................................................................................
CRCDIRB Register Description ........................................................................................
CRCINIRES Register Description .....................................................................................
CRCRESR Register Description .......................................................................................
AES_ACCEL Registers .................................................................................................
AESACTL0 Register Description.......................................................................................
AESACTL1 Register Description.......................................................................................
AESASTAT Register Description ......................................................................................
AESAKEY Register Description ........................................................................................
AESADIN Register Description ........................................................................................
AESADOUT Register Description .....................................................................................
AESAXDIN Register Description .......................................................................................
AESAXIN Register Description .........................................................................................
WDT_A Registers ........................................................................................................
SLAU259E – May 2009 – Revised January 2013
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List of Tables
339
357
358
358
358
359
359
359
360
360
360
361
361
361
364
365
365
365
366
366
366
372
373
373
374
374
382
383
384
385
386
387
387
388
388
394
27
ECCN 5E002 TSPA - Technology / Software Publicly Available.
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12-2.
WDTCTL Register Description ......................................................................................... 395
13-1.
Timer Modes .............................................................................................................. 400
13-2.
Output Modes
13-3.
Timer_A Registers ....................................................................................................... 411
13-4.
TAxCTL Register Description
13-5.
TAxR Register Description.............................................................................................. 413
13-6.
TAxCCTLn Register Description ....................................................................................... 414
13-7.
TAxCCRn Register Description ........................................................................................ 416
13-8.
TAxIV Register Description ............................................................................................. 416
13-9.
TAxEX0 Register Description
14-1.
RTC Overview ............................................................................................................ 418
15-1.
RTC_A Registers
15-2.
RTCCTL0 Register Description ........................................................................................ 430
15-3.
RTCCTL1 Register Description ........................................................................................ 431
15-4.
RTCCTL2 Register Description ........................................................................................ 432
15-5.
RTCCTL3 Register Description ........................................................................................ 432
15-6.
RTCNT1 Register Description .......................................................................................... 433
15-7.
RTCNT2 Register Description .......................................................................................... 433
15-8.
RTCNT3 Register Description .......................................................................................... 433
15-9.
RTCNT4 Register Description .......................................................................................... 433
............................................................................................................
..........................................................................................
..........................................................................................
........................................................................................................
405
412
417
428
15-10. RTCSEC Register Description ......................................................................................... 434
15-11. RTCSEC Register Description ......................................................................................... 434
15-12. RTCMIN Register Description .......................................................................................... 435
15-13. RTCMIN Register Description .......................................................................................... 435
15-14. RTCHOUR Register Description ....................................................................................... 436
15-15. RTCHOUR Register Description ....................................................................................... 436
15-16. RTCDOW Register Description ........................................................................................ 437
15-17. RTCDAY Register Description ......................................................................................... 437
15-18. RTCDAY Register Description ......................................................................................... 437
438
15-20. RTCMON Register Description
438
15-21.
439
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
16-1.
16-2.
28
........................................................................................
........................................................................................
RTCYEARL Register Description ......................................................................................
RTCYEARL Register Description ......................................................................................
RTCYEARH Register Description .....................................................................................
RTCYEARH Register Description .....................................................................................
RTCAMIN Register Description ........................................................................................
RTCAMIN Register Description ........................................................................................
RTCAHOUR Register Description .....................................................................................
RTCAHOUR Register Description .....................................................................................
RTCADOW Register Description ......................................................................................
RTCADAY Register Description .......................................................................................
RTCADAY Register Description .......................................................................................
RTCPS0CTL Register Description.....................................................................................
RTCPS1CTL Register Description.....................................................................................
RT0PS Register Description ............................................................................................
RT1PS Register Description ............................................................................................
RTCIV Register Description ............................................................................................
RTC_D Registers ........................................................................................................
RTCCTL0 Register Description ........................................................................................
15-19. RTCMON Register Description
List of Tables
439
440
440
441
441
442
442
443
443
443
444
445
446
446
446
457
459
SLAU259E – May 2009 – Revised January 2013
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16-3.
RTCCTL1 Register Description ........................................................................................ 460
16-4.
RTCCTL2 Register Description ........................................................................................ 461
16-5.
RTCCTL3 Register Description ........................................................................................ 461
16-6.
RTCNT1 Register Description .......................................................................................... 462
16-7.
RTCNT2 Register Description .......................................................................................... 462
16-8.
RTCNT3 Register Description .......................................................................................... 462
16-9.
RTCNT4 Register Description .......................................................................................... 462
16-10. RTCSEC Register Description ......................................................................................... 463
16-11. RTCSEC Register Description ......................................................................................... 463
16-12. RTCMIN Register Description .......................................................................................... 464
16-13. RTCMIN Register Description .......................................................................................... 464
16-14. RTCHOUR Register Description ....................................................................................... 465
16-15. RTCHOUR Register Description ....................................................................................... 465
16-16. RTCDOW Register Description ........................................................................................ 466
16-17. RTCDAY Register Description ......................................................................................... 466
16-18. RTCDAY Register Description ......................................................................................... 466
........................................................................................
........................................................................................
RTCYEAR Register Description .......................................................................................
RTCYEAR Register Description .......................................................................................
RTCAMIN Register Description ........................................................................................
RTCAMIN Register Description ........................................................................................
RTCAHOUR Register Description .....................................................................................
RTCAHOUR Register Description .....................................................................................
RTCADOW Register Description ......................................................................................
RTCADAY Register Description .......................................................................................
RTCADAY Register Description .......................................................................................
RTCPS0CTL Register Description.....................................................................................
RTCPS1CTL Register Description.....................................................................................
RTCPS0 Register Description ..........................................................................................
RTCPS1 Register Description ..........................................................................................
RTCIV Register Description ............................................................................................
BIN2BCD Register Description .........................................................................................
BCD2BIN Register Description .........................................................................................
Result Availability (MPYFRAC = 0, MPYSAT = 0) ..................................................................
OP1 Registers ............................................................................................................
OP2 Registers ............................................................................................................
SUMEXT and MPYC Contents .........................................................................................
Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0) ...........................................
Result Availability in Saturation Mode (MPYSAT = 1) ..............................................................
MPY32 Registers ........................................................................................................
Alternative Registers.....................................................................................................
MPY32CTL0 Register Description .....................................................................................
REF Control of Reference System (REFMSTR = 1) (Default) .....................................................
Control of Reference System (REFMSTR = 0, ADC12_A only) ...................................................
REF Registers ............................................................................................................
REFCTL0 Register Description ........................................................................................
Conversion Mode Summary ............................................................................................
ADC10_A Registers .....................................................................................................
16-19. RTCMON Register Description
467
16-20. RTCMON Register Description
467
16-21.
468
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
18-1.
18-2.
18-3.
18-4.
19-1.
19-2.
SLAU259E – May 2009 – Revised January 2013
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List of Tables
468
469
469
470
470
471
471
471
472
473
474
474
475
476
476
480
481
481
482
485
486
492
493
494
499
500
502
503
511
520
29
ECCN 5E002 TSPA - Technology / Software Publicly Available.
www.ti.com
19-3.
ADC10CTL0 Register Description ..................................................................................... 521
19-4.
ADC10CTL1 Register Description ..................................................................................... 522
19-5.
ADC10CTL2 Register Description ..................................................................................... 524
19-6.
ADC10MEM0 Register Description .................................................................................... 525
19-7.
ADC10MEM0 Register Description .................................................................................... 525
19-8.
ADC10MCTL0 Register Description ................................................................................... 526
19-9.
ADC10HI Register Description ......................................................................................... 527
19-10. ADC10HI Register Description ......................................................................................... 527
19-11. ADC10LO Register Description ........................................................................................ 528
19-12. ADC10LO Register Description ........................................................................................ 528
19-13. ADC10IE Register Description ......................................................................................... 529
19-14. ADC10IFG Register Description ....................................................................................... 530
19-15. ADC10IV Register Description ......................................................................................... 531
20-1.
ADC12_A Conversion Result Formats ................................................................................ 540
20-2.
Conversion Mode Summary ............................................................................................ 540
20-3.
ADC12_A Registers ..................................................................................................... 550
20-4.
ADC12CTL0 Register Description ..................................................................................... 552
20-5.
ADC12CTL1 Register Description ..................................................................................... 554
20-6.
ADC12CTL2 Register Description ..................................................................................... 555
20-7.
ADC12MEMx Register Description .................................................................................... 556
20-8.
ADC12MCTLx Register Description ................................................................................... 557
20-9.
ADC12IE Register Description ......................................................................................... 558
20-10. ADC12IFG Register Description ....................................................................................... 560
20-11. ADC12IV Register Description ......................................................................................... 562
21-1.
Comp_B Registers ....................................................................................................... 570
21-2.
CBCTL0 Register Description .......................................................................................... 571
21-3.
CBCTL1 Register Description .......................................................................................... 572
21-4.
CBCTL2 Register Description .......................................................................................... 574
21-5.
CBCTL3 Register Description .......................................................................................... 575
21-6.
CBINT Register Description ............................................................................................ 577
21-7.
CBIV Register Description .............................................................................................. 578
22-1.
Receive Error Conditions
588
22-2.
BITCLK Modulation Pattern
590
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
30
...............................................................................................
............................................................................................
BITCLK16 Modulation Pattern .........................................................................................
Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 ................................................
Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 ................................................
USCI_A UART Mode Registers ........................................................................................
UCAxCTL0 Register Description .......................................................................................
UCAxCTL1 Register Description .......................................................................................
UCAxBR0 Register Description ........................................................................................
UCAxBR1 Register Description ........................................................................................
UCAxMCTL Register Description ......................................................................................
UCAxSTAT Register Description ......................................................................................
UCAxRXBUF Register Description ....................................................................................
UCAxTXBUF Register Description ....................................................................................
UCAxIRTCTL Register Description ....................................................................................
UCAxIRRCTL Register Description....................................................................................
UCAxABCTL Register Description.....................................................................................
UCAxIE Register Description ...........................................................................................
List of Tables
591
594
596
599
600
601
602
602
602
603
604
604
605
605
606
607
SLAU259E – May 2009 – Revised January 2013
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22-19. UCAxIFG Register Description ......................................................................................... 607
22-20. UCAxIV Register Description ........................................................................................... 608
23-1.
UCxSTE Operation ...................................................................................................... 613
23-2.
USCI_A SPI Mode Registers ........................................................................................... 618
23-3.
UCAxCTL0 Register Description ....................................................................................... 619
23-4.
UCAxCTL1 Register Description ....................................................................................... 620
23-5.
UCAxBR0 Register Description ........................................................................................ 621
23-6.
UCAxBR1 Register Description ........................................................................................ 621
23-7.
UCAxMCTL Register Description ...................................................................................... 621
23-8.
UCAxSTAT Register Description
23-9.
UCAxRXBUF Register Description .................................................................................... 623
......................................................................................
23-10. UCAxTXBUF Register Description
....................................................................................
622
623
23-11. UCAxIE Register Description ........................................................................................... 624
23-12. UCAxIFG Register Description ......................................................................................... 624
23-13. UCAxIV Register Description ........................................................................................... 625
23-14. USCI_B SPI Mode Registers ........................................................................................... 626
23-15. UCBxCTL0 Register Description ....................................................................................... 627
23-16. UCBxCTL1 Register Description ....................................................................................... 628
23-17. UCBxBR0 Register Description ........................................................................................ 629
23-18. UCBxBR1 Register Description ........................................................................................ 629
23-19. UCBxMCTL Register Description ...................................................................................... 629
23-20. UCBxSTAT Register Description
......................................................................................
630
23-21. UCBxRXBUF Register Description .................................................................................... 631
....................................................................................
UCBxIE Register Description ...........................................................................................
UCBxIFG Register Description .........................................................................................
UCBxIV Register Description ...........................................................................................
I2C State Change Interrupt Flags ......................................................................................
USCI_B Registers........................................................................................................
UCBxCTL0 Register Description .......................................................................................
UCBxCTL1 Register Description .......................................................................................
UCBxBR0 Register Description ........................................................................................
UCBxBR1 Register Description ........................................................................................
UCBxSTAT Register Description ......................................................................................
UCBxRXBUF Register Description ....................................................................................
UCBxTXBUF Register Description ....................................................................................
UCBxI2COA Register Description .....................................................................................
UCBxI2CSA Register Description .....................................................................................
UCBxIE Register Description ...........................................................................................
UCBxIFG Register Description .........................................................................................
UCBxIV Register Description ...........................................................................................
One-Byte Auto-Read Registers ........................................................................................
Two-Byte (One-Word) Auto-Read Registers .........................................................................
Radio Interface Error Conditions .......................................................................................
Radio Interface Interrupt Flags .........................................................................................
CC1101 Radio Core Interrupt Mapping ...............................................................................
CC1101-Based Radio Core Instruction Set – Command Strobes .................................................
CC1101-Based Radio Core Instruction Set ..........................................................................
Radio Core Status Byte Summary .....................................................................................
23-22. UCBxTXBUF Register Description
631
23-23.
632
23-24.
23-25.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
SLAU259E – May 2009 – Revised January 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
632
633
654
656
657
658
659
659
660
661
661
662
662
663
664
665
672
672
673
674
675
682
683
684
31
ECCN 5E002 TSPA - Technology / Software Publicly Available.
www.ti.com
25-9.
Data Rate Step Size ..................................................................................................... 685
25-10. Channel Filter Bandwidths (kHz) (Assuming a 26-MHz Crystal)
..................................................
685
25-11. Received Packet Status Byte 1 (First Byte Appended After Data) ................................................ 687
25-12. Received Packet Status Byte 2 (Second Byte Appended After Data) ............................................ 687
25-13. Symbol Encoding for 2-FSK and 2-GFSK Modulation .............................................................. 692
25-14. Sync Word Qualifier Mode .............................................................................................. 693
25-15. Typical RSSI Value in dBm at CS Threshold With Default MAGN_TARGET at 2.4 kBaud, 868 MHz ....... 695
25-16. Typical RSSI Value in dBm at CS Threshold With Default MAGN_TARGET at 250 kBaud, 868 MHz ...... 696
25-17. State Transition Timing .................................................................................................. 700
25-18. FIFO_THR Settings and the Corresponding FIFO Thresholds .................................................... 702
25-19. Configuration Registers ................................................................................................. 710
25-20. Status Registers .......................................................................................................... 711
25-21. GDOx Signal Selection (x = 0, 1, or 2) ................................................................................ 712
732
25-23.
734
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
27-1.
32
..........................................................................................................
RF1AIFCTL0 Register Description ....................................................................................
RF1AIFCTL1 Register Description ....................................................................................
RF1AIFERR Register Description .....................................................................................
RF1AIFERRV Register Description....................................................................................
RF1AIFIV Register Description ........................................................................................
RF1AIN Register Description ...........................................................................................
RF1AIFG Register Description .........................................................................................
RF1AIES Register Description .........................................................................................
RF1AIE Register Description ...........................................................................................
RF1AIV Register Description ...........................................................................................
LCD Voltage and Biasing Characteristics ............................................................................
LCD_B Registers.........................................................................................................
LCD_B Memory Registers .............................................................................................
LCD_B Blinking Memory Registers ...................................................................................
LCDBCTL0 Register Description.......................................................................................
LCDBCTL1 Register Description.......................................................................................
LCDBBLKCTL Register Description ...................................................................................
LCDBMEMCTL Register Description ..................................................................................
LCDBVCTL Register Description ......................................................................................
LCDBPCTL0 Register Description .....................................................................................
LCDBPCTL1 Register Description .....................................................................................
LCDBPCTL2 Register Description .....................................................................................
LCDBPCTL3 Register Description .....................................................................................
LCDBCPCTL Register Description ....................................................................................
LCDBIV Register Description...........................................................................................
EEM Configurations .....................................................................................................
25-22. RF1A Registers
List of Tables
735
736
737
737
738
738
739
739
740
748
762
763
764
765
766
767
768
769
771
771
772
772
773
774
779
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Preface
SLAU259E – May 2009 – Revised January 2013
Read This First
About This Manual
This manual describes the modules and peripherals of the CC430 family of devices. Each description
presents the module or peripheral in a general sense. Not all features and functions of all modules or
peripherals may be present on all devices. In addition, modules or peripherals may differ in their exact
implementation between device families, or may not be fully implemented on an individual device or
device family.
Pin functions, internal signal connections, and operational parameters differ from device to device. The
user should consult the device-specific data sheet for these details.
Related Documentation From Texas Instruments
For related documentation see the web site http://www.ti.com/msp430.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required
to take whatever measures may be required to correct this interference.
Notational Conventions
Program examples, are shown in a special typeface.
Glossary
ACLK
Auxiliary Clock; see Section 3.1
ADC
Analog-to-Digital Converter
BOR
Brown-Out Reset; see Section 1.2
BSL
Bootstrap Loader; see www.ti.com/msp430 for application reports
CPU
Central Processing Unit; see Section 4.1
DAC
Digital-to-Analog Converter
DCO
Digitally Controlled Oscillator; see Section 3.2.6
dst
Destination; see Section 4.5
FLL
Frequency Locked Loop; see Section 3.2.7
GIE Modes
General Interrupt Enable; see Section 1.3.3
INT(N/2)
Integer portion of N/2
I/O
Input/Output; see Chapter 8
ISR
Interrupt Service Routine
LSB
Least-Significant Bit
LSD
Least-Significant Digit
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LPM
Low-Power Mode; see Section 1.4; also named PM for Power Mode
MAB
Memory Address Bus
MCLK
Master Clock; see Section 3.1
MDB
Memory Data Bus
MSB
Most-Significant Bit
MSD
Most-Significant Digit
NMI
(Non)-Maskable Interrupt; see Section 1.3.1; also split to UNMI and SNMI
PC
Program Counter; see Section 4.3.1
PM
Power Mode; see Section 1.4
POR
Power-On Reset; see Section 1.2
PUC
Power-Up Clear; see Section 1.2
RAM
Random Access Memory
SCG
System Clock Generator; see Section 4.3.3
SFR
Special Function Register; Section 1.14
SMCLK
Sub-System Master Clock; see Section 3.1
SNMI
System NMI; see Section 1.3.1
SP
Stack Pointer; see Section 4.3.2
SR
Status Register; see Section 4.3.3
src
Source; see Section 4.5
TOS
Top of stack; see Section 4.3.2
UNMI
User NMI; see Section 1.3.1
WDT
Watchdog Timer; see Chapter 12
z16
16-bit address space
Register Bit Conventions
Each register is shown with a key indicating the accessibility of the each individual bit, and the initial
condition:
Register Bit Accessibility and Initial Condition
Key
34
Bit Accessibility
rw
Read/write
r
Read only
r0
Read as 0
r1
Read as 1
w
Write only
w0
Write as 0
w1
Write as 1
(w)
No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0.
h0
Cleared by hardware
h1
Set by hardware
-0,-1
Condition after PUC
-(0),-(1)
Condition after POR
-[0],-[1]
Condition after BOR
-{0},-{1}
Condition after Brownout
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Chapter 1
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System Resets, Interrupts, and Operating Modes, System
Control Module (SYS)
The system control module (SYS) is available on all devices. The following list shows the basic feature set
of SYS.
• Brownout reset (BOR) and power on reset (POR) handling
• Power up clear (PUC) handling
• (Non)maskable interrupt (SNMI and UNMI) event source selection and management
• Address decoding
• A user data-exchange mechanism using the JTAG mailbox (JMB)
• Bootstrap loader (BSL) entry mechanism
• Configuration management (device descriptors)
• Provides interrupt vector generators for reset and NMIs
Topic
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
...........................................................................................................................
System Control Module (SYS) Introduction ..........................................................
System Reset and Initialization ...........................................................................
Interrupts .........................................................................................................
Operating Modes ...............................................................................................
Principles for Low-Power Applications ................................................................
Connection of Unused Pins ................................................................................
Reset Pin (RST/NMI) Configuration ......................................................................
Configuring JTAG pins ......................................................................................
Boot Code ........................................................................................................
Bootstrap Loader (BSL) .....................................................................................
Memory Map – Uses and Abilities ........................................................................
JTAG Mailbox (JMB) System ..............................................................................
Device Descriptor Table .....................................................................................
SFR Registers ...................................................................................................
SYS Registers ...................................................................................................
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50
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51
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54
55
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70
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1.1
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System Control Module (SYS) Introduction
SYS is responsible for the interaction between various modules throughout the system. The functions that
SYS provides for are not inherent to the modules themselves. Address decoding, bus arbitration, interrupt
event consolidation, and reset generation are some examples of the many functions that SYS provides.
1.2
System Reset and Initialization
The system reset circuitry is shown in Figure 1-1 and sources a brownout reset (BOR), a power on reset
(POR), and a power up clear (PUC). Different events trigger these reset signals and different initial
conditions exist depending on which signal was generated.
A
•
•
•
•
BOR is a device reset. A BOR is only generated by the following events:
Powering up the device
A low signal on RST/NMI pin when configured in the reset mode
A wakeup event from LPMx.5 (LPM3.5 or LPM4.5) modes
A software BOR event
A POR is always generated when a BOR is generated, but a BOR is not generated by a POR. The
following events trigger a POR:
• A BOR signal
• A SVSH and/or SVSM low condition when enabled (see the PMM chapter for details)
• A SVSL and/or SVSL low condition when enabled (see the PMM chapter for details)
• A software POR event
A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The
following events trigger a PUC:
• A POR signal
• Watchdog timer expiration when watchdog mode only (see the WDT_A chapter for details)
• Watchdog timer password violation (see the WDT_A chapter for details)
• A Flash memory password violation (see the Flash Controller chapter for details)
• Power Management Module password violation (see the PMM chapter for details)
• Fetch from peripheral area
NOTE: The number and type of resets available may vary from device to device. See the devicespecific data sheet for all reset sources available.
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BOR shadow
s
Delay
brownout circuit
s clr
from port
wakeup logic
EN
PMMRSTIFG
s clr
RST/NMI
SYSNMI
notRST
Delay
BOR
Delay
POR
PMMBORIFG
s clr
PMMSWBOR event
SVSHIFG
s
from SVSH
SVSHPE
SVMHVLRIFG
s
from SVMH
SVMHVLRPE
SVSLIFG
s
from SVSL
SVSLPE
SVMHLVLRIFG
s
from SVML
SVMLVLRPE
PMMPORIFG
s
PMMSWPOR event
WDTIFG
s
Watchdog Timer
MCLK
… .
Module
PUCs
PUC Logic
Figure 1-1. BOR/POR/PUC Reset Circuit
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1.2.1 Device Initial Conditions After System Reset
After a BOR, the initial device conditions are:
• The RST/NMI pin is configured in the reset mode. See Section 1.7 on configuring the RST/NMI pin.
• I/O pins are switched to input mode as described in the Digital I/O chapter.
• Other peripheral modules and registers are initialized as described in their respective chapters in this
manual.
• Status register (SR) is reset.
• The watchdog timer powers up active in watchdog mode.
• Program counter (PC) is loaded with the boot code address and boot code execution begins at that
address. See Section 1.9 for more information regarding the boot code. Upon completion of the boot
code, the PC is loaded with the address contained at the SYSRSTIV reset location (0FFFEh).
After a system reset, user software must initialize the device for the application requirements. The
following must occur:
• Initialize the stack pointer (SP), typically to the top of RAM.
• Initialize the watchdog to the requirements of the application.
• Configure peripheral modules to the requirements of the application.
NOTE: A device that is unprogrammed or blank is defined as having its reset vector value, residing
at memory address FFFEh, equal to FFFFh. Upon system reset of a blank device, the device
enters operating mode LPM4 automatically. See Section 1.4 for information on operating
modes and Section 1.3.6 for details on interrupt vectors.
NOTE: Some SRAM locations can be modified by the boot code (refer to Section 1.9) after a BOR
event. These SRAM locations, when available, are at SRAM locations 01CFAh through
01CFFh and 023FAh through 023FFh.
1.3
Interrupts
The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as
shown in Figure 1-2. Interrupt priorities determine what interrupt is taken when more than one interrupt is
pending simultaneously.
There are three types of interrupts:
• System reset
• (Non)maskable
• Maskable
NOTE: The types of interrupt sources available and their respective priorities can change from
device to device. See the device-specific data sheet for all interrupt sources and their
priorities.
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BOR
...
RST/NMI
BOR/POR/PUC
circuit
CPU
POR
PUC
Password violations
high priority
.. . ..
System NMI
User NMI
Module_A_int
Module_B_int
low priority
INT
NMI
GIE
Interrupt
daisy chain
and vectors
Module_C_int
Module_D_int
MAB - 6LSBs
Figure 1-2. Interrupt Priority
1.3.1 (Non)Maskable Interrupts (NMIs)
In general, NMIs are not masked by the general interrupt enable (GIE) bit. The family supports two levels
of NMIs — system NMI (SNMI) and user NMI (UNMI). The NMI sources are enabled by individual interrupt
enable bits. When an NMI interrupt is accepted, other NMIs of that level are automatically disabled to
prevent nesting of consecutive NMIs of the same level. Program execution begins at the address stored in
the NMI vector as shown in Table 1-1. To allow software backward compatibility to users of earlier
MSP430 families, the software may, but does not need to, reenable NMI sources. The block diagram for
NMI sources is shown in Figure 1-3.
A
•
•
•
UNMI interrupt can be generated by following sources:
An edge on the RST/NMI pin when configured in NMI mode
An oscillator fault occurs
An access violation to the flash memory
A
•
•
•
•
SNMI interrupt can be generated by following sources:
Power Management Module (PMM) SVML/SVMH supply voltage fault
PMM high/low side delay expiration
Vacant memory access
JTAG mailbox (JMB) event
NOTE: The number and types of NMI sources may vary from device to device. See the devicespecific data sheet for all NMI sources available.
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1.3.2 SNMI Timing
Consecutive SNMIs that occur at a higher rate than they can be handled (interrupt storm) allow the main
program to execute one instruction after the SNMI handler is finished with a RETI instruction, before the
SNMI handler is executed again. Consecutive SNMIs are not interrupted by UNMIs in this case. This
avoids a blocking behavior on high SNMI rates.
ACCV
ACCVIFG
ACCVIE
NMI
User NMI
_IRQA
PUC
RETI
NMIIFG
R
NMIIE
S
… ..
User NMI
...IFG
...IE
OSC Fault
OFIFG
OFIE
SVML
SVMLIFG
SVMLIE
System NMI
_IRQA
PUC
RETI
Del. FF
SVMH
SVMHIFG
R
SVMHIE
S
… ..
System NMI
...IFG
...IE
JMB event
SYSJMBIFG
SYSJMBIE
Figure 1-3. NMIs With Reentrance Protection
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1.3.3 Maskable Interrupts
Maskable interrupts are caused by peripherals with interrupt capability. Each maskable interrupt source
can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the
general interrupt enable (GIE) bit in the status register (SR).
Each individual peripheral interrupt is discussed in its respective module chapter in this manual.
1.3.4 Interrupt Processing
When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are
set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)maskable interrupts (NMI) to be requested.
1.3.4.1
Interrupt Acceptance
The interrupt latency is six cycles, starting with the acceptance of an interrupt request, and lasting until the
start of execution of the first instruction of the interrupt service routine, as shown in Figure 1-4. The
interrupt logic executes the following:
1. Any currently executing instruction is completed.
2. The PC, which points to the next instruction, is pushed onto the stack.
3. The SR is pushed onto the stack.
4. The interrupt with the highest priority is selected if multiple interrupts occurred during the last
instruction and are pending for service.
5. The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set
for servicing by software.
6. All bits of SR are cleared except SCG0, thereby terminating any low-power mode. Because the GIE bit
is cleared, further interrupts are disabled.
7. The content of the interrupt vector is loaded into the PC; the program continues with the interrupt
service routine at that address.
SP
Before
Interrupt
After
Interrupt
Item1
Item1
Item2
TOS
Item2
PC
SP
SR
TOS
Figure 1-4. Interrupt Processing
NOTE: Enable and Disable Interrupt
Due to the pipelined CPU architecture, the instruction following the enable interrupt
instruction (EINT) is always executed, even if an interrupt service request is pending when
the interrupts are enabled.
If the enable interrupt instruction (EINT) is immediately followed by a disable interrupt
instruction (DINT), a pending interrupt might not be serviced. Further instructions after DINT
might execute incorrectly and result in unexpected CPU execution. It is recommended to
always insert at least one instruction between EINT and DINT. Note that any alternative
instruction use that sets and immediately clears the CPU status register GIE bit must be
considered in the same fashion.
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Return From Interrupt
The interrupt handling routine terminates with the instruction:
RETI //return from an interrupt service routine
The return from the interrupt takes five cycles to execute the following actions and is illustrated in
Figure 1-5.
1. The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are
now in effect, regardless of the settings used during the interrupt service routine.
2. The PC pops from the stack and begins execution at the point where it was interrupted.
Before
After
Return From Interrupt
Item1
Item1
SP
Item2
PC
SP
SR
TOS
Item2
PC
TOS
SR
Figure 1-5. Return From Interrupt
1.3.5 Interrupt Nesting
Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine. When interrupt nesting
is enabled, any interrupt occurring during an interrupt service routine interrupts the routine, regardless of
the interrupt priorities.
1.3.6 Interrupt Vectors
The interrupt vectors are located in the address range 0FFFFh to 0FF80h, for a maximum of 64 interrupt
sources. A vector is programmed by the user and points to the start location of the corresponding interrupt
service routine. Table 1-1 is an example of the interrupt vectors available. See the device-specific data
sheet for the complete interrupt vector list.
Table 1-1. Interrupt Sources, Flags, and Vectors
System
Interrupt
Word Address
Priority
...
Reset
...
0FFFEh
...
Highest
(Non)maskable
0FFFCh
…
...
(Non)maskable
(Non)maskable
(Non)maskable
...
0FFFAh
...
…
Device specific
0FFF8h
…
...
...
...
...
...
Interrupt Source
Interrupt Flag
Reset:
power up, external reset
watchdog,
flash password
...
WDTIFG
KEYV
System NMI:
PMM
User NMI:
NMI, oscillator fault,
flash memory access
violation
Watchdog timer
WDTIFG
Maskable
...
...
...
Device specific
…
…
…
Lowest
Reserved
42
...
NMIIFG
OFIFG
ACCVIFG
Maskable
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Some interrupt enable bits, and interrupt flags, as well as, control bits for the RST/NMI pin are located in
the special function registers (SFR). The SFR are located in the peripheral address range and are byte
and word accessible. See the device-specific data sheet for the SFR configuration.
1.3.6.1
Alternate Interrupt Vectors
It is possible to use the RAM as an alternate location for the interrupt vector locations. Setting the
SYSRIVECT bit in SYSCTL causes the interrupt vectors to be remapped to the top of RAM. Once set, any
interrupt vectors to the alternate locations now residing in RAM. Because SYSRIVECT is automatically
cleared on a BOR, it is critical that the reset vector at location 0FFFEh still be available and handled
properly in firmware.
1.3.7 SYS Interrupt Vector Generators
SYS collects all system NMI (SNMI) sources, user NMI (UNMI) sources, and BOR/POR/PUC (reset)
sources of all the other modules. They are combined into three interrupt vectors. The interrupt vector
registers SYSRSTIV, SYSSNIV, SYSUNIV are used to determine which flags requested an interrupt or a
reset. The interrupt with the highest priority of a group, when enabled, generates a number in the
corresponding SYSRSTIV, SYSSNIV, SYSUNIV register. This number can be directly added to the
program counter, causing a branch to the appropriate portion of the interrupt service routine. Disabled
interrupts do not affect the SYSRSTIV, SYSSNIV, SYSUNIV values. Reading SYSRSTIV, SYSSNIV,
SYSUNIV register automatically resets the highest pending interrupt flag of that register. If another
interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. Writing to
the SYSRSTIV, SYSSNIV, SYSUNIV register automatically resets all pending interrupt flags of the group.
1.3.7.1
SYSSNIV Software Example
The following software example shows the recommended use of SYSSNIV. The SYSSNIV value is added
to the PC to automatically jump to the appropriate routine. For SYSRSTIV and SYSUNIV, a similar
software approach can be used. The following is an example for a generic device. Vectors can change in
priority for a given device. The device specific data sheet should be referenced for the vector locations. All
vectors should be coded symbolically to allow for easy portability of code.
SNI_ISR:
ADD
RETI
JMP
JMP
JMP
JMP
JMP
JMP
JMBO_ISR:
...
RETI
SVML_ISR:
...
RETI
SVMH_ISR:
...
RETI
DLYL_ISR:
...
RETI
DLYH_ISR:
...
RETI
VMA_ISR:
...
RETI
JMBI_ISR:
...
RETI
&SYSSNIV,PC ; Add offset to jump table
; Vector 0: No interrupt
SVML_ISR
; Vector 2: SVMLIFG
SVMH_ISR
; Vector 4: SVMHIFG
DLYL_ISR
; Vector 6: SVSMLDLYIFG
DLYH_ISR
; Vector 8: SVSMHDLYIFG
VMA_ISR
; Vector 10: VMAIFG
JMBI_ISR
; Vector 12: JMBINIFG
; Vector 14: JMBOUTIFG
; Task_E starts here
; Return
; Vector 2
; Task_2 starts here
; Return
; Vector 4
; Task_4 starts here
; Return
; Vector 6
; Task_6 starts here
; Return
; Vector 8
; Task_8 starts here
; Return
; Vector A
; Task_A starts here
; Return
; Vector C
; Task_C starts here
; Return
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SYSBERRIV Bus Error Interrupt Vector Generator
Some devices, for example those that contain the USB module, include an additional system interrupt
vector generator, SYSBERRIV. In general, any type of system related bus error or timeout error is
associated with a user NMI event. Upon this event, the SYSUNIV contains an offset value corresponding
to a bus error event (BUSIFG). This offset can be added to the PC to automatically jump to the
appropriate NMI routine. Similarly, SYSBERRIV also contains an offset value corresponding to which
specific event caused the bus error event. The offset value in SYSBERRIV can be added inside the NMI
routine to automatically jump to the appropriate routine. In this way, the SYSBERRIV can be thought of as
an extension to the user NMI vectors.
1.4
Operating Modes
The MSP430 family is designed for ultralow-power applications and uses different operating modes shown
in Figure 1-6.
The operating modes take into account three different needs:
• Ultralow power
• Speed and data throughput
• Minimization of individual peripheral current consumption
The low-power modes LPM0 through LPM4 are configured with the CPUOFF, OSCOFF, SCG0, and
SCG1 bits in the SR. The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control
bits in the SR is that the present operating mode is saved onto the stack during an interrupt service
routine. Program flow returns to the previous operating mode if the saved SR value is not altered during
the interrupt service routine. Program flow can be returned to a different operating mode by manipulating
the saved SR value on the stack inside of the interrupt service routine. When setting any of the modecontrol bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled
clock are disabled until the clock becomes active. Peripherals may also be disabled with their individual
control register settings. All I/O port pins and RAM/registers are unchanged. Wakeup from LPM0 through
LPM4 is possible through all enabled interrupts.
When LPMx.5 (LPM3.5 or LPM4.5) is entered, the voltage regulator of the Power Management Module
(PMM) is disabled. All RAM and register contents are lost. Although the I/O register contents are lost, the
I/O pin states are locked upon LPMx.5 entry. See the Digital I/O chapter for further details. Wakeup from
LPM4.5 is possible via a power sequence, a RST event, or from specific I/O. Wakeup from LPM3.5 is
possible via a power sequence, a RST event, RTC event, or from specific I/O.
NOTE: LPM3.5 and LPM4.5 low power modes are not available on all devices. See the device
specific data sheet to see which LPMx.5 power modes are available.
NOTE: The TEST/SBWTCK pin is used for interfacing to the development tools via Spy-Bi-Wire and
JTAG. When the TEST/SBWTCK pin is high, wakeup times from LPM2, LPM3, and LPM4
may be different compared to when TEST/SBWTCK is low. Pay careful attention to the realtime behavior when exiting from LPM2, LPM3, and LPM4 with the device connected to a
development tool (for example, MSP-FET430UIF). See the PMM chapter for details.
44
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From active mode
LPMx.5:
VCORE = off
(all modules off
optional RTC)
Brownout
fault
RTC wakeup
Port wakeup
Security
violation
RST/NMI
(Reset wakeup)
RST/NMI ‡
(Reset event)
DoBOR
event
BOR
SVMH OVP-fault
Load calibration data
SVSH fault
SVML OVP-fault
DoPOR event
SVSL fault
POR
WDT Active
Time expired, Overflow
PMM
Password violation
WDT Active
Password violation
PUC
Flash
Password violation
Peripheral area fetch
CPUOFF=1
OSCOFF=0
SCG0=0
SCG1=0
LPM0:
CPU/MCLK = off
FLL = on
ACLK = on
VCORE = on
Active Mode: CPU is Active
Various Modules are active
PMMREGOFF = 1
to LPMx.5
†
†
†
†
†
CPUOFF=1
OSCOFF=0
SCG0=1
SCG1=0
CPUOFF=1
OSCOFF=0
SCG0=0
SCG1=1
LPM1:
CPU/MCLK = off
FLL = off
ACLK = on
VCORE = on
CPUOFF=1
OSCOFF=0
SCG0=1
SCG1=1
LPM2:
CPU/MCLK = off
FLL = off
ACLK = on
VCORE = on
CPUOFF=1
OSCOFF=1
SCG0=1
SCG1=1
LPM4:
CPU/MCLK = off
FLL = off
ACLK = off
VCORE = on
LPM3:
CPU/MCLK = off
FLL = off
ACLK = on
VCORE = on
Events
Operating modes/Reset phases
Arbitrary transitions
† Any enabled interrupt and NMI performs this transition
‡ An enabled reset always restarts the device
Figure 1-6. Operation Modes
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Table 1-2. Operation Modes
SCG1
0
(1)
SCG0
0
OSCOFF
CPUOFF
(1)
(1)
Mode
CPU and Clocks Status
0
0
Active
CPU, MCLK are active.
(2)
ACLK is active. SMCLK optionally active (SMCLKOFF = 0).
DCO is enabled if sources ACLK, MCLK, or SMCLK (SMCLKOFF = 0).
DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK
(SMCLKOFF = 0).
FLL is enabled if DCO is enabled.
0
0
0
1
LPM0
CPU, MCLK are disabled.
ACLK is active. SMCLK optionally active (SMCLKOFF = 0).
DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0).
DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK
(SMCLKOFF = 0).
FLL is enabled if DCO is enabled.
0
1
0
1
LPM1
CPU, MCLK are disabled.
ACLK is active. SMCLK optionally active (SMCLKOFF = 0).
DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0).
DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK
(SMCLKOFF = 0).
FLL is disabled.
1
0
0
1
LPM2
CPU, MCLK are disabled.
ACLK is active. SMCLK is disabled.
DCO is enabled if sources ACLK.
FLL is disabled.
1
1
0
1
LPM3
CPU, MCLK are disabled.
ACLK is active. SMCLK is disabled.
DCO is enabled if sources ACLK.
FLL is disabled.
(1)
(2)
(3)
46
1
1
1
1
LPM4
CPU and all clocks are disabled.
1
1
1
1
LPM3.5 (3)
When PMMREGOFF = 1, regulator is disabled. No memory retention. In this
mode, RTC operation is possible when configured properly. See the RTC module
for further details.
1
1
1
1
LPM4.5 (3)
When PMMREGOFF = 1, regulator is disabled. No memory retention. In this
mode, all clock sources are disabled; that is, no RTC operation is possible.
This bit is automatically reset when exiting low power modes. Please refer to Section 1.4.1 for details.
The low-power modes and, hence, the system clocks can be affected by the clock request system. See the UCS chapter for
details.
LPM3.5 and LPM4.5 modes are not available on all devices. See the device-specific data sheet for availability.
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1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4
An enabled interrupt event wakes the device from low-power operating modes LPM0 through LPM4. The
program flow for exiting LPM0 through LPM4 is:
• Enter interrupt service routine
– The PC and SR are stored on the stack.
– The CPUOFF, SCG1, and OSCOFF bits are automatically reset.
• Options for returning from the interrupt service routine
– The original SR is popped from the stack, restoring the previous operating mode.
– The SR bits stored on the stack can be modified within the interrupt service routine returning to a
different operating mode when the RETI instruction is executed.
; Enter LPM0 Example
BIS
#GIE+CPUOFF,SR
; ...
;
; Exit LPM0 Interrupt Service Routine
BIC
#CPUOFF,0(SP)
RETI
; Enter LPM3 Example
BIS
#GIE+CPUOFF+SCG1+SCG0,SR
; ...
;
; Exit LPM3 Interrupt Service Routine
BIC
#CPUOFF+SCG1+SCG0,0(SP)
RETI
; Enter LPM4 Example
BIS
#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR
; ...
;
; Exit LPM4 Interrupt Service Routine
BIC
#CPUOFF+OSCOFF+SCG1+SCG0,0(SP)
RETI
; Enter LPM0
; Program stops here
; Exit LPM0 on RETI
; Enter LPM3
; Program stops here
; Exit LPM3 on RETI
; Enter LPM4
; Program stops here
; Exit LPM4 on RETI
1.4.2 Entering and Exiting Low-Power Modes LPMx.5
LPMx.5 entry and exit is handled differently than the other low power modes. LPMx.5, when used
properly, gives the lowest power consumption available on a device. To achieve this, entry to LPMx.5
disables the LDO of the PMM module, removing the supply voltage from the core of the device. Since the
supply voltage is removed from the core, all register contents, as well as, SRAM contents are lost. Exit
from LPMx.5 causes a BOR event, which forces a complete reset of the system. Therefore, it is the
application's responsibility to properly reconfigure the device upon exit from LPMx.5.
The wakeup time from LPMx.5 is significantly longer than the wakeup time from the other power modes
(please see the device specific data sheet). This is primarily due to the facts that after exit from LPMx.5,
time is required for the core voltage supply to be regenerated, as well as, boot code execution to complete
before the application code can begin. Therefore, the usage of LPMx.5 is restricted to very low duty cycle
events.
There are two LPMx.5 power modes, LPM3.5 and LPM4.5. Not all of these are available on all devices.
See the device specific data sheet to see which LPMx.5 power modes are available. LPM4.5 allows for
the lowest power consumption available. No clock sources are active during LPM4.5. LPM3.5 is similar to
LPM4.5, but has the additional capability of having a RTC mode available. In addition to the wakeup
events possible in LPM4.5, RTC wakeup events are also possible in LPM3.5.
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The program flow for entering LPMx.5 is:
1. Configure I/O appropriately. See the Digital I/O chapter for complete details on configuring I/O for
LPMx.5.
• Set all ports to general purpose I/O. Configure each port to ensure no floating inputs based on the
application requirements.
• If wakeup from I/O is desired, configure input ports with interrupt capability appropriately.
2. If LPM3.5 is available, and desired, enable RTC operation. In addition, configure any RTC interrupts, if
desired for LPM3.5 wakeup event. See the RTC Overview chapter for complete details.
3. Ensure clock system settings allow LPMx.5 entry according to Table 3-1 in UCS chapter.
4. Enter LPMx.5 by setting PMMREGOFF=1 and LPM4 status register bits. The following code example
shows how to enter LPMx.5 mode. See the PMM chapter for further details.
; Enter LPMx.5 Example
MOV.B #PMMPW_H, &PMMCTL0_H
BIS.B #PMMREGOFF, &PMMCTL0_L
BIS
#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR
; Open PMM registers for write
;
; Enter LPMx.5 when PMMREGOFF is set.
NOTE: It is not possible to wakeup from LPMx.5 if its respective interrupt flag is already asserted. It
is recommended that the respective flag be cleared prior to entering LPMx.5. It is also
recommended that GIE = 1 be set prior to entry into LPMx.5. Any pending flags in this case
could then be serviced prior to LPMx.5 entry.
Although it is recommended to set GIE = 1 prior to entering LPMx.5, it is not required. Device
wakeup from LPMx.5 with an enabled wakeup function will still cause the device to wake up
from LPMx.5 even with GIE = 0. If GIE = 0 prior to LPMx.5, additional care may be required.
Should the respective interrupt event should occur during LPMx.5 entry, the device may not
recognize this or any future interrupt wakeup event on this function.
Exit from LPMx.5 is possible with a RST event, a power on cycle, or via specific I/O. Any exit from LPMx.5
causes a BOR. Program execution continues at the location stored in the system reset vector location
0FFFEh after execution of the boot code. The PMMLPM5IFG bit inside the PMM module is set indicating
that the device was in LPMx.5 prior to the wakeup event. Additionally, SYSRSTIV = 08h which can be
used to generate an efficient reset handler routine. During LPMx.5, all I/O pin conditions are automatically
locked to the current state. Upon exit from LPMx.5, the I/O pin conditions remain locked until the
application unlocks them. See the Digital I/O chapter for complete details. If LPM3.5 was in effect, RTC
operation continues uninterrupted upon wake-up. The program flow for exiting LPMx.5 is:
• Enter system reset service routine
– Reconfigure system as required for the application.
– Reconfigure I/O as required for the application.
1.4.3 Extended Time in Low-Power Modes
The temperature coefficient of the DCO should be considered when the DCO is disabled for extended lowpower mode periods. If the temperature changes significantly, the DCO frequency at wakeup may be
significantly different from when the low-power mode was entered and may be out of the specified
operating range. To avoid this, the DCO can be set to it lowest value before entering the low-power mode
for extended periods of time where temperature can change.
; Enter LPM4 Example with lowest DCO Setting
BIC
#SCG0, SR
MOV
#0100h, &UCSCTL0
modulation.
BIC
#DCORSEL2+DCORSEL1+DCORSEL0,&UCSCTL1
BIS
#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR
; ...
;
; Interrupt Service Routine
BIC
#CPUOFF+OSCOFF+SCG1+SCG0,0(SR)
48
; Disable FLL
; Set DCO tap to first tap, clear
; Lowest DCORSEL
; Enter LPM4
; Program stops
; Exit LPM4 on RETI
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Principles for Low-Power Applications
1.5
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Principles for Low-Power Applications
Often, the most important factor for reducing power consumption is using the device clock system to
maximize the time in LPM3 or LPM4 modes whenever possible.
• Use interrupts to wake the processor and control program flow.
• Peripherals should be switched on only when needed.
• Use low-power integrated peripheral modules in place of software driven functions. For example,
Timer_A and Timer_B can automatically generate PWM and capture external timing with no CPU
resources.
• Calculated branching and fast table look-ups should be used in place of flag polling and long software
calculations.
• Avoid frequent subroutine and function calls due to overhead.
• For longer software routines, single-cycle CPU registers should be used.
• Overwrite RAM control register RCCTL0 with all not available and unused segments set to powered
down (= 1). For information about used RAM segments see the device-specific data sheet.
If the application has low duty cycle, slow response time events, maximizing time in LPMx.5 can further
reduce power consumption significantly.
1.6
Connection of Unused Pins
The correct termination of all unused pins is listed in Table 1-3.
Table 1-3. Connection of Unused Pins (1)
Pin
Potential
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
XIN
DVSS
For dedicated XIN pins only. XIN pins with shared GPIO functions should be
programmed to GPIO and follow Px.0 to Px.7 recommendations.
XOUT
Open
For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be
programmed to GPIO and follow Px.0 to Px.7 recommendations.
XT2IN
DVSS
For dedicated XT2IN pins only. XT2IN pins with shared GPIO functions should be
programmed to GPIO and follow Px.0 to Px.7 recommendations.
XT2OUT
Open
For dedicated XT2OUT pins only. XT2OUT pins with shared GPIO functions should
be programmed to GPIO and follow Px.0 to Px.7 recommendations.
LCDCAP
DVSS
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown (2)
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general purpose I/O function (PJ.x). If not being
used, these should be switched to port function, output direction (PJDIR.n = 1).
When used as JTAG pins, these pins should remain open.
TEST
Open
This pin always has an internal pulldown enabled.
GUARD
DVCC
If radio module is not used in the application
R_BIAS
DVSS
If radio module is not used in the application
AVCC_RF
DVCC
If radio module is not used in the application
RF_N
Open
If radio module is not used in the application
RF_P
Open
If radio module is not used in the application
RF_XIN
DVSS
If radio module is not used in the application
RF_XOUT
Open
If radio module is not used in the application
V18
Open
For USB devices only when USB module is not being used in the application
(1)
(2)
50
Comment
Any unused pin with a secondary function that is shared with general purpose I/O should follow the Px.0 to Px.7 unused pin
connection guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4wire JTAG mode with TI tools such as FET interfaces or GANG programmers.
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Table 1-3. Connection of Unused Pins (1) (continued)
Pin
Potential
Comment
PUR (3)
DVSS
For USB devices only when USB module is not being used in the application
VUSB
Open
For USB devices only when USB module is not being used in the application
PU.0/DP
PU.1/DM
Open
For USB devices only when USB module is not being used in the application
VBUS, VSSU
DVSS
For USB devices only when USB module is not being used in the application
LDOI
DVSS
For devices with LDO-PWR module when not being used in the application.
LDOO
Open
For devices with LDO-PWR module when not being used in the application.
(3)
1.7
The default USB BSL evaluates the state of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is
invoked. Therefore, unless invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is
never used. A 1-MΩ resistor to ground is recommended.
Reset Pin (RST/NMI) Configuration
The reset pin can be configured as a reset function (default) or as an NMI function via the Special
Function Register (SFR), SFRRPCR. Setting SYSNMI causes the RST/NMI pin to be configured as an
external NMI source. The external NMI is edge sensitive, and its edge is selectable by SYSNMIIES.
Setting the NMIIE enables the interrupt of the external NMI. Upon an external NMI event, the NMIIFG is
set.
The RST/NMI pin can have either a pullup or pulldown present or not. SYSRSTUP selects either pullup or
pulldown and SYSRSTRE causes the pullup or pulldown to be enabled or not. If the RST/NMI pin is
unused, it is required to have either the internal pullup selected and enabled or an external resistor
connected to the RST/NMI pin as shown in Table 1-3.
NOTE: All devices except the MSP430F543x (non-A devices) have the internal pullup enabled. In
this case, no external pullup resistor is required.
1.8
Configuring JTAG pins
The JTAG pins are shared with general purpose I/O pins. There are several ways that the JTAG pins can
be selected for four wire JTAG mode via software. Normally, upon a BOR, SYSJTAGPIN is cleared. With
SYSJTAGPIN cleared, the JTAG are configured as general-purpose I/O. See the Digital I/O chapter for
details on controlling the JTAG pins as general purpose I/O. If SYSJTAG = 1, the JTAG pins are
configured to four wire JTAG mode and remain in this mode until another BOR condition occurs.
Therefore, SYSJTAGPIN is a write only once function. Clearing it by software is not possible, and the
device does not change from four wire JTAG mode to general purpose I/O.
1.9
Boot Code
The boot code is always executed after a BOR. The boot code loads factory stored calibration values of
the oscillator and reference voltages. In addition, it checks for the presence of a user-defined boot strap
loader (BSL).
1.10 Bootstrap Loader (BSL)
The BSL is software that is executed after start-up when a certain BSL entry condition is applied. The BSL
enables the user to communicate with the embedded memory in the microcontroller during the prototyping
phase, final production, and in service. All memory mapped resources, the programmable memory (flash
memory), the data memory (RAM), and the peripherals, can be modified by the BSL as required. The user
can define custom BSL code for flash-based devices and protect it against erasure and unintentional or
unauthorized access.
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On devices without USB, a basic BSL program is provided by TI. This supports the commonly used UART
protocol with RS232 interfacing, allowing flexible use of both hardware and software. To use the BSL, a
specific BSL entry sequence must be applied to specific device pins. The correct entry sequence causes
SYSBSLIND to be set. An added sequence of commands initiates the desired function. A boot-loading
session can be exited by continuing operation at a defined user program address or by applying the
standard reset sequence. Access to the device memory via the BSL is protected against misuse by a
user-defined password. Devices with USB have a USB based BSL program provided by TI. For more
details, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319) at
www.ti.com/msp430.
The amount of BSL memory that is available is device specific. The BSL memory size is organized into
segments and can be set using the SYSBSLSIZE bits. See the device specific data sheet for the number
and size of the segments available. It is possible to assign a small amount of RAM to the allocated BSL
memory. Setting SYSBSLR allocates the lowest 16 bytes of RAM for the BSL. When the BSL memory is
protected, access to these RAM locations is only possible from within the protected BSL memory
segments.
It may be desirable in some BSL applications to only allow changing of the Power Management Module
settings from the protected BSL segments. This is possible with the SYSPMMPE bit. Normally, this bit is
cleared and allows access of the PMM control registers from any memory location. Setting SYSPMMPE,
allows access to the PMM control registers only from the protected BSL memory. Once set, SYSPMMPE
can only be cleared by a BOR event.
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Memory Map – Uses and Abilities
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1.11 Memory Map – Uses and Abilities
This memory map represents the MSP430F5438 device. Though the address ranges differs from device
to device, overall behavior remains the same.
Can generate NMI on read/write/fetch
Generates PUC on fetch access
Protectable for read/write accesses
Always able to access PMM registers from (1); Mass erase by user possible
Mass erase by user possible
Bank erase by user possible
Segment erase by user possible
Address Range
Name and Usage
00000h-00FFFh
Peripherals with gaps
00000h-000FFh
Reserved for system extension
00100h-00FEFh
Peripherals
x
00FF0h-00FF3h
Descriptor type (2)
x
00FF4h-00FF7h
Start address of descriptor structure
x
01000h-011FFh
BSL 0
x
x
01200h-013FFh
BSL 1
x
x
01400h-015FFh
BSL 2
x
01600h-017FFh
BSL 3
x
017FCh-017FFh
Info D
x
01880h-018FFh
Info C
x
01900h-0197Fh
Info B
x
01980h-019FFh
Info A
x
01A00h-01A7Fh
Device Descriptor Table
01C00h-05BFFh
RAM 16 KB
05B80-05BFFh
0FF80h-0FFFFh
(2)
(3)
x
x
x
BSL Signature Location
01800h-0187Fh
05C00h-0FFFFh
(1)
Properties
x
Alternate Interrupt Vectors
Program
x
x (1)
x
x
x
x
Interrupt Vectors
10000h-45BFFh
Program
45C00h-FFFFFh
Vacant
x (3)
Access rights are separately programmable for SYS and PMM.
Fixed ID for all MSP430 devices. See Section 1.13.1 for further details.
On vacant memory space, the value 03FFFh is driven on the data bus.
1.11.1 Vacant Memory Space
Vacant memory is non-existent memory space. Accesses to vacant memory space generate a system
(non)maskable interrupt (SNMI) when enabled (VMAIE = 1). Reads from vacant memory results in the
value 3FFFh. In the case of a fetch, this is taken as JMP $. Fetch accesses from vacant peripheral space
result in a PUC. After the boot code is executed, it behaves like vacant memory space and also causes an
NMI on access.
1.11.2 JTAG Lock Mechanism via the Electronic Fuse
A device can be protected from unauthorized access by disabling the JTAG and SBW interface. This is
achieved by programming the electronic fuse. Programming the electronic fuse, completely disables the
debug and access capabilities associated with the JTAG and Spy-Bi-Wire interface. The JTAG is locked
by programming a certain signature into the device's' flash memory at dedicated addresses. The JTAG
security lock key resides at the end of the bootstrap loader (BSL) memory at addresses 17FCh through
17FFh. Anything other than 0h or FFFFFFFFh programmed to these addresses locks the JTAG interface.
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JTAG Mailbox (JMB) System
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All of the 5xx MSP430 devices come with a preprogrammed BSL (TI-BSL) code that, by default, protects
itself from unintended erase and write access. This is done by setting SYSBSLPE in the SYSBSLC
register. Since the JTAG security lock key resides in the BSL memory address range, appropriate action
must be taken to unprotect the BSL memory area before programming the protection key. For more
details on the electronic fuse see the MSP430 Programming Via the JTAG Interface User's Guide
(SLAU320) at www.ti.com/msp430.
Some JTAG commands are still possible after the device is secured, including the BYPASS command
(see IEEE1149-2001 Standard) and the JMB_EXCHANGE command which allows access to the JTAG
Mailbox System (see Section 1.12 for details).
NOTE: If a device has been protected, Texas Instruments cannot access the device for a customer
return. Access is only possible if a BSL is provided with its corresponding key or an unlock
mechanism is provided by the customer.
1.12 JTAG Mailbox (JMB) System
The SYS module provides the capability to exchange user data via the regular JTAG test/debug interface.
The idea behind the JMB is to have a direct interface to the CPU during debugging, programming, and
test that is identical for all '430 devices of this family and uses only few or no user application resources.
The JTAG interface was chosen because it is available on all '430 devices and is a dedicated resource for
debugging, programming and test.
Applications of the JMB are:
• Providing entry password for device lock/unlock protection
• Run-time data exchange (RTDX)
1.12.1 JMB Configuration
The JMB supports two transfer modes, 16-bit and 32-bit. Setting JMBMODE enables 32-bit transfer mode.
Clearing JMBMODE enables 16-bit transfer mode.
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox
Two 16-bit registers are available for outgoing messages to the JTAG port. JMBOUT0 is only used when
using 16-bit transfer mode (JMBMODE = 0). JMBOUT1 is used in addition to JMBOUT0 when using 32-bit
transfer mode (JMBMODE = 1). When the application wishes to send a message to the JTAG port, it
writes data to JMBOUT0 for 16-bit mode, or JMBOUT0 and JMBOUT1 for 32-bit mode.
JMBOUT0FG and JMBOUT1FG are read only flags that indicate the status of JMBOUT0 and JMBOUT1,
respectively. When JMBOUT0FG is set, JMBOUT0 has been read by the JTAG port and is ready to
receive new data. When JMBOUT0FG is reset, the JMBOUT0 is not ready to receive new data.
JMBOUT1FG behaves similarly.
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox
Two 16-bit registers are available for incoming messages from the JTAG port. Only JMBIN0 is used when
in 16-bit transfer mode (JMBMODE = 0). JMBIN1 is used in addition to JMBIN0 when using 32-bit transfer
mode (JMBMODE = 1). When the JTAG port wishes to send a message to the application, it writes data
to JMBIN0 for 16-bit mode, or JMBIN0 and JMBIN1 for 32-bit mode.
JMBIN0FG and JMBIN1FG are flags that indicate the status of JMBIN0 and JMBIN1, respectively. When
JMBIN0FG is set, JMBIN0 has data that is available for reading. When JMBIN0FG is reset, no new data is
available in JMBIN0. JMBIN1FG behaves similarly.
JMBIN0FG and JMBIN1FG can be configured to clear automatically by clearing JMBCLR0OFF and
JMBCLR1OFF, respectively. Otherwise, these flags must be cleared by software.
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1.12.4 JMB NMI Usage
The JMB handshake mechanism can be configured to use interrupts to avoid unnecessary polling if
desired. In 16-bit mode, JMBOUTIFG is set when JMBOUT0 has been read by the JTAG port and is
ready to receive data. In 32-bit mode, JMBOUTIFG is set when both JMBOUT0 and JMBOUT1 has been
read by the JTAG port and are ready to receive data. If JMBOUTIE is set, these events cause a system
NMI. In 16-bit mode, JMBOUTIFG is cleared automatically when data is written to JMBOUT0. In 32-bit
mode, JMBOUTIFG Is cleared automatically when data is written to both JMBOUT0 and JMBOUT1. In
addition, the JMBOUTIFG can be cleared when reading SYSSNIV. Clearing JMBOUTIE disables the NMI
interrupt.
In 16-bit mode, JMBINIFG is set when JMBIN0 is available for reading. In 32-bit mode, JMBINIFG is set
when both JMBIN0 and JMBIN1 are available for reading. If JMBOUTIE is set, these events cause a
system NMI. In 16-bit mode, JMBINIFG is cleared automatically when JMBIN0 is read. In 32-bit mode,
JMBINIFG Is cleared automatically when both JMBIN0 and JMBIN1 are read. In addition, the JMBINIFG
can be cleared when reading SYSSNIV. Clearing JMBINIE disables the NMI interrupt.
1.13 Device Descriptor Table
Each device provides a data structure in memory that allows an unambiguous identification of the device,
as well as, a more detailed description of the available modules on a given device. SYS provides this
information and can be used by device-adaptive SW tools and libraries to clearly identify a particular
device and all modules and capabilities contained within it. The validity of the device descriptor can be
verified by cyclic redundancy check (CRC).Figure 1-7 shows the logical order and structure of the device
descriptor table. The complete device descriptor table and its contents can be found in the device specific
data sheet.
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Descriptor start address
Info_length
CRC_length
Information block
CRC_value
DeviceID
Firmware revision
Device ID and Revision
Information
Hardware revision
Tag 1
Len 1
Value field 1
First TLV entry
(optional)
Additional TLV entries
(optional)
Tag N
Len N
Value field N
Final TLV entry
(optional)
Figure 1-7. Devices Descriptor Table
1.13.1 Identifying Device Type
The value read at address location 00FF0h identifies the family branch of the device. All values starting
with 80h indicate a hierarchical structure consisting of the information block and a TLV tag-length-value
(TLV) structure containing the various descriptors. Any other value than 80h read at address location
00FF0h indicates the device is of an older family and contains a flat descriptor beginning at location
0FF0h. The information block, shown in Figure 1-7 contains the device ID, die revisions, firmware
revisions, and other manufacturer and tool related information. The descriptors contains information about
the available peripherals, their subtypes and addresses and provides the information required to build
adaptive hardware drivers for operating systems.
The length of the descriptors represented by Info_length is computed as follows:
Length = 2Info_length in 32-bit words
(1)
For example, if Info_length = 5, then the length of the descriptors equals 128 bytes.
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1.13.2 TLV Descriptors
The TLV descriptors follow the information block. Because the information block is always a fixed length,
the start location of the TLV descriptors is fixed for a given device family. For the MSP430x5xx family, this
location is 01A08h. See the device-specific data sheet for the complete TLV structure and what
descriptors are available.
The TLV descriptors are unique to their respective TLV block and are always followed by the descriptor
block length.
Each TLV descriptor contains a tag field which identifies the descriptor type. Table 1-4 shows the currently
supported tags.
Table 1-4. Tag Values
Short Name
Value
Description
LDTAG
01h
Legacy descriptor (1xx, 2xx, 4xx families)
PDTAG
02h
Peripheral discovery descriptor
Reserved
03h
Future usage
Reserved
04h
Future usage
Blank descriptor
BLANK
05h
Reserved
06h
Future usage
ADCCAL
11h
ADC calibration
REFCAL
12h
REF calibration
Reserved
13h - FDh
Future usage
TAGEXT
FEh
Tag extender
Each tag field is unique to its respective descriptor and is always followed by a length field. The length
field is one byte if the tag value is 01h through 0FDh and represents the length of the descriptor in bytes.
If the tag value equals 0FEh (TAGEXT), the next byte extends the tag values, and the following two bytes
represent the length of the descriptor in bytes. In this way, a user can search through the TLV descriptor
table for a particular tag value, using a routine similar to below written in pseudo code:
// Identify the descriptor ID (d_ID_value) for the TLV descriptor of interest:
descriptor_address = TLV_START address;
while ( value at descriptor_address != d_ID_value && descriptor_address != TLV_TAGEND &&
descriptor_address < TLV_END)
{
// Point to next descriptor
descriptor_address = descriptor_address + (length of the current TLV block) + 2;
}
if (value at descriptor_address == d_ID_value) {
// Appropriate TLV decriptor has been found!
Return length of descriptor & descriptor_address as the location of the TLV descriptor
} else {
// No TLV descriptor found with a matching d_ID_value
Return a failing condition
}
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1.13.3 Peripheral Discovery Descriptor
This descriptor type can describe concatenated or distributed memory or peripheral mappings, as well as,
the number of interrupt vectors and their order. The peripheral discovery descriptor has tag value 02h
(PDTAG). Table 1-5 shows the structure of the peripheral discovery descriptor.
NOTE: Peripheral Discovery Descriptor is not available in every device. See the Device Descriptors
section in the device-specific data sheet for the availability and details on Peripheral
Discovery Descriptor.
Table 1-5. Peripheral Discovery Descriptor
Element
Size (bytes)
Comments
memory entry 1
2
Optional
memory entry 2
2
Optional
...
2
Optional
delimiter (00h)
1
Mandatory
peripheral count
1
Mandatory
peripheral entry 1
2
Optional
peripheral entry 2
2
Optional
...
2
Optional
Interrupt priority N-3
1
Optional
Interrupt priority N-4
1
Optional
...
1
Optional
delimiter (00h)
1
Mandatory
The structures for a memory entry and peripheral entry are shown below. A memory entry consists of two
bytes (one word). Table 1-6 shows the individual bit fields of a memory entry word and their respective
meanings. Similarly, a peripheral entry consists of two bytes (one word). Table 1-7 shows the individual bit
fields of a peripheral entry word and their respective meanings.
Table 1-6. Values for Memory Entry
Bit fields
[15:13]
Memory type
58
[12:9]
Size
000: None
0000: 0 B
001: RAM
0001: 128 B
[8]
[7]
[6:0]
More
Unit Size
Address value
0: End Entry
0: 0200h
0000000
1: More Entries
1: 010000h
0000001
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Table 1-6. Values for Memory Entry (continued)
Bit fields
[15:13]
Memory type
[12:9]
[8]
[7]
[6:0]
Size
More
Unit Size
Address value
010: EEPROM
0010: 256 B
0000010
011: Reserved
0011: 512 B
0000011
100: FLASH
0100: 1 KB
0000100
101: ROM
0101: 2KB
0000101
110: MemType
appended
0110: 4 KB
0000110
111: Undefined
0111: 8 KB
0000111
1000: 16 KB
0001000
1001: 32 KB
0001001
1010: 64 KB
0001010
1011: 128 KB
0001011
1100: 256 KB
0001100
1101: 512 KB
...
1110: Size
appended
...
1111: Undefined
1111111
Table 1-7. Values for Peripheral Entry
Bit fields
[15:8]
[7]
[6:0]
UnitSize
AdrVal
Any PID
0: 010h
0000000
Any PID
1: 0800h
0000001
Peripheral ID (PID)
(1)
(1)
Any PID
0000010
Any PID
0000011
Any PID
0000100
Any PID
0000101
Any PID
...
Any PID
...
Any PID
1111111
The Peripheral IDs are listed in Table 1-8. This is not a complete list, but shown as an example.
Table 1-8. Peripheral IDs (1)
(1)
Peripheral or Module
PID
No Module
00h
WDT
01h
SFR
02h
UCS
03h
SYS
04h
PMM
05h
Flash Controller
08h
CRC16
09h
Port 1, 2
51h
This table is not a complete list of all peripheral IDs available on a device, but is shown here for
illustrative purposes only.
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Table 1-8. Peripheral IDs (1) (continued)
60
Peripheral or Module
PID
Port 3, 4
52h
Port 5, 6
53h
Port 7, 8
54h
Port 9, 10
55h
Port J
5Fh
Timer A0
81h
Timer A1
82h
Special info appended
FEh
Undefined module
FFh
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Table 1-9 shows a simple example for a peripheral discovery descriptor of a hypothetical device:
Table 1-9. Sample Peripheral Discovery Descriptor
Hex
Binary
Entry type
Description
030h, 0Eh
001_1000_ 0_0_0001110
memory
RAM 16 KB; Start address = 01C00h (0Eh * 0200h) (1)
09Bh, 02Eh
100_1011_0_0_0101110
memory
FLASH 128 KB Start address = 05C00h (2Eh * 0200h)
00h
0000_0000_0000_0000
delimiter
No more memory entries
0Fh
0000_1111
peripheral count
Peripheral count = 15
02h, 10h
00000010_0_0010000
peripheral
SFR at address = 0100h (10h * 10h)
01h, 01h
00000001_0_0000001
peripheral
WDT at address = 0110h (0100h + 10h)
05h, 01h
00000101_0_0000001
peripheral
PMM at address = 0120h (0110h + 10h)
03h, 01h
00000011_0_0000001
peripheral
UCS at address = 0130h (0120h + 10h)
08h, 01h
00001000_0_0000001
peripheral
FLCTL at address = 0140h (0130h + 10h)
09h, 01h
00001001_0_0000001
peripheral
CRC16 at address = 0150h (0140h + 10h)
04h, 01h
00000100_0_0000001
peripheral
SYS at address = 0160h (0150h + 10h)
51h, 0Ah
01010001_0_0001010
peripheral
Port 1, 2 at address = 0200h (0160h + 10h * 10h)
52h, 02h
01010010_0_0000010
peripheral
Port 3, 4 at address = 0220h (0200h + 02h * 10h)
53h, 02h
01010011_0_0000010
peripheral
Port 5, 6 at address = 0240h (0220h + 02h * 10h)
54h, 02h
01010100_0_0000010
peripheral
Port 7, 8 at address = 0260h (0240h + 02h * 10h)
55h, 02h
01010101_0_0000010
peripheral
Port 9, 10 at address = 0280h (0260h + 02h * 10h)
5Fh, 0Ah
01011111_0_0001010
peripheral
Port J at address = 0320h (0280h + 0Ah * 10h)
81h, 02h
10000001_0_0000010
peripheral
Timer A0 at address = 0340h (0320h + 02h * 10h)
82h, 04h
10000010_0_0000100
peripheral
Timer A1 at address = 0380h (0340h + 04h * 10h)
–
No appended entries
SYSRSTIV @0FFFEh (implied)
SYSSNIV @0FFFC (implied)
SYSUNIV @ 0FFFA (implied)
(1)
81h
1000_0001
interrupt
TA0 CCR0 @ 0FFF8
81h
1000_0001
interrupt
TA0 CCR1, CCR1, TA0IFG@ 0FFF6
51h
0101_0001
interrupt
Port 1 @ 0FFF4
82h
1000_0010
interrupt
TA1CCR0 @ 0FFF2
51h
0101_0001
interrupt
Port 2 @ 0FFF0
81h
1000_0010
interrupt
TA1 CCR1, CCR1, TA1IFG@ 0FFEE
00h
0000_0000
delimiter
No more interrupt entries
In this example, the memory type is RAM (bits[15:13] = 001), the size is 16KB (bits[12:9] = 1000), and the starting address is
01C00h. The starting address is computed by taking the size field indicated by bit[7] ( in this case 0200h) and multiplying it by
the address value (bits[6:0] = 0001110. In this case, we have 0200h * 00Eh = 01C00h.
NOTE: The interrupt ordering has some implied rules:
•
For timers, CCR0 interrupt has higher priority over all other CCRn interrupts.
•
For communication ports, RX has higher priority over TX
•
For port pairs, Port 1 has higher priority over Port 2, Port 3 has higher priority over Port
4, etc.
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1.13.4 CRC Computation
The CRC checksum for the TLV structure is stored at memory locations 0x1A02 and 0x1A03. The least
significant byte (LSB) and most significant byte (MSB) reside at memory locations 0x1A02 and 0x1A03,
respectively. The checksum is computed using data stored at memory locations 0x1A04 through 0x1AFF.
The CRC checksum can be easily computed using the CRC16 module. The following simplified C code
utilizes the CRC16 module to compute the checksum. Please see the CRC16 chapter for further details on
the CRC algorithm implementation.
NOTE: The CRC module on the CC430F613x, CC430F612x, and CC430F513x devices does not
support the bit-wise reverse feature used in this code example. Registers CRCDIRB and
CRCRESR, along with their respective functionality, are not available.
unsigned int i;
unsigned char CRCRESULT_LSB, CRCRESULT_MSB;
WDTCTL = WDTPW + WDTHOLD;
CRCINIRES = 0xFFFF;
for (i = 0x01A04; i <= 0x01AFF; i++){
CRCDIRB_L = *(unsigned char*)(i);
}
CRCRESULT_LSB = CRCINIRES_L;
CRCRESULT_MSB = CRCINIRES_H;
62
// value stored @ 0x1A02
// value stored @ 0x1A03
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1.13.5 Calibration Values
The TLV structure contains calibration values that can be used to improve the measurement capability of
various functions. The calibration values available on a given device are shown in the TLV structure of the
device-specific data sheet.
1.13.5.1 REF Calibration
The calibration data for the REF module consists of three words, one word for each reference voltage
available (1.5, 2.0, and 2.5 V). The reference voltages are measured at room temperature. The measured
values are normalized by 1.5/2.0/2.5 V before being stored into the TLV structure:
CAL _ ADC _ 15VREF _ FACTOR =
VREF +
´ 215
1 .5V
CAL _ ADC _ 20VREF _ FACTOR =
VREF +
´ 215
2.0V
CAL _ ADC _ 25VREF _ FACTOR =
V REF +
´ 215
2 . 5V
(2)
In this way, a conversion result is corrected by multiplying it with the CAL_15VREF_FACTOR (or
CAL_20VREF_FACTOR, CAL_25VREF_FACTOR) and dividing the result by 215 as shown for each of the
respective reference voltages:
1
2 15
1
ADC(corrected ) = ADC(raw) ´ CAL _ ADC 20VREF _ FACTOR ´ 15
2
1
ADC(corrected ) = ADC(raw) ´ CAL _ ADC25VREF _ FACTOR ´ 15
2
ADC(corrected ) = ADC(raw) ´ CAL _ ADC15VREF _ FACTOR ´
(3)
In the following example, the integrated 1.5-V reference voltage is used during a conversion.
• Conversion result: 0x0100 = 256 decimal
• Reference voltage calibration factor (CAL_15VREF_FACTOR) : 0x7BBB
The following steps show how the ADC conversion result can be corrected:
• Multiply the conversion result by 2 (this step simplifies the final division): 0x0100 x 0x0002 = 0x0200
• Multiply the result by CAL_15VREF_FACTOR: 0x200 x 0x7FEE = 0x00F7_7600
• Divide the result by 216: 0x00F7_7600 / 0x0001_0000 = 0x0000_00F7 = 247 decimal
1.13.5.2 ADC Offset and Gain Calibration
The offset of the ADC is determined and stored as a twos-complement number in the TLV structure. The
offset error correction is done by adding the CAL_ADC_OFFSET to the conversion result.
ADC (offset _ corrected ) = ADC (raw) + CAL _ ADC _ OFFSET
(4)
The gain of the ADC12 is calculated by Equation 5:
CAL _ ADC _ GAIN _ FACTOR =
1
´ 215
GAIN
(5)
The conversion result is gain corrected by multiplying it with the CAL_ADC_GAIN_FACTOR and dividing
the result by 215:
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ADC ( gain _ corrected ) = ADC (raw) ´ CAL _ ADC _ GAIN _ FACTOR ´
1
215
(6)
If both gain and offset are corrected, the gain correction is done first:
ADC ( gain _ corrected ) = ADC (raw) ´ CAL _ ADC _ GAIN _ FACTOR ´
1
215
ADC ( final ) = ADC ( gain _ corrected ) + CAL _ ADC _ OFFSET
(7)
1.13.5.3 Temperature Sensor Calibration
The temperature sensor is calibrated using the internal voltage references. Each reference voltage
(1.5/2.0/2.5 V) contains a measured value for two temperatures, 30°C±3°C and 85°C ±3°C and are stored
in the TLV structure. The characteristic equation of the temperature sensor voltage, in mV is:
VSENSE = TC SENSOR ´ Temp + VSENSOR
(8)
The temperature coefficient, TCSENSORin mV/°C, represents the slope of the equation. VSENSOR, in mV,
represents the y-intercept of the equation. Temp, in °C, is the temperature of interest.
The temperature (Temp, °C) can be computed as follows for each of the reference voltages used in the
ADC measurement:
æ
ö
85 - 30
÷÷ + 30
Temp = (ADC (raw) - CAL _ ADC _ 15T 30 )´ çç
è CAL _ ADC _ 15T 85 - CAL _ ADC _ 15T 30 ø
æ
ö
85 - 30
÷÷ + 30
Temp = (ADC (raw) - CAL _ ADC _ 20T 30 )´ çç
è CAL _ ADC _ 20T 85 - CAL _ ADC _ 20T 30 ø
æ
ö
85 - 30
÷÷ + 30
Temp = (ADC (raw) - CAL _ ADC _ 25T 30 )´ çç
è CAL _ ADC _ 25T 85 - CAL _ ADC _ 25T 30 ø
(9)
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1.14 SFR Registers
The SFRs are listed in Table 1-11. The base address for the SFRs is listed in Table 1-10. Many of the bits
inside the SFRs are described in other chapters throughout this user's guide. These bits are marked with
a note and a reference. See the specific chapter of the respective module for details.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 1-10. SFR Base Address
Module
Base Address
SFR
00100h
Table 1-11. SFR Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
SFRIE1
Interrupt Enable
Read/write
Word
0000h
Section 5.4.4
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
0082h
Read/write
Byte
82h
Read/write
Byte
00h
Read/write
Word
0000h
00h
SFRIE1_L (IE1)
01h
SFRIE1_H (IE2)
02h
SFRIFG1
02h
SFRIFG1_L (IFG1)
03h
SFRIFG1_H (IFG2)
04h
Interrupt Flag
SFRRPCR
Reset Pin Control
04h
SFRRPCR_L
Read/write
Byte
00h
05h
SFRRPCR_H
Read/write
Byte
00h
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Section 1.14.3
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1.14.1 SFRIE1 Register
Interrupt Enable Register
Figure 1-8. SFRIE1 Register
15
14
13
12
r0
r0
r0
r0
11
10
9
8
r0
r0
r0
r0
Reserved
7
6
5
4
3
2
1
0
JMBOUTIE
JMBINIE
ACCVIE (1)
NMIIE
VMAIE
Reserved
OFIE (2)
WDTIE (3)
rw-0
rw-0
rw-0
rw-0
rw-0
r0
rw-0
rw-0
(1)
(2)
(3)
See the Flash Controller chapter for details.
See the UCS chapter for details.
See the WDT_A chapter for details.
Table 1-12. SFRIE1 Register Description
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0h
Reserved. Always reads as 0.
7
JMBOUTIE
RW
0h
JTAG mailbox output interrupt enable flag
0b = Interrupts disabled
1b = Interrupts enabled
6
JMBINIE
RW
0h
JTAG mailbox input interrupt enable flag
0b = Interrupts disabled
1b = Interrupts enabled
5
ACCVIE
RW
0h
Flash controller access violation interrupt enable flag
0b = Interrupts disabled
1b = Interrupts enabled
4
NMIIE
RW
0h
NMI pin interrupt enable flag
0b = Interrupts disabled
1b = Interrupts enabled
3
VMAIE
RW
0h
Vacant memory access interrupt enable flag
0b = Interrupts disabled
1b = Interrupts enabled
2
Reserved
R
0h
Reserved. Always reads as 0.
1
OFIE
RW
0h
Oscillator fault interrupt enable flag
0b = Interrupts disabled
1b = Interrupts enabled
0
WDTIE
RW
0h
Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for
interval timer mode. It is not necessary to set this bit for watchdog mode.
Because other bits in ~IE1 may be used for other modules, it is recommended to
set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or
CLR.B instruction
0b = Interrupts disabled
1b = Interrupts enabled
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1.14.2 SFRIFG1 Register
Interrupt Flag Register
Figure 1-9. SFRIFG1 Register
15
14
13
12
r0
r0
r0
r0
11
10
9
8
r0
r0
r0
r0
Reserved
7
6
5
4
3
2
1
0
JMBOUTIFG
JMBINIFG
Reserved
NMIIFG
VMAIFG
Reserved
OFIFG (1)
WDTIFG (2)
rw-(1)
rw-(0)
r0
rw-0
rw-0
r0
rw-(1)
rw-0
(1)
(2)
See the UCS chapter for details.
See the WDT_A chapter for details.
Table 1-13. SFRIFG1 Register Description
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0h
Reserved. Always reads as 0.
7
JMBOUTIFG
RW
1h
JTAG mailbox output interrupt flag
0b = No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is
cleared automatically when JMBO0 has been written with a new message to the
JTAG module by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is
cleared automatically when both JMBO0 and JMBO1 have been written with new
messages to the JTAG module by the CPU. This bit is also cleared when the
associated vector in SYSUNIV has been read.
1b = Interrupt pending, JMBO registers are ready for new messages. In 16-bit
mode (JMBMODE = 0), JMBO0 has been received by the JTAG module and is
ready for a new message from the CPU. In 32-bit mode (JMBMODE = 1) ,
JMBO0 and JMBO1 have been received by the JTAG module and are ready for
new messages from the CPU.
6
JMBINIFG
RW
0h
JTAG mailbox input interrupt flag
0b = No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is
cleared automatically when JMBI0 is read by the CPU. When in 32-bit mode
(JMBMODE = 1), this bit is cleared automatically when both JMBI0 and JMBI1
have been read by the CPU. This bit is also cleared when the associated vector
in SYSUNIV has been read
1b = Interrupt pending, a message is waiting in the JMBIN registers. In 16-bit
mode (JMBMODE = 0) when JMBI0 has been written by the JTAG module. In
32-bit mode (JMBMODE = 1) when JMBI0 and JMBI1 have been written by the
JTAG module.
5
Reserved
R
0h
Reserved. Always reads as 0.
4
NMIIFG
RW
0h
NMI pin interrupt flag
0b = No interrupt pending
1b = Interrupt pending
3
VMAIFG
RW
0h
Vacant memory access interrupt flag
0b = No interrupt pending
1b = Interrupt pending
2
Reserved
R
0h
Reserved. Always reads as 0.
1
OFIFG
RW
1h
Oscillator fault interrupt flag
0b = No interrupt pending
1b = Interrupt pending
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Table 1-13. SFRIFG1 Register Description (continued)
Bit
Field
Type
Reset
Description
0
WDTIFG
RW
0h
Watchdog timer interrupt flag. In watchdog mode, WDTIFG will self clear upon a
watchdog timeout event. The SYSRSTIV can be read to determine if the reset
was caused by a watchdog timeout event. In interval mode, WDTIFG is reset
automatically by servicing the interrupt, or can be reset by software. Because
other bits in ~IFG1 may be used for other modules, it is recommended to set or
clear WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or
CLR.B instructions.
0b = No interrupt pending
1b = Interrupt pending
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1.14.3 SFRRPCR Register
Reset Pin Control Register
Figure 1-10. SFRRPCR Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
Reserved
Reserved
r0
(1)
r0
r0
r0
3
2
1
0
SYSRSTRE (1)
SYSRSTUP (1)
SYSNMIIES
SYSNMI
rw-1
rw-1
rw-0
rw-0
All devices except the MSP430F5438 (non-A) default to pullup enabled on the reset pin.
Table 1-14. SFRRPCR Register Description
Bit
Field
Type
Reset
Description
15-4
Reserved
R
0h
Reserved. Always reads as 0.
3
SYSRSTRE
RW
1h
Reset pin resistor enable
0b = Pullup/pulldown resistor at the RST/NMI pin is disabled
1b = Pullup/pulldown resistor at the RST/NMI pin is enabled
2
SYSRSTUP
RW
1h
Reset resistor pin pullup/pulldown
0b = Pulldown is selected
1b = Pullup is selected
1
SYSNMIIES
RW
0h
NMI edge select. This bit selects the interrupt edge for the NMI when SYSNMI =
1. Modifying this bit can trigger an NMI. Modify this bit when SYSNMI = 0 to
avoid triggering an accidental NMI.
0b = NMI on rising edge
1b = NMI on falling edge
0
SYSNMI
RW
0h
NMI select. This bit selects the function for the RST/NMI pin.
0b = Reset function
1b = NMI function
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1.15 SYS Registers
The SYS configuration registers are listed in Table 1-16 and the base address is listed in Table 1-15. A
detailed description of each register and its bits is also provided. Each register starts at a word boundary.
Either word or byte data can be written to the SYS configuration registers.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 1-15. SYS Base Address
Module
Base Address
SYS
00180h
Table 1-16. SYS Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
SYSCTL
System Control
Read/write
Word
0000h
Section 1.15.1
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
0003h
Read/write
Byte
03h
Read/write
Byte
00h
Read/write
Word
0000h
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
0000h
00h
SYSCTL_L
01h
SYSCTL_H
02h
02h
SYSBSLC_L
03h
SYSBSLC_H
06h
SYSJMBC
06h
SYSJMBC_L
07h
SYSJMBC_H
08h
SYSJMBI0
Bootstrap Loader Configuration
JTAG Mailbox Control
JTAG Mailbox Input 0
08h
SYSJMBI0_L
Read/write
Byte
00h
09h
SYSJMBI0_H
Read/write
Byte
00h
0Ah
Read/write
Word
0000h
0Ah
SYSJMBI1_L
Read/write
Byte
00h
0Bh
SYSJMBI1_H
Read/write
Byte
00h
0Ch
SYSJMBI1
SYSJMBO0
JTAG Mailbox Input 1
Read/write
Word
0000h
0Ch
SYSJMBO0_L
Read/write
Byte
00h
0Dh
SYSJMBO0_H
Read/write
Byte
00h
Read/write
Word
0000h
Read/write
Byte
00h
0Eh
70
SYSBSLC
SYSJMBO1
0Eh
SYSJMBO1_L
0Fh
SYSJMBO1_H
JTAG Mailbox Output 0
JTAG Mailbox Output 1
Section 1.15.2
Section 1.15.3
Section 1.15.4
Section 1.15.5
Section 1.15.6
Section 1.15.7
Read/write
Byte
00h
18h
SYSBERRIV
Bus Error Vector Generator
Read
Word
0000h
Section 1.15.11
1Ah
SYSUNIV
User NMI Vector Generator
Read
Word
0000h
Section 1.15.8
1Ch
SYSSNIV
System NMI Vector Generator
Read
Word
0000h
Section 1.15.9
1Eh
SYSRSTIV
Reset Vector Generator
Read
Word
0002h
Section 1.15.10
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1.15.1 SYSCTL Register
SYS Control Register
Figure 1-11. SYSCTL Register
15
14
13
12
r0
r0
r0
r0
11
10
9
8
r0
r0
r0
r0
Reserved
7
6
Reserved
r0
5
4
3
2
1
0
SYSJTAGPIN
SYSBSLIND
Reserved
SYSPMMPE
Reserved
SYSRIVECT
rw-[0]
r-0
r0
rw-[0]
r0
rw-[0]
r0
Table 1-17. SYSCTL Register Description
Bit
Field
Type
Reset
Description
15-6
Reserved
R
0h
Reserved. Always reads as 0.
5
SYSJTAGPIN
RW
0h
Dedicated JTAG pins enable. Setting this bit disables the shared functionality of
the JTAG pins and permanently enables the JTAG function. This bit can only be
set once. Once it is set it remains set until a BOR occurs.
0b = Shared JTAG pins (JTAG mode selectable via SBW sequence)
1b = Dedicated JTAG pins (explicit 4-wire JTAG mode selection)
4
SYSBSLIND
RW
0h
BSL entry indication. This bit indicates a BSL entry sequence detected on the
Spy-Bi-Wire pins.
0b = No BSL entry sequence detected
1b = BSL entry sequence detected
3
Reserved
R
0h
Reserved. Always reads as 0.
2
SYSPMMPE
RW
0h
PMM access protect. This controls the accessibility of the PMM control registers.
Once set to 1, it only can be cleared by a BOR.
0b = Access from anywhere in memory
1b = Access only from the protected BSL segments
1
Reserved
R
0h
Reserved. Always reads as 0.
0
SYSRIVECT
RW
0h
RAM-based interrupt vectors
0b = Interrupt vectors generated with end address TOP of lower 64k flash FFFFh
1b = Interrupt vectors generated with end address TOP of RAM
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1.15.2 SYSBSLC Register
Bootstrap Loader Configuration Register
Figure 1-12. SYSBSLC Register
15
14
SYSBSLPE
SYSBSLOFF
rw-[0]
rw-[0]
7
6
13
12
11
r0
r0
r0
5
4
3
9
8
r0
r0
r0
2
1
Reserved
Reserved
r0
10
r0
r0
SYSBSLR
r0
r0
rw-[0]
0
SYSBSLSIZE
rw-[1]
rw-[1]
Table 1-18. SYSBSLC Register Description
Bit
Field
Type
Reset
Description
15
SYSBSLPE
RW
0h
Bootstrap loader memory protection enable for the size covered in SYSBSLSIZE.
By default, this bit is cleared by hardware with a BOR event (as indicated above),
however the boot code that checks for an available BSL may set this bit via
software in order to protect the BSL. Since devices normally come with a TI BSL
preprogrammed and protected, the boot code sets this bit.
0b = Area not protected. Read, program, and erase of BSL memory is possible.
1b = Area protected
14
SYSBSLOFF
RW
0h
Bootstrap loader memory disable for the size covered in SYSBSLSIZE
0b = BSL memory is addressed when this area is read.
1b = BSL memory behaves like vacant memory. Reads cause 3FFFh to be read.
Fetches cause JMP $ to be executed.
13-3
Reserved
R
0h
Reserved. Always reads as 0.
2
SYSBSLR
RW
0h
RAM assigned to BSL
0b = No RAM assigned to BSL area
1b = Lowest 16 bytes of RAM assigned to BSL
1-0
SYSBSLSIZE
RW
03h
Bootstrap loader size. Defines the space and size of flash memory that is
reserved for the BSL.
00b = Size: BSL segment 3
01b = Size: BSL segments 2 and 3
10b = Size: BSL segments 1, 2, and 3
11b = Size: BSL segments 1, 2, 3, and 4
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1.15.3 SYSJMBC Register
JTAG Mailbox Control Register
Figure 1-13. SYSJMBC Register
15
14
13
12
r0
r0
r0
r0
11
10
9
8
r0
r0
r0
r0
Reserved
7
6
5
4
3
2
1
0
JMBCLR1OFF
JMBCLR0OFF
Reserved
JMBM0DE
JMBOUT1FG
JMBOUT0FG
JMBIN1FG
JMBIN0FG
rw-(0)
rw-(0)
r0
rw-0
r-(1)
r-(1)
rw-(0)
rw-(0)
Table 1-19. SYSJMBC Register Description
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0h
Reserved. Always reads as 0.
7
JMBCLR1OFF
RW
0h
Incoming JTAG Mailbox 1 flag auto-clear disable
0b = JMBIN1FG cleared on read of JMB1IN register
1b = JMBIN1FG cleared by software
6
JMBCLR0OFF
RW
0h
Incoming JTAG Mailbox 0 flag auto-clear disable
0b = JMBIN0FG cleared on read of JMB0IN register
1b = JMBIN0FG cleared by software
5
Reserved
R
0h
Reserved. Always reads as 0.
4
JMBMODE
RW
0h
This bit defines the operation mode of JMB for JMBI0/1 and JMBO0/1. Before
switching this bit, pad and flush out any partial content to avoid data drops.
0b = 16-bit transfers using JMBO0 and JMBI0 only
1b = 32-bit transfers using JMBO0/1 and JMBI0/1
3
JMBOUT1FG
RW
1h
Outgoing JTAG Mailbox 1 flag. This bit is cleared automatically when a message
is written to the upper byte of JMBO1 or as word access (by the CPU, DMA,…)
and is set after the message was read via JTAG.
0b = JMBO1 is not ready to receive new data.
1b = JMBO1 is ready to receive new data.
2
JMBOUT0FG
RW
1h
Outgoing JTAG Mailbox 0 flag. This bit is cleared automatically when a message
is written to the upper byte of JMBO0 or as word access (by the CPU, DMA,…)
and is set after the message was read via JTAG.
0b = JMBO0 is not ready to receive new data.
1b = JMBO0 is ready to receive new data.
1
JMBIN1FG
RW
0h
Incoming JTAG Mailbox 1 flag. This bit is set when a new message (provided via
JTAG) is available in JMBI1. This flag is cleared automatically on read of JMBI1
when JMBCLR1OFF = 0 (auto clear mode). On JMBCLR1OFF = 1, JMBIN1FG
needs to be cleared by SW.
0b = JMBI1 has no new data.
1b = JMBI1 has new data available.
0
JMBIN0FG
RW
0h
Incoming JTAG Mailbox 0 flag. This bit is set when a new message (provided via
JTAG) is available in JMBI0. This flag is cleared automatically on read of JMBI0
when JMBCLR0OFF = 0 (auto clear mode). On JMBCLR0OFF = 1, JMBIN0FG
needs to be cleared by SW.
0b = JMBI1 has no new data.
1b = JMBI1 has new data available.
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1.15.4 SYSJMBI0 Register
JTAG Mailbox Input 0 Register
Figure 1-14. SYSJMBI0 Register
15
14
13
12
r-0
r-0
r-0
r-0
7
6
5
4
11
10
9
8
r-0
r-0
r-0
r-0
3
2
1
0
r-0
r-0
r-0
r-0
MSGHI
MSGLO
r-0
r-0
r-0
r-0
Table 1-20. SYSJMBI0 Register Description
Bit
Field
Type
Reset
Description
15-8
MSGHI
R
0h
JTAG mailbox incoming message high byte
7-0
MSGLO
R
0h
JTAG mailbox incoming message low byte
1.15.5 SYSJMBI1 Register
JTAG Mailbox Input 0 Register
Figure 1-15. SYSJMBI1 Register
15
14
13
12
11
10
9
8
r-0
r-0
r-0
r-0
3
2
1
0
r-0
r-0
r-0
r-0
MSGHI
r-0
r-0
r-0
r-0
7
6
5
4
MSGLO
r-0
r-0
r-0
r-0
Table 1-21. SYSJMBI1 Register Description
Bit
Field
Type
Reset
Description
15-8
MSGHI
R
0h
JTAG mailbox incoming message high byte
7-0
MSGLO
R
0h
JTAG mailbox incoming message low byte
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1.15.6 SYSJMBO0 Register
JTAG Mailbox Output 0 Register
Figure 1-16. SYSJMBO0 Register
15
14
13
12
rw-0
rw-0
rw-0
rw-0
7
6
5
4
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
MSGHI
MSGL0
rw-0
rw-0
rw-0
rw-0
Table 1-22. SYSJMBO0 Register Description
Bit
Field
Type
Reset
Description
15-8
MSGHI
RW
0h
JTAG mailbox outgoing message high byte
7-0
MSGLO
RW
0h
JTAG mailbox outgoing message low byte
1.15.7 SYSJMBO1 Register
JTAG Mailbox Output 1 Register
Figure 1-17. SYSJMBO1 Register
15
14
13
12
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
MSGHI
rw-0
rw-0
rw-0
rw-0
7
6
5
4
MSGL0
rw-0
rw-0
rw-0
rw-0
Table 1-23. SYSJMBO1 Register Description
Bit
Field
Type
Reset
Description
15-8
MSGHI
RW
0h
JTAG mailbox outgoing message high byte
7-0
MSGLO
RW
0h
JTAG mailbox outgoing message low byte
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1.15.8 SYSUNIV Register
User NMI Vector Register
NOTE: Additional events for more complex devices are appended to this table; sources that are
removed reduce the length of this table. The vectors are expected to be accessed symbolic
only with the corresponding include file of the device in use.
Figure 1-18. SYSUNIV Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-0
r-0
r-0
r0
SYSUNVEC
SYSUNVEC
r0
r0
r0
r-0
Table 1-24. SYSUNIV Register Description
Bit
Field
Type
Reset
Description
15-0
SYSUNIV
R
0h
User NMI vector. Generates a value that can be used as address offset for fast
interrupt service routine handling. Writing to this register clears all pending user
NMI flags.
00h = No interrupt pending
02h = NMIIFG interrupt pending (highest priority)
04h = OFIFG interrupt pending
06h = ACCVIFG interrupt pending
08h = BUSIFG interrupt pending (Not present on all devices. See device-specific
datasheet)
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1.15.9 SYSSNIV Register
System NMI Vector Register
NOTE: Additional events for more complex devices are appended to this table; sources that are
removed reduce the length of this table. The vectors are expected to be accessed symbolic
only with the corresponding include file of the used device.
Figure 1-19. SYSSNIV Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-0
r-0
r-0
r0
SYSSNVEC
SYSSNVEC
r0
r0
r0
r-0
Table 1-25. SYSSNIV Register Description
Bit
Field
Type
Reset
Description
15-0
SYSSNIV
R
0h
System NMI vector. Generates a value that can be used as address offset for
fast interrupt service routine handling. Writing to this register clears all pending
system NMI flags.
00h = No interrupt pending
02h = SVMLIFG interrupt pending (highest priority)
04h = SVMHIFG interrupt pending
06h = SVSMLDLYIFG interrupt pending
08h = SVSMHDLYIFG interrupt pending
0Ah = VMAIFG interrupt pending
0Ch = JMBINIFG interrupt pending
0Eh = JMBOUTIFG interrupt pending
10h = SVMLVLRIFG interrupt pending
12h = SVMHVLRIFG interrupt pending
14h = Reserved
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1.15.10 SYSRSTIV Register
Reset Interrupt Vector Register
NOTE: Additional events for more complex devices are appended to this table; sources that are removed
reduce the length of this table. The vectors are expected to be accessed symbolic only with the
corresponding include file of the used device.
Figure 1-20. SYSRSTIV Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-0
r-0
r-1
r0
SYSRSTVEC
r0
r0
r0
r0
7
6
5
4
SYSRSTVEC
r0
r0
r-0
r-0
Table 1-26. SYSRSTIV Register Description
Bit
Field
Type
Reset
Description
15-0
SYSRSTIV
R
0h
Reset interrupt vector. Generates a value that can be used as address offset for
fast interrupt service routine handling to identify the last cause of a reset (BOR,
POR, PUC) . Writing to this register clears all pending reset source flags.
00h = No interrupt pending
02h = Brownout (BOR) (highest priority)
04h = RST/NMI (BOR)
06h = PMMSWBOR (BOR)
08h = Wakeup from LPMx.5 (BOR)
0Ah = Security violation (BOR)
0Ch = SVSL (POR)
0Eh = SVSH (POR)
10h = SVML_OVP (POR)
12h = SVMH_OVP (POR)
14h = PMMSWPOR (POR)
16h = WDT time out (PUC)
18h = WDT password violation (PUC)
1Ah = Flash password violation (PUC)
1Ch = Reserved
1Eh = PERF peripheral/configuration area fetch (PUC)
20h = PMM password violation (PUC)
22h to 3Eh = Reserved
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1.15.11 SYSBERRIV Register
System Bus Error Interrupt Vector Register
NOTE: Additional events for more complex devices are appended to this table; sources that are removed
reduce the length of this table. The vectors are expected to be accessed symbolic only with the
corresponding include file of the used device.
Figure 1-21. SYSBERRIV Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-0
r-0
r-0
r0
SYSBERRIV
r0
r0
r0
r0
7
6
5
4
SYSBERRIV
r0
r0
r0
r-0
Table 1-27. SYSBERRIV Register Description
Bit
Field
Type
Reset
Description
15-0
SYSBERRIV
R
0h
System bus error interrupt vector. Generates a value that can be used as an
address offset for fast interrupt service routine handling. Writing to this register
clears all pending flags.
00h = No interrupt pending
02h = USB module timed out. Wait state time out of 8 clock cycles. 16 clock
cycles only on the F552x and F551x devices.
04h = Reserved for future extensions
06h = Reserved for future extensions
08h = Reserved for future extensions
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Chapter 2
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Power Management Module and Supply Voltage
Supervisor
This chapter describes the operation
Supply Voltage Supervisor (SVS).
Topic
2.1
2.2
2.3
80
of
the
Power
Management
Module
(PMM)
and
...........................................................................................................................
Page
Power Management Module (PMM) Introduction ................................................... 81
PMM Operation ................................................................................................. 83
PMM Registers .................................................................................................. 96
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2.1
Power Management Module (PMM) Introduction
PMM features include:
• Wide supply voltage (DVCC) range: 1.8 V to 3.6 V
• Generation of voltage for the device core (VCORE) with up to four programmable levels
• Supply voltage supervisor (SVS) for DVCC and VCORE with programmable threshold levels
• Supply voltage monitor (SVM) for DVCC and VCORE with programmable threshold levels
• Brownout reset (BOR)
• Software accessible power-fail indicators
• I/O protection during power-fail condition
• Software selectable supervisor or monitor state output (optional)
The PMM manages all functions related to the power supply and its supervision for the device. Its primary
functions are first to generate a supply voltage for the core logic, and second, provide several
mechanisms for the supervision and monitoring of both the voltage applied to the device (DVCC) and the
voltage generated for the core (VCORE).
The PMM uses an integrated low-dropout voltage regulator (LDO) to produce a secondary core voltage
(VCORE) from the primary one applied to the device (DVCC). In general, VCORE supplies the CPU, memories
(flash and RAM), and the digital modules, while DVCC supplies the I/Os and all analog modules (including
the oscillators). The VCORE output is maintained using a dedicated voltage reference. VCORE is
programmable up to four steps, to provide only as much power as is needed for the speed that has been
selected for the CPU. This enhances power efficiency of the system. The input or primary side of the
regulator is referred to in this chapter as its high side. The output or secondary side is referred to in this
chapter as its low side.
The required minimum voltage for the core depends on the selected MCLK rate. Figure 2-1 shows the
relationship between the system frequency for a given core voltage setting, as well as the minimum
required voltage applied to the device. Figure 2-1 is only an example—see the device-specific data sheet
to determine which core voltage levels are supported and what level of system frequency performance is
possible for a given device.
f3
System Frequency - MHz
3
f2
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
f1
f0
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 2-1. System Frequency, Supply Voltage, and Core Voltage – See Device-Specific Data Sheet
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The PMM module provides means for DVCC and VCORE to be supervised and monitored. Both of these
functions detect when a voltage falls under a specific threshold. In general, the difference is that
supervision results in a power-on reset (POR) event, while monitoring results in the generation of an
interrupt flag that software may then handle. As such, DVCC is supervised and monitored by the high-side
supervisor (SVSH) and high-side monitor (SVMH), respectively. VCORE is supervised and monitored by the
low-side supervisor (SVSL) and low-side monitor (SVML), respectively. Thus, there are four separate
supervision and monitoring modules that can be active at any given time. The thresholds enforced by
these modules are derived from the same voltage reference used by the regulator to generate VCORE.
In addition to the SVSH, SVMH, SVSL, and SVML modules, VCORE is further monitored by the brownout reset
(BOR) circuit. As DVCC ramps up from 0 V at power up, the BOR keeps the device in reset until VCORE is at
a sufficient level for operation at the default MCLK rate and for the SVSH and SVSL mechanisms to be
activated. During operation, the BOR also generates a reset if VCORE falls below a preset threshold. BOR
can be used to provide an even lower-power means of monitoring the supply rail if the flexibility of the
SVSL is not required.
The block diagram of the PMM is shown in Figure 2-2.
Control bits
Regulator
DVCC
SVSH
SVMH
Ports ON
PMMCOREV
Reference
VCORE
SVSL
SVML
BOR
NOR
OR
To reset logic
To reset logic
Figure 2-2. PMM Block Diagram
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2.2
PMM Operation
2.2.1 VCORE and the Regulator
DVCC can be powered from a wide input voltage range, but the core logic of the device must be kept at a
voltage lower than what this range allows. For this reason, a regulator has been integrated into the PMM.
The regulator derives the necessary core voltage (VCORE) from DVCC.
Higher MCLK speeds require higher levels of VCORE. Higher levels of VCORE consume more power, and so
the core voltage has been made programmable in up to four steps to allow it to provide only as much
power as is required for a given MCLK setting. The level is controlled by the PMMCOREV bits. Note that
the default setting, the lowest value of PMMCOREV, enables operation of MCLK over a very wide
frequency range. As such, no PMM changes are required for many applications. See the device-specific
data sheet for performance characteristics and core step levels supported.
Before increasing MCLK to a higher speed, it is necessary for software to ensure that the VCORE level is
sufficiently high for the chosen frequency. Failure to do so may force the CPU to attempt operation without
sufficient power, which can cause unpredictable results. See Section 2.2.4 for more information on the
appropriate procedure to raise VCORE for higher MCLK frequencies.
The regulator supports two different load settings to optimize power. The high-current mode is required
when:
• The CPU is in active, LPM0, or LPM1 modes
• A clock source greater than 32 kHz is used to drive any module
• An interrupt is executed
Otherwise, the low-current mode is used. The hardware controls the load settings automatically, according
to the criteria above.
2.2.2 Supply Voltage Supervisor and Monitor
The high-side supervisor and monitor (SVSH and SVMH) oversee DVCC, and the low-side supervisor and
monitor (SVSL and SVML) oversee VCORE. By default, all of these modules are active, but each can be
disabled using the corresponding enable bit (SVSHE, SVMHE, SVSLE, SVMLE), resulting in some power
savings.
Typical application scenarios for supply voltage supervisors and monitors are:
• High-Side Supervisor, SVSH
– Supervision of external power supply (DVCC)
– Device reset because of low battery or supply voltage
• High-Side Monitor, SVMH
– Monitoring of external power supply (DVCC)
– Detection of low battery voltage (Pre-warning)
• Low-Side Supervisor, SVSL
– Supervision of internal core voltage used to supply digital core
– Device reset because of disruptive conditions at external VCORE pin (for example a short). The
internal core voltage never drops below a critical level if parasitic events at the external VCORE pin
are avoided.
• Low-Side Monitor, SVML
– Monitoring of internal core voltage used to supply digital core
– Detection of correct internal voltage levels when changing (especially increasing) the core voltage
level before changing, for example, to higher system frequencies (also see Section 2.2.4).
2.2.2.1
SVS and SVM Thresholds
The voltage thresholds enforced by the SVS and SVM modules are selectable. Table 2-1 shows the SVS
and SVM threshold registers, the voltage threshold they control, and the number of threshold options.
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Table 2-1. SVS and SVM Thresholds
Register
SVSHRVL
SVSMHRRL
SVSLRVL
SVSMLRRL
(1)
Description
SVSH reset voltage level
SVSH, SVMH reset release voltage level
Available Steps
SVSH_IT-
4
SVSH_IT+, SVMH
8
SVSL_IT-
4
SVSL_IT+, SVML
4 (1)
SVSL reset voltage level
SVSL, SVML reset release voltage level
Threshold
The register settings support up to eight levels (0 through 7); however, levels 3 through 7 are identical.
2.2.2.1.1 Recommended SVSL Settings
For each of the core voltages, there are two supply voltage supervisor levels available. The SVSLRVL bits
define the voltage level of VCORE below which the reset is activated. The SVSMLRRL bits define the
voltage level of VCORE at which the reset is released. Although various settings can be chosen, there is
one set of SVSLRVL and SVSMLRRL settings that is well suited for each core voltage selected by
PMMCOREV. By default, an SVSL event always generates a POR (SVSLPE = 1), and it is recommended
to always configure SVSLPE = 1 for reliable device startup. The most commonly used and recommended
settings are shown in Table 2-2.
Table 2-2. Recommended SVSL Settings
PMMCOREV[1:0]
DVCC (V)
SVSLRVL[1:0]
Sets SVSL_IT-Level
SVSMLRRL[2:0]
Sets SVSL_IT+ and SVML
levels
00
≥ 1.8
00
000
01
≥ 2.0
01
001
10
≥ 2.2
10
010
11
≥ 2.4
11
011
2.2.2.1.1.1 Recommended SVSH Settings
For the high-side supply, there are two supply voltage supervisor levels available. The SVSMHRRL bits
define the voltage level of DVCC at which the reset is released. The SVSHRVL register defines the
voltage level of DVCC below which the reset is turned on. These settings should be selected according to
the minimum voltages required for device operation in a given application, as well as system power supply
characteristics. See the device-specific data sheet for threshold values corresponding to the settings
shown here. Although various settings are available, the most common are based on the maximum
frequency required which, in turn, determines the minimum DVCC level supervised. By default, an SVSH
event always generates a POR (SVSHPE = 1), and it is recommended to always configure SVSHPE = 1
for reliable device startup. The most commonly used and recommended settings are shown in Table 2-3 .
Table 2-3. Recommended SVSH Settings
fSYS Max
(MHz)
DVCC
(V)
SVSHRVL[1:0]
Sets SVSH_IT-Level
SVSMHRRL[2:0]
Sets SVSH_IT+ and
SVMH Levels
PMMCOREV[1:0]
8
>1.8
00
000
00
12
>2.0
01
001
01
20
>2.2
10
010
10
25
>2.4
11
011
11
The available voltage threshold settings of SVSH and SVMH are dependent on the voltage level setting of
VCORE. Table 2-4 summarizes all the possible settings available. All other settings not listed are invalid
and should not be used. Figure 2-3 shows the available settings for the SVMH.
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Table 2-4. Available SVSH and SVMH Settings Versus VCORE Settings
PMMCOREV[1:0]
SVSHRVL[1:0]
Sets SVSH_IT-Level
SVSMHRRL[2:0]
Sets SVSH_IT+ and SVMH Levels
00
00 through 11
000 through 011
01
00 through 11
001 through 100
10
00 through 11
010 through 101
11
00 through 11
011 through 111
111 (7)
Invalid
110 (6)
SVSMHRRLx
101 (5)
100 (4)
011 (3)
Valid
010 (2)
001 (1)
Invalid
000 (0)
00
01
10
11
PMMCOREVx
Figure 2-3. Available SVMH Settings Versus VCORE Settings
The behavior of the SVS and SVM according to these thresholds is best portrayed graphically. Figure 2-4
shows how the supervisors and monitors respond to various supply failure conditions.
As Figure 2-4 shows, there is hysteresis built into the supervision thresholds, such that the thresholds in
force depend on whether the voltage rail is going up or down. There is no hysteresis in the monitoring
thresholds.
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Voltage
DVCC
SVMH,SVSH_IT+
SVSH_ITVCORE
SVML,SVSL_IT+
SVSL_IT-
Set SVMHIFG
Set SVMHVLRIFG
Set SVSHIFG
Set SVMLIFG
Set SVMLVLRIFG
Set SVSLIFG
POR
Time
Figure 2-4. High-Side and Low-Side Voltage Failure and Resulting PMM Actions
2.2.2.2
High-Side Supervisor (SVSH) and High-Side Monitor (SVMH)
The SVSH and SVMH modules are enabled by default. They can be disabled by clearing the SVSHE and
SVMHE bits, respectively. Their block diagrams are shown in Figure 2-5.
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SVMHVLRPE
SVMHOVPE
0
Set POR
1
SVMHIE
Set
SVMH Interrupt
SVMHIFG
IFG
SVMHFP
SVMHE
SVMH
Set
ON
SVMHVLRIFG
IFG
SVSMHRRL
SVMHVLRIE
SVSHFP
SVSH
Set SVSHIFG
ON
SVSHRVL
SVSHE
Set POR
SVSMHDLYIFG
IFG
High power mode
LPM or SVSMHCTL
change
SVSHPE
Set
SVSHMD
SVMH Reached Interrupt
SVSMHDLYIE
High Side Delay Interrupt
EN
SVSMHEVM
Figure 2-5. High-Side SVS and SVM
If DVCC falls below the SVSH level, SVSHIFG (SVSH interrupt flag) is set. If DVCC remains below the SVSH
level and software attempts to clear SVSHIFG, it is immediately set again by hardware. If the SVSHPE
(SVSH POR enable) bit is set when SVSHIFG gets set, a POR is generated.
If DVCC falls below the SVMH level, SVMHIFG (SVMH interrupt flag) is set. If DVCC remains below the SVMH
level and software attempts to clear SVMHIFG, it is immediately set again by hardware. If the SVMHIE
(SVMH interrupt enable) bit is set when SVMHIFG gets set, an interrupt is generated. If a POR is desired
when SVMHIFG is set, the SVMH can be configured to do so by setting the SVMHVLRPE (SVMH voltage
level reached POR enable) bit while SVMHOVPE bit is cleared.
If DVCC rises above the SVMH level, the SVMHVLRIFG (SVMH voltage level reached) interrupt flag is set. If
SVMHVLRIE (SVMH voltage level reached interrupt enable) is set when this occurs, an interrupt is also
generated.
Alternatively the SVMH module can be used for overvoltage detection, but only with the highest core
voltage setting (PMMCOREV = 11b), . This is accomplished by setting the SVMHOVPE (SVMH
overvoltage POR enable) bit in addition to setting SVMHVLRPE. Under these conditions, if a rising DVCC
exceeds safe device operation, a POR is generated.
The SVSH and SVMH modules have configurable performance modes for power-saving operation. (See
Section 2.2.9 for more information.) If these SVSH and SVMH power modes are modified, or if a voltage
level is modified, a delay element masks the interrupts and POR sources until the SVSH and SVMH circuits
have settled. When SVSMHDLYST (delay status) reads zero, the delay has expired. In addition, the
SVSMHDLYIFG (SVSH and SVMH delay expired) interrupt flag is set. If the SVSMHDLYIE (SVSH and
SVMH delay expired interrupt enable) is set when this occurs, an interrupt is also generated.
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In case of power-fail conditions, setting SVSHMD causes the SVSH interrupt flag to be set in LPM2, LPM3,
and LPM4. If SVSHMD is not set, the SVSH interrupt flag is not set in LPM2, LPM3, and LPM4. In addition,
all SVSH and SVMH events can be masked by setting SVSMHEVM. For most applications, SVSMHEVM
should be cleared.
All the interrupt flags of SVSH and SVMH remain set until cleared by a BOR or by software.
2.2.2.3
Low-Side Supervisor (SVSL) and Low-Side Monitor (SVML)
The SVSL and SVML modules are enabled by default. They can be disabled by clearing SVSLE and
SVMLE bits, respectively. Their block diagrams are shown in Figure 2-6.
SVMLVLRPE
SVMLOVPE
0
Set POR
1
SVMLIE
SVML Interrupt
SVMLIFG
Set
IFG
SVMLFP
SVMLE
SVML
Set
ON
SVMLVLRIFG
IFG
SVSMLRRL
SVML Reached Interrupt
SVMLVLRIE
SVSLFP
SVSL
Set SVSLIFG
ON
SVSLRVL
SVSLE
SVSMLDLYIFG
Set
SVSLMD
IFG
High power mode
LPM or SVSMLCTL
change
Set POR
SVSLPE
Low Side Delay Interrupt
SVSMLDLYIE
EN
SVSMLEVM
Figure 2-6. Low-Side SVS and SVM
If VCORE falls below the SVSL level, SVSLIFG (SVSL interrupt flag) is set. If VCORE remains below the SVSL
level and software attempts to clear SVSLIFG, it is immediately set again by hardware. If the SVSLPE
(SVSL POR enable) bit is set when SVSLIFG gets set, a POR is generated.
If VCORE falls below the SVML level, SVMLIFG (SVML interrupt flag) is set. If VCORE remains below the SVML
level and software attempts to clear SVMLIFG, it is immediately set again by hardware. If the SVMLIE
(SVML interrupt enable) bit is set when SVMLIFG gets set, an interrupt is generated. If a POR is desired
when SVMLIFG is set, the SVML can be configured to do so by setting the SVMLVLRPE (SVML voltage
level reached POR enable) bit while SVMLOVPE bit is cleared.
If VCORE rises above the SVML level, the SVMLVLRIFG (SVML voltage level reached) interrupt flag is set. If
SVMLVLRIE (SVML voltage level reached interrupt enable) is set when this occurs, an interrupt is also
generated.
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The SVML module can also be used for overvoltage detection. This is accomplished by setting the
SVMLOVPE (SVML overvoltage POR enable) bit, in addition to setting SVMLVLRPE. Under these
conditions, if VCORE exceeds safe device operation, a POR is generated.
The SVSL and SVML modules have configurable performance modes for power-saving operation. (See
Section 2.2.9 for more information.) If these SVSL and SVML power modes are modified, or if a voltage
level is modified, a delay element masks the interrupts and POR sources until the SVSL and SVML circuits
have settled. When SVSMLDLYST (delay status) reads zero, the delay has expired. In addition, the
SVSMLDLYIFG (SVSL/SVML delay expired) interrupt flag is set. If the SVSMLDLYIE (SVSL /SVML delay
expired interrupt enable) is set when this occurs, an interrupt is also generated.
In case of power-fail conditions, setting SVSLMD causes the SVSL interrupt flag to be set in LPM2, LPM3,
and LPM4. If SVSLMD is not set, the SVSL interrupt flag is not set in LPM2, LPM3, and LPM4. In addition,
all SVSL and SVML events can be masked by setting SVSMLEVM. For most applications, SVSMLEVM
should be cleared.
All the interrupt flags of SVSL and SVML remain set until cleared by a BOR or by software.
2.2.3 Supply Voltage Supervisor and Monitor - Power-Up
When the device is powering up, the SVSH and SVSL functions are enabled by default. Initially, DVCC is
low, and therefore the PMM holds the device in POR reset. When both the SVSH and SVSL levels are met,
the reset is released. Figure 2-7 shows this process.
Voltage
DVCC
SVSH_IT+
VCORE
SVSL_IT+
Reset from SVSH
Reset from SVSL
POR
Time
Figure 2-7. PMM Action at Device Power-Up
After this point, both voltage domains are supervised and monitored while the respective modules are
enabled.
2.2.4 Increasing VCORE to Support Higher MCLK Frequencies
With a reset, VCORE and all the PMM thresholds, default to their lowest possible levels. These default
settings allow a wide range of MCLK operation, and in many applications no change to these levels is
required. However, if the application requires the performance provided by higher MCLK frequencies,
software should ensure that VCORE has been raised to a sufficient voltage level before changing MCLK,
since failing to supply sufficient voltage to the CPU could produce unpredictable results. For a given
device, minimum VCORE levels required for maximum MCLK frequencies have been established (See the
device data sheet for specific values).
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After setting PMMCOREV to increase VCORE, there is a time delay until the new voltage has been
established. Software must not raise MCLK until the necessary core voltage has settled. SVML can be
used to verify that VCORE has met the required minimum value, prior to increasing MCLK. Figure 2-8 shows
this procedure.
Voltage
VCORE
SVML
6
1
3
4
5
2
SVSL
Time
Figure 2-8. Changing VCORE and SVML and SVSL Levels
It is critical that the VCORE level be increased by only one level at a time. The following steps 1 through 4
show the procedure to increase VCORE by one level. This sequence is repeated to change the VCORE level
until the targeted level is obtained:
• Step 1: Program the SVMH and SVSH to the next level to ensure DVCC is high enough for the next VCORE
level. Program the SVML to the next level and wait for (SVSMLDLYIFG) to be set.
• Step 2: Program PMMCOREV to the next VCORE level.
• Step 3: Wait for the voltage level reached (SVMLVLRIFG) flag.
• Step 4: Program the SVSL to the next level.
As a reference, the following is a C code example for increasing VCORE. The sample libraries provide
routines for increasing and decreasing the VCORE and should be used whenever possible.
; C Code example for increasing core voltage.
; Note: Change core voltage one level at a time.
void SetVCoreUp (unsigned int level)
{
// Open PMM registers for write access
PMMCTL0_H = 0xA5;
// Make sure no flags are set for iterative sequences
while ((PMMIFG & SVSMHDLYIFG) == 0);
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}
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NOTE: See the MSP430x5xx and MSP430x6xx Core Libraries (SLAA448). These libraries contain
useful and ready-to-use functions for easily configuring and using the PMM module.
2.2.5 Decreasing VCORE for Power Optimization
The risk posed by increasing MCLK frequency does not exist when decreasing MCLK from the current
VCORE or higher settings, because higher VCORE levels can still support MCLK frequencies below the ones
for which they were intended. However, significant power efficiency gains can be made by operating VCORE
at the lowest value required for a given MCLK frequency. It is critical that the VCORE level be decreased by
only one level at a time. The following steps show the procedure to decrease VCORE by one level. This
sequence is repeated to change the VCORE level until the targeted level is obtained:
Steps 5 through 6 show the procedure to decrease VCORE:
• Step 5: Program the SVML and SVSL to the new level and wait for (SVSMLDLYIFG) to be set.
• Step 6: Program PMMCOREV to the new VCORE level.
It is critical when lowering the VCORE setting that the maximum MCLK frequency for the new VCORE setting is
not violated (see the device-specific data sheet).
2.2.6 Transition From LPM3 and LPM4 Modes to AM
The LDO requires time to settle when the application transitions from low-power modes to active modes. If
a transition from LPM3 or LPM4 occurs and the devices does not stay in active mode long enough, the
LDO does not have time to settle sufficiently. Circuitry inside the LDO ensures that the LDO has its
minimum required time to settle to its proper operating voltage. The circuitry ensures that every eighth
transition from LPM3 or LPM4 causes the LDO to remain on long enough to properly settle. This is
handled automatically and requires no setting by the application.
2.2.7 LPM3.5 and LPM4.5
LPM3.5 and LMP4.5 are additional low-power modes in which the regulator of the PMM is completely
disabled, providing additional power savings. Not all devices support all LPMx.5 modes, so see the
device-specific data sheet. Because there is no power supplied to VCORE during LPMx.5, the CPU and
all digital modules including RAM are unpowered. This disables the entire device and, as a result, the
contents of the registers and RAM are lost. Any essential values should be stored to flash prior to entering
LPMx.5. PMMREGOFF bit is used to disable the regulator. See the SYS module for complete descriptions
and proper uses of LMPx.5.
Because the regulator of the PMM is disabled upon entering LPMx.5, all I/O register configurations are
lost. Therefore, the configuration of I/O pins must be handled differently to ensure that all pins in the
application behave in a controlled manner upon entering and exiting LPMx.5. Properly setting the I/O pins
is critical to achieving the lowest possible power consumption in LPMx.5, as well as preventing any
possible uncontrolled input or output I/O state in the application. The application has complete control of
the I/O pin conditions preventing the possibility of unwanted spurious activity upon entry and exit from
LPMx.5. The I/O pin state is held and locked based on the settings prior to LPMx.5 entry. Upon entry into
LPMx.5, the LOCKLPM5 bit in PM5CTL0 of the PMM module is set automatically. Note that only the pin
condition is retained. All other port configuration register settings are lost. See the Digital I/O chapter for
further details.
2.2.8 Brownout Reset (BOR), Software BOR, Software POR
The primary function of the brownout reset (BOR) circuit occurs when the device is powering up. It is
functional very early in the power-up ramp, generating a POR that initializes the system. It also functions
when no SVS is enabled and a brownout condition occurs. It sustains this reset until the input power is
sufficient for the logic, for proper reset of the system.
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In an application, it may be desired to cause a BOR via software. Setting PMMSWBOR causes a
software-driven BOR. PMMBORIFG is set accordingly. Note that a BOR also initiates a POR and PUC.
PMMBORIFG can be cleared by software or by reading SYSRSTIV. Similarly, it is possible to cause a
POR via software by setting PMMSWPOR. PMMPORIFG is set accordingly. A POR also initiates a PUC.
PMMPORIFG can be cleared by software or by reading SYSRSTIV. Both PMMSWBOR and PMMSWPOR
are self clearing. See the SYS module for complete descriptions of BOR, POR, and PUC resets.
2.2.9 SVS and SVM Performance Modes and Wakeup Times
The supervisors/monitors can function in one of two modes: normal and full performance. The difference
is a tradeoff in response time versus the power consumed; full-performance mode has a faster response
time but consumes considerably more power than normal mode. Full-performance mode might be
considered in applications in which the decoupling of the external power supply cannot adequately prevent
fast spikes on DVCC from occurring, or when the application has a particular intolerance to failure. In such
cases, full-performance mode provides an additional layer of protection.
There are two ways to control the performance mode: manual and automatic. In manual mode, the
normal/full-performance selection is the same for every operational mode except LPMx.5 (the SVS and
SVM are always disabled in LPMx.5). In this case, the normal or full-performance selection is made with
the SVSHFP, SVMHFP, SVSLFP, or SVMLFP bit, for their respective modules.
In automatic mode, hardware changes the normal or full-performance selection depending on the
operational mode in effect.
The wakeup time of the device from low-power modes is affected by the settings of the SVSL and SVML
performance modes as listed in Table 2-6, Table 2-7, Table 2-8, and Table 2-9. The wakeup time from
low-power modes is not affected by the settings of the SVSH and SVMH. All wake-ups from LPMx.5
(LPM3.5 or LPM4.5), are defined by the data sheet parametric, tWAKE-UP-LPM5, regardless of the performance
modes for SVSL or SVML, because these are disabled in LPMx.5.
The tables in Section 2.2.9.1 and Section 2.2.9.2 show the required settings to select the control and
performance modes for SVSL, SVML, SVSH, and SVMH.
NOTE: Low-Power Modes
Even if the CPU requests a specific low-power mode, the device might not go into that state
because of modules requesting clocks that should be switched off or have higher
frequencies or because of modules requesting a higher drive capability of the LDO. The lowpower modes mentioned in the tables assume that the device is actually in the requested
state; that is, no module is requesting a deviating clock setting or drive capability.
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2.2.9.1
Low-Side SVS and SVM Control and Performance Mode Selection
Table 2-5. SVSL and SVML Control Mode Selection
SVSMLACE
SVSLMD
SVSL Control Mode
0
0
Automatic (see Table 2-6)
SVML Control Mode
Manual (see Table 2-8)
0
1
Manual (see Table 2-7)
Manual (see Table 2-8)
1
0
Automatic (see Table 2-6)
Automatic (see Table 2-9)
1
1
Automatic (see Table 2-6)
Automatic (see Table 2-9)
Table 2-6. SVSL Automatic Performance Control
SVSLE
SVSLMD
SVSLFP
AM, LPM0, LPM1
SVSL State
LPM2, LPM3, LPM4
SVSL State
Wakeup Time
LPM2, LPM3, LPM4
0
x
x
Off
Off
tWAKE-UP-FAST
1
0
0
Normal
Off
tWAKE-UP-SLOW
1
0
1
Full performance
Off
tWAKE-UP-FAST
1
1
0
Normal
Off
tWAKE-UP-SLOW
1
1
1
Full performance
Normal
tWAKE-UP-FAST
Table 2-7. SVSL Manual Performance Modes
SVSLE
SVSLFP
AM, LPM0, LPM1
SVSL State
LPM2, LPM3, LPM4
SVSL State
Wakeup Time
LPM2, LPM3, LPM4
0
x
Off
Off
tWAKE-UP-FAST
1
0
Normal
Normal
tWAKE-UP-SLOW
1
1
Full performance
Full performance
tWAKE-UP-FAST
Table 2-8. SVML Automatic Performance Control
SVMLE
SVMLFP
AM, LPM0, LPM1
SVML State
LPM2, LPM3, LPM4
SVML State
Wakeup Time
LPM2, LPM3, LPM4
0
x
Off
Off
tWAKE-UP-FAST
1
0
Normal
Off
tWAKE-UP-SLOW
1
1
Full performance
Normal
tWAKE-UP-FAST
Table 2-9. SVML Manual Performance Modes
SVMLE
SVMLFP
AM, LPM0, LPM1
SVML State
LPM2, LPM3, LPM4
SVML State
Wakeup Time
LPM2, LPM3, LPM4
0
x
Off
Off
tWAKE-UP-FAST
1
0
Normal
Normal
tWAKE-UP-SLOW
1
1
Full performance
Full performance
tWAKE-UP-FAST
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High-Side SVS and SVM Control and Performance Mode Selection
Table 2-10. SVSH and SVMH Control Mode Selection
SVSMHACE
SVSHMD
SVSH Control Mode
0
0
Automatic (see Table 2-11)
SVMH Control Mode
Manual (see Table 2-13)
0
1
Manual (see Table 2-12)
Manual (see Table 2-13)
1
0
Automatic (see Table 2-11)
Automatic (see Table 2-14)
1
1
Automatic (see Table 2-11)
Automatic (see Table 2-14)
Table 2-11. SVSH Automatic Performance Control
SVSHE
SVSHMD
SVSHFP
AM, LPM0, LPM1
SVSH State
LPM2, LPM3, LPM4
SVSH State
0
x
x
Off
Off
1
0
0
Normal
Off
1
0
1
Full performance
Off
1
1
0
Normal
Off
1
1
1
Full performance
Normal
Table 2-12. SVSH Manual Performance Modes
SVSHE
SVSHFP
AM, LPM0, LPM1
SVSH State
LPM2, LPM3, LPM4
SVSH State
0
x
Off
Off
1
0
Normal
Normal
1
1
Full performance
Full performance
Table 2-13. SVMH Automatic Performance Control
SVMHE
SVMHFP
AM, LPM0, LPM1
SVMH State
LPM2, LPM3, LPM4
SVMH State
Off
0
x
Off
1
0
Normal
Off
1
1
Full performance
Normal
Table 2-14. SVMH Manual Performance Modes
SVMHE
2.2.9.3
SVMHFP
AM, LPM0, LPM1
SVMH State
LPM2, LPM3, LPM4
SVMH State
0
x
Off
Off
1
0
Normal
Normal
1
1
Full performance
Full performance
Wakeup Times in Debug Mode
The TEST/SBWTCK pin is used for interfacing to the development tools via Spy-Bi-Wire and JTAG. When
the TEST/SBWTCK pin is high, wakeup times from LPM2, LPM3, and LPM4 may be different compared to
when TEST/SBWTCK is low. When the TEST/SBWTCK pin is high, all delays associated with the SVSL
and SVML settings have no effect and the device wakes within tWAKE-UP-FAST . Pay careful attention to the
real-time behavior when exiting from LPM2, LPM3, and LPM4 with the device connected to a development
tool (for example, MSP-FET430UIF).
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2.2.10 PMM Interrupts
Interrupt flags generated by the PMM are routed to the system NMI interrupt vector generator register,
SYSSNIV. When the PMM causes a reset, a value is generated in the system reset interrupt vector
generator register, SYSRSTIV, corresponding to the source of the reset. These registers are defined
within the SYS module. More information on the relationship between the PMM and SYS modules is
available in the SYS chapter.
2.2.11 Port I/O Control
The PMM provides a means of ensuring that I/O pins cannot behave in uncontrolled fashion during an
undervoltage event. During these times, outputs are disabled, both normal drive and the weak
pullup/pulldown function. If the CPU is functioning normally, and then an undervoltage event occurs, any
pin configured as an input has its PxIN register value locked in at the point the event occurs, until voltage
is restored. During the undervoltage event, external voltage changes on the pin are not registered
internally. This helps prevent erratic behavior from occurring.
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional)
The state of SVMLIFG, SVMLVLRIFG, SVMHIFG, and SVMLVLRIFG can be monitored on the external
SVMOUT pin. Each of these interrupt flags can be enabled (SVMLOE, SVMLVLROE, SVMHOE,
SVMLVLROE) to generate an output signal. The polarity of the output is selected by the SVMOUTPOL bit.
If SVMOUTPOL is set, the output is set to 1 if an enabled interrupt flag is set.
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PMM Registers
The PMM registers are listed in Table 2-15. The base address of the PMM module can be found in the
device-specific data sheet. The address offset of each PMM register is given in Table 2-15. The password,
PMMPW, defined in the PMMCTL0 register controls access to all PMM, SVS, and SVM registers. Once
the correct password is written, the write access is enabled. The write access is disabled by writing a
wrong password in byte mode to the PMMCTL0 upper byte. Word accesses to PMMCTL0 with a wrong
password triggers a PUC. A write access to a register other than PMMCTL0 while write access is not
enabled causes a PUC.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 2-15. PMM Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
PMMCTL0
PMM control register 0
Read/write
Word
9600h
Section 2.3.1
00h
PMMCTL0_L
Read/write
Byte
00h
01h
PMMCTL0_H
Read/write
Byte
96h
Read/write
Word
0000h
02h
PMM control register 1
02h
PMMCTL1_L
Read/write
Byte
00h
03h
PMMCTL1_H
Read/write
Byte
00h
Read/write
Word
4400h
04h
SVSMHCTL
SVS and SVM high side control register
04h
SVSMHCTL_L
Read/write
Byte
00h
05h
SVSMHCTL_H
Read/write
Byte
44h
Read/write
Word
4400h
Read/write
Byte
00h
Read/write
Byte
44h
Read/write
Word
0020h
06h
SVSMLCTL
06h
SVSMLCTL_L
07h
SVSMLCTL_H
08h
SVSMIO
SVS and SVM low side control register
SVSIN and SVMOUT control register
(optional)
08h
SVSMIO_L
Read/write
Byte
20h
09h
SVSMIO_H
Read/write
Byte
00h
Read/write
Word
0000h
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
1100h
Read/write
Byte
00h
Read/write
Byte
11h
Read/write
Word
0000h
0Ch
PMMIFG
0Ch
PMMIFG_L
0Dh
PMMIFG_H
0Eh
PMMRIE
0Eh
PMMRIE_L
0Fh
PMMRIE_H
10h
96
PMMCTL1
PM5CTL0
PMM interrupt flag register
PMM interrupt enable register
Power mode 5 control register 0
10h
PM5CTL0_L
Read/write
Byte
00h
11h
PM5CTL0_H
Read/write
Byte
00h
Power Management Module and Supply Voltage Supervisor
Section 2.3.2
Section 2.3.3
Section 2.3.4
Section 2.3.5
Section 2.3.6
Section 2.3.7
Section 2.3.8
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2.3.1 PMMCTL0 Register
Power Management Module Control Register 0
Figure 2-9. PMMCTL0 Register
15
14
13
12
rw-1
rw-0
rw-0
rw-1
7
6
11
10
9
8
rw-0
rw-1
rw-1
rw-0
1
PMMPW
PMMHPMRE
rw-0
5
Reserved
r-0
r-0
4
3
2
PMMREGOFF
PMMSWPOR
PMMSWBOR
rw-0
rw-0
rw-0
0
PMMCOREV
rw-[0]
rw-[0]
Table 2-16. PMMCTL0 Register Description
Bit
Field
Type
Reset
Description
15-8
PMMPW
RW
96h
PMM password. Always read as 096h. When using word operations, must be
written with 0A5h or a PUC is generated. When using byte operation, writing
0A5h unlocks all PMM registers. When using byte operation, writing anything
different than 0A5h locks all PMM registers.
7
PMMHPMRE
RW
0h
Global high power module request enable. If the PMMHPMRE bit is set, any
module is able to request the PMM high-power mode.
6-5
Reserved
R
0h
Reserved. Always reads as 0.
4
PMMREGOFF
RW
0h
Regulator off (see the SYS chapter for details)
3
PMMSWPOR
RW
0h
Software power-on reset. Setting this bit to 1 triggers a POR. This bit is self
clearing.
2
PMMSWBOR
RW
0h
Software brownout reset. Setting this bit to 1 triggers a BOR. This bit is self
clearing.
1-0
PMMCOREV
RW
0h
Core voltage (see the device-specific data sheet for supported levels and
corresponding voltages)
00b = V(CORE) level 0
01b = V(CORE) level 1
10b = V(CORE) level 2
11b = V(CORE) level 3
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2.3.2 PMMCTL1 Register
Power Management Module Control Register 1
Figure 2-10. PMMCTL1 Register
15
14
13
12
11
10
9
8
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
6
5
4
3
2
1
Reserved
7
Reserved
r-0
Reserved
r-0
rw-[0]
Reserved
rw-[0]
0
Reserved
r-0
r-0
rw-0
rw-0
Table 2-17. PMMCTL1 Register Description
Bit
Field
Type
Reset
Description
15-6
Reserved
R
0h
Reserved. Always reads as 0.
5-4
Reserved
RW
0h
Reserved. Must always be written with 0.
3-2
Reserved
R
0h
Reserved. Always reads as 0.
1-0
Reserved
RW
0h
Reserved. Must always be written with 0.
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2.3.3 SVSMHCTL Register
Supply Voltage Supervisor and Monitor High-Side Control Register
Figure 2-11. SVSMHCTL Register
15
14
13
12
11
10
SVMHFP
SVMHE
Reserved
SVMHOVPE
SVSHFP
SVSHE
rw-[0]
rw-1
r-0
rw-[0]
rw-[0]
rw-1
2
7
6
5
4
3
SVSMHACE
SVSMHEVM
Reserved
SVSHMD
SVSMHDLYST
rw-[0]
rw-0
r-0
rw-0
r-0
9
8
SVSHRVL
rw-[0]
rw-[0]
1
0
SVSMHRRL
rw-[0]
rw-[0]
rw-[0]
Table 2-18. SVSMHCTL Register Description
Bit
Field
Type
Reset
Description
15
SVMHFP
RW
0h
SVM high-side full-performance mode. If this bit is set, the SVMH operates in
full-performance mode.
0b = Normal mode. See the device-specific data sheet for response times.
1b = Full-performance mode. See the device-specific data sheet for response
times.
14
SVMHE
RW
1h
SVM high-side enable. If this bit is set, the SVMH is enabled.
13
Reserved
R
0h
Reserved. Always reads as 0.
12
SVMHOVPE
RW
0h
SVM high-side overvoltage enable. If this bit is set, the SVMH overvoltage
detection is enabled. If SVMHVLRPE is also set, a POR occurs on an
overvoltage condition.
11
SVSHFP
RW
0h
SVS high-side full-performance mode. If this bit is set, the SVSH operates in fullperformance mode.
0b = Normal mode. See the device-specific data sheet for response times.
1b = Full-performance mode. See the device-specific data sheet for response
times.
10
SVSHE
RW
1h
SVS high-side enable. If this bit is set, the SVSH is enabled.
9-8
SVSHRVL
RW
0h
SVS high-side reset voltage level. If DVCC falls short of the SVSH voltage level
selected by SVSHRVL, a reset is triggered (if SVSHPE = 1). The voltage levels
are defined in the device-specific data sheet.
7
SVSMHACE
RW
0h
SVS and SVM high-side automatic control enable. If this bit is set, the low-power
mode of the SVSH and SVMH circuits is under hardware control.
6
SVSMHEVM
RW
0h
SVS and SVM high-side event mask. If this bit is set, the SVSH and SVMH
events are masked.
0b = No events are masked.
1b = All events are masked.
5
Reserved
R
0h
Reserved. Always reads as 0.
4
SVSHMD
RW
0h
SVS high-side mode. If this bit is set, the SVSH interrupt flag is set in LPM2,
LPM3, and LPM4 in case of power-fail conditions. If this bit is not set, the SVSH
interrupt is not set in LPM2, LPM3, and LPM4.
3
SVSMHDLYST
RW
0h
SVS and SVM high-side delay status. If this bit is set, the SVSH and SVMH
events are masked for some delay time. The delay time depends on the power
mode of the SVSH and SVMH. If SVMHFP = 1 and SVSHFP = 1 (that is, fullperformance mode), the delay is shorter. See the device-specific data sheet for
details. The bit is cleared by hardware if the delay has expired.
2-0
SVSMHRRL
RW
0h
SVS and SVM high-side reset release voltage level. These bits define the reset
release voltage level of the SVSH. It is also used for the SVMH to define the
voltage reached level. The voltage levels are defined in the device-specific data
sheet.
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2.3.4 SVSMLCTL Register
Supply Voltage Supervisor and Monitor Low-Side Control Register
Figure 2-12. SVSMLCTL Register
15
14
13
12
11
10
SVMLFP
SVMLE
Reserved
SVMLOVPE
SVSLFP
SVSLE
rw-[0]
rw-1
r-0
rw-[0]
rw-[0]
rw-1
2
7
6
5
4
3
SVSMLACE
SVSMLEVM
Reserved
SVSLMD
SVSMLDLYST
rw-[0]
rw-0
r-0
rw-0
r-0
9
8
SVSLRVL
rw-[0]
rw-[0]
1
0
SVSMLRRL
rw-[0]
rw-[0]
rw-[0]
Table 2-19. SVSMLCTL Register Description
Bit
Field
Type
Reset
Description
15
SVMLFP
RW
0h
SVM low-side full-performance mode. If this bit is set, the SVML operates in fullperformance mode.
0b = Normal mode. See the device-specific data sheet for response times.
1b = Full-performance mode. See the device-specific data sheet for response
times.
14
SVMLE
RW
1h
SVM low-side enable. If this bit is set, the SVML is enabled.
13
Reserved
R
0h
Reserved. Always reads as 0.
12
SVMLOVPE
RW
0h
SVM low-side overvoltage enable. If this bit is set, the SVML overvoltage
detection is enabled.
11
SVSLFP
RW
0h
SVS low-side full-performance mode. If this bit is set, the SVSL operates in fullperformance mode.
0b = Normal mode. See the device-specific data sheet for response times.
1b = Full-performance mode. See the device-specific data sheet for response
times.
10
SVSLE
RW
1h
SVS low-side enable. If this bit is set, the SVSL is enabled.
9-8
SVSLRVL
RW
0h
SVS low-side reset voltage level. If V(CORE) falls short of the SVSL voltage
level selected by SVSLRVL, a reset is triggered (if SVSLPE = 1).
7
SVSMLACE
RW
0h
SVS and SVM low-side automatic control enable. If this bit is set, the low-power
mode of the SVSL and SVML circuits is under hardware control.
6
SVSMLEVM
RW
0h
SVS and SVM low-side event mask. If this bit is set, the SVSL and SVML events
are masked.
0b = No events are masked.
1b = All events are masked.
5
Reserved
R
0h
Reserved. Always reads as 0.
4
SVSLMD
RW
0h
SVS low-side mode. If this bit is set, the SVSL interrupt flag is set in LPM2,
LPM3 and LPM4 in case of power-fail conditions. If this bit is not set, the SVSL
interrupt is not set in LPM2, LPM3, and LPM4.
3
SVSMLDLYST
RW
0h
SVS and SVM low-side delay status. If this bit is set, the SVSL and SVML events
are masked for a delay time. The delay time depends on the power mode of the
SVSL and SVML. If SVMLFP = 1 and SVSLFP = 1 (that is, full-performance
mode), the delay is shorter. The bit is cleared by hardware if the delay has
expired.
2-0
SVSMLRRL
RW
0h
SVS and SVM low-side reset release voltage level. These bits define the reset
release voltage level of the SVSL. It is also used for the SVML to define the
voltage reached level.
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2.3.5 SVSMIO Register
SVSIN and SVMOUT Control Register
Figure 2-13. SVSMIO Register
15
14
13
Reserved
r-0
r-0
7
r-0
6
Reserved
r-0
12
11
SVMHVLROE
SVMHOE
rw-[0]
rw-[0]
r-0
2
5
4
3
SVMOUTPOL
SVMLVLROE
SVMLOE
rw-[1]
rw-[0]
rw-[0]
r-0
10
9
8
Reserved
r-0
r-0
1
0
Reserved
r-0
r-0
r-0
Table 2-20. SVSMIO Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Always reads as 0.
12
SVMHVLROE
RW
0h
SVM high-side voltage level reached output enable. If this bit is set, the
SVMHVLRIFG bit is output to the device SVMOUT pin. The device-specific port
logic has to be configured accordingly.
11
SVMHOE
RW
0h
SVM high-side output enable. If this bit is set, the SVMHIFG bit is output to the
device SVMOUT pin. The device-specific port logic has to be configured
accordingly.
10-6
Reserved
R
0h
Reserved. Always reads as 0.
5
SVMOUTPOL
RW
1h
SVMOUT pin polarity. If this bit is set, SVMOUT is active high. An error condition
is signaled by a 1 at SVMOUT. If SVMOUTPOL is cleared, the error condition is
signaled by a 0 at the SVMOUT pin.
4
SVMLVLROE
RW
0h
SVM low-side voltage level reached output enable. If this bit is set, the
SVMLVLRIFG bit is output to the device SVMOUT pin. The device-specific port
logic has to be configured accordingly.
3
SVMLOE
RW
0h
SVM low-side output enable. If this bit is set, the SVMLIFG bit is output to the
device SVMOUT pin. The device-specific port logic has to be configured
accordingly.
2-0
Reserved
R
0h
Reserved. Always reads as 0.
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2.3.6 PMMIFG Register
Power Management Module Interrupt Flag Register
Figure 2-14. PMMIFG Register
15
14
PMMLPM5IFG
Reserved
rw-[0]
r-0
13
12
SVSLIFG
(1)
rw-[0]
rw-[0]
(1)
11
10
9
8
Reserved
PMMPORIFG
PMMRSTIFG
PMMBORIFG
r-0
rw-[0]
rw-[0]
rw-[0]
7
6
5
4
3
2
1
0
Reserved
SVMHVLRIFG (
SVMHIFG
SVSMHDLYIF
G
Reserved
SVMLVLRIFG (1
SVMLIFG
SVSMLDLYIFG
r-0
rw-[0]
rw-[0]
rw-0
r-0
rw-[0]
rw-[0]
rw-0
1)
(1)
SVSHIFG
(1)
)
After power up, the reset value depends on the power sequence.
After power up, the reset value depends on the power sequence.
Table 2-21. PMMIFG Register Description
Bit
Field
Type
Reset
Description
15
PMMLPM5IFG
RW
0h
LPMx.5 flag. This bit is set if the system was in LPMx.5 before. The bit is cleared
by software or by reading the reset vector word. A power failure on the DVCC
domain clears the bit.
0b = No interrupt pending
1b = Interrupt pending
14
Reserved
R
0h
Reserved. Always reads as 0.
13
SVSLIFG
RW
0h
SVS low-side interrupt flag. The bit is cleared by software or by reading the reset
vector word.
0b = No interrupt pending
1b = Interrupt pending
12
SVSHIFG
RW
0h
SVS high-side interrupt flag. The bit is cleared by software or by reading the
reset vector word.
0b = No interrupt pending
1b = Interrupt pending
11
Reserved
R
0h
Reserved. Always reads as 0.
10
PMMPORIFG
RW
0h
PMM software power-on reset interrupt flag. This interrupt flag is set if a software
POR is triggered. The bit is cleared by software or by reading the reset vector
word, SYSRSTIV.
0b = No interrupt pending
1b = Interrupt pending
9
PMMRSTIFG
RW
0h
PMM reset pin interrupt flag. This interrupt flag is set if the RST/NMI pin is the
reset source. The bit is cleared by software or by reading the reset vector word.
0b = No interrupt pending
1b = Interrupt pending
8
PMMBORIFG
RW
0h
PMM software brownout reset interrupt flag. This interrupt flag is set if a software
BOR (PMMSWBOR) is triggered. The bit is cleared by software or by reading the
reset vector word, SYSRSTIV.
0b = No interrupt pending
1b = Interrupt pending
7
Reserved
R
0h
Reserved. Always reads as 0.
6
SVMHVLRIFG
RW
0h
SVM high-side voltage level reached interrupt flag. The bit is cleared by software
or by reading the reset vector (SVSHPE = 1) word or by reading the interrupt
vector (SVSHPE = 0) word.
0b = No interrupt pending
1b = Interrupt pending
5
SVMHIFG
RW
0h
SVM high-side interrupt flag. The bit is cleared by software.
0b = No interrupt pending
1b = Interrupt pending
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Table 2-21. PMMIFG Register Description (continued)
Bit
Field
Type
Reset
Description
4
SVSMHDLYIFG
RW
0h
SVS and SVM high-side delay expired interrupt flag. This interrupt flag is set if
the delay element expired. The bit is cleared by software or by reading the
interrupt vector word.
0b = No interrupt pending
1b = Interrupt pending
3
Reserved
R
0h
Reserved. Always reads as 0.
2
SVMLVLRIFG
RW
0h
SVM low-side voltage level reached interrupt flag. The bit is cleared by software
or by reading the reset vector (SVSLPE = 1) word or by reading the interrupt
vector (SVSLPE = 0) word.
0b = No interrupt pending
1b = Interrupt pending
1
SVMLIFG
RW
0h
SVM low-side interrupt flag. The bit is cleared by software.
0b = No interrupt pending
1b = Interrupt pending
0
SVSMLDLYIFG
RW
0h
SVS and SVM low-side delay expired interrupt flag. This interrupt flag is set if the
delay element expired. The bit is cleared by software or by reading the interrupt
vector word.
0b = No interrupt pending
1b = Interrupt pending
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2.3.7 PMMRIE Register
Power Management Module Reset and Interrupt Enable Register
Figure 2-15. PMMRIE Register
15
14
Reserved
r-0
13
12
SVMHVLRPE
SVSHPE
rw-[0]
rw-[1]
r-0
11
10
Reserved
r-0
9
8
SVMLVLRPE
SVSLPE
rw-[0]
rw-[1]
r-0
7
6
5
4
3
2
1
0
Reserved
SVMHVLRIE
SVMHIE
SVSMHDLYIE
Reserved
SVMLVLRIE
SVMLIE
SVSMLDLYIE
r-0
rw-0
rw-0
rw-0
r-0
rw-0
rw-0
rw-0
Table 2-22. PMMRIE Register Description
Bit
Field
Type
Reset
Description
15-14
Reserved
R
0h
Reserved. Always reads as 0.
13
SVMHVLRPE
RW
0h
SVM high-side voltage level reached power-on reset enable. If this bit is set,
exceeding the SVMH voltage level triggers a POR.
12
SVSHPE
RW
1h
SVS high-side power-on reset enable. If this bit is set, falling below the SVSH
voltage level triggers a POR.
11-10
Reserved
R
0h
Reserved. Always reads as 0.
9
SVMLVLRPE
RW
0h
SVM low-side voltage level reached power-on reset enable. If this bit is set,
exceeding the SVML voltage level triggers a POR.
8
SVSLPE
RW
1h
SVS low-side power-on reset enable. If this bit is set, falling below the SVSL
voltage level triggers a POR.
7
Reserved
R
0h
Reserved. Always reads as 0.
6
SVMHVLRIE
RW
0h
SVM high-side reset voltage level interrupt enable
5
SVMHIE
RW
0h
SVM high-side interrupt enable. This bit is cleared by software or if the interrupt
vector word is read.
4
SVSMHDLYIE
RW
0h
SVS and SVM high-side delay expired interrupt enable
3
Reserved
R
0h
Reserved. Always reads as 0.
2
SVMLVLRIE
RW
0h
SVM low-side reset voltage level interrupt enable
1
SVMLIE
RW
0h
SVM low-side interrupt enable. This bit is cleared by software or if the interrupt
vector word is read.
0
SVSMLDLYIE
RW
0h
SVS and SVM low-side delay expired interrupt enable
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2.3.8 PM5CTL0 Register
Power Mode 5 Control Register 0
Figure 2-16. PM5CTL0 Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
Reserved
Reserved
r0
r0
r0
r0
0
LOCKLPM5
r0
r0
r0
rw-[0]
Table 2-23. PM5CTL0 Register Description
Bit
Field
Type
Reset
Description
15-1
Reserved
R
0h
Reserved. Always reads as 0.
0
LOCKLPM5
RW
0h
Lock I/O pin configuration upon entry to or exit from LPMx.5. When power is
applied to the device, this bit, once set, can only be cleared by the user or via
another power cycle.
Note: This bit was formerly named LOCKIO, and some application reports and
code examples may continue to use this terminology.
0b = I/O pin configuration is not locked and defaults to its reset condition.
1b = I/O pin configuration remains locked. Pin state is held during LPMx.5 entry
and exit.
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Chapter 3
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Unified Clock System (UCS)
The Unified Clock System (UCS) module provides the various clocks for a device. This chapter describes
the operation of the UCS module, which is implemented in all devices.
106
Topic
...........................................................................................................................
3.1
3.2
3.3
3.4
Unified Clock System (UCS) Introduction ...........................................................
UCS Operation ................................................................................................
Module Oscillator (MODOSC) ............................................................................
UCS Module Registers .....................................................................................
Unified Clock System (UCS)
Page
107
109
119
120
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3.1
Unified Clock System (UCS) Introduction
The UCS module supports low system cost and ultralow power consumption. Using three internal clock
signals, the user can select the best balance of performance and low power consumption. The UCS
module can be configured to operate without any external components, with one or two external crystals,
or with resonators, under full software control.
The UCS module includes up to five clock sources:
• XT1CLK: Low-frequency oscillator that can be used with low-frequency 32768-Hz watch crystals
• VLOCLK: Internal very low power, low frequency oscillator with 10 kHz typical frequency
• REFOCLK: Internal, trimmed, low-frequency oscillator with 32768 Hz typical frequency, with the ability
to be used as a clock reference into the FLL
• DCOCLK: Internal digitally-controlled oscillator (DCO) that can be stabilized by the FLL
• XT2CLK: RF XT2 oscillator required for radio functionality
Three clock signals are available from the UCS module:
• ACLK: Auxiliary clock. The ACLK is software selectable as XT1CLK, REFOCLK, VLOCLK, DCOCLK,
DCOCLKDIV, and when available, XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4,
8, 16, or 32 within the FLL block. ACLK can be divided by 1, 2, 4, 8, 16, or 32. ACLK/n is ACLK
divided by 1, 2, 4, 8, 16, or 32 and is available externally at a pin. ACLK is software selectable by
individual peripheral modules.
• MCLK: Master clock. MCLK is software selectable as XT1CLK, REFOCLK, VLOCLK, DCOCLK,
DCOCLKDIV, and XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32
within the FLL block. MCLK can be divided by 1, 2, 4, 8, 16, or 32. MCLK is used by the CPU and
system.
• SMCLK: Subsystem master clock. SMCLK is software selectable as XT1CLK, REFOCLK, VLOCLK,
DCOCLK, DCOCLKDIV, and XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4, 8,
16, or 32 within the FLL block. SMCLK can be divided by 1, 2, 4, 8, 16, or 32. SMCLK is software
selectable by individual peripheral modules.
The block diagram of the UCS module is shown in Figure 3-1.
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ACLK_REQEN
ACLK_REQ
SELA
OSCOFF
3
Oscillator
XT1 Fault
Detection
XT1BYPASS
ACLK Enable Logic
DIVPA
EN
1
XT1CLK
000
001
010
011
100
101
110
111
0
VLO
REFO
XIN
3
3
VLOCLK
REFOCLK
XT1
0V
LF
Divider
/1/2/4/8/16/32
DIVA
3
Divider
/1/2/4/8/16/32
0
ACLK/n
ACLK
1
MCLK_REQEN
MCLK_REQ
XOUT
SELREF
3
0V
2
XCAP
FLL
2
XT1DRIVE
FLLREFCLK
FLLREFDIV
3
SCG0 PUC
Divider
/1/2/4/8/12/16
10
FLLN
Divider
/(N+1)
off Reset
+
10-bit
Frequency
Integrator
−
SELM
000
001
010
011
100
101
110
111
CPUOFF
3
MCLK Enable Logic
EN
3
000
001
010
011
100
101
110
111
SCG1 DCORSELDISMOD DCO,
MOD
10
3
off
DCO
DC
+
Generator
Modulator
DIVM
3
Divider
/1/2/4/8/16/32
0
MCLK
1
SMCLK_REQEN
SMCLK_REQ
FLLD
SELS
3
SMCLKOFF
3
DCOCLK
Prescaler
/1/2/4/8/16/32
SMCLK Enable Logic
DCOCLKDIV
EN
3
000
001
010
011
100
101
110
111
XT2 Oscillator
XT2CLK
Fault
Detection
XT2OFF
DIVS
3
Divider
/1/2/4/8/16/32
0
SMCLK
1
MODOSC_REQEN
RF_XIN
XT2
to Radio
RF_XOUT
MODOSC_REQ
Unconditonal MODOSC
requests
.
RF Oscillator
EN
MODOSC
MODCLK
Figure 3-1. UCS Block Diagram
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3.2
UCS Operation
After a PUC, the UCS module default configuration is:
• XT1 is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK.
• DCOCLKDIV is selected for MCLK.
• DCOCLKDIV is selected for SMCLK.
• FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK.
• XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are
configured for XT1 operation.
• RF oscillator sourcing XT2CLK disabled.
As previously stated, FLL operation with XT1 is selected by default, but XT1 is disabled. The crystal pins
(XIN, XOUT) are shared with general-purpose I/Os. To enable XT1, the PSEL bits associated with the
crystal pins must be set. When a 32,768 Hz crystal is used for XT1CLK, the fault control logic immediately
causes ACLK to be sourced by the REFOCLK, because XT1 is not stable immediately (see
Section 3.2.12). Once crystal startup is obtained and settled, the FLL stabilizes MCLK and SMCLK to
1.048576 MHz and fDCO = 2.097152 MHz.
Status register control bits (SCG0, SCG1, OSCOFF, and CPUOFF) configure the MSP430 operating
modes and enable or disable portions of the UCS module (see the SYS chapter). Registers UCSCTL0
through UCSCTL8, configure the UCS module.
The UCS module can be configured or reconfigured by software at any time during program execution.
NOTE:
For devices using RTC_B, RTC_C, or RTC_D (RTC modules supporting LPM3.5) setting bit
RTCHOLD = 0 in register RTCCTL1 also enables XT1, independent from UCS configuration.
3.2.1 UCS Module Features for Low-Power Applications
Conflicting requirements typically exist in battery-powered applications:
• Low clock frequency for energy conservation and time keeping
• High clock frequency for fast response times and fast burst processing capabilities
• Clock stability over operating temperature and supply voltage
• Low-cost applications with less-constrained clock accuracy requirements
The UCS module addresses these conflicting requirements by allowing the user to select from the three
available clock signals: ACLK, MCLK, and SMCLK.
All three available clock signals can be sourced via any of the available clock sources (XT1CLK, VLOCLK,
REFOCLK, DCOCLK, DCOCLKDIV, or XT2CLK), giving complete flexibility in the system clock
configuration. A flexible clock distribution and divider system is provided to fine tune the individual clock
requirements.
3.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
The internal VLO provides a typical frequency of 10 kHz (see device-specific data sheet for parameters)
without requiring a crystal. The VLO provides for a low-cost ultralow-power clock source for applications
that do not require an accurate time base.
The VLO is enabled when it is used to source ACLK, MCLK, or SMCLK (SELA = {1} or SELM = {1} or
SELS = {1}).
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3.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO)
The internal trimmed low-frequency REFO can be used for cost-sensitive applications where a crystal is
not required or desired. REFO is internally trimmed to 32.768 kHz typical and provides for a stable
reference frequency that can be used as FLLREFCLK. REFO, combined with the FLL, provides for a
flexible range of system clock settings without the need for a crystal. REFO consumes no power when not
being used.
REFO is enabled under any of the following conditions:
• REFO is a source for ACLK (SELA = {2}) and in active mode (AM) through LPM3 (OSCOFF = 0)
• REFO is a source for MCLK (SELM = {2}) and in active mode (AM) (CPUOFF = 0)
• REFO is a source for SMCLK (SELS = {2}) and in active mode (AM) through LPM1 (SMCLKOFF = 0)
• REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for ACLK (SELA = {3,4})
and in active mode (AM) through LPM3 (OSCOFF = 0)
• REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for MCLK (SELM = {3,4})
and in active mode (AM) (CPUOFF = 0)
• REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for SMCLK
(SELS = {3,4}) and in active mode (AM) through LPM1 (SMCLKOFF = 0)
3.2.4 XT1 Oscillator
The XT1 oscillator supports ultralow-current consumption using a 32,768 Hz watch crystal. A watch crystal
connects to XIN and XOUT without any other external components. The software-selectable XCAP bits
configure the internally provided load capacitance for the XT1 crystal in LF mode. This capacitance can be
selected as 2 pF, 6 pF, 9 pF, or 12 pF (typical). Additional external capacitors can be added if necessary.
The drive settings of XT1 can be increased with the XT1DRIVE bits. At power up, the XT1 starts with the
highest drive settings for fast, reliable startup. If needed, user software can reduce the drive strength to
further reduce power. .
XT1 may be used with an external clock signal on the XIN pin in either LF or HF mode by setting
XT1BYPASS. When used with an external signal, the external frequency must meet the data sheet
parameters for the chosen mode. XT1 is powered down when used in bypass mode.
Some devices support XT1 bypass operation with external clock inputs that reside on a different external
supply domain, called DVIO. Please refer to the device specific datasheet. On these devices, DVIO has a
voltage range of 1.8V ± 10 %. When using the XT1 bypass operation with external clock inputs that reside
on DVIO, it is required that XT1BYPASSLV = 1. For example, when XT1BYPASSLV = 1, it is assumed the
external clock signal swings from 0V to DVIO. With XT1BYPASS = 0, it is assumed the external clock
signal swings from 0V to DVCC. The usage of XT1BYPASSLV allows for interfacing to external clock
sources that reside on either the DVCC or DVIO supply domains. When used with an external signal, the
external frequency must meet the data sheet parameters for the chosen mode. XT1 is powered down
when used in bypass mode.
The XT1 pins are shared with general-purpose I/O ports. At power up, the default operation is XT1.
However, XT1 remains disabled until the ports shared with XT1 are configured for XT1 operation. The
configuration of the shared I/O is determined by the PSEL bit associated with XIN and the XT1BYPASS
bit. Setting the PSEL bit causes the XIN and XOUT ports to be configured for XT1 operation. If
XT1BYPASS is also set, XT1 is configured for bypass mode of operation, and the oscillator associated
with XT1 is powered down. In bypass mode of operation, XIN can accept an external clock input signal
and XOUT is configured as a general-purpose I/O. The PSEL bit associated with XOUT is a don't care.
If the PSEL bit associated with XIN is cleared, both XIN and XOUT ports are configured as generalpurpose I/Os, and XT1 is disabled.
XT1 is enabled under any of the following conditions:
• XT1 is a source for ACLK (SELA = {0}) and in active mode (AM) through LPM3 (OSCOFF = 0)
• XT1 is a source for MCLK (SELM = {0}) and in active mode (AM) (CPUOFF = 0)
• XT1 is a source for SMCLK (SELS = {0}) and in active mode (AM) through LPM1 (SMCLKOFF = 0)
• XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for ACLK (SELA = {3,4})
and in active mode (AM) through LPM3 (OSCOFF = 0)
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•
•
•
XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for MCLK (SELM = {3,4})
and in active mode (AM) (CPUOFF = 0)
XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for SMCLK (SELS = {3,4})
and in active mode (AM) through LPM1 (SMCLKOFF = 0)
XT1OFF = 0. XT1 enabled in active mode (AM) through LPM4. For devices that support LPMx.5, XT1
also remains enabled.
3.2.5 RF XT2 Oscillator
The RF XT2 oscillator's main purpose is to provide a reference clock to the on-chip radio module. But it
also sources XT2CLK and XT2CLK can be used to source ACLK, MCLK, SMCLK or FLLREFCLK.
The RF oscillator is enabled if it is used by the radio; that is, if the radio module is not in its sleep state.
With XT2OFF = 0 the RF oscillator is permanently enabled even when the radio is in sleep mode. With
XT2OFF = 1 the RF oscillator is disabled when the radio enters sleep mode. When the RF oscillator is
disabled the corresponding fault flag XT2OFFG is set and if the RF oscillator is selected to source ACLK,
MCLK, SMCLK or FLLREFCLK the corresponding fail-safe mechanism takes over.
3.2.6 Digitally-Controlled Oscillator (DCO)
The DCO is an integrated digitally controlled oscillator. The DCO frequency can be adjusted by software
using the DCORSEL, DCO, and MOD bits. The DCO frequency can be optionally stabilized by the FLL to
a multiple frequency of FLLREFCLK/n. The FLL can accept different reference sources selectable via the
SELREF bits. Reference sources include XT1CLK, REFOCLK, or XT2CLK. The value of n is defined by
the FLLREFDIV bits (n = 1, 2, 4, 8, 12, or 16). The default is n = 1. There may be scenarios in which FLL
operation is not required or desired; in these cases, no FLLREFCLK is necessary. This can be
accomplished by setting SELREF = {7}.
The FLLD bits configure the FLL prescaler divider value D to 1, 2, 4, 8, 16, or 32. By default, D = 2, and
MCLK and SMCLK are sourced from DCOCLKDIV, providing a clock frequency DCOCLK/2.
The divider (N + 1) and the divider value D define the DCOCLK and DCOCLKDIV frequencies, where
N > 0. Writing N = 0 causes the divider to be set to 2.
fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n)
fDCOCLKDIV = (N + 1) × (fFLLREFCLK ÷ n)
Adjusting DCO Frequency
By default, FLL operation is enabled. FLL operation can be disabled by setting SCG0 or SCG1. Once
disabled, the DCO continues to operate at the current settings defined in UCSCTL0 and UCSCTL1. The
DCO frequency can be adjusted manually if desired. Otherwise, the DCO frequency is stabilized by the
FLL operation.
After a PUC, DCORSEL = {2} and DCO = {0}. MCLK and SMCLK are sourced from DCOCLKDIV.
Because the CPU executes code from MCLK, which is sourced from the fast-starting DCO, code
execution begins from PUC in less than 5 µs.
The frequency of DCOCLK is set by the following functions:
• The three DCORSEL bits select one of eight nominal frequency ranges for the DCO. These ranges are
defined for an individual device in the device-specific data sheet.
• The five DCO bits divide the DCO range selected by the DCORSEL bits into 32 frequency steps,
separated by approximately 8%.
• The five MOD bits switch between the frequency selected by the DCO bits and the next-higher
frequency set by {DCO + 1}. When DCO = {31}, the MOD bits have no effect, because the DCO is
already at the highest setting for the selected DCORSEL range.
3.2.7 Frequency Locked Loop (FLL)
The FLL continuously counts up or down a frequency integrator. The output of the frequency integrator
that drives the DCO can be read in UCSCTL0, UCSCTL1 (bits MOD and DCO). The count is adjusted +1
with the frequency fFLLREFCLK/n (n = 1, 2, 4, 8, 12, or 16) or –1 with the frequency fDCOCLK/[D × (N+1)].
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Reading MOD and DCO bits
The integrator is updated via the DCOCLK, which may differ in frequency of operation of
MCLK. It is possible that immediate reads of a previously written value are not visible to the
user since the update to the integrator has not occurred. This is normal. Once the integrator
is updated at the next successive DCOCLK, the correct value can be read.
In addition, since the MCLK can be asynchronous to the integrator updates, reading the
values may be cause a corrupted value to be read under this condition. In this case, a
majority vote method should be performed.
Five of the integrator bits (UCSCTL0 bits 12 to 8) set the DCO frequency tap. Thirty-two taps are
implemented for the DCO, and each is approximately 8% higher than the previous. The modulator mixes
two adjacent DCO frequencies to produce fractional taps.
For a given DCO bias range setting, time must be allowed for the DCO to settle on the proper tap for
normal operation. (n × 32) fFLLREFCLK cycles are required between taps requiring a worst case of
(n × 32 × 32) fFLLREFCLK cycles for the DCO to settle. The value n is defined by the FLLREFDIV bits (n = 1,
2, 4, 8, 12, or 16).
3.2.8 DCO Modulator
The modulator mixes two DCO frequencies, fDCO and fDCO+1 to produce an intermediate effective
frequency between fDCO and fDCO+1 and spread the clock energy, reducing electromagnetic interference
(EMI). The modulator mixes fDCO and fDCO+1 for 32 DCOCLK clock cycles and is configured with the MOD
bits. When MOD = {0}, the modulator is off.
The modulator mixing formula is:
t = (32 – MOD) × tDCO + MOD × tDCO+1
Figure 3-2 shows the modulator operation.
When FLL operation is enabled, the modulator settings and DCO are controlled by the FLL hardware. If
FLL operation is not desired, the modulator settings and DCO control can be configured with software.
MODx
31
24
16
15
5
4
3
2
Lower DCO Tap Frequency fDCO
Upper DCO Tap Frequency fDCO+1
1
0
Figure 3-2. Modulator Patterns
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3.2.9 Disabling FLL Hardware and Modulator
The FLL is disabled when the status register bits SCG0 or SCG1 are set. When the FLL is disabled, the
DCO runs at the previously selected tap and DCOCLK is not automatically stabilized.
The DCO modulator is disabled when DISMOD is set. When the DCO modulator is disabled, the DCOCLK
is adjusted to the DCO tap selected by the DCO bits.
NOTE:
DCO operation without FLL
When the FLL operation is disabled, the DCO continues to operate at the current settings.
Because it is not stabilized by the FLL, temperature and voltage variations influence the
frequency of operation. See the device-specific data sheet for voltage and temperature
coefficients to ensure reliable operation.
3.2.10 FLL Operation From Low-Power Modes
An interrupt service request clears SCG1, CPUOFF, and OSCOFF if set, but does not clear SCG0. This
means that for FLL operation from within an interrupt service routine entered from LPM1, 3, or 4, the FLL
remains disabled and the DCO operates at the previous setting as defined in UCSCTL0 and UCSCTL1.
SCG0 can be cleared by user software if FLL operation is required.
3.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules
A peripheral module requests its clock sources automatically from the UCS module if required for its
proper operation, regardless of the current mode of operation, as shown in Figure 3-3.
A peripheral module asserts one of three possible clock request signals based on its control bits:
ACLK_REQ, MCLK_REQ, or SMCLK_REQ. These request signals are based on the configuration and
clock selection of the respective module. For example, if a timer selects ACLK as its clock source and the
timer is enabled, the timer generates an ACLK_REQ signal to the UCS system. The UCS, in turn, enables
ACLK regardless of the LPM settings.
Any clock request from a peripheral module causes its respective clock off signal to be overridden, but
does not change the setting of clock off control bit. For example, a peripheral module may require ACLK
that is currently disabled by the OSCOFF bit (OSCOFF = 1). The module can request ACLK by generating
an ACLK_REQ. This causes the OSCOFF bit to have no effect, thereby allowing ACLK to be available to
the requesting peripheral module. The OSCOFF bit remains at its current setting (OSCOFF = 1).
If the requested source is not active, the software NMI handler must take care of the required actions. For
the previous example, if ACLK was sourced by XT1 and XT1 was not enabled, an oscillator fault condition
occurs and the software must handle the event. The watchdog, due to its security requirement, actively
selects the VLOCLK source if the originally selected clock source is not available.
Due to the clock request feature, care must be taken in the application when entering low-power modes to
save power. Although the device enters the selected low-power mode, a clock request may exhibit more
current consumption than the specified values in the data sheet.
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0
SMCLK_REQ
0
MCLK_REQ
0
0
ACLK_REQ
ACLK_REQ
MCLK_REQ
SMCLK_REQ
UCS
ACLK_REQ
MCLK_REQ
SMCLK_REQ
Module n−2
Module n−1
ACLK_REQ
MCLK_REQ
SMCLK_REQ
Module n
SMCLK
MCLK
ACLK
Direct clock request
in Watchdog mode
WDTACLKON
WDTSMCLKON
Watch Dog Timer Module
Figure 3-3. Module Request Clock System
By default, the clock request logic is enabled. The clock request logic can be disabled by clearing
ACLKREQEN, MCLKREQEN, or SMCLKREQEN, for each respective system clock. When ACLKREQEN
or MCLKREQEN bits are set, or active, the clock is available to the system and prevents entry into a lowpower mode until all modules requesting the clock are disabled. When ACLKREQEN or MCLKREQEN bits
are cleared, or disabled, the clock is always halted as defined by the low-power modes. The
SMCLKREQEN logic behaves similarly, but is also influenced by the SMCLKOFF bit in the UCSCTL6
register.Table 3-1 shows the relationship between the system clocks and the low-power modes in
conjunction with the clock request logic.
Table 3-1. Clock Request System and Power Modes
ACLK
Mode
ACLKREQEN
=0
ACLKREQEN
=1
MCLKREQEN
=1
SMCLKOFF = 1
SMCLKREQEN SMCLKREQEN SMCLKREQEN SMCLKREQEN
=0
=1
=0
=1
Active
Active
Active
Active
Active
Active
Disabled
Active
Active
Active
Disabled
Active
Active
Active
Disabled
Active
LPM1
Active
Active
Disabled
Active
Active
Active
Disabled
Active
LPM2
Active
Active
Disabled
Active
Disabled
Active
Disabled
Active
LPM3
Active
Active
Disabled
Active
Disabled
Active
Disabled
Active
LPM4
Disabled
Active
Disabled
Active
Disabled
Active
Disabled
Active
(3)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled (3)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
LPM4.5
(1)
(3)
MCLKREQEN
=0
AM
(1)
(2)
SMCLK
SMCLKOFF = 0
LPM0
LPM3.5
(1)
MCLK
Disabled
(2)
Disabled (2)
Disabled
Any clock request prior to entry into LPM3.5 or LPM4.5 is ignored and LPM3.5 or LPM4.5 entry occurs. For the special case
when XT1OFF = 0 or XT2OFF = 0, the LPMx.5 request is ignored and the device does not enter LPMx.5.
Watchdog mode requesting ACLK prevents LPMx.5 entry.
Any module requesting ACLK prevents LPMx.5 entry.
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3.2.11.1 LPM3.5 and LPM4.5 Clock Request Handling
While ACLK is requested by at least one module (ACLKREQEN = 1), LPMx.5 cannot be entered. After
clearing the ACLK request enable signal (ACLKREQEN = 0), the device is able to enter LPMx.5 (except
for watchdog mode–see following note). See Entering and Exiting Low-Power Modes LPMx.5 for details
on how to enter LPMx.5.
NOTE: Watchdog Mode Using ACLK
When a device is configured to use watchdog mode (WDTTMSEL = 0) and is sourced by
ACLK (WDTSSEL = 01b), the device cannot enter LPMx.5 regardless of whether or not the
ACLK request enable signal (ACLKREQEN) is cleared.
3.2.12 UCS Module Fail-Safe Operation
The UCS module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for
XT1, DCO, and XT2 as shown in Figure 3-4. The available fault conditions are:
• Low-frequency oscillator fault (XT1LFOFFG) for XT1 in LF mode
• High-frequency oscillator fault (XT1HFOFFG) for XT1 in HF mode
• High-frequency oscillator fault (XT2OFFG) for XT2
• DCO fault flag (DCOFFG) for the DCO
The crystal oscillator fault bits XT1LFOFFG, XT1HFOFFG, and XT2OFFG are set if the corresponding
crystal oscillator is turned on and not operating properly. Once set, the fault bits remain set until reset in
software, regardless if the fault condition no longer exists. If the user clears the fault bits and the fault
condition still exists, the fault bits are automatically set, otherwise they remain cleared.
When using XT1 operation in LF mode as the reference source into the FLL (SELREF = {0}), a crystal
fault automatically causes the FLL reference source, FLLREFCLK, to be sourced by the REFO.
XT1LFOFFG is set. When using XT1 operation in HF mode as the reference source into the FLL, a crystal
fault causes no FLLREFCLK signal to be generated and the FLL continues to count down to zero in an
attempt to lock FLLREFCLK and DCOCLK/[D × (N + 1)]. The DCO tap moves to the lowest position (DCO
are cleared) and the DCOFFG is set. DCOFFG is also set if the N-multiplier value is set too high for the
selected DCO frequency range, resulting in the DCO tap moving to the highest position (UCSCTL0.12 to
UCSCTL0.8 are set). The DCOFFG remains set until cleared by the user. If the user clears the DCOFFG
and the fault condition remains, it is automatically set, otherwise it remains cleared. XT1HFOFFG is set.
When using XT2 as the reference source into the FLL, a crystal fault causes no FLLREFCLK signal to be
generated, and the FLL continues to count down to zero in an attempt to lock FLLREFCLK and
DCOCLK/[D × (N + 1)]. The DCO tap moves to the lowest position (DCO are cleared) and the DCOFFG is
set. DCOFFG is also set if the N-multiplier value is set too high for the selected DCO frequency range,
resulting in the DCO tap moving to the highest position (UCSCTL0.12 to UCSCTL0.8 are set). The
DCOFFG remains set until cleared by the user. If the user clears the DCOFFG and the fault condition
remains, it is automatically set, otherwise it remains cleared. XT2OFFG is set.
The OFIFG oscillator-fault interrupt flag is set and latched at POR or when any oscillator fault
(XT1LFOFFG, XT1HFOFFG, XT2OFFG, or DCOFFG) is detected. When OFIFG is set and OFIE is set,
the OFIFG requests an NMI. When the interrupt is granted, the OFIE is not reset automatically as it is in
previous MSP430 families. It is no longer required to reset the OFIE. NMI entry and exit circuitry removes
this requirement. The OFIFG flag must be cleared by software. The source of the fault can be identified by
checking the individual fault bits.
If a fault is detected for the oscillator sourcing MCLK, MCLK is automatically switched to the DCO for its
clock source (DCOCLKDIV) for all clock sources except XT1 LF mode. If MCLK is sourced from XT1 in LF
mode, an oscillator fault causes MCLK to be automatically switched to the REFO for its clock source
(REFOCLK). This does not change the SELM bit settings. This condition must be handled by user
software.
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If a fault is detected for the oscillator sourcing SMCLK, SMCLK is automatically switched to the DCO for
its clock source (DCOCLKDIV) for all clock sources except XT1 LF mode. If SMCLK is sourced from XT1
in LF mode, an oscillator fault causes SMCLK to be automatically switched to the REFO for its clock
source (REFOCLK). This does not change the SELS bit settings. This condition must be handled by user
software.
If a fault is detected for the oscillator sourcing ACLK, ACLK is automatically switched to the DCO for its
clock source (DCOCLKDIV) for all clock sources except XT1 LF mode. If ACLK is sourced from XT1 in LF
mode, an oscillator fault causes ACLK to be automatically switched to the REFO for its clock source
(REFOCLK). This does not change the SELA bit settings. This condition must be handled by user
software.
NOTE:
DCO active during oscillator fault
DCOCLKDIV is active even at the lowest DCO tap. The clock signal is available for the CPU
to execute code and service an NMI during an oscillator fault.
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DCO _ Fault
S
S
Q
DCO _ OF
Q
DCOFFG
R
R
R
POR
XT 1 _ LF _ OscFault
S
S
Q
Q
XT 1 _ LFOF
XT 1 LFOFFG
R
R
R
XT 1 _ HF _ OscFault
S
S
Q
Q
XT 1 _ HFOF
XT 1 HFOFFG
R
R
R
XT 2 _ OscFault
S
S
Q
Q
XT 2 OFFG
XT 2 _ OF
OscFault_Set
R
R
S
R
OFIFG
NMIRS
Q
Q
OscFault_Clr
S
PUC
R
OFIE
Q
R
NMI _ IRQA
Figure 3-4. Oscillator Fault Logic
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Fault conditions
DCO_Fault: DCOFFG is set if DCO bits in UCSCTL0 register value equals {0} or {31}.
XT1_LF_OscFault: This signal is set after the XT1 (LF mode) oscillator has stopped
operation and cleared after operation resumes. The fault condition causes XT1LFOFFG to
be set and remain set. If the user clears XT1LFOFFG and the fault condition still exists,
XT1LFOFFG remains set.
XT1_HF_OscFault: This signal is set after the XT1 (HF mode) oscillator has stopped
operation and cleared after operation resumes. The fault condition causes XT1HFOFFG to
be set and remain set. If the user clears XT1HFOFFG and the fault condition still exists,
XT1HFOFFG remains set.
XT2_OscFault: This signal is set after the XT2 oscillator has stopped operation and cleared
after operation resumes. The fault condition causes XT2OFFG to be set and remain set. If
the user clears XT2OFFG and the fault condition still exists, XT2OFFG remains set.
NOTE:
Fault logic
Please note that as long as a fault condition still exists, the OFIFG remains set. The
application must take special care when clearing the OFIFG signal. If no fault condition
remains when the OFIFG signal is cleared, the clock logic switches back to the original user
settings prior to the fault condition.
NOTE:
Fault logic counters
Each crystal oscillator circuit has hardware counters. These counters are reset each time a
fault condition occurs on its respective oscillator, causing the fault flag to be set. The
counters begin to count after the fault condition is removed. Once the maximum count is
reached, the fault flag is removed.
In XT1 LF mode, the maximum count is 8192. In XT1 HF mode (and XT2 when available),
the maximum count is 1024. In bypass modes, regardless of LF or HF settings, the
maximum count is 8192.
3.2.13 Synchronization of Clock Signals
When switching MCLK or SMCLK from one clock source to the another, the switch is synchronized to
avoid critical race conditions as shown in Figure 3-5:
• The current clock cycle continues until the next rising edge.
• The clock remains high until the next rising edge of the new clock.
• The new clock source is selected and continues with a full high period.
Select
ACLK
DCOCLK
ACLK
MCLK
DCOCLK
Wait for
ACLK
ACLK
Figure 3-5. Switch MCLK from DCOCLK to XT1CLK
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3.3
Module Oscillator (MODOSC)
The UCS module also supports an internal oscillator, MODOSC, that is used by the flash memory
controller module and, optionally, by other modules in the system. The MODOSC sources MODCLK.
3.3.1 MODOSC Operation
To conserve power, MODOSC is powered down when not needed and enabled only when required. When
the MODOSC source is required, the respective module requests it. MODOSC is enabled based on
unconditional and conditional requests. Setting MODOSCREQEN enables conditional requests.
Unconditional requests are always enabled. It is not necessary to set MODOSCREQEN for modules that
use unconditional requests; for example, flash controller or ADC12_A.
The flash memory controller only requires MODCLK when performing write or erase operations. When
performing such operations, the flash memory controller issues an unconditional request for the MODOSC
source. Upon doing so, the MODOSC source is enabled, if not already enabled from other modules'
previous requests.
The ADC12_A may optionally use MODOSC as a clock source for its conversion clock. The user chooses
the ADC12OSC as the conversion clock source. During a conversion, the ADC12_A module issues an
unconditional request for the ADC12OSC clock source. Upon doing so, the MODOSC source is enabled, if
not already enabled from other modules' previous requests.
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UCS Module Registers
The UCS module registers are listed in Table 3-2. The base address can be found in the device-specific
data sheet. The address offset is listed in Table 3-2.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 3-2. UCS Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
UCSCTL0
Unified Clock System Control 0
Section 3.4.1
Read/write
Word
0000h
00h
UCSCTL0_L
Read/write
Byte
00h
01h
UCSCTL0_H
Read/write
Byte
00h
Read/write
Word
0020h
Read/write
Byte
20h
Read/write
Byte
00h
Read/write
Word
101Fh
02h
UCSCTL1_L
03h
UCSCTL1_H
04h
Unified Clock System Control 2
UCSCTL2_L
Read/write
Byte
1Fh
05h
UCSCTL2_H
Read/write
Byte
10h
Read/write
Word
0000h
UCSCTL3
Unified Clock System Control 3
06h
UCSCTL3_L
Read/write
Byte
00h
07h
UCSCTL3_H
Read/write
Byte
00h
Read/write
Word
0044h
08h
UCSCTL4
Unified Clock System Control 4
08h
UCSCTL4_L
Read/write
Byte
44h
09h
UCSCTL4_H
Read/write
Byte
00h
Read/write
Word
0000h
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
C1CDh
Read/write
Byte
CDh
Read/write
Byte
C1h
Read/write
Word
0703h
Read/write
Byte
03h
Read/write
Byte
07h
Read/write
Word
0707h
Read/write
Byte
07h
Read/write
Byte
07h
0Ah
UCSCTL5
0Ah
UCSCTL5_L
0Bh
UCSCTL5_H
0Ch
UCSCTL6
0Ch
UCSCTL6_L
0Dh
UCSCTL6_H
0Eh
UCSCTL7
0Eh
UCSCTL7_L
0Fh
UCSCTL7_H
10h
UCSCTL8
10h
UCSCTL8_L
11h
UCSCTL8_H
12h
120
UCSCTL2
Unified Clock System Control 1
04h
06h
(1)
UCSCTL1
02h
UCSCTL9
Unified Clock System Control 5
Unified Clock System Control 6
Unified Clock System Control 7
Unified Clock System Control 8
Unified Clock System Control 9
(1)
Read/write
Word
0000h
12h
UCSCTL9_L
Read/write
Byte
00h
13h
UCSCTL9_H
Read/write
Byte
00h
Section 3.4.2
Section 3.4.3
Section 3.4.4
Section 3.4.5
Section 3.4.6
Section 3.4.7
Section 3.4.8
Section 3.4.9
Section 3.4.10
This register is not available on all devices. See the device-specific data sheet.
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3.4.1 UCSCTL0 Register
Unified Clock System Control 0 Register
Figure 3-6. UCSCTL0 Register
15
14
13
12
11
r0
rw-0
rw-0
rw-0
5
4
3
2
Reserved
r0
r0
7
6
10
8
rw-0
rw-0
1
0
DCO
MOD
rw-0
9
rw-0
Reserved
rw-0
rw-0
rw-0
r0
r0
r0
Table 3-3. UCSCTL0 Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Always reads as 0.
12-8
DCO
RW
0h
DCO tap selection. These bits select the DCO tap and are modified automatically
during FLL operation.
7-3
MOD
RW
0h
Modulation bit counter. These bits select the modulation pattern. All MOD bits
are modified automatically during FLL operation. The DCO register value is
incremented when the modulation bit counter rolls over from 31 to 0. If the
modulation bit counter decrements from 0 to the maximum count, the DCO
register value is also decremented.
2-0
Reserved
R
0h
Reserved. Always reads as 0.
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3.4.2 UCSCTL1 Register
Unified Clock System Control 1 Register
Figure 3-7. UCSCTL1 Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
Reserved
Reserved
r0
DCORSEL
rw-0
rw-1
2
Reserved
rw-0
r0
r0
1
0
Reserved
DISMOD
rw-0
rw-0
Table 3-4. UCSCTL1 Register Description
Bit
Field
Type
Reset
Description
15-7
Reserved
R
0h
Reserved. Always reads as 0.
6-4
DCORSEL
RW
2h
DCO frequency range select. These bits select the DCO frequency range of
operation defined in the device-specific datasheet.
3-2
Reserved
R
0h
Reserved. Always reads as 0.
1
Reserved
RW
0h
Reserved. Always reads as 0.
0
DISMOD
RW
0h
Modulation. This bit enables or disables the modulation.
0b = Modulation enabled
1b = Modulation disabled
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3.4.3 UCSCTL2 Register
Unified Clock System Control 2 Register
Figure 3-8. UCSCTL2 Register
15
14
13
Reserved
12
11
10
9
r0
r0
rw-0
rw-0
3
2
1
0
rw-1
rw-1
rw-1
rw-1
FLLD
Reserved
r0
rw-0
rw-0
rw-1
7
6
5
4
8
FLLN
FLLN
rw-0
rw-0
rw-0
rw-1
Table 3-5. UCSCTL2 Register Description
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads as 0.
14-12
FLLD
RW
1h
FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This
results in an additional multiplier for the multiplier bits. See also multiplier bits.
000b = f(DCOCLK)/1
001b = f(DCOCLK)/2
010b = f(DCOCLK)/4
011b = f(DCOCLK)/8
100b = f(DCOCLK)/16
101b = f(DCOCLK)/32
110b = Reserved for future use. Defaults to f(DCOCLK)/32.
111b = Reserved for future use. Defaults to f(DCOCLK)/32.
11-10
Reserved
R
0h
Reserved. Always reads as 0.
9-0
FLLN
RW
1Fh
Multiplier bits. These bits set the multiplier value N of the DCO. N must be
greater than 0. Writing zero to FLLN causes N to be set to 1.
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3.4.4 UCSCTL3 Register
Unified Clock System Control 3 Register
Figure 3-9. UCSCTL3 Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
Reserved
Reserved
r0
SELREF
rw-0
rw-0
Reserved
rw-0
r0
FLLREFDIV
rw-0
rw-0
rw-0
Table 3-6. UCSCTL3 Register Description
Bit
Field
Type
Reset
Description
15-7
Reserved
R
0h
Reserved. Always reads as 0.
6-4
SELREF
RW
0h
FLL reference select. These bits select the FLL reference clock source.
000b = XT1CLK
001b = Reserved for future use. Defaults to XT1CLK.
010b = REFOCLK
011b = Reserved for future use. Defaults to REFOCLK.
100b = Reserved for future use. Defaults to REFOCLK.
101b = XT2CLK when available, otherwise REFOCLK.
110b = Reserved for future use. XT2CLK when available, otherwise REFOCLK.
111b =
3
Reserved
R
0h
Reserved. Always reads as 0.
2-0
FLLREFDIV
RW
0h
FLL reference divider. These bits define the divide factor for f(FLLREFCLK). The
divided frequency is used as the FLL reference frequency.
000b = f(FLLREFCLK)/1
001b = f(FLLREFCLK)/2
010b = f(FLLREFCLK)/4
011b = f(FLLREFCLK)/8
100b = f(FLLREFCLK)/12
101b = f(FLLREFCLK)/16
110b = Reserved for future use. Defaults to f(FLLREFCLK)/16.
111b = Reserved for future use. Defaults to f(FLLREFCLK)/16.
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3.4.5 UCSCTL4 Register
Unified Clock System Control 4 Register
Figure 3-10. UCSCTL4 Register
15
14
r0
r0
7
6
13
12
11
10
r0
r0
r0
rw-0
5
4
3
2
Reserved
Reserved
r0
Reserved
rw-0
8
SELA
SELS
rw-1
9
rw-0
r0
rw-0
rw-0
1
0
SELM
rw-1
rw-0
rw-0
Table 3-7. UCSCTL4 Register Description
Bit
Field
Type
Reset
Description
15-11
Reserved
R
0h
Reserved. Always reads as 0.
10-8
SELA
RW
0h
Selects the ACLK source
000b = XT1CLK
001b = VLOCLK
010b = REFOCLK
011b = DCOCLK
100b = DCOCLKDIV
101b = XT2CLK when available, otherwise DCOCLKDIV
110b = Reserved for future use. Defaults to XT2CLK.
111b = Reserved for future use. Defaults to XT2CLK.
7
Reserved
R
0h
Reserved. Always reads as 0.
6-4
SELS
RW
4h
Selects the SMCLK source
000b = XT1CLK
001b = VLOCLK
010b = REFOCLK
011b = DCOCLK
100b = DCOCLKDIV
101b = XT2CLK when available, otherwise DCOCLKDIV
110b = Reserved for future use. Defaults to XT2CLK.
111b = Reserved for future use. Defaults to XT2CLK.
3
Reserved
R
0h
Reserved. Always reads as 0.
2-0
SELM
RW
4h
Selects the MCLK source
000b = XT1CLK
001b = VLOCLK
010b = REFOCLK
011b = DCOCLK
100b = DCOCLKDIV
101b = XT2CLK when available, otherwise DCOCLKDIV
110b = Reserved for future use. Defaults to XT2CLK.
111b = Reserved for future use. Defaults to XT2CLK.
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3.4.6 UCSCTL5 Register
Unified Clock System Control 5 Register
Figure 3-11. UCSCTL5 Register
15
14
13
Reserved
DIVPA
r0
rw-0
7
6
Reserved
r0
12
10
Reserved
rw-0
rw-0
5
4
DIVS
rw-0
11
rw-0
rw-0
3
2
r0
8
DIVA
r0
Reserved
rw-0
9
rw-0
rw-0
1
0
DIVM
rw-0
rw-0
rw-0
Table 3-8. UCSCTL5 Register Description
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads as 0.
14-12
DIVPA
RW
0h
ACLK source divider available at external pin. Divides the frequency of ACLK
and presents it to an external pin.
000b = f(ACLK)/1
001b = f(ACLK)/2
010b = f(ACLK)/4
011b = f(ACLK)/8
100b = f(ACLK)/16
101b = f(ACLK)/32
110b = Reserved for future use. Defaults to f(ACLK)/32.
111b = Reserved for future use. Defaults to f(ACLK)/32.
11
Reserved
R
0h
Reserved. Always reads as 0.
10-8
DIVA
RW
0h
ACLK source divider. Divides the frequency of the ACLK clock source.
000b = f(ACLK)/1
001b = f(ACLK)/2
010b = f(ACLK)/4
011b = f(ACLK)/8
100b = f(ACLK)/16
101b = f(ACLK)/32
110b = Reserved for future use. Defaults to f(ACLK)/32.
111b = Reserved for future use. Defaults to f(ACLK)/32.
7
Reserved
R
0h
Reserved. Always reads as 0.
6-4
DIVS
RW
0h
SMCLK source divider
000b = f(SMCLK)/1
001b = f(SMCLK)/2
010b = f(SMCLK)/4
011b = f(SMCLK)/8
100b = f(SMCLK)/16
101b = f(SMCLK)/32
110b = Reserved for future use. Defaults to f(SMCLK)/32.
111b = Reserved for future use. Defaults to f(SMCLK)/32.
3
Reserved
R
0h
Reserved. Always reads as 0.
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Table 3-8. UCSCTL5 Register Description (continued)
Bit
Field
Type
Reset
Description
2-0
DIVM
RW
0h
MCLK source divider
000b = f(MCLK)/1
001b = f(MCLK)/2
010b = f(MCLK)/4
011b = f(MCLK)/8
100b = f(MCLK)/16
101b = f(MCLK)/32
110b = Reserved for future use. Defaults to f(MCLK)/32.
111b = Reserved for future use. Defaults to f(MCLK)/32.
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3.4.7 UCSCTL6 Register
Unified Clock System Control 6 Register
Figure 3-12. UCSCTL6 Register
15
14
13
r0
r0
r0
12
11
10
9
r0
r0
r0
r0
3
Reserved
7
6
XT1DRIVE (1)
rw-1
(1)
rw-1
5
4
XTS
XT1BYPASS
rw-0
rw-0
8
XT2OFF
2
XCAP (1)
rw-1
rw-1
rw-1
1
0
SMCLKOFF
XT1OFF
rw-0
rw-1
The configuration of these bits is retained during LPM3.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPM3.5 before clearing LOCKLPM5 is required.
Table 3-9. UCSCTL6 Register Description
Bit
Field
Type
Reset
Description
15-9
Reserved
R
0h
Reserved. Always reads as 0.
8
XT2OFF
RW
1h
Turns off the XT2 oscillator
0b = XT2 is on
1b = XT2 is off if it is not used by the radio; that is, if the radio is not in sleep
state
7-6
XT1DRIVE
RW
3h
The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts
with the highest supply current for reliable and quick startup. If needed, user
software can reduce the drive strength.
00b = Lowest current consumption for XT1 LF mode. XT1 oscillator operating
range in HF mode is 4 MHz to 8 MHz.
01b = Increased drive strength for XT1 LF mode. XT1 oscillator operating range
in HF mode is 8 MHz to 16 MHz.
10b = Increased drive capability for XT1 LF mode. XT1 oscillator operating range
in HF mode is 16 MHz to 24 MHz.
11b = Maximum drive capability and maximum current consumption for XT1 LF
mode. XT1 oscillator operating range in HF mode is 24 MHz to 32 MHz.
5
XTS
RW
0h
XT1 mode select
0b = Low-frequency mode. XCAP bits define the capacitance at the XIN and
XOUT pins.
1b = High-frequency mode. XCAP bits are not used.
4
XT1BYPASS
RW
0h
XT1 bypass select
0b = XT1 sourced internally
1b = XT1 sourced externally from pin
3-2
XCAP
RW
3h
Oscillator capacitor selection. These bits select the capacitors applied to the LF
crystal or resonator in the LF mode (XTS = 0). The effective capacitance (seen
by the crystal) is C(eff) ≈ (C(XIN) + 2 pF) / 2. It is assumed that
C(XIN) = C(XOUT) and that a parasitic capacitance of 2 pF is added by the
package and the printed circuit board. For details about the typical internal and
the effective capacitors, see the device-specific data sheet.
1
SMCLKOFF
RW
0h
SMCLK off. This bit turns off the SMCLK.
0b = SMCLK on
1b = SMCLK off
0
XT1OFF
RW
1h
XT1 off. This bit turns off the XT1.
0b = XT1 is on if XT1 is selected via the port selection and XT1 is not in bypass
mode of operation.
1b = XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not
used as a reference source required for FLL operation.
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3.4.8 UCSCTL7 Register
Unified Clock System Control 7 Register
Figure 3-13. UCSCTL7 Register
15
14
13
r0
rw-0
6
5
Reserved
11
rw-(0)
rw-(1)
Reserved
r0
7
Reserved
r0
(1)
12
r0
r0
10
9
rw-(1)
r-1
Reserved
8
Reserved
r-1
4
3
2
1
0
Reserved
XT2OFFG (1)
XT1HFOFFG (1)
XT1LFOFFG
DCOFFG
rw-(0)
rw-(0)
rw-(0)
rw-(1)
rw-(1)
Not available on all devices. When not available, this bit is reserved.
Table 3-10. UCSCTL7 Register Description
Bit
Field
Type
Reset
Description
15-14
Reserved
R
0h
Reserved. Always reads as 0.
13-12
Reserved
RW
0h
Reserved. Must always be written with 0.
11-10
Reserved
RW
3h
Reserved. The states of these bits should be ignored.
9-8
Reserved
R
3h
Reserved. The states of these bits should be ignored.
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4
Reserved
RW
0h
Reserved. The state of this bit should be ignored.
RW
0h
XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is
set if a XT2 fault condition exists. XT2OFFG can be cleared via software. If the
XT2 fault condition still remains, XT2OFFG is set.
0b = No fault condition occurred after the last reset.
1b = XT2 fault. An XT2 fault occurred after the last reset.
(1)
3
XT2OFFG
2
XT1HFOFFG (1)
RW
0h
XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set.
XT1HFOFFG is set if a XT1 fault condition exists. XT1HFOFFG can be cleared
via software. If the XT1 fault condition still remains, XT1HFOFFG is set.
0b = No fault condition occurred after the last reset.
1b = XT1 fault. An XT1 fault occurred after the last reset.
1
XT1LFOFFG
RW
1h
XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set.
XT1LFOFFG is set if a XT1 fault condition exists. XT1LFOFFG can be cleared
via software. If the XT1 fault condition still remains, XT1LFOFFG is set.
0b = No fault condition occurred after the last reset.
1b = XT1 fault (LF mode). A XT1 fault occurred after the last reset.
0
DCOFFG
RW
1h
DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is
set if DCO = {0} or DCO = {31}. DCOFFG can be cleared via software. If the
DCO fault condition still remains, DCOFFG is set.
0b = No fault condition occurred after the last reset.
1b = DCO fault. A DCO fault occurred after the last reset.
(1)
Not available on all devices. When not available, this bit is reserved.
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3.4.9 UCSCTL8 Register
Unified Clock System Control 8 Register
Figure 3-14. UCSCTL8 Register
15
14
13
r0
r0
r0
6
5
12
11
10
r0
r0
rw-(1)
Reserved
7
Reserved
r0
r0
r0
9
8
Reserved
rw-(1)
rw-(1)
4
3
2
1
0
Reserved
MODOSCREQ
EN
SMCLKREQEN
MCLKREQEN
ACLKREQEN
rw-(0)
rw-(0)
rw-(1)
rw-(1)
rw-(1)
Table 3-11. UCSCTL8 Register Description
Bit
Field
Type
Reset
Description
15-11
Reserved
R
0h
Reserved. Always reads as 0.
10-8
Reserved
R
0h
Reserved. Must always be written as 1.
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4
Reserved
R
0h
Reserved. Must always be written as 0.
3
MODOSCREQEN
RW
0h
MODOSC clock request enable. Setting this enables conditional module requests
for MODOSC.
0b = MODOSC conditional requests are disabled.
1b = MODOSC conditional requests are enabled.
2
SMCLKREQEN
RW
1h
SMCLK clock request enable. Setting this enables conditional module requests
for SMCLK
0b = SMCLK conditional requests are disabled.
1b = SMCLK conditional requests are enabled.
1
MCLKREQEN
RW
1h
MCLK clock request enable. Setting this enables conditional module requests for
MCLK
0b = MCLK conditional requests are disabled.
1b = MCLK conditional requests are enabled.
0
ACLKREQEN
RW
1h
ACLK clock request enable. Setting this enables conditional module requests for
ACLK
0b = ACLK conditional requests are disabled.
1b = ACLK conditional requests are enabled.
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3.4.10 UCSCTL9 Register
Unified Clock System Control 9 Register
This register is not available on all devices. See the device-specific data sheet.
Figure 3-15. UCSCTL9 Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
4
3
2
1
0
Reserved
r0
r0
r0
7
6
5
Reserved
r0
r0
r0
XT2BYPASSLV XT1BYPASSLV
r0
r0
r0
rw-0
rw-0
Table 3-12. UCSCTL9 Register Description
Bit
Field
Type
Reset
Description
15-2
Reserved
R
0h
Reserved. Always reads as 0.
1
XT2BYPASSLV
RW
0h
Selects XT2 bypass input swing level. Must be set for reduced swing operation.
0b = Input range from 0 to DVCC
1b = Input range from 0 to DVIO
0
XT1BYPASSLV
RW
0h
Selects XT1 bypass input swing level. Must be set for reduced swing operation.
0b = Input range from 0 to DVCC
1b = Input range from 0 to DVIO
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CPUX
This chapter describes the extended MSP430X 16-bit RISC CPU (CPUX) with 1MB memory access, its
addressing modes, and instruction set.
NOTE: The MSP430X CPU implemented on these devices has, in some cases, slightly different
cycle counts from the MSP430X CPU implemented on the 2xx and 4xx families.
132
Topic
...........................................................................................................................
4.1
4.2
4.3
4.4
4.5
4.6
MSP430X CPU (CPUX) Introduction ...................................................................
Interrupts ........................................................................................................
CPU Registers .................................................................................................
Addressing Modes ...........................................................................................
MSP430 and MSP430X Instructions ...................................................................
Instruction Set Description ...............................................................................
CPUX
Page
133
135
136
142
159
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4.1
MSP430X CPU (CPUX) Introduction
The MSP430X CPU incorporates features specifically designed for modern programming techniques, such
as calculated branching, table processing, and the use of high-level languages such as C. The MSP430X
CPU can address a 1MB address range without paging. The MSP430X CPU is completely backward
compatible with the MSP430 CPU.
The MSP430X CPU features include:
• RISC architecture
• Orthogonal architecture
• Full register access including program counter (PC), status register (SR), and stack pointer (SP)
• Single-cycle register operations
• Large register file reduces fetches to memory.
• 20-bit address bus allows direct access and branching throughout the entire memory range without
paging.
• 16-bit data bus allows direct manipulation of word-wide arguments.
• Constant generator provides the six most often used immediate values and reduces code size.
• Direct memory-to-memory transfers without intermediate register holding
• Byte, word, and 20-bit address-word addressing
The block diagram of the MSP430X CPU is shown in Figure 4-1.
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MDB - Memor y Data Bus
19
Memory Address Bus - MAB
0
16 15
R0/PC Program Counter
0
R1/SP Pointer Stack
0
R2/SR Status Register
R3/CG2 Constant Generator
R4
General Purpose
R5
General Purpose
R6
General Purpose
R7
General Purpose
R8
General Purpose
R9
General Purpose
R10
General Purpose
R11
General Purpose
R12
General Purpose
R13
General Purpose
R14
General Purpose
R15
General Purpose
20
16
Zero, Z
Carry, C
Overflow,V
Negative,N
dst
src
MCLK
16/20-bit ALU
Figure 4-1. MSP430X CPU Block Diagram
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4.2
Interrupts
The MSP430X has the following interrupt structure:
• Vectored interrupts with no polling necessary
• Interrupt vectors are located downward from address 0FFFEh.
The interrupt vectors contain 16-bit addresses that point into the lower 64-KB memory. This means all
interrupt handlers must start in the lower 64-KB memory.
During an interrupt, the program counter (PC) and the status register (SR) are pushed onto the stack as
shown in Figure 4-2. The MSP430X architecture stores the complete 20-bit PC value efficiently by
appending the PC bits 19:16 to the stored SR value automatically on the stack. When the RETI instruction
is executed, the full 20-bit PC is restored making return from interrupt to any address in the memory range
possible.
Item n-1
SPold
PC.15:0
SP
PC.19:16
SR.11:0
Figure 4-2. PC Storage on the Stack for Interrupts
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CPU Registers
The CPU incorporates 16 registers (R0 through R15). Registers R0, R1, R2, and R3 have dedicated
functions. Registers R4 through R15 are working registers for general use.
4.3.1 Program Counter (PC)
The 20-bit Program Counter (PC, also called R0) points to the next instruction to be executed. Each
instruction uses an even number of bytes (2, 4, 6, or 8 bytes), and the PC is incremented accordingly.
Instruction accesses are performed on word boundaries, and the PC is aligned to even addresses.
Figure 4-3 shows the PC.
19
16 15
1
Program Counter Bits 19 to 1
0
0
Figure 4-3. Program Counter
The PC can be addressed with all instructions and addressing modes. A few examples:
MOV.W
#LABEL,PC
; Branch to address LABEL (lower 64 KB)
MOVA
#LABEL,PC
; Branch to address LABEL (1MB memory)
MOV.W
LABEL,PC
; Branch to address in word LABEL
; (lower 64 KB)
MOV.W
@R14,PC
; Branch indirect to address in
; R14 (lower 64 KB)
ADDA
#4,PC
; Skip two words (1 MB memory)
The BR and CALL instructions reset the upper four PC bits to 0. Only addresses in the lower 64-KB
address range can be reached with the BR or CALL instruction. When branching or calling, addresses
beyond the lower 64-KB range can only be reached using the BRA or CALLA instructions. Also, any
instruction to directly modify the PC does so according to the used addressing mode. For example,
MOV.W #value,PC clears the upper four bits of the PC, because it is a .W instruction.
The PC is automatically stored on the stack with CALL (or CALLA) instructions and during an interrupt
service routine. Figure 4-4 shows the storage of the PC with the return address after a CALLA instruction.
A CALL instruction stores only bits 15:0 of the PC.
SPold
Item n
PC.19:16
SP
PC.15:0
Figure 4-4. PC Storage on the Stack for CALLA
The RETA instruction restores bits 19:0 of the PC and adds 4 to the stack pointer (SP). The RET
instruction restores bits 15:0 to the PC and adds 2 to the SP.
4.3.2 Stack Pointer (SP)
The 20-bit Stack Pointer (SP, also called R1) is used by the CPU to store the return addresses of
subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be
used by software with all instructions and addressing modes. Figure 4-5 shows the SP. The SP is
initialized into RAM by the user, and is always aligned to even addresses.
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Figure 4-6 shows the stack usage. Figure 4-7 shows the stack usage when 20-bit address words are
pushed.
19
1
Stack Pointer Bits 19 to 1
MOV.W
MOV.W
PUSH
POP
2(SP),R6
R7,0(SP)
#0123h
R8
;
;
;
;
0
0
Copy Item I2 to R6
Overwrite TOS with R7
Put 0123h on stack
R8 = 0123h
Figure 4-5. Stack Pointer
Address
I1
0xxxh
0xxxh - 2
I2
0xxxh - 4
I3
SP
PUSH #0123h
POP R8
I1
I1
I2
I2
I3
I3
SP
0123h
0xxxh - 6
SP
0xxxh - 8
Figure 4-6. Stack Usage
SPold
Item n-1
Item.19:16
SP
Item.15:0
Figure 4-7. PUSHX.A Format on the Stack
The special cases of using the SP as an argument to the PUSH and POP instructions are described and
shown in Figure 4-8.
PUSH SP
POP SP
SPold
SP1
SPold
SP2
The stack pointer is changed after
a PUSH SP instruction.
SP1
The stack pointer is not changed after a POP SP
instruction. The POP SP instruction places SP1 into the
stack pointer SP (SP2 = SP1)
Figure 4-8. PUSH SP, POP SP Sequence
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4.3.3 Status Register (SR)
The 16-bit Status Register (SR, also called R2), used as a source or destination register, can only be used
in register mode addressed with word instructions. The remaining combinations of addressing modes are
used to support the constant generator. Figure 4-9 shows the SR bits. Do not write 20-bit values to the
SR. Unpredictable operation can result.
15
9
Reserved
8
7
V
SCG1
0
SCG0
OSC CPU
GIE
OFF OFF
N
Z C
rw-0
Figure 4-9. SR Bits
Table 4-1 describes the SR bits.
Table 4-1. SR Bit Description
Bit
Description
Reserved
Reserved
V
Overflow. This bit is set when the result of an arithmetic operation overflows the signed-variable range.
ADDC(.B), ADDCX(.B.A),
Set when:
positive + positive = negative
negative + negative = positive
otherwise reset
SUB(.B), SUBX(.B,.A), SUBC(.B),SUBCX(.B,.A),
SUBA, CMP(.B), CMPX(.B,.A), CMPA
Set when:
positive – negative = negative
negative – positive = positive
otherwise reset
ADD(.B), ADDX(.B,.A),
ADDA
SCG1
System clock generator 1. This bit may be used to enable or disable functions in the clock system depending on the
device family; for example, DCO bias enable or disable.
SCG0
System clock generator 0. This bit may be used to enable or disable functions in the clock system depending on the
device family; for example, FLL enable or disable.
OSCOFF
Oscillator off. This bit, when set, turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or
SMCLK.
CPUOFF
CPU off. This bit, when set, turns off the CPU.
SCG1
The bits CPUOFF, OSCOFF, SCG0 and SCG1 request the system to enter a low-power mode
SCG0
OSCOFF
CPUOFF
GIE
General interrupt enable. This bit, when set, enables maskable interrupts. When reset, all maskable interrupts are
disabled.
N
Negative. This bit is set when the result of an operation is negative and cleared when the result is positive.
Z
Zero. This bit is set when the result of an operation is 0 and cleared when the result is not 0.
C
Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred.
NOTE: Bit manipulations of the SR should be done by the following instructions: MOV, BIS, and
BIC.
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4.3.4 Constant Generator Registers (CG1 and CG2)
Six commonly-used constants are generated with the constant generator registers R2 (CG1) and R3
(CG2), without requiring an additional 16-bit word of program code. The constants are selected with the
source register addressing modes (As), as described in Table 4-2.
Table 4-2. Values of Constant Generators CG1, CG2
Register
As
Constant
Remarks
R2
00
–
Register mode
R2
01
(0)
Absolute address mode
R2
10
00004h
+4, bit processing
R2
11
00008h
+8, bit processing
R3
00
00000h
0, word processing
R3
01
00001h
+1
R3
10
00002h
+2, bit processing
R3
11
FFh, FFFFh, FFFFFh
–1, word processing
The constant generator advantages are:
• No special instructions required
• No additional code word for the six constants
• No code memory access required to retrieve the constant
The assembler uses the constant generator automatically if one of the six constants is used as an
immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed
explicitly; they act as source-only registers.
4.3.4.1
Constant Generator – Expanded Instruction Set
The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows
the MSP430 assembler to support 24 additional emulated instructions. For example, the single-operand
instruction:
CLR dst
is emulated by the double-operand instruction with the same length:
MOV R3,dst
where the #0 is replaced by the assembler, and R3 is used with As = 00.
INC dst
is replaced by:
ADD 0(R3),dst
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4.3.5 General-Purpose Registers (R4 –R15)
The 12 CPU registers (R4 to R15) contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register
clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction.
The SXT instruction extends the sign through the complete 20-bit register.
Figure 4-10 through Figure 4-14 show the handling of byte, word, and address-word data. Note the reset
of the leading most significant bits (MSBs) if a register is the destination of a byte or word instruction.
Figure 4-10 shows byte handling (8-bit data, .B suffix). The handling is shown for a source register and a
destination memory byte and for a source memory byte and a destination register.
Register-Byte Operation
Byte-Register Operation
High Byte Low Byte
19 16 15
0
87
Un- Unused
Register
used
High Byte
Memory
19 16 15
Memory
Low Byte
Unused
87
0
Unused
Operation
Register
Operation
Memory
0
0
Register
Figure 4-10. Register-Byte and Byte-Register Operation
Figure 4-11 and Figure 4-12 show 16-bit word handling (.W suffix). The handling is shown for a source
register and a destination memory word and for a source memory word and a destination register.
Register-Word Operation
High Byte Low Byte
19 16 15
0
87
UnRegister
used
Memory
Operation
Memory
Figure 4-11. Register-Word Operation
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Word-Register Operation
High Byte
Low Byte
Memory
19 16 15
Unused
87
0
Register
Operation
Register
0
Figure 4-12. Word-Register Operation
Figure 4-13 and Figure 4-14 show 20-bit address-word handling (.A suffix). The handling is shown for a
source register and a destination memory address-word and for a source memory address-word and a
destination register.
Register - Ad dress-Word Operation
High Byte Low Byte
19 16 15
0
87
Register
Memory +2
Unused
Memory
Operation
Memory +2
0
Memory
Figure 4-13. Register – Address-Word Operation
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Address-Word - Register Operation
High Byte Low Byte
19 16 15
0
87
Memory +2
Unused
Memory
Register
Operation
Register
Figure 4-14. Address-Word – Register Operation
4.4
Addressing Modes
Seven addressing modes for the source operand and four addressing modes for the destination operand
use 16-bit or 20-bit addresses (see Table 4-3). The MSP430 and MSP430X instructions are usable
throughout the entire 1MB memory range.
Table 4-3. Source and Destination Addressing
As, Ad Addressing Mode
Syntax
Description
00, 0
Register
Rn
01, 1
Indexed
X(Rn)
(Rn + X) points to the operand. X is stored in the next word, or stored in combination of
the preceding extension word and the next word.
01, 1
Symbolic
ADDR
(PC + X) points to the operand. X is stored in the next word, or stored in combination of
the preceding extension word and the next word. Indexed mode X(PC) is used.
01, 1
Absolute
&ADDR
The word following the instruction contains the absolute address. X is stored in the next
word, or stored in combination of the preceding extension word and the next word.
Indexed mode X(SR) is used.
10, –
Indirect Register
@Rn
Rn is used as a pointer to the operand.
11, –
Indirect
Autoincrement
@Rn+
Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B
instructions, by 2 for .W instructions, and by 4 for .A instructions.
11, –
Immediate
#N
Register contents are operand.
N is stored in the next word, or stored in combination of the preceding extension word
and the next word. Indirect autoincrement mode @PC+ is used.
The seven addressing modes are explained in detail in the following sections. Most of the examples show
the same addressing mode for the source and destination, but any valid combination of source and
destination addressing modes is possible in an instruction.
NOTE:
Use of Labels EDE, TONI, TOM, and LEO
Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels.
They are only labels and have no special meaning.
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4.4.1 Register Mode
Operation:
Length:
Comment:
Byte operation:
Word operation:
Address-word
operation:
SXT exception:
Example:
The operand is the 8-, 16-, or 20-bit content of the used CPU register.
One, two, or three words
Valid for source and destination
Byte operation reads only the eight least significant bits (LSBs) of the source
register Rsrc and writes the result to the eight LSBs of the destination register Rdst.
The bits Rdst.19:8 are cleared. The register Rsrc is not modified.
Word operation reads the 16 LSBs of the source register Rsrc and writes the result
to the 16 LSBs of the destination register Rdst. The bits Rdst.19:16 are cleared.
The register Rsrc is not modified.
Address-word operation reads the 20 bits of the source register Rsrc and writes the
result to the 20 bits of the destination register Rdst. The register Rsrc is not
modified
The SXT instruction is the only exception for register operation. The sign of the low
byte in bit 7 is extended to the bits Rdst.19:8.
BIS.W R5,R6 ;
This instruction logically ORs the 16-bit data contained in R5 with the 16-bit
contents of R6. R6.19:16 is cleared.
Before:
After:
Address
Space
21036h
21034h
Register
Address
Space
xxxxh
R5
AA550h
21036h
xxxxh
D506h
R6
11111h
21034h
D506h
PC
Register
PC
R5
AA550h
R6
0B551h
A550h.or.1111h = B551h
Example:
BISX.A R5,R6 ;
This instruction logically ORs the 20-bit data contained in R5 with the 20-bit
contents of R6.
The extension word contains the A/L bit for 20-bit data. The instruction word uses
byte mode with bits A/L:B/W = 01. The result of the instruction is:
Before:
After:
Address
Space
Register
Address
Space
21036h
xxxxh
R5
AA550h
21036h
xxxxh
21034h
D546h
R6
11111h
21034h
D546h
21032h
1800h
21032h
1800h
PC
Register
PC
R5
AA550h
R6
BB551h
AA550h.or.11111h = BB551h
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4.4.2 Indexed Mode
The Indexed mode calculates the address of the operand by adding the signed index to a CPU register.
The Indexed mode has three addressing possibilities:
• Indexed mode in lower 64-KB memory
• MSP430 instruction with Indexed mode addressing memory above the lower 64-KB memory
• MSP430X instruction with Indexed mode
4.4.2.1
Indexed Mode in Lower 64-KB Memory
If the CPU register Rn points to an address in the lower 64 KB of the memory range, the calculated
memory address bits 19:16 are cleared after the addition of the CPU register Rn and the signed 16-bit
index. This means the calculated memory address is always located in the lower 64 KB and does not
overflow or underflow out of the lower 64-KB memory space. The RAM and the peripheral registers can be
accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4-15.
Lower 64 KB
Rn.19:16 = 0
19 16 15
FFFFF
0
CPU Register Rn
0
S
16-bit byte index
16-bit signed index
Rn.19:0
00000
Lower 64KB
10000
0FFFF
16-bit signed add
0
Memory address
Figure 4-15. Indexed Mode in Lower 64 KB
Length:
Operation:
Comment:
Example:
Source:
Destination:
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Two or three words
The signed 16-bit index is located in the next word after the instruction and is added to
the CPU register Rn. The resulting bits 19:16 are cleared giving a truncated 16-bit
memory address, which points to an operand address in the range 00000h to 0FFFFh.
The operand is the content of the addressed memory location.
Valid for source and destination. The assembler calculates the register index and inserts
it.
ADD.B 1000h(R5),0F000h(R6);
This instruction adds the 8-bit data contained in source byte 1000h(R5) and the
destination byte 0F000h(R6) and places the result into the destination byte. Source and
destination bytes are both located in the lower 64 KB due to the cleared bits 19:16 of
registers R5 and R6.
The byte pointed to by R5 + 1000h results in address 0479Ch + 1000h = 0579Ch after
truncation to a 16-bit address.
The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after
truncation to a 16-bit address.
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Before:
After:
Address
Space
4.4.2.2
Register
Address
Space
Register
1103Ah
xxxxh
R5
0479Ch
1103Ah
xxxxh
PC R5
0479Ch
11038h
F000h
R6
01778h
11038h
F000h
R6
01778h
11036h
1000h
11036h
1000h
11034h
55D6h
11034h
55D6h
0077Ah
xxxxh
0077Ah
xxxxh
00778h
xx45h
01778h
+F000h
00778h
00778h
xx77h
0579Eh
xxxxh
0579Eh
xxxxh
0579Ch
xx32h
0479Ch
+1000h
0579Ch
0579Ch
xx32h
PC
32h
+45h
77h
src
dst
Sum
MSP430 Instruction With Indexed Mode in Upper Memory
If the CPU register Rn points to an address above the lower 64-KB memory, the Rn bits 19:16 are used
for the address calculation of the operand. The operand may be located in memory in the range Rn ±32
KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow
or underflow into the lower 64-KB memory space (see Figure 4-16 and Figure 4-17).
Upper Memory
Rn.19:16 > 0
19
FFFFF
16 15
0
1 ... 15
Rn.19:0
CPU Register Rn
Rn ± 32 KB
S
Lower 64 KB
10000
0FFFF
00000
S
16-bit byte index
16-bit signed index
(sign extended to 20 bits)
20-bit signed add
Memory address
Figure 4-16. Indexed Mode in Upper Memory
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Rn.19:0
10000
0,FFFF
Rn.19:0
Rn.19:0
Lower 64 KB
Rn.19:0
±32 KB
±32 KB
FFFFF
0000C
Figure 4-17. Overflow and Underflow for Indexed Mode
Length:
Operation:
Comment:
Example:
Source:
Destination:
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Two or three words
The sign-extended 16-bit index in the next word after the instruction is added to the
20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an
address in the range 0 to FFFFFh. The operand is the content of the addressed
memory location.
Valid for source and destination. The assembler calculates the register index and
inserts it.
ADD.W 8346h(R5),2100h(R6) ;
This instruction adds the 16-bit data contained in the source and the destination
addresses and places the 16-bit result into the destination. Source and destination
operand can be located in the entire address range.
The word pointed to by R5 + 8346h. The negative index 8346h is sign extended,
which results in address 23456h + F8346h = 1B79Ch.
The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h.
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Before:
After:
Address
Space
Register
Address
Space
Register
1103Ah
xxxxh
R5
23456h
1103Ah
xxxxh
PC R5
23456h
11038h
2100h
R6
15678h
11038h
2100h
R6
15678h
11036h
8346h
11036h
8346h
11034h
5596h
11034h
5596h
1777Ah
xxxxh
1777Ah
xxxxh
17778h
2345h
15678h
+02100h
17778h
17778h
7777h
1B79Eh
xxxxh
1B79Eh
xxxxh
1B79Ch
5432h
23456h
+F8346h
1B79Ch
1B79Ch
5432h
PC
05432h
+02345h
07777h
src
dst
Sum
Figure 4-18. Example for Indexed Mode
4.4.2.3
MSP430X Instruction With Indexed Mode
When using an MSP430X instruction with Indexed mode, the operand can be located anywhere in the
range of Rn + 19 bits.
Length:
Operation:
Comment:
Example:
Source:
Destination:
Three or four words
The operand address is the sum of the 20-bit CPU register content and the 20-bit
index. The 4 MSBs of the index are contained in the extension word; the 16 LSBs
are contained in the word following the instruction. The CPU register is not modified
Valid for source and destination. The assembler calculates the register index and
inserts it.
ADDX.A 12346h(R5),32100h(R6) ;
This instruction adds the 20-bit data contained in the source and the destination
addresses and places the result into the destination.
Two words pointed to by R5 + 12346h which results in address 23456h + 12346h =
3579Ch.
Two words pointed to by R6 + 32100h which results in address 45678h + 32100h =
77778h.
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The extension word contains the MSBs of the source index and of the destination index and the A/L bit for
20-bit data. The instruction word uses byte mode due to the 20-bit data length with bits A/L:B/W = 01.
Before:
After:
Address
Space
2103Ah
xxxxh
21038h
2100h
21036h
Register
Address
Space
Register
23456h
2103Ah
xxxxh
PC R5
23456h
45678h
21038h
2100h
R6
45678h
2346h
21036h
2346h
21034h
55D6h
21034h
55D6h
21032h
1883h
21032h
1883h
7777Ah
0001h
7777Ah
0007h
77778h
2345h
45678h
+32100h
77778h
77778h
7777h
3579Eh
0006h
3579Eh
0006h
3579Ch
5432h
23456h
+12346h
3579Ch
3579Ch
5432h
R5
R6
PC
65432h
+12345h
77777h
src
dst
Sum
4.4.3 Symbolic Mode
The Symbolic mode calculates the address of the operand by adding the signed index to the PC. The
Symbolic mode has three addressing possibilities:
• Symbolic mode in lower 64-KB memory
• MSP430 instruction with Symbolic mode addressing memory above the lower 64-KB memory.
• MSP430X instruction with Symbolic mode
4.4.3.1
Symbolic Mode in Lower 64 KB
If the PC points to an address in the lower 64 KB of the memory range, the calculated memory address
bits 19:16 are cleared after the addition of the PC and the signed 16-bit index. This means the calculated
memory address is always located in the lower 64 KB and does not overflow or underflow out of the lower
64-KB memory space. The RAM and the peripheral registers can be accessed this way and existing
MSP430 software is usable without modifications as shown in Figure 4-19.
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Lower 64 KB
PC.19:16 = 0
19 16 15
FFFFF
0
Program
counter PC
0
S
Lower 64 KB
10000
0FFFF
PC.19:0
00000
16-bit byte index
16-bit signed
PC index
16-bit signed add
0
Memory address
Figure 4-19. Symbolic Mode Running in Lower 64 KB
Operation:
Length:
Comment:
Example:
Source:
Destination:
The signed 16-bit index in the next word after the instruction is added temporarily to
the PC. The resulting bits 19:16 are cleared giving a truncated 16-bit memory
address, which points to an operand address in the range 00000h to 0FFFFh. The
operand is the content of the addressed memory location.
Two or three words
Valid for source and destination. The assembler calculates the PC index and
inserts it.
ADD.B EDE,TONI ;
This instruction adds the 8-bit data contained in source byte EDE and destination
byte TONI and places the result into the destination byte TONI. Bytes EDE and
TONI and the program are located in the lower 64 KB.
Byte EDE located at address 0579Ch, pointed to by PC + 4766h, where the PC
index 4766h is the result of 0579Ch – 01036h = 04766h. Address 01036h is the
location of the index for this example.
Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated
16-bit result of 00778h – 1038h = FF740h. Address 01038h is the location of the
index for this example.
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Before:
After:
Address
Space
4.4.3.2
Address
Space
0103Ah
xxxxh
0103Ah
xxxxh
01038h
F740h
01038h
F740h
01036h
4766h
01036h
4766h
01034h
05D0h
01034h
50D0h
0077Ah
xxxxh
0077Ah
xxxxh
00778h
xx45h
01038h
+0F740h
00778h
00778h
xx77h
0579Eh
xxxxh
0579Eh
xxxxh
0579Ch
xx32h
01036h
+04766h
0579Ch
0579Ch
xx32h
PC
PC
32h
+45h
77h
src
dst
Sum
MSP430 Instruction With Symbolic Mode in Upper Memory
If the PC points to an address above the lower 64-KB memory, the PC bits 19:16 are used for the address
calculation of the operand. The operand may be located in memory in the range PC ± 32 KB, because the
index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into
the lower 64-KB memory space as shown in Figure 4-20 and Figure 4-21.
Upper Memory
PC.19:16 > 0
19
FFFFF
16 15
0
Program
counter PC
1 ... 15
PC.19:0
PC ±32 KB
10000
0FFFF
00000
Lower 64 KB
S
S
16-bit byte index
16-bit signed PC index
(sign extended to 20 bits)
20-bit signed add
Memory address
Figure 4-20. Symbolic Mode Running in Upper Memory
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PC.19:0
PC.19:0
PC.19:0
Lower 64 KB
10000
0FFFF
PC.19:0
±32 KB
±32 KB
FFFFF
0000C
Figure 4-21. Overflow and Underflow for Symbolic Mode
Length:
Operation:
Comment:
Two or three words
The sign-extended 16-bit index in the next word after the instruction is added to the
20 bits of the PC. This delivers a 20-bit address, which points to an address in the
range 0 to FFFFFh. The operand is the content of the addressed memory location.
Valid for source and destination. The assembler calculates the PC index and
inserts it
Example:
ADD.W EDE,&TONI ;
Source:
This instruction adds the 16-bit data contained in source word EDE and destination
word TONI and places the 16-bit result into the destination word TONI. For this
example, the instruction is located at address 2F034h.
Word EDE at address 3379Ch, pointed to by PC + 4766h, which is the 16-bit result
of 3379Ch – 2F036h = 04766h. Address 2F036h is the location of the index for this
example.
Word TONI located at address 00778h pointed to by the absolute address 00778h
Destination:
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Before:
After:
Address
Space
4.4.3.3
Address
Space
2F03Ah
xxxxh
2F03Ah
xxxxh
2F038h
0778h
2F038h
0778h
2F036h
4766h
2F036h
4766h
2F034h
5092h
2F034h
5092h
3379Eh
xxxxh
3379Eh
xxxxh
3379Ch
5432h
3379Ch
5432h
0077Ah
xxxxh
0077Ah
xxxxh
00778h
2345h
00778h
7777h
PC
2F036h
+04766h
3379Ch
PC
5432h
+2345h
7777h
src
dst
Sum
MSP430X Instruction With Symbolic Mode
When using an MSP430X instruction with Symbolic mode, the operand can be located anywhere in the
range of PC + 19 bits.
Length:
Operation:
Comment:
Example:
Source:
Destination:
152
CPUX
Three or four words
The operand address is the sum of the 20-bit PC and the 20-bit index. The 4 MSBs
of the index are contained in the extension word; the 16 LSBs are contained in the
word following the instruction.
Valid for source and destination. The assembler calculates the register index and
inserts it.
ADDX.B EDE,TONI ;
This instruction adds the 8-bit data contained in source byte EDE and destination
byte TONI and places the result into the destination byte TONI.
Byte EDE located at address 3579Ch, pointed to by PC + 14766h, is the 20-bit
result of 3579Ch – 21036h = 14766h. Address 21036h is the address of the index
in this example.
Byte TONI located at address 77778h, pointed to by PC + 56740h, is the 20-bit
result of 77778h – 21038h = 56740h. Address 21038h is the address of the index in
this example.
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Before: Address Space
After:
Address Space
2103Ah
xxxxh
2103Ah
xxxxh
21038h
6740h
21038h
6740h
21036h
4766h
21036h
4766h
21034h
50D0h
21034h
50D0h
21032h
18C5h
21032h
18C5h
7777Ah
xxxxh
7777Ah
xxxxh
77778h
xx45h
21038h
+56740h
77778h
77778h
xx77h
3579Eh
xxxxh
3579Eh
xxxxh
3579Ch
xx32h
21036h
+14766h
3579Ch
3579Ch
xx32h
PC
PC
32h
+45h
77h
src
dst
Sum
4.4.4 Absolute Mode
The Absolute mode uses the contents of the word following the instruction as the address of the operand.
The Absolute mode has two addressing possibilities:
• Absolute mode in lower 64-KB memory
• MSP430X instruction with Absolute mode
4.4.4.1
Absolute Mode in Lower 64 KB
If an MSP430 instruction is used with Absolute addressing mode, the absolute address is a 16-bit value
and, therefore, points to an address in the lower 64 KB of the memory range. The address is calculated as
an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers
can be accessed this way and existing MSP430 software is usable without modifications.
Length:
Operation:
Comment:
Two or three words
The operand is the content of the addressed memory location.
Valid for source and destination. The assembler calculates the index from 0 and
inserts it.
Example:
ADD.W &EDE,&TONI ;
Source:
Destination:
This instruction adds the 16-bit data contained in the absolute source and
destination addresses and places the result into the destination.
Word at address EDE
Word at address TONI
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Before: Address Space
Address Space
xxxxh
xxxxh
2103Ah
21038h
7778h
21038h
7778h
2103Ah
4.4.4.2
After:
21036h
579Ch
21034h
5292h
xxxxh
0777Ah
xxxxh
07778h
2345h
07778h
7777h
0579Eh
xxxxh
0579Eh
xxxxh
0579Ch
5432h
0579Ch
5432h
21036h
579Ch
21034h
5292h
0777Ah
PC
PC
5432h
+2345h
7777h
src
dst
Sum
MSP430X Instruction With Absolute Mode
If an MSP430X instruction is used with Absolute addressing mode, the absolute address is a 20-bit value
and, therefore, points to any address in the memory range. The address value is calculated as an index
from 0. The 4 MSBs of the index are contained in the extension word, and the 16 LSBs are contained in
the word following the instruction.
154
Length:
Operation:
Comment:
Three or four words
The operand is the content of the addressed memory location.
Valid for source and destination. The assembler calculates the index from 0 and
inserts it.
Example:
ADDX.A &EDE,&TONI ;
Source:
Destination:
This instruction adds the 20-bit data contained in the absolute source and
destination addresses and places the result into the destination.
Two words beginning with address EDE
Two words beginning with address TONI
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Before:
After:
Address
Space
Address
Space
2103Ah
xxxxh
2103Ah
xxxxh
21038h
7778h
21038h
7778h
21036h
579Ch
21036h
579Ch
21034h
52D2h
21034h
52D2h
21032h
1987h
21032h
1987h
7777Ah
0001h
7777Ah
0007h
77778h
2345h
77778h
7777h
3579Eh
0006h
3579Eh
0006h
3579Ch
5432h
3579Ch
5432h
PC
PC
65432h
+12345h
77777h
src
dst
Sum
4.4.5 Indirect Register Mode
The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand. The
Indirect Register mode always uses a 20-bit address.
Length:
Operation:
Comment:
One, two, or three words
The operand is the content the addressed memory location. The source register
Rsrc is not modified.
Valid only for the source operand. The substitute for the destination operand is
0(Rdst).
Example:
ADDX.W @R5,2100h(R6)
Source:
Destination:
This instruction adds the two 16-bit operands contained in the source and the
destination addresses and places the result into the destination.
Word pointed to by R5. R5 contains address 3579Ch for this example.
Word pointed to by R6 + 2100h, which results in address 45678h + 2100h = 7778h
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Before:
After:
Address
Space
Register
Address
Space
Register
21038h
xxxxh
R5
3579Ch
21038h
xxxxh
PC R5
3579Ch
21036h
2100h
R6
45678h
21036h
2100h
R6
45678h
21034h
55A6h
21034h
55A6h
4777Ah
xxxxh
4777Ah
xxxxh
47778h
2345h
47778h
7777h
3579Eh
xxxxh
3579Eh
xxxxh
3579Ch
5432h
3579Ch
5432h
PC
45678h
+02100h
47778h
R5
5432h
+2345h
7777h
src
dst
Sum
R5
4.4.6 Indirect Autoincrement Mode
The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand. Rsrc
is then automatically incremented by 1 for byte instructions, by 2 for word instructions, and by 4 for
address-word instructions immediately after accessing the source operand. If the same register is used for
source and destination, it contains the incremented address for the destination access. Indirect
Autoincrement mode always uses 20-bit addresses.
Length:
Operation:
Comment:
Example:
Source:
Destination:
156
CPUX
One, two, or three words
The operand is the content of the addressed memory location.
Valid only for the source operand
ADD.B @R5+,0(R6)
This instruction adds the 8-bit data contained in the source and the destination
addresses and places the result into the destination.
Byte pointed to by R5. R5 contains address 3579Ch for this example.
Byte pointed to by R6 + 0h, which results in address 0778h for this example
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Before:
After:
Address
Space
Register
Address
Space
Register
21038h
xxxxh
R5
3579Ch
21038h
xxxxh
PC R5
3579Dh
21036h
0000h
R6
00778h
21036h
0000h
R6
00778h
21034h
55F6h
21034h
55F6h
0077Ah
xxxxh
0077Ah
xxxxh
00778h
xx45h
00778h
xx77h
3579Dh
xxh
3579Dh
xxh
3579Ch
32h
3579Ch
xx32h
PC
00778h
+0000h
00778h
R5
32h
+45h
77h
src
dst
Sum
R5
4.4.7 Immediate Mode
The Immediate mode allows accessing constants as operands by including the constant in the memory
location following the instruction. The PC is used with the Indirect Autoincrement mode. The PC points to
the immediate value contained in the next word. After the fetching of the immediate operand, the PC is
incremented by 2 for byte, word, or address-word instructions. The Immediate mode has two addressing
possibilities:
• 8-bit or 16-bit constants with MSP430 instructions
• 20-bit constants with MSP430X instruction
4.4.7.1
MSP430 Instructions With Immediate Mode
If an MSP430 instruction is used with Immediate addressing mode, the constant is an 8- or 16-bit value
and is stored in the word following the instruction.
Length:
Operation:
Comment:
Example:
Source:
Destination:
Two or three words. One word less if a constant of the constant generator can be
used for the immediate operand.
The 16-bit immediate source operand is used together with the 16-bit destination
operand.
Valid only for the source operand
ADD #3456h,&TONI
This instruction adds the 16-bit immediate operand 3456h to the data in the
destination address TONI.
16-bit immediate value 3456h
Word at address TONI
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Before:
After:
Address
Space
4.4.7.2
Address
Space
2103Ah
xxxxh
2103Ah
xxxxh
21038h
0778h
21038h
0778h
21036h
3456h
21036h
3456h
21034h
50B2h
21034h
50B2h
0077Ah
xxxxh
0077Ah
xxxxh
00778h
2345h
00778h
579Bh
PC
PC
3456h
+2345h
579Bh
src
dst
Sum
MSP430X Instructions With Immediate Mode
If an MSP430X instruction is used with Immediate addressing mode, the constant is a 20-bit value. The 4
MSBs of the constant are stored in the extension word, and the 16 LSBs of the constant are stored in the
word following the instruction.
Length:
Three or four words. One word less if a constant of the constant generator can be
used for the immediate operand.
The 20-bit immediate source operand is used together with the 20-bit destination
operand.
Valid only for the source operand
Operation:
Comment:
Example:
ADDX.A #23456h,&TONI ;
This instruction adds the 20-bit immediate operand 23456h to the data in the
destination address TONI.
20-bit immediate value 23456h
Two words beginning with address TONI
Source:
Destination:
Before:
After:
Address
Space
Address
Space
158
CPUX
2103Ah
xxxxh
2103Ah
xxxxh
21038h
7778h
21038h
7778h
21036h
3456h
21036h
3456h
21034h
50F2h
21032h
1907h
21034h
50F2h
21032h
1907h
7777Ah
0001h
7777Ah
0003h
77778h
2345h
77778h
579Bh
PC
PC
23456h
+12345h
3579Bh
src
dst
Sum
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4.5
MSP430 and MSP430X Instructions
MSP430 instructions are the 27 implemented instructions of the MSP430 CPU. These instructions are
used throughout the 1MB memory range unless their 16-bit capability is exceeded. The MSP430X
instructions are used when the addressing of the operands or the data length exceeds the 16-bit capability
of the MSP430 instructions.
There are three possibilities when choosing between an MSP430 and MSP430X instruction:
• To use only the MSP430 instructions – The only exceptions are the CALLA and the RETA instruction.
This can be done if a few, simple rules are met:
– Place all constants, variables, arrays, tables, and data in the lower 64 KB. This allows the use of
MSP430 instructions with 16-bit addressing for all data accesses. No pointers with 20-bit addresses
are needed.
– Place subroutine constants immediately after the subroutine code. This allows the use of the
symbolic addressing mode with its 16-bit index to reach addresses within the range of PC + 32 KB.
• To use only MSP430X instructions – The disadvantages of this method are the reduced speed due to
the additional CPU cycles and the increased program space due to the necessary extension word for
any double-operand instruction.
• Use the best fitting instruction where needed.
Section 4.5.1 lists and describes the MSP430 instructions, and Section 4.5.2 lists and describes the
MSP430X instructions.
4.5.1 MSP430 Instructions
The MSP430 instructions can be used, regardless if the program resides in the lower 64 KB or beyond it.
The only exceptions are the instructions CALL and RET, which are limited to the lower 64-KB address
range. CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the
entire address range with no code size overhead.
4.5.1.1
MSP430 Double-Operand (Format I) Instructions
Figure 4-22 shows the format of the MSP430 double-operand instructions. Source and destination words
are appended for the Indexed, Symbolic, Absolute, and Immediate modes. Table 4-4 lists the 12 MSP430
double-operand instructions.
15
12
11
Op-code
8
Rsrc
7
6
5
Ad B/W
4
As
0
Rdst
Source or Destination 15:0
Destination 15:0
Figure 4-22. MSP430 Double-Operand Instruction Format
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Table 4-4. MSP430 Double-Operand Instructions
Mnemonic
S-Reg, DReg
Operation
MOV(.B)
src,dst
ADD(.B)
src,dst
ADDC(.B)
SUB(.B)
(1)
V
N
Z
C
src → dst
–
–
–
–
src + dst → dst
*
*
*
*
src,dst
src + dst + C → dst
*
*
*
*
src,dst
dst + .not.src + 1 → dst
*
*
*
*
SUBC(.B)
src,dst
dst + .not.src + C → dst
*
*
*
*
CMP(.B)
src,dst
dst - src
*
*
*
*
DADD(.B)
src,dst
src + dst + C → dst (decimally)
*
*
*
*
BIT(.B)
src,dst
src .and. dst
0
*
*
Z
BIC(.B)
src,dst
.not.src .and. dst → dst
–
–
–
–
BIS(.B)
src,dst
src .or. dst → dst
–
–
–
–
XOR(.B)
src,dst
src .xor. dst → dst
*
*
*
Z
AND(.B)
src,dst
src .and. dst → dst
0
*
*
Z
(1)
4.5.1.2
Status Bits
* = Status bit is affected.
– = Status bit is not affected.
0 = Status bit is cleared.
1 = Status bit is set.
MSP430 Single-Operand (Format II) Instructions
Figure 4-23 shows the format for MSP430 single-operand instructions, except RETI. The destination word
is appended for the Indexed, Symbolic, Absolute, and Immediate modes. Table 4-5 lists the seven singleoperand instructions.
15
7
Op-code
6
5
B/W
4
0
Ad
Rdst
Destination 15:0
Figure 4-23. MSP430 Single-Operand Instructions
Table 4-5. MSP430 Single-Operand Instructions
Status Bits
(1)
Mnemonic
S-Reg, DReg
Operation
V
N
Z
C
RRC(.B)
dst
C → MSB →.......LSB → C
0
*
*
*
RRA(.B)
dst
MSB → MSB →....LSB → C
0
*
*
*
PUSH(.B)
src
SP - 2 → SP, src → SP
–
–
–
–
SWPB
dst
bit 15...bit 8 ↔ bit 7...bit 0
–
–
–
–
CALL
dst
Call subroutine in lower 64 KB
–
–
–
–
TOS → SR, SP + 2 → SP
*
*
*
*
0
*
*
Z
RETI
TOS → PC,SP + 2 → SP
SXT
(1)
160
CPUX
dst
Register mode: bit 7 → bit 8...bit 19
Other modes: bit 7 → bit 8...bit 15
* = Status bit is affected.
– = Status bit is not affected.
0 = Status bit is cleared.
1 = Status bit is set.
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4.5.1.3
Jump Instructions
Figure 4-24 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset
of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit PC.
This allows jumps in a range of –511 to +512 words relative to the PC in the full 20-bit address space.
Jumps do not affect the status bits. Table 4-6 lists and describes the eight jump instructions.
15
13
12
Op-Code
10
Condition
9
8
S
0
10-Bit Signed PC Offset
Figure 4-24. Format of Conditional Jump Instructions
Table 4-6. Conditional Jump Instructions
4.5.1.4
Mnemonic
S-Reg, D-Reg
Operation
JEQ, JZ
Label
Jump to label if zero bit is set
JNE, JNZ
Label
Jump to label if zero bit is reset
JC
Label
Jump to label if carry bit is set
JNC
Label
Jump to label if carry bit is reset
JN
Label
Jump to label if negative bit is set
JGE
Label
Jump to label if (N .XOR. V) = 0
JL
Label
Jump to label if (N .XOR. V) = 1
JMP
Label
Jump to label unconditionally
Emulated Instructions
In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make
code easier to write and read, but do not have op-codes themselves. Instead, they are replaced
automatically by the assembler with a core instruction. There is no code or performance penalty for using
emulated instructions. The emulated instructions are listed in Table 4-7.
Table 4-7. Emulated Instructions
Status Bits
(1)
Instruction
Explanation
Emulation
V
N
Z
C
ADC(.B) dst
Add Carry to dst
ADDC(.B) #0,dst
*
*
*
*
BR dst
Branch indirectly dst
MOV dst,PC
–
–
–
–
CLR(.B) dst
Clear dst
MOV(.B) #0,dst
–
–
–
–
CLRC
Clear Carry bit
BIC #1,SR
–
–
–
0
CLRN
Clear Negative bit
BIC #4,SR
–
0
–
–
CLRZ
Clear Zero bit
BIC #2,SR
–
–
0
–
DADC(.B) dst
Add Carry to dst decimally
DADD(.B) #0,dst
*
*
*
*
DEC(.B) dst
*
*
*
*
Decrement dst by 1
SUB(.B) #1,dst
DECD(.B) dst
Decrement dst by 2
SUB(.B) #2,dst
*
*
*
*
DINT
Disable interrupt
BIC #8,SR
–
–
–
–
EINT
Enable interrupt
BIS #8,SR
–
–
–
–
INC(.B) dst
Increment dst by 1
ADD(.B) #1,dst
*
*
*
*
INCD(.B) dst
Increment dst by 2
ADD(.B) #2,dst
*
*
*
*
INV(.B) dst
Invert dst
XOR(.B) #–1,dst
*
*
*
*
(1)
* = Status bit is affected.
– = Status bit is not affected.
0 = Status bit is cleared.
1 = Status bit is set.
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Table 4-7. Emulated Instructions (continued)
4.5.1.5
Instruction
Explanation
Emulation
NOP
No operation
POP dst
Pop operand from stack
RET
RLA(.B) dst
Status Bits
(1)
V
N
Z
C
MOV R3,R3
–
–
–
–
MOV @SP+,dst
–
–
–
–
Return from subroutine
MOV @SP+,PC
–
–
–
–
Shift left dst arithmetically
ADD(.B) dst,dst
*
*
*
*
RLC(.B) dst
Shift left dst logically through Carry
ADDC(.B) dst,dst
*
*
*
*
SBC(.B) dst
Subtract Carry from dst
SUBC(.B) #0,dst
*
*
*
*
SETC
Set Carry bit
BIS #1,SR
–
–
–
1
SETN
Set Negative bit
BIS #4,SR
–
1
–
–
SETZ
Set Zero bit
BIS #2,SR
–
–
1
–
TST(.B) dst
Test dst (compare with 0)
CMP(.B) #0,dst
0
*
*
1
MSP430 Instruction Execution
The number of CPU clock cycles required for an instruction depends on the instruction format and the
addressing modes used – not the instruction itself. The number of clock cycles refers to MCLK.
4.5.1.5.1 Instruction Cycles and Length for Interrupt, Reset, and Subroutines
Table 4-8 lists the length and the CPU cycles for reset, interrupts, and subroutines.
Table 4-8. Interrupt, Return, and Reset Cycles and Length
Execution Time
(MCLK Cycles)
Length of Instruction
(Words)
Return from interrupt RETI
5
1
Return from subroutine RET
4
1
Interrupt request service (cycles needed before first
instruction)
6
–
WDT reset
4
–
Reset (RST/NMI)
4
–
Action
4.5.1.5.2 Format II (Single-Operand) Instruction Cycles and Lengths
Table 4-9 lists the length and the CPU cycles for all addressing modes of the MSP430 single-operand
instructions.
Table 4-9. MSP430 Format II Instruction Cycles and Length
No. of Cycles
RRA, RRC
SWPB, SXT
PUSH
CALL
Length of
Instruction
Rn
1
3
4
1
SWPB R5
@Rn
3
3
4
1
RRC @R9
@Rn+
3
3
4
1
SWPB @R10+
N/A
3
4
2
CALL #LABEL
X(Rn)
4
4
5
2
CALL 2(R7)
EDE
4
4
5
2
PUSH EDE
&EDE
4
4
6
2
SXT &EDE
Addressing Mode
#N
162
CPUX
Example
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4.5.1.5.3 Jump Instructions Cycles and Lengths
All jump instructions require one code word and take two CPU cycles to execute, regardless of whether
the jump is taken or not.
4.5.1.5.4 Format I (Double-Operand) Instruction Cycles and Lengths
Table 4-10 lists the length and CPU cycles for all addressing modes of the MSP430 Format I instructions.
Table 4-10. MSP430 Format I Instructions Cycles and Length
Addressing Mode
No. of Cycles
Length of
Instruction
Rm
1
1
MOV R5,R8
PC
3
1
BR R9
4 (1)
2
ADD R5,4(R6)
EDE
4
(1)
2
XOR R8,EDE
&EDE
4 (1)
2
MOV R5,&EDE
Rm
2
1
AND @R4,R5
PC
4
1
BR @R8
x(Rm)
5
(1)
2
XOR @R5,8(R6)
EDE
5 (1)
2
MOV @R5,EDE
(1)
Source
Rn
Destination
x(Rm)
@Rn
&EDE
@Rn+
5
2
XOR @R5,&EDE
Rm
2
1
ADD @R5+,R6
PC
4
1
BR @R9+
x(Rm)
5
(1)
2
XOR @R5,8(R6)
EDE
5 (1)
2
MOV @R9+,EDE
(1)
&EDE
#N
5
Rm
PC
BR #2AEh
3
MOV #0300h,0(SP)
EDE
5
(1)
3
ADD #33,EDE
&EDE
5 (1)
3
ADD #33,&EDE
Rm
3
2
MOV 2(R5),R7
PC
5
2
BR 2(R6)
6 (1)
3
MOV 4(R7),TONI
x(Rm)
6
(1)
3
ADD 4(R4),6(R9)
&TONI
6 (1)
3
MOV 2(R4),&TONI
Rm
3
2
AND EDE,R6
PC
5
2
BR EDE
TONI
6
(1)
3
CMP EDE,TONI
x(Rm)
6 (1)
3
MOV EDE,0(SP)
(1)
3
MOV EDE,&TONI
Rm
6
3
2
MOV &EDE,R8
PC
5
2
BR &EDE
TONI
6
(1)
3
MOV &EDE,TONI
x(Rm)
6 (1)
3
MOV &EDE,0(SP)
(1)
3
MOV &EDE,&TONI
&TONI
(1)
MOV #20,R9
2
&TONI
&EDE
MOV @R9+,&EDE
2
3
TONI
EDE
2
2
5 (1)
x(Rm)
x(Rn)
Example
6
MOV, BIT, and CMP instructions execute in one fewer cycle.
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4.5.2 MSP430X Extended Instructions
The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Most
MSP430X instructions require an additional word of op-code called the extension word. Some extended
instructions do not require an additional word and are noted in the instruction description. All addresses,
indexes, and immediate numbers have 20-bit values when preceded by the extension word.
There are two types of extension words:
• Register or register mode for Format I instructions and register mode for Format II instructions
• Extension word for all other address mode combinations
4.5.2.1
Register Mode Extension Word
The register mode extension word is shown in Figure 4-25 and described in Table 4-11. An example is
shown in Figure 4-27.
15
12
11
10
1
0001
9
00
8
7
6
5
4
ZC
#
A/L
0
0
3
0
(n-1)/Rn
Figure 4-25. Extension Word for Register Modes
Table 4-11. Description of the Extension Word Bits for Register Mode
Bit
Description
15:11
Extension word op-code. Op-codes 1800h to 1FFFh are extension words.
10:9
Reserved
ZC
Zero carry
#
The executed instruction uses the status of the carry bit C.
1
The executed instruction uses the carry bit as 0. The carry bit is defined by the result of the final operation after
instruction execution.
Repetition
A/L
4.5.2.2
0
0
The number of instruction repetitions is set by extension word bits 3:0.
1
The number of instruction repetitions is defined by the value of the four LSBs of Rn. See description for bits 3:0.
Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data
length of the instruction.
A/L
B/W
Comment
0
0
Reserved
0
1
20-bit address word
1
0
16-bit word
1
1
8-bit byte
5:4
Reserved
3:0
Repetition count
#=0
These four bits set the repetition count n. These bits contain n – 1.
#=1
These four bits define the CPU register whose bits 3:0 set the number of repetitions. Rn.3:0 contain n – 1.
Non-Register Mode Extension Word
The extension word for non-register modes is shown in Figure 4-26 and described in Table 4-12. An
example is shown in Figure 4-28.
15
0
0
0
12
11
1
1
10
7
Source bits 19:16
6
5
4
A/L
0
0
3
0
Destination bits 19:16
Figure 4-26. Extension Word for Non-Register Modes
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Table 4-12. Description of Extension Word Bits for Non-Register Modes
Bit
Description
15:11
Extension word op-code. Op-codes 1800h to 1FFFh are extension words.
Source Bits The four MSBs of the 20-bit source. Depending on the source addressing mode, these four MSBs may belong to an
19:16
immediate operand, an index, or to an absolute address.
A/L
Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used
data length of the instruction.
A/L
5:4
B/W Comment
0
0
Reserved
0
1
20-bit address word
1
0
16-bit word
1
1
8-bit byte
Reserved
Destination The four MSBs of the 20-bit destination. Depending on the destination addressing mode, these four MSBs may
Bits 19:16 belong to an index or to an absolute address.
NOTE:
B/W and A/L bit settings for SWPBX and SXTX
A/L
0
0
1
1
15
14
13
12
11
0
0
0
1
1
Op-code
XORX.A
B/W
0
1
0
1
10
SWPBX.A, SXTX.A
N/A
SWPB.W, SXTX.W
N/A
9
00
8
7
6
5
ZC
#
A/L
Ad B/W
Rsrc
4
3
2
1
Rsvd
(n-1)/Rn
As
Rdst
0
R9,R8
1: Repetition count
in bits 3:0
0: Use Carry
0
0
0
1
1
14(XOR)
0
9
XORX instruction
0
01:Address word
0
0
0
0
0
1
0
8(R8)
Destination R8
Source R9
Destination
register mode
Source
register mode
Figure 4-27. Example for Extended Register or Register Instruction
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15
14
13
12
11
0
0
0
1
1
10
9
8
7
Source 19:16
Op-code
6
A/L
Ad B/W
Rsrc
5
4
3
2
1
0
Rsvd
Destination 19:16
As
Rdst
Source 15:0
Destination 15:0
XORX.A #12345h, 45678h(R15)
X(Rn)
18xx extension word
0
0
0
1
01: Address
word
@PC+
12345h
1
1
14 (XOR)
0 (PC)
1
0
0
4
1
3
15 (R15)
Immediate operand LSBs: 2345h
Index destination LSBs: 5678h
Figure 4-28. Example for Extended Immediate or Indexed Instruction
4.5.2.3
Extended Double-Operand (Format I) Instructions
All 12 double-operand instructions have extended versions as listed in Table 4-13.
Table 4-13. Extended Double-Operand Instructions
Mnemonic
Operands
Operation
MOVX(.B,.A)
src,dst
ADDX(.B,.A)
src,dst
ADDCX(.B,.A)
SUBX(.B,.A)
CPUX
(1)
V
N
Z
C
src → dst
–
–
–
–
src + dst → dst
*
*
*
*
src,dst
src + dst + C → dst
*
*
*
*
src,dst
dst + .not.src + 1 → dst
*
*
*
*
SUBCX(.B,.A)
src,dst
dst + .not.src + C → dst
*
*
*
*
CMPX(.B,.A)
src,dst
dst – src
*
*
*
*
DADDX(.B,.A)
src,dst
src + dst + C → dst (decimal)
*
*
*
*
BITX(.B,.A)
src,dst
src .and. dst
0
*
*
Z
BICX(.B,.A)
src,dst
.not.src .and. dst → dst
–
–
–
–
BISX(.B,.A)
src,dst
src .or. dst → dst
–
–
–
–
XORX(.B,.A)
src,dst
src .xor. dst → dst
*
*
*
Z
ANDX(.B,.A)
src,dst
src .and. dst → dst
0
*
*
Z
(1)
166
Status Bits
* = Status bit is affected.
– = Status bit is not affected.
0 = Status bit is cleared.
1 = Status bit is set.
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The four possible addressing combinations for the extension word for Format I instructions are shown in
Figure 4-29.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
1
1
0
0
ZC
#
A/L
0
0
n-1/Rn
0
B/W
0
0
dst
A/L
0
0
src
Op-code
0
0
0
1
1
src.19:16
Op-code
Ad B/W
src
3
0
0
0
0
0
dst
As
src.15:0
0
0
0
1
1
0
0
0
src
Op-code
0
A/L
0
Ad B/W
dst.19:16
0
As
dst
dst.15:0
0
0
0
1
1
src.19:16
src
Op-code
A/L
0
Ad B/W
0
dst.19:16
As
dst
src.15:0
dst.15:0
Figure 4-29. Extended Format I Instruction Formats
If the 20-bit address of a source or destination operand is located in memory, not in a CPU register, then
two words are used for this operand as shown in Figure 4-30.
15
Address+2
14
13
12
11
10
9
8
7
6
5
4
0 .......................................................................................0
3
2
1
0
19:16
Operand LSBs 15:0
Address
Figure 4-30. 20-Bit Addresses in Memory
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Extended Single-Operand (Format II) Instructions
Extended MSP430X Format II instructions are listed in Table 4-14.
Table 4-14. Extended Single-Operand Instructions
Status Bits
Mnemonic
Operands
Operation
CALLA
dst
Call indirect to subroutine (20-bit address)
POPM.A
#n,Rdst
Pop n 20-bit registers from stack
POPM.W
#n,Rdst
Pop n 16-bit registers from stack
PUSHM.A
#n,Rsrc
PUSHM.W
#n,Rsrc
PUSHX(.B,.A)
src
Push 8-, 16-, or 20-bit source to stack
RRCM(.A)
#n,Rdst
Rotate right Rdst n bits through carry (16-, 20-bit register)
1 to 4
RRUM(.A)
#n,Rdst
Rotate right Rdst n bits unsigned (16-, 20-bit register)
RRAM(.A)
#n,Rdst
RLAM(.A)
#n,Rdst
RRCX(.B,.A)
dst
RRUX(.B,.A)
Rdst
RRAX(.B,.A)
SWPBX(.A)
V
N
Z
C
–
–
–
–
1 to 16
–
–
–
–
1 to 16
–
–
–
–
Push n 20-bit registers to stack
1 to 16
–
–
–
–
Push n 16-bit registers to stack
1 to 16
–
–
–
–
–
–
–
–
0
*
*
*
1 to 4
0
*
*
*
Rotate right Rdst n bits arithmetically (16-, 20-bit register)
1 to 4
0
*
*
*
Rotate left Rdst n bits arithmetically (16-, 20-bit register)
1 to 4
*
*
*
*
Rotate right dst through carry (8-, 16-, 20-bit data)
1
0
*
*
*
Rotate right dst unsigned (8-, 16-, 20-bit)
1
0
*
*
*
dst
Rotate right dst arithmetically
1
0
*
*
*
dst
Exchange low byte with high byte
1
–
–
–
–
SXTX(.A)
Rdst
Bit7 → bit8 ... bit19
1
0
*
*
Z
SXTX(.A)
dst
Bit7 → bit8 ... MSB
1
0
*
*
Z
(1)
n
(1)
* = Status bit is affected.
– = Status bit is not affected.
0 = Status bit is cleared.
1 = Status bit is set.
The three possible addressing mode combinations for Format II instructions are shown in Figure 4-31.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
1
1
0
0
ZC
#
A/L
0
0
n-1/Rn
B/W
0
0
dst
A/L
0
0
B/W
1
x
dst
A/L
0
0
dst.19:16
B/W
x
1
dst
Op-code
0
0
0
1
1
0
0
0
0
Op-code
0
0
0
1
1
0
0
0
0
Op-code
3
0
0
0
0
0
dst.15:0
Figure 4-31. Extended Format II Instruction Format
168
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4.5.2.4.1 Extended Format II Instruction Format Exceptions
Exceptions for the Format II instruction formats are shown in Figure 4-32 through Figure 4-35.
15
8
7
Op-code
4
3
n-1
0
Rdst - n+1
Figure 4-32. PUSHM and POPM Instruction Format
15
12
11
C
10
9
4
n-1
3
Op-code
0
Rdst
Figure 4-33. RRCM, RRAM, RRUM, and RLAM Instruction Format
15
12
11
8
7
4
3
0
C
Rsrc
Op-code
0(PC)
C
#imm/abs19:16
Op-code
0(PC)
#imm15:0 / &abs15:0
C
Rsrc
Op-code
0(PC)
index15:0
Figure 4-34. BRA Instruction Format
15
4
3
0
Op-code
Rdst
Op-code
Rdst
index15:0
Op-code
#imm/ix/abs19:16
#imm15:0 / index15:0 / &abs15:0
Figure 4-35. CALLA Instruction Format
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Extended Emulated Instructions
The extended instructions together with the constant generator form the extended emulated instructions.
Table 4-15 lists the emulated instructions.
Table 4-15. Extended Emulated Instructions
170
Instruction
Explanation
Emulation
ADCX(.B,.A) dst
Add carry to dst
ADDCX(.B,.A) #0,dst
BRA dst
Branch indirect dst
MOVA dst,PC
RETA
Return from subroutine
MOVA @SP+,PC
CLRA Rdst
Clear Rdst
MOV #0,Rdst
CLRX(.B,.A) dst
Clear dst
MOVX(.B,.A) #0,dst
DADCX(.B,.A) dst
Add carry to dst decimally
DADDX(.B,.A) #0,dst
DECX(.B,.A) dst
Decrement dst by 1
SUBX(.B,.A) #1,dst
DECDA Rdst
Decrement Rdst by 2
SUBA #2,Rdst
DECDX(.B,.A) dst
Decrement dst by 2
SUBX(.B,.A) #2,dst
INCX(.B,.A) dst
Increment dst by 1
ADDX(.B,.A) #1,dst
INCDA Rdst
Increment Rdst by 2
ADDA #2,Rdst
INCDX(.B,.A) dst
Increment dst by 2
ADDX(.B,.A) #2,dst
INVX(.B,.A) dst
Invert dst
XORX(.B,.A) #-1,dst
RLAX(.B,.A) dst
Shift left dst arithmetically
ADDX(.B,.A) dst,dst
RLCX(.B,.A) dst
Shift left dst logically through carry
ADDCX(.B,.A) dst,dst
SBCX(.B,.A) dst
Subtract carry from dst
SUBCX(.B,.A) #0,dst
TSTA Rdst
Test Rdst (compare with 0)
CMPA #0,Rdst
TSTX(.B,.A) dst
Test dst (compare with 0)
CMPX(.B,.A) #0,dst
POPX dst
Pop to dst
MOVX(.B, .A) @SP+,dst
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4.5.2.6
MSP430X Address Instructions
MSP430X address instructions are instructions that support 20-bit operands but have restricted
addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode,
except for the MOVA instruction as listed in Table 4-16. Restricting the addressing modes removes the
need for the additional extension-word op-code improving code density and execution time. Address
instructions should be used any time an MSP430X instruction is needed with the corresponding restricted
addressing mode.
Table 4-16. Address Instructions, Operate on 20-Bit Register Data
Status Bits
(1)
Mnemonic
Operands
Operation
V
N
Z
C
ADDA
Rsrc,Rdst
Add source to destination register
*
*
*
*
Move source to destination
–
–
–
–
Compare source to destination register
*
*
*
*
Subtract source from destination register
*
*
*
*
#imm20,Rdst
MOVA
Rsrc,Rdst
#imm20,Rdst
z16(Rsrc),Rdst
EDE,Rdst
&abs20,Rdst
@Rsrc,Rdst
@Rsrc+,Rdst
Rsrc,z16(Rdst)
Rsrc,&abs20
CMPA
Rsrc,Rdst
#imm20,Rdst
SUBA
Rsrc,Rdst
#imm20,Rdst
(1)
* = Status bit is affected.
– = Status bit is not affected.
0 = Status bit is cleared.
1 = Status bit is set.
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MSP430X Instruction Execution
The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format
and the addressing modes used, not the instruction itself. The number of clock cycles refers to MCLK.
4.5.2.7.1 MSP430X Format II (Single-Operand) Instruction Cycles and Lengths
Table 4-17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended singleoperand instructions.
Table 4-17. MSP430X Format II Instruction Cycles and Length
Instruction
@Rn
@Rn+
#N
X(Rn)
EDE
&EDE
RRAM
n, 1
–
–
–
–
–
–
RRCM
n, 1
–
–
–
–
–
–
RRUM
n, 1
–
–
–
–
–
–
RLAM
n, 1
–
–
–
–
–
–
PUSHM
2+n, 1
–
–
–
–
–
–
PUSHM.A
2+2n, 1
–
–
–
–
–
–
POPM
2+n, 1
–
–
–
–
–
–
POPM.A
2+2n, 1
–
–
–
–
–
–
5, 1
6, 1
6, 1
5, 2
5 (1), 2
7, 2
7, 2
RRAX(.B)
1+n, 2
4, 2
4, 2
–
5, 3
5, 3
5, 3
RRAX.A
1+n, 2
6, 2
6, 2
–
7, 3
7, 3
7, 3
RRCX(.B)
1+n, 2
4, 2
4, 2
–
5, 3
5, 3
5, 3
RRCX.A
1+n, 2
6, 2
6, 2
–
7, 3
7, 3
7, 3
CALLA
CPUX
(1)
PUSHX(.B)
4, 2
4, 2
4, 2
4, 3
5 ,3
5, 3
5, 3
PUSHX.A
5, 2
6, 2
6, 2
5, 3
7 (1), 3
7, 3
7, 3
POPX(.B)
3, 2
–
–
–
5, 3
5, 3
5, 3
POPX.A
4, 2
–
–
–
7, 3
7, 3
7, 3
(1)
172
Execution Cycles, Length of Instruction (Words)
Rn
Add one cycle when Rn = SP
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4.5.2.7.2 MSP430X Format I (Double-Operand) Instruction Cycles and Lengths
Table 4-18 lists the length and CPU cycles for all addressing modes of the MSP430X extended Format I
instructions.
Table 4-18. MSP430X Format I Instruction Cycles and Length
Addressing Mode
Source
Destination
Rn
Rm (1)
PC
x(Rm)
@Rn
4
2
ADDX R9,PC
7 (3)
3
ANDX.A R5,4(R6)
(2)
(3)
BITX.W R5,&EDE
Rm
3
4
2
BITX @R5,R8
PC
5
6
2
ADDX @R9,PC
9
(3)
3
ANDX.A @R5,4(R6)
9
(3)
3
XORX @R8,EDE
9
(3)
3
BITX.B @R5,&EDE
6
(2)
6
(2)
6
(2)
7
Rm
3
4
2
BITX @R5+,R8
PC
5
6
2
ADDX.A @R9+,PC
(3)
(2)
x(Rm)
6
3
ANDX @R5+,4(R6)
EDE
6 (2)
9 (3)
3
XORX.B @R8+,EDE
(2)
(3)
6
3
(4)
&EDE
Rm
PC
9
3
BITX @R5+,&EDE
3
3
BITX #20,R8
9
4
4
3
ADDX.A #FE000h,PC
6 (2)
8 (3)
4
ANDX #1234,4(R6)
6
(2)
8
(3)
4
XORX #A5A5h,EDE
6
(2)
8
(3)
4
BITX.B #12,&EDE
5
3
BITX 2(R5),R8
4
(4)
TONI
6
7
3
SUBX.A 2(R6),PC
7 (2)
10 (3)
4
ANDX 4(R7),4(R6)
(2)
(3)
x(Rm)
7
4
XORX.B 2(R6),EDE
&TONI
7 (2)
10 (3)
4
BITX 8(SP),&EDE
Rm
4
5
3
BITX.B EDE,R8
PC (4)
6
7
3
ADDX.A EDE,PC
10
(3)
4
ANDX EDE,4(R6)
10
(3)
4
ANDX EDE,TONI
10
(3)
4
BITX EDE,&TONI
TONI
x(Rm)
&TONI
7
(2)
7
(2)
7
(2)
10
Rm
4
5
3
BITX &EDE,R8
PC (4)
6
7
3
ADDX.A &EDE,PC
(3)
(2)
TONI
7
4
ANDX.B &EDE,4(R6)
x(Rm)
7 (2)
10 (3)
4
XORX &EDE,TONI
(2)
(3)
4
BITX &EDE,&TONI
&TONI
(4)
4
5 (2)
XORX R8,EDE
EDE
(3)
BITX.B R5,R8
3
x(Rm)
(2)
2
3
PC
(1)
2
7 (3)
Rm
&EDE
2
5 (2)
&EDE
EDE
.B/.W/.A
5
&EDE
x(Rn)
.A
&EDE
EDE
#N
Examples
.B/.W
EDE
x(Rm)
@Rn+
Length of
Instruction
No. of Cycles
7
10
10
Repeat instructions require n + 1 cycles, where n is the number of times the instruction is executed.
Reduce the cycle count by one for MOV, BIT, and CMP instructions.
Reduce the cycle count by two for MOV, BIT, and CMP instructions.
Reduce the cycle count by one for MOV, ADD, and SUB instructions.
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4.5.2.7.3 MSP430X Address Instruction Cycles and Lengths
Table 4-19 lists the length and the CPU cycles for all addressing modes of the MSP430X address
instructions.
Table 4-19. Address Instruction Cycles and Length
Addressing Mode
x(Rn)
EDE
&EDE
174
MOVA
CMPA
ADDA
SUBA
Rn
1
1
1
1
CMPA R5,R8
PC
3
3
1
1
SUBA R9,PC
x(Rm)
4
–
2
–
MOVA R5,4(R6)
EDE
4
–
2
–
MOVA R8,EDE
&EDE
4
–
2
–
MOVA R5,&EDE
Rm
3
–
1
–
MOVA @R5,R8
PC
5
–
1
–
MOVA @R9,PC
Rm
3
–
1
–
MOVA @R5+,R8
PC
5
–
1
–
MOVA @R9+,PC
Rm
2
3
2
2
CMPA #20,R8
PC
3
3
2
2
SUBA #FE000h,PC
Rm
4
–
2
–
MOVA 2(R5),R8
PC
6
–
2
–
MOVA 2(R6),PC
Rm
4
–
2
–
MOVA EDE,R8
PC
6
–
2
–
MOVA EDE,PC
Rm
4
–
2
–
MOVA &EDE,R8
PC
6
–
2
–
MOVA &EDE,PC
Rn
#N
CPUX
Example
CMPA
ADDA
SUBA
Destination
@Rn+
Length of Instruction
(Words)
MOVA
BRA
Source
@Rn
Execution Time
(MCLK Cycles)
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4.6
Instruction Set Description
Table 4-20 shows all available instructions:
Table 4-20. Instruction Map of MSP430X
000
040
080
RRC
RRC.
B
SWP
B
0xxx
10xx
14xx
18xx
1Cxx
20xx
24xx
28xx
2Cxx
30xx
34xx
38xx
3Cxx
4xxx
5xxx
6xxx
7xxx
8xxx
9xxx
Axxx
Bxxx
Cxxx
Dxxx
Exxx
Fxxx
0C0
100
140
180
1C0
200
240
280
2C0
MOVA, CMPA, ADDA, SUBA, RRCM, RRAM, RLAM, RRUM
RRA.
PUS PUS
RRA
SXT
CALL
B
H
H.B
PUSHM.A, POPM.A, PUSHM.W, POPM.W
300
340
RETI
CALL
A
380
3C0
Extension word for Format I and Format II instructions
JNE, JNZ
JEQ, JZ
JNC
JC
JN
JGE
JL
JMP
MOV, MOV.B
ADD, ADD.B
ADDC, ADDC.B
SUBC, SUBC.B
SUB, SUB.B
CMP, CMP.B
DADD, DADD.B
BIT, BIT.B
BIC, BIC.B
BIS, BIS.B
XOR, XOR.B
AND, AND.B
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4.6.1 Extended Instruction Binary Descriptions
Detailed MSP430X instruction binary descriptions are shown in the following tables.
Instruction
Group
Instruction
15
MOVA
Instruction
Identifier
src or data.19:16
12
11
8
7
dst
4
3
0
src
0
0
0
0
dst
MOVA @Rsrc,Rdst
0
src
0
0
0
1
dst
MOVA @Rsrc+,Rdst
0
&abs.19:16
0
0
1
0
dst
MOVA &abs20,Rdst
0
0
src
0
1
1
dst
MOVA x(Rsrc),Rdst
0
0
src
1
1
0
&abs.19:16
1
1
1
dst
0
0
0
0
0
0
0
0
0
0
0
0
0
0
&abs.15:0
0
x.15:0
±15-bit index x
0
MOVA Rsrc,&abs20
&abs.15:0
0
0
0
0
src
0
MOVA Rsrc,X(Rdst)
x.15:0
0
0
0
0
imm.19:16
±15-bit index x
1
0
0
0
dst
MOVA #imm20,Rdst
0
0
1
dst
CMPA #imm20,Rdst
0
1
0
dst
ADDA #imm20,Rdst
0
1
1
dst
SUBA #imm20,Rdst
imm.15:0
CMPA
0
0
0
0
imm.19:16
ADDA
0
0
0
0
imm.19:16
SUBA
0
0
0
0
imm.19:16
MOVA
0
0
0
0
src
1
1
0
0
dst
MOVA Rsrc,Rdst
CMPA
0
0
0
0
src
1
1
0
1
dst
CMPA Rsrc,Rdst
ADDA
0
0
0
0
src
1
1
1
0
dst
ADDA Rsrc,Rdst
SUBA
0
0
0
0
src
1
1
1
1
dst
SUBA Rsrc,Rdst
1
imm.15:0
1
imm.15:0
1
imm.15:0
Instruction
Group
Instruction
15
Instruction
Identifier
Bit Loc. Inst. ID
12
11
10
9
8
7
dst
4
3
0
RRCM.A
0
0
0
0
n–1
0
0
0
1
0
0
dst
RRCM.A #n,Rdst
RRAM.A
0
0
0
0
n–1
0
1
0
1
0
0
dst
RRAM.A #n,Rdst
RLAM.A
0
0
0
0
n–1
1
0
0
1
0
0
dst
RLAM.A #n,Rdst
RRUM.A
0
0
0
0
n–1
1
1
0
1
0
0
dst
RRUM.A #n,Rdst
RRCM.W
0
0
0
0
n–1
0
0
0
1
0
1
dst
RRCM.W #n,Rdst
RRAM.W
0
0
0
0
n–1
0
1
0
1
0
1
dst
RRAM.W #n,Rdst
RLAM.W
0
0
0
0
n–1
1
0
0
1
0
1
dst
RLAM.W #n,Rdst
RRUM.W
0
0
0
0
n–1
1
1
0
1
0
1
dst
RRUM.W #n,Rdst
176 CPUX
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Instruction
Instruction Identifier
15
dst
12
11
8
7
6
5
4
3
RETI
0
0
0
1
0
0
1
1
0
0
0
0
0
0
CALLA
0
0
0
1
0
0
1
1
0
1
0
0
dst
CALLA Rdst
0
0
0
1
0
0
1
1
0
1
0
1
dst
CALLA x(Rdst)
0
0
0
x.15:0
0
0
0
1
0
0
1
1
0
1
1
0
dst
CALLA @Rdst
0
0
0
1
0
0
1
1
0
1
1
1
dst
CALLA @Rdst+
0
0
0
1
0
0
1
1
1
0
0
0
&abs.19:16
CALLA &abs20
0
0
1
x.19:16
&abs.15:0
0
0
0
1
0
0
1
1
1
CALLA EDE
CALLA x(PC)
x.15:0
0
0
0
1
0
0
1
1
1
0
1
1
CALLA #imm20
imm.19:16
imm.15:0
Reserved
0
0
0
1
0
0
1
1
1
0
1
0
x
x
x
x
Reserved
0
0
0
1
0
0
1
1
1
1
x
x
x
x
x
x
PUSHM.A
0
0
0
1
0
1
0
0
n–1
PUSHM.W
0
0
0
1
0
1
0
1
POPM.A
0
0
0
1
0
1
1
0
POPM.W
0
0
0
1
0
1
1
1
dst
PUSHM.A #n,Rdst
n–1
dst
PUSHM.W #n,Rdst
n–1
dst – n + 1
POPM.A #n,Rdst
n–1
dst – n + 1
POPM.W #n,Rdst
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4.6.2 MSP430 Instructions
The MSP430 instructions are listed and described on the following pages.
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4.6.2.1
ADC
* ADC[.W]
* ADC.B
Syntax
Add carry to destination
Add carry to destination
ADC dst or
ADC.W dst
ADC.B dst
Operation
Emulation
dst + C → dst
ADDC #0,dst
ADDC.B #0,dst
Description
Status Bits
Mode Bits
Example
ADD
ADC
Example
ADD.B
ADC.B
The carry bit (C) is added to the destination operand. The previous contents of the
destination are lost.
N: Set if result is negative, reset if positive
Z: Set if result is zero, reset otherwise
C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise
Set if dst was incremented from 0FFh to 00, reset otherwise
V: Set if an arithmetic overflow occurs, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12.
@R13,0(R12)
2(R12)
; Add LSDs
; Add carry to MSD
The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12.
@R13,0(R12)
1(R12)
; Add LSDs
; Add carry to MSD
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ADD
ADD[.W]
ADD.B
Syntax
Add source word to destination word
Add source byte to destination byte
ADD src,dst or ADD.W src,dst
ADD.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
ADD.W
Example
ADD.W
JC
...
Example
ADD.B
JNC
...
180
CPUX
src + dst → dst
The source operand is added to the destination operand. The previous content of the
destination is lost.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
V: Set if the result of two positive operands is negative, or if the result of two negative
numbers is positive, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
Ten is added to the 16-bit counter CNTR located in lower 64 K.
#10,&CNTR
; Add 10 to 16-bit counter
A table word pointed to by R5 (20-bit address in R5) is added to R6. The jump to label
TONI is performed on a carry.
@R5,R6
TONI
; Add table word to R6. R6.19:16 = 0
; Jump if carry
; No carry
A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is
performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0
@R5+,R6
TONI
; Add byte to R6. R5 + 1. R6: 000xxh
; Jump if no carry
; Carry occurred
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4.6.2.3
ADDC
ADDC[.W]
ADDC.B
Syntax
Add source word and carry to destination word
Add source byte and carry to destination byte
ADDC src,dst or ADDC.W src,dst
ADDC.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
ADDC.W
Example
ADDC.W
JC
...
Example
ADDC.B
JNC
...
src + dst + C → dst
The source operand and the carry bit C are added to the destination operand. The
previous content of the destination is lost.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
V: Set if the result of two positive operands is negative, or if the result of two negative
numbers is positive, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
Constant value 15 and the carry of the previous instruction are added to the 16-bit
counter CNTR located in lower 64 K.
#15,&CNTR
; Add 15 + C to 16-bit CNTR
A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The
jump to label TONI is performed on a carry. R6.19:16 = 0
@R5,R6
TONI
; Add table word + C to R6
; Jump if carry
; No carry
A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The
jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented
by 1. R6.19:8 = 0
@R5+,R6
TONI
; Add table byte + C to R6. R5 + 1
; Jump if no carry
; Carry occurred
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AND
AND[.W]
AND.B
Syntax
Logical AND of source word with destination word
Logical AND of source byte with destination byte
AND src,dst or AND.W src,dst
AND.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
MOV
AND
JZ
...
src .and. dst → dst
The source operand and the destination operand are logically ANDed. The result is
placed into the destination. The source operand is not affected.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if the result is not zero, reset otherwise. C = (.not. Z)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The bits set in R5 (16-bit data) are used as a mask (AA55h) for the word TOM located in
the lower 64 K. If the result is zero, a branch is taken to label TONI. R5.19:16 = 0
#AA55h,R5
R5,&TOM
TONI
;
;
;
;
Load 16-bit mask to R5
TOM .and. R5 -> TOM
Jump if result 0
Result > 0
or shorter:
AND
JZ
Example
AND.B
182
CPUX
#AA55h,&TOM
TONI
; TOM .and. AA55h -> TOM
; Jump if result 0
A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R5 is
incremented by 1 after the fetching of the byte. R6.19:8 = 0
@R5+,R6
; AND table byte with R6. R5 + 1
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4.6.2.5
BIC
BIC[.W]
BIC.B
Syntax
Clear bits set in source word in destination word
Clear bits set in source byte in destination byte
BIC src,dst or BIC.W src,dst
BIC.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
BIC
Example
BIC.W
Example
BIC.B
(.not. src) .and. dst → dst
The inverted source operand and the destination operand are logically ANDed. The
result is placed into the destination. The source operand is not affected.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
The bits 15:14 of R5 (16-bit data) are cleared. R5.19:16 = 0
#0C000h,R5
; Clear R5.19:14 bits
A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0
@R5,R7
; Clear bits in R7 set in @R5
A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1.
@R5,&P1OUT
; Clear I/O port P1 bits set in @R5
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BIS
BIS[.W]
BIS.B
Syntax
Set bits set in source word in destination word
Set bits set in source byte in destination byte
BIS src,dst or BIS.W src,dst
BIS.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
BIS
Example
BIS.W
Example
BIS.B
184
CPUX
src .or. dst → dst
The source operand and the destination operand are logically ORed. The result is placed
into the destination. The source operand is not affected.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Bits 15 and 13 of R5 (16-bit data) are set to one. R5.19:16 = 0
#A000h,R5
; Set R5 bits
A table word pointed to by R5 (20-bit address) is used to set bits in R7. R7.19:16 = 0
@R5,R7
; Set bits in R7
A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is
incremented by 1 afterwards.
@R5+,&P1OUT
; Set I/O port P1 bits. R5 + 1
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4.6.2.7
BIT
BIT[.W]
BIT.B
Syntax
Test bits set in source word in destination word
Test bits set in source byte in destination byte
BIT src,dst or BIT.W src,dst
BIT.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
BIT
JNZ
...
Example
BIT.W
JC
...
Example
BIT.B
JNC
...
src .and. dst
The source operand and the destination operand are logically ANDed. The result affects
only the status bits in SR.
Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared!
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if the result is not zero, reset otherwise. C = (.not. Z)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
Test if one (or both) of bits 15 and 14 of R5 (16-bit data) is set. Jump to label TONI if this
is the case. R5.19:16 are not affected.
#C000h,R5
TONI
; Test R5.15:14 bits
; At least one bit is set in R5
; Both bits are reset
A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label
TONI if at least one bit is set. R7.19:16 are not affected.
@R5,R7
TONI
; Test bits in R7
; At least one bit is set
; Both are reset
A table byte pointed to by R5 (20-bit address) is used to test bits in output Port1. Jump
to label TONI if no bit is set. The next table byte is addressed.
@R5+,&P1OUT
TONI
; Test I/O port P1 bits. R5 + 1
; No corresponding bit is set
; At least one bit is set
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4.6.2.8
BR, BRANCH
* BR,
BRANCH
Syntax
Operation
Emulation
Description
Status Bits
Example
186
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CPUX
Branch to destination in lower 64K address space
BR dst
dst → PC
MOV dst,PC
An unconditional branch is taken to an address anywhere in the lower 64K address
space. All source addressing modes can be used. The branch instruction is a word
instruction.
Status bits are not affected.
Examples for all addressing modes are given.
BR
#EXEC
; Branch to label EXEC or direct branch (for example #0A4h)
; Core instruction MOV @PC+,PC
BR
EXEC
; Branch to the address contained in EXEC
; Core instruction MOV X(PC),PC
; Indirect address
BR
&EXEC
;
;
;
;
BR
R5
; Branch to the address contained in R5
; Core instruction MOV R5,PC
; Indirect R5
BR
@R5
;
;
;
;
Branch to the address contained in the word
pointed to by R5.
Core instruction MOV @R5,PC
Indirect, indirect R5
BR
@R5+
;
;
;
;
;
;
;
Branch to the address contained in the word pointed
to by R5 and increment pointer in R5 afterwards.
The next time-S/W flow uses R5 pointer-it can
alter program execution due to access to
next address in a table pointed to by R5
Core instruction MOV @R5,PC
Indirect, indirect R5 with autoincrement
BR
X(R5)
;
;
;
;
;
Branch to the address contained in the address
pointed to by R5 + X (for example table with address
starting at X). X can be an address or a label
Core instruction MOV X(R5),PC
Indirect, indirect R5 + X
Branch to the address contained in absolute
address EXEC
Core instruction MOV X(0),PC
Indirect address
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4.6.2.9
CALL
CALL
Syntax
Operation
Description
Status Bits
Mode Bits
Examples
CALL
CALL
Call a subroutine in lower 64 K
CALL dst
dst → tmp 16-bit dst is evaluated and stored
SP – 2 → SP
PC → @SP updated PC with return address to TOS
tmp → PC saved 16-bit dst to PC
A subroutine call is made from an address in the lower 64 K to a subroutine address in
the lower 64 K. All seven source addressing modes can be used. The call instruction is a
word instruction. The return is made with the RET instruction.
Status bits are not affected.
PC.19:16 cleared (address in lower 64 K)
OSCOFF, CPUOFF, and GIE are not affected.
Examples for all addressing modes are given.
Immediate Mode: Call a subroutine at label EXEC (lower 64 K) or call directly to address.
#EXEC
#0AA04h
; Start address EXEC
; Start address 0AA04h
Symbolic Mode: Call a subroutine at the 16-bit address contained in address EXEC.
EXEC is located at the address (PC + X) where X is within PC ± 32 K.
CALL
EXEC
; Start address at @EXEC. z16(PC)
Absolute Mode: Call a subroutine at the 16-bit address contained in absolute address
EXEC in the lower 64 K.
CALL
&EXEC
; Start address at @EXEC
Register mode: Call a subroutine at the 16-bit address contained in register R5.15:0.
CALL
R5
; Start address at R5
Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by
register R5 (20-bit address).
CALL
@R5
; Start address at @R5
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4.6.2.10 CLR
* CLR[.W]
* CLR.B
Syntax
Clear destination
Clear destination
CLR dst or
CLR.W dst
CLR.B dst
Operation
0 → dst
Emulation
MOV #0,dst
MOV.B #0,dst
Description
Status Bits
Example
CLR
Example
CLR
Example
CLR.B
188
CPUX
The destination operand is cleared.
Status bits are not affected.
RAM word TONI is cleared.
TONI
; 0 -> TONI
Register R5 is cleared.
R5
RAM byte TONI is cleared.
TONI
; 0 -> TONI
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4.6.2.11 CLRC
* CLRC
Syntax
Operation
Clear carry bit
Emulation
Description
Status Bits
BIC #1,SR
Mode Bits
Example
CLRC
DADD
DADC
CLRC
0→C
The carry bit (C) is cleared. The clear carry instruction is a word instruction.
N: Not affected
Z: Not affected
C: Cleared
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by
R12.
; C=0: defines start
; add 16-bit counter to low word of 32-bit counter
; add carry to high word of 32-bit counter
@R13,0(R12)
2(R12)
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4.6.2.12 CLRN
* CLRN
Syntax
Operation
Clear negative bit
Emulation
Description
BIC #4,SR
Status Bits
Mode Bits
Example
SUBR
SUBRET
190
CPUX
CLRN
0→N
or
(.NOT.src .AND. dst → dst)
The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination
operand. The result is placed into the destination. The clear negative bit instruction is a
word instruction.
N: Reset to 0
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
The negative bit in the SR is cleared. This avoids special treatment with negative
numbers of the subroutine called.
CLRN
CALL
SUBR
......
......
JN
SUBRET
......
......
......
RET
; If input is negative: do nothing and return
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4.6.2.13 CLRZ
* CLRZ
Syntax
Operation
Clear zero bit
Emulation
Description
BIC #2,SR
Status Bits
Mode Bits
Example
CLRZ
0→Z
or
(.NOT.src .AND. dst → dst)
The constant 02h is inverted (0FFFDh) and logically ANDed with the destination
operand. The result is placed into the destination. The clear zero bit instruction is a word
instruction.
N: Not affected
Z: Reset to 0
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
The zero bit in the SR is cleared.
CLRZ
Indirect, Auto-Increment mode: Call a subroutine at the 16-bit address contained in the
word pointed to by register R5 (20-bit address) and increment the 16-bit address in R5
afterwards by 2. The next time the software uses R5 as a pointer, it can alter the
program execution due to access to the next word address in the table pointed to by R5.
CALL
@R5+
; Start address at @R5. R5 + 2
Indexed mode: Call a subroutine at the 16-bit address contained in the 20-bit address
pointed to by register (R5 + X); for example, a table with addresses starting at X. The
address is within the lower 64 KB. X is within ±32 KB.
CALL
X(R5)
; Start address at @(R5+X). z16(R5)
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4.6.2.14 CMP
CMP[.W]
CMP.B
Syntax
Compare source word and destination word
Compare source byte and destination byte
CMP src,dst or CMP.W src,dst
CMP.B src,dst
Operation
(.not.src) + 1 + dst
or
dst – src
Emulation
Description
BIC #2,SR
Status Bits
Mode Bits
Example
CMP
JEQ
...
Example
CMP.W
JL
...
Example
CMP.B
JEQ
...
192
CPUX
The source operand is subtracted from the destination operand. This is made by adding
the 1s complement of the source + 1 to the destination. The result affects only the status
bits in SR.
Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared.
N: Set if result is negative (src > dst), reset if positive (src = dst)
Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source operand
from a negative destination operand delivers a positive result, reset otherwise (no
overflow).
OSCOFF, CPUOFF, and GIE are not affected.
Compare word EDE with a 16-bit constant 1800h. Jump to label TONI if EDE equals the
constant. The address of EDE is within PC + 32 K.
#01800h,EDE
TONI
; Compare word EDE with 1800h
; EDE contains 1800h
; Not equal
A table word pointed to by (R5 + 10) is compared with R7. Jump to label TONI if R7
contains a lower, signed 16-bit number. R7.19:16 is not cleared. The address of the
source operand is a 20-bit address in full memory range.
10(R5),R7
TONI
; Compare two signed numbers
; R7 < 10(R5)
; R7 >= 10(R5)
A table byte pointed to by R5 (20-bit address) is compared to the value in output Port1.
Jump to label TONI if values are equal. The next table byte is addressed.
@R5+,&P1OUT
TONI
; Compare P1 bits with table. R5 + 1
; Equal contents
; Not equal
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4.6.2.15 DADC
* DADC[.W]
* DADC.B
Syntax
Add carry decimally to destination
Add carry decimally to destination
DADC dst or
DADC.W dst
DADC.B dst
Operation
Emulation
dst + C → dst (decimally)
DADD #0,dst
DADD.B #0,dst
Description
Status Bits
Mode Bits
Example
The
N:
Z:
C:
carry bit (C) is added decimally to the destination.
Set if MSB is 1
Set if dst is 0, reset otherwise
Set if destination increments from 9999 to 0000, reset otherwise
Set if destination increments from 99 to 00, reset otherwise
V: Undefined
OSCOFF, CPUOFF, and GIE are not affected.
The four-digit decimal number contained in R5 is added to an eight-digit decimal number
pointed to by R8.
CLRC
DADD
DADC
Example
;
;
;
;
R5,0(R8)
2(R8)
The two-digit decimal number contained in R5 is added to a four-digit decimal number
pointed to by R8.
CLRC
DADD.B
DADC
Reset carry
next instruction's start condition is defined
Add LSDs + C
Add carry to MSD
;
;
;
;
R5,0(R8)
1(R8)
Reset carry
next instruction's start condition is defined
Add LSDs + C
Add carry to MSDs
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4.6.2.16 DADD
* DADD[.W]
* DADD.B
Syntax
Add source word and carry decimally to destination word
Add source byte and carry decimally to destination byte
DADD src,dst or DADD.W src,dst
DADD.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
DADD
Example
CLRC
DADD.W
DADD.W
JC
...
Example
CLRC
DADD.B
194
CPUX
src + dst + C → dst (decimally)
The source operand and the destination operand are treated as two (.B) or four (.W)
binary coded decimals (BCD) with positive signs. The source operand and the carry bit C
are added decimally to the destination operand. The source operand is not affected. The
previous content of the destination is lost. The result is not defined for non-BCD
numbers.
N: Set if MSB of result is 1 (word > 7999h, byte > 79h), reset if MSB is 0
Z: Set if result is zero, reset otherwise
C: Set if the BCD result is too large (word > 9999h, byte > 99h), reset otherwise
V: Undefined
OSCOFF, CPUOFF, and GIE are not affected.
Decimal 10 is added to the 16-bit BCD counter DECCNTR.
#10h,&DECCNTR
; Add 10 to 4-digit BCD counter
The eight-digit BCD number contained in 16-bit RAM addresses BCD and BCD+2 is
added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5
contain the MSDs). The carry C is added, and cleared.
&BCD,R4
&BCD+2,R5
OVERFLOW
;
;
;
;
;
Clear carry
Add LSDs. R4.19:16 = 0
Add MSDs with carry. R5.19:16 = 0
Result >9999,9999: go to error routine
Result ok
The two-digit BCD number contained in word BCD (16-bit address) is added decimally to
a two-digit BCD number contained in R4. The carry C is added, also. R4.19:8 = 0
&BCD,R4
; Clear carry
; Add BCD to R4 decimally.
R4: 0,00ddh
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4.6.2.17 DEC
* DEC[.W]
* DEC.B
Syntax
Decrement destination
Decrement destination
DEC dst or
DEC.W dst
DEC.B dst
Operation
Emulation
dst – 1 → dst
SUB #1,dst
SUB.B #1,dst
Description
Status Bits
Mode Bits
Example
The
N:
Z:
C:
V:
destination operand is decremented by one. The original contents are lost.
Set if result is negative, reset if positive
Set if dst contained 1, reset otherwise
Reset if dst contained 0, set otherwise
Set if an arithmetic overflow occurs, otherwise reset.
Set if initial value of destination was 08000h, otherwise reset.
Set if initial value of destination was 080h, otherwise reset.
OSCOFF, CPUOFF, and GIE are not affected.
R10 is decremented by 1.
DEC
R10
; Decrement R10
; Move a block of 255 bytes from memory location starting with EDE to
; memory location starting with TONI. Tables should not overlap: start of
; destination address TONI must not be within the range EDE to EDE+0FEh
L$1
MOV
MOV
MOV.B
DEC
JNZ
#EDE,R6
#255,R10
@R6+,TONI-EDE-1(R6)
R10
L$1
Do not transfer tables using the routine above with the overlap shown in Figure 4-36.
EDE
TONI
EDE+254
TONI+254
Figure 4-36. Decrement Overlap
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4.6.2.18 DECD
* DECD[.W]
* DECD.B
Syntax
Double-decrement destination
Double-decrement destination
DECD dst or
DECD.W dst
DECD.B dst
Operation
Emulation
dst – 2 → dst
SUB #2,dst
SUB.B #2,dst
Description
Status Bits
Mode Bits
Example
The
N:
Z:
C:
V:
destination operand is decremented by two. The original contents are lost.
Set if result is negative, reset if positive
Set if dst contained 2, reset otherwise
Reset if dst contained 0 or 1, set otherwise
Set if an arithmetic overflow occurs, otherwise reset
Set if initial value of destination was 08001 or 08000h, otherwise reset
Set if initial value of destination was 081 or 080h, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
R10 is decremented by 2.
DECD
;
;
;
;
R10
; Decrement R10 by two
Move a block of 255 bytes from memory location starting with EDE to
memory location starting with TONI.
Tables should not overlap: start of destination address TONI must not
be within the range EDE to EDE+0FEh
L$1
Example
MOV
MOV
MOV.B
DECD
JNZ
#EDE,R6
#255,R10
@R6+,TONI-EDE-2(R6)
R10
L$1
Memory at location LEO is decremented by two.
DECD.B
LEO
; Decrement MEM(LEO)
Decrement status byte STATUS by two
DECD.B
196
CPUX
STATUS
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4.6.2.19 DINT
* DINT
Syntax
Operation
Disable (general) interrupts
Emulation
Description
BIC #8,SR
DINT
0 → GIE
or
(0FFF7h .AND. SR → SR / .NOT.src .AND. dst → dst)
Status Bits
Mode Bits
Example
DINT
NOP
MOV
MOV
EINT
All interrupts are disabled.
The constant 08h is inverted and logically ANDed with the SR. The result is placed into
the SR.
Status bits are not affected.
GIE is reset. OSCOFF and CPUOFF are not affected.
The general interrupt enable (GIE) bit in the SR is cleared to allow a nondisrupted move
of a 32-bit counter. This ensures that the counter is not modified during the move by any
interrupt.
; All interrupt events using the GIE bit are disabled
COUNTHI,R5
COUNTLO,R6
; Copy counter
; All interrupt events using the GIE bit are enabled
NOTE: Disable interrupt
If any code sequence needs to be protected from interruption, DINT should be executed at
least one instruction before the beginning of the uninterruptible sequence, or it should be
followed by a NOP instruction.
NOTE: Enable and Disable Interrupt
Due to the pipelined CPU architecture, the instruction following the enable interrupt
instruction (EINT) is always executed, even if an interrupt service request is pending when
the interrupts are enabled.
If the enable interrupt instruction (EINT) is immediately followed by a disable interrupt
instruction (DINT), a pending interrupt might not be serviced. Further instructions after DINT
might execute incorrectly and result in unexpected CPU execution. It is recommended to
always insert at least one instruction between EINT and DINT. Note that any alternative
instruction use that sets and immediately clears the CPU status register GIE bit must be
considered in the same fashion.
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4.6.2.20 EINT
* EINT
Syntax
Operation
Enable (general) interrupts
Emulation
Description
BIS #8,SR
EINT
1 → GIE
or
(0008h .OR. SR → SR / .src .OR. dst → dst)
Status Bits
Mode Bits
Example
All interrupts are enabled.
The constant #08h and the SR are logically ORed. The result is placed into the SR.
Status bits are not affected.
GIE is set. OSCOFF and CPUOFF are not affected.
The general interrupt enable (GIE) bit in the SR is set.
PUSH.B
BIC.B
EINT
MaskOK
&P1IN
@SP,&P1IFG
BIT
#Mask,@SP
JEQ
MaskOK
......
BIC
#Mask,@SP
......
INCD
SP
; Reset only accepted flags
; Preset port 1 interrupt flags stored on stack
; other interrupts are allowed
; Flags are present identically to mask: jump
; Housekeeping: inverse to PUSH instruction
; at the start of interrupt subroutine. Corrects
; the stack pointer.
RETI
NOTE: Enable and Disable Interrupt
Due to the pipelined CPU architecture, the instruction following the enable interrupt
instruction (EINT) is always executed, even if an interrupt service request is pending when
the interrupts are enabled.
If the enable interrupt instruction (EINT) is immediately followed by a disable interrupt
instruction (DINT), a pending interrupt might not be serviced. Further instructions after DINT
might execute incorrectly and result in unexpected CPU execution. It is recommended to
always insert at least one instruction between EINT and DINT. Note that any alternative
instruction use that sets and immediately clears the CPU status register GIE bit must be
considered in the same fashion.
198
CPUX
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4.6.2.21 INC
* INC[.W]
* INC.B
Syntax
Increment destination
Increment destination
INC dst or
INC.W dst
INC.B dst
Operation
Emulation
Description
Status Bits
Mode Bits
Example
INC.B
CMP.B
JEQ
dst + 1 → dst
ADD #1,dst
The destination operand is incremented by one. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 0FFFFh, reset otherwise
Set if dst contained 0FFh, reset otherwise
C: Set if dst contained 0FFFFh, reset otherwise
Set if dst contained 0FFh, reset otherwise
V: Set if dst contained 07FFFh, reset otherwise
Set if dst contained 07Fh, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch
to OVFL is taken.
STATUS
#11,STATUS
OVFL
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4.6.2.22 INCD
* INCD[.W]
* INCD.B
Syntax
Double-increment destination
Double-increment destination
INCD dst or
INCD.W dst
INCD.B dst
Operation
Emulation
Description
Status Bits
Mode Bits
Example
dst + 2 → dst
ADD #2,dst
The destination operand is incremented by two. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 0FFFEh, reset otherwise
Set if dst contained 0FEh, reset otherwise
C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise
Set if dst contained 0FEh or 0FFh, reset otherwise
V: Set if dst contained 07FFEh or 07FFFh, reset otherwise
Set if dst contained 07Eh or 07Fh, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The item on the top of the stack (TOS) is removed without using a register.
.......
PUSH
R5
INCD
SP
;
;
;
;
R5 is the result of a calculation, which is stored
in the system stack
Remove TOS by double-increment from stack
Do not use INCD.B, SP is a word-aligned register
RET
Example
INCD.B
200
CPUX
The byte on the top of the stack is incremented by two.
0(SP)
; Byte on TOS is increment by two
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4.6.2.23 INV
* INV[.W]
* INV.B
Syntax
Invert destination
Invert destination
INV dst or
INV.W dst
INV.B dst
Operation
Emulation
.not.dst → dst
XOR #0FFFFh,dst
XOR.B #0FFh,dst
Description
Status Bits
Mode Bits
Example
MOV
INV
INC
Example
MOV.B
INV.B
INC.B
The destination operand is inverted. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 0FFFFh, reset otherwise
Set if dst contained 0FFh, reset otherwise
C: Set if result is not zero, reset otherwise ( = .NOT. Zero)
V: Set if initial destination operand was negative, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
Content of R5 is negated (2s complement).
#00AEh,R5
R5
R5
;
; Invert R5,
; R5 is now negated,
R5 = 000AEh
R5 = 0FF51h
R5 = 0FF52h
Content of memory byte LEO is negated.
#0AEh,LEO
LEO
LEO
;
MEM(LEO) = 0AEh
; Invert LEO,
MEM(LEO) = 051h
; MEM(LEO) is negated, MEM(LEO) = 052h
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4.6.2.24 JC, JHS
JC
JHS
Syntax
Jump if carry
Jump if higher or same (unsigned)
JC label
JHS label
Operation
If C = 1: PC + (2 × Offset) → PC
If C = 0: execute the following instruction
Description
The carry bit C in the SR is tested. If it is set, the signed 10-bit word offset contained in
the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This
means a jump in the range –511 to +512 words relative to the PC in the full memory
range. If C is reset, the instruction after the jump is executed.
JC is used for the test of the carry bit C.
JHS is used for the comparison of unsigned numbers.
Status bits are not affected
OSCOFF, CPUOFF, and GIE are not affected.
The state of the port 1 pin P1IN.1 bit defines the program flow.
Status Bits
Mode Bits
Example
BIT.B
JC
...
Example
CMP
JHS
...
Example
CMPA
JHS
...
202
CPUX
#2,&P1IN
Label1
; Port 1, bit 1 set? Bit -> C
; Yes, proceed at Label1
; No, continue
If R5 ≥ R6 (unsigned), the program continues at Label2.
R6,R 5
Label2
; Is R5 >= R6? Info to C
; Yes, C = 1
; No, R5 < R6. Continue
If R5 ≥ 12345h (unsigned operands), the program continues at Label2.
#12345h,R5
Label2
; Is R5 >= 12345h? Info to C
; Yes, 12344h < R5 <= F,FFFFh. C = 1
; No, R5 < 12345h. Continue
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4.6.2.25 JEQ, JZ
JEQ
JZ
Syntax
Jump if equal
Jump if zero
JEQ label
JZ label
Operation
If Z = 1: PC + (2 × Offset) → PC
If Z = 0: execute following instruction
Description
The zero bit Z in the SR is tested. If it is set, the signed 10-bit word offset contained in
the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This
means a jump in the range –511 to +512 words relative to the PC in the full memory
range. If Z is reset, the instruction after the jump is executed.
JZ is used for the test of the zero bit Z.
JEQ is used for the comparison of operands.
Status bits are not affected
OSCOFF, CPUOFF, and GIE are not affected.
The state of the P2IN.0 bit defines the program flow.
Status Bits
Mode Bits
Example
BIT.B
JZ
...
Example
CMPA
JEQ
...
Example
ADDA
JZ
...
#1,&P2IN
Label1
; Port 2, bit 0 reset?
; Yes, proceed at Label1
; No, set, continue
If R5 = 15000h (20-bit data), the program continues at Label2.
#15000h,R5
Label2
; Is R5 = 15000h? Info to SR
; Yes, R5 = 15000h. Z = 1
; No, R5 not equal 15000h. Continue
R7 (20-bit counter) is incremented. If its content is zero, the program continues at
Label4.
#1,R7
Label4
; Increment R7
; Zero reached: Go to Label4
; R7 not equal 0. Continue here.
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4.6.2.26 JGE
JGE
Syntax
Operation
Jump if greater or equal (signed)
Description
The negative bit N and the overflow bit V in the SR are tested. If both bits are set or both
are reset, the signed 10-bit word offset contained in the instruction is multiplied by two,
sign extended, and added to the 20-bit PC. This means a jump in the range -511 to +512
words relative to the PC in full Memory range. If only one bit is set, the instruction after
the jump is executed.
JGE is used for the comparison of signed operands: also for incorrect results due to
overflow, the decision made by the JGE instruction is correct.
Note that JGE emulates the nonimplemented JP (jump if positive) instruction if used after
the instructions AND, BIT, RRA, SXTX, and TST. These instructions clear the V bit.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
If byte EDE (lower 64 K) contains positive data, go to Label1. Software can run in the full
memory range.
Status Bits
Mode Bits
Example
TST.B
JGE
...
Example
CMP
JGE
...
Example
CMPA
JGE
...
204
CPUX
JGE label
If (N .xor. V) = 0: PC + (2 × Offset) → PC
If (N .xor. V) = 1: execute following instruction
&EDE
Label1
; Is EDE positive? V <- 0
; Yes, JGE emulates JP
; No, 80h <= EDE <= FFh
If the content of R6 is greater than or equal to the memory pointed to by R7, the program
continues a Label5. Signed data. Data and program in full memory range.
@R7,R6
Label5
; Is R6 >= @R7?
; Yes, go to Label5
; No, continue here
If R5 ≥ 12345h (signed operands), the program continues at Label2. Program in full
memory range.
#12345h,R5
Label2
; Is R5 >= 12345h?
; Yes, 12344h < R5 <= 7FFFFh
; No, 80000h <= R5 < 12345h
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4.6.2.27 JL
JL
Syntax
Operation
Jump if less (signed)
Description
The negative bit N and the overflow bit V in the SR are tested. If only one is set, the
signed 10-bit word offset contained in the instruction is multiplied by two, sign extended,
and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative
to the PC in full memory range. If both bits N and V are set or both are reset, the
instruction after the jump is executed.
JL is used for the comparison of signed operands: also for incorrect results due to
overflow, the decision made by the JL instruction is correct.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
If byte EDE contains a smaller, signed operand than byte TONI, continue at Label1. The
address EDE is within PC ± 32 K.
Status Bits
Mode Bits
Example
CMP.B
JL
...
Example
CMP
JL
...
Example
CMPA
JL
...
JL label
If (N .xor. V) = 1: PC + (2 × Offset) → PC
If (N .xor. V) = 0: execute following instruction
&TONI,EDE
Label1
; Is EDE < TONI
; Yes
; No, TONI <= EDE
If the signed content of R6 is less than the memory pointed to by R7 (20-bit address), the
program continues at Label5. Data and program in full memory range.
@R7,R6
Label5
; Is R6 < @R7?
; Yes, go to Label5
; No, continue here
If R5 < 12345h (signed operands), the program continues at Label2. Data and program
in full memory range.
#12345h,R5
Label2
; Is R5 < 12345h?
; Yes, 80000h =< R5 < 12345h
; No, 12344h < R5 <= 7FFFFh
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4.6.2.28 JMP
JMP
Syntax
Operation
Description
Status Bits
Mode Bits
Example
MOV.B
JMP
Example
ADD
RETI
JMP
JMP
RETI
206
CPUX
Jump unconditionally
JMP label
PC + (2 × Offset) → PC
The signed 10-bit word offset contained in the instruction is multiplied by two, sign
extended, and added to the 20-bit PC. This means an unconditional jump in the range
–511 to +512 words relative to the PC in the full memory. The JMP instruction may be
used as a BR or BRA instruction within its limited range relative to the PC.
Status bits are not affected
OSCOFF, CPUOFF, and GIE are not affected.
The byte STATUS is set to 10. Then a jump to label MAINLOOP is made. Data in lower
64 K, program in full memory range.
#10,&STATUS
MAINLOOP
; Set STATUS to 10
; Go to main loop
The interrupt vector TAIV of Timer_A3 is read and used for the program flow. Program in
full memory range, but interrupt handlers always starts in lower 64 K.
&TAIV,PC
IHCCR1
IHCCR2
;
;
;
;
;
Add Timer_A interrupt vector to PC
No Timer_A interrupt pending
Timer block 1 caused interrupt
Timer block 2 caused interrupt
No legal interrupt, return
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4.6.2.29 JN
JN
Syntax
Operation
Description
Status Bits
Mode Bits
Example
TST.B
JN
...
Example
SUB
JN
...
Example
SUBA
JN
...
Jump if negative
JN label
If N = 1: PC + (2 × Offset) → PC
If N = 0: execute following instruction
The negative bit N in the SR is tested. If it is set, the signed 10-bit word offset contained
in the instruction is multiplied by two, sign extended, and added to the 20-bit program
PC. This means a jump in the range -511 to +512 words relative to the PC in the full
memory range. If N is reset, the instruction after the jump is executed.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
The byte COUNT is tested. If it is negative, program execution continues at Label0. Data
in lower 64 K, program in full memory range.
&COUNT
Label0
; Is byte COUNT negative?
; Yes, proceed at Label0
; COUNT >= 0
R6 is subtracted from R5. If the result is negative, program continues at Label2. Program
in full memory range.
R6,R5
Label2
; R5 - R6 -> R5
; R5 is negative: R6 > R5 (N = 1)
; R5 >= 0. Continue here.
R7 (20-bit counter) is decremented. If its content is below zero, the program continues at
Label4. Program in full memory range.
#1,R7
Label4
; Decrement R7
; R7 < 0: Go to Label4
; R7 >= 0. Continue here.
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4.6.2.30 JNC, JLO
JNC
JLO
Syntax
Jump if no carry
Jump if lower (unsigned)
JNC label
JLO label
Operation
If C = 0: PC + (2 × Offset) → PC
If C = 1: execute following instruction
Description
The carry bit C in the SR is tested. If it is reset, the signed 10-bit word offset contained in
the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This
means a jump in the range –511 to +512 words relative to the PC in the full memory
range. If C is set, the instruction after the jump is executed.
JNC is used for the test of the carry bit C.
JLO is used for the comparison of unsigned numbers.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
If byte EDE < 15, the program continues at Label2. Unsigned data. Data in lower 64 K,
program in full memory range.
Status Bits
Mode Bits
Example
CMP.B
JLO
...
Example
ADD
JNC
...
208
CPUX
#15,&EDE
Label2
; Is EDE < 15? Info to C
; Yes, EDE < 15. C = 0
; No, EDE >= 15. Continue
The word TONI is added to R5. If no carry occurs, continue at Label0. The address of
TONI is within PC ± 32 K.
TONI,R5
Label0
; TONI + R5 -> R5. Carry -> C
; No carry
; Carry = 1: continue here
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4.6.2.31 JNZ, JNE
JNZ
JNE
Syntax
Jump if not zero
Jump if not equal
JNZ label
JNE label
Operation
If Z = 0: PC + (2 × Offset) → PC
If Z = 1: execute following instruction
Description
The zero bit Z in the SR is tested. If it is reset, the signed 10-bit word offset contained in
the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This
means a jump in the range –511 to +512 words relative to the PC in the full memory
range. If Z is set, the instruction after the jump is executed.
JNZ is used for the test of the zero bit Z.
JNE is used for the comparison of operands.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
The byte STATUS is tested. If it is not zero, the program continues at Label3. The
address of STATUS is within PC ± 32 K.
Status Bits
Mode Bits
Example
TST.B
JNZ
...
Example
CMP
JNE
...
Example
SUBA
JNZ
...
STATUS
Label3
; Is STATUS = 0?
; No, proceed at Label3
; Yes, continue here
If word EDE ≠ 1500, the program continues at Label2. Data in lower 64 K, program in full
memory range.
#1500,&EDE
Label2
; Is EDE = 1500? Info to SR
; No, EDE not equal 1500.
; Yes, R5 = 1500. Continue
R7 (20-bit counter) is decremented. If its content is not zero, the program continues at
Label4. Program in full memory range.
#1,R7
Label4
; Decrement R7
; Zero not reached: Go to Label4
; Yes, R7 = 0. Continue here.
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4.6.2.32 MOV
MOV[.W]
MOV.B
Syntax
Move source word to destination word
Move source byte to destination byte
MOV src,dst or MOV.W src,dst
MOV.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
MOV
Example
Loop
Example
Loop
210
CPUX
src → dst
The source operand is copied to the destination. The source operand is not affected.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Move a 16-bit constant 1800h to absolute address-word EDE (lower 64 K)
#01800h,&EDE
; Move 1800h to EDE
The contents of table EDE (word data, 16-bit addresses) are copied to table TOM. The
length of the tables is 030h words. Both tables reside in the lower 64 K.
MOV
MOV
#EDE,R10
@R10+,TOM-EDE-2(R10)
CMP
JLO
...
#EDE+60h,R10
Loop
;
;
;
;
;
;
Prepare pointer (16-bit address)
R10 points to both tables.
R10+2
End of table reached?
Not yet
Copy completed
The contents of table EDE (byte data, 16-bit addresses) are copied to table TOM. The
length of the tables is 020h bytes. Both tables may reside in full memory range, but must
be within R10 ± 32 K.
MOVA
MOV
MOV.B
#EDE,R10
#20h,R9
@R10+,TOM-EDE-1(R10)
DEC
JNZ
...
R9
Loop
;
;
;
;
;
;
;
Prepare pointer (20-bit)
Prepare counter
R10 points to both tables.
R10+1
Decrement counter
Not yet done
Copy completed
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4.6.2.33 NOP
* NOP
Syntax
Operation
Emulation
Description
Status Bits
No operation
NOP
None
MOV #0, R3
No operation is performed. The instruction may be used for the elimination of instructions
during the software check or for defined waiting times.
Status bits are not affected.
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4.6.2.34 POP
* POP[.W]
* POP.B
Syntax
Pop word from stack to destination
Pop byte from stack to destination
POP dst
POP.B dst
Operation
@SP → temp
SP + 2 → SP
temp → dst
Emulation
MOV @SP+,dst or MOV.W @SP+,dst
MOV.B @SP+,dst
Description
The stack location pointed to by the SP (TOS) is moved to the destination. The SP is
incremented by two afterwards.
Status bits are not affected.
The contents of R7 and the SR are restored from the stack.
Status Bits
Example
POP
POP
R7
SR
Example
The contents of RAM byte LEO is restored from the stack.
POP.B
Example
LEO
; The low byte of the stack is moved to LEO.
The contents of R7 is restored from the stack.
POP.B
Example
R7
; The low byte of the stack is moved to R7,
; the high byte of R7 is 00h
The contents of the memory pointed to by R7 and the SR are restored from the stack.
POP.B
0(R7)
POP
SR
NOTE:
; Restore R7
; Restore status register
;
;
:
;
:
;
;
The low byte of the stack is moved to the
the byte which is pointed to by R7
Example:
R7 = 203h
Mem(R7) = low byte of system stack
Example:
R7 = 20Ah
Mem(R7) = low byte of system stack
Last word on stack moved to the SR
System stack pointer
The system SP is always incremented by two, independent of the byte suffix.
212
CPUX
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4.6.2.35 PUSH
PUSH[.W]
PUSH.B
Syntax
Save a word on the stack
Save a byte on the stack
PUSH dst or
PUSH.W dst
PUSH.B dst
Operation
Description
Status Bits
Mode Bits
Example
PUSH
PUSH
Example
PUSH.B
PUSH.B
SP – 2 → SP
dst → @SP
The 20-bit SP SP is decremented by two. The operand is then copied to the RAM word
addressed by the SP. A pushed byte is stored in the low byte; the high byte is not
affected.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
Save the two 16-bit registers R9 and R10 on the stack
R9
R10
; Save R9 and R10 XXXXh
; YYYYh
Save the two bytes EDE and TONI on the stack. The addresses EDE and TONI are
within PC ± 32 K.
EDE
TONI
; Save EDE
; Save TONI
xxXXh
xxYYh
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4.6.2.36 RET
* RET
Syntax
Operation
Description
Status Bits
Mode Bits
Example
SUBR
Return from subroutine
RET
@SP →PC.15:0
Saved PC to PC.15:0.
PC.19:16 ← 0
SP + 2 → SP
The 16-bit return address (lower 64 K), pushed onto the stack by a CALL instruction is
restored to the PC. The program continues at the address following the subroutine call.
The four MSBs of the PC.19:16 are cleared.
Status bits are not affected.
PC.19:16: Cleared
OSCOFF, CPUOFF, and GIE are not affected.
Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64 K
after the CALL.
CALL
...
PUSH
...
POP
RET
#SUBR
R14
R14
;
;
;
;
;
;
Call subroutine starting at SUBR
Return by RET to here
Save R14 (16 bit data)
Subroutine code
Restore R14
Return to lower 64 K
Item n
SP
SP
Item n
PCReturn
Stack before RET
instruction
Stack after RET
instruction
Figure 4-37. Stack After a RET Instruction
214
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4.6.2.37 RETI
RETI
Syntax
Operation
Description
Status Bits
Mode Bits
Example
INTRPT
Return from interrupt
RETI
@SP → SR.15:0
SP + 2 → SP
@SP → PC.15:0
SP + 2 → SP
Restore saved SR with PC.19:16
Restore saved PC.15:0
Housekeeping
The SR is restored to the value at the beginning of the interrupt service routine. This
includes the four MSBs of the PC.19:16. The SP is incremented by two afterward.
The 20-bit PC is restored from PC.19:16 (from same stack location as the status bits)
and PC.15:0. The 20-bit PC is restored to the value at the beginning of the interrupt
service routine. The program continues at the address following the last executed
instruction when the interrupt was granted. The SP is incremented by two afterward.
N: Restored from stack
C: Restored from stack
Z: Restored from stack
V: Restored from stack
OSCOFF, CPUOFF, and GIE are restored from stack.
Interrupt handler in the lower 64 K. A 20-bit return address is stored on the stack.
PUSHM.A
...
POPM.A
RETI
#2,R14
#2,R14
;
;
;
;
Save R14 and R13 (20-bit data)
Interrupt handler code
Restore R13 and R14 (20-bit data)
Return to 20-bit address in full memory range
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4.6.2.38 RLA
* RLA[.W]
* RLA.B
Syntax
Rotate left arithmetically
Rotate left arithmetically
RLA dst or
RLA.W dst
RLA.B dst
Operation
Emulation
C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0
ADD dst,dst
ADD.B dst,dst
Description
The destination operand is shifted left one position as shown in Figure 4-38. The MSB is
shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a
signed multiplication by 2.
An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed; the
result has changed sign.
Word
15
0
0
C
Byte
7
0
Figure 4-38. Destination Operand—Arithmetic Shift Left
Status Bits
Mode Bits
Example
RLA
An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed; the
result has changed sign.
N: Set if result is negative, reset if positive
Z: Set if result is zero, reset otherwise
C: Loaded from the MSB
V: Set if an arithmetic overflow occurs; the initial value is 04000h ≤ dst < 0C000h,
reset otherwise
Set if an arithmetic overflow occurs; the initial value is 040h ≤ dst < 0C0h, reset
otherwise
OSCOFF, CPUOFF, and GIE are not affected.
R7 is multiplied by 2.
R7
Example
; Shift left R7
(x 2)
The low byte of R7 is multiplied by 4.
RLA.B
RLA.B
R7
R7
; Shift left low byte of R7
; Shift left low byte of R7
(x 2)
(x 4)
NOTE: RLA substitution
The assembler does not recognize the instructions:
RLA
@R5+
RLA.B
@R5+
RLA(.B) @R5
@R5+,-1(R5)
ADD(.B) @R5
They must be substituted by:
ADD
216
CPUX
@R5+,-2(R5)
ADD.B
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4.6.2.39 RLC
* RLC[.W]
* RLC.B
Syntax
Rotate left through carry
Rotate left through carry
RLC dst or
RLC.W dst
RLC.B dst
C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C
Operation
Emulation
Description
ADDC dst,dst
The destination operand is shifted left one position as shown in Figure 4-39. The carry bit
(C) is shifted into the LSB, and the MSB is shifted into the carry bit (C).
Word
15
0
7
0
C
Byte
Figure 4-39. Destination Operand—Carry Left Shift
Set if result is negative, reset if positive
Set if result is zero, reset otherwise
Loaded from the MSB
Set if an arithmetic overflow occurs; the initial value is 04000h ≤ dst < 0C000h,
reset otherwise
Set if an arithmetic overflow occurs; the initial value is 040h ≤ dst < 0C0h, reset
otherwise
OSCOFF, CPUOFF, and GIE are not affected.
R5 is shifted left one position.
Status Bits
N:
Z:
C:
V:
Mode Bits
Example
RLC
R5
Example
; (R5 x 2) + C -> R5
The input P1IN.1 information is shifted into the LSB of R5.
BIT.B
RLC
#2,&P1IN
R5
Example
; Information -> Carry
; Carry=P0in.1 -> LSB of R5
The MEM(LEO) content is shifted left one position.
RLC.B
LEO
; Mem(LEO) x 2 + C -> Mem(LEO)
NOTE: RLA substitution
The assembler does not recognize the instructions:
RLC
@R5+
RLC.B
@R5+
RLC(.B) @R5
They must be substituted by:
ADDC
@R5+,-2(R5)
ADDC.B
@R5+,-1(R5)
ADDC(.B) @R5
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4.6.2.40 RRA
RRA[.W]
RRA.B
Syntax
Operation
Description
Rotate right arithmetically destination word
Rotate right arithmetically destination byte
RRA.B dst or
RRA.W dst
MSB → MSB → MSB–1 → ... LSB+1 → LSB → C
The destination operand is shifted right arithmetically by one bit position as shown in
Figure 4-40. The MSB retains its value (sign). RRA operates equal to a signed division
by 2. The MSB is retained and shifted into the MSB–1. The LSB+1 is shifted into the
LSB. The previous LSB is shifted into the carry bit C.
N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The signed 16-bit number in R5 is shifted arithmetically right one position.
Status Bits
Mode Bits
Example
RRA
R5
Example
RRA.B
; R5/2 -> R5
The signed RAM byte EDE is shifted arithmetically right one position.
EDE
; EDE/2 -> EDE
19
C
0
15
0
0
0
19
C
0
0
0
0
0
0
0
0
0
0
0
0
7
0
MSB
LSB
15
0
MSB
LSB
Figure 4-40. Rotate Right Arithmetically RRA.B and RRA.W
218
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4.6.2.41 RRC
RRC[.W]
RRC.B
Syntax
Rotate right through carry destination word
Rotate right through carry destination byte
RRC dst or
RRC.W dst
RRC.B dst
C → MSB → MSB–1 → ... LSB+1 → LSB → C
The destination operand is shifted right by one bit position as shown in Figure 4-41. The
carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C.
N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
RAM word EDE is shifted right one bit position. The MSB is loaded with 1.
Operation
Description
Status Bits
Mode Bits
Example
SETC
RRC
; Prepare carry for MSB
; EDE = EDE >> 1 + 8000h
EDE
19
C
0
15
0
0
0
19
C
0
0
0
0
0
0
0
0
0
0
0
0
7
0
MSB
LSB
15
0
MSB
LSB
Figure 4-41. Rotate Right Through Carry RRC.B and RRC.W
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4.6.2.42 SBC
* SBC[.W]
* SBC.B
Syntax
Subtract borrow (.NOT. carry) from destination
Subtract borrow (.NOT. carry) from destination
SBC dst or
SBC.W dst
SBC.B dst
Operation
dst + 0FFFFh + C → dst
dst + 0FFh + C → dst
Emulation
SUBC #0,dst
SUBC.B #0,dst
Description
Status Bits
Mode Bits
Example
SUB
SBC
@R13,0(R12)
2(R12)
Example
; Subtract LSDs
; Subtract carry from MSD
The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by
R12.
SUB.B
SBC.B
NOTE:
The carry bit (C) is added to the destination operand minus one. The previous contents
of the destination are lost.
N: Set if result is negative, reset if positive
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
Set to 1 if no borrow, reset if borrow
V: Set if an arithmetic overflow occurs, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by
R12.
@R13,0(R12)
1(R12)
; Subtract LSDs
; Subtract carry from MSD
Borrow implementation
The borrow is treated as a .NOT. carry:
Borrow
Yes
No
220
CPUX
Carry Bit
0
1
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4.6.2.43 SETC
* SETC
Syntax
Operation
Emulation
Description
Status Bits
Mode Bits
Example
DSUB
Set carry bit
SETC
1→C
BIS #1,SR
The carry bit (C) is set.
N: Not affected
Z: Not affected
C: Set
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Emulation of the decimal subtraction:
Subtract R5 from R6 decimally.
Assume that R5 = 03987h and R6 = 04137h.
ADD
#06666h,R5
INV
R5
SETC
DADD
R5,R6
;
;
;
;
;
;
;
;
;
Move content R5 from 0-9 to 6-0Fh
R5 = 03987h + 06666h = 09FEDh
Invert this (result back to 0-9)
R5 = .NOT. R5 = 06012h
Prepare carry = 1
Emulate subtraction by addition of:
(010000h - R5 - 1)
R6 = R6 + R5 + 1
R6 = 0150h
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4.6.2.44 SETN
* SETN
Syntax
Operation
Emulation
Description
Status Bits
Mode Bits
222
CPUX
Set negative bit
SETN
1→N
BIS #4,SR
The negative bit (N) is set.
N: Set
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
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4.6.2.45 SETZ
* SETZ
Syntax
Operation
Emulation
Description
Status Bits
Mode Bits
Set zero bit
SETZ
1→N
BIS #2,SR
The zero bit (Z) is set.
N: Not affected
Z: Set
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
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4.6.2.46 SUB
SUB[.W]
SUB.B
Syntax
Subtract source word from destination word
Subtract source byte from destination byte
SUB src,dst or SUB.W src,dst
SUB.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
SUB
Example
SUB
JZ
...
Example
SUB.B
224
CPUX
(.not.src) + 1 + dst → dst or dst – src → dst
The source operand is subtracted from the destination operand. This is made by adding
the 1s complement of the source + 1 to the destination. The source operand is not
affected, the result is written to the destination operand.
N: Set if result is negative (src > dst), reset if positive (src ≤ dst)
Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source operand
from a negative destination operand delivers a positive result, reset otherwise (no
overflow)
OSCOFF, CPUOFF, and GIE are not affected.
A 16-bit constant 7654h is subtracted from RAM word EDE.
#7654h,&EDE
; Subtract 7654h from EDE
A table word pointed to by R5 (20-bit address) is subtracted from R7. Afterwards, if R7
contains zero, jump to label TONI. R5 is then auto-incremented by 2. R7.19:16 = 0.
@R5+,R7
TONI
; Subtract table number from R7. R5 + 2
; R7 = @R5 (before subtraction)
; R7 <> @R5 (before subtraction)
Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32K.
The address R12 points to is in full memory range.
CNT,0(R12)
; Subtract CNT from @R12
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4.6.2.47 SUBC
SUBC[.W]
SUBC.B
Syntax
Subtract source word with carry from destination word
Subtract source byte with carry from destination byte
SUBC src,dst or SUBC.W src,dst
SUBC.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
SUBC.W
Example
SUB
SUBC
SUBC
Example
SUBC.B
(.not.src) + C + dst → dst or dst – (src – 1) + C → dst
The source operand is subtracted from the destination operand. This is done by adding
the 1s complement of the source + carry to the destination. The source operand is not
affected, the result is written to the destination operand. Used for 32, 48, and 64-bit
operands.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source operand
from a negative destination operand delivers a positive result, reset otherwise (no
overflow)
OSCOFF, CPUOFF, and GIE are not affected.
A 16-bit constant 7654h is subtracted from R5 with the carry from the previous
instruction. R5.19:16 = 0
#7654h,R5
; Subtract 7654h + C from R5
A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit
counter in RAM, pointed to by R7. R5 points to the next 48-bit number afterwards. The
address R7 points to is in full memory range.
@R5+,0(R7)
@R5+,2(R7)
@R5+,4(R7)
; Subtract LSBs. R5 + 2
; Subtract MIDs with C. R5 + 2
; Subtract MSBs with C. R5 + 2
Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction
is used. The address of CNT is in lower 64 K.
&CNT,0(R12)
; Subtract byte CNT from @R12
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4.6.2.48 SWPB
SWPB
Syntax
Operation
Description
Swap bytes
SWPB dst
dst.15:8 ↔ dst.7:0
The high and the low byte of the operand are exchanged. PC.19:16 bits are cleared in
register mode.
Status bits are not affected
OSCOFF, CPUOFF, and GIE are not affected.
Exchange the bytes of RAM word EDE (lower 64 K)
Status Bits
Mode Bits
Example
MOV
SWPB
#1234h,&EDE
&EDE
; 1234h -> EDE
; 3412h -> EDE
Before SWPB
15
8
7
0
High Byte
Low Byte
After SWPB
15
8
7
0
Low Byte
High Byte
Figure 4-42. Swap Bytes in Memory
Before SWPB
19
16 15
x
8
7
High Byte
0
Low Byte
After SWPB
19
16
0
... 0
15
8
Low Byte
7
0
High Byte
Figure 4-43. Swap Bytes in a Register
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4.6.2.49 SXT
SXT
Syntax
Operation
Description
Status Bits
Mode Bits
Example
MOV.B
SXT
ADD
Example
MOV.B
SXT
ADDA
Extend sign
SXT dst
dst.7 → dst.15:8, dst.7 → dst.19:8 (register mode)
Register mode: the sign of the low byte of the operand is extended into the bits
Rdst.19:8.
Rdst.7 = 0: Rdst.19:8 = 000h afterwards
Rdst.7 = 1: Rdst.19:8 = FFFh afterwards
Other modes: the sign of the low byte of the operand is extended into the high byte.
dst.7 = 0: high byte = 00h afterwards
dst.7 = 1: high byte = FFh afterwards
N: Set if result is negative, reset otherwise
Z: Set if result is zero, reset otherwise
C: Set if result is not zero, reset otherwise (C = .not.Z)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The signed 8-bit data in EDE (lower 64 K) is sign extended and added to the 16-bit
signed data in R7.
&EDE,R5
R5
R5,R7
; EDE -> R5. 00XXh
; Sign extend low byte to R5.19:8
; Add signed 16-bit values
The signed 8-bit data in EDE (PC +32 K) is sign extended and added to the 20-bit data
in R7.
EDE,R5
R5
R5,R7
; EDE -> R5. 00XXh
; Sign extend low byte to R5.19:8
; Add signed 20-bit values
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4.6.2.50 TST
* TST[.W]
* TST.B
Syntax
Test destination
Test destination
TST dst or
TST.W dst
TST.B dst
Operation
dst + 0FFFFh + 1
dst + 0FFh + 1
Emulation
CMP #0,dst
CMP.B #0,dst
Description
Status Bits
Mode Bits
Example
R7POS
R7NEG
R7ZERO
Example
R7POS
R7NEG
R7ZERO
228
CPUX
The destination operand is compared with zero. The status bits are set according to the
result. The destination is not affected.
N: Set if destination is negative, reset if positive
Z: Set if destination contains zero, reset otherwise
C: Set
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at
R7POS.
TST
JN
JZ
......
......
......
R7
R7NEG
R7ZERO
;
;
;
;
;
;
Test R7
R7 is negative
R7 is zero
R7 is positive but not zero
R7 is negative
R7 is zero
The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not
zero, continue at R7POS.
TST.B
JN
JZ
......
.....
......
R7
R7NEG
R7ZERO
;
;
;
;
;
;
Test low
Low byte
Low byte
Low byte
Low byte
Low byte
byte of R7
of R7 is negative
of R7 is zero
of R7 is positive but not zero
of R7 is negative
of R7 is zero
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4.6.2.51 XOR
XOR[.W]
XOR.B
Syntax
Exclusive OR source word with destination word
Exclusive OR source byte with destination byte
XOR src,dst or XOR.W src,dst
XOR.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
XOR
Example
XOR
Example
XOR.B
INV.B
src .xor. dst → dst
The source and destination operands are exclusively ORed. The result is placed into the
destination. The source operand is not affected. The previous content of the destination
is lost.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if result is not zero, reset otherwise (C = .not. Z)
V: Set if both operands are negative before execution, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
Toggle bits in word CNTR (16-bit data) with information (bit = 1) in address-word TONI.
Both operands are located in lower 64 K.
&TONI,&CNTR
; Toggle bits in CNTR
A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. R6.19:16 = 0.
@R5,R6
; Toggle bits in R6
Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE.
R7.19:8 = 0. The address of EDE is within PC ± 32 K.
EDE,R7
R7
; Set different bits to 1 in R7.
; Invert low byte of R7, high byte is 0h
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4.6.3 Extended Instructions
The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space.
MSP430X instructions require an additional word of op-code called the extension word. All addresses,
indexes, and immediate numbers have 20-bit values when preceded by the extension word. The
MSP430X extended instructions are listed and described in the following pages.
230
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4.6.3.1
ADCX
* ADCX.A
* ADCX.[W]
* ADCX.B
Syntax
Add carry to destination address-word
Add carry to destination word
Add carry to destination byte
ADCX.A dst
ADCX dst or
ADCX.B dst
Operation
Emulation
ADCX.W dst
dst + C → dst
ADDCX.A #0,dst
ADDCX #0,dst
ADDCX.B #0,dst
Description
Status Bits
Mode Bits
Example
INCX.A
ADCX.A
The carry bit (C) is added to the destination operand. The previous contents of the
destination are lost.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
V: Set if the result of two positive operands is negative, or if the result of two negative
numbers is positive, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The 40-bit counter, pointed to by R12 and R13, is incremented.
@R12
@R13
; Increment lower 20 bits
; Add carry to upper 20 bits
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ADDX
ADDX.A
ADDX.[W]
ADDX.B
Syntax
Add source address-word to destination address-word
Add source word to destination word
Add source byte to destination byte
ADDX.A src,dst
ADDX src,dst or ADDX.W src,dst
ADDX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
ADDX.A
Example
ADDX.W
JC
...
Example
ADDX.B
JNC
...
src + dst → dst
The source operand is added to the destination operand. The previous contents of the
destination are lost. Both operands can be located in the full address space.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
V: Set if the result of two positive operands is negative, or if the result of two negative
numbers is positive, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
Ten is added to the 20-bit pointer CNTR located in two words CNTR (LSBs) and
CNTR+2 (MSBs).
#10,CNTR
; Add 10 to 20-bit pointer
A table word (16-bit) pointed to by R5 (20-bit address) is added to R6. The jump to label
TONI is performed on a carry.
@R5,R6
TONI
; Add table word to R6
; Jump if carry
; No carry
A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is
performed if no carry occurs. The table pointer is auto-incremented by 1.
@R5+,R6
TONI
; Add table byte to R6. R5 + 1. R6: 000xxh
; Jump if no carry
; Carry occurred
Note: Use ADDA for the following two cases for better code density and execution.
ADDX.A
ADDX.A
232
CPUX
Rsrc,Rdst
#imm20,Rdst
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4.6.3.3
ADDCX
ADDCX.A
ADDCX.[W]
ADDCX.B
Syntax
Add source address-word and carry to destination address-word
Add source word and carry to destination word
Add source byte and carry to destination byte
ADDCX.A src,dst
ADDCX src,dst or ADDCX.W src,dst
ADDCX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
src + dst + C → dst
The source operand and the carry bit C are added to the destination operand. The
previous contents of the destination are lost. Both operands may be located in the full
address space.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
V: Set if the result of two positive operands is negative, or if the result of two negative
numbers is positive, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
Constant 15 and the carry of the previous instruction are added to the 20-bit counter
CNTR located in two words.
ADDCX.A
Example
; Add 15 + C to 20-bit CNTR
A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The
jump to label TONI is performed on a carry.
ADDCX.W
JC
...
Example
#15,&CNTR
@R5,R6
TONI
; Add table word + C to R6
; Jump if carry
; No carry
A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The
jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented
by 1.
ADDCX.B
JNC
...
@R5+,R6
TONI
; Add table byte + C to R6. R5 + 1
; Jump if no carry
; Carry occurred
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ANDX
ANDX.A
ANDX.[W]
ANDX.B
Syntax
Logical AND of source address-word with destination address-word
Logical AND of source word with destination word
Logical AND of source byte with destination byte
ANDX.A src,dst
ANDX src,dst or ANDX.W src,dst
ANDX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
MOVA
ANDX.A
JZ
...
src .and. dst → dst
The source operand and the destination operand are logically ANDed. The result is
placed into the destination. The source operand is not affected. Both operands may be
located in the full address space.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if the result is not zero, reset otherwise. C = (.not. Z)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The bits set in R5 (20-bit data) are used as a mask (AAA55h) for the address-word TOM
located in two words. If the result is zero, a branch is taken to label TONI.
#AAA55h,R5
R5,TOM
TONI
;
;
;
;
Load 20-bit mask to R5
TOM .and. R5 -> TOM
Jump if result 0
Result > 0
or shorter:
ANDX.A
JZ
Example
ANDX.B
234
CPUX
#AAA55h,TOM
TONI
; TOM .and. AAA55h -> TOM
; Jump if result 0
A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0.
The table pointer is auto-incremented by 1.
@R5+,R6
; AND table byte with R6. R5 + 1
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4.6.3.5
BICX
BICX.A
BICX.[W]
BICX.B
Syntax
Clear bits set in source address-word in destination address-word
Clear bits set in source word in destination word
Clear bits set in source byte in destination byte
BICX.A src,dst
BICX src,dst or BICX.W src,dst
BICX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
BICX.A
Example
BICX.W
Example
BICX.B
(.not. src) .and. dst → dst
The inverted source operand and the destination operand are logically ANDed. The
result is placed into the destination. The source operand is not affected. Both operands
may be located in the full address space.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
The bits 19:15 of R5 (20-bit data) are cleared.
#0F8000h,R5
; Clear R5.19:15 bits
A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0.
@R5,R7
; Clear bits in R7
A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1.
@R5,&P1OUT
; Clear I/O port P1 bits
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BISX
BISX.A
BISX.[W]
BISX.B
Syntax
Set bits set in source address-word in destination address-word
Set bits set in source word in destination word
Set bits set in source byte in destination byte
BISX.A src,dst
BISX src,dst or BISX.W src,dst
BISX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
BISX.A
Example
BISX.W
Example
BISX.B
236
CPUX
src .or. dst → dst
The source operand and the destination operand are logically ORed. The result is placed
into the destination. The source operand is not affected. Both operands may be located
in the full address space.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Bits 16 and 15 of R5 (20-bit data) are set to one.
#018000h,R5
; Set R5.16:15 bits
A table word pointed to by R5 (20-bit address) is used to set bits in R7.
@R5,R7
; Set bits in R7
A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1.
@R5,&P1OUT
; Set I/O port P1 bits
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4.6.3.7
BITX
BITX.A
BITX.[W]
BITX.B
Syntax
Test bits set in source address-word in destination address-word
Test bits set in source word in destination word
Test bits set in source byte in destination byte
BITX.A src,dst
BITX src,dst or BITX.W src,dst
BITX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
BITX.A
JNZ
...
Example
BITX.W
JC
...
Example
BITX.B
JNC
...
src .and. dst → dst
The source operand and the destination operand are logically ANDed. The result affects
only the status bits. Both operands may be located in the full address space.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if the result is not zero, reset otherwise. C = (.not. Z)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
Test if bit 16 or 15 of R5 (20-bit data) is set. Jump to label TONI if so.
#018000h,R5
TONI
; Test R5.16:15 bits
; At least one bit is set
; Both are reset
A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label
TONI if at least one bit is set.
@R5,R7
TONI
; Test bits in R7: C = .not.Z
; At least one is set
; Both are reset
A table byte pointed to by R5 (20-bit address) is used to test bits in input Port1. Jump to
label TONI if no bit is set. The next table byte is addressed.
@R5+,&P1IN
TONI
; Test input P1 bits. R5 + 1
; No corresponding input bit is set
; At least one bit is set
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CLRX
* CLRX.A
* CLRX.[W]
* CLRX.B
Syntax
Clear destination address-word
Clear destination word
Clear destination byte
CLRX.A dst
CLRX dst or
CLRX.B dst
Operation
Emulation
CLRX.W dst
0 → dst
MOVX.A #0,dst
MOVX #0,dst
MOVX.B #0,dst
Description
Status Bits
Mode Bits
Example
CLRX.A
238
CPUX
The destination operand is cleared.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
RAM address-word TONI is cleared.
TONI
; 0 -> TONI
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4.6.3.9
CMPX
CMPX.A
CMPX.[W]
CMPX.B
Syntax
Compare source address-word and destination address-word
Compare source word and destination word
Compare source byte and destination byte
CMPX.A src,dst
CMPX src,dst or CMPX.W src,dst
CMPX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
CMPX.A
JEQ
...
Example
CMPX.W
JL
...
Example
CMPX.B
JEQ
...
(.not. src) + 1 + dst or dst – src
The source operand is subtracted from the destination operand by adding the 1s
complement of the source + 1 to the destination. The result affects only the status bits.
Both operands may be located in the full address space.
N: Set if result is negative (src > dst), reset if positive (src ≤ dst)
Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source operand
from a negative destination operand delivers a positive result, reset otherwise (no
overflow)
OSCOFF, CPUOFF, and GIE are not affected.
Compare EDE with a 20-bit constant 18000h. Jump to label TONI if EDE equals the
constant.
#018000h,EDE
TONI
; Compare EDE with 18000h
; EDE contains 18000h
; Not equal
A table word pointed to by R5 (20-bit address) is compared with R7. Jump to label TONI
if R7 contains a lower, signed, 16-bit number.
@R5,R7
TONI
; Compare two signed numbers
; R7 < @R5
; R7 >= @R5
A table byte pointed to by R5 (20-bit address) is compared to the input in I/O Port1.
Jump to label TONI if the values are equal. The next table byte is addressed.
@R5+,&P1IN
TONI
; Compare P1 bits with table. R5 + 1
; Equal contents
; Not equal
Note: Use CMPA for the following two cases for better density and execution.
CMPA
CMPA
Rsrc,Rdst
#imm20,Rdst
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4.6.3.10 DADCX
* DADCX.A
* DADCX.[W]
* DADCX.B
Syntax
Add carry decimally to destination address-word
Add carry decimally to destination word
Add carry decimally to destination byte
DADCX.A dst
DADCX dst or
DADCX.B dst
Operation
Emulation
DADCX.W dst
dst + C → dst (decimally)
DADDX.A #0,dst
DADDX #0,dst
DADDX.B #0,dst
Description
Status Bits
Mode Bits
Example
The carry bit (C) is added decimally to the destination.
N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset
if MSB is 0
Z: Set if result is zero, reset otherwise
C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte >
99h), reset otherwise
V: Undefined
OSCOFF, CPUOFF, and GIE are not affected.
The 40-bit counter, pointed to by R12 and R13, is incremented decimally.
DADDX.A
DADCX.A
240
CPUX
#1,0(R12)
0(R13)
; Increment lower 20 bits
; Add carry to upper 20 bits
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4.6.3.11 DADDX
DADDX.A
DADDX.[W]
DADDX.B
Syntax
Add source address-word and carry decimally to destination address-word
Add source word and carry decimally to destination word
Add source byte and carry decimally to destination byte
DADDX.A src,dst
DADDX src,dst or DADDX.W src,dst
DADDX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
src + dst + C → dst (decimally)
The source operand and the destination operand are treated as two (.B), four (.W), or
five (.A) binary coded decimals (BCD) with positive signs. The source operand and the
carry bit C are added decimally to the destination operand. The source operand is not
affected. The previous contents of the destination are lost. The result is not defined for
non-BCD numbers. Both operands may be located in the full address space.
N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset
if MSB is 0.
Z: Set if result is zero, reset otherwise
C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte >
99h), reset otherwise
V: Undefined
OSCOFF, CPUOFF, and GIE are not affected.
Decimal 10 is added to the 20-bit BCD counter DECCNTR located in two words.
DADDX.A
Example
; Add 10 to 20-bit BCD counter
The eight-digit BCD number contained in 20-bit addresses BCD and BCD+2 is added
decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain
the MSDs).
CLRC
DADDX.W
DADDX.W
JC
...
Example
#10h,&DECCNTR
BCD,R4
BCD+2,R5
OVERFLOW
;
;
;
;
;
Clear carry
Add LSDs
Add MSDs with carry
Result >99999999: go to error routine
Result ok
The two-digit BCD number contained in 20-bit address BCD is added decimally to a twodigit BCD number contained in R4.
CLRC
DADDX.B
; Clear carry
; Add BCD to R4 decimally.
; R4: 000ddh
BCD,R4
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4.6.3.12 DECX
* DECX.A
* DECX.[W]
* DECX.B
Syntax
Decrement destination address-word
Decrement destination word
Decrement destination byte
DECX.A dst
DECX dst or
DECX.B dst
Operation
Emulation
DECX.W dst
dst – 1 → dst
SUBX.A #1,dst
SUBX #1,dst
SUBX.B #1,dst
Description
Status Bits
Mode Bits
Example
DECX.A
242
CPUX
The destination operand is decremented by one. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 1, reset otherwise
C: Reset if dst contained 0, set otherwise
V: Set if an arithmetic overflow occurs, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
RAM address-word TONI is decremented by one.
TONI
; Decrement TONI
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4.6.3.13 DECDX
* DECDX.A
* DECDX.[W]
* DECDX.B
Syntax
Double-decrement destination address-word
Double-decrement destination word
Double-decrement destination byte
DECDX.A dst
DECDX dst or
DECDX.B dst
Operation
Emulation
DECDX.W dst
dst – 2 → dst
SUBX.A #2,dst
SUBX #2,dst
SUBX.B #2,dst
Description
Status Bits
Mode Bits
Example
The destination operand is decremented by two. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 2, reset otherwise
C: Reset if dst contained 0 or 1, set otherwise
V: Set if an arithmetic overflow occurs, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
RAM address-word TONI is decremented by two.
DECDX.A
TONI
; Decrement TONI
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4.6.3.14 INCX
* INCX.A
* INCX.[W]
* INCX.B
Syntax
Increment destination address-word
Increment destination word
Increment destination byte
INCX.A dst
INCX dst or
INCX.B dst
Operation
Emulation
INCX.W dst
dst + 1 → dst
ADDX.A #1,dst
ADDX #1,dst
ADDX.B #1,dst
Description
Status Bits
Mode Bits
Example
INCX.A
244
CPUX
The destination operand is incremented by one. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 0FFFFFh, reset otherwise
Set if dst contained 0FFFFh, reset otherwise
Set if dst contained 0FFh, reset otherwise
C: Set if dst contained 0FFFFFh, reset otherwise
Set if dst contained 0FFFFh, reset otherwise
Set if dst contained 0FFh, reset otherwise
V: Set if dst contained 07FFFh, reset otherwise
Set if dst contained 07FFFh, reset otherwise
Set if dst contained 07Fh, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
RAM address-wordTONI is incremented by one.
TONI
; Increment TONI (20-bits)
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4.6.3.15 INCDX
* INCDX.A
* INCDX.[W]
* INCDX.B
Syntax
Double-increment destination address-word
Double-increment destination word
Double-increment destination byte
INCDX.A dst
INCDX dst or
INCDX.B dst
Operation
Emulation
INCDX.W dst
dst + 2 → dst
ADDX.A #2,dst
ADDX #2,dst
ADDX.B #2,dst
Description
Status Bits
Mode Bits
Example
The destination operand is incremented by two. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 0FFFFEh, reset otherwise
Set if dst contained 0FFFEh, reset otherwise
Set if dst contained 0FEh, reset otherwise
C: Set if dst contained 0FFFFEh or 0FFFFFh, reset otherwise
Set if dst contained 0FFFEh or 0FFFFh, reset otherwise
Set if dst contained 0FEh or 0FFh, reset otherwise
V: Set if dst contained 07FFFEh or 07FFFFh, reset otherwise
Set if dst contained 07FFEh or 07FFFh, reset otherwise
Set if dst contained 07Eh or 07Fh, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
RAM byte LEO is incremented by two; PC points to upper memory.
INCDX.B
LEO
; Increment LEO by two
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4.6.3.16 INVX
* INVX.A
* INVX.[W]
* INVX.B
Syntax
Invert destination
Invert destination
Invert destination
INVX.A dst
INVX dst or
INVX.B dst
Operation
Emulation
INVX.W dst
.NOT.dst → dst
XORX.A #0FFFFFh,dst
XORX #0FFFFh,dst
XORX.B #0FFh,dst
Description
Status Bits
Mode Bits
Example
INVX.A
INCX.A
Example
INVX.B
INCX.B
246
CPUX
The destination operand is inverted. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if dst contained 0FFFFFh, reset otherwise
Set if dst contained 0FFFFh, reset otherwise
Set if dst contained 0FFh, reset otherwise
C: Set if result is not zero, reset otherwise ( = .NOT. Zero)
V: Set if initial destination operand was negative, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
20-bit content of R5 is negated (2s complement).
R5
R5
; Invert R5
; R5 is now negated
Content of memory byte LEO is negated. PC is pointing to upper memory.
LEO
LEO
; Invert LEO
; MEM(LEO) is negated
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4.6.3.17 MOVX
MOVX.A
MOVX.[W]
MOVX.B
Syntax
Move source address-word to destination address-word
Move source word to destination word
Move source byte to destination byte
MOVX.A src,dst
MOVX src,dst or MOVX.W src,dst
MOVX.B src,dst
src → dst
The source operand is copied to the destination. The source operand is not affected.
Both operands may be located in the full address space.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Move a 20-bit constant 18000h to absolute address-word EDE
Operation
Description
Status Bits
Mode Bits
Example
MOVX.A
Example
Loop
; Move 18000h to EDE
The contents of table EDE (word data, 20-bit addresses) are copied to table TOM. The
length of the table is 030h words.
MOVA
MOVX.W
#EDE,R10
@R10+,TOM-EDE-2(R10)
CMPA
JLO
...
#EDE+60h,R10
Loop
Example
Loop
#018000h,&EDE
;
;
;
;
;
;
Prepare pointer (20-bit address)
R10 points to both tables.
R10+2
End of table reached?
Not yet
Copy completed
The contents of table EDE (byte data, 20-bit addresses) are copied to table TOM. The
length of the table is 020h bytes.
MOVA
MOV
MOVX.W
#EDE,R10
#20h,R9
@R10+,TOM-EDE-2(R10)
DEC
JNZ
...
R9
Loop
;
;
;
;
;
;
;
Prepare pointer (20-bit)
Prepare counter
R10 points to both tables.
R10+1
Decrement counter
Not yet done
Copy completed
Ten of the 28 possible addressing combinations of the MOVX.A instruction can use the
MOVA instruction. This saves two bytes and code cycles. Examples for the addressing
combinations are:
MOVX.A
MOVX.A
MOVX.A
MOVX.A
MOVX.A
MOVX.A
Rsrc,Rdst
#imm20,Rdst
&abs20,Rdst
@Rsrc,Rdst
@Rsrc+,Rdst
Rsrc,&abs20
MOVA
MOVA
MOVA
MOVA
MOVA
MOVA
Rsrc,Rdst
#imm20,Rdst
&abs20,Rdst
@Rsrc,Rdst
@Rsrc+,Rdst
Rsrc,&abs20
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;
;
;
;
;
;
Reg/Reg
Immediate/Reg
Absolute/Reg
Indirect/Reg
Indirect,Auto/Reg
Reg/Absolute
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The next four replacements are possible only if 16-bit indexes are sufficient for the
addressing:
MOVX.A
MOVX.A
MOVX.A
MOVX.A
248
CPUX
z20(Rsrc),Rdst
Rsrc,z20(Rdst)
symb20,Rdst
Rsrc,symb20
MOVA
MOVA
MOVA
MOVA
z16(Rsrc),Rdst
Rsrc,z16(Rdst)
symb16,Rdst
Rsrc,symb16
;
;
;
;
Indexed/Reg
Reg/Indexed
Symbolic/Reg
Reg/Symbolic
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4.6.3.18 POPM
POPM.A
POPM.[W]
Syntax
Operation
Description
Status Bits
Mode Bits
Example
POPM.A
Example
POPM.W
Restore n CPU registers (20-bit data) from the stack
Restore n CPU registers (16-bit data) from the stack
1 ≤ n ≤ 16
POPM.W #n,Rdst or POPM #n,Rdst
1 ≤ n ≤ 16
POPM.A: Restore the register values from stack to the specified CPU registers. The SP
is incremented by four for each register restored from stack. The 20-bit values from
stack (two words per register) are restored to the registers.
POPM.W: Restore the 16-bit register values from stack to the specified CPU registers.
The SP is incremented by two for each register restored from stack. The 16-bit values
from stack (one word per register) are restored to the CPU registers.
Note : This instruction does not use the extension word.
POPM.A: The CPU registers pushed on the stack are moved to the extended CPU
registers, starting with the CPU register (Rdst – n + 1). The SP is incremented by (n ×
4) after the operation.
POPM.W: The 16-bit registers pushed on the stack are moved back to the CPU
registers, starting with CPU register (Rdst – n + 1). The SP is incremented by (n × 2)
after the instruction. The MSBs (Rdst.19:16) of the restored CPU registers are cleared.
Status bits are not affected, except SR is included in the operation.
OSCOFF, CPUOFF, and GIE are not affected.
Restore the 20-bit registers R9, R10, R11, R12, R13 from the stack
POPM.A #n,Rdst
#5,R13
; Restore R9, R10, R11, R12, R13
Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack.
#5,R13
; Restore R9, R10, R11, R12, R13
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4.6.3.19 PUSHM
PUSHM.A
PUSHM.[W]
Syntax
Operation
Description
Status Bits
Mode Bits
Example
PUSHM.A
Example
PUSHM.W
250
CPUX
Save n CPU registers (20-bit data) on the stack
Save n CPU registers (16-bit words) on the stack
1 ≤ n ≤ 16
PUSHM.W #n,Rdst or PUSHM #n,Rdst
1 ≤ n ≤ 16
PUSHM.A: Save the 20-bit CPU register values on the stack. The SP is decremented
by four for each register stored on the stack. The MSBs are stored first (higher
address).
PUSHM.W: Save the 16-bit CPU register values on the stack. The SP is decremented
by two for each register stored on the stack.
PUSHM.A: The n CPU registers, starting with Rdst backwards, are stored on the stack.
The SP is decremented by (n × 4) after the operation. The data (Rn.19:0) of the pushed
CPU registers is not affected.
PUSHM.W: The n registers, starting with Rdst backwards, are stored on the stack. The
SP is decremented by (n × 2) after the operation. The data (Rn.19:0) of the pushed
CPU registers is not affected.
Note : This instruction does not use the extension word.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
Save the five 20-bit registers R9, R10, R11, R12, R13 on the stack
PUSHM.A #n,Rdst
#5,R13
; Save R13, R12, R11, R10, R9
Save the five 16-bit registers R9, R10, R11, R12, R13 on the stack
#5,R13
; Save R13, R12, R11, R10, R9
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4.6.3.20 POPX
* POPX.A
* POPX.[W]
* POPX.B
Syntax
Restore single address-word from the stack
Restore single word from the stack
Restore single byte from the stack
POPX.A dst
POPX dst or
POPX.B dst
POPX.W dst
Operation
Restore the 8-, 16-, 20-bit value from the stack to the destination. 20-bit addresses are
possible. The SP is incremented by two (byte and word operands) and by four
(address-word operand).
Emulation
Description
MOVX(.B,.A) @SP+,dst
Status Bits
Mode Bits
Example
POPX.W
Example
POPX.A
The item on TOS is written to the destination operand. Register mode, Indexed mode,
Symbolic mode, and Absolute mode are possible. The SP is incremented by two or
four.
Note: the SP is incremented by two also for byte operations.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
Write the 16-bit value on TOS to the 20-bit address &EDE
&EDE
; Write word to address EDE
Write the 20-bit value on TOS to R9
R9
; Write address-word to R9
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4.6.3.21 PUSHX
PUSHX.A
PUSHX.[W]
PUSHX.B
Syntax
Save single address-word to the stack
Save single word to the stack
Save single byte to the stack
PUSHX.A src
PUSHX src or
PUSHX.B src
Operation
Description
Status Bits
Mode Bits
Example
PUSHX.B
Example
PUSHX.A
252
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PUSHX.W src
Save the 8-, 16-, 20-bit value of the source operand on the TOS. 20-bit addresses are
possible. The SP is decremented by two (byte and word operands) or by four (addressword operand) before the write operation.
The SP is decremented by two (byte and word operands) or by four (address-word
operand). Then the source operand is written to the TOS. All seven addressing modes
are possible for the source operand.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
Save the byte at the 20-bit address &EDE on the stack
&EDE
; Save byte at address EDE
Save the 20-bit value in R9 on the stack.
R9
; Save address-word in R9
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4.6.3.22 RLAM
RLAM.A
RLAM.[W]
Syntax
Rotate left arithmetically the 20-bit CPU register content
Rotate left arithmetically the 16-bit CPU register content
RLAM.A #n,Rdst
RLAM.W #n,Rdst or RLAM #n,Rdst
1≤n≤4
1≤n≤4
C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0
The destination operand is shifted arithmetically left one, two, three, or four positions as
shown in Figure 4-44. RLAM works as a multiplication (signed and unsigned) with 2, 4,
8, or 16. The word instruction RLAM.W clears the bits Rdst.19:16.
Note : This instruction does not use the extension word.
N: Set if result is negative
.A: Rdst.19 = 1, reset if Rdst.19 = 0
.W: Rdst.15 = 1, reset if Rdst.15 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the MSB (n = 1), MSB-1 (n = 2), MSB-2 (n = 3), MSB-3 (n = 4)
V: Undefined
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit operand in R5 is shifted left by three positions. It operates equal to an
arithmetic multiplication by 8.
Operation
Description
Status Bits
Mode Bits
Example
RLAM.A
#3,R5
19
16
0000
C
C
; R5 = R5 x 8
15
0
MSB
LSB
19
0
MSB
LSB
0
0
Figure 4-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A
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4.6.3.23 RLAX
* RLAX.A
* RLAX.[W]
* RLAX.B
Syntax
Rotate left arithmetically address-word
Rotate left arithmetically word
Rotate left arithmetically byte
RLAX.A dst
RLAX dst or
RLAX.B dst
RLAX.W dst
C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0
Operation
Emulation
ADDX.A dst,dst
ADDX dst,dst
ADDX.B dst,dst
Description
The destination operand is shifted left one position as shown in Figure 4-45. The MSB
is shifted into the carry bit (C) and the LSB is filled with 0. The RLAX instruction acts as
a signed multiplication by 2.
N: Set if result is negative, reset if positive
Z: Set if result is zero, reset otherwise
C: Loaded from the MSB
V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h;
reset otherwise
Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h;
reset otherwise
Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset
otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit value in R7 is multiplied by 2
Status Bits
Mode Bits
Example
RLAX.A
R7
; Shift left R7 (20-bit)
0
C
MSB
LSB
0
Figure 4-45. Destination Operand-Arithmetic Shift Left
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4.6.3.24 RLCX
* RLCX.A
* RLCX.[W]
* RLCX.B
Syntax
Rotate left through carry address-word
Rotate left through carry word
Rotate left through carry byte
RLCX.A dst
RLCX dst or
RLCX.B dst
Operation
Emulation
RLCX.W dst
C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C
ADDCX.A dst,dst
ADDCX dst,dst
ADDCX.B dst,dst
Description
Status Bits
Mode Bits
Example
RLCX.A
Example
RLCX.B
The destination operand is shifted left one position as shown in Figure 4-46. The carry
bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
N: Set if result is negative, reset if positive
Z: Set if result is zero, reset otherwise
C: Loaded from the MSB
V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h;
reset otherwise
Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h;
reset otherwise
Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset
otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit value in R5 is shifted left one position.
R5
; (R5 x 2) + C -> R5
The RAM byte LEO is shifted left one position. PC is pointing to upper memory.
LEO
; RAM(LEO) x 2 + C -> RAM(LEO)
0
C
MSB
LSB
Figure 4-46. Destination Operand-Carry Left Shift
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4.6.3.25 RRAM
RRAM.A
RRAM.[W]
Syntax
Rotate right arithmetically the 20-bit CPU register content
Rotate right arithmetically the 16-bit CPU register content
1≤n≤4
1≤n≤4
RRAM.A #n,Rdst
RRAM.W #n,Rdst or RRAM #n,Rdst
MSB → MSB → MSB–1 ... LSB+1 → LSB → C
The destination operand is shifted right arithmetically by one, two, three, or four bit
positions as shown in Figure 4-47. The MSB retains its value (sign). RRAM operates
equal to a signed division by 2, 4, 8, or 16. The MSB is retained and shifted into MSB-1.
The LSB+1 is shifted into the LSB, and the LSB is shifted into the carry bit C. The word
instruction RRAM.W clears the bits Rdst.19:16.
Note : This instruction does not use the extension word.
N: Set if result is negative
.A: Rdst.19 = 1, reset if Rdst.19 = 0
.W: Rdst.15 = 1, reset if Rdst.15 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The signed 20-bit number in R5 is shifted arithmetically right two positions.
Operation
Description
Status Bits
Mode Bits
Example
RRAM.A
Example
#2,R5
; R5/4 -> R5
The signed 20-bit value in R15 is multiplied by 0.75. (0.5 + 0.25) × R15.
PUSHM.A
RRAM.A
ADDX.A
RRAM.A
#1,R15
#1,R15
@SP+,R15
#1,R15
16
19
C
C
0000
;
;
;
;
Save extended R15 on stack
R15 y 0.5 -> R15
R15 y 0.5 + R15 = 1.5 y R15 -> R15
(1.5 y R15) y 0.5 = 0.75 y R15 -> R15
15
0
MSB
LSB
19
0
MSB
LSB
Figure 4-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A
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4.6.3.26 RRAX
RRAX.A
RRAX.[W]
RRAX.B
Syntax
Rotate right arithmetically the 20-bit operand
Rotate right arithmetically the 16-bit operand
Rotate right arithmetically the 8-bit operand
RRAX.A Rdst
RRAX.W Rdst
RRAX Rdst
RRAX.B Rdst
RRAX.A dst
RRAX dst or
RRAX.B dst
Operation
Description
Status Bits
Mode Bits
Example
RPT
RRAX.A
Example
RRAX.W dst
MSB → MSB → MSB–1 ... LSB+1 → LSB → C
Register mode for the destination: the destination operand is shifted right by one bit
position as shown in Figure 4-48. The MSB retains its value (sign). The word instruction
RRAX.W clears the bits Rdst.19:16, the byte instruction RRAX.B clears the bits
Rdst.19:8. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX
here operates equal to a signed division by 2.
All other modes for the destination: the destination operand is shifted right arithmetically
by one bit position as shown in Figure 4-49. The MSB retains its value (sign), the LSB
is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All
addressing modes, with the exception of the Immediate mode, are possible in the full
memory.
N: Set if result is negative, reset if positive
.A: dst.19 = 1, reset if dst.19 = 0
.W: dst.15 = 1, reset if dst.15 = 0
.B: dst.7 = 1, reset if dst.7 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The signed 20-bit number in R5 is shifted arithmetically right four positions.
#4
R5
; R5/16 -> R5
The signed 8-bit value in EDE is multiplied by 0.5.
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RRAX.B
C
www.ti.com
&EDE
19
8
7
0
0
0
MSB
LSB
19
C
C
; EDE/2 -> EDE
16
0000
15
0
MSB
LSB
19
0
MSB
LSB
Figure 4-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode
C
C
C
7
0
MSB
LSB
15
0
MSB
LSB
31
20
0
0
19
0
MSB
LSB
Figure 4-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode
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4.6.3.27 RRCM
RRCM.A
RRCM.[W]
Syntax
Rotate right through carry the 20-bit CPU register content
Rotate right through carry the 16-bit CPU register content
RRCM.A #n,Rdst
RRCM.W #n,Rdst or RRCM #n,Rdst
Operation
Description
Status Bits
Mode Bits
1≤n≤4
1≤n≤4
C → MSB → MSB–1 ... LSB+1 → LSB → C
The destination operand is shifted right by one, two, three, or four bit positions as
shown in Figure 4-50. The carry bit C is shifted into the MSB, the LSB is shifted into the
carry bit. The word instruction RRCM.W clears the bits Rdst.19:16.
Note : This instruction does not use the extension word.
N: Set if result is negative
.A: Rdst.19 = 1, reset if Rdst.19 = 0
.W: Rdst.15 = 1, reset if Rdst.15 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
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The address-word in R5 is shifted right by three positions. The MSB–2 is loaded with 1.
SETC
RRCM.A
Example
; Prepare carry for MSB-2
; R5 = R5 » 3 + 20000h
#3,R5
The word in R6 is shifted right by two positions. The MSB is loaded with the LSB. The
MSB–1 is loaded with the contents of the carry flag.
RRCM.W
#2,R6
; R6 = R6 » 2. R6.19:16 = 0
19
0
C
C
16
15
0
MSB
LSB
19
0
MSB
LSB
Figure 4-50. Rotate Right Through Carry RRCM[.W] and RRCM.A
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4.6.3.28 RRCX
RRCX.A
RRCX.[W]
RRCX.B
Syntax
Rotate right through carry the 20-bit operand
Rotate right through carry the 16-bit operand
Rotate right through carry the 8-bit operand
RRCX.A Rdst
RRCX.W Rdst
RRCX Rdst
RRCX.B Rdst
RRCX.A dst
RRCX dst or
RRCX.B dst
Operation
Description
Status Bits
Mode Bits
Example
SETC
RRCX.A
Example
RRCX.W dst
C → MSB → MSB–1 ... LSB+1 → LSB → C
Register mode for the destination: the destination operand is shifted right by one bit
position as shown in Figure 4-51. The word instruction RRCX.W clears the bits
Rdst.19:16, the byte instruction RRCX.B clears the bits Rdst.19:8. The carry bit C is
shifted into the MSB, the LSB is shifted into the carry bit.
All other modes for the destination: the destination operand is shifted right by one bit
position as shown in Figure 4-52. The carry bit C is shifted into the MSB, the LSB is
shifted into the carry bit. All addressing modes, with the exception of the Immediate
mode, are possible in the full memory.
N: Set if result is negative
.A: dst.19 = 1, reset if dst.19 = 0
.W: dst.15 = 1, reset if dst.15 = 0
.B: dst.7 = 1, reset if dst.7 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit operand at address EDE is shifted right by one position. The MSB is loaded
with 1.
EDE
; Prepare carry for MSB
; EDE = EDE » 1 + 80000h
The word in R6 is shifted right by 12 positions.
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RPT
RRCX.W
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#12
R6
; R6 = R6 » 12. R6.19:16 = 0
8
19
C
0--------------------0
19
C
C
16
0
0
0
0
7
0
MSB
LSB
15
0
MSB
LSB
19
0
MSB
LSB
Figure 4-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode
C
C
C
7
0
MSB
LSB
15
0
MSB
LSB
31
20
0
0
19
0
MSB
LSB
Figure 4-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode
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4.6.3.29 RRUM
RRUM.A
RRUM.[W]
Syntax
Rotate right through carry the 20-bit CPU register content
Rotate right through carry the 16-bit CPU register content
RRUM.A #n,Rdst
RRUM.W #n,Rdst or RRUM #n,Rdst
1≤n≤4
1≤n≤4
0 → MSB → MSB–1 ... LSB+1 → LSB → C
The destination operand is shifted right by one, two, three, or four bit positions as
shown in Figure 4-53. Zero is shifted into the MSB, the LSB is shifted into the carry bit.
RRUM works like an unsigned division by 2, 4, 8, or 16. The word instruction RRUM.W
clears the bits Rdst.19:16.
Note : This instruction does not use the extension word.
N: Set if result is negative
.A: Rdst.19 = 1, reset if Rdst.19 = 0
.W: Rdst.15 = 1, reset if Rdst.15 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The unsigned address-word in R5 is divided by 16.
Operation
Description
Status Bits
Mode Bits
Example
RRUM.A
Example
#4,R5
; R5 = R5 » 4. R5/16
The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0.
RRUM.W
#1,R6
; R6 = R6/2. R6.19:15 = 0
16
19
0000
C
15
0
MSB
LSB
0
C 0
19
0
MSB
LSB
Figure 4-53. Rotate Right Unsigned RRUM[.W] and RRUM.A
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4.6.3.30 RRUX
RRUX.A
RRUX.[W]
RRUX.B
Syntax
Shift right unsigned the 20-bit CPU register content
Shift right unsigned the 16-bit CPU register content
Shift right unsigned the 8-bit CPU register content
RRUX.A Rdst
RRUX.W Rdst
RRUX Rdst
RRUX.B Rdst
C=0 → MSB → MSB–1 ... LSB+1 → LSB → C
RRUX is valid for register mode only: the destination operand is shifted right by one bit
position as shown in Figure 4-54. The word instruction RRUX.W clears the bits
Rdst.19:16. The byte instruction RRUX.B clears the bits Rdst.19:8. Zero is shifted into
the MSB, the LSB is shifted into the carry bit.
N: Set if result is negative
.A: dst.19 = 1, reset if dst.19 = 0
.W: dst.15 = 1, reset if dst.15 = 0
.B: dst.7 = 1, reset if dst.7 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The word in R6 is shifted right by 12 positions.
Operation
Description
Status Bits
Mode Bits
Example
RPT
RRUX.W
#12
R6
; R6 = R6 » 12. R6.19:16 = 0
19
C
8
0--------------------0
7
0
MSB
LSB
0
19
C
0
16
0
0
0
15
0
MSB
LSB
0
C 0
19
0
MSB
LSB
Figure 4-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode
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4.6.3.31 SBCX
* SBCX.A
* SBCX.[W]
* SBCX.B
Syntax
Subtract borrow (.NOT. carry) from destination address-word
Subtract borrow (.NOT. carry) from destination word
Subtract borrow (.NOT. carry) from destination byte
SBCX.A dst
SBCX dst or
SBCX.B dst
SBCX.W dst
Operation
dst + 0FFFFFh + C → dst
dst + 0FFFFh + C → dst
dst + 0FFh + C → dst
Emulation
SBCX.A #0,dst
SBCX #0,dst
SBCX.B #0,dst
Description
Status Bits
Mode Bits
Example
SUBX.B
SBCX.B
NOTE:
The carry bit (C) is added to the destination operand minus one. The previous contents
of the destination are lost.
N: Set if result is negative, reset if positive
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB of the result, reset otherwise
Set to 1 if no borrow, reset if borrow
V: Set if an arithmetic overflow occurs, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by
R12.
@R13,0(R12)
1(R12)
; Subtract LSDs
; Subtract carry from MSD
Borrow implementation
The borrow is treated as a .NOT. carry:
Borrow
Yes
No
Carry Bit
0
1
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4.6.3.32 SUBX
SUBX.A
SUBX.[W]
SUBX.B
Syntax
Subtract source address-word from destination address-word
Subtract source word from destination word
Subtract source byte from destination byte
SUBX.A src,dst
SUBX src,dst or SUBX.W src,dst
SUBX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
SUBX.A
Example
SUBX.W
JZ
...
Example
SUBX.B
(.not. src) + 1 + dst → dst or dst – src → dst
The source operand is subtracted from the destination operand. This is done by adding
the 1s complement of the source + 1 to the destination. The source operand is not
affected. The result is written to the destination operand. Both operands may be located
in the full address space.
N: Set if result is negative (src > dst), reset if positive (src ≤ dst)
Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source operand
from a negative destination operand delivers a positive result, reset otherwise (no
overflow)
OSCOFF, CPUOFF, and GIE are not affected.
A 20-bit constant 87654h is subtracted from EDE (LSBs) and EDE+2 (MSBs).
#87654h,EDE
; Subtract 87654h from EDE+2|EDE
A table word pointed to by R5 (20-bit address) is subtracted from R7. Jump to label
TONI if R7 contains zero after the instruction. R5 is auto-incremented by two. R7.19:16 =
0.
@R5+,R7
TONI
; Subtract table number from R7. R5 + 2
; R7 = @R5 (before subtraction)
; R7 <> @R5 (before subtraction)
Byte CNT is subtracted from the byte R12 points to in the full address space. Address of
CNT is within PC ± 512 K.
CNT,0(R12)
; Subtract CNT from @R12
Note: Use SUBA for the following two cases for better density and execution.
SUBX.A
SUBX.A
266
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#imm20,Rdst
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4.6.3.33 SUBCX
SUBCX.A
SUBCX.[W]
SUBCX.B
Syntax
Subtract source address-word with carry from destination address-word
Subtract source word with carry from destination word
Subtract source byte with carry from destination byte
SUBCX.A src,dst
SUBCX src,dst or SUBCX.W src,dst
SUBCX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
(.not. src) + C + dst → dst or dst – (src – 1) + C → dst
The source operand is subtracted from the destination operand. This is made by adding
the 1s complement of the source + carry to the destination. The source operand is not
affected, the result is written to the destination operand. Both operands may be located
in the full address space.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source operand
from a negative destination operand delivers a positive result, reset otherwise (no
overflow).
OSCOFF, CPUOFF, and GIE are not affected.
A 20-bit constant 87654h is subtracted from R5 with the carry from the previous
instruction.
SUBCX.A
Example
; Subtract 87654h + C from R5
A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit
counter in RAM, pointed to by R7. R5 auto-increments to point to the next 48-bit number.
SUBX.W
SUBCX.W
SUBCX.W
Example
#87654h,R5
@R5+,0(R7)
@R5+,2(R7)
@R5+,4(R7)
; Subtract LSBs. R5 + 2
; Subtract MIDs with C. R5 + 2
; Subtract MSBs with C. R5 + 2
Byte CNT is subtracted from the byte R12 points to. The carry of the previous instruction
is used. 20-bit addresses.
SUBCX.B
&CNT,0(R12)
; Subtract byte CNT from @R12
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4.6.3.34 SWPBX
SWPBX.A
SWPBX.[W]
Syntax
Swap bytes of lower word
Swap bytes of word
SWPBX.A dst
SWPBX dst or
Operation
Description
Status Bits
Mode Bits
Example
MOVX.A
SWPBX.A
Example
SWPBX.W dst
dst.15:8 ↔ dst.7:0
Register mode: Rn.15:8 are swapped with Rn.7:0. When the .A extension is used,
Rn.19:16 are unchanged. When the .W extension is used, Rn.19:16 are cleared.
Other modes: When the .A extension is used, bits 31:20 of the destination address are
cleared, bits 19:16 are left unchanged, and bits 15:8 are swapped with bits 7:0. When
the .W extension is used, bits 15:8 are swapped with bits 7:0 of the addressed word.
Status bits are not affected.
OSCOFF, CPUOFF, and GIE are not affected.
Exchange the bytes of RAM address-word EDE
#23456h,&EDE
EDE
; 23456h -> EDE
; 25634h -> EDE
Exchange the bytes of R5
MOVA
SWPBX.W
#23456h,R5
R5
; 23456h -> R5
; 05634h -> R5
Before SWPBX.A
19
16 15
8
X
7
0
High Byte
Low Byte
After SWPBX.A
19
16
15
8
X
7
0
Low Byte
High Byte
Figure 4-55. Swap Bytes SWPBX.A Register Mode
Before SWPBX.A
31
20 19
16
X
X
After SWPBX.A
31
20 19
0
X
8
15
7
High Byte
16
Low Byte
8
15
Low Byte
0
7
0
High Byte
Figure 4-56. Swap Bytes SWPBX.A In Memory
268
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Before SWPBX
19
16 15
8
X
7
High Byte
0
Low Byte
After SWPBX
19
16
15
8
0
7
Low Byte
0
High Byte
Figure 4-57. Swap Bytes SWPBX[.W] Register Mode
Before SWPBX
15
8
7
High Byte
0
Low Byte
After SWPBX
15
8
Low Byte
7
0
High Byte
Figure 4-58. Swap Bytes SWPBX[.W] In Memory
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4.6.3.35 SXTX
SXTX.A
SXTX.[W]
Syntax
Extend sign of lower byte to address-word
Extend sign of lower byte to word
SXTX.A dst
SXTX dst or
SXTX.W dst
dst.7 → dst.15:8, Rdst.7 → Rdst.19:8 (Register mode)
Register mode: The sign of the low byte of the operand (Rdst.7) is extended into the bits
Rdst.19:8.
Other modes: SXTX.A: the sign of the low byte of the operand (dst.7) is extended into
dst.19:8. The bits dst.31:20 are cleared.
SXTX[.W]: the sign of the low byte of the operand (dst.7) is extended into dst.15:8.
N: Set if result is negative, reset otherwise
Z: Set if result is zero, reset otherwise
C: Set if result is not zero, reset otherwise (C = .not.Z)
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The signed 8-bit data in EDE.7:0 is sign extended to 20 bits: EDE.19:8. Bits 31:20
located in EDE+2 are cleared.
Operation
Description
Status Bits
Mode Bits
Example
SXTX.A
&EDE
; Sign extended EDE -> EDE+2/EDE
SXTX.A Rdst
19
16 15
8 7 6
0
S
SXTX.A dst
31
0
20 19
......
16 15
8 7 6
0
0
S
Figure 4-59. Sign Extend SXTX.A
SXTX[.W] Rdst
19
16 15
8
7
6
0
6
0
S
SXTX[.W] dst
15
8
7
S
Figure 4-60. Sign Extend SXTX[.W]
270
CPUX
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4.6.3.36 TSTX
* TSTX.A
* TSTX.[W]
* TSTX.B
Syntax
Test destination address-word
Test destination word
Test destination byte
TSTX.A dst
TSTX dst or
TSTX.B dst
TSTX.W dst
Operation
dst + 0FFFFFh + 1
dst + 0FFFFh + 1
dst + 0FFh + 1
Emulation
CMPX.A #0,dst
CMPX #0,dst
CMPX.B #0,dst
Description
Status Bits
Mode Bits
Example
LEOPOS
LEONEG
LEOZERO
The destination operand is compared with zero. The status bits are set according to the
result. The destination is not affected.
N: Set if destination is negative, reset if positive
Z: Set if destination contains zero, reset otherwise
C: Set
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
RAM byte LEO is tested; PC is pointing to upper memory. If it is negative, continue at
LEONEG; if it is positive but not zero, continue at LEOPOS.
TSTX.B
JN
JZ
......
......
......
LEO
LEONEG
LEOZERO
;
;
;
;
;
;
Test LEO
LEO is negative
LEO is zero
LEO is positive but not zero
LEO is negative
LEO is zero
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4.6.3.37 XORX
XORX.A
XORX.[W]
XORX.B
Syntax
Exclusive OR source address-word with destination address-word
Exclusive OR source word with destination word
Exclusive OR source byte with destination byte
XORX.A src,dst
XORX src,dst or XORX.W src,dst
XORX.B src,dst
Operation
Description
Status Bits
Mode Bits
Example
XORX.A
Example
XORX.W
Example
XORX.B
INV.B
272
CPUX
src .xor. dst → dst
The source and destination operands are exclusively ORed. The result is placed into
the destination. The source operand is not affected. The previous contents of the
destination are lost. Both operands may be located in the full address space.
N: Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z: Set if result is zero, reset otherwise
C: Set if result is not zero, reset otherwise (carry = .not. Zero)
V: Set if both operands are negative (before execution), reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
Toggle bits in address-word CNTR (20-bit data) with information in address-word TONI
(20-bit address)
TONI,&CNTR
; Toggle bits in CNTR
A table word pointed to by R5 (20-bit address) is used to toggle bits in R6.
@R5,R6
; Toggle bits in R6. R6.19:16 = 0
Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE
(20-bit address)
EDE,R7
R7
; Set different bits to 1 in R7
; Invert low byte of R7. R7.19:8 = 0.
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4.6.4 Address Instructions
MSP430X address instructions are instructions that support 20-bit operands but have restricted
addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode,
except for the MOVA instruction. Restricting the addressing modes removes the need for the additional
extension-word op-code improving code density and execution time. The MSP430X address instructions
are listed and described in the following pages.
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ADDA
ADDA
Syntax
Add 20-bit source to a 20-bit destination register
ADDA Rsrc,Rdst
ADDA #imm20,Rdst
Operation
Description
Status Bits
Mode Bits
Example
ADDA
JC
...
274
CPUX
src + Rdst → Rdst
The 20-bit source operand is added to the 20-bit destination CPU register. The previous
contents of the destination are lost. The source operand is not affected.
N: Set if result is negative (Rdst.19 = 1), reset if positive (Rdst.19 = 0)
Z: Set if result is zero, reset otherwise
C: Set if there is a carry from the 20-bit result, reset otherwise
V: Set if the result of two positive operands is negative, or if the result of two negative
numbers is positive, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs.
#0A4320h,R5
TONI
; Add A4320h to 20-bit R5
; Jump on carry
; No carry occurred
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4.6.4.2
BRA
* BRA
Syntax
Operation
Emulation
Description
Status Bits
Mode Bits
Examples
BRA
BRA
Branch to destination
BRA dst
dst → PC
MOVA dst,PC
An unconditional branch is taken to a 20-bit address anywhere in the full address
space. All seven source addressing modes can be used. The branch instruction is an
address-word instruction. If the destination address is contained in a memory location
X, it is contained in two ascending words: X (LSBs) and (X + 2) (MSBs).
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Examples for all addressing modes are given.
Immediate mode: Branch to label EDE located anywhere in the 20-bit address space or
branch directly to address.
#EDE
#01AA04h
; MOVA
#imm20,PC
Symbolic mode: Branch to the 20-bit address contained in addresses EXEC (LSBs) and
EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within +32 K.
Indirect addressing.
BRA
EXEC
; MOVA
z16(PC),PC
Note: If the 16-bit index is not sufficient, a 20-bit index may be used with the following
instruction.
MOVX.A
EXEC,PC
; 1M byte range with 20-bit index
Absolute mode: Branch to the 20-bit address contained in absolute addresses EXEC
(LSBs) and EXEC+2 (MSBs). Indirect addressing.
BRA
&EXEC
; MOVA
&abs20,PC
Register mode: Branch to the 20-bit address contained in register R5. Indirect R5.
BRA
R5
; MOVA
R5,PC
Indirect mode: Branch to the 20-bit address contained in the word pointed to by register
R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5.
BRA
@R5
; MOVA
@R5,PC
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Indirect, Auto-Increment mode: Branch to the 20-bit address contained in the words
pointed to by register R5 and increment the address in R5 afterwards by 4. The next
time the software flow uses R5 as a pointer, it can alter the program execution due to
access to the next address in the table pointed to by R5. Indirect, indirect R5.
BRA
@R5+
; MOVA
@R5+,PC. R5 + 4
Indexed mode: Branch to the 20-bit address contained in the address pointed to by
register (R5 + X) (for example, a table with addresses starting at X). (R5 + X) points to
the LSBs, (R5 + X + 2) points to the MSBs of the address. X is within R5 + 32 K.
Indirect, indirect (R5 + X).
BRA
X(R5)
; MOVA
z16(R5),PC
Note: If the 16-bit index is not sufficient, a 20-bit index X may be used with the following
instruction:
MOVX.A
276
CPUX
X(R5),PC
; 1M byte range with 20-bit index
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4.6.4.3
CALLA
CALLA
Syntax
Operation
Description
Status Bits
Mode Bits
Examples
CALLA
CALLA
Call a subroutine
CALLA dst
dst → tmp 20-bit dst is evaluated and stored
SP – 2 → SP
PC.19:16 → @SP updated PC with return address to TOS (MSBs)
SP – 2 → SP
PC.15:0 → @SP updated PC to TOS (LSBs)
tmp → PC saved 20-bit dst to PC
A subroutine call is made to a 20-bit address anywhere in the full address space. All
seven source addressing modes can be used. The call instruction is an address-word
instruction. If the destination address is contained in a memory location X, it is
contained in two ascending words, X (LSBs) and (X + 2) (MSBs). Two words on the
stack are needed for the return address. The return is made with the instruction RETA.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Examples for all addressing modes are given.
Immediate mode: Call a subroutine at label EXEC or call directly an address.
#EXEC
#01AA04h
; Start address EXEC
; Start address 01AA04h
Symbolic mode: Call a subroutine at the 20-bit address contained in addresses EXEC
(LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is
within +32 K. Indirect addressing.
CALLA
EXEC
; Start address at @EXEC. z16(PC)
Absolute mode: Call a subroutine at the 20-bit address contained in absolute addresses
EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing.
CALLA
&EXEC
; Start address at @EXEC
Register mode: Call a subroutine at the 20-bit address contained in register R5. Indirect
R5.
CALLA
R5
; Start address at @R5
Indirect mode: Call a subroutine at the 20-bit address contained in the word pointed to
by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5.
CALLA
@R5
; Start address at @R5
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Indirect, Auto-Increment mode: Call a subroutine at the 20-bit address contained in the
words pointed to by register R5 and increment the 20-bit address in R5 afterwards by 4.
The next time the software flow uses R5 as a pointer, it can alter the program execution
due to access to the next word address in the table pointed to by R5. Indirect, indirect
R5.
CALLA
@R5+
; Start address at @R5. R5 + 4
Indexed mode: Call a subroutine at the 20-bit address contained in the address pointed
to by register (R5 + X); for example, a table with addresses starting at X. (R5 + X)
points to the LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5
+ 32 K. Indirect, indirect (R5 + X).
CALLA
278
CPUX
X(R5)
; Start address at @(R5+X). z16(R5)
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4.6.4.4
CLRA
* CLRA
Syntax
Operation
Emulation
Description
Status Bits
Example
CLRA
Clear 20-bit destination register
CLRA Rdst
0 → Rdst
MOVA #0,Rdst
The destination register is cleared.
Status bits are not affected.
The 20-bit value in R10 is cleared.
R10
; 0 -> R10
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CMPA
CMPA
Syntax
Compare the 20-bit source with a 20-bit destination register
CMPA Rsrc,Rdst
CMPA #imm20,Rdst
Operation
Description
Status Bits
Mode Bits
Example
CMPA
JEQ
...
Example
CMPA
JGE
...
280
CPUX
(.not. src) + 1 + Rdst or Rdst – src
The 20-bit source operand is subtracted from the 20-bit destination CPU register. This
is made by adding the 1s complement of the source + 1 to the destination register. The
result affects only the status bits.
N: Set if result is negative (src > dst), reset if positive (src ≤ dst)
Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
C: Set if there is a carry from the MSB, reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source
operand from a negative destination operand delivers a positive result, reset
otherwise (no overflow)
OSCOFF, CPUOFF, and GIE are not affected.
A 20-bit immediate operand and R6 are compared. If they are equal, the program
continues at label EQUAL.
#12345h,R6
EQUAL
; Compare R6 with 12345h
; R6 = 12345h
; Not equal
The 20-bit values in R5 and R6 are compared. If R5 is greater than (signed) or equal to
R6, the program continues at label GRE.
R6,R5
GRE
; Compare R6 with R5 (R5 - R6)
; R5 >= R6
; R5 < R6
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4.6.4.6
DECDA
* DECDA
Syntax
Operation
Emulation
Description
Status Bits
Mode Bits
Example
DECDA
Double-decrement 20-bit destination register
DECDA Rdst
Rdst – 2 → Rdst
SUBA #2,Rdst
The destination register is decremented by two. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if Rdst contained 2, reset otherwise
C: Reset if Rdst contained 0 or 1, set otherwise
V: Set if an arithmetic overflow occurs, otherwise reset
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit value in R5 is decremented by 2.
R5
; Decrement R5 by two
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4.6.4.7
INCDA
* INCDA
Syntax
Operation
Emulation
Description
Status Bits
Mode Bits
Example
INCDA
282
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CPUX
Double-increment 20-bit destination register
INCDA Rdst
Rdst + 2 → Rdst
ADDA #2,Rdst
The destination register is incremented by two. The original contents are lost.
N: Set if result is negative, reset if positive
Z: Set if Rdst contained 0FFFFEh, reset otherwise
Set if Rdst contained 0FFFEh, reset otherwise
Set if Rdst contained 0FEh, reset otherwise
C: Set if Rdst contained 0FFFFEh or 0FFFFFh, reset otherwise
Set if Rdst contained 0FFFEh or 0FFFFh, reset otherwise
Set if Rdst contained 0FEh or 0FFh, reset otherwise
V: Set if Rdst contained 07FFFEh or 07FFFFh, reset otherwise
Set if Rdst contained 07FFEh or 07FFFh, reset otherwise
Set if Rdst contained 07Eh or 07Fh, reset otherwise
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit value in R5 is incremented by two.
R5
; Increment R5 by two
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4.6.4.8
MOVA
MOVA
Syntax
Move the 20-bit source to the 20-bit destination
MOVA Rsrc,Rdst
MOVA
MOVA
MOVA
MOVA
MOVA
MOVA
MOVA
MOVA
Operation
Description
Status Bits
Mode Bits
Examples
MOVA
#imm20,Rdst
z16(Rsrc),Rdst
EDE,Rdst
&abs20,Rdst
@Rsrc,Rdst
@Rsrc+,Rdst
Rsrc,z16(Rdst)
Rsrc,&abs20
src → Rdst
Rsrc → dst
The 20-bit source operand is moved to the 20-bit destination. The source operand is not
affected. The previous content of the destination is lost.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Copy 20-bit value in R9 to R8
R9,R8
; R9 -> R8
Write 20-bit immediate value 12345h to R12
MOVA
#12345h,R12
; 12345h -> R12
Copy 20-bit value addressed by (R9 + 100h) to R8. Source operand in addresses (R9 +
100h) LSBs and (R9 + 102h) MSBs.
MOVA
100h(R9),R8
; Index: + 32 K. 2 words transferred
Move 20-bit value in 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs) to R12
MOVA
&EDE,R12
; &EDE -> R12. 2 words transferred
Move 20-bit value in 20-bit addresses EDE (LSBs) and EDE+2 (MSBs) to R12. PC
index ± 32 K.
MOVA
EDE,R12
; EDE -> R12. 2 words transferred
Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses
@R9 LSBs and @(R9 + 2) MSBs.
MOVA
@R9,R8
; @R9 -> R8. 2 words transferred
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Copy 20-bit value R9 points to (20 bit address) to R8. R9 is incremented by four
afterwards. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs.
MOVA
@R9+,R8
; @R9 -> R8. R9 + 4. 2 words transferred.
Copy 20-bit value in R8 to destination addressed by (R9 + 100h). Destination operand
in addresses @(R9 + 100h) LSBs and @(R9 + 102h) MSBs.
MOVA
R8,100h(R9)
; Index: +- 32 K. 2 words transferred
Move 20-bit value in R13 to 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs)
MOVA
R13,&EDE
; R13 -> EDE. 2 words transferred
Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC
index ± 32 K.
MOVA
284
CPUX
R13,EDE
; R13 -> EDE. 2 words transferred
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4.6.4.9
RETA
* RETA
Syntax
Operation
Return from subroutine
Emulation
Description
MOVA @SP+,PC
Status Bits
Mode Bits
Example
SUBR
RETA
@SP → PC.15:0 LSBs (15:0) of saved PC to PC.15:0
SP + 2 → SP
@SP → PC.19:16 MSBs (19:16) of saved PC to PC.19:16
SP + 2 → SP
The 20-bit return address information, pushed onto the stack by a CALLA instruction, is
restored to the PC. The program continues at the address following the subroutine call.
The SR bits SR.11:0 are not affected. This allows the transfer of information with these
bits.
N: Not affected
Z: Not affected
C: Not affected
V: Not affected
OSCOFF, CPUOFF, and GIE are not affected.
Call a subroutine SUBR from anywhere in the 20-bit address space and return to the
address after the CALLA
CALLA
...
PUSHM.A
...
POPM.A
RETA
#SUBR
#2,R14
#2,R14
;
;
;
;
;
;
Call subroutine starting at SUBR
Return by RETA to here
Save R14 and R13 (20 bit data)
Subroutine code
Restore R13 and R14 (20 bit data)
Return (to full address space)
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4.6.4.10 SUBA
SUBA
Syntax
Subtract 20-bit source from 20-bit destination register
SUBA Rsrc,Rdst
SUBA #imm20,Rdst
Operation
Description
Status Bits
Mode Bits
Example
SUBA
JC
...
286
CPUX
(.not.src) + 1 + Rdst → Rdst or Rdst – src → Rdst
The 20-bit source operand is subtracted from the 20-bit destination register. This is
made by adding the 1s complement of the source + 1 to the destination. The result is
written to the destination register, the source is not affected.
N: Set if result is negative (src > dst), reset if positive (src ≤ dst)
Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
C: Set if there is a carry from the MSB (Rdst.19), reset otherwise
V: Set if the subtraction of a negative source operand from a positive destination
operand delivers a negative result, or if the subtraction of a positive source
operand from a negative destination operand delivers a positive result, reset
otherwise (no overflow)
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at
label TONI.
R5,R6
TONI
; R6 - R5 -> R6
; Carry occurred
; No carry
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4.6.4.11 TSTA
* TSTA
Syntax
Operation
Test 20-bit destination register
Emulation
Description
CMPA #0,Rdst
Status Bits
Mode Bits
Example
R7POS
R7NEG
R7ZERO
TSTA Rdst
dst + 0FFFFFh + 1
dst + 0FFFFh + 1
dst + 0FFh + 1
The destination register is compared with zero. The status bits are set according to the
result. The destination register is not affected.
N: Set if destination register is negative, reset if positive
Z: Set if destination register contains zero, reset otherwise
C: Set
V: Reset
OSCOFF, CPUOFF, and GIE are not affected.
The 20-bit value in R7 is tested. If it is negative, continue at R7NEG; if it is positive but
not zero, continue at R7POS.
TSTA
R7
JN
R7NEG
JZ
R7ZERO
......
......
......
;
;
;
;
;
;
Test R7
R7 is negative
R7 is zero
R7 is positive but not zero
R7 is negative
R7 is zero
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Chapter 5
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Flash Memory Controller
This chapter describes the operation of the flash memory controller.
Topic
5.1
5.2
5.3
5.4
288
...........................................................................................................................
Flash Memory Introduction ...............................................................................
Flash Memory Segmentation .............................................................................
Flash Memory Operation ..................................................................................
FCTL Registers ...............................................................................................
Flash Memory Controller
Page
289
290
292
307
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5.1
Flash Memory Introduction
The flash memory is byte, word, and long-word addressable and programmable. The flash memory
module has an integrated controller that controls programming and erase operations. The module contains
three registers, a timing generator, and a voltage generator to supply program and erase voltages. The
cumulative high-voltage time must not be exceeded, and each 32-bit word can be written not more than
four times (in byte, word, or long word write modes) before another erase cycle (see device-specific data
sheet for details).
The flash memory features include:
• Internal programming voltage generation
• Byte, word (2 bytes), and long (4 bytes) programmable
• Ultralow power operation
• Segment erase, bank erase (device specific), and mass erase
• Marginal 0 and marginal 1 read modes
• Each bank (device specific) can be erased individually while program execution can proceed in a
different flash bank.
NOTE: Bank operations are not supported on all devices. See the device-specific data sheet for
banks supported and their respective sizes.
The block diagram of the flash memory and controller is shown in Figure 5-1.
MAB
MDB
Control Registers Address/Data Latch
Timing
Generator
Flash
Memory
Array
Programming
Voltage
Generator
Figure 5-1. Flash Memory Module Block Diagram
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Flash Memory Segmentation
The flash main memory is partitioned into 512-byte segments. Single bits, bytes, or words can be written
to flash memory, but a segment is the smallest size of the flash memory that can be erased.
The flash memory is partitioned into main and information memory sections. There is no difference in the
operation of the main and information memory sections. Code and data can be located in either section.
The difference between the sections is the segment size.
There are four information memory segments, A through D. Each information memory segment contains
128 bytes and can be erased individually.
The bootstrap loader (BSL) memory consists of four segments, A through D. Each BSL memory segment
contains 512 bytes and can be erased individually.
The main memory segment size is 512 byte. See the device-specific data sheet for the start and end
addresses of each bank, when available, and for the complete memory map of a device.
Figure 5-2 shows the flash segmentation using an example of 256-KB flash that has four banks of 64 KB
(segments A through D) and information memory.
128-byte Information
Memory Segment A
128-byte Information
Memory Segment C
128-byte Information
Memory Segment B
128-byte Information
Memory Segment D
512-byte
BSL Memory A
512-byte
BSL Memory B
512-byte
BSL Memory C
512-byte
BSL Memory D
Segment 0
Segment 0
Segment 0
64-kbyte
Flash Memory
Bank A
64-kbyte
Flash Memory
Bank B
Segment 1
Segment 2
Segment X
64-kbyte
Flash Memory
Bank C
64-kbyte
Flash Memory
Bank D
Segment 125
Segment 126
Segment 127
Figure 5-2. 256-KB Flash Memory Segments Example
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5.2.1 Segment A
Segment A of the information memory is locked separately from all other segments with the LOCKA bit. If
LOCKA = 1, segment A cannot be written or erased, and all information memory is protected from being
segment erased. If LOCKA = 0, segment A can be erased and written like any other flash memory
segment.
The state of the LOCKA bit is toggled when a 1 is written to it. Writing a 0 to LOCKA has no effect. This
allows existing flash programming routines to be used unchanged.
; Unlock Info Memory
MOV
#FWPW,&FCTL4
; Unlock SegmentA
BIT
#LOCKA,&FCTL3
JZ
SEGA_UNLOCKED
MOV
#FWPW+LOCKA,&FCTL3
SEGA_UNLOCKED
; SegmentA is unlocked
; Lock SegmentA
BIT
#LOCKA,&FCTL3
JNZ
SEGA_LOCKED
MOV
#FWPW+LOCKA,&FCTL3
SEGA_LOCKED
; SegmentA is locked
; Lock Info Memory
MOV
#FWPW+LOCKINFO,&FCTL4
; Clear LOCKINFO, if set
;
;
;
;
Test LOCKA
Already unlocked?
No, unlock SegmentA
Yes, continue
;
;
;
;
Test LOCKA
Already locked?
No, lock SegmentA
Yes, continue
; Set LOCKINFO
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Flash Memory Operation
The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased
or written, the flash timing generator and voltage generator are off, and the memory operates identically to
ROM.
Read and fetch while erase – The flash memory allows execution of a program from flash while a
different flash bank is erased. Data reads are also possible from any flash bank not being erased.
NOTE:
Read and fetch while erase
The read and fetch while erase feature is available in flash memory configurations where
more than one flash bank is available. If there is one flash bank available, holding the
complete flash program memory, the read from the program memory and information
memory and BSL memory during the erase is not provided. Table 5-1 summarizes which
flash operations are supported for devices that support read and fetch while erasing.
Table 5-1. Supported Simultaneous Code Execution and Flash Operations
Simultaneous Code Execution
Flash Operation
Within Flash
Within RAM
Bank Erase
Supported
Executed code must not reside in the
bank to be erased
Supported
Segment Erase
Not Supported
Supported
Byte, word, long-word write
Not supported
Supported
Flash memory is in-system programmable (ISP) without the need for additional external voltage. The CPU
can program the flash memory. The flash memory write and erase modes are selected by the BLKWRT,
WRT, MERAS, and ERASE bits and are:
• Byte, word, or long-word (32-bit) write
• Block write
• Segment erase
• Bank erase (only main memory)
• Mass erase (all main memory banks)
• Read during bank erase (except for the one currently read from)
Reading or writing to flash memory while it is busy programming or erasing (page, mass, or bank) from
the same bank is prohibited. Any flash erase or programming can be initiated from within flash memory or
RAM.
5.3.1 Erasing Flash Memory
The logical value of an erased flash memory bit is 1. Each bit can be programmed from 1 to 0 individually,
but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is
one segment. There are three erase modes selected by the ERASE and MERAS bits listed in Table 5-2.
Table 5-2. Erase Modes
(1)
MERAS
ERASE
0
1
Erase Mode
Segment erase
1
0
Bank erase (of one bank) selected by the dummy write address (1)
1
1
Mass erase (all memory banks are erased. Information memory A to D and BSL segments A to D are
not erased)
Bank operations are not supported on all devices. See the device-specific data sheet for support of bank operations.
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5.3.1.1
Erase Cycle
An erase cycle is initiated by a dummy write to the address range of the segment to be erased. The
dummy write starts the erase operation and is required for all erase operations including mass erase.
Figure 5-3 shows the erase cycle timing. The BUSY bit is set immediately after the dummy write and
remains set throughout the erase cycle. BUSY, MERAS, and ERASE are automatically cleared when the
cycle completes. No additional dummy write access should be made while the control bits are cleared,
otherwise, ACCVIFG is set. The mass erase cycle timing is not dependent on the amount of flash memory
present on a device. Erase cycle times are equivalent for all devices.
Generate
Programming Voltage
Erase Operation Active
Remove
Programming Voltage
Erase Time, Current Consumption is Increased
BUSY
tErase = tMass_erase, Segment_erase, Bank_erase
Figure 5-3. Erase Cycle Timing
5.3.1.2
Erasing Main Memory
The main memory consists of one or more banks. Each bank can be erased individually (bank erase). All
main memory banks can be erased in the mass erase mode.
5.3.1.3
Erasing Information Memory or BSL Flash Segments
The information memory A to D and the BSL segments A to D can only be erased in segment erase
mode. They are not erased during a bank erase or a mass erase. Erasing is only possible by first clearing
the LOCKINFO bit.
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Initiating Erase From Flash
An erase cycle can be initiated from within flash memory. During a bank erase, code can be executed
from flash or RAM. The executed code cannot be located in a bank to be erased.
For any segment erase, the CPU is held until the erase cycle completes regardless of the bank the code
resides in. After the segment erase cycle ends, the CPU resumes code execution with the instruction
following the dummy write.
When initiating an erase cycle from within flash memory, it is possible to erase the code needed for
execution after the erase operation. If this occurs, CPU execution is unpredictable after the erase cycle.
The flow to initiate an erase from flash is shown in Figure 5-4.
Disable watchdog
Yes
BUSY = 1
Setup flash controller and
erase mode
Dummy write
Set LOCK = 1, (Set LOCKINFO = 1)
reenable watchdog
Figure 5-4. Erase Cycle From Flash
;
;
;
;
Segment Erase from flash.
Assumes Program Memory. Information memory or BSL
requires LOCKINFO to be cleared as well.
Assumes ACCVIE = NMIIE = OFIE = 0.
MOV
#WDTPW+WDTHOLD,&WDTCTL
; Disable WDT
L1 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L1
; Loop while busy
MOV
#FWPW,&FCTL3
; Clear LOCK
MOV
#FWPW+ERASE,&FCTL1
; Enable segment erase
CLR
&0FC10h
; Dummy write
L2 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L2
; Loop while busy
MOV
#FWPW+LOCK,&FCTL3
; Done, set LOCK
...
; Re-enable WDT?
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5.3.1.5
Initiating Erase From RAM
An erase cycle can be initiated from RAM. In this case, the CPU is not held and continues to execute
code from RAM. The mass erase (all main memory banks) operation is initiated while executing from
RAM. The BUSY bit is used to determine the end of the erase cycle. If the flash is busy completing a bank
erase, flash addresses of a different bank can be used to read data or to fetch instructions. While the flash
is BUSY, starting an erase cycle or a programming cycle causes an access violation, ACCIFG is set to 1,
and the result of the erase operation is unpredictable.
The flow to initiate an erase from flash from RAM is shown in Figure 5-5.
Disable watchdog
Yes
BUSY = 1
Setup flash controller and
erase mode
Dummy write
Yes
BUSY = 1
Set LOCK = 1, (Set LOCKINFO = 1)
Reenable watchdog
Figure 5-5. Erase Cycle From RAM
;
;
;
;
segment Erase from RAM.
Assumes Program Memory. Information memory or BSL
requires LOCKINFO to be cleared as well.
Assumes ACCVIE = NMIIE = OFIE = 0.
MOV
#WDTPW+WDTHOLD,&WDTCTL
; Disable WDT
L1 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L1
; Loop while busy
MOV
#FWPW,&FCTL3
; Clear LOCK
MOV
#FWPW+ERASE,&FCTL1
; Enable page erase
CLR
&0FC10h
; Dummy write
L2 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L2
; Loop while busy
MOV
#FWPW+LOCK,&FCTL3
; Done, set LOCK
...
; Re-enable WDT?
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5.3.2 Writing Flash Memory
The write modes, selected by the WRT and BLKWRT bits, are listed in Table 5-3.
Table 5-3. Write Modes
BLKWRT
WRT
0
1
Write Mode
Byte or word write
1
0
Long-word write
1
1
Long-word block write
The write modes use a sequence of individual write instructions. Using the long-word write mode is
approximately twice as fast as the byte or word mode. Using the long-word block write mode is
approximately four times faster than byte or word mode, because the voltage generator remains on for the
complete block write, and long-words are written in parallel. Any instruction that modifies a destination can
be used to modify a flash location in either byte or word write mode, long-word write mode, or block longword write mode.
The BUSY bit is set while the write operation is active and cleared when the operation completes. If the
write operation is initiated from RAM, the CPU must not access flash while BUSY is set to 1. Otherwise,
an access violation occurs, ACCVIFG is set, and the flash write is unpredictable.
5.3.2.1
Byte or Word Write
A byte or word write operation can be initiated from within flash memory or from RAM. When initiating
from within flash memory, the CPU is held while the write completes. After the write completes, the CPU
resumes code execution with the instruction following the write access. The byte, word, and long-word
write timing is shown in Figure 5-6. Byte, word, and long-word write times are identical.
Generate
Programming Voltage
Programming Operation Active
Remove
Programming Voltage
Programming Time, VCC Current Consumption is Increased
BUSY
tWrite
Figure 5-6. Byte, Word, and Long-Word Write Timing
When a byte or word write is executed from RAM, the CPU continues to execute code from RAM. The
BUSY bit must be zero before the CPU accesses flash again, otherwise an access violation occurs,
ACCVIFG is set, and the write result is unpredictable.
In any write mode, the internally-generated programming voltage is applied to the complete 128-byte
block. The cumulative programming time, tCPT, must not be exceeded for any block. Each byte, word, or
long-word write adds to the cumulative program time of a segment. If the maximum cumulative program
time is reached or exceeded, the segment must be erased. Further programming or using the data returns
unpredictable results (see the device-specific data sheet for specifications).
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5.3.2.2
Initiating Byte or Word Write From Flash
The flow to initiate a byte or word write from flash is shown in Figure 5-7.
Disable watchdog
Setup flash controller
and set WRT = 1
Write byte or word
Set WRT = 0, LOCK = 1,
reenable watchdog
Figure 5-7. Initiating a Byte or Word Write From Flash
; Byte or word write from flash.
; Assumes 0x0FF1E is already erased
; Assumes ACCVIE = NMIIE = OFIE = 0.
MOV
#WDTPW+WDTHOLD,&WDTCTL
;
MOV
#FWPW,&FCTL3
;
MOV
#FWPW+WRT,&FCTL1
;
MOV
#0123h,&0FF1Eh
;
MOV
#FWPW,&FCTL1
;
MOV
#FWPW+LOCK,&FCTL3
;
...
;
Disable WDT
Clear LOCK
Enable write
0123h -> 0x0FF1E
Done. Clear WRT
Set LOCK
Re-enable WDT?
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Initiating Byte or Word Write From RAM
The flow to initiate a byte or word write from RAM is shown in Figure 5-8.
Disable watchdog
Yes
BUSY = 1
Setup flash controller
and set WRT = 1
Write byte or word
Yes
BUSY = 1
Set WRT = 0, LOCK = 1,
Reenable watchdog
Figure 5-8. Initiating a Byte or Word Write From RAM
; Byte or
; Assumes
; Assumes
MOV
L1 BIT
JNZ
MOV
MOV
MOV
L2 BIT
JNZ
MOV
MOV
...
298
word write from RAM.
0x0FF1E is already erased
ACCVIE = NMIIE = OFIE = 0.
#WDTPW+WDTHOLD,&WDTCTL
#BUSY,&FCTL3
L1
#FWPW,&FCTL3
#FWPW+WRT,&FCTL1
#0123h,&0FF1Eh
#BUSY,&FCTL3
L2
#FWPW,&FCTL1
#FWPW+LOCK,&FCTL3
Flash Memory Controller
;
;
;
;
;
;
;
;
;
;
;
Disable WDT
Test BUSY
Loop while busy
Clear LOCK
Enable write
0123h -> 0x0FF1E
Test BUSY
Loop while busy
Clear WRT
Set LOCK
Re-enable WDT?
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5.3.2.4
Long-Word Write
A long-word write operation can be initiated from within flash memory or from RAM. The BUSY bit is set to
1 after 32 bits are written to the flash controller and the programming cycle starts. When initiating from
within flash memory, the CPU is held while the write completes. After the write completes, the CPU
resumes code execution with the instruction following the write access. The long-word write timing is
shown in Figure 5-6.
A long-word consists of four consecutive bytes aligned to at 32-bit address (only the lower two address
bits are different). The bytes can be written in any order or any combination of bytes and words. If a byte
or word is written more than once, the last data written to the four bytes are stored into the flash memory.
If a write to a flash address outside of the 32-bit address happens before all four bytes are available, the
data written so far is discarded, and the latest byte or word written defines the new 32-bit aligned address.
When 32 bits are available, the write cycle is executed. When executing from RAM, the CPU continues to
execute code. The BUSY bit must be zero before the CPU accesses flash again, otherwise an access
violation occurs, ACCVIFG is set, and the write result is unpredictable.
In long-word write mode, the internally-generated programming voltage is applied to a complete 128-byte
block. The cumulative programming time, tCPT, must not be exceeded for any block. Each write adds to the
cumulative program time of a segment. If the maximum cumulative program time is reached or exceeded,
the segment must be erased. Further programming or using the data returns unpredictable results.
With each write, the amount of time the block is subjected to the programming voltage accumulates. If the
cumulative programming time is reached or exceeded, the block must be erased before further
programming or use (see the device-specific data sheet for specifications).
5.3.2.5
Initiating Long-Word Write From Flash
The flow to initiate a long-word write from flash is shown in Figure 5-9.
Disable watchdog
Setup flash controller
and set BLKWRT = 1
Write 4 bytes or 2 words
Set BLKWRT = 0, LOCK = 1,
Reenable watchdog
Figure 5-9. Initiating Long-Word Write From Flash
; Long-word write from flash.
; Assumes 0x0FF1C and 0x0FF1E is already erased
; Assumes ACCVIE = NMIIE = OFIE = 0.
MOV
#WDTPW+WDTHOLD,&WDTCTL
; Disable WDT
MOV
#FWPW,&FCTL3
; Clear LOCK
MOV
#FWPW+BLKWRT,&FCTL1
; Enable 2-word write
MOV
#0123h,&0FF1Ch
; 0123h -> 0x0FF1C
MOV
#45676h,&0FF1Eh
; 04567h -> 0x0FF1E
MOV
#FWPW,&FCTL1
; Done. Clear BLKWRT
MOV
#FWPW+LOCK,&FCTL3
; Set LOCK
...
; Re-enable WDT?
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Initiating Long-Word Write From RAM
The flow to initiate a long-word write from RAM is shown in Figure 5-10.
Disable watchdog
Yes
BUSY = 1
Setup flash controller
and set BLKWRT = 1
Write 4 bytes or 2 words
Yes
BUSY = 1
Set BLKWRT=0, LOCK = 1,
Reenable watchdog
Figure 5-10. Initiating Long-Word Write from RAM
; Two 16-bit word writes from RAM.
; Assumes 0x0FF1C and 0x0FF1E is already erased
; Assumes ACCVIE = NMIIE = OFIE = 0.
MOV
#WDTPW+WDTHOLD,&WDTCTL
; Disable WDT
L1 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L1
; Loop while busy
MOV
#FWPW,&FCTL3
; Clear LOCK
MOV
#FWPW+BLKWRT,&FCTL1
; Enable write
MOV
#0123h,&0FF1Ch
; 0123h -> 0x0FF1C
MOV
#4567h,&0FF1Eh
; 4567h -> 0x0FF1E
L2 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L2
; Loop while busy
MOV
#FWPW,&FCTL1
; Clear WRT
MOV
#FWPW+LOCK,&FCTL3
; Set LOCK
...
; Re-enable WDT?
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5.3.2.7
Block Write
The block write can be used to accelerate the flash write process when many sequential bytes or words
need to be programmed. The flash programming voltage remains on for the duration of writing the 128byte row. The cumulative programming time, tCPT, must not be exceeded for any row during a block write.
Only long-word writes are possible using block write mode.
A block write cannot be initiated from within flash memory. The block write must be initiated from RAM.
The BUSY bit remains set throughout the duration of the block write. The WAIT bit must be checked
between writing four bytes, or two words, to the block. When WAIT is set, then four bytes, or two 16-bit
words, of the block can be written. When writing successive blocks, the BLKWRT bit must be cleared after
the current block is completed. BLKWRT can be set initiating the next block write after the required flash
recovery time given by tEND. BUSY is cleared following each block write completion, indicating the next
block can be written. Figure 5-11 shows the block write timing. The first long-word write requires tBlock,0 and
the last long-write requires tBlock,N. All other blocks require tBlock,1-(N-1).
BLKWRT bit
Write to Flash; e.g., MOV #0123h, &Flash
MOV #4567h, &Flash1
Remove
Programming Voltage
Programming Operation Active
Generate
Programming Voltage
Cumulative Programming Time < tCPT, VCC Current Consumption is Increased
BUSY
tBlock,0
tBlock,1–(N-1)
tBlock,N
WAIT
Figure 5-11. Block-Write Cycle Timing
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Block Write Flow and Example
A block write flow is shown in Figure 5-12 and the following code example.
Disable watchdog
Yes
BUSY = 1
Setup flash controller
Set BLKWRT = WRT = 1
Write 4 bytes or 2 words
Yes
WAIT = 0?
No
Block Border?
Set BLKWRT=0
Yes
BUSY = 1
Yes
Another
Block?
Set WRT = 0, LOCK = 1,
Reenable WDT
Figure 5-12. Block Write Flow
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; Write one block starting at 0F000h.
; Must be executed from RAM, Assumes Flash is already erased.
; Assumes ACCVIE = NMIIE = OFIE = 0.
MOV
#32,R5
; Use as write counter
MOV
#0F000h,R6
; Write pointer
MOV
#WDTPW+WDTHOLD,&WDTCTL
; Disable WDT
L1 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L1
; Loop while busy
MOV
#FWPW,&FCTL3
; Clear LOCK
MOV
#FWPW+BLKWRT+WRT,&FCTL1
; Enable block write
L2 MOV
Write_Value1,0(R6)
; Write 1st location
MOV
Write_Value2,2(R6)
; Write 2nd word
L3 BIT
#WAIT,&FCTL3
; Test WAIT
JZ
L3
; Loop while WAIT=0
INCD
R6
; Point to next words
INCD
R6
; Point to next words
DEC
R5
; Decrement write counter
JNZ
L2
; End of block?
MOV
#FWPW,&FCTL1
; Clear WRT, BLKWRT
L4 BIT
#BUSY,&FCTL3
; Test BUSY
JNZ
L4
; Loop while busy
MOV
#FWPW+LOCK,&FCTL3
; Set LOCK
...
; Re-enable WDT if needed
5.3.3 Flash Memory Access During Write or Erase
When a write or an erase operation is initiated from RAM while BUSY = 1, the CPU may not write to any
flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable.
ACCVIFG is also set if a Flash write or erase access is attempted without any Flash write or erase mode
selected first.
When a write operation is initiated from within flash memory, the CPU continues code execution with the
next instruction fetch after the write cycle completed (BUSY = 0).
The op-code 3FFFh is the JMP PC instruction. This causes the CPU to loop until the flash operation is
finished. When the operation is finished and BUSY = 0, the flash controller allows the CPU to fetch the opcode and program execution resumes.
The flash access conditions while BUSY = 1 are listed in Table 5-4.
Table 5-4. Flash Access While Flash is Busy (BUSY = 1)
Flash Operation
Bank erase
Segment erase
Word or byte write
or long-word write
Block write
Flash Access
WAIT
Read
0
Result
From the erased bank: ACCVIFG = 0. 03FFFh is the value read.
From any other flash location: ACCVIFG = 0. Valid read.
Write
0
ACCVIFG = 1. Write is ignored.
Instruction fetch
0
From the erased bank: ACCVIFG = 0. CPU fetches 03FFFh. This is the
JMP PC instruction.
From any other flash location: ACCVIFG = 0. Valid instruction fetch.
Read
0
ACCVIFG = 0: 03FFFh is the value read.
Write
0
ACCVIFG = 1: Write is ignored.
Instruction fetch
0
ACCVIFG = 0: CPU fetches 03FFFh. This is the JMP PC instruction.
Read
0
ACCVIFG = 0: 03FFFh is the value read.
Write
0
ACCVIFG = 1: Write is ignored.
Instruction fetch
0
ACCVIFG = 0: CPU fetches 03FFFh. This is the JMP PC instruction.
Any
0
ACCVIFG = 1: LOCK = 1, block write is exited.
Read
1
ACCVIFG = 0: 03FFFh is the value read.
Write
1
ACCVIFG = 0: Valid write
Instruction fetch
1
ACCVIFG = 1: LOCK = 1, block write is exited
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Interrupts are automatically disabled during any flash operation.
The watchdog timer (in watchdog mode) should be disabled before a flash erase cycle. A reset aborts the
erase and the result is unpredictable. After the erase cycle has completed, the watchdog may be
reenabled.
5.3.4 Stopping Write or Erase Cycle
Any write or erase operation can be stopped before its normal completion by setting the emergency exit
bit EMEX. Setting the EMEX bit stops the active operation and resets the flash controller. All flash
operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset. The LOCK
bit of FCTL3 is set. The result of the intended operation is unpredictable.
5.3.4.1
EMEX With Single Bank Flash Memory
For devices with single bank flash memories, write and erase operations initiated from flash, the CPU is
held until the flash operation completes. Therefore it is not possible to perform an emergency exit by the
EMEX bit. The emergency exit of write or erase operations initiated from RAM can be performed using the
EMEX bit. The BUSY bit is used to determine the end of the emergency exit cycle. The user must ensure
that code execution does not continue until the BUSY bit is cleared by the flash controller.
5.3.4.2
EMEX With Multiple Bank Flash Memory
For devices with multiple bank flash memories, write and segment erase operations initiated from flash,
regardless of which bank the code resides in, the CPU is held until the flash operation completes.
Therefore it is not possible to perform an emergency exit by the EMEX bit. For bank erase, there is a
possibility to perform an EMEX if the bank being erased is not where the code resides. The BUSY bit is
used to determine the end of the emergency exit cycle. The user must ensure that code execution does
not continue until the BUSY bit is cleared by the flash controller.
The emergency exit of write or any erase operations initiated from RAM can be performed using the
EMEX bit. The BUSY bit is used to determine the end of the emergency exit cycle. The user must ensure
that code execution does not continue until the BUSY bit is cleared by the flash controller.
5.3.5 Checking Flash Memory
The result of a programming cycle of the flash memory can be checked by calculating and storing a
checksum (CRC) of parts or the complete flash memory content. The CRC module can be used for this
purpose (see the device-specific data sheet). During the runtime of the system, the known checksums can
be recalculated and compared with the expected values stored in the flash memory. The program
checking the flash memory content is executed in RAM.
To get an early indication of weak memory cells, reading the flash can be done in combination with the
device-specific marginal read modes. The marginal read modes are controlled by the FCTL4.MRG0 and
FCTL4.MRG1 register bits if available (device specific). During marginal read mode, marginally
programmed flash memory bit locations can be detected. One method for identifying such memory
locations would be to periodically perform a checksum calculation over a section of flash memory (for
example, a flash segment) and repeating this procedure with the marginal read mode enabled. If they do
not match, it could indicate an insufficiently programmed flash memory location. It is possible to refresh
the affected Flash memory segment by disabling marginal read mode, copying to RAM, erasing the flash
segment, and writing back to it from RAM.
The program checking the flash memory contents must be executed from RAM. Executing code from flash
automatically disables the marginal read mode. The marginal read modes are controlled by the MRG0 and
MRG1 register bits. Setting MRG1 is used to detect insufficiently programmed flash cells containing a "1"
(erased bits). Setting MRG0 is used to detect insufficiently programmed flash cells containing a "0"
(programmed bits). Only one of these bits should be set at a time. Therefore, a full marginal read check
requires two passes of checking the flash memory content’s integrity. During marginal read mode, the
flash access speed (MCLK) must be limited to 1 MHz (see the device-specific data sheet).
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5.3.6 Configuring and Accessing the Flash Memory Controller
The FCTLx registers are 16-bit password-protected read and write registers. Any read or write access
must use word instructions, and write accesses must include the write password 0A5h in the upper byte.
Any write to any FCTLx register with a value other than 0A5h in the upper byte is a password violation,
sets the KEYV flag, and triggers a PUC system reset. Any read of any FCTLx registers reads 096h in the
upper byte.
Any write to FCTL1 during an erase or byte, word, double-word write operation is an access violation and
sets ACCVIFG. Writing to FCTL1 is allowed in block write mode when WAIT = 1, but writing to FCTL1 in
block write mode when WAIT = 0 is an access violation and sets ACCVIFG.
Any write to FCTL2 (this register is currently not implemented) when BUSY = 1 is an access violation.
Any FCTLx register may be read when BUSY = 1. A read does not cause an access violation.
5.3.7 Flash Memory Controller Interrupts
The flash controller has two interrupt sources, KEYV and ACCVIFG. ACCVIFG is set when an access
violation occurs. When the ACCVIE bit is reenabled after a flash write or erase, a set ACCVIFG flag
generates an interrupt request. The ACCVIE bit resides in the Special Function Register, SFRIE1 (see the
SYS chapter for details). ACCVIFG sources the NMI interrupt vector, so it is not necessary for GIE to be
set for ACCVIFG to request an interrupt. ACCVIFG may also be checked by software to determine if an
access violation occurred. ACCVIFG must be reset by software.
The password violation flag, KEYV, is set when any of the flash control registers are written with an
incorrect password. When this occurs, a PUC is generated immediately, resetting the device.
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5.3.8 Programming Flash Memory Devices
There are three options for programming a flash device. All options support in-system programming.
• Program via JTAG
• Program via the BSL
• Program via a custom solution
5.3.8.1
Programming Flash Memory Via JTAG
Devices can be programmed via the JTAG port. The JTAG interface requires four signals (five signals on
20- and 28-pin devices), ground, and optionally VCC and RST/NMI.
The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not
reversible. Further access to the device via JTAG is not possible For more details, see the MSP430
Programming Via the JTAG Interface User's Guide (SLAU320).
5.3.8.2
Programming Flash Memory Via Bootstrap Loader (BSL)
Every flash device contains a BSL. The BSL enables users to read or program the flash memory or RAM
using a UART serial interface. Access to the flash memory via the BSL is protected by a 256-bit userdefined password. For more details, see the MSP430 Programming Via the Bootstrap Loader User's
Guide (SLAU319).
5.3.8.3
Programming Flash Memory Via Custom Solution
The ability of the MSP430 CPU to write to its own flash memory allows for in-system and external custom
programming solutions as shown in Figure 5-13. The user can choose to provide data through any means
available (for example, UART or SPI). User-developed software can receive the data and program the
flash memory. Because this type of solution is developed by the user, it can be completely customized to
fit the application needs for programming, erasing, or updating the flash memory.
Commands, data, etc.
Host
MSP430
UART,
Px.x,
SPI,
etc.
Flash memory
CPU executes
user software
Read/write flash memory
Figure 5-13. User-Developed Programming Solution
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5.4
FCTL Registers
The flash memory controller (FCTL) registers are listed in Table 5-5. The base address can be found in
the device-specific data sheet. The address offset is given in Table 5-5.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 5-5. FCTL Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
FCTL1
Flash Memory Control 1
Section 5.4.1
Read/write
Word
9600h
00h
FCTL1_L
Read/Write
Byte
00h
01h
FCTL1_H
Read/Write
Byte
96h
Read/write
Word
9658h
Read/Write
Byte
58h
Read/Write
Byte
96h
Read/write
Word
9600h
04h
FCTL3
04h
FCTL3_L
05h
FCTL3_H
06h
FCTL4
Flash Memory Control 3
Flash Memory Control 4
06h
FCTL4_L
Read/Write
Byte
00h
07h
FCTL4_H
Read/Write
Byte
96h
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Section 5.4.3
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5.4.1 FCTL1 Register
Flash Memory Control 1 Register
Figure 5-14. FCTL1 Register
15
14
13
12
11
10
9
8
FRPW/FWPW
7
6
5
BLKWRT
WRT
SWRT
4
rw-0
rw-0
rw-0
3
Reserved
r-0
r-0
2
1
0
MERAS
ERASE
Reserved
rw-0
rw-0
r-0
Table 5-6. FCTL1 Register Description
Bit
Field
Type
Reset
Description
15-8
FRPW/FWPW
RW
96h
FCTL password. Always read as 096h. Must be written as 0A5h or a PUC is
generated.
7
BLKWRT
RW
0h
Block write. BLKWRT and WRT are used together to select the write mode.
The values shown below are for BLKWRT-WRT.
0-0 = Reserved
0-1 = Byte or word write
1-0 = Long-word write
1-1 = Long-word block write
6
WRT
RW
0h
Write. BLKWRT and WRT are used together to select the write mode.
The values shown below are for BLKWRT-WRT.
0-0 = Reserved
0-1 = Byte or word write
1-0 = Long-word write
1-1 = Long-word block write
5
SWRT
RW
0h
Smart write. If this bit is set, the program time is shortened. The programming
quality has to be checked by marginal read modes.
4-3
Reserved
R
0h
Reserved. Always reads as 0.
2
MERAS
Mass erase. MERAS and ERASE are used together to select the erase mode.
MERAS and ERASE are automatically reset when EMEX is set or a flash erase
operation has completed.
The values shown below are for MERAS-ERASE.
0-0 = No erase
0-1 = Segment erase
1-0 = Bank erase (erase of one bank)
1-1 = Mass erase (erase all flash memory banks)
1
ERASE
Erase. MERAS and ERASE are used together to select the erase mode. MERAS
and ERASE are automatically reset when EMEX is set or a flash erase operation
has completed.
The values shown below are for MERAS-ERASE.
0-0 = No erase
0-1 = Segment erase
1-0 = Bank erase (erase of one bank)
1-1 = Mass erase (erase all flash memory banks)
0
Reserved
308
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R
0h
Reserved. Always reads as 0.
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5.4.2 FCTL3 Register
Flash Memory Control 3 Register
Figure 5-15. FCTL3 Register
15
14
13
12
11
10
9
8
FRPW/FWPW
7
6
5
4
3
2
1
0
Reserved
LOCKA
EMEX
LOCK
WAIT
ACCVIFG
KEYV
BUSY
r-0
rw-1
rw-0
rw-1
r-1
rw-0
rw-(0)
rw-0
Table 5-7. FCTL3 Register Description
Bit
Field
Type
Reset
Description
15-8
FRPW/FWPW
RW
96h
FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC is
generated.
7
Reserved
R
0h
Reserved. Always reads as 0.
6
LOCKA
RW
1h
Segment A lock. Write a 1 to this bit to change its state. Writing 0 has no effect.
0b = Segment A of the information memory is unlocked and can be written or
erased in segment erase mode.
1b = Segment A of the information memory is locked and can not be written or
erased in segment erase mode.
5
EMEX
RW
0h
Emergency exit. Setting this bit stops any erase or write operation. The LOCK bit
is set.
0b = No emergency exit
1b = Emergency exit
4
LOCK
RW
1h
Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit can
be set any time during a byte or word write or erase operation, and the operation
completes normally. In the block write mode, if the LOCK bit is set while
BLKWRT = WAIT = 1, BLKWRT and WAIT are reset and the mode ends
normally.
0b = Unlocked
1b = Locked
3
WAIT
R
1h
Wait. Indicates the flash memory is being written to.
0b = Flash memory is not ready for the next byte or word write.
1b = Flash memory is ready for the next byte or word write.
2
ACCVIFG
RW
0h
Access violation interrupt flag
0b = No interrupt pending
1b = Interrupt pending
1
KEYV
RW
0h
Flash password violation. This bit indicates an incorrect FCTLx password was
written to any flash control register and generates a PUC when set. KEYV must
be reset with software.
0b = FCTLx password was written correctly.
1b = FCTLx password was written incorrectly.
0
BUSY
RW
0h
Busy. This bit indicates if the flash is currently busy erasing or programming.
0b = Not busy
1b = Busy
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5.4.3 FCTL4 Register
Flash Memory Control 4 Register
Figure 5-16. FCTL4 Register
15
14
13
12
11
10
9
2
1
8
FRPW/FWPW
7
6
5
4
LOCKINFO
Reserved
MRG1
MRG0
rw-0
r-0
rw-0
rw-0
3
Reserved
r-0
r-0
0
VPE
r-0
rw-0
Table 5-8. FCTL4 Register Description
Bit
Field
Type
Reset
Description
15-8
FRPW/FWPW
RW
96h
FCTLx password. Always reads as 096h. Must be written as 0A5h or a PUC is
generated.
7
LOCKINFO
RW
0h
Lock information memory. If set, the information memory cannot be erased in
segment erase mode and cannot be written to.
6
Reserved
R
0h
Reserved. Always reads as 0.
5
MRG1
RW
0h
Marginal read 1 mode. This bit enables the marginal 1 read mode. The marginal
read 1 bit is valid for reads from the flash memory only. During a fetch cycle, the
marginal mode is turned off automatically. If both MRG1 and MRG0 are set,
MRG1 is active and MRG0 is ignored.
0b = Marginal 1 read mode is disabled.
1b = Marginal 1 read mode is enabled.
4
MRG0
RW
0h
Marginal read 0 mode. This bit enables the marginal 0 read mode. The marginal
read 1 bit is valid for reads from the flash memory only. During a fetch cycle, the
marginal mode is turned off automatically. If both MRG1 and MRG0 are set,
MRG1 is active and MRG0 is ignored.
0b = Marginal 0 read mode is disabled.
1b = Marginal 0 read mode is enabled.
3-1
Reserved
R
0h
Reserved. Always reads as 0.
0
VPE
RW
0h
Voltage changed during program error. This bit is set by hardware and can only
be cleared by software. If DVCC changed significantly during programming, this
bit is set to indicate an invalid result. The ACCVIFG bit is set if VPE is set.
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5.4.4 SFRIE1 Register
Interrupt Enable 1 Register
Figure 5-17. SFRIE1 Register
15
14
13
12
11
10
9
8
5
4
3
2
1
0
OTHER
7
6
ACCVIE
rw-0
Table 5-9. SFRIE1 Register Description
Bit
Field
Type
Reset
15-6
5
Description
These bits may be used by other modules (see the device-specific data sheet
and the SYS chapter for details).
ACCVIE
RW
0h
Flash memory access violation interrupt enable. This bit enables the ACCVIFG
interrupt. Because other bits in SFRIE1 may be used for other modules, it is
recommended to set or clear this bit using BIS or BIC instructions, rather than
MOV or CLR instructions. See the SYS chapter for more details.
0b = Interrupt not enabled
1b = Interrupt enabled
4-0
These bits may be used by other modules (see the device-specific data sheet
and the SYS chapter for details).
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Chapter 6
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RAM Controller (RAMCTL)
The RAM controller (RAMCTL) allows control of the operation of the RAM.
Topic
6.1
6.2
6.3
312
...........................................................................................................................
Page
RAM Controller (RAMCTL) Introduction .............................................................. 313
RAMCTL Operation .......................................................................................... 313
RAMCTL Registers .......................................................................................... 314
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6.1
RAM Controller (RAMCTL) Introduction
The RAMCTL provides access to the different power modes of the RAM. The RAMCTL allows the ability
to reduce the leakage current while the CPU is off. The RAM can also be switched off. In retention mode,
the RAM content is saved while the RAM content is lost in off mode. The RAM is partitioned in sectors,
typically of 4KB (sector) size. See the device-specific data sheet for actual block allocation and size. Each
sector is controlled by the RAM controller RAM Sector Off control bit (RCRSyOFF) of the RAMCTL
Control 0 register (RCCTL0). The RCCTL0 register is protected with a key. Only if the correct key is
written during a word write, the RCCTL0 register content can be modified. Byte write accesses or write
accesses with a wrong key are ignored.
6.2
RAMCTL Operation
Active mode
In active mode, the RAM can be read and written at any time. If a RAM address of a sector must hold
data, the whole sector cannot be switched off.
Low-power modes
In all low-power modes, the CPU is switched off. As soon as the CPU is switched off, the RAM enters
retention mode to reduce the leakage current.
RAM off mode
Each sector can be turned off independently of each other by setting the respective RCRSyOFF bit to
1. Reading from a switched off RAM sector returns 0 as data. All data previously stored into a switched
off RAM sector is lost and cannot be read, even if the sector is turned on again.
Stack pointer
The program stack is located in RAM. Sectors holding the stack must not be turned off if an interrupt
has to be executed, or a low-power mode is entered.
USB buffer memory
On devices with USB, the USB buffer memory is located in RAM. Sector 7 is used for this purpose.
RCRS7OFF can be set to switch off this memory if it is not required for USB operation or is not being
utilized in normal operation.
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RAMCTL Registers
The RAMCTL module register is listed in Table 6-1. The base address can be found in the device-specific
data sheet. The address offset is given in Table 6-1.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 6-1. RAMCTL Registers
314
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
RCCTL0
RAM Controller Control 0
Section 6.3.1
Read/write
Word
6900h
00h
RCCTL0_L
Read/write
Byte
00h
01h
RCCTL0_H
Read/write
Byte
69h
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6.3.1 RCCTL0 Register
RAM Controller Control 0 Register
Figure 6-1. RCCTL0 Register
15
14
13
12
rw-0
rw-1
rw-1
rw-0
11
10
9
8
rw-1
rw-0
rw-0
rw-1
RCKEY
7
6
5
4
3
2
1
0
RCRS7OFF
RCRS6OFF
RCRS5OFF
RCRS4OFF
RCRS3OFF
RCRS2OFF
RCRS1OFF
RCRS0OFF
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
Table 6-2. RCCTL0 Register Description
Bit
Field
Type
Reset
Description
15-8
RCKEY
RW
69h
RAM controller key. Always read as 69h. Must be written as 5Ah, otherwise the
RAMCTL write is ignored.
7
RCRS7OFF
RW
0h
RAM controller RAM sector 7 off. Setting the bit to 1 turns off the RAM sector 7.
All data of the RAM sector 7 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
6
RCRS6OFF
RW
0h
RAM controller RAM sector 6 off. Setting the bit to 1 turns off the RAM sector 6.
All data of the RAM sector 6 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
5
RCRS5OFF
RW
0h
RAM controller RAM sector 5 off. Setting the bit to 1 turns off the RAM sector 5.
All data of the RAM sector 5 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
4
RCRS4OFF
RW
0h
RAM controller RAM sector 4 off. Setting the bit to 1 turns off the RAM sector 4.
All data of the RAM sector 4 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
3
RCRS3OFF
RW
0h
RAM controller RAM sector 3 off. Setting the bit to 1 turns off the RAM sector 3.
All data of the RAM sector 3 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
2
RCRS2OFF
RW
0h
RAM controller RAM sector 2 off. Setting the bit to 1 turns off the RAM sector 2.
All data of the RAM sector 2 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
1
RCRS1OFF
RW
0h
RAM controller RAM sector 1 off. Setting the bit to 1 turns off the RAM sector 1.
All data of the RAM sector 1 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
0
RCRS0OFF
RW
0h
RAM controller RAM sector 0 off. Setting the bit to 1 turns off the RAM sector 0.
All data of the RAM sector 0 is lost. See the device-specific data sheet to find the
the number of RAM sectors available along with their respective address ranges
and sizes.
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Chapter 7
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Direct Memory Access (DMA) Controller Module
The direct memory access (DMA) controller module transfers data from one address to another without
CPU intervention. This chapter describes the operation of the DMA controller.
Topic
7.1
7.2
7.3
316
...........................................................................................................................
Page
Direct Memory Access (DMA) Introduction ......................................................... 317
DMA Operation ................................................................................................ 319
DMA Registers ................................................................................................ 330
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7.1
Direct Memory Access (DMA) Introduction
The DMA controller transfers data from one address to another, without CPU intervention, across the
entire address range. For example, the DMA controller can move data from the ADC conversion memory
to RAM.
Devices that contain a DMA controller may have up to eight DMA channels available. Therefore,
depending on the number of DMA channels available, some features described in this chapter are not
applicable to all devices. See the device-specific data sheet for number of channels supported.
Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system
power consumption by allowing the CPU to remain in a low-power mode, without having to awaken to
move data to or from a peripheral.
DMA controller features include:
• Up to eight independent transfer channels
• Configurable DMA channel priorities
• Requires only two MCLK clock cycles per transfer
• Byte or word and mixed byte/word transfer capability
• Block sizes up to 65535 bytes or words
• Configurable transfer trigger selections
• Selectable-edge or level-triggered transfer
• Four addressing modes
• Single, block, or burst-block transfer modes
The DMA controller block diagram is shown in Figure 7-1.
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JTAG Active
DMA0TSEL
ROUNDROBIN
DMADT
5
DMA0TRIG0
DMA0TRIG1
NMI Interrupt Request
ENNMI
Halt
00000
00001
2
DMADSTINCR
DMADSTBYTE
3
DMA Channel 0
DMA0SA
DMA0DA
DMA0SZ
DMA0TRIG31
11111
2
DMA1TSEL
5
DMA1TRIG0
DMA1TRIG1
00000
00001
DMA Priority and Control
to USB
if available
DMADT
2
Address
Space
DMA1DA
DMA1SZ
to USB
if available
2
5
DMAnTRIG0
DMAnTRIG1
3
DMA1SA
11111
DMAnTSEL
DMADSTINCR
DMADSTBYTE
DMA Channel1
2
DMA1TRIG31
DMASRSBYTE
DMASRCINCR
DMAEN
DMASRSBYTE
DMASRCINCR
DMAEN
DMADSTINCR
DMADSTBYTE
DMADT
3
DMA Channel n
DMAnSA
00000
00001
DMAnDA
DMAnSZ
2
DMAnTRIG31
DMASRSBYTE
DMASRCINCR
DMAEN
DMARMWDIS
11111
Halt CPU
to USB
if available
Figure 7-1. DMA Controller Block Diagram
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7.2
DMA Operation
The DMA controller is configured with user software. The setup and operation of the DMA is discussed in
the following sections.
7.2.1 DMA Addressing Modes
The DMA controller has four addressing modes. The addressing mode for each DMA channel is
independently configurable. For example, channel 0 may transfer between two fixed addresses, while
channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 7-2.
The addressing modes are:
• Fixed address to fixed address
• Fixed address to block of addresses
• Block of addresses to fixed address
• Block of addresses to block of addresses
The addressing modes are configured with the DMASRCINCR and DMADSTINCR control bits. The
DMASRCINCR bits select if the source address is incremented, decremented, or unchanged after each
transfer. The DMADSTINCR bits select if the destination address is incremented, decremented, or
unchanged after each transfer.
Transfers may be byte to byte, word to word, byte to word, or word to byte. When transferring word to
byte, only the lower byte of the source-word transfers. When transferring byte to word, the upper byte of
the destination-word is cleared when the transfer occurs.
DMA
Controller
Address Space
Fixed Address To Fixed Address
DMA
Controller
Address Space
Block Of Addresses To Fixed Address
DMA
Controller
Address Space
Fixed Address To Block Of Addresses
DMA
Controller
Address Space
Block Of Addresses To Block Of Addresses
Figure 7-2. DMA Addressing Modes
7.2.2 DMA Transfer Modes
The DMA controller has six transfer modes selected by the DMADT bits as listed in Table 7-1. Each
channel is individually configurable for its transfer mode. For example, channel 0 may be configured in
single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates
in repeated block mode. The transfer mode is configured independently from the addressing mode. Any
addressing mode can be used with any transfer mode.
Two types of data can be transferred selectable by the DMAxCTL DSTBYTE and SRCBYTE fields. The
source and/or destination location can be either byte or word data. It is also possible to transfer byte to
byte, word to word, or any combination.
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Table 7-1. DMA Transfer Modes
DMADT
Transfer Mode
Description
000
Single transfer
Each transfer requires a trigger. DMAEN is automatically cleared when DMAxSZ
transfers have been made.
001
Block transfer
A complete block is transferred with one trigger. DMAEN is automatically cleared at
the end of the block transfer.
Burst-block transfer
CPU activity is interleaved with a block transfer. DMAEN is automatically cleared at
the end of the burst-block transfer.
100
Repeated single transfer
Each transfer requires a trigger. DMAEN remains enabled.
101
Repeated block transfer
A complete block is transferred with one trigger. DMAEN remains enabled.
Repeated burst-block
transfer
CPU activity is interleaved with a block transfer. DMAEN remains enabled.
010, 011
110, 111
7.2.2.1
Single Transfer
In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state
diagram is shown in Figure 7-3.
The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCR and
DMASRCINCR bits select if the destination address and the source address are incremented or
decremented after each transfer. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer. The DMAxSZ
register is decremented after each transfer. When the DMAxSZ register decrements to zero, it is reloaded
from its temporary register and the corresponding DMAIFG flag is set. When DMADT = {0}, the DMAEN
bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer
to occur.
In repeated single transfer mode, the DMA controller remains enabled with DMAEN = 1, and a transfer
occurs every time a trigger occurs.
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DMAEN = 0
Reset
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ
DMAEN = 0
DMAEN = 1
DMAxSZ → T_Size
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
[ DMADT = {0}
AND DMAxSZ = 0]
OR DMAEN = 0
DMAABORT = 1
Idle
DMAREQ = 0
DMAABORT=0
DMAxSZ > 0
AND DMAEN = 1
Wait forTrigger
2 x MCLK
[+Trigger AND DMALEVEL = 0 ]
OR
[Trigger = 1 AND DMALEVEL = 1]
Hold CPU,
Transfer one word/byte
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND Trigger = 0]
DMADT = {4}
AND DMAxSZ = 0
AND DMAEN = 1
Decrement DMAxSZ
Modify T_SourceAdd
Modify T_DestAdd
Figure 7-3. DMA Single Transfer State Diagram
7.2.2.2
Block Transfer
In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADT = {1}
,the DMAEN bit is cleared after the completion of the block transfer and must be set again before another
block transfer can be triggered. After a block transfer has been triggered, further trigger signals occurring
during the block transfer are ignored. The block transfer state diagram is shown in Figure 7-4.
The DMAxSZ register is used to define the size of the block, and the DMADSTINCR and DMASRCINCR
bits select if the destination address and the source address are incremented or decremented after each
transfer of the block. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The
DMAxSZ register is decremented after each transfer of the block and shows the number of transfers
remaining in the block. When the DMAxSZ register decrements to zero, it is reloaded from its temporary
register and the corresponding DMAIFG flag is set.
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During a block transfer, the CPU is halted until the complete block has been transferred. The block
transfer takes 2 × MCLK × DMAxSZ clock cycles to complete. CPU execution resumes with its previous
state after the block transfer is complete.
In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The
next trigger after the completion of a repeated block transfer triggers another block transfer.
DMAEN = 0
Reset
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ
DMAEN = 0
DMAEN = 1
DMAxSZ → T_Size
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
[DMADT = {1}
AND DMAxSZ = 0]
OR
DMAEN = 0
DMAABORT = 1
Idle
DMAREQ = 0
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMAABORT = 0
Wait forTrigger
DMADT = {5}
AND DMAxSZ = 0
AND DMAEN = 1
[+TriggerAND DMALEVEL= 0 ]
OR
[Trigger=1AND DMALEVEL=1]
2 × MCLK
Hold CPU,
Transfer one word/byte
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND Trigger = 0]
DMAxSZ > 0
Decrement DMAxSZ
Modify T_SourceAdd
Modify T_DestAdd
Figure 7-4. DMA Block Transfer State Diagram
7.2.2.3
Burst-Block Transfer
In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes
two MCLK cycles after every four byte/word transfers of the block, resulting in 20% CPU execution
capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared.
DMAEN must be set again before another burst-block transfer can be triggered. After a burst-block
transfer has been triggered, further trigger signals occurring during the burst-block transfer are ignored.
The burst-block transfer state diagram is shown in Figure 7-5.
The DMAxSZ register is used to define the size of the block, and the DMADSTINCR and DMASRCINCR
bits select if the destination address and the source address are incremented or decremented after each
transfer of the block. If DMAxSZ = 0, no transfers occur.
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The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The
DMAxSZ register is decremented after each transfer of the block and shows the number of transfers
remaining in the block. When the DMAxSZ register decrements to zero, it is reloaded from its temporary
register and the corresponding DMAIFG flag is set.
In repeated burst-block mode, the DMAEN bit remains set after completion of the burst-block transfer and
no further trigger signals are required to initiate another burst-block transfer. Another burst-block transfer
begins immediately after completion of a burst-block transfer. In this case, the transfers must be stopped
by clearing the DMAEN bit, or by an (non)maskable interrupt (NMI) when ENNMI is set. In repeated burstblock mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is
stopped.
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DMAEN = 0
Reset
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ
DMAEN = 0
DMAEN = 1
DMAxSZ → T_Size
[DMADT = {2, 3}
DMAxSA → T_SourceAdd
AND DMAxSZ = 0]
DMAxDA → T_DestAdd
OR
DMAEN = 0
DMAABORT = 1
Idle
DMAABORT=0
Wait for Trigger
2 × MCLK
[+Trigger AND DMALEVEL = 0 ]
OR
[Trigger=1 AND DMALEVEL=1]
Hold CPU,
Transfer one word/byte
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND
Trigger = 0]
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
Decrement DMAxSZ
Modify T_SourceAdd
Modify T_DestAdd
DMAxSZ > 0 AND
a multiple of 4 words/bytes
were transferred
DMAxSZ > 0
DMAxSZ > 0
[DMADT = {6, 7}
AND DMAxSZ = 0]
2 × MCLK
Burst State
(release CPU for 2 × MCLK)
Figure 7-5. DMA Burst-Block Transfer State Diagram
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7.2.3 Initiating DMA Transfers
Each DMA channel is independently configured for its trigger source with the DMAxTSEL. The
DMAxTSEL bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable
DMA triggers may occur.Table 7-2 describes the trigger operation for each type of module. See the
device-specific data sheet for the list of triggers available, along with their respective DMAxTSEL values.
When selecting the trigger, the trigger must not have already occurred, or the transfer does not take place.
NOTE:
DMA trigger selection and USB
On devices that contain a USB module, the triggers selection from DMA channels 0, 1, or 2
can be used for the USB time stamp event selection (see the USB module description for
further details).
7.2.3.1
Edge-Sensitive Triggers
When DMALEVEL = 0, edge-sensitive triggers are used, and the rising edge of the trigger signal initiates
the transfer. In single-transfer mode, each transfer requires its own trigger. When using block or burstblock modes, only one trigger is required to initiate the block or burst-block transfer.
7.2.3.2
Level-Sensitive Triggers
When DMALEVEL = 1, level-sensitive triggers are used. For proper operation, level-sensitive triggers can
only be used when external trigger DMAE0 is selected as the trigger. DMA transfers are triggered as long
as the trigger signal is high and the DMAEN bit remains set.
The trigger signal must remain high for a block or burst-block transfer to complete. If the trigger signal
goes low during a block or burst-block transfer, the DMA controller is held in its current state until the
trigger goes back high or until the DMA registers are modified by software. If the DMA registers are not
modified by software, when the trigger signal goes high again, the transfer resumes from where it was
when the trigger signal went low.
When DMALEVEL = 1, transfer modes selected when DMADT = {0, 1, 2, 3} are recommended because
the DMAEN bit is automatically reset after the configured transfer.
7.2.4 Halting Executing Instructions for DMA Transfers
The DMARMWDIS bit controls when the CPU is halted for DMA transfers. When DMARMWDIS = 0, the
CPU is halted immediately and the transfer begins when a trigger is received. In this case, it is possible
that CPU read-modify-write operations can be interrupted by a DMA transfer. When DMARMWDIS = 1,
the CPU finishes the currently executing read-modify-write operation before the DMA controller halts the
CPU and the transfer begins (see Table 7-2).
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Table 7-2. DMA Trigger Operation
Module
DMA
Operation
A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer
starts.
A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG triggers channel 2,
and DMA2IFG triggers channel 0. None of the DMAxIFG flags are automatically reset when the transfer starts.
A transfer is triggered by the external trigger DMAE0.
Timer_A
A transfer is triggered when the TAxCCR0 CCIFG flag is set. The TAxCCR0 CCIFG flag is automatically reset
when the transfer starts. If the TAxCCR0 CCIE bit is set, the TAxCCR0 CCIFG flag dies not trigger a transfer.
A transfer is triggered when the TAxCCR2 CCIFG flag is set. The TAxCCR2 CCIFG flag is automatically reset
when the transfer starts. If the TAxCCR2 CCIE bit is set, the TAxCCR2 CCIFG flag does not trigger a transfer.
Timer_B
A transfer is triggered when the TBxCCR0 CCIFG flag is set. The TBxCCR0 CCIFG flag is automatically reset
when the transfer starts. If the TBxCCR0 CCIE bit is set, the TBxCCR0 CCIFG flag does not trigger a transfer.
A transfer is triggered when the TBxCCR2 CCIFG flag is set. The TBxCCR2 CCIFG flag is automatically reset
when the transfer starts. If the TBxCCR2 CCIE bit is set, the TBxCCR2 CCIFG flag does not trigger a transfer.
USCI_Ax
A transfer is triggered when USCI_Ax receives new data. UCAxRXIFG is automatically reset when the transfer
starts. If UCAxRXIE is set, the UCAxRXIFG does not trigger a transfer.
A transfer is triggered when USCI_Ax is ready to transmit new data. UCAxTXIFG is automatically reset when the
transfer starts. If UCAxTXIE is set, the UCAxTXIFG does not trigger a transfer.
USCI_Bx
A transfer is triggered when USCI_Bx receives new data. UCBxRXIFG is automatically reset when the transfer
starts. If UCBxRXIE is set, the UCBxRXIFG does not trigger a transfer.
A transfer is triggered when USCI_Bx is ready to transmit new data. UCBxTXIFG is automatically reset when the
transfer starts. If UCBxTXIE is set, the UCBxTXIFG does not trigger a transfer.
DAC12_A
A transfer is triggered when the DAC12_xCTL0 DAC12IFG flag is set. The DAC12_xCTL0 DAC12IFG flag is
automatically cleared when the transfer starts. If the DAC12_xCTL0 DAC12IE bit is set, the DAC12_xCTL0
DAC12IFG flag does not trigger a transfer.
ADC12_A
A transfer is triggered by an ADC12IFG flag. When single-channel conversions are performed, the
corresponding ADC12IFG is the trigger. When sequences are used, the ADC12IFG for the last conversion in the
sequence is the trigger. A transfer is triggered when the conversion is completed and the ADC12IFG is set.
Setting the ADC12IFG with software does not trigger a transfer. All ADC12IFG flags are automatically reset
when the associated ADC12MEMx register is accessed by the DMA controller.
MPY
Reserved
A transfer is triggered when the hardware multiplier is ready for a new operand.
No transfer is triggered.
7.2.5 Stopping DMA Transfers
There are two ways to stop DMA transfers in progress:
• A single, block, or burst-block transfer may be stopped with an NMI, if the ENNMI bit is set in register
DMACTL1.
• A burst-block transfer may be stopped by clearing the DMAEN bit.
7.2.6 DMA Channel Priorities
The default DMA channel priorities are DMA0 through DMA7. If two or three triggers happen
simultaneously or are pending, the channel with the highest priority completes its transfer (single, block, or
burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in
progress are not halted if a higher-priority channel is triggered. The higher-priority channel waits until the
transfer in progress completes before starting.
The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is
set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the
channels always stays the same, DMA0-DMA1-DMA2, for example, for three channels. When the
ROUNDROBIN bit is cleared, the channel priority returns to the default priority.
326
DMA Priority
Transfer Occurs
New DMA Priority
DMA0-DMA1-DMA2
DMA1
DMA2-DMA0-DMA1
DMA2-DMA0-DMA1
DMA2
DMA0-DMA1-DMA2
DMA0-DMA1-DMA2
DMA0
DMA1-DMA2-DMA0
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7.2.7 DMA Transfer Cycle Time
The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or
complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after
synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the
DMA cycle time is dependent on the MSP430 operating mode and clock system setup.
If the MCLK source is active but the CPU is off, the DMA controller uses the MCLK source for each
transfer, without reenabling the CPU. If the MCLK source is off, the DMA controller temporarily restarts
MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer. The CPU
remains off and after the transfer completes, MCLK is turned off. The maximum DMA cycle time for all
operating modes is shown in Table 7-3.
Table 7-3. Maximum Single-Transfer DMA Cycle Time
CPU Operating Mode Clock Source
Maximum DMA Cycle Time
Active mode MCLK = DCOCLK
4 MCLK cycles
Active mode MCLK = LFXT1CLK
4 MCLK cycles
Low-power mode LPM0/1 MCLK = DCOCLK
5 MCLK cycles
Low-power mode LPM3/4 MCLK = DCOCLK
5 MCLK cycles + 5 µs (1)
Low-power mode LPM0/1 MCLK = LFXT1CLK
5 MCLK cycles
Low-power mode LPM3 MCLK = LFXT1CLK
5 MCLK cycles
Low-power mode LPM4 MCLK = LFXT1CLK
5 MCLK cycles + 5 µs (1)
(1)
The additional 5 µs are needed to start the DCOCLK. It is the t(LPMx) parameter in the data sheet.
7.2.8 Using DMA With System Interrupts
DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the
completion of the transfer. NMIs can interrupt the DMA controller if the ENNMI bit is set.
System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other
routine must execute with no interruptions, the DMA controller should be disabled prior to executing the
routine.
7.2.9 DMA Controller Interrupts
Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode when the
corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an
interrupt request is generated.
All DMAIFG flags are prioritized, with DMA0IFG being the highest, and combined to source a single
interrupt vector. The highest-priority enabled interrupt generates a number in the DMAIV register. This
number can be evaluated or added to the program counter (PC) to automatically enter the appropriate
software routine. Disabled DMA interrupts do not affect the DMAIV value.
Any access, read or write, of the DMAIV register automatically resets the highest pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
For example, assume that DMA0 has the highest priority. If the DMA0IFG and DMA2IFG flags are set
when the interrupt service routine accesses the DMAIV register, DMA0IFG is reset automatically. After the
RETI instruction of the interrupt service routine is executed, the DMA2IFG generates another interrupt.
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DMAIV Software Example
The following software example shows the recommended use of DMAIV and the handling overhead for an
eight channel DMA controller. The DMAIV value is added to the PC to automatically jump to the
appropriate routine.
The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself.
;Interrupt handler for DMAxIFG
DMA_HND
...
ADD
RETI
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
Interrupt latency
Add offset to Jump table
Vector 0: No interrupt
Vector 2: DMA channel 0
Vector 4: DMA channel 1
Vector 6: DMA channel 2
Vector 8: DMA channel 3
Vector 10: DMA channel 4
Vector 12: DMA channel 5
Vector 14: DMA channel 6
Vector 16: DMA channel 7
6
3
5
2
2
2
2
2
2
2
2
...
RETI
; Vector 16: DMA channel 7
; Task starts here
; Back to main program
5
...
RETI
; Vector 14: DMA channel 6
; Task starts here
; Back to main program
5
...
RETI
; Vector 12: DMA channel 5
; Task starts here
; Back to main program
5
...
RETI
; Vector 10: DMA channel 4
; Task starts here
; Back to main program
5
...
RETI
; Vector 8: DMA channel 3
; Task starts here
; Back to main program
5
...
RETI
; Vector 6: DMA channel 2
; Task starts here
; Back to main program
5
...
RETI
; Vector 4: DMA channel 1
; Task starts here
; Back to main program
5
...
RETI
; Vector 2: DMA channel 0
; Task starts here
; Back to main program
5
DMA7_HND
DMA6_HND
DMA5_HND
DMA4_HND
DMA3_HND
DMA2_HND
DMA1_HND
DMA0_HND
328
&DMAIV,PC
DMA0_HND
DMA1_HND
DMA2_HND
DMA3_HND
DMA4_HND
DMA5_HND
DMA6_HND
DMA7_HND
;
;
;
;
;
;
;
;
;
;
;
Cycles
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2
7.2.10 Using the USCI_B I C Module With the DMA Controller
The USCI_B I2C module provides two trigger sources for the DMA controller. The USCI_B I2C module can
trigger a transfer when new I2C data is received and the when the transmit data is needed.
7.2.11 Using ADC12 With the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMx
register to another location. DMA transfers are done without CPU intervention and independently of any
low-power modes. The DMA controller increases throughput of the ADC12 module, and enhances lowpower applications allowing the CPU to remain off while data transfers occur.
DMA transfers can be triggered from any ADC12IFG flag. When CONSEQx = {0,2}, the ADC12IFG flag for
the ADC12MEMx used for the conversion can trigger a DMA transfer. When CONSEQx = {1,3}, the
ADC12IFG flag for the last ADC12MEMx in the sequence can trigger a DMA transfer. Any ADC12IFG flag
is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx.
7.2.12 Using DAC12 With the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT
register. DMA transfers are done without CPU intervention and independently of any low-power modes.
The DMA controller increases throughput to the DAC12 module, and enhances low-power applications
allowing the CPU to remain off while data transfers occur.
Applications requiring periodic waveform generation can benefit from using the DMA controller with the
DAC12. For example, an application that produces a sinusoidal waveform may store the sinusoid values
in a table. The DMA controller can continuously and automatically transfer the values to the DAC12 at
specific intervals creating the sinusoid with zero CPU execution. The DAC12_xCTL DAC12IFG flag is
automatically cleared when the DMA controller accesses the DAC12_xDAT register.
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7.3
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DMA Registers
The DMA module registers are listed in Table 7-4. The base addresses can be found in the device-specific
data sheet. Each channel starts at its respective base address. The address offsets are listed in Table 7-4.
Table 7-4. DMA Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
DMACTL0
DMA Control 0
Read/write
Word
0000h
Section 7.3.1
02h
DMACTL1
DMA Control 1
Read/write
Word
0000h
Section 7.3.2
04h
DMACTL2
DMA Control 2
Read/write
Word
0000h
Section 7.3.3
06h
DMACTL3
DMA Control 3
Read/write
Word
0000h
Section 7.3.4
08h
DMACTL4
DMA Control 4
Read/write
Word
0000h
Section 7.3.5
0Eh
DMAIV
DMA Interrupt Vector
Read only
Word
0000h
Section 7.3.10
00h
DMA0CTL
DMA Channel 0 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA0SA
DMA Channel 0 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA0DA
DMA Channel 0 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA0SZ
DMA Channel 0 Transfer Size
Read/write
Word
undefined
Section 7.3.9
00h
DMA1CTL
DMA Channel 1 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA1SA
DMA Channel 1 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA1DA
DMA Channel 1 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA1SZ
DMA Channel 1 Transfer Size
Read/write
Word
undefined
Section 7.3.9
00h
DMA2CTL
DMA Channel 2 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA2SA
DMA Channel 2 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA2DA
DMA Channel 2 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA2SZ
DMA Channel 2 Transfer Size
Read/write
Word
undefined
Section 7.3.9
00h
DMA3CTL
DMA Channel 3 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA3SA
DMA Channel 3 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA3DA
DMA Channel 3 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA3SZ
DMA Channel 3 Transfer Size
Read/write
Word
undefined
Section 7.3.9
00h
DMA4CTL
DMA Channel 4 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA4SA
DMA Channel 4 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA4DA
DMA Channel 4 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA4SZ
DMA Channel 4 Transfer Size
Read/write
Word
undefined
Section 7.3.9
00h
DMA5CTL
DMA Channel 5 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA5SA
DMA Channel 5 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA5DA
DMA Channel 5 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA5SZ
DMA Channel 5 Transfer Size
Read/write
Word
undefined
Section 7.3.9
00h
DMA6CTL
DMA Channel 6 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA6SA
DMA Channel 6 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA6DA
DMA Channel 6 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA6SZ
DMA Channel 6 Transfer Size
Read/write
Word
undefined
Section 7.3.9
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Table 7-4. DMA Registers (continued)
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
DMA7CTL
DMA Channel 7 Control
Read/write
Word
0000h
Section 7.3.6
02h
DMA7SA
DMA Channel 7 Source Address
Read/write
Word,
double word
undefined
Section 7.3.7
06h
DMA7DA
DMA Channel 7 Destination Address
Read/write
Word,
double word
undefined
Section 7.3.8
0Ah
DMA7SZ
DMA Channel 7 Transfer Size
Read/write
Word
undefined
Section 7.3.9
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7.3.1 DMACTL0 Register
DMA Control 0 Register
Figure 7-6. DMACTL0 Register
15
14
13
12
11
r0
r0
rw-(0)
rw-(0)
6
5
4
3
Reserved
r0
7
9
8
rw-(0)
rw-(0)
rw-(0)
2
1
0
rw-(0)
rw-(0)
DMA1TSEL
Reserved
r0
10
DMA0TSEL
r0
r0
rw-(0)
rw-(0)
rw-(0)
Table 7-5. DMACTL0 Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Always reads as 0.
12-8
DMA1TSEL
RW
0h
DMA 1 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA1TRIG0
00001b = DMA1TRIG1
00010b = DMA1TRIG2
⋮
11110b = DMA1TRIG30
11111b = DMA1TRIG31
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-0
DMA0TSEL
RW
0h
DMA 0 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA0TRIG0
00001b = DMA0TRIG1
00010b = DMA0TRIG2
⋮
11110b = DMA0TRIG30
11111b = DMA0TRIG31
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7.3.2 DMACTL1 Register
DMA Control 1 Register
Figure 7-7. DMACTL1 Register
15
14
13
12
11
r0
r0
rw-(0)
rw-(0)
6
5
4
3
10
Reserved
r0
7
8
rw-(0)
rw-(0)
rw-(0)
2
1
0
rw-(0)
rw-(0)
DMA3TSEL
Reserved
r0
9
DMA2TSEL
r0
r0
rw-(0)
rw-(0)
rw-(0)
Table 7-6. DMACTL1 Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Always reads as 0.
12-8
DMA3TSEL
RW
0h
DMA 3 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA3TRIG0
00001b = DMA3TRIG1
00010b = DMA3TRIG2
⋮
11110b = DMA3TRIG30
11111b = DMA3TRIG31
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-0
DMA2TSEL
RW
0h
DMA 2 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA2TRIG0
00001b = DMA2TRIG1
00010b = DMA2TRIG2
⋮
11110b = DMA2TRIG30
11111b = DMA2TRIG31
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7.3.3 DMACTL2 Register
DMA Control 2 Register
Figure 7-8. DMACTL2 Register
15
14
13
12
11
r0
r0
rw-(0)
rw-(0)
6
5
4
3
Reserved
r0
7
9
8
rw-(0)
rw-(0)
rw-(0)
2
1
0
rw-(0)
rw-(0)
DMA5TSEL
Reserved
r0
10
DMA4TSEL
r0
r0
rw-(0)
rw-(0)
rw-(0)
Table 7-7. DMACTL2 Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Always reads as 0.
12-8
DMA5TSEL
RW
0h
DMA 5 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA5TRIG0
00001b = DMA5TRIG1
00010b = DMA5TRIG2
⋮
11110b = DMA5TRIG30
11111b = DMA5TRIG31
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-0
DMA4TSEL
RW
0h
DMA 4 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA4TRIG0
00001b = DMA4TRIG1
00010b = DMA4TRIG2
⋮
11110b = DMA4TRIG30
11111b = DMA4TRIG31
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7.3.4 DMACTL3 Register
DMA Control 3 Register
Figure 7-9. DMACTL3 Register
15
14
13
12
11
r0
r0
rw-(0)
rw-(0)
6
5
4
3
10
Reserved
r0
7
8
rw-(0)
rw-(0)
rw-(0)
2
1
0
rw-(0)
rw-(0)
DMA7TSEL
Reserved
r0
9
DMA6TSEL
r0
r0
rw-(0)
rw-(0)
rw-(0)
Table 7-8. DMACTL3 Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Always reads as 0.
12-8
DMA7TSEL
RW
0h
DMA 7 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA7TRIG0
00001b = DMA7TRIG1
00010b = DMA7TRIG2
⋮
11110b = DMA7TRIG30
11111b = DMA7TRIG31
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-0
DMA6TSEL
RW
0h
DMA 6 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment.
00000b = DMA6TRIG0
00001b = DMA6TRIG1
00010b = DMA6TRIG2
⋮
11110b = DMA6TRIG30
11111b = DMA6TRIG31
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7.3.5 DMACTL4 Register
DMA Control 4 Register
Figure 7-10. DMACTL4 Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
Reserved
Reserved
r0
r0
r0
r0
r0
2
1
0
DMARMWDIS
ROUNDROBIN
ENNMI
rw-(0)
rw-(0)
rw-(0)
Table 7-9. DMACTL4 Register Description
Bit
Field
Type
Reset
Description
15-3
Reserved
R
0h
Reserved. Always reads as 0.
2
DMARMWDIS
RW
0h
Read-modify-write disable. When set, this bit inhibits any DMA transfers from
occurring during CPU read-modify-write operations.
0b = DMA transfers can occur during read-modify-write CPU operations.
1b = DMA transfers inhibited during read-modify-write CPU operations
1
ROUNDROBIN
RW
0h
Round robin. This bit enables the round-robin DMA channel priorities.
0b = DMA channel priority is DMA0-DMA1-DMA2 - ...... -DMA7.
1b = DMA channel priority changes with each transfer.
0
ENNMI
RW
0h
Enable NMI. This bit enables the interruption of a DMA transfer by an NMI. When
an NMI interrupts a DMA transfer, the current transfer is completed normally,
further transfers are stopped and DMAABORT is set.
0b = NMI does not interrupt DMA transfer.
1b = NMI interrupts a DMA transfer.
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7.3.6 DMAxCTL Register
DMA Channel x Control Register
Figure 7-11. DMAxCTL Register
15
14
13
Reserved
11
rw-(0)
rw-(0)
DMADT
r0
rw-(0)
7
6
rw-(0)
DMADSTBYTE DMASRCBYTE
rw-(0)
12
10
9
rw-(0)
rw-(0)
DMADSTINCR
8
DMASRCINCR
rw-(0)
5
4
3
2
1
0
DMALEVEL
DMAEN
DMAIFG
DMAIE
DMAABORT
DMAREQ
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Table 7-10. DMAxCTL Register Description
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads as 0.
14-12
DMADT
RW
0h
DMA transfer mode
000b = Single transfer
001b = Block transfer
010b = Burst-block transfer
011b = Burst-block transfer
100b = Repeated single transfer
101b = Repeated block transfer
110b = Repeated burst-block transfer
111b = Repeated burst-block transfer
11-10
DMADSTINCR
RW
0h
DMA destination increment. This bit selects automatic incrementing or
decrementing of the destination address after each byte or word transfer. When
DMADSTBYTE = 1, the destination address increments/decrements by one.
When DMADSTBYTE = 0, the destination address increments/decrements by
two. The DMAxDA is copied into a temporary register and the temporary register
is incremented or decremented. DMAxDA is not incremented or decremented.
00b = Destination address is unchanged.
01b = Destination address is unchanged.
10b = Destination address is decremented.
11b = Destination address is incremented.
9-8
DMASRCINCR
RW
0h
DMA source increment. This bit selects automatic incrementing or decrementing
of the source address for each byte or word transfer. When DMASRCBYTE = 1,
the source address increments/decrements by one. When DMASRCBYTE = 0,
the source address increments/decrements by two. The DMAxSA is copied into a
temporary register and the temporary register is incremented or decremented.
DMAxSA is not incremented or decremented.
00b = Source address is unchanged.
01b = Source address is unchanged.
10b = Source address is decremented.
11b = Source address is incremented.
7
DMADSTBYTE
RW
0h
DMA destination byte. This bit selects the destination as a byte or word.
0b = Word
1b = Byte
6
DMASRCBYTE
RW
0h
DMA source byte. This bit selects the source as a byte or word.
0b = Word
1b = Byte
5
DMALEVEL
RW
0h
DMA level. This bit selects between edge-sensitive and level-sensitive triggers.
0b = Edge sensitive (rising edge)
1b = Level sensitive (high level)
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Table 7-10. DMAxCTL Register Description (continued)
Bit
Field
Type
Reset
Description
4
DMAEN
RW
0h
DMA enable
0b = Disabled
1b = Enabled
3
DMAIFG
RW
0h
DMA interrupt flag
0b = No interrupt pending
1b = Interrupt pending
2
DMAIE
RW
0h
DMA interrupt enable
0b = Disabled
1b = Enabled
1
DMAABORT
RW
0h
DMA abort. This bit indicates if a DMA transfer was interrupt by an NMI.
0b = DMA transfer not interrupted
1b = DMA transfer interrupted by NMI
0
DMAREQ
RW
0h
DMA request. Software-controlled DMA start. DMAREQ is reset automatically.
0b = No DMA start
1b = Start DMA
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7.3.7 DMAxSA Register
DMA Channel x Source Address Register
Figure 7-12. DMAxSA Register
31
30
29
28
27
26
25
24
r0
r0
r0
r0
r0
r0
r0
r0
23
22
21
20
19
18
17
16
Reserved
Reserved
DMAxSA
r0
r0
r0
r0
15
14
13
12
rw
rw
rw
rw
11
10
9
8
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
DMAxSA
rw
rw
rw
rw
7
6
5
4
DMAxSA
rw
rw
rw
rw
Table 7-11. DMAxSA Register Description
Bit
Field
Type
Reset
Description
31-20
Reserved
R
0h
Reserved. Always reads as 0.
19-0
DMAxSA
RW
undefined
DMA source address. The source address register points to the DMA source
address for single transfers or the first source address for block transfers. The
source address register remains unchanged during block and burst-block
transfers. There are two words for the DMAxSA register. Bits 31-20 are
reserved and always read as zero. Reading or writing bits 19-16 requires the
use of extended instructions. When writing to DMAxSA with word instructions,
bits 19-16 are cleared.
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7.3.8 DMAxDA Register
DMA Channel x Destination Address Register
Figure 7-13. DMAxDA Register
31
30
29
28
27
26
25
24
r0
r0
r0
r0
r0
r0
r0
r0
23
22
21
20
19
18
17
16
Reserved
Reserved
DMAxDA
r0
r0
r0
r0
15
14
13
12
rw
rw
rw
rw
11
10
9
8
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
DMAxDA
rw
rw
rw
rw
7
6
5
4
DMAxDA
rw
rw
rw
rw
Table 7-12. DMAxDA Register Description
Bit
Field
Type
Reset
Description
31-20
Reserved
R
0h
Reserved. Always reads as 0.
19-0
DMAxDA
RW
undefined
DMA destination address. The destination address register points to the DMA
destination address for single transfers or the first destination address for block
transfers. The destination address register remains unchanged during block and
burst-block transfers. There are two words for the DMAxDA register. Bits 31-20
are reserved and always read as zero. Reading or writing bits 19-16 requires
the use of extended instructions. When writing to DMAxDA with word
instructions, bits 19-16 are cleared.
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7.3.9 DMAxSZ Register
DMA Channel x Size Address Register
Figure 7-14. DMAxSZ Register
15
14
13
12
rw
rw
rw
rw
7
6
5
4
11
10
9
8
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
DMAxSZ
DMAxSZ
rw
rw
rw
rw
Table 7-13. DMAxSZ Register Description
Bit
Field
Type
Reset
Description
15-0
DMAxSZ
RW
undefined
DMA size. The DMA size register defines the number of byte/word data per
block transfer. DMAxSZ register decrements with each word or byte transfer.
When DMAxSZ decrements to 0, it is immediately and automatically reloaded
with its previously initialized value.
00000h = Transfer is disabled.
00001h = One byte or word is transferred.
00002h = Two bytes or words are transferred.
⋮
0FFFFh = 65535 bytes or words are transferred.
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7.3.10 DMAIV Register
DMA Interrupt Vector Register
Figure 7-15. DMAIV Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-(0)
r-(0)
r-(0)
r0
DMAIV
DMAIV
r0
r0
r-(0)
r-(0)
Table 7-14. DMAIV Register Description
Bit
Field
Type
Reset
Description
15-0
DMAIV
R
0h
DMA interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: DMA channel 0; Interrupt Flag: DMA0IFG; Interrupt
Priority: Highest
04h = Interrupt Source: DMA channel 1; Interrupt Flag: DMA1IFG
06h = Interrupt Source: DMA channel 2; Interrupt Flag: DMA2IFG
08h = Interrupt Source: DMA channel 3; Interrupt Flag: DMA3IFG
0Ah = Interrupt Source: DMA channel 4; Interrupt Flag: DMA4IFG
0Ch = Interrupt Source: DMA channel 5; Interrupt Flag: DMA5IFG
0Eh = Interrupt Source: DMA channel 6; Interrupt Flag: DMA6IFG
10h = Interrupt Source: DMA channel 7; Interrupt Flag: DMA7IFG; Interrupt
Priority: Lowest
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Chapter 8
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Digital I/O Module
This chapter describes the operation of the digital I/O ports in all devices.
Topic
...........................................................................................................................
8.1
8.2
8.3
8.4
Digital I/O Introduction .....................................................................................
Digital I/O Operation .........................................................................................
I/O Configuration and LPMx.5 Low-Power Modes ................................................
Digital I/O Registers .........................................................................................
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8.1
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Digital I/O Introduction
The digital I/O features include:
• Independently programmable individual I/Os
• Any combination of input or output
• Individually configurable P1 and P2 interrupts. Some devices may include additional port interrupts.
• Independent input and output data registers
• Individually configurable pullup or pulldown resistors
Devices within the family may have up to twelve digital I/O ports implemented (P1 to P11 and PJ). Most
ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for
ports available). Each I/O line is individually configurable for input or output direction, and each can be
individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors, as
well as, configurable drive strength, full or reduced. PJ contains only four I/O lines.
Ports P1 and P2 always have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be
individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All
P1 I/O lines source a single interrupt vector P1IV, and all P2 I/O lines source a different, single interrupt
vector P2IV. On some devices, additional ports with interrupt capability may be available (see the devicespecific data sheet for details) and contain their own respective interrupt vectors.
Individual ports can be accessed as byte-wide ports or can be combined into word-wide ports and
accessed via word formats. Port pairs P1 and P2, P3 and P4, P5 and P6, and so on, are associated with
the names PA, PB, PC, and so on, respectively. All port registers are handled in this manner with this
naming convention except for the interrupt vector registers; for example, PAIV does not exist for P1IV and
P2IV.
When writing to port PA with word operations, all 16 bits are written to the port. When writing to the lower
byte of the PA port using byte operations, the upper byte remains unchanged. Similarly, writing to the
upper byte of the PA port using byte instructions leaves the lower byte unchanged. When writing to a port
that contains less than the maximum number of bits possible, the unused bits are a "don't care". Ports PB,
PC, PD, PE, and PF behave similarly.
Reading of the PA port using word operations causes all 16 bits to be transferred to the destination.
Reading the lower or upper byte of the PA port (P1 or P2) and storing to memory using byte operations
causes only the lower or upper byte to be transferred to the destination, respectively. Reading of the PA
port and storing to a general-purpose register using byte operations causes the byte transferred to be
written to the least significant byte of the register. The upper significant byte of the destination register is
cleared automatically. Ports PB, PC, PD, PE, and PF behave similarly. When reading from ports that
contain less than the maximum bits possible, unused bits are read as zeros (similarly for port PJ).
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8.2
Digital I/O Operation
The digital I/O are configured with user software. The setup and operation of the digital I/O are discussed
in the following sections.
8.2.1 Input Registers (PxIN)
Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the
pin is configured as I/O function. These registers are read only.
• Bit = 0: Input is low
• Bit = 1: Input is high
NOTE:
Writing to read-only registers PxIN
Writing to these read-only registers results in increased current consumption while the write
attempt is active.
8.2.2 Output Registers (PxOUT)
Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the pin is
configured as I/O function, output direction.
• Bit = 0: Output is low
• Bit = 1: Output is high
If the pin is configured as I/O function, input direction and the pullup/pulldown resistor are enabled; the
corresponding bit in the PxOUT register selects pullup or pulldown.
• Bit = 0: Pin is pulled down
• Bit = 1: Pin is pulled up
8.2.3 Direction Registers (PxDIR)
Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of the
selected function for the pin. PxDIR bits for I/O pins that are selected for other functions must be set as
required by the other function.
• Bit = 0: Port pin is switched to input direction
• Bit = 1: Port pin is switched to output direction
8.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN)
Each bit in each PxREN register enables or disables the pullup/pulldown resistor of the corresponding I/O
pin. The corresponding bit in the PxOUT register selects if the pin contains a pullup or pulldown.
• Bit = 0: Pullup/pulldown resistor disabled
• Bit = 1: Pullup/pulldown resistor enabled
Table 8-1 summarizes the usage of PxDIR, PxREN, and PxOUT for proper I/O configuration.
Table 8-1. I/O Configuration
PxDIR
PxREN
PxOUT
0
0
x
I/O Configuration
Input
0
1
0
Input with pulldown resistor
0
1
1
Input with pullup resistor
1
x
x
Output
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8.2.5 Output Drive Strength Registers (PxDS)
Each bit in each PxDS register selects either full drive or reduced drive strength. Default is reduced drive
strength.
• Bit = 0: Reduced drive strength
• Bit = 1: Full drive strength
NOTE:
Drive strength and EMI
All outputs default to reduced drive strength to reduce EMI. Using full drive strength can
result in increased EMI.
8.2.6 Function Select Registers (PxSEL)
Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet
to determine pin functions. Each PxSEL bit is used to select the pin function – I/O port or peripheral
module function.
• Bit = 0: I/O Function is selected for the pin
• Bit = 1: Peripheral module function is selected for the pin
Setting PxSEL = 1 does not automatically set the pin direction. Other peripheral module functions may
require the PxDIR bits to be configured according to the direction needed for the module function. See the
pin schematics in the device-specific data sheet.
NOTE:
P1 and P2 interrupts are disabled when PxSEL = 1
When any PxSEL bit is set, the corresponding pin’s interrupt function is disabled. Therefore,
signals on these pins does not generate P1 or P2 interrupts, regardless of the state of the
corresponding P1IE or P2IE bit.
When a port pin is selected as an input to a peripheral, the input signal to the peripheral is a latched
representation of the signal at the device pin. While its corresponding PxSEL = 1, the internal input signal
follows the signal at the pin. However, if its PxSEL = 0, the input to the peripheral maintains the value of
the input signal at the device pin before its corresponding PxSEL bit was reset.
8.2.7 Port Interrupts
Each pin in ports P1 and P2 has interrupt capability, configured with the PxIFG, PxIE, and PxIES
registers. On some devices, additional ports have interrupt capability (see the device-specific data sheet).
All P1 interrupt flags are prioritized, with P1IFG.0 being the highest, and combined to source a single
interrupt vector. The highest priority enabled interrupt generates a number in the P1IV register. This
number can be evaluated or added to the program counter to automatically enter the appropriate software
routine. Disabled P1 interrupts do not affect the P1IV value. The same functionality exists for P2. The PxIV
registers are word access only. Some devices may contain additional port interrupts besides P1 and P2.
See the device specific data sheet to determine which port interrupts are available.
Each PxIFG bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal
edge occurs at the pin. All PxIFG interrupt flags request an interrupt when their corresponding PxIE bit
and the GIE bit are set. Software can also set each PxIFG flag, providing a way to generate a softwareinitiated interrupt.
• Bit = 0: No interrupt is pending
• Bit = 1: An interrupt is pending
Only transitions, not static levels, cause interrupts. If any PxIFG flag becomes set during a Px interrupt
service routine, or is set after the RETI instruction of a Px interrupt service routine is executed, the set
PxIFG flag generates another interrupt. This ensures that each transition is acknowledged.
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NOTE:
PxIFG flags when changing PxOUT, PxDIR, or PxREN
Writing to P1OUT, P1DIR, P1REN, P2OUT, P2DIR, or P2REN can result in setting the
corresponding P1IFG or P2IFG flags.
Any access (read or write) of the P1IV register automatically resets the highest pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
For example, assume that P1IFG.0 has the highest priority. If the P1IFG.0 and P1IFG.2 flags are set when
the interrupt service routine accesses the P1IV register, P1IFG.0 is reset automatically. After the RETI
instruction of the interrupt service routine is executed, the P1IFG.2 generates another interrupt.
Port P2 interrupts behave similarly, and source a separate single interrupt vector and utilize the P2IV
register.
Port Interrupt Software Example
The following software example shows the recommended use of P1IV and the handling overhead. The
P1IV value is added to the PC to automatically jump to the appropriate routine. The P2IV is similar.
The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself.
;Interrupt handler for P1
P1_HND
...
ADD
&P1IV,PC
RETI
JMP
P1_0_HND
JMP
P1_1_HND
JMP
P1_2_HND
JMP
P1_3_HND
JMP
P1_4_HND
JMP
P1_5_HND
JMP
P1_6_HND
JMP
P1_7_HND
;
;
;
;
;
;
;
;
;
;
;
P1_7_HND
Interrupt latency
Add offset to Jump table
Vector 0: No interrupt
Vector 2: Port 1 bit 0
Vector 4: Port 1 bit 1
Vector 6: Port 1 bit 2
Vector 8: Port 1 bit 3
Vector 10: Port 1 bit 4
Vector 12: Port 1 bit 5
Vector 14: Port 1 bit 6
Vector 16: Port 1 bit 7
Cycles
6
3
5
2
2
2
2
2
2
2
2
...
RETI
; Vector 16: Port 1 bit 7
; Task starts here
; Back to main program
5
...
RETI
; Vector 14: Port 1 bit 6
; Task starts here
; Back to main program
5
...
RETI
; Vector 12: Port 1 bit 5
; Task starts here
; Back to main program
5
...
RETI
; Vector 10: Port 1 bit 4
; Task starts here
; Back to main program
5
...
RETI
; Vector 8: Port 1 bit 3
; Task starts here
; Back to main program
5
...
RETI
; Vector 6: Port 1 bit 2
; Task starts here
; Back to main program
5
P1_6_HND
P1_5_HND
P1_4_HND
P1_3_HND
P1_2_HND
P1_1_HND
;
;
;
;
;
;
...
RETI
P1_0_HND
...
RETI
Vector 4: Port 1 bit 1
Task starts here
Back to main program
Vector 2: Port 1 bit 0
Task starts here
Back to main program
5
5
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Interrupt Edge Select Registers (PxIES)
Each PxIES bit selects the interrupt edge for the corresponding I/O pin.
• Bit = 0: Respective PxIFG flag is set with a low-to-high transition
• Bit = 1: Respective PxIFG flag is set with a high-to-low transition
NOTE:
Writing to PxIES
Writing to P1IES or P2IES for each corresponding I/O can result in setting the corresponding
interrupt flags.
PxIES
0→1
0→1
1→0
1→0
PxIN
0
1
0
1
PxIFG
May be set
Unchanged
Unchanged
May be set
Interrupt Enable Registers (PxIE)
Each PxIE bit enables the associated PxIFG interrupt flag.
• Bit = 0: The interrupt is disabled
• Bit = 1: The interrupt is enabled
8.2.8 Configuring Unused Port Pins
Unused I/O pins should be configured as I/O function, output direction, and left unconnected on the PC
board, to prevent a floating input and reduce power consumption. The value of the PxOUT bit is don't
care, because the pin is unconnected. Alternatively, the integrated pullup/pulldown resistor can be enabled
by setting the PxREN bit of the unused pin to prevent the floating input. See the SYS chapter for
termination of unused pins.
NOTE:
Configuring port J and shared JTAG pins:
Application should ensure that port PJ is configured properly to prevent a floating input.
Because port PJ is shared with the JTAG function, floating inputs may not be noticed when
in an emulation environment. Port J is initialized to high-impedance inputs by default.
8.3
I/O Configuration and LPMx.5 Low-Power Modes
NOTE: The LPMx.5 low-power modes may not be available on all devices. The LPM4.5 power mode
allows for lowest power consumption and no clocks are available. The LPM3.5 power mode
allows for RTC mode operation at the lowest power consumption available. See the SYS
chapter for details; also see the device-specific datasheet for LPMx.5 low-power modes that
are available. With respect to the digital I/O, this section is applicable for both LPM3.5 and
LPM4.5.
The regulator of the Power Management Module (PMM) is disabled upon entering LPMx.5 (LPM3.5 or
LPM4.5), which causes all I/O register configurations to be lost. Because the I/O register configurations
are lost, the configuration of I/O pins must be handled differently to ensure that all pins in the application
behave in a controlled manner upon entering and exiting LPMx.5. Properly setting the I/O pins is critical to
achieving the lowest possible power consumption in LPMx.5, as well as preventing any possible
uncontrolled input or output I/O state in the application. The application has complete control of the I/O pin
conditions preventing the possibility of unwanted spurious activity upon entry and exit from LPMx.5. The
detailed flow for entering and exiting LPMx.5 with respect to the I/O operation is as follows:
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1. Set all I/Os to general purpose I/Os and configure as needed. Each I/O can be set to input high
impedance, input with pulldown, input with pullup, output high (low or high drive strength), or output low
(low or high drive strength). It is critical that no inputs are left floating in the application, otherwise
excess current may be drawn in LPMx.5. Configuring the I/O in this manner ensures that each pin is in
a safe condition prior to entering LPMx.5.
Optionally, configure input interrupt pins for wake-up from LPMx.5. To wake the device from LPMx.5, a
general-purpose I/O port must contain an input port with interrupt capability. Not all devices include
wakeup from LPMx.5 via I/O, and not all inputs with interrupt capability offer wakeup from LPMx.5. See
the device-specific data sheet for availability. To configure a port to wake up the device, it should be
configured properly prior to entering LPMx.5. Each port should be configured as general-purpose input.
Pulldowns or pullups can be applied if required. Setting the PxIES bit of the corresponding register
determines the edge transition that wakes the device. Lastly, the PxIE for the port must be enabled, as
well as the general interrupt enable.
NOTE: It is not possible to wakeup from LPMx.5 if its respective interrupt flag is already asserted. It
is recommended that the respective flag be cleared prior to entering LPMx.5. It is also
recommended that GIE = 1 be set prior to entry into LPMx.5. Any pending flags in this case
could then be serviced prior to LPMx.5 entry.
Although it is recommended to set GIE = 1 prior to entering LPMx.5, it is not required. Device
wakeup from LPMx.5 with an enabled wakeup function will still cause the device to wake up
from LPMx.5 even with GIE = 0. If GIE = 0 prior to LPMx.5, additional care may be required.
Should the respective interrupt event should occur during LPMx.5 entry, the device may not
recognize this or any future interrupt wakeup event on this function.
2. Enter LPMx.5 with LPMx.5 entry sequence, enable general interrupts for wake-up:
MOV.B #PMMPW_H, &PMMCTL0_H
BIS.B #PMMREGOFF, &PMMCTL0_L
BIS
#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR
; Open PMM registers for write
;
; Enter LPMx.5 when PMMREGOFF is set
3. Upon entry into LPMx.5, LOCKLPM5 residing in PM5CTL0 of the PMM module is set automatically.
The I/O pin states are held and locked based on the settings prior to LPMx.5 entry. Note that only the
pin conditions are retained. All other port configuration register settings such as PxDIR, PxREN,
PxOUT, PxDS, PxIES, and PxIE contents are lost.
4. An LPMx.5 wakeup event (for example, an edge on a configured wakeup input pin) starts the BOR
entry sequence together with the regulator. All peripheral registers are set to their default conditions.
Upon exit from LPMx.5, the I/O pins remain locked while LOCKLPM5 remains set. Keeping the I/O
pins locked ensures that all pin conditions remain stable upon entering the active mode regardless of
the default I/O register settings.
5. Once in active mode, the I/O configuration and I/O interrupt configuration that was not retained during
LPMx.5 should be restored to the values prior to entering LPMx.5. It is recommended to reconfigure
the PxIES and PxIE to their previous settings to prevent a false port interrupt from occurring. The
LOCKLPM5 bit can then be cleared, which releases the I/O pin conditions and I/O interrupt
configuration. Any changes to the port configuration registers while LOCKLPM5 is set, have no effect
on the I/O pins.
6. After enabling the I/O interrupts, the I/O interrupt that caused the wakeup can be serviced indicated by
the PxIFG flags. These flags can be used directly, or the corresponding PxIV register may be used.
Note that the PxIFG flag cannot be cleared until the LOCKLPM5 bit has been cleared.
NOTE: It is possible that multiple events occurred on various ports. In these cases, multiple PxIFG
flags will be set, and it cannot be determined which port has caused the I/O wakeup.
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Digital I/O Registers
The digital I/O registers are listed in Table 8-2. The base addresses can be found in the device-specific
data sheet. Each port grouping begins at its base address. The address offsets are given in Table 8-2.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 8-2. Digital I/O Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
0Eh
P1IV
Port 1 Interrupt Vector
Read only
Word
0000h
Section 8.4.1
0Eh
P1IV_L
Read only
Byte
00h
0Fh
P1IV_H
Read only
Byte
00h
1Eh
P2IV
Read only
Word
0000h
1Eh
P2IV_L
Read only
Byte
00h
1Fh
P2IV_H
Read only
Byte
00h
00h
P1IN or
PAIN_L
Port 1 Input
Read only
Byte
02h
P1OUT or
PAOUT_L
Port 1 Output
Read/write
Byte
undefined
Section 8.4.10
04h
P1DIR or
PADIR_L
Port 1 Direction
Read/write
Byte
00h
Section 8.4.11
06h
P1REN or
PAREN_L
Port 1 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
08h
P1DS or
PADS_L
Port 1 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Ah
P1SEL or
PASEL_L
Port 1 Port Select
Read/write
Byte
00h
Section 8.4.14
18h
P1IES or
PAIES_L
Port 1 Interrupt Edge Select
Read/write
Byte
undefined
Section 8.4.3
1Ah
P1IE or
PAIE_L
Port 1 Interrupt Enable
Read/write
Byte
00h
Section 8.4.4
1Ch
P1IFG or
PAIFG_L
Port 1 Interrupt Flag
Read/write
Byte
00h
Section 8.4.5
01h
P2IN or
PAIN_H
Port 2 Input
Read only
Byte
03h
P2OUT or
PAOUT_H
Port 2 Output
Read/write
Byte
undefined
Section 8.4.10
05h
P2DIR or
PADIR_H
Port 2 Direction
Read/write
Byte
00h
Section 8.4.11
07h
P2REN or
PAREN_H
Port 2 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
09h
P2DS or
PADS_H
Port 2 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Bh
P2SEL or
PASEL_H
Port 2 Port Select
Read/write
Byte
00h
Section 8.4.14
19h
P2IES or
PAIES_H
Port 2 Interrupt Edge Select
Read/write
Byte
undefined
Section 8.4.6
1Bh
P2IE or
PAIE_H
Port 2 Interrupt Enable
Read/write
Byte
00h
Section 8.4.7
1Dh
P2IFG or
PAIFG_H
Port 2 Interrupt Flag
Read/write
Byte
00h
Section 8.4.8
00h
P3IN or
PBIN_L
Port 3 Input
Read only
Byte
02h
P3OUT or
PBOUT_L
Port 3 Output
Read/write
Byte
350 Digital I/O Module
Port 2 Interrupt Vector
Section 8.4.2
Section 8.4.9
Section 8.4.9
Section 8.4.9
undefined
Section 8.4.10
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Table 8-2. Digital I/O Registers (continued)
Offset
Acronym
Register Name
Type
Access
Reset
Section
04h
P3DIR or
PBDIR_L
Port 3 Direction
Read/write
Byte
00h
Section 8.4.11
06h
P3REN or
PBREN_L
Port 3 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
08h
P3DS or
PBDS_L
Port 3 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Ah
P3SEL or
PBSEL_L
Port 3 Port Select
Read/write
Byte
00h
Section 8.4.14
01h
P4IN or
PBIN_H
Port 4 Input
Read only
Byte
03h
P4OUT or
PBOUT_H
Port 4 Output
Read/write
Byte
undefined
Section 8.4.10
05h
P4DIR or
PBDIR_H
Port 4 Direction
Read/write
Byte
00h
Section 8.4.11
07h
P4REN or
PBREN_H
Port 4 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
09h
P4DS or
PBDS_H
Port 4 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Bh
P4SEL or
PBSEL_H
Port 4 Port Select
Read/write
Byte
00h
Section 8.4.14
00h
P5IN or
PCIN_L
Port 5 Input
Read only
Byte
02h
P5OUT or
PCOUT_L
Port 5 Output
Read/write
Byte
undefined
Section 8.4.10
04h
P5DIR or
PCDIR_L
Port 5 Direction
Read/write
Byte
00h
Section 8.4.11
06h
P5REN or
PCREN_L
Port 5 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
08h
P5DS or
PCDS_L
Port 5 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Ah
P5SEL or
PCSEL_L
Port 5 Port Select
Read/write
Byte
00h
Section 8.4.14
01h
P6IN or
PCIN_H
Port 6 Input
Read only
Byte
03h
P6OUT or
PCOUT_H
Port 6 Output
Read/write
Byte
undefined
Section 8.4.10
05h
P6DIR or
PCDIR_H
Port 6 Direction
Read/write
Byte
00h
Section 8.4.11
07h
P6REN or
PCREN_H
Port 6 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
09h
P6DS or
PCDS_H
Port 6 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Bh
P6SEL or
PCSEL_H
Port 6 Port Select
Read/write
Byte
00h
Section 8.4.14
00h
P7IN or
PDIN_L
Port 7 Input
Read only
Byte
02h
P7OUT or
PDOUT_L
Port 7 Output
Read/write
Byte
undefined
Section 8.4.10
04h
P7DIR or
PDDIR_L
Port 7 Direction
Read/write
Byte
00h
Section 8.4.11
06h
P7REN or
PDREN_L
Port 7 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
08h
P7DS or
PDDS_L
Port 7 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Ah
P7SEL or
PDSEL_L
Port 7 Port Select
Read/write
Byte
00h
Section 8.4.14
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Section 8.4.9
Section 8.4.9
Section 8.4.9
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Table 8-2. Digital I/O Registers (continued)
Offset
Acronym
Register Name
Type
Access
01h
P8IN or
PDIN_H
Port 8 Input
Read only
Byte
03h
P8OUT or
PDOUT_H
Port 8 Output
Read/write
Byte
undefined
Section 8.4.10
05h
P8DIR or
PDDIR_H
Port 8 Direction
Read/write
Byte
00h
Section 8.4.11
07h
P8REN or
PDREN_H
Port 8 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
09h
P8DS or
PDDS_H
Port 8 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Bh
P8SEL or
PDSEL_H
Port 8 Port Select
Read/write
Byte
00h
Section 8.4.14
00h
P9IN or
PEIN_L
Port 9 Input
Read only
Byte
02h
P9OUT or
PEOUT_L
Port 9 Output
Read/write
Byte
undefined
Section 8.4.10
04h
P9DIR or
PEDIR_L
Port 9 Direction
Read/write
Byte
00h
Section 8.4.11
06h
P9REN or
PEREN_L
Port 9 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
08h
P9DS or
PEDS_L
Port 9 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Ah
P9SEL or
PESEL_L
Port 9 Port Select
Read/write
Byte
00h
Section 8.4.14
01h
P10IN or
PEIN_H
Port 10 Input
Read only
Byte
03h
P10OUT or
PEOUT_H
Port 10 Output
Read/write
Byte
undefined
Section 8.4.10
05h
P10DIR or
PEDIR_H
Port 10 Direction
Read/write
Byte
00h
Section 8.4.11
07h
P10REN or
PEREN_H
Port 10 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
09h
P10DS or
PEDS_H
Port 10 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Bh
P10SEL or
PESEL_H
Port 10 Port Select
Read/write
Byte
00h
Section 8.4.14
00h
P11IN or
PFIN_L
Port 11 Input
Read only
Byte
02h
P11OUT or
PFOUT_L
Port 11 Output
Read/write
Byte
undefined
Section 8.4.10
04h
P11DIR or
PFDIR_L
Port 11 Direction
Read/write
Byte
00h
Section 8.4.11
06h
P11REN or
PFREN_L
Port 11 Resistor Enable
Read/write
Byte
00h
Section 8.4.12
08h
P11DS or
PFDS_L
Port 11 Drive Strength
Read/write
Byte
00h
Section 8.4.13
0Ah
P11SEL or
PFSEL_L
Port 11 Port Select
Read/write
Byte
00h
Section 8.4.14
00h
PAIN
Port A Input
Read only
Word
00h
PAIN_L
Read only
Byte
01h
PAIN_H
Read only
Byte
02h
PAOUT
Read/write
Word
undefined
02h
PAOUT_L
Read/write
Byte
undefined
03h
PAOUT_H
Read/write
Byte
undefined
04h
PADIR
Read/write
Word
0000h
352 Digital I/O Module
Port A Output
Port A Direction
Reset
Section
Section 8.4.9
Section 8.4.9
Section 8.4.9
Section 8.4.9
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Table 8-2. Digital I/O Registers (continued)
Offset
Acronym
04h
PADIR_L
05h
PADIR_H
06h
PAREN
06h
Register Name
Type
Access
Reset
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
0000h
PAREN_L
Read/write
Byte
00h
07h
PAREN_H
Read/write
Byte
00h
08h
PADS
Read/write
Word
0000h
08h
PADS_L
Read/write
Byte
00h
09h
PADS_H
Read/write
Byte
00h
0Ah
PASEL
Read/write
Word
0000h
0Ah
PASEL_L
Read/write
Byte
00h
0Bh
PASEL_H
Read/write
Byte
00h
18h
PAIES
Read/write
Word
undefined
18h
PAIES_L
Read/write
Byte
undefined
19h
PAIES_H
Read/write
Byte
undefined
1Ah
PAIE
Read/write
Word
0000h
1Ah
PAIE_L
Read/write
Byte
00h
1Bh
PAIE_H
Read/write
Byte
00h
1Ch
PAIFG
Read/write
Word
0000h
1Ch
PAIFG_L
Read/write
Byte
00h
1Dh
PAIFG_H
Read/write
Byte
00h
00h
PBIN
Read only
Word
00h
PBIN_L
Read only
Byte
01h
PBIN_H
Read only
Byte
02h
PBOUT
Read/write
Word
undefined
02h
PBOUT_L
Read/write
Byte
undefined
03h
PBOUT_H
Read/write
Byte
undefined
04h
PBDIR
Read/write
Word
0000h
04h
PBDIR_L
Read/write
Byte
00h
05h
PBDIR_H
Read/write
Byte
00h
06h
PBREN
Read/write
Word
0000h
06h
PBREN_L
Read/write
Byte
00h
07h
PBREN_H
Read/write
Byte
00h
08h
PBDS
Read/write
Word
0000h
08h
PBDS_L
Read/write
Byte
00h
09h
PBDS_H
Read/write
Byte
00h
0Ah
PBSEL
Read/write
Word
0000h
0Ah
PBSEL_L
Read/write
Byte
00h
0Bh
PBSEL_H
Read/write
Byte
00h
00h
PCIN
Read only
Word
00h
PCIN_L
Read only
Byte
01h
PCIN_H
Read only
Byte
02h
PCOUT
Read/write
Word
undefined
02h
PCOUT_L
Read/write
Byte
undefined
03h
PCOUT_H
Read/write
Byte
undefined
04h
PCDIR
Read/write
Word
0000h
04h
PCDIR_L
Read/write
Byte
00h
05h
PCDIR_H
Read/write
Byte
00h
Port A Resistor Enable
Port A Drive Strength
Port A Port Select
Port A Interrupt Edge Select
Port A Interrupt Enable
Port A Interrupt Flag
Port B Input
Port B Output
Port B Direction
Port B Resistor Enable
Port B Drive Strength
Port B Port Select
Port C Input
Port C Output
Port C Direction
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Table 8-2. Digital I/O Registers (continued)
Offset
Acronym
Register Name
Type
Access
Reset
06h
PCREN
Port C Resistor Enable
Read/write
Word
0000h
06h
PCREN_L
Read/write
Byte
00h
07h
PCREN_H
Read/write
Byte
00h
08h
PCDS
Read/write
Word
0000h
08h
PCDS_L
Read/write
Byte
00h
09h
PCDS_H
Read/write
Byte
00h
0Ah
PCSEL
Read/write
Word
0000h
0Ah
PCSEL_L
Read/write
Byte
00h
0Bh
PCSEL_H
Read/write
Byte
00h
00h
PDIN
Read only
Word
00h
PDIN_L
Read only
Byte
01h
PDIN_H
Read only
Byte
02h
PDOUT
Read/write
Word
undefined
02h
PDOUT_L
Read/write
Byte
undefined
03h
PDOUT_H
Read/write
Byte
undefined
04h
PDDIR
Read/write
Word
0000h
04h
PDDIR_L
Read/write
Byte
00h
05h
PDDIR_H
Read/write
Byte
00h
06h
PDREN
Read/write
Word
0000h
06h
PDREN_L
Read/write
Byte
00h
07h
PDREN_H
Read/write
Byte
00h
08h
PDDS
Read/write
Word
0000h
08h
PDDS_L
Read/write
Byte
00h
09h
PDDS_H
Read/write
Byte
00h
0Ah
PDSEL
Read/write
Word
0000h
0Ah
PDSEL_L
Read/write
Byte
00h
0Bh
PDSEL_H
Read/write
Byte
00h
00h
PEIN
Read only
Word
00h
PEIN_L
Read only
Byte
01h
PEIN_H
Read only
Byte
02h
PEOUT
Read/write
Word
undefined
02h
PEOUT_L
Read/write
Byte
undefined
03h
PEOUT_H
Read/write
Byte
undefined
04h
PEDIR
Read/write
Word
0000h
04h
PEDIR_L
Read/write
Byte
00h
05h
PEDIR_H
Read/write
Byte
00h
06h
PEREN
Read/write
Word
0000h
06h
PEREN_L
Read/write
Byte
00h
07h
PEREN_H
Read/write
Byte
00h
08h
PEDS
Read/write
Word
0000h
08h
PEDS_L
Read/write
Byte
00h
09h
PEDS_H
Read/write
Byte
00h
0Ah
PESEL
Read/write
Word
0000h
0Ah
PESEL_L
Read/write
Byte
00h
0Bh
PESEL_H
Read/write
Byte
00h
00h
PFIN
Read only
Word
00h
PFIN_L
Read only
Byte
354 Digital I/O Module
Port C Drive Strength
Port C Port Select
Port D Input
Port D Output
Port D Direction
Port D Resistor Enable
Port D Drive Strength
Port D Port Select
Port E Input
Port E Output
Port E Direction
Port E Resistor Enable
Port E Drive Strength
Port E Port Select
Port F Input
Section
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Table 8-2. Digital I/O Registers (continued)
Offset
Acronym
01h
PFIN_H
02h
PFOUT
02h
PFOUT_L
03h
PFOUT_H
04h
PFDIR
04h
05h
06h
PFREN
06h
07h
08h
PFDS
08h
09h
0Ah
PFSEL
0Ah
PFSEL_L
0Bh
PFSEL_H
00h
PJIN
00h
PJIN_L
01h
PJIN_H
02h
PJOUT
02h
PJOUT_L
03h
PJOUT_H
04h
PJDIR
04h
Register Name
Type
Access
Read only
Byte
Read/write
Word
undefined
Read/write
Byte
undefined
Read/write
Byte
undefined
Read/write
Word
0000h
PFDIR_L
Read/write
Byte
00h
PFDIR_H
Read/write
Byte
00h
Read/write
Word
0000h
PFREN_L
Read/write
Byte
00h
PFREN_H
Read/write
Byte
00h
Read/write
Word
0000h
PFDS_L
Read/write
Byte
00h
PFDS_H
Read/write
Byte
00h
Read/write
Word
0000h
Read/write
Byte
00h
Read/write
Byte
00h
Read only
Word
Read only
Byte
Read only
Byte
Read/write
Word
undefined
Read/write
Byte
undefined
Read/write
Byte
undefined
Read/write
Word
0000h
PJDIR_L
Read/write
Byte
00h
05h
PJDIR_H
Read/write
Byte
00h
06h
PJREN
Read/write
Word
0000h
06h
PJREN_L
Read/write
Byte
00h
07h
PJREN_H
Read/write
Byte
00h
08h
PJDS
Read/write
Word
0000h
08h
PJDS_L
Read/write
Byte
00h
09h
PJDS_H
Read/write
Byte
00h
Port F Output
Port F Direction
Port F Resistor Enable
Port F Drive Strength
Port F Port Select
Port J Input
Port J Output
Port J Direction
Port J Resistor Enable
Port J Drive Strength
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8.4.1 P1IV Register
Port 1 Interrupt Vector Register
Figure 8-1. P1IV Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-0
r-0
r-0
r0
P1IV
P1IV
r0
r0
r0
r-0
Table 8-3. P1IV Register Description
Bit
Field
Type
Reset
Description
15-0
P1IV
R
0h
Port 1 interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG.0; Interrupt
Priority: Highest
04h = Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG.1
06h = Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG.2
08h = Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG.3
0Ah = Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG.4
0Ch = Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG.5
0Eh = Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG.6
10h = Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG.7; Interrupt
Priority: Lowest
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8.4.2 P2IV Register
Port 2 Interrupt Vector Register
Figure 8-2. P2IV Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-0
r-0
r-0
r0
P2IV
P2IV
r0
r0
r0
r-0
Table 8-4. P2IV Register Description
Bit
Field
Type
Reset
Description
15-0
P2IV
R
0h
Port 2 interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG.0; Interrupt
Priority: Highest
04h = Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG.1
06h = Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG.2
08h = Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG.3
0Ah = Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG.4
0Ch = Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG.5
0Eh = Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG.6
10h = Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG.7; Interrupt
Priority: Lowest
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8.4.3 P1IES Register
Port 1 Interrupt Edge Select Register
Figure 8-3. P1IES Register
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
P1IES
Table 8-5. P1IES Register Description
Bit
Field
Type
Reset
Description
7-0
P1IES
RW
undefined
Port 1 interrupt edge select
0b = P1IFG flag is set with a low-to-high transition.
1b = P1IFG flag is set with a high-to-low transition.
8.4.4 P1IE Register
Port 1 Interrupt Enable Register
Figure 8-4. P1IE Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
P1IE
rw-0
rw-0
rw-0
rw-0
Table 8-6. P1IE Register Description
Bit
Field
Type
Reset
Description
7-0
P1IE
RW
0h
Port 1 interrupt enable
0b = Corresponding port interrupt disabled
1b = Corresponding port interrupt enabled
8.4.5 P1IFG Register
Port 1 Interrupt Flag Register
Figure 8-5. P1IFG Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
P1IFG
rw-0
rw-0
rw-0
rw-0
Table 8-7. P1IFG Register Description
Bit
Field
Type
Reset
Description
7-0
P1IFG
RW
0h
Port 1 interrupt flag
0b = No interrupt is pending
1b = Interrupt is pending
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8.4.6 P2IES Register
Port 2 Interrupt Edge Select Register
Figure 8-6. P2IES Register
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
P2IES
Table 8-8. P2IES Register Description
Bit
Field
Type
Reset
Description
7-0
P2IES
RW
undefined
Port 2 interrupt edge select
0b = P2IFG flag is set with a low-to-high transition.
1b = P2IFG flag is set with a high-to-low transition.
8.4.7 P2IE Register
Port 2 Interrupt Enable Register
Figure 8-7. P2IE Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
P2IE
rw-0
rw-0
rw-0
rw-0
Table 8-9. P2IE Register Description
Bit
Field
Type
Reset
Description
7-0
P2IE
RW
0h
Port 2 interrupt enable
0b = Corresponding port interrupt disabled
1b = Corresponding port interrupt enabled
8.4.8 P2IFG Register
Port 2 Interrupt Flag Register
Figure 8-8. P2IFG Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
P2IFG
rw-0
rw-0
rw-0
rw-0
Table 8-10. P2IFG Register Description
Bit
Field
Type
Reset
Description
7-0
P2IFG
RW
0h
Port 2 interrupt flag
0b = No interrupt is pending
1b = Interrupt is pending
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8.4.9 PxIN Register
Port x Input Register
Figure 8-9. PxIN Register
7
6
5
4
r
r
r
r
3
2
1
0
r
r
r
r
PxIN
Table 8-11. PxIN Register Description
Bit
Field
Type
Reset
Description
7-0
PxIN
R
undefined
Port x input. Read only.
8.4.10 PxOUT Register
Port x Output Register
Figure 8-10. PxOUT Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
PxOUT
rw
rw
rw
rw
Table 8-12. PxOUT Register Description
Bit
Field
Type
Reset
Description
7-0
PxOUT
RW
undefined
Port x output
When I/O configured to output mode:
0b = Output is low
1b = Output is high
When I/O configured to input mode and pullups/pulldowns enabled:
0b = Pulldown selected
1b = Pullup selected
8.4.11 PxDIR Register
Port x Direction Register
Figure 8-11. PxDIR Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
PxDIR
rw-0
rw-0
rw-0
rw-0
Table 8-13. PxDIR Register Description
Bit
Field
Type
Reset
Description
7-0
PxDIR
RW
0h
Port x direction
0b = Port configured as input
1b = Port configured as output
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8.4.12 PxREN Register
Port x Pullup/Pulldown Resistor Enable Registers
Figure 8-12. PxREN Register
7
6
5
4
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
PxREN
Table 8-14. PxREN Register Description
Bit
Field
Type
Reset
Description
7-0
PxREN
RW
0h
Port x pullup/pulldown resistor enable. When respective port is configured as
input, setting this bit will enable the pullup or pulldown. See Table 8-1
0b = Pullup or pulldown disabled.
1b = Pullup or pulldown enabled.
8.4.13 PxDS Register
Port x Drive Strength Register
Figure 8-13. PxDS Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
PxDS
rw-0
rw-0
rw-0
rw-0
Table 8-15. PxDS Register Description
Bit
Field
Type
Reset
Description
7-0
PxDS
RW
0h
Port x drive strength
0b = Reduced output drive strength
1b = Full output drive strength
8.4.14 PxSEL Register
REGISTERDESCRIPTION
Figure 8-14. PxSEL Register
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
PxSEL
rw-0
rw-0
rw-0
rw-0
Table 8-16. PxSEL Register Description
Bit
Field
Type
Reset
Description
7-0
PxSEL
RW
0h
Port x function selection
0b = I/O function is selected
1b = Peripheral module function is selected
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Chapter 9
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Port Mapping Controller
The port mapping controller allows a flexible mapping of digital functions to port pins. This chapter
describes the port mapping controller.
Topic
9.1
9.2
9.3
362
...........................................................................................................................
Page
Port Mapping Controller Introduction ................................................................. 363
Port Mapping Controller Operation .................................................................... 363
Port Mapping Controller Registers ..................................................................... 365
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9.1
Port Mapping Controller Introduction
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins.
The port mapping controller features are:
• Configuration protected by write access key.
• Default mapping provided for each port pin (device-dependent, the device pinout in the device-specific
data sheet).
• Mapping can be reconfigured during runtime.
• Each output signal can be mapped to several output pins.
9.2
Port Mapping Controller Operation
The port mapping is configured with user software. The setup is discussed in the following sections.
9.2.1 Access
To enable write access to any of the port mapping controller registers, the correct key must be written into
the PMAPKEYID register. The PMAPKEYID register always reads 096A5h. Writing the key 02D52h grants
write access to all port mapping controller registers. Read access is always possible.
If an invalid key is written while write access is granted, any further write accesses are prevented. It is
recommended that the application completes mapping configuration by writing an invalid key.
There is a timeout counter implemented that is incremented with each (assembler) instruction, and when it
counts to 32, the write access is locked again. Any access to the port mapping controller registers resets
the counter. Interrupts should be disabled during the configuration process or the application should take
precautions that the execution of an interrupt service routine does not accidentally cause a permanent
lock of the port mapping registers; for example, by using the reconfiguration capability (see Section 9.2.2).
The access status is reflected in the PMAPLOCK bit.
By default, the port mapping controller allows only one configuration after PUC. A second attempt to
enable write access by writing the correct key is ignored, and the registers remain locked. A PUC is
required to disable the permanent lock again. If it is necessary to reconfigure the mapping during runtime,
the PMAPRECFG bit must be set during the first write access timeslot. If PMAPRECFG is cleared during
later configuration sessions, no more configuration sessions are possible.
9.2.2 Mapping
For each port pin, Px.y, on ports providing the mapping functionality, a mapping register, PxMAPy, is
available. Setting this register to a certain value maps a module's input and output signals to the
respective port pin Px.y. The port pin itself is switched from a general purpose I/O to the selected
peripheral/secondary function by setting the corresponding PxSEL.y bit to 1. If the input or the output
function of the module is used, it is typically defined by the setting the PxDIR.y bit. If PxDIR.y = 0, the pin
is an input, if PxDIR.y = 1, the pin is an output. There are also peripherals (for example, the USCI module)
that control the direction or even other functions of the pin (for example, open drain), and these options
are documented in the mapping table.
With the port mapping functionality the output of a module can be mapped to multiple pins. Also the input
of a module can receive inputs from multiple pins. When mapping multiple inputs onto one function, care
needs to be taken because the input signals are logically ORed together without applying any priority;
therefore, a logic one on any of the inputs results in a logic one at the module. If the PxSEL.y bit is 0, the
corresponding input signal is a logic zero.
The mapping is device-dependent; see the device-specific data sheet for available functions and specific
values. The use of mapping mnemonics to abstract the underlying PxMAPy values is recommended to
allow simple portability between different devices. Table 9-1 shows some examples for mapping
mnemonics of some common peripherals.
All mappable port pins provide the function PM_ANALOG (0FFh). Setting the port mapping register
PxMAPy to PM_ANALOG together with PxSEL.y = 1 disables the output driver and the input Schmitttrigger, to prevent parasitic cross currents when applying analog signals.
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Table 9-1. Examples for Port Mapping Mnemonics and Functions
Input Pin Function
With PxSEL.y = 1 and PxDIR.y = 0
PxMAPy Mnemonic
364
Output Pin Function
With PxSEL.y = 1 and PxDIR.y = 1
PM_NONE
None
DVSS
PM_ACLK
None
ACLK
PM_MCLK
None
MCLK
PM_SMCLK
None
SMCLK
PM_TA0CLK
Timer_A0 clock input
DVSS
PM_TA0CCR0A
Timer_A0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
PM_TA0CCR1A
Timer_A0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
PM_TA0CCR2A
Timer_A0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
PM_TA0CCR3A
Timer_A0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
PM_TA0CCR4A
Timer_A0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
PM_TA1CLK
Timer_A1 clock input
DVSS
PM_TA1CCR0A
Timer_A1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
PM_TA1CCR1A
Timer_A1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
PM_TA1CCR2A
Timer_A1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
PM_TBCLK
Timer_B clock input
DVSS
PM_TBOUTH
Timer_B outputs high impedance
DVSS
PM_TBCCR0A
Timer_B CCR0 capture input CCI0A
TB CCR0 compare output Out0
[direction controlled by Timer_B (TBOUTH)]
PM_TBCCR1A
Timer_B CCR1 capture input CCI1A
TB CCR1 compare output Out1
[direction controlled by Timer_B (TBOUTH)]
PM_TBCCR2A
Timer_B CCR2 capture input CCI2A
TB CCR2 compare output Out2
[direction controlled by Timer_B (TBOUTH)]
PM_TBCCR3A
Timer_B CCR3 capture input CCI3A
TB CCR3 compare output Out3
[direction controlled by Timer_B (TBOUTH)]
PM_TBCCR4A
Timer_B CCR4 capture input CCI4A
TB CCR4 compare output Out4
[direction controlled by Timer_B (TBOUTH)]
PM_TBCCR5A
Timer_B CCR5 capture input CCI3A
TB CCR5 compare output Out5
[direction controlled by Timer_B (TBOUTH)]
PM_TBCCR6A
Timer_B CCR6 capture input CCI4A
TB CCR6 compare output Out6
[direction controlled by Timer_B (TBOUTH)]
PM_UCA0RXD
USCI_A0 UART RXD (direction controlled by USCI - input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (direction controlled by USCI - output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
PM_ANALOG
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying
analog signals
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9.3
Port Mapping Controller Registers
The control register for the port mapping controller are listed in Table 9-2. The mapping registers are listed
in Table 9-3. The mapping registers can also be accessed as words, as shown in Table 9-4.
Table 9-2. Port Mapping Control Registers
Offset
Acronym
Register Name
Type
Reset
00h
PMAPKEYID
Port mapping key register
Read/write
Reset with PUC
02h
PMAPCTL
Port mapping control register
Read/write
Reset with PUC
Table 9-3. Port Mapping Registers for Port Px – Byte Access
Offset
Acronym
Register Name
Type
Reset
00h
PxMAP0
Port Px.0 mapping register
Read/write
Device dependent
01h
PxMAP1
Port Px.1 mapping register
Read/write
Device dependent
02h
PxMAP2
Port Px.2 mapping register
Read/write
Device dependent
03h
PxMAP3
Port Px.3 mapping register
Read/write
Device dependent
04h
PxMAP4
Port Px.4 mapping register
Read/write
Device dependent
05h
PxMAP5
Port Px.5 mapping register
Read/write
Device dependent
06h
PxMAP6
Port Px.6 mapping register
Read/write
Device dependent
07h
PxMAP7
Port Px.7 mapping register
Read/write
Device dependent
Table 9-4. Port Mapping Registers for Port Px – Word Access
Offset
Acronym
Register Name
Type
Reset
00h
PxMAP01
Port Px.0/Port Px.1 mapping register
Read/write
Device dependent
02h
PxMAP23
Port Px.2/Port Px.3 mapping register
Read/write
Device dependent
04h
PxMAP45
Port Px.4/Port Px.5 mapping register
Read/write
Device dependent
06h
PxMAP67
Port Px.6/Port Px.7 mapping register
Read/write
Device dependent
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9.3.1 PMAPKEYID Register
Port Mapping Key Register
Figure 9-1. PMAPKEYID Register
15
14
13
12
11
10
9
8
3
2
1
0
PMAPKEYx
7
6
5
4
PMAPKEYx
Table 9-5. PMAPKEYID Register Description
Bit
Field
Type
Reset
Description
15-0
PMAPKEYx
RW
96A5h
Port write access key. Always reads 096A5h. Must be written 02D52h for write
access to the port mapping registers.
9.3.2 PMAPCTL Register
Port Mapping Control Register
Figure 9-2. PMAPCTL Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
Reserved
Reserved
r0
r0
r0
r0
r0
r0
1
0
PMAPRECFG
PMAPLOCKED
rw-0
r-1
Table 9-6. PMAPCTL Register Description
Bit
Field
Type
Reset
Description
15-2
Reserved
R
0h
Reserved. Always reads as 0.
1
PMAPRECFG
RW
0h
Port mapping reconfiguration control bit
0b = Configuration allowed only once
1b = Allow reconfiguration of port mapping
0
PMAPLOCKED
R
1h
Port mapping lock bit. Read only
0b = Access to mapping registers is granted
1b = Access to mapping registers is locked
9.3.3 PxMAPy Register
Port Px.y Mapping Register
Figure 9-3. PxMAPy Register
7
6
5
4
3
2
1
0
rw-0 (1)
rw-0 (1)
rw-0 (1)
rw-0 (1)
PMAPx
rw-0 (1)
(1)
rw-0 (1)
rw-0 (1)
rw-0 (1)
If not all bits are required to decode all provided functions, the unused bits are r0.
Table 9-7. PxMAPy Register Description
Bit
Field
Type
Reset
Description
7-0
PMAPx
RW
0h
Selects secondary port function. Settings are device-dependent; see the devicespecific data sheet.
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Chapter 10
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Cyclic Redundancy Check (CRC) Module
The cyclic redundancy check (CRC) module provides a signature for a given data sequence. This chapter
describes the operation and use of the CRC module.
NOTE: The CRC module on the CC430F613x, CC430F612x, and CC430F513x devices does not
support the bit-wise reverse feature described in this module description. Registers
CRCDIRB and CRCRESR, along with their respective functionality, are not available.
Topic
10.1
10.2
10.3
10.4
...........................................................................................................................
Cyclic Redundancy Check (CRC) Module Introduction .........................................
CRC Standard and Bit Order .............................................................................
CRC Checksum Generation ..............................................................................
CRC Registers .................................................................................................
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10.1 Cyclic Redundancy Check (CRC) Module Introduction
The CRC module produces a signature for a given sequence of data values. The signature is generated
through a feedback path from data bits 0, 4, 11, and 15 (see Figure 10-1). The CRC signature is based on
the polynomial given in the CRC-CCITT-BR polynomial (see Equation 10) .
f(x) = x16 + x12 + x5 +1
(10)
Data In
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Bit
15
Bit
12
Bit
11
Bit
10
Bit
6
Bit
5
Bit
4
Bit
3
Bit
1
Bit
0
Shift Clock
Figure 10-1. LFSR Implementation of CRC-CCITT Standard, Bit 0 is the MSB of the Result
Identical input data sequences result in identical signatures when the CRC is initialized with a fixed seed
value, whereas different sequences of input data, in general, result in different signatures.
10.2 CRC Standard and Bit Order
The definitions of the various CRC standards were done in the era of main frame computers, and by
convention bit 0 was treated as the MSB. Today, as in most microcontrollers such as the MSP430, bit 0
normally denotes the LSB. In Figure 10-1, the bit convention shown is as given in the original standards
i.e. bit 0 is the MSB. The fact that bit 0 is treated for some as LSB, and for others as MSB, continues to
cause confusion. The CRC16 module therefore provides a bit reversed register pair for CRC16 operations
to support both conventions.
368
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10.3 CRC Checksum Generation
The CRC generator is first initialized by writing a 16-bit word (seed) to the CRC Initialization and Result
(CRCINIRES) register. Any data that should be included into the CRC calculation must be written to the
CRC Data Input (CRCDI or CRCDIRB) register in the same order that the original CRC signature was
calculated. The actual signature can be read from the CRCINIRES register to compare the computed
checksum with the expected checksum.
Signature generation describes a method on how the result of a signature operation can be calculated.
The calculated signature, which is computed by an external tool, is called checksum in the following text.
The checksum is stored in the product's memory and is used to check the correctness of the CRC
operation result.
10.3.1 CRC Implementation
To allow parallel processing of the CRC, the linear feedback shift register (LFSR) functionality is
implemented with an XOR tree. This implementation shows the identical behavior as the LFSR approach
after 8 bits of data are shifted in when the LSB is 'shifted' in first. The generation of a signature calculation
has to be started by writing a seed to the CRCINIRES register to initialize the register. Software or
hardware (for example, DMA) can transfer data to the CRCDI or CRCDIRB register (for example, from
memory). The value in CRCDI or CRCDIRB is then included into the signature, and the result is available
in the signature result registers at the next read access (CRCINIRES and CRCRESR). The signature can
be generated using word or byte data.
If a word data is processed, the lower byte at the even address is used at the first clock (MCLK) cycle.
During the second clock cycle, the higher byte is processed. Thus, it takes two clock cycles to process
word data, while it takes only one clock (MCLK) cycle to process byte data.
Data bytes written to CRCDIRB in word mode or the data byte in byte mode are bit-wise reversed before
the CRC engine adds them to the signature. The bits among each byte are reversed. Data bytes written to
CRCDI in word mode or the data byte in byte mode are not bit reversed before use by the CRC engine.
If the Check Sum itself (with reversed bit order) is included into the CRC operation (as data written to
CRCDI or CRCDIRB), the result in the CRCINIRES and CRCRESR registers must be zero.
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Data In
8-bit or 16-bit
CRC Data In Register CRCDI
8
8
Byte MUX
8
Write to CRCINIRES
16
16
CRC Initialization and Result Register
CRCINIRES
Figure 10-2. Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers
10.3.2 Assembler Examples
10.3.2.1 General Assembler Example
This example demonstrates the operation of the on-chip CRC:
...
PUSH
PUSH
MOV
MOV
MOV
L1 MOV
CMP
JLO
MOV
TST
JNZ
...
POP
POP
370
R4
R5
#StartAddress,R4
#EndAddress,R5
&INIT, &CRCINIRES
@R4+,&CRCDI
R5,R4
L1
&Check_Sum,&CRCDI
&CRCINIRES
CRC_ERROR
R5
R4
Cyclic Redundancy Check (CRC) Module
; Save registers
; StartAddress < EndAddress
;
;
;
;
;
;
;
;
;
;
INIT to CRCINIRES
Item to Data In register
End address reached?
No
Yes, Include checksum
Result = 0?
No, CRCRES <> 0: error
Yes, CRCRES=0:
information ok.
Restore registers
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10.3.2.2 Reference Data Sequence
The details of the implemented CRC algorithm is shown by the following data sequences using word or
byte accesses and the CRC data-in as well as the CRC data-in reverse byte registers:
...
mov
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
#0FFFFh,&CRCINIRES
#00031h,&CRCDI_L
#00032h,&CRCDI_L
#00033h,&CRCDI_L
#00034h,&CRCDI_L
#00035h,&CRCDI_L
#00036h,&CRCDI_L
#00037h,&CRCDI_L
#00038h,&CRCDI_L
#00039h,&CRCDI_L
;
;
;
;
;
;
;
;
;
;
initialize CRC
"1"
"2"
"3"
"4"
"5"
"6"
"7"
"8"
"9"
cmp
#089F6h,&CRCINIRES
jeq
br
&Success
&Error
;
;
;
;
compare result
CRCRESR contains 06F91h
no error
to error handler
mov
mov.w
mov.w
mov.w
mov.w
mov.b
#0FFFFh,&CRCINIRES
#03231h,&CRCDI
#03433h,&CRCDI
#03635h,&CRCDI
#03837h,&CRCDI
#039h, &CRCDI_L
;
;
;
;
;
;
initialize CRC
"1" & "2"
"3" & "4"
"5" & "6"
"7" & "8"
"9"
cmp
#089F6h,&CRCINIRES
jeq
br
&Success
&Error
; compare result
; CRCRESR contains 06F91h
; no error
; to error handler
...
mov
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
mov.b
#0FFFFh,&CRCINIRES
#00031h,&CRCDIRB_L
#00032h,&CRCDIRB_L
#00033h,&CRCDIRB_L
#00034h,&CRCDIRB_L
#00035h,&CRCDIRB_L
#00036h,&CRCDIRB_L
#00037h,&CRCDIRB_L
#00038h,&CRCDIRB_L
#00039h,&CRCDIRB_L
;
;
;
;
;
;
;
;
;
;
initialize CRC
"1"
"2"
"3"
"4"
"5"
"6"
"7"
"8"
"9"
cmp
#029B1h,&CRCINIRES
jeq
br
&Success
&Error
;
;
;
;
compare result
CRCRESR contains 08D94h
no error
to error handler
...
mov
mov.w
mov.w
mov.w
mov.w
mov.b
#0FFFFh,&CRCINIRES
#03231h,&CRCDIRB
#03433h,&CRCDIRB
#03635h,&CRCDIRB
#03837h,&CRCDIRB
#039h, &CRCDIRB_L
;
;
;
;
;
;
initialize CRC
"1" & "2"
"3" & "4"
"5" & "6"
"7" & "8"
"9"
cmp
#029B1h,&CRCINIRES
jeq
br
&Success
&Error
;
;
;
;
compare result
CRCRESR contains 08D94h
no error
to error handler
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10.4 CRC Registers
The CRC module registers are listed in Table 10-1. The base address can be found in the device-specific
data sheet. The address offset is given in Table 10-1.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 10-1. CRC Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
0000h
CRCDI
CRC Data In
Read/write
Word
0000h
Section 10.4.1
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
0000h
Read/write
Byte
00h
Read/write
Byte
00h
Read/write
Word
FFFFh
0004h CRCINIRES_L
Read/write
Byte
FFh
0005h CRCINIRES_H
Read/write
Byte
FFh
Read only
Word
FFFFh
0006h CRCRESR_L
Read/write
Byte
FFh
0007h CRCRESR_H
Read/write
Byte
FFh
0000h CRCDI_L
0001h CRCDI_H
0002h
CRCDIRB
CRC Data In Reverse Byte
(1)
0002h CRCDIRB_L
0003h CRCDIRB_H
0004h
0006h
(1)
372
CRCINIRES
CRCRESR
CRC Initialization and Result
CRC Result Reverse (1)
Section 10.4.2
Section 10.4.3
Section 10.4.4
Not available on MSP430F543x and MSP430F541x non-A versions.
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10.4.1 CRCDI Register
CRC Data In Register
Figure 10-3. CRCDI Register
15
14
13
12
rw-0
rw-0
rw-0
rw-0
7
6
5
4
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
CRCDI
CRCDI
rw-0
rw-0
rw-0
rw-0
Table 10-2. CRCDI Register Description
Bit
Field
Type
Reset
Description
15-0
CRCDI
RW
0h
CRC data in. Data written to the CRCDI register is included to the present
signature in the CRCINIRES register according to the CRC-CCITT standard.
10.4.2 CRCDIRB Register
CRC Data In Reverse Register
Figure 10-4. CRCDIRB Register
15
14
13
12
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
CRCDIRB
rw-0
rw-0
rw-0
rw-0
7
6
5
4
CRCDIRB
rw-0
rw-0
rw-0
rw-0
Table 10-3. CRCDIRB Register Description
Bit
Field
Type
Reset
Description
15-0
CRCDIRB
RW
0h
CRC data in reverse byte. Data written to the CRCDIRB register is included to
the present signature in the CRCINIRES and CRCRESR registers according to
the CRC-CCITT standard. Reading the register returns the register CRCDI
content.
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10.4.3 CRCINIRES Register
CRC Initialization and Result Register
Figure 10-5. CRCINIRES Register
15
14
13
12
rw-1
rw-1
rw-1
rw-1
7
6
5
4
11
10
9
8
rw-1
rw-1
rw-1
rw-1
3
2
1
0
rw-1
rw-1
rw-1
rw-1
CRCINIRES
CRCINIRES
rw-1
rw-1
rw-1
rw-1
Table 10-4. CRCINIRES Register Description
Bit
Field
Type
Reset
Description
15-0
CRCINIRES
RW
FFFFh
CRC initialization and result. This register holds the current CRC result
(according to the CRC-CCITT standard). Writing to this register initializes the
CRC calculation with the value written to it. The value just written can be read
from CRCINIRES register.
10.4.4 CRCRESR Register
CRC Reverse Result Register
Figure 10-6. CRCRESR Register
15
14
13
12
r-1
r-1
r-1
r-1
7
6
5
4
11
10
9
8
r-1
r-1
r-1
r-1
3
2
1
0
r-1
r-1
r-1
r-1
CRCRESR
CRCRESR
r-1
r-1
r-1
r-1
Table 10-5. CRCRESR Register Description
Bit
Field
Type
Reset
Description
15-0
CRCRESR
R
FFFFh
CRC reverse result. This register holds the current CRC result (according to the
CRC-CCITT standard). The order of bits is reversed (for example,
CRCINIRES[15] = CRCRESR[0]) compared to the order of bits in the
CRCINIRES register (see example code).
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Chapter 11
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AES Accelerator
The AES accelerator module performs AES128 encryption or decryption in hardware. This chapter
describes the AES accelerator.
Topic
11.1
11.2
11.3
...........................................................................................................................
Page
AES Accelerator Introduction ............................................................................ 376
AES Accelerator Operation ............................................................................... 377
AES_ACCEL Registers ..................................................................................... 382
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11.1 AES Accelerator Introduction
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys
according to the advanced encryption standard (AES) (FIPS PUB 197) in hardware.
The AES accelerator features are:
• Encryption and decryption according to AES FIPS PUB 197 with 128-bit key
• On-the-fly key expansion for encryption and decryption
• Off-line key generation for decryption
• Byte and word access to key, input, and output data
• AES ready interrupt flag
The AES accelerator block diagram is shown in Figure 11-1.
AESADIN
AESAKEY
Key Buffer
AES128
Encryption/
Decryption
Core
AESADOUT
Figure 11-1. AES Accelerator Block Diagram
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11.2 AES Accelerator Operation
The AES accelerator is configured with user software. The setup and operation is discussed in the
following sections.
Internally, the AES algorithm’s operations are performed on a two-dimensional array of bytes called the
State. For AES-128, the State consists of four rows of bytes, each containing four bytes. The input is
assigned to the State array as illustrated in Figure 11-2, with in[0] being the first data byte written into the
AES accelerator data input register, AESADIN. The encrypt or decrypt operations are then conducted on
the State array, after which its final values can be read from the output with out[0] being the first data byte
read from the AES accelerator data output register, AESADOUT.
Input bytes
State array
Output bytes
in[0]
in[4]
in[8]
in[12]
s[0,0] s[0,1] s[0,2] s[0,3]
out[0] out[4] out[8] out[12]
in[1]
in[5]
in[9]
in[13]
s[1,0] s[1,1] s[1,2] s[1,3]
out[1] out[5] out[9] out[13]
in[2]
in[6]
in[10] in[14]
s[2,0] s[2,1] s[2,2] s[2,3]
out[2] out[6] out[10] out[14]
in[3]
in[7]
in[11] in[15]
s[3,0] s[3,1] s[3,2] s[3,3]
out[3] out[7] out[11] out[15]
Figure 11-2. AES State Array Input and Output
The module allows word and byte access to all data registers, AESAKEY, AESADIN, and AESADOUT.
Word and byte access should not be mixed while reading from or writing into one of the registers.
However, it is possible to write one of the registers using byte access and another using word access.
NOTE:
Access Restrictions
While the AES accelerator is busy (AESBUSY = 1), AESADOUT always reads as zero, the
AESDOUTCNTx counter, the AESDOUTRD flag, and the AESDINWR flag are reset, any
attempt to change AESOPx, AESDINWR, or AESKEYWR is ignored, and writing to
AESAKEY or AESADIN aborts the current operation, the complete module is reset (except
for AESRDYIE and AESOPx), and the AES error flag AESERRFG is set.
AESADIN and AESAKEY are write-only registers and always read as zero.
Writing data into AESADIN influences the content of the corresponding output data; for
example, writing in[0] alters out[0], writing in[1] alters out[1], etc., but interleafed operation is
possible; for example, first reading out[0], then writing in[0], and continuing with reading
out[1], writing in[1], etc.
NOTE: When using a code debugger, the AES module does not stop its operation when program
code is halted or single stepped.
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11.2.1 Encryption
Figure 11-3 shows the encryption process with the cipher being a series of transformations that converts
the plaintext written into the AESADIN register to a ciphertext that can be read from the AESADOUT
register using the cipher key provided via the AESAKEY register.
Cipher Key
(AESAKEY)
Plaintext
(AESADIN)
Initial Key
Initial Round
Round Key 1
Round 1
Round Key 2
Round 2
Round Key 9
Round 9
Round Key 10
Final Round
Cipher
Encryption Process
Ciphertext
(AESADOUT)
Figure 11-3. AES-128 Encryption Process
The steps to perform encryption are:
1. Set AESOPx = 00 to select encryption. Changing the AESOPx bits clears the AESKEYWR flag, and a
new key must be loaded in the next step.
2. Load the 128-bit key into AESAKEY or set the AESKEYWR flag by software, if the key from a previous
operation should be used. When all 16 bytes are written, the AESKEYWR flag indicates completion.
If a key was loaded previously without changing AESOPx, the AESKEYWR flag is cleared with the first
write access to AESAKEY. Loading the key mist be completed before the next step is performed.
3. Load 128-bit data into AESADIN, or set the AESDINWR flag by software if the output data from a
previous operation should be encrypted. When all 16 bytes are written, the AESDINWR flag indicates
completion. The module starts encrypting the presented data when AESDINWR = 1.
4. While the AES module is performing encryption, the AESBUSY bit is 1. The encryption takes
167 MCLK clock cycles. After its completion, the AESRDYIFG is set, and the result can be read from
AESADOUT. When all 16 bytes are read, the AESDOUTRD flag indicates completion.
The AESRDYIFG flag is cleared when reading AESADOUT or writing to AESAKEY or AESADIN.
5. If additional data should be encrypted with the same key loaded in step 2, new data can be written into
AESADIN after the results of the operation on the previous data were read from AESADOUT. When an
additional 16 data bytes are written, the module automatically starts the encryption using the key
loaded in step 2.
When using the output feedback (OFB) cipher block chaining mode, setting the AESDINWR flag is
sufficient to trigger the next encryption, and the module starts the encryption automatically using the
output data from the previous encryption as input data.
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11.2.2 Decryption
Figure 11-4 shows the decryption process with the inverse cipher being a series of transformations that
convert the ciphertext written into the AESADIN register to a plaintext that can be read from the
AESADOUT register using the cipher key provided via the AESAKEY register.
Decrypt Key Generation
Decryption Process – Inverse Cipher
Initial Key
Initial Key
Inverse
Initial Round
Round Key 1
Round Key 1
Inverse Round 1
Round Key 2
Round Key 2
Inverse Round 2
Round Key 9
Round Key 9
Inverse Round 9
Round Key 10
Round Key 10
Inverse
Final Round
Inverse Cipher
Plaintext
(AESADOUT)
Cipher Key
(AESAKEY)
Ciphertext
(AESADIN)
Figure 11-4. AES-128 Decryption Process using AESOPx = 01
The steps to perform decryption are:
1. Set AESOPx = 01 to select decryption using the same key used for encryption. Set AESOPx = 11 if
the first-round key required for decryption (round key 10) is already generated and is loaded in step 2.
Changing the AESOPx bits clears the AESKEYWR flag, and a new key must be loaded in step 2.
2. Load the 128-bit key into AESAKEY, or set the AESKEYWR flag by software, if the key from a
previous operation should be used. When all 16 bytes are written, the AESKEYWR flag indicates
completion.
If a key was loaded previously without changing AESOPx, the AESKEYWR flag is cleared with the first
write access to AESAKEY. Loading the key must be completed before the next step is performed.
3. Load 128-bit data into AESADIN or set the AESDINWR flag by software if the output data from a
previous operation should be decrypted. When all 16 bytes are written, the AESDINWR flag indicates
completion. The module starts decrypting the presented data as soon as AESDINWR = 1.
4. While the AES module is performing decryption, the AESBUSY bit is 1. The decryption takes
214 MCLK clock cycles with AESOPx = 01 and 167 MCLK clock cycles with AESOPx = 11. After its
completion, the AESRDYIFG is set, and the result can be read from AESADOUT. When all 16 bytes
are read the AESDOUTRD flag indicates completion.
The AESRDYIFG flag is cleared when reading AESADOUT or writing to AESAKEY or AESADIN.
5. If additional data should be decrypted with the same key loaded in step 2, new data can be written into
AESADIN after the results of the operation on the previous data were read from AESADOUT. When
additional 16 data bytes are written, the module automatically starts the decryption using the key
loaded in step 2.
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11.2.3 Decryption Key Generation
Figure 11-5 shows the decryption process with a pregenerated decryption key. In this case, the decryption
key is calculated first with AESOPx = 10, then the precalculated key can be used together with the
decryption operation AESOPx = 11.
Decrypt Key Generation
(AESOPx = 10)
Decryption Process – Inverse Cipher
(AESOPx = 11)
Initial Key
Initial Key
Inverse
Initial Round
Round Key 1
Round Key 1
Inverse Round 1
Round Key 2
Round Key 2
Inverse Round 2
Round Key 9
Round Key 9
Inverse Round 9
Round Key 10
Round Key 10
Inverse
Final Round
Pregenerated Key
(AESADOUT)
Pregenerated Key
(AESAKEY)
Ciphertext
(AESADIN)
Inverse Cipher
Plaintext
(AESADOUT)
Cipher Key
(AESAKEY)
Figure 11-5. AES-128 Decryption Process using AESOPx = 10 and 11
To generate the decryption key independent from the actual decryption, the following steps are required:
1. Set AESOPx = 10 to select decryption key generation. Changing the AESOPx bits clears the
AESKEYWR flag, and a new key must be loaded in step 2.
2. Load the 128-bit key into AESAKEY, or set the AESKEYWR flag by software if the key from a previous
operation should be used. When all 16 bytes are written, the AESKEYWR flag indicates completion.
The generation of the first round key required for decryption is started immediately.
3. While the AES module is performing the key generation, the AESBUSY bit is 1. It takes 52 CPU clock
cycles to complete the key generation. After its completion, the AESRDYIFG is set, and the result can
be read from AESADOUT. When all 16 bytes are read, the AESDOUTRD flag indicates completion.
The AESRDYIFG flag is cleared when reading AESADOUT or writing to AESAKEY or AESADIN.
4. If data should be decrypted with the generated key, AESOPx must be set to 11. Then the generated
key must be loaded or, if it was just generated with AESOPx = 10, it is sufficient to set the
AESKEYWR flag by software to indicate that the key is already valid. Afterward, the steps described in
Section 11.2.2 to load the data, etc., must be followed.
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11.2.4 Using the AES Accelerator With Low-Power Modes
The AES accelerator module provides automatic clock activation for MCLK for use with low-power modes.
When the AES accelerator is busy, it automatically activates MCLK, regardless of the control-bit settings
for the clock source. The clock remains active until the AES accelerator completes its operation.
11.2.5 AES Accelerator Interrupts
The AESRDYIFG interrupt flag is set when the AES module completes the selected operation on the
provided data. An interrupt request is generated if AESRDYIE and GIE are also set. AESRDYIFG is
automatically reset if the AES interrupt is serviced, if AESADOUT is read, or if AESADIN or AESAKEY are
written. AESRDYIFG is reset after a PUC or with AESSWRST = 1. AESRDYIE is reset after a PUC but is
not reset by AESSWRST = 1.
11.2.6 Implementing Block Cipher Modes
All block cipher modes can be implemented using the AES accelerator together with software. A separate
application report describes the block cipher modes together with their implementation in software.
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11.3 AES_ACCEL Registers
The AES Accelerator registers are listed in Table 11-1.
Table 11-1. AES_ACCEL Registers
382
Offset
Acronym
Register Name
Type
Access
Reset
Section
000h
AESACTL0
AES accelerator control register 0
Read/write
Word
00h
Section 11.3.1
002h
AESACTL1
AES accelerator control register 1
Read/write
Word
00h
Section 11.3.2
004h
AESASTAT
AES accelerator status register
Read only
Word
00h
Section 11.3.3
006h
AESAKEY
AES accelerator key register
Read/write
Word
00h
Section 11.3.4
008h
AESADIN
AES accelerator data in register
Read/write
Word
00h
Section 11.3.5
00Ah
AESADOUT
AES accelerator data out register
Read/write
Word
00h
Section 11.3.6
00Ch
AESAXDIN
AES accelerator XORed data in
register
Read/write
Word
00h
Section 11.3.7
00Eh
AESAXIN
AES accelerator XORed data in
register (no trigger)
Read/write
Word
00h
Section 11.3.8
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11.3.1 AESACTL0 Register
AES accelerator control register 0
AESACTL0 is shown in Figure 11-6 and described in Table 11-2.
Figure 11-6. AESACTL0 Register
15
14
AESCMEN
13
Reserved
rw-0
r0
7
6
AESSWRST
r0
5
AESCMx
rw-0
r0
12
11
AESRDYIE
AESERRFG
rw-0
rw-0
4
3
Reserved
r0
r0
10
9
8
Reserved
AESRDYIFG
r0
r0
2
1
rw-0
0
AESKLx
rw-0
AESOPx
rw-0
rw-0
rw-0
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
Table 11-2. AESACTL0 Register Description
Bit
Field
Type
Reset
Description
15
AESCMEN
RW
0h
AESCMEN enables the support of the ciphermodes ECB, CBC, OFB and CFB
together with the DMA.
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
0 = No DMA triggers are generated
1 = DMA ciphermode support operation is enabled and the corresponding DMA
triggers are generated.
14-13
Reserved
R
0h
Reserved
12
AESRDYIE
RW
0h
AES ready interrupt enable. AESRDYIE is not reset by AESSWRST = 1.
0 = Interrupt disabled
1 = Interrupt enabled
11
AESERRFG
RW
0h
AES error flag. AESAKEY or AESADIN were written while an AES operation was
in progress. The bit must be cleared by software.
0 = No error
1 = Error occurred
10-9
Reserved
R
0h
Reserved
8
AESRDYIFG
RW
0h
AES ready interrupt flag. Set when the selected AES operation was completed
and the result can be read from AESADOUT. Automatically cleared when
AESADOUT is read or AESAKEY or AESADIN is written.
0 = No interrupt pending
1 = Interrupt pending
7
AESSWRST
RW
0h
AES software reset. Immediately resets the complete AES accelerator module
even when busy except for the AESRDYIE, the AESKLx and the AESOPx bits. It
also clears the (internal) state memory.
The AESSWRST bit is automatically reset and is always read as zero.
0 = No reset
1 = Reset AES accelerator module
6-5
AESCMx
R
0h
AES cipher mode select. These bits are ignored for AESCMEN=0.
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
00 = ECB
01 = CBC
10 = OFB
11 = CFB
4
Reserved
R
0h
Reserved
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Table 11-2. AESACTL0 Register Description (continued)
Bit
Field
Type
Reset
Description
3-2
AESKLx
RW
0h
AES key length. These bits define which of the 3 AES standards is performed.
The AESKLx bits are not reset by AESSWRST = 1.
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
00 = AES128. The keysize is 128 bit.
01 = AES192. The keysize is 192 bit.
10 = AES256. The keysize is 256 bit.
11 = Reserved
1-0
AESOPx
RW
0h
AES operation. The AESOPx bits are not reset by AESSWRST = 1.
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
00 = Encryption
01 = Decryption. The provided key is the same key used for encryption.
10 = Generate first round key required for decryption.
11 = Decryption. The provided key is the first round key required for decryption.
11.3.2 AESACTL1 Register
AES Accelerator Control Register 1
AESACTL1 is shown in Figure 11-7 and described in Table 11-3.
Figure 11-7. AESACTL1 Register
15
14
13
12
11
10
9
8
Reserved
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
AESBLKCNTx
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
Table 11-3. AESACTL1 Register Description
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0
Reserved. Always reads 0.
7-0
AESBLKCNTx
RW
0
Cipher Block Counter. Number of blocks to be encrypted or decrypted with block
cipher modes enabled (AESCMEN=1). Ignored if AESCMEN=0.
The block counter decrements with each performed encryption or decryption.
Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
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11.3.3 AESASTAT Register
AES Accelerator Status Register
AESASTAT is shown in Figure 11-8 and described in Table 11-4.
Figure 11-8. AESASTAT Register
15
14
13
12
11
10
AESDOUTCNTx
r-0
r-0
7
6
r-0
r-0
5
4
AESKEYCNTx
r-0
r-0
9
8
r-0
r-0
AESDINCNTx
r-0
r-0
r-0
r-0
3
2
1
0
AESDOUTRD
AESDINWR
AEKEYWR
AESBUSY
r-0
rw-0
rw-0
r-0
Table 11-4. AESASTAT Register Description
Bit
Field
Type
Reset
Description
15-12
AESDOUTCNTx
R
0h
Bytes read via AESADOUT. Reset when AESDOUTRD is reset.
If AESDOUTCNTx = 0 and AESDOUTRD = 0, no bytes were read.
If AESDOUTCNTx = 0 and AESDOUTRD = 1, all bytes were read.
11-8
AESDINCNTx
R
0h
Bytes written via AESADIN, AESAXDIN or AESAXIN. Reset when AESDINWR is
reset.
If AESDINCNTx = 0 and AESDINWR = 0, no bytes were written.
If AESDINCNTx = 0 and AESDINWR = 1, all bytes were written.
7-4
AESKEYCNTx
R
0h
Bytes written via AESAKEY for AESKLx=00, words written via AESAKEY if
AESKLx=01,10,11. Reset when AESKEYWR is reset.
If AESKEYCNTx = 0 and AESKEYWR = 0, no bytes were written.
If AESKEYCNTx = 0 and AESKEYWR = 1, all bytes were written.
3
AESDOUTRD
R
0h
All 16 bytes read from AESADOUT.
AESDOUTRD is reset by PUC, AESSWRST, an error condition, changing
AESOPx, changing AESKLx, when the AES accelerator is busy, and when the
output data is read again.
0 = Not all bytes read
1 = All bytes read
2
AESDINWR
RW
0h
All 16 bytes written to AESADIN, AESAXDIN or AESAXIN. This bit can be
modified by software only if AESCMEN=0. Changing its state by software also
resets the AESDINCNTx bits.
AESDINWR is reset by PUC, AESSWRST, an error condition, changing
AESOPx, changing AESKLx, the start to (over)write the data, and when the AES
accelerator is busy. Because it is reset when AESOPx or AESKLx is changed it
can be set by software again to indicate that the current data is still valid.
0 = Not all bytes written
1 = All bytes written
1
AESKEYWR
RW
0h
All 16 bytes written to AESAKEY. This bit can be modified by software but it
must not be reset by software (1→0) if AESCMEN=1. Changing its state by
software also resets the AESKEYCNTx bits.
AESKEYWR is reset by PUC, AESSWRST, an error condition, changing
AESOPx, changing AESKLx, and the start to (over)write a new key. Because it is
reset when AESOPx is changed it can be set by software again to indicate that
the loaded key is still valid.
0 = Not all bytes written
1 = All bytes written
0
AESBUSY
R
0h
AES accelerator module busy; encryption, decryption, or key generation in
progress.
0 = Not busy
1 = Busy
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11.3.4 AESAKEY Register
AES Accelerator Key Register
AESAKEY is shown in Figure 11-9 and described in Table 11-5.
Figure 11-9. AESAKEY Register
15
14
13
12
11
10
9
8
AESKEY1x (Key Byte n+1)
w-0
w-0
w-0
7
6
5
w-0
w-0
w-0
w-0
w-0
4
3
2
1
0
w-0
w-0
w-0
AESKEY0x (Key Byte n)
w-0
w-0
w-0
w-0
w-0
Table 11-5. AESAKEY Register Description
Bit
Field
Type
Reset
Description
15-8
AESKEY1x
W
0
AES key byte n+1 when AESAKEY is written as word.
Do not use these bits for byte access.
Do not mix word and byte access.
Always reads as zero.
The key is reset by PUC or by AESSWRST = 1.
7-0
AESKEY0x
W
0
AES key byte n when AESAKEY is written as word.
AES next key byte when AESAKEY_L is written as byte.
Do not mix word and byte access.
Always reads as zero.
The key is reset by PUC or by AESSWRST = 1.
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11.3.5 AESADIN Register
AES Accelerator Data In Register
AESADIN is shown in Figure 11-10 and described in Table 11-6.
Figure 11-10. AESADIN Register
15
14
13
12
11
10
9
8
AESDIN1x (DIN Byte n+1)
w-0
w-0
w-0
7
6
5
w-0
w-0
w-0
w-0
w-0
4
3
2
1
0
w-0
w-0
w-0
AESDIN0x (DIN Byte n)
w-0
w-0
w-0
w-0
w-0
Table 11-6. AESADIN Register Description
Bit
Field
Type
Reset
Description
15-8
AESDIN1x
W
0
AES data in byte n+1 when AESADIN is written as word.
Do not use these bits for byte access.
Do not mix word and byte access.
Always reads as zero.
7-0
AESDIN0x
W
0
AES data in byte n when AESADIN is written as word.
AES next data in byte when AESADIN_L is written as byte.
Do not mix word and byte access.
Always reads as zero.
11.3.6 AESADOUT Register
AES Accelerator Data Out Register
AESADOUT is shown in Figure 11-11 and described in Table 11-7.
Figure 11-11. AESADOUT Register
15
14
13
12
11
10
9
8
2
1
0
AESDOUT1x (DOUT Byte n+1)
7
6
5
4
3
AESDOUT0x (DOUT Byte n)
Table 11-7. AESADOUT Register Description
Bit
Field
Type
Reset
Description
15-8
AESDOUT1x
R
0
AES data out byte n+1 when AESADOUT is read as word.
Do not use these bits for byte access.
Do not mix word and byte access.
7-0
AESDOUT0x
R
0
AES data out byte n when AESADOUT is read as word.
AES next data out byte when AESADOUT_L is read as byte.
Do not mix word and byte access.
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11.3.7 AESAXDIN Register
AES accelerator XORed data in register
AESAXDIN is shown in Figure 11-12 and described in Table 11-8.
Figure 11-12. AESAXDIN Register
15
14
13
12
11
10
9
8
AESXDIN1x (XDIN Byte n+1)
w-0
w-0
w-0
7
6
5
w-0
w-0
w-0
w-0
w-0
4
3
2
1
0
w-0
w-0
w-0
AESXDIN0x (XDIN Byte n)
w-0
w-0
w-0
w-0
w-0
Table 11-8. AESAXDIN Register Description
Bit
Field
Type
Reset
Description
15-8
AESXDIN1x
W
0
AES data in byte n+1 when AESAXDIN is written as word.
Do not use these bits for byte access.
Do not mix word and byte access.
Always reads as zero.
7-0
AESXDIN0x
W
0
AES data in byte n when AESAXDIN is written as word.
AES next data in byte when AESAXDIN_L is written as byte.
Do not mix word and byte access.
Always reads as zero.
11.3.8 AESAXIN Register
AES accelerator XORed data in register (no trigger)
AESAXIN is shown in Figure 11-13 and described in Table 11-9.
Figure 11-13. AESAXIN Register
15
14
13
12
11
10
9
8
AESXIN1x (DIN Byte n+1)
w-0
w-0
w-0
7
6
5
w-0
w-0
w-0
w-0
w-0
4
3
2
1
0
w-0
w-0
w-0
AESXIN0x (DIN Byte n)
w-0
w-0
w-0
w-0
w-0
Table 11-9. AESAXIN Register Description
Bit
Field
Type
Reset
Description
15-8
AESXIN1x
W
0
AES data in byte n+1 when AESAXIN is written as word.
Do not use these bits for byte access.
Do not mix word and byte access.
Always reads as zero.
7-0
AESXIN0x
W
0
AES data in byte n when AESAXIN is written as word.
AES next data in byte when AESAXIN_L is written as byte.
Do not mix word and byte access.
Always reads as zero.
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Chapter 12
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Watchdog Timer (WDT_A)
The watchdog timer is a 32-bit timer that can be used as a watchdog or as an interval timer. This chapter
describes the watchdog timer. The enhanced watchdog timer, WDT_A, is implemented in all devices.
Topic
12.1
12.2
12.3
...........................................................................................................................
Page
WDT_A Introduction ......................................................................................... 390
WDT_A Operation ............................................................................................ 392
WDT_A Registers ............................................................................................ 394
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12.1 WDT_A Introduction
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart
after a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be configured as an interval timer and
can generate interrupts at selected time intervals.
Features of the watchdog timer module include:
• Eight software-selectable time intervals
• Watchdog mode
• Interval mode
• Password-protected access to Watchdog Timer Control ( WDTCTL) register
• Selectable clock source
• Can be stopped to conserve power
• Clock fail-safe feature
The watchdog timer block diagram is shown in Figure 12-1.
NOTE:
Watchdog timer powers up active.
After a PUC, the WDT_A module is automatically configured in the watchdog mode with an
initial ~32-ms reset interval using the SMCLK. The user must setup or halt the WDT_A prior
to the expiration of the initial reset interval.
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32Bit WDT extension
00
01
Int.
Flag
WDTQn
10
11
Q23
Q19
00
01
10
11
PUC
0
16-bit
Counter
1
CLK
1
MDB
MSB
Q27
0
Pulse
Generator
WDTCTL
Q31
0
1
Q15
Q13
1
Password
Compare
Q9
Q6
Clear
16-bit
Counter
(Asyn)
CLK
0
1
0
EQU
Write Enable
Low Byte
EQU
SMCLK
00
ACLK
01
VLOCLK
10
X_CLK
11
R/W
WDTHOLD
WDTSSEL1
WDTSSEL0
WDTTMSEL
WDTCNTCL
WDTIS2
WDTIS1
WDTIS0
LSB
X_CLK request
Clock
Request
Logic
SMCLK request
ACLK request
VLOCLK request
Figure 12-1. Watchdog Timer Block Diagram
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12.2 WDT_A Operation
The watchdog timer module can be configured as either a watchdog or interval timer with the WDTCTL
register. WDTCTL is a 16-bit password-protected read/write register. Any read or write access must use
word instructions and write accesses must include the write password 05Ah in the upper byte. Any write to
WDTCTL with any value other than 05Ah in the upper byte is a password violation and triggers a PUC
system reset, regardless of timer mode. Any read of WDTCTL reads 069h in the upper byte. Byte reads
on WDTCTL high or low part result in the value of the low byte. Writing byte wide to upper or lower parts
of WDTCTL results in a PUC.
12.2.1 Watchdog Timer Counter (WDTCNT)
The WDTCNT is a 32-bit up counter that is not directly accessible by software. The WDTCNT is controlled
and its time intervals are selected through the Watchdog Timer Control (WDTCTL) register. The WDTCNT
can be sourced from SMCLK, ACLK, VLOCLK, or X_CLK on some devices. The clock source is selected
with the WDTSSEL bits. The timer interval is selected with the WDTIS bits.
12.2.2 Watchdog Mode
After a PUC condition, the WDT module is configured in the watchdog mode with an initial ~32-ms reset
interval using the SMCLK. The user must setup, halt, or clear the watchdog timer prior to the expiration of
the initial reset interval or another PUC is generated. When the watchdog timer is configured to operate in
watchdog mode, either writing to WDTCTL with an incorrect password, or expiration of the selected time
interval triggers a PUC. A PUC resets the watchdog timer to its default condition.
12.2.3 Interval Timer Mode
Setting the WDTTMSEL bit to 1 selects the interval timer mode. This mode can be used to provide
periodic interrupts. In interval timer mode, the WDTIFG flag is set at the expiration of the selected time
interval. A PUC is not generated in interval timer mode at expiration of the selected timer interval, and the
WDTIFG enable bit WDTIE remains unchanged.
When the WDTIE bit and the GIE bit are set, the WDTIFG flag requests an interrupt. The WDTIFG
interrupt flag is automatically reset when its interrupt request is serviced, or it may be reset by software.
The interrupt vector address in interval timer mode is different from that in watchdog mode.
NOTE:
Modifying the watchdog timer
The watchdog timer interval should be changed together with WDTCNTCL = 1 in a single
instruction to avoid an unexpected immediate PUC or interrupt. The watchdog timer should
be halted before changing the clock source to avoid a possible incorrect interval.
12.2.4 Watchdog Timer Interrupts
The watchdog timer uses two bits in the SFRs for interrupt control:
• WDT interrupt flag, WDTIFG, located in SFRIFG1.0
• WDT interrupt enable, WDTIE, located in SFRIE1.0
When using the watchdog timer in the watchdog mode, the WDTIFG flag sources a reset vector
interrupt.The WDTIFG will self clear upon a watchdog timeout event. The SYSRSTIV can be read to
determine if the reset was caused by a watchdog timeout event.
When using the watchdog timer in interval timer mode, the WDTIFG flag is set after the selected time
interval and requests a watchdog timer interval timer interrupt if the WDTIE and the GIE bits are set. The
interval timer interrupt vector is different from the reset vector used in watchdog mode. In interval timer
mode, the WDTIFG flag is reset automatically when the interrupt is serviced, or can be reset with
software.
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12.2.5 Clock Fail-Safe Feature
The WDT_A provides a fail-safe clocking feature, ensuring the clock to the WDT_A cannot be disabled
while in watchdog mode. This means that the low-power modes may be affected by the choice for the
WDT_A clock.
If SMCLK or ACLK fails as the WDT_A clock source, VLOCLK is automatically selected as the WDT_A
clock source.
When the WDT_A module is used in interval timer mode, there is no fail-safe feature within WDT_A for
the clock source.
12.2.6 Operation in Low-Power Modes
The devices have several low-power modes. Different clock signals are available in different low-power
modes. The requirements of the application and the type of clocking that is used determine how the
WDT_A should be configured. For example, the WDT_A should not be configured in watchdog mode with
a clock source that is originally sourced from DCO, XT1 in high-frequency mode, or XT2 via SMCLK or
ACLK, if the user wants to use low-power mode 3. In this case, SMCLK or ACLK would remain enabled,
increasing the current consumption of LPM3. When the watchdog timer is not required, the WDTHOLD bit
can be used to hold the WDTCNT, reducing power consumption.
12.2.7 Software Examples
Any write operation to WDTCTL must be a word operation with 05Ah (WDTPW) in the upper byte:
; Periodically clear an active watchdog
MOV #WDTPW+WDTIS2+WDTIS1+WDTCNTCL,&WDTCTL
;
; Change watchdog timer interval
MOV #WDTPW+WDTCNTCL+SSEL,&WDTCTL
;
; Stop the watchdog
MOV #WDTPW+WDTHOLD,&WDTCTL
;
; Change WDT to interval timer mode, clock/8192 interval
MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS2+WDTIS0,&WDTCTL
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12.3 WDT_A Registers
The watchdog timer module registers are listed in Table 12-1. The base address for the watchdog timer
module registers and special function registers (SFRs) can be found in device-specific data sheets. The
address offset is given in Table 12-1.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 12-1. WDT_A Registers
394
Offset
Acronym
Register Name
Type
Access
Reset
Section
0Ch
WDTCTL
Watchdog Timer Control
Read/write
Word
6904h
Section 12.3.1
0Ch
WDTCTL_L
Read/write
Byte
04h
0Dh
WDTCTL_H
Read/write
Byte
69h
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12.3.1 WDTCTL Register
Watchdog Timer Control Register
Figure 12-2. WDTCTL Register
15
14
13
12
11
10
2
9
8
1
0
WDTPW
7
6
WDTHOLD
rw-0
5
WDTSSEL
rw-0
rw-0
4
3
WDTTMSEL
WDTCNTCL
rw-0
r0(w)
WDTIS
rw-1
rw-0
rw-0
Table 12-2. WDTCTL Register Description
Bit
Field
Type
Reset
Description
15-8
WDTPW
RW
69h
Watchdog timer password. Always read as 069h. Must be written as 5Ah; if any
other value is written, a PUC is generated.
7
WDTHOLD
RW
0h
Watchdog timer hold. This bit stops the watchdog timer. Setting WDTHOLD = 1
when the WDT is not in use conserves power.
0b = Watchdog timer is not stopped.
1b = Watchdog timer is stopped.
6-5
WDTSSEL
RW
0h
Watchdog timer clock source select
00b = SMCLK
01b = ACLK
10b = VLOCLK
11b = X_CLK; VLOCLK in devices that do not support X_CLK
4
WDTTMSEL
RW
0h
Watchdog timer mode select
0b = Watchdog mode
1b = Interval timer mode
3
WDTCNTCL
RW
0h
Watchdog timer counter clear. Setting WDTCNTCL = 1 clears the count value to
0000h. WDTCNTCL is automatically reset.
0b = No action
1b = WDTCNT = 0000h
2-0
WDTIS
RW
4h
Watchdog timer interval select. These bits select the watchdog timer interval to
set the WDTIFG flag and/or generate a PUC.
000b = Watchdog clock source /(2^31) (18h:12m:16s at 32.768 kHz)
001b = Watchdog clock source /(2^27) (01h:08m:16s at 32.768 kHz)
010b = Watchdog clock source /(2^23) (00h:04m:16s at 32.768 kHz)
011b = Watchdog clock source /(2^19) (00h:00m:16s at 32.768 kHz)
100b = Watchdog clock source /(2^15) (1 s at 32.768 kHz)
101b = Watchdog clock source /(2^13) (250 ms at 32.768 kHz)
110b = Watchdog clock source /(2^9) (15.625 ms at 32.768 kHz)
111b = Watchdog clock source /(2^6) (1.95 ms at 32.768 kHz)
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Chapter 13
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Timer_A
Timer_A is a 16-bit timer/counter with multiple capture/compare registers. There can be multiple Timer_A
modules on a given device (see the device-specific data sheet). This chapter describes the operation and
use of the Timer_A module.
Topic
13.1
13.2
13.3
396
Timer_A
...........................................................................................................................
Page
Timer_A Introduction ....................................................................................... 397
Timer_A Operation ........................................................................................... 399
Timer_A Registers ........................................................................................... 411
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13.1 Timer_A Introduction
Timer_A is a 16-bit timer/counter with up to seven capture/compare registers. Timer_A can support
multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Timer_A features include:
• Asynchronous 16-bit timer/counter with four operating modes
• Selectable and configurable clock source
• Up to seven configurable capture/compare registers
• Configurable outputs with pulse width modulation (PWM) capability
• Asynchronous input and output latching
• Interrupt vector register for fast decoding of all Timer_A interrupts
The block diagram of Timer_A is shown in Figure 13-1.
NOTE:
Use of the word count
Count is used throughout this chapter. It means the counter must be in the process of
counting for the action to take place. If a particular value is directly written to the counter, an
associated action does not take place.
NOTE:
Nomenclature
There may be multiple instantiations of Timer_A on a given device. The prefix TAx is used,
where x is a greater than equal to zero indicating the Timer_A instantiation. For devices with
one instantiation, x = 0. The suffix n, where n = 0 to 6, represents the specific
capture/compare registers associated with the Timer_A instantiation.
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Timer Block
TASSEL
ID
2
TAxCLK
00
ACLK
01
SMCLK
10
INCLK
11
IDEX
2
Timer Clock
3
Divider
/1.../8
Divider
/1/2/4/8
MC
15
0
2
16-bit Timer
TAxR
Clear
Count
Mode
RC
EQU0
Set TAxCTL
TAIFG
TACLR
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCIS
CM
2
2
CCI6A
00
CCI6B
01
GND
10
VCC
11
logic
COV
SCS
Capture
Mode
Timer Clock
15
0
0
Sync
TAxCCR6
1
Compararator 6
CCI
EQU6
SCCI
Y
A
EN
CAP
0
1
Set TAxCCR6
CCIFG
OUT
EQU0
Output
Unit4
D Set Q
Timer Clock
3
OUT6 Signal
Reset
POR
OUTMOD
Figure 13-1. Timer_A Block Diagram
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13.2 Timer_A Operation
The Timer_A module is configured with user software. The setup and operation of Timer_A are discussed
in the following sections.
13.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TAxR, increments or decrements (depending on mode of operation) with
each rising edge of the clock signal. TAxR can be read or written with software. Additionally, the timer can
generate an interrupt when it overflows.
TAxR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and count
direction for up/down mode.
NOTE:
Modifying Timer_A registers
It is recommended to stop the timer before modifying its operation (with exception of the
interrupt enable, interrupt flag, and TACLR) to avoid errant operating conditions.
When the timer clock is asynchronous to the CPU clock, any read from TAxR should occur
while the timer is not operating or the results may be unpredictable. Alternatively, the timer
may be read multiple times while operating, and a majority vote taken in software to
determine the correct reading. Any write to TAxR takes effect immediately.
13.2.1.1 Clock Source Select and Divider
The timer clock can be sourced from ACLK, SMCLK, or externally via TAxCLK or INCLK. The clock
source is selected with the TASSEL bits. The selected clock source may be passed directly to the timer or
divided by 2, 4, or 8, using the ID bits. The selected clock source can be further divided by 2, 3, 4, 5, 6, 7,
or 8 using the TAIDEX bits. The timer clock divider logic is reset when TACLR is set.
NOTE:
Timer_A dividers
After programming ID or TAIDEX bits, set the TACLR bit. This clears the contents of TAxR
and resets the clock divider logic to a defined state. The clock dividers are implemented as
down counters. Therefore, when the TACLR bit is cleared, the timer clock immediately
begins clocking at the first rising edge of the Timer_A clock source selected with the
TASSEL bits and continues clocking at the divider settings set by the ID and TAIDEX bits.
13.2.2 Starting the Timer
The timer may be started or restarted in the following ways:
• The timer counts when MC > { 0 } and the clock source is active.
• When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TAxCCR0. The
timer may then be restarted by writing a nonzero value to TAxCCR0. In this scenario, the timer starts
incrementing in the up direction from zero.
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13.2.3 Timer Mode Control
The timer has four modes of operation: stop, up, continuous, and up/down (see Table 13-1). The
operating mode is selected with the MC bits.
Table 13-1. Timer Modes
MC
Mode
Description
00
Stop
The timer is halted.
01
Up
The timer repeatedly counts from zero to the value of TAxCCR0
10
Continuous
The timer repeatedly counts from zero to 0FFFFh.
11
Up/down
The timer repeatedly counts from zero up to the value of TAxCCR0 and back down to zero.
13.2.3.1 Up Mode
The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly
counts up to the value of compare register TAxCCR0, which defines the period (see Figure 13-2). The
number of timer counts in the period is TAxCCR0 + 1. When the timer value equals TAxCCR0, the timer
restarts counting from zero. If up mode is selected when the timer value is greater than TAxCCR0, the
timer immediately restarts counting from zero.
TAxCCR0
Figure 13-2. Up Mode
The TAxCCR0 CCIFG interrupt flag is set when the timer counts to the TAxCCR0 value. The TAIFG
interrupt flag is set when the timer counts from TAxCCR0 to zero. Figure 13-3 shows the flag set cycle.
Timer Clock
Timer
CCR0-1
CCR0
0h
1h
CCR0-1
CCR0
0h
Set TAxCTL TAIFG
Set TAxCCR0 CCIFG
Figure 13-3. Up Mode Flag Setting
13.2.3.1.1 Changing Period Register TAxCCR0
When changing TAxCCR0 while the timer is running, if the new period is greater than or equal to the old
period or greater than the current count value, the timer counts up to the new period. If the new period is
less than the current count value, the timer rolls to zero. However, one additional count may occur before
the counter rolls to zero.
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13.2.3.2 Continuous Mode
In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in
Figure 13-4. The capture/compare register TAxCCR0 works the same way as the other capture/compare
registers.
0FFFFh
0h
Figure 13-4. Continuous Mode
The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero. Figure 13-5 shows the flag set
cycle.
Timer Clock
Timer
FFFEh
0h
FFFFh
1h
FFFEh
FFFFh
0h
Set TAxCTL TAIFG
Figure 13-5. Continuous Mode Flag Setting
13.2.3.3 Use of Continuous Mode
The continuous mode can be used to generate independent time intervals and output frequencies. Each
time an interval is completed, an interrupt is generated. The next time interval is added to the TAxCCRn
register in the interrupt service routine. Figure 13-6 shows two separate time intervals, t0 and t1, being
added to the capture/compare registers. In this usage, the time interval is controlled by hardware, not
software, without impact from interrupt latency. Up to n (where n = 0 to 6), independent time intervals or
output frequencies can be generated using capture/compare registers.
TAxCCR1b
TAxCCR0b
TAxCCR1c
TAxCCR0c
TAxCCR0d
0FFFFh
TAxCCR1a
TAxCCR1d
TAxCCR0a
t0
t0
t1
t0
t1
t1
Figure 13-6. Continuous Mode Time Intervals
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Time intervals can be produced with other modes as well, where TAxCCR0 is used as the period register.
Their handling is more complex since the sum of the old TAxCCRn data and the new period can be higher
than the TAxCCR0 value. When the previous TAxCCRn value plus tx is greater than the TAxCCR0 data,
the TAxCCR0 value must be subtracted to obtain the correct time interval.
13.2.3.4 Up/Down Mode
The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical
pulse generation is needed. The timer repeatedly counts up to the value of compare register TAxCCR0
and back down to zero (see Figure 13-7). The period is twice the value in TAxCCR0.
0FFFFh
TAxCCR0
0h
Figure 13-7. Up/Down Mode
The count direction is latched. This allows the timer to be stopped and then restarted in the same direction
it was counting before it was stopped. If this is not desired, the TACLR bit must be set to clear the
direction. The TACLR bit also clears the TAxR value and the timer clock divider.
In up/down mode, the TAxCCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once
during a period, separated by one-half the timer period. The TAxCCR0 CCIFG interrupt flag is set when
the timer counts from TAxCCR0-1 to TAxCCR0, and TAIFG is set when the timer completes counting
down from 0001h to 0000h. Figure 13-8 shows the flag set cycle.
Timer Clock
Timer
CCR0-1
CCR0
CCR0-1
CCR0-2
1h
0h
Up/Down
Set TAxCTL TAIFG
Set TAxCCR0 CCIFG
Figure 13-8. Up/Down Mode Flag Setting
13.2.3.4.1 Changing Period Register TAxCCR0
When changing TAxCCR0 while the timer is running and counting in the down direction, the timer
continues its descent until it reaches zero. The new period takes effect after the counter counts down to
zero.
When the timer is counting in the up direction, and the new period is greater than or equal to the old
period or greater than the current count value, the timer counts up to the new period before counting
down.
When the timer is counting in the up direction and the new period is less than the current count value, the
timer begins counting down. However, one additional count may occur before the counter begins counting
down.
402
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13.2.3.5 Use of Up/Down Mode
The up/down mode supports applications that require dead times between output signals (see section
Timer_A Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must
never be in a high state simultaneously. In the example shown in Figure 13-9, the tdead is:
tdead = ttimer × (TAxCCR1 – TAxCCR2)
Where:
tdead = Time during which both outputs need to be inactive
ttimer = Cycle time of the timer clock
TAxCCRn = Content of capture/compare register n
The TAxCCRn registers are not buffered. They update immediately when written to. Therefore, any
required dead time is not maintained automatically.
0FFFFh
TAxCCR0
TAxCCR1
TAxCCR2
0h
Dead Time
Output Mode 6: Toggle/Set
Output Mode 2: Toggle/Reset
EQU1
EQU1
EQU1
EQU1
TAIFG
EQU0
EQU0
EQU2 EQU2
EQU2
EQU2
TAIFG
Interrupt Events
Figure 13-9. Output Unit in Up/Down Mode
13.2.4 Capture/Compare Blocks
Up to seven identical capture/compare blocks, TAxCCRn (where n = 0 to 7), are present in Timer_A. Any
of the blocks may be used to capture the timer data or to generate time intervals.
13.2.4.1 Capture Mode
The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used
for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to
external pins or internal signals and are selected with the CCIS bits. The CM bits select the capture edge
of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a
capture occurs:
• The timer value is copied into the TAxCCRn register.
• The interrupt flag CCIFG is set.
The input signal level can be read at any time via the CCI bit. Devices may have different signals
connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals.
The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS
bit synchronizes the capture with the next timer clock. Setting the SCS bit to synchronize the capture
signal with the timer clock is recommended (see Figure 13-10).
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Timer Clock
Timer
n–2
n–1
n
n+1
n+3
n+2
n+4
CCI
Capture
Set TAxCCRn CCIFG
Figure 13-10. Capture Signal (SCS = 1)
NOTE:
Changing Capture Inputs
Changing capture inputs while in capture mode may cause unintended capture events. To
avoid this scenario, capture inputs should only be changed when capture mode is disabled
(CM = {0} or CAP = 0).
Overflow logic is provided in each capture/compare register to indicate if a second capture was performed
before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 1311. COV must be reset with software.
Idle
Capture
No
Capture
Taken
Capture Read
Read
Taken
Capture
Capture
Taken
Capture
Capture Read and No Capture
Capture
Clear Bit COV
in Register TAxCCTLn
Second
Capture
Taken
COV = 1
Idle
Figure 13-11. Capture Cycle
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13.2.4.1.1 Capture Initiated by Software
Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then
sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a
capture each time CCIS0 changes state:
MOV
#CAP+SCS+CCIS1+CM_3,&TA0CCTL1
XOR
#CCIS0,&TA0CCTL1
NOTE:
; Setup TA0CCTL1, synch. capture mode
; Event trigger on both edges of capture input.
; TA0CCR1 = TA0R
Capture Initiated by Software
In general, changing capture inputs while in capture mode may cause unintended capture
events. For this scenario, switching the capture input between VCC and GND, disabling the
capture mode is not required.
13.2.4.2 Compare Mode
The compare mode is selected when CAP = 0. The compare mode is used to generate PWM output
signals or interrupts at specific time intervals. When TAxR counts to the value in a TAxCCRn, where n
represents the specific capture/compare register.
• Interrupt flag CCIFG is set.
• Internal signal EQUn = 1.
• EQUn affects the output according to the output mode.
• The input signal CCI is latched into SCCI.
13.2.5 Output Unit
Each capture/compare block contains an output unit. The output unit is used to generate output signals,
such as PWM signals. Each output unit has eight operating modes that generate signals based on the
EQU0 and EQUn signals.
13.2.5.1 Output Modes
The output modes are defined by the OUTMOD bits and are described in Table 13-2. The OUTn signal is
changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7
are not useful for output unit 0 because EQUn = EQU0.
Table 13-2. Output Modes
OUTMODx
Mode
Description
000
Output
The output signal OUTn is defined by the OUT bit. The OUTn signal updates immediately
when OUT is updated.
001
Set
The output is set when the timer counts to the TAxCCRn value. It remains set until a reset
of the timer, or until another output mode is selected and affects the output.
010
Toggle/Reset
The output is toggled when the timer counts to the TAxCCRn value. It is reset when the
timer counts to the TAxCCR0 value.
011
Set/Reset
The output is set when the timer counts to the TAxCCRn value. It is reset when the timer
counts to the TAxCCR0 value.
100
Toggle
The output is toggled when the timer counts to the TAxCCRn value. The output period is
double the timer period.
101
Reset
The output is reset when the timer counts to the TAxCCRn value. It remains reset until
another output mode is selected and affects the output.
110
Toggle/Set
The output is toggled when the timer counts to the TAxCCRn value. It is set when the timer
counts to the TAxCCR0 value.
111
Reset/Set
The output is reset when the timer counts to the TAxCCRn value. It is set when the timer
counts to the TAxCCR0 value.
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13.2.5.1.1 Output Example—Timer in Up Mode
The OUTn signal is changed when the timer counts up to the TAxCCRn value and rolls from TAxCCR0 to
zero, depending on the output mode. An example is shown in Figure 13-12 using TAxCCR0 and
TAxCCR1.
0FFFFh
TAxCCR0
TAxCCR1
0h
Output Mode 1: Set
Output Mode 2: Toggle/Reset
Output Mode 3: Set/Reset
Output Mode 4: Toggle
Output Mode 5: Reset
Output Mode 6: Toggle/Set
Output Mode 7: Reset/Set
EQU0
TAIFG
EQU1
EQU0
TAIFG
EQU1
EQU0
TAIFG
Interrupt Events
Figure 13-12. Output Example – Timer in Up Mode
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13.2.5.1.2 Output Example – Timer in Continuous Mode
The OUTn signal is changed when the timer reaches the TAxCCRn and TAxCCR0 values, depending on
the output mode. An example is shown in Figure 13-13 using TAxCCR0 and TAxCCR1.
0FFFFh
TAxCCR0
TAxCCR1
0h
Output Mode 1: Set
Output Mode 2: Toggle/Reset
Output Mode 3: Set/Reset
Output Mode 4: Toggle
Output Mode 5: Reset
Output Mode 6: Toggle/Set
Output Mode 7: Reset/Set
TAIFG
EQU1
EQU0 TAIFG
EQU1
EQU0
Interrupt Events
Figure 13-13. Output Example – Timer in Continuous Mode
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13.2.5.1.3 Output Example – Timer in Up/Down Mode
The OUTn signal changes when the timer equals TAxCCRn in either count direction and when the timer
equals TAxCCR0, depending on the output mode. An example is shown in Figure 13-14 using TAxCCR0
and TAxCCR2.
0FFFFh
TAxCCR0
TAxCCR2
0h
Output Mode 1: Set
Output Mode 2: Toggle/Reset
Output Mode 3: Set/Reset
Output Mode 4: Toggle
Output Mode 5: Reset
Output Mode 6: Toggle/Set
Output Mode 7: Reset/Set
TAIFG
EQU2
EQU2
EQU2
EQU2
EQU0
EQU0
TAIFG
Interrupt Events
Figure 13-14. Output Example – Timer in Up/Down Mode
NOTE:
Switching between output modes
When switching between output modes, one of the OUTMOD bits should remain set during
the transition, unless switching to mode 0. Otherwise, output glitching can occur, because a
NOR gate decodes output mode 0. A safe method for switching between output modes is to
use output mode 7 as a transition state:
BIS
BIC
408
Timer_A
#OUTMOD_7,&TA0CCTL1
#OUTMOD,&TA0CCTL1
; Set output mode=7
; Clear unwanted bits
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13.2.6 Timer_A Interrupts
Two interrupt vectors are associated with the 16-bit Timer_A module:
• TAxCCR0 interrupt vector for TAxCCR0 CCIFG
• TAxIV interrupt vector for all other CCIFG flags and TAIFG
In capture mode, any CCIFG flag is set when a timer value is captured in the associated TAxCCRn
register. In compare mode, any CCIFG flag is set if TAxR counts to the associated TAxCCRn value.
Software may also set or clear any CCIFG flag. All CCIFG flags request an interrupt when their
corresponding CCIE bit and the GIE bit are set.
13.2.6.1 TAxCCR0 Interrupt
The TAxCCR0 CCIFG flag has the highest Timer_A interrupt priority and has a dedicated interrupt vector
as shown in Figure 13-15. The TAxCCR0 CCIFG flag is automatically reset when the TAxCCR0 interrupt
request is serviced.
Capture
EQU0
CAP
D
Timer Clock
Set
CCIE
Q
IRQ, Interrupt Service Requested
Reset
IRACC, Interrupt Request Accepted
POR
Figure 13-15. Capture/Compare TAxCCR0 Interrupt Flag
13.2.6.2 TAxIV, Interrupt Vector Generator
The TAxCCRy CCIFG flags and TAIFG flags are prioritized and combined to source a single interrupt
vector. The interrupt vector register TAxIV is used to determine which flag requested an interrupt.
The highest-priority enabled interrupt generates a number in the TAxIV register (see register description).
This number can be evaluated or added to the program counter to automatically enter the appropriate
software routine. Disabled Timer_A interrupts do not affect the TAxIV value.
Any access, read or write, of the TAxIV register automatically resets the highest-pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
For example, if the TAxCCR1 and TAxCCR2 CCIFG flags are set when the interrupt service routine
accesses the TAxIV register, TAxCCR1 CCIFG is reset automatically. After the RETI instruction of the
interrupt service routine is executed, the TAxCCR2 CCIFG flag generates another interrupt.
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13.2.6.2.1 TAxIV Software Example
The following software example shows the recommended use of TAxIV and the handling overhead. The
TAxIV value is added to the PC to automatically jump to the appropriate routine. The example assumes a
single instantiation of the largest timer configuration available.
The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself. The latencies are:
• Capture/compare block TA0CCR0: 11 cycles
• Capture/compare blocks TA0CCR1, TA0CCR2, TA0CCR3, TA0CCR4, TA0CCR5, TA0CCR6:
16 cycles
• Timer overflow TA0IFG: 14 cycles
; Interrupt handler for TA0CCR0 CCIFG.
CCIFG_0_HND
;
...
; Start of handler Interrupt latency
RETI
Cycles
6
5
; Interrupt handler for TA0IFG, TA0CCR1 through TA0CCR6 CCIFG.
TA0_HND
410
...
ADD
RETI
JMP
JMP
JMP
JMP
JMP
JMP
&TA0IV,PC
CCIFG_1_HND
CCIFG_2_HND
CCIFG_3_HND
CCIFG_4_HND
CCIFG_5_HND
CCIFG_6_HND
;
;
;
;
;
;
;
;
;
Interrupt latency
Add offset to Jump table
Vector 0: No interrupt
Vector 2: TA0CCR1
Vector 4: TA0CCR2
Vector 6: TA0CCR3
Vector 8: TA0CCR4
Vector 10: TA0CCR5
Vector 12: TA0CCR6
6
3
5
2
2
2
2
2
2
TA0IFG_HND
...
RETI
; Vector 14: TA0IFG Flag
; Task starts here
CCIFG_6_HND
...
RETI
; Vector 12: TA0CCR6
; Task starts here
; Back to main program
5
CCIFG_5_HND
...
RETI
; Vector 10: TA0CCR5
; Task starts here
; Back to main program
5
CCIFG_4_HND
...
RETI
; Vector 8: TA0CCR4
; Task starts here
; Back to main program
5
CCIFG_3_HND
...
RETI
; Vector 6: TA0CCR3
; Task starts here
; Back to main program
5
CCIFG_2_HND
...
RETI
; Vector 4: TA0CCR2
; Task starts here
; Back to main program
5
CCIFG_1_HND
...
RETI
; Vector 2: TA0CCR1
; Task starts here
; Back to main program
5
Timer_A
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13.3 Timer_A Registers
Timer_A registers are listed in Table 13-3 for the largest configuration available. The base address can be
found in the device-specific data sheet.
Table 13-3. Timer_A Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
TAxCTL
Timer_Ax Control
Read/write
Word
0000h
Section 13.3.1
02h
TAxCCTL0
Timer_Ax Capture/Compare Control 0
Read/write
Word
0000h
Section 13.3.3
04h
TAxCCTL1
Timer_Ax Capture/Compare Control 1
Read/write
Word
0000h
Section 13.3.3
06h
TAxCCTL2
Timer_Ax Capture/Compare Control 2
Read/write
Word
0000h
Section 13.3.3
08h
TAxCCTL3
Timer_Ax Capture/Compare Control 3
Read/write
Word
0000h
Section 13.3.3
0Ah
TAxCCTL4
Timer_Ax Capture/Compare Control 4
Read/write
Word
0000h
Section 13.3.3
0Ch
TAxCCTL5
Timer_Ax Capture/Compare Control 5
Read/write
Word
0000h
Section 13.3.3
0Eh
TAxCCTL6
Timer_Ax Capture/Compare Control 6
Read/write
Word
0000h
Section 13.3.3
10h
TAxR
Timer_Ax Counter
Read/write
Word
0000h
Section 13.3.2
12h
TAxCCR0
Timer_Ax Capture/Compare 0
Read/write
Word
0000h
Section 13.3.4
14h
TAxCCR1
Timer_Ax Capture/Compare 1
Read/write
Word
0000h
Section 13.3.4
16h
TAxCCR2
Timer_Ax Capture/Compare 2
Read/write
Word
0000h
Section 13.3.4
18h
TAxCCR3
Timer_Ax Capture/Compare 3
Read/write
Word
0000h
Section 13.3.4
1Ah
TAxCCR4
Timer_Ax Capture/Compare 4
Read/write
Word
0000h
Section 13.3.4
1Ch
TAxCCR5
Timer_Ax Capture/Compare 5
Read/write
Word
0000h
Section 13.3.4
1Eh
TAxCCR6
Timer_Ax Capture/Compare 6
Read/write
Word
0000h
Section 13.3.4
2Eh
TAxIV
Timer_Ax Interrupt Vector
Read only
Word
0000h
Section 13.3.5
20h
TAxEX0
Timer_Ax Expansion 0
Read/write
Word
0000h
Section 13.3.6
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13.3.1 TAxCTL Register
Timer_Ax Control Register
Figure 13-16. TAxCTL Register
15
14
13
rw-(0)
rw-(0)
rw-(0)
6
5
12
11
10
9
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Reserved
7
rw-(0)
TASSEL
4
ID
MC
rw-(0)
rw-(0)
8
rw-(0)
rw-(0)
3
2
1
0
Reserved
TACLR
TAIE
TAIFG
rw-(0)
w-(0)
rw-(0)
rw-(0)
Table 13-4. TAxCTL Register Description
Bit
Field
Type
Reset
Description
15-10
Reserved
RW
0h
Reserved
9-8
TASSEL
RW
0h
Timer_A clock source select
00b = TAxCLK
01b = ACLK
10b = SMCLK
11b = INCLK
7-6
ID
RW
0h
Input divider. These bits along with the TAIDEX bits select the divider for the
input clock.
00b = /1
01b = /2
10b = /4
11b = /8
5-4
MC
RW
0h
Mode control. Setting MCx = 00h when Timer_A is not in use conserves power.
00b = Stop mode: Timer is halted
01b = Up mode: Timer counts up to TAxCCR0
10b = Continuous mode: Timer counts up to 0FFFFh
11b = Up/down mode: Timer counts up to TAxCCR0 then down to 0000h
3
Reserved
RW
0h
Reserved
2
TACLR
RW
0h
Timer_A clear. Setting this bit resets TAxR, the timer clock divider logic, and the
count direction. The TACLR bit is automatically reset and is always read as zero.
1
TAIE
RW
0h
Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
0b = Interrupt disabled
1b = Interrupt enabled
0
TAIFG
RW
0h
Timer_A interrupt flag
0b = No interrupt pending
1b = Interrupt pending
412
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13.3.2 TAxR Register
Timer_Ax Counter Register
Figure 13-17. TAxR Register
15
14
13
12
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
6
5
4
11
10
9
8
rw-(0)
rw-(0)
rw-(0)
rw-(0)
3
2
1
0
rw-(0)
rw-(0)
rw-(0)
rw-(0)
TAxR
TAxR
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Table 13-5. TAxR Register Description
Bit
Field
Type
Reset
Description
15-0
TAxR
RW
0h
Timer_A register. The TAxR register is the count of Timer_A.
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13.3.3 TAxCCTLn Register
Timer_Ax Capture/Compare Control n Register
Figure 13-18. TAxCCTLn Register
15
14
13
rw-(0)
rw-(0)
6
5
CM
12
11
10
9
SCS
SCCI
Reserved
CAP
rw-(0)
rw-(0)
r-(0)
r-(0)
rw-(0)
CCIS
rw-(0)
7
OUTMOD
rw-(0)
rw-(0)
rw-(0)
8
4
3
2
1
0
CCIE
CCI
OUT
COV
CCIFG
rw-(0)
r
rw-(0)
rw-(0)
rw-(0)
Table 13-6. TAxCCTLn Register Description
Bit
Field
Type
Reset
Description
15-14
CM
RW
0h
Capture mode
00b = No capture
01b = Capture on rising edge
10b = Capture on falling edge
11b = Capture on both rising and falling edges
13-12
CCIS
RW
0h
Capture/compare input select. These bits select the TAxCCR0 input signal. See
the device-specific data sheet for specific signal connections.
00b = CCIxA
01b = CCIxB
10b = GND
11b = VCC
11
SCS
RW
0h
Synchronize capture source. This bit is used to synchronize the capture input
signal with the timer clock.
0b = Asynchronous capture
1b = Synchronous capture
10
SCCI
RW
0h
Synchronized capture/compare input. The selected CCI input signal is latched
with the EQUx signal and can be read via this bit.
9
Reserved
R
0h
Reserved. Reads as 0.
8
CAP
RW
0h
Capture mode
0b = Compare mode
1b = Capture mode
7-5
OUTMOD
RW
0h
Output mode. Modes 2, 3, 6, and 7 are not useful for TAxCCR0 because EQUx
= EQU0.
000b = OUT bit value
001b = Set
010b = Toggle/reset
011b = Set/reset
100b = Toggle
101b = Reset
110b = Toggle/set
111b = Reset/set
4
CCIE
RW
0h
Capture/compare interrupt enable. This bit enables the interrupt request of the
corresponding CCIFG flag.
0b = Interrupt disabled
1b = Interrupt enabled
3
CCI
R
0h
Capture/compare input. The selected input signal can be read by this bit.
2
OUT
RW
0h
Output. For output mode 0, this bit directly controls the state of the output.
0b = Output low
1b = Output high
414
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Table 13-6. TAxCCTLn Register Description (continued)
Bit
Field
Type
Reset
Description
1
COV
RW
0h
Capture overflow. This bit indicates a capture overflow occurred. COV must be
reset with software.
0b = No capture overflow occurred
1b = Capture overflow occurred
0
CCIFG
RW
0h
Capture/compare interrupt flag
0b = No interrupt pending
1b = Interrupt pending
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13.3.4 TAxCCRn Register
Timer_A Capture/Compare n Register
Figure 13-19. TAxCCRn Register
15
14
13
12
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
6
5
4
11
10
9
8
rw-(0)
rw-(0)
rw-(0)
rw-(0)
3
2
1
0
rw-(0)
rw-(0)
rw-(0)
rw-(0)
TAxCCRn
TAxCCRn
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Table 13-7. TAxCCRn Register Description
Bit
Field
Type
Reset
Description
15-0
TAxCCR0
RW
0h
Compare mode: TAxCCRn holds the data for the comparison to the timer value
in the Timer_A Register, TAR.
Capture mode: The Timer_A Register, TAR, is copied into the TAxCCRn register
when a capture is performed.
13.3.5 TAxIV Register
Timer_Ax Interrupt Vector Register
Figure 13-20. TAxIV Register
15
14
13
12
11
10
9
8
TAIV
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
r0
r0
r0
r0
r-(0)
r-(0)
r-(0)
r0
TAIV
Table 13-8. TAxIV Register Description
Bit
Field
Type
Reset
Description
15-0
TAIV
R
0h
Timer_A interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG;
Interrupt Priority: Highest
04h = Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG
06h = Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG
08h = Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG
0Ah = Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG
0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt
Priority: Lowest
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13.3.6 TAxEX0 Register
Timer_Ax Expansion 0 Register
Figure 13-21. TAxEX0 Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
Reserved
TAIDEX (1)
Reserved
r0
(1)
r0
r0
r0
r0
rw-(0)
rw-(0)
rw-(0)
After programming TAIDEX bits and configuration of the timer, set TACLR bit to ensure proper reset of the timer divider logic.
Table 13-9. TAxEX0 Register Description
Bit
Field
Type
Reset
Description
15-3
Reserved
R
0h
Reserved. Reads as 0.
2-0
TAIDEX
RW
0h
Input divider expansion. These bits along with the ID bits select the divider for
the input clock.
000b = Divide by 1
001b = Divide by 2
010b = Divide by 3
011b = Divide by 4
100b = Divide by 5
101b = Divide by 6
110b = Divide by 7
111b = Divide by 8
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Chapter 14
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Real-Time Clock (RTC) Overview
14.1 RTC Overview
Table 14-1. RTC Overview
RTC_A
RTC_D
Feature
LPM3.5, Calendar and Counter
Mode
Calendar Mode
Yes
Yes
Counter Mode
Yes
Yes
Programmable Alarms
Yes
Yes
Password Protected Calendar Registers
No
No
ALCK, SMCLK
32-kHz crystal oscillator
LPM3.5 Support
No
Yes
Offset Calibration Register
Yes
Yes
Input Clocks
Temperature Compensation Register
Frequency Adjustment Range
No
-2.17ppm × 59 ≈ -128ppm
+4.34ppm × 59 ≈ +256 ppm
Frequency Adjustment Steps
-2.035 ppm, +4.069 pmm
-2.17 ppm, +4.34 pmm
Temperature Compensation
With software, manipulating offset
calibration value
With software, manipulating offset
calibration value
64 min
60 min
Integrated for Calendar Mode
Integrated for Calendar Mode
plus separate conversion registers
Calibration and Compensation Period
BCD to Binary Conversion
418
No
-2.035ppm × 63 ≈ -128ppm
+4.069ppm × 63 ≈ +256 ppm
Real-Time Clock (RTC) Overview
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Chapter 15
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Real-Time Clock (RTC_A)
The Real-Time Clock (RTC_A) module provides clock counters with a calendar, a flexible programmable
alarm, and calibration. This chapter describes the RTC_A module.
Topic
15.1
15.2
15.3
...........................................................................................................................
Page
RTC_A Introduction ......................................................................................... 420
RTC_A Operation ............................................................................................. 422
RTC_A Registers ............................................................................................. 428
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15.1 RTC_A Introduction
The RTC_A module provides a real-time clock and calendar function that can also be configured as a
general-purpose counter.
RTC_A features include:
• Configurable for real-time clock with calendar function or general-purpose counter
• Provides seconds, minutes, hours, day of week, day of month, month, and year in real-time clock with
calendar function
• Interrupt capability
• Selectable BCD or binary format in real-time clock mode
• Programmable alarms in real-time clock mode
• Calibration logic for time offset correction in real-time clock mode
The RTC_A block diagram is shown in Figure 15-1.
NOTE:
Real-time clock initialization
Most RTC_A module registers have no initial condition. These registers must be configured
by user software before use.
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RT0PSHOLD
RT0SSEL
RT0IP
EN
ACLK
SMCLK
RT0PS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0
1
3
111
110
100
101
011
010
3
000
RT0PSDIV
001
111
110
101
100
011
010
001
000
Set_RT0PSIFG
RTCCALS RTCCAL RTCMODE
5
Calibration
Logic EN
RT1PSHOLD
RT1SSEL
2
3
RT1PS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Keepout
Logic
RTCSSEL
2
00
01
10
11
Set_RT1PSIFG
111
110
101
100
011
001
3
010
111
110
101
100
011
010
001
000
000
RT1PSDIV
RT1IP
EN
00
01
10
11
Set_RTCRDYIFG
RTCHOLD
RTCBCD
EN
31 ... 24
23 ... 16
RTCNT4/
RTCDOW
RTCNT3/
RTCHOUR
15 ...
8
RTCNT2/
RTCMIN
7
...
0
RTCNT1/
RTCSEC
8-bit overflow/minute changed
16-bit overflow/hour changed
24-bit overflow/midnight
32-bit overflow/noon
RTCTEV
2
00 Set_RTCTEVIFG
01
10
11
EN
Calendar
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
EN
Alarm
RTCADOW
RTCADAY
RTCAHOUR
Set_RTCAIFG
RTCAMIN
Figure 15-1. RTC_A
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15.2 RTC_A Operation
The RTC_A module can be configured as a real-time clock with calendar function (calendar mode) or as a
32-bit general purpose counter (counter mode) with the RTCMODE bit.
15.2.1 Counter Mode
Counter mode is selected when RTCMODE is reset. In this mode, a 32-bit counter is provided that is
directly accessible by software. Switching from calendar mode to counter mode resets the count value
(RTCNT1, RTCNT2, RTCNT3, RTCNT4), as well as the prescale counters (RT0PS, RT1PS).
The clock to increment the counter can be sourced from ACLK, SMCLK, or prescaled versions of ACLK or
SMCLK. Prescaled versions of ACLK or SMCLK are sourced from the prescale dividers (RT0PS and
RT1PS). RT0PS and RT1PS output /2, /4, /8, 16, /32, /64, /128, and /256 versions of ACLK and SMCLK,
respectively. The output of RT0PS can be cascaded with RT1PS. The cascaded output can be used as a
clock source input to the 32-bit counter.
Four individual 8-bit counters are cascaded to provide the 32-bit counter. This provides 8-bit, 16-bit, 24-bit,
or 32-bit overflow intervals of the counter clock. The RTCTEV bits select the respective trigger event. An
RTCTEV event can trigger an interrupt by setting the RTCTEVIE bit. Each counter, RTCNT1 through
RTCNT4, is individually accessible and may be written to.
RT0PS and RT1PS can be configured as two 8-bit counters or cascaded into a single 16-bit counter.
RT0PS and RT1PS can be halted on an individual basis by setting their respective RT0PSHOLD and
RT1PSHOLD bits. When RT0PS is cascaded with RT1PS, setting RT0PSHOLD causes both RT0PS and
RT1PS to be halted. The 32-bit counter can be halted several ways depending on the configuration. If the
32-bit counter is sourced directly from ACLK or SMCLK, it can be halted by setting RTCHOLD. If it is
sourced from the output of RT1PS, it can be halted by setting RT1PSHOLD or RTCHOLD. Finally, if it is
sourced from the cascaded outputs of RT0PS and RT1PS, it can be halted by setting RT0PSHOLD,
RT1PSHOLD, or RTCHOLD.
NOTE:
Accessing the RTCNT1, RTCNT2, RTCNT3, RTCNT4, RT0PS, RT1PS registers
When the counter clock is asynchronous to the CPU clock, any read from any RTCNT1,
RTCNT2, RTCNT3, RTCNT4, RT0PS, or RT1PS register should occur while the counter is
not operating. Otherwise, the results may be unpredictable. Alternatively, the counter may be
read multiple times while operating, and a majority vote taken in software to determine the
correct reading. Any write to these registers takes effect immediately.
15.2.2 Calendar Mode
Calendar mode is selected when RTCMODE is set. In calendar mode, the RTC_A module provides
seconds, minutes, hours, day of week, day of month, month, and year in selectable BCD or hexadecimal
format. The calendar includes a leap-year algorithm that considers all years evenly divisible by four as
leap years. This algorithm is accurate from the year 1901 through 2099.
15.2.2.1
Real-Time Clock and Prescale Dividers
The prescale dividers, RT0PS and RT1PS, are automatically configured to provide a 1-s clock interval for
the RTC_A. RT0PS is sourced from ACLK. ACLK must be set to 32768 Hz (nominal) for proper RTC_A
calendar operation. RT1PS is cascaded with the output ACLK/256 of RT0PS. The RTC_A is sourced with
the /128 output of RT1PS, thereby providing the required 1-s interval. Switching from counter to calendar
mode clears the seconds, minutes, hours, day-of-week, and year counts and sets day-of-month and
month counts to 1. In addition, RT0PS and RT1PS are cleared.
When RTCBCD = 1, BCD format is selected for the calendar registers. The format must be selected
before the time is set. Changing the state of RTCBCD clears the seconds, minutes, hours, day-of-week,
and year counts and sets day-of-month and month counts to 1. In addition, RT0PS and RT1PS are
cleared.
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In calendar mode, the RT0SSEL, RT1SSEL, RT0PSDIV, RT1PSDIV, RT0PSHOLD, RT1PSHOLD, and
RTCSSEL bits are don't care. Setting RTCHOLD halts the real-time counters and prescale counters,
RT0PS and RT1PS.
15.2.2.2
Real-Time Clock Alarm Function
The RTC_A module provides for a flexible alarm system. There is a single user-programmable alarm that
can be programmed based on the settings contained in the alarm registers for minutes, hours, day of
week, and day of month. The user-programmable alarm function is only available in the calendar mode of
operation.
Each alarm register contains an alarm enable (AE) bit that can be used to enable the respective alarm
register. By setting AE bits of the various alarm registers, a variety of alarm events can be generated.
• Example 1: A user wishes to set an alarm every hour at 15 minutes past the hour; that is, at 00:15:00,
01:15:00, 02:15:00, and so on. This is possible by setting RTCAMIN to 15. By setting the AE bit of the
RTCAMIN and clearing all other AE bits of the alarm registers, the alarm is enabled. When enabled,
the AF is set when the count transitions from 00:14:59 to 00:15:00, 01:14:59 to 01:15:00, 02:14:59 to
02:15:00, etc.
• Example 2: A user wishes to set an alarm every day at 04:00:00. This is possible by setting
RTCAHOUR to 4. By setting the AE bit of the RTCHOUR and clearing all other AE bits of the alarm
registers, the alarm is enabled. When enabled, the AF is set when the count transitions from 03:59:59
to 04:00:00.
• Example 3: A user wishes to set an alarm for 06:30:00. RTCAHOUR would be set to 6 and RTCAMIN
would be set to 30. By setting the AE bits of RTCAHOUR and RTCAMIN, the alarm is enabled. Once
enabled, the AF is set when the the time count transitions from 06:29:59 to 06:30:00. In this case, the
alarm event occurs every day at 06:30:00.
• Example 4: A user wishes to set an alarm every Tuesday at 06:30:00. RTCADOW would be set to 2,
RTCAHOUR would be set to 6 and RTCAMIN would be set to 30. By setting the AE bits of
RTCADOW, RTCAHOUR and RTCAMIN, the alarm is enabled. Once enabled, the AF is set when the
the time count transitions from 06:29:59 to 06:30:00 and the RTCDOW transitions from 1 to 2.
• Example 5: A user wishes to set an alarm the fifth day of each month at 06:30:00. RTCADAY would be
set to 5, RTCAHOUR would be set to 6 and RTCAMIN would be set to 30. By setting the AE bits of
RTCADAY, RTCAHOUR and RTCAMIN, the alarm is enabled. Once enabled, the AF is set when the
the time count transitions from 06:29:59 to 06:30:00 and the RTCDAY equals 5.
NOTE:
Invalid alarm settings
Invalid alarm settings are not checked via hardware. It is the user's responsibility to ensure
that valid alarm settings are entered.
NOTE:
Invalid time and date values
Writing of invalid date and/or time information or data values outside the legal ranges
specified in the RTCSEC, RTCMIN, RTCHOUR, RTCDAY, RTCDOW, RTCYEARH,
RTCYEARL, RTCAMIN, RTCAHOUR, RTCADAY, and RTCADOW registers can result in
unpredictable behavior.
NOTE:
Setting the alarm
To prevent potential erroneous alarm conditions from occurring, the alarms should be
disabled by clearing the RTCAIE, RTCAIFG, and AE bits prior to writing new time values to
the RTC time registers.
15.2.2.3
Reading or Writing Real-Time Clock Registers in Calendar Mode
Because the system clock may be asynchronous to the RTC_A clock source, special care must be taken
when accessing the real-time clock registers.
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In calendar mode, the real-time clock registers are updated once per second. To prevent reading any realtime clock register at the time of an update, which could result in an invalid time being read, a keepout
window is provided. The keepout window is centered approximately -128/32768 s around the update
transition. The read-only RTCRDY bit is reset during the keepout window period and set outside the
keepout the window period. Any read of the clock registers while RTCRDY is reset is considered to be
potentially invalid, and the time read should be ignored.
An easy way to safely read the real-time clock registers is to use the RTCRDYIFG interrupt flag. Setting
RTCRDYIE enables the RTCRDYIFG interrupt. Once enabled, an interrupt is generated based on the
rising edge of the RTCRDY bit, causing the RTCRDYIFG to be set. At this point, the application has
nearly a complete second to safely read any or all of the real-time clock registers. This synchronization
process prevents reading the time value during transition. The RTCRDYIFG flag is reset automatically
when the interrupt is serviced, or can be reset with software.
In counter mode, the RTCRDY bit remains reset. RTCRDYIE is a don't care and RTCRDYIFG remains
reset.
NOTE:
Reading or writing real-time clock registers
When the counter clock is asynchronous to the CPU clock, any read from any RTCSEC,
RTCMIN, RTCHOUR, RTCDOW, RTCDAY, RTCMON, RTCYEARL, or RTCYEARH register
while the RTCRDY is reset may result in invalid data being read. To safely read the counting
registers, either polling of the RTCRDY bit or the synchronization procedure previously
described can be used. Alternatively, the counter register can be read multiple times while
operating, and a majority vote taken in software to determine the correct reading. Reading
the RT0PS and RT1PS can only be handled by reading the registers multiple times and a
majority vote taken in software to determine the correct reading or by halting the counters.
Any write to any counting register takes effect immediately. However, the clock is stopped
during the write. In addition, RT0PS and RT1PS registers are reset. This could result in
losing up to 1 s during a write. Writing of data outside the legal ranges or invalid time stamp
combinations results in unpredictable behavior.
15.2.3 Real-Time Clock Interrupts
The RTC_A module has five interrupt sources available, each with independent enables and flags.
15.2.3.1
Real-Time Clock Interrupts in Calendar Mode
In calendar mode, five sources for interrupts are available, namely RT0PSIFG, RT1PSIFG, RTCRDYIFG,
RTCTEVIFG, and RTCAIFG. These flags are prioritized and combined to source a single interrupt vector.
The interrupt vector register (RTCIV) is used to determine which flag requested an interrupt.
The highest-priority enabled interrupt generates a number in the RTCIV register (see register description).
This number can be evaluated or added to the program counter (PC) to automatically enter the
appropriate software routine. Disabled RTC interrupts do not affect the RTCIV value.
Any access, read or write, of the RTCIV register automatically resets the highest-pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
In addition, all flags can be cleared via software.
The user-programmable alarm event sources the real-time clock interrupt, RTCAIFG. Setting RTCAIE
enables the interrupt. In addition to the user-programmable alarm, the RTC_A module provides for an
interval alarm that sources real-time clock interrupt, RTCTEVIFG. The interval alarm can be selected to
cause an alarm event when RTCMIN changed or RTCHOUR changed, every day at midnight (00:00:00)
or every day at noon (12:00:00). The event is selectable with the RTCTEV bits. Setting the RTCTEVIE bit
enables the interrupt.
The RTCRDY bit sources the real-time clock interrupt, RTCRDYIFG, and is useful in synchronizing the
read of time registers with the system clock. Setting the RTCRDYIE bit enables the interrupt.
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RT0PSIFG can be used to generate interrupt intervals selectable by the RT0IP bits. In calendar mode,
RT0PS is sourced with ACLK at 32768 Hz, so intervals of 16384 Hz, 8192 Hz, 4096 Hz, 2048 Hz,
1024 Hz, 512 Hz, 256 Hz, or 128 Hz are possible. Setting the RT0PSIE bit enables the interrupt.
RT1PSIFG can generate interrupt intervals selectable by the RT1IP bits. In calendar mode, RT1PS is
sourced with the output of RT0PS, which is 128 Hz (32768/256 Hz). Therefore, intervals of 64 Hz, 32 Hz,
16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz, or 0.5 Hz are possible. Setting the RT1PSIE bit enables the interrupt.
15.2.3.2 Real-Time Clock Interrupts in Counter Mode
In counter mode, three interrupt sources are available: RT0PSIFG, RT1PSIFG, and RTCTEVIFG.
RTCAIFG and RTCRDYIFG are cleared. RTCRDYIE and RTCAIE are don't care.
RT0PSIFG can be used to generate interrupt intervals selectable by the RT0IP bits. In counter mode,
RT0PS is sourced with ACLK or SMCLK, so divide ratios of /2, /4, /8, /16, /32, /64, /128, and /256 of the
respective clock source are possible. Setting the RT0PSIE bit enables the interrupt.
RT1PSIFG can be used to generate interrupt intervals selectable by the RT1IP bits. In counter mode,
RT1PS is sourced with ACLK, SMCLK, or the output of RT0PS, so divide ratios of /2, /4, /8, /16, /32, /64,
/128, and /256 of the respective clock source are possible. Setting the RT1PSIE bit enables the interrupt.
The RTC_A module provides for an interval timer that sources real-time clock interrupt, RTCTEVIFG. The
interval timer can be selected to cause an interrupt event when an 8-bit, 16-bit, 24-bit, or 32-bit overflow
occurs within the 32-bit counter. The event is selectable with the RTCTEV bits. Setting the RTCTEVIE bit
enables the interrupt.
15.2.3.2.1 RTCIV Software Example
The following software example shows the recommended use of RTCIV and the handling overhead. The
RTCIV value is added to the PC to automatically jump to the appropriate routine.
The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself.
; Interrupt handler for RTC interrupt flags.
Cycles
RTC_HND
; Interrupt latency
6
ADD
&RTCIV,PC
; Add offset to Jump table
3
RETI
; Vector 0: No interrupt
5
JMP
RTCRDYIFG_HND
; Vector 2: RTCRDYIFG
2
JMP
RTCTEVIFG_HND
; Vector 4: RTCTEVIFG
2
JMP
RTCAIFG
; Vector 6: RTCAIFG
5
JMP
RT0PSIFG
; Vector 8: RT0PSIFG
5
JMP
RT1PSIFG
; Vector A: RT1PSIFG
5
RETI
; Vector C: Reserved
5
RTCRDYIFG_HND
; Vector 2: RTCRDYIFG Flag
to
; Task starts here
RETI
5
RTCTEVIFG_HND
; Vector 4: RTCTEVIFG
to
; Task starts here
RETI
; Back to main program
5
RTCAIFG_HND
; Vector 6: RTCAIFG
to
; Task starts here
RT0PSIFG_HND
; Vector 8: RT0PSIFG
to
; Task starts here
RT1PSIFG_HND
; Vector A: RT1PSIFG
to
; Task starts here
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15.2.4 Real-Time Clock Calibration
The RTC_A module has calibration logic that allows for adjusting the crystal frequency in approximately
+4-ppm or –2-ppm steps, allowing for higher time keeping accuracy from standard crystals.The RTCCAL
bits are used to adjust the frequency. When RTCCALS is set, each RTCCAL LSB causes a ≈ +4-ppm
adjustment. When RTCCALS is cleared, each RTCCAL LSB causes a ≈ –2-ppm adjustment. Calibration is
available only in calendar mode. In counter mode (RTCMODE = 0), the calibration logic is disabled.
Calibration is accomplished by periodically adjusting the RT1PS counter based on the RTCCALS and
RTCCALx settings. In calendar mode, the RT0PS divides the nominial 37268-Hz low-frequency (LF)
crystal clock input by 256. A 64-minute period has 32768 cycles/sec × 60 sec/min × 64 min = 125829120
cycles. Therefore a –2-ppm reduction in frequency (down calibration) approximately equates to adding an
additional 256 cycles every 125829120 cycles (256/125829120 = 2.035 ppm). This is accomplished by
holding the RT1PS counter for one additional clock of the RT0PS output within a 64-minute period.
Similary, a +4-ppm increase in frequency (up calibration) approximately equates to removing 512 cycles
every 125829120 cycle (512/125829120 = 4.069 ppm). This is accomplished by incrementing the RT1PS
counter for two additional clocks of the RT0PS output within a 64-minute period. Each RTCCALx
calibration bit causes either 256 LF crystal clock cycles to be added every 64 minutes or 512 LF crystal
clock cycles to be subtracted every 64 minutes, giving a frequency adjustment of approximately –2 ppm or
+4 ppm, respectively.
To calibrate the frequency, the RTCCLK output signal is available at a pin. The RTCCALF bits can be
used to select the frequency rate of the RTCCLK output signal, either no signal, 512 Hz, 256 Hz, or 1 Hz.
The basic flow to calibrate the frequency is as follows:
1. Configure the RTCCLK pin.
2. Measure the RTCCLK output signal with an appropriate resolution frequency counter; that is, within the
resolution required.
3. Compute the absolute error in ppm: Absolute Error (ppm) = |106 × ( fMEASURED – fRTCCLK) / fRTCCLK|, where
fRTCCLK is the expected frequency of 512 Hz, 256 Hz, or 1 Hz.
4. Adjust the frequency, by performing the following:
(a) If the frequency is too low, set RTCALS = 1 and apply the appropriate RTCCALx bits, where
RTCCALx = (Absolute Error) / 4.069, rounded to the nearest integer.
(b) If the frequency is too high, clear RTCALS = 0 and apply the appropriate RTCCALx bits, where
RTCCALx = (Absolute Error) / 2.035, rounded to the nearest integer.
For example, assume that RTCCLK is output at a frequency of 512 Hz. The measured RTCCLK is
511.9658 Hz. The frequency error is approximately 66.8 ppm low. To increase the frequency by 66.8 ppm,
RTCCALS would be set, and RTCCAL would be set to 16 (66.8/4.069). Similarly, assume that the
measured RTCCLK is 512.0125 Hz. The frequency error is approximately 24.4 ppm high. To decrease the
frequency by 24.4 ppm, RTCCALS would be cleared, and RTCCAL would be set to 12 (24.4 / 2.035).
The calibration corrects only initial offsets and does not adjust for temperature and aging effects. This can
be handled by periodically measuring temperature and using the crystal's charateristic curve to adjust the
ppm based on temperature as required. In counter mode (RTCMODE = 0), the calibration logic is
disabled.
NOTE: Minimum Possible Calibration
The minimial calibration possible is -4 ppm or +8 ppm. For example, setting RTCCALS = 0
and RTCCAL = 0h would result in a -4 ppm decrease in frequency. Similarly, setting
RTCCALS = 1 and RTCCAL = 0h would result in a +8 ppm increase in frequency.
426
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NOTE:
Calibration output frequency
The 512-Hz and 256-Hz output frequencies observed at the RTCCLK pin are not affected by
changes in the calibration settings since these output frequencies are generated prior to the
calibration logic. The 1-Hz output frequency is affected by changes in the calibration settings.
Because the frequency change is small and infrequent over a very long time interval, it can
be difficult to observe.
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15.3 RTC_A Registers
The RTC_A module registers are listed in and Table 15-1. The base register for the RTC_A module
registers can be found in the device-specific data sheet. The address offsets are given in Table 15-1.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 15-1. RTC_A Registers
Offset
Acronym
Register Name
Type
Access
Reset
00h
RTCCTL01
Real-Time Clock Control 0, 1
Read/write
Word
4000h
00h
RTCCTL0
Real-Time Clock Control 0
Read/write
Byte
00h
Real-Time Clock Control 1
Read/write
Byte
40h
or RTCCTL01_L
01h
RTCCTL1
or RTCCTL01_H
02h
RTCCTL23
Real-Time Clock Control 2, 3
Read/write
Word
0000h
02h
RTCCTL2
Real-Time Clock Control 2
Read/write
Byte
00h
Real-Time Clock Control 3
Read/write
Byte
00h
Real-Time Prescale Timer 0 Control
Read/write
Word
0100h
Read/write
Byte
00h
Read/write
Byte
01h
Read/write
Word
0100h
Read/write
Byte
00h
Read/write
Byte
01h
or RTCCTL23_L
03h
RTCCTL3
or RTCCTL23_H
08h
RTCPS0CTL
08h
RTCPS0CTLL
or RTCPS0CTL_L
09h
RTCPS0CTLH
or RTCPS0CTL_H
0Ah
RTCPS1CTL
0Ah
RTCPS1CTLL
Real-Time Prescale Timer 1 Control
or RTCPS1CTL_L
0Bh
RTCPS0CTLH
or RTCPS0CTL_H
0Ch
RTCPS
Real-Time Prescale Timer 0, 1 Counter
Read/write
Word
undefined
0Ch
RT0PS
Real-Time Prescale Timer 0 Counter
Read/write
Byte
undefined
Real-Time Prescale Timer 1 Counter
Read/write
Byte
undefined
Real Time Clock Interrupt Vector
Read
Word
0000h
Read
Byte
00h
Read
Byte
00h
Read/write
Word
undefined
Read/write
Byte
undefined
Read/write
Byte
undefined
Read/write
Word
undefined
Read/write
Byte
undefined
or RTCPS_L
0Dh
RT1PS
or RTCPS_H
0Eh
RTCIV
0Eh
RTCIV_L
0Fh
RTCIV_H
10h
RTCTIM0
Real-Time Clock Seconds, Minutes
or RTCNT12
Real-Time Counter 1, 2
RTCSEC
Real-Time Clock Seconds
RTCNT1
Real-Time Counter 1
10h
or RTCTIM0_L
11h
RTCMIN
Real-Time Clock Minutes
RTCNT2
Real-Time Counter 2
or RTCTIM0_H
12h
12h
RTCTIM1
Real-Time Clock Hour, Day of Week
or RTCNT34
Real-Time Counter 3, 4
RTCHOUR
Real-Time Clock Hour
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Table 15-1. RTC_A Registers (continued)
Offset
Acronym
Register Name
RTCNT3
Real-Time Counter 3
Type
Access
Reset
Read/write
Byte
undefined
or RTCTIM1_L
13h
RTCDOW
Real-Time Clock Day of Week
RTCNT4
Real-Time Counter 4
or RTCTIM1_H
14h
RTCDATE
Real-Time Clock Date
Read/write
Word
undefined
14h
RTCDAY
Real-Time Clock Day of Month
Read/write
Byte
undefined
Real-Time Clock Month
Read/write
Byte
undefined
Real-Time Clock Year
Read/write
Word
undefined
Read/write
Byte
undefined
Read/write
Byte
undefined
or RTCDATE_L
15h
RTCMON
or RTCDATE_H
16h
RTCYEAR
16h
RTCYEARL
or RTCYEAR_L
17h
RTCYEARH
or RTCYEAR_H
18h
RTCAMINHR
Real-Time Clock Minutes, Hour Alarm
Read/write
Word
undefined
18h
RTCAMIN
Real-Time Clock Minutes Alarm
Read/write
Byte
undefined
Real-Time Clock Hours Alarm
Read/write
Byte
undefined
or RTCAMINHR_L
19h
RTCAHOUR
or RTCAMINHR_H
1Ah
RTCADOWDAY
Real-Time Clock Day of Week, Day of Month
Alarm
Read/write
Word
undefined
1Ah
RTCADOW
Real-Time Clock Day of Week Alarm
Read/write
Byte
undefined
Real-Time Clock Day of Month Alarm
Read/write
Byte
undefined
or RTCADOWDAY_L
1Bh
RTCADAY
or RTCADOWDAY_H
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15.3.1 RTCCTL0 Register
Real-Time Clock Control 0 Register
Figure 15-2. RTCCTL0 Register
7
6
5
4
3
2
1
0
Reserved
RTCTEVIE
RTCAIE
RTCRDYIE
Reserved
RTCTEVIFG
RTCAIFG
RTCRDYIFG
r0
rw-0
rw-0
rw-0
r0
rw-(0)
rw-(0)
rw-(0)
Table 15-2. RTCCTL0 Register Description
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved. Always reads as 0.
6
RTCTEVIE
RW
0h
Real-time clock time event interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
5
RTCAIE
RW
0h
Real-time clock alarm interrupt enable. This bit remains cleared when in counter
mode (RTCMODE = 0).
0b = Interrupt not enabled
1b = Interrupt enabled
4
RTCRDYIE
RW
0h
Real-time clock read ready interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
3
Reserved
R
0h
Reserved. Always reads as 0.
2
RTCTEVIFG
RW
0h
Real-time clock time event flag
0b = No time event occurred.
1b = Time event occurred.
1
RTCAIFG
RW
0h
Real-time clock alarm flag. This bit remains cleared when in counter mode
(RTCMODE = 0).
0b = No time event occurred.
1b = Time event occurred.
0
RTCRDYIFG
RW
0h
Real-time clock read ready flag
0b = RTC cannot be read safely.
1b = RTC can be read safely.
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15.3.2 RTCCTL1 Register
Real-Time Clock Control Register 1
Figure 15-3. RTCCTL1 Register
7
6
5
4
RTCBCD
RTCHOLD
RTCMODE
RTCRDY
rw-(0)
rw-(1)
rw-(0)
r-(0)
3
2
1
rw-(0)
rw-(0)
RTCSSEL
rw-(0)
0
RTCTEV
rw-(0)
Table 15-3. RTCCTL1 Register Description
Bit
Field
Type
Reset
Description
7
RTCBCD
RW
0h
Real-time clock BCD select. Selects BCD counting for real-time clock. Applies to
calendar mode (RTCMODE = 1) only; setting is ignored in counter mode.
Changing this bit clears seconds, minutes, hours, day of week, and year to 0 and
sets day of month and month to 1. The real-time clock registers must be set by
software afterwards.
0b = Binary (hexadecimal) code selected
1b = Binary coded decimal (BCD) code selected
6
RTCHOLD
RW
1h
Real-time clock hold
0b = Real-time clock (32-bit counter or calendar mode) is operational.
1b = In counter mode (RTCMODE = 0), only the 32-bit counter is stopped. In
calendar mode (RTCMODE = 1), the calendar is stopped as well as the prescale
counters, RT0PS and RT1PS. RT0PSHOLD and RT1PSHOLD are don't care.
5
RTCMODE
RW
0h
Real-time clock mode
0b = 32-bit counter mode
1b = Calendar mode. Switching between counter and calendar mode resets the
real-time clock counter registers. Switching to calendar mode clears seconds,
minutes, hours, day of week, and year to 0 and sets day of month and month to
1. The real-time clock registers must be set by software afterwards. RT0PS and
RT1PS are also cleared.
4
RTCRDY
RW
0h
Real-time clock ready
0b = RTC time values in transition (calendar mode only)
1b = RTC time values safe for reading (calendar mode only). This bit indicates
when the real-time clock time values are safe for reading (calendar mode only).
In counter mode, RTCRDY signal remains cleared.
3-2
RTCSSEL
RW
0h
Real-time clock source select. Selects clock input source to the RTC/32-bit
counter. In calendar mode, these bits are don't care. The clock input is
automatically set to the output of RT1PS.
00b = ACLK
01b = SMCLK
10b = Output from RT1PS
11b = Output from RT1PS
1-0
RTCTEV
RW
0h
Real-time clock time event
Counter mode (RTCMODE = 0)
00b = 8-bit overflow
01b = 16-bit overflow
10b = 24-bit overflow
11b = 32-bit overflow
Calendar mode (RTCMODE = 1)
00b = Minute changed
01b = Hour changed
10b = Every day at midnight (00:00)
11b = Every day at noon (12:00)
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15.3.3 RTCCTL2 Register
Real-Time Clock Control 2 Register
Figure 15-4. RTCCTL2 Register
7
6
RTCCALS
Reserved
rw-(0)
r0
5
4
3
rw-(0)
rw-(0)
rw-(0)
2
1
0
rw-(0)
rw-(0)
rw-(0)
RTCCAL
Table 15-4. RTCCTL2 Register Description
Bit
Field
Type
Reset
Description
7
RTCCALS
RW
0h
Real-time clock calibration sign
0b = Frequency adjusted down
1b = Frequency adjusted up
6
Reserved
R
0h
Reserved. Always reads as 0.
5-0
RTCCAL
RW
0h
Real-time clock calibration. Each LSB represents approximately +4ppm
(RTCCALS = 1) or a –2ppm (RTCCALS = 0) adjustment in frequency.
15.3.4 RTCCTL3 Register
Real-Time Clock Control 3 Register
Figure 15-5. RTCCTL3 Register
7
6
5
4
3
2
1
Reserved
r0
r0
r0
0
RTCCALF
r0
r0
r0
rw-(0)
rw-(0)
Table 15-5. RTCCTL3 Register Description
Bit
Field
Type
Reset
Description
7-2
Reserved
R
0h
Reserved. Always reads as 0.
1-0
RTCCALF
RW
0h
Real-time clock calibration frequency. Selects frequency output to RTCCLK pin
for calibration measurement. The corresponding port must be configured for the
peripheral module function. The RTCCLK is not available in counter mode and
remains low, and the RTCCALF bits are don't care.
00b = No frequency output to RTCCLK pin
01b = 512 Hz
10b = 256 Hz
11b = 1 Hz
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15.3.5 RTCNT1 Register
Real-Time Clock Counter 1 Register – Counter Mode
Figure 15-6. RTCNT1 Register
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
RTCNT1
Table 15-6. RTCNT1 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT1
RW
undefined
The RTCNT1 register is the count of RTCNT1
15.3.6 RTCNT2 Register
Real-Time Clock Counter 2 Register – Counter Mode
Figure 15-7. RTCNT2 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCNT2
rw
rw
rw
rw
Table 15-7. RTCNT2 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT2
RW
undefined
The RTCNT2 register is the count of RTCNT2
15.3.7 RTCNT3 Register
Real-Time Clock Counter 3 Register – Counter Mode
Figure 15-8. RTCNT3 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCNT3
rw
rw
rw
rw
Table 15-8. RTCNT3 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT3
RW
undefined
The RTCNT3 register is the count of RTCNT3
15.3.8 RTCNT4 Register
Real-Time Clock Counter 4 Register – Counter Mode
Figure 15-9. RTCNT4 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCNT4
rw
rw
rw
rw
Table 15-9. RTCNT4 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT4
RW
undefined
The RTCNT4 register is the count of RTCNT4.
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15.3.9 RTCSEC Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Seconds Register – Calendar Mode With Hexadecimal Format
Figure 15-10. RTCSEC Register
7
6
5
4
3
r-0
rw
rw
rw
0
r-0
2
1
0
rw
rw
rw
1
0
Seconds
Table 15-10. RTCSEC Register Description
Bit
Field
Type
Reset
Description
7-6
0
R
0h
Always 0
5-0
Seconds
RW
undefined
Seconds (0 to 59)
15.3.10 RTCSEC Register – Calendar Mode With BCD Format
Real-Time Clock Seconds Register – Calendar Mode With BCD Format
Figure 15-11. RTCSEC Register
7
6
0
5
4
3
2
Seconds – high digit
r-0
rw
rw
Seconds – low digit
rw
rw
rw
rw
rw
Table 15-11. RTCSEC Register Description
Bit
Field
Type
Reset
Description
7
0
R
0h
Always 0
6-4
Seconds – high digit
RW
undefined
Seconds – high digit (0 to 5)
3-0
Seconds – low digit
RW
undefined
Seconds – low digit (0 to 9)
434
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15.3.11 RTCMIN Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Minutes Register – Calendar Mode With Hexadecimal Format
Figure 15-12. RTCMIN Register
7
6
5
4
3
r-0
rw
rw
rw
0
r-0
2
1
0
rw
rw
rw
1
0
Minutes
Table 15-12. RTCMIN Register Description
Bit
Field
Type
Reset
Description
7-6
0
R
0h
Always 0
5-0
Minutes
RW
undefined
Minutes (0 to 59)
15.3.12 RTCMIN Register – Calendar Mode With BCD Format
Real-Time Clock Minutes Register – Calendar Mode With BCD Format
Figure 15-13. RTCMIN Register
7
6
0
5
4
3
Minutes – high digit
r-0
rw
rw
2
Minutes – low digit
rw
rw
rw
rw
rw
Table 15-13. RTCMIN Register Description
Bit
Field
Type
Reset
Description
7
0
R
0h
Always 0
6-4
Minutes – high digit
RW
undefined
Minutes – high digit (0 to 5)
3-0
Minutes – low digit
RW
undefined
Minutes – low digit (0 to 9)
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15.3.13 RTCHOUR Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Hours Register – Calendar Mode With Hexadecimal Format
Figure 15-14. RTCHOUR Register
7
6
r-0
r-0
5
4
3
r-0
rw
rw
0
2
1
0
rw
rw
1
0
Hours
rw
Table 15-14. RTCHOUR Register Description
Bit
Field
Type
Reset
Description
7-5
0
R
0h
Always 0
4-0
Hours
RW
undefined
Hours (0 to 23)
15.3.14 RTCHOUR Register – Calendar Mode With BCD Format
Real-Time Clock Hours Register – Calendar Mode With BCD Format
Figure 15-15. RTCHOUR Register
7
6
5
0
r-0
4
3
2
Hours – high digit
r-0
rw
rw
Hours – low digit
rw
rw
rw
rw
Table 15-15. RTCHOUR Register Description
Bit
Field
Type
Reset
Description
7-6
0
R
0h
Always 0
5-4
Hours – high digit
RW
undefined
Hours – high digit (0 to 2)
3-0
Hours – low digit
RW
undefined
Hours – low digit (0 to 9)
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15.3.15 RTCDOW Register – Calendar Mode
Real-Time Clock Day of Week Register – Calendar Mode
Figure 15-16. RTCDOW Register
7
6
5
r-0
r-0
r-0
4
3
2
r-0
r-0
rw
0
1
0
Day of week
rw
rw
Table 15-16. RTCDOW Register Description
Bit
Field
Type
Reset
Description
7-3
0
R
0h
Always 0
2-0
Day of week
RW
undefined
Day of week (0 to 6)
15.3.16 RTCDAY Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Day of Month Register – Calendar Mode With Hexadecimal Format
Figure 15-17. RTCDAY Register
7
6
5
4
3
0
r-0
2
1
0
rw
rw
1
0
Day of month
r-0
r-0
rw
rw
rw
Table 15-17. RTCDAY Register Description
Bit
Field
Type
Reset
Description
7-5
0
R
0h
Always 0
4-0
Day of month
RW
undefined
Day of month (1 to 28, 29, 30, 31)
15.3.17 RTCDAY Register – Calendar Mode With BCD Format
Real-Time Clock Day of Month Register – Calendar Mode With BCD Format
Figure 15-18. RTCDAY Register
7
6
5
0
r-0
4
3
Day of month – high digit
r-0
rw
rw
2
Day of month – low digit
rw
rw
rw
rw
Table 15-18. RTCDAY Register Description
Bit
Field
Type
Reset
7-6
0
R
0h
Description
5-4
Day of month – high
digit
RW
undefined
Day of month – high digit (0 to 3)
3-0
Day of month – low
digit
RW
undefined
Day of month – low digit (0 to 9)
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15.3.18 RTCMON Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Month Register – Calendar Mode With Hexadecimal Format
Figure 15-19. RTCMON Register
7
6
r-0
r-0
5
4
3
2
r-0
r-0
rw
rw
0
1
0
rw
rw
1
0
Month
Table 15-19. RTCMON Register Description
Bit
Field
Type
Reset
Description
7-4
0
R
0h
Always 0
3-0
Month
RW
undefined
Month (1 to 12)
15.3.19 RTCMON Register – Calendar Mode With BCD Format
Real-Time Clock Month Register – Calendar Mode With BCD Format
Figure 15-20. RTCMON Register
7
6
5
4
0
r-0
3
2
Month – high
digit
r-0
r-0
rw
Month – low digit
rw
rw
rw
rw
Table 15-20. RTCMON Register Description
Bit
Field
Type
Reset
Description
7-5
0
R
0h
Always 0
4
Month – high digit
RW
undefined
Month – high digit (0 or 1)
3-0
Month – low digit
RW
undefined
Month – low digit (0 to 9)
438
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15.3.20 RTCYEARL Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Year Low-Byte Register – Calendar Mode With Hexadecimal Format
Figure 15-21. RTCYEARL Register
7
6
5
rw
rw
rw
4
3
2
1
0
rw
rw
rw
1
0
Year – low byte of 0 to 4095
rw
rw
Table 15-21. RTCYEARL Register Description
Bit
Field
Type
Reset
Description
7-0
Year
RW
undefined
Year – low byte of 0 to 4095
15.3.21 RTCYEARL Register – Calendar Mode With BCD Format
Real-Time Clock Year Low-Byte Register – Calendar Mode With BCD Format
Figure 15-22. RTCYEARL Register
7
6
5
4
3
Decade
rw
rw
2
Year – lowest digit
rw
rw
rw
rw
rw
rw
Table 15-22. RTCYEARL Register Description
Bit
Field
Type
Reset
Description
7-4
Decade
RW
undefined
Decade (0 to 9)
3-0
Year – lowest digit
RW
undefined
Year – lowest digit (0 to 9)
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15.3.22 RTCYEARH Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Year High-Byte Register – Calendar Mode With Hexadecimal Format
Figure 15-23. RTCYEARH Register
7
6
r-0
r-0
5
4
3
r-0
r-0
rw
0
2
1
0
Year – high byte of 0 to 4095
rw
rw
rw
1
0
Table 15-23. RTCYEARH Register Description
Bit
Field
Type
Reset
Description
7-4
0
R
0h
Always 0
3-0
Year
RW
undefined
Year – high byte of 0 to 4095
15.3.23 RTCYEARH Register – Calendar Mode With BCD Format
Real-Time Clock Year High-Byte Register – Calendar Mode With BCD Format
Figure 15-24. RTCYEARH Register
7
6
0
5
4
3
2
Century – high digit
r-0
rw
rw
Century – low digit
rw
rw
rw
rw
rw
Table 15-24. RTCYEARH Register Description
Bit
Field
Type
Reset
Description
7
0
R
0h
Always 0
6-4
Century – high digit
RW
undefined
Century – high digit (0 to 4)
3-0
Century – low digit
RW
undefined
Century – low digit (0 to 9)
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15.3.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Minutes Alarm Register – Calendar Mode With Hexadecimal Format
Figure 15-25. RTCAMIN Register
7
6
AE
0
rw
r-0
5
4
3
rw
rw
rw
2
1
0
rw
rw
rw
1
0
Minutes
Table 15-25. RTCAMIN Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
Alarm enable
6
0
R
0h
Always 0
5-0
Minutes
RW
undefined
Minutes (0 to 59)
15.3.25 RTCAMIN Register – Calendar Mode With BCD Format
Real-Time Clock Minutes Alarm Register – Calendar Mode With BCD Format
Figure 15-26. RTCAMIN Register
7
6
AE
5
4
3
Minutes – high digit
rw
rw
rw
2
Minutes – low digit
rw
rw
rw
rw
rw
Table 15-26. RTCAMIN Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
0h
Alarm enable
6-4
Minutes – high digit
RW
undefined
Minutes – high digit (0 to 5)
3-0
Minutes – low digit
RW
undefined
Minutes – low digit (0 to 9)
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15.3.26 RTCAHOUR Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Hours Alarm Register – Calendar Mode With Hexadecimal Format
Figure 15-27. RTCAHOUR Register
7
6
AE
5
4
3
r-0
rw
rw
0
rw
r-0
2
1
0
rw
rw
1
0
Hours
rw
Table 15-27. RTCAHOUR Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
Alarm enable
6-5
0
R
0h
Always 0
4-0
Hours
RW
undefined
Hours (0 to 23)
15.3.27 RTCAHOUR Register – Calendar Mode With BCD Format
Real-Time Clock Hours Alarm Register – Calendar Mode With BCD Format
Figure 15-28. RTCAHOUR Register
7
6
AE
0
rw
r-0
5
4
3
2
Hours – high digit
rw
rw
Hours – low digit
rw
rw
rw
rw
Table 15-28. RTCAHOUR Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
Alarm enable
6
0
R
0h
Always 0
5-4
Hours – high digit
RW
undefined
Hours – high digit (0 to 2)
3-0
Hours – low digit
RW
undefined
Hours – low digit (0 to 9)
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15.3.28 RTCADOW Register
Real-Time Clock Day of Week Alarm Register – Calendar Mode
Figure 15-29. RTCADOW Register
7
6
5
r-0
r-0
AE
4
3
2
r-0
r-0
rw
0
rw
1
0
Day of week
rw
rw
Table 15-29. RTCADOW Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
Alarm enable
6-3
0
R
0h
Always 0
2-0
Day of week
RW
undefined
Day of week (0 to 6)
15.3.29 RTCADAY Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Day of Month Alarm Register – Calendar Mode With Hexadecimal Format
Figure 15-30. RTCADAY Register
7
6
AE
5
4
3
0
rw
r-0
2
1
0
rw
rw
1
0
Day of month
r-0
rw
rw
rw
Table 15-30. RTCADAY Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
Alarm enable
6-5
0
R
0h
Always 0
4-0
Day of month
RW
undefined
Day of month (1 to 28, 29, 30, 31)
15.3.30 RTCADAY Register – Calendar Mode With BCD Format
Real-Time Clock Day of Month Alarm Register – Calendar Mode With BCD Format
Figure 15-31. RTCADAY Register
7
6
AE
0
rw
r-0
5
4
3
Day of month – high digit
rw
rw
2
Day of month – low digit
rw
rw
rw
rw
Table 15-31. RTCADAY Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
Alarm enable
6
0
R
0h
Always 0
5-4
Day of month – high
digit
RW
undefined
Day of month – high digit (0 to 3)
3-0
Day of month – low
digit
RW
undefined
Day of month – low digit (0 to 9)
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15.3.31 RTCPS0CTL Register
Real-Time Clock Prescale Timer 0 Control Register
Figure 15-32. RTCPS0CTL Register
15
14
Reserved
RT0SSEL
rw-0
rw-0
rw-0
rw-0
6
5
4
7
13
12
10
rw-0
r0
3
2
RT0PSDIV
Reserved
r0
11
9
Reserved
RT0IP
r0
r0
rw-0
rw-0
rw-0
8
RT0PSHOLD
r0
rw-1
1
0
RT0PSIE
RT0PSIFG
rw-0
rw-(0)
Table 15-32. RTCPS0CTL Register Description
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads as 0.
14
RT0SSEL
RW
0h
Prescale timer 0 clock source select. Selects clock input source to the RT0PS
counter. In real-time clock calendar mode, these bits are do not care. RT0PS
clock input is automatically set to the output of RT0PS.
0b = ACLK
1b = SMCLK
13-11
RT0PSDIV
RW
0h
Prescale timer 0 clock divide. These bits control the divide ratio of the RT0PS
counter. In real-time clock calendar mode, these bits are don't care for RT0PS
and RT1PS. RT0PS clock output is automatically set to /256. RT1PS clock
output is automatically set to /128.
00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 16
00b = Divide by 32
01b = Divide by 64
10b = Divide by 128
11b = Divide by 256
10-9
Reserved
R
0h
Reserved. Always reads as 0.
8
RT0PSHOLD
RW
1h
Prescale timer 0 hold. In real-time clock calendar mode, this bit is don't care.
RT0PS is stopped via the RTCHOLD bit.
0b = RT0PS operational
1b = RT0PS held
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-2
RT0IP
RW
0h
Prescale timer 0 interrupt interval
00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 16
00b = Divide by 32
01b = Divide by 64
10b = Divide by 128
11b = Divide by 256
1
RT0PSIE
RW
0h
Prescale timer 0 interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
0
RT0PSIFG
RW
0h
Prescale timer 0 interrupt flag
0b = No time event occurred
1b = Time event occurred
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15.3.32 RTCPS1CTL Register
Real-Time Clock Prescale Timer 1 Control Register
Figure 15-33. RTCPS1CTL Register
15
14
13
12
rw-0
rw-0
rw-0
6
5
4
RT1SSEL
rw-0
10
rw-0
r0
3
2
RT1PSDIV
7
Reserved
r0
11
9
Reserved
RT1IP
r0
r0
rw-0
rw-0
rw-0
8
RT1PSHOLD
r0
rw-1
1
0
RT1PSIE
RT1PSIFG
rw-0
rw-(0)
Table 15-33. RTCPS1CTL Register Description
Bit
Field
Type
Reset
Description
15-14
RT1SSEL
RW
0h
Prescale timer 1 clock source select. Selects clock input source to the RT1PS
counter. In real-time clock calendar mode, these bits are do not care. RT1PS
clock input is automatically set to the output of RT0PS.
00b = ACLK
01b = SMCLK
10b = Output from RT0PS
11b = Output from RT0PS
13-11
RT1PSDIV
RW
0h
Prescale timer 1 clock divide. These bits control the divide ratio of the RT0PS
counter. In real-time clock calendar mode, these bits are don't care for RT0PS
and RT1PS. RT0PS clock output is automatically set to /256. RT1PS clock
output is automatically set to /128.
00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 16
00b = Divide by 32
01b = Divide by 64
10b = Divide by 128
11b = Divide by 256
10-9
Reserved
R
0h
Reserved. Always reads as 0.
8
RT1PSHOLD
RW
1h
Prescale timer 1 hold. In real-time clock calendar mode, this bit is don't care.
RT1PS is stopped via the RTCHOLD bit.
0b = RT1PS operational
1b = RT1PS held
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-2
RT1IP
RW
0h
Prescale timer 1 interrupt interval
00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 16
00b = Divide by 32
01b = Divide by 64
10b = Divide by 128
11b = Divide by 256
1
RT1PSIE
RW
0h
Prescale timer 1 interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
0
RT1PSIFG
RW
0h
Prescale timer 1 interrupt flag
0b = No time event occurred
1b = Time event occurred
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15.3.33 RT0PS Register
Real-Time Clock Prescale Timer 0 Counter Register
Figure 15-34. RT0PS Register
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
RT0PS
Table 15-34. RT0PS Register Description
Bit
Field
Type
Reset
Description
7-0
RT0PS
RW
Undefined
Prescale timer 0 counter value
15.3.34 RT1PS Register
Real-Time Clock Prescale Timer 1 Counter Register
Figure 15-35. RTPS1 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RT1PS
rw
rw
rw
rw
Table 15-35. RT1PS Register Description
Bit
Field
Type
Reset
Description
7-0
RT1PS
RW
Undefined
Prescale timer 1 counter value
15.3.35 RTCIV Register
Real-Time Clock Interrupt Vector Register
Figure 15-36. RTCIV Register
15
14
13
12
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-(0)
r-(0)
r-(0)
r0
RTCIV
r0
r0
r0
r0
7
6
5
4
RTCIV
r0
r0
r0
r-(0)
Table 15-36. RTCIV Register Description
Bit
Field
Type
Reset
Description
15-0
RTCIV
R
0h
Real-time clock interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG
04h = Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG
06h = Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG
08h = Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG
0Ah = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG
0Ch = Reserved
0Eh = Reserved
10h = Reserved ; Interrupt Priority: Lowest
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Chapter 16
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Real-Time Clock D (RTC_D)
The real-time clock RTC_D module provides clock counters with calendar mode, a flexible programmable
alarm, and calibration. The RTC_D also supports operation in LPMx.5. This chapter describes the RTC_D
module.
Topic
16.1
16.2
16.3
...........................................................................................................................
Page
Real-Time Clock RTC_D Introduction ................................................................. 448
RTC_D Operation ............................................................................................. 450
RTC_D Registers ............................................................................................. 457
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16.1 Real-Time Clock RTC_D Introduction
The RTC_D module provides configurable clock counters.
RTC_D features include:
• Configurable for real-time clock with calendar function ar general-purpose counter
• Real-time clock and calendar mode providing seconds, minutes, hours, day of week, day of month,
month, and year (including leap year correction)
• Interrupt capability
• Selectable BCD or binary format in real-time clock and calendar mode
• Programmable alarms in real-time clock and calendar mode
• Calibration logic for time offset correction in real-time clock and calendar mode
• Operation in LPMx.5
The RTC_D block diagram is shown in Figure 16-1.
NOTE:
Real-time clock initialization
Most RTC_D module registers have no initial condition. These registers must be configured
by user software before use.
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RT0PSHOLD
RT0IP
EN
RT0PS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
from 32kHz Crystal Osc.
3
111
110
100
101
011
001
3
010
RT0PSDIV
000
111
110
101
100
011
010
001
000
Set_RT0PSIFG
RTCCALS RTCCAL RTCMODE
5
Calibration
Logic EN
RT1PSHOLD
RT1SSEL
2
3
RT1PS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Keepout
Logic
RTCSSEL
2
00
01
10
11
Set_RT1PSIFG
111
110
101
100
011
010
3
001
111
110
101
100
011
010
001
000
000
RT1PSDIV
RT1IP
EN
00
01
10
11
Set_RTCRDYIFG
RTCHOLD
RTCBCD
EN
31 ... 24
23 ... 16
RTCNT4/
RTCDOW
RTCNT3/
RTCHOUR
15 ...
8
RTCNT2/
RTCMIN
7
...
0
RTCNT1/
RTCSEC
8-bit overflow/minute changed
16-bit overflow/hour changed
24-bit overflow/midnight
32-bit overflow/noon
RTCTEV
2
00 Set_RTCTEVIFG
01
10
11
EN
Calendar
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
EN
Alarm
RTCADOW
RTCADAY
RTCAHOUR
Set_RTCAIFG
RTCAMIN
Figure 16-1. RTC_D Block Diagram
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16.2 RTC_D Operation
The RTC_D module can be configured as a real-time clock with calendar function (calendar mode) or as a
32-bit general prupose counter (counter mode) with the RTCMODE bit.
16.2.1 Counter Mode
Counter mode is selected when RTCMODE is reset. In this mode, a 32-bit counter is provided that is
directly accessible by software. Switching from calendar mode to counter mode does not reset the count
value (RTCNT1, RTCNT2, RTCNT3, RTCNT4) nor the prescale counters (RT0PS, RT1PS). These
registers must be configured by user software before use.
The clock to increment the counter can be sourced from the 32kHz cyrstal oscillator, or prescaled versions
of the 32kHz cyrstal oscillator clock. Prescaled versions are sourced from the prescale dividers (RT0PS
and RT1PS). RT0PS and RT1PS can output /2, /4, /8, 16, /32, /64, /128, and /256 versions of the 32kHz
clock. The output of RT0PS can be cascaded with RT1PS. The cascaded output can also be used as a
clock source input to the 32-bit counter.
Four individual 8-bit counters are cascaded to provide the 32-bit counter. This provides 8-bit, 16-bit, 24-bit,
or 32-bit overflow intervals of the counter clock. The RTCTEV bits select the respective trigger event. An
RTCTEV event can trigger an interrupt by setting the RTCTEVIE bit. Each counter, RTCNT1 through
RTCNT4, is individually accessible and may be written to.
RT0PS and RT1PS can be configured as two 8-bit counters or cascaded into a single 16-bit counter.
RT0PS and RT1PS can be halted on an individual basis by setting their respective RT0PSHOLD and
RT1PSHOLD bits. When RT0PS is cascaded with RT1PS, setting RT0PSHOLD causes both RT0PS and
RT1PS to be halted. The 32-bit counter can be halted several ways depending on the configuration. If the
32-bit counter is sourced directly by the 32kHz cyrstal clock, it can be halted by setting RTCHOLD. If it is
sourced from the output of RT1PS, it can be halted by setting RT1PSHOLD or RTCHOLD. Finally, if it is
sourced from the cascaded outputs of RT0PS and RT1PS, it can be halted by setting RT0PSHOLD,
RT1PSHOLD, or RTCHOLD.
NOTE:
Accessing the RTCNT1, RTCNT2, RTCNT3, RTCNT4, RT0PS, RT1PS registers
When the counter clock is asynchronous to the CPU clock, any read from any RTCNT1,
RTCNT2, RTCNT3, RTCNT4, RT0PS, or RT1PS register should occur while the counter is
not operating. Otherwise, the results may be unpredictable. Alternatively, the counter may be
read multiple times while operating, and a majority vote taken in software to determine the
correct reading. Any write to these registers takes effect immediately.
16.2.2 Calendar Mode
Calendar mode is selected when RTCMODE is set. In calendar mode, the RTC_D module provides
seconds, minutes, hours, day of week, day of month, month, and year in selectable BCD or hexadecimal
format. The calendar includes a leap-year algorithm that considers all years evenly divisible by four as
leap years. This algorithm is accurate from the year 1901 through 2099. Switching from counter mode to
calendar mode does not reset the calendar registers (RTCSEC, RTCMIN, RTCHOUR, RTCDAY,
RTCDOW, and RTCYEAR) nor the prescale counters (RT0PS, RT1PS). These registers must be
configured by user software before use.
16.2.2.1 Real-Time Clock and Prescale Dividers
The prescale dividers, RT0PS and RT1PS, are automatically configured to provide a 1-s clock interval for
the RTC_D. The low-frequency oscillator must be operated at 32768 Hz (nominal) for proper RTC_D
operation. RT0PS is sourced directly from the low-frequency crystal oscillator. RT1PS is cascaded with
the output ACLK/256 of RT0PS. The RTC_A is sourced with the /128 output of RT1PS, thereby providing
the required 1-s interval. Switching from counter to calendar mode clears the seconds, minutes, hours,
day-of-week, and year counts and sets day-of-month and month counts to 1. In addition, RT0PS and
RT1PS are cleared. When RTCBCD = 1, BCD format is selected for the calendar registers. Setting
RTCHOLD halts the real-time counters and prescale counters, RT0PS and RT1PS.
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16.2.2.2 Real-Time Clock Alarm Function
The RTC_D module provides for a flexible alarm system. There is a single user-programmable alarm that
can be programmed based on the settings contained in the alarm registers for minutes, hours, day of
week, and day of month. The user-programmable alarm function is only available in the calendar mode of
operation.
Each alarm register contains an alarm enable (AE) bit that can be used to enable the respective alarm
register. By setting AE bits of the various alarm registers, a variety of alarm events can be generated.
• Example 1: A user wishes to set an alarm every hour at 15 minutes past the hour, that is, at 00:15:00,
01:15:00, 02:15:00, and so on. This is possible by setting RTCAMIN to 15. By setting the AE bit of the
RTCAMIN and clearing all other AE bits of the alarm registers, the alarm is enabled. When enabled,
the RTCAIFG is set when the count transitions from 00:14:59 to 00:15:00, 01:14:59 to 01:15:00,
02:14:59 to 02:15:00, etc.
• Example 2: A user wishes to set an alarm every day at 04:00:00. This is possible by setting
RTCAHOUR to 4. By setting the AE bit of the RTCHOUR and clearing all other AE bits of the alarm
registers, the alarm is enabled. When enabled, the RTCAIFG is set when the count transitions from
03:59:59 to 04:00:00.
• Example 3: A user wishes to set an alarm for 06:30:00. RTCAHOUR would be set to 6 and RTCAMIN
would be set to 30. By setting the AE bits of RTCAHOUR and RTCAMIN, the alarm is enabled. Once
enabled, the RTCAIFG is set when the time count transitions from 06:29:59 to 06:30:00. In this case,
the alarm event occurs every day at 06:30:00.
• Example 4: A user wishes to set an alarm every Tuesday at 06:30:00. RTCADOW would be set to 2,
RTCAHOUR would be set to 6 and RTCAMIN would be set to 30. By setting the AE bits of
RTCADOW, RTCAHOUR, and RTCAMIN, the alarm is enabled. Once enabled, the RTCAIFG is set
when the time count transitions from 06:29:59 to 06:30:00 and the RTCDOW transitions from 1 to 2.
• Example 5: A user wishes to set an alarm the fifth day of each month at 06:30:00. RTCADAY would be
set to 5, RTCAHOUR would be set to 6 and RTCAMIN would be set to 30. By setting the AE bits of
RTCADAY, RTCAHOUR, and RTCAMIN, the alarm is enabled. Once enabled, the RTCAIFG is set
when the time count transitions from 06:29:59 to 06:30:00 and the RTCDAY equals 5.
NOTE:
Setting the alarm
Prior to setting an initial alarm, all alarm registers including the AE bits should be cleared.
To prevent potential erroneous alarm conditions from occurring, the alarms should be
disabled by clearing the RTCAIE, RTCAIFG, and AE bits prior to writing initial or new time
values to the RTC time registers.
NOTE:
Invalid alarm settings
Invalid alarm settings are not checked via hardware. It is the user's responsibility that valid
alarm settings are entered.
NOTE:
Invalid time and date values
Writing of invalid date and/or time information or data values outside the legal ranges
specified in the RTCSEC, RTCMIN, RTCHOUR, RTCDAY, RTCDOW, RTCYEAR,
RTCAMIN, RTCAHOUR, RTCADAY, and RTCADOW registers can result in unpredictable
behavior.
Also after switching from counter mode to calendar mode the registers must be correctly
initialized to ensure values inside their legal ranges.
16.2.2.3 Reading or Writing Real-Time Clock Registers in Calendar Mode
Because the system clock may be asynchronous to the RTC_D clock source, special care must be taken
when accessing the real-time clock registers.
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The real-time clock registers are updated once per second. To prevent reading any real-time clock register
at the time of an update that could result in an invalid time being read, a keep-out window is provided. The
keep-out window is centered approximately 128/32768 seconds around the update transition. The readonly RTCRDY bit is reset during the keep-out window period and set outside the keep-out the window
period. Any read of the clock registers while RTCRDY is reset is considered to be potentially invalid, and
the time read should be ignored.
An easy way to safely read the real-time clock registers is to utilize the RTCRDYIFG interrupt flag. Setting
RTCRDYIE enables the RTCRDYIFG interrupt. Once enabled, an interrupt is generated based on the
rising edge of the RTCRDY bit, causing the RTCRDYIFG to be set. At this point, the application has
nearly a complete second to safely read any or all of the real-time clock registers. This synchronization
process prevents reading the time value during transition. The RTCRDYIFG flag is reset automatically
when the interrupt is serviced, or it can be reset with software.
In counter mode, the RTCRDY bit remains reset. RTCRDYIE is a don't care and RTCRDYIFG remains
reset.
NOTE:
Reading or writing real-time clock registers
When the counter clock is asynchronous to the CPU clock, any read from any RTCSEC,
RTCMIN, RTCHOUR, RTCDOW, RTCDAY, RTCMON, or RTCYEAR register while the
RTCRDY is reset may result in invalid data being read. To safely read the counting registers,
either polling of the RTCRDY bit or the synchronization procedure previously described can
be used. Alternatively, the counter register can be read multiple times while operating, and a
majority vote taken in software to determine the correct reading. Reading the RT0PS and
RT1PS can only be handled by reading the registers multiple times and a majority vote taken
in software to determine the correct reading or by halting the counters.
Any write to any counting register takes effect immediately. However, the clock is stopped
during the write. In addition, RT0PS and RT1PS registers are reset. This could result in
losing up to 1 second during a write. Writing of data outside the legal ranges or invalid time
stamp combinations results in unpredictable behavior.
452
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16.2.3 Real-Time Clock Interrupts
The RTC_D module has six interrupt sources available, each with independent enables and flags.
16.2.3.1 Real-Time Clock Interrupts in Calendar Mode
Six sources for interrupts are available, namely RT0PSIFG, RT1PSIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, and RTCOFIFG. These flags are prioritized and combined to source a single interrupt vector.
The interrupt vector register (RTCIV) is used to determine which flag requested an interrupt.
The highest-priority enabled interrupt generates a number in the RTCIV register (see register description).
This number can be evaluated or added to the program counter (PC) to automatically enter the
appropriate software routine. Disabled RTC interrupts do not affect the RTCIV value.
Any access, read or write, of the RTCIV register automatically resets the highest-pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
In addition, all flags can be cleared via software.
The user-programmable alarm event sources the real-time clock interrupt, RTCAIFG. Setting RTCAIE
enables the interrupt. In addition to the user-programmable alarm, the RTC_D module provides for an
interval alarm that sources real-time clock interrupt, RTCTEVIFG. The interval alarm can be selected to
cause an alarm event when RTCMIN changed or RTCHOUR changed, every day at midnight (00:00:00)
or every day at noon (12:00:00). The event is selectable with the RTCTEV bits. Setting the RTCTEVIE bit
enables the interrupt.
The RTCRDY bit sources the real-time clock interrupt, RTCRDYIFG, and is useful in synchronizing the
read of time registers with the system clock. Setting the RTCRDYIE bit enables the interrupt.
RT0PSIFG can be used to generate interrupt intervals selectable by the RT0IP bits. RT0PS is sourced
with low-frequency oscillator clock at 32768 Hz, so intervals of 16384 Hz, 8192 Hz, 4096 Hz, 2048 Hz,
1024 Hz, 512 Hz, 256 Hz, or 128 Hz are possible. Setting the RT0PSIE bit enables the interrupt.
RT1PSIFG can be used to generate interrupt intervals selectable by the RT1IP bits. RT1PS is sourced
with the output of RT0PS, which is 128 Hz (32768/256 Hz). Therefore, intervals of 64 Hz, 32 Hz, 16 Hz,
8 Hz, 4 Hz, 2 Hz, 1 Hz, or 0.5 Hz are possible. Setting the RT1PSIE bit enables the interrupt.
The RTCOFIFG bit flags a failure of the 32-kHz crystal oscillator. It's main purpose is to wake-up the CPU
from LPM3.5 in case an oscillator failure occurred.
16.2.3.2
Real-Time Clock Interrupts in Counter Mode
In counter mode, four interrupt sources are available: RT0PSIFG, RT1PSIFG, RTCTEVIFG, and
RTCOFIFG. RTCAIFG and RTCRDYIFG are cleared. RTCRDYIE and RTCAIE are don't care.
RT0PSIFG can be used to generate interrupt intervals selectable by the RT0IP bits. In counter mode,
divide ratios of /2, /4, /8, /16, /32, /64, /128, and /256 of the clock source are possible. Setting the
RT0PSIE bit enables the interrupt.
RT1PSIFG can be used to generate interrupt intervals selectable by the RT1IP bits. In counter mode,
RT1PS is sourced with low-frequency oscillator clock, or the output of RT0PS, so divide ratios of /2, /4, /8,
/16, /32, /64, /128, and /256 of the respective clock source are possible. Setting the RT1PSIE bit enables
the interrupt.
In Counter Mode, the RTC_D module provides for an interval timer that sources real-time clock interrupt,
RTCTEVIFG. The interval timer can be selected to cause an interrupt event when an 8-bit, 16-bit, 24-bit,
or 32-bit overflow occurs within the 32-bit counter. The event is selectable with the RTCTEV bits. Setting
the RTCTEVIE bit enables the interrupt.
The RTCOFIFG bit flags a failure of the 32-kHz crystal oscillator. It's main purpose is to wake-up the CPU
from LPM3.5 in case an oscillator failure occurred.
16.2.3.2.1 RTCIV Software Example
The following software example shows the recommended use of RTCIV and the handling overhead. The
RTCIV value is added to the PC to automatically jump to the appropriate routine.
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The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself.
; Interrupt handler for RTC interrupt flags.
RTC_HND
ADD &RTCIV,PC
RETI
JMP RTCRDYIFG_HND
JMP RTCTEVIFG_HND
JMP RTCAIFG_HND
JMP RT0PSIFG_HND
JMP RT1PSIFG_HND
JMP RTCOFIFG_HND
RETI
;
;
;
;
;
;
;
;
;
;
Interrupt latency
Add offset to Jump table
Vector 0: No interrupt
Vector 2: RTCRDYIFG
Vector 4: RTCTEVIFG
Vector 6: RTCAIFG
Vector 8: RT0PSIFG
Vector A: RT1PSIFG
Vector C: RTCOFIFG
Vector E: Reserved
6
3
5
2
2
5
5
5
5
5
RTCRDYIFG_HND
...
RETI
; Vector 2: RTCRDYIFG Flag
; Task starts here
; Back to main program
5
RTCTEVIFG_HND
...
RETI
; Vector 4: RTCTEVIFG Flag
; Task starts here
; Back to main program
5
RTCAIFG_HND
...
RETI
; Vector 6: RTCAIFG Flag
; Task starts here
; Back to main program
5
RT0PSIFG_HND
...
RETI
; Vector 8: RT0PSIFG Flag
; Task starts here
; Back to main program
5
RT1PSIFG_HND
...
RETI
; Vector A: RT1PSIFG Flag
; Task starts here
; Back to main program
5
RTCOFIFG_HND
...
RETI
; Vector C: RTCOFIFG Flag
; Task starts here
; Back to main program
5
16.2.4 Real-Time Clock Calibration
The RTC_D module has calibration logic that allows for adjusting the crystal frequency in approximately
+4-ppm or –2-ppm steps, allowing for higher time keeping accuracy from standard crystals.The RTCCALx
bits are used to adjust the frequency. When RTCCALS is set, each RTCCALx LSB causes a ≈ +4-ppm
adjustment. When RTCCALS is cleared, each RTCCALx LSB causes a ≈ –2-ppm adjustment. Calibration
is available in calendar mode only. In counter mode (RTCMODE=0), the calibration logic is disabled.
Calibration is accomplished by periodically adjusting the RT1PS counter based on the RTCCALS and
RTCCALx settings. In calendar mode, the RT0PS divides the nominial 37268-Hz low-frequency (LF)
crystal clock input by 256. A 60-minute period has 32768 cycles/sec × 60 sec/min × 60 min = 117964800
cycles. Therefore, a –2-ppm reduction in frequency (down calibration) approximately equates to adding an
additional 256 cycles every 117964800 cycles (256/117964800 = 2.17 ppm). This is accomplished by
holding the RT1PS counter for one additional clock of the RT0PS output within a 60-minute period.
Similary, a +4-ppm increase in frequency (up calibration) approximately equates to removing 512 cycles
every 117964800 cycle (512/117964800 = 4.34 ppm). This is accomplished by incrementing the RT1PS
counter for two additional clocks of the RT0PS output within a 60-minute period. Each RTCCALx
calibration bit causes either 256 LF crystal clock cycles to be added every 60 minutes or 512 LF crystal
clock cycles to be subtracted every 60 minutes, giving a frequency adjustment of approximately -2 ppm or
+4 ppm, respectively.
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To calibrate the frequency, the RTCCLK output signal is available at a pin. RTCCALF bits can be used to
select the frequency rate of the output signal, either no signal, 512 Hz, 256 Hz, or 1 Hz.
The basic flow to calibrate the frequency is as follows:
1. Configure the RTCCLK pin.
2. Measure the RTCCLK output signal with an appropriate resolution frequency counter ; that is, within
the resolution required.
3. Compute the absolute error in ppm: Absolute error (ppm) = |106 (fMEASURED - fRTCCLK)/fRTCCLK|, where
fRTCCLK is the expected frequency of 512 Hz, 256 Hz, or 1 Hz.
4. Adjust the frequency by performing the following:
(a) If the frequency is too low, set RTCCALS = 1 and apply the appropriate RTCCALx bits, where
RTCCALx = (Absolute Error) / 4.34 rounded to the nearest integer
(b) If the frequency is too high, clear RTCCALS = 0 and apply the appropriate RTCCALx bits, where
RTCCALx = (Absolute Error) / 2.17 rounded to the nearest integer
For example, assume that RTCCLK is configured to output at a frequency of 512 Hz. The measured
RTCCLK is 511.9658 Hz. This frequency error is approximately 66.8 ppm too low. To increase the
frequency by 66.8 ppm, RTCCALS would be set, and RTCCALx would be set to 15 (66.8/4.34). Similarly,
assume that the measured RTCCLK is 512.0125 Hz. The frequency error is approximately 24.4 ppm too
high. To decrease the frequency by 24.4 ppm, RTCCALS would be cleared, and RTCCAL would be set to
11 (24.4/2.17).
The calibration corrects only initial offsets and does not adjust for temperature and aging effects. These
effects can be handled by periodically measuring temperature and using the crystal's charateristic curve to
adjust the ppm based on temperature, as required. In counter mode (RTCMODE = 0), the calibration logic
is disabled.
NOTE:
Calibration output frequency
The 512-Hz and 256-Hz output frequencies observed at the RTCCLK pin are not affected by
changes in the calibration settings since these output frequencies are generated prior to the
calibration logic. The 1-Hz output frequency is affected by changes in the calibration settings.
Because the frequency change is small and infrequent over a very long time interval, it can
be difficult to observe.
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16.2.5 Real-Time Clock Operation in LPMx.5 Low-Power Mode
The regulator of the Power Management Module (PMM) is disabled upon entering LPMx.5, which causes
most of the RTC_D configuration registers to be lost; only the counters are retained. Table 16-1 lists the
retained registers in LPMx.5. Also the configuration of the interrupts is stored so that the configured
interrupts can cause a wakeup upon exit from LPMx.5.
The following interrupt flags can be used as RTC_D wake-up interrupt sources:
•
•
•
•
RTCTEVIFG: Real-time clock time event interrupt flag
RTCAIFG: Real-time clock alarm interrupt flag
RT1PSIFG: Prescale timer 1 interrupt flag
RTCOFIFG: 32-kHz crystal oscillator fault interrupt flag
After restoring the configuration registers and clearing LOCKLPM5, the interrupts can be serviced as
usual. The detailed flow is as follows:
1. Set all I/Os to general purpose I/Os and configure as needed. Optionally configure input interrupt pins
for wake-up. Configure RTC_D interrupts for wake-up (set RTCTEVIE, RTCAIE, RT1PSIE, or
RTCOFIE. If the alarm interrupt is also used as wake-up event, the alarm registers must be configured
as needed).
2. Ensure clock system settings allow LPMx.5 entry according to Table 3-1 in UCS chapter.
3. Enter LPMx.5 with LPMx.5 entry sequence.
bis #PMMKEY + REGOFF, &PMMCTL0
bis #LPM4, SR
4. LOCKLPM5 is automatically set by hardware upon entering LPMx.5, the core voltage regulator is
disabled, and all clocks are disabled except for the 32-kHz crystal oscillator clock if the RTC is enabled
with RTCHOLD = 0.
5. An LPMx.5 wake-up event, such as an edge on a wake-up input pin, are an RTC_D interrupt event
and start the BOR entry sequence together with the core voltage regulator. All peripheral registers are
set to their default conditions. The I/O pin state remains locked as well as the interrupt configuration for
the RTC_D.
6. The device can be configured. The I/O configuration and the RTC_D control and interrupt configuration
that was not retained during LPMx.5 should be restored to the values prior to entering LPMx.5. After
restoring the configuration registers the LOCKLPM5 bit can be cleared, this releases the I/O pin
conditions as well as the RTC_D interrupt configuration.
7. After enabling I/O and RTC_D interrupts, the interrupt that caused the wake-up can be serviced.
If the RTC is enabled (RTCHOLD = 0), the 32-kHz oscillator remains active during LPMx.5. The fault
detection also remains functional. If a fault occurs during LPMx.5 and the RTCOFIE was set before
entering LPMx.5, a wake-up event is issued.
456
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16.3 RTC_D Registers
The RTC_D registers are listed in Table 16-1. This table also lists the retention during LPMx.5. Registers
that are not retained during LPMx.5 must be restored after exit from LPMx.5. The base address for the
RTC_D module registers can be found in the device-specific data sheet. The address offsets are given in
Table 16-1.
NOTE: Most registers have word or byte register access. For a generic register ANYREG, the suffix
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 16-1. RTC_D Registers
Offset
Acronym
Register Name
Type
Access
Reset
LPMx.5 or
Backup
00h
RTCCTL01
Real-Time Clock Control 0, 1
Read/write
Word
4000h
not retained
00h
RTCCTL0
Real-Time Clock Control 0
Read/write
Byte
00h
not retained
Real-Time Clock Control 1
Read/write
Byte
40h
not retained
or RTCCTL01_L
01h
RTCCTL1
or RTCCTL01_H
02h
RTCCTL23
Real-Time Clock Control 2, 3
Read/write
Word
0000h
retained
02h
RTCCTL2
Real-Time Clock Control 2
Read/write
Byte
00h
retained
Real-Time Clock Control 3
Read/write
Byte
00h
retained
Real-Time Prescale Timer 0 Control
Read/write
Word
0000h
not retained
Read/write
Byte
00h
not retained
Read/write
Byte
00h
not retained
Read/write
Word
0000h
not retained
Read/write
Byte
00h
not retained
Read/write
Byte
00h
not retained
or RTCCTL23_L
03h
RTCCTL3
or RTCCTL23_H
08h
RTCPS0CTL
08h
RTCPS0CTLL
or RTCPS0CTL_L
09h
RTCPS0CTLH
or RTCPS0CTL_H
0Ah
RTCPS1CTL
0Ah
RTCPS1CTLL
Real-Time Prescale Timer 1 Control
or RTCPS1CTL_L
0Bh
RTCPS0CTLH
or RTCPS0CTL_H
0Ch
RTCPS
Real-Time Prescale Timer 0, 1 Counter
Read/write
Word
none
retained
0Ch
RT0PS
Real-Time Prescale Timer 0 Counter
Read/write
Byte
none
retained
Real-Time Prescale Timer 1 Counter
Read/write
Byte
none
retained
not retained
or RTCPS_L
0Dh
RT1PS
or RTCPS_H
0Eh
RTCIV
Real Time Clock Interrupt Vector
Read
Word
0000h
10h
RTCTIM0
Real-Time Clock Seconds, Minutes
Read/write
Word
undefined retained
or RTCNT12
Real-Time Counter 1, 2
RTCSEC
Real-Time Clock Seconds
Read/write
Byte
undefined retained
RTCNT1
Real-Time Counter 1
Read/write
Byte
undefined retained
10h
or RTCTIM0_L
11h
RTCMIN
Real-Time Clock Minutes
RTCNT2
Real-Time Counter 2
or RTCTIM0_H
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Table 16-1. RTC_D Registers (continued)
Offset
Acronym
Register Name
Type
Access
Reset
12h
RTCTIM1
Real-Time Clock Hour, Day of Week
Read/write
Word
undefined retained
or RTCNT34
Real-Time Counter 3, 4
RTCHOUR
Real-Time Clock Hour
Read/write
Byte
undefined retained
RTCNT3
Real-Time Counter 3
Read/write
Byte
undefined retained
12h
LPMx.5 or
Backup
or RTCTIM1_L
13h
RTCDOW
Real-Time Clock Day of Week
RTCNT4
Real-Time Counter 4
or RTCTIM1_H
14h
RTCDATE
Real-Time Clock Date
Read/write
Word
undefined retained
14h
RTCDAY
Real-Time Clock Day of Month
Read/write
Byte
undefined retained
Real-Time Clock Month
Read/write
Byte
undefined retained
or RTCDATE_L
15h
RTCMON
or RTCDATE_H
16h
RTCYEAR
Real-Time Clock Year (1)
Read/write
Word
undefined retained
18h
RTCAMINHR
Real-Time Clock Minutes, Hour Alarm
Read/write
Word
undefined retained
18h
RTCAMIN
Real-Time Clock Minutes Alarm
Read/write
Byte
undefined retained
Real-Time Clock Hours Alarm
Read/write
Byte
undefined retained
or RTCAMINHR_L
19h
RTCAHOUR
or RTCAMINHR_H
1Ah
RTCADOWDAY
Real-Time Clock Day of Week, Day of
Month Alarm
Read/write
Word
undefined retained
1Ah
RTCADOW
Real-Time Clock Day of Week Alarm
Read/write
Byte
undefined retained
Real-Time Clock Day of Month Alarm
Read/write
Byte
undefined retained
or
RTCADOWDAY_L
1Bh
RTCADAY
or
RTCADOWDAY_H
1Ch
BIN2BCD
Binary-to-BCD conversion register
Read/write
Word
00h
not retained
1Eh
BCD2BIN
BCD-to-binary conversion register
Read/write
Word
00h
not retained
(1)
458
Do not access the year register RTCYEAR in byte mode.
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16.3.1 RTCCTL0 Register
Real-Time Clock Control 0 Register
Figure 16-2. RTCCTL0 Register
7
6
RTCOFIE
(1)
RTCTEVIE
rw-0
(1)
5
(1)
RTCAIE
rw-0
(1)
rw-0
4
3
2
1
0
RTCRDYIE
RTCOFIFG
RTCTEVIFG
RTCAIFG
RTCRDYIFG
rw-0
rw-(0)
rw-(0)
rw-(0)
rw-(0)
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required.
Table 16-2. RTCCTL0 Register Description
Bit
Field
Type
Reset
Description
7
RTCOFIE
RW
0h
32-kHz crystal oscillator fault interrupt enable. This interrupt can be used as
LPMx.5 wake-up event.
0b = Interrupt not enabled
1b = Interrupt enabled (LPMx.5 wake-up enabled)
6
RTCTEVIE
RW
0h
Real-time clock time event interrupt enable. In modules supporting LPMx.5 this
interrupt can be used as LPMx.5 wake-up event.
0b = Interrupt not enabled
1b = Interrupt enabled (LPMx.5 wake-up enabled)
5
RTCAIE
RW
0h
Real-time clock alarm interrupt enable. In modules supporting LPMx.5 this
interrupt can be used as LPMx.5 wake-up event.
0b = Interrupt not enabled
1b = Interrupt enabled (LPMx.5 wake-up enabled)
4
RTCRDYIE
RW
0h
Real-time clock ready interrupt enable.
0b = Interrupt not enabled
1b = Interrupt enabled
3
RTCOFIFG
RW
0h
32-kHz crystal oscillator fault interrupt flag. This interrupt can be used as LPMx.5
wake-up event. It also indicates a clock failure during backup operation.
0b = No interrupt pending
1b = Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset.
2
RTCTEVIFG
RW
0h
Real-time clock time event interrupt flag. In modules supporting LPMx.5 this
interrupt can be used as LPMx.5 wake-up event.
0b = No time event occurred.
1b = Time event occurred.
1
RTCAIFG
RW
0h
Real-time clock alarm interrupt flag. In modules supporting LPMx.5 this interrupt
can be used as LPMx.5 wake-up event.
0b = No time event occurred.
1b = Time event occurred.
0
RTCRDYIFG
RW
0h
Real-time clock ready interrupt flag
0b = RTC cannot be read safely.
1b = RTC can be read safely.
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16.3.2 RTCCTL1 Register
Real-Time Clock Control Register 1
Figure 16-3. RTCCTL1 Register
7
6
RTCBCD
RTCHOLD
rw-(0)
(1)
5
(1)
4
RTCMODE
rw-(1)
(1)
rw-(1)
RTCRDY
r-(1)
3
2
RTCSSELx
rw-(0)
1
(1)
rw-(0)
0
RTCTEVx
(1)
rw-(0)
rw-(0)
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required.
Table 16-3. RTCCTL1 Register Description
Bit
Field
Type
Reset
Description
7
RTCBCD
RW
0h
Real-time clock BCD select. Selects BCD counting for real-time clock. Applies to
calendar mode (RTCMODE = 1) only; setting is ignored in counter mode.
0b = Binary hexadecimal code selected
1b = BCD Binary coded decimal (BCD) code selected
6
RTCHOLD
RW
1h
Real-time clock hold
0b = Real-time clock (32-bit counter or calendar mode) is operational.
1b = In counter mode (RTCMODE = 0), only the 32-bit counter is stopped. In
calendar mode (RTCMODE = 1), the calendar is stopped as well as the prescale
counters, RT0PS and RT1PS. RT0PSHOLD and RT1PSHOLD are don't care.
5
RTCMODE
RW
1h
Real-time clock mode
0b = 32-bit counter mode
1b = Calendar mode. Switching between counter and calendar mode does not
reset the real-time clock/counter registers. These registers must be configured by
user software before use.
4
RTCRDY
RW
1h
Real-time clock ready
0b = RTC time values in transition (calendar mode only).
1b = RTC time values safe for reading (calendar mode only). This bit indicates
when the real-time clock time values are safe for reading (calendar mode only).
In counter mode, RTCRDY remains cleared.
3-2
RTCSSELx
RW
0h
Real-time clock source select. In counter mode, selects clock input source to the
32-bit counter. In calendar mode, these bits are don't care. The clock input is
automatically set to the output of RT1PS.
00b = 32-kHz crystal oscillator clock
01b = 32-kHz crystal oscillator clock
10b = Output from RT1PS
11b = Output from RT1PS
1-0
RTCTEVx
RW
0h
Real-time clock time event. Specifies the interrupt interval.
Calendar Mode (RTCMODE = 1)
00b = Minute changed
01b = Hour changed
10b = Every day at midnight (00:00)
11b = Every day at noon (12:00)
Counter Mode (RTCMODE = 0)
00b = 8-bit overflow
01b = 16-bit overflow
10b = 24-bit overflow
11b = 32-bit overflow
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16.3.3 RTCCTL2 Register
Real-Time Clock Control 2 Register
Figure 16-4. RTCCTL2 Register
7
6
RTCCALS
Reserved
rw-(0)
r0
5
4
3
rw-(0)
rw-(0)
rw-(0)
2
1
0
rw-(0)
rw-(0)
rw-(0)
RTCCALx
Table 16-4. RTCCTL2 Register Description
Bit
Field
Type
Reset
Description
7
RTCCALS
RW
0h
Real-time clock calibration sign
0b = Frequency adjusted down
1b = Frequency adjusted up
6
Reserved
R
0h
Reserved. Always reads as 0.
5-0
RTCCALx
RW
0h
Real-time clock calibration. Each LSB represents approximately +4-ppm
(RTCCALS = 1) or a –2-ppm (RTCCALS = 0) adjustment in frequency.
16.3.4 RTCCTL3 Register
Real-Time Clock Control 3 Register
Figure 16-5. RTCCTL3 Register
7
6
5
4
3
2
1
Reserved
r0
r0
r0
0
RTCCALFx
r0
r0
r0
rw-(0)
rw-(0)
Table 16-5. RTCCTL3 Register Description
Bit
Field
Type
Reset
Description
7-2
Reserved
R
0h
Reserved. Always reads as 0.
1-0
RTCCALFx
RW
0h
Real-time clock calibration frequency. Selects frequency output to RTCCLK pin
for calibration measurement. The corresponding port must be configured for the
peripheral module function. The RTCCLK is not available in counter mode and
remains low, and the RTCCALF bits are don't care.
00b = No frequency output to RTCCLK pin
01b = 512 Hz
10b = 256 Hz
11b = 1 Hz
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16.3.5 RTCNT1 Register
Real-Time Clock Counter 1 Register – Counter Mode
Figure 16-6. RTCNT1 Register
7
6
5
4
rw
rw
rw
rw
3
2
1
0
rw
rw
rw
rw
RTCNT1
Table 16-6. RTCNT1 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT1
RW
undefined
The RTCNT1 register is the count of RTCNT1
16.3.6 RTCNT2 Register
Real-Time Clock Counter 2 Register – Counter Mode
Figure 16-7. RTCNT2 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCNT2
rw
rw
rw
rw
Table 16-7. RTCNT2 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT2
RW
undefined
The RTCNT2 register is the count of RTCNT2
16.3.7 RTCNT3 Register
Real-Time Clock Counter 3 Register – Counter Mode
Figure 16-8. RTCNT3 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCNT3
rw
rw
rw
rw
Table 16-8. RTCNT3 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT3
RW
undefined
The RTCNT3 register is the count of RTCNT3
16.3.8 RTCNT4 Register
Real-Time Clock Counter 4 Register – Counter Mode
Figure 16-9. RTCNT4 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RTCNT4
rw
rw
rw
rw
Table 16-9. RTCNT4 Register Description
Bit
Field
Type
Reset
Description
7-0
RTCNT4
RW
undefined
The RTCNT4 register is the count of RTCNT4.
462
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16.3.9 RTCSEC Register – Hexadecimal Format
Real-Time Clock Seconds Register – Hexadecimal Format
Figure 16-10. RTCSEC Register
7
6
5
4
3
r-0
rw
rw
rw
0
r-0
2
1
0
rw
rw
rw
1
0
Seconds
Table 16-10. RTCSEC Register Description
Bit
Field
Type
Reset
Description
7-6
0
R
0h
Always reads as 0.
5-0
Seconds
RW
undefined
Seconds (0 to 59)
16.3.10 RTCSEC Register – BCD Format
Real-Time Clock Seconds Register – BCD Format
Figure 16-11. RTCSEC Register
7
6
0
5
4
3
Seconds – high digit
r-0
rw
rw
2
Seconds – low digit
rw
rw
rw
rw
rw
Table 16-11. RTCSEC Register Description
Bit
Field
Type
Reset
Description
7
0
R
0h
Always reads as 0.
6-4
Seconds – high digit
RW
undefined
Seconds – high digit (0 to 5)
3-0
Seconds – low digit
RW
undefined
Seconds – low digit (0 to 9)
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16.3.11 RTCMIN Register – Hexadecimal Format
Real-Time Clock Minutes Register – Hexadecimal Format
Figure 16-12. RTCMIN Register
7
6
5
4
3
r-0
rw
rw
rw
0
r-0
2
1
0
rw
rw
rw
1
0
Minutes
Table 16-12. RTCMIN Register Description
Bit
Field
Type
Reset
Description
7-6
0
R
0h
Always reads as 0.
5-0
Minutes
RW
undefined
Minutes (0 to 59)
16.3.12 RTCMIN Register – BCD Format
Real-Time Clock Minutes Register – BCD Format
Figure 16-13. RTCMIN Register
7
6
0
5
4
3
2
Minutes – high digit
r-0
rw
rw
Minutes – low digit
rw
rw
rw
rw
rw
Table 16-13. RTCMIN Register Description
Bit
Field
Type
Reset
Description
7
0
R
0h
Always reads as 0.
6-4
Minutes – high digit
RW
undefined
Minutes – high digit (0 to 5)
3-0
Minutes – low digit
RW
undefined
Minutes – low digit (0 to 9)
464
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16.3.13 RTCHOUR Register – Hexadecimal Format
Real-Time Clock Hours Register – Hexadecimal Format
Figure 16-14. RTCHOUR Register
7
6
r-0
r-0
5
4
3
r-0
rw
rw
0
2
1
0
rw
rw
1
0
Hours
rw
Table 16-14. RTCHOUR Register Description
Bit
Field
Type
Reset
Description
7-5
0
R
0h
Always reads as 0.
4-0
Hours
RW
undefined
Hours (0 to 23)
16.3.14 RTCHOUR Register – BCD Format
Real-Time Clock Hours Register – BCD Format
Figure 16-15. RTCHOUR Register
7
6
5
0
r-0
4
3
Hours – high digit
r-0
rw
rw
2
Hours – low digit
rw
rw
rw
rw
Table 16-15. RTCHOUR Register Description
Bit
Field
Type
Reset
Description
7-6
0
R
0h
Always reads as 0.
5-4
Hours – high digit
RW
undefined
Hours – high digit (0 to 2)
3-0
Hours – low digit
RW
undefined
Hours – low digit (0 to 9)
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16.3.15 RTCDOW Register – Calendar Mode
Real-Time Clock Day of Week Register – Calendar Mode
Figure 16-16. RTCDOW Register
7
6
5
r-0
r-0
r-0
4
3
2
r-0
r-0
rw
0
1
0
Day of week
rw
rw
1
0
rw
rw
1
0
Table 16-16. RTCDOW Register Description
Bit
Field
Type
Reset
Description
7-3
0
R
0h
Always reads as 0.
2-0
Day of week
RW
undefined
Day of week (0 to 6)
16.3.16 RTCDAY Register – Hexadecimal Format
Real-Time Clock Day of Month Register – Hexadecimal Format
Figure 16-17. RTCDAY Register
7
6
5
4
3
0
r-0
2
Day of month
r-0
r-0
rw
rw
rw
Table 16-17. RTCDAY Register Description
Bit
Field
Type
Reset
Description
7-5
0
R
0h
Always reads as 0.
4-0
Day of month
RW
undefined
Day of month (1 to 28, 29, 30, 31)
16.3.17 RTCDAY Register – BCD Format
Real-Time Clock Day of Month Register – BCD Format
Figure 16-18. RTCDAY Register
7
6
5
0
r-0
4
3
Day of month – high digit
r-0
rw
rw
2
Day of month – low digit
rw
rw
rw
rw
Table 16-18. RTCDAY Register Description
Bit
Field
Type
Reset
7-6
0
R
0h
5-4
Day of month – high
digit
RW
undefined
Day of month – high digit (0 to 3)
3-0
Day of month – low
digit
RW
undefined
Day of month – low digit (0 to 9)
466
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Description
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16.3.18 RTCMON Register – Hexadecimal Format
Real-Time Clock Month Register – Hexadecimal Format
Figure 16-19. RTCMON Register
7
6
r-0
r-0
5
4
3
2
r-0
r-0
rw
rw
0
1
0
rw
rw
1
0
Month
Table 16-19. RTCMON Register Description
Bit
Field
Type
Reset
Description
7-4
0
R
0h
Always reads as 0.
3-0
Month
RW
undefined
Month (1 to 12)
16.3.19 RTCMON Register – BCD Format
Real-Time Clock Month Register – BCD Format
Figure 16-20. RTCMON Register
7
6
5
4
0
r-0
3
Month – high
digit
r-0
r-0
rw
2
Month – low digit
rw
rw
rw
rw
Table 16-20. RTCMON Register Description
Bit
Field
Type
Reset
Description
7-5
0
R
0h
Always reads as 0.
4
Month – high digit
RW
undefined
Month – high digit (0 or 1)
3-0
Month – low digit
RW
undefined
Month – low digit (0 to 9)
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16.3.20 RTCYEAR Register – Calendar Mode With Hexadecimal Format
Real-Time Clock Year Register – Calendar Mode With Hexadecimal Format
Figure 16-21. RTCYEAR Register
15
14
13
12
11
r-0
r-0
r-0
r-0
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
9
8
0
10
9
8
Year – high byte of 0 to 4095
Year – low byte of 0 to 4095
rw
rw
rw
rw
rw
Table 16-21. RTCYEAR Register Description
Bit
Field
Type
Reset
Description
15-12
0
R
0h
Always reads as 0.
11-0
Year
RW
undefined
Year (0 to 4095)
16.3.21 RTCYEAR Register – Calendar Mode With BCD Format
Real-Time Clock Year Register – Calendar Mode With BCD Format
Figure 16-22. RTCYEAR Register
15
14
0
13
12
11
10
Century – high digit
r-0
rw
7
6
Century – low digit
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
Decade
rw
rw
Year – lowest digit
rw
rw
rw
rw
rw
rw
Table 16-22. RTCYEAR Register Description
Bit
Field
Type
Reset
Description
15
0
R
0h
Always reads as 0.
14-12
Century – low digit
RW
undefined
Century – high digit (0 to 4)
11-8
Century_Low
RW
undefined
Century – low digit (0 to 9)
7-4
Decade
RW
undefined
Decade (0 to 9)
3-0
Year – lowest digit
RW
undefined
Year – lowest digit (0 to 9)
468
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16.3.22 RTCAMIN Register – Hexadecimal Format
Real-Time Clock Minutes Alarm Register – Hexadecimal Format
Figure 16-23. RTCAMIN Register
7
6
AE
0
rw
r-0
5
4
3
rw
rw
rw
2
1
0
rw
rw
rw
1
0
Minutes
Table 16-23. RTCAMIN Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
AE
6
0
R
0h
Always reads as 0.
5-0
Minutes
RW
undefined
Minutes (0 to 59)
16.3.23 RTCAMIN Register – BCD Format
Real-Time Clock Minutes Alarm Register – BCD Format
Figure 16-24. RTCAMIN Register
7
6
AE
5
4
3
Minutes – high digit
rw
rw
rw
2
Minutes – low digit
rw
rw
rw
rw
rw
Table 16-24. RTCAMIN Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
0h
AE
6-4
Minutes – high digit
RW
undefined
Minutes – high digit (0 to 5)
3-0
Minutes – low digit
RW
undefined
Minutes – low digit (0 to 9)
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16.3.24 RTCAHOUR Register – Hexadecimal Format
Real-Time Clock Hours Alarm Register – Hexadecimal Format
Figure 16-25. RTCAHOUR Register
7
6
AE
5
4
3
r-0
rw
rw
0
rw
r-0
2
1
0
rw
rw
1
0
Hours
rw
Table 16-25. RTCAHOUR Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
AE
6-5
0
R
0h
Always reads as 0.
4-0
Hours
RW
undefined
Hours (0 to 23)
16.3.25 RTCAHOUR Register – BCD Format
Real-Time Clock Hours Alarm Register – BCD Format
Figure 16-26. RTCAHOUR Register
7
6
AE
0
rw
r-0
5
4
3
2
Hours – high digit
rw
rw
Hours – low digit
rw
rw
rw
rw
Table 16-26. RTCAHOUR Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
AE
6
0
R
0h
Always reads as 0.
5-4
Hours – high digit
RW
undefined
Hours – high digit (0 to 2)
3-0
Hours – low digit
RW
undefined
Hours – low digit (0 to 9)
470
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16.3.26 RTCADOW Register
Real-Time Clock Day of Week Alarm Register – Calendar Mode
Figure 16-27. RTCADOW Register
7
6
5
r-0
r-0
AE
4
3
2
r-0
r-0
rw
1
0
rw
0
Day of week
rw
rw
1
0
rw
rw
1
0
Table 16-27. RTCADOW Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
AE
6-3
0
R
0h
Always reads as 0.
2-0
Day of week
RW
undefined
Day of week (0 to 6)
16.3.27 RTCADAY Register – Hexadecimal Format
Real-Time Clock Day of Month Alarm Register – Hexadecimal Format
Figure 16-28. RTCADAY Register
7
6
AE
5
4
3
0
rw
r-0
2
Day of month
r-0
rw
rw
rw
Table 16-28. RTCADAY Register Description
Bit
Field
Type
Reset
Description
7
AE
RW
undefined
AE
6-5
0
R
0h
Always reads as 0.
4-0
Day of month
RW
undefined
Day of month (1 to 28, 29, 30, 31)
16.3.28 RTCADAY Register – BCD Format
Real-Time Clock Day of Month Alarm Register – BCD Format
Figure 16-29. RTCADAY Register
7
6
AE
0
rw
r-0
5
4
3
Day of month – high digit
rw
rw
2
Day of month – low digit
rw
rw
rw
rw
Table 16-29. RTCADAY Register Description
Bit
Field
Type
Reset
7
AE
RW
undefined
Description
6
0
R
0h
5-4
Day of month – high
digit
RW
undefined
Day of month – high digit (0 to 3)
3-0
Day of month – low
digit
RW
undefined
Day of month – low digit (0 to 9)
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16.3.29 RTCPS0CTL Register
Real-Time Clock Prescale Timer 0 Control Register
Figure 16-30. RTCPS0CTL Register
15
14
13
12
Reserved
r0
RT0PSDIV
r0
rw-(0)
rw-(0)
6
5
4
7
11
r0
(1)
9
rw-(0)
r0
3
2
r0
r0
rw-(0)
rw-(0)
rw-(0)
8
RT0PSHOLD (1)
Reserved
RT0IP (1)
Reserved
(1)
10
(1)
r0
rw-(1)
1
0
RT0PSIE
RT0PSIFG
rw-0
rw-(0)
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required.
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required.
Table 16-30. RTCPS0CTL Register Description
Bit
Field
Type
Reset
Description
15-14
Reserved
R
0h
Reserved. Always reads as 0.
13-11
RT0PSDIV
RW
0h
Prescale timer 0 clock divide. These bits control the divide ratio of the RT0PS
counter. In real-time clock calendar mode, these bits are don't care for RT0PS
and RT1PS. RT0PS clock output is automatically set to /256. RT1PS clock
output is automatically set to /128.
000b = Divide by 2
001b = Divide by 4
010b = Divide by 8
011b = Divide by 16
100b = Divide by 32
101b = Divide by 64
110b = Divide by 128
111b = Divide by 256
10-9
Reserved
R
0h
Reserved. Always reads as 0.
8
RT0PSHOLD
RW
1h
Prescale timer 0 hold. In real-time clock calendar mode, this bit is don't care.
RT0PS is stopped via the RTCHOLD bit.
0b = RT0PS is operational.
1b = RT0PS is held.
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-2
RT0IP
RW
0h
Prescale timer 0 interrupt interval
000b = Divide by 2
001b = Divide by 4
010b = Divide by 8
011b = Divide by 16
100b = Divide by 32
101b = Divide by 64
110b = Divide by 128
111b = Divide by 256
1
RT0PSIE
RW
0h
Prescale timer 0 interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
0
RT0PSIFG
RW
0h
Prescale timer 0 interrupt flag
0b = No time event occurred.
1b = Time event occurred.
472
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16.3.30 RTCPS1CTL Register
Real-Time Clock Prescale Timer 1 Control Register
Figure 16-31. RTCPS1CTL Register
15
14
RT1SSELx
13
12
(1)
rw-(0)
RT1PSDIVx
rw-(0)
rw-(0)
rw-(0)
6
5
4
7
11
r0
(1)
9
rw-(0)
r0
3
2
r0
r0
rw-(0)
rw-(0)
8
RT1PSHOLD (1)
Reserved
r0
RT1IPx (1)
Reserved
(1)
10
(1)
rw-(0)
rw-(1)
1
0
RT1PSIE
RT1PSIFG
rw-0
rw-(0)
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required.
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore,
reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required.
Table 16-31. RTCPS1CTL Register Description
Bit
Field
Type
Reset
Description
15-14
RT1SSELx
RW
0h
Prescale timer 1 clock source select. Selects clock input source to the RT1PS
counter. In real-time clock calendar mode, these bits are do not care. RT1PS
clock input is automatically set to the output of RT0PS.
00b = 32-kHz crystal oscillator clock
01b = 32-kHz crystal oscillator clock
10b = Output from RT0PS
11b = Output from RT0PS
13-11
RT1PSDIVx
RW
0h
Prescale timer 1 clock divide. These bits control the divide ratio of the RT0PS
counter. In real-time clock calendar mode, these bits are don't care for RT0PS
and RT1PS. RT0PS clock output is automatically set to /256. RT1PS clock
output is automatically set to /128.
000b = Divide by 2
001b = Divide by 4
010b = Divide by 8
011b = Divide by 16
100b = Divide by 32
101b = Divide by 64
110b = Divide by 128
111b = Divide by 256
10-9
Reserved
R
0h
Reserved. Always reads as 0.
8
RT1PSHOLD
RW
1h
Prescale timer 1 hold. In real-time clock calendar mode, this bit is don't care.
RT1PS is stopped via the RTCHOLD bit.
0b = RT1PS is operational.
1b = RT1PS is held.
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-2
RT1IPx
RW
0h
Prescale timer 1 interrupt interval
000b = Divide by 2
001b = Divide by 4
010b = Divide by 8
011b = Divide by 16
100b = Divide by 32
101b = Divide by 64
110b = Divide by 128
111b = Divide by 256
1
RT1PSIE
RW
0h
Prescale timer 1 interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled (LPMx.5 wake-up enabled.)
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Table 16-31. RTCPS1CTL Register Description (continued)
Bit
Field
Type
Reset
Description
0
RT1PSIFG
RW
0h
Prescale timer 1 interrupt flag. This interrupt can be used as LPMx.5 wake-up
event.
0b = No time event occurred.
1b = Time event occurred.
16.3.31 RTCPS0 Register
Real-Time Clock Prescale Timer 0 Counter Register
Figure 16-32. RTCPS0 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RT0PS
rw
rw
rw
rw
Table 16-32. RTCPS0 Register Description
Bit
Field
Type
Reset
Description
7-0
RT0PS
RW
undefined
Prescale timer 0 counter value
16.3.32 RTCPS1 Register
Real-Time Clock Prescale Timer 1 Counter Register
Figure 16-33. RTCPS1 Register
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RT1PS
rw
rw
rw
rw
Table 16-33. RTCPS1 Register Description
Bit
Field
Type
Reset
Description
7-0
RT1PS
RW
undefined
Prescale timer 1 counter value
474
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16.3.33 RTCIV Register
Real-Time Clock Interrupt Vector Register
Figure 16-34. RTCIV Register
15
14
13
12
r0
r0
r0
r0
7
6
5
4
11
10
9
8
r0
r0
r0
r0
3
2
1
0
r-(0)
r-(0)
r-(0)
r0
RTCIVx
RTCIVx
r0
r0
r0
r0
Table 16-34. RTCIV Register Description
Bit
Field
Type
Reset
Description
15-0
RTCIVx
R
0h
Real-time clock interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG; Interrupt
Priority: Highest
04h = Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG
06h = Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG
08h = Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG
0Ah = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG
0Ch = Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG
0Eh = Reserved; Interrupt Priority: Lowest
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16.3.34 BIN2BCD Register
Binary-to-BCD Conversion Register
Figure 16-35. BIN2BCD Register
15
14
13
12
rw-0
rw-0
rw-0
rw-0
7
6
5
4
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
BIN2BCDx
BIN2BCDx
rw-0
rw-0
rw-0
rw-0
Table 16-35. BIN2BCD Register Description
Bit
Field
Type
Reset
Description
15-0
BIN2BCDx
RW
0h
Read: 16-bit BCD conversion of previously written 12-bit binary number
Write: 12-bit binary number to be converted
16.3.35 BCD2BIN Register
BCD-to-Binary Conversion Register
Figure 16-36. BCD2BIN Register
15
14
13
12
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
BCD2BINx
rw-0
rw-0
rw-0
rw-0
7
6
5
4
BCD2BINx
rw-0
rw-0
rw-0
rw-0
Table 16-36. BCD2BIN Register Description
Bit
Field
Type
Reset
Description
15-0
BCD2BINx
RW
0h
Read: 12-bit binary conversion of previously written 16-bit BCD number
Write: 16-bit BCD number to be converted
476
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Chapter 17
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32-Bit Hardware Multiplier (MPY32)
This chapter describes the 32-bit hardware multiplier (MPY32). The MPY32 module is implemented in all
devices.
Topic
17.1
17.2
17.3
...........................................................................................................................
Page
32-Bit Hardware Multiplier (MPY32) Introduction ................................................. 478
MPY32 Operation ............................................................................................. 480
MPY32 Registers ............................................................................................. 492
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17.1 32-Bit Hardware Multiplier (MPY32) Introduction
The MPY32 is a peripheral and is not part of the CPU. This means its activities do not interfere with the
CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU
instructions.
The MPY32 supports:
• Unsigned multiply
• Signed multiply
• Unsigned multiply accumulate
• Signed multiply accumulate
• 8-bit, 16-bit, 24-bit, and 32-bit operands
• Saturation
• Fractional numbers
• 8-bit and 16-bit operation compatible with 16-bit hardware multiplier
• 8-bit and 24-bit multiplications without requiring a "sign extend" instruction
The MPY32 block diagram is shown in Figure 17-1.
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Accessible
Register
MPY
MPYS
MAC
MACS
MPY32H
MPY32L
MPYS32H
MPYS32L
MAC32H
MAC32L
MACS32H
MACS32L
31
16
OP1 (high word)
15
OP2
OP2H
0
OP1 (low word)
31
OP2L
16
OP2 (high word)
16-bit Multiplexer
15
0
OP2 (low word)
16-bit Multiplexer
16×16 Multiplier
OP1_32
OP2_32
MPYMx
MPYSAT
MPYFRAC
MPYC
2
Control
Logic
32-bit Adder
32-bit Demultiplexer
SUMEXT
RES3
RES2
RES1/RESHI
RES0/RESLO
32-bit Multiplexer
Figure 17-1. MPY32 Block Diagram
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17.2 MPY32 Operation
The MPY32 supports 8-bit, 16-bit, 24-bit, and 32-bit operands with unsigned multiply, signed multiply,
unsigned multiply-accumulate, and signed multiply-accumulate operations. The size of the operands are
defined by the address the operand is written to and if it is written as word or byte. The type of operation is
selected by the address the first operand is written to.
The hardware multiplier has two 32-bit operand registers – operand one (OP1) and operand two (OP2),
and a 64-bit result register accessible via registers RES0 to RES3. For compatibility with the 16×16
hardware multiplier, the result of a 8-bit or 16-bit operation is accessible via RESLO, RESHI, and
SUMEXT, as well. RESLO stores the low word of the 16×16-bit result, RESHI stores the high word of the
result, and SUMEXT stores information about the result.
The result of a 8-bit or 16-bit operation is ready in three MCLK cycles and can be read with the next
instruction after writing to OP2, except when using an indirect addressing mode to access the result.
When using indirect addressing for the result, a NOP is required before the result is ready.
The result of a 24-bit or 32-bit operation can be read with successive instructions after writing OP2 or
OP2H starting with RES0, except when using an indirect addressing mode to access the result. When
using indirect addressing for the result, a NOP is required before the result is ready.
Table 17-1 summarizes when each word of the 64-bit result is available for the various combinations of
operand sizes. With a 32-bit-wide second operand, OP2L and OP2H must be written. Depending on when
the two 16-bit parts are written, the result availability may vary; thus, the table shows two entries, one for
OP2L written and one for OP2H written. The worst case defines the actual result availability.
Table 17-1. Result Availability (MPYFRAC = 0, MPYSAT = 0)
Result Ready in MCLK Cycles
Operation
(OP1 × OP2)
RES0
RES1
RES2
RES3
MPYC Bit
8/16 × 8/16
3
3
4
4
3
OP2 written
24/32 × 8/16
3
5
6
7
7
OP2 written
8/16 × 24/32
24/32 × 24/32
480
32-Bit Hardware Multiplier (MPY32)
After
3
5
6
7
7
OP2L written
N/A
3
4
4
4
OP2H written
3
8
10
11
11
OP2L written
N/A
3
5
6
6
OP2H written
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17.2.1 Operand Registers
Operand one (OP1) has 12 registers (see Table 17-2) used to load data into the multiplier and also select
the multiply mode. Writing the low word of the first operand to a given address selects the type of multiply
operation to be performed, but does not start any operation. When writing a second word to a high-word
register with suffix 32H, the multiplier assumes a 32-bit-wide OP1, otherwise, 16 bits are assumed. The
last address written prior to writing OP2 defines the width of the first operand. For example, if MPY32L is
written first followed by MPY32H, all 32 bits are used and the data width of OP1 is set to 32 bits. If
MPY32H is written first followed by MPY32L, the multiplication ignores MPY32H and assumes a 16-bitwide OP1 using the data written into MPY32L.
Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for
successive operations. It is not necessary to rewrite the OP1 value to perform the operations.
Table 17-2. OP1 Registers
OP1 Register
Operation
MPY
Unsigned multiply – operand bits 0 up to 15
MPYS
Signed multiply – operand bits 0 up to 15
MAC
Unsigned multiply accumulate –operand bits 0 up to 15
MACS
Signed multiply accumulate – operand bits 0 up to 15
MPY32L
Unsigned multiply – operand bits 0 up to 15
MPY32H
Unsigned multiply – operand bits 16 up to 31
MPYS32L
Signed multiply – operand bits 0 up to 15
MPYS32H
Signed multiply – operand bits 16 up to 31
MAC32L
Unsigned multiply accumulate – operand bits 0 up to 15
MAC32H
Unsigned multiply accumulate – operand bits 16 up to 31
MACS32L
Signed multiply accumulate – operand bits 0 up to 15
MACS32H
Signed multiply accumulate – operand bits 16 up to 31
Writing the second operand to the OP2 initiates the multiply operation. Writing OP2 starts the selected
operation with a 16-bit-wide second operand together with the values stored in OP1. Writing OP2L starts
the selected operation with a 32-bit-wide second operand and the multiplier expects a the high word to be
written to OP2H. Writing to OP2H without a preceding write to OP2L is ignored.
Table 17-3. OP2 Registers
OP2 Register
Operation
OP2
Start multiplication with 16-bit-wide OP2 – operand bits 0 up to 15
OP2L
Start multiplication with 32-bit-wide OP2 – operand bits 0 up to 15
OP2H
Continue multiplication with 32-bit-wide OP2 – operand bits 16 up to 31
For 8-bit or 24-bit operands, the operand registers can be accessed with byte instructions. Accessing the
multiplier with a byte instruction during a signed operation automatically causes a sign extension of the
byte within the multiplier module. For 24-bit operands, only the high word should be written as byte. If the
24-bit operands are sign-extended as defined by the register, that is used to write the low word to,
because this register defines if the operation is unsigned or signed.
The high-word of a 32-bit operand remains unchanged when changing the size of the operand to 16 bit,
either by modifying the operand size bits or by writing to the respective operand register. During the
execution of the 16-bit operation, the content of the high-word is ignored.
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Changing of first or second operand during multiplication
By default, changing OP1 or OP2 while the selected multiply operation is being calculated
renders any results invalid that are not ready at the time the new operands are changed.
Writing OP2 or OP2L aborts any ongoing calculation and starts a new operation. Results that
are not ready at that time are also invalid for following MAC or MACS operations.
To avoid this behavior, the MPYDLYWRTEN bit can be set to 1. Then, all writes to any
MPY32 registers are delayed with MPYDLY32 = 0 until the 64-bit result is ready or with
MPYDLY32 = 1 until the 32-bit result is ready. For MAC and MACS operations, the complete
64-bit result should always be ready.
See Table 17-1 for how many CPU cycles are needed until a certain result register is ready
and valid for each of the different modes.
17.2.2 Result Registers
The multiplication result is always 64 bits wide. It is accessible via registers RES0 to RES3. Used with a
signed operation, MPYS or MACS, the results are appropriately sign extended. If the result registers are
loaded with initial values before a MACS operation, the user software must take care that the written value
is properly sign extended to 64 bits.
NOTE:
Changing of result registers during multiplication
The result registers must not be modified by the user software after writing the second
operand into OP2 or OP2L until the initiated operation is completed.
In addition to RES0 to RES3, for compatibility with the 16×16 hardware multiplier, the 32-bit result of a 8bit or 16-bit operation is accessible via RESLO, RESHI, and SUMEXT. In this case, the result low register
RESLO holds the lower 16 bits of the calculation result and the result high register RESHI holds the upper
16 bits. RES0 and RES1 are identical to RESLO and RESHI, respectively, in usage and access of
calculated results.
The sum extension register SUMEXT contents depend on the multiply operation and are listed in
Table 17-4. If all operands are 16 bits wide or less, the 32-bit result is used to determine sign and carry. If
one of the operands is larger than 16 bits, the 64-bit result is used.
The MPYC bit reflects the multiplier's carry as listed in Table 17-4 and, thus, can be used as 33rd or 65th
bit of the result, if fractional or saturation mode is not selected. With MAC or MACS operations, the MPYC
bit reflects the carry of the 32-bit or 64-bit accumulation and is not taken into account for successive MAC
and MACS operations as the 33rd or 65th bit.
Table 17-4. SUMEXT and MPYC Contents
Mode
SUMEXT
MPYC
MPY
SUMEXT is always 0000h.
MPYC is always 0.
MPYS
SUMEXT contains the extended sign of the result.
MPYC contains the sign of the result.
00000h
Result was positive or zero
0
Result was positive or zero
0FFFFh
Result was negative
1
Result was negative
MAC
MACS
SUMEXT contains the carry of the result.
MPYC contains the carry of the result.
0000h
No carry for result
0
No carry for result
0001h
Result has a carry
1
Result has a carry
SUMEXT contains the extended sign of the result.
MPYC contains the carry of the result.
00000h
Result was positive or zero
0
No carry for result
0FFFFh
Result was negative
1
Result has a carry
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17.2.2.1 MACS Underflow and Overflow
The multiplier does not automatically detect underflow or overflow in MACS mode. For example, working
with 16-bit input data and 32-bit results (that is, using only RESLO and RESHI), the available range for
positive numbers is 0 to 07FFF FFFFh and for negative numbers is 0FFFF FFFFh to 08000 0000h. An
underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive
number. An overflow occurs when the sum of two positive numbers yields a result that is in the range for a
negative number.
The SUMEXT register contains the sign of the result in both cases described above, 0FFFFh for a 32-bit
overflow and 0000h for a 32-bit underflow. The MPYC bit in MPY32CTL0 can be used to detect the
overflow condition. If the carry is different from the sign reflected by the SUMEXT register, an overflow or
underflow occurred. User software must handle these conditions appropriately.
17.2.3 Software Examples
Examples for all multiplier modes follow. All 8×8 modes use the absolute address for the registers,
because the assembler does not allow .B access to word registers when using the labels from the
standard definitions file.
There is no sign extension necessary in software. Accessing the multiplier with a byte instruction during a
signed operation automatically causes a sign extension of the byte within the multiplier module.
; 32x32 Unsigned Multiply
MOV
#01234h,&MPY32L
MOV
#01234h,&MPY32H
MOV
#05678h,&OP2L
MOV
#05678h,&OP2H
;
...
;
;
;
;
;
; 16x16 Unsigned Multiply
MOV
#01234h,&MPY
MOV
#05678h,&OP2
;
...
; Load 1st operand
; Load 2nd operand
; Process results
Load low word of
Load high word of
Load low word of
Load high word of
Process results
1st
1st
2nd
2nd
operand
operand
operand
operand
1st
1st
2nd
2nd
operand
operand
operand
operand
; 8x8 Unsigned Multiply. Absolute addressing.
MOV.B
#012h,&MPY_B
; Load 1st operand
MOV.B
#034h,&OP2_B
; Load 2nd operand
;
...
; Process results
; 32x32 Signed Multiply
MOV
#01234h,&MPYS32L
MOV
#01234h,&MPYS32H
MOV
#05678h,&OP2L
MOV
#05678h,&OP2H
;
...
;
;
;
;
;
; 16x16 Signed Multiply
MOV
#01234h,&MPYS
MOV
#05678h,&OP2
;
...
; Load 1st operand
; Load 2nd operand
; Process results
; 8x8 Signed Multiply. Absolute
MOV.B
#012h,&MPYS_B
;
MOV.B
#034h,&OP2_B
;
;
...
;
Load low word of
Load high word of
Load low word of
Load high word of
Process results
addressing.
Load 1st operand
Load 2nd operand
Process results
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17.2.4 Fractional Numbers
The MPY32 provides support for fixed-point signal processing. In fixed-point signal processing, fractional
number are numbers that have a fixed number of digits after (and sometimes also before) the radix point.
To classify different ranges of binary fixed-point numbers, a Q-format is used. Different Q-formats
represent different locations of the radix point. Figure 17-2 shows the format of a signed Q15 number
using 16 bits. Every bit after the radix point has a resolution of 1/2, and the most significant bit (MSB) is
used as the sign bit. The most negative number is 08000h and the maximum positive number is 07FFFh.
This gives a range from –1.0 to 0.999969482 ≈ 1.0 for the signed Q15 format with 16 bits.
15 bits
S
1
2
1
4
1
8
1
16
...
Fractional part
Radix point
Sign bit
Figure 17-2. Q15 Format Representation
The range can be increased by shifting the radix point to the right as shown in Figure 17-3. The signed
Q14 format with 16 bits gives a range from –2.0 to 1.999938965 ≈ 2.0.
14 bits
S
1
1
2
1
4
1
8
1
16
...
Figure 17-3. Q14 Format Representation
The benefit of using 16-bit signed Q15 or 32-bit signed Q31 numbers with multiplication is that the product
of two number in the range from –1.0 to 1.0 is always in that same range.
17.2.4.1 Fractional Number Mode
Multiplying two fractional numbers using the default multiplication mode with MPYFRAC = 0 and
MPYSAT = 0 gives a result with two sign bits. For example, if two 16-bit Q15 numbers are multiplied, a
32-bit result in Q30 format is obtained. To convert the result into Q15 format manually, the first 15 trailing
bits and the extended sign bit must be removed. However, when the fractional mode of the multiplier is
used, the redundant sign bit is automatically removed, yielding a result in Q31 format for the multiplication
of two 16-bit Q15 numbers. Reading the result register RES1 gives the result as 16-bit Q15 number. The
32-bit Q31 result of a multiplication of two 32-bit Q31 numbers is accessed by reading registers RES2 and
RES3.
The fractional mode is enabled with MPYFRAC = 1 in register MPY32CTL0. The actual content of the
result registers is not modified when MPYFRAC = 1. When the result is accessed using software, the
value is left shifted one bit, resulting in the final Q formatted result. This allows user software to switch
between reading both the shifted (fractional) and the unshifted result. The fractional mode should only be
enabled when required and disabled after use.
In fractional mode, the SUMEXT register contains the sign extended bits 32 and 33 of the shifted result for
16×16-bit operations and bits 64 and 65 for 32×32-bit operations – not only bits 32 or 64, respectively.
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The MPYC bit is not affected by the fractional mode. It always reads the carry of the nonfractional result.
; Example using
; Fractional 16x16 multiplication
BIS
#MPYFRAC,&MPY32CTL0
MOV
&FRACT1,&MPYS
MOV
&FRACT2,&OP2
MOV
&RES1,&PROD
BIC
#MPYFRAC,&MPY32CTL0
;
;
;
;
;
Turn
Load
Load
Save
Back
on fractional mode
1st operand as Q15
2nd operand as Q15
result as Q15
to normal mode
Table 17-5. Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0)
Result Ready in MCLK Cycles
Operation
(OP1 × OP2)
RES0
RES1
RES2
RES3
MPYC Bit
8/16 × 8/16
3
3
4
4
3
24/32 × 8/16
3
5
6
7
7
OP2 written
8/16 × 24/32
3
5
6
7
7
OP2L written
N/A
3
4
4
4
OP2H written
3
8
10
11
11
OP2L written
N/A
3
5
6
6
OP2H written
24/32 × 24/32
After
OP2 written
17.2.4.2 Saturation Mode
The multiplier prevents overflow and underflow of signed operations in saturation mode. The saturation
mode is enabled with MPYSAT = 1 in register MPY32CTL0. If an overflow occurs, the result is set to the
most-positive value available. If an underflow occurs, the result is set to the most-negative value available.
This is useful to reduce mathematical artifacts in control systems on overflow and underflow conditions.
The saturation mode should only be enabled when required and disabled after use.
The actual content of the result registers is not modified when MPYSAT = 1. When the result is accessed
using software, the value is automatically adjusted to provide the most-positive or most-negative result
when an overflow or underflow has occurred. The adjusted result is also used for successive multiply-andaccumulate operations. This allows user software to switch between reading the saturated and the
nonsaturated result.
With 16×16 operations, the saturation mode only applies to the least significant 32 bits; that is, the result
registers RES0 and RES1. Using the saturation mode in MAC or MACS operations that mix 16×16
operations with 32×32, 16×32, or 32×16 operations leads to unpredictable results.
With 32×32, 16×32, and 32×16 operations, the saturated result can only be calculated when RES3 is
ready.
Enabling the saturation mode does not affect the content of the SUMEXT register nor the content of the
MPYC bit.
; Example using
; Fractional 16x16 multiply accumulate with Saturation
; Turn on fractional and saturation mode:
BIS
#MPYSAT+MPYFRAC,&MPY32CTL0
MOV
&A1,&MPYS
; Load A1 for 1st term
MOV
&K1,&OP2
; Load K1 to get A1*K1
MOV
&A2,&MACS
; Load A2 for 2nd term
MOV
&K2,&OP2
; Load K2 to get A2*K2
MOV
&RES1,&PROD
; Save A1*K1+A2*K2 as result
BIC
#MPYSAT+MPYFRAC,&MPY32CTL0
; turn back to normal
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Table 17-6. Result Availability in Saturation Mode (MPYSAT = 1)
Result Ready in MCLK Cycles
Operation
(OP1 × OP2)
RES0
RES1
RES2
RES3
MPYC Bit
8/16 × 8/16
3
3
N/A
N/A
3
24/32 × 8/16
7
7
7
7
7
OP2 written
8/16 × 24/32
7
7
7
7
7
OP2L written
4
4
4
4
4
OP2H written
11
11
11
11
11
OP2L written
6
6
6
6
6
OP2H written
24/32 × 24/32
After
OP2 written
Figure 17-4 shows the flow for 32-bit saturation used for 16×16 bit multiplications and the flow for 64-bit
saturation used in all other cases. Primarily, the saturated results depends on the carry bit MPYC and the
MSB of the result. Secondly, if the fractional mode is enabled, it depends also on the two MSBs of the
unshift result, that is, the result that is read with fractional mode disabled.
32-bit Saturation
MPYC=0 and
unshifted RES1,
bit15=1
64-bit Saturation
Yes
Overflow:
RES3 unchanged
RES2 unchanged
RES1 = 07FFFh
RES0 = 0FFFFh
Yes
Underflow:
RES3 unchanged
RES2 unchanged
RES1 = 08000h
RES0 = 00000h
Yes
MPYC=1 and
unshifted RES3,
bit15=0
No
No
MPYFRAC=1
MPYFRAC=1
Yes
Yes
Yes
Overflow:
RES3 unchanged
RES2 unchanged
RES1 = 07FFFh
RES0 = 0FFFFh
Yes
Unshifted RES3,
bit 15=0 and
bit 14=1
Overflow:
RES3 = 07FFFh
RES2 = 0FFFFh
RES1 = 0FFFFh
RES0 = 0FFFFh
No
No
Unshifted RES1,
bit 15=1 and
bit 14=0
Underflow:
RES3 = 08000h
RES2 = 00000h
RES1 = 00000h
RES0 = 00000h
No
No
Unshifted RES1,
bit 15=0 and
bit 14=1
Overflow:
RES3 = 07FFFh
RES2 = 0FFFFh
RES1 = 0FFFFh
RES0 = 0FFFFh
No
No
MPYC=1 and
unshifted RES1,
bit15=0
Yes
MPYC=0 and
unshifted RES3,
bit15=1
Yes
Underflow:
RES3 unchanged
RES2 unchanged
RES1 = 08000h
RES0 = 00000h
No
32-bit Saturation
completed
Yes
Unshifted RES3,
bit 15=1 and
bit 14=0
Underflow:
RES3 = 08000h
RES2 = 00000h
RES1 = 00000h
RES0 = 00000h
No
64-bit Saturation
completed
Figure 17-4. Saturation Flow Chart
486
32-Bit Hardware Multiplier (MPY32)
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NOTE:
Saturation in fractional mode
In case of multiplying –1.0 × –1.0 in fractional mode, the result of +1.0 is out of range, thus,
the saturated result gives the most positive result.
When using multiply-and-accumulate operations, the accumulated values are saturated as if
MPYFRAC = 0; only during read accesses to the result registers the values are saturated
taking the fractional mode into account. This provides additional dynamic range during the
calculation and only the end result is then saturated if needed.
The following example illustrates a special case showing the saturation function in fractional mode. It also
uses the 8-bit functionality of the MPY32 module.
; Turn on fractional and saturation mode,
; clear all other bits in MPY32CTL0:
MOV
#MPYSAT+MPYFRAC,&MPY32CTL0
;Pre-load result registers to demonstrate overflow
MOV
#0,&RES3
;
MOV
#0,&RES2
;
MOV
#07FFFh,&RES1
;
MOV
#0FA60h,&RES0
;
MOV.B
#050h,&MACS_B
; 8-bit signed MAC operation
MOV.B
#012h,&OP2_B
; Start 16x16 bit operation
MOV
&RES0,R6
; R6 = 0FFFFh
MOV
&RES1,R7
; R7 = 07FFFh
The result is saturated because already the result not converted into a fractional number shows an
overflow. The multiplication of the two positive numbers 00050h and 00012h gives 005A0h. 005A0h added
to 07FFF FA60h results in 8000 059Fh, without MPYC being set. Because the MSB of the unmodified
result RES1 is 1 and MPYC = 0, the result is saturated according Figure 17-4.
NOTE:
Validity of saturated result
The saturated result is valid only if the registers RES0 to RES3, the size of OP1 and OP2,
and MPYC are not modified.
If the saturation mode is used with a preloaded result, user software must ensure that MPYC
in the MPY32CTL0 register is loaded with the sign bit of the written result; otherwise, the
saturation mode erroneously saturates the result.
17.2.5 Putting It All Together
Figure 17-5 shows the complete multiplication flow, depending on the various selectable modes for the
MPY32 module.
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New Multiplication
Started
Yes
No
No
16×16
?
Yes
Yes
No
MAC or MACS
?
MAC or MACS
?
Yes
Yes
Clear Result:
RES1 = 00000h
RES0 = 00000h
MPYSAT=1
?
non-fractional
32-bit Saturation
Perform 16×16
MPY or MPYS
Operation
MPYSAT=1
?
No
No
Perform 16×16
MAC or MACS
Operation
non-fractional
64-bit Saturation
Perform
MAC or MACS
Operation
Perform
MPY or MPYS
Operation
Yes
Yes
MPYFRAC=1
?
MPYFRAC=1
?
No
Shift 64bit result.
Calculate SUMEXTbased on
MPYC and bit15 of
unshifted RES1.
Shift 64bit result.
Calculate SUMEXTbased on
MPYC and bit15 of
unshifted RES3.
Yes
No
Yes
MPYSAT=1
?
No
Clear Result:
RES3 = 00000h
RES2 = 00000h
RES1 = 00000h
RES0 = 00000h
MPYSAT=1
?
32-bit Saturation
64-bit Saturation
No
Multiplication
completed
Figure 17-5. Multiplication Flow Chart
488
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Given the separation in processing of 16-bit operations (32-bit results) and 32-bit operations (64-bit
results) by the module, it is important to understand the implications when using MAC/MACS operations
and mixing 16-bit operands or results with 32-bit operands or results. User software must address these
points during use when mixing these operations. The following code illustrates the issue.
; Mixing 32x24 multiplication with 16x16 MACS operation
MOV
#MPYSAT,&MPY32CTL0
; Saturation mode
MOV
#052C5h,&MPY32L
; Load low word of 1st operand
MOV
#06153h,&MPY32H
; Load high word of 1st operand
MOV
#001ABh,&OP2L
; Load low word of 2nd operand
MOV.B
#023h,&OP2H_B
; Load high word of 2nd operand
;... 5 NOPs required
MOV
&RES0,R6
; R6 = 00E97h
MOV
&RES1,R7
; R7 = 0A6EAh
MOV
&RES2,R8
; R8 = 04F06h
MOV
&RES3,R9
; R9 = 0000Dh
; Note that MPYC = 0!
MOV
#0CCC3h,&MACS
; Signed MAC operation
MOV
#0FFB6h,&OP2
; 16x16 bit operation
MOV
&RESLO,R6
; R6 = 0FFFFh
MOV
&RESHI,R7
; R7 = 07FFFh
The second operation gives a saturated result because the 32-bit value used for the 16×16-bit MACS
operation was already saturated when the operation was started; the carry bit MPYC was 0 from the
previous operation, but the MSB in result register RES1 is set. As one can see in the flow chart, the
content of the result registers are saturated for multiply-and-accumulate operations after starting a new
operation based on the previous results, but depending on the size of the result (32 bit or 64 bit) of the
newly initiated operation.
The saturation before the multiplication can cause issues if the MPYC bit is not properly set as the
following code shows.
;Pre-load result registers to demonstrate overflow
MOV
#0,&RES3
;
MOV
#0,&RES2
;
MOV
#0,&RES1
;
MOV
#0,&RES0
;
; Saturation mode and set MPYC:
MOV
#MPYSAT+MPYC,&MPY32CTL0
MOV.B
#082h,&MACS_B
; 8-bit signed MAC operation
MOV.B
#04Fh,&OP2_B
; Start 16x16 bit operation
MOV
&RES0,R6
; R6 = 00000h
MOV
&RES1,R7
; R7 = 08000h
Even though the result registers were loaded with all zeros, the final result is saturated. This is because
the MPYC bit was set, causing the result used for the multiply-and-accumulate to be saturated to
08000 0000h. Adding a negative number to it would again cause an underflow, thus, the final result is also
saturated to 08000 0000h.
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17.2.6 Indirect Addressing of Result Registers
When using indirect or indirect autoincrement addressing mode to access the result registers and the
multiplier requires three cycles until result availability according to Table 17-1, at least one instruction is
needed between loading the second operand and accessing the result registers:
; Access multiplier 16x16 results with indirect addressing
MOV
#RES0,R5
; RES0 address in R5 for indirect
MOV
&OPER1,&MPY
; Load 1st operand
MOV
&OPER2,&OP2
; Load 2nd operand
NOP
; Need one cycle
MOV
@R5+,&xxx
; Move RES0
MOV
@R5,&xxx
; Move RES1
In case of a 32×16 multiplication, there is also one instruction required between reading the first result
register RES0 and the second result register RES1:
; Access
MOV
MOV
MOV
MOV
NOP
MOV
NOP
MOV
MOV
multiplier 32x16 results with indirect addressing
#RES0,R5
; RES0 address in R5 for indirect
&OPER1L,&MPY32L
; Load low word of 1st operand
&OPER1H,&MPY32H
; Load high word of 1st operand
&OPER2,&OP2
; Load 2nd operand (16 bits)
; N