Dfi DV970 Manual
DV970
COM Express Basic Module
User’s Manual
A47900935
1
Chapter 1 Introduction
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Copyright
FCC and DOC Statement on Class B
This publication contains information that is protected by copyright. No part of it may be reproduced in any form or by any means or used to make any transformation/adaptation without
the prior written permission from the copyright holders.
This equipment has been tested and found to comply with the limits for a Class B digital
device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference
to radio communications. However, there is no guarantee that interference will not occur in a
particular installation. If this equipment does cause harmful interference to radio or television
reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
This publication is provided for informational purposes only. The manufacturer makes no
representations or warranties with respect to the contents or use of this manual and specifically disclaims any express or implied warranties of merchantability or fitness for any particular
purpose. The user will assume the entire risk of the use or the results of the use of this document. Further, the manufacturer reserves the right to revise this publication and make changes
to its contents at any time, without obligation to notify any person or entity of such revisions
or changes.
•
•
•
Changes after the publication’s first release will be based on the product’s revision. The website
will always provide the most updated information.
•
© 2019. All Rights Reserved.
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and the receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver
is connected.
Consult the dealer or an experienced radio TV technician for help.
Trademarks
Notice:
Product names or trademarks appearing in this manual are for identification purpose only and
are the properties of the respective owners.
1. The changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.
2. Shielded interface cables must be used in order to comply with the emission limits.
COM Express Specification Reference
PICMG® COM Express ModuleTM Base Specification.
http://www.picmg.org/
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Chapter 1 Introduction
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Table of Contents
Copyright..........................................................................2
Chapter 3 - Hardware Installation............................11
Trademarks.......................................................................2
Board Layout..............................................................................................................11
Mechanical Diagram...............................................................................................11
COM Express Specification Reference....................2
System Memory........................................................................................................12
Connectors..................................................................................................................13
FCC and DOC Statement on Class B.......................2
CPU Fan Connector................................................................................................................................ 13
COM Express Connectors.................................................................................................................... 14
Warranty ...........................................................................4
COM Express Connectors Signals and Descriptions...................................16
Standby Power LED.................................................................................................28
Static Electricity Precautions......................................4
Cooling Option..........................................................................................................28
Safety Measures..............................................................4
Chapter 4 - BIOS Setup................................................31
About the Package........................................................5
Overview ....................................................................................................................31
Insyde BIOS Setup Utility.......................................................................................32
Optional Items................................................................5
Main............................................................................................................................................................. 32
Advanced ................................................................................................................................................. 32
UEFI Device Manager............................................................................................................................ 37
Security....................................................................................................................................................... 43
Boot............................................................................................................................................................. 44
Exit................................................................................................................................................................ 45
Before Using the System Board................................5
Chapter 1 - Introduction.............................................6
Chapter 5 - Supported Software..............................47
Specifications............................................................................................................... 6
Features.......................................................................................................................... 7
Chapter 2 - Concept......................................................8
COM Express Module Standards.......................................................................... 8
Specification Comparison Table........................................................................... 9
DV970 PCIe Lanes Routing Table.......................................................................10
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Chapter 1 Introduction
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Warranty
Static Electricity Precautions
1. Warranty does not cover damages or failures that arised from misuse of the product, inability to use the product, unauthorized replacement or alteration of components and product specifications.
It is quite easy to inadvertently damage your PC, system board, components or devices even
before installing them in your system unit. Static electrical discharge can damage computer
components without causing any signs of physical damage. You must take extra care in handling them to ensure against electrostatic build-up.
2. The warranty is void if the product has been subjected to physical abuse, improper installation, modification, accidents or unauthorized repair of the product.
1. To prevent electrostatic build-up, leave the system board in its anti-static bag until you are
ready to install it.
3. Unless otherwise instructed in this user’s manual, the user may not, under any circumstances, attempt to perform service, adjustments or repairs on the product, whether in or
out of warranty. It must be returned to the purchase point, factory or authorized service
agency for all such work.
2. Wear an antistatic wrist strap.
3. Do all preparation work on a static-free surface.
4. We will not be liable for any indirect, special, incidental or consequential damages to the
product that has been modified or altered.
4. Hold the device only by its edges. Be careful not to touch any of the components, contacts
or connections.
5. Avoid touching the pins or contacts on all modules and connectors. Hold modules or connectors by their ends.
Important:
Electrostatic discharge (ESD) can damage your processor, disk drive and other components. Perform the upgrade instruction procedures described at an ESD workstation only. If such a station is not available, you can provide some ESD protection by
wearing an antistatic wrist strap and attaching it to a metal part of the system chassis. If a wrist strap is unavailable, establish and maintain contact with the system
chassis throughout any procedures requiring ESD protection.
Safety Measures
To avoid damage to the system:
• Use the correct AC input voltage range.
To reduce the risk of electric shock:
• Unplug the power cord before removing the system chassis cover for installation or servicing. After installation or servicing, cover the system chassis before plugging the power
cord.
4
Chapter 1 Introduction
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About the Package
The package contains the following items. If any of these items are missing or damaged,
please contact your dealer or sales representative for assistance.
•
•
One DV970 board
One CPU Cooler (Height: 23.6mm for SKUs with normal temp. & 47.8mm for SKUs with
wide temp.)
Optional Items
•
•
COM333-I carrier board kit
Heat spreader (Height: 11mm)
The board and accessories in the package may not come similar to the information listed
above. This may differ in accordance with the sales region or models in which it was sold. For
more information about the standard package in your region, please contact your dealer or
sales representative.
Before Using the System Board
Before using the system board, prepare basic system components.
If you are installing the system board in a new system, you will need at least the following
internal components.
•
•
Memory module
Storage devices such as hard disk drive, etc.
You will also need external system peripherals you intend to use which will normally include at
least a keyboard, a mouse and a video display monitor.
5
Chapter 1 Introduction
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Chapter 1
Chapter 1 - Introduction
Specifications
SYSTEM
Processor Intel Atom® Processor C3000 Series, BGA1310
Intel Atom® C3958 Processor, 16 Cores, 16M Cache, 2.0GHz, 31W
Intel Atom® C3808 Processor, 12 Cores, 12M Cache, 2.0GHz, 25W
Intel Atom® C3758 Processor, 8 Cores, 16M Cache, 2.2GHz, 25W
Intel Atom® C3708 Processor, 8 Cores, 16M Cache, 1.7GHz, 17W
Memory
Two 260-pin ECC SODIMM up to 32GB
Supports dual channel DDR4 1866/2133/2400MHz
(Max. memory speed depends on CPU SKU)
I/O
BIOS
EXPANSION Interface
Insyde SPI 128Mbit
PCIe
PCIe
PCIe
PCIe
x2
x2
x1
x8
SATA
2 x SATA 3.0 (up to 6Gb/s)
DIO
1 x 8-bit DIO (4 in, 4 out)
Output &
Interval
System reset, programmable via software from 1 to 255
Seconds
SECURITY
TPM
Available upon request
POWER
Type
12V, 5VSB, VCC_RTC (ATX mode)
12V, VCC_RTC (AT mode)
Consumption Boot up: 26.652W
Idle: 24.226W
Max. Load (Intel PTU): 40.206W
S5 mode (WOL disabled): 7.4W/1.75W@5V standby power
(with carrier board/without carrier board)
S5 mode (WOL enabled): 8.55W/2.9W@5V standby power
(with carrier board/without carrier board)
or 2 x PCIe x1 (Gen 3)
(Gen 3) + 1 x PCIe x1 (Gen 2) or
(Lane 8 Gen 3, Lane 12 Gen 2)
or 2 x PCIe x4 or 4 x PCIe x2 or 4 x PCIe x1 (Gen 3)
100G:
B1: 1 x PCIe x8 or 2 x PCIe x4 or 4 x PCIe x2 or 4 x PCIe x1 (Gen 3)
B3: 2 x PCIe x2 or 2 x PCIe x1 (Gen 3)
B4: 2 x PCIe x2 or 2 x PCIe x1 (Gen 3)
ETHERNET
2 x USB 3.0
4 x USB 2.0
WATCHDOG
TIMER
000G/200G/300G:
B1: 2 x
B2: 1 x
2x
B3: 1 x
USB
OS SUPPORT
1 x LPC
1 x I2C
1 x SMBus
2 x UART (TX/RX)
Controller PHY for X557 or CS4227/CS4223 and Controller for Intel® I210AT/
Intel® I210IT
2 x Independent 10GbE Media Access Controller (dependent on SKU)
Supports up to two 10GBASE-KR Interfaces and up to four 10GbE
MAC ports
Supports Intel® X557-AT/AT2/AT4 10GbE PHY
Supports Inphi CS4227 (2 port)/CS4223 (4 port)
(maximum bandwidth is 20Gb when 4 ports of 10G interface active at
the same time)
ENVIRONMENT
Windows Server 2012
Windows Server 2016
Yocto Project v1.8/v2.0
Temperature Intel Atom® C3758 & C3958 (normal temp.): support 0 to
60°C operating temperature
Intel Atom® C3708 & C3808 (wide temp.): support -40 to
85°C operating temperature
Storage Temperature:
-40 to 85°C
Humidity
Operating: 5 to 90% RH
Storage: 5 to 90% RH
MTBF
Intel Atom®C3758 & C3958 (normal temp.):
2,055,292 hrs@25°C; 1,158,756 hrs@45°C; 747,377 hrs
@60°C excluding accessories
Intel Atom® C3708 & C3808 (wide temp.):
2,142,843 hrs@25°C; 1,186,002 hrs@45°C; 758,590 hrs
@60°C excluding accessories
1 x Intel® I210AT (10/100/1000Mbps) (normal temp.) or
1 x Intel® I210IT (10/100/1000Mbps) (wide temp.)
Calculation Model: Telcordia Issue 2, Method Case 3
Environment: GB, GC – Ground Benign, Controlled
Mechanical
Dimensions
COM Express® Basic
95mm (3.74") x 125mm (4.9")
Compliance
PICMG COM Express® R3.0, Type 7
6
Chapter 1 Introduction
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Chapter 1
Features
• Watchdog Timer
The Watchdog Timer function allows your application to regularly “clear” the system at the set
time interval. If the system hangs or fails to function, it will reset at the set time interval so
that your system will continue to operate.
• DDR4
DDR4 delivers increased system bandwidth and improves performance. The advantages of
DDR4 provide an extended battery life and improve the performance at a lower power than
DDR3/DDR2.
• Serial ATA
Serial ATA is a storage interface that is compliant with SATA 1.0a specification. With speed of
up to 6Gb/s (SATA 3.0), it improves hard drive performance faster than the standard parallel ATA whose data transfer rate is 100MB/s. However, the bandwidth of the SATA 3.0 will be
limited by carrier board design.
• 10 Gigabit and Gigabit Ethernet
This system, based on the COM Express Type 7 revision 3.0 standard, supports up to two
10GbE KR interface lanes as well as NC-SI sideband signals. In addition, the Intel Atom® C3000
processor series comes with integrated Intel® Ethernet that supports up to four 10GbE adapters.
• USB
The system board supports the USB 3.0. It is capable of running at a maximum transmission
speed of up to 5 Gbit/s (625 MB/s) and is faster than USB 2.0 (480 Mbit/s, or 60 MB/s) and
USB 1.1 (12Mb/s). USB 3.0 reduces the time required for data transmission and is backward
compatible with USB 2.0. It is a marked improvement in device transfer speeds between your
computer and a wide range of simultaneously accessible external Plug and Play peripherals.
7
Chapter 1 Introduction
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Chapter 2
Chapter 2 - Concept
COM Express Module Standards
The figure below shows the dimensions of the different types of COM Express modules.
DV970 is a COM Express Basic module. Its dimension is 95mm x 125mm (4.92” x 3.74”).
Common for all Form Factors
Extended only
Basic only
Compact only
Compact and Basic only
Mini only
106.00
Extended
Compact
91.00
Basic
70.00
51.00
Mini
18.00
6.00
0.00
4.00
151.00
121.00
91.00
80.00
74.20
16.50
4.00
0.00
8
Chapter 2 Concept
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PICMG® COM.0
Chapter 2
COM Express® Module Base Specification
Revision 3.0 March 31,2017
3
3.2
Required and Optional Features
Module Pin-out Types 6-7 & 10 - Required and Optional Features
COM Express Required and Optional features are summarized in the following table. The
features identified as Minimum (Min.) shall be implemented by all Modules. Features
identified up to Maximum (Max) may be additionally implemented by a Module.
Specification Comparison Table
Change Key:
The
table below shows the COM Express standard specifications and the corresponding specifications supported on the DV970 module.
Table 3.2: Module Pin-out - Required and Optional Features A-B Connector
Type 7 Based on Type 6. Modules trades all audio and video interfaces, 2 SATA ports and four USB 2.0 for
additional PCI Express lanes, four 10 Gb Ethernet ports and an NC-SI management interface for the GbE port.
Connector
Feature
COM Express Module Base
Specification Type 7
Min / Max
DFI DV970
Type 7
(000G/200G/300G)
DFI DV970
Type 7
(100G)
4
3
8
NA
4
1
1
NA
NA
NA
NA
NA
NA
2
0
2
NA
4
0
NA
2
1 LPC
1
0
6
2
8
NA
4
0
0
NA
NA
NA
NA
NA
NA
2
0
2
NA
4
0
NA
2
1 LPC
1
0
1
8
1
1
1
1
0
8
1
1
1
1
0
8
1
1
1
1
0/1
1
1
1/1
0/1
1
1
1
1
1
1
2
1
1
4
1
1
1
1
1
2
1
1
4
1
1
1
24
24
Features
System I/O
A-B
A-B , C-D
C-D
C-D
C-D
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
C-D
A-B
A-B
C-D
PCI Express Lanes 0 - 5
PCI Express Lanes 6 - 15
PCI Express Lanes 16 - 31
PCI Express Graphics (PEG)
10G LAN Ports 0 - 3
NC-SI
1Gb LAN Port 0
DDI 0
DDIs 1 - 3
LVDS Channel A
LVDS Channel B
eDP on LVDS CH A pins
VGA Port
Serial Ports 1 - 2
CAN interface on SER1
SATA Ports
HDA Digital Interface
USB 2.0 Ports
USB0 Client
USB7 Client
USB 3.0 Ports
LPC Bus or eSPI
SPI (Devices)
Rapid Shutdown
A-B2
A-B
A-B
A-B
A-B
A-B
A-B
A-B
A-B
SDIO (muxed on GPIO)
General Purpose I/O
SMBus
I2C
Watchdog Timer
Speaker Out
Carrier Board BIOS Flash
Support
Reset Functions
Trusted Platform Module
A-B
A-B
A-B
A-B
A-B
A-B
1
A-B
1
A-B
1
A-B
Thermal Protection
Battery Low Alarm
Suspend/Wake Signals
Power Button Support
Power Good
VCC_5V_SBY Contacts
Sleep Input
Lid Input
Carrier Board Fan Control
A-B , C-D
VCC_12V Contacts
6/6
0 / 10
0 / 16
NA
0/4
0/1
1/1
NA
NA
NA
NA
NA
NA
0/2
0/1
0/2
NA
4/4
0/1
NA
0/4
1/1
1/2
0/1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
1
1
3
1
1
4
1
1
1
C3758
C3708
25
25
17
Number of 64-bit Intel Atom Microarchitecture
Goldmont Cores
16
12
8
8
Processor Base Frequency (GHz)
2.0
2.0
2.2
1.7
Total SoC L2 Cache (MB)
16
12
16
16
Max. Number of Memory Channels Available
Max. DDR4 (1.2V) Memory Data Rate Supported
(MT/s)
Number of High-Speed I/O (HSIO) Lanes Shared
between PCIe, SATA, and USB 3.0
HSIO Lane Numbers (0 through 19) Available
2
2400
2133
20
Lanes 0-19
Max. Number of PCI Express (8.0/5.0/2.5 GT/s)
Lanes
16 via HSIO Lanes
from Lanes 0-15
Max. Number of SATA (6.0/3.0/1.5 Gbps) Lanes
16 via HSIO Lanes
from Lanes 4-19
Max. Number of Sets of USB 3.0 Signals
(SSTX+/SSTX- SSRX+/SSRX-)
4 via HSIO Lanes
from Lanes 16-19
Number of Sets of USB 2.0 Signals
(DATA+/DATA-)
4
LAN Controller 0 (Gb/s)*
10/2.5/1
LAN Controller 1 (Gb/s)*
10/2.5/1
* Each LAN controller must run the same LEK.
Power Management
0
0
0
1
1
4
0
0
0
C3808
31
®
System Management
0
8
1
1
0
1
C3958
Thermal Design Power (TDP) (Watts)
Note: Different SKUs may require different BIOS.
Power
24 / 24
1. Indicates 12V-tolerant features on former VCC_12V signals.
2. Cells in the connected columns spanning rows provide a rough approximation of features
sharing connector pins.
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Chapter 2 Concept
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Chapter 2
DV970 PCIe Lanes Routing Table
This table below summarizes the configuration of High-Speed I/O (HSIO) Lanes shared among
PCIe, SATA, and USB 3.0 for different SKUs of DV970.
PICMG COM.0 R3.0 Type‐7
PCIe Lanes Mapping
Bucket
Lane NO.
Lane 0
Lane 1
Lane 2
Lane 3
B1
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 9
Lane 10
Lane 11
B2
Lane 12
Lane 13
Lane 14
Lane 15
Lane 16
Lane 17
Lane 18
Lane 19
B3
Lane 20
Lane 21
Lane 22
Lane 23
Lane 24
Lane 25
Lane 26
Lane 27
B4
Lane 28
Lane 29
Lane 30
Lane 31
USB3_P0
USB3_P1
USB3
USB3_P2
USB3_P3
SATA3_P0
SATA3
SATA3_P1
DV970
(000G/200G/300G)
Link Width
via HSIO
Lane 0‐1
x2 (default)
x1 (optional)
N.C.
via HSIO
Lanes 4‐5
x1 (optional)
x2 (default)
DV970
(100G)
Link Width
via HSIO
Lane 0‐7
x8
(default)
N.C.
via HSIO
Lanes 2‐3
x4
(optional)
x1 (optional)
x2 (default)
N.C.
via HSIO
x2
(optional)
x2
(optional)
x2
(optional)
x2
(optional)
x4
(optional)
x1 (default for BMC)
x1 (optional)
x1 (optional)
x1 (optional)
x1 (optional)
N.C.
x1 (optional)
N.C.
via HSIO
Lane 8‐15
x8
(default)
x2
(optional)
x2
(optional)
x2
(optional)
x2
(optional)
x4
(optional)
x4
(optional)
N.C.
x1 (optional)
x1 (optional)
x1 (optional)
x1 (optional)
via HSIO
Lane 8‐9
x2 (default)
x1 (optional)
N.C.
via HSIO
Lane 12‐13
x2 (default)
x1 (optional)
N.C.
via HSIO
Lane 10‐11
x2 (default)
x1 (optional)
N.C.
via HSIO
Lane 14‐15
x2 (default)
x1 (optional)
N.C.
via HSIO
via HSIO
USB3_P0
USB3_P1
USB3_P0
USB3_P1
via HSIO
via HSIO
N.C.
via HSIO
via HSIO
SATA3_P0
SATA3_P1
N.C.
SATA3_P0
SATA3_P1
via HSIO
via HSIO
10
Chapter 2 Concept
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Chapter 3
Chapter 3 - Hardware Installation
91.00
121.00
Mechanical Diagram
0.00
4.00
Board Layout
95.00
91.00
CPU fan
DDR4_2 SODIMM
C3000 Series
DDR4_1 SODIMM
Intel Atom
P17C9X2G
304SL
®
Intel Atom
46.63
Processor C3000 Series
1
1
SPI Flash BIOS
Standby
Power LED
80.00
54.77
TPM (optional)
0.00
4.00
Intel
I210AT or
I210IT
121.00
125.00
4.00
0.00
45.35
0.00
C
A
Top View
Lorem ipsum
0.00
6.00
18.00
iTE
IT8528E
D110
D1
COM Express Connector
C110
B110
C1
B1
1
COM Express Connector
A A A
A110
5
A1
Bottom View
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Chapter 3 Hardware Installation
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Chapter 3
Installing a SODIMM Module
Important:
Electrostatic discharge (ESD) can damage your board, processor, disk drives, add-in
boards, and other components. Perform installation procedures at an ESD workstation
only. If such a station is not available, you can provide some ESD protection by wearing an antistatic wrist strap and attaching it to a metal part of the system chassis. If
a wrist strap is unavailable, establish and maintain contact with the system chassis
throughout any procedures requiring ESD protection.
Note:
The system board used in the following illustrations may not resemble the actual one.
These illustrations are for reference only.
System Memory
1. Make sure the PC and all other peripheral devices connected to it has been powered down.
2. Disconnect all power cords and cables.
Important:
When the Standby Power LED is red, it indicates that there is power on the board.
Power off the PC then unplug the power cord prior to installing any devices. Failure to
do so will cause severe damage to the board and components.
3. Locate the SODIMM socket on the system board.
4. Note the key on the socket. The key ensures that the module can be plugged into the
socket in only one direction.
DDR4_1
DDR4_2
Standby
Power LED
12
Chapter 3 Hardware Installation
Chapter 3
5. Grasping the module by its edges, align the module into the socket at an approximately 30
degrees angle. Apply firm even pressure to each end of the module until it slips down into
the socket. The contact fingers on the edge of the module will almost completely disappear
inside the socket.
Connectors
CPU Fan Connector
Sense
+12V
Ground
1
3
6. Push down the module until the clips at each end of the socket lock into position. You will
feel a distinctive “click”, indicating the module is correctly locked into position.
Connect the CPU fan’s cable connector to the CPU fan connector on the board. The cooling fan
will provide adequate airflow throughout the chassis to prevent overheating the CPU and board
components.
Clip
Clip
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Chapter 3 Hardware Installation
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Chapter 3
COM Express Connectors
C
A
The COM Express connectors are used to interface the DV970 COM Express board to a carrier
board. Connect the COM Express connectors (located on the solder side of the board) to the
COM Express connectors on the carrier board.
1
5
A A A
COM Express Connectors
Refer to the following pages for the pin functions of these connectors.
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Chapter 3 Hardware Installation
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Chapter 3
COM Express Connectors-Continued
Row A
Row B
A1 GND (FIXED)
B1 GND (FIXED)
A2 GBE0_MDI3B2 GBE0_ACT#
A3 GBE0_MDI3+
B3 LPC_FRAME#
A4 GBE0_LINK100#
B4 LPC_AD0
A5 GBE0_LINK1000#
B5 LPC_AD1
A6 GBE0_MDI2B6 LPC_AD2
A7 GBE0_MDI2+
B7 LPC_AD3
A8 GBE0_LINK#
B8 LPC_DRQ0#
A9 GBE0_MDI1B9 LPC_DRQ1#
A10 GBE0_MDI1+
B10 LPC_CLK
A11 GND (FIXED)
B11 GND (FIXED)
A12 GBE0_MDI0B12 PWRBTN#
A13 GBE0_MDI0+
B13 SMB_CK
A14 GBE0_CTREF
B14 SMB_DAT
A15 SUS_S3#
B15 SMB_ALERT#
A16 SATA0_TX+
B16 SATA1_TX+
A17 SATA0_TXB17 SATA1_TXA18 SUS_S4#
B18 SUS_STAT#
A19 SATA0_RX+
B19 SATA1_RX+
A20 SATA0_RXB20 SATA1_RXA21 GND (FIXED)
B21 GND (FIXED)
A22 N.C.
B22 N.C.
A23 N.C.
B23 N.C.
A24 SUS_S5#
B24 PWR_OK
A25 N.C.
B25 N.C.
A26 N.C.
B26 N.C.
A27 BATLOW#
B27 WDT
A28 (S)ATA_ACT#
B28 RSVD
A29 RSVD
B29 RSVD
A30 RSVD
B30 RSVD
A31 GND (FIXED)
B31 GND (FIXED)
A32 RSVD
B32 SPKR
A33 RSVD
B33 I2C_CK
A34 BIOS_DIS0#
B34 I2C_DAT
A35 THRMTRIP#
B35 THRM#
A36 N.C.
B36 N.C.
A37 N.C.
B37 N.C.
A38 GND
B38 GND
A39 PCIE_TX12+
B39 PCIE_RX12+
A40 PCIE_TX12B40 PCIE_RX12A41 GND (FIXED)
B41 GND (FIXED)
A42 USB2B42 USB3A43 USB2+
B43 USB3+
A44 USB_2_3_OC#
B44 USB_0_1_OC#
A45 USB0B45 USB1A46 USB0+
B46 USB1+
A47 VCC_RTC
B47 ESPI_EN#
A48 RSVD
B48 N.C.
A49 GBE0_SDP
B49 SYS_RESET#
A50 LPC_SERIRQ
B50 CB_RESET#
A51 GND (FIXED)
B51 GND (FIXED)
A52 PCIE_TX5+
B52 PCIE_RX5+
A53 PCIE_TX5B53 PCIE_RX5A54 GPI0
B54 GPO1
A55 PCIE_TX4+
B55 PCIE_RX4+
DV970 only supports LPC interface, no eSPI mode interface.
Row A
A56 PCIE_TX4A57 GND
A58 PCIE_TX3+
A59 PCIE_TX3A60 GND (FIXED)
A61 PCIE_TX2+
A62 PCIE_TX2A63 GPI1
A64 PCIE_TX1+
A65 PCIE_TX1A66 GND
A67 GPI2
A68 PCIE_TX0+
A69 PCIE_TX0A70 GND (FIXED)
A71 PCIE_TX8+
A72 PCIE_TX8A73 GND
A74 PCIE_TX9+
A75 PCIE_TX9A76 GND
A77 N.C.
A78 N.C.
A79 GND
A80 GND (FIXED)
A81 N.C.
A82 N.C.
A83 GND
A84 NCSI_TX_EN
A85 GPI3
A86 RSVD
A87 RSVD
A88 PCIE_CK_REF+
A89 PCIE_CK_REFA90 GND (FIXED)
A91 SPI_POWER
A92 SPI_MISO
A93 GPO0
A94 SPI_CLK
A95 SPI_MOSI
A96 TPM_PP
A97 N.C.
A98 SER0_TX
A99 SER0_RX
A100 GND (FIXED)
A101 SER1_TX
A102 SER1_RX
A103 LID#
A104 VCC_12V
A105 VCC_12V
A106 VCC_12V
A107 VCC_12V
A108 VCC_12V
A109 VCC_12V
A110 GND (FIXED)
Row B
B56 PCIE_RX4B57 GPO2
B58 PCIE_RX3+
B59 PCIE_RX3B60 GND (FIXED)
B61 PCIE_RX2+
B62 PCIE_RX2B63 GPO3
B64 PCIE_RX1+
B65 PCIE_RX1B66 WAKE0#
B67 WAKE1#
B68 PCIE_RX0+
B69 PCIE_RX0B70 GND (FIXED)
B71 PCIE_RX8+
B72 PCIE_RX8B73 GND
B74 PCIE_RX9+
B75 PCIE_RX9B76 GND
B77 N.C.
B78 N.C.
B79 GND
B80 GND (FIXED)
B81 N.C.
B82 N.C.
B83 GND
B84 VCC_5V_SBY
B85 VCC_5V_SBY
B86 VCC_5V_SBY
B87 VCC_5V_SBY
B88 BIOS_DIS1#
B89 NCSI_RX_ER
B90 GND (FIXED)
B91 NCSI_CLK_IN
B92 NCSI_RXD1
B93 NCSI_RXD0
B94 NCSI_CRS_DV
B95 NCSI_TXD1
B96 NCSI_TXD0
B97 SPI_CS#
B98 NCSI_ARB_IN
B99 NCSI_ARB_OUT
B100 GND (FIXED)
B101 FAN_PWMOUT
B102 FAN_TACHIN
B103 SLEEP#
B104 VCC_12V
B105 VCC_12V
B106 VCC_12V
B107 VCC_12V
B108 VCC_12V
B109 VCC_12V
B110 GND (FIXED)
Row C
C1 GND (FIXED)
C2 GND
C3 USB_SSRX0C4 USB_SSRX0+
C5 GND
C6 USB_SSRX1C7 USB_SSRX1+
C8 GND
C9 N.C.
C10 N.C.
C11 GND (FIXED)
C12 N.C.
C13 N.C.
C14 GND
C15 10G_PHY_MDC_SCL3
C16 10G_PHY_MDC_SCL2
C17 10G_SDP2
C18 GND
C19 PCIE_RX6+
C20 PCIE_RX6C21 GND (FIXED)
C22 PCIE_RX7+
C23 PCIE_RX7C24 10G_INT2
C25 GND
C26 10G_KR_RX3+
C27 10G_KR_RX3C28 GND
C29 10G_KR_RX2+
C30 10G_KR_RX2C31 GND (FIXED)
C32 10G_SFP_SDA3
C33 10G_SFP_SDA2
C34 10G_PHY_RST_23
C35 10G_PHY_RST_01
C36 10G_LED_SDA
C37 10G_LED_SCL
C38 10G_SFP_SDA1
C39 10G_SFP_SDA0
C40 10G_SDP0
C41 GND (FIXED)
C42 10G_KR_RX1+
C43 10G_KR_RX1C44 GND
C45 10G_PHY_MDC_SCL1
C46 10G_PHY_MDC_SCL0
C47 10G_INT0
C48 GND
C49 10G_KR_RX0+
C50 10G_KR_RX0C51 GND (FIXED)
C52 PCIE_RX16+
C53 PCIE_RX16C54 TYPE0#
C55 PCIE_RX17+
Row D
D1 GND (FIXED)
D2 GND
D3 USB_SSTX0D4 USB_SSTX0+
D5 GND
D6 USB_SSTX1D7 USB_SSTX1+
D8 GND
D9 N.C.
D10 N.C.
D11 GND (FIXED)
D12 N.C.
D13 N.C.
D14 GND
D15 10G_PHY_MDIO_SDA3
D16 10G_PHY_MDIO_SDA2
D17 10G_SDP3
D18 GND
D19 PCIE_TX6+
D20 PCIE_TX6D21 GND (FIXED)
D22 PCIE_TX7+
D23 PCIE_TX7D24 10G_INT3
D25 GND
D26 10G_KR_TX3+
D27 10G_KR_TX3D28 GND
D29 10G_KR_TX2+
D30 10G_KR_TX2D31 GND (FIXED)
D32 10G_SFP_SCL3
D33 10G_SFP_SCL2
D34 10G_PHY_CAP_23
D35 10G_PHY_CAP_01
D36 RSVD
D37 RSVD
D38 10G_SFP_SCL1
D39 10G_SFP_SCL0
D40 10G_SDP1
D41 GND (FIXED)
D42 10G_KR_TX1+
D43 10G_KR_TX1D44 GND
D45 10G_PHY_MDIO_SDA1
D46 10G_PHY_MDIO_SDA0
D47 10G_INT1
D48 GND
D49 10G_KR_TX0+
D50 10G_KR_TX0D51 GND (FIXED)
D52 PCIE_TX16+
D53 PCIE_TX16D54 RSVD
D55 PCIE_TX17+
Row C
C56 PCIE_RX17C57 N.C.
C58 PCIE_RX18+
C59 PCIE_RX18C60 GND (FIXED)
C61 PCIE_RX19+
C62 PCIE_RX19C63 RSVD
C64 RSVD
C65 PCIE_RX20+
C66 PCIE_RX20C67 RAPID_SHUTDOWN
C68 PCIE_RX21+
C69 PCIE_RX21C70 GND (FIXED)
C71 PCIE_RX22+
C72 PCIE_RX22C73 GND
C74 PCIE_RX23+
C75 PCIE_RX23C76 GND
C77 RSVD
C78 PCIE_RX24+
C79 PCIE_RX24C80 GND (FIXED)
C81 PCIE_RX25+
C82 PCIE_RX25C83 RSVD
C84 GND
C85 N.C.
C86 N.C.
C87 GND
C88 N.C.
C89 N.C.
C90 GND (FIXED)
C91 PCIE_RX28+
C92 PCIE_RX28C93 GND
C94 PCIE_RX29+
C95 PCIE_RX29C96 GND
C97 RSVD
C98 N.C.
C99 N.C.
C100 GND (FIXED)
C101 N.C.
C102 N.C.
C103 GND
C104 VCC_12V
C105 VCC_12V
C106 VCC_12V
C107 VCC_12V
C108 VCC_12V
C109 VCC_12V
C110 GND (FIXED)
Row D
D56 PCIE_TX17D57 TYPE2#
D58 PCIE_TX18+
D59 PCIE_TX18D60 GND (FIXED)
D61 PCIE_TX19+
D62 PCIE_TX19D63 RSVD
D64 RSVD
D65 PCIE_TX20+
D66 PCIE_TX20D67 GND
D68 PCIE_TX21+
D69 PCIE_TX21D70 GND (FIXED)
D71 PCIE_TX22+
D72 PCIE_TX22D73 GND
D74 PCIE_TX23+
D75 PCIE_TX23D76 GND
D77 RSVD
D78 PCIE_TX24+
D79 PCIE_TX24D80 GND (FIXED)
D81 PCIE_TX25+
D82 PCIE_TX25D83 RSVD
D84 GND
D85 N.C.
D86 N.C.
D87 GND
D88 N.C.
D89 N.C.
D90 GND (FIXED)
D91 PCIE_TX28+
D92 PCIE_TX28D93 GND
D94 PCIE_TX29+
D95 PCIE_TX29D96 GND
D97 RSVD
D98 N.C.
D99 N.C.
D100 GND (FIXED)
D101 N.C.
D102 N.C.
D103 GND
D104 VCC_12V
D105 VCC_12V
D106 VCC_12V
D107 VCC_12V
D108 VCC_12V
D109 VCC_12V
D110 GND (FIXED)
15
Chapter 3 Hardware Installation
www.dfi.com
Chapter 3
COM Express Connectors Signals and Descriptions
Pin Types
I
Input to the Module
O
Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
Power Inputs used for power delivery to the Module electronics.
KR 10GBASE-KR compatible signal.
Gigabit Ethernet Signals Descriptions
Signal
GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3GBE0_ACT#
GBE0_LINK#
GBE0_LINK100#
GBE0_LINK1000#
Pin#
A13
A12
A10
A9
A7
A6
A3
A2
B2
A8
A4
A5
Pin Type
I/O Analog
I/O Analog
I/O Analog
I/O Analog
I/O Analog
I/O Analog
I/O Analog
I/O Analog
OD CMOS
OD CMOS
OD CMOS
OD CMOS
Pwr Rail /Tolerance
3.3V max Suspend
3.3V max Suspend
3.3V max Suspend
3.3V max Suspend
3.3V max Suspend
3.3V max Suspend
3.3V max Suspend
3.3V max Suspend
3.3V Suspend/3.3V
3.3V Suspend/3.3V
3.3V Suspend/3.3V
3.3V Suspend/3.3V
COMe SPEC PU/PD
DV970 PU/PD
Module Base Specification R3.0
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec modes. Some pairs
are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/B1_DA+/TX+/TX+/MDI[1]+/B1_DB+/RX+/RX+/MDI[2]+/B1_DC+/MDI[3]+/B1_DD+/Gigabit
Gigabit
Gigabit
Gigabit
GBE0_CTREF
A14
REF
GND min, 3.3V max
N.C.
GBE0_SDP
A49
I/O
3.3V Suspend/3.3V
RSVD PU 10KΩ
Pin#
B91
B93
B92
B96
B95
Pin Type
I CMOS
O CMOS
O CMOS
I CMOS
I CMOS
Pwr Rail /Tolerance
3.3V Suspend/3.3V
3.3V Suspend/3.3V
3.3V Suspend/3.3V
3.3V Suspend/3.3V
3.3V Suspend/3.3V
NCSI_CRS_DV
B94
O CMOS
3.3V Suspend/3.3V
NCSI_TX_EN
A84
I CMOS
3.3V Suspend/3.3V
NCSI_RX_ER
B89
O CMOS
3.3V Suspend/3.3V
NCSI_ARB_IN
B98
I CMOS
3.3V Suspend/3.3V
NCSI_ARB_OUT
B99
O CMOS
3.3V Suspend/3.3V
Ethernet
Ethernet
Ethernet
Ethernet
Controller
Controller
Controller
Controller
0
0
0
0
activity indicator, active low.
link indicator, active low.
100 Mbit / sec link indicator, active low.
1000 Mbit / sec link indicator, active low.
Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The
reference voltage is determined by the requirements of the Module PHY and may
be as low as 0V and as high as 3.3V. The reference voltage output shall be
current limited on the Module. In the case in which the reference is shorted to
ground, the current shall be limited to 250 mA or less.
Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for
IEEE1588 support such as a 1pps signal.
NC-SI Signals Descriptions
Signal
NCSI_CLK_IN
NCSI_RXD0
NCSI_RXD1
NCSI_TXD0
NCSI_TXD1
10Gb Ethernet Signals Descriptions
Chapter
Signal 3 Hardware Installation
Pin#
COMe SPEC PU/PD
PD 10KΩ
PD 10KΩ
PD 10KΩ
DV970 PU/PD
PD 10KΩ to GND
PD 3KΩ to GND
PD 3KΩ to GND
PD 10KΩ to GND
PD 10KΩ to GND
PD 10KΩ to GND
PD 10KΩ
PU 10KΩ to 3.3V Suspend
PD 10KΩ to GND
RSVD PU 10KΩ to
3.3V Suspend
RSVD PU 4.7KΩ to
3.3V Suspend
(IPD 20KΩ)
Module Base Specification R3.0
NC-SI Clock reference for receive, transmit, and control interface.
NC-SI Receive Data (from NC to BMC).
NC-SI Receive Data (from NC to BMC).
NC-SI Transmit Data (from BMC to NC).
NC-SI Transmit Data (from BMC to NC).
NC-SI Carrier Sense/Receive Data Valid to MC, indicating that the transmitted
data from NC to BMC is valid.
NC-SI Transmit enable.
NC-SI Receive error.
NC-SI hardware arbitration input.
NC-SI hardware arbitration output.
16
Pin Type
Pwr Rail /Tolerance
COMe SPEC PU/PD
DV970 PU/PD
Module Base Specification R3.0
www.dfi.com
NCSI_RX_ER
B89
O CMOS
3.3V Suspend/3.3V
NCSI_ARB_IN
B98
I CMOS
3.3V Suspend/3.3V
NCSI_ARB_OUT
B99
O CMOS
3.3V Suspend/3.3V
RSVD PU 10KΩ to
3.3V Suspend
RSVD PU 4.7KΩ to
3.3V Suspend
(IPD 20KΩ)
Chapter 3
PU 10KΩ to 3.3V Suspend
NC-SI Receive error.
NC-SI hardware arbitration input.
NC-SI hardware arbitration output.
10Gb Ethernet Signals Descriptions
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
10G_KR_TX0+
D49
O KR
AC coupled at receiver
10G_KR_TX0-
D50
O KR
AC coupled at receiver
10G_KR_TX1+
D42
O KR
AC coupled at receiver
10G_KR_TX1-
D43
O KR
AC coupled at receiver
10G_KR_TX2+
D29
O KR
AC coupled at receiver
10G_KR_TX2-
D30
O KR
AC coupled at receiver
10G_KR_TX3+
D26
O KR
AC coupled at receiver
10G_KR_TX3-
D27
O KR
AC coupled at receiver
10G_KR_RX0+
10G_KR_RX010G_KR_RX1+
10G_KR_RX110G_KR_RX2+
10G_KR_RX210G_KR_RX3+
10G_KR_RX310G_PHY_MDIO_SDA0
C49
C50
C42
C43
C29
C30
C26
C27
D46
I KR
I KR
I KR
I KR
I KR
I KR
I KR
I KR
O CMOS
AC
AC
AC
AC
AC
AC
AC
AC
10G_PHY_MDIO_SDA1
D45
10G_PHY_MDIO_SDA2
D16
10G_PHY_MDIO_SDA3
D15
10G_PHY_MDC_SCL0
C46
10G_PHY_MDC_SCL1
C45
10G_PHY_MDC_SCL2
C16
10G_PHY_MDC_SCL3
C15
10G_PHY_CAP_01
D35
coupled
coupled
coupled
coupled
coupled
coupled
coupled
coupled
on
on
on
on
on
on
on
on
COMe SPEC PU/PD
Module
Module
Module
Module
Module
Module
Module
Module
AC
AC
AC
AC
AC
AC
AC
AC
Coupling
Coupling
Coupling
Coupling
Coupling
Coupling
Coupling
Coupling
capacitor
capacitor
capacitor
capacitor
capacitor
capacitor
capacitor
capacitor
for details on AC coupling
for details on AC coupling
for details on AC coupling
for details on AC coupling
for details on AC coupling
for details on AC coupling
for details on AC coupling
MDIO:
PU 2.2KΩ to
3.3V Suspend
MDIO Mode: Management Data I/O interface mode data signal for serial data
transfers between the MAC and an external PHY.
I2C Mode: I2C data signal, of the 2-wire management interface used for serial
data transfers between the MAC and an external PHY.
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
MDC :
PU 2.2KΩ to
3.3V Suspend
MDIO Mode: Management Data I/O Interface mode clock signal for serial data
transfers between the MAC and an external PHY.
I2C Mode: I2C Clock signal, of the 2-wire management interface used for serial
data transfers between the MAC and an external PHY.
PU 10KΩ to 3.3V Suspend
PU 100KΩ to
3.3V Suspend
Phy mode capability pin: Indicates if the PHY for 10G lanes 0 and 1 is capable of
configuration by I²C. High indicates MDIO-only configuration, and low indicates
configuration capability via I²C or MDIO. The actual protocol used for PHY
configuration is determined by the module, in part based on this input. The actual
protocol used is indicated over the dedicated I²C interface
Phy mode capability pin: Indicates if the PHY for 10G lanes 2 and 3 is capable of
configuration by I²C. High indicates MDIO-only configuration, and low indicates
configurationcapability via I²C or MDIO. The actual protocol used for PHY
configuration is determined by the module, in part based on this input. The actual
protocol used is indicated over the dedicated I²C interface
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
3.3V Suspend/3.3V
10G_PHY_CAP_23
D34
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
PU 100KΩ to
3.3V Suspend
10G_SFP_SDA0
C39
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
IPU 5KΩ,
RSV PU 4.7KΩ to
3.3V Suspend
10G_SFP_SDA1
C38
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SDA2
C33
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SDA3
C32
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
Chapter 3 Hardware Installation
for details on AC coupling
PU 2.2KΩ to 3.3V Suspend
I/O OD
CMOS
I/O OD
CMOS
I/O OD
CMOS
Module Base Specification R3.0
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, transmit output differential pairs.
See section ‘AC Coupling of 10G_KR_TX Signals‘ below
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
10GBASE-KR ports, receive input differential pairs.
3.3V Suspend/3.3V
I/O OD
CMOS
O CMOS
I CMOS
DV970 PU/PD
17
IPU 5KΩ,
RSV PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
www.dfi.com
10G_SFP_SDA0
C39
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SDA1
C38
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SDA2
C33
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SDA3
C32
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SCL0
D39
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SCL1
D38
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SCL2
D33
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SFP_SCL3
D32
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_LED_SDA
C36
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_LED_SCL
C37
I/O OD
CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_INT0
C47
I CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_INT1
D47
I CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_INT2
C24
I CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_INT3
D24
I CMOS
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
10G_SDP0
C40
I/O CMOS
3.3V Suspend/3.3V
10G_SDP1
D40
I/O CMOS
3.3V Suspend/3.3V
10G_SDP2
C17
I/O CMOS
3.3V Suspend/3.3V
10G_SDP3
D17
I/O CMOS
3.3V Suspend/3.3V
10G_PHY_RST_01
C35
O CMOS
3.3V Suspend/3.3V
10G_PHY_RST_23
C34
O CMOS
3.3V Suspend/3.3V
I/O OD
CMOS
I/O OD
CMOS
I/O OD
CMOS
I/O OD
CMOS
protocol used is indicated over the dedicated I²C interface
Chapter 3
IPU 5KΩ,
RSV PU 4.7KΩ to
3.3V Suspend
IPU 5KΩ,
RSV PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
IPU 5KΩ,
RSV PU 4.7KΩ to
3.3V Suspend
IPU 5KΩ,
RSV PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
PU 4.7KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
PU 10KΩ to
3.3V Suspend
PU 10KΩ to
3.3V Suspend
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C data signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C clock signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C clock signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C clock signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C clock signal of the 2-wire management interface used by the 10GbE controller
to access the management registers of an external Optical SFP Module.
I2C Data of the 2-wire interface that transfers LED signals and PHY straps for I2C
or MDIO operation of optical PHYs. Refer to the details in I2C Data Mapping to
Carrier Board Based PCA9539 I/O Expander.
I2C Clock of the 2-wire interface that transfers LED and strap signals for I2C or
MDIO operation of optical PHYs.
Interrupt pin from copper PHY or optical SFP Module to the 10GbE controller.
Interrupt pin from copper PHY or optical SFP Module to the 10GbE controller.
Interrupt pin from copper PHY or optical SFP Module to the 10GbE controller.
Interrupt pin from copper PHY or optical SFP Module to the 10GbE controller.
Software-Definable Pins. Can also be used for IEEE1588 support such as a 1pps
signal.
Software-Definable Pins. Can also be used for IEEE1588 support such as a 1pps
signal.
Software-Definable Pins. Can also be used for IEEE1588 support such as a 1pps
signal.
Software-Definable Pins. Can also be used for IEEE1588 support such as a 1pps
signal.
Output signal that resets an optical PHY on port 0 and port1 (with copper PHY
this signal is not used).
Output signal that resets an Optical PHY on port 2 and port 3 (with Copper PHY
this signal is not used).
SATA Signals Descriptions
Signal
SATA0_TX+
SATA0_TXSATA0_RX+
SATA0_RXSATA1_TX+
SATA1_TXSATA1_RX+
SATA1_RX-
Pin#
A16
A17
A19
A20
B16
B17
B19
B20
Pin Type
O SATA
O SATA
I SATA
I SATA
O SATA
O SATA
I SATA
I SATA
Pwr Rail /Tolerance
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
(S)ATA_ACT#
A28
I/O CMOS
3.3V / 3.3V
COMe SPEC PU/PD
AC
AC
AC
AC
AC
AC
AC
AC
18
Chapter
3 Hardware
General
Purpose Installation
PCI Express Lanes Signals Descriptions
DV970 PU/PD
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
AND Gate out,
up to 3.3V
Module Base Specification R3.0
Serial ATA Channel 0 transmit differential pair.
Serial ATA Channel 0 receive differential pair.
Serial ATA Channel 1 transmit differential pair.
Serial ATA Channel 1 receive differential pair.
Serial ATA (activity indicator), active low.
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SATA0_TX+
SATA0_TXSATA0_RX+
SATA0_RXSATA1_TX+
SATA1_TXSATA1_RX+
SATA1_RX-
A16
A17
A19
A20
B16
B17
B19
B20
O SATA
O SATA
I SATA
I SATA
O SATA
O SATA
I SATA
I SATA
AC
AC
AC
AC
AC
AC
AC
AC
coupled
coupled
coupled
coupled
coupled
coupled
coupled
coupled
(S)ATA_ACT#
A28
I/O CMOS
3.3V / 3.3V
on
on
on
on
on
on
on
on
Module
Module
Module
Module
Module
Module
Module
Module
AC
AC
AC
AC
AC
AC
AC
AC
Chapter 3
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
Coupling capacitor
AND Gate out,
up to 3.3V
Serial ATA Channel 0 transmit differential pair.
Serial ATA Channel 0 receive differential pair.
Serial ATA Channel 1 transmit differential pair.
Serial ATA Channel 1 receive differential pair.
Serial ATA (activity indicator), active low.
General Purpose PCI Express Lanes Signals Descriptions
Signal
PCIE_TX0+
PCIE_TX0PCIE_RX0+
PCIE_RX0PCIE_TX1+
PCIE_TX1PCIE_RX1+
PCIE_RX1PCIE_TX2+
PCIE_TX2PCIE_RX2+
PCIE_RX2PCIE_TX3+
PCIE_TX3PCIE_RX3+
PCIE_RX3PCIE_TX4+
PCIE_TX4PCIE_RX4+
PCIE_RX4PCIE_TX5+
PCIE_TX5PCIE_RX5+
PCIE_RX5PCIE_TX6+
PCIE_TX6PCIE_RX6+
PCIE_RX6PCIE_TX7+
PCIE_TX7PCIE_RX7+
PCIE_RX7PCIE_TX8+
PCIE_TX8PCIE_RX8+
PCIE_RX8PCIE_TX9+
PCIE_TX9PCIE_RX9+
PCIE_RX9PCIE_TX10+
PCIE_TX10PCIE_RX10+
PCIE_RX10PCIE_TX11+
PCIE_TX11PCIE_RX11+
PCIE_RX11PCIE_TX12+
Chapter
3 Hardware
PCIE_TX12-
Pin#
A68
A69
B68
B69
A64
A65
B64
B65
A61
A62
B61
B62
A58
A59
B58
B59
A55
A56
B55
B56
A52
A53
B52
B53
D19
D20
C19
C20
D22
D23
C22
C23
A71
A72
B71
B72
A74
A75
B74
B75
A77
A78
B77
B78
A81
A82
B81
B82
A39
Installation
A40
Pin Type
Pwr Rail /Tolerance
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
COMe SPEC PU/PD
DV970 PU/PD
AC Coupling capacitor
AC Coupling capacitor
Module Base Specification R3.0
PCI Express Differential Transmit Pairs 0
PCI Express Differential Receive Pairs 0
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 1
PCI Express Differential Receive Pairs 1
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 2
PCI Express Differential Receive Pairs 2
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 3
PCI Express Differential Receive Pairs 3
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 4
PCI Express Differential Receive Pairs 4
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 5
PCI Express Differential Receive Pairs 5
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 6
PCI Express Differential Receive Pairs 6
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 7
PCI Express Differential Receive Pairs 7
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
19
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 8
Different connector layout for Type 7
PCI Express Differential Receive Pairs 8
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 9
Different connector layout for Type 7
PCI Express Differential Receive Pairs 9
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 10
Different connector layout for Type 7
PCI Express Differential Receive Pairs 10
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 11
Different connector layout for Type 7
PCI Express Differential Receive Pairs 11
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 12
Different connector layout for Type 7
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PCIE_TX9+
PCIE_TX9PCIE_RX9+
PCIE_RX9PCIE_TX10+
PCIE_TX10PCIE_RX10+
PCIE_RX10PCIE_TX11+
PCIE_TX11PCIE_RX11+
PCIE_RX11PCIE_TX12+
PCIE_TX12PCIE_RX12+
PCIE_RX12PCIE_TX13+
PCIE_TX13PCIE_RX13+
PCIE_RX13PCIE_TX14+
PCIE_TX14PCIE_RX14+
PCIE_RX14PCIE_TX15+
PCIE_TX15PCIE_RX15+
PCIE_RX15PCIE_TX16+
PCIE_TX16PCIE_RX16+
PCIE_RX16PCIE_TX17+
PCIE_TX17PCIE_RX17+
PCIE_RX17PCIE_TX18+
PCIE_TX18PCIE_RX18+
PCIE_RX18PCIE_TX19+
PCIE_TX19PCIE_RX19+
PCIE_RX19PCIE_TX20+
PCIE_TX20PCIE_RX20+
PCIE_RX20PCIE_TX21+
PCIE_TX21PCIE_RX21+
PCIE_RX21PCIE_TX22+
PCIE_TX22PCIE_RX22+
PCIE_RX22PCIE_TX23+
PCIE_TX23PCIE_RX23+
PCIE_RX23PCIE_TX24+
PCIE_TX24PCIE_RX24+
Chapter
3 Hardware
PCIE_RX24-
A74
A75
B74
B75
A77
A78
B77
B78
A81
A82
B81
B82
A39
A40
B39
B40
A36
A37
B36
B37
A25
A26
B25
B26
A22
A23
B22
B23
D52
D53
C52
C53
D55
D56
C55
C56
D58
D59
C58
C59
D61
D62
C61
C62
D65
D66
C65
C66
D68
D69
C68
C69
D71
D72
C71
C72
D74
D75
C74
C75
D78
D79
C78
Installation
C79
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
AC Coupling capacitor
AC Coupling capacitor
Chapter 3
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AC Coupling capacitor
AC Coupling capacitor
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
20
AC Coupling capacitor
AC Coupling capacitor
PCI Express Differential Transmit Pairs 9
Different connector layout for Type 7
PCI Express Differential Receive Pairs 9
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 10
Different connector layout for Type 7
PCI Express Differential Receive Pairs 10
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 11
Different connector layout for Type 7
PCI Express Differential Receive Pairs 11
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 12
Different connector layout for Type 7
PCI Express Differential Receive Pairs 12
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 13
Different connector layout for Type 7
PCI Express Differential Receive Pairs 13
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 14
Different connector layout for Type 7
PCI Express Differential Receive Pairs 14
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 15
Different connector layout for Type 7
PCI Express Differential Receive Pairs 15
Different connector layout for Type 7
PCI Express Differential Transmit Pairs 16
These are the same lines as Type 7 PEG_TX0±
PCI Express Differential Receive Pairs 16
These are the same lines as Type 7 PEG_RX0±
PCI Express Differential Transmit Pairs 17
These are the same lines as Type 7 PEG_TX1±
PCI Express Differential Receive Pairs 17
These are the same lines as Type 7 PEG_RX1±
PCI Express Differential Transmit Pairs 18
These are the same lines as Type 7 PEG_TX2±
PCI Express Differential Receive Pairs 18
These are the same lines as Type 7 PEG_RX2±
PCI Express Differential Transmit Pairs 19
These are the same lines as Type 7 PEG_TX3±
PCI Express Differential Receive Pairs 19
These are the same lines as Type 7 PEG_RX3±
PCI Express Differential Transmit Pairs 20
These are the same lines as Type 7 PEG_TX4±
PCI Express Differential Receive Pairs 20
These are the same lines as Type 7 PEG_RX4±
PCI Express Differential Transmit Pairs 21
These are the same lines as Type 7 PEG_TX5±
PCI Express Differential Receive Pairs 21
These are the same lines as Type 7 PEG_RX5±
PCI Express Differential Transmit Pairs 22
These are the same lines as Type 7 PEG_TX6±
PCI Express Differential Receive Pairs 22
These are the same lines as Type 7 PEG_RX6±
PCI Express Differential Transmit Pairs 23
These are the same lines as Type 7 PEG_TX7±
PCI Express Differential Receive Pairs 23
These are the same lines as Type 7 PEG_RX7±
PCI Express Differential Transmit Pairs 24
These are the same lines as Type 7 PEG_TX8±
PCI Express Differential Receive Pairs 24
These are the same lines as Type 7 PEG_RX8±
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PCIE_RX21+
PCIE_RX21PCIE_TX22+
PCIE_TX22PCIE_RX22+
PCIE_RX22PCIE_TX23+
PCIE_TX23PCIE_RX23+
PCIE_RX23PCIE_TX24+
PCIE_TX24PCIE_RX24+
PCIE_RX24PCIE_TX25+
PCIE_TX25PCIE_RX25+
PCIE_RX25PCIE_TX26+
PCIE_TX26PCIE_RX26+
PCIE_RX26PCIE_TX27+
PCIE_TX27PCIE_RX27+
PCIE_RX27PCIE_TX28+
PCIE_TX28PCIE_RX28+
PCIE_RX28PCIE_TX29+
PCIE_TX29PCIE_RX29+
PCIE_RX29PCIE_TX30+
PCIE_TX30PCIE_RX30+
PCIE_RX30PCIE_TX31+
PCIE_TX31PCIE_RX31+
PCIE_RX31PCIE_CLK_REF+
PCIE_CLK_REF-
C68
C69
D71
D72
C71
C72
D74
D75
C74
C75
D78
D79
C78
C79
D81
D82
C81
C82
D85
D86
C85
C86
D88
D89
C88
C89
D91
D92
C91
C92
D94
D95
C94
C95
D98
D99
C98
C99
D101
D102
C101
C102
A88
A89
PCI Express Differential Receive Pairs 21
These are the same lines as Type 7 PEG_RX5±
PCI Express Differential Transmit Pairs 22
These are the same lines as Type 7 PEG_TX6±
PCI Express Differential Receive Pairs 22
These are the same lines as Type 7 PEG_RX6±
PCI Express Differential Transmit Pairs 23
These are the same lines as Type 7 PEG_TX7±
PCI Express Differential Receive Pairs 23
These are the same lines as Type 7 PEG_RX7±
PCI Express Differential Transmit Pairs 24
These are the same lines as Type 7 PEG_TX8±
PCI Express Differential Receive Pairs 24
These are the same lines as Type 7 PEG_RX8±
PCI Express Differential Transmit Pairs 25
These are the same lines as Type 7 PEG_TX9±
PCI Express Differential Receive Pairs 25
These are the same lines as Type 7 PEG_RX9±
PCI Express Differential Transmit Pairs 26
These are the same lines as Type 7 PEG_TX10±
PCI Express Differential Receive Pairs 26
These are the same lines as Type 7 PEG_RX10±
PCI Express Differential Transmit Pairs 27
These are the same lines as Type 7 PEG_TX11±
PCI Express Differential Receive Pairs 27
These are the same lines as Type 7 PEG_RX11±
PCI Express Differential Transmit Pairs 28
These are the same lines as Type 7 PEG_TX12±
PCI Express Differential Receive Pairs 28
These are the same lines as Type 7 PEG_RX12±
PCI Express Differential Transmit Pairs 29
These are the same lines as Type 7 PEG_TX13±
PCI Express Differential Receive Pairs 29
These are the same lines as Type 7 PEG_RX13±
PCI Express Differential Transmit Pairs 30
These are the same lines as Type 7 PEG_TX14±
PCI Express Differential Receive Pairs 30
These are the same lines as Type 7 PEG_RX14±
PCI Express Differential Transmit Pairs 31
These are the same lines as Type 7 PEG_TX15±
PCI Express Differential Receive Pairs 31
These are the same lines as Type 7 PEG_RX15±
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
PCIE
Pin Type
Pwr Rail /Tolerance
I/O USB
3.3V Suspend/3.3V
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 1.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 2.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 3.
3.3V Suspend/3.3V
IPU 20KΩ
RSV PU 10KΩ to
3V3 Suspend.
USB over-current sense, USB channels 0 and 1. A pull-up for this line shall be
present on the Module. An open drain driver from a USB current monitor on the
Carrier Board may drive this line low. Do not pull this line high on the Carrier
Board.
IPU 20KΩ
RSV PU 10KΩ to
USB over-current sense, USB channels 2 and 3. A pull-up for this line shall be
present on the Module. An open drain driver from a USB current monitor
on the
www.dfi.com
Carrier Board may drive this line low. Do not pull this line high on the Carrier
Chapter 3
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Reference clock output for all PCI Express and PCI Express Graphics lanes.
USB Signals Descriptions
Signal
Pin#
USB0+
A46
USB0-
A45
USB1+
USB1USB2+
USB2USB3+
USB3-
B46
B45
A43
A42
B43
B42
USB_0_1_OC#
B44
I CMOS
COMe SPEC PU/PD
PU 10KΩ to 3.3V Suspend
21
Chapter
3 Hardware Installation
USB_2_3_OC#
A44
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
DV970 PU/PD
Module Base Specification R3.0
USB differential pairs, channels 0. For type 7 only, USB0 may be configured as a
USB client or as a host, or both at the Module designer's discretion. All other USB
ports, if implemented, shall be host ports.
I/O USB
3.3V Suspend/3.3V
I/O USB
3.3V Suspend/3.3V
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 2.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 3.
B44
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
IPU 20KΩ
RSV PU 10KΩ to
3V3 Suspend.
USB over-current sense, USB channels 0 and 1. A pull-up for this line shall be
present on the Module. An open drain driver from a USB current monitor on the
Carrier Board may drive this line low. Do not pull this line high on the Carrier
Board.
USB_2_3_OC#
A44
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
IPU 20KΩ
RSV PU 10KΩ to
3V3 Suspend.
USB over-current sense, USB channels 2 and 3. A pull-up for this line shall be
present on the Module. An open drain driver from a USB current monitor on the
Carrier Board may drive this line low. Do not pull this line high on the Carrier
Board.
USB_SSTX0+
USB_SSTX0USB_SSRX0+
USB_SSRX0USB_SSTX1+
USB_SSTX1USB_SSRX1+
USB_SSRX1USB_SSTX2+
USB_SSTX2USB_SSRX2+
USB_SSRX2USB_SSTX3+
USB_SSTX3USB_SSRX3+
USB_SSRX3-
D4
D3
C4
C3
D7
D6
C7
C6
D10
D9
C10
C9
D13
D12
C13
C12
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
USB0-
A45
USB1+
USB1USB2+
USB2USB3+
USB3-
B46
B45
A43
A42
B43
B42
USB_0_1_OC#
USB0_HOST_PRSNT
B48
LPC Signals Descriptions
Descriptions
Pin#
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
I COMS
3.3V Suspend/3.3V
Pin Type
Pin Type
Pwr Rail /Tolerance
Pwr Rail /Tolerance
3.3V / 3.3V
1.8V /Suspend
/ 1.8V
3.3V
3.3V
LPC and eSPI Signals
Signal
LPC_AD0
Signal
LPC_AD1
LPC_AD0 / ESPI_IO_0
LPC_AD2
LPC_AD1 / ESPI_IO_1
LPC_AD3
LPC_AD2 / ESPI_IO_2
LPC_AD3 / ESPI_IO_3
B4
Pin#
B5
B4
B6
B5
B7
B6
LPC_FRAME#
B3
O CMOS
LPC_FRAME# / ESPI_CS0#
B3
O CMOS
I/O CMOS
I/O CMOS
B7
LPC_DRQ0#
B8
LPC_DRQ0# / ESPI_ALERT0#
LPC_DRQ1#
B8
B9
LPC_DRQ1# / ESPI_ARERT1#
B9
LPC_SERIRQ
A50
LPC_SERIRQ / ESPI_CS1#
A50
LPC_CLK
B10
SUS_STAT#
B18
BIOS_DIS0#
A34
Chapter
3 Hardware Installation
BIOS_DIS1#
B88
I CMOS
I CMOS
I/O CMOS
O CMOS
I/O CMOS
O CMOS
O CMOS
O CMOS
Chapter 3
USB differential pairs, channel 1.
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
AC Coupling capacitor
N.C.
COMe SPEC PU/PD
COMe SPEC PU/PD
ESPI mode:
PU 1KΩ to 1.8V
ESPI mode:
PU 1KΩ to 1.8V
LPC_SERIRQ :
PU 8.2K to 3.3V
LPC_SERIRQ :
PU 8.2KΩ to 3.3V
series 22Ω resistor
NA
PU 10KΩ to 3.3V
PU 10KΩ to 3.3V,
not PU
support
mode.
10KΩESPI
to 3.3V
PU 10KΩ to 3.3V,
not support ESPI mode.
PU 10KΩ to 3.3V
PU 10KΩ to 3.3V
series 22Ω resistor
IPU 20KΩ to
3V3 Suspend.
3.3V Suspend / 3.3V
1.8V Suspend / 1.8V
PU 10K to 3V3 Suspend.
PU 10K to 3V3 Suspend.
Additional transmit signal differential pairs for the SuperSpeed USB data path.
Additional receive signal differential pairs for the SuperSpeed USB data path.
Additional transmit signal differential pairs for the SuperSpeed USB data path.
Additional receive signal differential pairs for the SuperSpeed USB data path.
Module USB client may detect the presence of a USB host on USB0. A high value
indicates that a host is present.
DV970 PU/PD (LPC mode) Module Base Specification R3.0
DV970 PU/PD (LPC mode) Module Base Specification R3.0
LPC multiplexed address, command and data bus.
LPC Mode: LPC multiplexed address, command and data bus.
ESPI Mode: eSPI Master Data Input / Outputs These are bi-directional
input/output pins used to transfer data between master and slaves.
3.3V / 3.3V
1.8V /Suspend
/ 1.8V
3.3V
3.3V
1.8V Suspend / 1.8V
3.3V / 3.3V
1.8V Suspend / 1.8V
3.3V / 3.3V
1.8V Suspend / 1.8V
3.3V / 3.3V
1.8V Suspend / 1.8V
Additional transmit signal differential pairs for the SuperSpeed USB data path.
Additional receive signal differential pairs for the SuperSpeed USB data path.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
1.8V Suspend / 1.8V
3.3V / 3.3V
1.8V Suspend / 1.8V
3.3V / 3.3V
1.8V Suspend / 1.8V
Additional transmit signal differential pairs for the SuperSpeed USB data path.
Additional receive signal differential pairs for the SuperSpeed USB data path.
22
I CMOS
USB client or as a host, or both at the Module designer's discretion. All other USB
ports, if implemented, shall be host ports.
PU 10KΩ to
3V3 Suspend.
PU 10KΩ to
LPCMode:
frame indicates
start ofthe
an start
LPC cycle
LPC
LPC framethe
indicates
of an LPC cycle
ESPI Mode: eSPI Master Chip Select Outputs Driving Chip Select0#. A
lowselects a particular eSPI slave for the transaction. Each of the eSPI slaves is
connected to a dedicated Chip Selectn# pin.
LPC serial DMA request
LPC Mode: LPC serial DMA request
ESPI Mode: eSPI pins used by eSPI slave to request service from the eSPI
master.
LPC serial interrupt
LPC Mode: LPC serial interrupt
ESPI Mode: eSPI Master Chip Select Outputs Driving Chip Select# A low selects
a particular eSPI slave for the transaction. Each of the eSPI slaves is connected to
aLPC
dedicated
Chip Selectn#
clock output
- 33MHz pin.
nominal
SUS_STAT# indicates imminent suspend operation. It is used to notify LPC
devices that a low power state will be entered soon. LPC devices may need to
preserve memory or isolate outputs during the low power state.
Selection straps to determine the BIOS boot device. The Carrier should only float
these or pull them low, please refer to 4.13 for strapping options of BIOS disable
www.dfi.com
signals.
B10
A50
3.3V / 3.3V
O CMOS
I/O CMOS 1.8V
3.3VSuspend
/ 3.3V / 1.8V
O CMOS
1.8V Suspend / 1.8V
SUS_STAT#
/ ESPI_RESET#
LPC_CLK
B18
B10
OOCMOS
CMOS
3.3V
3.3VSuspend
/ 3.3V / 3.3V
1.8V
1.8VSuspend
Suspend/ /1.8V
1.8V
SUS_STAT#
ESPI_EN#
B18
B47
CMOS
IOCMOS
3.3V Suspend / 3.3V
NA
1.8V Suspend / 1.8V
BIOS_DIS0#
BIOS_DIS0#
A34
A34
BIOS_DIS1#
BIOS_DIS1#
B88
B88
LPC_CLK / ESPI_CK
LPC_SERIRQ
IICMOS
CMOS
NA
NA
Chapter 3series 22Ω resistor
series 22Ω resistor
LPC_SERIRQ :
PU 8.2K to 3.3V
series 22Ω resistor
PU 20KΩ to logic high.
PU
PU10KΩ
10K to 3V3
3V3 Suspend.
Suspend.
PU
PU10KΩ
10K to 3V3
3V3 Suspend.
Suspend.
PU 10KΩ to 3.3V
IPU 20KΩ to
series
22Ω resistor
3V3 Suspend.
IPU20KΩ
20KΩtoto
PU
3V3Suspend.
Suspend.
3V3
PU
PU10KΩ
10KΩtoto
3V3
3V3Suspend.
Suspend.
PU
PU10KΩ
10KΩtoto
3V3
3V3Suspend.
Suspend.
LPC Mode: LPC clock output - 33MHz nominal
ESPI Mode: eSPI Master Clock Output This pin provides the reference timing for
LPC serial interrupt
all the serial input and output operations.
LPC Mode: SUS_STAT# indicates imminent suspend operation. It is used to
notify LPC devices that a low power state will be entered soon. LPC devices may
LPC to
clock
outputmemory
- 33MHzornominal
need
preserve
isolate outputs during the low power state.
ESPI Mode: eSPI Reset, Reset the eSPI interface for both master and slaves.
eSPI Reset# is typically driven from eSPI master to eSPI slaves.
This
signal is used
by the
Carrier to
indicateoperation.
the operating
of notify
the LPC/eSPI
SUS_STAT#
indicates
imminent
suspend
It is mode
used to
LPC
bus.
If leftthat
unconnected
on state
the carrier,
modesoon.
(default)
selected.
pulled
devices
a low power
will beLPC
entered
LPC is
devices
mayIfneed
to
topreserve
GND on memory
the carrier,
eSPI mode
is selected.
Thislow
signal
is pulled
or isolate
outputs
during the
power
state. to a logic high
on the module through a resistor. The Carrier should only float this line or pull it
low
Selection
device.
The
Carrier
should
only
float
Selectionstraps
strapstotodetermine
determinethe
theBIOS
BIOSboot
boot
device.
The
Carrier
should
only
float
these
toto
4.13
forfor
strapping
options
of of
BIOS
disable
theseororpull
pullthem
themlow,
low,please
pleaserefer
refer
4.13
strapping
options
BIOS
disable
signals.
signals.
SPI Signals Descriptions
Signal
Pin#
Pin Type
SPI_CS#
B97
O CMOS
SPI_MISO
A92
I CMOS
SPI_MOSI
A95
O CMOS
SPI_CLK
A94
O CMOS
SPI_POWER
A91
O
Pwr Rail /Tolerance
3.3V Suspend / 3.3V
1.8V Suspend / 3.3V
3.3V Suspend / 3.3V
1.8V Suspend / 3.3V
3.3V Suspend / 3.3V
1.8V Suspend / 3.3V
3.3V Suspend / 3.3V
1.8V Suspend / 3.3V
COMe SPEC PU/PD
DV970 (SPI_3VDU) PU/PD Module Base Specification R3.0
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1
Series resistor 33Ω
Series resistor 33Ω
Data in to Module from Carrier SPI
Data out from Module to Carrier SPI
Clock from Module to Carrier SPI
Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The
Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less
than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices
on the Carrier Board.
3.3V Suspend / 3.3V
1.8V Suspend / 3.3V
General Purpose Serial Interface Signals Descriptions
Signal
SER0_TX
Pin#
A98
Pin Type
O CMOS-T
Pwr Rail /Tolerance
5V/12V
SER0_RX
A99
I CMOS-T
5V/12V
SER1_TX /
CAN_TX
SER1_RX /
CAN_RX
A101
O CMOS-T
A102
I CMOS-T
COMe SPEC PU/PD
DV970 PU/PD
PU 10KΩ to 3.3V
& isolate by Diode
5V/12V
3.3V/12V
5V/12V
3.3V/12V
PU 10KΩ to 3.3V
& isolate by Diode
Module Base Specification R3.0
General purpose serial port 0 transmitter
General purpose serial port 0 receiver
General purpose serial port 1 transmitter
CAN TX output for CAN Bus channel 0.
General purpose serial port 1 receiver
RX input for CAN Bus channel 0.
I2C Signal Descriptions
Signal
Pin#
I2C_CK
B33
I2C_DAT
B34
Pin Type
I/O OD
CMOS
I/O OD
CMOS
Pwr Rail /Tolerance
COMe SPEC PU/PD
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
COMe SPEC PU/PD
DV970 PU/PD
PU 2.2KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
Module Base Specification R3.0
General purpose I2C port clock output
General purpose I2C port data I/O line
Miscellaneous Signal Descriptions
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
SPKR
B32
O CMOS
3.3V / 3.3V
3.3V / 3.3V
WDT
B27
O CMOS
FAN_PWMOUT
B101
O OD CMOS 3.3V / 12V
FAN_TACHIN
B102
I OD CMOS 3.3V / 12V
Chapter 3 Hardware Installation
DV970 PU/PD
PD 100KΩ to GND.
23
PU 47KΩ to 3.3V
RSV PD 100KΩ to GND
PU 47KΩ to 3.3V
Module Base Specification R3.0
Output for audio enunciator - the "speaker" in PC-AT systems. This port provides
the PC beep signal and is mostly intended for debugging purposes.
Output indicating that a watchdog time-out event has occurred.
Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control
the fan's RPM.
Fan tachometer input for a fan with a two pulse output.
Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM
chip has
www.dfi.com
I2C Signal Descriptions
Signal
Pin#
I2C_CK
B33
I2C_DAT
B34
Pin Type
I/O OD
CMOS
I/O OD
CMOS
PU/PD
Chapter 3 DV970
PU 2.2KΩ to
Pwr Rail /Tolerance
COMe SPEC PU/PD
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
Pwr Rail /Tolerance
COMe SPEC PU/PD
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
Module Base Specification R3.0
General purpose I2C port clock output
General purpose I2C port data I/O line
Miscellaneous Signal Descriptions
Signal
Pin#
Pin Type
SPKR
B32
O CMOS
3.3V / 3.3V
WDT
B27
O CMOS
3.3V / 3.3V
FAN_PWMOUT
B101
O OD CMOS 3.3V / 12V
FAN_TACHIN
B102
I OD CMOS 3.3V / 12V
TPM_PP
A96
I CMOS
3.3V / 3.3V
DV970 PU/PD
PD 100KΩ to GND.
RSV PD 100KΩ to GND
PU 47KΩ to 3.3V
PU 47KΩ to 3.3V
PD to GND.
PD 100KΩ to GND.
Module Base Specification R3.0
Output for audio enunciator - the "speaker" in PC-AT systems. This port provides
the PC beep signal and is mostly intended for debugging purposes.
Output indicating that a watchdog time-out event has occurred.
Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control
the fan's RPM.
Fan tachometer input for a fan with a two pulse output.
Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has
an internal pull down. This signal is used to indicate Physical Presence to the
TPM.
Power and System Management Signals Descriptions
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
COMe SPEC PU/PD
DV970 PU/PD
PWRBTN#
B12
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
PU 10KΩ to
3.3V Suspend
SYS_RESET#
B49
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
PU 10KΩ to
3.3V Suspend
Reset button input. Active low request for Module to reset and reboot. May be
falling edge sensitive. For situations when SYS_RESET# is not able to reestablish
control of the system, PWR_OK or a power cycle may be used.
CB_RESET#
B50
O CMOS
3.3V Suspend/3.3V
PD 100KΩ to GND
Reset output from Module to Carrier Board. Active low. Issued by Module chipset
and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V
power input that falls below the minimum specification, a watchdog timeout, or
may be initiated by the Module software.
PWR_OK
B24
I CMOS
3.3V / 3.3V
SUS_STAT#
B18
O CMOS
3.3V Suspend / 3.3V
SUS_S3#
A15
O CMOS
3.3V Suspend/3.3V
PD 100KΩ to GND
SUS_S4#
SUS_S5#
WAKE0#
A18
A24
B66
O CMOS
O CMOS
I CMOS
3.3V Suspend/3.3V
3.3V Suspend/3.3V
3.3V Suspend/3.3V
PD 100KΩ to GND
PD 100KΩ to GND
PU 10KΩ to 3.3V Suspend
WAKE1#
B67
I CMOS
3.3V Suspend/3.3V
PU 10KΩ to 3.3V Suspend
BATLOW#
A27
I CMOS
3.3V Suspend/ 3.3V
PU 10KΩ to 3.3V Suspend
LID#
A103
I OD CMOS 3.3V Suspend/12V
PU 47KΩ to 3.3V Suspend
SLEEP#
B103
I OD CMOS 3.3V Suspend/12V
PU 47KΩ to 3.3V Suspend
PU to 3.3V
PU to 3.3V
PU 2.2KΩ to
3.3V Suspend
PU 10KΩ to
3.3V Suspend
Module Base Specification R3.0
A falling edge creates a power button event. Power button events can be used to
bring a system out of S5 soft off and other suspend states, as well as powering
the system down.
Power OK from main power supply. A high value indicates that the power is good.
This signal can be used to hold off Module startup to allow Carrier based FPGAs
or other configurable devices time to be programmed.
Indicates imminent suspend operation; used to notify LPC devices. Not used in
eSPI implementations.
Indicates system is in Suspend to RAM state. Active low output. An inverted copy
of SUS_S3# on the Carrier Board may be used to enable the non-standby power
on a typical ATX supply.
Indicates system is in Suspend to Disk state. Active low output.
Indicates system is in Soft Off state.
PCI Express wake up signal.
General purpose wake up signal. May be used to implement wake-up on PS2
keyboard or mouse activity.
Indicates that external battery is low. This port provides a battery-low signal to
the Module for orderly transitioning to power saving or power cut-off ACPI
modes. In a type 7 system, BATLOW# can be used as a power fail indication.
PU 47KΩ to 3.3V Suspend
LID switch. Low active signal used by the ACPI operating system for a LID switch.
& isolate by Diode
PU 47KΩ to 3.3V Suspend Sleep button. Low active signal used by the ACPI operating system to bring the
& isolate by Diode
system to sleep state or to wake it up again.
Rapid Shutdown Signals Descriptions
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
RAPID_SHUTDOWN
C67
I CMOS
5.0V Suspend / 5.0V
Thermal Protection Signals Descriptions
Signal 3 Hardware Installation
Pin#
Pin Type
Chapter
COMe SPEC PU/PD
DV970 PU/PD
Module Base Specification R3.0
Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source
impedance for ≥ 20 µs.
24
Pwr Rail /Tolerance
COMe SPEC PU/PD
DV970 PU/PD
IPU 10KΩ to 3.3V
Module Base Specification R3.0
www.dfi.com
Chapter 3
Rapid Shutdown Signals Descriptions
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
RAPID_SHUTDOWN
C67
I CMOS
5.0V Suspend / 5.0V
COMe SPEC PU/PD
DV970 PU/PD
Module Base Specification R3.0
Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source
impedance for ≥ 20 µs.
Thermal Protection Signals Descriptions
Signal
THRM#
THRMTRIP#
Pin#
B35
A35
Pin Type
I CMOS
O CMOS
Pwr Rail /Tolerance
3.3V / 3.3V
3.3V / 3.3V
COMe SPEC PU/PD
DV970 PU/PD
IPU 10KΩ to 3.3V
Pin Type
I/O OD
CMOS
I/O OD
CMOS
Pwr Rail /Tolerance
COMe SPEC PU/PD
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
3.3V Suspend/3.3V
PU 2.2KΩ to 3.3V Suspend
DV970 PU/PD
PU 2.2KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
PU 2.2KΩ to
3.3V Suspend
Module Base Specification R3.0
Input from off-Module temp sensor indicating an over-temp situation.
Active low output indicating that the CPU has entered thermal shutdown.
SMBUS Signals Descriptions
Signal
Pin#
SMB_CK
B13
SMB_DAT
B14
SMB_ALERT#
B15
I CMOS
3.3V Suspend/3.3V
Pin Type
Pwr Rail /Tolerance
O CMOS
3.3V / 3.3V
I CMOS
3.3V / 3.3V
Pin Type
Pwr Rail /Tolerance
Module Base Specification R3.0
System Management Bus bidirectional clock line.
System Management Bus bidirectional data line.
System Management Bus Alert – active low input can be used to generate an
SMI# (System Management Interrupt) or to wake the system.
GPIO Signals Descriptions
Signal
GPO0
GPO1
GPO2
GPO3
GPI0
GPI1
GPI2
GPI3
Pin#
A93
B54
B57
B63
A54
A63
A67
A85
COMe SPEC PU/PD
DV970 PU/PD
Module Base Specification R3.0
General purpose output pins. Upon a hardware reset, these outputs should be
low.
PU
PU
PU
PU
47KΩ
47KΩ
47KΩ
47KΩ
to
to
to
to
3.3V
3.3V
3.3V
3.3V
General purpose input pins. Pulled high internally on the Module.
Power and GND Signal Descriptions
Signal
VCC_12V
VCC_5V_SBY
VCC_RTC
GND
Chapter 3 Hardware
Pin#
A104~A109
B104~B109
C104~C109
D104~D109
B84~B87
COMe SPEC PU/PD
Module Base Specification R3.0
Primary power input: +12V nominal. All available VCC_12V pins on the
connector(s) shall be used.
Power
Standby power input: +5.0V nominal. If VCC5_SBY is used, all available
VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and
suspend functions. May be left unconnected if these functions are not used in the
system design.
Real-time clock circuit-power input. Nominally +3.0V.
Power
A47
Power
A1, A11, A21, A31,
A38, A41, A51, A57,
A60, A66, A70, A73,
A76, A79, A80, A83,
A90, A100, A110, B1,
B11, B21 ,B31, B38,
B41, B51, B60, B70,
B73, B76, B79, B80,
B83, B90, B100, B110,
C1, C2, C5, C8, C11,
C14, C18, C21, C25,
C28, C31, C41, C44, Power
C48, C51, C60, C70,
C73, C76, C80, C84,
C87, C90, C93, C96,
C100, C103, C110,
Installation
D1, D2, D5, D8, D11,
DV970 PU/PD
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier Board GND
plane.
25
www.dfi.com
VCC_12V
B104~B109
C104~C109
D104~D109
Power
VCC_5V_SBY
B84~B87
VCC_RTC
A47
Power
A1, A11, A21, A31,
A38, A41, A51, A57,
A60, A66, A70, A73,
A76, A79, A80, A83,
A90, A100, A110, B1,
B11, B21 ,B31, B38,
B41, B51, B60, B70,
B73, B76, B79, B80,
B83, B90, B100, B110,
C1, C2, C5, C8, C11,
C14, C18, C21, C25,
C28, C31, C41, C44, Power
C48, C51, C60, C70,
C73, C76, C80, C84,
C87, C90, C93, C96,
C100, C103, C110,
D1, D2, D5, D8, D11,
D14, D18, D21, D25,
D28, D31, D41, D44,
D48, D51, D60, D67,
D70, D73, D76, D80,
D84, D87, D90, D93,
D96, D100, D103,
D110
GND
Primary power input: +12V nominal. All available VCC_12V pins on the
connector(s) shall be used.
Chapter 3
Standby power input: +5.0V nominal. If VCC5_SBY is used, all available
VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and
suspend functions. May be left unconnected if these functions are not used in the
system design.
Real-time clock circuit-power input. Nominally +3.0V.
Power
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier Board GND
plane.
Module type Signal Descriptions
Signal
TYPE0#
Pin#
C54
Pin Type
Pwr Rail /Tolerance
COMe SPEC PU/PD
DV970 PU/PD (T7)
PD 0Ω to GND
PDS
TYPE1#
C57
PDS
N.C.
TYPE2#
D57
PDS
PD 0Ω to GND
TYPE10#
A97
PDS
N.C.
26
Chapter 3 Hardware Installation
Module Base Specification R3.0
The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented
on the Module. The pins are tied on the Module to either ground (GND) or are
no-connects (NC). For Pin-out Type 1 and Type 10, these pins are not present
(X).
TYPE2#
X
NC
NC
NC
NC
GND
GND
TYPE1#
X
NC
NC
GND
GND
NC
NC
TYPE0#
X
pin out Type 1 (deprecated)
NC
pin out Type 2 (deprecated)
GND
pin out Type 3 (no IDE) (deprecated)
NC
pin out Type 4 (no PCI) (deprecated)
GND
pin out Type 5 (no IDE、PCI) (deprecated)
NC
pin out Type 6 (no IDE, no PCI)
GND
pin out Type 7
*
The Carrier Board should implement combinatorial logic that monitors the Module
TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX
power supply) if an incompatible Module pin out type is detected. The Carrier
Board logic may also implement a fault indicator such as an LED.
Dual use pin. Indicates to the Carrier Board that a Type 10 Module is installed.
Indicates to the Carrier that a Rev 1.0 or a Rev 2.0/3.0 Module is installed.
TYPE10#
NC Pin-out R2.0
PD Pin-out Type 10 pull down to ground with 47K resistor
12V Pin-out R1.0
This pin is reclaimed from the VCC_12V pool. In R1.0 Modules this pin will
connect to other VCC_12V pins. In R2.0 this pin is defined as a no connect for
types 1-6. In R3.0 this pin is defined as a no connect for types 6 and 7. A Carrier
can detect a R1.0 Module by the presence of 12V on this pin. R2.0 Module types
1-6 will no connect this pin. R3.0 Module types 6 and 7 will no connect this pin.
Type 10 Modules shall pull this pin to ground through a 47K resistor.www.dfi.com
GND
GND
Chapter 3
TYPE2#
TYPE10#
D57
A97
PD 0Ω to GND
PDS
PDS
N.C.
NC
NC
NC
GND
pin out Type 6 (no IDE, no PCI)
pin out Type 7
*
The Carrier Board should implement combinatorial logic that monitors the Module
TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX
power supply) if an incompatible Module pin out type is detected. The Carrier
Board logic may also implement a fault indicator such as an LED.
Dual use pin. Indicates to the Carrier Board that a Type 10 Module is installed.
Indicates to the Carrier that a Rev 1.0 or a Rev 2.0/3.0 Module is installed.
TYPE10#
NC Pin-out R2.0
PD Pin-out Type 10 pull down to ground with 47K resistor
12V Pin-out R1.0
This pin is reclaimed from the VCC_12V pool. In R1.0 Modules this pin will
connect to other VCC_12V pins. In R2.0 this pin is defined as a no connect for
types 1-6. In R3.0 this pin is defined as a no connect for types 6 and 7. A Carrier
can detect a R1.0 Module by the presence of 12V on this pin. R2.0 Module types
1-6 will no connect this pin. R3.0 Module types 6 and 7 will no connect this pin.
Type 10 Modules shall pull this pin to ground through a 47K resistor.
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Chapter 3
Standby Power LED
Cooling Option
Heat Sink with Fan
Note:
The system board used in the following illustrations may not resemble the actual
board. These illustrations are for reference only.
Standby
Power LED
This LED will be red when module board has suspend power rail.
Top View of the Heat Sink
1
Bottom View of the Heat Sink
•
“1” denotes the location of the thermal pad designed to contact the corresponding components on DV970.
Important:
Remove the plastic covering from the thermal pads prior to mounting the heat sink
onto DV970.
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Chapter 3
Installing DV970 onto a Carrier Board
2. Apply firm even pressure to the side with the connectors first and push down the entire
board. You will hear a “click”, indicating the module is correctly seated in the COM Express connectors of the carrier board.
Important:
The carrier board used in this section is for reference purpose only and may not
resemble your carrier board. These illustrations are mainly to guide you on how to
install DV970 onto the carrier board of your choice.
1. Grasp DV970 by its edges and position it on top of the carrier board with its mounting
holes aligned with the standoffs on the carrier board. This helps align the COM Express
connectors of the two boards to each other.
Pressing points
COM Express connectors
on DV970
BIOS ROM socket
COM Express connectors on the
carrier board
Note:
The illustrations above show the pressing points of the module onto the carrier board.
Be careful when pressing the module, it may damage the socket.
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Chapter 3
3. Install a heat sink onto the DV970 with the carrier board. First align the mounting holes of
the heat sink with the mounting holes of the module.
4
2
Heat sink
DV970
Carrier board
Side View of the Heat sink, Module, and Carrier Board
5
1
3
Note:
Install the heat sink according to the sequence of the screws shown in the image
above to avoid damage to the CPU.
4. Connect the heat sink and fan’s cable to the fan connector on DV970.
Fan connector
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Chapter 4
Chapter 4 - BIOS Setup
Legends
Overview
The BIOS is a program that takes care of the basic level of communication between the CPU
and peripherals. It contains codes for various advanced features found in this system board.
The BIOS allows you to configure the system and save the configuration in a battery-backed
CMOS so that the data retains even when the power is off. In general, the information stored
in the CMOS RAM of the EEPROM will stay unchanged unless a configuration change has been
made such as a hard drive replaced or a device added.
It is possible that the CMOS battery will fail causing CMOS data loss. If this happens, you need
to install a new CMOS battery and reconfigure the BIOS settings.
Note:
The BIOS is constantly updated to improve the performance of the system board;
therefore the BIOS screens in this chapter may not appear the same as the actual
one. These screens are for reference purpose only.
Default Configuration
Most of the configuration settings are either predefined according to the Load Optimal Defaults
settings which are stored in the BIOS or are automatically detected and configured without
requiring any actions. There are a few settings that you may need to change depending on
your system configuration.
KEYs
Function
F1
Help
<Esc>
Exit
Up and Down Arrows
Select Item
Right and Left Arrows
Select Item
<F5>/<F6>
Change Values
<Enter>
Select 
<F9>
Setup Defaults
<F10>
Save and Exit
Submenu
Scroll Bar
When a scroll bar appears to the right of the setup screen, it indicates that there are more
available fields not shown on the screen. Use the up and down arrow keys to scroll through all
the available fields.
Entering the BIOS Setup Utility
Submenu
The BIOS Setup Utility can only be operated from the keyboard and all commands are keyboard commands. The commands are available on the right side of each setup screen.
When ““ appears on the left of a particular field, it indicates that a submenu which contains
additional options are available for that field. To display the submenu, move the highlight to
that field and press <Enter>.
The BIOS Setup Utility does not require an operating system to run. After you power up the
system, the BIOS message appears on the screen and the memory count begins. After the
memory test, the message “Press DEL to run setup” will appear on the screen. If the message
disappears before you respond, restart the system or press the “Reset” button. You may also
restart the system by pressing the <Ctrl> <Alt> and <Del> keys simultaneously.
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Chapter 4
Insyde BIOS Setup Utility
Advanced
Main
The Advanced menu allows you to configure your system for basic operation. Some entries are
defaults required by the system board, while others, if enabled, will improve the performance
of your system or let you set some features according to your preference.
The Main menu is the first screen that you will see when you enter the BIOS setup utility.
Important:
Setting incorrect field values may cause the system to malfunction.
Main
Advanced
Security
InsydeH20 Setup Utility
Boot
Exit
Rev. 5.0
ACPI Configuration Setting
ACPI Configuration
CPU Configuration
Video Configuration
Audio Configuration
SATA Configuration
USB Configuration
PCI Express Configuration
ME Configuration
MEBX Configuration
 Active Management Technology Supoort
 PC Health Status








F1 Help
Esc Exit
↑/↓ Select Item
←/→ Select Item
F5/F6 Change Values
Enter Select  SubMenu
F9 Setup Defaults
F10 Save and Exit
System Date
The date format is <month>, <date>, <year>. Day displays a day, from Sunday to
Saturday. Month displays the month, from January to December. Date displays the
date, from 1 to 31. Year displays the year, from 1980 to 2099.
System Time
The time format is <hour>, <minute>, <second>. The time is based on the 24-hour
military-time clock. For example, 1 p.m. is 13:00:00. Hour displays hours from 00 to
23. Minute displays minutes from 00 to 59. Second displays seconds from 00 to 59.
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Chapter 4
ACPI Settings
CPU Configuration
This section configures the system’s ACPI settings.
This section configures the CPU.
Wake on LAN
Intel® SpeedStep™
Enable or disable the use of LAN signals to wake up the system.
After G3
Enable or disable the Enhanced Intel® SpeedStep™ Technology, which helps optimize the balance between system’s power consumption and performance. After it is
enabled in the BIOS, you can take advantage of its offering by setting power schemes
from the operating system’s power options.
Specify which state the system should be in when power is re-applied after a power
failure (G3, the mechanical-off, state).
CPU C States
Always On The system is powered on.
Always Off The system is powered off.
Enable or disable CPU power management. It allows the CPU to go to C states when
it’s not 100% utilized.
Wake on RTC
Automatically power the system on at a particular time every day from the real-time clock
battery. Specify the wake up time of the day below: <hour>, <minute>, <second>.
Note:
For some Linux-based operating systems such as Debian, CentOS, Ubuntu,
you may need to set “CPU C States” to “disabled” before installation.
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Chapter 4
Video Configuration
SATA Configuration
This section configures video settings.
This section configures SATA controllers.
Primary Display
SATA Controller(s)
Select the primary display for the system. The options are PCI (the default BMC VGA)
and PEG (PCIe graphics card). The order of video device initialization will be as follows:
Enable or disable Serial ATA devices.
SATA Speed
PCI (default): PCI graphics device -> PCIe graphics device
Select Serial ATA device speed: Gen1 (1.5 Gbit/s), Gen2 (3 Gbit/s), Gen 3 (6 Gbit/s)
or auto.
PEG: PCIe graphics device -> PCI graphics device
SATA3_0, SATA3_1 and Hot Plug
Enable or disable each Serial ATA port and its hot plug function.
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Chapter 4
USB Configuration
PCI Express Configuration
This section configures the parameters of the USB devices.
This section configures the settings of the PCIe root ports.
Legacy USB Support
Disabled
Disable USB keyboard/mouse/storage support.
Enabled
Enable USB keyboard/mouse/storage support under UEFI and DOS environment.
UEFI Only
Enable USB keyboard/mouse/storage support only under UEFI environment.
XHCI Hand-off
Set this option to disabled if the operating system supports xHCI hand-off (i.e. more
recent versions of Windows) and enabled if the operating system does not support
xHCI hand-off (i.e. older versions of Windows).
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Chapter 4
PCIE IP Configuration
PCI Express Root Port Configuration
This section configures PCIe lanes.
This section configures the PCI Express root ports.
Bifurcation PCIE0/PCIE1
PCIe Speed
The PCIE bifurcation method allows you to split a PCIE lane into multiple lanes by
dividing its bandwidth.
Select the speed of the PCI Express Root Port: Auto, Gen1 (2.5 GT/s), Gen2 (5.0 GT/s)
or Gen3 (8.0 GT/s).
The options are as follows for PCIE0 and PCIE1:
Hot Plug
Auto:
P0.....................x8 (the default setting for SKU 100G)
P2,
P0...............x4, x4
P2, P1, P0..............x4, x2, x2
P3, P2,
, P0.........x2, x2, x4
P3, P2, P1, P0.........x2, x2, x2, x2 (the default setting for SKUs 000G/200G/300G)
Enable or disable the hot plug function of each PCI Express root port.
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Chapter 4
Debug Configuration
UEFI Device Manager
This section configures the debug function.
This Device Manager menu is used to configure UEFI network settings when the “Network
Stack” is enabled in the “Dual” or “UEFI” boot mode. Refer to the “Boot” section in this chapter. After this function is selected, the screen will warn you that you are going to exit the BIOS
setup utility.
Dynamic EFI Debug
Enable or disable output of the debugging messages through a serial port. (On
COM333-I carrier board, the designated serial port will be COM1 pin header.)
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Chapter 4
Network Device List
Blink LEDs
The “Device Manager” screen is displayed. And if the “Network Stack” option is enabled
from the “Boot” menu, the “Network Device List” should be shown in the “Device list”.
Select “Network Device List” to view all of the detected network devices. For each
network device, you can select to view and configure its settings. In addition, you can
select either the IPv4 or IPv6 network settings for UEFI network configuration.
Enter the duration (seconds) to blink the Ethernet port’s LED to indicate its presence.
NIC Configuration
This screen configures the Ethernet controller. Select the link speed from the following
options: Auto Negotiated, 10Mbps Half, 10Mbps Full, 100Mbps Half, and 100Mbps Full.
Wake on LAN
Enable or disable the wake-on-LAN function for this network device.
IPv4 Network Configuration
NIC Configuration Menu
This screen configures the IP addressing method (DHCP or static IP). For static IP addressing, configure the following:
Local IP address and subnet mask: Enter the IP address in the IPv4 format:
x . x . x . x (x must be a decimal value between 0 and 255).
Local Gateway: Enter the gateway address in the IPv4 format.
Local DNS (Domain Name System) Servers: Enter DNS (Domain Name System) server
IP addresses in the IPv4 format.
This screen shows hardware information for the Ethernet controllers and configures
their operation.
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Chapter 4
SIO IT8528E
This section configures the parameters of the system’s super I/O chip IT8528E.
IPv6 Network Configuration
If you select to use IPv6 network settings, enter the Interface ID (64 bit).
Policy: Select either automatic or manual. And select "Advanced Configuration" to
configure IPv6 network address manually if the manual option is selected.
New IPv6 address: Enter the IP address in the IPv6 format:
x : x : x : x : x : x : x : x (x can be any hexadecimal value between 0 and FFFF). Place
a space to separate each IP address to enter more than one address.
New Gateway addresses: Enter gateway addresses in the IPv6 format.
New DNS addresses: Enter DNS (Domain Name System) server IP addresses in the
IPv6 format.
COM Port 1 and COM Port 2
Enable or disable each serial port. The screen also shows the base I/O address and
IRQ assignment of each port.
WDT
Enable or disable the watchdog function. A counter will appear if you select to enable
WDT. Input any value between 1 and 255.
SYS Fix Fan Speed Count
Set the fan speed. The range is from 1 (lowest speed)-100% (full speed).
CPU Smart Fan Control
Enable or disable the system or CPU smart fan.
Boundary 1 to Boundary 4
Set the boundary temperatures that determine the operation of the fan with different fan speeds accordingly. For example, when the system or the CPU temperature
reaches boundary temperature 1, the system or CPU fan should be turned on and
operate at the designated speed. The range of the temperature is from 0 to 127oC.
Fan Speed Count 1 to Fan Speed Count 4
Set the fan speed. The range is from 1 (lowest speed)-100% (full speed).
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Chapter 4
PC Health Status
SIO AST2500
This section displays PC health status.
This section configures the parameters of the system’s super I/O chip AST2500.
BMC_UART1
Enable or disable BMC UART1 port.
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Chapter 4
Console Redirection
Console redirection lets you monitor and control the system from a remote station by re-directing the host screen output through a serial port.
Console Serial Redirect
COM 1/COM 2/BMC UART/BMC SOL
Enable or disable the console redirection function. (The default is disabled.) If you
select to enable it, please configure the following parameters for serial communication between the system and a remote station:
Enable or disable console redirection for COM 1, COM 2, BMC UART and BMC serialover-LAN port. If you select to enable it, please choose to use the global setting or
configure the following parameters for serial communication between the system and a
remote station:
Terminal type: VT_100, VT_100+, VT_UTF8, or PC_ANSI.
Baud rate: 115200, 57600, 38400, 19200, 9600, 4800, 2400 or 1200.
Data bits: 8 bits or 7 bits.
Parity: None, Even or Odd.
Stop bits: 1 bit or 2 bits.
Flow control: None, RTS/CTS or XON/XOFF
Terminal type: VT_100, VT_100+, VT_UTF8, or PC_ANSI.
Baud rate: 115200, 57600, 38400, 19200, 9600, 4800, 2400 or 1200.
Data bits: 8 bits or 7 bits.
Parity: None, Even or Odd.
Stop bits: 1 bit or 2 bits.
Flow control: None, RTS/CTS or XON/XOFF
This above settings are global and can be used for all of the designated serial ports
for console redirection.
UseGlobalSetting
Enable this option to use the global setting from previous menu without the need to
configure each port individually for console redirection.
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Chapter 4
H2O IPMI Configuration
BMC Configuration
This section configures Intelligent Platform Management Interface (IPMI) settings.
This section configures BMC (Baseboard Management Controller) settings.
LAN Channel Number
Select the channel number for the onboard BMC: 01 or 02. Channel 01 is designated as
the LAN I210 Port (LAN 1 port on the COM 333-I carrier board) whereas Channel 02 is
designated as the BMC management PORT (MGMT_PORT on COM333-I).
IPMI Support
Enable or disable the support for IPMI. The default is disabled.
The screwn also lists BMC (Baseboard Management Controller) related information such
as firmware version and status.
IPv4 Source
BMC Warmup Time
Select the IP address addressing method for communicating with the BMC. If DHCP
is selected, a DHCP (Dynamic Host Configuration Protocol) server in your network will
automatically assign an available IP address for the system. If Static is selected, you need
to assign a valid IP address as well as the following information manually:
Select the time needed for the BMC to power on and start functioning. The valid range
is from 0 to 240 seconds.
ACPI SPMI Table
IPv4 address and subnet mask: Enter the IP address in the IPv4 format:
x . x . x . x (x must be a decimal value between 0 and 255).
IPv4 Gateway Address: Enter the gateway address in the IPv4 format.
Enable or disable the ACPI SPMI Table for installing IPMI drivers.
Boot Option Support
IPv6 Mode
Enable or disable the display of IPMI options at startup.
Enable or disalbe IPv6 addressing scheme.
BMC Configuration
If you select to use IPv6 network settings, enter the IPv6 prefix length (enter an integer
between 1 and 128; the default is 64 bit).
IPv6 Static address: Enter the IP address in the IPv6 format:
x : x : x : x : x : x : x : x (x can be any hexadecimal value between 0 and FFFF).
IPv6 Gateway addresses: Enter gateway addresses in the IPv6 format.
Configure the BMC functions.
SDR List
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Chapter 4
Security
SDR List
This section lists SDR (Sensor Data Record) information.
This section configures security-related settings.
TPM Availability (optional)
Show or hide TPM availability and its configurations.
TPM Operation
Select one of the supported operation: Enable, Disable, or No Operation.
No Operation: No changes to the current state.
Disable: Disable and deactivate TPM.
Enable: Enable and activate TPM.
Clear TPM
Remove all TPM ownership contents.
Set Supervisor Password
Set the administrative password for entering the BIOS setup utility or upon entering
the power-on self-test (POST) process. The length of the password must be greater
than 1 character and less than or equal to 10 characters.
Power-on Password
If you select to set the supervisor password, this option will be shown. Enable or disable prompt for password at system startup.
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Chapter 4
Boot
POST messages or the OEM logo at startup. Select “Disabled (default)” to display the
POST messages and select Enabled to display the OEM logo.
This section configures boot options.
Boot Device Priority
This section configures legacy or EFI boot order or both depending on the “Boot
Type” selected.
NumLock
Select the power-on state for the Num Lock key: on or off (default).
Boot Type
Select the boot type. The options are Legacy Boot Type, UEFI Boot Type and Dual Boot
Type (default).
EFI Boot Menu
Network Stack
This option is shown only when the boot type is set to Dual or UEFI.
Enable or disable UEFI network stack. It supports the operation of these functions or
software: Windows 8 BitLocker Network Unlock, UEFI IPv4/IPv6 PXE and legacy PXE
option ROM.
If this function is enabled, you can then go to “Advanced”>”UEFI Device Manager” to
configure network settings for network connection under the UEFI environment. The
default is disabled.
PXE Boot Capability (UEFI mode) /PXE Boot to LAN (Legacy mode)
Enable or disable Preboot eXecution Environment (PXE) boot to LAN. In the UEFI or Dual
boot mode, this function can only be enabled if the Network Stack support is enabled.
The default is disabled.
Use + and - keys to rearrange the priority list for boot devices.
Legacy Boot Menu
Normal
For this option, determine the boot order for the devices within each category. Use
the + and - key to arrange the priority of the boot type devices in the list. The first
device in the list has the highest boot priority.
Advance
For this option, determine the boot order for all bootable devices. Use + and - keys
to arrange the priority of the detected boot devices in the list. The first device in the
list has the highest boot priority.
USB Boot
Enable this function to boot from a USB flash drive.
Quiet Boot
Enable or disable the quiet boot function to configure the screen’s display between
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Chapter 4
Exit
This section configures options for exiting the BIOS setup utility.
Exit Saving Changes
Select this field and press <Enter> to exit BIOS setup and save your changes.
Load Optimal Defaults
Select this field and press <Enter> to load the optimal defaults.
Discard Changes
Select this field and press <Enter>to exit the BIOS setup without saving your changes.
Save Setting to file
Select this option to save BIOS configuration settings to a USB drive. The operation will
fail if there aren’t any USB devices detected on the system. The saved configuration
will have the DSF file extension and can be used for restoration.
Restore Setting from file
Select this option to restore BIOS configuration settings from a USB drive. Note that
this option will not be available if there aren’t any USB devices detected on the system.
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Chapter 4
Updating the BIOS
Notice: BIOS SPI ROM
To update the BIOS, you will need the new BIOS file and a flash utility. Please contact technical support or your sales representative for the latest BIOS file and the firmware update utility.
For instructions on how to update BIOS with the flash utility, please see https://www.dfi.com/
Knowledge/Video/31 from the Knowledge Base of the DFI website.
1. The Intel® Server Platform Services (SPS) has already been integrated into this system
board. Due to safety concerns, the BIOS (SPI ROM) chip cannot be removed from this
system board and used on another system board of the same model.
RRead file successfully.
2. The BIOS (SPI ROM) on this system board must be the original equipment from the factory
and cannot be used to replace one which has been utilized on other system boards.
(path= “platform.ini”)
3. If you do not follow the methods above, the Intel® Server Platform Services will not be
updated and will cease to be effective.
Information
Please do not remove the AC power
Notes:
a. You can take advantage of flash tools to update the default configuration of the
BIOS (SPI ROM) to the latest version anytime.
b. When the BIOS IC needs to be replaced, you have to populate it properly onto the
system board after the EEPROM programmer has been burned and follow the
technical personnel's instructions to confirm that the MAC address should be
burned or not.
Insyde H20FFT (Flash Firmware Tool) Version (SEG) 100.00.08.10
Copyright(c) 2012 - 2016, Insyde Software Corp. All Rights Reserved.
Initializing
Current BIOS Model name: DV970
New BIOS Model name: DV970
Current BIOS version: 65.05A
New BIOS version: 65.05A
Updating Block at FFFFF000h
0%
25%
50%
75%
C:\DV970>_
100%
100%
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Chapter 5
Chapter 5 - Supported Software
Intel Chipset Software Installation Utility
The system requires you to install drivers for some devices to operate properly. To download
the latest driver, please go to the DFI Download Center:
The Intel Chipset Software Installation Utility is used for updating Windows® INF files so that the
Intel chipset can be recognized and configured properly in the system.
https://www.dfi.com/downloadcenter
To install the utility, unzip the driver package and click the executable file in the package folder.
Once you are in the "Download Center" page, select your product or type the model name and
click "Search" to find product-related resources such as documentation and drivers.
1. Setup is ready to install
the utility. Click “Next” to
continue.
Drivers are available for the following devices in Windows Server 2012 & 2016:
•
Intel® Chipset Device Software
•
Graphics Driver (optional, ASPEED Graphics Windows WDDM Driver)
•
Intel® LAN Driver
2. Read the license agreement,
then click “Accept” if you accept the terms and conditions.
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Chapter 5
Graphics Drivers (optional)
3. Go through the readme
document for system requirements and installation
tips, then click “Install”.
To install the ASPEED Graphics Windows WDDM Driver, unzip the driver package and click the
executable file in the package folder.
1. The welcome screen appears.
4. Please wait while the installation is in progress.
2. Setup is now ready to
install the graphics driver.
Click “Install” to begin the
installation.
5. Click “Finish” to exit the
installation utility.
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Chapter 5
Intel LAN Drivers
3. Please wait while the installation is in progress.
To install the driver, unzip the driver package and click the executable file in the package folder.
1. Setup is preparing to install
the driver. Click “Install
Drivers and Software” to
continue.
4. Click “Install” to confirm that
you would like to install this
device software.
2. The welcome screen appears to inform you that
Intel® network drivers and
networking services will be
installed.
5. Click “Finish” to exit the
installation utility.
3. Read the license agreement,
then click “Next” if you accept
the terms and conditions.
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Chapter 5
4. Choose the components to
be installed and click “Next”
to begin the installation.
5. After the installation is
complete, click “Finish”.
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