NXP LPC80X Low-Cost Microcontrollers (MCUs) based on Arm® Cortex®-M0 Core Data Sheet

NXP LPC80X Low-Cost Microcontrollers (MCUs) based on Arm® Cortex®-M0  Core Data Sheet

LPC802

32-bit ARM Cortex-M0+ microcontroller; up to 16 KB flash and 2 KB SRAM; 12-bit ADC; Comparator;

Rev. 1.8 — 25 September 2019 Product data sheet

The LPC802 is an ARM Cortex-M0+ based, low-cost 32-bit MCU family of processors operating at CPU frequencies of up to 15 MHz. The LPC802 supports 16 KB of flash memory and 2 KB of SRAM.

The peripheral complement of the LPC802 includes one I 2 C-bus interface, up to two USARTs, one SPI interface, one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one 12-bit ADC, one analog comparator, function-configurable I/O ports through a switch matrix, and up to 17 general-purpose I/O pins.

For additional documentation related to the LPC802 parts, see Section 19 “References”

.

2. Features and benefits

    System:  ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz with single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported.

Memory:  16 KB on-chip EEPROM based flash programming memory.

 Code Read Protection (CRP).  2 KB SRAM.

Dual I/O power (LPC802M011JDH20):  Independent supplies on each package side permitting level-shifting signals from one off-chip voltage domain to another and/or interfacing directly to off-chip peripherals operating at different supply levels.

 The switch matrix provides level shifter functionality to allow up to two selected signals to be routed from user-selected pins in one voltage domain to selected pins in the alternate domain. This feature can also be used on a single supply device if voltage level shifting is not required.

ROM API support:  Boot loader.

 Supports Flash In-Application Programming (IAP).

 Supports In-System Programming (ISP) through USART.

NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

       On-chip ROM APIs for integer divide.

 Free Running Oscillator (FRO) API.

Digital peripherals:  High-speed GPIO interface connected to the ARM Cortex-M0+ I/O bus with up to 17 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter. GPIO direction control supports independent set/clear/toggle of individual bits.

 High-current source output driver (20 mA) on three pins.

 Switch matrix for flexible configuration of each I/O pin function.

 CRC engine.

Timers:  One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, and external count.

 Two channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.

 Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input.

 Windowed Watchdog timer (WWDT).

Analog peripherals:  One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports two independent conversion sequences.  Comparator with four input pins and external or internal reference voltage.

Serial peripherals:  Two USART interfaces with pin functions assigned through the switch matrix and one fractional baud rate generators.  One SPI controller with pin functions assigned through the switch matrix.  One I 2 C-bus interface. Supports Standard mode and Fast mode. Clock generation:  Free Running Oscillator (FRO). This oscillator provides selectable 9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.

 1 MHz low power oscillator can be used as a clock source.

 Clock output function with divider that can reflect all internal clock sources.

Power control:  Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode.

 Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and I 2 C peripherals.

 Wake-up from deep power-down mode on multiple pins.

 Timer-controlled self wake-up from sleep, deep-sleep, and power-down modes.

 Power-On Reset (POR).

 Brownout detect (BOD).

LPC802

Product data sheet

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Rev. 1.8 — 25 September 2019

© NXP Semiconductors B.V. 2019. All rights reserved.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

    Unique device serial number for identification.

Single or dual power supplies (1.71 V to 3.6 V).

Operating temperature range -40 °C to +105 °C.

Available in WLCSP16, TSSOP16, TSSOP20, and HVQFN33 packages.

3. Applications

      Sensor gateways Industrial Gaming controllers 8/16-bit applications Consumer Climate control      Simple motor control Portables and wearables Lighting Motor control Fire and security applications

Table 1.

Ordering information Type number Package Name

LPC802M001JDH16 TSSOP16 LPC802M001JDH20 LPC802M011JDH20 LPC802M001JHI33 TSSOP20 TSSOP20 HVQFN33 LPC802UK WLCSP16

Description

plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm wafer level chip-size package; 16 (4  4) bumps; 1.86  1.86  0.3 mm

Version

SOT403-1 SOT360-1 SOT360-1 n/a SOT1393-2

4.1 Ordering options Table 2.

Type number Ordering options

LPC802M001JDH16 16 LPC802M001JDH20 LPC802M011JDH20 16 16 LPC802M001JHI33 LPC802UK 16 16 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 13 17 16 17 13 yes TSSOP16 TSSOP20 TSSOP20 HVQFN33 WLCSP16 LPC802

Product data sheet

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NXP Semiconductors

5. Marking

20

LPC802 32-bit ARM Cortex-M0+ microcontroller

Terminal 1 index area Terminal 1 index area

Fig 1.

1

aaa-014766

TSSOP20 and TSSOP16 package markings Fig 2.

Terminal 1 index area

HVQFN33 package marking

aaa-014382

LPC802

Product data sheet

aaa-015675

Fig 3.

WLCSP16 package marking

The LPC802 HVQFN33 packages have the following top-side marking:

• • • – –

First line: LPC802M0 Second line: xxxx Third line: yywwx[R] yyww: Date code with yy = year and ww = week.

xR = Boot code version and device revision.

The LPC802 TSSOP20 packages typically have the following top-side marking:

• • • • – –

First line: LPC802 Second line: M0y1

y: 0 or 1 Third line: xxxx Fourth line: xxywwx[R] yww: Date code with y = year and ww = week.

xR = Boot code version and device revision.

All information provided in this document is subject to legal disclaimers.

Rev. 1.8 — 25 September 2019

© NXP Semiconductors B.V. 2019. All rights reserved.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

The LPC802 TSSOP16 packages have the following top-side marking:

• • • • – –

First line: LPC802 Second line: M001J Third line: xxxx Fourth line: ywwx[R] yww: Date code with y = year and ww = week.

xR = Boot code version and device revision.

The LPC802 WLCSP16 packages have the following top-side marking:

• • • •

First line: LPC802 Second line: xxxxx Third line: xyywwx[R]

– –

yyww: Date code with ww = week and yy = year.

xR = Boot code version and device revision.

Fourth line: xxx - yyy

Table 3.

Revision identifier (R) Device revision table

0A 1A 1B 1C (TSSOP16 only) 1D

Revision description

Initial device revision with Boot ROM version 13.0

Second device revision with Boot ROM version 13.1

Third device revision with Boot ROM version 13.1

Fourth device revision with Boot ROM version 13.1

Fifth device revision with Boot ROM version 13.1

LPC802

Product data sheet

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Rev. 1.8 — 25 September 2019

© NXP Semiconductors B.V. 2019. All rights reserved.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

GPIOs GPIOs AND GPOINT IOP bus DEBUG INTERFACE ARM Cortex M0+ T0 Match/ Capture COMP Inputs ADC inputs and Triggers GPIOs ISP Access Port Multilayer AHB Matrix M0 P0 P1 P2 Flash interface Boot ROM 8 kB SRAM 2 kB CLKIN RESET Clock Generation, Power Control, and other System Functions Voltage Regulator CLKOUT Vdd Flash 16 kB

APB slave group

System control IOCON Registers CTIMER0 Periph Input Mux Selects Comparator PMU Registers 12-bit ADC Switch Matrix Wakeup Timer Multi-Rate Timer LPOSc Windowed WDT AHB to APB bridge UART 0 and 1 SPI0 I2C 0 UART0,1 SPI0 I2C0

aaa-028309

Fig 4.

LPC802 block diagram

LPC802

Product data sheet

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 7.1 Pinning Fig 5.

PIO0_16/ADC_3/ACMP_I4 PIO0_17/ADC_9 PIO0_13/ADC_10 PIO0_12 RESET/PIO0_5 PIO0_4/ADC_11/TRST SWCLK/PIO0_3/TCK SWDIO/PIO0_2/TMS PIO0_11/ADC_6/WKTCLKIN PIO0_10/ADC_7 9 10 1 2 3 4 5 6 7 8

TSSOP20

aaa-026614

20 19 PIO0_14/ADC_2/ACMP_I3 PIO0_0/ACMP_I1/TDO 18 VREFP 17 16 15 14 13 12 11 PIO0_7/ADC_1/ACMPV REF V SS V DD PIO0_8/ADC_5 PIO0_9/ADC_4 PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI PIO0_15/ADC_8

Pin configuration TSSOP20 - 1 package (LPC802M001JDH20 - single supply device) Fig 6.

PIO0_16/ADC_3/ACMP_I4 VDD IO PIO0_13/ADC_10 PIO0_12 RESET/PIO0_5 PIO0_4/ADC_11/TRST SWCLK/PIO0_3/TCK SWDIO/PIO0_2/TMS PIO0_11/ADC_6/WKTCLKIN PIO0_10/ADC_7 9 10 5 6 7 8 1 2 3 4

TSSOP20

aaa-026615

14 13 12 11 18 17 16 15 20 19 PIO0_14/ADC_2/ACMP_I3 PIO0_0/ACMP_I1/TDO VREFP PIO0_7/ADC_1/ACMPV REF V SS V DD PIO0_8/ADC_5 PIO0_9/ADC_4 PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI PIO0_15/ADC_8

Pin configuration TSSOP20 - 2 package with VDDIO (LPC802M011JDH20 - dual supply device)

LPC802

Product data sheet

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

PIO0_17/ADC_9 PIO0_13/ADC10 PIO0_12 RESET/PIO0_5 PIO0_4/ADC_11/nTRST PIO0_3/SWCLK/TCK PIO0_2/SWDIO/TMS PIO0_11/ADC_6/WKTCLKIN 1 2 3 4 5 6 7 8

TSSOP16

aaa-026619

12 11 10 9 16 15 14 13 PIO0_0/ACMP_I1/TDO VREFP PIO0_7/ADC_1/ACMPV REF V SS V DD PIO0_8/ADC_5 PIO0_9/ADC_4 PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI

Fig 7.

Pin configuration TSSOP16 package

terminal 1 index area PIO0_17/ADC_9 PIO0_13/ADC_10 PIO0_12 RESET/PIO0_5 PIO0_4/ADC_11/TRSTN SWCLK/PIO0_3/TCK SWDIO/PIO0_2/TMS PIO0_11/ADC_6/WKTCLKIN 5 6 7 8 1 2 3 4 33 V SS 20 19 18 17 24 23 22 21 PIO0_0/ACMP_I1/TDO VREFP PIO0_7/ADC_1/ACMPV REF n.c.

VDD PIO0_8/ADC_5 PIO0_9/ADC_4 PIO0_1/ADC_0/ACMP_I2/TDI/CLKIN

aaa-026616

Fig 8.

Pin configuration HVQFN33 package

Transparent top view LPC802

Product data sheet

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description

Table 4

shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable through the switch matrix between GPIO and the comparator, ADC, SWD, and RESET pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only.

Movable functions for the I2C, USART, SPI, CTimer pins and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions.

The following exceptions apply: Do not assign more than one output to any pin. However, an output and/or one or more inputs can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled.

Eight GPIO pins trigger a wake-up from deep power-down mode. If the part must wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. The GPIO pins should be pulled HIGH externally before entering deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit deep power-down mode and wakes up the part.

The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode.

PIO0_2, PIO0_3, and PIO0_12 are the high drive output pins. PIO0_4, PIO0_8, PIO0_9, PIO0_10, PIO0_11, PIO0_13, PIO0_15, and PIO0_17 are the WAKEUP pins.

LPC802

Product data sheet

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Rev. 1.8 — 25 September 2019

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 4.

Symbol Pin description Reset state

[1]

Type Description

PIO0_0/ ACMP_I1/TDO PIO0_1/ADC_0/ ACMP_I2/CLKIN/TDI/ SWDIO/PIO0_2/ TMS SWCLK/PIO0_3/ TCK PIO0_4/ADC_11/ TRSTN RESET/PIO0_5 PIO0_7/ADC_1/ ACMPV REF 19 12 8 7 6 5 17 19 16 24 12 9 17 8 7 6 5 7 6 5 4 7 6 5 4 17 14 22 D3 A4 A2 B1

[3]

I; PU I I/O B2 C2 C3

[2] [2] [3] [2] [4][5] [2]

I; PU I; PU I; PU I; PU I; PU I; PU I I IO A IO A IO IO IO A IO IO A

PIO0_0 —

General-purpose port 0 input/output 0.

In ISP mode, this is the U0_RXD pin (for single supply devices).

In boundary scan mode: TDO (Test Data Out).

ACMP_I1 —

Analog comparator input 1.

PIO0_1 —

General-purpose port 0 input/output 1.

In boundary scan mode: TDI (Test Data In).

ACMP_I2 —

Analog comparator input 2.

CLKIN —

External clock input.

SWDIO —

Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select).

PIO0_2 —

General-purpose port 0 input/output 2.

SWCLK —

Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock).

PIO0_3 —

General-purpose port 0 input/output 3.

PIO0_4 —

General-purpose port 0 input/output 4. In ISP mode, this pin is the U0_TXD pin (for single supply devices).

In boundary scan mode: TRST (Test Reset).

ADC_11 —

ADC input 11.

RESET —

External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed.

PIO0_5 —

General-purpose port 0 input/output 5.

PIO0_7 —

General-purpose port 0 input/output 7.

ADC_1 —

ADC input 1.

ACMPV REF —

Alternate reference voltage for the analog comparator.

LPC802

Product data sheet

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 4.

Symbol Pin description Reset state [1] Type Description

PIO0_8/ADC_5 PIO0_9/ADC_4 PIO0_10/ADC_7 PIO0_11/ADC_6/ WKTCLKIN PIO0_12 PIO0_13/ADC_10 PIO0_14/ ACMP_I3/ADC_2 PIO0_15/ADC8 PIO0_16/ ACMP_I4/ADC_3 PIO0_17/ADC_9 LPC802

Product data sheet

14 13 10 9 4 3 20 11 1 2 14 11 19 13 10 9 4 3 20 11 1 10 8 3 2 1 18 9 8 3 2 25 16 32 1 B3 A3

[2]

A1 D1

[2] [2] [6] [2]

I; PU I; PU I; PU I; PU -

[2]

I; PU I; PU I IO A IO A IO A IO A C1

[3]

I; PU IO D2

[2]

I; PU -

[2]

I; PU -

[2]

I; PU A A IO IO A IO IO IO A

PIO0_8 —

General-purpose port 0 input/output 8. In ISP mode, this is the U0_RXD pin (for dual supply devices).

ADC_5 —

ADC input 5.

PIO0_9 —

General-purpose port 0 input/output 9. In ISP mode, this is the U0_TXD pin (for dual supply devices)

ADC_4 —

ADC input 4.

PIO0_10 —

General-purpose port 0 input/output 10.

ADC_7 —

ADC input 7.

PIO0_11 —

General-purpose port 0 input/output 11.

ADC_6 —

ADC input 6.

WKTCKLKIN —

This pin can host an external clock for the self-wake-up timer. To use the pin as a self-wake-up timer clock input, select the external clock in the wake-up timer CTRL register. The external clock input is active in sleep, deep-sleep, and power-down modes.

PIO0_12 —

handler.

General-purpose port 0 input/output 12. ISP entry pin. A LOW level on this pin during reset starts the ISP command

PIO0_13 —

General-purpose port 0 input/output 13.

ADC_10 —

ADC input 10.

PIO0_14 —

General-purpose port 0 input/output 14.

ACMP_I3 —

Analog comparator common input 3.

ADC_2 —

ADC input 2.

PIO0_15 —

General-purpose port 0 input/output 15.

ADC_8 —

ADC input 8.

PIO0_16 —

General-purpose port 0 input/output 16.

ACMP_I4 —

Analog comparator common input 4.

ADC_3 —

ADC input 3.

PIO0_17 —

General-purpose port 0 input/output 17.

ADC_9 —

ADC input 9.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 4.

Symbol Pin description Reset state [1] Type Description

V VDD V DD SS IO VREFP 15 16 18 15 2 16 18 12 13 15 20 33 23

[8]

B4 C4 D4 A If VDDIO is present, VDD is the supply voltage for the I/Os on the right side of the package and the core voltage regulator. If VDDIO is not present, VDD also supplies voltage to the I/Os on the left side of the package.

If present, it is the supply voltage for the I/Os on the left side of the package. Ground.

VREFP —

ADC positive reference voltage. Must be equal or lower than V DD .

no connect.

n.c.

10, 11, 12, 13, 14, 15, 21, 26, 27, 28, 29, 30, 31 [1] [2] [3] [4] [5] [6] [7] [8] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V DD level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see

Section 15.5 “Pin states in different power modes” . For termination on unused pins, see Section 15.4 “Termination of unused pins” .

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

See Figure 16

for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is not available in deep power-down mode. Use the WAKEUP pins to reset the chip and wake up from deep power-down mode.

The WKTCLKIN function is enabled in the PINENABLE0 register in the PMU. See the LPC802 user manual.

The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled.

Thermal pad for HVQFN33.

LPC802

Product data sheet

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

Movable functions for the I2C, USART, SPI, CTimer pins and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the fixed functions of the pin.

Table 5.

Movable functions (assign to pins PIO0_0 to PIO0_5, PIO0_7 to PIO0_17 through switch matrix) Function name

Ux_TXD

Type Description

O Transmitter output for USART0 to USART1. Ux_RXD Ux_RTS Ux_CTS Ux_SCLK I I O I/O Receiver input for USART0 to USART1. Request To Send output for USART0. Clear To Send input for USART0. Serial clock input/output for USART0 to USART1 in synchronous mode.

SPIx_SCK SPIx_MOSI SPIx_MISO SPIx_SSEL0 SPIx_SSEL1 I2Cx_SDA I2Cx_SCL ACMP_O I/O I/O I/O I/O I/O I/O I/O O Serial clock for SPI0.

Master Out Slave In for SPI0.

Master In Slave Out for SPI0.

Slave select 0 for SPI0.

Slave select 1 for SPI0.

I 2 C0 bus data input/output.

I 2 C0 bus clock input/output.

Analog comparator output.

CLKOUT O GPIO_INT_BMAT O T0_MAT0 T0_MAT1 O O T0_MAT2 T0_MAT3 T0_CAP0 T0_CAP1 I I O O T0_CAP2 LVLSHFT_IN0 LVLSHFT_IN1 LVLSHFT_OUT0 LVLSHFT_OUT1 I I I O O Clock output.

Output of the pattern match engine.

Timer Match channel 0.

Timer Match channel 1.

Timer Match channel 2.

Timer Match channel 3.

Timer Capture channel 0. Timer Capture channel 1. Timer Capture channel 2.

Level shift input 0.

Level shift input 1.

Level shift output 0.

Level shift output 1.

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 15 MHz using a two-stage pipeline. The core revision is r0p1.

Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer.

9.2 On-chip flash program memory

The LPC802 contain up to 16 KB of on-chip EEPROM based flash program memory.

9.3 On-chip SRAM

The LPC802 contain a total of 2 KB on-chip static RAM data memory.

9.4 On-chip ROM

The on-chip ROM contains the bootloader:

• • • • •

Boot loader.

Supports Flash In-Application Programming (IAP).

Supports In-System Programming (ISP) through USART.

On-chip ROM APIs for integer divide.

Free Running Oscillator (FRO) API.

9.5 Memory map

The LPC802 incorporates several distinct memory regions. interrupt vector area supports address remapping.

Figure 9 shows the overall

map of the entire address space from the user program viewpoint following reset. The The ARM private peripheral bus includes the ARM core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes.

LPC802

Product data sheet

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NXP Semiconductors Memory space

(reserved) private peripheral bus (reserved) GPIO interrupts GPIO (reserved) AHB peripherals (reserved) APB peripherals (reserved) RAM (reserved) Boot ROM (reserved) Flash memory (up to 16 KB) 0xFFFF FFFF 0xE010 0000 0xE000 0000 0xA000 8000 0xA000 4000 0xA000 0000 0x5001 4000 0x5000 0000 0x4008 0000 0x4000 0000 0x1000 0800 0x1000 0000 0x0F00 2000 0x0F00 0000 0x0000 4000 0x0000 0000 active interrupt vectors 0x0000 00C0 0x0000 0000

LPC802 32-bit ARM Cortex-M0+ microcontroller AHB perpherals

(reserved) CRC engine 0x5001 4000 0x5000 4000 0x5000 0000 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 31-30 29 28 27 26 25 24

APB perpherals

(reserved) (reserved) (reserved) (reserved) USART1 USART0 (reserved) (reserved) SPI (reserved) I2C (reserved) Syscon IOCON (reserved) (reserved) CTIMER 0 (reserved) (reserved) (reserved) (reserved) Analog Comparator PMU ADC (reserved) (reserved) (reserved) Switch Matrix Wake-up Timer Multi-Rate Timer Watchdog timer 0x4007 FFFF 0x4007 8000 0x4007 4000 0x4007 0000 0x4006 C000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 C000 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000

aaa-027121

Fig 9.

LPC802 Memory mapping

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

9.6.1 Features • • • • • • • •

Nested Vectored Interrupt Controller is a part of the ARM Cortex-M0+.

Tightly coupled interrupt controller provides low interrupt latency.

Controls system exceptions and peripheral interrupts.

Supports 32 vectored interrupts.

In the LPC802, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts. Four programmable interrupt priority levels with hardware priority level masking.

Software interrupt generation using the ARM exceptions SVCall and PendSV.

Supports NMI.

9.6.2 Interrupt sources

Each peripheral device has at least one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source.

9.7 System tick timer

The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

9.8 I/O configuration

The IOCON block controls the configuration of the I/O pins. Each digital or mixed digital/analog pin with the PIO0_n designator in

Table 4

can be configured as follows:

• • • • • • •

Enable or disable the weak internal pull-up and pull-down resistors.

Select a pseudo open-drain mode. The input cannot be pulled up above V DD . The pins are not 5 V tolerant when V DD is grounded.

Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see

Figure 12 “LPC802 clock generation”

). You can also bypass the glitch filter.

Invert the input signal.

Hysteresis can be enabled or disabled.

The switch matrix setting enables the analog input mode on pins with analog and digital functions. Enabling the analog mode disconnects the digital functionality.

The LPC802 uses a dual voltage I/O feature. The pins on one side of the package are supplied by VDDIO and the pins on the other side are supplied by VDD. Each of these two supplies can be connected to different voltages within the allowed Vdd range. This feature allows the device to level-shift signals from one off-chip voltage domain to another. LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller •

The switch matrix provides level shifter functionality to allow up to two selected signals to be routed from user-selected pins in one voltage domain to selected pins in the alternate domain. This feature can also be used on a single supply device if voltage level shifting is not required.

Remark:

The functionality of each I/O pin is flexible and is determined entirely through the switch matrix. See

Section 9.9

for details.

9.8.1 Standard I/O pad configuration

Figure 10

shows the possible pin modes for standard I/O pins with analog input function:

• • • • • •

Digital output driver with configurable open-drain output.

Digital input: Weak pull-up resistor (PMOS device) enabled/disabled.

Digital input: Weak pull-down resistor (NMOS device) enabled/disabled.

Digital input: Repeater mode enabled/disabled.

Digital input: Programmable input digital filter selectable on all pins.

Analog input: Selected through the switch matrix.

V DD V DD open-drain enable output enable data output pin configured as digital output driver strong pull-up strong pull-down ESD ESD PIN V SS V DD repeater mode enable pull-up enable weak pull-up weak pull-down pull-down enable data input pin configured as digital input select data inverter SWM PINENABLE for analog input analog input pin configured as analog input

Fig 10. Standard I/O pad configuration

transmission gate LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.9 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, CTimer, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in

Table 5 .

Functions that need specialized pads can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in

Section 7.2 “Pin description”

. If a fixed-pin function is disabled, any other movable function can be assigned to this pin.

9.10 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.

LPC802 use accelerated GPIO functions:

• • •

GPIO registers are on the ARM Cortex-M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 7 MHz.

An entire port value can be written in one instruction.

Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

9.10.1 Features • • • • • •

Bit level port registers allow a single instruction to set and clear any number of bits in one write operation.

Direction control of individual bits.

All I/O default to GPIO inputs with internal pull-up resistors enabled after reset.

Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 10

).

Direction (input/output) can be set and cleared individually.

Pin direction bits can be toggled.

9.11 Pin interrupt

The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt. The registers that control the pin interrupt are on the IO+ bus for fast single-cycle access.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.11.1 Features • – –

Pin interrupts

Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC.

Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

Level-sensitive interrupt pins can be HIGH- or LOW-active.

Pin interrupts can wake up the LPC802 from sleep mode, deep-sleep mode, and power-down mode.

9.12 USART0/1

All USART functions are movable functions and are assigned to pins through the switch matrix.

9.12.1 Features • • • • • • • • • • • • • • •

Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins.

7, 8, or 9 data bits and 1 or 2 stop bits.

Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) Parity generation and checking: odd, even, or none.

One transmit and one receive data buffer.

RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. Received data and status can optionally be read from a single register.

Break generation and detection.

Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

Built-in Baud Rate Generator.

A fractional rate divider is shared among all UARTs.

Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected.

Separate data and flow control loopback modes for testing.

Baud rate clock can also be output in asynchronous mode.

9.13 SPI0

All SPI functions are movable functions and are assigned to pins through the switch matrix.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.13.1 Features • • • • • •

Maximum data rates of up to 15 Mbit/s in master mode and up to 18 Mbit/s in slave mode for SPI functions connected to all digital pins.

Data frames of 1 to 16 bits supported directly. Larger frames supported by software. Master and slave operation.

Data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an SPI memory.

Control information can optionally be written along with data, which allows very versatile operation, including “any length” frames.

One Slave Select input/output with selectable polarity and flexible usage.

Remark:

Texas Instruments SSI and National Microwire modes are not supported.

9.14 I2C-bus interface (I2C0)

The I 2 C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2 C is a multi-master bus and can be controlled by more than one bus master.

9.14.1 Features • • • • • • •

I2C0 supports standard and fast mode with data rates of up to 400 kbit/s.

Independent Master, Slave, and Monitor functions.

Supports both Multi-master and Multi-master with Slave functions.

Multiple I 2 C slave addresses supported in hardware.

One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I 2 C bus addresses.

10-bit addressing supported with software assist.

Supports SMBus.

9.15 CTimer 9.15.1 General-purpose 32-bit timers/external event counter

The LPC802 has one general-purpose 32-bit timer/counter.

The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The timer/counter also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.15.1.1 Features • • • • • • • – –

A 32-bit timer/counter with a programmable 32-bit prescaler.

Counter or timer operation.

Up to three 32-bit captures can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. The number of capture inputs for each timer that are actually available on device pins can vary by device.

Four 32-bit match registers that allow: Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

– – – –

Reset timer on match with optional interrupt generation.

Shadow registers are added for glitch-free PWM output.

For each timer, up to 4 external outputs corresponding to match registers with the following capabilities (the number of match outputs for each timer that are actually available on device pins can vary by device):

Set LOW on match.

Set HIGH on match.

Toggle on match.

Do nothing on match.

The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.

Up to 4 match registers can be configured for PWM operation, allowing up to 3 single edged controlled PWM outputs. (The number of match outputs for each timer that are actually available on device pins can vary by device.)

9.16 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with two channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels.

9.16.1 Features • • •

31-bit interrupt timer Two channels independently counting down from individually set values Bus stall, repeat and one-shot interrupt modes

9.17 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to service the watchdog timer periodically within a programmable time window.

9.17.1 Features •

Internally resets chip if not periodically reloaded during the programmable time-out period.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller • • • • • • • •

Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable.

Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.

Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

Incorrect feed sequence causes reset or interrupt if enabled.

Flag to indicate watchdog reset.

Programmable 24-bit timer with internal prescaler.

Selectable time period from (T cy(WDCLK)  256  4) to (T cy(WDCLK)  2 24  4) in multiples of T cy(WDCLK)  4.

The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator (WDOSC).

9.18 Self-Wake-up Timer (WKT)

The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is used as a wake-up timer, this write can occur prior to entering a reduced power mode.

9.18.1 Features • • •

32-bit loadable down counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request.

The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the low-power oscillator, and the FRO. The low-power oscillator can be used as the clock source in sleep, deep-sleep, and power-down modes. The WKT can be used for waking up the part from any reduced power mode or for general-purpose timing.

9.19 Analog comparator (ACMP)

The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages. After power-up and after switching the input channels of the comparator, the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. Settling times are given in

Table 27 .

The analog comparator output is a movable function and is assigned to a pin through the switch matrix. The comparator inputs and the voltage reference are enabled through the switch matrix.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

ext. VDDCMP V DD LADREF LADEN and nACOMP_PD 1 0 31 voltage ladder out 0 COMP_VP_SEL LADSEL 0 buf COMSTAT ACOMP_PD ACMP_I1 ACMP_I2 ACMP_I3 ACMP_I4 VSS internal bandgap reference voltage VSS 7 0 7 HYS buf n.c.

0 SYNC D Q D Q 1 COMPSA to ACMP_O CONTROL / STATUS REGISTER BITS COMP_VM_SEL EDGESEL ACOMP_RST_N S Q R 2 of 3 sampling edge detect EDGECLR or ACOMP_RST_N COMPEDGE (to INTERRUPT)

aaa-028402

Fig 11. Comparator block diagram 9.19.1 Features • • • • • • • • •

Selectable 0 mV, 10 mV (  5 mV), and 20 mV (  10 mV), 40 mV (  20 mV) input hysteresis.

Two selectable external voltages (V DD or ACMPV REF ); fully configurable on either positive or negative input channel.

Internal voltage reference from band gap selectable on either positive or negative input channel.

32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail.

Voltage ladder can be separately powered down for applications only requiring the comparator function.

Interrupt output is connected to NVIC.

Comparator level output is connected to output pin ACMP_O.

One comparator output is internally collected to the ADC trigger input multiplexer.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.20 Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12 bit and fast conversion rates of up to 480 KSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible trigger sources are the pin triggers, the analog comparator output, and the ARM TXEV.

The ADC includes a hardware threshold compare function with zero-crossing detection.

Remark:

For best performance, select VREFP and VREFN at the same voltage levels as V DD and V SS . When selecting VREFP and VREFN different from VDD and VSS, ensure that the voltage midpoints are the same: (VREFP-VREFN)/2 + VREFN = V DD /2

9.20.1 Features • • • • • • •

12-bit successive approximation analog to digital converter.

12-bit conversion rate of up to 480 KSamples/s.

Two configurable conversion sequences with independent triggers.

Optional automatic high/low threshold comparison and zero-crossing detection.

Power-down mode and low-power operating mode.

Measurement range VREFN to VREFP (not to exceed V DD voltage level). Burst conversion mode for single or multiple inputs.

9.21 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers.

9.21.1 Features • • • • • – –

Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

CRC-CCITT: x 16 + x 12 + x 5 + 1 CRC-16: x 16 + x 15 + x 2 + 1 CRC-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 Bit order reverse and 1’s complement programmable setting for input data and CRC sum.

Programmable seed number setting.

Supports CPU PIO or DMA back-to-back transfer.

– –

Accept any size of data width per write: 8, 16 or 32-bit.

8-bit write: 1-cycle operation.

16-bit write: 2-cycle operation (8-bit x 2-cycle).

32-bit write: 4-cycle operation (8-bit x 4-cycle).

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NXP Semiconductors 9.22 Clocking and power control LPC802 32-bit ARM Cortex-M0+ microcontroller

fro clk_in lposc_clk fro_div 00 01 10 11 (1) Main clock select MAINCLKSEL[1:0] main_clk fro main_clk “none” clk_in lposc_clk “none” 000 001 010 011 100 111 CLKOUT Divider CLKOUTDIV CLKOUT CLKOUT select CLKOUTSEL[2:0] (1) : synchronized multiplexer, see register desriptions for details.

Fig 12. LPC802 clock generation

SYSAHBCLKCTRL (one bit per destination) to AHB peripherals, AHB matrix, memories, etc.

main_clk Divider to CPU SYSAHBCLKDIV fro clk_in “none” 00 01 11 ADC Clock Divider ADC clock select ADCCLKSEL[1:0] ADCCLKDIV to ADC

aaa-027119

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NXP Semiconductors

fro main_clk “none” 00 01 11 Fractional Rate Divider 0 (FRG0) FRG0 clock select FRG0CLKSEL[1:0] FRG0DIV, FRG0MULT

Fig 13. LPC802 clock generation (continued) LPC802 32-bit ARM Cortex-M0+ microcontroller

One for each USART (USART0 and USART1) fro main_clk frg0clk fro_div “none” 000 001 010 100 111 UARTn clock select UARTnCLKSEL[2:0] to USARTn fro main_clk frg0clk fro_div “none” 000 001 010 100 111 I2C clock select I2CCLKSEL[2:0] fro main_clk frg0clk fro_div “none” 000 001 010 100 111 SPl clock select SPICLKSEL[2:0] to I2C to SPI

aaa-027120

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller SYSCON

system clock SYSAHBCLKCTRL (WKT clock enable) FRO PDRUNCFG (enable FRO and FRO output FRO_PD, FROOUT_PD) 12 MHz

WKT

div 750 kHz 1 MHz CTRL CLKSEL SET_EXTCLK 32-bit counter COUNT LPOSC PDRUNCFG WKTCLKIN

Fig 14. LPC802 WKT clocking

aaa-028308

fro FRO OSCILLATOR set_fro_frequency() API 30/24/18 MHz (default = 24 MHz) Divide by 2 15/12/9 MHz (default = 12 MHz) Divide by 2 fro_div

aaa-028307

Fig 15. LPC802 FRO subsystem Table 6.

Name

clk_in frg_clk fro_div fro

Clocking diagram signal name descriptions Description

The internal clock that comes from the main CLK_IN pin function. That function must be connected to the pin by selecting it in the SWM block.

The output of the Fractional Rate Generator. The FRG and its source selection are shown in

Figure 13

.

Divided output of the currently selected on-chip FRO oscillator. See

Figure 15 .

The output of the currently selected on-chip FRO oscillator. See Figure 15

.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 6.

Name

main_clk “none” lposc_clk

Clocking diagram signal name descriptions Description

The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source selection are shown in

Figure 12 .

A tied-off source that should be selected to save power when the output of the related multiplexer is not used.

The output of the 1 MHz low power oscillator. It must also be enabled in the PDRUNCFG0 register.

9.22.1 Internal oscillators

The LPC802 include two independent oscillators: 1. Free Running Oscillator. 2. Low power oscillator.

Following reset, the LPC802 operates from the FRO until switched by software allowing the part to run without any external clock and the bootloader code to operate at a known frequency. See

Figure 12 for an overview of the LPC802 clock generation.

9.22.1.1 Free Running Oscillator (FRO)

The FRO provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage.

• • •

This oscillator provides a selectable 15 MHz, 12 MHz, and 9 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 7.5 MHz, 6 MHz, and 4.5 MHz for system clock.

The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.

By default, the FRO output frequency is default system (CPU) clock frequency of 12 MHz.

9.22.1.2 Low Power Oscillator (LPOsc)

The LPOsc is an independent oscillator which can be used as a system clock. The frequency of the LPCOsc is 1 MHz.

9.22.2 Clock input

An external clock source can be supplied on the selected CLKIN pin. When selecting a clock signal for the CLKIN pin, follow the specifications for digital I/O pins in

Table 12 “Static characteristics, supply pins” and

Table 18 “Dynamic characteristics: I/O pins [1] ” .

The maximum frequency for both clock signals is 15 MHz.

9.22.3 Clock output

The LPC802 features a clock output function that routes any oscillator or the main clock can be selected to the CLKOUT function. The CLKOUT function can be connected to any digital pin through the switch matrix.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.22.4 Power control

The LPC802 supports the ARM Cortex-M0+ sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control.

9.22.4.1 Sleep mode

When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep mode does not need any special sequence but re-enabling the clock to the ARM core.

In sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

9.22.4.2 Deep-sleep mode

In deep-sleep mode, the LPC802 core is in sleep mode and all peripheral clocks and all clock sources are off except for the FRO or low-power oscillator if selected. The FRO output is disabled. In addition, all analog blocks are shut down and the flash is in standby mode. In deep-sleep mode, the application can keep the low power oscillator and the BOD circuit running for self-timed wakeup and BOD protection. The LPC802 can wake up from deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode), or the I2C blocks (in slave mode).

Any interrupt used for waking up from deep-sleep mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

9.22.4.3 Power-down mode

In power-down mode, the LPC802 is in sleep mode and all peripheral clocks and all clock sources are off except for low-power oscillator if selected. In addition, all analog blocks and the flash are shut down. In power-down mode, the application can keep the low-power oscillator and the BOD circuit running for self-timed wake up and BOD protection. The LPC802 can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode), or the I2C blocks (in slave mode).

Any interrupt used for waking up from power-down mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

Power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times.

9.22.4.4 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the WAKEUP pins. The LPC802 can wake up from deep power-down mode via eight WAKEUP pins. See

Section 9.18 “Self-Wake-up Timer (WKT)” . Five general-purpose registers are

available to store information during deep power-down mode.

The LPC802 can be prevented from entering deep power-down mode by setting a lock bit in the PMU block. Locking out deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times.

When entering deep power-down mode, an external pull-up resistor is required on the WAKEUP pins to hold it HIGH.

Table 7.

Peripheral Peripheral configuration in reduced power modes Sleep mode Deep-sleep mode

FRO FRO output Flash software configurable software configurable software configurable BOD LPOsc/WWDT software configurable software configurable Digital peripherals software configurable Wake-up buffers software configurable (cannot be used as wake-up source) ADC software configurable on off standby software configurable software configurable off software configurable (cannot be used as wake-up source) off

Power-down mode

off off off

Deep power-down mode

off off off software configurable off software configurable off off software configurable (cannot be used as wake-up source) off off software configurable off LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 8.

Wake-up sources for reduced power modes power mode

Sleep Deep-sleep and power-down

Wake-up source

Any interrupt Pin interrupts BOD interrupt

Conditions

Enable interrupt in NVIC.

BOD reset WWDT interrupt WWDT reset Self-Wake-up Timer (WKT) time-out Interrupt from USART/SPI/I2C peripheral Deep power-down WAKEUP pins

• • • • • •

Enable pin interrupts in NVIC and STARTERP0 registers.

• • •

Enable interrupt in NVIC and STARTERP1 registers. Enable interrupt in BODCTRL register.

BOD powered in PDSLEEPCFG register.

• • • • • • • • • • •

Enable reset in BODCTRL register.

BOD powered in PDSLEEPCFG register.

Enable interrupt in NVIC and STARTERP1 registers. WWDT running. Enable WWDT in WWDT MOD register and feed.

Enable interrupt in WWDT MOD register.

LPOsc powered in PDSLEEPCFG register.

WWDT running.

Enable reset in WWDT MOD register.

LPOsc powered in PDSLEEPCFG register.

Enable interrupt in NVIC and STARTERP1 registers. Enable low-power oscillator in the LPOSCCLKEN register in the SYSCON block.

Select low-power clock for WKT clock in the WKT CTRL register.

Start the WKT by writing a time-out value to the WKT COUNT register.

Enable interrupt in NVIC and STARTERP1 registers. Enable USART/I2C/SPI interrupts.

Provide an external clock signal to the peripheral.

Configure the USART in synchronous slave mode and I2C and SPI in slave mode.

Enable the WAKEUP function in the WUENAREG register in the PMU.

9.22.5 Wake-up process

The LPC802 begin operation at power-up by using the FRO as the clock source allowing chip operation to resume quickly. If LPOsc or external clock sources are needed by the application, software must enable these features and wait for them to stabilize before they are used as a clock source.

9.23 System control 9.23.1 Reset

Reset has four sources on the LPC802: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the FRO and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

LPC802

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9 '' 9 '' 5SX 9 '' (6' UHVHW QV5& */,7&+),/7(5 3,1 (6' 9 66

DDD

Fig 16. Reset pad configuration 9.23.2 Brownout detection

The LPC802 includes one reset level and three interrupt levels for monitoring the voltage on the V DD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. One threshold level can be selected to cause a forced reset of the chip.

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller CAUTION 9.23.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP.

In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For details, see the

LPC802 user manual

.

There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using the ISP entry pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART.

If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can be disabled. For details, see the

LPC802 user manual

.

9.23.4 APB interface

The APB peripherals are located on one APB bus.

9.23.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the main static RAM, the ROM, and the APB peripherals. LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.24 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC802 is in reset. The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode. See

Table 4 .

To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250  s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH).

Remark:

The JTAG interface cannot be used for debug purposes.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

10. Limiting values

Table 9.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

V DD V V I ref

Parameter

supply voltage (core and external rail) reference voltage input voltage

Conditions

on pin VREFP 5 V tolerant I/O pins; V DD  1.71 V V IA analog input voltage 3 V tolerant I/O pin ACMPV REF on digital pins configured for an analog function

[2] [5] [6][7] [8]

Min

 0.5

[3][4]

 0.5

 0.5

 0.5

 0.5 I DD supply current I I SS latch ground current I/O latch-up current per supply pin (TSSOP20) per supply pin (TSSOP16) per supply pin (HVQFN33) per supply pin (WLCSP16) per ground pin (TSSOP20) per ground pin (TSSOP16) per ground pin (HVQFN33) per supply pin (WLCSP16)  (0.5V

DD ) < V I < (1.5V

DD ); T j < 125  C T T stg j(max) storage temperature maximum junction temperature

[9]

 65

Max

+4.6

V DD  5.4

 3.6

 4.6

40 30 50 30 40 30 50 30 100 +150 150

Unit

V V V V V mA mA mA  C  C LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 9.

Limiting values

…continued In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions

P tot(pack) total power dissipation (per package) TSSOP16, based on package heat transfer, not device power consumption.

TSSOP16, based on package heat transfer, not device power consumption.

TSSOP20, based on package heat transfer, not device power consumption.

TSSOP20, based on package heat transfer, not device power consumption.

V esd electrostatic discharge voltage HVQFN33, based on package heat transfer, not device power consumption.

HVQFN33, based on package heat transfer, not device power consumption.

WLCSP16, based on package heat transfer, not device power consumption.

WLCSP16, based on package heat transfer, not device power consumption.

human body model; all pins.

[11] [11] [12] [11] [12] [11] [12] [12] [10]

-

Min Max

0.29

0.22

0.36

0.26

0.91

0.34

0.65

0.27

2000

Unit

W W W W W W W W V [1] [2] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V SS unless otherwise noted.

Maximum/minimum voltage above the maximum operating voltage (see Table 12 ) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

Applies to all 5 V tolerant I/O pins except the 3 V tolerant pin PIO0_7.

[3] [4] [5] [6] Including the voltage on outputs in 3-state mode.

V DD present or not present.

An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 10 6 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[7] [8] If the comparator is configured with the common mode input V IC = V DD , the other comparator input can be up to 0.2 V above or below V DD without affecting the hysteresis range of the comparator function.

It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[9] Dependent on package type.

[10] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k  series resistor.

[11] JEDEC (4.5 in  4 in); still air.

[12] Single layer (4.5 in  3 in); still air.

LPC802

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11. Thermal characteristics

The average chip junction temperature, T j (  C), can be calculated using the following equation:

T j

=

T amb

+ 

P D

R th j a

  (1)

• • •

T amb = ambient temperature (  C), R th(j-a) = the package junction-to-ambient thermal resistance (  C/W) P D = sum of internal and I/O power dissipation The internal power dissipation is the product of I in some applications.

DD and V DD . The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant

Table 10.

Symbol Thermal resistance Parameter TSSOP20 package

R th(j-a) thermal resistance from junction-to-ambient

Conditions Max/min

JEDEC (4.5 in  4 in); still air 110  15 % single-layer (4.5 in air  3 in); still 153  15 % 22  15 %

Unit

 C/W  C/W  C/W R th(j-c) thermal resistance from junction-to-case

TSSOP16 package

R th(j-a) thermal resistance from junction-to-ambient JEDEC (4.5 in  4 in); still air 133  15 % single-layer (4.5 in air  3 in); still 182  15 % 32  15 %  C/W  C/W  C/W R th(j-c) thermal resistance from junction-to-case

HVQFN33 package

R th(j-a) thermal resistance from junction-to-ambient JEDEC (4.5 in  4 in); still air 43  15 % single-layer (4.5 in air  3 in); still 115  15 % 19  15 %  C/W  C/W  C/W R th(j-c) thermal resistance from junction-to-case

WLCSP16 package

R th(j-a) thermal resistance from junction-to-ambient R th(j-c) thermal resistance from junction-to-case JEDEC (4.5 in  4 in); still air 69.2

 15 % single-layer (4.5 in air  3 in); still 168  15 % 1.1

 15 %  C/W  C/W  C/W LPC802

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12. Static characteristics

12.1 General operating conditions Table 11.

General operating conditions

T amb =

40

C to +105

C, unless otherwise specified.

Symbol Parameter Conditions

f clk V DD clock frequency supply voltage (core and external rail) internal CPU/system clock For ADC operations V DDIO I/O rail V ref ADC positive reference voltage

Pin capacitance

For ADC operations on pin VREFP C io input/output capacitance pins with analog and digital functions pins with digital functions only

[2] [2]

-

Min

1.71

2.5

1.71

2.5

2.5

-

Typ

[1]

[1] [2] Typical ratings are not guaranteed. The values listed are for room temperature (25  C), nominal supply voltages. Including bonding pad capacitance. Based on simulation, not tested in production.

Max

15 3.6

3.6

3.6

3.6

V DD 7.1

2.8

12.2 Power consumption

Power measurements in active, sleep, deep-sleep, and power-down modes were performed under the following conditions:

• • •

Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

Configure GPIO pins as outputs using the GPIO DIR register.

Write 1 to the GPIO CLR register to drive the outputs LOW.

V V V V

Unit

MHz V pF pF LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 12.

Static characteristics, supply pins

T amb =

40

C to +105

C, unless otherwise specified.

Symbol Parameter Conditions

I DD supply current Active mode; code while(1){} executed from flash; I DD I DD I DD supply current supply current supply current system clock = 1 MHz V DD = 3.3 V system clock = 9 MHz V DD = 3.3 V system clock = 12 MHz V DD = 3.3 V system clock = 15 MHz V DD = 3.3 V Sleep mode system clock = 9 MHz V DD = 3.3 V system clock = 12 MHz V DD = 3.3 V system clock = 15 MHz V DD = 3.3 V Deep-sleep mode; V DD = 3.3 V; T amb = 25  C T amb = 105  C Power-down mode; V DD = 3.3 V T amb = 25  C T amb = 105  C Deep power-down mode; V DD = 3.3 V; T amb = 25  C T amb = 105  C

[3][5][6][10]

-

[3][4][5][6]

-

[3][4][5][6]

-

[3][4][5][6]

-

[3][4][5][6]

-

[3][4][5][6]

-

[3][4][5][6]

-

[3][7]

-

[3][7]

-

[8]

-

Min

Typ [1][2]

0.5

0.8

1.0

1.3

0.4

0.5

0.6

100 6 0.15

-

Max

[9]

175 240 14 75 0.5

7 [1] [2] [3] [4] [5] [6] [7] [8] I Typical ratings are not guaranteed. The values listed are for room temperature (25 Characterized through bench measurements using typical samples.

DD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

FRO enabled.

BOD disabled.

All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block.

All oscillators and analog blocks turned off.

WAKEUP function pin pulled HIGH externally.

[9] Tested in production, VDD = 3.6 V.

[10] LPOsc enabled, FRO disabled.

 C), V DD = 3.3 V.

Unit

mA mA mA mA mA mA mA  A  A  A  A  A  A LPC802

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, '' —$

LPC802 32-bit ARM Cortex-M0+ microcontroller

DDD

WHPSHUDWXUHƒ& Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register.

Fig 17. Deep-sleep mode: Typical supply current I DD versus temperature for different supply voltages V DD

DDD

, '' —$ WHPSHUDWXUHƒ& Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register.

Fig 18. Power-down mode: Typical supply current I DD versus temperature for different supply voltages V DD

LPC802

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, '' —$

LPC802 32-bit ARM Cortex-M0+ microcontroller

DDD

WHPSHUDWXUHƒ& WKT not running.

Fig 19. Deep power-down mode: Typical supply current I DD versus temperature for different supply voltages V DD

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 12.2.1 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG. and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code accessing the peripheral is executed. Measured on a typical sample at T amb = 25  C. The supply currents are shown for system clock frequencies of 12 MHz and 15 MHz.

Table 13.

Peripheral Power consumption for individual analog and digital blocks Typical supply current in μ A Notes System clock frequency = n/a 12 MHz 15 MHz

FRO BOD Flash 80 LPOsc 1 GPIO + pin interrupt 74 39 40 54 FRO = 12MHz. FRO output disabled.

Independent of main clock frequency.

FRO; independent of main clock frequency.

GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register.

SWM IOCON CTimer MRT WWDT I2C0 SPI0 USART0 USART1 Comparator ACMP ADC CRC 24 28 28 45 31 44 33 39 40 36 61 61 61 37 30 36 37 56 41 58 42 46 50 46 78 78 78 50 Digital controller only. Analog portion of the ADC disabled in the PDRUNCFG register.

Combined analog and digital logic. ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 1 in the ADC CTRL register (ADC in low-power mode).

Combined analog and digital logic. ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 0 in the ADC CTRL register (ADC powered).

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 12.3 Pin characteristics Table 14.

Static characteristics, electrical pin characteristics

T amb =

40

C to +105

C, unless otherwise specified.

Symbol Parameter Conditions Standard port pins configured as digital pins, RESET

I I IL IH LOW-level input current V HIGH-level input current I = 0 V; on-chip pull-up resistor disabled V I = V DD disabled ; on-chip pull-down resistor I OZ V V I O V IH OFF-state output current input voltage output voltage HIGH-level input voltage V O = 0 V; V O = V DD ; on-chip pull-up/down resistors disabled V DD  1.71 V; 5 V tolerant pins except PIO0_7 V DD = 0 V output active -

Min

0 0 0 0.7V

DD -

Typ

0.5

0.5

0.5

I I V IL V hys V V OH OL OH OL LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current I OH = 4 mA; 2.5 V <= V DD <= 3.6 V I OH = 3 mA; 1.71 V <= V DD < 2.5 V I OL = 4 mA; 2.5 V <= V DD <= 3.6 V I OL = 3 mA; 1.71 V <= V DD < 2.5 V V OH = V DD  0.4 V; 2.5 V  V DD  3.6 V V OH = V DD  0.5 V; 1.71 V  V DD  2.5 V V OL = 0.5 V 2.5 V  V DD  3.6 V 1.71 V  V DD < 2.5 V V OH = 0 V I OHS HIGH-level short-circuit output current

[3]

I I OLS I I pd pu pull-down current pull-up current V I = 5 V V I = 0 V; 2.0 V  V DD  3.6 V 1.71 V  V DD < 2.0 V

[4] [4]

V DD < V I < 5 V

High-drive output pin configured as digital pin (PIO0_2, PIO0_3, and PIO0_12)

I IL IH LOW-level short-circuit output current V LOW-level input current V HIGH-level input current I OL = V = 0 V; on-chip pull-up resistor disabled V I = V disabled DD DD ; on-chip pull-down resistor

[3]

3 4 3 10 10 7 0 0.4

V DD  0.4 V DD  0.5 4 50 50 50 0 0.5

0.5

[1]

Max Unit

10

[2]

10

[2]

10

[2]

nA nA 5.4

3.6

V DD nA V V V V 0.3V

DD 0.5

0.5

V V V V V V mA mA 45 50 150 90 85 0 mA mA mA mA  A  A  A  A 10

[2]

10

[2]

nA nA LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 14.

Static characteristics, electrical pin characteristics

…continued T amb =

40

C to +105

C, unless otherwise specified.

Symbol Parameter Conditions

I OZ V I OFF-state output current input voltage V O = 0 V; V O = V DD ; on-chip pull-up/down resistors disabled V DD  1.8 V -

Min

0 -

Typ

0.5

[1] Max

10 5.0

[2]

Unit

nA V I I I I I V V V V V V O IH IL hys OH OL OH OL OLS pd pu output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current LOW-level short-circuit output current pull-down current pull-up current V DD = 0 V output active I OH = 20 mA; 2.5 V <= V DD < 3.6 V I OH = 12 mA; 1.71 V <= V DD < 2.5 V I OL = 4 mA; 2.5 V <= V DD <= 3.6 V I OL = 3 mA; 1.71 V <= V DD < 2.5 V V OH = V DD  0.6 V; 2.5 V <= V DD < 3.6 V V OH = V DD  0.6 V; 1.71 V <= V DD < 2.5 V V OL = 0.5 V 2.5 V  V DD  3.6 V 1.71 V  V DD < 2.5 V V OL = V DD V I = 5 V V I = 0 V; 2.0 V  V DD  3.6 V 1.71 V  V DD < 2.0 V V DD < V I < 5 V

[3] [4] [4]

0 0 0.7V

V DD  0.6 V DD  0.6 20 12 4 3 10 10 7 0 DD 0.4

50 50 50 0 [1] [2] [3] [4] Typical ratings are not guaranteed. The values listed are for room temperature (25  C), nominal supply voltages. Based on characterization. Not tested in production.

Allowed as long as the current limit does not exceed the maximum current allowed by the device.

Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 20 .

3.6

V DD 50 150 90 85 0 V V V 0.3V

DD 0.5

V V V V V mA mA mA mA mA  A  A  A  A  A LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

pin PIO0_n IOL I pd + A V DD pin PIO0_n + IOH Ipu A

aaa-010819

9 2+ 9

Fig 20. Pin input/output current measurement 12.3.1 Electrical pin characteristics

DDD

9 2+ 9 & & & &

DDD

& & & & , 2+ P$ , 2+ P$ Conditions: V DD = 1.8 V; on pin PIO0_12.

Conditions: V DD = 3.3 V; on pin PIO0_12.

Fig 21. High-drive output: Typical HIGH-level output voltage V OH versus HIGH-level output current I OH

LPC802

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NXP Semiconductors

, 2/ P$ & & & &

DDD

, 2/ P$

LPC802 32-bit ARM Cortex-M0+ microcontroller

DDD

& & & & 9 2/ 9 9 2/ 9 Conditions: V DD = 1.8 V; standard port pins and high-drive pin PIO0_12.

Conditions: V DD = 3.3 V; standard port pins and high-drive pin PIO0_12.

Fig 22. Typical LOW-level output current I OL versus LOW-level output voltage V OL

DDD DDD

9 2+ 9 9 2+ 9 & & & & & & & & , 2+ P$ , 2+ P$ Conditions: V DD = 1.8 V; standard port pins.

Conditions: V DD = 3.3 V; standard port pins.

Fig 23. Typical HIGH-level output voltage V OH versus HIGH-level output source current I OH

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, SX —$

DDD

, SX —$

LPC802 32-bit ARM Cortex-M0+ microcontroller

DDD

9 , 9 Conditions: V DD = 1.8 V; standard port pins.

Fig 24. Typical pull-up current I PU versus input voltage V I

DDD

, SG —$ , SG —$ 9 , 9 Conditions: V DD = 3.3 V; standard port pins.

DDD

& & & & & & & & 9 , 9 Conditions: V DD = 1.8 V; standard port pins.

Fig 25. Typical pull-down current I PD versus input voltage V I

9 , 9 Conditions: V DD = 3.3 V; standard port pins.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

13. Dynamic characteristics

13.1 Flash memory (EEPROM based) Table 15.

Flash characteristics

T amb =

40

C to +105

C. Based on JEDEC NVM qualification.

Symbol Parameter Conditions Min

N endu t ret endurance retention time powered

[1]

10 -

Typ

200,000 500,000 t er erase time not powered page or multiple consecutive pages, sector or multiple consecutive sectors 20 1.03

t prog programming time

[2]

2.5

-

Max Unit

cycles years years ms ms [1] [2] Number of program/erase cycles.

Programming times are given for writing 64 bytes to the flash. T amb <= +85  C. Flash programming with IAP calls (see

LPC802 user manual

).

13.2 FRO Table 16.

Dynamic characteristic: FRO

T amb =

40

C to +105

C; 1.7 V

V DD

3.6 V.

Symbol Min Typ

[1]

FRO clock frequency; Condition: 0

C

T amb

70

C

f osc(RC) 9 -1 % 9

Max

9 +1 % f f osc(RC) f osc(RC) 15 -1 % 15

FRO clock frequency; Condition:

20

C

T amb

70

C

osc(RC) f osc(RC) 12 -1 % 9 -2 % 12 -2 % 12 9 12 f f osc(RC) 15 -2 % 15

FRO clock frequency; Condition:

40

C

T amb

105

C

15 +1 % osc(RC) f osc(RC) 9 -3.5 % 12 -3.5 % 9 12 9 +2.5 % 12 +2.5 % f osc(RC) 15 -3.5 % 15 12 +1 % 15 +1 % 9 +1 % 12 +1 % 15 +2.5 % [1]

Unit

MHz MHz MHz MHz MHz MHz MHz MHz MHz Typical ratings are not guaranteed. The values listed are at room temperature (25  C), nominal supply voltages.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 17.

Dynamic characteristic: LPOsc

T amb =

40

C to +105

C; 1.71 V

V DD

3.6 V.

Symbol Parameter Conditions

f osc(RC) LPOsc clock frequency [1]

Min

1 -3%

Typ

1

[1]

Max

1 +3%

Unit

MHz Typical ratings are not guaranteed. The values listed are at room temperature (25  C), nominal supply voltages.

13.3 I/O pins Table 18.

Dynamic characteristics: I/O pins [1]

T amb =

40

C to +105

C; 3.0 V

V DD

3.6 V.

Symbol Parameter Conditions

t r t f rise time fall time pin configured as output pin configured as output [1] Applies to standard port pins and RESET pin.

Min

3.0

2.5

-

Typ Max

5.0

5.0

Unit

ns ns

13.4 WKTCLKIN pin (wake-up clock input) Table 19.

Dynamic characteristics: WKTCLKIN pin

T amb =

40

C to +105

C; 1.71 V

V DD

3.6 V.

Symbol Parameter Conditions

f clk clock frequency power-down, deep-sleep, and active mode t CHCX t CLCX clock HIGH time clock LOW time [1] Assuming a square-wave input clock.

[1]

-

Min Max

10

Unit

MHz 50 50

13.5 I 2 C-bus Table 20.

Dynamic characteristic: I 2 C-bus pins

[1]

T amb =

40

C to +105

C; values guaranteed by design.

[2]

Symbol Parameter Conditions

f SCL SCL clock frequency Standard-mode t f fall time

[4][5][6]

Fast-mode of both SDA and SCL signals Standard-mode Fast-mode t t LOW HIGH LOW period of the SCL clock HIGH period of the SCL clock Standard-mode Fast-mode Standard-mode Fast-mode

Min

0 0

Max

100 400 300 20 + 0.1  C b 4.7

1.3

4.0

0.6

300 ns ns ns  s  s  s  s

Unit

kHz kHz ns LPC802

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W I

LPC802 32-bit ARM Cortex-M0+ microcontroller Table 20.

Dynamic characteristic: I 2 C-bus pins [1]

T amb =

40

C to +105

C; values guaranteed by design.

[2]

Symbol Parameter Conditions

t HD;DAT data hold time

[3][4][7]

Standard-mode Fast-mode t SU;DAT data set-up time

[8][9]

Standard-mode Fast-mode

Min

0 0 250 100 -

Max Unit

 s  s ns ns [1] [2] [3] [4] [5] [6] [7] [8] [9] See the I 2 C-bus specification

UM11045

for details.

Parameters are valid over operating temperature range unless otherwise specified. t HD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V IH (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

C b = total capacitance of one bus line in pF.

The maximum t f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f .

The maximum t HD;DAT could be 3.45  s and 0.9  s for Standard-mode and Fast-mode but must be less than the maximum of t VD;DAT or t VD;ACK by a transition time (see

UM10204

). This maximum must only be met if the device does not stretch the LOW period (t LOW ) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

t SU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge.

A Fast-mode I 2 C-bus device can be used in a Standard-mode I 2 C-bus system but the requirement t SU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r(max) + t SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I 2 C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

W 68'$7 6'$ W +''$7 W 9''$7 W I W +,*+ 6&/ W /2: 6 I 6&/

DDD

Fig 26. I 2 C-bus pins clock timing

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 13.6 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode is 15 Mbit/s, and the maximum supported bit rate for SPI slave mode is 1/(2 x 28 ns) = 17.8 Mbit/s at 3.0v <= VDD <= 3.6v and 1/(2 x 32 ns) = 15.6 Mbit/s at 1.7v <= VDD <= 3.0v.

Remark:

SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins.

Table 21.

SPI dynamic characteristics

T amb =

40

C to 105

C; C L = 20 pF; input slew = 1 ns. Simulated parameters sampled at the 30 % and 70 % level of the rising or falling edge; values guaranteed by design. Delays introduced by the external trace or external device are not considered.

Symbol SPI master Parameter Conditions Min Max Unit

t t t DS DH v(Q)

SPI slave

t DS t DH t v(Q) data set-up time data set-up time data hold time data output valid time 1.71 V <= V DD <= 3.6 V 1.71 V <= V DD <= 3.6 V 1.71 V <= V DD <= 3.6 V 1.71 V <= V 1.71 V <= V 3.0 V <= V DD DD DD <= 3.6 V <= 3.6 V <= 3.6 V 1.71 V <= V DD < 3.0 V 10 7 0 10 7 0 0 2 28 32 ns ns ns ns ns ns ns LPC802

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SCK (CPOL = 0) SCK (CPOL = 1) SSEL T cy(clk)

LPC802 32-bit ARM Cortex-M0+ microcontroller

MOSI (CPHA = 0) t v(Q) DATA VALID (MSB) MISO (CPHA = 0) DATA VALID (MSB) DATA VALID t DS t DH DATA VALID t v(Q) DATA VALID (LSB) DATA VALID (LSB) IDLE IDLE DATA VALID (MSB) DATA VALID (MSB) MOSI (CPHA = 1) MISO (CPHA = 1) t v(Q) DATA VALID (LSB) DATA VALID t DS t DH DATA VALID t v(Q) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB)

aaa-014969

T cy(clk) = CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC802

User manual

.

Fig 27. SPI master timing

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

T cy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MISO (CPHA = 0) t v(Q) DATA VALID (MSB) MOSI (CPHA = 0) DATA VALID (MSB) DATA VALID t DS t DH DATA VALID t v(Q) DATA VALID (LSB) DATA VALID (LSB) MISO (CPHA = 1) MOSI (CPHA = 1) IDLE IDLE t v(Q) DATA VALID (LSB) DATA VALID (LSB) DATA VALID t DS t DH DATA VALID t v(Q) DATA VALID (MSB) DATA VALID (MSB) IDLE IDLE DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB)

aaa-014970

Fig 28. SPI slave timing

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 13.7 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master synchronous mode is 10 Mbit/s, and the maximum supported bit rate for USART slave synchronous mode is 10 Mbit/s.

Remark:

USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins

Table 22.

USART dynamic characteristics

T amb =

40

C to 105

C; 1.71 V <= V DD <= 3.6 V unless noted otherwise; C L = 10 pF; input slew = 10 ns. Simulated parameters sampled at the 30 %/70 % level of the falling or rising edge; values guaranteed by design.

Symbol Parameter USART master (in synchronous mode) Conditions Min Max Unit

t t t su(D) h(D) v(Q) data input set-up time data input hold time data output valid time 3.0 V <= V DD <= 3.6 V 1.71 V <= V DD < 3.0 V 3.0 V <= V DD <= 3.6 V 1.71 V <= V DD < 3.0 V 3.0 V <= V DD <= 3.6 V 1.71 V <= V DD < 3.0 V 34 36 0 0 0 0 7 6 ns ns ns ns ns ns t t

USART slave (in synchronous mode)

t su(D) data input set-up time h(D) v(Q) data input hold time data output valid time 3.0 V <= V DD <= 3.6 V 1.71 V <= V DD < 3.0 V 3.0 V <= V DD <= 3.6 V 1.71 V <= V DD < 3.0 V 3.0 V <= V DD <= 3.6 V 1.71 V <= V DD < 3.0 V 8 3 10 5 0 0 39 42 ns ns ns ns ns ns T cy(clk) Un_SCLK (CLKPOL = 0) Un_SCLK (CLKPOL = 1) TXD START t v(Q) t vQ) BIT1 RXD START BIT0 t su(D) t h(D) BIT0 BIT1

aaa-015074

Fig 29. USART timing

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 13.8 Wake-up process Table 23.

Dynamic characteristic: Typical wake-up times from low power modes

V DD = 3.3 V;T amb = 25

C; Using FRO (15 MHz) as the system clock.

Symbol Parameter Conditions Min

Typ [1]

Max Unit

t wake wake-up time from sleep mode from deep-sleep mode from power-down mode from deep power-down mode

[2][3] [2] [2] [4]

1.97

2.07

25 313   s s  s  s [1] [2] [3] [4] Typical ratings are not guaranteed. The values listed are at room temperature (25  C), nominal supply voltages.

The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR) wake-up handler. ISR is located in SRAM.

FRO enabled, all peripherals off. Wake up from deep power-down causes the part to go through entire reset process. The wake-up time measured is the time between when the Wake-Up pin is triggered to wake the device up and when a GPIO output pin is set in the reset handler.

14. Characteristics of analog peripherals

14.1 BOD Table 24.

BOD static characteristics [1]

T amb = 25

C.

Symbol Parameter Conditions

V th threshold voltage interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion -

Min Typ

2.24

2.40

2.52

2.64

2.81

2.90

1.51

1.54

-

Max Unit

V V V V V V V V [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see

the

LPC802

user manual

.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 14.2 ADC Table 25.

12-bit ADC static characteristics

T amb =

40

C to +105

C unless noted otherwise; V DD = 2.5 V to 3.6 V; VREFP = V DD ; VREFN = V SS .

Symbol Parameter Conditions Min Typ Max

V IA V ref C ia analog input voltage reference voltage analog input capacitance on pin VREFP 0 2.5

V V DD DD 26 f clk(ADC) f s E D ADC clock frequency sampling frequency differential linearity error

[2] [2] [5][4]

 1 15 480 E E V Z i L(adj) O err(fs) integral non-linearity offset error full-scale error voltage input impedance f s = 480 Ksamples/s

[6][4] [7][4] [8][4] [1][9] [10]

0.1

 4  3 0.1

-

Unit

V V pF MHz Ksamples/s LSB LSB LSB % M  [1] [2] [3] [4]

The input resistance of ADC channel 0 is higher than for all other channels. See Figure 30 .

In the ADC TRM register, set VRANGE = 0 (default).

In the ADC TRM register, set VRANGE = 1 (default).

Based on characterization. Not tested in production.

[5] [6] [7] The differential linearity error (E D

) is the difference between the actual step width and the ideal step width. See Figure 30

.

The integral non-linearity (E L(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See

Figure 30 .

The offset error (E O ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See

Figure 30

.

[8] The full-scale error voltage or gain error (E G ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 30 .

[9] T amb = 25  C; maximum sampling frequency f s = 480 Ksamples/s and analog input capacitance C ia = 26 pF.

[10] Input impedance Z i

(see Section 14.2.1

) is inversely proportional to the sampling frequency and the total input capacity including C

ia and C io : Z i  1 / (f s  C i ). See

Table 12

for C io .

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

offset error E O gain error E G 4095 4094 4093 4092 4091 4090 (2) 7 code out 6 5 4 3 2 1 0 1 offset error E O 2 (4) (5) (3) 3 4 1 LSB (ideal) 5 6 7 V IA (LSB ideal ) (1) 4090 4091 4092 4093 4094 4095 4096 1 LSB = VREFP - V SS 4096

002aaf436

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E D ).

(4) Integral non-linearity (E L(adj) ).

(5) Center of a step of the actual transfer curve.

Fig 30. 12-bit ADC characteristics

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 14.2.1 ADC input impedance

Figure 31

shows the ADC input impedance. In this figure:

• • • • • • • • •

ADCx represents ADC input channel 0.

ADCy represents ADC input channels 1 to 11.

R 1 and R sw are the switch-on resistance on the ADC input channel.

If ADC input channel 0 is selected, the ADC input signal goes through R 1 + R sw to the sampling capacitor (C ia ).

If ADC input channels 1 to 11 are selected, the ADC input signal goes through R sw to the sampling capacitor (C ia ).

Typical values, R 1 = 5.6 k  , R sw = 6.9 k  To calculate total resistance, use the following equation:

– – – –

R TOTAL = R external + R internal R external = External resistance on the ADC input channel.

R internal for channel 0 = R 1 +R SW = 12.5 k  .

R internal for channels 1 to 11 = 6.9 k  .

See

Table 11 for C

io .

See

Table 25

for C ia .

ADC

DAC Cia Rsw R1 Cio ADCx ADCy Cio

aaa-017600

Fig 31. ADC input impedance

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 14.3 Comparator and internal voltage reference Table 26.

Internal voltage reference static and dynamic characteristics

T amb =

40

C to +105

C; V DD = 3.3 V; hysteresis disabled in the comparator CTRL register.

Symbol Parameter Conditions Min Typ Max Unit

V O output voltage T amb = 25  C to 105  C T amb = 25  C 860 904 940 mV mV

aaa-014424

0.910

V ref (V) 0.905

0.900

0.895

0.890

-40 -10 20 50 80 temperature (°C) V DD = 3.3 V; characterized through bench measurements on typical samples.

Fig 32. Typical internal voltage reference output voltage

110

Table 27.

Comparator characteristics

T amb =

40

C to +105

C unless noted otherwise; V DD = 1.71 V to 3.6 V.

Symbol Parameter Conditions Static characteristics

I V ref(cmp) DD comparator reference voltage supply current pin ACMPV REF VP > VM; T amb = 25 ° C; V DD = 3.3 V VM > VP; T amb = 25 ° C; V DD = 3.3 V V IC DV O V offset common-mode input voltage output voltage variation offset voltage V IC = 0.1 V; V DD = 3.0 V V IC = 1.5 V; V DD = 3.0 V V IC = 2.9 V; V DD = 3.0V

Dynamic characteristics

t startup start-up time nominal process; V DD = 3.3 V; T amb = 25 ° C

[2] [2] [2] [2] [2]

-

Min Typ

1.5

0 0 4 6 6 90 60 13 -

Max

3.6

V DD V DD

Unit

V  A  A V V mV mV mV  s LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 27.

Comparator characteristics

…continued T amb =

40

C to +105

C unless noted otherwise; V DD = 1.71 V to 3.6 V.

Symbol Parameter Conditions

t PD t PD V hys propagation delay propagation delay hysteresis voltage HIGH to LOW; V 105 ° C DD = 3.0 V; T amb = V IC = 0.1 V; 100 mV overdrive input V IC = 0.1 V; rail-to-rail input V IC = 1.5 V; 100 mV overdrive input V IC = 1.5 V; rail-to-rail input V IC = 2.9 V; 100 mV overdrive input V IC = 2.9 V; rail-to-rail input LOW to HIGH; V DD = 3.0 V; T amb = 105 ° C V IC = 0.1 V; 100 mV overdrive input V IC = 0.1 V; rail-to-rail input V IC = 1.5 V; 100 mV overdrive input V IC = 1.5 V; rail-to-rail input V IC = 2.9 V; 100 mV overdrive input V IC = 2.9 V; rail-to-rail input positive hysteresis; V DD = 3.0 V; V IC = 1.5 V; T amb = 105 ° C; settings: 5 mV V hys hysteresis voltage 10 mV 20 mV negative hysteresis; V DD = 3.0 V; V IC = 1.5 V; T amb = 105 ° C; settings: 5 mV 10 mV 20 mV R lad ladder resistance -

[1][2][4] [1][2] [1][2][4] [1][2] [1][2][4] [1][2]

-

[1][2][4] [1][2] [1][2][4] [1][2] [1][2][4] [1][2] [3]

-

[1][3]

-

Min Typ

320 260 300 160 400 80 170 80 120 220 160 320 6 11 21 11 18 30 1 [1] [2] [3] [4] C L = 10 pF Characterized on typical samples, not tested in production.

Input hysteresis is relative to the reference input channel and is software programmable. 100 mV overdrive corresponds to a square wave from 50 mV below the reference (V IC ) to 50 mV above the reference.

-

Max

-

Table 28.

Comparator voltage ladder dynamic characteristics

T amb =

40

C to +105

C; V DD = 1.8 V to 3.6 V.

Symbol Parameter Conditions Min

t s(pu) power-up settling time to 99% of voltage ladder output value

[1]

t s(sw) switching settling time to 99% of voltage ladder output value

[1]

[1] Characterized on typical samples, not tested in production.

Typ

17 18 -

Max Unit Unit

 s  s ns ns ns ns ns ns ns ns ns ns ns ns mV mV mV mV mV mV M  LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Table 29.

Comparator voltage ladder reference static characteristics

V DD = 1.8 V to 3.6 V. T amb = -40

C to + 105

C; external or internal reference.

Symbol Parameter Conditions Min Typ

[1]

E V(O) output voltage error decimal code = 00 decimal code = 08 decimal code = 16

[2]

 6  1  1 decimal code = 24 decimal code = 30 decimal code = 31  1  1  1 [1] [2] Characterized though limited samples. Not tested in production.

All peripherals except comparator, temperature sensor, and FRO turned off.

-

Max

% % % %

Unit

mV % LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

15. Application information

15.1 Start-up behavior

Figure 33

shows the start-up timing after reset. The FRO 12 MHz oscillator provides the default clock at Reset and provides a clean system clock shortly after the supply pins reach operating voltage.

FRO starts FRO status internal reset V DD valid threshold = 1.71 V GND t a μs t b μs supply ramp-up time boot time t c μs user code processor status boot code execution finishes; user code starts

aaa-028455

Fig 33. Start-up timing Table 30.

Parameter

t a t b t c

Typical start-up timing parameters Description

FRO start time Internal reset de-asserted Boot time

Value

 26  s 101  s 36  s

15.2 Connecting power, clocks, and debug functions

Figure 34

shows the basic board connections used to power the LPC802 and provide debug capabilities via the serial wire port.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

3.3 V SWD connector (4) 1 3 5 n.c.

7 9 3.3 V 2 4 6 n.c.

8 10 n.c.

~10 kΩ - 100 kΩ (5) SWDIO/PIO0_2 3.3 V ~10 kΩ - 100 kΩ SWCLK/PIO0_3 (5) RESETN/PIO0_5 V SS GND GND V DD 0.1 μF 0.01 μF (1) 3.3 V

LPC802

GND PIO0_7/ADC_1/ACMPV REF (4) (ADC_1), (2) (ACMPVREF) ISP select pin PIO0_12 (4) ADC_0 VREFP 0.1 μF 0.1 μF 10 μF (2) 3.3 V GND GND

aaa-026823

(1) Position the decoupling capacitors of 0.1 μ F and 0.01 μ F as close as possible to the V DD pin. Add one set of decoupling capacitors to each V DD pin.

(2) Position the decoupling capacitors of 0.1 μ F as close as possible to the VREFN and V DD pins. The 10 μ F bypass capacitor filters the power line. Tie VREFP to V DD if the ADC is not used. Tie VREFN to V SS if ADC is not used.

(3) Uses the ARM 10-pin interface for SWD.

(4) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 4

.

(5) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by default.

Fig 34. Power, clock, and debug connections

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 15.3 I/O power consumption

I/O pins are contributing to the overall dynamic and static power consumption of the part. If pins are configured as digital inputs, a static current can flow depending on the voltage level at the pin and the setting of the internal pull-up and pull-down resistors. This current can be calculated using the parameters R pu and R pd given in

Table 14

for a given input voltage V I . For pins set to output, the current drive strength is given by parameters I OH and I OL

in Table 14 , but for calculating the total static current, you also need to consider any

external loads connected to the pin.

I/O pins also contribute to the dynamic power consumption when the pins are switching because the V DD supply provides the current to charge and discharge all internal and external capacitive loads connected to the pin in addition to powering the I/O circuitry.

The contribution from the I/O switching current I sw can be calculated as follows for any given switching frequency f sw if the external capacitive load (C ext

) is known (see Table 14

for the internal I/O capacitance): I sw = V DD x f sw x (C io + C ext ) LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 15.4 Termination of unused pins

Table 31 shows how to terminate pins that are

not

used in the application. In many cases, unused pins may should be connected externally or configured correctly by software to minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0 to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 31.

Pin

all PIOn_m VREFP

Termination of unused pins

-

Default state

I; PU

[1]

Recommended termination of unused pins

Can be left unconnected if driven LOW and configured as GPIO output with pull-up disabled by software.

Tie to VDD. [1] I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up.

15.5 Pin states in different power modes Table 32.

Pin Pin states in different power modes

PIOn_m pins RESET

Active Sleep Deep-sleep/power down

As configured in the IOCON

[1]

. Default: internal pull-up enabled.

Reset function enabled. Default: input, internal pull-up enabled.

Deep power-down

Floating.

Reset function disabled; floating; if the part is in deep power-down mode.

[1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes.

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16. Package outline

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

20 Z y 1 D c E A X v M A pin 1 index e H E 11 b p 10 w M A 2 A 1 L L p detail X Q θ A 0 2.5

scale

DIMENSIONS (mm are the original dimensions) UNIT A max.

A 1 A 2 A 3 b p c

mm 1.1

0.15

0.05

0.95

0.80

0.25

0.30

0.19

0.2

0.1

D (1)

6.6

6.4

E (2)

4.5

4.3

e

0.65

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE VERSION IEC REFERENCES JEDEC JEITA

SOT360-1 MO-153

H E

6.6

6.2

5 mm

L

1

L p

0.75

0.50

Q

0.4

0.3

v w y

0.2

0.13

0.1

Z (1)

0.5

0.2

θ 8 o 0 o

EUROPEAN PROJECTION ISSUE DATE

99-12-27 03-02-19

Fig 35. Package outline SOT360-1 (TSSOP20)

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

D c E A X v M A y 16 Z 9 H E 1 pin 1 index e b p 8 w M A 2 A 1 L L p detail X Q θ A 0 2.5

scale

DIMENSIONS (mm are the original dimensions) UNIT A max.

A 1 A 2 A 3 b p c

mm 1.1

0.15

0.05

0.95

0.80

0.25

0.30

0.19

0.2

0.1

D (1)

5.1

4.9

E (2)

4.5

4.3

e

0.65

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE VERSION IEC REFERENCES JEDEC JEITA

SOT403-1 MO-153

H E

6.6

6.2

5 mm

L

1

L p

0.75

0.50

Q

0.4

0.3

v w

0.2

0.13

y

0.1

Z (1)

0.40

0.06

θ 8 o 0 o

EUROPEAN PROJECTION ISSUE DATE

99-12-27 03-02-18

Fig 36. Package outline SOT (TSSOP16)

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm

D B A terminal 1 index area E A A1 c detail X L 8 9 e e1 1/2 e b 16 17 e v w C C A B y1 C C y Eh 1/2 e e2 terminal 1 index area 1 32 25 24 Dh 0 2.5

scale Dimensions (mm are the original dimensions) Unit (1) A (1) A 1 b c D (1) D h E (1) E h e e 1 e 2 mm max nom min 0.85

0.05

0.00

0.30

0.18

0.2

5.1

4.9

3.75

3.45

5.1

4.9

3.75

3.45

0.5

3.5

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. 3.5

Outline version IEC JEDEC References JEITA MO-220 L 0.5

0.3

Fig 37. Package outline HVQFN33 (5 x 5 x 0.85 mm)

v 5 mm w y y 1 0.1

0.05

0.05

0.1

European projection X LPC802

Product data sheet

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hvqfn33f_po

Issue date 11-10-11 11-10-17 © NXP Semiconductors B.V. 2019. All rights reserved.

68 of 81

NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Fig 38. Package outline WLCSP16 (1.86

1.86

0.3 mm)

LPC802

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NXP Semiconductors

17. Soldering

Footprint information for reflow soldering of TSSOP20 package LPC802 32-bit ARM Cortex-M0+ microcontroller SOT360-1

Hx Gx P2 (0.125) (0.125) Hy Gy C D2 (4x) P1 D1 Generic footprint pattern Refer to the package outline drawing for actual layout By Ay solder land occupied area DIMENSIONS in mm P1 P2 Ay 0.650

0.750

7.200

By C 4.500

1.350

D1 0.400

D2 Gx 0.600

6.900

Gy Hx 5.300

7.300

Hy 7.450

Fig 39. Reflow soldering of the TSSOP20 package

LPC802

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sot360-1_fr

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NXP Semiconductors Footprint information for reflow soldering of TSSOP16 package LPC802 32-bit ARM Cortex-M0+ microcontroller SOT403-1

Hx Gx P2 (0.125) (0.125) Hy Gy C D2 (4x) P1 D1 Generic footprint pattern Refer to the package outline drawing for actual layout By Ay solder land occupied area DIMENSIONS in mm P1 P2 Ay 0.650

0.750

7.200

By C 4.500

1.350

D1 0.400

D2 Gx 0.600

5.600

Gy Hx 5.300

5.800

Hy 7.450

Fig 40. Reflow soldering of the TSSOP16 package

LPC802

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sot403-1_fr

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NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package LPC802 32-bit ARM Cortex-M0+ microcontroller

Hx Gx see detail X P nSPx Hy Gy SLy By Ay nSPy C SLx Bx Ax D solder land solder paste occupied area detail X 0.60

0.30

Dimensions in mm P Ax Ay 0.5

Issue date 5.95

5.95

11-11-15 11-11-20 Bx 4.25

By 4.25

C 0.85

D 0.27

Gx 5.25

Gy 5.25

Fig 41. Reflow soldering for the HVQFN33 (5x5) package

Hx 6.2

Hy 6.2

SLx 3.75

SLy 3.75

nSPx 3 nSPy 3

002aag766

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Fig 42. Reflow soldering for the WLCSP16 (4x4) package (1 of 3)

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Fig 43. Reflow soldering for the WLCSP16 (4x4) package (2 of 3)

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller Fig 44. Reflow soldering for the WLCSP16 (4x4) package (3 of 3)

LPC802

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

18. Abbreviations

Table 33.

Acronym

AHB APB BOD GPIO RC SPI SMBus TEM UART

Abbreviations Description

Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General-Purpose Input/Output Resistor-Capacitor Serial Peripheral Interface System Management Bus Transverse ElectroMagnetic Universal Asynchronous Receiver/Transmitter

19. References

[1] [2] [3] [4] LPC802 User manual UM11045. LPC802 Errata sheet.

I2C-bus specification

UM10204

.

Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf

LPC802

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20. Revision history

Table 34.

Revision history Document ID

LPC802 v.1.8

Modifications: LPC802 v.1.7

Modifications: LPC802 v.1.6

Modifications: LPC802 v.1.5

Modifications: LPC802 v.1.4

Modifications: LPC802 v.1.3

Modifications: LPC802 v.1.2

Modifications: LPC802 v.1.1

Modifications: LPC802 v.1

Release date Data sheet status Change notice Supersedes

20190917

Product data sheet Added device revision 1D.

20190917

Product data sheet Updated device revision.

LPC802 v.1.7

LPC802 v.1.6

20180427

• •

Product data sheet Added LPC802UK part.

LPC802 v.1.5

Added text to

Section 9.22.4.4 “Deep power-down mode” : Five general-purpose

registers are available to store information during deep power-down mode.

• •

Updated

Section 9.22.1 “Internal oscillators” . Changed heading title.

Updated

Section 15.2 “Connecting power, clocks, and debug functions” : removed text:

connect the external crystal.

20180312

Product data sheet Updated Table 3 “Device revision table”.

LPC802 v.1.4

20180227

• •

Product data sheet LPC802 v.1.3

Added Figure 38 “Package outline WLCSP16 (1.86 ´1.86 ´ 0.3 mm)”.

Added Figure 42 “Reflow soldering for the WLCSP16 (4x4) package (1 of 3)”, Figure 43 “Reflow soldering for the WLCSP16 (4x4) package (2 of 3)”, and Figure 44 “Reflow soldering for the WLCSP16 (4x4) package (3 of 3)”.

• •

Updated title of Section 13.1 “Flash memory (EEPROM based)”.

Updated Table 12 “Static characteristics, supply pins”: Added condition: system clock = 1 MHz, VDD = 3.3 V.

Updated Table 16 “Dynamic characteristic: FRO”: Max values: FRO clock frequency; Condition:  20  C  T amb  70  C and FRO clock frequency; Condition:  40  C  T amb  105  C. 20180209

• •

Product data sheet Updated Section 2 “Features and benefits”.

LPC802 v.1.2

Updated Table 5 “Movable functions (assign to pins PIO0_0 to PIO0_5, PIO0_7 to PIO0_17 through switch matrix)”.

• •

Added level shifter functionality to Section 9.8 “I/O configuration”.

Updated Table 16 “Dynamic characteristic: FRO”: Changed frequencies to 9 MHz, 12 MHz, and 15 MHz. Added Condition:  20  C  T amb  70  C and Condition:  40  C  T amb  70  C.

20171222

• • •

Product data sheet Updated Figure 4 “LPC802 block diagram”.

Updated Figure 12 “LPC802 clock generation”.

LPC802 v.1.1

Updated Table 7 “Peripheral configuration in reduced power modes”: In deep-sleep mode flash is on standby.

20171222

Product data sheet LPC802 v.1

Updated Figure 21 “High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH” at 1.8 V.

20171218 Product data sheet LPC802

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21. Legal information

21.1 Data sheet status Document status

[1][2]

Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet

Product status

[3]

Development Qualification Production

Definition

This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

21.2 Definitions Draft —

The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet —

A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification —

The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

21.3 Disclaimers Limited warranty and liability —

Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale

of NXP Semiconductors.

Right to make changes —

NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use —

NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications —

Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors LPC802

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products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values —

Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale —

NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license —

intellectual property rights.

Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or

Export control —

This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products —

Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I 2 C-bus —

logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

salesaddresses@nxp.com

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23. Contents

1 2

3 4

4.1

General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

5

6

7

7.1

7.2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pinning information . . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Movable functions . . . . . . . . . . . . . . . . . . . . . . 13

9 Functional description . . . . . . . . . . . . . . . . . . 14

9.1 9.2 9.3 9.4 9.5

9.6 9.6.1 9.6.2 9.7 9.8

9.8.1

9.9 9.10 9.10.1 9.11

ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 14 On-chip flash program memory . . . . . . . . . . . 14 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 14 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Nested Vectored Interrupt Controller (NVIC) . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16 System tick timer . . . . . . . . . . . . . . . . . . . . . . 16 I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 16

Standard I/O pad configuration. . . . . . . . . . . . 17

Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 18 Fast General-Purpose parallel I/O (GPIO) . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.11.1 9.12 9.12.1 9.13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 USART0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.13.1 9.14 9.14.1 9.15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus interface (I2C0) . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.15.1

9.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.16

General-purpose 32-bit timers/external event counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 21 9.16.1 9.17 9.17.1

9.18 9.18.1 9.19

9.19.1

9.20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Windowed WatchDog Timer (WWDT) . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Self-Wake-up Timer (WKT). . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Analog comparator (ACMP) . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Analog-to-Digital Converter (ADC) . . . . . . . . . 24 9.20.1 9.21 9.21.1

9.22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clocking and power control . . . . . . . . . . . . . . 25

9.22.1 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 28 9.22.1.1 Free Running Oscillator (FRO) . . . . . . . . . . . . 28 9.22.1.2 Low Power Oscillator (LPOsc) . . . . . . . . . . . . 28

LPC802

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.8 — 25 September 2019

9.22.2 9.22.3 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.22.4

9.22.5

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.22.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.22.4.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 29 9.22.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 29

9.22.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 30

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 31 9.23 9.23.1

9.23.2

9.23.3

System control . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Brownout detection . . . . . . . . . . . . . . . . . . . . 32

Code security (Code Read Protection - CRP) 33 9.23.4 9.23.5

9.24

APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 33 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Emulation and debugging . . . . . . . . . . . . . . . 34

10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 35

11

12

12.1 12.2

12.2.1

12.3

12.3.1

Thermal characteristics . . . . . . . . . . . . . . . . . 37

Static characteristics . . . . . . . . . . . . . . . . . . . 38

General operating conditions . . . . . . . . . . . . . 38 Power consumption . . . . . . . . . . . . . . . . . . . . 38

Peripheral power consumption. . . . . . . . . . . . 42

Pin characteristics . . . . . . . . . . . . . . . . . . . . . 43

Electrical pin characteristics. . . . . . . . . . . . . . 45

13 Dynamic characteristics . . . . . . . . . . . . . . . . . 48

13.1 13.2

13.7

13.8

Flash memory (EEPROM based). . . . . . . . . . 48 FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13.3 13.4 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 WKTCLKIN pin (wake-up clock input) . . . . . . 49 13.5 I 2

C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 51

USART interface . . . . . . . . . . . . . . . . . . . . . . 54

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 55

14

14.1

14.2

14.2.1

14.3

15

15.1 15.2

15.3

15.4 15.5

Characteristics of analog peripherals . . . . . . 55

BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ADC input impedance . . . . . . . . . . . . . . . . . . 58

Comparator and internal voltage reference . . 59

Application information . . . . . . . . . . . . . . . . . 62

Start-up behavior . . . . . . . . . . . . . . . . . . . . . . 62 Connecting power, clocks, and debug functions . 62

I/O power consumption . . . . . . . . . . . . . . . . . 64

Termination of unused pins . . . . . . . . . . . . . . 65 Pin states in different power modes . . . . . . . . 65

16

17

18 19

20

21

21.1 21.2 21.3

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 66

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 76 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Revision history . . . . . . . . . . . . . . . . . . . . . . . 77

Legal information . . . . . . . . . . . . . . . . . . . . . . 78

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 78 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 78

© NXP Semiconductors N.V. 2019. All rights reserved.

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NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller

21.4

22

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Contact information. . . . . . . . . . . . . . . . . . . . . 79

23 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

LPC802

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.8 — 25 September 2019

© NXP Semiconductors N.V. 2019. All rights reserved.

81 of 81

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