NXP i.MX257 Reference guide

NXP i.MX257 Reference guide
i.MX25
Multimedia Applications
Processor Reference Manual
Supports
i.MX251 (MCIMX251)
i.MX253 (MCIMX253)
i.MX255 (MCIMX255)
i.MX257 (MCIMX257)
i.MX258 (MCIMX258)
IMX25RM
Rev. 2
01/2011
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Contents
Paragraph
Number
Title
Page
Number
Contents
Chapter 1
IC Architecture Overview
1.1
1.1.1
1.2
1.2.1
1.2.2
1.2.3
i.MX25 Overview ............................................................................................................ 1-1
Key Features ................................................................................................................ 1-2
Architecture Overview..................................................................................................... 1-3
Functional Domains Overview .................................................................................... 1-3
Advanced Power Management Overview.................................................................... 1-4
Modules Inventory ....................................................................................................... 1-5
Chapter 2
Memory Map
2.1
2.2
System Memory Map....................................................................................................... 2-1
SDMA Peripheral Memory Map ..................................................................................... 2-5
Chapter 3
Interrupts and DMA Events
3.1
3.2
ARM926 Platform Interrupts........................................................................................... 3-1
SDMA Event Mapping .................................................................................................... 3-3
Chapter 4
External Signals and Pin Multiplexing
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.5
4.6
IOMUX Overview ........................................................................................................... 4-1
Pin-Muxing Control ......................................................................................................... 4-3
Software Mux Control Registers (SW_MUX_CTL)................................................... 4-3
SW_SELECT_INPUT Register Definition ................................................................. 4-5
Pin-Setting Control .......................................................................................................... 4-6
Software Pad Control Registers (SW_PAD_CTL) ...................................................... 4-7
Software Pad Group Control Registers (SW_PAD_CTL_GRP) ................................. 4-9
Special Functionality ..................................................................................................... 4-13
General Purpose Register (IOMUXC_GPR1) ........................................................... 4-13
Interrupt Observe Control Register (IOMUXC_OBSERVE_INT_MUX)................ 4-14
Loopback and GPIO Capture..................................................................................... 4-17
Boot-Related Pins ...................................................................................................... 4-18
Special Pins................................................................................................................ 4-19
Register Memory Map ................................................................................................... 4-19
Daisy Chain List ............................................................................................................ 4-30
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Paragraph
Number
4.7
4.7.1
4.7.2
Title
Page
Number
Pin Multiplexing ............................................................................................................ 4-37
Pin Multiplexing Overview........................................................................................ 4-37
Detailed Pin Multiplexing Description ...................................................................... 4-39
Chapter 5
Clock Distribution
5.1
5.2
5.3
5.4
External Clock Sources.................................................................................................... 5-1
PLLs................................................................................................................................. 5-2
Clock Gating .................................................................................................................... 5-2
Core PLL Clock Generation ............................................................................................ 5-2
Chapter 6
Reset
6.1
6.2
6.3
6.4
Reset Types ...................................................................................................................... 6-1
Reset Sources ................................................................................................................... 6-1
Reset State Machine......................................................................................................... 6-1
Reset Sequence ................................................................................................................ 6-2
Chapter 7
System Boot
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.8
7.8.1
Overview.......................................................................................................................... 7-1
Boot Sources .................................................................................................................... 7-1
Boot Modes...................................................................................................................... 7-2
Boot Configuration ...................................................................................................... 7-2
Boot Flow Diagram ..................................................................................................... 7-7
Internal Boot Mode (BOOT_MODE[1:0]=00)............................................................ 7-8
External Boot Mode (BOOT_MODE[1:0] = 10)....................................................... 7-29
UART/USB Serial Download Mode (BOOT_MODE[1:0]=11)................................ 7-29
Exception Handling ....................................................................................................... 7-35
Error Logging ................................................................................................................ 7-35
USB Low-Power Boot Mode ......................................................................................... 7-35
High Assurance Boot (HAB) ......................................................................................... 7-38
High-Assurance Boot (HAB) Security Types............................................................ 7-38
Function Prototypes ................................................................................................... 7-41
API Jump Table Addresses ........................................................................................ 7-43
DryIce Initialization................................................................................................... 7-43
Serial Download protocol .............................................................................................. 7-44
Get Status................................................................................................................... 7-45
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Contents
Paragraph
Number
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.9
7.9.1
7.9.2
7.10
7.11
7.11.1
7.11.2
Title
Page
Number
Read Memory ............................................................................................................ 7-45
Write Memory............................................................................................................ 7-46
Re-enumerate ............................................................................................................. 7-46
Write File ................................................................................................................... 7-46
Completed.................................................................................................................. 7-47
Flash Code Image Detection.......................................................................................... 7-48
Overview.................................................................................................................... 7-48
Impact of Flash Code Image Detection ..................................................................... 7-48
Boot Image Redundancy on NAND Devices................................................................. 7-48
Booting From a NAND Device...................................................................................... 7-50
Overview.................................................................................................................... 7-50
Flash Header Details.................................................................................................. 7-54
Chapter 8
Power Management
8.1
8.1.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
Power Domains ................................................................................................................ 8-1
Power-Supply Requirements ....................................................................................... 8-1
Power Saving Methodology............................................................................................. 8-1
Active Power Savings .................................................................................................. 8-1
Leakage Power Saving................................................................................................. 8-2
Power Modes ............................................................................................................... 8-2
Power-Up and Power-Down Sequence ............................................................................ 8-3
Power-Up Sequence..................................................................................................... 8-3
Chapter 9
1-Wire Module (1-Wire)
9.1
9.1.1
9.1.2
9.2
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
Overview.......................................................................................................................... 9-1
Features........................................................................................................................ 9-1
Modes of Operation ..................................................................................................... 9-2
External Signals ............................................................................................................... 9-2
Memory Map and Register Definition ............................................................................. 9-2
Memory Map ............................................................................................................... 9-2
Register Descriptions ................................................................................................... 9-2
Functional Description..................................................................................................... 9-8
Normal Operating Modes ............................................................................................ 9-8
Low Power Mode....................................................................................................... 9-11
Clocks ........................................................................................................................ 9-11
Reset........................................................................................................................... 9-11
Interrupts.................................................................................................................... 9-11
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Contents
Paragraph
Number
Title
Page
Number
Chapter 10
ARM9 Platform Overview
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
10.2.10
10.2.11
10.2.12
10.3
10.4
10.5
10.5.1
10.5.2
10.5.3
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.7
10.7.1
10.7.2
10.8
10.8.1
10.8.2
10.8.3
10.8.4
10.9
10.9.1
10.9.2
Introduction.................................................................................................................... 10-1
ARM9 Platform Submodules......................................................................................... 10-2
ARM926EJ-S Processor ............................................................................................ 10-2
ARM9 Embedded Trace Macrocell & Embedded Trace Buffer ............................... 10-3
5x5 Multi-Layer AHB Crossbar Switch (MAX) ....................................................... 10-3
ARM Abort Processing Engine (AAPE) ................................................................... 10-4
ARM Simple Interrupt Controller (ASIC)................................................................. 10-5
ROM Controller and BIST Engine (ROMC) ............................................................. 10-5
AHB <-> IP-Bus Interface (AIPS) ............................................................................ 10-5
MAX Internal Slave Port Muxes (MAXMUX) ......................................................... 10-8
ROM Patch (ROMPATCH)........................................................................................ 10-9
Clock Control Module (CLKCTL) .......................................................................... 10-10
Just Another Module (JAM) .................................................................................... 10-11
Test Wrapper............................................................................................................ 10-11
ARM9 Platform Hierarchy .......................................................................................... 10-12
JTAG ID Register......................................................................................................... 10-12
System Memory Map................................................................................................... 10-13
ARM9 Platform Memory Map ................................................................................ 10-14
External Boot ........................................................................................................... 10-15
Memory Map Considerations .................................................................................. 10-15
Platform Clocking........................................................................................................ 10-15
ARM926EJ-S Clock Considerations ....................................................................... 10-15
ARM926EJ-S JTAG Port Clocking Considerations ................................................ 10-16
External Alternate Bus Master Interfaces ................................................................ 10-16
External Secondary AHB Ports ............................................................................... 10-17
Platform Resets ............................................................................................................ 10-17
hreset_b.................................................................................................................... 10-17
POR and JTAG_TRST_B ........................................................................................ 10-17
Power Management ..................................................................................................... 10-18
Register Level Clock Gating.................................................................................... 10-18
Block Level Clock Gating ....................................................................................... 10-18
External Clock Gating ............................................................................................. 10-18
Well Biasing............................................................................................................. 10-19
Platform AHB Interfaces ............................................................................................. 10-19
Definition of AHB-Lite ........................................................................................... 10-19
Alternate Bus Master Ports ...................................................................................... 10-19
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Contents
Paragraph
Number
Title
Page
Number
Chapter 11
ARM9 Platform AAPE
11.1
11.1.1
11.1.2
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
Introduction.................................................................................................................... 11-1
Overview.................................................................................................................... 11-1
Features...................................................................................................................... 11-2
Memory Map and Register Definition ........................................................................... 11-3
Memory Map ............................................................................................................. 11-3
Register Summary...................................................................................................... 11-4
Register Descriptions ................................................................................................. 11-4
AAPE Functional Description ....................................................................................... 11-8
D-AHB Abort Tracking, Abort Forcing, and Data Override .................................... 11-8
I-AHB Abort Tracking and Data Override ................................................................ 11-8
Chapter 12
Advanced Technology Attachment (ATA)
12.1
12.1.1
12.1.2
12.2
12.2.1
12.2.2
12.3
12.4
12.4.1
12.4.2
12.4.3
12.5
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.5.6
12.5.7
12.6
Overview........................................................................................................................ 12-1
Features...................................................................................................................... 12-3
Modes of Operation ................................................................................................... 12-3
External Signal Description ........................................................................................... 12-4
Signal Descriptions .................................................................................................... 12-5
ATA Bus Timing ........................................................................................................ 12-6
Advanced DMA in DMA Master Mode ...................................................................... 12-15
Memory Map and Register Definitions ....................................................................... 12-17
Memory Map ........................................................................................................... 12-17
Register Summary.................................................................................................... 12-19
Register Descriptions ............................................................................................... 12-23
Functional Description................................................................................................. 12-40
Resetting the ATA Bus............................................................................................. 12-41
Programming ATA Bus Timing and iordy_en ......................................................... 12-41
Access to ATA Bus in PIO Mode ............................................................................ 12-41
Receiving Data from ATA Bus in DMA Slave Mode.............................................. 12-42
Transmitting Data to ATA Bus in DMA Slave Mode .............................................. 12-43
Using DMA Master Mode to Receive Data From the ATA Bus ............................. 12-44
Using DMA Master Mode To Transmit Data to the ATA bus ................................. 12-45
Initialization and Application of ATA.......................................................................... 12-46
Chapter 13
Digital Audio Multiplexer (AUDMUX)
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Contents
Paragraph
Number
13.1
13.1.1
13.1.2
13.2
13.3
13.3.1
13.3.2
13.3.3
13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
Title
Page
Number
Overview........................................................................................................................ 13-2
Features...................................................................................................................... 13-4
Modes of Operation ................................................................................................... 13-4
External Signal Description ........................................................................................... 13-4
Memory Map and Register Definitions ......................................................................... 13-5
Memory Map ............................................................................................................. 13-5
Register Summary...................................................................................................... 13-5
Register Descriptions ................................................................................................. 13-6
Functional Description................................................................................................. 13-13
AUDMUX Ports Overview...................................................................................... 13-13
Operating Modes...................................................................................................... 13-14
AUDMUX Default Configuration ........................................................................... 13-30
Connectivity Between Ports..................................................................................... 13-31
AUDMUX Clocking ................................................................................................ 13-34
Chapter 14
ARM926EJ-S Simple Interrupt Controller (ASIC)
14.1
14.1.1
14.2
14.3
14.3.1
14.3.2
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
Introduction.................................................................................................................... 14-1
Features...................................................................................................................... 14-1
Overview........................................................................................................................ 14-2
Interrupt Controller Programming Model...................................................................... 14-3
Register Summary...................................................................................................... 14-3
Detailed Register Descriptions .................................................................................. 14-5
ARM926EJ-S Interrupt Controller Operation ............................................................. 14-20
ARM926EJ-S Prioritization of Exception Sources ................................................. 14-20
ASIC Prioritization of Interrupt Sources ................................................................. 14-20
Assigning and Enabling Interrupt Sources .............................................................. 14-20
Enabling Interrupts Sources..................................................................................... 14-21
Writing Reentrant Normal Interrupt Routines ......................................................... 14-21
Low Power Entry Sequence..................................................................................... 14-22
AHB Interface of ASIC ........................................................................................... 14-23
Chapter 15
Clock Controller Module (CCM)
15.1
15.1.1
15.1.2
15.1.3
15.2
Introduction.................................................................................................................... 15-1
Overview.................................................................................................................... 15-1
Features...................................................................................................................... 15-2
Modes of Operation ................................................................................................... 15-2
External Signal Description ........................................................................................... 15-2
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Paragraph
Number
15.3
15.3.1
15.3.2
15.3.3
15.4
15.4.1
15.4.2
15.4.3
Title
Page
Number
Memory Map and Register Definition ........................................................................... 15-3
Memory Map ............................................................................................................. 15-3
Register Summary...................................................................................................... 15-4
Register Descriptions ................................................................................................. 15-9
Functional Description................................................................................................. 15-47
Clock Control and Gating ........................................................................................ 15-47
Reset Module ........................................................................................................... 15-49
Power Management ................................................................................................. 15-51
Chapter 16
ARM9 Platform Clock Control Module (CLKCTL)
16.1
16.2
16.3
16.3.1
16.3.2
Introduction.................................................................................................................... 16-1
Clock Gating .................................................................................................................. 16-3
Memory Map and Register Definition ........................................................................... 16-4
Register Summary...................................................................................................... 16-4
Register Descriptions ................................................................................................. 16-5
Chapter 17
CMOS Sensor Interface (CSI)
17.1
17.2
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
17.4
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
17.4.6
17.4.7
17.4.8
17.4.9
17.4.10
CSI Architecture ............................................................................................................ 17-2
CSI Interface Signal Description ................................................................................... 17-3
Principles of Operation .................................................................................................. 17-3
Data Transfer With The Embedded DMA Controllers .............................................. 17-3
Gated Clock Mode ..................................................................................................... 17-4
Non-Gated Clock Mode............................................................................................. 17-5
CCIR656 Interlace Mode........................................................................................... 17-5
CCIR656 Progressive Mode ...................................................................................... 17-7
Error Correction for CCIR656 Coding ...................................................................... 17-8
Interrupt Generation....................................................................................................... 17-8
Start Of Frame Interrupt (SOF_INT)......................................................................... 17-8
End Of Frame Interrupt (EOF_INT).......................................................................... 17-9
Change Of Field Interrupt (COF_INT)...................................................................... 17-9
CCIR Error Interrupt (ECC_INT).............................................................................. 17-9
RxFIFO Full Interrupt (RxFF_INT) .......................................................................... 17-9
Statistic FIFO Full Interrupt (STATFF_INT) .......................................................... 17-10
RxFIFO Overrun Interrupt (RFF_OR_INT)............................................................ 17-10
Statistic FIFO Overrun Interrupt (SFF_OR_INT) ................................................... 17-10
Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1)............. 17-10
Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2)............. 17-10
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Paragraph
Number
17.4.11
17.4.12
17.5
17.5.1
17.5.2
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.6.5
17.6.6
17.6.7
17.6.8
17.6.9
17.6.10
17.6.11
17.6.12
17.6.13
17.6.14
17.6.15
Title
Page
Number
Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF).............. 17-10
AHB Bus Response Error Interrupt (HRESP_ERR_INT) ...................................... 17-10
Data Packing Style....................................................................................................... 17-10
RX FIFO Path .......................................................................................................... 17-11
STAT FIFO Path ...................................................................................................... 17-12
Memory Map and Register Definition ......................................................................... 17-13
CSI Memory Map .................................................................................................... 17-13
Register Summary.................................................................................................... 17-13
CSI Control Register 1 (CSICR1) ........................................................................... 17-17
CSI Control Register 2 (CSICR2) ........................................................................... 17-21
CSI Control Register 3 (CSICR3) ........................................................................... 17-22
CSI STATFIFO Register (CSISTATFIFO) .............................................................. 17-24
CSI RxFIFO Register (CSIRFIFO) ......................................................................... 17-25
CSI RX Count Register (CSIRXCNT) .................................................................... 17-25
CSI Status Register (CSISR) ................................................................................... 17-26
CSI STATFIFO DMA Start Address Register (CSIDMASA-STATFIFO).............. 17-29
CSI STATFIFO DMA Transfer Size Register (CSIDMATS-STATFIFO)............... 17-30
CSI Frame Buffer1 DMA Start Address Register (CSIDMASA-FB1)................... 17-30
CSI Frame Buffer2 DMA Start Address Register (CSIDMASA-FB2)................... 17-31
CSI Frame Buffer Parameter Register (CSIFBUF_PARA) ..................................... 17-32
CSI Image Parameter Register (CSIIMAG_PARA) ................................................ 17-32
Chapter 18
Configurable Serial Peripheral Interface (CSPI)
18.1
18.1.1
18.1.2
18.2
18.3
18.3.1
18.3.2
18.3.3
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
Overview........................................................................................................................ 18-1
Features...................................................................................................................... 18-1
Modes and Operations ............................................................................................... 18-2
External Signals ............................................................................................................. 18-2
Memory Map and Register Definition ........................................................................... 18-3
Memory Map ............................................................................................................. 18-3
Register Summary...................................................................................................... 18-4
Register Descriptions ................................................................................................. 18-5
Functional Description................................................................................................. 18-15
Operating Modes...................................................................................................... 18-16
Low Power Modes ................................................................................................... 18-16
Operations................................................................................................................ 18-16
Clocks ...................................................................................................................... 18-22
Reset......................................................................................................................... 18-22
Interrupts.................................................................................................................. 18-22
DMA ........................................................................................................................ 18-23
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Paragraph
Number
18.4.8
18.5
18.6
Title
Page
Number
Byte Order................................................................................................................ 18-24
Initialization ................................................................................................................. 18-24
Applications ................................................................................................................. 18-25
Chapter 19
Embedded Cross Trigger (ECT)
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.7.1
19.7.2
19.7.3
19.8
19.9
19.10
19.10.1
19.10.2
19.10.3
19.10.4
19.10.5
19.10.6
19.10.7
19.10.8
19.10.9
19.10.10
19.10.11
19.10.12
19.10.13
19.10.14
19.10.15
19.10.16
19.10.17
19.10.18
19.10.19
19.10.20
19.10.21
Introduction.................................................................................................................... 19-1
Overview........................................................................................................................ 19-3
Features .......................................................................................................................... 19-3
Modes of Operation ....................................................................................................... 19-4
Signals Description ........................................................................................................ 19-4
Overview........................................................................................................................ 19-4
Detailed Signal Descriptions ......................................................................................... 19-9
EXTENDED_CTI_X signals (X = 0,1,2).................................................................. 19-9
CTM signals (X= 0,1,2 / Y = 0,1,2,3)...................................................................... 19-11
Global signals (X = 0,1,2)........................................................................................ 19-12
Memory Map/Register Definition................................................................................ 19-12
Register Summary........................................................................................................ 19-13
Register Descriptions ................................................................................................... 19-17
CTICONTROL Register .......................................................................................... 19-17
CTISTATUS Register .............................................................................................. 19-18
CTILOCK Register.................................................................................................. 19-18
CTIPROTECTION Register .................................................................................... 19-19
CTIINTACK Register .............................................................................................. 19-19
CTIAPPSET Register .............................................................................................. 19-20
CTIAPPCLEAR Register ........................................................................................ 19-21
CTIAPPPULSE Register ......................................................................................... 19-21
CTIINEN0–7 Register ............................................................................................. 19-22
CTIOUTEN0–7 Register ......................................................................................... 19-22
CTITRIGINSTATUS Register................................................................................. 19-23
CTITRIGOUTSTATUS Register............................................................................. 19-24
CTICHINSTATUS Register..................................................................................... 19-24
CTICHOUTSTATUS Register................................................................................. 19-25
CTITCR Register ..................................................................................................... 19-25
CTIITIP0 Register ................................................................................................... 19-26
CTIITIP1 Register ................................................................................................... 19-26
CTIITIP2 Register ................................................................................................... 19-27
CTIITIP3 Register ................................................................................................... 19-28
CTIITOP0 Register.................................................................................................. 19-28
CTIITOP1 Register.................................................................................................. 19-29
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Paragraph
Number
19.10.22
19.10.23
19.10.24
19.11
19.12
19.12.1
19.12.2
19.12.3
19.13
19.14
19.15
19.16
Title
Page
Number
CTIITOP2 Register.................................................................................................. 19-29
CTIITOP3 Register.................................................................................................. 19-30
ARM Identification Registers .................................................................................. 19-30
Functional Description................................................................................................. 19-35
Extended Cross Trigger Interface (EXTENDED_CTI)............................................... 19-35
Wrapper ................................................................................................................... 19-36
ECT_CTI ................................................................................................................. 19-37
IPS2AHB ................................................................................................................. 19-39
Cross Trigger Matrix (CTM) ....................................................................................... 19-39
Initialization/Application Information ......................................................................... 19-41
Initialization ................................................................................................................. 19-41
Application information............................................................................................... 19-42
Chapter 20
External Memory Interface (EMI)
20.1
20.1.1
20.2
20.3
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
Overview........................................................................................................................ 20-1
Features...................................................................................................................... 20-3
EMI Input/Output Signals.............................................................................................. 20-3
Memory Map/Register Definition................................................................................ 20-11
Functional Description................................................................................................. 20-12
Multi-Master Memory Interface (M3IF) ................................................................. 20-12
NAND Flash Controller (NFC) ............................................................................... 20-13
Enhanced SDRAM Controller (ESDRAMC) .......................................................... 20-14
EMI AHB Multiplexer............................................................................................. 20-16
EMI I/O Multiplexer ................................................................................................ 20-18
Chapter 21
Enhanced Periodic Interrupt Timer (EPIT)
21.1
21.1.1
21.1.2
21.2
21.3
21.3.1
21.3.2
21.3.3
21.4
21.4.1
21.4.2
Overview........................................................................................................................ 21-1
Features...................................................................................................................... 21-2
Modes and Operations ............................................................................................... 21-2
External Signals ............................................................................................................. 21-3
Memory Map and Register Definitions ......................................................................... 21-3
Memory Map ............................................................................................................. 21-3
Register Summary...................................................................................................... 21-4
Register Descriptions ................................................................................................. 21-4
Functional Description................................................................................................. 21-10
Operating Modes...................................................................................................... 21-10
Operations................................................................................................................ 21-10
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Number
21.4.3
21.4.4
21.5
21.5.1
Title
Page
Number
Clocks ...................................................................................................................... 21-11
Compare Event ........................................................................................................ 21-12
Initialization/Application Information ......................................................................... 21-13
Change of Clock Source .......................................................................................... 21-13
Chapter 22
Enhanced Serial Audio Interface (ESAI)
22.1
22.1.1
22.1.2
22.2
22.2.1
22.2.2
22.2.3
22.2.4
22.2.5
22.2.6
22.2.7
22.2.8
22.2.9
22.2.10
22.2.11
22.2.12
22.2.13
22.3
22.3.1
22.3.2
22.3.3
22.4
22.4.1
22.4.2
22.4.3
22.5
22.5.1
22.5.2
Introduction.................................................................................................................... 22-1
Features...................................................................................................................... 22-3
Modes of Operation ................................................................................................... 22-3
External Signal Description ........................................................................................... 22-5
Serial Transmit 0 Data Pin (SDO0) ........................................................................... 22-5
Serial Transmit 1 Data Pin (SDO1) ........................................................................... 22-5
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3)................................................. 22-5
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)................................................. 22-6
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)................................................. 22-6
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)................................................. 22-6
Receiver Serial Clock (SCKR) .................................................................................. 22-7
Transmitter Serial Clock (SCKT) .............................................................................. 22-8
Frame Sync for Receiver (FSR)................................................................................. 22-9
Frame Sync for Transmitter (FST) .......................................................................... 22-10
High Frequency Clock for Transmitter (HCKT) ..................................................... 22-10
High Frequency Clock for Receiver (HCKR).......................................................... 22-10
Serial I/O Flags ........................................................................................................ 22-11
Memory Map and Register Definition ......................................................................... 22-11
Memory Map ........................................................................................................... 22-11
Register Summary.................................................................................................... 22-13
Register Descriptions ............................................................................................... 22-18
Functional Description................................................................................................. 22-62
ESAI After Reset ..................................................................................................... 22-62
ESAI Interrupt Requests .......................................................................................... 22-63
ESAI DMA Requests from the FIFOs..................................................................... 22-64
Initialization Information ............................................................................................. 22-64
ESAI Initialization ................................................................................................... 22-64
ESAI Initialization Examples .................................................................................. 22-65
Chapter 23
Enhanced Secured Digital Host Controller (eSDHC)
23.1
Overview........................................................................................................................ 23-1
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Paragraph
Number
23.1.1
23.1.2
23.2
23.2.1
23.2.2
23.3
23.3.1
23.3.2
23.3.3
23.4
23.4.1
23.4.2
23.4.3
23.4.4
23.4.5
23.4.6
23.4.7
23.4.8
23.4.9
23.5
23.5.1
23.5.2
23.5.3
23.5.4
23.6
23.7
23.7.1
Title
Page
Number
.Features..................................................................................................................... 23-2
Modes of Operation ................................................................................................... 23-3
External Signals ............................................................................................................. 23-3
Overview.................................................................................................................... 23-3
Signal Descriptions .................................................................................................... 23-4
Memory Map and Register Definition ........................................................................... 23-5
Memory Map ............................................................................................................. 23-5
Register Summary...................................................................................................... 23-7
Register Descriptions ............................................................................................... 23-10
Functional Description................................................................................................. 23-45
Data Buffer............................................................................................................... 23-45
DMA AHB Interface ............................................................................................... 23-51
Register Bank Access using IP Bus Interface.......................................................... 23-52
SD Protocol Unit...................................................................................................... 23-52
Clock and Reset Manager Submodule (CRM) ........................................................ 23-54
SD Clock Generator................................................................................................. 23-54
SDIO Card Interrupts............................................................................................... 23-55
Card Insertion and Removal Detection.................................................................... 23-56
Power Management and Wake-up Events ............................................................... 23-56
Initialization/Application Information ......................................................................... 23-57
Command Send and Response Receive Basic Operation ........................................ 23-57
Card Identification Mode......................................................................................... 23-58
Card Accesses .......................................................................................................... 23-64
Switch Function ....................................................................................................... 23-70
MMC/SD/SDIO/CE-ATA Card Commands ................................................................ 23-73
Software Restrictions ................................................................................................... 23-78
Initialization Active ................................................................................................. 23-78
Chapter 24
Enhanced SDRAM Controller (ESDRAMC)
24.1
24.1.1
24.1.2
24.1.3
24.1.4
24.1.5
24.1.6
24.1.7
24.1.8
24.1.9
Overview........................................................................................................................ 24-3
SDRAM Command Controller .................................................................................. 24-3
Bank Models .............................................................................................................. 24-3
Row/Column Address Multiplexer ............................................................................ 24-3
ESDRAMC Control and Configuration Registers..................................................... 24-3
Refresh Request Counter ........................................................................................... 24-4
Command Sequencer ................................................................................................. 24-4
Size Logic .................................................................................................................. 24-4
Mobile/Low Power DDR (LPDDR) Interface ........................................................... 24-4
Features...................................................................................................................... 24-5
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Paragraph
Number
24.1.10
24.2
24.2.1
24.2.2
24.3
24.3.1
24.3.2
24.3.3
24.4
24.4.1
24.4.2
24.4.3
24.4.4
24.4.5
24.4.6
24.4.7
24.4.8
24.4.9
24.4.10
24.4.11
24.4.12
24.5
24.5.1
24.5.2
24.5.3
24.5.4
Title
Page
Number
Modes of Operation ................................................................................................... 24-6
External Signal Descriptions ......................................................................................... 24-7
Overview of Signals................................................................................................... 24-7
Detailed Signal Descriptions ..................................................................................... 24-8
Memory Map and Register Definition ........................................................................... 24-9
Memory Map ........................................................................................................... 24-10
Register Summary.................................................................................................... 24-10
Register Descriptions ............................................................................................... 24-13
Functional Description................................................................................................. 24-27
ESDRAMC Configurable Timing Parameters......................................................... 24-27
Enhanced SDRAM Controller Optimization Strategy............................................. 24-37
Address Multiplexing .............................................................................................. 24-43
Multiplexed Address Bus During Precharge or Load Mode Registers Modes........ 24-45
Refresh ..................................................................................................................... 24-46
Low Power Operating Modes .................................................................................. 24-47
SDRAM (SDR and LPDDR) Command Encoding................................................. 24-59
Normal Read/Write Mode ....................................................................................... 24-62
Precharge Command Mode ..................................................................................... 24-89
Auto-Refresh Mode ................................................................................................. 24-91
Manual Self-Refresh Mode...................................................................................... 24-92
Load Mode Register Mode ...................................................................................... 24-92
Initialization/Application Information ......................................................................... 24-94
Memory Device Selection........................................................................................ 24-94
Configuring the Controller for SDRAM Memory Arrays ....................................... 24-95
CAS Latency............................................................................................................ 24-95
SDRAM/LPDDR Initialization Sequence ............................................................... 24-95
Chapter 25
Fast Ethernet Controller (FEC)
25.1
25.1.1
25.2
25.2.1
25.2.2
25.2.3
25.2.4
25.3
25.3.1
25.3.2
25.3.3
Overview........................................................................................................................ 25-1
Features...................................................................................................................... 25-3
Modes of Operation ....................................................................................................... 25-4
Full- and Half-Duplex Operation............................................................................... 25-4
Interface Options........................................................................................................ 25-4
Address Recognition Options .................................................................................... 25-5
Internal Loopback ...................................................................................................... 25-5
Memory Map and Register Definition ........................................................................... 25-5
Top Level Module Memory Map............................................................................... 25-5
Detailed Memory Map (Control/Status Registers) .................................................... 25-6
Message Information Block (MIB) Counters Memory Map ..................................... 25-7
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Paragraph
Number
25.3.4
25.3.5
25.4
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.5
25.5.1
25.5.2
Title
Page
Number
MIIGSK Registers Memory Map ............................................................................ 25-10
Register Descriptions ............................................................................................... 25-10
Functional Description................................................................................................. 25-32
Network Interface Options....................................................................................... 25-32
FEC Frame Transmission ........................................................................................ 25-34
FEC Frame Reception.............................................................................................. 25-36
Full-Duplex Flow Control........................................................................................ 25-43
Internal and External Loopback............................................................................... 25-44
Initialization/Application Information ......................................................................... 25-44
Initialization Sequence............................................................................................. 25-44
Buffer Descriptors.................................................................................................... 25-46
Chapter 26
Controller Area Network (FlexCAN)
26.1
26.1.1
26.1.2
26.2
26.2.1
26.2.2
26.2.3
26.3
26.3.1
26.3.2
26.3.3
26.4
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.4.6
26.4.7
26.4.8
26.4.9
26.4.10
26.5
26.5.1
Introduction.................................................................................................................... 26-1
FlexCAN Module Features ........................................................................................ 26-3
Modes of Operation ................................................................................................... 26-3
External Signal Description ........................................................................................... 26-5
Overview.................................................................................................................... 26-5
CAN Rx Signal .......................................................................................................... 26-5
CAN Tx Signal .......................................................................................................... 26-5
Memory Map and Register Definition ........................................................................... 26-5
Memory Map ............................................................................................................. 26-5
Register Descriptions ................................................................................................. 26-6
Buffer Descriptions.................................................................................................. 26-25
Functional Description................................................................................................. 26-30
Overview.................................................................................................................. 26-30
Transmit Process...................................................................................................... 26-31
Arbitration Process .................................................................................................. 26-31
Receive Process ....................................................................................................... 26-32
Matching Process..................................................................................................... 26-34
Data Coherence........................................................................................................ 26-35
Rx FIFO ................................................................................................................... 26-38
CAN Protocol Related Features............................................................................... 26-39
Modes of Operation Detailed Descriptions ............................................................. 26-43
Interrupts.................................................................................................................. 26-46
Initialization/Application Information ......................................................................... 26-46
FlexCAN Initialization Sequence ............................................................................ 26-46
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Paragraph
Number
Title
Page
Number
Chapter 27
General Purpose Input/Output Module (GPIO)
27.1
27.1.1
27.2
27.3
27.3.1
27.3.2
27.3.3
27.4
27.4.1
27.4.2
27.5
27.5.1
27.5.2
Overview........................................................................................................................ 27-1
Features...................................................................................................................... 27-2
External Signal Description ........................................................................................... 27-2
Memory Map and Register Definition ........................................................................... 27-3
Memory Map ............................................................................................................. 27-3
Register Summary...................................................................................................... 27-3
Register Descriptions ................................................................................................. 27-5
GPIO Functional Description ...................................................................................... 27-11
Input/Output Signal Function .................................................................................. 27-11
Interrupt Control Unit .............................................................................................. 27-12
Initialization/Application Information ......................................................................... 27-12
GPIO Read Mode..................................................................................................... 27-12
GPIO Write Mode.................................................................................................... 27-12
Chapter 28
General Purpose Timer (GPT)
28.1
28.2
28.3
28.4
28.4.1
28.4.2
28.5
28.5.1
28.5.2
28.6
28.6.1
28.7
28.7.1
Overview........................................................................................................................ 28-2
Features .......................................................................................................................... 28-2
Modes of Operation ....................................................................................................... 28-2
External Signals ............................................................................................................. 28-3
Input Capture Trigger Signals (ipp_ind_capin[1:2]) ................................................. 28-3
Output Compare Signals (ipp_do_cmpout[1:3]) ....................................................... 28-3
Memory Map and Register Definition ........................................................................... 28-3
Memory Map ............................................................................................................. 28-3
Register Summary...................................................................................................... 28-4
Functional Description................................................................................................. 28-15
Operation ................................................................................................................. 28-15
Initialization/ Application Information ........................................................................ 28-19
Change of Clock Source .......................................................................................... 28-19
Chapter 29
Inter IC Module (I2C)
29.1
29.1.1
29.1.2
29.2
Overview........................................................................................................................ 29-1
Features...................................................................................................................... 29-3
Modes and Operations ............................................................................................... 29-3
External Signals ............................................................................................................. 29-3
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Paragraph
Number
29.3
29.3.1
29.3.2
29.3.3
29.4
29.4.1
29.4.2
29.4.3
29.4.4
29.4.5
29.4.6
29.4.7
29.4.8
29.4.9
29.4.10
29.4.11
29.4.12
29.5
29.5.1
29.5.2
29.5.3
29.5.4
29.5.5
29.5.6
29.5.7
29.6
Title
Page
Number
Memory Map and Register Definition ........................................................................... 29-4
Memory Map ............................................................................................................. 29-4
Register Summary...................................................................................................... 29-4
Register Descriptions ................................................................................................. 29-5
Functional Description................................................................................................. 29-11
I2C System Configuration........................................................................................ 29-11
I2C Protocol ............................................................................................................. 29-11
Arbitration Procedure .............................................................................................. 29-13
Clock Synchronization............................................................................................. 29-14
Handshaking ............................................................................................................ 29-14
Clock Stretching ...................................................................................................... 29-14
Peripheral Bus Accesses .......................................................................................... 29-14
Generation of Transfer Error on IP Bus................................................................... 29-15
Clocks ...................................................................................................................... 29-15
Reset......................................................................................................................... 29-15
Interrupts.................................................................................................................. 29-15
Byte Order................................................................................................................ 29-15
Initialization ................................................................................................................. 29-15
Initialization Sequence............................................................................................. 29-16
Generation of START .............................................................................................. 29-16
Post-Transfer Software Response ............................................................................ 29-16
Generation of STOP................................................................................................. 29-17
Generation of Repeated START .............................................................................. 29-17
Slave Mode .............................................................................................................. 29-17
Arbitration Lost........................................................................................................ 29-17
Software Restriction..................................................................................................... 29-22
Chapter 30
IC Identification Module (IIM)
30.1
30.1.1
30.1.2
30.2
30.3
30.3.1
30.3.2
30.3.3
30.4
30.4.1
30.4.2
Overview........................................................................................................................ 30-1
Features...................................................................................................................... 30-1
Modes of Operation ................................................................................................... 30-2
External Signal Description ........................................................................................... 30-2
Memory Map and Register Definition ........................................................................... 30-2
Memory Map ............................................................................................................. 30-2
Register Summary...................................................................................................... 30-3
Register Descriptions ................................................................................................. 30-5
Functional Description................................................................................................. 30-15
Fuse Functional Groups ........................................................................................... 30-15
Fusebox Interface..................................................................................................... 30-16
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Paragraph
Number
30.4.3
30.4.4
30.4.5
30.5
30.5.1
30.5.2
30.6
Title
Page
Number
Fuse Value Caching ................................................................................................. 30-21
Fuse Protection ........................................................................................................ 30-22
Fuse Bank Operations.............................................................................................. 30-24
Initialization/Application Information ......................................................................... 30-28
Initialization ............................................................................................................. 30-28
Programming ........................................................................................................... 30-29
Fuse Map...................................................................................................................... 30-32
Chapter 31
IPMUX
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.7.1
31.7.2
31.7.3
31.7.4
31.7.5
31.7.6
31.7.7
31.7.8
31.7.9
31.7.10
31.7.11
31.7.12
31.7.13
31.7.14
31.7.15
31.7.16
31.8
31.9
31.9.1
31.9.2
31.9.3
31.10
31.10.1
Introduction.................................................................................................................... 31-1
Overview........................................................................................................................ 31-2
Features .......................................................................................................................... 31-3
Modes of Operation ....................................................................................................... 31-3
External Signal Description ........................................................................................... 31-3
Overview........................................................................................................................ 31-3
Detailed Signal Descriptions ....................................................................................... 31-11
ipg_hard_async_reset_b........................................................................................... 31-11
master_clk................................................................................................................ 31-12
slave_clk .................................................................................................................. 31-12
ipt_se_gatedclk ........................................................................................................ 31-12
master_equal_slave .................................................................................................. 31-12
master_module_en_nonglobal ................................................................................. 31-12
master_module_en0, master_module_en1,… master_module_en33 ...................... 31-12
master_rdata[31:0] ................................................................................................... 31-12
master_xfr_err.......................................................................................................... 31-12
master_xfr_wait ....................................................................................................... 31-13
slave_ipg_clk_0, slave_ipg_clk_1,… slave_ipg_clk_33 ......................................... 31-13
slave_ipg_clk_s0, slave_ipg_clk_s1,… slave_ipg_clk_s33 .................................... 31-13
slave_module_en0, slave_module_en1,… slave_module_en33.............................. 31-13
slave_rdata0[31:0], slave_rdata1[31:0],… slave_rdata33[31:0].............................. 31-13
slave_xfr_err0, slave_xfr_err1,... slave_xfr_err33................................................... 31-13
slave_xfr_wait0, slave_xfr_wait1,... slave_xfr_wait33............................................ 31-13
Memory Map/Register Definition................................................................................ 31-14
Functional Description................................................................................................. 31-14
ipmux_mux (IPMUX MUX) ................................................................................... 31-14
ipmux_ipis (IPMUX IPS Interface Synchronizer)................................................... 31-16
ipmux_clock_gating (IPMUX Clock Gating).......................................................... 31-19
Application Information .............................................................................................. 31-20
Connecting the IPMUX in the SOC ........................................................................ 31-20
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Number
31.10.2
Title
Page
Number
Timing Diagrams ..................................................................................................... 31-23
Chapter 32
Keypad Port (KPP)
32.1
32.2
32.2.1
32.2.2
32.3
32.3.1
32.4
32.4.1
32.4.2
32.4.3
32.5
32.5.1
32.5.2
32.5.3
32.5.4
32.5.5
32.5.6
32.6
32.6.1
32.6.2
32.6.3
Introduction.................................................................................................................... 32-1
Overview........................................................................................................................ 32-2
Features...................................................................................................................... 32-2
Modes of Operation ................................................................................................... 32-2
External Signal Description ........................................................................................... 32-2
Overview.................................................................................................................... 32-2
Memory Map and Register Definition ........................................................................... 32-3
KPP Memory Map ..................................................................................................... 32-4
Register Summary...................................................................................................... 32-4
Register Descriptions ................................................................................................. 32-5
Functional Description................................................................................................... 32-9
Keypad Matrix Construction...................................................................................... 32-9
Keypad Port Configuration ........................................................................................ 32-9
Keypad Matrix Scanning ......................................................................................... 32-10
Keypad Standby ...................................................................................................... 32-10
Glitch Suppression on Keypad Inputs...................................................................... 32-10
Multiple Key Closures ............................................................................................. 32-11
Initialization/Application Information ......................................................................... 32-14
Typical Keypad Configuration and Scanning Sequence.......................................... 32-14
Key Press Interrupt Scanning Sequence .................................................................. 32-14
Additional Comments .............................................................................................. 32-14
Chapter 33
Liquid Crystal Display Controller (LCDC)
33.1
33.2
33.2.1
33.2.2
33.2.3
33.2.4
33.2.5
33.2.6
33.2.7
33.2.8
33.2.9
Introduction.................................................................................................................... 33-1
LCDC Operation............................................................................................................ 33-2
LCD Screen Format ................................................................................................... 33-3
Graphic Window on Screen ....................................................................................... 33-3
Panning ...................................................................................................................... 33-4
Display Data Mapping ............................................................................................... 33-4
Black-and-White Operation....................................................................................... 33-6
Greyscale Operation .................................................................................................. 33-6
Color Generation........................................................................................................ 33-7
Frame Rate Modulation Control (FRC)..................................................................... 33-9
Panel Interface Signals and Timing ......................................................................... 33-10
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Paragraph
Number
33.3
33.3.1
33.3.2
33.3.3
33.3.4
33.3.5
33.3.6
33.3.7
33.3.8
33.3.9
33.3.10
33.3.11
33.3.12
33.3.13
33.3.14
33.3.15
33.3.16
33.3.17
33.3.18
33.3.19
33.3.20
33.3.21
33.3.22
33.3.23
33.3.24
33.3.25
33.3.26
33.3.27
33.3.28
33.3.29
33.3.30
Title
Page
Number
Memory Map and Register Descriptions ..................................................................... 33-18
Memory Map ........................................................................................................... 33-18
Register Summary.................................................................................................... 33-19
Register Descriptions ............................................................................................... 33-22
LCDC Screen Start Address Register (LSSAR)...................................................... 33-23
LCDC Size Register (LSR)...................................................................................... 33-23
LCDC Virtual Page Width Register (LVPWR)........................................................ 33-24
LCDC Cursor Position Register (LCPR)................................................................. 33-25
LCDC Cursor Width, Height and Blink (LCWHBR).............................................. 33-26
LCDC Color Cursor Mapping Register (LCCMR) ................................................. 33-26
LCDC Panel Configuration Register (LPCR).......................................................... 33-28
LCDC Horizontal Configuration Register (LHCR)................................................. 33-30
LCDC Vertical Configuration Register (LVCR)...................................................... 33-31
LCDC Panning Offset Register (LPOR).................................................................. 33-32
LCDC Sharp Configuration Register (LSCR) ........................................................ 33-32
LCDC PWM Contrast Control Register (LPCCR).................................................. 33-34
LCDC DMA Control Register (LDCR)................................................................... 33-35
LCDC Refresh Mode Control Register (LRMCR).................................................. 33-36
LCDC Interrupt Configuration Register (LICR) ..................................................... 33-37
LCDC Interrupt Enable Register (LIER)................................................................. 33-38
LCDC Interrupt Status Register (LISR) .................................................................. 33-39
LCDC Graphic Window Start Address Register (LGWSAR)................................. 33-41
LCDC Graphic Window Size Register (LGWSR)................................................... 33-41
LCDC Graphic Window Virtual Page Width Register (LGWVPWR) .................... 33-42
LCDC Graphic Window Panning Offset Register (LGWPOR)............................... 33-43
LCDC Graphic Window Position Register (LGWPR) ............................................ 33-44
LCDC Graphic Window Control Register (LGWCR)............................................. 33-44
LCDC Graphic Window DMA Control Register (LGWDCR)................................ 33-45
LCDC AUS Mode Control Register (LAUSCR) ..................................................... 33-47
LCDC AUS Mode Cursor Control Register (LAUSCCR) ...................................... 33-48
Mapping RAMs: Background Lookup Table (BGLUT) and Graphic Window Lookup
Table (GWLUT) .................................................................................................. 33-48
Chapter 34
ARM9 Platform Multi-Layer AHB Crossbar Switch (MAX)
34.1
34.1.1
34.1.2
34.1.3
34.1.4
Introduction.................................................................................................................... 34-1
Overview.................................................................................................................... 34-1
Features...................................................................................................................... 34-3
Limitations ................................................................................................................. 34-3
General Operation...................................................................................................... 34-3
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Paragraph
Number
34.2
34.2.1
34.2.2
34.2.3
34.3
34.3.1
34.3.2
34.3.3
34.4
34.5
34.5.1
34.5.2
Title
Page
Number
MAX Registers .............................................................................................................. 34-4
Register Summary...................................................................................................... 34-4
MAX Register Descriptions....................................................................................... 34-6
Coherency ................................................................................................................ 34-10
Function ....................................................................................................................... 34-11
Arbitration................................................................................................................ 34-11
Priority Assignment ................................................................................................. 34-12
Slave Port Functionality........................................................................................... 34-13
Initialization/Application Information ......................................................................... 34-20
Interface ....................................................................................................................... 34-21
Master Ports ............................................................................................................. 34-21
Slave Ports ............................................................................................................... 34-22
Chapter 35
Multi-Master Memory Interface (M3IF)
35.1
35.1.1
35.1.2
35.2
35.2.1
35.2.2
35.2.3
35.3
35.3.1
35.3.2
35.3.3
35.3.4
35.3.5
35.4
35.4.1
Overview........................................................................................................................ 35-3
M3IF Interfaces.......................................................................................................... 35-3
Features...................................................................................................................... 35-4
Memory Map and Register Definition ........................................................................... 35-5
Memory Map ............................................................................................................. 35-5
Register Summary...................................................................................................... 35-7
Register Descriptions ............................................................................................... 35-10
Functional Description................................................................................................. 35-22
Master Port Gasket (MPG) ...................................................................................... 35-22
Master Port Gasket 64 (MPG64) ............................................................................. 35-35
M3IF Arbitration (M3A) ......................................................................................... 35-37
Master Arbitration and Buffering (MAB)................................................................ 35-41
Watermark and Snooping Logic .............................................................................. 35-45
Initialization/Application Information ......................................................................... 35-47
M3IF in a System..................................................................................................... 35-47
Chapter 36
NAND Flash Controller (NFC)
36.1
36.1.1
36.1.2
36.2
36.2.1
36.2.2
Overview........................................................................................................................ 36-1
Features...................................................................................................................... 36-2
Modes of Operation ................................................................................................... 36-3
External Signal Description ........................................................................................... 36-3
Overview of Signals................................................................................................... 36-4
Detailed Signal Descriptions ..................................................................................... 36-5
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Paragraph
Number
36.3
36.3.1
36.4
36.4.1
36.4.2
36.4.3
36.5
36.5.1
36.5.2
36.5.3
36.5.4
36.5.5
36.5.6
36.5.7
36.5.8
36.5.9
36.5.10
36.5.11
36.5.12
36.5.13
36.6
36.6.1
36.6.2
36.6.3
36.6.4
36.6.5
36.6.6
Title
Page
Number
NFC Buffer Memory Space ........................................................................................... 36-6
Main and Spare Area Buffers .................................................................................... 36-7
Memory Map and Register Definitions ......................................................................... 36-8
Memory Map ............................................................................................................. 36-8
Register Summary...................................................................................................... 36-9
Register Descriptions ............................................................................................... 36-11
Functional Description................................................................................................. 36-22
Overview.................................................................................................................. 36-22
Modes of Operation ................................................................................................. 36-23
Booting From a NAND Flash Device...................................................................... 36-24
NAND Flash Control Submodule............................................................................ 36-25
DMA Request Operation ......................................................................................... 36-27
Reed-Solomon Error Correcting Code Engine (ECC Engine) ................................ 36-27
Address Control Module.......................................................................................... 36-28
RAM Buffer (SRAM) .............................................................................................. 36-28
Read and Write Control ........................................................................................... 36-29
Data Output Control................................................................................................. 36-29
Host Control............................................................................................................. 36-29
AHB Bus Interface................................................................................................... 36-29
I/O Pin Sharing ........................................................................................................ 36-30
Initialization/Application Information ......................................................................... 36-30
Normal Operation .................................................................................................... 36-31
ECC Operation......................................................................................................... 36-43
Symmetric Mode—One Flash Clock Cycle per Input or Output Data Cycle ......... 36-44
Write Protection Operation...................................................................................... 36-45
Memory Configuration Examples ........................................................................... 36-49
Verified NAND models............................................................................................ 36-52
Chapter 37
Pulse-Width Modulator (PWM)
37.1
37.2
37.2.1
37.3
37.3.1
37.3.2
37.4
37.4.1
Overview........................................................................................................................ 37-1
Signal Description.......................................................................................................... 37-2
External Signals ......................................................................................................... 37-2
Memory Map and Register Definition ........................................................................... 37-2
Register Summary...................................................................................................... 37-3
Register Descriptions ................................................................................................. 37-4
Functional Description................................................................................................. 37-11
Operation ................................................................................................................. 37-11
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Number
Title
Page
Number
Chapter 38
Smart Direct Memory Access (SDMA) Controller
38.1
38.1.1
38.1.2
38.2
38.3
38.3.1
38.3.2
38.3.3
38.4
38.4.1
38.4.2
38.4.3
38.4.4
38.5
38.5.1
38.5.2
38.5.3
38.6
38.6.1
38.7
38.8
38.8.1
38.8.2
38.9
38.10
38.10.1
38.10.2
38.10.3
38.11
38.11.1
38.11.2
38.11.3
38.12
38.12.1
38.12.2
38.12.3
38.12.4
38.12.5
Introduction.................................................................................................................... 38-1
Overview.................................................................................................................... 38-2
Features...................................................................................................................... 38-3
Functional Description................................................................................................... 38-4
SDMA Core ................................................................................................................... 38-6
SDMA Core Structure ............................................................................................... 38-7
Program Control Unit (PCU)..................................................................................... 38-9
SDMA Core Memory .............................................................................................. 38-12
Scheduler ..................................................................................................................... 38-12
Primary Functions.................................................................................................... 38-12
Channels and DMA Requests .................................................................................. 38-12
Scheduler Functional Description............................................................................ 38-13
Context Switching.................................................................................................... 38-24
Functional Units........................................................................................................... 38-26
CRC Calculation Unit.............................................................................................. 38-26
Burst DMA Unit ...................................................................................................... 38-28
Peripheral DMA Unit............................................................................................... 38-31
SDMA Security Support .............................................................................................. 38-34
Locked Mode ........................................................................................................... 38-34
OnCE and PCU Debug States...................................................................................... 38-35
SDMA Clocks and Low Power Modes........................................................................ 38-36
Clock Gating and Low Power Modes ...................................................................... 38-36
Reset......................................................................................................................... 38-39
Software Interface ........................................................................................................ 38-39
Initialization Information ............................................................................................. 38-40
Hardware Reset........................................................................................................ 38-40
Channel Script Execution ........................................................................................ 38-40
Initialization and Script Execution Setup Sequence ................................................ 38-41
AP Memory Map and Control Register Definitions .................................................... 38-41
AP Memory Map ..................................................................................................... 38-41
Register Summary.................................................................................................... 38-43
Register Descriptions ............................................................................................... 38-47
SDMA Programming Model ....................................................................................... 38-71
State and Registers Per Channel .............................................................................. 38-71
General Purpose Registers ....................................................................................... 38-71
Functional Unit State ............................................................................................... 38-72
Context Switching.................................................................................................... 38-73
Address Space.......................................................................................................... 38-74
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Paragraph
Number
38.13
38.13.1
38.13.2
38.13.3
38.14
38.15
38.15.1
38.15.2
38.15.3
38.15.4
38.16
38.16.1
38.16.2
38.16.3
38.16.4
38.16.5
38.16.6
38.16.7
38.16.8
38.16.9
38.16.10
38.16.11
38.16.12
38.16.13
38.16.14
38.16.15
38.16.16
38.16.17
38.17
38.17.1
38.17.2
38.17.3
38.17.4
38.18
38.18.1
38.18.2
38.18.3
38.18.4
38.18.5
38.19
38.19.1
Title
Page
Number
SDMA Internal (Core) Memory Map and Internal Register Definitions..................... 38-77
SDMA Internal (Core) Registers Memory Map ...................................................... 38-77
Register Summary.................................................................................................... 38-78
SDMA Core Register Descriptions.......................................................................... 38-82
SDMA Peripheral Registers....................................................................................... 38-101
SDMA Initialization .................................................................................................. 38-101
Hardware Reset...................................................................................................... 38-101
Standard Boot Sequence ........................................................................................ 38-101
User-Defined Boot Sequence................................................................................. 38-102
Script Loading and Context Initialization.............................................................. 38-102
Instruction Description .............................................................................................. 38-102
Scheduling Instructions.......................................................................................... 38-102
Conditional Branch Instructions ............................................................................ 38-103
Unconditional Jump Instructions ........................................................................... 38-103
Subroutine Return Instructions .............................................................................. 38-103
Loop Instruction..................................................................................................... 38-104
Miscellaneous Instructions .................................................................................... 38-104
Logic Instructions .................................................................................................. 38-104
Arithmetic Instructions .......................................................................................... 38-104
Compare Instructions............................................................................................. 38-105
Test Instructions ..................................................................................................... 38-105
Byte Permutation Instructions ............................................................................... 38-105
Bit Shift Instructions.............................................................................................. 38-105
Bit Manipulation Instructions ................................................................................ 38-106
SDMA Memory Access Instructions..................................................................... 38-106
Functional Unit Instructions .................................................................................. 38-106
Illegal Instructions ................................................................................................. 38-106
Debug Instructions ................................................................................................. 38-107
Functional Units Programming Model ...................................................................... 38-107
Burst DMA Unit .................................................................................................... 38-108
Peripheral DMA Unit............................................................................................. 38-121
CRC Unit ............................................................................................................... 38-132
OnCE and Real-Time Debug ................................................................................. 38-135
The OnCE Controller................................................................................................. 38-136
OnCE Commands .................................................................................................. 38-136
Sending Commands to the OnCE Controller......................................................... 38-137
Executing a Command from the OnCE ................................................................. 38-138
Registers Descriptions ........................................................................................... 38-141
JTAG Interface Requirements................................................................................ 38-143
Using the OnCE ......................................................................................................... 38-145
Activating Clocks in Debug Mode......................................................................... 38-145
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Number
38.19.2
38.19.3
38.19.4
38.19.5
38.19.6
38.19.7
38.19.8
Title
Page
Number
Getting the Current Status...................................................................................... 38-145
Methods of Entering Debug Mode ........................................................................ 38-145
Executing Instructions in Debug Mode ................................................................. 38-146
Command Sequences Examples ............................................................................ 38-146
OnCE Event Detection Unit .................................................................................. 38-151
Clock Gating and Reset ......................................................................................... 38-152
Real Time Features ................................................................................................ 38-153
Chapter 39
Subscriber Identification Module (SIM)
39.1
39.1.1
39.1.2
39.1.3
39.1.4
39.1.5
39.1.6
39.1.7
39.1.8
39.1.9
39.1.10
39.2
39.2.1
39.2.2
39.3
39.3.1
39.3.2
39.3.3
39.4
39.4.1
39.4.2
39.4.3
39.4.4
39.4.5
39.4.6
39.4.7
39.4.8
39.4.9
39.4.10
39.5
Overview........................................................................................................................ 39-1
Features...................................................................................................................... 39-1
Modes of Operation ................................................................................................... 39-2
SIM Bus Interface Overview ..................................................................................... 39-2
SIM Clock Generator Overview ................................................................................ 39-3
SIM Transmitter Overview ........................................................................................ 39-3
SIM Receiver Overview............................................................................................. 39-4
SIM Port Control Overview....................................................................................... 39-4
SIM General Purpose Counter Overview .................................................................. 39-5
SIM LRC Block Overview ........................................................................................ 39-5
SIM CRC Block Overview ........................................................................................ 39-5
External Signal Description ........................................................................................... 39-5
Overview.................................................................................................................... 39-5
Detailed Signal Descriptions ..................................................................................... 39-6
Memory Map and Register Definition ........................................................................... 39-7
Memory Map ............................................................................................................. 39-8
Register Summary...................................................................................................... 39-9
Register Descriptions ............................................................................................... 39-13
Functional Description................................................................................................. 39-46
SIM Detail Block Diagram ...................................................................................... 39-47
SIM Bus Interface.................................................................................................... 39-48
SIM Clock Generator............................................................................................... 39-50
SIM Transmitter....................................................................................................... 39-52
SIM Receiver ........................................................................................................... 39-56
SIM Port Control ..................................................................................................... 39-62
SIM General Purpose Counter................................................................................. 39-64
SIM LRC Block ....................................................................................................... 39-65
SIM CRC Block....................................................................................................... 39-65
Module Interrupts .................................................................................................... 39-67
Initialization/Application Information ......................................................................... 39-67
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Number
39.5.1
39.5.2
39.5.3
39.5.4
39.6
Title
Page
Number
Configuring SIM for Operation ............................................................................... 39-67
Using the SIM Receiver........................................................................................... 39-72
Using SIM Transmitter ............................................................................................ 39-76
Suggested “T=1” Compliant Programming Model ................................................. 39-79
Definitions, Acronyms, and Abbreviations.................................................................. 39-83
Chapter 40
Secure JTAG Controller V1.1 (SJC)
40.1
40.2
40.2.1
40.2.2
40.2.3
40.2.4
40.3
40.3.1
40.3.2
40.4
40.4.1
40.4.2
40.4.3
40.5
40.5.1
40.5.2
40.5.3
40.5.4
40.5.5
40.5.6
40.6
40.6.1
40.6.2
40.7
SJC Overview ................................................................................................................ 40-1
SJCv1.1 Block Diagram ................................................................................................ 40-2
Modes of Operation ................................................................................................... 40-2
ARM IP Dependency on Functional Clock and RTCK ............................................. 40-5
ARM Core/ETB/DAP Bypass ................................................................................... 40-5
ARM Bypass Use-Case Scenarios............................................................................. 40-6
External Signal Description ......................................................................................... 40-12
Overview.................................................................................................................. 40-12
TAP controller.......................................................................................................... 40-14
SoC JTAG .................................................................................................................... 40-16
Register Summary.................................................................................................... 40-16
Accessing Extradebug Registers.............................................................................. 40-17
SoC JTAG Instruction Register................................................................................ 40-28
Security ........................................................................................................................ 40-32
Introduction.............................................................................................................. 40-32
Fuses Programming ................................................................................................. 40-33
JTAG Security Modes .............................................................................................. 40-33
Software Enabled JTAG........................................................................................... 40-34
ETM Kill Trace........................................................................................................ 40-34
External Boot Fuse................................................................................................... 40-35
Functional Description................................................................................................. 40-35
Cores Static Debug .................................................................................................. 40-35
Reset Mechanism..................................................................................................... 40-36
Initialization/Application Information ......................................................................... 40-37
Chapter 41
Smart Liquid Crystal Display Controller (SLCDC)
41.1
41.2
41.2.1
41.2.2
SLCDC Module Pin List................................................................................................ 41-1
Functional Description................................................................................................... 41-2
Word Size Definition ................................................................................................. 41-3
Image Endianness ...................................................................................................... 41-3
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Paragraph
Number
41.2.3
41.2.4
41.2.5
41.2.6
41.2.7
41.2.8
41.2.9
41.2.10
41.2.11
41.2.12
41.2.13
41.2.14
41.2.15
41.2.16
41.2.17
41.2.18
41.2.19
41.3
41.3.1
41.3.2
41.4
41.5
Title
Page
Number
Accessing the LCD Controller................................................................................... 41-3
Aborting SLCDC Transfers ..................................................................................... 41-14
Low-Power Mode Operation ................................................................................... 41-14
Memory Map ........................................................................................................... 41-14
Register Summary.................................................................................................... 41-15
SLDC Register Descriptions.................................................................................... 41-16
Data Buffer Base Address Register (DATABASEADR) ......................................... 41-18
Data Buffer Size Register (DATABUFSIZE) .......................................................... 41-18
Command Buffer Base Address Register (COMBASEADR) ................................. 41-19
Command Buffer Size Register (COMBUFSIZ)..................................................... 41-19
Command String Size Register (COMSTRINGSIZ)............................................... 41-20
FIFO Configuration Register (FIFOCONFIG)........................................................ 41-21
LCD Controller Configuration Register (LCDCONFIG)........................................ 41-21
LCD Transfer Configuration Register (LCDTRANSCONFIG).............................. 41-22
SLCDC Control/Status Register (SLCDCCONTROL/STATUS) ........................... 41-23
LCD Clock Configuration Register (LCDCLOCKCONFIG) ................................. 41-26
LCD Write Data Register (LCDWRITEDATA) ...................................................... 41-26
LCD Controller Interface............................................................................................. 41-27
Serial Interface......................................................................................................... 41-27
Parallel Interface ...................................................................................................... 41-29
LCD Clock Configuration............................................................................................ 41-30
R-AHB Interface and SLCDC FIFOs .......................................................................... 41-31
Chapter 42
Shared Peripheral Bus Arbiter (SPBA)
42.1
42.2
42.3
42.4
42.4.1
42.5
42.5.1
42.5.2
42.5.3
42.5.4
42.6
42.6.1
42.6.2
42.6.3
42.6.4
Introduction.................................................................................................................... 42-1
Overview........................................................................................................................ 42-2
Features .......................................................................................................................... 42-3
Modes of Operation ....................................................................................................... 42-3
Detailed Signal Descriptions ..................................................................................... 42-3
Memory Map and Register Definition ........................................................................... 42-4
Peripherals Memory Map .......................................................................................... 42-4
SPBA Registers Memory Map................................................................................... 42-5
SPBA Register Summary........................................................................................... 42-6
Register Descriptions ................................................................................................. 42-6
Functional Description................................................................................................... 42-8
Masters Arbitration .................................................................................................... 42-8
Resource Ownership Control................................................................................... 42-10
Access Control......................................................................................................... 42-11
Owner Election ........................................................................................................ 42-11
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Paragraph
Number
42.6.5
42.6.6
Title
Page
Number
Termination of Ownership ....................................................................................... 42-12
The Unowned State.................................................................................................. 42-12
Chapter 43
Synchronous Serial Interface (SSI)
43.1
43.1.1
43.1.2
43.2
43.2.1
43.2.2
43.3
43.3.1
43.3.2
43.3.3
43.4
43.4.1
43.4.2
43.4.3
43.4.4
43.4.5
43.4.6
43.4.7
43.5
Overview........................................................................................................................ 43-2
Features...................................................................................................................... 43-3
Modes of Operation ................................................................................................... 43-3
External Signal Description ......................................................................................... 43-20
Overview.................................................................................................................. 43-20
Detailed Signal Descriptions ................................................................................... 43-20
Memory Map and Register Definition ......................................................................... 43-25
SSI Memory Map..................................................................................................... 43-25
Register Summary.................................................................................................... 43-26
Register Descriptions ............................................................................................... 43-31
Functional Description................................................................................................. 43-72
SSI Architecture....................................................................................................... 43-72
SSI Clocking ............................................................................................................ 43-72
Receive Interrupt Enable Bit Description ................................................................ 43-77
Transmit Interrupt Enable Bit Description .............................................................. 43-77
Internal Frame and Clock Shutdown ....................................................................... 43-78
Frequency Measurement Block ............................................................................... 43-80
IP Bus Interface ....................................................................................................... 43-80
Initialization/Application Information ......................................................................... 43-81
Chapter 44
Touch Screen Controller (TSC) and Analog-to-Digital Converter (ADC)
44.1
44.1.1
44.1.2
44.2
44.2.1
44.2.2
44.2.3
44.2.4
44.2.5
44.2.6
44.3
44.3.1
Introduction.................................................................................................................... 44-1
Overview.................................................................................................................... 44-1
Features...................................................................................................................... 44-2
Application Information ................................................................................................ 44-3
Introduction to Resistive Touch Screens.................................................................... 44-3
Touch Screen Connection .......................................................................................... 44-7
Touch Screen Measurement....................................................................................... 44-8
ADC Acquisition ....................................................................................................... 44-9
Example Programs..................................................................................................... 44-9
Quick Reference for ADC Convert Configuration Programming ........................... 44-11
Functional Description................................................................................................. 44-14
Block Diagram......................................................................................................... 44-14
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Paragraph
Number
44.3.2
44.3.3
44.3.4
44.3.5
44.3.6
44.3.7
44.3.8
44.3.9
44.3.10
44.3.11
44.4
44.4.1
44.4.2
44.4.3
Page
Number
Title
Clocks ...................................................................................................................... 44-14
Reset......................................................................................................................... 44-15
ADC Power.............................................................................................................. 44-16
Pen Down Detect ..................................................................................................... 44-16
Wake up from Deep Sleep Mode ............................................................................. 44-17
Interrupt Request & DMA Request Generation ...................................................... 44-17
LCD Noise Reduction.............................................................................................. 44-18
Queues ..................................................................................................................... 44-19
Arbiter...................................................................................................................... 44-23
FIFOs ....................................................................................................................... 44-24
Memory Map and Register Definition ......................................................................... 44-25
Memory Map ........................................................................................................... 44-25
Register Summary.................................................................................................... 44-26
Register Descriptions ............................................................................................... 44-29
Chapter 45
UTMI-USB-PHY
45.1
45.2
45.3
45.4
45.5
45.5.1
Reference Documentation.............................................................................................. 45-1
Acronyms, and Abbreviations........................................................................................ 45-1
Overview........................................................................................................................ 45-1
External Signal Descriptions ......................................................................................... 45-3
Functional Description................................................................................................... 45-3
USB PHY sub-blocks ................................................................................................ 45-3
Chapter 46
Universal Asynchronous Receiver/Transmitter (UART)
46.1
46.1.1
46.1.2
46.2
46.2.1
46.3
46.3.1
46.3.2
46.3.3
46.4
46.4.1
46.4.2
46.4.3
Overview........................................................................................................................ 46-1
Features...................................................................................................................... 46-2
Modes of Operation ................................................................................................... 46-3
External Signals ............................................................................................................. 46-3
Detailed Signal Descriptions ..................................................................................... 46-4
Memory Map and Register Definition ........................................................................... 46-6
Memory Map ............................................................................................................. 46-6
Register Summary...................................................................................................... 46-7
Register Descriptions ............................................................................................... 46-11
Functional Description................................................................................................. 46-34
Interrupts and DMA Requests ................................................................................. 46-34
Clocks ...................................................................................................................... 46-35
General UART Definitions ...................................................................................... 46-36
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Paragraph
Number
46.4.4
46.4.5
46.4.6
46.4.7
46.4.8
46.4.9
46.4.10
46.4.11
46.4.12
46.5
Title
Page
Number
Transmitter............................................................................................................... 46-41
Receiver ................................................................................................................... 46-44
Binary Rate Multiplier (BRM) ................................................................................ 46-53
Infrared Interface ..................................................................................................... 46-54
Low Power Modes ................................................................................................... 46-60
UART Operation in System Debug State ................................................................ 46-61
Reset......................................................................................................................... 46-61
Transfer Error........................................................................................................... 46-62
Functional Timing.................................................................................................... 46-62
Initialization ................................................................................................................. 46-63
Chapter 47
Universal Serial Bus OTG and Host (USBOH)
47.1
47.1.1
47.1.2
47.2
47.2.1
47.3
47.3.1
47.4
47.4.1
47.4.2
47.4.3
47.4.4
47.4.5
47.4.6
47.5
47.5.1
47.5.2
47.5.3
47.5.4
47.5.5
47.5.6
47.5.7
Overview........................................................................................................................ 47-1
Features...................................................................................................................... 47-2
Modes of Operation ................................................................................................... 47-3
External Signal Description ........................................................................................... 47-4
Overview.................................................................................................................... 47-4
Memory Map/Register Definition.................................................................................. 47-7
Register Descriptions ................................................................................................. 47-9
Functional Description................................................................................................. 47-17
USB Host Controller................................................................................................ 47-17
USB OTG Controller ............................................................................................... 47-17
USB Power Control Module.................................................................................... 47-17
Full-Speed Transceiverless Link Logic (FS-TLL) Module ..................................... 47-19
ULPI/Serial Multiplexer .......................................................................................... 47-20
Interrupts.................................................................................................................. 47-20
Initialization/Application Information ......................................................................... 47-21
Software Model........................................................................................................ 47-21
Register Interface ..................................................................................................... 47-23
Host Data Structures ................................................................................................ 47-77
Host Operational Model........................................................................................... 47-99
EHCI Deviation ..................................................................................................... 47-177
Device Data Structures .......................................................................................... 47-184
Device Operational Model..................................................................................... 47-189
Chapter 48
Watchdog Timer (WDOG)
48.1
Overview........................................................................................................................ 48-1
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Paragraph
Number
48.1.1
48.1.2
48.2
48.3
48.3.1
48.3.2
48.3.3
48.4
48.4.1
48.4.2
48.4.3
48.4.4
48.4.5
48.4.6
48.4.7
48.4.8
48.4.9
48.4.10
48.5
Title
Page
Number
Features...................................................................................................................... 48-2
Modes and Operations ............................................................................................... 48-3
External Signals ............................................................................................................. 48-3
Memory Map and Register Definitions ......................................................................... 48-3
Memory Map ............................................................................................................. 48-4
Register Summary...................................................................................................... 48-4
Register Descriptions ................................................................................................. 48-4
Functional Description................................................................................................. 48-10
Time-Out Event ....................................................................................................... 48-10
Interrupt Event ......................................................................................................... 48-10
Power-Down Counter Event .................................................................................... 48-11
Low-Power Modes................................................................................................... 48-11
Debug Mode ............................................................................................................ 48-11
Operations................................................................................................................ 48-12
Clocks ...................................................................................................................... 48-14
Reset......................................................................................................................... 48-14
Interrupt ................................................................................................................... 48-14
Flow Diagrams......................................................................................................... 48-15
Initialization ................................................................................................................. 48-19
Chapter 49
Wireless External Interface Module (WEIM)
49.1
49.1.1
49.1.2
49.2
49.2.1
49.2.2
49.3
49.3.1
49.3.2
49.3.3
49.4
49.4.1
49.4.2
49.4.3
49.4.4
49.4.5
49.4.6
49.4.7
Overview........................................................................................................................ 49-1
Features...................................................................................................................... 49-3
Modes of Operation ................................................................................................... 49-3
External Signal Description ........................................................................................... 49-4
Overview.................................................................................................................... 49-4
Detailed Signal Descriptions ..................................................................................... 49-4
Memory Map and Register Definition ........................................................................... 49-8
Memory Map ............................................................................................................. 49-8
Register Summary...................................................................................................... 49-9
Register Descriptions ............................................................................................... 49-10
Functional Description................................................................................................. 49-27
Configurable Bus Sizing .......................................................................................... 49-27
WEIM Operational Modes....................................................................................... 49-28
Burst Mode Memory Operation............................................................................... 49-28
Burst Clock Divisor ................................................................................................. 49-29
Burst Clock Start...................................................................................................... 49-29
Page Mode Emulation.............................................................................................. 49-29
PSRAM Mode Operation......................................................................................... 49-30
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Paragraph
Number
49.4.8
49.4.9
49.4.10
49.4.11
49.4.12
49.4.13
49.5
49.6
49.6.1
49.6.2
49.6.3
49.6.4
49.6.5
49.6.6
Title
Page
Number
Multiplexed Address/Data Mode............................................................................. 49-30
Mixed AHB/Memory Burst Modes Support ........................................................... 49-30
AHB Bus Cycles Support ........................................................................................ 49-30
DTACK Mode.......................................................................................................... 49-32
Internal Input Data Capture ..................................................................................... 49-32
Error Conditions ...................................................................................................... 49-33
Initialization/Application Information ......................................................................... 49-33
External Bus Timing Diagrams.................................................................................... 49-34
Asynchronous Memory Accesses Timing Diagrams............................................... 49-35
Page Mode Timing Diagrams .................................................................................. 49-53
DTACK Mode Memory Accesses Timing Diagrams .............................................. 49-54
Burst Memory Accesses Timing Diagrams ............................................................. 49-57
Synchronous Accesses Timing Diagrams with PSRAM ......................................... 49-68
Multiplexed A/D Mode............................................................................................ 49-71
Appendix A
IOMUX Registers
Appendix B
Revision History
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Number
Title
Page
Number
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i.MX25 Reference Manual
Book I
Rev. 2
01/2011
MCIMX25 Multimedia Applications Processor, Rev. 2
Book I -2
Freescale Semiconductor
Chapter 1
IC Architecture Overview
This chapter introduces the i.MX25 architecture.
1.1
i.MX25 Overview
The i.MX25 is targeted for the automotive and general industrial markets. This multimedia applications
processor has the right mix of high performance, low power, and integration to support the growing needs
of the industrial and general embedded markets. The i.MX25 is partitioned into two major subsystems as
shown in Figure 1-1: the ARM926 platform and the SDMA platform with an external memory interface
(EMI).
DDR2 /
MDDR
NOR
Flash/
PSRAM
NAND
Flash
Ext. Graphics
Accelerator
Camera
Sensor
LCD Display 1
CSI
LCDC /
SLCDC
External Memory
Interface
Smart
DMA
ARM9
Platform
ARM926ejs
SPBA
ARM926 Peripherals
SSI
AUDMUX
HS USBOTG
HS USBOTGPHY
HS USB Host
L1 I/D cache
I2C(3)
SDMA Peripherals
SSI(1)
ESAI
UART(3)
CSPI(2)
12-bit A/D
TSC
SIM(2)
ATA
ASIC
UART(2)
MAX
CSPI
AIPS(2)
eSDHC(2)
ETM
CAN(2)
Internal
Memory
FEC
ECT
IOMUX
IIM
RTICv3
GPIO(3)
RNGB
EPIT(2)
SCC
DRYICE
PWM(4)
Timers
RTC
WDOG
1-WIRE
GPT(4)
KPP
3 FuseBox
Audio/Power
Management
JTAG
Bluetooth
MMC/SDIO
or WLAN
Keypad
Connectivity
Access
Figure 1-1. i.MX25 High-Level Block Diagram
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1-1
IC Architecture Overview
1.1.1
Key Features
The i.MX25 is based on the ARM926 platform. The ARM926 platform has the following features:
• ARM926EJS processor
• 16 Kbyte L1 instruction cache
• 16 Kbyte L1 data cache
• 400 MHz maximum frequency of the core and L1 cache
To boost the performance, the following hardware accelerators are integrated:
• Alpha blending at the LCD controller
• 128 Kbyte internal SRAM
• A/D controller and integrated touch screen controller
Security functions are enabled and accelerated by the following hardware:
• Secure JTAG Controller (SJC). Protects JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
• Real-Time Integrity Checker type2 (RTICv3). RTIC type1, enhanced with SHA-256 engine.
• Secure RAM module and the Security Monitor (SCCv3). Provides 2 Kbytes of secure storage of
sensitive information both in on-chip RAM and in off-chip, non-volatile memory.
• High Assurance Boot (HAB) with SHA-256.
• DryIce
— Second level encrypted key with enhanced tamper detection erase capability
— Tamper detectors
— Secure real time clock
— 32 KHz oscillator
The memory system consists of the following levels:
• Level-1 cache
— Instruction (16 Kbyte)
— Data (16 Kbyte)
• Level-2 memory
— Boot ROM, including HAB (32 Kbyte)
— Internal RAM (128 Kbyte)
— Secure RAM (2 Kbyte)
The i.MX25 provides the following interfaces to external devices:
• Two Controller Area Network (CAN) interfaces
• Two CE-ATA, SDIO/MMC interfaces (up to 416 Mbps)
• Three Configurable Serial Peripheral Interfaces (CSPI) - supporting speeds up to 52 Mbps each
• DDR2, Mobile DDR, and SDRAM (up to 133 MHz) [DAH: Also supports PSDRAM]
• Ethernet 10/100 Mbps
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IC Architecture Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Flash controller - MLC, SLC NAND and NOR
GPIO with interrupt capabilities
Three I2C (up to 400 Kbps each)
JTAG
Keypad port
1-Wire module
Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 MPix)
Parallel display (primary up to 24-bit, 1024x1024)
Parallel-ATA (P-ATA) -up to 66 MByte/s
Four Pulse Width Modulators (PWM)
Two Synchronous Serial Interfaces (SSI)
One Enhanced Serial Audio Interface (eSAI)
Five UART (up to 4.0 Mbps each)
USB 2.0 Host with FS PHY
USB 2.0 OTG (up to 480 Mbps) with HS PHY
Two Subscriber Identification Modules (SIM)
1.2
1.2.1
Architecture Overview
Functional Domains Overview
The i.MX25 consists of the following major subsystems:
• ARM926 platform
• SDMA platform and EMI
1.2.1.1
ARM926 Platform Overview
The ARM926 platform is responsible for running the operating system and applications software,
providing the user interface, and supplying access to integrated and external peripherals. The look and feel
of the device depends on the software running on this processor, ultimately tying market acceptance to the
availability of a wide variety of off-the-shelf, third-party software and development tools. Over the past
couple of years, the ARM CPU family has emerged as the de-facto standard for mobile application
processors. To leverage this growing software base, the ARM926 platform is based on the ARM
architecture. The ARM926 platform is built around an ARM926EJS core with 16 Kbyte instruction and
16 Kbyte data L1 caches, an MMU, a multi-ported crossbar switch, and advanced debug and trace
interfaces.
The ARM9 core is intended to operate at a maximum frequency of 400 MHz in order to support the
required multimedia use cases, such as concurrent video playback QVGA at 30 fps and MP3 audio decode.
Furthermore, an LCDC is integrated into the ARM926 platform to off-load the core from graphics overlay.
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1-3
IC Architecture Overview
Peripheral functionality belonging to the ARM926 platform includes the user interface, connectivity,
display, security, and memory interfaces and 128 Kbytes multipurpose SRAM. This SRAM can be used
as audio RAM, scratch pad RAM by the ARM9, or it can be accessed by the LCDC for use as a display
buffer.
1.2.1.2
SDMA Platform and EMI Overview
The shared domain is composed of the SDMA peripherals, a Smart DMA Engine (SDMA) and a number
of miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the
SDMA engine.
The external memory subsystem represents a significant investment in chipset cost and board area.
High-performance processors such as the ARM9 require a significant amount of bus bandwidth to achieve
their maximum potential. The challenge is to maximize the performance while minimizing the bandwidth.
To achieve that, the i.MX25 includes a hierarchical memory architecture including L1 caches and M2
memory. This reduces the bandwidth demands for the external bus and external memory. The external
memory subsystem supports a flexible external memory system, including support for SDRAM (SDR and
DDR), DDR2, Mobile DDR (mDDR), and NAND flash.
1.2.2
Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques have been
incorporated into the i.MX25 processor:
• Clock gating
• Power optimized synthesis
• Well biasing
• Dynamic Process and Temperature Compensation (DPTC)
• Dynamic Voltage and Frequency Scaling (DVFS)
Clock distribution circuits in digital ICs with the complexity of i.MX25 can consume as much as 40% of
the total dissipated power. By inserting gating into the clock paths, unused portions of the chip can be
disabled. Since static CMOS logic consumes only leakage power, significant power savings can be
realized. The i.MX25 clock gating is inserted both manually on a large functional block basis and
automatically within the blocks during logic synthesis. The i.MX25 integrates both clock gating and power
optimization into the synthesis design flow.
Well biasing is applying a voltage that is greater than Vdd to the nwells and lower than Vss to the P-wells.
The effect of applying this well back bias voltage is to reduce the subthreshold channel leakage. For the
90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of 10 over the
nominal leakage.
Additionally, the supply voltage for internal logic can be reduced from 1.4 V to 1.2V to 1.0 V during
periods of inactivity.
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IC Architecture Overview
1.2.3
Modules Inventory
Table 1-1 describes the ARM926 core.
Table 1-1. Core Summary
Core
Acronym
ARM9 or
ARM926
Core Name
Brief Description
Integrated Memory Includes
ARM926
platform
and
memory
The ARM926 platform consists of the ARM926EJS™
core, the ETM real-time debug modules, a 5x5 multilayer
AHB crossbar switch, and a “primary AHB” complex.
•
•
•
•
16-Kbyte Instruction L1 Cache
16-Kbyte Data L1 Cache
32-Kbyte ROM
128-Kbyte RAM
Table 1-2 describes the modules on the chip, as well as a description of the functionality, as well as the
names of the subsystem to which they belong.
Table 1-2. Digital and Analog Modules
Block
Mnemonic
Block Name
Domain1
Sub-System
Brief Description
Chapter
ATA
ATA Module
SDMA
Connectivity
Peripherals
The ATA block is a AT attachment host interface. Its
main use is to interface with IDE hard disc drives and
ATAPI optical disc drives. It interfaces with the ATA
device over a number of ATA signals.
—
AUDMUX
Digital Audio
Mux
ARM
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for
voice, audio, and synchronous data routing between
host serial interfaces (SSIs) and peripheral serial
interfaces (audio codecs). The AUDMUX has two sets
of interfaces: internal ports to on-chip peripherals, and
external ports to off-chip audio devices. Data is routed
by configuring the appropriate internal and external
ports.
—
CAN(2)
CAN Module
ARM
Connectivity
Peripherals
The CAN protocol is primarily designed to be used as a
vehicle serial data bus running at 1 Mbps.
—
CCM
Clock Control
Module
ARM
Clocks
This block generates all clocks for the peripherals in the
SDMA platform. The CCM also manages the ARM926
platform low power modes (WAIT, STOP), disabling
peripheral clocks appropriately for power conservation,
and provides alternate clock sources for the ARM926
and SDMA platforms.
—
CSPI(3)
Configurable
Serial
Peripheral
Interface
SDMA,
ARM
Connectivity
Peripherals
This module is a serial interface equipped with data
FIFOs, each master/slave-configurable SPI module is
capable of interfacing to both serial port interface
master and slave devices. The CSPI ready (SPI_RDY)
and slave select (SS) control signals enable fast data
communication with fewer software interrupts.
—
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IC Architecture Overview
Table 1-2. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Domain1
Brief Description
Chapter
External
Memory
Interface
The EMI module provides access to external memory
for the ARM and other masters. It is composed of main
sub-modules:
• M3IF provides arbitration between multiple masters
requesting access to the external memory.
• The SDRAM CTRL interfaces to DDR2 and SDR
interfaces.
• NANDFC provide an interface to NAND Flash
memories.
• The WEIM interfaces to NOR flash and PSRAM.
—
Enhanced
ARM
Periodic
Interrupt Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is
capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a
12-bit prescaler to adjust the input clock frequency to
the required time setting for the interrupts, and the
counter value can be programmed on the fly.
—
ESAI
Enhanced
Serial Audio
Interface
SDMA
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a
full-duplex serial port for serial communication with a
variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other DSPs.
The ESAI consists of independent transmitter and
receiver sections, each section with its own clock
generator.
—
FEC
Ethernet
SDMA
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support both 10- and 100- Mbps
Ethernet/IEEE Std. 802.3™ networks. An external
transceiver interface and transceiver function are
required to complete the interface to the media.
—
GPIO(3)
General
Purpose I/O
Modules
ARM
Pins
Used for general purpose input/output to external ICs.
Each GPIO module supports 32 bits of I/O.
—
GPT(4)
General
Purpose
Timers
ARM
Timer
Peripherals
Each GPT is a 32-bit "free-running" or "set and forget"
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in "set and forget" mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
—
EMI
EPIT(2)
External
Memory
Interface
SDMA
Sub-System
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IC Architecture Overview
Table 1-2. Digital and Analog Modules (continued)
Block
Mnemonic
I2C(3)
Block Name
Domain1
Sub-System
Brief Description
Chapter
I2C Module
ARM
ARM926
Platform
Peripherals
inter-IC Communication (I2C) is an industry-standard,
bi-directional serial bus that provides a simple, efficient
method of data exchange, minimizing the
interconnection between devices. I2C is suitable for
applications requiring occasional communications over
a short distance between many devices. The interface
operates up to 100 kbps with maximum bus loading and
timing. The I2C system is a true multiple-master bus,
including arbitration and collision detection that
prevents data corruption if multiple devices attempt to
control the bus simultaneously. This feature supports
complex applications with multiprocessor control and
can be used for rapid testing and alignment of end
products through external connections to an
assembly-line computer.
—
IIM
IC
Identification
Module
ARM
Security
Modules
The IIM provides the primary user-visible mechanism
for interfacing with on-chip fuse elements. Among the
uses for the fuses are unique chip identifiers, mask
revision numbers, cryptographic keys, and various
control signals requiring a fixed value.
—
IOMUX
I/O
Multiplexers
ARM
Pins
Each I/O multiplexer provides a flexible, scalable
multiplexing solution with the following features:
• Up to eight output sources multiplexed per pin
• Up to four destinations for each input pin
• Unselected input paths are held at constant level for
reduced power consumption
—
KPP
KeyPad Port
ARM
Connectivity
Peripherals
Can be used for either keypad matrix scanning or
general purpose I/O.
—
OSC24M
OSC24 MHz
Reference
Oscillator
Analog
Clock
The OSC24M oscillator provides a stable frequency
reference for the PLLs. This oscillator is designed to
work in conjunction with an external 24 MHz crystal.
—
OSC32K
OSC32 kHz
Reference
Oscillator
Analog
Clock
The OSC32K oscillator provides a stable frequency
reference for the RTC. This oscillator is designed to
work in conjunction with an external 32 KHz crystal.
—
1-WIRE
1-Wire
Interface
ARM
ARM926
Platform
Peripherals
1-WIRE provides the communication line to a 1 Kbit
Add-Only Memory (DS2502). The interface sends or
receives one bit at a time. The required protocol for
accessing the 1-Wire device, especially the DS2502, is
defined by Dallas Semiconductor Corporation.™ The
DS2502 holds battery characteristics information.
—
PWM(4)
Pulse Width
Modulator
ARM
ARM926
Platform
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images. The PWM can also generate tones. It
uses 16-bit resolution and a 4 × 16 data FIFO to
generate sound.
—
Real Time
Clock
ARM
Clocks
Provides the ARM926 platform with a clock function.
—
RTC
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1-7
IC Architecture Overview
Table 1-2. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Sub-System
Brief Description
Chapter
SIM(2)
Subscriber
Identification
Module
ARM
Security
The SIM is designed to facilitate communication to SIM
cards or Eurochip pre-paid phone cards.
—
SDMA
Smart DMA
Engine
SDMA
System
Controls
The SDMA provides DMA capabilities inside the
processor. It is a shared module that implements 32
DMA channels and has interface to connect to the
ARM926 platform, EMI interface and the shared
peripherals.
—
Secure JTAG
Controller
ARM
Pins
The SJC provides debug and test control with
maximum security.
—
SJC
SPBA
Shared
SDMA
Peripheral Bus
Arbiter
System
Controls
The SPBA controls access to the shared peripherals. It
supports shared peripheral ownership and access
rights to an owned peripheral.
—
SSI(2)
Synchronous
Serial
Interface
SDMA,
ARM
Connectivity
peripherals
The SSI is a full-duplex serial port that allows the
processor connected to it to communicate with a variety
of serial protocols, including the Freescale
Semiconductor SPI standard and the inter-IC sound
bus standard (I2S). The SSIs interface to the AUDMUX
for flexible audio routing.
—
Universal
SDMA,
Asynchronous ARM
Receiver/
Transmitters
Connectivity
Peripherals
Each UART provides serial communication capability
with external devices through an RS-232 cable using
the standard RS-232 non-return-to-zero (NRZ)
encoding format. Each module transmits and receives
characters containing either 7 or 8 bits (program
selectable). Each UART can also provide low-speed
IrDA compatibility through the use of external circuitry
that converts infrared signals to electrical signals (for
reception) or transforms electrical signals to signals
that drive an infrared LED (for transmission).
—
ARM
Connectivity
Peripherals
The USB module provides high performance USB
On-The-Go (OTG) and Host functionality (up to 480
Mbps), compatible with the USB 2.0 specification, the
OTG supplement and the ULPI 1.0 Low Pin Count
specification. The module has DMA capabilities
handling data transfer between internal buffers and
system memory. A OTG HS PHY and HOST FS PHY
are also integrated.
—
ARM
Timer
peripherals
Each module protects against system failures by
providing a method of escaping from unexpected
events or programming errors. Once activated, the
timer must be serviced by software on a periodic basis.
If servicing does not take place, the watchdog times out
and then either asserts a system reset signal or an
interrupt request signal, depending on the software
configuration.
—
UART(5)
USBOTG High-Speed
USBHOST USB
On-The-Go
WDOG
1
Domain1
Watchdog
Modules
ARM = ARM926 platform, SDMA = SDMA platform
i.MX25 Multimedia Applications Processor Reference Manual , Rev. 2
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Freescale Semiconductor
Chapter 2
Memory Map
This chapter introduces the memory architecture of the i.MX25 device. The i.MX25 memory is
hierarchical, with one level of cache between the microprocessors and the external memory.
The chapter is organized as follows:
• “Section 2.1, “System Memory Map,” presents the system memory map.
• “Section 2.2, “SDMA Peripheral Memory Map,” presents the SDMA master IP bus peripheral
memory map.
NOTE
All referenced addresses are physical addresses.
2.1
System Memory Map
Table 2-1 shows the system memory map for the i.MX25 device.
Table 2-1. System Memory Map
Address Range
Size
Region
Start
End
0x0000_0000
0x0000_3FFF
16 Kbytes
ROM (36 Kbytes)
0x0000_4000
0x0040_3FFF
4 Mbytes
Reserved
0x0040_4000
0x0040_8FFF
20 Kbytes
ROM (36 Kbytes)
0x0040_9000
0x0FFF_FFFF
252 Mbytes (minus 36 Kbytes)
Reserved
0x1000_0000
0x1FFF_FFFF
256 Mbytes
Reserved
0x2000_0000
0x2FFF_FFFF
256 Mbytes
Reserved
0x3000_0000
0x3FFF_FFFF
256 Mbytes
Reserved
0x4000_0000
0x43EF_FFFF
63 Mbytes
Reserved
0x43F0_0000
0x43F0_3FFF
16 Kbytes
AIPS A control registers
0x43F0_4000
0x43F0_7FFF
16 Kbytes
ARM926 platform MAX
0x43F0_8000
0x43F0_BFFF
16 Kbytes
ARM926 platform CLKCTL
0x43F0_C000
0x43F0_FFFF
16 Kbytes
ARM926 platform ETB registers
0x43F1_0000
0x43F1_3FFF
16 Kbytes
ARM926 platform ETB memory
0x43F1_4000
0x43F1_7FFF
16 Kbytes
ARM926 platform AAPE registers
0x43F1_8000
0x43F7_FFFF
416 Kbytes
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
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2-1
Memory Map
Table 2-1. System Memory Map (continued)
Address Range
Size
Region
Start
End
0x43F8_0000
0x43F8_3FFF
16 Kbytes
I2C-1
0x43F8_4000
0x43F8_7FFF
16 Kbytes
I2C-3
0x43F8_8000
0x43F8_BFFF
16 Kbytes
CAN-1
0x43F8_C000
0x43F8_FFFF
16 Kbytes
CAN-2
0x43F9_0000
0x43F9_3FFF
16 Kbytes
UART-1
0x43F9_4000
0x43F9_7FFF
16 Kbytes
UART-2
0x43F9_8000
0x43F9_BFFF
16 Kbytes
I2C-2
0x43F9_C000
0x43F9_FFFF
16 Kbytes
1-Wire
0x43FA_0000
0x43FA_3FFF
16 Kbytes
ATA (CPU side)
0x43FA_4000
0x43FA_7FFF
16 Kbytes
CSPI-1
0x43FA_8000
0x43FA_BFFF
16 Kbytes
KPP
0x43FA_C000
0x43FA_FFFF
16 Kbytes
IOMUXC
0x43FB_0000
0x43FB_3FFF
16 Kbytes
AUDMUX
0x43FB_4000
0x43FB_7FFF
16 Kbytes
Reserved
0x43FB_8000
0x43FB_BFFF
16 Kbytes
ECT (IP BUS A)
0x43FB_C000
0x43FB_FFFF
16 Kbytes
ECT (IP BUS B)
0x43FC_0000
0x43FF_FFFF
256 Kbytes
Reserved AIPS A off-platform slots
0x4400_0000
0x4FFF_FFFF
192 Mbytes
Reserved
0x5000_0000
0x5000_3FFF
16 Kbytes
SPBA base address
0x5000_4000
0x5000_7FFF
16 Kbytes
CSPI-3
0x5000_8000
0x5000_BFFF
16 Kbytes
UART-4
0x5000_C000
0x5000_FFFF
16 Kbytes
UART-3
0x5001_0000
0x5001_3FFF
16 Kbytes
CSPI-2
0x5001_4000
0x5001_7FFF
16 Kbytes
SSI-2
0x5001_8000
0x5001_BFFF
16 Kbytes
ESAI
0x5001_C000
0x5001_FFFF
16 Kbytes
Reserved
0x5002_0000
0x5002_3FFF
16 Kbytes
ATA
0x5002_4000
0x5002_7FFF
16 Kbytes
SIM-1
0x5002_8000
0x5002_BFFF
16 Kbytes
SIM-2
0x5002_C000
0x5002_FFFF
16 Kbytes
UART-5
0x5003_0000
0x5003_3FFF
16 Kbytes
TSC
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Memory Map
Table 2-1. System Memory Map (continued)
Address Range
Size
Region
Start
End
0x5003_4000
0x5003_7FFF
16 Kbytes
SSI-1
0x5003_8000
0x5003_BFFF
16 Kbytes
FEC
0x5003_C000
0x5003_FFFF
16 Kbytes
SPBA registers
0x5004_0000
0x51FF_FFFF
32 Mbytes (minus 256 Kbytes)
0x5200_0000
0x53EF_FFFF
31 Mbytes
Reserved
0x53F0_0000
0x53F0_3FFF
16 Kbytes
AIPS B control registers
0x53F0_4000
0x53F7_FFFF
496 Kbytes
Reserved
0x53F8_0000
0x53F8_3FFF
16 Kbytes
CCM
0x53F8_4000
0x53F8_7FFF
16 Kbytes
GPT-4
0x53F8_8000
0x53F8_BFFF
16 Kbytes
GPT-3
0x53F8_C000
0x53F8_FFFF
16 Kbytes
GPT-2
0x53F9_0000
0x53F9_3FFF
16 Kbytes
GPT-1
0x53F9_4000
0x53F9_7FFF
16 Kbytes
EPIT-1
0x53F9_8000
0x53F9_BFFF
16 Kbytes
EPIT-2
0x53F9_C000
0x53F9_FFFF
16 Kbytes
GPIO-4
0x53FA_0000
0x53FA_3FFF
16 Kbytes
PWM-2
0x53FA_4000
0x53FA_7FFF
16 Kbytes
GPIO-3
0x53FA_8000
0x53FA_BFFF
16 Kbytes
PWM-3
0x53FA_C000
0x53FA_FFFF
16 Kbytes
SCC
0x53FB_0000
0x53FB_3FFF
16 Kbytes
RNGB
0x53FB_4000
0x53FB_7FFF
16 Kbytes
eSDHC-1
0x53FB_8000
0x53FB_BFFF
16 Kbytes
eSDHC-2
0x53FB_C000
0x53FB_FFFF
16 Kbytes
LCDC
0x53FC_0000
0x53FC_3FFF
16 Kbytes
SLCDC
0x53FC_4000
0x53FC_7FFF
16 Kbytes
Reserved
0x53FC_8000
0x53FC_BFFF
16 Kbytes
PWM-4
0x53FC_C000
0x53FC_FFFF
16 Kbytes
GPIO-1
0x53FD_0000
0x53FD_3FFF
16 Kbytes
GPIO-2
0x53FD_4000
0x53FD_7FFF
16 Kbytes
SDMA
0x53FD_8000
0x53FD_BFFF
16 Kbytes
Reserved
0x53FD_C000
0x53FD_FFFF
16 Kbytes
WDOG
Reserved AIPS B
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2-3
Memory Map
Table 2-1. System Memory Map (continued)
Address Range
Size
Region
Start
End
0x53FE_0000
0x53FE_3FFF
16 Kbytes
PWM-1
0x53FE_4000
0x53FE_7FFF
16 Kbytes
Reserved
0x53FE_8000
0x53FE_BFFF
16 Kbytes
Reserved
0x53FE_C000
0x53FE_FFFF
16 Kbytes
RTICv3
0x53FF_0000
0x53FF_3FFF
16 Kbytes
IIM
0x53FF_4000
0x53FF_7FFF
16 Kbytes
USB
0x53FF_8000
0x53FF_BFFF
16 Kbytes
CSI
0x53FF_C000
0x53FF_FFFF
16 Kbytes
DryIce
0x5400_0000
0x5FFF_FFFF
192 Mbytes
Reserved (aliased AIPS B slots)
0x6000_0000
0x67FF_FFFF
128 Mbytes
ARM926 platform ROMPATCH
0x6800_0000
0x6FFF_FFFF
128 Mbytes
ARM926 platform ASIC
0x7000_0000
0x77FF_FFFF
128 Mbytes
Reserved
0x7800_0000
0x7801_FFFF
128 Kbytes
RAM
0x7802_0000
0x7FFF_FFFF
128 Mbytes (minus 128 Kbytes)
0x8000_0000
0x8FFF_FFFF
256 Mbytes
SDRAM bank 0
0x9000_0000
0x9FFF_FFFF
256 Mbytes
SDRAM bank 1
0xA000_0000
0xA7FF_FFFF
128 Mbytes
WEIM CS0 (flash 128)1
0xA800_0000
0xAFFF_FFFF
128 Mbytes
WEIM CS1 (flash 64)1
0xB000_0000
0xB1FF_FFFF
32 Mbytes
WEIM CS2 (SRAM)
0xB200_0000
0xB3FF_FFFF
32 Mbytes
WEIM CS3 (SRAM)
0xB400_0000
0xB5FF_FFFF
32 Mbytes
WEIM CS4
0xB600_0000
0xB7FF_FFFF
32 Mbytes
Reserved
0xB800_0000
0xB800_0FFF
4 Kbytes
Reserved
0xB800_1000
0xB800_1FFF
4 Kbytes
SDRAM control registers
0xB800_2000
0xB800_2FFF
4 Kbytes
WEIM control registers
0xB800_3000
0xB800_3FFF
4 Kbytes
M3IF control registers
0xB800_4000
0xB800_4FFF
4 Kbytes
EMI control registers
0xB800_5000
0xBAFF_FFFF
32 Mbytes (minus 20 Kbytes)
0xBB00_0000
0xBB00_0FFF
4 Kbytes
NAND flash main area buffer
0xBB00_1000
0xBB00_11FF
512 B
NAND flash spare area buffer
0xBB00_1200
0xBB00_1DFF
3 Kbytes
RAM alias
Reserved
Reserved
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Memory Map
Table 2-1. System Memory Map (continued)
Address Range
Size
1
Region
Start
End
0xBB00_1E00
0xBB00_1FFF
512 B
0xBB01_2000
0xBFFF_FFFF
96 Mbytes (minus 8 Kbytes)
Reserved
0xC000_0000
0xFFFF_FFFF
1024 Mbytes
Reserved
NAND flash control registers
WEIM CS0 and CS1 can be collapsed to form a single 256-Mbyte region from 0xA000_0000 to 0xAFFF_FFFF
2.2
SDMA Peripheral Memory Map
SDMA scripts can read and write to the context RAM, data RAM, shared-peripheral registers, and internal
registers. All of the data accessible to SDMA scripts make up the data memory space of the SDMA. The
address range is 16 bits and the data width is 32 bits. Each address corresponds to a 32-bit data word.
The SDMA can perform only 32-bit access to shared-peripheral registers. The i.MX25, shared peripheral
registers are treated as if byte addressed. This is a consequence of connections through the SPBA shared
peripheral bus outside of the SDMA. The result is that although address space 4 Kwords (16 Kbytes) is
allocated for each peripheral, only the first 4 Kbytes of the peripherals register space can be accessed. For
example, the shared peripheral register at address 0x3000 is mapped also to addresses 0x3001, 0x3002,
0x3003. A read or write access to any of these 4 addresses will respond as if the access was to address
0x3000.
Table 2-2 shows the memory map of the shared peripherals to SDMA-accessible memory space.
Table 2-2. SDMA Peripheral Memory Map
Peripheral
Base Address
Size
Comments
SDMA internal memory
0x0000
4 Kwords
map to SDMA Internal ROM/RAM
CSPI3
0x1000
4 Kwords
map to 4 Kbytes of CSPI3 address space
UART4
0x2000
4 Kwords
map to 4 Kbytes of UART4 address space
UART3
0x3000
4 Kwords
map to 4 Kbytes of UART3 address space
CSPI2
0x4000
4 Kwords
map to 4 Kbytes of CSPI2 address space
SSI2
0x5000
4 Kwords
map to 4 Kbytes of SSI2 address space
ESAI
0x6000
4 Kwords
map to 4 Kbytes of ESAI address space
SDMA internal registers
0x7000
4 Kwords
map to SDMA registers
ATA
0x8000
4 Kwords
map to 4 Kbytes of ATA address space
SIM1
0x9000
4 Kwords
map to 4 Kbytes of SIM1 address space
SIM2
0xA000
4 Kwords
map to 4 Kbytes of SIM2 address space
UART5
0xB000
4 Kwords
map to 4 Kbytes of UART5 address space
TCH/SC/ADCTL
0xC000
4 Kwords
map to 4 Kbytes of TCH/SC/ADCTL address space
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Memory Map
Table 2-2. SDMA Peripheral Memory Map (continued)
Peripheral
Base Address
Size
Comments
SSI1
0xD000
4 Kwords
map to 4 Kbytes of SSI1 address space
FEC
0xE000
4 Kwords
map to 4 Kbytes of FEC address space
SPBA Registers
0xF000
4 Kwords
map to 4 Kbytes of SPBA address space
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Chapter 3
Interrupts and DMA Events
This chapter provides the assignments for the interrupt requests of the AP domains:
• Section 3.1, “ARM926 Platform Interrupts”
This chapter also defines the DMA events in the following sections:
• Section 3.2, “SDMA Event Mapping”
3.1
ARM926 Platform Interrupts
The ARM926EJ-S Simple Interrupt Controller (ASIC) is designed to handle up to 64 interrupt requests.
Table 3-1 lists the ARM926 platform interrupt sources.
Table 3-1. ARM926 Platform Interrupt Sources
IRQ
Interrupt Source
Interrupt Description
0
CSPI-3
—
1
GPT-4
—
2
1-Wire
—
3
I2C-1
—
4
I2C-2
—
5
UART-4
—
6
RTIC
—
7
ESAI
—
8
ESDHC-2
—
9
ESDHC-1
—
10
I2C-3
—
11
SSI-2
—
12
SSI-1
—
13
CSPI-2
—
14
CSPI-1
—
15
ATA
—
16
GPIO-3
17
CSI
—
18
UART-3
—
Combined Interrupts - 1 Bit Int Or Of 32
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Interrupts and DMA Events
Table 3-1. ARM926 Platform Interrupt Sources (continued)
IRQ
Interrupt Source
Interrupt Description
19
IIM
—
20
SIM-1
—
21
SIM-2
—
22
RNGB
—
23
GPIO-4
24
KPP
25
DryIce
26
PWM-1
—
27
EPIT-2
—
28
EPIT-1
—
29
GPT-3
—
30
POWER FAIL
31
CCM
—
32
UART-2
—
33
NANDFC
34
SDMA
35
USB-HTG
—
36
PWM-2
—
37
USB-OTG
—
38
SLCDC
—
39
LCDC
—
40
UART-5
—
41
PWM-3
—
42
PWM-4
—
43
CAN-1
—
44
CAN-2
—
45
UART-1
—
46
TSC
—
47
Reserved
—
48
ECT
—
49
SCC SCM
SCM interrupt
50
SCC SMN
SMN interrupt
51
GPIO-2
Combined Interrupts - 1 Bit Int Or Of 32
Keypad Interrupt
Consolidated RTC Interrupt
power fail interrupt from external PAD
Consolidated Nand Flash Controller Interrupt
“AND” of all 32 interrupts from all the channels
Combined Interrupts - 1 Bit Int Or Of 32
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Interrupts and DMA Events
Table 3-1. ARM926 Platform Interrupt Sources (continued)
3.2
IRQ
Interrupt Source
Interrupt Description
52
GPIO-1
53
GPT-2
—
54
GPT-1
—
55
WDOG
—
56
DryIce
57
FEC
58
EXT_INT5
External interrupt for Power Management using GPIO-1[5]
59
EXT_INT4
External interrupt for Temp using GPIO-1[4]
60
EXT_INT3
External interrupt for Sensor using GPIO-1[3]
61
EXT_INT2
External interrupt for Sensor using GPIO-1[2]
62
EXT_INT1
External interrupt for Watch-dog using GPIO-1[1]
63
EXT_INT0
External interrupt for TV using GPIO-1[0]
Combined Interrupts - 1 Bit Int Or Of 32
security violation interrupt
—
SDMA Event Mapping
Table 3-2 shows the SDMA event mapping.
Table 3-2. SDMA Event Mapping
Event Number
DMA Source
Description
0
EXT DMA 0
External DMA request 0 from GPIO-4:GPIO[27]
1
CCM
2
ATA TXFER end
—
3
ATA TX FIFO
—
4
ATA RX FIFO
—
5
Reserved
—
6
CSP-2 RX
CSPI2 receive
7
CSPI-2 TX
CSPI2 transmit
8
CSPI-1 RX
CSPI1 receive
9
CSPI-1 TX
CSPI1 transmit
10
UART-3 RX
UART3 receive
11
UART-3 TX
UART3 transmit
12
UART-4 RX
UART4 receive
13
UART-4 TX
UART4 transmit
14
EXT DMA 1
External DMA request 1 from GPIO-4:GPIO[28]
DPTC, DVFS event
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Interrupts and DMA Events
Table 3-2. SDMA Event Mapping (continued)
Event Number
DMA Source
Description
15
EXT DMA 2
External DMA request 2 from GPIO-4:GPIO[29]
16
UART-2 RX
UART2 receive
17
UART-2 TX
UART2 transmit
18
UART-1 RX
UART1 receive
19
UART-1 TX
UART1 transmit
20
Reserved
—
21
Reserved
—
22
SSI-2 RX1
SSI2 receive channel 1
23
SSI-2 TX1
SSI2 transmit channel 1
24
SSI-2 RX0
SSI2 receive channel 0
25
SSI-2 TX0
SSI2 transmit channel 0
26
SSI-1 RX1
SSI1 receive channel 1
27
SSI-1 TX1
SSI1 transmit channel 1
28
SSI-1 RX0
SSI1 receive channel 0
29
SSI-1 TX0
SSI1 transmit channel 0
30
NANDFC
31
ECT
32
ESAI RX
—
33
ESAI TX
—
34
CSPI-3 RX
—
35
CSPI-3 TX
—
36
SIM-2 RX
—
37
SIM-2 TX
—
38
SIM-1 RX
—
39
SIM-1 TX
—
40
Reserved
—
41
Reserved
—
42
Reserved
—
43
Reserved
—
44
TSC GCQ
—
45
TSC TCQ
—
46
UART-5 RX
—
47
UART-5 TX
—
—
CTI trigger out
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Chapter 4
External Signals and Pin Multiplexing
The i.MX25 has a limited number of pins, and most pins are shared among multiple signals. This chapter
describes the external I/O signals and pin multiplexing (muxing) in order to help users to understand pin
assignment and the input-output multiplexer (IOMUX). It is also intended to enable software developers
to do appropriate muxing programming.
4.1
IOMUX Overview
The muxing hardware in i.MX25 is composed of the following:
• IOMUX—Combinational logic that does the muxing.
• IOMUX_CTL—Muxing controller which controls signal muxing, interrupt observability, and pin
settings.
The IOMUX module deals with signal multiplexing, and consists of combinatorial logic built with a basic
IOMUX cell. Each pin, which is shared by multiple signals, has a related IOMUX cell to handle signal
multiplexing.
The IOMUX_CTL module consists of registers and deals with interrupt and pin characteristic settings,
such as I/O driver voltage, slew rate, drive strength, open drain and pull/keeper, and so on.
Figure 4-1 shows a simplified SoC block diagram of pin muxing with two typical cases:
• Case 1 is a regular muxing example: Module A, Module B, and Module GPIO share the same pin
through the IOMUX, and muxing is controlled by the IOMUX_CTL.
• Case 2 is an example of no muxing: the pin is dedicated to Module C, signals are directly connected
between Module C and the pin, and no IOMUX cell is involved.
Each IOMUX cell can support up to eight muxing modes (ALT0–ALT7), which means that each pin can
ultimately be shared by eight signals.
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4-1
External Signals and Pin Multiplexing
GPR Register
IOMUX_CTL
SW_INPUT_SELECT Register
Pad Settings Control
SW_PAD_CTL Register
SW_MUX_CTL Register
Software Mux Control
Port ADIR
ALT_DIR[7:0]
Module A
Port AOUT
IOMUX_CELL
0
1
2
3
4
5
6
7
Port AIN
Port BDIR
IPP_OBE
IPP_IBE
Port BOUT
Module B
ALT_IN[7:0]
Port BIN
0
1
2
3
4
5
6
7
GPIODIR
GPIOOUT
GPIO
IPP_DO
IPP_IND
GPIOIN
ALT_OUT[7:0]
I/O Pad
ALT0_DEFAULT_IN
ALT1_DEFAULT_IN
.
.
ALT5_DEFAULT_IN
.
.
ALT7_DEFAULT_IN
Case1: Regular Muxing
Port CDIR
IPP_OBE
IPP_DO
Port COUT
IPP_IBE
Module C
Port CIN
IPP_IND
I/O Pad
Case2: No Muxing
Figure 4-1. Pin Multiplexing Block Diagram
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External Signals and Pin Multiplexing
4.2
Pin-Muxing Control
This section describes how to select the muxing mode for each pin through software programming. After
chip reset, each pin works in its primary mode, ALT0. Boot code or software programming are required to
enable the alternate modes (ALT1–ALT7).
Each pin’s signal muxing is controlled by a software mux control (SW_MUX_CTL) register. Each
SW_MUX_CTL register handles pin muxing for only one pin. The SW_MUX_CTL register also has the
ability to enable a loopback feature. See Section 4.2.1, “Software Mux Control Registers
(SW_MUX_CTL),” for more information.
The software select input (SW_SELECT_INPUT) register is user-accessible during IOMUX
programming which is required when there are multiple pins as muxing options. See Section 4.2.2,
“SW_SELECT_INPUT Register Definition,” for more information. Section 4.6, “Daisy Chain List,” also
provides information about SW_SELECT_INPUT settings.
4.2.1
Software Mux Control Registers (SW_MUX_CTL)
Each 32-bit SW_MUX_CTL register controls the signal multiplexing for one IOMUX cell. The
SW_MUX_CTL register is partitioned into two fields: mux mode select field (MUX_MODE) and
software input on field (SION). MUX_MODE controls the signal muxing on each pin, and SION controls
loopback and GPIO capture feature, although not all individual pins have the SION bit option.
When the SION bit is cleared, the pin works in normal mode and the I/O direction is determined by the
selected muxing mode. When the SION bit is set to 1, the pin operates in loopback mode. All modes’ input
path is forced on by software, and pin value feeds through into all modes’ input. In loopback mode, using
a GPIO module, users can capture the pin values.
Figure 4-2 shows the general format of an SW_MUX_CTL register. Table 4-1 shows the field descriptions.
SW_MUX_CTL registers follow the naming convention of
IOMUXC_SW_MUX_CTL_PAD_<Pin_Name>,
where <Pin_Name> is the pin name, which is different for each register.
IOMUXC_SW_MUX_CTL_PAD_<Pin_Name>
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
SION
MUX_MODE
W
Reset
—
—
—
—
—
—
—
—
—
—
—
0
—
0
Figure 4-2. SW_MUX_CTL Register Generic Format
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External Signals and Pin Multiplexing
Table 4-1. SW_MUX_CTL Field Descriptions
Field
31–5
Reserved
4
SION
Software Input On Field.
0 Normal mode: IO is determined by the selected muxing mode. (default)
1 Loopback mode: Input feedthrough, loopback feature enabled.
3
Reserved
2–0
MUX_MODE
4.2.1.1
Description
MUX Mode Select Field. Select one of the IOMUX modes to be used for the pin: <Pin_Name>
000 Select ALT0 mux mode (default)
001 Select ALT1 mux mode
010 Select ALT2 mux mode
011 Select ALT3 mux mode
100 Select ALT4 mux mode
101 Select ALT5 mux mode
110 Select ALT6 mux mode
111 Select ALT7 mux mode
Loopback Examples
The following examples illustrate how to use the loopback feature for bus-status detection and GPIO
capture.
Example 1: Bus-Status Detection
Figure 4-3 shows the case where module A drives the pin while simultaneously receiving or detecting the
pin value or bus status.
Port CDIR
IPP_OBE
IPP_DO
Port COUT
IPP_IBE
Module A
Port CIN
SION
IPP_IND
I/O Pin
Figure 4-3. Loopback Example 1: Bus-Status Detection
Example 2: GPIO Capture
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External Signals and Pin Multiplexing
Figure 4-4 shows the case where module A drives the pin while the GPIO module captures the pin value
or bus status.
Port CDIR
IPP_OBE
IPP_DO
Port COUT
IPP_IBE
Module A
SION
Port CIN
IPP_IND
I/O Pin
GPIO
Figure 4-4. Loopback Example 2: GPIO Capture
4.2.2
SW_SELECT_INPUT Register Definition
Each 32-bit Software Select Input Control (SW_SELECT_INPUT) register controls the input path to avoid
multi-driving problem. This register is only required when multiple pins drive the same internal port. This
usually happens when one input port has multiple pin-muxing options on different pins.
For example, in Figure 4-5, both pin A and pin B could be used as the input pin of an on-chip IP Instance,
and serve as Port C options. In such cases, a SW_SELECT_INPUT register is used to select the driving
pin. Section 4.6, “Daisy Chain List,” provides all instances and ports that are involved in the daisy chain,
and also lists pins and their corresponding SW_SELECT_INPUT register values.
SW_MUX_CTL_PAD_pinA
SW_MUX_CTL_PAD_pinB
SW_SELECT_INPUT
IOMUX
Port C mux option 1
IP Instance
iomux_cell A
mux
Port C
pin A
Port C mux option 2
iomux_cell B
pin B
Figure 4-5. Select Input from Pins
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4-5
External Signals and Pin Multiplexing
Two steps are required during IOMUX software programming in such cases. For example, in Figure 4-5,
if pin A is selected to work as the driving pin of Port C, then the following IOMUX programming steps
are required:
1. Set IOMUXC_SW_MUX_CTL_PAD_<pinA> to select the correct muxing mode for Port C.
2. Set IOMUXC_<Instance>_<PortC>_SELECT_INPUT to select the input driving from pin A.
SW_SELECT_INPUT registers follow the naming convention:
IOMUXC_<Instance>_<Port>_SELECT_INPUT.
Figure 4-6 shows the general format of an SW_SELECT_INPUT register. Table 4-2 shows the field
descriptions.
IOMUXC_<Instance>_<Port>_SELECT_INPUT
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
Daisy
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
Figure 4-6. SW_SELECT_INPUT Register Generic Format
Table 4-2. SW_SELECT_INPUT Field Descriptions
Field
Description
31–3
Reserved
2–0
Daisy
The actual width of the Daisy field is equal to the number of driving pins. For example, if there are
two driving pins then bits [2:1] are reserved, and bit 0 is the actual Daisy field.
Users can select a specific drive pin for an input port of a module to solve the multi-driving
problem (this is referred to as “daisy chaining”).
All the instances and ports that are involved in Daisy Chain are listed in Section 4.6, “Daisy Chain List,”
users can find the pins and correct values to program SW_SELECT_INPUT registers in Table 4-16.
4.3
Pin-Setting Control
This section describes how to set characteristic settings of each pin through software programming. The
software pad control registers (SW_PAD_CTL) control I/O driver voltage, slew rate, drive strength, open
drain, pull/keeper, DDR type, and so on. See Section 4.3.1, “Software Pad Control Registers
(SW_PAD_CTL),” for a full description.
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External Signals and Pin Multiplexing
Settings for some pins are controlled in groups instead of pin-by-pin. This is implemented by the software
pad group control registers (SW_PAD_CTL_GRP). See Section 4.3.2, “Software Pad Group Control
Registers (SW_PAD_CTL_GRP),” for more information.
4.3.1
Software Pad Control Registers (SW_PAD_CTL)
Each 32-bit SW_PAD_CTL register controls the software-configurable characteristics of an I/O pin. The
configurable settings include Slew Rate, Drive Strength, Open Drain, Pull/Keeper, Hysteresis, and so on.
DDR pins have different characteristics from GPIO pins. The generic format of the SW_PAD_CTL
register for GPIO pins is shown in Figure 4-7 and the format for DDR pins is shown in Figure 4-8.
Not all SW_PAD_CTL registers implement every bit defined in the generic definition. Some
characteristics of specific pins may have constant settings that are not software configurable. Only those
characteristics with CFG ( ) in the detailed pin muxing Table 4-18 are software-configurable.
Characteristics for some pins are configured in groups, not pin-by-pin. This is defined in Section 4.3.2,
“Software Pad Group Control Registers (SW_PAD_CTL_GRP).” If a characteristic is configurable as a
group, then the corresponding bit in the SW_PAD_CTL register is not used.
SW_PAD_CTL registers follow the naming convention: IOMUXC_SW_PAD_CTL_PAD_<Pin_Name>.
Figure 4-7 and Table 4-3 show the register definition for GPIO pins. Reset values are different for different
registers, depending on the registers’ functionality.
IOMUXC_SW_PAD_CTL_PAD_<Pin_Name>
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
HYS
PKE
PUE
n
n
n
W
Reset1
R
DVS
PUS
ODE
DSE
SRE
W
Reset1
—
—
n
—
—
—
—
n
n
n
n
n
n
Figure 4-7. SW_PAD_CTL Register Generic Format (GPIO Pins)
1
Reset values differ for different registers.
Table 4-3. SW_PAD_CTL Field Descriptions (GPIO Pins)
Field
31–14
13
DVS
Description
Reserved
Driver Voltage Select Bit. Select the correct driver for different I/O supplies1.
0 3.3 V I/O Driver
1 1.8 V I/O Driver
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External Signals and Pin Multiplexing
Table 4-3. SW_PAD_CTL Field Descriptions (GPIO Pins) (continued)
Field
Description
12–9
Reserved
8
HYS
Hysteresis enable bit. Select Schmitt trigger or CMOS input:
0 Hysteresis Disabled, CMOS input.
1 Hysteresis Enabled, Schmitt trigger input.
7
PKE
Pull/Keeper enable bit. when PKE = 0, PUE and PUS have no functionality.
0 Pull/Keeper Disabled
1 Pull/Keeper Enabled
6
PUE
Pull or keeper select bit. when PUE = 0, PUS has no functionality.
0 Keeper Enabled, Pull Disabled
1 Keeper Disabled, Pull Enabled
5–4
PUS
Pull up or down strength select bits.
00 100 KΩ Pull-down
01 47 KΩ Pull-up
10 100 KΩ Pull-up
11 22 KΩ Pull-up
3
ODE
Open drain enable bit. This bit selects open drain or CMOS output:
0 Output is CMOS
1 Output is Open Drain
2–1
DSE
Drive Strength Control Bits. These bits select standard, high or max pin drive strength2.
00 Nominal or standard drive strength
01 High drive strength
10 Max drive strength
11 Max drive strength
0
SRE
Slew Rate Control Bit. This bit selects between FAST/SLOW slew rate output.
0 Slow slew rate
1 Fast slew rate, used for high frequency designs
1
The DVS bit is used to select the different output drivers, 1.8 V (±10%) or 3.3 V (±10%). Each GPIO pin has two internal
output-buffer units designed for 1.8 V and 3.3 V respectively. For the 2.5 V supply case, the 1.8 V driver is applicable. Normally,
the DVS bit should be set to match the I/O supply.
2 I/O Drive strength depends on the application conditions. For GPIO pins, at a temperature of 25 °C and in the typical case, the
following drive strength can be referenced: Standard (2 mA), High (4 mA) and Max (8 mA) in SLOW mode at 3.3 V supply with
the equivalent impedances of 100 Ω, 50 Ω, and 25 Ω respectively. And, Standard (4 mA), High (6 mA) and Max (8 mA) in FAST
mode at 3.3 V supply with the equivalent impedances of 50 Ω, 33 Ω, and 25 Ω respectively.
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External Signals and Pin Multiplexing
DDR pins have different characteristics than GPIO pins. Figure 4-8 and Table 4-4 shows the register
definitions related to DDR pins. Reset values are different for different registers, depending on the
registers’ functionality.
IOMUXC_SW_PAD_CTL_PAD_<Pin_Name>
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
W
Reset
R
PKE
W
Reset1
—
—
—
—
—
—
—
—
n
Figure 4-8. SW_PAD_CTL Register Generic Format (DDR Pins)
1
Reset values differ for different registers.
Table 4-4. SW_PAD_CTL Field Descriptions (DDR Pins)
Field
Description
31–8
Reserved
7
PKE
Keeper Enable Bit. This bit enables the internal keeper capability of the DDR pin. The DDR pin has no Pull capability.
0 Internal Keeper Disabled
1 Internal Keeper Enabled
6–0
Reserved
Note: For DDR pins, there are three working modes with different drive strength. And in this device, the DDR mode and drive
strength of all DDR pins are controlled as a group, not on a pin-by-pin basis. For more information, see Section 4.3.2,
“Software Pad Group Control Registers (SW_PAD_CTL_GRP)”.
4.3.2
Software Pad Group Control Registers (SW_PAD_CTL_GRP)
The 32-bit software pad group control registers (SW_PAD_CTL_GRP) configure specific characteristics
for a pin group, where a pin group is defined as a set of pins sharing a common I/O pin settings. These
registers thus differ from the SW_PAD_CTL registers, which only configure characteristics for a single
pin.
In the i.MX25 device there are three characteristics that are controlled in groups: DDR Type, Drive Voltage
and Drive Strength.
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External Signals and Pin Multiplexing
4.3.2.1
DDR Type Group Control Register
(IOMUXC_SW_PAD_CTL_GRP_DDRTYPE)
The IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register controls the DDR type setting of all DDR pins.
Register settings only apply to DDR pins.
The register’s format is shown in Figure 4-9, and the register fields are described in Table 4-5. Users can
select the DDR type by programming the DDR_TYPE field in this register. Different DDR types
correspond to different drive strengths and impedance equivalence, as follows:
• The default setting for DDR_TYPE is 0b00, which is the setting that is suitable for most systems
using mobile DDR (mDDR) or DDR2 that do not require termination. mDDR and DDR2 types are
designed for 1.8 V (± 5%) applications. For DDRTYPE=00 at 25o C in the typical case, the
following drive strengths can be referenced: Standard (3.6 mA), High (7.2 mA), Max (10.8 mA)
with equivalent impedances of 90 Ω, 45 Ω, and 20 Ω respectively.
— For mDDR and DDR2 configurations with 1 load (single chip), DDRTYPE=00 and Standard
(3.6mA) drive strength is the typical setting and normally does not require termination
— For mDDR and DDR2 configurations with 2 loads (2 parallel chips), DDRTYPE=00 and High
(7.2mA) drive strength is the typical setting and normally does not require termination
• The DDR_TYPE setting of 0b01 corresponds to SDRAM. SDRAM type is designed for 3.3 V (±
5%) applications, with drive strengths Standard (4 mA), High (8 mA), Max (12 mA) and equivalent
impedances of 90 Ω, 45 Ω, and 30 Ω respectively.
• The DDR_TYPE setting of 0b10 corresponds to maximum drive strength (13.4 mA) with
equivalent impedance 20 Ω. Under this setting, the drive strength is not configurable, and the DSE
bits (drive strength group control register) have no functionality.
IOMUXC_SW_PAD_CTL_GRP_DDRTYPE
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
DDR_TYPE
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
Figure 4-9. SW_PAD_CTL_GRP_DDRTYPE Register Format
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External Signals and Pin Multiplexing
Table 4-5. SW_PAD_CTL_GRP_DDRTYPE Field Descriptions
Field
Description
31–13
Reserved
12–11
DDR_TYPE
DDR_TYPE Field
Select the working mode of all DDR pins. (Only valid for DDR pins.)
00 1.8 V mDDR and DDR2 type
01 3.3 V SDRAM type
10 Maximum drive
11 Reserved
10–0
4.3.2.2
Reserved
Drive Voltage Select Group Control Registers
(SW_PAD_CTL_GRP_DVS)
The general format for Driver Voltage Select (DVS) group control registers is shown in Figure 4-10 and
Table 4-6. This register allows users to select the different drivers for 1.8 V or 3.3 V. Table 4-7 shows the
list of i.MX25 registers for the DVS group. DVS control is only valid for GPIO pins.
IOMUXC_SW_PAD_CTL_GRP_DVS_<GROUP_NAME>
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
DVS
W
Reset
0
Figure 4-10. SW_PAD_CTL_GRP_DVS Generic Format
Table 4-6. SW_PAD_CTL_GRP_DVS Field Descriptions
Field
31–14
Description
Reserved
13
DVS
Driver Voltage Select Bit. Selects the correct output driver for different I/O supplies. (Only valid for GPIO pins)
Each GPIO pin has two internal output-buffer units designed for 1.8 V (±10%) and 3.3 V (±10%) respectively. For the
2.5 V supply case, the 1.8 V driver is applicable. Normally, the DVS bit should be set to match with the I/O supply.
0 3.3 V I/O Driver
1 1.8 V I/O Driver
12–0
Reserved
Table 4-7. SW_PAD_CTL_GRP_DVS Register List
Register Name
IOMUXC_SW_PAD_CTL_GRP_DVS_CSI
Comment
CSI power bank
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External Signals and Pin Multiplexing
Table 4-7. SW_PAD_CTL_GRP_DVS Register List (continued)
4.3.2.3
IOMUXC_SW_PAD_CTL_GRP_DVS_CCM
CCM power bank
IOMUXC_SW_PAD_CTL_GRP_DVS_JTAG
JTAG power bank
IOMUXC_SW_PAD_CTL_GRP_DVS_LCD
LCD power bank
IOMUXC_SW_PAD_CTL_GRP_DVS_MISC
MISC power bank
IOMUXC_SW_PAD_CTL_GRP_DVS_NFC
NFC power bank
IOMUXC_SW_PAD_CTL_GRP_DVS_SDHC1
SDHC1 power bank
Drive Strength Group Control Registers (SW_PAD_CTL_GRP_DSE)
The general format for drive strength group control registers is shown in Figure 4-11 and Table 4-8. The
DSE control field is valid for both DDR and GPIO pins. Table 4-9 shows the list of i.MX25 registers for
the drive strength group.
IOMUXC_SW_PAD_CTL_GRP_DSE_<GROUP_NAME>
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
0
0
0
0
0
0
0
0
0
4
0
3
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
DSE
W
Reset
0
0
0
0
0
0
0
Figure 4-11. SW_PAD_CTL_GRP_DSE Generic Format
Table 4-8. SW_PAD_CTL_GRP_DSE Field Descriptions
Field
Description
31–3
Reserved
2–1
DSE
Drive Strength Control Bits.
These bits select Standard, High or Max drive strength. (Valid for both DDR and GPIO pins.)
00 Nominal or standard drive strength
01 High drive strength
10 Max drive strength
11 Max drive strength
0
Reserved
Table 4-9. SW_PAD_CTL_GRP_DSE Register List
Register Name
Comment
IOMUXC_SW_PAD_CTL_GRP_DSE_CSI
Drive Strength Control of CSI group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_CSPI1
Drive Strength Control of CSPI1 group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_DDR
Drive Strength Control of DDR group pins
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External Signals and Pin Multiplexing
Table 4-9. SW_PAD_CTL_GRP_DSE Register List
4.4
IOMUXC_SW_PAD_CTL_GRP_DSE_FEC
Drive Strength Control of FEC group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_KPP
Drive Strength Control of KPP group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_LCD
Drive Strength Control of LCD group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_NFC
Drive Strength Control of NFC group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_UART
Drive Strength Control of UART group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_SDHC1
Drive Strength Control of SDHC1 group pins
IOMUXC_SW_PAD_CTL_GRP_DSE_WEIM
Drive Strength Control of WEIM group pins
Special Functionality
This section includes detailed descriptions of the following:
• General purpose register
• Interrupt observe control register
• Loopback and GPIO capture
• Boot-related pins
• Special pins
4.4.1
General Purpose Register (IOMUXC_GPR1)
The 32-bit general purpose register (IOMUXC_GPR1), shown in Figure 4-12, configures two EMI chip
select options.
IOMUXC_GPR1
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
18
17
16
0
0
0
0
0
3
2
1
0
0
0
W
Reset
R
W
Reset
SDCTL_CSD1 SDCTL_CSD0_
_SEL_B
SEL_B
0
0
Figure 4-12. IOMUXC_GPR1 Register
Table 4-10. IOMUXC_GPR1 Field Descriptions
Field
31–2
Description
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
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4-13
External Signals and Pin Multiplexing
Table 4-10. IOMUXC_GPR1 Field Descriptions (continued)
Field
Description
1
SDCTL_CSD1_SEL_B
EMI Chip Select Control Bit for SDCTL over WEIM. Select multiplexed chip select (CS3) between
SDRAM/DDR and WEIM in EMI.
0 SDCTL chip select
1 WEIM chip select
0
SDCTL_CSD0_SEL_B
EMI Chip Select Control Bit for SDCTL over WEIM. Select multiplexed chip select (CS2) between
S DRAM/DDR and WEIM in EMI.
0 SDCTL chip select
1 WEIM chip select
4.4.2
Interrupt Observe Control Register (IOMUXC_OBSERVE_INT_MUX)
The interrupt observe control register, shown in Figure 4-13, is used for interrupt observability control,
which controls the IOMUX to route specific internal interrupts to pin GPIO_A. The observed interrupt
could be used for debugging or software development.
IOMUXC_OBSERVE_INT_MUX
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
OBSRV
W
Reset
0
0
0
0
Figure 4-13. IOMUXC_OBSERVE_INT_MUX Register
Table 4-11. IOMUXC_OBSERVE_INT_MUX Field Descriptions
Field
31–7
6–0
OBSRV
Description
Reserved
This field is used to select the observed interrupt out or debug ports. The selected interrupt can be observed
on pin GPIO_A.
Table 4-12. Observed Interrupts List
OBSRV Bits[6:0]
Observed Interrupt Source
0000000
CSPI-3
0000001
GPT-4
0000010
1-Wire
0000011
I2C-1
0000100
I2C-2
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External Signals and Pin Multiplexing
Table 4-12. Observed Interrupts List (continued)
OBSRV Bits[6:0]
Observed Interrupt Source
0000101
UART-4
0000110
RTIC
0000111
ESAI
0001000
ESDHC-1
0001001
ESDHC-2
0001010
I2C-3
0001011
SSI-2
0001100
SSI-1
0001101
CSPI-2
0001110
CSPI-1
0001111
ATA
0010000
GPIO-3
0010001
CSI
0010010
UART-3
0010011
IIM
0010100
SIM-1
0010101
SIM-2
0010110
RNGB
0010111
GPIO-4
0011000
KPP
0011001
DRYICE
0011010
PWM-1
0011011
EPIT-2
0011100
EPIT-1
0011101
GPT-3
0011110
POWER FAIL
0011111
CCM
0100000
UART-2
0100001
NANDFC
0100010
SDMA
0100011
USB-HOST
0100100
PWM-2
0100101
USB-OTG
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External Signals and Pin Multiplexing
Table 4-12. Observed Interrupts List (continued)
OBSRV Bits[6:0]
Observed Interrupt Source
0100110
SLCDC
0100111
LCDC
0101000
UART-5
0101001
PWM-3
0101010
PWM-4
0101011
CAN-1
0101100
CAN-2
0101101
UART-1
0101110
TSC
0101111
Reserved as VDD
0110000
ECT
0110001
SCC SCM
0110010
SCC SMN
0110011
GPIO-2
0110100
GPIO-1
0110101
GPT-2
0110110
GPT-1
0110111
WDOG
0111000
DRYICE
0111001
FEC
0111010
EXT_INT5 using GPIO1[5]
0111011
EXT_INT4 using GPIO1[4]
0111100
EXT_INT3 using GPIO1[3]
0111101
EXT_INT2 using GPIO1[2]
0111110
EXT_INT1 using GPIO1[1]
0111111
EXT_INT0 using GPIO1[0]
1000000
SDMA Pin debug_yield
1000001
SDMA Pin debug_core_run
1000010
SDMA Pin debug_mode
1000011
SDMA Pin debug_bus_error
1000100
SDMA Pin debug_bus_device[0]
1000101
SDMA Pin debug_bus_device[1]
1000110
SDMA Pin debug_bus_device[2]
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External Signals and Pin Multiplexing
Table 4-12. Observed Interrupts List (continued)
OBSRV Bits[6:0]
4.4.3
Observed Interrupt Source
1000111
SDMA Pin debug_bus_device[3]
1001000
SDMA Pin debug_bus_device[4]
1001001
SDMA Pin debug_bus_rwb
1001010
SDMA Pin debug_matched_dmbus
1001011
SDMA Pin debug_rtbuffer_write
1001100
SDMA Pin debug_evt_chn_lines[0]
1001101
SDMA Pin debug_evt_chn_lines[1]
1001110
SDMA Pin debug_evt_chn_lines[2]
1001111
SDMA Pin debug_evt_chn_lines[3]
1010000
SDMA Pin debug_evt_chn_lines[4]
1010001
SDMA Pin debug_evt_chn_lines[5]
1010010
SDMA Pin debug_evt_chn_lines[6]
1010011
SDMA Pin debug_evt_chn_lines[7]
1010100
ARM926P platform Pin etm_portsize[0]
1010101
ARM926P platform Pin etm_portsize[1]
1010110
ARM926P platform Pin etm_portsize[2]
1010111
FEC Pin miigsk_int_col
1011000
FEC Pin miigsk_int_crs
1011001
FEC Pin miigsk_int_rx_clk
1011010
FEC Pin miigsk_int_rx_dv
1011011
FEC Pin miigsk_int_tx_clk
1011100
FEC Pin miigsk_mux_cnt_mii_mode
1011101
FEC Pin miigsk_slow_en
Loopback and GPIO Capture
Loopback is when the module drives the pin and also receives the pin value as an input. GPIO Capture is
when the module drives the pin and the value is captured by GPIO module.
These features are available through the SION (Software Input On) bit of the SW_MUX_CTL register
(Section 4.2.1, “Software Mux Control Registers (SW_MUX_CTL)). When the SION bit is set, it enables
the input path of all muxing modes on the pin by forcing IPP_IBE = 1 (see Figure 4-1), regardless of the
original pin direction control.
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External Signals and Pin Multiplexing
4.4.4
Boot-Related Pins
The boot modes are primarily controlled by two dedicated boot pins BOOT_MODE0 and
BOOT_MODE1. There are also a number of eFUSEs to further determine the specific boot mode and path
during the boot process. The fuse value can be determined by IIM or GPIO pins with the control of the
GPIO_BT_SEL fuse. When the GPIO_BT_SEL fuse is cleared, the fuse value is determined by the GPIO
pins. (See the Boot chapter for details.) The corresponding relationship between GPIO boot pins and
eFUSEs are listed in Table 4-13.
Table 4-13. Boot Related Pins
Pin Name
Direction at Boot
eFUSE Name
Details
BOOT_MODE0
INPUT
N/A
Boot mode select pins
BOOT_MODE1
INPUT
N/A
LD0
INPUT
BT_MEM_CTRL[0]
LD1
INPUT
BT_MEM_CTRL[1]
LD2
INPUT
BT_MEM_TYPE[0]
LD3
INPUT
BT_MEM_TYPE[1]
LD4
INPUT
BT_PAGE_SIZE[0]
LD5
INPUT
BT_PAGE_SIZE[1]
LD6
INPUT
BT_BUS_WIDTH[0]
LD7
INPUT
BT_BUS_WIDTH[1]
LD8
INPUT
BT_USB_SRC[0]
LD9
INPUT
BT_USB_SRC[1]
LD10
INPUT
BT_MLC_SEL
MLC/SLC NAND Flash Select
LD11
INPUT
BT_SPARE_SIZE
NAND Flash spare byte size
LD12
INPUT
BT_SRC[0]
Boot Select for eSDHC, CSPI, and I2C
LD13
INPUT
BT_SRC[1]
LD14
INPUT
BT_EEPROM_CFG
EEPROM config
LD15
INPUT
BT_UART_SRC[0]
UART boot select
HSYNC
INPUT
BT_UART_SRC[1]
VSYNC
INPUT
BT_UART_SRC[2]
LSCLK
INPUT
BT_LPB_FREQ[0]
OE_ACD
INPUT
BT_LPB_FREQ[1]
PWM
INPUT
BT_LPB_FREQ[2]
Boot memory device select
Boot memory type select
NAND Flash page size select
NAND bus width select
USB PHY selection select
LPB ARM core frequency select
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External Signals and Pin Multiplexing
Table 4-13. Boot Related Pins (continued)
Pin Name
Direction at Boot
eFUSE Name
CSI_MCLK
INPUT
BT_RES[0]
CSI_VSYNC
INPUT
BT_RES[1]
CSI_HSYNC
INPUT
BT_RES[2]
CSI_PIXCLK
INPUT
BT_RES[3]
Details
Reserved boot options
Note: In this device, the GPIO boot pins are latched by the CCM on chip reset when the fuse GPIO_BT_SEL is set to
0; no extra software pin-muxing programming is required. After reset, these pins work as normal GPIO pins in its
default functionality (ALT0 mode). If you still need the pins to work as boot pins, then the users need to configure
IOMUX to select the correct muxing mode.
4.4.5
Special Pins
Table 4-14 lists the special pins supported in the device.
Table 4-14. Special Pins List
Pin Name
Mux Mode
Function Name
Detailed Description
EXT_ARMCLK
ALT0
External ARM clock External ARM clock input, used for function test when internal ARM
clock is bypassed.
UPLL_BYPCLK
ALT0
PLL bypass control
UPLL bypass clock, used when internal UPLL is bypassed.
CLKO
ALT0
Clock out
Clock out pin from CCM, clock source is controllable and can also be
used for debug.
VSTBY_ACK
ALT0
CCM hreset_b out
This pin routes out CCM hreset_b for test and debugging in ALT0
mode.
VSTBY_ACK
ALT1
PMIC signal
Standby acknowledge from external PMIC
VSTBY_REQ
ALT0
Standby request from chip to PMIC
POWER_FAIL
ALT0
Power fail interrupt from PMIC
TEST_MODE
ALT0
TCU
Chip enter into test mode when TEST_MODE pin is asserted.
OSC24M_EXTAL
ALT0
24M Oscillator
24 MHz oscillator analog pin
OSC24M_XTAL
ALT0
OSC32K_EXTAL
ALT0
OSC32K_XTAL
ALT0
32 kHz oscillator analog pin
OSC_BYP
ALT0
32 kHz oscillator bypass-control pin
4.5
24 MHz oscillator analog pin
32K Oscillator
32 kHz oscillator analog pin
Register Memory Map
The IOMUX consists of three modules:
• IOMUX Module which contains the signals muxing logic
• Observe Module which contains the interrupt observability logic
• IOMUX_CTL Module which contains the muxing modes, observe and pin settings control logic
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External Signals and Pin Multiplexing
Table 4-15 shows the base addresses of IOMUX_CTL and the detailed register memory map. See the
system memory map for the IOMUXC_BASE_ADDR.
Table 4-15. IOMUX_CTL Memory Map
Base Address Offset
Register Name
Comment
0x0000
IOMUXC_GPR1
0x0004
IOMUXC_OBSERVE_INT_MUX
0x0008
IOMUXC_SW_MUX_CTL_PAD_A10
0x000c
IOMUXC_SW_MUX_CTL_PAD_A13
—
0x0010
IOMUXC_SW_MUX_CTL_PAD_A14
—
0x0014
IOMUXC_SW_MUX_CTL_PAD_A15
—
0x0018
IOMUXC_SW_MUX_CTL_PAD_A16
—
0x001c
IOMUXC_SW_MUX_CTL_PAD_A17
—
0x0020
IOMUXC_SW_MUX_CTL_PAD_A18
—
0x0024
IOMUXC_SW_MUX_CTL_PAD_A19
—
0x0028
IOMUXC_SW_MUX_CTL_PAD_A20
—
0x002c
IOMUXC_SW_MUX_CTL_PAD_A21
—
0x0030
IOMUXC_SW_MUX_CTL_PAD_A22
—
0x0034
IOMUXC_SW_MUX_CTL_PAD_A23
—
0x0038
IOMUXC_SW_MUX_CTL_PAD_A24
—
0x003c
IOMUXC_SW_MUX_CTL_PAD_A25
—
0x0040
IOMUXC_SW_MUX_CTL_PAD_EB0
—
0x0044
IOMUXC_SW_MUX_CTL_PAD_EB1
—
0x0048
IOMUXC_SW_MUX_CTL_PAD_OE
—
0x004c
IOMUXC_SW_MUX_CTL_PAD_CS0
—
0x0050
IOMUXC_SW_MUX_CTL_PAD_CS1
—
0x0054
IOMUXC_SW_MUX_CTL_PAD_CS4
—
0x0058
IOMUXC_SW_MUX_CTL_PAD_CS5
—
0x005c
IOMUXC_SW_MUX_CTL_PAD_NF_CE0
—
0x0060
IOMUXC_SW_MUX_CTL_PAD_ECB
—
0x0064
IOMUXC_SW_MUX_CTL_PAD_LBA
—
0x0068
IOMUXC_SW_MUX_CTL_PAD_BCLK
—
0x006c
IOMUXC_SW_MUX_CTL_PAD_RW
—
0x0070
IOMUXC_SW_MUX_CTL_PAD_NFWE_B
—
0x0074
IOMUXC_SW_MUX_CTL_PAD_NFRE_B
—
0x0078
IOMUXC_SW_MUX_CTL_PAD_NFALE
—
GPR register
INT_OBSRV register
SW_MUX_CTL register
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External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x007c
IOMUXC_SW_MUX_CTL_PAD_NFCLE
—
0x0080
IOMUXC_SW_MUX_CTL_PAD_NFWP_B
—
0x0084
IOMUXC_SW_MUX_CTL_PAD_NFRB
—
0x0088
IOMUXC_SW_MUX_CTL_PAD_D15
—
0x008c
IOMUXC_SW_MUX_CTL_PAD_D14
—
0x0090
IOMUXC_SW_MUX_CTL_PAD_D13
—
0x0094
IOMUXC_SW_MUX_CTL_PAD_D12
—
0x0098
IOMUXC_SW_MUX_CTL_PAD_D11
—
0x009c
IOMUXC_SW_MUX_CTL_PAD_D10
—
0x00a0
IOMUXC_SW_MUX_CTL_PAD_D9
—
0x00a4
IOMUXC_SW_MUX_CTL_PAD_D8
—
0x00a8
IOMUXC_SW_MUX_CTL_PAD_D7
—
0x00ac
IOMUXC_SW_MUX_CTL_PAD_D6
—
0x00b0
IOMUXC_SW_MUX_CTL_PAD_D5
—
0x00b4
IOMUXC_SW_MUX_CTL_PAD_D4
—
0x00b8
IOMUXC_SW_MUX_CTL_PAD_D3
—
0x00bc
IOMUXC_SW_MUX_CTL_PAD_D2
—
0x00c0
IOMUXC_SW_MUX_CTL_PAD_D1
—
0x00c4
IOMUXC_SW_MUX_CTL_PAD_D0
—
0x00c8
IOMUXC_SW_MUX_CTL_PAD_LD0
—
0x00cc
IOMUXC_SW_MUX_CTL_PAD_LD1
—
0x00d0
IOMUXC_SW_MUX_CTL_PAD_LD2
—
0x00d4
IOMUXC_SW_MUX_CTL_PAD_LD3
—
0x00d8
IOMUXC_SW_MUX_CTL_PAD_LD4
—
0x00dc
IOMUXC_SW_MUX_CTL_PAD_LD5
—
0x00e0
IOMUXC_SW_MUX_CTL_PAD_LD6
—
0x00e4
IOMUXC_SW_MUX_CTL_PAD_LD7
—
0x00e8
IOMUXC_SW_MUX_CTL_PAD_LD8
—
0x00ec
IOMUXC_SW_MUX_CTL_PAD_LD9
—
0x00f0
IOMUXC_SW_MUX_CTL_PAD_LD10
—
0x00f4
IOMUXC_SW_MUX_CTL_PAD_LD11
—
0x00f8
IOMUXC_SW_MUX_CTL_PAD_LD12
—
0x00fc
IOMUXC_SW_MUX_CTL_PAD_LD13
—
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External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0100
IOMUXC_SW_MUX_CTL_PAD_LD14
—
0x0104
IOMUXC_SW_MUX_CTL_PAD_LD15
—
0x0108
IOMUXC_SW_MUX_CTL_PAD_HSYNC
—
0x010c
IOMUXC_SW_MUX_CTL_PAD_VSYNC
—
0x0110
IOMUXC_SW_MUX_CTL_PAD_LSCLK
—
0x0114
IOMUXC_SW_MUX_CTL_PAD_OE_ACD
—
0x0118
IOMUXC_SW_MUX_CTL_PAD_CONTRAST
—
0x011c
IOMUXC_SW_MUX_CTL_PAD_PWM
—
0x0120
IOMUXC_SW_MUX_CTL_PAD_CSI_D2
—
0x0124
IOMUXC_SW_MUX_CTL_PAD_CSI_D3
—
0x0128
IOMUXC_SW_MUX_CTL_PAD_CSI_D4
—
0x012c
IOMUXC_SW_MUX_CTL_PAD_CSI_D5
—
0x0130
IOMUXC_SW_MUX_CTL_PAD_CSI_D6
—
0x0134
IOMUXC_SW_MUX_CTL_PAD_CSI_D7
—
0x0138
IOMUXC_SW_MUX_CTL_PAD_CSI_D8
—
0x013c
IOMUXC_SW_MUX_CTL_PAD_CSI_D9
—
0x0140
IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK
—
0x0144
IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC
—
0x0148
IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC
—
0x014c
IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK
—
0x0150
IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK
—
0x0154
IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT
—
0x0158
IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI
—
0x015c
IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO
—
0x0160
IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0
—
0x0164
IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1
—
0x0168
IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK
—
0x016c
IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY
—
0x0170
IOMUXC_SW_MUX_CTL_PAD_UART1_RXD
—
0x0174
IOMUXC_SW_MUX_CTL_PAD_UART1_TXD
—
0x0178
IOMUXC_SW_MUX_CTL_PAD_UART1_RTS
—
0x017c
IOMUXC_SW_MUX_CTL_PAD_UART1_CTS
—
0x0180
IOMUXC_SW_MUX_CTL_PAD_UART2_RXD
—
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External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0184
IOMUXC_SW_MUX_CTL_PAD_UART2_TXD
—
0x0188
IOMUXC_SW_MUX_CTL_PAD_UART2_RTS
—
0x018c
IOMUXC_SW_MUX_CTL_PAD_UART2_CTS
—
0x0190
IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
—
0x0194
IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
—
0x0198
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0
—
0x019c
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
—
0x01a0
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2
—
0x01a4
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3
—
0x01a8
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW0
—
0x01ac
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW1
—
0x01b0
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW2
—
0x01b4
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW3
—
0x01b8
IOMUXC_SW_MUX_CTL_PAD_KPP_COL0
—
0x01bc
IOMUXC_SW_MUX_CTL_PAD_KPP_COL1
—
0x01c0
IOMUXC_SW_MUX_CTL_PAD_KPP_COL2
—
0x01c4
IOMUXC_SW_MUX_CTL_PAD_KPP_COL3
—
0x01c8
IOMUXC_SW_MUX_CTL_PAD_FEC_MDC
—
0x01cc
IOMUXC_SW_MUX_CTL_PAD_FEC_MDIO
—
0x01d0
IOMUXC_SW_MUX_CTL_PAD_FEC_TDATA0
—
0x01d4
IOMUXC_SW_MUX_CTL_PAD_FEC_TDATA1
—
0x01d8
IOMUXC_SW_MUX_CTL_PAD_FEC_TX_EN
—
0x01dc
IOMUXC_SW_MUX_CTL_PAD_FEC_RDATA0
—
0x01e0
IOMUXC_SW_MUX_CTL_PAD_FEC_RDATA1
—
0x01e4
IOMUXC_SW_MUX_CTL_PAD_FEC_RX_DV
—
0x01e8
IOMUXC_SW_MUX_CTL_PAD_FEC_TX_CLK
—
0x01ec
IOMUXC_SW_MUX_CTL_PAD_RTCK
—
0x01f0
IOMUXC_SW_MUX_CTL_PAD_DE_B
—
0x01f4
IOMUXC_SW_MUX_CTL_PAD_GPIO_A
—
0x01f8
IOMUXC_SW_MUX_CTL_PAD_GPIO_B
—
0x01fc
IOMUXC_SW_MUX_CTL_PAD_GPIO_C
—
0x0200
IOMUXC_SW_MUX_CTL_PAD_GPIO_D
—
0x0204
IOMUXC_SW_MUX_CTL_PAD_GPIO_E
—
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External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0208
IOMUXC_SW_MUX_CTL_PAD_GPIO_F
—
0x020c
IOMUXC_SW_MUX_CTL_PAD_EXT_ARMCLK
—
0x0210
IOMUXC_SW_MUX_CTL_PAD_UPLL_BYPCLK
—
0x0214
IOMUXC_SW_MUX_CTL_PAD_VSTBY_REQ
—
0x0218
IOMUXC_SW_MUX_CTL_PAD_VSTBY_ACK
—
0x021c
IOMUXC_SW_MUX_CTL_PAD_POWER_FAIL
—
0x0220
IOMUXC_SW_MUX_CTL_PAD_CLKO
—
0x0224
IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE0
—
0x0228
IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE1
—
0x022c
IOMUXC_SW_PAD_CTL_PAD_A13
0x0230
IOMUXC_SW_PAD_CTL_PAD_A14
—
0x0234
IOMUXC_SW_PAD_CTL_PAD_A15
—
0x0238
IOMUXC_SW_PAD_CTL_PAD_A17
—
0x023c
IOMUXC_SW_PAD_CTL_PAD_A18
—
0x0240
IOMUXC_SW_PAD_CTL_PAD_A19
—
0x0244
IOMUXC_SW_PAD_CTL_PAD_A20
—
0x0248
IOMUXC_SW_PAD_CTL_PAD_A21
—
0x024c
IOMUXC_SW_PAD_CTL_PAD_A23
—
0x0250
IOMUXC_SW_PAD_CTL_PAD_A24
—
0x0254
IOMUXC_SW_PAD_CTL_PAD_A25
—
0x0258
IOMUXC_SW_PAD_CTL_PAD_EB0
—
0x025c
IOMUXC_SW_PAD_CTL_PAD_EB1
—
0x0260
IOMUXC_SW_PAD_CTL_PAD_OE
—
0x0264
IOMUXC_SW_PAD_CTL_PAD_CS4
—
0x0268
IOMUXC_SW_PAD_CTL_PAD_CS5
—
0x026c
IOMUXC_SW_PAD_CTL_PAD_NF_CE0
—
0x0270
IOMUXC_SW_PAD_CTL_PAD_ECB
—
0x0274
IOMUXC_SW_PAD_CTL_PAD_LBA
—
0x0278
IOMUXC_SW_PAD_CTL_PAD_RW
—
0x027c
IOMUXC_SW_PAD_CTL_PAD_NFRB
—
0x0280
IOMUXC_SW_PAD_CTL_PAD_D15
—
0x0284
IOMUXC_SW_PAD_CTL_PAD_D14
—
0x0288
IOMUXC_SW_PAD_CTL_PAD_D13
—
SW_PAD_CTL register
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External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x028c
IOMUXC_SW_PAD_CTL_PAD_D12
—
0x0290
IOMUXC_SW_PAD_CTL_PAD_D11
—
0x0294
IOMUXC_SW_PAD_CTL_PAD_D10
—
0x0298
IOMUXC_SW_PAD_CTL_PAD_D9
—
0x029c
IOMUXC_SW_PAD_CTL_PAD_D8
—
0x02a0
IOMUXC_SW_PAD_CTL_PAD_D7
—
0x02a4
IOMUXC_SW_PAD_CTL_PAD_D6
—
0x02a8
IOMUXC_SW_PAD_CTL_PAD_D5
—
0x02ac
IOMUXC_SW_PAD_CTL_PAD_D4
—
0x02b0
IOMUXC_SW_PAD_CTL_PAD_D3
—
0x02b4
IOMUXC_SW_PAD_CTL_PAD_D2
—
0x02b8
IOMUXC_SW_PAD_CTL_PAD_D1
—
0x02bc
IOMUXC_SW_PAD_CTL_PAD_D0
—
0x02c0
IOMUXC_SW_PAD_CTL_PAD_LD0
—
0x02c4
IOMUXC_SW_PAD_CTL_PAD_LD1
—
0x02c8
IOMUXC_SW_PAD_CTL_PAD_LD2
—
0x02cc
IOMUXC_SW_PAD_CTL_PAD_LD3
—
0x02d0
IOMUXC_SW_PAD_CTL_PAD_LD4
—
0x02d4
IOMUXC_SW_PAD_CTL_PAD_LD5
—
0x02d8
IOMUXC_SW_PAD_CTL_PAD_LD6
—
0x02dc
IOMUXC_SW_PAD_CTL_PAD_LD7
—
0x02e0
IOMUXC_SW_PAD_CTL_PAD_LD8
—
0x02e4
IOMUXC_SW_PAD_CTL_PAD_LD9
—
0x02e8
IOMUXC_SW_PAD_CTL_PAD_LD10
—
0x02ec
IOMUXC_SW_PAD_CTL_PAD_LD11
—
0x02f0
IOMUXC_SW_PAD_CTL_PAD_LD12
—
0x02f4
IOMUXC_SW_PAD_CTL_PAD_LD13
—
0x02f8
IOMUXC_SW_PAD_CTL_PAD_LD14
—
0x02fc
IOMUXC_SW_PAD_CTL_PAD_LD15
—
0x0300
IOMUXC_SW_PAD_CTL_PAD_HSYNC
—
0x0304
IOMUXC_SW_PAD_CTL_PAD_VSYNC
—
0x0308
IOMUXC_SW_PAD_CTL_PAD_LSCLK
—
0x030c
IOMUXC_SW_PAD_CTL_PAD_OE_ACD
—
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External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0310
IOMUXC_SW_PAD_CTL_PAD_CONTRAST
—
0x0314
IOMUXC_SW_PAD_CTL_PAD_PWM
—
0x0318
IOMUXC_SW_PAD_CTL_PAD_CSI_D2
—
0x031c
IOMUXC_SW_PAD_CTL_PAD_CSI_D3
—
0x0320
IOMUXC_SW_PAD_CTL_PAD_CSI_D4
—
0x0324
IOMUXC_SW_PAD_CTL_PAD_CSI_D5
—
0x0328
IOMUXC_SW_PAD_CTL_PAD_CSI_D6
—
0x032c
IOMUXC_SW_PAD_CTL_PAD_CSI_D7
—
0x0330
IOMUXC_SW_PAD_CTL_PAD_CSI_D8
—
0x0334
IOMUXC_SW_PAD_CTL_PAD_CSI_D9
—
0x0338
IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK
—
0x033c
IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC
—
0x0340
IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC
—
0x0344
IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK
—
0x0348
IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK
—
0x034c
IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT
—
0x0350
IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI
—
0x0354
IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO
—
0x0358
IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0
—
0x035c
IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1
—
0x0360
IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK
—
0x0364
IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY
—
0x0368
IOMUXC_SW_PAD_CTL_PAD_UART1_RXD
—
0x036c
IOMUXC_SW_PAD_CTL_PAD_UART1_TXD
—
0x0370
IOMUXC_SW_PAD_CTL_PAD_UART1_RTS
—
0x0374
IOMUXC_SW_PAD_CTL_PAD_UART1_CTS
—
0x0378
IOMUXC_SW_PAD_CTL_PAD_UART2_RXD
—
0x037c
IOMUXC_SW_PAD_CTL_PAD_UART2_TXD
—
0x0380
IOMUXC_SW_PAD_CTL_PAD_UART2_RTS
—
0x0384
IOMUXC_SW_PAD_CTL_PAD_UART2_CTS
—
0x0388
IOMUXC_SW_PAD_CTL_PAD_SD1_CMD
—
0x038c
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK
—
0x0390
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0
—
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-26
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0394
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1
—
0x0398
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2
—
0x039c
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3
—
0x03a0
IOMUXC_SW_PAD_CTL_PAD_KPP_ROW0
—
0x03a4
IOMUXC_SW_PAD_CTL_PAD_KPP_ROW1
—
0x03a8
IOMUXC_SW_PAD_CTL_PAD_KPP_ROW2
—
0x03ac
IOMUXC_SW_PAD_CTL_PAD_KPP_ROW3
—
0x03b0
IOMUXC_SW_PAD_CTL_PAD_KPP_COL0
—
0x03b4
IOMUXC_SW_PAD_CTL_PAD_KPP_COL1
—
0x03b8
IOMUXC_SW_PAD_CTL_PAD_KPP_COL2
—
0x03bc
IOMUXC_SW_PAD_CTL_PAD_KPP_COL3
—
0x03c0
IOMUXC_SW_PAD_CTL_PAD_FEC_MDC
—
0x03c4
IOMUXC_SW_PAD_CTL_PAD_FEC_MDIO
—
0x03c8
IOMUXC_SW_PAD_CTL_PAD_FEC_TDATA0
—
0x03cc
IOMUXC_SW_PAD_CTL_PAD_FEC_TDATA1
—
0x03d0
IOMUXC_SW_PAD_CTL_PAD_FEC_TX_EN
—
0x03d4
IOMUXC_SW_PAD_CTL_PAD_FEC_RDATA0
—
0x03d8
IOMUXC_SW_PAD_CTL_PAD_FEC_RDATA1
—
0x03dc
IOMUXC_SW_PAD_CTL_PAD_FEC_RX_DV
—
0x03e0
IOMUXC_SW_PAD_CTL_PAD_FEC_TX_CLK
—
0x03e4
IOMUXC_SW_PAD_CTL_PAD_RTCK
—
0x03e8
IOMUXC_SW_PAD_CTL_PAD_TDO
—
0x03ec
IOMUXC_SW_PAD_CTL_PAD_DE_B
—
0x03f0
IOMUXC_SW_PAD_CTL_PAD_GPIO_A
—
0x03f4
IOMUXC_SW_PAD_CTL_PAD_GPIO_B
—
0x03f8
IOMUXC_SW_PAD_CTL_PAD_GPIO_C
—
0x03fc
IOMUXC_SW_PAD_CTL_PAD_GPIO_D
—
0x0400
IOMUXC_SW_PAD_CTL_PAD_GPIO_E
—
0x0404
IOMUXC_SW_PAD_CTL_PAD_GPIO_F
—
0x0408
IOMUXC_SW_PAD_CTL_PAD_VSTBY_REQ
—
0x040c
IOMUXC_SW_PAD_CTL_PAD_VSTBY_ACK
—
0x0410
IOMUXC_SW_PAD_CTL_PAD_POWER_FAIL
—
0x0414
IOMUXC_SW_PAD_CTL_PAD_CLKO
—
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-27
External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0418
IOMUXC_SW_PAD_CTL_GRP_DVS_MISC
0x041c
IOMUXC_SW_PAD_CTL_GRP_DSE_FEC
—
0x0420
IOMUXC_SW_PAD_CTL_GRP_DVS_JTAG
—
0x0424
IOMUXC_SW_PAD_CTL_GRP_DSE_NFC
—
0x0428
IOMUXC_SW_PAD_CTL_GRP_DSE_CSI
—
0x042c
IOMUXC_SW_PAD_CTL_GRP_DSE_WEIM
—
0x0430
IOMUXC_SW_PAD_CTL_GRP_DSE_DDR
—
0x0434
IOMUXC_SW_PAD_CTL_GRP_DVS_CCM
—
0x0438
IOMUXC_SW_PAD_CTL_GRP_DSE_KPP
—
0x043c
IOMUXC_SW_PAD_CTL_GRP_DSE_SDHC1
—
0x0440
IOMUXC_SW_PAD_CTL_GRP_DSE_LCD
—
0x0444
IOMUXC_SW_PAD_CTL_GRP_DSE_UART
—
0x0448
IOMUXC_SW_PAD_CTL_GRP_DVS_NFC
—
0x044c
IOMUXC_SW_PAD_CTL_GRP_DVS_CSI
—
0x0450
IOMUXC_SW_PAD_CTL_GRP_DSE_CSPI1
—
0x0454
IOMUXC_SW_PAD_CTL_GRP_DDRTYPE
—
0x0458
IOMUXC_SW_PAD_CTL_GRP_DVS_SDHC1
—
0x045c
IOMUXC_SW_PAD_CTL_GRP_DVS_LCD
—
0x0460
IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
0x0464
IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
—
0x0468
IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT
—
0x046c
IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT
—
0x0470
IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
—
0x0474
IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
—
0x0478
IOMUXC_AUDMUX_P7_INPUT_DA_AMX_SELECT_INPUT
—
0x047c
IOMUXC_AUDMUX_P7_INPUT_TXFS_AMX_SELECT_INPUT
—
0x0480
IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT
—
0x0484
IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT
—
0x0488
IOMUXC_CSI_IPP_CSI_D_0_SELECT_INPUT
—
0x048c
IOMUXC_CSI_IPP_CSI_D_1_SELECT_INPUT
—
0x0490
IOMUXC_CSPI1_IPP_IND_SS3_B_SELECT_INPUT
—
0x0494
IOMUXC_CSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT
—
0x0498
IOMUXC_CSPI2_IPP_IND_DATAREADY_B_SELECT_INPUT
—
SW_PAD_CTL_GRP register
SW_SELECT_INPUT register
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-28
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x049c
IOMUXC_CSPI2_IPP_IND_MISO_SELECT_INPUT
—
0x04a0
IOMUXC_CSPI2_IPP_IND_MOSI_SELECT_INPUT
—
0x04a4
IOMUXC_CSPI2_IPP_IND_SS0_B_SELECT_INPUT
—
0x04a8
IOMUXC_CSPI2_IPP_IND_SS1_B_SELECT_INPUT
—
0x04ac
IOMUXC_CSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT
—
0x04b0
IOMUXC_CSPI3_IPP_IND_DATAREADY_B_SELECT_INPUT
—
0x04b4
IOMUXC_CSPI3_IPP_IND_MISO_SELECT_INPUT
—
0x04b8
IOMUXC_CSPI3_IPP_IND_MOSI_SELECT_INPUT
—
0x04bc
IOMUXC_CSPI3_IPP_IND_SS0_B_SELECT_INPUT
—
0x04c0
IOMUXC_CSPI3_IPP_IND_SS1_B_SELECT_INPUT
—
0x04c4
IOMUXC_CSPI3_IPP_IND_SS2_B_SELECT_INPUT
—
0x04c8
IOMUXC_CSPI3_IPP_IND_SS3_B_SELECT_INPUT
—
0x04cc
IOMUXC_ESDHC1_IPP_DAT4_IN_SELECT_INPUT
—
0x04d0
IOMUXC_ESDHC1_IPP_DAT5_IN_SELECT_INPUT
—
0x04d4
IOMUXC_ESDHC1_IPP_DAT6_IN_SELECT_INPUT
—
0x04d8
IOMUXC_ESDHC1_IPP_DAT7_IN_SELECT_INPUT
—
0x04dc
IOMUXC_ESDHC2_IPP_CARD_CLK_IN_SELECT_INPUT
—
0x04e0
IOMUXC_ESDHC2_IPP_CMD_IN_SELECT_INPUT
—
0x04e4
IOMUXC_ESDHC2_IPP_DAT0_IN_SELECT_INPUT
—
0x04e8
IOMUXC_ESDHC2_IPP_DAT1_IN_SELECT_INPUT
—
0x04ec
IOMUXC_ESDHC2_IPP_DAT2_IN_SELECT_INPUT
—
0x04f0
IOMUXC_ESDHC2_IPP_DAT3_IN_SELECT_INPUT
—
0x04f4
IOMUXC_ESDHC2_IPP_DAT4_IN_SELECT_INPUT
—
0x04f8
IOMUXC_ESDHC2_IPP_DAT5_IN_SELECT_INPUT
—
0x04fc
IOMUXC_ESDHC2_IPP_DAT6_IN_SELECT_INPUT
—
0x0500
IOMUXC_ESDHC2_IPP_DAT7_IN_SELECT_INPUT
—
0x0504
IOMUXC_FEC_FEC_COL_SELECT_INPUT
—
0x0508
IOMUXC_FEC_FEC_CRS_SELECT_INPUT
—
0x050c
IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT
—
0x0510
IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT
—
0x0514
IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT
—
0x0518
IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT
—
0x051c
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT
—
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-29
External Signals and Pin Multiplexing
Table 4-15. IOMUX_CTL Memory Map (continued)
Base Address Offset
Register Name
Comment
0x0520
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
—
0x0524
IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT
—
0x0528
IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT
—
0x052c
IOMUXC_KPP_IPP_IND_COL_4_SELECT_INPUT
—
0x0530
IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
—
0x0534
IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
—
0x0538
IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
—
0x053c
IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT
—
0x0540
IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
—
0x0544
IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
—
0x0548
IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
—
0x054c
IOMUXC_SIM1_PIN_SIM_RCVD1_IN_SELECT_INPUT
—
0x0550
IOMUXC_SIM1_PIN_SIM_SIMPD1_SELECT_INPUT
—
0x0554
IOMUXC_SIM1_SIM_RCVD1_IO_SELECT_INPUT
—
0x0558
IOMUXC_SIM2_PIN_SIM_RCVD1_IN_SELECT_INPUT
—
0x055c
IOMUXC_SIM2_PIN_SIM_SIMPD1_SELECT_INPUT
—
0x0560
IOMUXC_SIM2_SIM_RCVD1_IO_SELECT_INPUT
—
0x0564
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
—
0x0568
IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
—
0x056c
IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT
—
0x0570
IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
—
0x0574
IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
—
0x0578
IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
—
0x057c
IOMUXC_USB_TOP_IPP_IND_OTG_USB_OC_SELECT_INPUT
—
0x0580
IOMUXC_USB_TOP_IPP_IND_UH2_USB_OC_SELECT_INPUT
—
4.6
Daisy Chain List
Table 4-16 lists all the instances and ports which are involved in Daisy Chain, and also the corresponding
values of SW_SELECT_INPUT registers. SW_SELECT_INPUT registers follow the naming convention
of: IOMUXC_<Instance>_<Port>_SELECT_INPUT.
For example, if pin EB1 need to work as the input port p4_input_da_amx of instance AUDMUX, then
configure pin EB1 to work in ALT4 mode, and configure register
IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT to value 0x0 to solve Daisy Chain.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-30
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
AUDMUX
p4_input_da_amx
EB1
ALT4
0x0
FEC_MDIO
ALT2
0x1
EB0
ALT4
0x0
FEC_MDC
ALT2
0x1
CS4
ALT4
0x0
FEC_TX_EN
ALT2
0x1
CS5
ALT4
0x0
FEC_RDATA0
ALT2
0x1
OE
ALT4
0x0
FEC_TDATA0
ALT2
0x1
RW
ALT4
0x0
FEC_TDATA1
ALT2
0x1
SD1_DATA1
ALT3
0x0
POWER_FAIL
ALT4
0x1
SD1_DATA0
ALT3
0x0
VSTBY_REQ
ALT4
0x1
FEC_RDATA0
ALT4
0x0
GPIO_B
ALT6
0x1
FEC_RX_DV
ALT4
0x0
GPIO_D
ALT6
0x1
LD0
ALT2
0x0
UART1_RTS
ALT1
0x1
KPP_ROW2
ALT3
0x2
LD1
ALT2
0x0
UART1_CTS
ALT1
0x1
KPP_ROW3
ALT3
0x2
NF_CE0
ALT1
0x0
VSTBY_ACK
ALT2
0x1
p4_input_db_amx
p4_input_rxclk_amx
p4_input_rxfs_amx
p4_input_txclk_amx
p4_input_txfs_amx
p7_input_da_amx
p7_input_txfs_amx
CAN1
CAN2
CSI
ipp_ind_canrx
ipp_ind_canrx
ipp_csi_d[0]
ipp_csi_d[1]
CSPI1
ipp_ind_ss3_b
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-31
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List (continued)
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
CSPI2
ipp_cspi_clk_in
LD14
ALT2
0x0
SD1_DATA0
ALT1
0x1
LD15
ALT2
0x0
SD1_DATA1
ALT1
0x1
LD13
ALT2
0x0
SD1_CLK
ALT1
0x1
LD12
ALT2
0x0
SD1_CMD
ALT1
0x1
OE_ACD
ALT2
0x0
SD1_DATA2
ALT1
0x1
CONTRAST
ALT2
0x0
SD1_DATA3
ALT1
0x1
ECB
ALT6
0x0
CSI_D4
ALT7
0x1
LBA
ALT6
0x0
CSI_D5
ALT7
0x1
CS5
ALT6
0x0
CSI_D3
ALT7
0x1
CS4
ALT6
0x0
CSI_D2
ALT7
0x1
EB0
ALT6
0x0
CSI_D6
ALT7
0x1
EB1
ALT6
0x0
CSI_D7
ALT7
0x1
CSI_D8
ALT7
0x0
GPIO_D
ALT7
0x1
CSI_D9
ALT7
0x0
UART2_CTS
ALT6
0x1
ipp_ind_dataready_b
ipp_ind_miso
ipp_ind_mosi
ipp_ind_ss0_b
ipp_ind_ss1_b
CSPI3
ipp_cspi_clk_in
ipp_ind_dataready_b
ipp_ind_miso
ipp_ind_mosi
ipp_ind_ss0_b
ipp_ind_ss1_b
ipp_ind_ss2_b
ipp_ind_ss3_b
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-32
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List (continued)
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
ESDHC1
ipp_dat4_in
D12
ALT6
0x0
UART2_CTS
ALT1
0x1
D13
ALT6
0x0
UART2_RTS
ALT1
0x1
D14
ALT6
0x0
UART2_TXD
ALT1
0x1
D15
ALT6
0x0
UART2_RXD
ALT1
0x1
ipp_dat5_in
ipp_dat6_in
ipp_dat7_in
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-33
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List (continued)
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
ESDHC2
ipp_card_clk_in
LD9
ALT6
0x0
CSI_D7
ALT2
0x1
FEC_MDIO
ALT1
0x2
LD8
ALT6
0x0
CSI_D6
ALT2
0x1
FEC_MDC
ALT1
0x2
LD10
ALT6
0x0
CSI_MCLK
ALT2
0x1
FEC_TDATA0
ALT1
0x2
LD11
ALT6
0x0
CSI_VSYNC
ALT2
0x1
FEC_TDATA1
ALT1
0x2
LD12
ALT6
0x0
CSI_HSYNC
ALT2
0x1
FEC_TX_EN
ALT1
0x2
LD13
ALT6
0x0
CSI_PIXCLK
ALT2
0x1
FEC_RDATA0
ALT1
0x2
CSI_D2
ALT2
0x0
FEC_RDATA1
ALT2
0x1
CSI_D3
ALT2
0x0
FEC_RX_DV
ALT2
0x1
CSI_D4
ALT2
0x0
FEC_TX_CLK
ALT2
0x1
CSI_D5
ALT2
0x0
RTCK
ALT2
0x1
ipp_cmd_in
ipp_dat0_in
ipp_dat1_in
ipp_dat2_in
ipp_dat3_in
ipp_dat4_in
ipp_dat5_in
ipp_dat6_in
ipp_dat7_in
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-34
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List (continued)
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
FEC
fec_col
A18
ALT7
0x0
LD9
ALT5
0x1
UART2_RTS
ALT2
0x2
A25
ALT7
0x0
CONTRAST
ALT5
0x1
SD1_DATA3
ALT2
0x2
A20
ALT7
0x0
LD11
ALT5
0x1
SD1_CMD
ALT2
0x2
A21
ALT7
0x0
LD12
ALT5
0x1
SD1_CLK
ALT2
0x2
A24
ALT7
0x0
LD15
ALT5
0x1
SD1_DATA2
ALT2
0x2
A19
ALT7
0x0
LD10
ALT5
0x1
UART2_CTS
ALT2
0x2
FEC_RDATA1
ALT1
0x0
GPIO_C
ALT2
0x1
FEC_RX_DV
ALT1
0x0
GPIO_D
ALT2
0x1
HSYNC
ALT2
0x0
GPIO_A
ALT4
0x1
GPIO_E
ALT1
0x2
VSYNC
ALT2
0x0
CSPI1_SS1
ALT1
0x1
GPIO_B
ALT4
0x2
fec_crs
fec_rdata[2]
fec_rdata[3]
fec_rx_clk
fec_rx_er
I2C2
I2C2
I2C3
I2C3
ipp_scl_in
ipp_sda_in
ipp_scl_in
ipp_sda_in
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-35
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List (continued)
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
KPP
ipp_ind_col[4]
FEC_RDATA1
ALT6
0x0
GPIO_C
ALT3
0x1
FEC_RX_DV
ALT6
0x0
GPIO_D
ALT3
0x1
LD14
ALT4
0x0
CSI_D8
ALT1
0x1
LD15
ALT4
0x0
CSI_D9
ALT1
0x1
FEC_TX_EN
ALT6
0x0
GPIO_A
ALT3
0x1
FEC_RDATA0
ALT6
0x0
GPIO_B
ALT3
0x1
LD12
ALT4
0x0
CSI_D6
ALT1
0x1
LD13
ALT4
0x0
CSI_D7
ALT1
0x1
A19
ALT6
0x0
LD5
ALT4
0x1
A18
ALT6
0x0
LD4
ALT4
0x1
A17
ALT6
0x0
LD3
ALT4
0x1
A25
ALT6
0x0
OE_ACD
ALT4
0x1
A24
ALT6
0x0
LSCLK
ALT4
0x1
A23
ALT6
0x0
VSYNC
ALT4
0x1
CSPI1_SS1
ALT2
0x0
KPP_ROW2
ALT1
0x1
CSPI1_MOSI
ALT2
0x0
KPP_ROW0
ALT1
0x1
ipp_ind_col[5]
ipp_ind_col[6]
ipp_ind_col[7]
ipp_ind_row[4]
ipp_ind_row[5]
ipp_ind_row[6]
ipp_ind_row[7]
SIM1
pin_sim_rcvd1_in
pin_sim_simpd1
sim_rcvd1_io
SIM2
pin_sim_rcvd1_in
pin_sim_simpd1
sim_rcvd1_io
UART3
ipp_uart_rts_b
ipp_uart_rxd_mux
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-36
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-16. Daisy Chain List (continued)
Instance
Input Port
Pin
Mode
SW_SELECT_INPUT Value
UART4
ipp_uart_rts_b
LD10
ALT2
0x0
KPP_COL2
ALT1
0x1
VSTBY_REQ
ALT6
0x2
LD8
ALT2
0x0
KPP_COL0
ALT1
0x1
GPIO_E
ALT6
0x2
CS5
ALT3
0x0
CSI_D4
ALT1
0x1
LBA
ALT3
0x0
CSI_D2
ALT1
0x1
D10
ALT6
0x0
GPIO_B
ALT2
0x1
D8
ALT6
0x0
PWM
ALT6
0x1
ipp_uart_rxd_mux
UART5
ipp_uart_rts_b
ipp_uart_rxd_mux
USB_top
ipp_ind_otg_usb_oc
ipp_ind_uh2_usb_oc
4.7
Pin Multiplexing
This section shows pin muxing options. Both a high-level picture and detailed pin muxing options are
presented.
4.7.1
Pin Multiplexing Overview
Table 4-17 shows the main high-level pin muxing options.
.
Table 4-17. i.MX25 Simplified High-level Pin Muxing
i.MX25
Default Mode
Pin Num
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
21
LCDC
SLCDC (16)
CSI (8)
PATA (21)
SIM1 P1(6)
GPIO
SIM2 P1(2)
GPIO
UART4 (4)
SSI-P3 (4)
FEC (9)
CSPI2 (4)
KPP (4)
—
I2C3 (2)
SIM2 P1 (4)
SLCDC(2)
CSPI2 (2)
GPT4 (2)
—
1
PWM1
Mux Mode
—
ALT6
ALT7
USB ULPI (8) GPIO_BOO
T (20)
SDIO2 (6)
SSI-P3 (2)
GPIO
USB ULPI (6)
GPIO
—
PWM (1)
GPIO
WDOG (1)
—
GPIO
GPIO_BOO
T (1)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-37
External Signals and Pin Multiplexing
Table 4-17. i.MX25 Simplified High-level Pin Muxing (continued)
i.MX25
Default Mode
Mux Mode
Pin Num
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
12
CSI
UART5 (4)
SDIO2 (6)
ESAI (12)
SIM1 P0 (6)
GPIO
CSPI3 (8)
KPP (4)
SSI-P6 (2)
—
GPIO
OTG ULPI
(12)
SSI-P6 (4)
SDIO2 (4)
SIM2 P0 (6)
GPIO
2
I2C1
—
—
—
—
GPIO
6
CSPI1
—
UART3 (4)
—
—
GPIO
LCDC_D[16]
(1)
PWM2 (1)
—
—
GPIO
I2C3 (1)
—
—
—
GPIO
GPIO_BOO
T (4)
SLCDC (12)
—
ETM (6)
4
UART1
CSI_D[1:0]
(2)
GPT3 (2)
—
—
GPIO
4
UART2
SDIO1 (4)
FEC (9)
GPT1 (2)
EPIT2 (1)
GPIO
CSPI2/CSPI
3 SS (2)
DMA_EVT
(3)
6
SDIO1
CSPI2 (6)
—
—
GPIO
SLCDC (6)
ETM (6)
8
KPP
UART3
—
—
GPIO
—
—
CSI_D[1:0]
(2)
—
GPIO
—
—
PATA (8)
CAN1
GPIO
KPP (4)
LCDC (8)
CAN2
GPIO
LCDC_D[16]
(1)
—
GPIO
—
—
KPP (4)
I2C3 (2)
—
CAN1 (2)
—
SSI-P5
UART4
9
FEC
SDIO2 (6)
SSI-P4 (6)
I2C2 (2)
SDIO2 (3)
PWM3 (1)
6
GPIO
PWM2 (1)
PWM3 (1)
PWM4 (1)
USB
PWR/OC (2)
—
—
I2C2 (2)
GPT2 (2)
WDOG (1)
CSPI1
SS (2)
—
CAN2 (2)
—
I2C3 (1)
LCDC_D[16]
(1)
—
SSI-P7 (4)
—
—
LCDC_D[17]
(1)
EPIT1 (1)
—
GPIO
CSPI2 SS
(1)
CSPI3 SS
(1)
UART4 (4)
ECT (2)
11
CCM
—
CSPI1 SS (1)
EPIT1 (1)
-
1
TCU
—
—
—
—
—
—
—
8
JTAG
O-WIRE (1)
SDIO2 (1)
—
—
—
—
—
30
DDR/SDRAM
—
—
—
—
—
—
—
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-38
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-17. i.MX25 Simplified High-level Pin Muxing (continued)
i.MX25
Default Mode
Pin Num
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
16
WEIM DATA
LCDC_D[23:
16]
—
—
—
—
eSDHC1 (4)
—
—
—
—
GPIO
USB
PWR/OC (4)
—
—
—
—
—
GPIO
SIM1 P1 (6)
—
—
—
—
—
GPIO
SIM2 P1 (6)
—
SSI-P4 (6)
GPIO
CSPI3 (6)
—
26
WEIM ADDR
Mux Mode
7
WEIM CTL
—
—
—
7
WEIM CS
NFC CS (3)
—
—
CSPI1 SS
(1)
—
—
—
GPIO
—
GPIO
ETM (3)
6
NFC
—
—
—
—
GPIO
—
ETM
2
FS USBPHY
—
—
—
—
—
—
—
5
HS USBPHY
—
—
—
—
—
—
—
9
ADC
—
—
—
—
—
—
—
7
DRYICE
—
—
—
—
—
—
—
2
OSC24M
—
—
—
—
—
—
—
4.7.2
Detailed Pin Multiplexing Description
Table 4-18 shows in detail the pin muxing and pad settings of each pin. The Pin Name column lists the
i.MX25 pins and the Instance column lists the instantiated on-chip IP modules. For each pin that supports
pin muxing, there is a related IOMUX cell for muxing control. Each IOMUX cell can support up to eight
muxing modes: ALT0–ALT7, where ALT0 is the default mode. The Pad Settings column shows the pad
characteristic setting of each pin.
Following is an example to clarify Table 4-18.
• Muxing Mode:
Pin A10 serves as the WEIM address pin of EMI module (ALT0 mode) or as a GPIO (ALT5 mode).
Select the desired working mode by programing the SW_MUX_CTL register of pin A10, see
Section 4.2.1, “Software Mux Control Registers (SW_MUX_CTL).”
• Pad Settings:
The A10 pin has following settings:
— Drive Strength—CFG (High), which means the default drive strength is set as high, and
software-configurable.
— Keeper—Enabled, which means internal keeper is enabled, and non-software-configurable.
— DDR Type—CFG(mDDR), which means the DDR type is set as mDDR mode at default, and
software-configurable.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-39
External Signals and Pin Multiplexing
Only characteristics with CFG ( ) are software-configurable, and then users can program SW_PAD_CTL
registers in IOMUX_CTL to select different setting values.
Table 4-18. i.MX25 Detailed Pin Muxing
Pin Name
A0
Mode
Port
Pad Settings
EMI
EIM_DA_L[0]
EMI
EIM_DA_L[1]
A2
EMI
EIM_DA_L[2]
A3
EMI
EIM_DA_L[3]
A4
EMI
EIM_DA_L[4]
A5
EMI
EIM_DA_L[5]
A6
EMI
EIM_DA_L[6]
A7
EMI
EIM_DA_L[7]
A8
EMI
EIM_DA_H[8]
A9
EMI
EIM_DA_H[9]
ALT0
EMI
EIM_DA_H[10]
ALT5
GPIO4
GPIO[0]
MA10
No Muxing
(ALT0)
EMI
MA10
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
A11
No Muxing
(ALT0)
EMI
EIM_DA_H[11]
EMI
EIM_DA_H[12]
Drive Strength—CFG (High)
Keeper—Enabled
DDR Type—CFG (mDDR)
ALT0
EMI
EIM_DA_H[13]
ALT5
GPIO4
GPIO[1]
ALT7
LCDC
LCDC_CLS
ALT0
EMI
EIM_DA_H2[14]
ALT5
GPIO2
GPIO[0]
ALT6
SIM1
CLK1
ALT7
LCDC
LCDC_SPL
ALT0
EMI
EIM_DA_H2[15]
ALT5
GPIO2
GPIO[1]
ALT6
SIM1
RST1
ALT7
LCDC
LCDC_PS
A1
A10
A12
A13
A14
A15
No Muxing
(ALT0)
Instance
Drive Strength—CFG (High)
Keeper—Enabled
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—Enabled
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Enabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Enabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Enabled)
DDR Type—CFG (mDDR)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-40
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
A16
A17
A18
A19
A20
A21
A22
A23
Mode
Instance
Port
ALT0
EMI
EIM_A[16]
ALT5
GPIO2
GPIO[2]
ALT6
SIM1
VEN1
ALT7
LCDC
LCDC_REV
ALT0
EMI
EIM_A[17]
ALT5
GPIO2
GPIO[3]
ALT6
SIM1
TX1
ALT7
FEC
TX_ERR
ALT0
EMI
EIM_A[18]
ALT5
GPIO2
GPIO[4]
ALT6
SIM1
PD1
ALT7
FEC
COL
ALT0
EMI
EIM_A[19]
ALT5
GPIO2
GPIO[5]
ALT6
SIM1
RX1
ALT7
FEC
RX_ERR
ALT0
EMI
EIM_A[20]
ALT5
GPIO2
GPIO[6]
ALT6
SIM2
CLK1
ALT7
FEC
RDATA[2]
ALT0
EMI
EIM_A[21]
ALT5
GPIO2
GPIO[7]
ALT6
SIM2
RST1
ALT7
FEC
RDATA[3]
ALT0
EMI
EIM_A[22]
ALT5
GPIO2
GPIO[8]
ALT6
SIM2
VEN1
ALT7
FEC
TDATA[2]
ALT0
EMI
EIM_A[23]
ALT5
GPIO2
GPIO[9]
ALT6
SIM2
TX1
ALT7
FEC
TDATA[3]
Pad Settings
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-41
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
A24
Mode
Instance
Port
ALT0
EMI
EIM_A[24]
ALT5
GPIO2
GPIO[10]
ALT6
SIM2
PD1
ALT7
FEC
RX_CLK
ALT0
EMI
EIM_A[25]
ALT5
GPIO2
GPIO[11]
ALT6
SIM2
RX1
ALT7
FEC
CRS
No Muxing
(ALT0)
EMI
DRAM_D[0]
EMI
DRAM_D[1]
SD2
EMI
DRAM_D[2]
SD3
EMI
DRAM_D[3]
SD4
EMI
DRAM_D[4]
SD5
EMI
DRAM_D[5]
SD6
EMI
DRAM_D[6]
SD7
EMI
DRAM_D[7]
SD8
EMI
DRAM_D[8]
SD9
EMI
DRAM_D[9]
SD10
EMI
DRAM_D[10]
SD11
EMI
DRAM_D[11]
SD12
EMI
DRAM_D[12]
SD13
EMI
DRAM_D[13]
SD14
EMI
DRAM_D[14]
SD15
EMI
DRAM_D[15]
EMI
EIM_SDBA1
EMI
EIM_SDBA0
DQM0
EMI
DRAM_DQM[0]
DQM1
EMI
DRAM_DQM[1]
RAS
EMI
DRAM_RAS
CAS
EMI
DRAM_CAS
SDWE
EMI
DRAM_SDWE
SDCKE0
EMI
DRAM_SDCKE[0]
SDCKE1
EMI
DRAM_SDCKE[1]
A25
SD0
SD1
SDBA1
SDBA0
No Muxing
(ALT0)
Pad Settings
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—Enabled
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-42
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
Mode
Instance
Port
Pad Settings
SDCLK
No Muxing
(ALT0)
EMI
DRAM_SDCLK
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
SDQS0
No Muxing
(ALT0)
EMI
DRAM_SDQS[0]
EMI
DRAM_SDQS[1]
Drive Strength—CFG (High)
Keeper—Enabled
DDR Type—CFG (mDDR)
ALT0
EMI
EIM_EB0_B
ALT4
AUDMUX
AUD4_TXD
ALT5
GPIO2
GPIO[12]
ALT6
CSPI3
SS0
ALT0
EMI
EIM_EB1_B
ALT4
AUDMUX
AUD4_RXD
ALT5
GPIO2
GPIO[13]
ALT6
CSPI3
SS1
ALT0
EMI
EIM_OE
ALT4
AUDMUX
AUD4_TXC
ALT5
GPIO2
GPIO[14]
ALT0
EMI
EIM_CS0
ALT5
GPIO4
GPIO[2]
ALT0
EMI
EIM_CS1
ALT1
EMI
NANDF_CE3
ALT5
GPIO4
GPIO[3]
No Muxing
(ALT0)
EMI
EIM_CS2
EMI
EIM_CS3
ALT0
EMI
EIM_CS4
ALT1
EMI
NANDF_CE1
ALT3
UART5
CTS
ALT4
AUDMUX
AUD4_RXC
ALT5
GPIO3
GPIO[20]
ALT6
CSPI3
MOSI
ALT7
ARM926P_PLATF TRSYNC
ORM
SDQS1
EB0
EB1
OE
CS0
CS1
CS2
CS3
CS4
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configure—CFG (100 KΩ PD)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (1.8 V)
Pull/Keep Select—Pull
Slew Rate—CFG (FAST)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-43
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
CS5
NF_CE0
ECB
LBA
BCLK
RW
Mode
Instance
Port
ALT0
EMI
EIM_CS5
ALT1
EMI
NANDF_CE2
ALT2
EMI
DTACK_B
ALT3
UART5
RTS
ALT4
AUDMUX
AUD4_RXFS
ALT5
GPIO3
GPIO[21]
ALT6
CSPI3
MISO
ALT7
ARM926P_PLATF TRCLK
ORM
ALT0
EMI
NANDF_CE0
ALT1
CSPI1
SS3
ALT5
GPIO3
GPIO[22]
ALT7
ARM926P_PLATF TRACE[3]
ORM
ALT0
EMI
EIM_ECB
ALT3
UART5
TXD_MUX
ALT5
GPIO3
GPIO[23]
ALT6
CSPI3
SCLK
ALT0
EMI
EIM_LBA
ALT3
UART5
RXD_MUX
ALT5
GPIO3
GPIO[24]
ALT6
CSPI3
RDY
ALT0
EMI
EIM_BCLK
ALT5
GPIO4
GPIO[4]
ALT0
EMI
EIM_RW
ALT4
AUDMUX
AUD4_TXFS
ALT5
GPIO3
GPIO[25]
Pad Settings
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ
PD)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (1.8 V)
Pull/Keep Select—Pull
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—CFG (FAST)
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (1.8 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—Disabled
DDR Type—CFG (mDDR)
Drive Strength—CFG (High)
Keeper—CFG (Disabled)
DDR Type—CFG (mDDR)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-44
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
NFWE_B
NFRE_B
NFALE
NFCLE
NFWP_B
NFRB
D15
Mode
Instance
Port
ALT0
EMI
NANDF_WE_B
ALT5
GPIO3
GPIO[26]
ALT7
ARM926P_PLATF PIPESTAT[2]
ORM
ALT0
EMI
NANDF_RE_B
ALT5
GPIO3
GPIO[27]
ALT7
ARM926P_PLATF PIPESTAT[1]
ORM
ALT0
EMI
NANDF_ALE
ALT5
GPIO3
GPIO[28]
ALT7
ARM926P_PLATF PIPESTAT[0]
ORM
ALT0
EMI
NANDF_CLE
ALT5
GPIO3
GPIO[29]
ALT7
ARM926P_PLATF TRACE[0]
ORM
ALT0
EMI
NANDF_WP_B
ALT5
GPIO3
GPIO[30]
ALT7
ARM926P_PLATF TRACE[1]
ORM
ALT0
EMI
NANDF_RB
ALT5
GPIO3
GPIO[31]
ALT7
ARM926P_PLATF TRACE[2]
ORM
ALT0
EMI
EIM_D[15]
ALT1
LCDC
LCDC_LD[16]
ALT5
GPIO4
GPIO[5]
ALT6
ESDHC1
DAT7
Pad Settings
Hysteresis Enable—Disabled
Drive Strength—CFG (High)
Pull/Keep Enable—Disabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—FAST
Hysteresis Enable—Disabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—FAST
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-45
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
D14
D13
D12
D11
D10
D9
Mode
Instance
Port
ALT0
EMI
EIM_D[14]
ALT1
LCDC
LCDC_LD[17]
ALT5
GPIO4
GPIO[6]
ALT6
ESDHC1
DAT6
ALT0
EMI
EIM_D[13]
ALT1
LCDC
LCDC_LD[18]
ALT5
GPIO4
GPIO[7]
ALT6
ESDHC1
DAT5
ALT0
EMI
EIM_D[12]
ALT1
LCDC
LCDC_LD[19]
ALT5
GPIO4
GPIO[8]
ALT6
ESDHC1
DAT4
ALT0
EMI
EIM_D[11]
ALT1
LCDC
LCDC_LD[20]
ALT5
GPIO4
GPIO[9]
ALT6
USB_TOP
USBOTG_PWR
ALT0
EMI
EIM_D[10]
ALT1
LCDC
LCDC_LD[21]
ALT5
GPIO4
GPIO[10]
ALT6
USB_TOP
USBOTG_OC
ALT0
EMI
EIM_D[9]
ALT1
LCDC
LCDC_LD[22]
ALT5
GPIO4
GPIO[11]
ALT6
USB_TOP
USBH2_PWR
Pad Settings
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
Hysteresis Enable—Disabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
Hysteresis Enable—Disabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-46
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
LD0
Mode
Instance
Port
ALT0
EMI
EIM_D[8]
ALT1
LCDC
LCDC_LD[23]
ALT5
GPIO4
GPIO[12]
ALT6
USB_TOP
USBH2_OC
ALT0
EMI
EIM_D[7]
ALT5
GPIO4
GPIO[13]
ALT0
EMI
EIM_D[6]
ALT5
GPIO4
GPIO[14]
ALT0
EMI
EIM_D[5]
ALT5
GPIO4
GPIO[15]
ALT0
EMI
EIM_D[4]
ALT5
GPIO4
GPIO[16]
ALT0
EMI
EIM_D[3]
ALT5
GPIO4
GPIO[17]
ALT0
EMI
EIM_D[2]
ALT5
GPIO4
GPIO[18]
ALT0
EMI
EIM_D[1]
ALT5
GPIO4
GPIO[19]
ALT0
EMI
EIM_D[0]
ALT5
GPIO4
GPIO[20]
ALT0
LCDC
LCDC_LD[0]
ALT1
SLCDC
SLCDC_DATA[0]
ALT2
CSI
CSI_D[0]
ALT3
ATA
DATA[0]
ALT4
SIM1
CLK1
ALT5
GPIO2
GPIO[15]
ALT6
USB_TOP
USBH2_CLK
ALT7
CCM
BT_MEM_CTRL[0]
Pad Settings
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
Hysteresis Enable—Disabled
Drive Strength—CFG (High)
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—FAST
Hysteresis Enable—Disabled
Drive Strength—CFG (High)
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—FAST
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-47
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
LD1
LD2
LD3
LD4
Mode
Instance
Port
ALT0
LCDC
LCDC_LD[1]
ALT1
SLCDC
SLCDC_DATA[1]
ALT2
CSI
CSI_D[1]
ALT3
ATA
DATA[1]
ALT4
SIM1
RST1
ALT5
GPIO2
GPIO[16]
ALT6
USB_TOP
USBH2_DIR
ALT7
CCM
BT_MEM_CTRL[1]
ALT0
LCDC
LCDC_LD[2]
ALT1
SLCDC
SLCDC_DATA[2]
ALT2
CSI
CSI_D[15]
ALT3
ATA
DATA[2]
ALT4
SIM1
VEN1
ALT5
GPIO2
GPIO[17]
ALT6
USB_TOP
USBH2_STP
ALT7
CCM
BT_MEM_TYPE[0]
ALT0
LCDC
LCDC_LD[3]
ALT1
SLCDC
SLCDC_DATA[3]
ALT2
CSI
CSI_D[14]
ALT3
ATA
DATA[3]
ALT4
SIM1
TX1
ALT5
GPIO2
GPIO[18]
ALT6
USB_TOP
USBH2_NXT
ALT7
CCM
BT_MEM_TYPE[1]
ALT0
LCDC
LCDC_LD[4]
ALT1
SLCDC
SLCDC_DATA[4]
ALT2
CSI
CSI_D[13]
ALT3
ATA
DATA[4]
ALT4
SIM1
PD1
ALT5
GPIO2
GPIO[19]
ALT6
USB_TOP
USBH2_DATA[0]
ALT7
CCM
BT_PAGE_SIZE[0]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ
PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-48
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
LD5
LD6
LD7
LD8
Mode
Instance
Port
ALT0
LCDC
LCDC_LD[5]
ALT1
SLCDC
SLCDC_DATA[5]
ALT2
CSI
CSI_D[12]
ALT3
ATA
DATA[5]
ALT4
SIM1
RX1
ALT5
GPIO1
GPIO[19]
ALT6
USB_TOP
USBH2_DATA[1]
ALT7
CCM
BT_PAGE_SIZE[1]
ALT0
LCDC
LCDC_LD[6]
ALT1
SLCDC
SLCDC_DATA[6]
ALT2
CSI
CSI_D[11]
ALT3
ATA
DATA[6]
ALT4
SIM2
CLK1
ALT5
GPIO1
GPIO[20]
ALT6
USB_TOP
USBH2_DATA[2]
ALT7
CCM
BT_BUS_WIDTH[0]
ALT0
LCDC
LCDC_LD[7]
ALT1
SLCDC
SLCDC_DATA[7]
ALT2
CSI
CSI_D[10]
ALT3
ATA
DATA[7]
ALT4
SIM2
RST1
ALT5
GPIO1
GPIO[21]
ALT6
USB_TOP
USBH2_DATA[3]
ALT7
CCM
BT_BUS_WIDTH[1]
ALT0
LCDC
LCDC_LD[8]
ALT1
SLCDC
SLCDC_DATA[8]
ALT2
UART4
RXD_MUX
ALT3
ATA
DATA[8]
ALT4
AUDMUX
AUD3_TXD
ALT5
FEC
TX_ERR
ALT6
ESDHC2
CMD
ALT7
CCM
BT_USB_SRC[0]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-49
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
LD9
LD10
LD11
LD12
Mode
Instance
Port
ALT0
LCDC
LCDC_LD[9]
ALT1
SLCDC
SLCDC_DATA[9]
ALT2
UART4
TXD_MUX
ALT3
ATA
DATA[9]
ALT4
AUDMUX
AUD3_RXD
ALT5
FEC
COL
ALT6
ESDHC2
CLK
ALT7
CCM
BT_USB_SRC[1]
ALT0
LCDC
LCDC_LD[10]
ALT1
SLCDC
SLCDC_DATA[10]
ALT2
UART4
RTS
ALT3
ATA
DATA[10]
ALT4
AUDMUX
AUD3_TXC
ALT5
FEC
RX_ERR
ALT6
ESDHC2
DAT0
ALT7
CCM
BT_MLC_SEL
ALT0
LCDC
LCDC_LD[11]
ALT1
SLCDC
SLCDC_DATA[11]
ALT2
UART4
CTS
ALT3
ATA
DATA[11]
ALT4
AUDMUX
AUD3_TXFS
ALT5
FEC
RDATA[2]
ALT6
ESDHC2
DAT1
ALT7
CCM
BT_SPARE_SIZE
ALT0
LCDC
LCDC_LD[12]
ALT1
SLCDC
SLCDC_DATA[12]
ALT2
CSPI2
MOSI
ALT3
ATA
DATA[12]
ALT4
KPP
ROW[6]
ALT5
FEC
RDATA[3]
ALT6
ESDHC2
DAT2
ALT7
CCM
BT_SRC[0]
Pad Settings
Hysteresis Enable—CFG (Enabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-50
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
LD13
LD14
LD15
HSYNC
Mode
Instance
Port
ALT0
LCDC
LCDC_LD[13]
ALT1
SLCDC
SLCDC_DATA[13]
ALT2
CSPI2
MISO
ALT3
ATA
DATA[13]
ALT4
KPP
ROW[7]
ALT5
FEC
TDATA[2]
ALT6
ESDHC2
DAT3
ALT7
CCM
BT_SRC[1]
ALT0
LCDC
LCDC_LD[14]
ALT1
SLCDC
SLCDC_DATA[14]
ALT2
CSPI2
SCLK
ALT3
ATA
DATA[14]
ALT4
KPP
COL[6]
ALT5
FEC
TDATA[3]
ALT6
AUDMUX
AUD3_RXC
ALT7
CCM
BT_EEPROM_CFG
ALT0
LCDC
LCDC_LD[15]
ALT1
SLCDC
SLCDC_DATA[15]
ALT2
CSPI2
RDY
ALT3
ATA
DATA[15]
ALT4
KPP
COL[7]
ALT5
FEC
RX_CLK
ALT6
AUDMUX
AUD3_RXFS
ALT7
CCM
BT_UART_SRC[0]
ALT0
LCDC
LCDC_HSYN
ALT2
I2C3
SCL
ALT3
ATA
BUFFER_EN
ALT4
SIM2
VEN1
ALT5
GPIO1
GPIO[22]
ALT6
USB_TOP
USBH2_DATA[4]
ALT7
CCM
BT_UART_SRC[1]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-51
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
VSYNC
LSCLK
OE_ACD
CONTRAST
Mode
Instance
Port
ALT0
LCDC
LCDC_VSYN
ALT2
I2C3
SDA
ALT3
ATA
DMARQ
ALT4
SIM2
TX1
ALT5
GPIO1
GPIO[23]
ALT6
USB_TOP
USBH2_DATA[5]
ALT7
CCM
BT_UART_SRC[2]
ALT0
LCDC
LCDC_LSCLK
ALT1
SLCDC
SLCDC_CS
ALT3
ATA
DA_0
ALT4
SIM2
PD1
ALT5
GPIO1
GPIO[24]
ALT6
USB_TOP
USBH2_DATA[6]
ALT7
CCM
BT_LPB_FREQ[0]
ALT0
LCDC
LCDC_OE_ACD
ALT1
SLCDC
SLCDC_RS
ALT2
CSPI2
SS0
ALT3
ATA
DA_1
ALT4
SIM2
RX1
ALT5
GPIO1
GPIO[25]
ALT6
USB_TOP
USBH2_DATA[7]
ALT7
CCM
BT_LPB_FREQ[1]
ALT0
LCDC
LCDC_CONTRAST
ALT1
GPT4
CAPIN1
ALT2
CSPI2
SS1
ALT3
ATA
DA_2
ALT4
PWM4
PWMO
ALT5
FEC
CRS
ALT6
USB_TOP
USBH2_PWR
ALT7
WDOG
WDOG_B
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-52
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
PWM
CSI_D2
CSI_D3
CSI_D4
Mode
Instance
Port
ALT0
PWM1
PWMO
ALT1
GPT4
CMPOUT1
ALT5
GPIO1
GPIO[26]
ALT6
USB_TOP
USBH2_OC
ALT7
CCM
BT_LPB_FREQ[2]
ALT0
CSI
CSI_D[2]
ALT1
UART5
RXD_MUX
ALT2
ESDHC2
DAT4
ALT3
ESAI
SCKR
ALT4
SIM1
CLK0
ALT5
GPIO1
GPIO[27]
ALT6
USB_TOP
USBOTG_DATA[0]
ALT7
CSPI3
MOSI
ALT0
CSI
CSI_D[3]
ALT1
UART5
TXD_MUX
ALT2
ESDHC2
DAT5
ALT3
ESAI
FSR
ALT4
SIM1
RST0
ALT5
GPIO1
GPIO[28]
ALT6
USB_TOP
USBOTG_DATA[1]
ALT7
CSPI3
MISO
ALT0
CSI
CSI_D[4]
ALT1
UART5
RTS
ALT2
ESDHC2
DAT6
ALT3
ESAI
HCKR
ALT4
SIM1
VEN0
ALT5
GPIO1
GPIO[29]
ALT6
USB_TOP
USBOTG_DATA[2]
ALT7
CSPI3
SCLK
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—CFG (Enabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (FAST)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-53
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
CSI_D5
CSI_D6
CSI_D7
CSI_D8
Mode
Instance
Port
ALT0
CSI
CSI_D[5]
ALT1
UART5
CTS
ALT2
ESDHC2
DAT7
ALT3
ESAI
SCKT
ALT4
SIM1
TX0
ALT5
GPIO1
GPIO[30]
ALT6
USB_TOP
USBOTG_DATA[3]
ALT7
CSPI3
RDY
ALT0
CSI
CSI_D[6]
ALT1
KPP
ROW[6]
ALT2
ESDHC2
CMD
ALT3
ESAI
FST
ALT4
SIM1
PD0
ALT5
GPIO1
GPIO[31]
ALT6
USB_TOP
USBOTG_DATA[4]
ALT7
CSPI3
SS0
ALT0
CSI
CSI_D[7]
ALT1
KPP
ROW[7]
ALT2
ESDHC2
CLK
ALT3
ESAI
HCKT
ALT4
SIM1
RX0
ALT5
GPIO1
GPIO[6]
ALT6
USB_TOP
USBOTG_DATA[5]
ALT7
CSPI3
SS1
ALT0
CSI
CSI_D[8]
ALT1
KPP
COL[6]
ALT2
AUDMUX
AUD6_RXC
ALT3
ESAI
TX5_RX0
ALT4
SIM2
CLK0
ALT5
GPIO1
GPIO[7]
ALT6
USB_TOP
USBOTG_DATA[6]
ALT7
CSPI3
SS2
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—CFG (Enabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-54
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
CSI_D9
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
Mode
Instance
Port
ALT0
CSI
CSI_D[9]
ALT1
KPP
COL[7]
ALT2
AUDMUX
AUD6_RXFS
ALT3
ESAI
TX4_RX1
ALT4
SIM2
RST0
ALT5
GPIO4
GPIO[21]
ALT6
USB_TOP
USBOTG_DATA[7]
ALT7
CSPI3
SS3
ALT0
CSI
CSI_MCLK
ALT1
AUDMUX
AUD6_TXD
ALT2
ESDHC2
DAT0
ALT3
ESAI
TX3_RX2
ALT4
SIM2
VEN0
ALT5
GPIO1
GPIO[8]
ALT6
USB_TOP
USBOTG_DIR
ALT7
CCM
BT_RES[0]
ALT0
CSI
CSI_VSYNC
ALT1
AUDMUX
AUD6_RXD
ALT2
ESDHC2
DAT1
ALT3
ESAI
TX2_RX3
ALT4
SIM2
TX0
ALT5
GPIO1
GPIO[9]
ALT6
USB_TOP
USBOTG_STP
ALT7
CCM
BT_RES[1]
ALT0
CSI
CSI_HSYNC
ALT1
AUDMUX
AUD6_TXC
ALT2
ESDHC2
DAT2
ALT3
ESAI
TX1
ALT4
SIM2
PD0
ALT5
GPIO1
GPIO[10]
ALT6
USB_TOP
USBOTG_NXT
ALT7
CCM
BT_RES[2]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-55
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
CSI_PIXCLK
I2C1_CLK
I2C1_DAT
CSPI1_MOSI
CSPI1_MISO
Mode
Instance
Port
ALT0
CSI
CSI_PIXCLK
ALT1
AUDMUX
AUD6_TXFS
ALT2
ESDHC2
DAT3
ALT3
ESAI
TX0
ALT4
SIM2
RX0
ALT5
GPIO1
GPIO[11]
ALT6
USB_TOP
USBOTG_CLK
ALT7
CCM
BT_RES[3]
ALT0
I2C1
SCL
ALT5
GPIO1
GPIO[12]
ALT6
SLCDC
SLCDC_DATA[6]
ALT0
I2C1
SDA
ALT5
GPIO1
GPIO[13]
ALT6
SLCDC
SLCDC_DATA[7]
ALT0
CSPI1
MOSI
ALT2
UART3
RXD_MUX
ALT4
SDMA
SDMA_DBG_EVT_0
ALT5
GPIO1
GPIO[14]
ALT6
SLCDC
SLCDC_DATA[12]
ALT7
ARM926P_PLATF TRACE[4]
ORM
ALT0
CSPI1
MISO
ALT2
UART3
TXD_MUX
ALT4
SDMA
SDMA_DBG_EVT_1
ALT5
GPIO1
GPIO[15]
ALT6
SLCDC
SLCDC_DATA[13]
ALT7
ARM926P_PLATF TRACE[5]
ORM
Pad Settings
Hysteresis Enable—CFG (Enabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Keep)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Enabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Enabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-56
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
CSPI1_SS0
CSPI1_SS1
CSPI1_SCLK
CSPI1_RDY
UART1_RXD
Mode
Instance
Port
ALT0
CSPI1
SS0
ALT1
LCDC
LCDC_LD[16]
ALT2
PWM2
PWMO
ALT4
SDMA
SDMA_DBG_EVT_2
ALT5
GPIO1
GPIO[16]
ALT6
SLCDC
SLCDC_CS
ALT7
ARM926P_PLATF TRACE[6]
ORM
ALT0
CSPI1
SS1
ALT1
I2C3
SDA
ALT2
UART3
RTS
ALT4
SDMA
SDMA_DBG_EVT_3
ALT5
GPIO1
GPIO[17]
ALT6
SLCDC
SLCDC_RS
ALT7
ARM926P_PLATF TRACE[7]
ORM
ALT0
CSPI1
SCLK
ALT2
UART3
CTS
ALT4
SDMA
SDMA_DBG_EVT_4
ALT5
GPIO1
GPIO[18]
ALT6
SLCDC
SLCDC_DATA[14]
ALT7
ARM926P_PLATF TRACE[8]
ORM
ALT0
CSPI1
RDY
ALT4
SDMA
SDMA_DBG_EVT_5
ALT5
GPIO2
GPIO[22]
ALT6
SLCDC
SLCDC_DATA[15]
ALT7
ARM926P_PLATF TRACE[9]
ORM
ALT0
UART1
RXD_MUX
ALT3
UART2
DTR
ALT4
LCDC
LCDC_CLS
ALT5
GPIO4
GPIO[22]
ALT6
SLCDC
SLCDC_DATA[8]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-57
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
UART1_TXD
UART1_RTS
UART1_CTS
UART2_RXD
UART2_TXD
Mode
Instance
Port
ALT0
UART1
TXD_MUX
ALT3
UART2
DSR
ALT4
LCDC
LCDC_SPL
ALT5
GPIO4
GPIO[23]
ALT6
SLCDC
SLCDC_DATA[9]
ALT0
UART1
RTS
ALT1
CSI
CSI_D[0]
ALT2
GPT3
CAPIN1
ALT3
UART2
DCD
ALT4
LCDC
LCDC_PS
ALT5
GPIO4
GPIO[24]
ALT6
SLCDC
SLCDC_DATA[10]
ALT0
UART1
CTS
ALT1
CSI
CSI_D[1]
ALT2
GPT3
CMPOUT1
ALT3
UART2
RI
ALT4
LCDC
LCDC_REV
ALT5
GPIO4
GPIO[25]
ALT6
SLCDC
SLCDC_DATA[11]
ALT0
UART2
RXD_MUX
ALT1
ESDHC1
DAT7
ALT5
GPIO4
GPIO[26]
ALT0
UART2
TXD_MUX
ALT1
ESDHC1
DAT6
ALT2
FEC
TX_ERR
ALT5
GPIO4
GPIO[27]
ALT7
SDMA
EXTDMA_0
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—FAST
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-58
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
UART2_RTS
UART2_CTS
SD1_CMD
SD1_CLK
Mode
Instance
Port
ALT0
UART2
RTS
ALT1
ESDHC1
DAT5
ALT2
FEC
COL
ALT3
GPT1
CAPIN1
ALT4
EPIT2
DO_EPITO
ALT5
GPIO4
GPIO[28]
ALT6
CSPI2
SS3
ALT7
SDMA
EXTDMA_1
ALT0
UART2
CTS
ALT1
ESDHC1
DAT4
ALT2
FEC
RX_ERR
ALT3
GPT1
CMPOUT1
ALT5
GPIO4
GPIO[29]
ALT6
CSPI3
SS3
ALT7
SDMA
EXTDMA_2
ALT0
ESDHC1
CMD
ALT1
CSPI2
MOSI
ALT2
FEC
RDATA[2]
ALT4
SDMA
SDMA_DBG_EVT_S
EL
ALT5
GPIO2
GPIO[23]
ALT6
SLCDC
SLCDC_DATA[0]
ALT7
ARM926P_PLATF TRACE[10]
ORM
ALT0
ESDHC1
ALT1
CSPI2
ALT2
FEC
ALT4
SDMA
ALT5
GPIO2
ALT6
SLCDC
ALT7
ARM926P_PLATF TRACE[11]
ORM
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (47 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (FAST)
CLK
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (High)
MISO
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (47 KΩ PU)
RDATA[3]
Open Drain Enable—Disabled
SDMA_DBG_STAT_0 Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
GPIO[24]
Slew Rate—CFG (FAST)
SLCDC_DATA[1]
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-59
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
SD1_DATA0
SD1_DATA1
SD1_DATA2
Mode
Instance
Port
Pad Settings
ALT0
ESDHC1
DAT0
ALT1
CSPI2
ALT2
FEC
ALT3
AUDMUX
ALT4
SDMA
ALT5
GPIO2
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
SCLK
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (47 KΩ PU)
TDATA[2]
Open Drain Enable—Disabled
AUD7_TXFS
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
SDMA_DBG_STAT_1
Slew Rate—CFG (FAST)
GPIO[25]
ALT6
SLCDC
SLCDC_DATA[2]
ALT7
ARM926P_PLATF TRACE[12]
ORM
ALT0
ESDHC1
ALT1
CSPI2
ALT2
FEC
ALT3
AUDMUX
ALT4
SDMA
ALT5
GPIO2
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
RDY
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (47 KΩ PU)
TDATA[3]
Open Drain Enable—Disabled
AUD7_RXD
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
SDMA_DBG_STAT_2
Slew Rate—CFG (FAST)
GPIO[26]
ALT6
SLCDC
SLCDC_DATA[3]
ALT7
ARM926P_PLATF TRACE[13]
ORM
ALT0
ESDHC1
ALT1
CSPI2
ALT2
FEC
ALT3
AUDMUX
ALT4
SDMA
ALT5
GPIO2
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
SS0
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (47 KΩ PU)
RX_CLK
Open Drain Enable—Disabled
AUD7_RXC
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
SDMA_DBG_STAT_3
Slew Rate—CFG (FAST)
GPIO[27]
ALT6
SLCDC
SLCDC_DATA[4]
ALT7
ARM926P_PLATF TRACE[14]
ORM
DAT1
DAT2
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-60
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
SD1_DATA3
KPP_ROW0
KPP_ROW1
KPP_ROW2
KPP_ROW3
Mode
Instance
Port
ALT0
ESDHC1
DAT3
ALT1
CSPI2
SS1
ALT2
FEC
CRS
ALT3
AUDMUX
AUD7_RXFS
ALT5
GPIO2
GPIO[28]
ALT6
SLCDC
SLCDC_DATA[5]
ALT7
ARM926P_PLATF TRACE[15]
ORM
ALT0
KPP
ROW[0]
ALT1
UART3
RXD_MUX
ALT4
UART1
DTR
ALT5
GPIO2
GPIO[29]
ALT6
SDMA
SDMA_DBG_PC_0
ALT0
KPP
ROW[1]
ALT1
UART3
TXD_MUX
ALT4
UART1
DSR
ALT5
GPIO2
GPIO[30]
ALT6
SDMA
SDMA_DBG_PC_1
ALT0
KPP
ROW[2]
ALT1
UART3
RTS
ALT2
AUDMUX
AUD5_RXC
ALT3
CSI
CSI_D[0]
ALT4
UART1
DCD
ALT5
GPIO2
GPIO[31]
ALT6
SDMA
SDMA_DBG_PC_2
ALT0
KPP
ROW[3]
ALT1
UART3
CTS
ALT2
AUDMUX
AUD5_RXFS
ALT3
CSI
CSI_D[1]
ALT4
UART1
RI
ALT5
GPIO3
GPIO[0]
ALT6
SDMA
SDMA_DBG_PC_3
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (47 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-61
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
KPP_COL0
KPP_COL1
KPP_COL2
KPP_COL3
FEC_MDC
Mode
Instance
Port
ALT0
KPP
COL[0]
ALT1
UART4
RXD_MUX
ALT2
AUDMUX
AUD5_TXD
ALT5
GPIO3
GPIO[1]
ALT6
SDMA
SDMA_DBG_PC_4
ALT0
KPP
COL[1]
ALT1
UART4
TXD_MUX
ALT2
AUDMUX
AUD5_RXD
ALT5
GPIO3
GPIO[2]
ALT6
SDMA
SDMA_DBG_PC_5
ALT0
KPP
COL[2]
ALT1
UART4
RTS
ALT2
AUDMUX
AUD5_TXC
ALT5
GPIO3
GPIO[3]
ALT6
SDMA
SDMA_DBG_PC_6
ALT7
EMI
M3IF_CHOSEN_MA
STER_1
ALT0
KPP
COL[3]
ALT1
UART4
CTS
ALT2
AUDMUX
AUD5_TXFS
ALT5
GPIO3
GPIO[4]
ALT6
SDMA
SDMA_DBG_PC_7
ALT7
EMI
M3IF_CHOSEN_MA
STER_2
ALT0
FEC
MDC
ALT1
ESDHC2
CMD
ALT2
AUDMUX
AUD4_TXD
ALT3
ATA
DIOR
ALT5
GPIO3
GPIO[5]
ALT6
SDMA
SDMA_DBG_PC_8
ALT7
LCDC
LCDC_LD[16]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Enabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Enabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
4-62
Freescale Semiconductor
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
FEC_MDIO
FEC_TDATA0
FEC_TDATA1
FEC_TX_EN
Mode
Instance
Port
ALT0
FEC
MDIO
ALT1
ESDHC2
CLK
ALT2
AUDMUX
AUD4_RXD
ALT3
ATA
DIOW
ALT5
GPIO3
GPIO[6]
ALT6
SDMA
SDMA_DBG_PC_9
ALT7
LCDC
LCDC_LD[17]
ALT0
FEC
TDATA[0]
ALT1
ESDHC2
DAT0
ALT2
AUDMUX
AUD4_TXC
ALT3
ATA
DMACK
ALT5
GPIO3
GPIO[7]
ALT6
SDMA
SDMA_DBG_PC_10
ALT7
LCDC
LCDC_LD[18]
ALT0
FEC
TDATA[1]
ALT1
ESDHC2
DAT1
ALT2
AUDMUX
AUD4_TXFS
ALT3
ATA
RESET_B
ALT5
GPIO3
GPIO[8]
ALT6
SDMA
SDMA_DBG_PC_11
ALT7
LCDC
LCDC_LD[19]
ALT0
FEC
TX_EN
ALT1
ESDHC2
DAT2
ALT2
AUDMUX
AUD4_RXC
ALT3
ATA
IORDY
ALT4
CAN1
TXCAN
ALT5
GPIO3
GPIO[9]
ALT6
KPP
ROW[4]
ALT7
LCDC
LCDC_LD[20]
Pad Settings
Hysteresis Enable—CFG (Enabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (22 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
4-63
External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
FEC_RDATA0
FEC_RDATA1
FEC_RX_DV
FEC_TX_CLK
Mode
Instance
Port
ALT0
FEC
RDATA[0]
ALT1
ESDHC2
DAT3
ALT2
AUDMUX
AUD4_RXFS
ALT3
ATA
INTRQ
ALT4
CAN1
RXCAN
ALT5
GPIO3
GPIO[10]
ALT6
KPP
ROW[5]
ALT7
LCDC
LCDC_LD[21]
ALT0
FEC
RDATA[1]
ALT1
I2C2
SCL
ALT2
ESDHC2
DAT4
ALT3
ATA
CS0
ALT4
CAN2
TXCAN
ALT5
GPIO3
GPIO[11]
ALT6
KPP
COL[4]
ALT7
LCDC
LCDC_LD[22]
ALT0
FEC
RX_DV
ALT1
I2C2
SDA
ALT2
ESDHC2
DAT5
ALT3
ATA
CS1
ALT4
CAN2
RXCAN
ALT5
GPIO3
GPIO[12]
ALT6
KPP
COL[5]
ALT7
LCDC
LCDC_LD[23]
ALT0
FEC
TX_CLK
ALT1
PWM3
PWMO
ALT2
ESDHC2
DAT6
ALT3
LCDC
LCDC_LD[16]
ALT5
GPIO3
GPIO[13]
ALT6
SDMA
SDMA_DBG_PC_12
ALT7
EMI
M3IF_CHOSEN_MA
STER_0
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (FAST)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
Hysteresis Enable—CFG (Disabled)
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
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External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
RTCK
Mode
Instance
Port
Pad Settings
ALT0
ARM926P_PLATF RTCK
ORM
ALT1
OWIRE
LINE
ALT2
ESDHC2
DAT7
ALT5
GPIO3
GPIO[14]
ALT6
SDMA
SDMA_DBG_PC_13
TCK
No Muxing
(ALT0)
SJC
TCK
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PD
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
TMS
No Muxing
(ALT0)
SJC
TMS
SJC
TDI
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—47 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
SJC
TDO
Hysteresis Enable—Disabled
Drive Strength—CFG (High)
Pull/Keep Enable—Disabled
Pull Up/Down Configuration—47 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
No Muxing
(ALT0)
SJC
TRSTB
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—47 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
ALT0
SJC
DE_B
ALT5
GPIO2
GPIO[20]
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—47 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
TDI
TDO
TRSTB
DE_B
Hysteresis Enable—Enabled
Drive Strength—CFG (High)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—CFG (SLOW)
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External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
SJC_MOD
Mode
Port
Pad Settings
SJC
MOD
USBPHY1_VBUS
USBPHY_UTMI
USBPHY1_VBUS
—
USBPHY1_DP
USBPHY_UTMI
USBPHY1_DP
—
USBPHY1_DM
USBPHY_UTMI
USBPHY1_DM
—
USBPHY1_UID
USBPHY_UTMI
USBPHY1_UID
—
USBPHY1_RREF
USBPHY_UTMI
USBPHY1_RREF
—
USBPHY2_DM
USBXCVR
USBPHY2_DM
—
USBPHY2_DP
USBXCVR
USBPHY2_DP
—
ALT0
GPIO1
GPIO[0]
ALT1
PWM2
PWMO
ALT2
USB_TOP
USBOTG_PWR
ALT3
KPP
ROW[4]
ALT4
I2C3
SCL
ALT6
CAN1
TXCAN
ALT7
OBSRV_MODUL
E
INT_MUX_OUT
ALT0
GPIO1
GPIO[1]
ALT1
PWM3
PWMO
ALT2
USB_TOP
USBOTG_OC
ALT3
KPP
ROW[5]
ALT4
I2C3
SDA
ALT6
CAN1
RXCAN
GPIO_A
GPIO_B
No Muxing
(ALT0)
Instance
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
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External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
GPIO_C
GPIO_D
GPIO_E
GPIO_F
EXT_ARMCLK
UPLL_BYPCLK
Mode
Instance
Port
ALT0
GPIO1
GPIO[2]
ALT1
PWM4
PWMO
ALT2
I2C2
SCL
ALT3
KPP
COL[4]
ALT4
GPT2
CAPIN1
ALT5
CSPI1
SS2
ALT6
CAN2
TXCAN
ALT7
CSPI2
SS2
ALT0
GPIO1
GPIO[3]
ALT1
WDOG
WDOG_B
ALT2
I2C2
SDA
ALT3
KPP
COL[5]
ALT4
GPT2
CMPOUT1
ALT6
CAN2
RXCAN
ALT7
CSPI3
SS2
ALT0
GPIO1
GPIO[4]
ALT1
I2C3
SCL
ALT2
LCDC
LCDC_LD[16]
ALT4
AUDMUX
AUD7_TXD
ALT6
UART4
RXD_MUX
ALT7
ECT
CTI_TRIG_IN0_6
ALT0
GPIO1
GPIO[5]
ALT2
LCDC
LCDC_LD[17]
ALT3
EPIT1
DO_EPITO
ALT4
AUDMUX
AUD7_TXC
ALT6
UART4
TXD_MUX
ALT7
ECT
CTI_TRIG_OUT0_6
ALT0
CCM
EXT_ARMCLK
ALT5
GPIO3
GPIO[15]
ALT0
CCM
UPLL_BYPCLK
ALT5
GPIO3
GPIO[16]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—CFG (Pull)
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Disabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—CFG (Enabled)
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—CFG (100 KΩ PU)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Disabled
Drive Strength—Nominal
Pull/Keep Enable—Disabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Keep
Slew Rate—FAST
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External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
VSTBY_REQ
VSTBY_ACK
POWER_FAIL
RESET_B
POR_B
CLKO
BOOT_MODE0
BOOT_MODE1
Mode
Instance
Port
ALT0
CCM
VSTBY_REQ
ALT4
AUDMUX
AUD7_TXFS
ALT5
GPIO3
GPIO[17]
ALT6
UART4
RTS
ALT0
CCM
HRESET_B
ALT1
CCM
VSTBY_ACK
ALT2
CSPI1
SS3
ALT3
EPIT1
DO_EPITO
ALT5
GPIO3
GPIO[18]
ALT0
CCM
POWER_FAIL_INT
ALT4
AUDMUX
AUD7_RXD
ALT5
GPIO3
GPIO[19]
ALT6
UART4
CTS
No Muxing
(ALT0)
CCM
RESET_B
CCM
POR_B
ALT0
CCM
CLKO
ALT5
GPIO2
GPIO[21]
ALT0
CCM
BOOT_MODE[0]
ALT5
GPIO4
GPIO[30]
ALT0
CCM
BOOT_MODE[1]
ALT5
GPIO4
GPIO[31]
Pad Settings
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Disabled)
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—CFG (Nominal)
Pull/Keep Enable—CFG (Enabled)
Pull Up/Down Configuration—CFG (100 KΩ PD)
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—SLOW
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
Hysteresis Enable—NA
Drive Strength—CFG (Max)
Pull/Keep Enable—Disabled
Pull Up/Down Configuration—100 KΩ PU
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—FAST
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PD
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
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External Signals and Pin Multiplexing
Table 4-18. i.MX25 Detailed Pin Muxing (continued)
Pin Name
CLK_SEL
Mode
Port
Pad Settings
CCM
CLK_SEL
TCU
TEST_MODE
OSC24M_EXTAL No Muxing
(ALT0)
OSC24M_XTAL
OSC24M
EXTAL24M
—
OSC24M
XTAL24M
—
OSC32K_EXTAL
DRYICE
EXT32K
—
OSC32K_XTAL
DRYICE
XTAL32K
—
TAMPER_A
DRYICE
TAMPER_A
—
TAMPER_B
DRYICE
TAMPER_B
—
DRYICE
MESH_C
—
DRYICE
MESH_D
—
DRYICE
OSC_BYP
—
XP
ADC
XP
—
XN
ADC
XN
—
YP
ADC
YP
—
YN
ADC
YN
—
WIPER
ADC
WIPER
—
INAUX0
ADC
INAUX0
—
INAUX1
ADC
INAUX1
—
INAUX2
ADC
INAUX2
—
REF
ADC
REF
—
TEST_MODE
MESH_C
MESH_D
No Muxing
(ALT0)
Instance
No Muxing
(ALT0)
OSC_BYP
Hysteresis Enable—Enabled
Drive Strength—Nominal
Pull/Keep Enable—Enabled
Pull Up/Down Configuration—100 KΩ PD
Open Drain Enable—Disabled
Drive Voltage Select—CFG (3.3 V)
Pull/Keep Select—Pull
Slew Rate—NA
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External Signals and Pin Multiplexing
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Chapter 5
Clock Distribution
This chapter covers clocking distribution for the i.MX25 device.
Figure 5-1 shows a simplified block diagram of the clock distribution on the i.MX25 device.
ARM SCLK
arm_src_sel
532MHz
OSC22M
MCU
DPLL
arm_clk_div
ahb_clk_div
2B
2B
DIV
DIV
ARMclock
AHBSCLK
CKGATE
DIVGEN
399MHz
266M
clk_sel
/2
IPGSCLK
16
54
16
133MHz
PCLK
6BDIV
EXT266M
AHB clock
IPGclock
PERclock
USB clock
240MHz
USB
DPLL
Figure 5-1. i.MX25 Clock Distribution
The clock control module (CCM) generates the clocks for all the modules on i.MX25. The CCM has the
following features:
• Low-power mode (LPM) entry/exit control
• Clock distribution
• IP Bus accessible registers
• Reset control to the cores and peripherals
• Boot mode control logic
5.1
External Clock Sources
The OSC24M oscillator provides a frequency reference using a 24 MHz crystal with its corresponding
integrated biasing resistor and loading capacitors. This oscillator is designed to supply the USBPHY which
has very strict jitter requirements. The i.MX25 also uses this clock source as the primary PLL for the ARM
platform.
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Freescale Semiconductor
5-1
Clock Distribution
The OSC32K oscillator provides a second frequency reference using a 32 kHz crystal with its
corresponding integrated biasing resistor and loading capacitors. This oscillator is designed to supply the
real time clock (RTC) in DryIce.
The i.MX25 uses two clocks as the reference clocks in the system:
• CKIL - Real time clock. This clock must be active at all times. The frequency must be 32.768KHz.
CKIL must be present during reset.
• CKIH - High frequency input clock with a frequency between 13 MHz and 40 MHz. CKIH
generally is the 24 MHz output from the OSC24M and must be present for the i.MX25 to come out
of reset.
5.2
PLLs
There are two PLLs in the i.MX25 device as described in Table 5-1.
Table 5-1. i.MX25 PLLs
PLL Name
Reference Source
Options
Default Output
Frequency (MHz)
Comments
Type
Default State
Core PLL
CKIH
400
ARM platform clocks FracN, Dithering
On
USB PLL
CKIH
300
USB clock
On
5.3
FracN, Dithering
Clock Gating
Two levels of clock gating are implemented in the i.MX25, as follows:
• Clock tree root, as implemented in the clock controller module (CCM)
• Clock tree leaf nodes, as implemented in the modules themselves
Clock tree roots are gated off by programming the CCM or by putting the domain into a low-power mode.
Clock tree branches are gated off as follows:
• Automatically, when the modules on a branch request its clock be disabled
• By programming the CCM, or putting the domain into a low-power mode
There is an override bit in the CCM modules for each clock branch, which forces the clock tree and branch
to remain on.
5.4
Core PLL Clock Generation
The core PLL (also denoted MPLL) creates the clocks for the ARM platform and the SDMA platform. The
high frequency bus (AHB) clock and the low frequency bus (IP) clock of the ARM platform are
synchronous to the AP core clock. The clock frequency limitations and clock ratio restrictions between the
core, AHB, and IP clocks frequencies are:
•
•
•
Maximum AP core clock frequency is 399 MHz
Maximum AHB bus frequency is 133 MHz
Maximum IP bus frequency is 66.5 MHz
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Freescale Semiconductor
Clock Distribution
•
•
•
Clock ratios must be integers between Core:AHB, Core:IP, AHB:IP
AHB:IP clock ratio is fixed at 2:1
Core:AHB and Core:IP clock ratio can be 3:1, 2:1, or 1:1
Some examples of allowable clock frequencies are shown in Table 5-2.
Table 5-2. Clock Frequency Examples
Example
Core (MHz)
AHB (MHz)
IP (MHz)
1
399
133
66.5
2
266
133
66.5
3
133
133
66.5
4
133
66
66.5
5
300
100
50
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Clock Distribution
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 6
Reset
This chapter describes the following:
• Reset types
• Reset sources
• Reset state machine
• Reset sequence
6.1
Reset Types
Table 6-1 summarizes the three reset types (Power-on reset (POR), cold and warm resets).
Table 6-1. Reset Types
Reset Type
Reset I/O Pin
Power-on reset
(POR)
POR_B
Cold reset
RESET_B
ARM core and all other peripheral modules.
Warm reset
N/A
ARM core and all other peripheral modules.
6.2
Impact Modules
ARM core, OSC24M, DPLLs, fusebox, CCM, test logic and all other peripheral
modules.
Reset Sources
Table 6-2 shows reset sources, qualification conditions, and resulting reset types. Qualified resets are
qualified on the unsynchronized CKIL clock.
Table 6-2. Reset Sources and Qualification Conditions
Reset Source
Qualification Conditions Resulting Reset Type
POR_B
Unqualified
External low condition on RESET_B
Qualified for 4 CKIL clocks. Cold reset
External low condition on internal reset from WDOG
Qualified for 1 CKIL clock. Warm reset
Reset signal from the external JTAG connector
Unqualified
Warm reset
Software-initiated JTAG reset
Unqualified
Warm reset
6.3
Power-on reset (POR)
Reset State Machine
The reset state machine requires the presence of the CKIL clock.The reset sequence uses the IIM fuse-read
completion flag and EMI completion flag handshake signals to gate the progress of the state machine, to
ensure that these sequences complete before progressing.
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Freescale Semiconductor
6-1
Reset
6.4
Reset Sequence
The reset module controls or distributes all of the system reset signals used by i.MX25. Figure 6-1 gives a
simplified block diagram of the reset sequence. The signals and timing parameters shown in Figure 6-1 are
described in Table 6-3 and Table 6-4, respectively.
IIM &
F use
D P LL
US B
OS C 2 4 M
Ot her
M o d ules
Secret
M o d ules
MCU
EM I
S CC
ARM
D P LL
Time
t0
t1
t2
t3
t4
t5
ipp_por_b
por_reset_b
emi_reset_b
scc_reset_b
hreset_b/per_reset_b
reset_in_b and wdog_reset_b
will be started here
Figure 6-1. Reset Module Clock Diagram
Table 6-3. Reset Module Signals
Signal Name
ipp_por_b
Description
Resets OSC24M, which is input from external source
por_reset_b
Resets DPLLs, fusebox and IIM
emi_reset_b
Resets EMI module
scc_reset_b
Resets SCC and security modules
hreset_b
Resets ARM platform
per_reset
Resets peripheral modules
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Freescale Semiconductor
Reset
Table 6-4. Reset Module Timing Parameters
Timing Parameter
Description
t0
Time for the power-up sequence of all the supplies. After t0, OSC24M starts to work.
t1
t1 depends on boot mode:
• If boot mode is PROD mode (0b01) then t1 is 8 32-kHz cycles
• If boot mode is not PROD mode, then t1 is 256 32-kHz cycles
After t1, IIM, fusebox, and the DPLLs start to work
t2
4 32-kHz cycles+ 1 HCLK cycle. After t2, EMI starts to work.
t3
• For NAND boot, t3 is 32 32-kHz cycles + 1 HCLK cycle
• Otherwise t3 is 4 cycles 32-kHz + 1 HCLK cycle
After t3, the security modules and SCC start to work.
t4
• 1 HCLK cycle for hreset_b
• 1 ipg_clk cycle for per_reset_b
After t4, all other modules start to work
t5
Out of reset
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6-3
Reset
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Overview
Chapter 7
System Boot
7.1
Overview
This chapter describes the system boot sequence of the i.MX25 application processor, and describes the
various boot options.
The i.MX25 out-of-reset boot sequence makes use of the High-Assurance Boot (HAB) library to provide
a secure boot environment. The HAB process utilizes a combination of hardware and software, including
a public key infrastructure (PKI) protocol to protect the system from executing unauthorized images or
programs. In order for the HAB to allow user code to run, the code must be signed by the private key holder
which matches with the public key on i.MX25. The HAB library in the i.MX25 boot ROM also provides
a number of API functions, which allow the user to authenticate any defined region and signature at
run-time.
The i.MX25 also supports a HAB-bypass mode or direct external boot, in which the processor boots
directly from external memory (as traditional microprocessors do).
The boot ROM also provides a mechanism to download and flash new code using a serial connection.
Typically, a downloader application is downloaded to RAM, which facilitates the flash programming. The
download is performed over either the USB or UART connection.
The boot capabilities differ between i.MX25 packages, depending on the HAB-type security
configuration. Full flexibility is supported in the development (or engineering) configuration, while
significant limitations are imposed on the production (or secure) configuration.
7.2
Boot Sources
The i.MX25 boot process utilizes the following memory/device sources:
• NOR Flash memory through WEIM interface, chip select 0 (CS0):
— 16-bit slow asynchronous mode
— Supports muxed address/data modes
— 24-bit address is available for boot
• OneNAND memory through WEIM interface
• SLC (Binary) and MLC NAND Flash memory, through the NFC interface:
— 512-byte, 2-Kbyte and 4-Kbyte page sizes
— 4/8 bit ECC.
• LBA NAND devices through NFC interface (configured as SLC)
• SD/MMC cards through both eSDHC interfaces:
— Support for high capacity SD, eSD (Embedded SD, versions 2.0 and 2.1 Draft Rev. 0.3) and
MMC/eMMC (version 4.3 (MoviNAND), JEDSD84-A43) cards.
• EEPROM/serial Flash devices boot through any SPI interface
• EEPROM boot through any I2C interface
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7-1
Boot Modes
•
‘Streamed in’ (serial downloader) boot through USB OTG/UART interfaces.
7.3
Boot Modes
Three boot modes are supported in the i.MX25. Table 7-1 describes these boot modes in a summary.
Table 7-1. Boot Mode Summary
BOOT_MODE[1:0]
1
Boot Type1
Descriptions
00
Internal Boot
When power-on reset, i.MX25 executes the boot ROM code to load the boot
image from different boot sources. See Section 7.3.3 for more details.
01
Reserved
Reserved
10
External (Direct) Boot Direct boot from WEIM interface, independent of boot ROM code. See
Section 7.3.4 for more details.
11
USB/UART Serial
Boot
Load and execute code using serial devices:
• USB OTG (Full-Speed, using integrated PHY or external PHY)
• UART
See Section 7.3.5 for more details.
Boot type is determined by the values of boot mode contacts BOOT_MODE[1:0] sampled during the out-of-reset sequence
and stored in the Clock Controller Module (CCM) Status Register (RCSR)
Other boot configuration settings are obtained from the programmable eFUSEs or by sampling the
contacts during the out-of-reset sequence. In the i.MX25, a fuse, GPIO_BT_SEL, is provided for
flexibility between these two configuration settings.
• If GPIO_BT_SEL is blown, all boot options are configured by eFUSEs as detailed in Table 7-2
below. Boot ROM software may read the values from the RCSR, or from the e-fuses, using the IIM
module. It is the recommended configuration for deployed products.
• If GPIO_BT_SEL is left unblown, the various boot options are determined by sampling dedicated
contacts at out-of-reset. Every e-fuse option is associated with a dedicated pin(s), such that same
functionality is available for both boot options. For this case, regardless of fuse values, Boot ROM
code must read the options' values from RCSR register of the CCM module. Table 7-3 lists boot
option contacts.
7.3.1
Boot Configuration
This section lists the various boot modes and boot configurations as defined by the eFUSE values or
contacts sampled at out-of-reset.
7.3.1.1
eFUSE Configuration
eFUSE is described in detail in Chapter 30, “IC Identification Module (IIM).” In this section, only the part
related to boot is specifically listed here.
Table 7-2 shows the eFUSE settings used by the boot ROM code in the boot process.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
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Freescale Semiconductor
Boot Modes
Table 7-2. Fuse Description
eFUSE
Settings:
Intact reads as 0
Blown reads as 1
Definition
BT_SRC[1:0]
BT_UART_SRC[2:0]
BT_MLC_SEL
Chooses the specific device for booting.
If BT_MEM_CTL[1:0]==11 (Expansion card
device) && BT_MEM_TYPE[1:0]=00
(SD/MMC/MoviNAND) then
00 eSDHC-1
01 eSDHC-2
10 Reserved
11 Reserved
If BT_MEM_CTL[1:0]==11 (Expansion card
device) && BT_MEM_TYPE[1:0]=10 (Serial
ROM using I2C) then
00 I2C1
01 I2C2
10 I2C3
11 Reserved
If BT_MEM_CTL[1:0]==11 (Expansion card
device) && BT_MEM_TYPE[1:0]=11 (Serial
ROM using SPI) then
00 CSPI1
01 CSPI2
10 CSPI3
11 Reserved
Otherwise Reserved
Choosing the specific UART controller for
booting.
000 UART1
001 UART2
010 UART3
011 UART4
100 UART5
Otherwise Reserved
SLC/MLC NAND device.
0 SLC NAND device
1 MLC NAND device
BT_SPARE_SIZE1
Specifies the size of spare bytes for 4-Kbyte 0 128 bytes spare (Samsung)
page size NAND Flash devices.
1 218 bytes spare (Micron, Toshiba)
BT_USB_SRC[1:0]
USB boot source selection
00 USB OTG Internal UTMI PHY
01 USB OTG External ULPI PHY
10 Reserved
11 Reserved
BT_RES1, BT_RES2,
BT_RES3, BT_RES4
Reserved for boot options
Has a corresponded GPIO contact,
including a place in SRC SBMR register
—
—
BT_PAGE_SIZE[1:0]
NAND Flash page size. This field is used in If BT_MEM_CTL = NAND Flash then
conjunction with the BT_MEM_CTL[1:0]
00 512 bytes
setting
01 2 Kbytes
10 4 Kbytes
11 Reserved
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Boot Modes
Table 7-2. Fuse Description (continued)
eFUSE
Definition
BT_EEPROM_CFG
Settings:
Intact reads as 0
Blown reads as 1
Selects whether EEPROM device is used 0 Use EEPROM DCD
for load of device configuration data (DCD), 1 Don’t use EEPROM DCD
prior to boot from other devices (not
applicable when using EEPROM as boot
device)
GPIO_BT_SEL
GPIO boot select. Determines, whether
0 Boot mode configuration is set by contacts.
certain boot fuse values are controlled from 1 Boot mode configuration is set by fuses.
GPIO contacts or fuses.
HAB_TYPE[2:0]
High assurance boot security type
001 Engineering—allows any code to be
flashed and executed, even if it has no
valid signature (default)
100 Security disabled
Others Production (Security On)
BT_MEM_TYPE[1:0]
Boot memory type.
Interpreted by boot ROM software
according to BT_MEM_CTL setting.
If BT_MEM_CTL = WEIM then
00 NOR
01 Reserved
10 OneNAND
11 Reserved
If BT_MEM_CTL = NAND Flash
00 3 address cycles
01 4 address cycles
10 5 address cycles
11 Reserved
If BT_MEM_CTL = Expansion Card Device
00 SD/MMC/MoviNAND
01 Reserved
10 Serial ROM using I2C
11 Serial ROM using SPI
BT_BUS_WIDTH[1:0]
Selects boot device bus mode.
BT_MEM_CTL[1:0] = NAND Flash
00 8-bit bus
01 16-bit bus
10 Reserved
11 Reserved
BT_MEM_CTL[1:0] = WEIM (NOR)
00 Reserved
01 16-bit address/data unmultiplexed interface
10 Reserved
11 Reserved
BT_MEM_CTL[1:0] = Expansion Device (SPI)
00 2-Address word SPI device (16-bit)
01 3-Address word SPI device (24-bit)
10 Reserved
11 Reserved
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Boot Modes
Table 7-2. Fuse Description (continued)
eFUSE
BT_MEM_CTL[1:0]
Boot memory control type (memory device) 00 WEIM
01 NAND Flash
10 Reserved
11 Expansion Device (SD/MMC/MoviNAND,
support high storage, EEPROMs. See
BT_MEM_TYPE[1:0] settings for details).
DIR_BT_DIS
Direct external memory boot disable
0 Direct boot from external memory is
allowed
1 Direct boot from external memory is not
allowed
SRK_HASH[255:0]
Super root key hash
Varies—used by high-assurance boot (HAB)
HAB_CUS[7:0]
HAB customer code
Varies—used by HAB
BT_LPB[1:0]
Options for low power boot mode (for more 00 Generic PMIC and one GPIO input (low
details see Section 7.6
battery detection)
01 Generic PMIC and two GPIO inputs (low
battery and charger detection)
10 Reserved
11 AP power management IC.
BT_LPB_FREQ[2:0]
DIE-X-CORDINATE[7:0]
DIE-Y-CORDINATE[7:0]
WAFER_NO[4:0]
LOT_NO_ENC2[42:0]
1
2
Settings:
Intact reads as 0
Blown reads as 1
Definition
LPB ARM core frequency
000
001
010
011
100
101
110
111
133 MHz (Default)
CKIH
55.33 MHz
66 MHz
83 MHz
166 MHz
266 MHz
normal boot frequency
Manufacturing Information.
Varies—used by HAB
Used as 64-bit Unique part ID and Secure
JTAG Challenge Value. Burnt by Freescale
during the tester stage. 43-bit
LOT_NO_ENC field encodes LOT ID STD
II, including FAB ID inside.
512-byte page devices have 16 bytes spare area size, 2-Kbyte page devices have 64 bytes spare area size.
Lot Number Encoded field is 43-bit value, contains encoded ‘STD II’ lot ID.
7.3.1.2
Boot Fuses and Associated Contacts
Table 7-3 lists fuses and associated contacts used for boot. The input contacts listed are latched during
POR; however, the value is stored once POR is released. It overrides fuse values when the GPIO_BT_SEL
fuse is unblown. Also listed are boot mode contacts, and the functionality of other boot-related fuses and
contacts.
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Boot Modes
Table 7-3. Fuses and Associated Contacts Used for Boot
Contact
Direction at Boot
eFUSE Name
BOOT_MODE[1]
Input
N/A
VSYNC
Input
BT_UART_SRC[2]
HSYNC
Input
BT_UART_SRC[1]
LD15
Input
BT_UART_SRC[0]
LD14
Input
BT_EEPROM_CFG
LD[13:12]
Input
BT_SRC[1:0]
LD11
Input
BT_SPARE_SIZE
LD10
Input
BT_MLC_SEL
LD[9:8]
Input
BT_USB_SRC[1:0]
LD[7:6]
Input
BT_BUS_WIDTH[1:0]
LD[5:4]
Input
BT_PAGE_SIZE[1:0]
LD[3:2]
Input
BT_MEM_TYPE[1:0]
LD[1:0]
Input
BT_MEM_CTL[1:0]
PWM
Input
BT_LPB_FREQ[2]
OE_ACD
Input
BT_LPB_FREQ[1]
LSCLK
Input
BT_LPB_FREQ[0]
CSI_PIXCLK
Input
BT_RES4
CSI_HSYNC
Input
BT_RES3
CSI_VSYNC
Input
BT_RES2
CSI_MCLK
Input
BT_RES1
VSTBY_ACK
Output
N/A
Details
Boot Mode selection (See Table 7-1)
BOOT_MODE[0]
Boot Options, Contact value overrides fuse
settings for GPIO_BT_SEL = 0
Toggle on this contacts indicates finish of
internal system reset. After reset, this contact
can be used for other purposes.
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Boot Modes
7.3.2
Boot Flow Diagram
Figure 7-1 shows the i.MX25 boot sequence flow. Color coding (see legend) indicates the controlling
sources (hardware only, boot contacts, or eFUSEs).
Reset
Senna MCU ROM Code High Level Bootflow
Boot pins and fuses
are sampled
Direct Boot and
Type=WEIM
And DIR_BT_DIS=0
Read boot e-fuses
(Memory Bus Width)
Yes
Jump to CS0
Base address
KEY
Boot Pins
E- Fuses
Direct Boot and
No
Type=NAND
And DIR_BT_DIS=0
Copy 4Kb of data onto
the nfc buffer
Yes
Jump to nfc
Base address
Hardware
Low Power Boot
LPB
Wait mode
SCC To failure
Yes
TEST Selection
GPIO1[4:6]
FSL TEST MODE
Security HW test
(SCC key Check)
Secure HW test
No
Enter DRYICE HW
test(Random Key
Check)
INIT Security HW
FSL Test Mode
(Test Executive)
SCC To failure
Yes
FSL Test Mode
Security HW error?
No(or HAB_TYPE = ENG)
Yes
USB/UART
Bootloader
No
BT_MEM_ CTL ==
WEIM and
BT_MEM_TYPE ==
NOR
WEIM MUX mode
selection
BT_WEIM_MUXED[1:
0]
Yes
Basic Config and
Obtain base addr
Of boot device
Yes
Code Barker
Valid?
HAB checks
No
No
BT_MEM_ CTL ==
WEIM and
BT_MEM_TYPE ==
OneNand
HAB check
image is verified
?
ConfigureWEIM (CS0) interface
and Copy initial 1kB of data to
ONENAND RAM
Yes
yes
No
No
BT_MEM_CTL ==
NAND
Execute
Image
Yes
Configure NFC controller and copy initial
4k of data to NFC Buffer
No
PROD
BT_MEM_CTL ==
Expansion Card
Device(SD/eSD/MMC /
eMMC/CE-ATA)
Yes
Download image
Issue Reset to
PMIC
Yes
Configure CSPI1-3/I2C1-3(EEPROM)
And download initial 2k data to iRAM
Initialize RAM
USB
Yes
Configure IOMUX and PHY
No
Configure I2C Read ADR/
DATA pairs To iRAM
Start WDOG
timer
Watchdog
Asserted
Initialize USB Driver
No
BT_EEPROM_CFG
Blown?
ENG
Configure eSDHC1-eSDHC2 controller
and read initial 2k of data to IRAM
No
Boot Mem ctrl
CSPI/I2C (EEPROM)
HAB_TYPE?
UART/USB Secure
Download?
(Wait for activity on one of
devices)
UART
Initialize UART1
Execute code
(Check address validity)
Figure 7-1. i.MX25 Boot Flow
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Boot Modes
7.3.3
Internal Boot Mode (BOOT_MODE[1:0]=00)
Internal boot is selected by driving the value ‘00’ on the BOOT_MODE[1:0] contacts, at device power-up.
In this mode, the i.MX25 boots from internal boot ROM. The boot ROM code performs hardware
initialization, application image validation using the high-assurance boot (HAB) library, and then jumps
to an address derived from the application image. If any error occurs during internal boot the boot code
jumps to the UART/USB secure download.
Internal boot mode is the only mode in which a secure boot of the i.MX25 is possible.
7.3.3.1
Security Settings
External boot modes are considered non-secure by definition: the software in Flash is executed regardless
of its authenticity, and the SCC is automatically put into Non-Secure state so that it cannot be used to
decrypt information with the device-unique secret key.
Internal boot modes can have one of two security levels:
• Production: This level is intended for use with shipped products. All HAB functions are executed
and security hardware is initialized (the SCC enters Secure state), device configuration data (DCD)
is processed if present, and software in Flash or downloaded to RAM is authenticated by HAB
prior to its execution. (See Section 7.3.3.10, “Device Configuration Data (DCD),” for more
information.) The first error detected is logged, then the boot flow is aborted with control passing
to the download mode. With this level, execution does not leave the internal ROM unless the target
executable image has been authenticated.
• Engineering: This level is intended for use during the development phases of a product or if secure
boot is not required, but an internal boot to the ROM is still needed. All HAB functions are
executed as for a production device, security hardware is initialized (except the SCC is left in
Non-Secure state), DCD is processed if present, and software in Flash or downloaded to RAM is
authenticated by HAB prior to its execution. First error detected is logged, but without any change
to the boot flow. A Command Sequence File (CSF) must be present in this mode, even if it is
invalid or the pointer in the application header is NULL. See Section 7.3.3.9, “Flash Header,” for
more information. It is possible with this level to develop software without requiring that each
build be signed for HAB authentication, since the device will boot even if the code signatures are
missing.
7.3.3.2
Basic Initialization
On reset, the ARM has access to all shared peripherals.
By default, most of the module clocks are gated off in i.MX25. Table 7-4 shows the module clocks which
are enabled by default. All other modules’ clocks are enabled by ROM as described in Section 7.3.3.2.1,
“Normal Mode” and Section 7.3.3.2.2, “Low-Power Boot Mode.”
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Boot Modes
Table 7-4. Module Clocks Enabled by Default
Module
7.3.3.2.1
Clock Source
BROM, EMI, FEC
AHB
NFC
PER
FEC, IIM, SCC, DryIce, and SPBA
IPG
Normal Mode
Table 7-5 shows the clock configurations specified by ROM for normal mode.
Table 7-5. Normal Mode Clock Configuration
Clock Output
7.3.3.2.2
Speed
MPLL
399 MHz
UPLL
240 MHz
ARM core
199.5 MHz
AHB
99.75 MHz
IPG
49.875 MHz
Low-Power Boot Mode
In low-power boot (LPB) mode, MPLL is used as the source of the ARM core clock, serial bus clock (I2C,
CSPI, eSDHC, UART and so on), IPG, perclk_root, AHB bus clocks. ROM configures the ARM core
frequency value based on fuse BT_LPB_FREQ[2:0]. The maximal LPB ARM core frequency is
customized and stored in fuses BT_LPB_FREQ[2:0].
Table 7-6. ARM Core Frequency Encoding for BT_LPB_FREQ[2:0]
Code
Value
0
133 MHz (Default)
1
CKIH
2
55.33 MHz
3
66 MHz
4
83 MHz
5
166 MHz
6
266 MHz
7
Normal boot frequency
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Boot Modes
Table 7-7. Module Frequency List for LPB Frequencies
BT_LPB_FREQ[2:0]
0
1
2
3
4
5
6
7
PLL1 frequency
532
—
166
266
166
166
266
399
ARM frequency
133
24
55.33
66
83
166
266
199.5
ahb_clk_root
66.5
12
27.665
33
41.5
83
133
99.75
ipg_clk_root
33.25
6
13.8325
16.5
20.75
41.5
66.5
49.875
emi_slow_clk_root
66.5
12
27.665
33
41.5
83
133
99.75
nfc_clk_root
16.625
6
13.8325
16.5
10.375
13.8333
16.625
20
perclk_root
33.25
6
13.8325
16.5
20.75
41.5
66.5
49.875
esdhc_clk_root
16.625
3
6.91625
8.25
10.375
13.8333
16.625
49.875
cspi_clk_root
33.25
6
13.8325
16.5
20.75
41.5
66.5
49.875
i2c_clk_root
33.25
6
13.8325
16.5
20.75
41.5
66.5
49.875
7.3.3.3
External Device Selection
The i.MX25 supports the following devices for internal boot mode:
• NOR Flash with WEIM Interface, located on CS0, bus width of 16 bits.
• OneNAND.
• MLC NAND and SLC NAND Flash with NFC interface. Page sizes of 512 bytes, 2KB or 4KB,
bus width of 8-bit or 16-bit.
• SD/MMC/eSD/eMMC using all eSDHC interface, supporting all types of cards.
• eSD FAST BOOT and eMMC Boot Mode (FAST BOOT) are supported using all the eSDHC ports.
• EEPROM boot using SPI and I2C.
• Serial Flash using SPI.
The selection of external flash device type is determined by BT_MEM_CTL[1:0] and
BT_MEM_TYPE[1:0] eFUSEs. See Table 7-2 for more details.
7.3.3.4
NAND Flash Support
Several MLC/SLC NAND Flash devices from different vendors are supported by the boot ROM. The error
correction and control (ECC) module is used to detect errors. Both 8-bit ECC and 4-bit ECC are supported.
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Boot Modes
Table 7-8 shows the parameters used to configure the external NAND Flash. In particular, NAND Flash
boot requires that BT_MEM_CTL be set to 0b01. These parameters are either provided by eFUSEs or
sampled on input contacts during booting.
Table 7-8. Parameter Settings for External NAND Flash
Parameter
Definition
Settings
BT_MLC_SEL
SLC/MLC NAND device.
BT_SPARE_SIZE1
Specifies the size of spare bytes for 4-Kbyte page size NAND 0 128 bytes spare (Samsung)
Flash devices.
1 218 bytes spare (Micron, Toshiba)
BT_PAGE_SIZE[1:0]
NAND Flash page size. This field is used with conjunction with 00 512 bytes
the BT_MEM_CTL[1:0] setting
01 2 Kbytes
10 4 Kbytes
11 Reserved
BT_MEM_TYPE[1:0]
Boot memory type.
00
01
10
11
3 address cycles
4 address cycles
5 address cycles
Reserved
BT_BUS_WIDTH[1:0]
Selects boot device bus mode
00
01
10
11
8 bit bus
16 bit bus
Reserved
Reserved
BT_MEM_CTL[1:0]
Boot memory control type (memory device)
01 NAND Flash
1
0 SLC NAND device
1 MLC NAND device
512-byte page devices have 16 bytes spare area size, 2-Kbyte page devices have 64 bytes spare area size.
Since MLC NAND Flash devices do not guarantee error-free boot blocks, the i.MX25 boot code supports
boot redundancy to provide for the case when an unrecoverable error is detected within the first 4 Kbytes.
To make use of this feature, the user must duplicate the first 4 Kbytes of boot code (contained in NAND
Flash Block-0) to NAND Flash Block-1 in order to serve as a second-copy option.
The boot ROM code makes use of the duplicate boot code according to the following procedure:
• On device power-on, the boot ROM copies the first 4 Kbytes of boot code from the NAND Flash
to the NFC buffer.
• ECC checks the first 4 Kbytes of boot data from NAND Flash Block-0
— If no ECC errors are detected, the downloaded 4 Kbytes image as well as rest of the image is
copied to application destination pointer location (specified in the HAB header) and secure
boot is performed. The application image length is specified in the image header so the boot
ROM reads this to know how much image data to download.
— If ECC Error is detected in first 4 Kbytes of boot data from Block-0, the boot ROM code copies
the duplicated 4k boot data from the NAND flash block-1.
— If an error is detected in the subsequent boot block, boot ROM code logs an error and jumps to
the USB/UART bootloader. The logged error can be queried using the serial protocol.
— If there is no error in the data copy, then the boot ROM performs secure internal boot.
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Boot Modes
7.3.3.5
OneNAND Flash Boot Operation
OneNAND Flash devices are a 16-bit interface. The OneNAND Flash driver in boot ROM obtains the
device page size by issuing a software command and collecting the response from device.
At system power-up, OneNAND automatically copies the first 1 Kbyte of data from the Flash array (sector
0 and sector 1, page 0, block 0) to its internal RAM. This 1 Kbyte area in OneNAND’s internal RAM is
referred to in the following as “boot RAM”. The boot ROM copies the boot RAM contents to a destination
address determined by the app_dest_ptr entry of the application header (Section 7.3.3.9, “Flash Header”),
and decrements the length of the image to be read from OneNAND by 1 Kbyte. The boot RAM is
memory-mapped, and the copying operation is simple memory copying operation. The length of the image
to be read from the OneNAND device is specified in the Flash header structure shown in Table 7-10. Any
failure in the data load operation from OneNAND Flash forces the boot ROM to switch to USB
OTG/UART serial download.
At system power-up, the voltage detector in the device detects the rising edge of Vcc and activates the
internal power-on reset (POR) signal. This in turn triggers boot code loading, so the OneNAND’s boot
loader copies the first 1 Kbyte of the Flash array to boot RAM. The boot code copy operation starts 400 μs
after POR activation, and takes about 70 μs.The INT bit of Interrupt status register is then set on the
condition of ‘boot code copy done’ and RP rising edge.
In the OneNAND boot operation, the boot ROM instructs an on-chip General Purpose Timer (GPT) to
introduce a delay of around 500 μs, then waits for INT bit of the interrupt status register to be set. After
the INT bit is set, the boot ROM then proceeds with OneNAND initialization.
7.3.3.6
Serial ROM Support using SPI and I2C
The i.MX25 supports boot from serial memory devices such as EEPROM, and Serial Flash using the SPI
(Chip Select #1) and I2C interfaces.
The Boot ROM code determines the device type from the following parameters which are either provided
by eFUSEs or sampled on I/O contacts during boot:
• BT_MEM_TYPE[1:0]—SPI/I2C select.
• For SPI, “BT_BUS_WIDTH” selects between 2/3-address word devices. BT_SRC[1:0] selects
between CSPI1, CSPI2 and CSPI3.
• For I2C, BT_SRC[1:0] selects between I2C-1, I2C-2, or I2C-3.
See Table 7-3 for detailed settings.
7.3.3.6.1
CSPI Boot
Any of the CSPI modules can be used as boot device for booting from a serial device. The CSPI interface
is configured in Master mode. The serial device is connected to CSPI interface as slave.
CSPI boot proceeds as follows:
•
•
Boot ROM copies 2 Kbytes of data from the serial device to internal RAM.
DCD verification is attempted
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Boot Modes
— If DCD verification is successful, the ROM code copies the initial 2 Kbytes of data as well as
the rest of image directly to the application destination, extracted from application image.
— If DCD verification fails, ROM code execution logs and error and jumps to USB/UART serial
downloader.
The CSPI can read data from the EEPROM using either 2- or 3-byte addressing, with a burst length of
32 bytes.
NOTE
The Serial ROM is required to reside on Chip Select #1 of the CSPI module.
Using SPI as boot device, the i.MX25 supports boot from both Serial
EEPROMS, and Serial Flash devices.
7.3.3.6.2
I2C Boot
Any of the I2C modules can be used as boot device using the I2C interface for serial EEPROM boot. The
I2C interface is configured to operate at speeds up to 389.6 Kbps.
The I2C boot flow proceeds as follows:
1. The boot ROM code reads from fuses BT_SRC[1:0] and BT_MEM_TYPE to determine that the
I2C interface is to be used for boot, and to specify which I2C module is used.
2. The boot ROM then copies 2 Kbytes of data from the EEPROM device to internal RAM.
3. DCD verification is performed:
— If DCD verification is successful, the ROM code copies the initial 2 Kbytes of data as well as
the rest of image directly to application destination extracted from the application image.
— If DCD verification fails, ROM code execution logs the error and jumps to the USB/UART
serial downloader.
Table 7-9 shows the device select codes used by the i.MX25 to boot from EEPROM.
Table 7-9. EEPROM using I2C Device Select Code
Device Type Identifier
RW
Bits
7
6
5
4
3
2
1
0
Device Select Code
1
0
1
0
0
0
0
RW
1
7.3.3.7
Chip Enable Address1
These address bits, should be configured at the memory device, to match this ‘000’
value.
NOR Flash (using WEIM) Support
The i.MX25 device supports booting from the WEIM NOR Flash interface. The device configures the
NOR boot mode by hardware, due to existence of a direct NOR Flash boot option. The boot ROM code is
not required to change these options. The IOMUX settings at POR support NOR boot by default. The NOR
Flash interface works in asynchronous mode, and supports 16-bit muxed Address/Data and non-muxed
schemes, based on the BT_BUS_WIDTH[1:0] fuse settings.
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Boot Modes
24-bit address is available for boot. When booting, if there is no device contention on EIM[27:24], the
downloaded NOR driver can configure IOMUX to switch on 28-bit NOR address mode.
7.3.3.8
Expansion Card Device Support (SD/MMC)
The i.MX25 device supports booting from MMC and SD Card-compatible devices. Boot is also supported
for mass storage cards (high-capacity cards, SD and MMC version 4.3), SanDisk’s iNAND cards, and new
eSD (Embedded SD, version 2.0 and 2.1 Draft Rev 0.2, June 20th 2007)–type cards.
SD/MMC Boot can be performed using either eSDHC-1 or eSDHC-2, based on the BT_SRC[1:0] fuse
value or its associated input contact value at out-of-reset. See Table 7-2 for detailed settings. Low-voltage
devices (1.8 V) can also be supported using the application code, by control of the power supply level. This
task is not handled by the boot ROM code.
MMC/SD/eSD can be connected to either eSDHC-1 or eSDHC-2, and booting is done by copying first
2 Kbytes of data from MMC/SD/eSD device to internal RAM. After verifying the Barker value (0xB1)
from the boot image, the ROM code performs a DCD check. If successful, the ROM code then extracts the
destination pointer and the length of image to be copied to the RAM device where code execution occurs.
7.3.3.8.1
Secure Digital (SD) and Embedded Secure Digital (eSD) Cards)
The SD or eSD card frequency should be set to 311.71kHz for the negotiation phase. During negotiation
phase SD and eSD card voltage validation is performed. During voltage validation, boot code first checks
with high voltage settings and if it fails it checks with low voltage settings. Capacity of card is also
checked. Boot code supports high capacity and low capacity SD and eSD cards. After voltage validation,
card initialization is done. During card initialization boot code tries to set boot partition for both SD and
eSD device. If it fails, boot code assumes card as normal SD card otherwise as eSD card. After
initialization phase is over, boot code switches to a higher frequency, 16.625MHz. ROM also support
FAST_BOOT mode booting from eSD card. This mode can be selected by BT_SPARE_SIZE fuse.
The boot ROM uses 1-bit accesses to card. Application code can switch to 4- or 8-bit mode.
Figure 7-2 through Figure 7-4 show the SD/eSD boot flow.
7.3.3.8.2
MMC and eMMC
The MMC frequency is set to 311.71 kHz for the negotiation phase. During negotiation phase MMC, card
voltage validation is performed. During voltage validation, boot code first checks with high voltage
settings, if it fails it checks with Dual voltage settings and capacity of card is checked. Boot code supports
both high-capacity and low-capacity MMC cards. After voltage validation, card initialization is complete,
and boot code can switch to a higher frequency, 16.625 MHz.
eMMC is also interfaced using eSDHC and follows same flow as done by MMC. Boot partition can be
selected for eMMC cards, after the card initialization has been done. ROM reads the
BOOT_PARTITION_ENABLE field in the Ext_CSD[179] to get the boot partition to be set. If there is no
boot partition mentioned in BOOT_PARTITION_ENABLE field or the user partition has been mentioned,
ROM boots from the user partition. eMMC device support special “Boot mode”, which can be initiated by
issuing CMD0 with 0xFFFFFFFA. If BOOT ACK is enabled, the eMMC device sends the BOOT ACK
using DATA0 and ROM can read the BOOT ACK [S010E] to identify the eMMC device.
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Boot Modes
eMMC device with “Boot mode” feature is supported using eSDHC-1 and eSDHC-2 with BOOT ACK
enabled. ROM waits for 50ms to get the BOOT ACK and if BOOT ACK is received by ROM, then only
eMMC is booted in “Boot mode”, otherwise eMMC boots as a normal MMC card from the selected boot
partition. This boot mode can be selected by BT_MLC_SEL fuse. Only 1-bit bus width is used in ROM.
MoviNAND is also interfaced using eSDHC and follows the same flow as the MMC.
Figure 7-2 through Figure 7-4 show the boot flow for MMC and eMMC.
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Boot Modes
MMC/SD
Boot Entry
Point
eSDHC Software Reset
Set Identification frequency
(Approx 400 KHZ)
Introduce GPT delay of
2msec
Card S/W Reset
(CMD0)
Issue CMD 8 with
HV (3.3V)
SD Boot
No
SD Voltage Validation
1
Yes
Issue CMD 8 with LV
(1.8V)
Command
Successful ?
Start GPT delay of
1s for ACMD41
1
Yes
Yes
No
Command
Successful ?
Loop Cntr < 3000
and looping period
< 1s
Start GPT delay of
1s for ACMD41
No
Yes
Issue CMD55
Issue ACMD41 with
HV and HC
Increment loop
counter
Command
Successful ?
2
Yes
No
No
Yes
Yes
No
Yes
Yes
Issue ACMD41 with
LV and HC
Yes
Is Response
OCR for HC
No
Card is LC
SD
SD read SCR
Read 8 bytes response
(SCR0 value = spec ver and
bus width)
Yes
Sd
version
1.0 ?
Yes
Yes
Is
STATUS_APP_CMD[6]
== 1?
No
Set Block Length =
64 bytes, WML = 16
Send CMD6 to
switch commands
No
Command
Successful ?
Issue ACMD51
(RCA as argument)
Put card in data
Transfer Mode
(Issue CMD 7)
Card is LC
SD ver 1.x
Busy Bit == 1
No
Card is HC
SD
Command
Successful ?
No
Yes
Yes
Card is LC
SD
Set operating
frequency upto 20
MHz
2
Command
Successful ?
Increment loop
counter
Card is HC
SD
No
Get RCA
(Issue CMD3)
No
Command
Successful ?
Loop Cntr < 3000
and looping period
< 1s
Busy Bit == 1
Is Response
OCR for HC
Get CID from card
(Issue CMD2)
No
Command
Successful ?
Issue CMD55
SD Set Boot
Partition
5
Set Block Length =
512bytes , WML =
128
No
Yes
No
Card is eSD card and
Partition 1 got selected
Read 512 bit
response
Yes
No
6
Read R1 response
Command
Successful ?
Yes
Command
Successful ?
Send CMD13 to
read status
No
Card State ==
TRANS
No
Yes
No
Set Block Length
= 512bytes ,
WML = 128
Response[16] ==
x20?
Yes
Card state ==
trans
Yes
Send CMD37 to
select partition 1
Issue CMD55
(RCA as argument)
Set BL = 8 bytes, WML = 2
To read SCR register
No
No
Command
Successful ?
No
5
Command
Successful ?
Yes
Send CMD13 to read status
Figure 7-2. SD and MMC Boot Flow
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Boot Modes
2
eMMC BOOT ACK
Configure CMD and DAT0 line as GPIO
eMMC boot Flow
eSDHC reset and set the identification
frequency and wait for 2ms
Set CMD line low
3
Poll DAT0 for 55ms to get the boot ACK S 010E
Got eMMC boot
ACK?
No
Yes
Release DAT0 line
to eSDHC
Configure operating
frequency ~ 20MHz
Wait for 0.5 ms
No
DTOE set or
timer expires?
5
Set DTOCV
to 1 second
Wait for boot data to
come on DAT0
eMMC data read
Send virtual read
command to eSDHC
Yes
Release CMD and
DAT0 line to eSDHC
6
3
MMC volatage validation
Start GPT with 1s
delay for CMD1
Increment loop
counter
Issue CMD1 with HV
Command
Successful ?
No
Set RCA (Issue CMD3)
Get Spec Version
( Issue CMD9).
6
No
Yes
Busy Bit == 1
Yes
No
Is Response
OCR for HC
MMC Init
Get CID from card
(Issue CMD2)
Yes
Loop Cntr < 3000
and looping period
< 1s
Set operating frequency
to 20 MHz
Yes
Put card in data
Transfer Mode
(Issue CMD7)
Card is HC
MMC
No
Card is LC
MMC
4
Yes
Card State ==
TRANS
No
6
Figure 7-3. SD and MMC Boot Flow (continued)
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Boot Modes
C a rd re a d d a ta
5
6
R e a d 5 1 2 b y te s o f d a ta
fro m M M C /S D /e S D /
e M M C C a rd (C M D 1 7 )
a n d c o p y to IR A M
No
2 K D a ta R e a d ?
U S B /U A R T flo w
(S e ria l b o o t )
Yes
C h e c k fo r b a rk e r
No
B ra k e r
p re s e n t?
E x e c u te th e
Im a g e
J u m p to a p p lic a tio n
c o d e ju m p v e c to r
Yes
C h e c k fo r s e c u rity ty p e
Yes
S e c u rity
d is s a b le d ?
No
C o p y re s t o f im a g e
d a ta fro m S D /M M C /
e S D /e M M C to S D R A M
P a rs e v a lid
a d d re s s ra n g e
A d d re s s
ra n g e is
v a lid ?
C o p y 2 k d a ta
im a g e d a ta fro m
IR A M to S D R A M
No
6
Yes
C o n fig u re th e
d e v ic e u s in g D C D
Yes
D e v ic e
c o n fig u ra tio n
pass?
No
Figure 7-4. SD and MMC Boot Flow (continued)
7.3.3.9
Flash Header
The Flash header is a data structure that the boot code reads from Flash which provides information about
the application. The Flash header must be located at a known fixed address depending on the type of
external Flash device connected to i.MX25. The Flash header is only required when an internal boot mode
is selected from BOOT_MODE[0:1]. The required offsets of the Flash header for each device type are
described in Table 7-10.
Table 7-10. Flash Header Offset
Flash Type
Offset from Base Address
NOR
4 Kbyte = 0x1000 bytes
NAND
1 Kbyte = 0x400 bytes
OneNAND
256 bytes = 0x100 bytes
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Boot Modes
Table 7-10. Flash Header Offset (continued)
Flash Type
Offset from Base Address
SD/eSD/MMC/eMMC
1 kbyte = 0x400 bytes
I2C/CSPI EEPROM
1 kbyte = 0x400 bytes
.
Flash Memory
Dest. Memory
Flash base
Flash Header offset
*app_code_jump_vector
Flash Header offset
app_code_barker
*app_code_jump_vector
app_code_barker
*app_code_csf
*app_code_csf
**dcd_ptr_ptr
**dcd_ptr_ptr
*super_root_key
*super_root_key
*dcd_ptr
*dcd_ptr
*app_dest_ptr
*app_dest_ptr
application
application
device configuration data
External Flash hdr
device configuration data
External Flash hdr
super root key
super root key
certificates and csf data
certificates and csf data
Figure 7-5. Flash Header Example for Devices Other Than NOR Flash
The Flash header must conform to the structure defined below:
typedef struct
{
UINT32
UINT32
UINT32
DCD_T
hab_rsa_public_key
DCD_T
UINT32
} FLASH_HDR_T;
*app_code_jump_vector;
app_code_barker;
*app_code_csf;
**dcd_ptr_ptr;
*super_root_key;
*dcd_ptr;
*app_dest_ptr;
where:
UINT32 is a 32 bit unsigned integer
DCD_T is a structure that defines the device configuration table (see below for details)
hab_rsa_public_key is a structure defines the super root key
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Boot Modes
Table 7-11 shows the significance of the variables listed in the Flash header structure.
Table 7-11. Flash Header Structure Fields
Field Abbreviation
Significance
app_code_jump_vector pointer Points to the address of the first instruction of the application
app_code_barker
A value that the ROM uses to determine that the Flash device has been programmed. For
i.MX25 the app_code_barker value must be set to 0x000000B1.
app_code_csf pointer
Points to the certificate and command sequence file data. This data is used by the High
Assurance Boot (HAB) library included in the ROM to verify that the application is authentic.
Should be set to 0x0 when not used in a non-secure boot.
dcd_ptr_ptr double pointer
This pointer must be set to point to the dcd_ptr also contained in the Flash header structure.
super_root_key
Pointer to the super root key data. Should be set to 0x0 when not used in a non-secure boot.
The super root key data should conform to the structure shown in the following code excerpt.
typedef struct
{
UINT8 rsa_exponent[MAX_EXP_SIZE];
/* RSA public exponent */
UINT8
*rsa_modulus;
/* RSA modulus pointer */
UINT16 exponent_size;
/* Exponent size in bytes */
UINT16 modulus_size;
/* Modulus size in bytes*/
BOOLEAN init_flag;
/* Indicates if key initialized
*/
} hab_rsa_public_key;
where:
UINT8 is an 8 bit unsigned integer
UINT16 is a 16 bit unsigned integer
BOOLEAN is an 8 bit flag indicating TRUE or FALSE
The variables in this code excerpt have significance as shown in the table:
Variable
Significance
rsa_exponent
Exponent of the RSA key. Maximum exponent size is 4.
rsa_modulus
Pointer to the RSA key modulus.
exponent size Exponent size in bytes. Must be less than or equal to the maximum
exponent size.
modulus size:
Modulus size in bytes. Must be greater than or equal to 128 and less than
or equal to 256.
dcd_ptr
Points to the device configuration data (DCD) table. See Section 7.3.3.10, “Device
Configuration Data (DCD),” for further details on the DCD table.
app_dest_ptr
Used by the ROM for NAND/MMC/eMMC/SD/eSD/SPI(EEPROM)/OneNAND boot. During
boot the ROM copies the application data from boot Flash memory to destination RAM. This
pointer defines the location of destination memory where the ROM copies the application.
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Boot Modes
7.3.3.9.1
Flash Header for NAND Boot Devices
In the case of NAND boot, an additional Flash header must be defined as shown in the code example
below. This additional Flash header must be located immediately after the DCD table and contains the
length of the data to be read from boot device.
/* Flash Header Structure */
typedef struct {
UINT32 length;
/* Length of data to be read */
} FLASH_CFG_PARMS_T;
where: UINT32 is a 32 bit unsigned integer.
In this Flash header structure, the parameter ‘length’ determines the length of image to copy to RAM.
Address Cycle Values for NAND Boot Devices
The Address cycle value for the connected NAND device is obtained from the BT_MEM_TYPE eFUSEs.
See Table 7-8 for more information.
Error Detection and Correction
NFC automatically generates an ECC code for both main and spare data during NFC data load/read
to/from NAND Flash, and NFC updates ECC in the ECC status Register. NFC performs error detection
and error correction. If the number of ECC errors does not exceed the allowable limit (four for 4-bit ECC,
eight for 8-bit ECC), then NFC corrects those errors.
On device power on, the copy of first 4 Kbytes boot data from NAND Flash device Block-0 to NFC buffer
is done by boot ROM. Since in NAND Flash devices there are possibility of getting errors while reading
first 4 Kbytes boot data from first block (NAND device Block-0), the user is required to duplicate the first
4 Kbytes boot code to the subsequent block (NAND device Block-1), to serve as a second copy option.
The boot ROM code utilizes the duplicate boot code according to the following flow:
1. If no ECC errors are detected in first boot block, boot execution performs the secure internal boot.
2. If ECC Error is detected in first 4 Kbytes boot data from the first block, the boot ROM code copies
the 4 Kbytes boot data from the subsequent block:
— If no error detected in the subsequent boot block, boot flow continues performing the secure
internal boot.
— If an error is detected in the subsequent boot block, the boot ROM code logs an error and jumps
to USB/UART bootloader. The logged error can be queried using the serial protocol.
Figure 7-6 shows the arrangement of data in NAND Flash, in the case of duplicate boot code.
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Boot Modes
First 4 Kbytes Boot
Data starts
from Block 0
Rest of Image
BLOCK 0
of NAND
Copy of First 4 Kbytes
Boot Data from
Block 1
BLOCK 1
of NAND
Copy of Rest of
Image Block 1
BLOCK 2- n
Figure 7-6. Duplicate Boot Code Data in NAND Flash Device
7.3.3.9.2
Flash Header for SD/eSD/MMC/eMMC/MoviNAND Boot Devices
The SD/eSD/MMC/eMMC/MoviNAND boot block size is fixed at 2 Kbytes. An additional header must
be defined (just as in the NAND boot case), as described in Section 7.3.3.9.1, “Flash Header for NAND
Boot Devices.” See Figure 7-7. The header must be located immediately after the DCD table, and contains
the length of the data to be read from boot device. eSDHC automatically generates CRC code during
eSDHC data write/read to/from SD/eSD/MMC/eMMC/MoviNAND, and eSDHC updates the CRC in the
CRC status register. Boot software performs following operations:
1. Copy the 2 Kbytes boot block data into internal RAM.
2. Check the CRC for errors:
a) If no CRC error, then jump to address (base address plus the offset mentioned in Table 7-10 for
SD/eSD/MMC/eMMC/MoviNAND) of internal RAM to authenticate the application if
required.
b) If CRC error occurs, boot ROM code will log an error and jumps to USB/UART bootloader.
The logged error can be queried using the serial protocol.
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Boot Modes
2K Boot Block
Data starts from Block0
Rest of image
Figure 7-7. Representation of Data in SD/MMC Card
7.3.3.9.3
Flash Header for I2C/CSPI EEPROM Boot Devices
The I2C/CSPI EEPROM boot block size is fixed at 2 Kbytes. An additional header must be defined as in
the NAND boot case (described in Section 7.3.3.9.1, “Flash Header for NAND Boot Devices”): the header
is located immediately after the DCD table, and contains the length of the data to be read from the boot
device. Representation of image data in I2C/CSPI EEPROM is as shown in Figure 7-8.
The boot software performs the following operations:
1. Copy the 2 Kbytes boot block data into internal RAM.
2. Check the error using the Barker value:
a) If no error is found, then jump to the address (base address plus the offset described in
Table 7-10 for I2C/CSPI EEPROM) of internal RAM to authenticate the application if required.
b) If an error is found, then boot ROM code will log an error and jumps to USB/UART bootloader.
The logged error can be queried using the serial protocol.
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Boot Modes
2K Boot Block
Data
Starts from
BLOCK 0
Rest of Image
Figure 7-8. Representation of Data in I2C/CSPI EEPROM
7.3.3.9.4
Flash Header for OneNAND Boot Devices
In the OneNAND boot case, an additional header must be defined as for NAND boot (described in
Section 7.3.3.9.1, “Flash Header for NAND Boot Devices”). The header must be located immediately after
the DCD table, and contains the length of the data to be read from boot device.
The boot software performs the following operations:
1. At system power-up, OneNAND automatically copies 1 Kbyte data from the start of the Flash
array (sector 0 and sector 1, page 0, block 0) to its boot RAM, so that boot RAM contains the
OneNAND Flash header.
2. Boot ROM then copies the 1 Kbyte OneNAND boot RAM contents to the destination address
located in the app_dest_ptr entry of application header, and decrements length of the image to be
read from OneNAND by 1 Kbyte.
Boot RAM area is memory-mapped and copying operation will be simple memory copying
operation. The length of image to be read from OneNAND device is specified in the Flash header
structure described in Figure 7-9. Any failure in the data loading from OneNAND Flash forces the
processor boot ROM to switch to serial download.
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Boot Modes
1K Boot Block
Data
Starts from
BLOCK 0
Rest of Image
Figure 7-9. Representation of Data in OneNAND Flash
7.3.3.10
Device Configuration Data (DCD)
Some peripherals need to be configured before they can be used efficiently. The corresponding device
specific configuration data is called DCD.
Upon reset, the i.MX25 uses the default register values for all peripherals in the system. These settings
typically are not ideal for achieving optimal system performance.
For example, the EMI default settings allow core to interface to a NOR flash device immediately out of
reset. This allows to interface with any NOR flash device, but has the cost of slow performance. Besides
some peripherals like SDRAM etc. might require some sequence of register programming as part of
configuration before it's ready to be used. It is assumed that EMI registers and eSDRAMC registers will
be set up using DCD.
ROM bootstrap has a provision for accommodating solutions to above scenarios. To allow users to
configure for better performance, the ROM reads a DCD table from the flash device. The boot ROM
determines the location of the DCD table based on information located in the flash header shown in
Figure 7-5 above. This DCD table is an array of structures containing three elements (access type, address
and value) preceded by a barker code and length field. The number of DCD structure entries is limited to
60.
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Boot Modes
Table 7-12. DCD Block Description
Field Name
Description
Size (Bytes)
Value
DCD-barker
Barker for sanity check
4
0xB17219E9
DCD-block-length
The total length in bytes of theDCD block (excluding this length field as
well as the barker code)
4
—
Followed by an array of structures with following fields
DCD access type
Type of pointer (byte=0x1 halfword=0x2, word=0x4) in the following
field
4
—
DCD-address
The absolute address of the register to be programmed
4
—
DCD-value
The value to be programmed at above address
4
—
Note: The DCD is read as 32-bit words, and must therefore be aligned on a word boundary.
The set of registers programmable with DCD must be restricted for security. Since the device configuration
block is only post-authenticated (that is. after it has already been used), the restriction has to be very tight.
ROM bootstrap performs boundary checking of DCD-address in the device configuration block against
the valid range of addresses. The register sets allowed by the device configuration block include the
following:
• Clock Controller Module (CCM)
• UART-1–5
• Universal Synchronous Bus (USB)
• IOMUX (only for the drive-strength registers SW_PAD_CTL)
• Watchdog (WDOG)
• NAND flash controller (NFC)
• Enhanced synchronous dynamic RAM controller (eSDRAMC)
• Wireless external interface module (WEIM)
• Enhanced SD host controller (eSDHC-1 and eSDHC-2)
• I2C-1–3
• Configurable serial peripheral interface (CSPI) 1–3
• CS0–4
• CSD0–1
• Real Time Integrity Checker (RTIC)
ROM bootstrap has a look-up table of lower and upper addresses for each module allowed to be
programmed through the DCD. This table is utilized for verifying any attempt to configure a register. ROM
bootstrap determines the size of the block by reading DCD-block-length and copies it into IRAM. It is
considered to be an error if any of the following is true:
•
Any register address is outside the pre-defined range.
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Boot Modes
•
•
The length of the DCD exceeds the maximum acceptable size. That is MAX_HW_CFG_SIZE (in
bytes). Assuming maximum of sixty elements for the array it amounts to seven hundred and twenty
bytes.
Any other failure.
If successful, ROM bootstrap configures the HW registers and failure leads to non-initialization of the
intended modules. A DCD error (for example, writing to a non-supported address such as ROMPATCH)
causes the ROM boot code to enter the boot loader (serial download).
The DCD table must follow the structure below:
typedef struct
{
DCD_PREAMBLE_T preamble; /* Preamble */
/* Type / Address / data elements */
DCD_TYPE_ADDR_DATA_T type_addr_data[count]; /*where count would be some hardcoded value
less than 60*/
} DCD_T;
Where:
typedef struct
{
UINT32 barker; /* Barker for sanity check */
UINT32 length; /* Device configuration structure length (not including preamble) */
} DCD_PREAMBLE_T;
typedef struct
{
UINT32 type; /* Type of pointer (byte=0x1, halfword=0x2, word=0x4) */
UINT32 *addr; /* Address to write to */
UINT32 data; /* Data to write */
} DCD_TYPE_ADDR_DATA_T;
DCD_T typically contains the configuration data for WDOG, SDRAM, and EIM etc.
Example code:
DCD_T device_config_data =
{
{
IROM_DCD_BARKER, /* assuming this is pre-defined as macro */
(18 * sizeof(DCD_TYPE_ADDR_DATA_T))
},
{
{0x00000002, (UINT32 *)0x53fdc000, 0x00003F7E}, /* WDOG WCR */
{0x00000002, (UINT32 *)0x53fdc004, 0x00005555}, /* WDOG WSR */
{0x00000002, (UINT32 *)0x53fdc004, 0x0000aaaa}, /* WDOG WSR */
{0x00000004, (UINT32 *)0xb8002000, 0x14110802}, /* EIM CTL H 0x11134722 */
{0x00000004, (UINT32 *)0xb8002004, 0x80330d01}, /* EIM CTL L -0x50331D01- 16 Bit */
{0x00000004, (UINT32 *)0xb8002008, 0x00000800}, /* EIM CTL A */
{0x00000002, (UINT32 *)0xa0002394, 0x00000060}, /* EIM CS0 -6F0C- 16 Bit */
{0x00000002, (UINT32 *)0xa0002394, 0x00000003}, /* EIM CS0 -6F0C- 16 Bit */
{0x00000002, (UINT32 *)0xa0000000, 0x000000ff}, /* EIM CS0 - R/A - 16 Bit */
{0x00000004, (UINT32 *)0xb8001004, 0x000ac7a8}, /* SDRAM CS0 CFG0 - Timing */
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Boot Modes
{0x00000004,
{0x00000004,
{0x00000004,
{0x00000004,
{0x00000004,
{0x00000004,
{0x00000001,
{0x00000004,
(UINT32
(UINT32
(UINT32
(UINT32
(UINT32
(UINT32
(UINT32
(UINT32
*)0xb8001000,
*)0x80000400,
*)0xB8001000,
*)0x80000000,
*)0x80000000,
*)0xB8001000,
*)0x80000033,
*)0xB8001000,
0x92110080},
0x00000000},
0xa2110080},
0x00000000},
0x00000000},
0xb2110080},
0x00000000},
0x82114c80},
/*
/*
/*
/*
/*
/*
/*
/*
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
CS0
CS0
CS0
CS0
CS0
CS0
CS0
CS0
CTL0 - Enable */
- Precharge */
- Refresh */
- Refresh */
- Refresh */
- Load Mode */
- Load Mode */
- Norm Mode */
}
};
The code above is based on Table 7-13.
Table 7-13. Valid DCD Address Range
Address Range
Start Address
Length (in bytes)
CCM register set
0x53F80000
0x00004000
CSD0 memory
0x80000000
0x10000000
CSD1 memory
0x90000000
0x10000000
WEIM register set
0xB8002000
0x00001000
NFC register set
0xBB000000
0x00002000
CS0 memory
0xA0000000
0x08000000
CS1 memory
0xA8000000
0x08000000
CS2 memory
0xB0000000
0x02000000
CS3 memory
0xB2000000
0x02000000
CS4 memory
0xB4000000
0x02000000
USB memory
0x53FF4000
0x00004000
IOMUXC registers
0x43FAC000
0x00004000
UART1 register
0x43F90000
0x00004000
UART2 register
0x43F94000
0x00004000
UART3 register
0x5000C000
0x00004000
UART4 register
0x50008000
0x00004000
UART5 register
0x5002C000
0x00004000
I2C1 register
0x43F80000
0x00004000
I2C2 register
0x43F98000
0x00004000
I2C3 register
0x43F84000
0x00004000
CSPI1 register
0x43FA4000
0x00004000
CSPI2 register
0x50010000
0x00004000
CSPI3 register
0x50004000
0x00004000
WDOG register
0x53FDC000
0x00004000
eSDHC1 register
0x53FB4000
0x00004000
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Boot Modes
Table 7-13. Valid DCD Address Range
Address Range
Start Address
Length (in bytes)
eSDHC2 register
0x53FB8000
0x00004000
eSDRAM controller
0xB8001000
0x00001000
RTIC register
0x53FEC000
0x00004000
In the boot flow, the DCD data is used prior to being verified.The DCD data must be included as part of
the memory regions verified as indicated in one of the HAB CSF commands.
7.3.4
External Boot Mode (BOOT_MODE[1:0] = 10)
External boot is selected by driving value of ‘10’ on the BMOD[1:0] pins at device power up and fuse
DIR_BT_DIS is not blown. This mode is non-secure mode. In this mode, the core boots directly from
external memory (in the case of WEIM) or running NAND-flash boot. The supported direct external flash
types include the following:
• NOR flash using WEIM
• NAND flash
7.3.4.1
NOR Flash using WEIM
i.MX25 supports either muxed or non-muxed address data boot from WEIM interface.
NOTE
The boot from WEIM is reserved for debugging/testing purposes, and the
WEIM signals are muxed with the display port. If still user’s uses this mode,
it is up to the loaded code, to switch back the IO muxing to the display port,
on finish of boot.
7.3.4.2
NAND Flash
i.MX25 supports external boot from a NAND device. The initial 4 Kbytes of data is copied from the
Flash onto the NFC buffer and jumps to the base address of the NFC buffer to execute it.
7.3.5
UART/USB Serial Download Mode (BOOT_MODE[1:0]=11)
The UART/USB serial download mode is selected by driving a value of ‘11’ on the BOOT_MODE[1:0]
contacts at device power-up. Bootable UART is selected by BT_UART_SRC[2:0] fuses. Selection
between UART and USB download boot device is made by polling the UART and USB controllers in turn.
Whichever device shows activity first is selected.
This mode is also invoked when the external Flash device is not programmed or when a failure is
encountered during the boot flow process. It is invoked in any of the following conditions:
• ROM is in internal boot and none of the fuses for external Flash are satisfied.
• Security hardware failure
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Boot Modes
•
•
Run time exception occurs
Error returned by the HAB functions in production mode.
To determine the active serial port either UART or USB, the processor ROM polls UART and USB status
register for about 90 seconds. If there is no activity on either port within predefined polling loop time then
ROM will reset the device using WDOG. In USB/UART bootloader valid case the WDOG will be serviced
periodically. WDOG will expire and reset the device if the communication between the Host and the IC
hangs for more than 90 s or if the processor goes into an endless loop.
If UART1–5 (selected depending on the BT_UART_SRC[1:0] eFUSE values) is selected as the
communication path then UART1–5 is configured for baud rate 115.2 kbps, parity disable, 1 stop bit and
8-bit TX-RX character length and data is downloaded using the serial protocol. Otherwise, if USB is
selected, then the USB core and either the internal or external transceiver are configured.
For the UART, activity is detected using the receive data ready (RDR) flag showing at least one character
has been read into the FIFO.
For the USB, either the integrated on-chip PHY or the external PHY (using ULPI interface) can be used.
Activity is detected using the setup endpoint status register showing that the setup transaction is received.
The USB/UART boot flow is shown in Figure 7-10.
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Boot Modes
Figure 7-10. USB/UART Boot Flow
7.3.5.1
USB
The i.MX25 USB support is provided by the USB module (high performance USB On-The-Go (OTG)
functionality, compatible with the USB 2.0 specification, the OTG supplement and the ULPI
specification). The module consists of 2 independent USB cores (OTG and HOST), each with Serial and
ULPI USB ports. The OTG core also supply the UTMI interface for the internal UTMI PHY.
USB OTG port is the bootable USB device. Additional USB hosts are intended for intra-platform
communication, and are not bootable.
Since boot image loading through USB interface takes negligible time, the boot using USB is supported
by USB Full Speed mode only.
To enumerate the ROM boot USB function the host PC needs a compatible windows driver and a specific
application “ADS Tool kit”. Once enumerated, the USB boot device uses a specific protocol “Download
protocol” to download an application, DCD block or command sequence file (CSF) and launch the
application.
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Boot Modes
For USB boot, the USBOTG controller is used either with the integrated PHY (typical case) or using ULPI
interface to an external PHY: selection is determined either by fuses, or by sampling contacts at boot as
described in Table 7-15. The boot ROM USB driver configures the USB controller to function in Full
Speed mode. The control endpoints EP0IN and EP0OUT are configured for control transfer and for data
transfer in bulk mode. EP1OUT and EP2IN are configured as IN and OUT transactions respectively.
The supported transceivers are listed in Table 7-14.
Table 7-14. Supported Transceivers
Transceiver
7.3.5.1.1
Boot Speed
Interface
USB Controller
Mode
Integral PHY
Full Speed (FS) UTMI
FS Device
External PHY
Full Speed (FS) ULPI
FS Device
USB Configuration Details
A full-speed low-level USB OTG function device driver is supported. Supported USB transceivers
include:
• USB OTG Internal PHY.
• USB OTG External ULPI PHY.
Table 7-15. USB BOOT mode fuse setting
BOOT MODE
Senna Fuse
USB OTG Internal PHY
BT_USB_SRC=00
USB OTG External ULPI PHY
BT_USB_SRC=01
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Boot Modes
The VID/PID and strings for USB device driver are listed in Table 7-16.
Table 7-16. VID/PID and Strings for USB Device Driver
Descriptor
Value
VID
0x15A2
(Freescale vendor ID)
PID
003A
String Descriptor1
(iManufacturer)
Freescale Semiconductor Inc.
String Descriptor2
(iProduct)
SP Blank
SENNA
SE Blank
SENNA
NS Blank
SENNA
String Descriptor4
Freescale Flash
String Descriptor5
Freescale Flash
Remarks
Allocated Based on BPN
(Before Part Number)
A typical USB boot flow is shown in Figure 7-11.
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Boot Modes
Read BT_USB_SRC(1/0) fuse
BT_USB_SRC=01
BT_USB_SRC ??
BT_USB_SRC=00
Complete UTMI 8bit
synchronous Configuration
and USBOTG = FS
Complete ULPI 8 bit
Synchronous Configuration
and USBOTG = FS
ULPI, FS path
UTMI, FS path
Enable USB UPD Pullup
via a ULPI write
Complete the USB
enumeration process
Poll for Activity
Figure 7-11. USB Boot Flow
7.3.5.2
UART
All UART ports are bootable.
Once initialized, the UART boot device uses a specific protocol “Serial Downloader Protocol” to
download an application, DCD block or command sequence file (CSF) and launch the application.
The UART driver uses the communication parameters given in the Table 7-17 below.
Table 7-17. UART Configuration
Parameter
Value
Baud rate
115.2 kbps
Parity check
Disabled
Word size
8 bits
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Exception Handling
Table 7-17. UART Configuration (continued)
Parameter
7.4
Value
Stop bits
1 bit
RTS
Ignored
CTS
Controlled by host
Receive contact
RxD
Transmit contact
TxD
Exception Handling
No special interrupt handling routines are required during bootup. Instead, the iRAM exception table is
filled with the address of the USB/UART bootloader module, so that any exception or interrupt will result
in the RAM path being executed. Interrupts are disabled during boot ROM code execution, and can be
enabled after boot ROM code execution. Flash or RAM applications image are responsible for enabling of
interrupts as required.
7.5
Error Logging
All ROM errors are logged to address 0x7800_18D4.
7.6
USB Low-Power Boot Mode
i.MX25 supports low-power boot (LPB) mode with depleted or disconnected battery, from USB power
supply only.
ROM involvement in LPB is required to be minimal, while most required configuration operations are
performed by downloaded power management IC (PMIC) and USB drivers.
The platform current consumption during LPB ROM stage is less than 100 mA of VUSB. To meet this
requirement, the DRAM module can be disabled and the primary boot image downloaded to iRAM.
The BT_LPB fuse settings determine the LPB mode as shown in Table 7-18.
Table 7-18. BT_LPB eFUSE Settings and Associated LPB Modes
BT_LPB[1:0]
LPB Mode
00
LPB disabled
01
Generic PMIC and one GPIO input (low battery detection)
10
Generic PMIC and two GPIO inputs (low battery and charger detection)
11
Atlas AP PMIC
The PMICs indicate power conditions through the GPIO_C contact. For example, in the basic case
(BT_LPB[1:0]=01) where PMIC is used for low battery detection, then the signal is driven high is the
battery is ready for normal boot; the signal is driven low if the battery is low, depleted, or disconnected. In
the case where the PMIC is used for both battery and charger detection (BT_LPB[1:0]=01), then GPIO_F
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USB Low-Power Boot Mode
is used to indicate the charger status. For better flexibility, in BT_LPB[1:0]=01 mode, GPIO_F receives
an indication about charger presence in the system.
If the i.MX25 internal USB PHY has been selected (BT_USB_SRC=0), then the ROM receives a USB
charger indication from the internal USB PHY.
The BT_LPB_FREQ eFUSE settings determine the maximal LPB ARM frequency as shown in
Table 7-19.
Table 7-19. LPB_FREQ eFUSE Settings and Associated LPB ARM Frequencies
LPB_FREQ[2:0]
Frequency (MHz)
000
133 (default)
001
CKIH
010
55.33
011
66
100
83
101
166
110
266
111
Normal boot frequency
ROM code supports all primary boot devices in LPB mode. However the assumption that UART and USB
boot devices will not be used by customers in LPB mode.
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USB Low-Power Boot Mode
The LPB negotiation flowchart is shown in Figure 7-12.
LPB
(Low power
Boot check)
yes
Is BT_LPB[1:0]==0x00?
(LPB Disabled)
no
BT_LPB[1:0]==11
(Is ATLAS AP allowed?)
ATLAS AP LPB
yes
no
If PM IC_INT pin
asserted ‘1'
If GPIO1_C==0
(Low power condition exists
?)
No
yes
yes
BT_LPB[1:0]==10 AND
GPIO1_F==1
(W all adapter/Charger
detected ?)
No
yes
No
Set the IIM _SCS1
register to 0x00
Set the IIM _SCS1
register to 0x03
If((lowpowerboot) &&
(BT_DPLUS ==0))
yes
NO RM AL BO OT
Clock
Boot on LPB freq
Copy Initial 2K From the
boot device
(Unlim ited power budget)
Copy Initial 2K From the
boot device
Initiate an Attach
Event on the USB
interface
No
Copy the rest of the
Im age and continue
with the secure flow
Figure 7-12. USB Low-Power Boot Flow
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High Assurance Boot (HAB)
7.7
High Assurance Boot (HAB)
The boot flow handles all the security aspects, to ensure complete secure boot (based on fuse settings).
This includes handling HAB modes, performing various code checks and initializing the security hardware
secure real time clock (SRTC).
The high assurance boot (HAB) component of the ROM protects against the potential threat of attackers
modifying areas of code or data in programmable memory to make it behave in an incorrect manner. The
HAB also prevents attempts to gain access to features which should not be available. The integration of
the HAB feature with ROM code ensures that i.MX25 does not enter an operational state if the existing
hardware security modules have detected a condition that may be a security compromise, or if areas of
memory deemed to be important have been modified.
Figure 7-13 illustrates the components used during a secure boot. The processor security components are
RTICv3, DryIce and SCCv3. They are supported through the HAB Library. The HAB uses either the
RTICv3 hardware accelerator or its internal software implementation to support the SHA256 message
digest operations that are part of the signature authentication process.
RTICv3
ROM
Core
Processor
HAB
SCCv3, DryIce
Flash
RAM
Figure 7-13. Secure Boot Components
7.7.1
High-Assurance Boot (HAB) Security Types
The HAB requires the location of two components in the boot device: the starting address of the super root
key (SRK) data and the starting address of the command sequence file (CSF) data. Both of these
components are defined in the Flash header as illustrated in Figure 7-5. The SRK defined in the application
data located in the boot device is validated by the HAB. The HAB will perform a SHA-256 hash digest of
the SRK provided in the application data. It will then compare the computed hash with that stored in the
i.MX25 eFUSEs. If validation of the SRK is unsuccessful, the ROM will enter the serial bootloader.
The CSF provides the signature and certificate information of the piece of software to authenticate. The
CSF is generated by using a client/server code signing tool (CST). Contact your Freescale representative
for further information regarding code signing for HAB.
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High Assurance Boot (HAB)
The boot flow is influenced by the device’s HAB TYPE as specified in Table 7-20.
Table 7-20. HAB Security Types
HAB TYPE
HAB_TYPE[2:0] Fuse Value
Action
HAB_ENGINEERING
0x1(0b001) (default)
Initialize secure hardware, execute DCD block and authenticate
applications prior to their execution. Any errors detected are logged,
but have no influence on the boot flow.
HAB_PRODUCT
Any value in range
0b000–0b111 except for
0b001 and 0b100
Initialize secure hardware, execute DCD block and authenticate
applications prior to their execution. Any errors detected are logged
and control passes to the USB/UART Bootloader.
7.7.1.1
HAB_ENGINEERING Security Type
This level is intended for use during the development phases of a product. All HAB functions are executed
as for a production device—security hardware is initialized (except the SCC is left in non-secure state),
the DCD is processed if present, and the software in Flash or downloaded to RAM is authenticated by HAB
prior to its execution. Any errors detected are logged, but have no influence on the boot flow. With this
level it is possible to develop software without requiring that each build be signed for HAB authentication,
since the device will boot even if the code signatures are missing.
7.7.1.2
HAB_PRODUCTION Security Type
This level is intended for use with shipping products. All HAB functions are executed − security hardware
is initialized (the SCC enters Secure state), DCD is processed if present, and software in Flash or
downloaded to RAM is authenticated by HAB prior to its execution. Any errors detected are logged, and
the boot flow is aborted with control passing to the download mode. With this level, execution does not
leave the internal ROM unless the target executable image has been authenticated.
In HAB_PRODUCTION mode, all the ROM errors are logged to the pu_irom_error_status variable (see
Section 7.5, “Error Logging”). The address of pu_irom_error_status is 0x7800_18C0. All the HAB
errors/status can be found in Table 7-21.
Table 7-21. HAB Status Codes
Name
Description
Value
HAB_DATA_OUT_OF_BOUNDS
Data specified is out of bounds.
0x8D
HAB_FAIL_ASSERT
Error during Assert Verification.
0x55
Hash verification failed (including hash verification on certificates).
0x36
Certificate parsing failed, or the certificate contained an unsupported
key (including unsupported key length).
0x33
Signature verification failed (including signature verification on
certificate).
0x35
Super-Root key installation failed.
0x47
Failure not matching any other description.
0x39
CSF Command Sequence contains an unsupported command identifier.
0x4B
HAB_FAIL_HASH_VERIFICATION
HAB_FAIL_PK_VER
HAB_FAIL_SIG_VERIFICATION
HAB_FAIL_SUPER_ROOT_INSTALL
HAB_FAILURE
HAB_INVALID_CSF_COMMAND
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High Assurance Boot (HAB)
Table 7-21. HAB Status Codes (continued)
Name
Description
Value
HAB_INVALID_CSF_HEADER
Absence of expected CSF Header (including mismatched HAB
Version).
0x4E
HAB_INVALID_CSF_LENGTH
CSF length is unsupported.
0x4D
CSF TYPE does not match processor TYPE.
0x2E
CSF UID does not match either processor UID or generic UID.
0x2D
HAB_INVALID_CSF_CODE
CSF customer/product code does not match processor
Customer/Product code.
0x3A
HAB_INVALID_KEY_INDEX
Key index is either unsupported, or an attempt is made to overwrite the
Super-Root key from a CSF command, or an attempt to write a non-CSF
subordinate key to HAB_CSF_KEY_INDEX
0x87
Successful operation completion.
0xF0
SCC unexpectedly not in Secure State.
0x17
HAB_SECURE_RAM_BAD_KEY
Secure RAM secret key invalid.
0x1E
HAB_SECURE_RAM_CLR_FAIL
Secure RAM initialization failure.
0x1D
Secure RAM Self Test failure.
0x1B
SCC unexpectedly not in Non-Secure State
0x53
HAB_SECURE_RAM_INT_ERR
Secure RAM internal failure.
0x2b
HAB_SECURE_RAM_SEC_KEY
Secure RAM secret key unexpectedly in use.
0x27
SAHARA failure.
0x3C
HAB_SAHARA_SCC_FAIL
SAHARA/SCC connectivity failure.
0x59
HAB_RTIC_REGION_FAIL
All RTIC regions are allocated.
0xA3
HAB_RTIC_SCC_FAIL
RTIC/SCC connectivity failure.
0x93
HAB_RNG_SCC_FAIL
RNG/SCC connectivity failure.
0x95
RNG self test failure.
0x99
DryIce Random key test failure
0x9C
HAB_INVALID_CSF_TYPE
HAB_INVALID_CSF_UID
HAB_PASSED
HAB_SCC_NOT_SECURE
HAB_SECURE_RAM_FAIL
HAB_SCC_FAIL
HAB_SAHARA_FAIL
HAB_RNG_SELF_TEST_FAIL
HAB_DRYICE_BAD_RANDOM_KEY
HAB_DRYICE_BAD_PROGRAMMED_KEY DryIce Programmed key test failure
HAB_DRYICE_REG_WRITE_FAIL
HAB_DRYICE_BAD_XOR_KEY
HAB_SHW_DISABLED
HAB_UNINITIALISED_KEY_INDEX
HAB_UNSUPPORTED_ALGORITHM
HAB_INVALID_WRITE_REG
0x9A
DryIce register write fail
0xAA
DryIce XORed key test failure
0xA5
SHW is not enabled.
0x0F
An attempt is made to read a key from the list of subordinate public keys
at a location where no key is installed.
0x8B
Algorithm type is either invalid or otherwise unsupported.
0x8E
Write operation to register failed.
0x66
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High Assurance Boot (HAB)
7.7.2
Function Prototypes
The following three HAB functions are available to application code residing outside of the ROM. These
functions can be considered trustworthy since they are located in ROM and cannot be changed. Note that
the HAB API functions may only be called from external images that have not yet enabled the MMU.
7.7.2.1
pu_irom_boot_decision
Syntax:
void pu_irom_boot_decision(void)
Description:
Entry point for the serial downloader. Performs the check of whether to use UART or USB for the
serial bootloader.
Inputs:
None.
Returned Value:
None.
PreConditions/Assumptions:
GPIO for selecting USB Serial PHY and ULPI PHY is set appropriately.
Post Conditions:
None.
7.7.2.2
hab_csf_check
Syntax:
hab_result hab_csf_check(
UINT8
UINT32
csf_count,
*csf_list);
Description
Performs integrity checks on software in programmable memory as instructed by CSFs.
Inputs:
The number of CSFs to be processed and their locations
Returned Value:
The structure:
typedef struct
{
unsigned char status; /* Status code */
unsigned char type; /* HAB type from Table 7-20 */
} hab_result;
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High Assurance Boot (HAB)
with processor TYPE and one of the following status codes:
• HAB_PASSED if all CSFs are valid and all verifications in all CSFs are satisfied.
• HAB_DATA_OUT_OF_BOUNDS if csf_count is 0, csf_count exceeds maximum length of CSF
chain or csf_list is NULL.
• Appropriate error code for other failures as stated in Table 7-21.
• HAB_FAILURE otherwise.
Pre Condition/Assumptions:
• Verified blocks list and subordinate keys list are initialized. That means the hab_health_check() has
been called prior to invoking hab_csf_check.
• The parameter csf_list points to a list of length csf_count.
Post Conditions:
• The subordinate keys list contains successfully validated subordinate keys.
• The verified blocks list contains the list of successfully verified data blocks, padded at the end of
the list to indicate that no more verified block is available. The list of verified block is verified
using hab_assert_verification.
7.7.2.3
hab_assert_verification
Syntax:
hab_result hab_assert_verification(
UINT8
UINT32
*block_start,
block_length);
Description:
Perform only after a CSF Check. Determines if a block of data lies within the regions of the
pre-authenticated block or the regions verified during CSF Check. If SCC is supported, the state of
the SCC (if enabled and the processor TYPE is not engineering) is also tested to ensure that the
hardware is secure.
Inputs:
Starting address and length (in bytes) of the data block.
Returned Value:
The structure:
typedef struct
{
unsigned char status; /* Status code */
unsigned char type; /* HAB type from Table 7-20 */
} hab_result;
with processor TYPE and one of the following status codes:
— HAB_PASSED if all tests pass,
— HAB_FAIL_ASSERT if block is not pre-authenticated or in regions verified during CSF
Check,
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High Assurance Boot (HAB)
— HAB_SCC_NOT_SECURE if SCC supported and is not in the secure state and processor
TYPE is not engineering,
— HAB_FAILURE otherwise.
Pre Condition/Assumptions:
The verified blocks list contains (start, length) pairs of 32 bit values, padded at the end of the list
to indicate that no more verified block is available. If the given block has been verified or
pre-authenticated, it is assumed to lie wholly within the boundaries of a single block in the verified
blocks list.
Post Conditions:
None.
7.7.3
API Jump Table Addresses
The address of the HAB functions are available using a jump table defined in the ROM. Table 7-22 lists
the functions and the associated jump table address.
Table 7-22. HAB API Jump Table Addresses
HAB API Function
Jump Table Address
hab_csf_check
0x88
hab_assert_verification
0x8C
pu_irom_boot_decision
0x00406968
7.7.4
DryIce Initialization
The DryIce module is initialized by the ROM as part of the HAB library. The DryIce secured registers
cannot be configured by non-secure software. Non-secure software is considered as an application image
executing after a secure boot that is not in supervisor mode and should not be confused with image data or
code verified by HAB.
A dedicated non-secure access (NSA) bit in the DryIce control register can allow unsecured software to
update the DryIce secured registers. This bit can only be set by secured software. In any case DryIce,
secured registers like DryIce key select, random key, programmed key, timer counter and monotonic
counter registers cannot be configured once the corresponding lock bits are set in DryIce control register.
The initialization steps performed by HAB as part of boot ROM depends on HAB_TYPE and DryIce state.
No DryIce programming is performed by the HAB when the HAB_TYPE is Engineering or Security
disabled.
For more information on the DryIce module, see your Freescale representative.
7.7.4.1
HAB Support for DryIce in Valid/Non-Valid State
Prior to exiting from the ROM, the HAB ensures that the DryIce is configured appropriately for the given
DryIce state.
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Serial Download protocol
For secure applications HAB enables an image to configure the DryIce register settings. When the HAB
command sequence file included in the application includes the following WRITE_TO_REGISTER
(WTR) command:
WRITE_TO_REGISTER <DryIce General Purpose Reg (GPR)> 4 0xCA69_3569
Then HAB will refrain from setting any of the lock bits in DryIce. However, if the CSF does not include
this specific WTR command, then the HAB does not allow DryIce to be configured by setting lock bits in
the DryIce control register prior to leaving the boot ROM.
Note that when using the above WTR command to leave the DryIce unlocked, it is recommended that this
be the first command in the CSF.
7.7.4.1.1
Normal Boot Support
For a normal application, the HAB always sets the soft lock bits for the timer and monotonic counter in
the DryIce control register. The HAB also sets other soft lock bits based on the value of the secure key
select (SKS) bit in the DryIce key select register.
• If SKS is set to random key or random key XORed with IIM key, the HAB sets the soft lock bits
for key select and random key.
• If SKS is set to programmed key or programmed key XORed with IIM key, the HAB sets the soft
lock bits for key select, programmed key read and programmed key write.
• If the above two conditions are not met, the default SKS is the IIM key. In this case, the HAB sets
the soft lock bit for key select.
7.7.4.1.2
External Boot Support
Direct (non-secure) boot modes (for example, direct NAND Flash boot) require the boot ROM to be
executed first. If the DryIce module is in the Valid/Non-Valid state, the HAB sets the SWR bit in the DryIce
control register which performs a POR on the DryIce. During the POR, the DryIce state is changed to the
FAIL state.
7.7.4.2
HAB Support for DryIce in Fail State
When DryIce is in the FAIL state, no specific DryIce Programming is performed by HAB.
7.8
Serial Download protocol
This section describes the serial download protocol used for all boot devices in the serial bootloader on
i.MX25.
Each stage in the protocol begins with a command issued by the host to the device, followed by a response
from the device to the host. For most commands, that completes the protocol stage. The exception is the
Write File command, which has an additional data stream sent from the host to the device after the
response. The protocol is terminated by the host issuing a Write File command with application file type.
After processing the Write File commands, the device interprets the next command as a Completed
command, and resumes execution of the boot flow in order to authenticate the downloaded application (if
required) and then execute it.
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Serial Download protocol
7.8.1
Get Status
The Get Status command retrieves the error log stored during a failed boot (or the success code when the
serial bootloader is selected deliberately).
Table 7-23. Get Status Command
Command
0x05
0x05
–
–
–
Response
SC
SC
SC
SC
SC
–
–
–
–
–
–
The fields have the following interpretation:
• SC = Status Code. Four copies of the status code are sent.
• – = Don’t Care (but must be present)
7.8.2
Read Memory
The Read Memory command reads a stream of bytes, half-words or words of data starting from a given
address in memory. At production-level security, this command is ignored.
Table 7-24. Read Memory Command
Command
0x01
0x01
Response
(failure)
ACK[3:0]
Response
(success)
ACK[3:0]
A[3:0]
DS
C[3:0]
–
–
–
–
–
Data stream starting from lowest address
The fields have the following interpretation:
• A[3:0] = Target address (most-significant byte first).
• DS = Data Size (0x08 = byte, 0x10 = half-word, 0x20 = word). Unsupported DS values result in
the failure response.
• C[3:0] = Number of data elements (bytes, half-words or words as appropriate) in data stream
(most-significant byte first).
• ACK[3:0] = 0x56, 0x78, 0x78, 0x56.
• – = Don’t Care (but must be present)
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Serial Download protocol
7.8.3
Write Memory
The Write Memory command reads a byte, half-word, or word of data to a given address.
Table 7-25. Write Memory Command
0x02
A[3:0]
Response
(failure)
ACK[3:0]
0x12
Response
(success)
ACK[3:0]
Command
0x02
0x8A
DS
–
0x8A
0x12
–
–
–
D[3:0]
–
The fields have the following interpretation:
• A[3:0] = Target address (most-significant byte first).
• DS = Data Size (0x08 = byte, 0x10 = half-word, 0x20 = word). Unsupported DS values result in
the failure response.
• D[3:0] = Data to write (most-significant byte first). For DS = 0x08, only D[0] is used. For DS =
0x10, only D[1:0] is used.
• ACK[3:0] = 0x12, 0x34, 0x34, 0x12 for production-level security, and 0x56, 0x78, 0x78, 0x56
otherwise.
• – = Don’t Care (but must be present)
At production-level security, the address ranges that may be written are restricted to those listed for DCD.
Attempts to write outside of the valid ranges are ignored and result in the failure response. For other
security levels, no restrictions apply to the target address.
7.8.4
Re-enumerate
The re-enumerate command resets the USB connection with an updated descriptor.
Table 7-26. Re-Enumerate Command
Command
0x09
0x09
–
–
Response
0x89
0x23
0x23
0x89
–
–
–
–
–
SN[3:0]
–
The fields have the following interpretation:
• SN[3:0] = Serial number for enumeration descriptor.
• – = Don’t Care (but must be present)
7.8.5
Write File
The Write File command writes a stream of bytes to a given address in memory. The byte stream may be
assigned a file type in order to distinguish CSF, DCD and application files. An application file type leads
to the termination the serial download protocol, with the next command (whatever the command byte
values) being treated as the Completed command.
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Serial Download protocol
Table 7-27. Write File Command
Command
0x04
A[3:0]
–
Q[3:0]
–
–
–
–
FT
ACK[3:0]
Response
Data
0x04
Byte stream with data for lowest address first
The fields have the following interpretation:
• A[3:0] = Target address (most-significant byte first).
• C[3:0] = Number of bytes in data stream (most-significant byte first).
• FT= File Type (0xAA = application (terminates protocol), 0xCC = CSF, 0xEE = DCD). With
unrecognized FT values, the file is still downloaded, but the pointers to the three essential files are
not modified.
• ACK[3:0] = 0x12, 0x34, 0x34, 0x12 for production-level security, and 0x56, 0x78, 0x78, 0x56
otherwise.
• – = Don’t Care (but must be present)
• At production-level security, the address ranges which may be written are restricted to those listed
for DCD. Attempts to write outside of the valid ranges are ignored and result in the failure
response. For other security levels, no restrictions apply to the target address.
• In case of application file type, the Flash header should still be provided. It must be located with a
0x0 offset, meaning right before the application code that will be authenticated (if secure boot), and
executed.
7.8.6
Completed
The Completed command is required after the Write File command with application file type (0xAA) in
order to terminate the protocol. The content of the command is irrelevant, but a command must be sent.
This command triggers authentication and DCD processing (if required) followed by execution of the
application. At production-level security, if application authentication fails, the serial download protocol
resumes, with the status code for authentication failure available through the Get Status command.
Table 7-28. Completed Command
Command
–
–
–
–
Response
0x88
0x88
0x88
0x88
–
–
–
–
–
–
–
The fields have the following interpretation:
• – = Don’t Care (but must be present)
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Flash Code Image Detection
7.9
Flash Code Image Detection
7.9.1
Overview
If the HAB security type is set as HAB_ENGINEERING then any code to be flashed and executed, even
if it has no valid signature.
In the production process, there are two ways to flash an image into Flash memory:
• Flash the memory IC before it is installed on the PCB
• Use the i.MX25 ROM’s serial downloader library.
In production, the serial downloader mode can not be entered using boot contact configuration. Instead,
the following code-flashing functionality is provided:
1. The ROM boot code first checks a known fixed Flash address for a Barker code.
2. If the Barker code is missing, the boot assumes an empty Flash and calls the serial downloader
routine.
7.9.2
Impact of Flash Code Image Detection
Flash code image detection has no impact on customers that are using secure parts, since they already have
to restructure the Flash image map to accommodate the HAB signature.
Customers that are not using security and do not want to use the external boot option are responsible to
ensure that the predefined address in Flash contains a Barker code.
7.10
Boot Image Redundancy on NAND Devices
Table 7-29 shows the address/command scheme implemented by the i.MX25 for accessing various types
of NAND devices. When using the redundancy feature, the image code is limited to a size of one block.
Table 7-29. NAND Device Accesses
Device
Number of Page
address
Per
cycles
Block
Address
Notes
Command
Command
#1
#2
#3
#4
1/2-Kbyte
page,
SLC/MLC
4
32
5 LSB bits of Row1 give
offset in block & 13
remaining bits choose
block number
0x00
Col1
Row1 Row2 Row3
2KB SLC
5
62
6 LSB bits of Row1 give
offset in block & 11
remaining bits choose
block number
0x00
Col1
Col2
#5
None
None
Row1 Row2 Row3
0x30
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Boot Image Redundancy on NAND Devices
Table 7-29. NAND Device Accesses (continued)
Device
Number of Page
address
Per
cycles
Block
Address
Notes
Command
Command
#1
#2
#3
#4
#5
2KB MLC
4
128
7 LSB bits of Row1 give
offset in block & 9
remaining bits choose
block number
0x00
Col1
Col2
Row1 Row2
None
0x30
4KB
SLC/MLC
5
128
7 LSB bits of Row1 give
offset in block & 12
remaining bits choose
block number
0x00
Col1
Col2
Row1 Row2 Row3
0x30
Table 7-30 below provides details on block addressing:
Table 7-30. NAND Device Addressing
Device
Page Copying for
8 KByte Block
Address Cycles
0.5-Kbyte Page SLC/MLC
Page 1
0x00,0x00,0x00,0x00
Page 2
0x00,0x01,0x00,0x00
Page 3
0x00,0x02,0x00,0x00
Page 4
0x00,0x03,0x00,0x00
Page 5
0x00,0x04,0x00,0x00
Page 6
0x00,0x05,0x00,0x00
Page 7
0x00.0x06,0x00,0x00
Page 8
0x00,0x07,0x00,0x00
Next Block Accesses (upon Error)
Page 1
0x00,0x20,0x00,0x00
Page 2
0x00,0x21,0x00,0x00
Page 3
0x00,0x22,0x00,0x00
Page 4
0x00,0x23,0x00,0x00
Page 5
0x00,0x24,0x00,0x00
Page 6
0x00,0x25,0x00,0x00
Page 7
0x00.0x26,0x00,0x00
Page 8
0x00,0x27,0x00,0x00
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Booting From a NAND Device
Table 7-30. NAND Device Addressing (continued)
Device
2-Kbyte Page SLC
Page Copying for
8 KByte Block
Address Cycles
Page 1
0x00,0x00,0x00,0x00,0x00
Page 2
0x00,0x00,0x01,0x00,0x00
Next Block Accesses (upon Error)
2-Kbyte Page MLC
Page 1
0x00,0x00,0x40,0x00,0x00
Page 2
0x00,0x00,0x41,0x00,0x00
Page 1
—
Page 2
—
Next Block Accesses (upon Error)
4-Kbyte Page SLC/MLC
Page 1
—
Page 2
—
Page 1
0x00,0x00,0x00,0x00,0x00
Next Block Accesses (Upon Error)
Page 1
7.11
7.11.1
0x00,0x00,0x80,0x00,0x00
Booting From a NAND Device
Overview
This section explains the eFUSE settings required for booting from a NAND device. The Boot ROM
copies only the Initial Program Loader (IPL), authenticates the IPL and jumps to execute the IPL. The IPL
is a small program responsible for downloading and executing the rest of the program image. Also a brief
description is given on the various components of the IPL (Initial Program Loader).
Download and
Jump
BOOT ROM
INITIAL PROGRAM
LOADER
(IPL)
Figure 7-14. ROM Copies The IPL And Jump To Execute It
The various components that needs to be present in the IPL is dependent on the HAB_TYPE[2:0] fuse
values. Figure 7-15 below shows the typical example about the IPL image layout.
• DCD DATA: Device configuration data.This block consist of the barker value (0xB17219E9),
length of the DCD, and the access-type address-value triplets.
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Booting From a NAND Device
•
•
•
•
•
External Flash Header: The Length of the IPL has to be present in this field. It is expected to be
present at the location where DCD data ends.
APPLN: Customer application Code.
Flash Header: This Block Contains the Information about the IPL.This is expected to be present at
a fixed offset. For NAND, this is at 0x400 byte offset from the base address.
CSF DATA: Certificate and Command sequence file data
SRK DATA: Super Root key data.
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Booting From a NAND Device
The required IPL fields depend on the HAB_TYPE[2:0] fuse values. Figure 7-15 shows a typical layout
for the IPL image.
NAND
FLASH
DESTINATION
MEMORY
Flash base
0x000
0x80000000
0x80000100
DCD DATA
External flash header
DCD DATA
External flash header
APPLN
APPLN
0x80000300
Flash header
0x400
0x80000400
FLASH HEADER
FLASH HEADER
0x80000500
CSF DATA
CSF DATA
0x80004F00
SRK DATA
SRK DATA
app_start_addr
app_barker
csf_ptr
dcd_ptr_ptr
srk_ptr
dcd_ptr
app_dest_ptr
Flash header
structure
Figure 7-15. IPL Component Layout in Flash and Destination Memory
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Booting From a NAND Device
Table 7-31 shows the significance of the fields shown in Figure 7-15.
Table 7-31. IPL Fields
Field Name
Significance
DCD DATA
Device configuration data.This block consist of the Barker value (0xB172_19E9), length of the DCD, then the
access type- address -value triplets.
External flash The length of the IPL must be present in this field, at the location where DCD data ends.
header
APPLN
FLASH
HEADER
Customer application code
This block contains the information about the IPL.This is expected to be present at a fixed offset from the base
address. For NAND the offset is 0x400, measured in bytes.
CSF DATA
Certificate and command sequence file (CSF) data
SRK DATA
Super Root key data
The IPL should consist of the following components for various HAB TYPE values:
• HAB TYPE = HAB_ENGEERING (0b001)
— FLASH HEADER
— APPLN
— CSF DATA—not mandatory
— SRK DATA—not mandatory
— DCD DATA—not mandatory
• Case 2: HAB TYPE = HAB_PRODUCTION (Any value from 0b000–0b111 other than 0b001 or
0b100)
— FLASH HEADER
— APPLN
— CSF DATA
— SRK DATA
— DCD DATA—not mandatory
• Case 3: HAB TYPE = HAB_SEC_DISABLED (0b100)
— FLASH HEADER
— APPLN
Table 7-32 shows eFUSE settings required for SLC NAND Flash (page size 512 bytes, bus width 8 bits, 3
address cycles, spare area 128 bytes).
Table 7-32. eFUSE Settings for SLC NAND Flash Boot
Field Name
Setting
BT_MEM_CTL[1:0]
01
BT_MEM_TYPE[1:0]
00
BT_BUS_WIDTH[1:0]
00
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Table 7-32. eFUSE Settings for SLC NAND Flash Boot (continued)
Field Name
Setting
BT_PAGE_SIZE[1:0]
00
BT_MLC_SEL
0
BT_SPARE_SIZE
0
In addition to the settings shown in Table 7-32, the HAB TYPE[2:0] eFUSEs and BOOT_MODE contacts
must be set according to the intended case.
For internal boot mode operation, the IPL for NAND must have the Flash header placed at an offset of
0x400 from the base address.
7.11.2
7.11.2.1
Flash Header Details
HAB_ENGEERING Mode
In internal boot mode with HAB security type HAB_ENGINEERING (BOOT_MODE[1:0] = 00 and
HAB TYPE[2:0] = 010), the Flash header needs to have a proper app_start_addr, app_barker
(0x0000_00B1), dcd_ptr_ptr, dcd_ptr, or app_dest_ptr. The other pointers in the Flash header can be
NULL.
The dcd_ptr_ptr must point to the dcd_ptr in the Flash header structure, which in turn points to the DCD
data. The dcd_ptr_ptr field must be set to the FLASH_HEADER start address + 0x14; for example, if the
Flash header starts at 0x1000_2400, then the dcd_ptr_ptr setting must be 0x1000_2414).
The ROM copies the initial 4 Kbytes of data from the Flash to the NFC buffer, installs the DCD data, then
copies the initial 4 Kbytes of data from the NFC buffer to the destination address pointed to by the
app_dest_ptr. In the IPL, the IPL length field is expected at the end of the DCD table. The ROM uses this
field to copy the rest of the image from the NAND device to the destination RAM indicated by
app_dest_ptr. If the app_dest_ptr is an internal RAM address, then no DCD needs to be installed. In this
case, the DCD data can contain only the DCD Barker field and the DCD block length field, whose value
is equal to zero.
The format of the srk_ptr can be found from the Flash header section of the System boot chapter.
A typical Flash header structure for Engineering mode is shown in the following example code:
struct flash_hdr {
UINT32 app_start_addr;
UINT32 app_barker;
UINT32 csf_ptr;
UINT32 dcd_ptr_ptr;
const hab_rsa_public_key *srk_ptr;
UINT32 dcd_ptr;
UINT32 app_dest_ptr;
}const start_app = {0x80000300, 0x000000B1, 0x00, (0x80000400+0x14), 0x00,
0x80000100,0x80000000};
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7.11.2.2
HAB_PRODUCTION Mode
In internal boot mode with HAB security type HAB_PRODUCTION (BOOT_MODE[1:0] = 00 and HAB
TYPE[2:0] any value except 0b001 and 0b100),then all Flash header fields must be properly filled. The
ROM copies the initial 4 Kbytes data from the Flash to the NFC buffer, installs the DCD data, then copies
the initial 4 Kbytes data from the NFC buffer to the destination address indicated by app_dest_ptr.
In the IPL, the IPL length is expected by the ROM code at the end of the DCD table. The ROM uses this
field to copy the rest of the image from the NAND device to the RAM destination indicated by
app_dest_ptr. Then, the Security check is performed on the downloaded code.
The following regions in the IPL must be signed:
• Flash Header
• Application Code
• DCD data.
These regions must be included in the CSF certificate during the signing.
The SRK hash values must be blown onto the Fuses SRK_HASH[255:0].
The SCC key values must be blown onto the fuses SCC_KEY[0:163]. If unblown, then the SCC will move
to an insecure state, and the production test case fails.
The Unique ID UID[0:63] and Customer Code HAB_CUS[7:0] fuses also must be blown to appropriate
values that match with those included in the CSF file.
A typical Flash header structure for HAB_PRODUCTION mode is shown in the following code example:
struct flash_hdr {
UINT32 app_start_addr;
UINT32 app_barker;
UINT32 csf_ptr;
UINT32 dcd_ptr_ptr;
const hab_rsa_public_key *srk_ptr;
UINT32 dcd_ptr;
UINT32 app_dest_ptr;
}const start_app = {0x80000300, 0x000000B1, 0x80000500, (0x80000400+0x14)), 0x80004F00,
0x80000100,0x80000000};
7.11.2.3
HAB_SEC_DISABLED Mode
In internal boot mode with HAB security disabled (BOOT_MODE[1:0] = 00 and
HAB_TYPE[2:0] = 100), then the Flash header only requires the app_start_addr and the app_barker fields
(app_barker has value 0x0000_00B1). The ROM code first copies the initial 4 Kbytes of data to the NFC
buffer, checks the Barker value, then jumps to app_start_addr.
A typical flash header is as follows:
struct flash_hdr {
UINT32 app_start_addr;
UINT32 app_barker;
UINT32 csf_ptr;
UINT32 dcd_ptr_ptr;
const hab_rsa_public_key *srk_ptr;
UINT32 dcd_ptr;
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Booting From a NAND Device
UINT32 app_dest_ptr;
}const start_app = {0xBB000000, 0x000000B1, 0x0, 0x0, 0x0, 0x0,0xBB000000};
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Chapter 8
Power Management
This chapter describes the power savings methodology, power supply requirements, and power-up and
power-down sequences for the device.
8.1
Power Domains
Power management for the device is organized into the following power domains:
• Digital logic domain. This includes the core logic domain and I/O domain.
• Analog domain, including the OSC24M, PLLs, USBPHY, fusebox, and touch-screen controller
(TSC).
8.1.1
Power-Supply Requirements
See the device datasheet’s “DC Operating Characteristics” for power supply requirements.
8.2
Power Saving Methodology
The clock-control module (CCM) supports several power management techniques to reduce active and
static power consumption, as follows:
• Active power savings, including clock gating, software controlled dynamic voltage and frequency
scaling (DVFS), dynamic process and temperature compensation (DPTC).
• Leakage power savings, including active well bias (AWB)
• Low-power modes, including wait, doze, stop, and sleep modes
8.2.1
Active Power Savings
Active power savings features include the following:
• Dynamic voltage and frequency scaling (DVFS) allows dynamic software control of voltage and
frequency scaling. The core clock domain frequency and chip voltage can be changed on-the-fly
while all modules (including the core) continue normal operation.
• Dynamic process and temperature compensation (DPTC) enables part-specific voltage reduction
in the digital domain. Voltage reduction for each part is determined by device characteristics that
vary due to manufacturing process variations and temperature.
• Two levels of clock gating of idle modules:
— Clock tree roots, as implemented in the clock controller module (CCM)
— Clock tree leaf nodes, as implemented in the modules themselves
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Power Management
8.2.2
Leakage Power Saving
Active well bias (AWB) is used to control leakage in low-power modes. See the section on well bias
support in the CCM chapter.
8.2.3
Power Modes
Table 8-1 shows the device’s power modes.
Table 8-1. Power Modes
Power Mode
Conditions
Run
•
•
•
•
Wait
• ARM core is in wait-for-interrupt mode (clock off)
• Well bias is off
• Core PLL is on
• USB PLL is off (optional)
• OSC24M is on
• OSC32K is on
• All other modules are off (optional)
Note: Turning off the USB PLL and other modules makes the device use less power.
Doze
• ARM platform clock is off
• Well bias is on
• Core PLL is on
• USB PLL is off (optional)
• OSC24M is on
• OSC32K is on
• All the other modules are off (optional)
Note: Turning off the USB PLL and other modules makes the device use less power.
Stop
•
•
•
•
•
All PLLs are off
Well bias is on
OSC24M is off
OSC32K is on
All the other modules are off
Sleep
•
•
•
•
•
•
All PLLs are off
Well bias is on
OSC24M is off
OSC32K is on
All the other modules are off
Core voltage is reduced to 1 V
8.2.3.1
ARM core and platform are active
Well bias is off
Clocks are on
Modules are active
SDRAM Operation in Low Power Modes
When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in distributed-refresh
mode or in self-refresh mode. The SDRAM wake-up latency is approximately 20 system clock cycles
(HCLK). The SDRAMC can send a command to wake up the SDRAM from self-refresh mode in an
SDRAM cycle and SDRAMC cannot access the SDRAM in at least the following two cycles or more,
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Power Management
based on the device type. (based on device type, see the low power mode table in the SDRAMC block
guide.)
In wait, doze, and run modes, the power-down timers within the SDRAMC can be enabled to cause the
SDRAM to enter power-down mode if no activity is detected. The SDRAMC still controls the refresh, and
when necessary temporarily takes the SDRAM out of power-down mode to perform a refresh. In
power-down mode, the clock to the SDRAM is gated off and the CKE pin (SDRAM device input) goes
low.
When the system enters sleep mode, the SDRAM enters self-refresh mode. Self-refresh mode is exited
when the chip exits sleep mode and re-enables the CCM MPLL enable bit (MPEN).
8.3
Power-Up and Power-Down Sequence
Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in
this section to ensure reliable operation of the device. Recommended power-up and power-down
sequences are given in the following subsections.
CAUTION
Deviations from the guidelines in this section may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the i.MX25 (worst-case scenario)
NOTE
For security applications, the coin battery must be connected during both power-up and power-down
sequences to ensure that security keys are not unintentionally erased.
8.3.1
Power-Up Sequence
The following power-up sequence is recommended:
1. Assert power on reset (POR).
2. Turn on digital logic domain and I/O power supplies VDDn and NVCCx.
3. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,
USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD,
MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses
are not being programmed). The minimum time between turning on each power supply is the time
it takes for the previous supply to be stable.
4. Negate the POR signal.
•
NOTE
The user is advised to connect FUSEVDD to GND except when fuses
are being programmed, in order to prevent unintentional blowing of
fuses.
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Power Management
•
•
Other power-up sequences may be possible; however, the above
sequence has been verified and is recommended.
There is a 1-ms minimum time between supplies coming up, and a 1-ms
minimum time between POR_B assert and deassert.
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Chapter 9
1-Wire Module (1-Wire)
9.1
Overview
The 1-Wire module provides the communication link to a generic 1-Kbit add-only memory. The module
sends or receives one bit at a time with an option for software to manage the data using bytes. The required
protocol for accessing the generic 1-Wire device is defined by Maxim-Dallas. The generic 1-Wire device
holds battery characteristics information.
Figure 9-1 shows a block diagram of the 1-Wire module.
to Host
Peripheral Bus
to Registers
Interrupt Generation
(for byte and SRA transfers only)
Interrupt
1-Wire Bus Protocol Functions
Reset/Presence-Detect
Bit Transfers
OWIRE_LINE
Clock Divider
Main Clock
Byte Transfers
Time Base
(1 MHz)
Search ROM Accelerator (SRA)
Figure 9-1. 1-Wire Module Block Diagram
9.1.1
Features
The 1-Wire module includes the following features:
• Performs the 1-Wire bus protocol to communicate with an external 1-Wire device.
• Provides a clock divider to a generate a 1-Wire bus reference clock (derived from the main clock
provided internally to the module).
• Supports byte transfers with optional interrupts for more efficient programming.
• Provides search ROM accelerator mode to speed the search ROM protocol.
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9.1.2
Modes of Operation
The 1-Wire module supports the following operations:
• Normal Operating Modes (See on page 9-8.)
— Bit or Byte Transfers
— Reset/Presence-detect Pulse
— Search ROM Accelerator Mode
• Low Power Mode (See on page 9-11.)
9.2
External Signals
Table 9-1 shows the signal that interfaces with a generic 1-Wire device.
Table 9-1. 1-Wire Module Signal
Signal
I/O
OWIRE_LI I/O
NE
9.3
Function
1-Wire bus
Requires an external pull-up resistor. The recommended resistor value is specified by the generic 1-Wire
device used in a given system.
Memory Map and Register Definition
This section provides the module memory map and detailed descriptions of all registers.
9.3.1
Memory Map
Table 9-2 shows the 1-Wire memory map.
Table 9-2. 1-Wire Memory Map
Base Address Offset
Register
Access
Reset Value
Section/Page
0x0000 (CONTROL)
Control register
R/W
0x0000
9.3.2.1/9-3
0x0002 (TIME_DIVIDER)
Time Divider register
R/W
0x0000
9.3.2.2/9-4
0x0004 (RESET)
Reset register
R/W
0x0000
9.3.2.3/9-4
0x0006 (COMMAND)
Command Register
R/W
0x0000
9.3.2.4/9-5
0x0008 (TX/RX)
Transmit/Receive Register
R/W
0x0000
9.3.2.5/9-5
0x000A (INTERRUPT)
Interrupt Register
R
0x000E
9.3.2.6/9-6
0x000C (INTERRUPT_EN)
Interrupt Enable Register
R/W
0x0000
9.3.2.7/9-7
9.3.2
Register Descriptions
This section provides the detailed descriptions for the registers. All registers are byte-addressable.
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9.3.2.1
Control Register (CONTROL)
The control register is used to initiate the reset/presence-detect sequence and bit transfers. The register also
provides the presence-detect status and bit-read status.
Figure 9-2 shows the register. Table 9-3 describes the register fields.
Offset 0x0000 (CONTROL)
R
Access: User read/write
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
WR0
WR1
0
0
PST
RPP
3
2
1
0
RDST
0
0
0
0
0
0
0
W
RESET
0
0
0
0
0
0
0
0
0
0
Figure 9-2. Control Register
Table 9-3. Control Register Field Descriptions
Field
Description
15–8
Reserved
7
RPP
Reset/Presence-detect Pulse. This bit is self-clearing and is cleared after the presence or absence of an
external device is determined. See Section 9.4.1.1, “Reset/Presence-Detect Pulse.”
When writing:
0 Do nothing.
1 Generate Reset Pulse and sample the bus for the presence pulse from the external device.
When reading:
0 Reset pulse complete.
1 Sequence not complete.
6
PST
Presence Status. This bit is valid after the RPP bit is self-cleared.
0 Device is not present.
1 Device is present.
5
WR0
Write 0. This bit is self-clearing and is cleared when the write of the bit is complete. See Section 9.4.1.2.1,
“Write-0 Sequence.”
When writing:
0 Do nothing.
1 Write a 0 bit to the interface.
When reading:
0 Write sequence complete.
1 Sequence not complete.
4
WR1
Write 1 / Read. This bit is self-clearing and is cleared when the write sequence is complete. See
Section 9.4.1.2.2, “Write-1/Read Sequence.”
When writing:
0 Do nothing
1 Write a 1 bit to the interface and sample the bus.
When reading:
0 Sequence complete.
1 Sequence not complete.
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Table 9-3. Control Register Field Descriptions (Continued)
Field
3
RDST
2–0
9.3.2.2
Description
Read Status. This bit is valid after the WR1 bit is self cleared.
0 A 0 has been sampled.
1 A 1 has been sampled.
Reserved
Time Divider Register (TIME_DIVIDER)
The time divider register is used for dividing the main clock (ipg_clk) input down to 1 MHz to generate
the module’s time base.
Figure 9-3 shows the register. Table 9-4 describes the register fields.
Offset 0x0002 (TIME_DIVIDER)
R
Access: User read/write
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
DVDR
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-3. Time Divider Register
Table 9-4. Time Divider Register Field Descriptions
Field
Description
15–8
Reserved
7–0
DVDR
Divider Factor. The internal clock divider uses this field to generate the required time base for the module.
See Section 9.4.3, “Clocks.”
0x00 1 (default)
0x01 2
----0xFF 256
9.3.2.3
Reset Register (RESET)
The reset register is used to perform a software reset of the 1-Wire module. Figure 9-4 shows the register.
Table 9-5 describes the register fields.
Offset 0x0004 (RESET)
R
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RST
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-4. Reset Register
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Table 9-5. Reset Register Field Descriptions
Field
Description
15–1
Reserved
0
RST
Software Reset. See Section 9.4.4.2, “Software Reset.”
0 Do not perform a software reset.
1 Initiate a software reset and hold the module in the software-reset state.
9.3.2.4
Command Register (COMMAND)
The 1-Wire module can be configured to run in Search ROM Accelerator mode using the command
register. See Section 9.4.1.4, “Search ROM Accelerator Mode.”
Figure 9-5 shows the register. Table 9-6 describes the register fields.
Offset 0x0006 (COMMAND)
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
1
0
0
SRA
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-5. Command Register
Table 9-6. Command Register Field Descriptions
Field
Description
15–2
Reserved
1
SRA
Search ROM Accelerator. This bit is cleared when the reset-presence-pulse bit CONTROL[RPP] is set.
0 Deactivate the search ROM accelerator.
1 Switch to search ROM accelerator mode.
0
Reserved
9.3.2.5
Transmit/Receive Register (TX/RX)
Data sent and received from the 1-Wire module passes through the Transmit/Receive (TX/RX) register
location. The 1-Wire module is double-buffered with separate transmit and receive buffers connected to
the TX/RX register. See Section 9.4.1.3, “Byte Transfers.”
Figure 9-6 shows the register. Table 9-7 describes the register fields.
Offset 0x0008 (TX/RX)
R
Access: User read/write
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
DATA
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-6. Transmit/Receive Register
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Table 9-7. Transmit/Receive Register Field Descriptions
Field
Description
15–8
Reserved
7-0
DATA
Data byte.
When writing:
The data byte is written to the Transmit buffer.
When reading:
A data byte is read from the Receive buffer. The data is valid only when INTERRUPT[RBF] is set.
9.3.2.6
Interrupt Register (INTERRUPT)
Flags for the reset/presence-detect sequence and byte transfer operations are located in the Interrupt
Register. These flags can generate an interrupt if the corresponding enable bit is set in the Interrupt Enable
Register.
If interrupts are enabled, reading the Interrupt Register clears the interrupt even if all the current flags are
not cleared; the interrupt service routine should clear all pending flags during each routine call.
NOTE
When a byte is written to the Transmit/Receive Register, software then waits
for a Transmit Shift Register Empty (TSRE) interrupt to occur. When the
TSRE flag is set, the Receive Buffer Full (RBF) flag is also set. The RBF
flag does not trigger an interrupt, assuming it is disabled. However, software
should read the Transmit/Receive Register to clear the RBF flag in order to
give a proper status of the pending interrupts.
Figure 9-7 shows the register. Table 9-8 describes the register fields.
Offset 0x000A (INTERRUPT)
R
Access: User read
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
RSRF RBF TSRE TBE
1
0
PDR
PD
1
0
W
RESET
0
0
1
1
Figure 9-7. Interrupt Register
Table 9-8. Interrupt Register Field Descriptions
Field
Description
15–6
Reserved
5
RSRF
Receive shift register full. Hardware automatically clears this flag when data in the receive shift register
is transferred to the receive buffer.
0 The receive shift register is empty or currently receiving data.
1 A byte is waiting in the receive shift register to be transferred to the receive buffer.
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Table 9-8. Interrupt Register Field Descriptions (Continued)
Field
Description
4
RBF
Receive Buffer Full. This flag is cleared when software reads the byte from the TX/RX register. This flag
prevents new data from being shifted into the receive buffer from the receive shift register.
0 No new data
1 A byte is waiting to be read from the TX/RX register.
3
TSRE
Transmit Shift Register Empty. Hardware automatically clears this flag when data in the transmit buffer is
transferred to the transmit shift register.
0 Sending data
1 The transmit shift register is empty and is ready to receive the next byte from the Transmit buffer.
2
TBE
Transmit Buffer Empty. This flag is cleared when software writes a byte to the TX/RX register.
0 The Transmit buffer is currently sending data to the transmit shift register.
1 Nothing to transmit
1
PDR
Presence Detect Result. When a presence-detect (PD) interrupt occurs, this bit reflects the result of the
presence-detect sequence. Note that this bit does not generate an interrupt.
0 Device found
1 Device not found
0
PD
Presence Detect. After an 1-Wire reset has been issued, this flag is set after the appropriate amount of
time for a presence detect pulse to have occurred.
This flag is cleared when software reads the interrupt register.
0 A reset/presence-detect sequence has not been issued.
1 Reset/presence-detect sequence has completed. The result is provided in the PDR bit.
9.3.2.7
Interrupt Enable Register (INTERRUPT_EN)
The Interrupt Enable Register allows the system programmer to specify the source of interrupts. During a
reset (hardware or software), all bits in this register are cleared, disabling all interrupt sources.
Figure 9-8 shows the register. Table 9-9 describes the register fields.
Offset 0x000C (INTERRUPT_EN)
R
Access: User read/write
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
5
4
3
2
ERSF ERBF ETSE ETBE
1
0
IAS
EPD
0
0
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-8. Interrupt Enable Register
Table 9-9. Interrupt Enable Register Field Descriptions
Field
Description
15–6
Reserved
5
ERSF
Enable receive shift register full interrupt.
0 Disable interrupt.
1 Enable interrupt.
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Table 9-9. Interrupt Enable Register Field Descriptions (Continued)
Field
9.4
Description
4
ERBF
Enable Receive Buffer Full Interrupt.
0 Disable interrupt.
1 Enable interrupt.
3
ETSE
Enable Transmit Shift Register Empty Interrupt.
0 Disable interrupt.
1 Enable interrupt.
2
ETBE
Enable Transmit Buffer Empty Interrupt.
0 Disable interrupt.
1 Enable interrupt.
1
IAS
Interrupt Trigger Active State. This bit determines the polarity for all interrupts. Note that this bit is not an
interrupt-enable bit.
0 Active high interrupt
1 Active low interrupt
0
EPD
Enable Presence Detect.
0 Disable interrupt.
1 Enable interrupt.
Functional Description
The 1-Wire module interfaces with a generic 1-Kbit add-only memory, through a simple 1-bit bus.
Software uses the 1-Wire bus to program and read the 1-Kbyte memory.
The protocol involves first issuing one of four ROM function commands before the EPROM is accessible:
• Read ROM
• Match ROM
• Search ROM
• Skip ROM
Through the 1-Wire bus, the host software interfaces with the generic 1-Wire device and allows the
required commands to be issued to control the EPROM of a generic 1-Wire device. The host (through the
1-Wire interface) is the bus master, and the generic 1-Wire device(s) are the slave(s)
9.4.1
Normal Operating Modes
The 1-Wire module supports the following 1-Wire bus protocol functions:
• Reset/Presence-detect pulse using the control register (See Section 9.4.1.1,
“Reset/Presence-Detect Pulse”)
• Bit Transfers using the control register (See Section 9.4.1.2, “Bit Transfers”)
• Byte Transfers using the TX/RX register (See Section 9.4.1.3, “Byte Transfers”)
• Search ROM Accelerator Mode using the Command register and the TX/RX register (See
Section 9.4.1.4, “Search ROM Accelerator Mode”)
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9.4.1.1
Reset/Presence-Detect Pulse
The 1-Wire module provides for an automated initialization sequence for the 1-Wire bus. Software initiates
the initialization sequence by setting CONTROL[RPP]. The automated initialization sequence is as
follows:
1. Generate a reset pulse.
2. Listen for a response from an external device by sampling for the 1-Wire device presence bit.
3. After an amount of time determined by the 1-Wire standard, latch the presence bit (true or false) in
CONTROL[PST].
If an external device is detected (PST = 1), software can begin communications on the 1-Wire bus.
The presence pulse is used by the 1-Wire to determine if at least one generic 1-Wire device is connected.
Software determines if more than one generic 1-Wire device exists; see Section 9.4.1.1,
“Reset/Presence-Detect Pulse.”
9.4.1.2
Bit Transfers
After the initialization sequence (see Section 9.4.1.1, “Reset/Presence-Detect Pulse”), software can write
and read one bit at a time using the control register.
9.4.1.2.1
Write-0 Sequence
The Write-0 sequence writes a zero bit to the generic 1-Wire device. Setting the CONTROL[WR0] bit
initiates the Write-0 pulse sequence. Once the write is complete, the WR0 bit is automatically cleared.
9.4.1.2.2
Write-1/Read Sequence
The Write-1 sequence writes a one bit to the generic 1-Wire device. Setting the CONTROL[WR1] bit
initiates the Write-1 pulse sequence. Once the write is complete, the WR1 bit is automatically cleared.
Because the Write-1 and Read timings are identical, this sequence also reads a bit from the bus. The
sampled value is stored in the read status bit CONTROL[RDST] and is valid after the WR1 bit is
self-cleared.
9.4.1.3
Byte Transfers
After the initialization sequence (see Section 9.4.1.1, “Reset/Presence-Detect Pulse”), software can
transfer a byte at a time using the TX/RX register. Writing to the register connects to the Transmit buffer;
reading to the register connects to the Receive buffer. See Figure 9-9.
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Tx Buffer
Tx Shift Register
OWIRE_LINE
TX/RX Register
Rx Shift Register
Rx Buffer
Figure 9-9. Byte Transfers
The Transmit buffer connects to an internal Transmit Shift Register where data is shifted serially onto the
bus LSB first. Similarly, the Receive buffer connects to an internal Receive Shift Register where data is
sampled serially from the bus.
Software can read a byte from the generic 1-Wire device as follows:
1. Write 0xFF to the Transmit/Receive register location (connected to the Transmit buffer).
2. Wait for the receive-buffer-full (INTERRUPT[RBF]) interrupt (or poll the flag bit directly if the
interrupt is disabled). During this time, the hardware is writing ones on the bus while sampling the
wired-AND of the data from the device. The read data is shifted into the Receive Shift Register.
When a byte is collected in the Receive Shift Register, the data is transferred to the Receive buffer,
and the RBF flag is set.
3. Read from the Transmit/Receive register location (connected to the Receive buffer) upon receiving
the RBF interrupt.
If the Receive buffer is full, new data is not shifted from the Receive Shift Register until the current data
is read. To prevent the loss of data, software must read the TX/RX register to clear the receive-buffer-full
flag (INTERRUPT[RBF]). This allows the Receive Shift Register to shift new data into the Receive buffer.
9.4.1.4
Search ROM Accelerator Mode
In search ROM accelerator mode, the 1-Wire module relieves software from having to perform single-bit
operations on the bus and helps to determine whether more than one generic 1-Wire device exists.
The host transmits the 16-byte search value based on the last ROM value found. These 16 bytes are 0x00
for the first run. The 16 bytes returned contain the new ROM code and are also used to generate the next
16 bytes to transmit. This process is repeated until serial numbers duplicate to find all devices.
The 1-Wire module enters search ROM accelerator mode when COMMAND[SRA] is set. This protocol
specifies that the bus master read two bits (a bit and its complement), then writes a bit to specify which
devices should remain on the bus for further processing. This mode requires that a reset followed by the
search ROM command (0xF0) has already been issued on the 1-Wire bus.
The 1-Wire module automatically exits search ROM accelerator mode if the 1-Wire bus is re-initialized;
see Section 9.4.1.1, “Reset/Presence-Detect Pulse.”
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9.4.2
Low Power Mode
The 1-Wire module automatically goes into low-power mode whenever it is not communicating with a
generic 1-Wire device. The main clock is gated off in low-power mode.
As soon as software writes to any register, the 1-Wire module exits low-power mode.
9.4.3
Clocks
The 1-Wire module takes a main clock as a module input and passes it through a clock divider. (See the
block diagram in Figure 9-1.) Software must program the divider factor to generate a 1-MHz clock that is
used as an internal time base for the module, as given by Equation 9-1.
time_base = main_clock ÷ (TIME_DIVIDER[DVDR] + 1)
Eqn. 9-1
For example, if the main clock frequency is 30 MHz, the value to write to the divider register is 29. If the
main clock input frequency is not an integer, the programmer must ensure the time base frequency is within
the range given by Equation 9-2.
0.98 MHz ≤ time_base ≤ 1.02 MHz
Eqn. 9-2
NOTE
A main clock frequency below 10 MHz causes improper function of the
module.
9.4.4
Reset
The 1-Wire module supports two levels of reset: hardware and software.
9.4.4.1
Hardware Reset
Whenever a device reset occurs, a hard reset is performed on the 1-Wire module, clearing all values written
to all registers.
9.4.4.2
Software Reset
Software initiates a software reset by setting the reset bit RESET[RST]. A software reset clears all data
written to the registers except for the command and interrupt registers (COMMAND, INTERRUPT).
Note that the reset register (RESET) itself is not cleared during a software reset. Software must clear the
RST bit to release the software reset.
9.4.5
Interrupts
The 1-Wire generates interrupts through the programming of the interrupt enable register; see
Section 9.3.2.7, “Interrupt Enable Register (INTERRUPT_EN).” The 1-Wire can generate interrupts under
the following conditions:
• Receive shift register or buffer full
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•
•
Transmit shift register or buffer empty
Presence detect
Once any of these conditions are met, the Interrupt register (see Section 9.3.2.6, “Interrupt Register
(INTERRUPT)”) sets the corresponding bit and generates an interrupt if enabled in the interrupt enable
register. The IAS bit within the interrupt enable register determines if the interrupt generated is active low,
or active high. By default all interrupts are active high, and software should not modify IAS.
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Chapter 10
ARM9 Platform Overview
10.1
Introduction
The ARM9 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 5x5 Multi-Layer AHB
crossbar switch (MAX), and two internal AHB complexes. The instruction bus of the ARM926EJ-S
processor (I-AHB) is connected directly to MAX Master Port 0. The data bus of the ARM926EJ-S
processor (D-AHB) is connected directly to MAX Master Port 1. Three alternate bus master interfaces are
connected to MAX Master Ports 2, 3 and 4. The five slave ports of the MAX are AHB-Lite-compatible
buses. Slave Ports 0, 1 and 2 are designated for external platform accesses. Slave ports 3 and 4 are internal
to the platform. Slave port 3 has three slave connected to it: an AIPS(A) peripheral interface gasket, the
ROM controller and the ASIC interrupt module. Slave port 4 has two slaves connected to it: an AIPS(B)
peripheral interface gasket and the ROMPATCH configuration registers.
The ROMPATCH module supports external boot mechanism in addition to patching of ROM.
Internal MAXMUX modules reside on MAX slave ports 3 and 4 and provide address decoding, read data
muxing, bus watchdog timers and other miscellaneous functions for these AHB systems within the
platform. A clock control module (CLKCTL) is provided to support a power conscious design
methodology as well as implementation of several clock synchronization circuits and registers for use both
inside and outside the platform.
An ARM Abort Processing Engine (AAPE) sits on the ARM926EJ-S Instruction AHB and Data AHB to
ensure that aborted accesses on those busses are not filtered out by the instruction cache or data cache but
are in fact recognized by the core.
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ARM9 Platform Overview
A block diagram of the ARM9 Platform is shown in Figure 10-1.
16k I$ MMU 16k D$
INT
I-AHB
JTAG
D-AHB
AAPE
ARM926EJ-S
M0
S0
M1
S1
ETM
Secondary
Slave
Ports
S2
MAXMUX(2)
MAX
5x5 (x32)
ETM9
ETM
ASIC
Interrupts
AIPSA
Peripherals
ROMC
ROM
ETB9
8kB Trace Buffer
S3
Alternate
Bus
Masters
bus tracking
rom data
patched data
M2
M3
M4
S4
ROMPATCH
boot_ext
ext_boot_addr
AIPSB
Peripherals
Internal IP Bus
JTAG
Resets
gated_clks
a9p_clk_off
arm9_active
CLKCTL
gp_cntrl
Figure 10-1. ARM9 Platform Block Diagram
10.2
ARM9 Platform Submodules
The submodules of the platform are listed below along with short functional descriptions.
10.2.1
ARM926EJ-S Processor
The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors
targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit THUMB
instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port
is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9
real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S
integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces,
and separate instruction and data caches.
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ARM9 Platform Overview
The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both
instruction and data caches are 16 Kbyte. The cache is virtually accessed and virtually tagged. The data
cache has physical tags as well. The MMU provides virtual memory facilities which are required to support
various platform operating systems such as Symbian OS, Windows CE and Linux. The MMU contains
eight fully associative TLB entries for lockdown and 64 set associative entries. See the ARM926EJ-S
Technical Reference Manual for more information.
10.2.2
ARM9 Embedded Trace Macrocell & Embedded Trace Buffer
The ARM9 platform includes an ARM9 Embedded Trace Macrocell (ETM9) and Embedded Trace Buffer
(ETB) supporting real-time instruction and data tracing. The ETM9/ETB external interface may run at the
ARM926EJ-S clock frequency or at half the ARM926EJ-S clock frequency. The Embedded Trace Buffer
is sized at 2048x32 and can be used as general scratch pad memory when not being used for real-time
tracing. This scratch pad memory is accessible using the AIPSA, on platform slot 4. The ETB registers can
be accessed using the AIPSA, on platform slot 3. See the ETM9 and ETB technical reference manuals for
more information.
10.2.3
5x5 Multi-Layer AHB Crossbar Switch (MAX)
The ARM926EJ-S processor instruction and data buses and all alternate bus master interfaces arbitrate for
resources using a 5x5 Multi-Layer AHB Crossbar Switch (MAX). There are five (M0 - M4) fully
functional master ports and five (S0 - S4) fully functional slave ports. The MAX is unidirectional. All
master and slave ports are AHB-Lite-compatible. See Section 10.9.1, “Definition of AHB-Lite,” for an
explanation of AHB-Lite.
The design of the crossbar switch allows for concurrent transactions to proceed from any master port to
any slave port. That is, it is possible for five slave ports to be active at the same time as a result of five
independent master requests. If a particular slave port is simultaneously requested by more than one master
port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the
bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration
schemes supported are fixed, programmable fixed, programmable default input port parking, and a round
robin arbitration scheme.
The Crossbar Switch also monitors the max_halt_request input which request a bus grant from all five
slave ports. The priority of the max_halt_request is programmable and defaults to the highest. Upon
receiving bus grants for all five output ports, the max_halted output asserts. At this point, the clock control
module can turn off hclk and be assured there are no outstanding AHB transactions in progress. Once the
CCM is granted a port, no other master receives a grant on that port until the CCM bus request
(max_halt_request) negates.
Brief descriptions below provide more detail on the MAX. For complete functionality, see the ARM9
Platform “Multi-Layer AHB Crossbar Switch” Module (MAX) specification.
10.2.3.1
MAX Configuration Registers
The Crossbar Switch has configuration and control registers accessible using the IPBus (on platform slot
1 of the AIPSA). Programmable registers exist to control arbitration schemes, bus parking, as well as other
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ARM9 Platform Overview
crossbar bus switch functionality. Alternate master priority registers exists within the MAX module for
each slave output port. The alternate priority register can be selected for use by the internal arbitration
logic.
A write-block sticky bit is implemented for those applications where it is desirable to prevent changes to
the MAX registers after boot. See the MAX module design specification for more details.
10.2.3.2
Master Ports
Master Port 0 of the MAX is connected directly to the ARM926EJ-S I-AHB. Master Port 1 of the MAX
is connected directly to the ARM926EJ-S D-AHB. The other three master ports exit the platform and are
connected to external alternate bus masters. Multiple external masters may be attached to a single alternate
bus master port using use of an external arbiter.
Master Port priorities are determined by the MAX priority register bit settings. See the MAX module
design specification for more details.
10.2.3.3
Slave Ports
Slave ports 0 through 4 are identical AHB-Lite buses. Slave ports 0, 1 and 2 are secondary AHB slave
ports, are accessible off platform, and have no on platform slaves connected to them. Slave ports 3 and 4
are internal to the platform only.
10.2.3.4
Debug Support
In addition to the JTAG, ETM9 and ETB9 interfaces, several internal ARM926EJ-S signals have been
brought out of the platform. These signals, along with alternate bus master and secondary AHB signals
already available on the top-level of the platform, enable the user to gain insight into the operation of the
processor and the MAX.
10.2.4
ARM Abort Processing Engine (AAPE)
The ARM Abort Processing Engine (AAPE) ensures that cacheable or bufferable accesses that are aborted
(receive an AHB ERROR response) on the ARM926EJ-S I-AHB or D-AHB are recognized by the
ARM926EJ-S and not lost in the instruction cache or data cache. The registers of the AAPE can be
accessed using AIPS A on-platform slot 5.
Cacheable or bufferable accesses on the ARM926EJ-S D-AHB that are aborted result in the AAPE zeroing
out the data on the D-AHB and sending an abort signal directly to the ARM926EJ-S. Cacheable or
bufferable accesses on the ARM926EJ-S I-AHB that are aborted result in the AAPE overriding the I-AHB
data with a software interrupt appropriate for the current mode of operation (ARM, THUMB or JAVA).
See the AAPE specification for more details.
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10.2.5
ARM Simple Interrupt Controller (ASIC)
NOTE
The ARM simple interrupt controller (ASIC) module is the same one used
on the ARM9 platform (AVIC) with the vectoring feature removed for use
with an ARM9. This is Freescale IP.
The ARM9 platform interrupt controller is called the ASIC and is accessible to the ARM926EJ-S only
using MAX slave port 3. It generates normal and fast interrupts to the ARM926EJ-S processor.
See the ASIC chapter for more details on ASIC operation.
10.2.6
ROM Controller and BIST Engine (ROMC)
The rom_connect input on the ARM9 Platform must be tied high if ROM exists on the ROMC interface.
The ROMC module supports a minimum of 1 Kbyte of ROM and a maximum of 4 Mbyte. Non
power-of-two sizes between 1 Kbyte and 4 Mbyte are supported by strapping the rom_size[11:0] inputs,
which correspond to slave port 3 AHB haddr[21:10]. The rom_wait input should be tied high at
integration time if a wait state is required to make read data timing on ROM accesses. A configurable BIST
engine is provided.
10.2.6.1
ROM Addressing
The first 16 Kbyte of ROM is always mapped starting at haddr[31:0]=0x0000_0000. Any ROM larger
than 16 Kbyte has the remainder of its space mapped starting at haddr[31:0]=0x0040_4000. Any ROM
size smaller than 16 Kbyte, is aliased throughout the 16 Kbyte region. Accesses to the “hole” between
these two regions are terminated with an ERROR response by the ROMC.
10.2.7
AHB <-> IP-Bus Interface (AIPS)
There are two AIPS modules instantiated in the ARM9 platform (AIPS A and AIPS B). The AIPS module
design supports many configuration options so that it may be reused across multiple systems. This section
begins with a short description of the generic AIPS module, followed by specific implementation details
of the two AIPS instantiations used in the ARM9 platform.
10.2.7.1
Brief Description of the Generic AIPS Module
The AIPS module interfaces an AHB-Lite 2.0 bus to the IP-Bus in order to foster reuse of SRS-compatible
peripherals. Each AIPS module requires a minimum of 2 hclk clocks for a read, and 3 hclk clocks for a
write. An AIPS module supports a maximum of 32 on-platform peripherals, 32 off-platform peripherals,
and two global external module enables. Each AIPS module occupies a total of 64 Mbytes of address
space. Each standard peripheral connected to an AIPS module consumes 16 Kbyte of the memory map
(ipsa_module_en[31:0]). The two global external IPS module enables are provided to support a 63-Mbyte
address space (ips_module_en_glbl[1] consumes 32 Mbytes; ips_module_en_glbl[0] consumes 31
Mbyte) for peripherals needing a larger slice of the memory map. Each AIPS module contains
programmable security access control registers for all downstream peripherals.
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10.2.7.2
AIPS Configuration on the ARM9 Platform
This section discusses the particular configuration of both AIPS modules (AIPS A and AIPS B) used
within the ARM9 platform. Some of the configuration options are controlled during synthesis, and some
are handled with tie-offs in an AIPS wrapper.
The attributes common to both AIPS modules used in the ARM9 platform are as follows:
•
•
•
•
•
•
•
•
•
•
32-bit data path.
Write buffering is disabled.
Memory map option #1 is used.
The AIPS_DLY_CYCLE parameter is disabled.
The aips_byte_config[0] input is tied high and the aips_byte_config[1] input is tied to the
cfg_bigend output of the ARM926EJ-S so both Big Endian and Little Endian modes are supported.
The only “sideband” signal implemented in each AIPS module is the ips*_cacheable output.
Only hresp[0] is driven: hresp[2:1] are tied off within the wrapper.
The AIPS modules do not support 64-bit data accesses.
Although the AIPS modules on the ARM9 platform are designed for 32-bit operation on the IP-Bus
side, they support connection of 8-bit and 16-bit peripherals. However, the AIPS does not support
accesses of a larger size than the peripheral maximum width. This means a 32-bit access to a 16-bit
or 8-bit peripheral as well as a 16-bit access to an 8-bit peripheral are not supported and the AIPS
responds with hresp = ERROR to any such access attempt.
The aips_rstcfg[63:0] inputs control the reset configuration of the Master Privilege Register
(MPR) within the AIPS module. These inputs have been tied-off in the wrapper to configure the
AIPS to allow the ARM926EJ-S processor to be the default “trusted” master out of reset. All other
masters are non-trusted. Note the ARM926EJ-S can reprogram the MPR at any time after reset.
Table 10-1 shows the default (out of reset) privilege configuration of the ARM926EJ-S processor
(trusted). Table 10-2 shows the default (out of reset) privilege configuration for all bus masters other than
the ARM926EJ-S processor (non-trusted).
Table 10-1. AIPS MPR Reset Configuration for Trusted Master (ARM9)
Default (out of reset) ARM926EJ-S Trusted Master Privileges (hmaster = 0x1)
Master Buffered Writes: No buffered Writes
Master Trusted for Reads: Yes - Trusted
Master Trusted for Writes: Yes - Trusted
Master Privilege Level: Supervisor accesses are NOT downgraded to User accesses
Table 10-2. AIPS MPR Configuration for Non-Trusted Masters
Default (out of reset) Non-Trusted Master Privileges (hmaster != 0x1)
Master Buffered Writes: No buffered Writes
Master Trusted for Reads: No - Not Trusted
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Table 10-2. AIPS MPR Configuration for Non-Trusted Masters (continued)
Default (out of reset) Non-Trusted Master Privileges (hmaster != 0x1)
Master Trusted for Writes: No - Not Trusted
Master Privilege Level: Supervisor accesses ARE downgraded to User accesses
10.2.7.3
AIPS A Peripheral Support
AIPS A shares MAX slave port 3 with the ROM controller (ROMC) and the ARM simple interrupt
controller (ASIC). AIPS A is configured to support 16 standard (16 Kbyte) external peripherals, as well as
the two global external module enables (31 Mbyte and 32 Mbyte). AIPS A also supports 5 on-platform
peripherals as shown in Table 10-3.
Table 10-3. On-platform IP-Bus Peripherals (AIPS “A”)
10.2.7.4
On-platform Peripheral
AIPS “A” On-platform Slot
MAX Configuration Registers
1
CLKCTL (General Purpose Registers)
2
ETB Registers
3
ETB Memory
4
AAPE Registers
5
AIPS B Peripheral Support
AIPS B shares MAX slave port 4 with the ROMPATCH. AIPS B is configured to support 32 standard (16
Kbyte) external peripherals, as well as the two global external module enables (31 Mbyte and 32 Mbyte).
AIPS B does not support any on-platform peripherals.
10.2.7.5
Peripheral Summary
Table 10-4 is a summary of the total ARM9 platform internal (on-platform) and external (off-platform)
peripherals which are supported.
Table 10-4. Summary of ARM9 Platform Peripheral Support
AIPS Module
Number of On-Platform
Peripherals
Number of Off-Platform Number of Off-platform Global Module Enables
Peripherals
(31MB, 32MB)
AIPS A
5
16
1, 1
AIPS B
None
32
1, 1
Total
5
48
2, 2
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10.2.7.6
Register Reset Summary
Table 10-5 is a summary of the reset state of the registers for AIPSA.
Table 10-5. Summary of ARM9 Platform AIPSA Register Reset State
Register
Reset Value
Master Privilege Register (0–7)
0x07000000
Master Privilege Register (8–15)
0x00000000
Peripheral Access Control Register (0–7)
0x54444400
Peripheral Access Control Register (8–15)
0x00000000
Peripheral Access Control Register (16–23)
0x00000000
Peripheral Access Control Register (24–31)
0x00000000
Off Platform Peripheral Access Control Register (0–7)
0x44444444
Off Platform Peripheral Access Control Register (8–15)
0x44444444
Off Platform Peripheral Access Control Register (16–23)
0x00000000
Off Platform Peripheral Access Control Register (24–31)
0x00000000
Off Platform Peripheral Access Control Register (32–33)
0x44000000
Table 10-6 is a summary of the reset state of the registers for AIPSB.
Table 10-6. Summary of ARM9 Platform AIPSB Register Reset State
10.2.8
Register
Reset Value
Master Privilege Register (0–7)
0x07000000
Master Privilege Register (8–15)
0x00000000
Peripheral Access Control Register (0–7)
0x50000000
Peripheral Access Control Register (8–15)
0x00000000
Peripheral Access Control Register (16–23)
0x00000000
Peripheral Access Control Register (24–31)
0x00000000
Off Platform Peripheral Access Control Register (0–7)
0x44444444
Off Platform Peripheral Access Control Register (8–15)
0x44444444
Off Platform Peripheral Access Control Register (16–23)
0x44444444
Off Platform Peripheral Access Control Register (24–31)
0x44444444
Off Platform Peripheral Access Control Register (32–33)
0x44000000
MAX Internal Slave Port Muxes (MAXMUX)
There are two instantiations of the MAXMUX module in the ARM9 platform. The first instantiation
resides on MAX slave port 3 and handles the AHB infrastructure for the AIPS A, ASIC and ROMC
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modules. The second instantiation resides on MAX slave port 4 and handles the AHB infrastructure for
the AIPS B and ROMPATCH modules.
10.2.8.1
Peripheral Bus Timeout Monitors
The ARM9 platform MAX module returns an AHB hresp = ERROR termination status on attempted
accesses to undefined regions of memory. Likewise, the AIPS module returns and AHB hresp = ERROR
termination status on attempted accesses to unpopulated regions of the peripheral space. The memory
controller (ROMC) is, by design, either zero or one wait state responders. The ASIC and ROMPATCH are
also single wait state responders (CHECK). However, the danger still exists that peripherals residing on
the AIPS module’s (2) IP-Buses could hang and not properly terminate an access. Therefore, the ARM9
platform supports AHB bus timeout monitors on each internal MAX slave port. The timeout monitors are
implemented in each instantiation of the MAXMUX module.
The timeout interval for both modules are set by the bmon_timeout[1:0] inputs which are statically tied
off at integration time. The timeout monitors both share a single enable bit in the general purpose register
of the CLKCTL module. When the timeout monitors are enabled, and AHB access to either internal MAX
slave port that does not terminate within the time it takes for the bus monitor to reach zero are terminated
by the timeout monitor in the MAXMUX module. The timeout monitor terminates a “hung” access by
forcing an hresp = ERROR and hready termination. The bus timeout clock counts for the
bmon_timeout[1:0] encoding is shown in Table 10-7.
Table 10-7. Bus Monitor Timeout Interval
bmon_timeout[1:0]
Timeout Interval
00
31 clocks
01
127 clocks
10
511 clocks
11
2047 clocks
NOTE
The ARM9 platform does not include timeout monitors for MAX slave
ports 0, 1 and 2.
10.2.9
ROM Patch (ROMPATCH)
The ROM patch module (ROMPATCH) is used to patch errant ROM code. The registers of the
ROMPATCH are programmed by the ARM926EJ-S using MAX slave port 4. The ROMPATCH only
patches accesses to the ROMC. The ROMPATCH module can be used to patch source code or data tables.
The module supports 16 patches.
10.2.9.1
External Boot
An external boot feature exists in the ROMPATCH module which allows patching of the reset vector fetch
(address = 0x0000_0000) if the boot_int signal is negated. This mechanism causes the ARM926EJ-S to,
in effect, fetch the reset vector from the address indicated by the ext_boot_addr[31:2] inputs.
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10.2.10 Clock Control Module (CLKCTL)
The Clock Control Module (CLKCTL) performs module level clock gating and ARM926EJ-S JTAG
synchronization. Additionally, the CLKCTL module is a 32-bit peripheral connected to AIPS A
on-platform IP-Bus slot 2. The IP-Bus interface allows access to a general purpose control register and a
read only TAPID register. Four of the general purpose control outputs, a9p_gp_cntrl[3:0], are ported to
the top-level of the ARM9 platform. The upper 12 bits are used internally and are not brought to the
top-level. Additionally a TAPID version, tapid_ver[3:0], is brought in from the top-level.
TAPID_VER[3:0]
(external to ARM926P)
AIPS A IP-Bus
CLKCTL
(Slot 2)
A9P_GP_CNTRL[3:0]
(external to ARM926P)
CLKCTL_GP_CNTRL[15:4]
(internal to ARM926P)
Figure 10-2. CLKCTL General Purpose Register Interface
10.2.10.1 CLKCTL Registers
The CLKCTL module is connected to AIPS A IP-Bus on-platform slot 2 as a 32-bit peripheral. The
registers residing in the CLKCTL module are shown in Table 10-8.
Table 10-8. CLKCTL Registers
AIPSA_ADDR[4:2]
Register Name
Register Definition
Width
3’b000
GP_CNTRL
General Purpose Control Register
[15:0]
3’b001
GP_SER
General Purpose Set Enable Register
[15:0]
3’b010
GP_CER
General Purpose Clear Enable Register
[15:0]
3’b100
TAPID
TAPID Register (Read Only)
[31:0]
10.2.10.1.1 GP_CNTRL, GP_SER and GP_CER Registers
The GP_CNTRL register is write/read. All bits in the CP_CNTRL register are cleared on reset. All bits of
the GP_CNTRL register may be written concurrently by writing directly to the GP_CNTRL register. To
prevent the need to perform a read-modify write operation when the user wishes to set or clear a single bit
in the GP_CNTRL register the GP_SER and GP_CER registers have been added. A single bit may be set
in the GP_CNRL register by writing a one to the relative bit location in the Set Enable Register (GP_SER).
Similarly, a single bit may be cleared by writing a one to the relative bit location in the Clear Enable
Register (GP_CER). Reading the GP_SER or GP_CER registers returns all zeros.
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Table 10-9 details the functions of all the bits in the CLKCTL module General Purpose Control Register.
Table 10-9. CLKCTL General Purpose Control Bit (GP_CNTRL) Usage
GP_CNTRL Register Bit
Reset Value
Description
[3:0]
4’b0000
[4]
1’b0
When set, enables the peripheral bus timeout monitors. See
Section 10.2.8.1, “Peripheral Bus Timeout Monitors,” for more
information.
[5]
1’b0
Reserved for future use.
[6]
1’b0
When set, this bit enables clocks to the ETB. Clocks to the
ETB are automatically issued when a debugger is connected
(dbgen asserted). However, if the ETB memory is to be used
as general purpose memory, this bit must be set. This bit
should not be set in a non-debug mode environment if the ETB
memory is not going to be used.
[7]
1’b0
When set this bit allows a9p_clk_off to assert even when
debug activity is present.
[10:8]
3’b000
[11]
1’b0
[15:12]
4’b0000
Driven off-platform for use at the SoC level.
Reserved for future use.
When set, this bit enables the MAX Slave Port Sharing Widget
(SPSW).
Reserved for future use.
10.2.10.1.2 TAPID Register
The TAPID register is provided for software to determine the version of the platform. These bits
correspond to the static state of the tapid[31:0] signals which include the tapid_ver[3:0] platform inputs.
See Section 10.4, “JTAG ID Register,” for more details.
10.2.10.2 JTAG Synchronization
The CLKCTL module synchronizes the external JTAG interface to the ARM926EJ-S clock (clk). The
inputs and outputs of the synchronization circuit are connected to the JTAG interface on the ARM926EJ-S,
ETM9 and ETB9 modules.
10.2.11 Just Another Module (JAM)
The JAM (Just Another Module) implements miscellaneous logic with the platform. Functionality within
the JAM includes muxing of BIST outputs from the instruction cache memory, data cache memory, MMU
memory, ETB memory and ROMC memory.
10.2.12 Test Wrapper
The ARM9 Platform test architecture is composed primarily of two functions: scan and BIST. The test
module (ARM926P_TEST) includes a test control unit which decodes primary test mode input signals and
places the platform into various test modes including scan, ac path testing, BIST, and safe state. These test
modes support the ability to test a deeply embedded platform.
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10.3
ARM9 Platform Hierarchy
The first two levels of the ARM9 Platform design hierarchy are shown in Figure 10-3.
ARM9P PLATFORM
ARM926P_CORE
ARM926P_TEST
ARM926P_DEBUG
ARM926P_WRAPPER
ETM9
ARM926P_TCU
ARM926EJ-S
ETB9
ARM926P_ROUTER
AAPE
CLKCTL
MAX
(CROSSBAR SWITCH)
JAM
MAXMUX_S3
MAXMUX_S4
AIPS A
AIPS B
ROMC
ROMPATCH
ASIC
Figure 10-3. ARM9 Platform Hierarchy
10.4
JTAG ID Register
The ARM926EJ-S processor has a 32-bit input bus which corresponds to the JTAG ID register. This 32-bit
register is defined as shown in Table 10-10. ARM requires bits [31:12] be set in accordance with their
general rules such that Multi-ICE can auto-detect the device type.
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Table 10-10. ARM926EJ-S JTAG ID Register Definition
tapid[31:28]
tapid[27:12]
Version
Part Number
0x0
0x7926
tapid[11:8]
tapid[7:1]
tapid[0]
Manufacturing ID
tapid_ver[3:0]
1
0b010_0000
1
Normally, the Freescale Manufacturing ID is 0x00E. However, since ARM uses all of the available bits
that are usually used to track platform level revisions, the top 4 bits of the manufacturing ID are brought
out for use at the system level (tapid_ver[3:0]), and the rest of the manufacturing ID is used to indicate
platform revisions.
JTAG ID register bits [11:8] (tapid_ver[3:0] on the platform I/O) are incremented by the system
integration team as appropriate throughout the life of the system.
JTAG ID register bits [7:1] are incremented by the ARM9 platform team as appropriate to indicate
platform revisions.
10.5
System Memory Map
The memory map decode is based on haddr[31:27] on the MAX master ports, which is decoded to
determine which slave port has been selected. Five bits are used, which is more than optimal; however,
this is necessary to try and keep the ARM9 platform memory map consistent with that of the ARM9
platform. Table 10-11 shows a simplified breakdown of the regions decoded within the 4GB address space.
Table 10-11. ARM9 Platform High Level Address and Location Map
haddr[31:27]
Size
Usage
Location
0000x
256 Mbyte
ROM
MAX Slave Port 3
0001x
256 Mbyte
Reserved
—
001xx
512 Mbyte
Reserved
—
0100x
256 Mbyte
AIPS A
MAX Slave Port 3
0101x
256 Mbyte
AIPS B
MAX Slave Port 4
01100
128 Mbyte
ROMPATCH
MAX Slave Port 4
01101
128 Mbyte
ASIC
MAX Slave Port 3
0111x
256 Mbyte
Secondary AHB
MAX Slave Port 2
10xxx
1 Gbyte
Secondary AHB
MAX Slave Port 11
11xxx
1 Gbyte
Secondary AHB
MAX Slave Port 02
1
If MAX slave port sharing is disabled accesses to haddr[31:30] = 2’b10 are steered to MAX slave port 1 only. If MAX slave
port sharing is enabled accesses to haddr[31:30] = 2’b10 can potentially be steered to MAX slave port 0 in addition to MAX
slave port 1.
2 If MAX slave port sharing is disabled accesses to haddr[31:30] = 2’b11 are steered to MAX slave port 0 only. If MAX slave
port sharing is enabled accesses to haddr[31:30] = 2’b11 can potentially be steered to MAX slave port 1 in addition to MAX
slave port 0.
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10.5.1
ARM9 Platform Memory Map
Table 10-12 shows the complete ARM9 Platform memory map.
Table 10-12. ARM9 Platform Detailed Memory Map
1
Address Range
Size
Use
0000_0000 - 0000_3FFF
16 Kbyte
ROM: First 16 Kbyte
0000_4000 - 0040_3FFF
4 Mbyte
Reserved
0040_4000 - 007F_FFFF
4080 Kbyte
ROM: Exceeding 16 Kbyte
0080_0000 - 0FFF_FFFF
248 Mbyte
Reserved
1000_0000 - 3FFF_FFFF
768 Mbyte
Reserved
4000_0000 - 41FF_FFFF
32 Mbyte
AIPS A Off platform global module enable 0
4200_0000 - 43EF_FFFF
31 Mbyte
AIPS A Off platform global module enable 1
43F0_0000 - 43F0_3FFF
16 Kbyte
AIPS A Control Registers (on platform slot 0)
43F0_4000 - 43F0_7FFF
16 Kbyte
AIPS A - MAX Registers (on platform slot 1)
43F0_8000 - 43F0_BFFF
16 Kbyte
AIPS A - CLKCTL (on platform slot 2)
43F0_C000 - 43F0_FFFF
16 Kbyte
AIPS A - ETB Registers (on platform slot 3)
43F1_0000 - 43F1_3FFF
16 Kbyte
AIPS A - ETB Memory (on platform slot 4)
43F1_4000 - 43F1_7FFF
16 Kbyte
AIPS A - AAPE Registers (on platform slot 5)
43F1_8000 - 43F7_FFFF
416 Kbyte
Reserved (AIPS A Unused on platform slots [31:6])
43F8_0000 - 43FB_FFFF
256 Kbyte
AIPS A Off platform slots [15:0]
43FC_0000 - 43FF_FFFF
256 Kbyte
Reserved (AIPS A Unused off platform slots [31:16])
4400_0000 - 4FFF_FFFF
192 Mbyte
Reserved (Aliased AIPS A Space)
5000_0000 - 51FF_FFFF
32 Mbyte
AIPS B Off platform global module enable 0
5200_0000 - 53EF_FFFF
31 Mbyte
AIPS B Off platform global module enable 1
53F0_0000 - 53F0_3FFF
16 Kbyte
AIPS B Control Registers (on platform slot 0)
53F0_4000 - 53F7_FFFF
496 Kbyte
Reserved (AIPS B Unused on platform slots [31:1])
53F8_0000 - 53FF_FFFF
512 Kbyte
AIPS B Off platform slots [31:0]
5400_0000 - 5FFF_FFFF
192 Mbyte
Reserved (Aliased AIPS B Space)
6000_0000 - 67FF_FFFF
128 Mbyte
ROMPATCH (Aliased throughout entire region)
6800_0000 - 6FFF_FFFF
128 Mbyte
ASIC (Aliased throughout entire region)
7000_0000 - 7FFF_FFFF
256 Mbyte
Secondary AHB (MAX Slave Port 2)
8000_0000 - BFFF_FFFF
1 Gbyte
Secondary AHB (MAX Slave Port 1)1
C000_0000 - FFFF_FFFF
1 Gbyte
Secondary AHB (MAX Slave Port 0)2
If MAX slave port sharing is disabled accesses to haddr[31:30] = 2’b10 are steered to MAX slave port 1 only. If MAX
slave port sharing is enabled accesses to haddr[31:30] = 2’b10 can potentially be steered to MAX slave port 0 in addition
to MAX slave port 1.
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2
If MAX slave port sharing is disabled accesses to haddr[31:30] = 2’b11 are steered to MAX slave port 0 only. If MAX
slave port sharing is enabled accesses to haddr[31:30] = 2’b11 can potentially be steered to MAX slave port 1 in addition
to MAX slave port 0.
10.5.2
External Boot
When the boot_int input signal is asserted, the ARM926EJ-S boots internal from ROM on slave port 3
AHB. When boot_int is negated, the ARM926EJ-S reset vector fetch is routed to an address indicated by
the ext_boot_addr[31:2] input pins. This vectoring is done by the ROMPATCH module, which monitors
accesses to the ROMC and over-rides the reset vector fetch.
NOTE
When boot_int is negated and the ARM926EJ-S boots externally the
ARM9 Platform is placed in an insecure state.
10.5.3
•
•
•
•
•
Memory Map Considerations
Accesses to non-aliased “Reserved” locations in Table 10-12 result in an AHB error response.
Accesses to unsupported address locations through the MAX result in an AHB error response and
the access does not pass through the MAX.
Accesses to address locations on either internal AHB bus (MAX slave ports 3 or 4) which do not
map to a specific module time-out in 128 AHB clock cycles.
Accesses to unimplemented locations within the ARM simple interrupt controller (ASIC) and
ROMPATCH register space are terminated without a bus-error. Writes have no effect and reads
return all zeros.
Accesses to the ASIC and ROMPATCH are restricted to the ARM926EJ-S. Any master other than
the ARM926EJ-S attempting to access the ASIC or the ROMPATCH receive an immediate AHB
error response.
10.6
Platform Clocking
This section describes some of the clocking considerations within the ARM9 Platform. The circuits
contained in the ARM9 Platform to address most of these issues are implemented within the Clock Control
Module (CLKCTL).
10.6.1
ARM926EJ-S Clock Considerations
The ARM926EJ-S processor design uses a single clock, clk. In many systems, it is desirable for the
ARM926EJ-S processor to run at a higher frequency than the AHB system bus (which runs on hclk). To
support this, ARM926EJ-S requires a separate AHB clock enable for each of the two bus masters. dhclken
is used to signify the rising edge of hclk for the system in which the data BIU is the bus master. ihclken
is used to signify the rising edge of hclk for the system in which the instruction BIU is the bus master.
Figure 10-4 shows the relationship between clk, hclk and dhclken/ihclken. The ARM9 Platform provides
a single hclken_early input pin that is fed to CLKCTL module, wherein it gets synchronized with respect
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ARM9 Platform Overview
to clk (hclken). hclken is fed to both the dhclken and ihclken inputs on the ARM926EJ-S. If hclk and
clk are the same frequency, the hclken_early input to the platform must be tied high.
Figure 10-4. AHB Clock Relationship
clk and hclk must be synchronous and the skew between clk and hclk to the ARM9 Platform should be
minimized. This requires some synchronization inside the chip clock control module.
10.6.2
ARM926EJ-S JTAG Port Clocking Considerations
The ARM926EJ-S does not support direct connection to the JTAG interface. The JTAG interface must be
synchronized to the clk domain. This synchronization takes place within the platform CLKCTL module.
See the ARM9 Platform CLKCTL design specification for more detail.
10.6.2.1
JTAG_TCK
The jtag_tck clock must be less than 1/8 the frequency of the clk input in order for the JTAG port and
synchronizer to function properly. Note that the frequency of clk can vary when executing low-power
code. Therefore, care must be taken such that jtag_tck is less than 1/8 the lowest possible frequency of clk.
10.6.3
External Alternate Bus Master Interfaces
Both alternate bus master ports on the ARM9 Platform must have the AHB synchronized to hclk external
to the platform. All alternate bus master AHB inputs and outputs to/from the ARM9 Platform are
synchronous to hclk. The Baseband processor, for instance, may be running at 66 MHz. Synchronization
off platform must be implemented such that the alternate bus master interface to the ARM9 Platform
would run at the hclk frequency.
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10.6.4
External Secondary AHB Ports
All three secondary AHB ports inputs and outputs to and from the ARM9 Platform must be synchronous
to the hclk and runs at the hclk frequency.
10.7
Platform Resets
This section describes the various ARM9 Platform reset inputs. Figure 10-5 shows the reset paths within
the ARM9 Platform.
ARM9 Platform
ARM926P_CORE
ARM926P_TEST
hreset_b
tcu_hreset_b
hreset_b
ARM926EJ-S
HRESETn
DBGnTRST
ETM9
nRESET
CLKCTL
nTRST
por
dbg_clear_b
OR
&
sync
jtag_trst_b
ETB9
HRESETn
nTRST
clk
nRESET
hreset_b
(to all other platform modules)
Figure 10-5. ARM9 Platform Resets
10.7.1
hreset_b
The hreset_b input is the asynchronous system reset for both the clk and hclk domains. It is gated with a
test mode signal in the scan wrapper, and is then buffered for distribution throughout the platform.
10.7.2
POR and JTAG_TRST_B
The power-on-reset (por) and the JTAG reset (jtag_trst_b) are combined in the CLKCTL module to drive
the dbg_clear_b signal to the ARM926EJ-S and ETM9 modules. The dbg_clear_b output of the
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ARM9 Platform Overview
CLKCTL module can be considered as the JTAG or debug reset of the platform. The dbg_clear_b signal
asserts asynchronously when either por or jtag_trst_b asserts, and negates synchronously to clk (through
a synchronizer).
10.8
10.8.1
Power Management
Register Level Clock Gating
Under normal operating conditions, clocks internal to the platform are only issued to registers or banks of
flops that need a rising edge for proper functionality. Otherwise, the clocks are held low.
10.8.2
Block Level Clock Gating
Clocks to individual modules within the platform are enabled only when necessary. On the internal AHBs
for example, the CLKCTL module only enables hclk to a slave module when the current AHB access is
addressed to that module. Slaves can also drive a signal to the CLKCTL if it requires its hclk to run for
any other reason. See the CLKCTL module design specification for more detail.
10.8.3
External Clock Gating
The ARM926EJ-S processor may be put into a low-power state by the wait-for-interrupt instruction. This
instruction switches the ARM926EJ-S into a low-power state until either an interrupt (nIRQ/nFIQ) or a
debug request occurs. The switch into the low-power state is indicated by the assertion of the
arm_standbywfi output signal. If arm_standbywfi is asserted then it is guaranteed that all ARM926EJ-S
external interfaces are in an IDLE state. The arm_standbywfi signal is intended to be used to shut down
clocks to the other parts of the system, such as external coprocessors, which do not need to be clocked if
the ARM926EJ-S is idle. The ARM926EJ-S clk must not be stopped during wait-for-interrupt mode if an
external debugger is connected to the JTAG port. An active clk is required to be able to write values into
the ARM9EJ-S debug control register, which is required for a debugger to be able to force
wait-for-interrupt mode to be exited. It should also be noted that the ARM926EJ-S needs clk to run in order
for an interrupt to cause the negation of arm_standbywfi.
The JTAG synchronizer in the CLKCTL module needs to have an “always” clock running to it in order to,
at any time, detect JTAG activity and thereby determine that a debugger is connected to the JTAG port.
The presence of an active JTAG debugger is detected by monitoring the JTAG TMS signal. After por (or
trst_b) assertion, a low state on TMS coincident with a rising-edge on tck transitions the JTAG
tap-controller from the test-logic-reset state to the run-test-idle state. The dbgen signal is asserted, and
held asserted, whenever the tap-controller is not in the test-logic-reset state. Once dbgen asserts, an active
trst_b or por is required to clear it (that is, once a debugger is detected to be connected, it is assumed to
stay connected).
When asserted, the a9p_clk_off output of the platform indicates to an external clock control module that
clk and hclken_early should be turned off at the earliest opportunity. However, in order to assure that no
alternate bus masters are in the middle of a transaction, the external clock control module must assert the
max_halt_request input of the crossbar switch. This requests ownership of all AHB Output Ports. Once
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max_halted is asserted, the external clock control module is then free to gate off hclk as all transactions
on both the internal and secondary AHB.
Low power entry and exit sequences are described in the ARM simple interrupt controller (ASIC) chapter.
10.8.4
Well Biasing
A well bias clamp enable input, wt_en, is driven by an external clock control module to the ARM9
Platform. When asserted, VBB+ is shorted to VDD and VBB- is shorted to GND.
10.9
Platform AHB Interfaces
This sections describes the major bus interfaces of the ARM9 Platform and the crossbar switch. A simple
block diagram of the bus connections to the platform is shown in Figure 10-1. A definition of AHB-Lite,
a functional description of the alternate bus master ports, and finally a description of the multi-layer
crossbar switch slave ports follows.
10.9.1
Definition of AHB-Lite
All master and slave ports of the Multi-Layer AHB Crossbar switch are AHB-Lite-compatible. Therefore
all AHBs connected externally to the ARM9 Platform must be AHB-Lite-compatible.
The definition of “AHB-Lite” for the ARM9 Platform is as follows:
• AHB split and retry protocols are not supported within the ARM9 Platform. This means that all
slaves connected to AHB-Lite ports (input or output) are prohibited from requesting a split or a
retry. This also means there is only one response signal, hresp0.
• AMBA bus request and bus grant are not supported on the AHB-Lite interfaces.
• Bursts are supported. The default configuration of the Crossbar Switch (MAX) insures no early
fixed length burst terminations due to the switch arbiter.
10.9.2
Alternate Bus Master Ports
There are three alternate bus master ports (ABM) on the ARM9 Platform which are connected directly to
the Multi-Layer AHB Crossbar Switch. These three ABM interfaces are AHB-Lite-compatible.
10.9.2.1
hmaster
Alternate bus masters external to the ARM9 Platform should be aware that two values of the hmaster field
are used by bus masters internal to the platform. The reserved and available hmaster encoding is shown
in Table 10-13.
Table 10-13. hmaster Encodings
hmaster
Use
0x0
Reserved: MAX default
0x1
Reserved: ARM926EJ-S I-AHB and D-AHB
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Table 10-13. hmaster Encodings (continued)
hmaster
10.9.2.2
Use
0x9
RTIC
0xb
eSDHC2
0xc
SDMA
0xd
USB OTG
Bus Error
A slave two cycle ERROR response (hresp0 = HIGH) allows for a bus master to cancel the remaining
transfers in a burst. However, this is not an AHB requirement, and it is acceptable for the master to
continue the remaining transfers of the burst.
AHB error responses generated on accesses to cacheable or bufferable memory address on the I-AHB and
D-AHB interfaces of the ARM926EJ-S are normally ignored by the processor. In the ROMPATCH
module, a feature can be enabled which, on the above described accesses, gates 0’s onto hrdata[31:0] on
data reads, and SWI opcodes onto hrdata[31:0] for instruction prefetches. At the same time, the
ROMPATCH module generates an abort which guarantees entry into the ARM926EJ-S abort exception
handler.
10.9.2.3
Halt Request (max_halt_request)
Care must be taken to ensure that the Halt Low Priority bit is not changing as the Clock Control Module
Halt request is asserted. This results in unpredictable behavior. This can be avoided by not modifying this
bit in the Slave General Purpose Control Register or in the Alternate Slave General Purpose Control
register in software where Halt could be requested. Also, the Halt Low Priority bit should be programmed
the same in both the Slave General Purpose Control Register and the Alternate Slave General Purpose
Control Register, if it is likely the MAX can change between the General Purpose and Alternate registers
during the time Halt could be requested.
Care should also be taken to ensure that the Clock Control Module Halt request is not asserted until at least
two clock cycles after the last locked access performed by any master connected to the MAX.
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AIPS A
ASIC
ROMC
romc_rdata
hsel_asic
hsel_aipsa
s3_haddr
s3_hcontrol
s3_hwdata
ROMPATCH
hsel_romc
patched romc_rdata
AHB
MULTI-LAYER
CROSSBAR
SWITCH
(MAX)
aipsa_rdata
s3_haddr
asic_rdata
addr
decode
select
s3_hrdata[31:0]
s3_hrdata
s3_hready
s3_hready
s3_hresp0
s3_hresp0
(ONLY SLAVE PORT 3
SIGNALS ARE SHOWN)
combine
hready_out, hresp0 from slaves
bus monitor
MAXMUX_S3
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Chapter 11
ARM9 Platform AAPE
11.1
Introduction
The ARM926EJ-S ARM Abort Processing Engine (AAPE) is a 32-bit IP Bus peripheral which monitors
the Instruction AHB (I-AHB) and the Data AHB (D-AHB) to ensure that when bufferable or cacheable
accesses receive AHB ERROR responses, the cache controller does not mask them off, thereby allowing
the acknowledgement and processing of the ERROR response.
11.1.1
Overview
The AAPE module provides the following features:
• Concurrent and separate monitoring of the I-AHB (instruction bus) and the D-AHB (data bus) of
ARM926EJ-S core
• D-AHB abort generation and address tracking
• D-AHB data override for aborted READs separately enabled from abort generation
• I-AHB data override for aborted instruction prefetches
• IP Bus Register Interface
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ARM9 Platform AAPE
The block diagram of the AAPE is shown in Figure 11-1.
aape_dabort
dhrdata
32
D-AHB control
32’b0
aape_dhrdata
32
I-AHB control
aape_rdata_mux
aape_swigen
dhaddr
ihrdata
32
32’b0
aape_ihrdata
32
aape_registers
read_enables
write_enables
ips bus
aape_address_decode
Figure 11-1. AAPE Block Diagram
11.1.2
Features
When enabled, the AAPE tracks cacheable/bufferable accesses on the D-AHB bus that terminate in an
ERROR response, and forces data aborts in the ARM926EJ-S. The address of the aborted accesses are
latched to allow subsequent processing by software. The AAPE can also be enabled to override the data of
the aborted reads with zeros. The abort generation and data override features can be enabled separately.
One scenario which makes use of the separate enablements is one in which illegal accesses to secure
memory should yield zeroed out data, but not necessarily cause the ARM926EJ-S to enter the ABORT
mode.
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ARM9 Platform AAPE
Abort tracking can also be enabled separately on the I-AHB. When enabled, The AAPE overrides aborted
instruction fetches with the SWI (Software Interrupt) instruction or the Undefined Java byte code.
However, no abort forcing is done by the AAPE for instruction fetches that terminate in AHB error
responses. There is no latching of the address that has the AHB ERROR response.
11.2
Memory Map and Register Definition
The AAPE module has three registers: the control register, the status register, and the abort address register
(read-only). The registers are IP bus compliant. Read and write transfers both require one IP bus clock
cycle. The registers can only be accessed in supervisor mode. Additionally, these registers can only be read
from or written to by 32-bit accesses. User mode, byte and half-word accesses result in a transfer error.
The registers are fully decoded. Write accesses to unimplemented locations within the AAPE result in a
transfer error. Read accesses to unimplemented locations within the AAPE do not return an error response
but return all 0s as read data.
This section includes the module memory map and detailed descriptions of all registers. For the base
address of a particular module instantiation, see the system memory map.
11.2.1
Memory Map
The memory map for the AAPE program-visible registers is show in Table 11-1.
Table 11-1. AAPE Memory Map
Base Address
Offset
Register
Access
Reset Value
Section/Page
0x000
Abort Control Register (ABCNTL)
R/W
0x0000_0000
11.2.3.1/11-5
0x004
Abort Status Register (ABSR)
R/W
0x0000_0000
11.2.3.2/11-6
0x008
Abort Address Register (ABDADR)
R
0x0000_0000
11.2.3.3/11-7
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11.2.2
Register Summary
Table 11-2 is the register summary table.
Table 11-2. AAPE Register Summary
Name
31
ABCNTL
($BASE + R
0x000)
0
26
0 0 0 0
25
0
24
0
0 0 0 0 0 0
17
16
15
0
0
0
10
0 0 0 0
9
8
0
IAOEN
7
1
0
0 0 0 0 0 0 0
0
DAOEN DAGEN
W
ABSR
($BASE + R
0x004)
0
0 0 0 0
0
0
0
0 0 0 0 0 0
0
0
0 0 0 0
0
0
0
0 0 0 0 0 0 0
IAB
DAB
W
ABDADR
($BASE + R
0x008)
DABORTADDR
W
11.2.3
Register Descriptions
This section provides detailed descriptions of the AAPE registers.
Register conventions: Figure 11-2 and Table 11-3 explain conventions used in register diagrams and
tables.
Always
reads 1
1
Always
reads 0
0
R/W
Read- BIT WriteWrite 1 BIT
Read rtc Self-clear 0 N/A
bit BIT only bit
only bit BIT to clear w1c to clear BIT
bit BIT
Figure 11-2. Register Field Conventions
Table 11-3. General Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
BIT
Bit or field name. Its presence in the read or write row indicates that it can correspondingly be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
rtc
Read to clear. A read-only status bit that is automatically cleared when read.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
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Table 11-3. General Register Conventions (continued)
Convention
Description
Reset Values
0
Resets to 0 (zero).
1
Resets to 1 (one).
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
11.2.3.1
Reset value is determined by polarity of indicated signal.
Abort Control Register (ABCNTL)
The AAPE abort control register (ABCNTL) enables the abort tracking logic and data override for the
I-AHB and D-AHB busses. Figure 11-3 shows the register. Table 11-4 describes the register fields.
Offset 0x0000
R
Access: Supervisor read / write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
IAOE
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
DAOE DAGE
N
N
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-3. ABCNTL Register Diagram
Table 11-4. ABCNTL Register Field Description
Field
Description
31–26
Reserved
25
IAOEN
I-AHB Aborted RDATA Override Enable. This bit is cleared by Reset or by writing a 0 to the bit. Setting this bit
enables the I-AHB abort tracking engine and the override of the RDATA bus when a I-AHB abort of
cacheable/bufferable data occurs.
For an aborted cacheable/bufferable fetch the value sent to the I-Cache depends on the operating mode of
the ARM926EJ-S core. In THUMB mode, the value sent is a THUMB SWI #16 (0xDF10) on both halves of the
aape_ihrdata bus. In ARM mode, the value sent is an ARM SWI #16 (0xEF000010). In Java mode, the value
sent is the byte code 0xFF on both halves of the aape_ihrdata bus
0 I-AHB abort tracking and aborted RDATA Override disabled.
1 I-AHB abort tracking and aborted RDATA Override enabled.
24–10
Reserved
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Table 11-4. ABCNTL Register Field Description (continued)
Field
Description
9
DAOEN
D-AHB Aborted RDATA Override Enable. This bit is cleared by Reset or by writing a 0 to the bit. Setting this
bit enables the D-AHB abort tracking engine, and drive 0s on the aape_dhrdata bus when a D-AHB abort of
cacheable/bufferable data occurs, but does not enable the assertion of aape_dabort.
For an aborted cacheable/bufferable access the value sent to the D-Cache is all 0’s.
0 D-AHB abort tracking and aborted RDATA Override disabled.
1 D-AHB abort tracking and aborted RDATA Override enabled.
8
DAGEN
D-AHB Abort Cache Override Enable. This bit is cleared by Reset or by writing a 0 to the bit. Setting this bit
enables the D-AHB abort tracking engine. The AAPE generates assert aape_dabort which is ORed with the
abort from the D-Cache when a D-AHB abort occurs on a cacheable/bufferable access.
0 D-AHB abort tracking disabled.
1 D-AHB abort tracking and abort forcing enabled.
7–0
Reserved
11.2.3.2
Abort Status Register (ABSR)
The AAPE abort status register (ABSR) has two bits to flag the occurrence of ERROR responses on the
I-AHB and D-AHB busses. The IAB status bit is set when an ERROR response occurs on the I-AHB bus
for a bufferrable/cacheable read access, provided that bit IAOEN of the ABCNTL register is set. Once set,
IAB stays set until cleared by a Reset condition or by writing a 1 to the bit.
Similarly, the DAB status bit is set when an ERROR response occurs on the D-AHB bus for a
bufferable/cacheable read access, provided that either DAOEN or DAGEN bit or both in the ABCNTL
register is set. Once set DAB stays set until cleared by a Reset condition or by writing a 1 to the bit.
Figure 11-4 shows the register. Table 11-5 describes the register fields.
Offset 0x0004
R
Access: Supervisor read / write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IAB
W
Reset
R
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
w1c
0
Figure 11-4. ABSR Register Diagram
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Table 11-5. ABSR Field Descriptions
Field
Description
31–16
Reserved
16
IAB
I-AHB Abort indicator. Indicates that a cacheable or bufferable abort occurred on the I-AHB. Reset and writing
a 1 to this bit clears it.
0 Normal
1 I-AHB cacheable or bufferable access abort occurred
15–1
Reserved
0
DAB
D-AHB Abort indicator. Indicates that a cacheable or bufferable abort occurred on the D-AHB. Reset and
writing a 1 to this bit clears it.
0 Normal
1 D-AHB cacheable or bufferable access abort occurred
11.2.3.3
Abort Address Register (ABDADR)
The D-AHB Abort Address Register (ABDADR) records the address of D-AHB cacheable or bufferable
accesses that terminate with an AHB ERROR response when either or both DAOEN or DAGEN bits of
the ABCNTL register is set. It can only be updated with an address that generated the abort if the DAB
flag in the ABSR register is in the cleared state when the aborted access occurs. Once the address is
captured (the DAB flag in ABSR is also set then), it remains until the DAB flag in the ABSR register is
cleared by software writing a 1 to it. After the DAB flag is cleared this register is then allowed to latch the
address of the next aborted access. This register reads 0s when the DAB bit is cleared. Writing to this
register has no effect. This read-only register is cleared on reset. Figure 11-5 shows the register. Table 11-6
describes the register fields.
Offset 0x0008
31
Access: Supervisor read
30
29
28
27
26
R
25
24
23
22
21
20
19
18
17
16
DABORTADDR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
DABORTADDR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 11-5. ABDADR Register Diagram
Table 11-6. ABDADR Field Description
Name
Description
31–0
DABORTADDR
D-AHB Abort Address. Address of the first D-AHB aborted access before the DAB bit in the ABSR register
is set. The address can only be latched if either or both DAOEN or DAGEN bits in ABCNTL is set and the
DAB flag in ABSR register is cleared.
This value remains until the DAB bit is cleared. When DAB is cleared, these bits read as 0s until the next
occurrence of an abort data access, when the corresponding address is latched.
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ARM9 Platform AAPE
11.3
AAPE Functional Description
11.3.1
D-AHB Abort Tracking, Abort Forcing, and Data Override
Abort tracking on the D-AHB is enabled by setting either the DAOEN or DAGEN bit in the ABCNTL
register. Abort forcing is enabled by setting the DAGEN bit. Setting the DAOEN bit enables the data
override function on the D-AHB.
11.3.1.1
D-AHB Abort Tracking
The AAPE performs abort tracking on the D-AHB by:
• Identifying “taken” cacheable and/or bufferable accesses on D-AHB through the decoding of
dhprot[3:2] (either or both signals asserted), dhtrans[1] (asserted), and dhready (asserted),
• Identifying whether the access terminates with AHB ERROR monitoring the assertion of dhresp0,
• Setting the DAB abort flag DAB in the ABSR if an AHB ERROR occurs,
• Updating the ABDADR register with the address of the “taken” and aborted data access. A new
address can only be latched if the DAB bit has been cleared previously.
11.3.1.2
Abort Forcing On Aborted D-AHB Accesses
If abort forcing is enabled and abort tracking indicates a D-AHB ERROR response, the AAPE asserts the
aape_dabort signal until the ARM926EJS recognizes the abort and enters the abort mode. The abort
handler software can subsequently read the ABDADR register to obtain the address of the aborted data
access. The handler should also check the setting of DAB status flag, then clear it by writing a 1 to this bit.
Clearing the DAB bit allows a subsequent aborted address to be latched in the ABDADR register. Reading
the ABDADR register has no effect on the DAB status bit.
11.3.1.3
D-AHB Abort Data Override
If the data override function is enabled and abort tracking indicates a D-AHB ERROR response, the AAPE
drives zeros on the aape_dhrdata bus, that is, returning zeros to the aborted read access. This data
conforms to the normal set up and hold timing of the D-AHB bus. For reads that terminate normally, the
AAPE allows the value on the dhrdata data bus to flow through to the aape_dhrdata bus.
11.3.2
I-AHB Abort Tracking and Data Override
The abort tracking and data override functions on the I-AHB is enabled by setting the IAOEN in the
ABCNTL register.
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ARM9 Platform AAPE
11.3.2.1
I-AHB Abort Tracking
The AAPE performs abort tracking on the I-AHB by the following:
• Identifying cacheable and/or bufferable accesses on I-AHB through the decoding of ihprot[3:2]
(either or both signals asserted), ihtrans[1] (asserted), and ihready (asserted),
• Identifying whether the access terminates with AHB ERROR monitoring the assertion of ihresp0,
• Setting the IAB abort flag in the ABSR register.
11.3.2.2
I-AHB Abort Data Override
If abort tracking indicates an I-AHB ERROR response, the AAPE drives an SWI instruction on the
aape_ihrdata bus. Depending on the current mode of the ARM926EJ-S, a 32- bit SWI (ARM mode), two
16-bit SWI instructions for the upper and lower half words (THUMB), or four undefined instructions
(0xFF) are generated for each byte lane.
The ARM SWI has the opcode value 0xEF occupying bits [31:24], and a value of 16 in the comment field
(bits [23:0]. The THUMB SWI has the opcode value 0xDF occupying bits [15:8], and a value of 16 in the
comment field (bits [7:0]). When the SWI is eventually executed, the handler software loads the SWI
instruction and extract the comment value to identify an instruction fetch abort and branch to the proper
handler for further processing.
The following two code snippets illustrate how the SWI might be processed. The difference between the
two examples is due to the presence or absence of the ROMPATCH module which also makes use of the
SWI mechanism to perform opcode patching operations. The comment field values used by the
ROMPATCH range from 0 to 15.
11.3.2.2.1
Software Response to I-AHB Abort (No ROMPATCH Present)
stmfd
mrs
tst
ldrneh
bicne
ldreq
biceq
cmp
ldreq
ldrne
mov
bx
ldmfd
11.3.2.2.2
sp!, {r0-r1,lr}@ push register onto SWI stack
r0, spsr @ get saved status register
r0, #[email protected] check if call was in THUMB mode
r0, [lr,#-2]@ yes: load opcode half-word and
r0, r0, #[email protected] yes: extract THUMB comment
r0, [lr,#-4]@ no: load opcode word and
r0, r0, #[email protected] no: extract ARM comment
@ now r0 has comment field
r0, #16 @ compare to 16
r1, [email protected] = 16: pointer to I-AHB abort handler
r1, [email protected] != 16: pointer to standard SWI
@ handler
lr, pc
@ != 16: set link register
r1
@ != 16: jump to standard SWI
@ handler
sp!, {r0-r1,pc}^@ != 16: pop registers from stack
Software Response to I-AHB Abort (ROMPATCH Present)
stmfd
mrs
tst
ldrneh
bicne
sp!, {r0-r1,lr}@ push register onto SWI stack
r0, spsr @ get saved status register
r0, #[email protected] check if call was in THUMB mode
r0, [lr,#-2]@ yes: load opcode half-word and
r0, r0, #[email protected] yes: extract THUMB comment
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ARM9 Platform AAPE
ldreq
biceq
cmp
ldrlt
ldrlt
strlt
ldmltfd
ldreq
ldrgt
mov
bx
ldmfd
r0, [lr,#-4]@ no: load opcode word and
r0, r0, #[email protected] no: extract ARM comment
@ now r0 has comment field
r0, #16 @ compare to 16
lr, [email protected] < 16: get top of current ROMPATCH
@ table; global variable which is
@ changeable per context
r1, [lr, r0 lsl #2]@ < 16: read function pointer from
@ table assumed an array of pointers
@ patch functions
r1, [sp, #8]@ < 16: store function pointer onto
@ stack in position of link register
sp!, {r0-r1,pc}^@ < 16: "fake" return from SWI, will
@ vector core to appropriate patch
@ function and set core back to previous
@ mode of operating
r1, [email protected] = 16: pointer to I-AHB abort handler
r1, [email protected] > 16: pointer to standard SWI
@ handler
lr, pc
@ > 16: set link register
r1
@ > 16: jump to standard SWI
@ handler
sp!, {r0-r1,pc}^@ > 16: pop registers from stack
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Chapter 12
Advanced Technology Attachment (ATA)
12.1
Overview
The ATA block is an AT attachment host interface, which is compatible with the ATA-6 standard. Its main
use is to interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA
device over a number of ATA signals.
See Figure 12-1 for the block diagram of the ATA interface.
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Advanced Technology Attachment (ATA)
Timing
Parameters
ATA
Protocol
Engine
Control
Register
DMA
Bus
Bus
Interface
CPU
Bus
ata_reset_b
ata_dior
ata_diow
ata_cs1
ata_cs0
ata_da2
ata_da1
ata_da0
ata_dmarq
ata_dmack
ata_intrq
ata_iordy
ata_data[15:0]
Interrupt
Interface
FIFO
control
ata_buffer_en
FIFO
128 bytes
AHB
slave
AHB
Interface
ADMA
control
AHB_DMACTRL_INF
DMA
control
Figure 12-1. ATA Interface Block Diagram
In Figure 12-1, the CPU and DMA buses communicate with the host processor and host DMA unit,
respectively. The AHB bus enables direct transfers to and from external memory. All internal registers are
visible from both the CPU and DMA buses, allowing smart DMA access to program the interface.
Two access modes are possible over the ATA bus: PIO mode and DMA mode. There are also two types of
DMA mode: DMA slave mode (controlled by the host DMA) and DMA master mode (controlled by the
internal DMA master). See Section 12.1.2, “Modes of Operation,” for more information about these access
modes.
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Advanced Technology Attachment (ATA)
12.1.1
Features
The ATA interface includes the following features:
• Programmable timing on the ATA bus. Works with a wide range of bus frequencies.
• Compatible with ATA-6 specification
•
•
•
•
•
•
•
•
•
–
Supports PIO modes 0–4
–
Supports multiword DMA (MDMA) modes 0, 1, and 2
–
Supports ultra DMA (UDMA) modes 0–4 with a bus clock of at least 50 MHz
– Supports ultra DMA (UDMA) mode 5 with a bus clock of at least 80 MHz
128-byte FIFO included within the interface
FIFO receive, transmit, and end-of-transmission alarms to DMA unit
Zero-wait cycles transfer between DMA bus and FIFO (enables fast FIFO reads/writes)
Supports AMBA 2.0 specification
Supports 32-bit system memory addressing
Supports DMA reads/writes by IPS bus (DMA slave mode)
Supports single DMA reads and writes by the AHB bus (DMA master mode)
Supports scatter-gather (ADMA) DMA reads and writes by the AHB bus (DMA master mode)
Supports 4-words burst length set by software
12.1.2
Modes of Operation
The interface offers two alternative modes of operation, PIO mode and DMA mode (which includes DMA
slave and DMA master modes).
12.1.2.1
PIO Mode
An access to the ATA bus in PIO mode occurs whenever an ATA PIO register is read or written to by the
host CPU or the host (smart) DMA unit. During a PIO transfer, the incoming IP bus cycle is translated to
an ATA PIO bus cycle by the ATA protocol engine. No buffering of data occurs, so the host CPU or host
DMA cycle is stalled until the ATA bus read data is available on read, or is stalled until the IP bus data can
be put on the ATA bus during a write.
PIO accesses can be made at any time, even during a running ATA DMA transfer. In this case, the DMA
transfer is paused, the PIO cycle is completed, and the DMA transfer is resumed.
12.1.2.2
DMA Mode
In DMA mode, data is transferred between the ATA bus and the FIFO. Two different DMA protocols are
supported on the ATA bus: ultra DMA (UDMA) mode and multiword DMA (MDMA) mode. These are
described in more detail in the sections indicated below.
In DMA mode transfers, data is transferred between the ATA bus and the FIFO. Either the host smart DMA
unit or the internal DMA master is responsible to write/read data to/from the FIFO to keep the transfer
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Advanced Technology Attachment (ATA)
going. The case where the smart DMA unit is responsible is designated as DMA slave mode; while the
case where the internal DMA master is responsible is designated as DMA master mode.
In DMA slave mode, the fifo_rcv_alarm and fifo_tx_alarm signals are sent to the host DMA unit to avoid
FIFO overflow and underflow, respectively. An additional alarm signal (fifo_txfer_end_alarm) signals the
end of the transfer to the smart DMA, which then completes the transfer and informs the CPU. Further
details on these alarm signals are given in Section 12.4.3.6, “FIFO Alarm Register (FIFO_ALARM).”
In DMA master mode, prior to transfer, the DMA master must be programmed with the burst length, DMA
system start base address or ADMA descriptor table start address (if a descriptor table has been prepared),
and DMA mode. DMA transfer to the AHB bus is initiated when the DMA master receives the
sys_dma_req signal. Further details on DMA master mode operation are given in Section 12.5.6, “Using
DMA Master Mode to Receive Data From the ATA Bus,” and Section 12.5.7, “Using DMA Master Mode
To Transmit Data to the ATA bus.”
The typical packet size is 32 bytes (8 32-bit words), but other packet sizes can also be handled.
Further details on DMA mode may be found in the following sections:
• Section 12.5.4, “Receiving Data from ATA Bus in DMA Slave Mode”
• Section 12.5.5, “Transmitting Data to ATA Bus in DMA Slave Mode”
• Section 12.5.6, “Using DMA Master Mode to Receive Data From the ATA Bus”
• Section 12.5.7, “Using DMA Master Mode To Transmit Data to the ATA bus”
12.2
External Signal Description
Table 12-1 lists the signals between this module and peripherals within the chip.
Table 12-1. Signal Properties
Name
Function
Reset State
Type
ata_reset_b
ATA bus reset signal. Active low. If active, the ATA device is reset1.
0
out
ata_dior
ATA bus read strobe
1
out
ata_diow
ATA bus write strobe
1
out
ata_cs1
ATA bus chip select 1
1
out
ata_cs0
ATA bus chip select 0
1
out
ata_da2
ATA bus address line 2
0
out
ata_da1
ATA bus address line 1
0
out
ata_da0
ATA bus address line 0
0
out
ata_dmarq
ATA bus DMA request
—
in
ata_dmack
ATA bus DMA acknowledge
1
out
ata_intrq
ATA bus interrupt request
—
in
ata_iordy
ATA bus iordy
—
out
Hi-z
tristate in-out
ata_data[15:0]
ATA data bus (little-endian)
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Advanced Technology Attachment (ATA)
1
This signal is a standard ATA bus signal. It conforms with the ATA specification.
12.2.1
Signal Descriptions
For a detailed description of the ATA bus signals, see the ATA-6 specification.
12.2.1.1
ata_reset_b (out)
When negated, the ATA reset signal indicates the ATA bus is in reset state. The ATA bus is in reset
whenever the appropriate bit in the control register is cleared. After system reset, the ATA bus is reset.
12.2.1.2
ata_dior (out)
During PIO and MDMA transfers, the DIOR ATA signal functions as a read strobe. During UDMA data
in bursts, it functions as HDMARDY. During UDMA data out burst mode, it functions as host strobe.
12.2.1.3
ata_diow (out)
During PIO and MDMA transfers, the DIOW ATA signal functions as a write strobe. During UDMA burst
mode, it is used by the host terminate running UDMA transfers.
12.2.1.4
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0 (out)
The address group of the ATA bus consists of the chip selects ata_cs0 and ata_cs1, and the address lines
ata_da2, ata_da1, and ata_da0. All five lines follow the same timing.
12.2.1.5
ata_dmarq (in)
The ATA bus device DMA request is pulled high by the device if it wants to transfer data using MDMA
or UDMA mode.
12.2.1.6
ata_dmack (out)
The ATA bus host DMA acknowledge is pulled low by the host when it grants the DMA request.
12.2.1.7
ata_intrq (in)
The ATA bus interrupt request is pulled high by the device whenever it wants to interrupt the host CPU.
12.2.1.8
ata_iordy (in)
The ATA bus IORDY line has three functions:
• IORDY—Active low, wait during PIO cycles
• DDMARDY—Active low, device ready during UDMA out-transfers
• DSTROBE—Device strobe during UDMA in-transfers
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Advanced Technology Attachment (ATA)
12.2.1.9
ata_data[15:0] (in/out—tristate)
The ATA data bus signal carries data to/from the ATA device.
12.2.1.10 ata_buffer_en
When the buffer direction control signal is asserted, data is driven outward to the device; when negated,
data is driven inward to the host.
12.2.2
ATA Bus Timing
This section describes the ATA bus timing and explains how to ensure that the ATA interface meets timing
requirements. Timing diagrams and timing relation equations are provided.
12.2.2.1
Timing Parameters
Table 12-2 shows the ATA timing parameters and their determining factors. Determining factors include
the system design, the bus buffer used, the cable delay and the cable skew.
Table 12-2. Timing Parameters
Name
T
Meaning
Controlled by
Bus clock period
clock generator
ti_ds
Set-up time ata_data to ata_iordy edge (UDMA-in only)
top level design
ti_dh
hold time ata_iordy edge to ata_data (UDMA-in only)
top level design
tco
propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
top level design
tsu
set-up time ata_data to bus clock L-to-H
top level design
tsui
set-up time ata_iordy to bus clock H-to-L
top level design
thi
hold time ata_iordy to bus clock H to L
top level design
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
top level design
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write),
ata_buffer_en
tskew2
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write),
ata_buffer_en
transceiver
tskew3
Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read)
transceiver
Max buffer propagation delay
transceiver
tbuf
tcable1
cable propagation delay for ata_data
cable
tcable2
cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
cable
tskew4
Max difference in cable propagation delay between ata_iordy and ata_data (read)
cable
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Advanced Technology Attachment (ATA)
Table 12-2. Timing Parameters (continued)
Name
Meaning
Controlled by
tskew5
Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data (write)
cable
tskew6
Max difference in cable propagation delay without accounting for ground bounce
cable
12.2.2.2
12.2.2.2.1
PIO Mode Timing
PIO Read Mode Timing
A timing diagram for PIO read mode is given in Figure 12-2.
t1
t2r
t9
ADDR
(See note 1)
t5
DIOR
READ Data(15:0)
t6
tA
IORDY
IORDY
trd1
Figure 12-2. PIO Read Mode Timing
To meet timing requirements, a number of timing parameters must be controlled. Table 12-2 shows
relations between different timing parameters, and identifies parameters in the ATA timing registers which
may be programmed by the user to satisfy timing constraints (see Section 12.4.3.2, “Timing Registers”).
In Table 12-2 (and Table 12-3 below), the first column lists parameters from the ATA specification; the
second column refers to timing parameters shown in Figure 12-2; the third column shows the relation
between these timing parameters and programmable values; and the fourth column identifies the registers
that may be programmed to meet the timing relations.
Table 12-3. Timing Parameter Relations for PIO Read
PIO Read
ATA
Mode Timing
Parameter
Parameter1
Relation
Programmable Register
t1
t1
t1(min) = time_1 * T - (tskew1 + tskew2 + tskew5)
time_1
t2 (read)
t2r
t2(min) = time_2r * T - (tskew1 + tskew2 + tskew5)
time_2r
t9
t9
t9(min) = time_9 * T - (tskew1 + tskew2 + tskew6)
time_9
t5
t5
t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2
time_2 (affects tsu and tco)
tA
tA
tA(min) = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax
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Advanced Technology Attachment (ATA)
Table 12-3. Timing Parameter Relations for PIO Read (continued)
PIO Read
ATA
Mode Timing
Parameter
Parameter1
1
trd
trd1
t0
—
Relation
Programmable Register
trd1(max) = (-trd)+ (tskew3 + tskew4)
trd1(min) = (time_pio_rdx - 0.5)*T - (tsu + thi)
(time_pio_rdx - 0.5) * T > tsu + thi + tskew3 + tskew4
time_pio_rdx
t0(min) = (time_1 + time_2r+ time_9) * T
time_1, time_2r, time_9
See Figure 12-2.
12.2.2.2.2
PIO Write Mode Timing
A timing diagram for PIO write mode is given in Figure 12-3.
t1
t2w
t9
ADDR
(See note 1)
DIOR
DIOW
buffer_en
Write Data(15:0)
ton
tB t4 toff
tA
t1
IORDY
IORDY
Figure 12-3. PIO Write Mode Timing
Table 12-4 shows relations between timing parameters, and identifies parameters in the ATA timing
registers which may be programmed by the user to meet timing constraints (see Section 12.4.3.2, “Timing
Registers”).
Table 12-4. Timing Parameters Relations for PIO Write
ATA
Parameter
PIO Write Mode Timing
Parameter1
t1
t1
t2 (write)
t2w
t9
Programmable
Value
Relation
t1(min) = time_1 * T - (tskew1 + tskew2 + tskew5)
time_1
t2(min) = time_2w * T - (tskew1 + tskew2 + tskew5)
time_2w
t9
t9(min) = time_9 * T - (tskew1 + tskew2 + tskew6)
time_9
t3
—
t3(min) = (time_2w - time_on)* T - (tskew1 + tskew2 +tskew5)
if not met,
increase
time_2w
t4
t4
t4(min) = time_4 * T - tskew1
time_4
tA
tA
tA = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax
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Advanced Technology Attachment (ATA)
Table 12-4. Timing Parameters Relations for PIO Write (continued)
1
ATA
Parameter
PIO Write Mode Timing
Parameter1
t0
—
t0(min) = (time_1 + time_2 + time_9) * T
—
—
Avoid bus contention when switching buffer on by making ton
long enough
—
—
—
Avoid bus contention when switching buffer off by making toff
long enough
—
Programmable
Value
Relation
time_1, time_2r,
time_9
See Figure 12-3.
12.2.2.3
Timing in Multiword DMA (MDMA) Mode
Figure 12-4 and Figure 12-5 show read and write timings respectively for MDMA mode.
tk1
DMARQ
ADDR
(See note 1)
DMACK
DIOR
tm
READ Data(15:0)
td
tk
te
tgr
tkjn
tfr
Figure 12-4. MDMA Read Timing
tk1
DMARQ
ADDR
(See note 1)
DMACK
buffer_en
DIOW
tm ton td1
tk
td
tkjn toff
Write Data(15:0)
Figure 12-5. MDMA Write Timing
To meet timing requirements for MDMA mode, a number of timing parameters must be controlled.
Table 12-5 shows the relations between different timing parameters, and identifies parameters in the ATA
timing registers which may be programmed by the user to satisfy timing constraints (see Section 12.4.3.2,
“Timing Registers”).
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Advanced Technology Attachment (ATA)
In Table 12-5, the first column lists parameters from the ATA specification; the second column refers to
timing parameters shown in Figure 12-4 and Figure 12-5; the third column shows the relation between
these timing parameters and programmable values; and the fourth column identifies the registers which
may be programmed to meet timing constraints.
Table 12-5. Timing Parameter Relations for MDMA Read and Write
ATA
Parameter
MDMA Read Timing1 and
MDMA Write Timing2
tm, ti
tm
tm(min) = ti(min) = time_m * T - (tskew1 + tskew2 + tskew5)
time_m
td
td, td1
td1(min) = td(min) = time_d * T - (tskew1 + tskew2 + tskew6)
time_d
tk
tk3
tk(min) = time_k * T - (tskew1 + tskew2 + tskew6)
time_k
t0
—
t0(min) = (time_d + time_k) * T
time_d, time_k
tg (read)
tgr
tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr(min-drive) = td - te(drive)
time_d
tf (read)
tfr
tfr(min) = 5 ns
(met by design)
tg(write)
—
tg(min-write) = time_d * T -(tskew1 + tskew2 + tskew5)
time_d
tf(write)
—
tf(min-write) = time_k * T - (tskew1 + tskew2 + tskew6)
time_k
tL
—
tL(max) = (time_d + time_k-2)*T - (tsu + tco + 2*tbuf +
2*tcable2)
time_d, time_k4
tn, tj
tkjn
tn= tj= tkjn = time_jn * T - (tskew1 + tskew2 + tskew6)
time_jn
—
ton
toff
ton = time_on * T - tskew1
toff = time_off * T - tskew1
Programmable
Value
Relation
—
1
See Figure 12-4.
See Figure 12-5.
3 tk1 in the MDMA figures (Figure 12-4 and Figure 12-5) equals (tk -2*T)
4 tk1 in the MDMA figures equals (tk -2*T)
2
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-10
Freescale Semiconductor
Advanced Technology Attachment (ATA)
12.2.2.4
Timing for Ultra DMA (UDMA) Data In-Transfers
Figure 12-6 shows timing for the start of a UDMA data in-transfer.
tack
ADDR
DMARQ
DMACK
tenv
DIOR
DIOW
tc1
tc1
IORDY
DATA READ
tds
tdh
Figure 12-6. Timing for Start of UDMA Data In-transfer
Figure 12-7 shows timing for host termination of a UDMA data in-transfer.
ADDR
tack
DMARQ
DMACK
DIOR
trp
DIOW
tc1
tc1
tmli
tx1
IORDY
tmli
DATA READ
tds
tdh
tzah
tzah
ton tdzfs tcvh
toff
DATA WRITE
buffer_en
Figure 12-7. Timing for Host Termination of UDMA Transfer
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
12-11
Advanced Technology Attachment (ATA)
Figure 12-8 shows timing for device termination of a UDMA data in-transfer.
ADDR
tack
DMARQ
DMACK
DIOR
DIOW
tmli
tc1
tc1 tss1 tli5
IORDY
tmli
DATA READ
tds
tdh
tzah
tzah
ton tdzfs tcvh
toff
DATA WRITE
buffer_en
Figure 12-8. Timing for Device Termination of a UDMA Transfer
Timing parameters for UDMA data in-bursts are listed in Table 12-6. The UDMA in-burst timing
parameters listed in the second column refer to Figure 12-6 through Figure 12-8.
Table 12-6. Timing Parameter Relations for UDMA Data In-Bursts
ATA Parameter
UDMA In-burst
Timing Parameter
tack
tack
tack(min) = (time_ack * T) - (tskew1 + tskew2)
time_ack
tenv
tenv
tenv(min) = (time_env * T) - (tskew1 + tskew2)
tenv(max) = (time_env * T) + (tskew1 + tskew2)
time_env
trp
trp
trp(min) = time_rp * T - (tskew1 + tskew2 + tskew6)
time_rp
1
Relation
Programmable
Value
(time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive) time_rp
—
tx1
tmli
tmli1
tmli1(min) = (time_mlix + 0.4) * T
time_mlix
tzah
tzah
tzah(min) = (time_zah + 0.4) * T
time_zah
tdzfs
tdzfs
tdzfs = (time_dzfs * T) - (tskew1 + tskew2)
time_dzfs
tcvh
tcvh
tcvh = (time_cvh *T) - (tskew1 + tskew2)
time_cvh
—
ton
toff2
ton = time_on * T - tskew1
toff = time_off * T - tskew1
—
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2
Make ton and toff big enough to avoid bus contention.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-12
Freescale Semiconductor
Advanced Technology Attachment (ATA)
12.2.2.5
Timing for UDMA Data Out-Transfers
Figure 12-9 shows the timing for the start of a UDMA data out-transfer.
tack
ADDR
DMARQ
DMACK
tenv
DIOW
DIOR
buffer_en
tcyc
ton
tcyc
tdzfs tdvs tdvh tdvs
DATA WRITE
tli1
IORDY
trfs1
Figure 12-9. Timing of Start of UDMA Data Out-Transfer
Figure 12-10 shows the timing for host termination of a UDMA data out-transfer.
ADDR
tack
DMARQ
DMACK
DIOW
tss
DIOR
tcyc
tli2
tcyc1
tdzfs_mli tcvh
toff
DATA WRITE
IORDY
tli3
buffer_en
Figure 12-10. Timing of Host Termination of UDMA Data Out-Transfer
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
12-13
Advanced Technology Attachment (ATA)
Figure 12-11 shows timing for device termination of a UDMA data out-transfer.
ADDR
tack
DMARQ
tli2
DMACK
DIOW
DIOR
tcyc
trfs1
tdzfs_mli tcvh
toff
DATA WRITE
IORDY
buffer_en
Figure 12-11. Timing for Device Termination of UDMA Data Out-Transfer
Timing parameters and relations for UDMA data out-bursts are listed in Table 12-7. The UDMA out-burst
timing parameters listed in the second column refer to Figure 12-9, Figure 12-10, and Figure 12-11.
Table 12-7. Timing Parameters and Relations for UDMA Out-Burst
ATA Parameter
UDMA Out-burst
Timing Parameter
Programmable
Value
tack
tack
tack(min) = (time_ack * T) - (tskew1 + tskew2)
time_ack
tenv
tenv
tenv(min) = (time_env * T) - (tskew1 + tskew2)
tenv(max) = (time_env * T) + (tskew1 + tskew2)
time_env
tdvs
tdvs
tdvs = (time_dvs * T) - (tskew1 + tskew2)
time_dvs
tdvh
tdvh
tdvs = (time_dvh * T) - (tskew1 + tskew2)
time_dvh
tcyc
tcyc
tcyc = time_cyc * T - (tskew1 + tskew2)
time_cyc
t2cyc
—
t2cyc = time_cyc * 2 * T
time_cyc
trfs1
trfs
trfs = 1.6 * T + tsui + tco + tbuf + tbuf
—
tdzfs
tss
tss
tmli
tdzfs_mli
tli
Timing Relation
—
tdzfs = time_dzfs * T - (tskew1)
time_dzfs
tss = time_ss * T - (tskew1 + tskew2)
time_ss
tdzfs_mli =max(time_dzfs, time_mli) * T - (tskew1 + tskew2)
—
tli1
tli1 > 0
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
tcvh
tcvh = (time_cvh *T) - (tskew1 + tskew2)
—
ton
toff
ton = time_on * T - tskew1
toff = time_off * T - tskew1
time_cvh
—
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-14
Freescale Semiconductor
Advanced Technology Attachment (ATA)
12.3
Advanced DMA in DMA Master Mode
Two optional DMA algorithms are supported for the Host Controller in DMA master mode:
• Single DMA (SDMA): After an SDMA transfer command is completed, a DMA interrupt is
generated and the new system address is programmed by the Host Driver. The 32-bit System
Address Register is used as a data pointer and limited to 32-bit system memory addressing.
• Advanced DMA (ADMA): ADMA defines a programmable descriptor table in the system
memory. The Host Driver can calculate the system address at the sector boundary and programs
the descriptor table before executing ADMA. This reduces the frequency of interrupts to the host
system, and higher speed DMA transfer is realized because a Host CPU intervention is not needed
during a long DMA-based data transfer. Furthermore, ADMA can support 32-bit or 64-bit system
memory addressing. In ADMA, the 64-bit ADMA System Address Register is used as a Descriptor
pointer instead of the 32-bit System Address Register.
Figure 12-12. Host Controller Block Diagram
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
12-15
Advanced Technology Attachment (ATA)
Figure 12-13. 32-Bit Descriptor Table Definition
NOTE
Data length is specified in the same way as the transfer Sector Size of the
Sector Size Register. For example, 0x0001 indicates 1 byte, 0x0200
indicates 512 bytes, and so on. The data length should be a multiple of the
sector size.
Figure 12-14. State Diagram for ADMA
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-16
Freescale Semiconductor
Advanced Technology Attachment (ATA)
12.4
Memory Map and Register Definitions
12.4.1
Memory Map
Table 12-8 shows the ATA memory map.
Table 12-8. ATA Memory Map
Register
Description
Access
Reset
Value
Section/Page
Offset: 00 (TIME_OFF)
TIME_OFF
transceiver timing parameter. Controls
toff
R/W
0x01
12.4.3.2.1/12-24
Offset: 01 (TIME_ON)
TIME_ON
transceiver timing parameter. Controls
ton
R/W
0x01
12.4.3.2.2/12-24
TIME_1
PIO timing parameter. Controls t1
R/W
0x01
12.4.3.2.3/12-25
Offset: 03 (TIME_2W)
TIME_2W
PIO timing parameter. Controls t2
during write cycles
R/W
0x01
12.4.3.2.4/12-25
Offset: 04 (TIME_2R)
TIME_2R
PIO timing parameter. Controls t2
during read cycles
R/W
0x01
12.4.3.2.5/12-25
Offset: 05 (TIME_AX)
TIME_AX
PIO timing parameter. Controls tA
R/W
0x01
12.4.3.2.6/12-25
TIME_PIO_RDX
PIO timing parameter. Controls trd
R/W
0x01
12.4.3.2.7/12-26
Offset: 07 (TIME_4)
TIME_4
PIO timing parameter. Controls t4
R/W
0x01
12.4.3.2.8/12-26
Offset: 08 (TIME_9)
TIME_9
PIO timing parameter. Controls t9
R/W
0x01
12.4.3.2.9/12-26
Offset: 09 (TIME_M)
TIME_M
MDMA timing parameter. Controls tm
R/W
0x01
12.4.3.2.10/12-26
Offset: 0A (TIME_JN)
TIME_JN
MDMA timing parameter. Controls tn
and tj
R/W
0x01
12.4.3.2.11/12-27
Offset: 0B (TIME_D)
TIME_D
MDMA timing parameter. Controls td
R/W
0x01
12.4.3.2.12/12-27
Offset: 0C (TIME_K)
TIME_K
MDMA timing parameter. Controls tk
R/W
0x01
12.4.3.2.13/12-27
Offset: 0D (TIME_ACK)
TIME_ACK
UDMA timing parameter. Controls tack
R/W
0x01
12.4.3.2.14/12-27
Offset: 0E (TIME_ENV)
TIME_ENV
UDMA timing parameter. Controls tenv
R/W
0x01
12.4.3.2.15/12-28
Offset: 0F (TIME_RPX)
TIME_RPX
UDMA timing parameter. Controls trp
R/W
0x01
12.4.3.2.16/12-28
Offset: 10 (TIME_ZAH)
TIME_ZAH
UDMA timing parameter. Controls tzah
R/W
0x01
12.4.3.2.17/12-28
Offset: 11 (TIME_MLIX)
TIME_MLIX
UDMA timing parameter. Controls tmli
R/W
0x01
12.4.3.2.18/12-28
Offset: 12 (TIME_DVH)
TIME_DVH
UDMA timing parameter. Controls tdvh
R/W
0x01
12.4.3.2.19/12-29
Offset: 13 (TIME_DZFS)
TIME_DZFS
UDMA timing parameter. Controls tdzfs
R/W
0x01
12.4.3.2.20/12-29
Offset: 14 (TIME_DVS)
TIME_DVS
UDMA timing parameter. Controls tdvs
R/W
0x01
12.4.3.2.21/12-29
Offset: 15 (TIME_CVH)
TIME_CVH
UDMA timing parameter. Controls tcvh
R/W
0x01
12.4.3.2.22/12-29
TIME_SS
UDMA timing parameter. Controls tss
R/W
0x01
12.4.3.2.23/12-30
TIME_CYC
UDMA timing parameter. Controls tcyc
and t2cyc
R/W
0x01
12.4.3.2.24/12-30
Address
Offset: 02 (TIME_1)
Offset: 06 (TIME_PIO_RDX)
Offset: 16 (TIME_SS)
Offset: 17 (TIME_CYC)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
12-17
Advanced Technology Attachment (ATA)
Table 12-8. ATA Memory Map (continued)
Address
Register
Description
Access
Reset
Value
Section/Page
Offset: 1C (FIFO_DATA_16)
FIFO_DATA_16
16 bit wide data port to/from FIFO
R/W
0x00
12.4.3.3.1/12-30
Offset: 18 (FIFO_DATA_32)
FIFO_DATA_32
32 bit wide data port to/from FIFO
R/W
0x000
0
12.4.3.3.1/12-30
FIFO_FILL
FIFO filling in halfwords
Read
only
0x00
12.4.3.3.2/12-31
ATA_CONTROL
ATA interface control register
R/W
0x00
12.4.3.4/12-31
Offset: 28
(INTERRUPT_PENDING)
INTERRUPT_
PENDING
Interrupt pending register
Read
only
0x1–1
12.4.3.5.1/12-33
Offset: 2C
(INTERRUPT_ENABLE)
INTERRUPT_
ENABLE
Interrupt enable register
R/W
0x0–1
12.4.3.5.2/12-34
INTERRUPT_CLEAR
Interrupt clear register
Write
only
0x––1
12.4.3.5.3/12-35
FIFO_ALARM
FIFO alarm threshold
R/W
0x00
12.4.3.6/12-36
ADMA_ERR_STATUS
ADMA error status register
Read
only
0x00
12.4.3.7/12-36
Offset: 3C
(SYS_DMA_BADDR)
SYS_DMA_BADDR
single DMA transfer start base
address
R/W
0x00
12.4.3.8/12-37
Offset: 40
(ADMA_SYS_ADDR)
ADMA_SYS_ADDR
ADMA descriptor table start address
R/W
0x00
12.4.3.9/12-38
BLOCK_CNT
sector number for DMA transfer
R/W
0x00
12.4.3.10/12-39
BURST_LENGTH
burst length for a burst transfer on
AHB
R/W
0x10
12.4.3.11/12-39
Offset: 50 (SECTOR_SIZE)
SECTOR_SIZE
sector size for device
R/W
0x200
12.4.3.12/12-39
Offset: A02 (DRIVE_DATA)
DRIVE_DATA
drive data register
16-bit
RW
—
12.4.3.13/12-40
DRIVE_FEATURES
drive features register
R/W
—
12.4.3.13/12-40
drive sector count register
R/W
—
12.4.3.13/12-40
DRIVE_SECTOR_NU
M
drive sector number register
R/W
—
12.4.3.13/12-40
Offset: B0
(DRIVE_CYL_LOW)
DRIVE_CYL_LOW
drive cylinder low register
R/W
—
12.4.3.13/12-40
Offset: B4
(DRIVE_CYL_HIGH)
DRIVE_CYL_HIGH
drive cylinder high register
R/W
—
12.4.3.13/12-40
Offset: B8
(DRIVE_DEV_HEAD)
DRIVE_DEV_HEAD
drive device head register
R/W
—
12.4.3.13/12-40
Offset: BC3
(DRIVE_COMMAND)
DRIVE_COMMAND
drive command register
Write
only
—
12.4.3.13/12-40
Offset: 20 (FIFO_FILL)
Offset: 24 (ATA_CONTROL)
Offset: 30
(INTERRUPT_CLEAR)
Offset: 34 (FIFO_ALARM)
Offset: 38
(ADMA_ERR_STATUS)
Offset: 48 (BLOCK_CNT)
Offset: 4C
(BURST_LENGTH)
Offset: A4
(DRIVE_FEATURES)
Offset: A8
DRIVE_SECTOR_CO
(DRIVE_SECTOR_COUNT)
UNT
Offset: AC
(DRIVE_SECTOR_NUM)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-18
Freescale Semiconductor
Advanced Technology Attachment (ATA)
Table 12-8. ATA Memory Map (continued)
Address
Section/Page
Read
only
—
12.4.3.13/12-40
Drive alternate status register
Read
only
—
12.4.3.13/12-40
Drive control register
Write
only
—
12.4.3.13/12-40
Description
Access
DRIVE_STATUS
drive status register
DRIVE_ALT_STATUS
DRIVE_CONTROL
Offset: BC
(DRIVE_STATUS)
Offset: D84
(DRIVE_ALT_STATUS)
Reset
Value
Register
Offset: D8
(DRIVE_CONTROL)
1
Dashes in “Reset Value” column indicate that some bits in the register have no reset value.
An access at offset A0 reads or writes the 16-bit drive data register.
3
The drive command and drive status registers are both at offset BC. A write at offset BC accesses the drive command register,
while a read at the same offset accesses the drive status register.
4 The drive alternate status and drive control registers are both at offset D8. A write at offset D8 accesses the drive control register,
while a read at the same offset accesses the drive alternate status register.
2
12.4.2
Register Summary
Figure 12-15 shows the key to the register fields and Table 12-9 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT Writebit
only bit
only bit
Write 1 BIT Self-clear 0
to clear
bit
BIT
w1c
BIT
N/A
Figure 12-15. Key to Register Fields
Table 12-9. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
slfclr
Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero.
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
12-19
Advanced Technology Attachment (ATA)
Table 12-9. Register Figure Conventions (continued)
Convention
u
Description
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
Table 12-10 summarizes the ATA registers. The registers at offsets A0 through D8 are addressable, but not
present in the ATA interface module. These registers are not included in Table 12-10—they are described
in Section 12.4.3.13, “Drive Registers Connected to ATA Bus.”
Table 12-10. ATA Register Summary
Name
Offset: 00 (TIME_OFF)
7
R
6
5
4
3
2
1
0
TIME_OFF[7:0]
W
Offset: 01 (TIME_ON)
R
TIME_ON[7:0]
W
Offset: 02 (TIME_1)
R
TIME_1[7:0]
W
Offset: 03 (TIME_2W)
R
TIME_2W[7:0]
W
Offset: 04 (TIME_2R)
R
TIME_2R[7:0]
W
Offset: 05 (TIME_AX)
R
TIME_AX[7:0]
W
Offset: 06 (TIME_PIO_RDX)
R
TIME_RDX[7:0]
W
Offset: 07 (TIME_4)
R
TIME_4[7:0]
W
Offset: 08 (TIME_9)
R
TIME_9[7:0]
W
Offset: 09 (TIME_M)
R
TIME_M[7:0]
W
Offset: 0A (TIME_JN)
R
TIME_JN[7:0]
W
Offset: 0B (TIME_D)
R
TIME_D[7:0]
W
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-20
Freescale Semiconductor
Advanced Technology Attachment (ATA)
Table 12-10. ATA Register Summary (continued)
Name
7
Offset: 0C (TIME_K)
6
5
4
R
3
2
1
0
TIME_K[7:0]
W
Offset: 0D (TIME_ACK)
R
TIME_ACK[7:0]
W
Offset: 0E (TIME_ENV)
R
TIME_ENV[7:0]
W
Offset: 0F (TIME_RPX)
R
TIME_RPX[7:0]
W
Offset: 10 (TIME_ZAH)
R
TIME_ZAH[7:0]
W
Offset: 11 (TIME_MLIX)
R
TIME_MLIX[7:0]
W
Offset: 12 (TIME_DVH)
R
TIME_DVH[7:0]
W
Offset: 13 (TIME_DZFS)
R
TIME_DZFS[7:0]
W
Offset: 14 (TIME_DVS)
R
TIME_DVS[7:0]
W
Offset: 15 (TIME_CVH)
R
TIME_CVH[7:0]
W
Offset: 16 (TIME_SS)
R
TIME_SS[7:0]
W
Offset: 17 (TIME_CYC)
R
TIME_CYC[7:0]fifo_data[15:0]
W
Name
Offset: 1C
(FIFO_DATA_16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
fifo_data[15:0]
W
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
12-21
Advanced Technology Attachment (ATA)
Table 12-10. ATA Register Summary (continued)
Name
Name
Offset: 18
(FIFO_DATA_32)
7
6
5
4
3
2
1
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
fifo_data[23:16]
W
R
fifo_data[15:0]
W
Name
Offset: 20 (FIFO_FILL)
7
6
5
R
4
3
2
1
0
10
9
8
dma_st
art_sto
p
dma_e
nable
FIFO_FILL[7:0]
W
Name
Offset: 24 (ATA_CONTROL)
15
14
13
R
dma_sr
st
W
R
W
Name
Offset: 28 (INTERRUPT_PENDING)
R
12
7
6
5
fifo_rst
_b
ata_rst
_b
7
6
5
ata_
intrq1
fifo_
underflow
ata_
intrq1
4
11
dma_sel
3
2
1
0
dma_
pending
dma_ul
tra_selected
dma_
write
iordy_
en
4
3
2
1
0
fifo_
overflow
controll
er_
idle
ata_
irtrq2
dma_tr
dma_er
ans_ov
r
er
fifo_
underflow
fifo_
overflow
controll
er_
idle
ata_
irtrq2
dma_tr
dma_er
ans_ov
r
er
fifo_
underfl
ow
fifo_
overflo
w
fifo_tx_ fifo_rcv
en
_en
W
Offset: 2C (INTERRUPT_ENABLE)
R
W
Offset: 30 (INTERRUPT_CLEAR)
R
W
Offset: 34 (FIFO_ALARM)
R
dma_er dma_tr
r
ans_ov
er
FIFO_ALARM[7:0]
W
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
12-22
Freescale Semiconductor
Advanced Technology Attachment (ATA)
Table 12-10. ATA Register Summary (continued)
Name
7
6
5
4
3
R
W
Offset: 3C
(SYS_DMA_BAD
DR)
1
adma_l
en_mis
match
Offset: 38 (ADMA_ERR_STATUS)
Name
2
0
adma_err_state
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
sys_dma_baddr[15:0]
W
R
sys_dma_baddr[31:16]
W
Offset: 40
(ADMA_SYS_AD
DR)
R
adma_sys_addr[15:0]
W
R
adma_sys_addr[31:16]
W
Name
Offset: 48
(BLOCK_CNT)
Offset: 4C
(BURST_LENGT
H)
Offset: 50
(SECTOR_SIZE)
12.4.3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
block_cnt
W
R
burst_length[5:0]
W
R
sector_size
W
Register Descriptions
This section contains the detailed register descriptions for the ATA registers.
12.4.3.1
Byte Order
The ATA interface works both in little-endian or big-endian mode. The addresses of all registers are the
same in either mode. The 16-bit and 32-bit registers represent strings of 2 or 4 bytes. The byte order in the
16-bit or 32-bit register is dependent on the mode selection.
•
Little-endian mode, 16- or 32-bit register:
–
bits [7:0]: byte 0
–
bits [15:8]: byte 1
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Advanced Technology Attachment (ATA)
–
bits [23:8]: byte 2
– bits [31:24]: byte 3
• Big-endian mode, 32-bit register
•
–
bits [31:24]: byte 0
–
bits [23:16]: byte 1
–
bits [15:8]: byte 2
– bits [7:0]: byte 3
Big-endian, 16-bit register
–
bits [15:8]: byte 0
–
bits [7:0]: byte 1
12.4.3.2
Timing Registers
The registers at offsets 0x00 through 0x17 contain timing parameters. These timing parameters control the
timing on the ATA bus.
Every timing parameter is 8 bits wide and can assume valid values between 0x01 and 0xFF. The reset value
for all registers is 0x01.
12.4.3.2.1
TIME_OFF Register
Figure 12-16 shows the valid bits in the TIME_OFF register, and Table 12-8 describes the bit fields.
Offset: 00 (TIME_OFF)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_OFF[7:0]
W
RESET
0
0
0
0
0
Figure 12-16. TIME_OFF Register
12.4.3.2.2
TIME_ON Register
Figure 12-17 shows the valid bits in the TIME_ON register, and Table 12-8 describes the bit fields.
Offset: 01 (TIME_ON)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_ON[7:0]
W
RESET
0
0
0
0
0
Figure 12-17. TIME_ON Register
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12.4.3.2.3
TIME_1 Register
Figure 12-18 shows the valid bits in the TIME_1 register, and Table 12-8 describes the bit fields.
Offset: 02 (TIME_1)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_1[7:0]
W
RESET
0
0
0
0
0
Figure 12-18. TIME_1 Register
12.4.3.2.4
TIME_2W Register
Figure 12-19 shows the valid bits in the TIME_2W register, and Table 12-8 describes the bit fields.
Offset: 03 (TIME_2W)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_2W[7:0]
W
RESET
0
0
0
0
0
Figure 12-19. TIME_2W Register
12.4.3.2.5
TIME_2R Register
Figure 12-20 shows the valid bits in the TIME_2R register, and Table 12-8 describes the bit fields.
Offset: 04 (TIME_2R)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_2R[7:0]
W
RESET
0
0
0
0
0
Figure 12-20. TIME_2R Register
12.4.3.2.6
TIME_AX Register
Figure 12-21 shows the valid bits in the TIME_AX register, and Table 12-8 describes the bit fields.
Offset: 05 (TIME_AX)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_AX[7:0]
W
RESET
0
0
0
0
0
Figure 12-21. TIME_AX Register
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Advanced Technology Attachment (ATA)
12.4.3.2.7
TIME_PIO_RDX Register
Figure 12-22 shows the valid bits in the TIME_PIO_RDX register, and Table 12-8 describes the bit fields.
Offset: 06 (TIME_PIO_RDX)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_RDX[7:0]
W
RESET
0
0
0
0
0
Figure 12-22. TIME_PIO_RDX Register
12.4.3.2.8
TIME_4 Register
Figure 12-23 shows the valid bits in the TIME_4 register, and Table 12-8 describes the bit fields.
Offset: 07 (TIME_4)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_4[7:0]
W
RESET
0
0
0
0
0
Figure 12-23. TIME_4 Register
12.4.3.2.9
TIME_9 Register
Figure 12-24 shows the valid bits in the TIME_9 register, and Table 12-8 describes the bit fields.
Offset: 08 (TIME_9)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_9[7:0]
W
RESET
0
0
0
0
0
Figure 12-24. TIME_9 Register
12.4.3.2.10 TIME_M Register
Figure 12-25 shows the valid bits in the TIME_M register, and Table 12-8 describes the bit fields.
Offset: 09 (TIME_M)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_M[7:0]
W
RESET
0
0
0
0
0
Figure 12-25. TIME_M
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12.4.3.2.11 TIME_JN Register
Figure 12-26 shows the valid bits in the TIME_JN register, and Table 12-8 describes the bit fields.
Offset: 0A (TIME_JN)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_JN[7:0]
W
RESET
0
0
0
0
0
Figure 12-26. TIME_JN Register
12.4.3.2.12 TIME_D Register
Figure 12-27 shows the valid bits in the TIME_D register, and Table 12-8 describes the bit fields.
Offset: 0B (TIME_D)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_D[7:0]
W
RESET
0
0
0
0
0
Figure 12-27. TIME_D Register
12.4.3.2.13 TIME_K Register
Figure 12-28 shows the valid bits in the TIME_K register, and Table 12-8 describes the bit fields.
Offset: 0C (TIME_K)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_K[7:0]
W
RESET
0
0
0
0
0
Figure 12-28. TIME_K Register
12.4.3.2.14 TIME_ACK Register
Figure 12-29 shows the valid bits in the TIME_ACK register, and Table 12-8 describes the bit fields.
Offset: 0D (TIME_ACK)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_ACK[7:0]
W
RESET
0
0
0
0
0
Figure 12-29. TIME_ACK Register
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12.4.3.2.15 TIME_ENV Register
Figure 12-30 shows the valid bits in the TIME_ENV register, and Table 12-8 describes the bit fields.
Offset: 0E (TIME_ENV)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_ENV[7:0]
W
RESET
0
0
0
0
0
Figure 12-30. TIME_ENV Register
12.4.3.2.16 TIME_RPX Register
Figure 12-31 shows the valid bits in the TIME_RPX register, and Table 12-8 describes the bit fields.
Offset: 0F (TIME_RPX)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_RPX[7:0]
W
RESET
0
0
0
0
0
Figure 12-31. TIME_RPX Register
12.4.3.2.17 TIME_ZAH Register
Figure 12-32 shows the valid bits in the TIME_ZAH register, and Table 12-8 describes the bit fields.
Offset: 10 (TIME_ZAH)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_ZAH[7:0]
W
RESET
0
0
0
0
0
Figure 12-32. TIME_ZAH Register
12.4.3.2.18 TIME_MLIX Register
Figure 12-33 shows the valid bits in the TIME_MLIX register, and Table 12-8 describes the bit fields.
Offset: 11 (TIME_MLIX)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_MLIX[7:0]
W
RESET
0
0
0
0
0
Figure 12-33. TIME_MLIX
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12.4.3.2.19 TIME_DVH Register
Figure 12-34 shows the valid bits in the TIME_DVH register, and Table 12-8 describes the bit fields.
Offset: 12 (TIME_DVH)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_DVH[7:0]
W
RESET
0
0
0
0
0
Figure 12-34. TIME_DVH Register
12.4.3.2.20 TIME_DZFS Register
Figure 12-35 shows the valid bits in the TIME_DZFS register, and Table 12-8 describes the bit fields.
Offset: 13 (TIME_DZFS)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_DZFS[7:0]
W
RESET
0
0
0
0
0
Figure 12-35. TIME_DZFS Register
12.4.3.2.21 TIME_DVS Register
Figure 12-36 shows the valid bits in the TIME_DVS register, and Table 12-8 describes the bit fields.
Offset: 14 (TIME_DVS)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_D[7:0]
W
RESET
0
0
0
0
0
Figure 12-36. TIME_DVS
12.4.3.2.22 TIME_CVH Register
Figure 12-37 shows the valid bits in the TIME_CVH register, and Table 12-8 describes the bit fields.
Offset: 15 (TIME_CVH)
7
Access: User read/write
6
5
R
4
3
2
1
0
0
0
1
TIME_CVH[7:0]
W
RESET
0
0
0
0
0
Figure 12-37. TIME_CVH Register
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12.4.3.2.23 TIME_SS Register
Figure 12-38 shows the valid bits in the TIME_SS register, and Table 12-8 describes the bit fields.
Offset: 16 (TIME_SS)
Access: User read/write
7
6
5
4
R
3
2
1
0
0
0
1
TIME_SS[7:0]
W
RESET
0
0
0
0
0
Figure 12-38. TIME_SS Register
12.4.3.2.24 TIME_CYC Register
Figure 12-39 shows the valid bits in the TIME_CYC register, and Table 12-8 describes the bit fields.
Offset: 17 (TIME_CYC)
Access: User read/write
7
6
5
4
R
3
2
1
0
0
0
1
TIME_CYC[7:0]
W
RESET
0
0
0
0
0
Figure 12-39. TIME_CYC
12.4.3.3
12.4.3.3.1
FIFO Data Registers
FIFO_Data Register in 16-bit and 32-bit Modes (FIFO_DATA_16,
FIFO_DATA_32)
The FIFO_DATA register is used to read or write data to the internal FIFO. It can be accessed as a 16-bit
register or as a 32-bit register. Word writes (respectively long writes) put two bytes (respectively four
bytes) into the FIFO. Word reads (respectively long reads) read two bytes (respectively four bytes) from
the FIFO.
Figure 12-40 shows the valid bits in the FIFO_Data Register in 16-bit mode.
Offset: 1C (FIFO_DATA_16)
15
14
13
12
Access: User read/write
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
FIFO_DATA[15:0]
W
RESET
—
—
—
—
—
—
—
—
—
Figure 12-40. FIFO_Data Register In 16-bit Mode
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Figure 12-41 shows the valid bits in the FIFO_Data Register in 32-bit mode.
Offset: 18 (FIFO_DATA_32)
31
30
29
Access: User read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
R
FIFO_DATA[32:16]
W
RESET
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
FIFO_DATA[15:0]
W
RESET
—
—
—
—
—
—
—
—
—
Figure 12-41. FIFO_Data Register in 32-bit Mode
12.4.3.3.2
FIFO Fill Register (FIFO_FILL)
FIFO_FILL is a read-only register. Any read returns the current number of halfwords present in the FIFO.
Figure 12-42 shows the valid bits in the FIFO_FILL register.
Offset: 20 (FIFO_FILL)
Access: User read-only
7
6
5
R
4
3
2
1
0
0
0
0
FIFO_FILL[7:0]
W
RESET
0
0
0
0
0
Figure 12-42. FIFO_FILL Register
12.4.3.4
ATA Control Register (ATA_CONTROL)
Figure 12-43 shows the valid bits in the ATA control register, and Table 12-11 describes the bit fields.
Offset: 24 (ATA_CONTROL)
15
Access: User read/write
14
13
12
11
10
R
dma_srst
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
fifo_rst_b
ata_rst_b
fifo_tx_en
fifo_rcv_en
dma_write
iordy_en
0
0
0
0
0
0
R
W
RESET:
8
dma_start_s
dma_enable
top
dma_select
W
RESET:
9
dma_pend- dma_ultra_s
ing
elected
0
0
Figure 12-43. ATA Control Register
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Advanced Technology Attachment (ATA)
Table 12-11. ATA Control Register Field Descriptions
Field
Description
15-13
Reserved
N/A
12
dma_srst
This field controls if internal DMA controller is in reset or enabled
0 > internal DMA controller normal operation
1 > internal DMA controller reset
11-10
dma_select
9
dma_start_stop
8
dma_enable
This field controls DMA mode selected
00 > Single DMA select
01 > 32-bit ADMA select
10 > 64-bit ADMA select
11 > reserved
This field controls DMA master start or stop
0 > stop DMA master
1 > start DMA master
This field controls DMA master enable
0 > DMA master is disable
1 > DMA master is enable
7
fifo_rst_b
This field controls the internal FIFO reset
0 FIFO reset
1 FIFO normal operation
6
ata_rst_b
This bit controls the level on the ata_reset_b pin, which controls the reset of the internal ATA
protocol engine.
0 ata_reset_b = 0, ATA drive is reset, and internal protocol engine reset.
1 ata_reset_b = 1, ATA drive is not reset; internal protocol engine normal operation.
5
fifo_tx_en
FIFO transmit enable. This bit controls whether the FIFO makes transmit data requests to the DMA.
If enabled, the FIFO requests the DMA to refill it whenever the FIFO level drops below the alarm
threshold.
0 FIFO refill by DMA disabled
1 FIFO refill by DMA enabled
4
fifo_rcv_en
FIFO receive enable. This bit controls whether the FIFO makes receive data requests to the DMA.
If enabled, the FIFO requests the DMA to empty it whenever the FIFO level meets or exceeds the
alarm threshold.
0 FIFO empty by DMA disabled
1 FIFO empty by DMA enabled
3
dma_pending
DMA pending bit. This bit controls whether the ATA interface responds to a DMA request originating
in the drive. If this bit is set, the ATA interface starts a MDMA or UDMA burst whenever the drive
asserts the ata_dmarq signal.
0 ATA interface does not start DMA burst
1 ATA interface starts MDMA or UDMA burst whenever drive asserts dmarq
2
dma_ultra_selected
This bit determines the protocol (UDMA or MDMA) for any new DMA burst
1=UDMA protocol is used
0=MDMA protocol is used
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Table 12-11. ATA Control Register Field Descriptions (continued)
Field
Description
1
dma_write
This bit determines the data direction on any new DMA burst
1=DMA out burst, ATA interface writes to drive
0=DMA in burst, ATA interface reads from drive
0
iordy_en
12.4.3.5
This bit determines whether ata_iordy handshake is used during PIO mode
1=IORDY handshake is used
0=IORDY is disregarded
Interrupt Registers
The three interrupt registers control the interrupt interface between the ATA module and the CPU/DMA.
Two interrupts (ipbus_int and fifo_txfe_end_alarm) are controlled by these registers, as follows:
• The ipbus_int interrupt is controlled by bits 1,2,3,4,5 and 6 of the interrupt registers. It is asserted
if one of the 6 bits is set in the interrupt_pending register, while the same bit is set in the
interrupt_enable register. This interrupt goes to the CPU.
• The fifo_txfer_end_alarm interrupt is controlled by bit 7 of the interrupt registers. If ata_intrq1 is
set in both the interrupt enable and interrupt pending register, then fifo_txfer_end_alarm is
asserted. The purpose of this interrupt is to inform the DMA that the running data transfer has
ended. This interrupt goes to the smart DMA.
12.4.3.5.1
Interrupt Pending Register (INTERRUPT_PENDING)
Figure 12-44 shows the valid bits in the interrupt pending register, and Table 12-12 describes the bit fields.
Offset: 28 (INTERRUPT_PENDING)
R
Access: User read-only
7
6
5
ata_intrq1
fifo_
underflow
fifo_
overflow
01
0
0
4
3
controller_
ata_irtrq2
idle
2
1
dma_err
dma_trans
_over
0
0
0
W
RESET
1
0
—
Figure 12-44. Interrupt_Pending Register
1
Interrupts ata_intrq1 and ata_intrq2 only reset to 0 if during reset the interrupt input is low.
Table 12-12. Interrupt Pending Register Field Description
Field
7
ata_intrq1
6
fifo_underflow
5
fifo_overflow
Description
ATA interrupt request 1. This bit reflects the value of the ata_intrq interrupt input. It is set in the
when the drive interrupt is pending, and cleared otherwise. The interrupt clear register has no
influence on this bit.
FIFO underflow. This bit reports FIFO underflow. Sticky bit. It is set when there is a FIFO underflow
condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register.
FIFO overflow. This bit reports FIFO overflow. Sticky bit. It is set when there is a FIFO overflow
condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register.
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Table 12-12. Interrupt Pending Register Field Description (continued)
Field
Description
4
controller_idle
Controller Idle. This bit reports controller idle. It is set when the ATA protocol engine is idle, there
is no activity on the ATA bus. It is cleared when there is activity on the ATA bus. The interrupt clear
register has no influence on this bit.
3
ata_intrq2
ATA interrupt request 2. This bit reflects the value of the ata_intrq interrupt input. It is set when the
drive interrupt is pending, and cleared otherwise. It has exactly same functioning as ata_intrq1, but
this bit affects ipbus_int, while the other affects interrupt to the DMA.
2
dma_err
DMA error. This bit reflects Single DMA error or ADMA error interrupt.It is set in the interrupt
pending register when AHB bus response error, ADMA read or write error and ADMA length
mismatch error happen. When the bit is set in the interrupt pending register, and the same bit is
set in the interrupt enable register, ipbus_int is active, signaling interrupt to the CPU. It is cleared
by writing a ‘1’ to this bit in the interrupt clear register
1
dma_trans_over
DMA transfer over. This bit reflects Single DMA or ADMA read or write transfer over. It is set in the
interrupt pending register when Single DMA or ADMA transfer is over without error. When the bit
is set in the interrupt pending register, and the same bit is set in the interrupt enable register,
ipbus_int is active, signaling interrupt to the CPU. It is cleared by writing a ‘1’ to this bit in the
interrupt clear register.
0
Reserved
12.4.3.5.2
N/A
Interrupt Enable Register (INTERRUPT_ENABLE)
Figure 12-45 shows the valid bits in the interrupt enable register, and Table 12-13 describes the bit fields.
Offset: 2C (INTERRUPT_ENABLE)
7
6
5
ata_intrq1
fifo_
underflow
fifo_
overflow
0
0
0
R
W
RESET
Access: User read/write
4
3
controller_
ata_irtrq2
idle
0
2
1
dma_err
dma_trans
_over
0
0
0
0
—
Figure 12-45. Interrupt_Enable Register
Table 12-13. Interrupt Enable Register Field Description
Field
Description
7
ata_intrq1
ATA interrupt request 1. If this bit is set, then fifo_txfer_end_alarm is driven to the DMA when the
corresponding bit is set in the interrupt enable register. This informs the DMA that the current
transfer is finished. The interrupt clear register has no influence on this bit.
6
fifo_underflow
FIFO underflow. If this bit is set, then ipbus_int is driven to the CPU when the corresponding bit is
set in the interrupt enable register.
5
fifo_overflow
FIFO overflow. If this bit is set, then ipbus_int is driven to the CPU when the same bit is set in the
interrupt enable register.
4
controller_idle
Controller Idle. If this bit is set, then ipbus_int is driven to the CPU when the same bit is set in the
interrupt enable register. The interrupt clear register has no influence on this bit.
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Table 12-13. Interrupt Enable Register Field Description
Field
Description
3
ata_intrq2
ATA interrupt request 2. This bit reflects the value of the ata_intrq interrupt input. If this bit is set,
then ipbus_int is driven to the CPU when the same bit is set in the interrupt enable register. This
informs the CPU that the drive is requesting attention. The interrupt clear register has no influence
on this bit.
2
dma_err
DMA error. This bit reflects Single DMA error or ADMA error interrupt.It is set in the interrupt
pending register when AHB bus response error, ADMA read or write error and ADMA length
mismatch error happen. When the bit is set in the interrupt pending register, and the same bit is
set in the interrupt enable register, ipbus_int is active, signaling interrupt to the CPU. It is cleared
by writing a ‘1’ to this bit in the interrupt clear register
1
dma_trans_over
DMA transfer over. This bit reflects Single DMA or ADMA read or write transfer over. It is set in the
interrupt pending register when Single DMA or ADMA transfer is over without error. When the bit
is set in the interrupt pending register, and the same bit is set in the interrupt enable register,
ipbus_int is active, signaling interrupt to the CPU. It is cleared by writing a ‘1’ to this bit in the
interrupt clear register.
0
Reserved
12.4.3.5.3
N/A
Interrupt Clear Register (INTERRUPT_CLEAR)
Figure 12-46 shows the valid bits in the interrupt clear register, and Table 12-14 describes the bit fields.
Offset: 30 (INTERRUPT_CLEAR)
7
Access: User write-only
6
5
fifo_
underflow
fifo_
overflow
—
—
4
3
2
1
0
R
W
RESET
—
dma_err dma_trans
_overf
—
—
—
—
—
Figure 12-46. Interrupt_Clear Register
Table 12-14. Interrupt Clear Register Field Description
Field
7
Reserved
Description
N/A
6
fifo_underflow
FIFO underflow. Writing ‘1’ to this bit clears the corresponding bit in the interrupt pending register.
5
fifo_overflow
FIFO overflow. Writing ‘1’ to this bit clears the corresponding bit in the interrupt pending register.
4–3
Reserved
N/A
2
dma_err
DMA error. Writing ‘1’ to this bit clears the corresponding bit in the interrupt pending register.
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Table 12-14. Interrupt Clear Register Field Description (continued)
Field
Description
1
dma_trans_over
DMA transfer over. Writing ‘1’ to this bit clears the corresponding bit in the interrupt pending
register.
0
Reserved
12.4.3.6
N/A
FIFO Alarm Register (FIFO_ALARM)
This register contains the threshold (in 16-bit halfword units) which triggers fifo_rcv_alarm or
fifo_tx_alarm signals to the DMA interface.
• If the fifo_rcv_en bit is set in the ATA control register and fifo_fill ≥ fifo_alarm, then the
fifo_rcv_alarm signal is asserted to request the DMA to empty the FIFO.
• If the fifo_tx_en bit is set in the ATA control register and fifo_fill < fifo_alarm), then the
fifo_tx_alarm signal is asserted to request the DMA to refill the FIFO.
For single DMA and ADMA transfers, the recommended value for FIFO_ALARM is 0x20.
Figure 12-47 shows the valid bits in the FIFO alarm register.
Offset: 34 (FIFO_ALARM)
Access: User read/write
7
6
5
4
R
3
2
1
0
0
0
0
FIFO_ALARM[7:0]
W
RESET
0
0
0
0
0
Figure 12-47. FIFO Alarm Register
12.4.3.7
ADMA_ERR_STATUS Register
Figure 12-48 shows the valid bits in the ADMA_ERR_STATUS register.
Offset: 38 (ADMA_ERR_STATUS)
7
R
W
RESET:
6
5
4
3
reserved
0
0
0
0
0
2
adma_len_m
ismatch
0
1
0
adma_err_state
0
0
Figure 12-48. ADMA_ERR_STATUS Register
This register indicates what kind of error has happened. When an ADMA error interrupt occurs, the
ADMA error states field in this register holds the ADMA state, and the ADMA system address register
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holds the address around the error descriptor. For recovering the error, the host driver requires the ADMA
state to identify the error descriptor address as given in Table 12-15.
Table 12-15. ADMA Error States Register Field Descriptor
Fields
Descriptor
7-3
uncommitted
N/A
2
adma_len_mismatch. Total data length in descriptor table does not match the total sector data set by
adma_len_mismatch command
1-0
adma_err_state
12.4.3.8
adma_err_state. ADMA state when error occurs.
00 ST_STOP—Previous location set in the ADMA system address register is the error descriptor
address.
01 ST_FDS—Current location set in the ADMA system address register is the error descriptor address.
10 ST_CARD—This state is never set because it only increments the descriptor pointer and does not
generate an ADMA error.
11 ST_TFR—Previous location set in the ADMA system address register is the error descriptor address.
SYS_DMA_BADDR Register
See Figure 12-49 for illustration of valid bits in the SYS_DMA_BADDR register.
Offset: 3C (SYS_DMA_BADDR)
7
6
5
R
W
RESET:
4
3
2
1
0
10
9
8
18
17
16
26
25
24
sys_dma_baddr[7:0]
0
15
14
13
R
W
RESET:
12
11
sys_dma_baddr[15:8]
0
23
22
21
R
W
RESET:
20
19
sys_dma_baddr[23:16]
0
31
R
W
RESET:
30
29
28
27
sys_dma_baddr[31:24]
0
Figure 12-49. SYS_DMA_BADDR Register
This register contains the system memory address for a DMA transfer. When the host controller stops a
DMA transfer, this register points to the system address of the next contiguous data position. It can be
accessed only if a transaction is executing (that is, after a transaction has stopped). Read operations during
transfers may return an invalid value. The host driver initializes this register before starting a DMA
transaction. After DMA has stopped, the system address of the next contiguous data position can be read
from this register.
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12.4.3.9
ADMA_SYS_ADDR Register
See Figure 12-50 for an illustration of valid bits in the ADMA_SYS_ADDR register.
Offset: 40 (ADMA_SYS_ADDR)
7
6
5
R
W
RESET:
3
2
1
0
10
9
8
18
17
16
26
25
24
34
33
32
42
41
40
50
49
48
58
57
56
adma_sys_addr[7:0]
0
15
14
13
R
W
RESET:
12
11
adma_sys_addr[15:8]
0
23
22
21
R
W
RESET:
20
19
adma_sys_addr[23:16]
0
31
30
29
R
W
RESET:
28
27
adma_sys_addr[31:24]
0
39
8
37
R
W
RESET:
36
35
adma_sys_addr[39:32]
0
47
46
45
R
W
RESET:
44
43
adma_sys_addr[47:40]
0
55
54
53
R
W
RESET:
52
51
adma_sys_addr[55:48]
0
63
R
W
RESET:
4
62
61
60
59
adma_sys_addr[63:56]
0
Figure 12-50. ADMA_SYS_ADDR Register
This register holds the byte address of the executing command of the descriptor table. The 32-bit descriptor
uses the lower 32 bits of this register (only the 32-bit descriptor is supported). At the start of ADMA, the
host driver sets the starting address of the descriptor table. The ADMA engine increments this register
address on every fetch of a descriptor command. When the ADMA is stopped at the block gap, this register
indicates the address of the next executable descriptor command. When the ADMA error interrupt is
generated, this register holds the valid descriptor address depending on the ADMA state.
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12.4.3.10 BLOCK_CNT Register
See Figure 12-51 for an illustration of valid bits in the BLOCK_CNT register.
Offset: 48 (BLOCK_CNT)
7
R
W
RESET:
R
W
RESET:
6
5
4
3
2
1
0
0
10
0
9
0
8
0
0
0
block_cnt[7:0]
0
15
0
14
0
13
0
12
0
11
block_cnt[15:8]
0
0
0
0
0
Figure 12-51. BLOCK_CNT Register
This register is block number set for a DMA transfer command. It can support 1 to 65535 blocks.
12.4.3.11 BURST_LENGTH Register
This register controls the burst length and may be set by software. Only burst lengths of 4 words are
supported, so this register must be set to 4.
Figure 12-52 shows the valid bits in the BURST_LENGTH register.
Offset: 4C (BURST_LENGTH)
7
R
W
RESET:
6
5
4
3
2
1
0
0
0
burst_length[5:0]
0
0
0
1
0
0
Figure 12-52. BURST_LENGTH Register
Table 12-16. BURST_LENGTH Register Field Descriptor
Field
Descriptor
7-6
Uncommitted
N/A
5-0
burst_length
Burst_length:
000001 = 1 words
00001x = 2 words
0001xx = 4 words
001xxx = 8 words
01xxxx = 16 words
1xxxxx = 32 words
12.4.3.12 SECTOR_SIZE Register
This register is for sector size set. The default value is 512 bytes.
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Advanced Technology Attachment (ATA)
Figure 12-53 shows the valid bits in the SECTOR_SIZE register.
Offset: 50 (SECTOR_SIZE)
7
R
W
RESET:
6
5
4
3
2
1
0
0
0
1
sector_size
0
0
1
0
0
Figure 12-53. SECTOR_SIZE Register
12.4.3.13 Drive Registers Connected to ATA Bus
Some drive registers are addressable but are not present in the ATA interface module. These are listed in
Table 12-17. If a read or write access is made to one of these registers, the read or write is mapped to a PIO
read or write cycle on the ATA bus, and the corresponding register in the device attached to the ATA bus
is accessed. No description of these registers is given here; consult the ATA specification for information
on these registers.
If the drive_data register is accessed while the ATA interface operates in big-endian mode, the bytes
to/from the ATA bus are swapped. No swaps occur in little-endian mode or for the other registers.
Table 12-17. Drive Registers connected to ATA Bus
Address
Name
Description
Access
drive_data
Drive data register
R/W
drive_features
Drive features register
R/W
Offset: A8 (DRIVE_SECTOR_COUNT)
drive_sector_count
Drive sector count register
R/W
Offset: AC (DRIVE_SECTOR_NUM)
drive_sector_num
Drive sector number register
R/W
Offset: B0 (DRIVE_CYL_LOW)
drive_cyl_low
Drive cylinder low register
R/W
Offset: B4 (DRIVE_CYL_HIGH)
drive_cyl_high
Drive cylinder high register
R/W
Offset: B8 (DRIVE_DEV_HEAD)
drive_dev_head
Drive device head register
R/W
Offset: BC (DRIVE_COMMAND)
drive_command
Drive command register
Write-only
drive_status
Drive status register
Read-only
drive_alt_status
Drive alternate status register
Read-only
drive_control
Drive control register
Write-only
Offset: A0 (DRIVE_DATA)
Offset: A4 (DRIVE_FEATURES)
Offset: BC (DRIVE_STATUS)
Offset: D8 (DRIVE_ALT_STATUS)
Offset: D8 (DRIVE_CONTROL)
12.5
Functional Description
The ATA interface provides two alternative modes for communication with the ATA peripherals connected
to the ATA bus:
• PIO mode read/write operations through the ATA bus
• DMA transfers through the ATA bus, including:
— DMA slave mode transfers between host and FIFO, which utilize the IPS bus
— DMA master mode transfers between external memory and FIFO, which utilize the AHB bus
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The operation of the peripheral under these two modes is described in detail in subsequent sections.
12.5.1
Resetting the ATA Bus
The ATA bus reset ata_reset_b is asserted whenever ata_rst_b (bit #6) of the ATA control register is cleared
(see Section 12.4.3.4, “ATA Control Register (ATA_CONTROL)”). Clearing the bit also resets the ATA
protocol engine. When the bit is set, the reset is released.
12.5.2
Programming ATA Bus Timing and iordy_en
The timing of the ATA interface is programmable using the 24 timing registers described in Section 12.4,
“Memory Map and Register Definitions.” Programming the registers requires that the ATA bus be idle, so
before reprogramming the user should ensure the following:
a) The dma_pending bit in the ATA control register is cleared (see Section 12.4.3.4, “ATA Control
Register (ATA_CONTROL)”).
b) The controller_idle bit in the interrupt pending register is set (see Section 12.4.3.5.1, “Interrupt
Pending Register (INTERRUPT_PENDING)”).
These two conditions can be met by first clearing dma_pending and then waiting until controller_idle is
set before reprogramming the timing parameters. If dma_pending was set before the reprogramming
started, it should be set again after the new timing is in effect to allow the drive to finish the current DMA
transfer.
The bus timing should only be reprogrammed during an ongoing DMA transfer when the operating system
requires a change in the bus clock (for example, in dynamic voltage frequency scaling).
The controller_idle bit must be set before reprogramming the bus timing: otherwise, the new timing values
may affect a bus cycle that is still running and cause an error. PIO reads or writes to the ATA bus terminate
after the bus cycle with the CPU has been terminated.
The iordy_en bit in the ATA control register determines whether the ATA interface responds to the drive’s
IORDY signal. Just as with timing registers, it should only be reprogrammed when dma_pending is
cleared and controller_idle is set.
12.5.3
Access to ATA Bus in PIO Mode
Before accessing the ATA bus in PIO mode, the user must do the following:
a) Set the ata_rst_b bit in the ATA control register
b) Program the timing parameters
The drive is accessed in PIO mode simply by reading or writing to the correct drive register. The bus cycle
is translated to an ATA cycle, and the drive is accessed.
Reads and writes to the drive are not possible while the ATA bus is in reset; the attempted operation fails
and is discarded.
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Advanced Technology Attachment (ATA)
12.5.4
Receiving Data from ATA Bus in DMA Slave Mode
In DMA receive slave mode, the protocol engine transfers data from the drive to the FIFO using the
multiword DMA (MDMA) or ultra DMA (UMDMA) protocol. The transfer pauses when any of the
following conditions occur:
• The FIFO is full.
• The drive negates its DMA request signal ata_dmarq.
• The dma_pending bit in the ata_control register is cleared.
When the condition is removed, the transfer restarts. At the end of the transfer, the drive signals the host
by asserting the ata_intrq signal. Alternatively, the host can read the device status register, which also
indicates when the transfer has ended.
The transfer of data from FIFO to memory is handled by the host system DMA. DMA data transfers from
device to host are set up as follows:
1. Make sure the ATA bus is not in reset and all timing registers are programmed.
2. Make sure the FIFO is empty by reading it until empty or by resetting it.
3. Initialize the DMA channel connected to fifo_rcv_alarm. Every time the fifo_rcv_alarm is high,
the DMA should read <packetsize> 32-bit words from the FIFO, and store them in main memory
(here “packetsize” is defined as the number of 32-bit words in a packet; typically, packetsize = 8).
This keeps the transfer going while avoiding FIFO overrun.
4. Write 2*<packetsize> to the FIFO alarm register (note that this setting corresponds to one packet
of data, because the alarm threshold is specified in units of 16-bit halfwords). Thus the FIFO
notifies the DMA when there is at least one packet ready for transfer.
5. Ensure the FIFO is out of reset by setting the fifo_rst_b bit in the ATA control register (see
Section 12.4.3.4, “ATA Control Register (ATA_CONTROL)”).
6. Set the fifo_rcv_en bit in the ATA control register. This enables the DMA to empty the FIFO.
7. Set the dma_pending bit, and clear the dma_write bit. Also, program ultra_mode_selected=0 (for
MDMA) or ultra_mode_selected=1 (for UDMA).
Steps (1–7) have prepared the host side of the DMA.
8. Send commands to the drive in PIO mode that cause it to request DMA transfer on the ATA bus
(consult the ATA specification for the specifics of this operation).
9. At this point, when the drive requests a DMA transfer by pulling ata_dmarq high, the ATA interface
acknowledges with ata_dmack, and the transfer starts. Data is transferred automatically to the
FIFO, and from there to the host memory.
10. During the transfer, the host can monitor for end of transfer by reading some device ATA registers.
These reads cause the running DMA to pause; after the read is complete, the DMA resumes.
Alternatively, the host can wait until the drive asserts ata_intrq, which also indicates end of transfer.
11. When the transfer ends, the host or host DMA should wait until the controller_idle bit is set in the
ATA control register, then read the remaining halfwords from the FIFO and transfer these to
memory. Note that there may be less than <packetsize> remaining 32-bit words, in which case the
transfer is not performed automatically by the DMA.
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12.5.5
Transmitting Data to ATA Bus in DMA Slave Mode
In DMA transmit mode, the protocol engine transfers data from the FIFO to the drive using the multiword
DMA (MDMA) or ultra DMA (UDMA) protocol. The transfer pauses when one of following conditions
occurs:
• The FIFO is empty
• The drive negates its DMA request signal ata_dmarq
• The dma_pending bit in the ata_control register is cleared
When the condition is removed, the transfer restarts. At the end of the transfer, the drive signals the host
by asserting the ata_intrq signal. Alternatively, the host can read the device status register, which also
indicates when the transfer has ended.
The transfer of data from FIFO to memory is handled by the host system DMA. DMA data transfers from
host to device are set up as follows:
1. Make sure the ATA bus is not in reset, and all timing registers are programmed.
2. Make sure the FIFO is empty by reading it until empty or by resetting it.
3. Initialize the DMA channel connected to fifo_tx_alarm. Every time the fifo_tx_alarm signal is
high, the DMA should read <packetsize> 32-bit words from the main memory and write them to
the FIFO (typical packetsize is 8 32-bit words). Program the DMA so that it does not transfer more
than <sectorsize> 32-bit words total.
4. Write FIFO_SIZE – 2 × <packetsize> to the FIFO alarm register. In this way, FIFO notifies the
DMA when there is room for at least one additional packet. FIFO_SIZE is given in 16-bit
halfwords: the typical value is 64 halfwords, or 128 bytes.
5. Prepare the ATA for a DMA transfer from host to device as follows:
a) Make sure the FIFO is out of reset by setting bit fifo_rst_b in the ATA control register (see
Section 12.4.3.4, “ATA Control Register (ATA_CONTROL)”).
b) Program fifo_tx_en=1 in the ATA control register. This enables the FIFO to be filled by DMA.
c) Program dma_pending =1 and dma_write=1. Also, program ultra_mode_selected =0 (for
MDMA) or ultra_mode_selected=1 (for UDMA).
Steps (1–5) have prepared the host side of the DMA.
6. Send commands to the drive in PIO mode that cause it to request a DMA transfer on the ATA bus
(consult the ATA specification for the specifics of this operation).
7. At this point, when the drive requests a DMA transfer by pulling ata_dmarq high, the ATA interface
acknowledges with ata_dmack, and the transfer starts. Data is transferred automatically from the
FIFO, and also from host memory to FIFO.
8. During the transfer, the host can monitor for end of transfer by reading some device ATA registers.
These reads cause the running DMA to pause; after the read is completed, the DMA resumes.
Alternatively, the host can wait unit the drive asserts ata_intrq, which also indicates end of transfer.
When the transfer ends, no additional FIFO manipulations are needed.
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Advanced Technology Attachment (ATA)
12.5.6
Using DMA Master Mode to Receive Data From the ATA Bus
In DMA master mode for receiving data from the ATA bus, the internal DMA engine initializes a burst
data write transfer on the AHB bus when the internal signal sys_dma_req is asserted.
Sys_dma_req is asserted when these conditions occur:
•
fifo_rcv_alarm in DMA read
•
In a DMA read, the data left in the FIFO is not enough to trigger the fifo_alarm, but the sector word
counter has not reached a sector boundary
Sys_dma_req is negated when these conditions occur:
•
A burst transfer ends
•
DMA start is set
•
The host is not active
For single DMA, burst length is the minimum set by software, FIFO alarm, and left data number in the last
sector word counter.
For ADMA, burst length is the minimum set by software, FIFO alarm, left data number in the last sector
word counter, and left data number indicated in a descriptor pair.
The following list describes the steps in setting up a DMA data transfer from the device to external
memory:
1. Make sure that the ATA bus is not in reset, and that all timing registers are programmed.
2. Make sure the FIFO is empty by reading it until empty, or by resetting it.
3. To make the ATA ready for a DMA transfer from device to host, do the following:
a) Make sure the FIFO is out of reset by setting the bit fifo_rst_b to 1 in the ata_control register.
b) Program fifo_rcv_en=1 in the ata_control register. This enables the FIFO to by emptied by the
DMA.
c) Program dma_pending =1, dma_write=0, ultra_mode_selected=0/1 in the ata_control register.
ultra_mode_selected should be 1; it should be 0 if you want to transfer data using MDMA
mode.
4. To make the internal DMA controller ready for a DMA transfer, do the following:
a) Program fifo_alarm, burst_length, block_cnt, DMA system start base address (data buffer start
address) for single DMA mode, or ADMA system address (descriptor table start address) for
ADMA mode.
b) Program dma_en = 1, dma_select=01 (if you select ADMA mode), dma_start_stop=1. If you
select ADMA mode, make sure that the descriptor table is ready before starting a DMA
transfer.
5. Now the host side of the DMA is ready. Send commands to the drive in PIO mode that cause it to
request a DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this
document. See the ATA specification for information on communicating with the drive.
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6. When the drive requests a DMA transfer by pulling ata_dmarq high, the ATA interface
acknowledges with ata_dmack, and the transfer starts. Data is transferred automatically to the
FIFO, and then to the external memory.
7. When sys_dma_req is asserted, the DMA engine will write burst length data from FIFO to external
memory.
8. During the transfer, the host can detect end of transfer by waiting for a dma_trans_over interrupt.
After the end of transfer is detected, the host must reset dma_start_stop to 0.
12.5.7
Using DMA Master Mode To Transmit Data to the ATA bus
In DMA master mode for transmitting data to the ATA bus, the internal DMA engine initializes a burst
data read transfer on the AHB bus when the internal signal sys_dma_req is asserted.
Sys_dma_req is asserted when these conditions occur:
•
fifo_tx_alarm in DMA write
Sys_dma_req is negated when these conditions occur:
•
A burst transfer ends
•
DMA start is set
•
The host is not active
For Single DMA, burst length is the minimum set by software and the FIFO alarm.
For ADMA, burst length is the minimum set by software, the FIFO alarm, and the left data number
indicated in a descriptor pair.
The following list describes the steps in setting up a DMA data transfer from external memory to the
device:
1. Make sure the ATA bus is not in reset, and all timing registers are programmed.
2. Make sure the FIFO is empty by reading it until empty, or by resetting it.
3. To make the ATA ready for a DMA transfer from host to device, do following:
a) Make sure the FIFO is out of reset by setting bit fifo_rst_b to 1 in the ATA control register.
b) Program fifo_tx_en=1 in ata_control register. This enables the FIFO to be filled by DMA.
c) Program dma_pending =1, dma_write=1, ultra_mode_selected=0/1 in ata_control register.
ultra_mod_selected should be 1 if you want to transfer data using UDMA mode, it should be 0
if you want to transfer data using MDMA mode.
4. To make the internal DMA controller ready for a DMA transfer, do the following:
a) Program fifo_alarm, burst_length, block_cnt, and the DMA system start base address (data
buffer start address) for single DMA mode, or ADMA system address (descriptor table start
address) for ADMA mode.
b) Program dma_en = 1, dma_select=01(if select ADMA mode), dma_start_stop=1. If select
ADMA mode, it is necessary to make sure descriptor table is ready before start DMA transfer.
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Advanced Technology Attachment (ATA)
5. When sys_dma_req is asserted, DMA engine will read a burst length data from external memory
to FIFO.
6. Now, the host side of the DMA is ready. Send commands to the drive in PIO mode that cause it to
request DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this
document. You should consult the ATA specification to know how to communicate with the drive.
7. When the drive now requests DMA transfer by pulling ata_dmarq high, the ATA interface
acknowledges with ata_dmack, and the transfer starts. Data is transferred automatically from the
FIFO if FIFO is not empty.
8. During the transfer, the host can detect end of transfer by waiting for ata_intrq2 interrupt. After the
end of transfer is detected, the host must reset dma_start_stop to 0.
12.6
Initialization and Application of ATA
If the host asserts RESET, the ATA device executes the hardware reset protocol, regardless of power
management mode. For more details about the power-on and hardware reset protocol, see the ATA
specification).
The host issues an IDENTIFY DEVICE command after the power-on reset or hardware reset protocol is
complete, in order to determine the current status of features implemented by the device.
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Chapter 13
Digital Audio Multiplexer (AUDMUX)
This chapter describes a module integrated into an SoC. The chapter is intended for a module driver
software developer. It describes module-level operation and programming. To understand how the module
is integrated at the SoC level, a system software developer should see discussions of the module in the
appropriate SoC-level chapter(s).
Table 13-1 defines terms used in this chapter.
Table 13-1. Definition Of Terms
Term
Definition
PTCR
Port Timing Control Register
PDCR
Port Data Control Register
CNMCR
CE Bus Network Mode Control Register
FSPOL
Frame sync polarity
CLKPOL
Clock polarity
TFSDIR
Transmit Frame Sync Direction Control
TCLKDIR
Transmit Clock Direction Control
RFSDIR
Receive Frame Sync Direction Control
RCLKDIR
Receive Clock Direction Control
TFSEL
Transmit Frame Sync Port Select
RFSEL
Receive Frame Sync Port Select
TCSEL
Transmit Clock Port Select
RCSEL
Receive Clock Port Select
RXDSEL
Receive Data Port Select
INMMASK
CE Bus
CEN
Internal Network Mode Masking
Consumer Electronic Bus
CE Bus Enable
CNTHI
CE Bus disable signal High Period Count
CNTLO
CE Bus disable signal Low Period Count
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Digital Audio Multiplexer (AUDMUX)
13.1
Overview
The Digital Audio Mux (AUDMUX) provides a programmable interconnect device for voice, audio, and
synchronous data routing between host serial interfaces (such as SSI) and peripheral serial interfaces (that
is, audio and voice CODECs, also known as coder-decoders). The AUDMUX interconnections allow
multiple, simultaneous, audio/voice/data flows between the ports in point-to-point or point-to-multipoint
configurations. This section includes a top level diagram that shows the functional organization of the
module, including all off-chip signals.
The AUDMUX allows the audio system connectivity to be modified through programming (as opposed to
altering the PCB schematics of the system). Figure 13-1 shows the block diagram. The full description of
the module is in Section 13.4, “Functional Description.”
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Digital Audio Multiplexer (AUDMUX)
Fsn,Clkn
TxDn,RxDn
TFS7,TCLK7
TFS7
TFS1,TCLK1
TCLK7
TFS1
Port 1
RFS7,RCLK7
Port 7
TCLK1
RFS7
RFS1,RCLK1
RCLK7
RFS1
RCLK1
Da7
Db7
Da1
Db1
TFS6,TCLK6
TFS6
TFS2,TCLK2
TCLK6
RFS6,RCLK6
TFS2
RFS6
Port 2
TCLK2
Port 6
RCLK6
RFS2,RCLK2
RFS2
Da6
RCLK2
Db6
Da2
Db2
TFS5,TCLK5
TFS5
TCLK5
RFS5,RCLK5
TFS3,TCLK3
Port 5
RFS5
TFS3
RCLK5
TCLK3
Port 3
RFS3,RCLK3
Da5
RFS3
Db5
RCLK3
TFS4,TCLK4
Da3
TFS4
Db3
TCLK4
RFS4,RCLK4
RFS4
Port 4
RCLK4
Da4
Db4
Figure 13-1. AUDMUX Block Diagram
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Digital Audio Multiplexer (AUDMUX)
13.1.1
Features
Key features of the module include the following:
• Three internal ports
• Four external ports
• Full 6-wire SSI interfaces for asynchronous receive and transmit
• Configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interfaces
• Independent Tx/Rx Frame sync and clock direction selection for host or peripheral
• Each host interface’s capability to connect to any other host or peripheral interface in a
point-to-point or point-to-multipoint (network mode)
• Transmit and Receive Data switching to support external network mode
• CE Bus network mode to provide synchronous switching on RxD
13.1.2
Modes of Operation
Each AUDMUX port can be configured to operate in the following modes:
• Normal mode—the port is connected point-to-point to a single other port
• Internal network mode—the port is connected point-to-multipoint to multiple other ports
• CE bus network mode—the port receives data from the CE bus port (port 7) and one other port as
selected by software.
Additionally, each port can operate in synchronous or asynchronous timing modes.
Modes of operation are described in more detail in Section 13.1.2, “Modes of Operation”.
13.2
External Signal Description
Table 13-2 lists AUDMUX pin-level signals for the external ports, where:
• Pn is P4, through P7
• m = n – 3.
The port is configured as an external port by a static system-level signal input pn_int_ext_select.
Table 13-2. Off-Chip Module Signals
Name
Module Port
I/O
AUDm_TXD
Pn
I/O
AUDm_RXD
Pn
AUDm_TXC
Function
Reset State
Pull-up
Transmit Data from Pn
1
Active
I/O
Receive Data at Pn
1
Active
Pn
I/O
Transmit Clock input/output at Pn
1
—
AUDm_RXC
Pn
I/O
Receive Clock input/output at Pn
1
—
AUDm_TXFS
Pn
I/O
Transmit Frame sync input/output at Pn
1
—
AUDm_RXFS
Pn
I/O
Receive Frame sync input/output at Pn
1
—
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Digital Audio Multiplexer (AUDMUX)
13.3
Memory Map and Register Definitions
This section includes the module memory map and detailed descriptions of all registers. For the base
address of a particular module instantiation, see the system memory map.
13.3.1
Memory Map
The AUDMUX memory map is shown in Table 13-3.
Table 13-3. AUDMUX Memory Map
Address
Register
Access
Reset Value
Section/Page
0x0000 (PTCR1)
Port Timing Control Register 1
RW
0xAD40_0800
13.3.3.4/13-8
0x0004 (PDCR1)
Port Data Control Register 1
RW
0x0000_A000
13.3.3.5/13-10
0x0008 (PTCR2)
Port Timing Control Register 2
RW
0xA500_0800
13.3.3.4/13-8
0x000C (PDCR2)
Port Data Control Register 2
RW
0x0000_8000
13.3.3.5/13-10
0x0010 (PTCR3)
Port Timing Control Register 3
RW
0x9CC0_0800
13.3.3.4/13-8
0x0014 (PDCR3)
Port Data Control Register 3
RW
0x0000_6000
13.3.3.5/13-10
0x0018 (PTCR4)
Port Timing Control Register 4
RW
0x0000_0800
13.3.3.4/13-8
0x001C (PDCR4)
Port Data Control Register 4
RW
0x0000_4000
13.3.3.5/13-10
0x0020 (PTCR5)
Port Timing Control Register 5
RW
0x0000_0800
13.3.3.4/13-8
0x0024 (PDCR5)
Port Data Control Register 5
RW
0x0000_2000
13.3.3.5/13-10
0x0028 (PTCR6)
Port Timing Control Register 6
RW
0x0000_0800
13.3.3.4/13-8
0x002C (PDCR6)
Port Data Control Register 6
RW
0x0000_0000
13.3.3.5/13-10
0x0030 (PTCR7)
Port Timing Control Register 7
RW
0x0000_0800
13.3.3.4/13-8
0x0034 (PDCR7)
Port Data Control Register 7
RW
0x0000_C000
13.3.3.5/13-10
0x0038 (CNMCR)
CE Bus Network Mode Control Register (CNMCR)
RW
0x0003_1010
13.3.3.6/13-12
13.3.2
Register Summary
Table 13-4 shows the control register and address mapping for the AUDMUX.
Table 13-4. Register Summary
Address1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
[(n - 1) x 8] + 0x0000
PTCRn
TF
S
DI
W
R
R
RCSEL[3:0]
W
TCL
KDI
R
TFSEL[3:0]
SY
N
0
RFS
DIR
TCSEL[3:0]
0
0
0
0
0
RCL
KDI
R
RFSEL[3:0]
0
0
0
0
0
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Digital Audio Multiplexer (AUDMUX)
Table 13-4. Register Summary (continued)
Address1
R
[(n - 1) x 8] + 0x0004
PDCRn
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
0
W
R
RXDSEL[2:0]
W
R
0
0
0
MODE[1:0]
0
0
0
INMMASK[7:0]
0
0
0
0
0
W
0x0038 (CNMCR)
FS
CLK
CEN PO
POL
L
R
CNTHI[7:0]
CNTLOW[7:0]
W
1
n ranges from 1 through 7.
13.3.3
Register Descriptions
There are two configuration registers for each port. There is also a separate register for CE Bus Network
mode control. Each pair of configuration registers is identical for each port; however, the default values
following a reset differ as shown in Table 13-3.
• Section 13.4.3.1, “Default Port Configuration,” describes the default configuration of the ports.
• Section 13.4.3.2, “Default CE Bus Configuration,” describes the default configuration of the CE
Bus.
13.3.3.1
Default Port Configuration
After a reset, each port defaults to normal mode (PDCRn[MODE] = 00) with synchronous timing mode
(PTCRn[SYN] = 1) enabled.
The default port-to-port connections are as follows:
• Port 1 to Port 6
— Port 6 provides the clock and frame sync.
• Port 2 to Port 5
— Port 5 provides the clock and frame sync.
• Port 3 to Port 4
— Port 4 provides the clock and frame sync.
• Port 7 to Port 7 (in data loopback mode)
— Clock and frame syncs are inputs.
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Digital Audio Multiplexer (AUDMUX)
13.3.3.2
Default CE Bus Configuration
The default configuration of all the ports is to set the MODE field to normal mode (that is, no port selects
CE Bus network mode). Correspondingly, the default configuration of the CEN field in the CNMCR is
clear. To minimize AUDMUX setup for audio testing, the rest of the CNMCR fields default to the
following configuration:
• FSPOL is set.
• CLKPOL is set.
• CNTHI is set to 16.
• CNTLOW is set to 16.
This configuration uses a frame sync that is logic high when asserted.
The clock is driven by the transmitter on the rising edge and is sampled by the receiver on the falling edge.
The AUDMUX switches between devices on the rising edge; this provides a buffer of one-half clock period
between the moment data is sampled and when the AUDMUX switches between devices. Refer to
Figure 13-16 for a timing diagram where FSPOL and CLKPOL are both set.
CNTHI and CNTLOW are set to 16 to allow CE Bus to drive data during timeslot 1 and the other device
to drive data during timeslots 0, 2,..., N-1 where N is the number of timeslots used and each timeslot has
16 bits.
13.3.3.3
Register Conventions
Figure 13-2 and Table 13-5 explain conventions used in register diagrams and tables.
Always
reads 1
1
Always
reads 0
0
R/W
Read- BIT WriteWrite 1 BIT
Read rtc Self-clear 0 N/A
bit BIT only bit
only bit BIT to clear w1c to clear BIT
bit BIT
Figure 13-2. Register Field Conventions
Table 13-5. General Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
BIT
Bit or field name. Its presence in the read or write row indicates that it can correspondingly be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
rtc
Read to clear. A read-only status bit that is automatically cleared when read.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
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Digital Audio Multiplexer (AUDMUX)
Table 13-5. General Register Conventions (continued)
Convention
Description
Reset Values
0
Resets to 0 (zero).
1
Resets to 1 (one).
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
13.3.3.4
Reset value is determined by polarity of indicated signal.
Port Timing Control Register n (PTCRn)
PTCRn is the Port Timing Control Register for Port n, where n ranges from 1 through 7.
Offset 0x0000 (PTCR1)
Access: User read/write
0x0008 (PTCR2)
0x0010 (PTCR3)
0x0018 (PTCR4)
0x0020 (PTCR5)
0x0028 (PTCR6)
0x0030 (PTCR7)
31
R TFS
W DIR
30
27
26
TCLK
DIR
TFSEL[3:0]
Reset
W
Reset
22
TCSEL[3:0]
21
20
RFS
DIR
17
RFSEL[3:0]
16
RCLK
DIR
(See Table 13-3 for reset values.)
15
R
25
12
RCSEL[3:0]
11
10
0
SYN
—
(See Table 13-3 for reset values.)
Figure 13-3. Port Timing Control Register for Port n
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Digital Audio Multiplexer (AUDMUX)
Table 13-6. Port Timing Control Register Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as an
output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the TFSEL
settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
21
RFS DIR
20–17
RFSEL[3:0]
16
RCLKDIR
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
…
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output or
input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL settings
determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
…
x110 Port 7
x111 Reserved
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as an
output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the RFSEL
settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be sourced
from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
…
x110 Port 7
x111 Reserved
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output or
input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL settings
determine the source port of the clock.
0 RxClk is an input
1 RxClk is an output
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Digital Audio Multiplexer (AUDMUX)
Table 13-6. Port Timing Control Register Field Descriptions (continued)
Field
Description
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced from
TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
…
x110 Port 7
x111 Reserved
11
SYN
Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the transmit and
receive sections use common clock and frame sync signals (that is, the port is a 4-wire interface). When
SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the
transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
13.3.3.5
Port Data Control Register n (PDCRn)
Figure 13-4 PDCRn is the Port Data Control Register for Port n, where n ranges from 1 through 7.
Offset 0x0004 (PDCR1)
Access: User Read/Write
0x000C (PDCR2)
0x0014 (PDCR3)
0x001C (PDCR4)
0x0024 (PDCR5)
0x002C (PDCR6)
0x0034 (PDCR7)
31
16
R
—
W
Reset
(See Table 13-3 for reset values.)
15
R
W
Reset
13
RXDSEL[2:0]
12
TXRX
EN
11
10
—
9
8
7
MODE[1:0]
0
INMMASK[7:0]
(See Table 13-3 for reset values.)
Figure 13-4. Port Data Control Register for Port n
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Digital Audio Multiplexer (AUDMUX)
Table 13-7 lists the PDCRn register field descriptions.
Table 13-7. PDCR (Port n) Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
12
TXRXEN
11–10
Description
Reserved
Receive Data Select. Selects the source port for the RxD data. RXDSEL is ignored if MODE = 01 (that is,
Internal Network Mode is enabled).
xxx Port number for RxD
000 Port 1
…
110 Port 7
111 Reserved
Transmit/Receive Switch Enable. Swaps the transmit and receive signals.
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
9–8
MODE[1:0]
Mode Select. This field selects the mode in which the port is to operate. The modes of operation include the
following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDed together. RXDSEL is ignored. INMMASK
determines which RxD signals are ANDed together.
• CE Bus Network mode, in which the port receives data from CE Bus port (Port 7) and any other port as
selected by RXDSEL[3:0] in different time slots within a frame. The ce_bus_dis signal routes the data from
the CE Bus port if low; otherwise, data from the other port (as selected by RXDSEL) is routed to the port.
00 Normal mode
01 Internal Network mode
10 CE Bus Network mode
11 Reserved
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which the RxD signals are to be ANDed
together for internal network mode. Bit 6 represents RxD from Port 7 and bit0 represents RxD from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
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Digital Audio Multiplexer (AUDMUX)
13.3.3.6
CE Bus Network Mode Control Register (CNMCR)
Figure 13-5 shows the CE bus network mode control register.
Offset 0x0038 (CNMCR)
Access: User Read/Write
31
19
R
—
W
Reset
0
0
0
0
0
0
0
15
R
Reset
CEN
0
0
8
7
0
0
0
0
0
1
0
0
0
0
17
16
FSPO CLKP
L
OL
1
1
0
CNTHI[7:0]
W
18
CNTLOW[7:0]
0
0
0
0
0
0
1
0
0
0
0
Figure 13-5. CE Bus Network Mode Control Register (CNMCR)
Table 13-8 shows the CNCMR field descriptions.
Table 13-8. CNMCR Field Descriptions
Field
31–19
18
CEN
Description
Reserved
CE Bus enable. This signal controls the generation of ce_bus_dis signal. If set, the ce_bus_dis signal is
generated as per the CNTHI and CNTLOW settings.
0 CE Bus disable signal is held low.
1 CE Bus disable signal is generated.
17
FSPOL
Frame Sync Polarity Select. This field selects the frame sync polarity of the CE Bus port (Port 7) used for the
generation of ce_bus_dis signal.
0 Polarity 0
1 Polarity 1
16
CLKPOL
Clock Polarity Select. This field selects the bit clock polarity of the CE Bus port (Port 7) used for generation
of ce_bus_dis signal.
0 Polarity 0
1 Polarity 1
15–8
CNTHI[7:0]
CE Bus disable signal high period count. This field selects the number of bit clocks for which the CE Bus
disable signal ce_bus_dis is to remain high following the detection of the frame sync, that is, when CE Bus
is not transferring data. This allows the user to specify the time until the CE Bus starts transmitting (with
respect to the beginning of timeslot 0).
00000000 0 bit clock period
00000001 1 bit clock period
00000010 2 bit clock period
…
11111111= 255 bit clock period
• If operating in 4-wire mode (SYN is set), the clock used for ce_bus_dis generation is selected by the
TCSEL[3:0] field of Port 7’s control register PTCR7. The frame sync used for ce_bus_dis generation is
selected by the TFSEL[3:0] field of Port 7’s control register PTCR7.
If operating in 6-wire mode (SYN is clear), the clock used for ce_bus_dis generation is selected by the
RCSEL[3:0] field of Port 7’s control register PTCR7. The frame sync used for ce_bus_dis generation is
selected by the RFSEL[3:0] field of Port 7’s control register PTCR7.
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Digital Audio Multiplexer (AUDMUX)
Table 13-8. CNMCR Field Descriptions (continued)
Field
Description
7–0
CNTLOW[7:0]
CNTLOW - CE Bus disable signal low period count. This field selects the number of bit clocks for which the
CE Bus disable signal ce_bus_dis is to remain low, that is, when CE Bus is transferring data.
00000000 = 0 bit clock period
00000001 = 1 bit clock period
00000010 = 2 bit clock period
...
...
...
11111111 = 255 bit clock period
• If operating in 4-wire mode (SYN is set), the clock used for ce_bus_dis generation is selected by the
TCSEL[3:0] field of Port 7’s control register PTCR7. The frame sync used for ce_bus_dis generation is
selected by the TFSEL[3:0] field of Port 7’s control register PTCR7.
If operating in 6-wire mode (SYN is clear), the clock used for ce_bus_dis generation is selected by the
RCSEL[3:0] field of Port 7’s control register PTCR7. The frame sync used for ce_bus_dis generation is
selected by the RFSEL[3:0] field of Port 7’s control register PTCR7.
13.3.3.6.1
CE_Bus_dis Signal Generation Limitations
Certain restrictions are in place for the utilization of CE Bus network mode. They are as follows:
• Only early frame syncs are supported.
• CE Bus data transfers only take place in contiguous time slots.
• Only one port can be connected to the CE Bus port at a time.
• CE Bus Network mode can be used for only two ports (Port 7 and one other port).
Transmission of data by CE bus and frame sync generation by the master (CE bus/port) occurs on the same
clock edge. This assures a 1/2-bit delay between the moment the RxD lines are switched inside the
AUDMUX (as driven by ce_bus_dis) and the moment the receive data is sampled by the serial interface.
13.4
Functional Description
This section provides a complete functional description of the AUDMUX module. Figure 13-1 shows the
AUDMUX block diagram.
13.4.1
AUDMUX Ports Overview
There is no functional difference among Ports 1 through 7. The main difference is whether a port is
connected to an on-chip serial interface (for example, SSI) or connected to the chip’s pads to connect to
off-chip serial devices (that is, any 4-wire or 6-wire external SSI, voice, I2S, or AC97 CODEC).
Port 7 can be physically connected to any of the peripherals previously mentioned, as well as the CE Bus.
The limitation of connecting CE Bus only at Port 7 is because of data selection in CE bus network mode
at Ports 1 to 7. Ports 1 to 6 communicate with CE Bus devices by being configured to connect to Port 7.
All ports can be configured as four- or six-wire interfaces. When configured as a six-wire interface, the
additional RFS and RCLK signals of the interface enable the serial interface to be used in asynchronous
mode with separate receive and transmit clocks.
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Digital Audio Multiplexer (AUDMUX)
All ports have a Tx/Rx switch to provide flexibility in supporting network mode configurations. The Tx/Rx
switch enables the transmit and receive data lines to be swapped so that mastership of the serial bus can be
passed among multiple external devices connected to a single port.
In addition to supporting the default (point-to-point) normal mode, all ports also support two special types
of network mode—internal network mode and CE bus network mode. With internal network mode, a
point-to-multipoint network configuration with an arbitrary number of slaves can be supported if the
external slaves are put into the high-impedance state (as defined in the SSI network mode protocol) and
have pull-up resistors on their TxD contacts. (Alternatively, this can be viewed as requiring a pull-up
resistor on the corresponding AUDMUX RxD contact.) With CE bus network mode, a point-to-multipoint
network with two slaves can be supported; the slaves do not have to put the TxD line into high-impedance
state, and they do not require any pull-up resistors.
Bit clock direction selection enables each port to be configured as a master or slave in the flow.
Possible scenarios include:
• SSI (internal port) drives a voice CODEC and a BT (Blue tooth) CODEC (both on external Port 6)
and the Bottom Connector (on external Port 7) simultaneously using network mode. SSI is the
master.
• An external processor (external port - Port 5) drives a voice CODEC and a BT CODEC (both on
external Port 6) and the Bottom Connector (on Port 7) simultaneously using network mode. The
external processor is the master.
13.4.2
Operating Modes
The following terms are used in the descriptions of AUDMUX operating modes:
• Network mode—Time-division multiplexed protocol for sending unique data to multiple devices
on a serial bus.
• Internal network mode—Physical bus configuration where multiple serial buses are effectively
connected within the AUDMUX using digital logic to create point-to-multipoint connectivity. An
arbitrary number of devices are supported. Devices must be put into the high-impedance state as
specified by the network mode protocol. TxDATA lines of devices must be pulled high.
• External network mode—Physical bus configuration where multiple serial buses are electrically
connected together on a printed circuit board (that is, external to the AUDMUX). Devices must put
their TxDATA lines into the high-impedance state as specified by the network mode protocol.
• CE bus network mode—Physical bus configuration where multiple serial buses are effectively
connected within the AUDMUX using digital logic in order to create point-to-multipoint
connectivity. This mode can only utilize three AUDMUX ports simultaneously. One of the ports
must be Port 7. Devices do not have to be put into the high-impedance state, nor do they require
pull-up resistors on their TxDATA contacts.
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Digital Audio Multiplexer (AUDMUX)
13.4.2.1
Port Receive Data Modes
Each port has logic to select which data lines are used to create the RxD line for the corresponding host
interface. Figure 13-6 shows the logic used to create the RxD line for Port 1. This logic has the following
modes of operation (as determined by MODE[1:0]):
• Normal mode—see Section 13.4.2.1.1, “Normal Mode,” for more information
• CE bus network mode—see Section 13.4.2.1.3, “CE Bus Network Mode,” for more information
• Internal network mode—see Section 13.4.2.1.2, “Internal Network Mode,” for more information
INMMASK[7:0]
1
AUDMUX boundary
Signal selection for
internal network mode
1
RxD
(Port x)
0
TxD1_in
TxD2_in
TxD3_in
TxD4_in
TxD5_in
TxD6_in
TxD7_in
MODE
RXDSEL[2:0]
Figure 13-6. Receive Data Logic for Port n
13.4.2.1.1
Normal Mode
In normal mode (MODE = 00), the port is connected in a point-to-point configuration (as a master or a
slave) and the RXDSEL[2:0] setting selects the transmit signal from any port. In normal mode, any data
format can be used (that is, SSI normal mode, SSI network mode, AC-97, and others.
13.4.2.1.2
Internal Network Mode
In internal network mode (MODE = 01), the output of the AND gate is routed (using the output of the port)
to the RxD signal of the corresponding host interface. The INMMASK bit vector selects the transmit
signals of the ports that are to be connected in network mode. The transmit signals received at the
AUDMUX ports (TxDn_in) are ANDed together to form the output. In internal network mode, only one
device can be transmitting in its predesignated timeslot and all other transmit signals must remain high (be
in high-impedance state and pulled-up). Therefore, non-active signals in the selection will be high and do
not influence the output of the AND gate.
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Digital Audio Multiplexer (AUDMUX)
Network mode is a protocol where a master SSI is connected to more than one slave SSI device and
communication occurs on a time-slotted frame. Though network mode can allow master-slave and
slave-slave communication, internal network mode supports only master-slave communication.
There are two scenarios where internal network mode can be used with external network mode:
1. Slave-only devices are attached to an external port.
2. A master device is attached to an external port and all slave devices connected to the same external
port are disabled.
NOTE
When internal network mode is enabled at an external port, RXDSEL[3:0]
for RxDn_obe selection is ignored and RxD_obe is always driven high (that
is, asserted for all timeslots). All slave devices connected to the same port
must be disabled.
Internal Network Mode Example 1
SSI_m and SSI_n are used with Port 4 in internal network mode as shown in Figure 13-7. No pull-up
resistors are required because the interfaces combined in internal network mode are on-chip interfaces.
AUDMUX
Port 4
Device
Port 1
Port 5
KEY
SSI_m
Port x
Internal
Network Mode
Enabled
Port x
Active
Port x
Inactive
Port 2
Port 6
SSI_n
Port 3
Port 7
Figure 13-7. Block Diagram For Example 1
See Figure 13-8 for the timing diagram of Example 1. The clock and frame sync signals show the bit and
frame timing for the serial bus. The vertical dashed lines divide the frame into four timeslots.
The data lines for SSI_m and SSI_n (as well as their output enables) are shown. The on-chip interfaces
drive a logic ‘1’ when their output enables are logic ‘0’. The combined TxDATA line, which is the logical
AND of the individual TxDATA lines, is used for Port 4’s TxDATA line.
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Digital Audio Multiplexer (AUDMUX)
...
CLK
...
...
...
FS
SSI_m TxD
T0 (SSI_m LEFT)
T1 (SSI_m RIGHT)
T2
T3
SSI_m OE
SSI_n TxD
T0
T1
T2 (SSI_n LEFT)
T3 (SSI_n RIGHT)
T2 (SSI_n LEFT)
T3 (SSI_n RIGHT)
SSI_n OE
Combined TxD
(Port 4 RxD)
T0 (SSI_m LEFT)
T1 (SSI_m RIGHT)
Figure 13-8. Example Using Internal Ports for Transmit Data
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Digital Audio Multiplexer (AUDMUX)
Internal Network Mode Example 2
Figure 13-9 shows the case where SSI, port 4, and port 5 are used with port 6 in internal network mode.
Port 4 and port 5 are external ports so pull-up resistors are required on the port 4 RxDATA and port 5
RxDATA contacts. This example shows the timing associated with using adjacent timeslots for the SSI,
Port 4, and Port 5.
Pull-up Resistor On
TxDATA Required
AUDMUX
Port 4
SSI
Device
Pull-up Resistor On
TxDATA Required
Port 1
Port 5
Device
KEY
Port 2
Port 6
Device
Port 3
Port n
Internal
Network Mode
Enabled
Port n
Active
Port n
Inactive
Port 7
Figure 13-9. Block Diagram for Example 2
The resistance value of the pull-up resistors must be sufficiently high such that a value of 0 can be pulled
up to logic 1 within half of a period of the bit clock. The required resistance must be no larger than:
Rmax = 1 / (2 × fbc × C)
where:
fbc is the frequency of the bit clock
C is the total system capacitance (including capacitance of ICs, board traces, and so on)
Figure 13-10 shows the timing diagram for this example. The clock and frame sync signals show the bit
and frame timing for the serial bus. The vertical dashed lines divide the frame into four timeslots. Adjacent
timeslots are allocated to SSI, port 4, port 5, and port 4, respectively.
The data lines for the SSI, port 4, and port 5 are shown. The SSI transmits a logic 1 when its corresponding
output enable is a logic 0. The data lines from port 4 and port 5 at the contact are pulled high by pull-up
resistors when they are in the high-impedance state. The data lines from port 4 and port 5 at the AUDMUX
are pure digital signals and are constantly driven. The combined TxDATA line, which is the logical AND
of the SSI, port 4, and port 5’s TxDATA lines, is used for port 6’s TxDATA line.
The highlighted areas in Figure 13-10show the transition time that occurs while a TxDATA line is being
pulled high. In this example, this transition time is a maximum of half the period of the serial bit clock.
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Digital Audio Multiplexer (AUDMUX)
This prevents corruption of the first data bit of the next timeslot. It is critical that the pull-up resistance is
sufficient for the given bit clock frequency and system capacitance.
Hysteresis must be enabled at port 4’s RxDATA contact and port 5’s RxDATA contact to prevent the digital
signals created by the contact from toggling rapidly during the pull-up period. The contacts typically
require a transition within 25 ns unless hysteresis is enabled. Instead of using hysteresis, one could select
a pull-up resistor sufficiently high to pull-up the signal at the contact within 25 ns; however, that would
result in a higher resistance value and higher current drain.
...
CLK
...
...
...
FS
T0
SSI TxD
T1
T2
T3
HiZ
T3
SSI OE
1/2 Bit
Port 4 TxD
(At SoC Contact)
1/2 Bit
HiZ
Port 4 TxD
(At AUDMUX)
T1
T1
T3
1/2 Bit
Port 5 TxD
(At SoC Contact)
HiZ
HiZ
HiZ
T2
Port 5 TxD
(At AUDMUX)
Combined TxD
(Port 6 RxD)
T2
T0
T1
T2
T3
Figure 13-10. Example Using External Ports for Transmit Data in Consecutive Timeslots
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Digital Audio Multiplexer (AUDMUX)
Internal Network Mode Example 3
Figure 13-11 shows the case where SSI and port 4 are used with port 6 in internal network mode. Since
port 4 is an external port, a pull-up resistor is required on the port 4 TxDATA contact. This example shows
the timing associated with inserting empty timeslots after the timeslots have been used by external ports.
Pull-up Resistor On
TxDATA Required
AUDMUX
Port 4
SSI
Device
Port 1
Port 5
KEY
Port 2
Port 6
Device
Port 3
Port n
Internal
Network Mode
Enabled
Port n
Active
Port n
Inactive
Port 7
Figure 13-11. Block Diagram for Example 3
The resistance value of the pull-up resistor must be sufficiently high such that a logic 0 can be pulled up
to logic 1 by the time that the next occupied timeslot occurs. This allows a much weaker pull-up to be used
as compared to Example 2. The required resistance must be no larger than:
Rmax = (4 × n + 1) / (2 × fbc × C)
where:
n is the number of bits per timeslot
fbc is the frequency of the bit clock
C is the total system capacitance (ICs, board traces, and so on)
Figure 13-12 shows the timing diagram for this example. The clock and frame sync signals show the bit
and frame timing for the serial bus. The vertical dashed lines divide the frame into four timeslots. In this
example, empty timeslots are inserted after the timeslots have been used by external ports.
The data lines for the SSI and Port 4 are shown. The SSI transmits a logic 1 when its corresponding output
enable is a logic 0. The data line from Port 4 at the contact is pulled high by a pull-up resistor when they
are in the high-impedance state. The data line from Port 4 at the AUDMUX is a pure digital signal and is
constantly driven. The combined TxDATA line, which is the logical AND of the SSI and Port 4’s TxDATA
lines, is used for Port 6’s RxDATA line.
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Digital Audio Multiplexer (AUDMUX)
The highlighted areas in Figure 13-12show the transition time that occurs while port 4’s TxDATA line is
being pulled high. In this example, this transition time is a maximum of two timeslots plus 1/2 the period
of the serial bit clock. This prevents corruption of the first data bit of the next timeslot. It is critical that the
pull-up resistance is sufficient for the given bit clock frequency and system capacitance.
Hysteresis must be enabled at port 4’s RxDATA contact to prevent the digital signal created by the contact
from toggling rapidly during the extended pull-up period. The contacts typically require a transition within
25 ns unless hysteresis is enabled.
...
CLK
...
...
...
FS
SSI TxD
T0
T1
T2
T3
HiZ
T1
HiZ
HiZ
SSI OE
1/2 Bit
Port 4 TxD
(At SoC Contact)
Port 4 TxD
(At AUDMUX)
T1
Combined TxD
(Port 6 RxD)
T0
T1
Figure 13-12. Example Using External Ports for Transmit Data in Nonconsecutive Timeslots
13.4.2.1.3
CE Bus Network Mode
To support network mode with devices connected to CE bus, a special network mode has been added. In
CE bus network mode (MODE[1:0] = 10), a 2 × 1 multiplexer is used to synchronously switch between
two ports (that is, network slaves) as determined by a signal called ce_bus_dis, which is generated by the
AUDMUX. CE bus network mode supports switching between two ports. One of the ports is the CE bus
port (Port 7) and the other port is selected by RXDSEL[2:0]. In contrast to internal network mode, external
ports do not require pull-up resistors, as the CE bus network mode logic switches data lines according to
the timeslot timing.
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Digital Audio Multiplexer (AUDMUX)
ce_bus_dis Signal Generation
The AUDMUX uses clock and frame sync timing to generate the ce_bus_dis signal (and thus drive the
synchronous multiplexer used in CE bus network mode). The CE bus controls a contiguous block of
timeslots. In addition, each timeslot is controlled by one of the two ports. For example, Port 7 (CE bus)
could transmit in timeslots 1-2 and Port 6 could transmit in timeslots 0 and 3.
If the CEN bit is set, the ce_bus_dis signal generation logic is enabled. Otherwise, the signal generation
logic is disabled and the ce_bus_dis signal remains low.
The CNTLOW[7:0] field controls the number of bit clock periods for which the ce_bus_dis signal is held
low. This establishes the length of the CE Bus port’s timeslot(s).
The CNTHI[7:0] field controls the number of bit clock periods for which the ce_bus_dis signal is held high
after frame sync detection. This establishes the number of bits between the frame sync detection and the
start of the CE bus port’s timeslot(s). The internal counter used to determine the deassertion of the
ce_bus_dis signal is reset on every frame sync. This assures that the number of bit clock periods during
which the ce_bus_dis signal is held high after the assertion of frame sync is always correct.
The Port 7 control register PTCR7 selects the frame sync used to generate the ce_bus_dis signal. If the
SYN bit is set, then frame sync is determined by the TFSDIR and TFSEL[3:0] fields of PTCR7. If the SYN
bit is clear (that is, Port 7 is 6-wire), then TxFS is determined by the TFSDIR and TFSEL[3:0] and the
RxFS is determined by the RFSDIR and RFSEL[3:0] fields.
Similarly, the Port 7 control register PTCR7 determines the bit clock used for counting the low and high
periods of the ce_bus_dis signal. If the SYN bit is set, then the bit clock is determined by the TCLKDIR
and TCSEL[3:0] fields of PTCR7. If the SYN bit is clear (that is, Port 7 is 6-wire), then TxCLK is
determined by the TCLKDIR and TCSEL[3:0] and the RxCLK is determined by RCLKDIR and
RCSEL[3:0] fields of PTCR7.
The FSPOL and CLKPOL fields of the CNMCR determine the frame sync and bit clock polarities used
for frame sync detection. Different scenarios with combinations of frame sync and bit clock polarities are
shown in Figure 13-13 through Figure 13-17. For all these scenarios, CEN is set to 1. In RxDn_in, n can
be any number from 1 and 6.
The CE bus network mode control register CNMCR is used to control the generation of the ce_bus_dis
signal. See Section 13.3.3.6, “CE Bus Network Mode Control Register (CNMCR),” for complete details
on the CNMCR.
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Digital Audio Multiplexer (AUDMUX)
FS
Bit CLK
RxDATA1
RxDn_in
CE bus data
RxDn_in
ce_bus_dis
Figure 13-13. ce_bus_dis Signal Timing for FSPOL=0, CLKPOL=0, CNTLOW=3, CNTHI=0
FS
Bit CLK
RxDATA1
RxDn_in
RxDn_in
CE bus data
ce_bus_dis
Figure 13-14. ce_bus_dis Signal Timing with FSPOL=0, CLKPOL=1, CNTLOW=0b11, CNTHI=0b11
FS
Bit CLK
RxDATA1
RxDn_in
CE bus data
RxDn_in
ce_bus_dis
Figure 13-15. ce_bus_dis Signal Timing with FSPOL=1, CLKPOL=0, CNTLOW=0b11, CNTHI=0
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Digital Audio Multiplexer (AUDMUX)
FS
Bit CLK
RxDATA1
RxDn_in
CE bus data
RxDn_in
ce_bus_dis
Figure 13-16. ce_bus_dis Signal Timing with FSPOL=1, CLKPOL=1, CNTLOW=0b11, CNTHI=0b11
FS
Bit CLK
RxDATA1
RxDn_in
CE bus data
RxDn_in
ce_bus_dis
Figure 13-17. ce_bus_dis Signal Timing with FSPOL=1, CLKPOL=1, CNTLOW=0b110, CNTHI=0
13.4.2.2
Transmit Data Output Enable Assertion
The TxDATA line from the internal network mode master (connected at any internal port) is put into the
high-impedance state at the contact depending upon the assertion or negation of TxD_obe. Its
corresponding output enable is generated by the network mode master.
In the case of an external network mode master (connected at an external port), the corresponding
TxD_obe is always asserted after the port data register configuration.
13.4.2.3
Tx/Rx Switch and External Network Mode
External network mode is the traditional network mode connection. It is called external network mode to
differentiate from the internal network mode. In external network mode, devices are connected to a single
external port in a star or multi-drop configuration.
In network mode, there can be only one master (driving the frame sync and clock source) with the other
devices configured in normal slave mode or network slave mode. Unlike internal network mode, both
master-slave and slave-slave communication can take place in external network mode. CODEC devices
transmit on a single timeslot while processor serial interfaces (that is, SSI) can process more than one
timeslot of data while in network master or slave mode.
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Digital Audio Multiplexer (AUDMUX)
Figure 13-18 shows the Tx/Rx data switch. RxD_obe is the output buffer enable signal and RxD_out is the
data transmit signal from the serial interface. The TxD_in signal is the receive data signal going towards
the RXDSEL multiplexers of all ports.
D_TxRx is the data contact that serves as the chip-level transmit data contact when the TxRx switch is not
enabled. D_RxTx is the data contact that serves as the chip-level receive data contact when the TxRx
switch is not enabled. The roles of these contacts are reversed when the TxRx switch is enabled.
When TXRXEN is disabled (TXRXEN=0), RxD_out is routed to D_TxRx and D_RxTx is routed to
TxD_in. The output buffer enable, selected by RXDSEL[2:0], is routed to Db_obe.
When the Tx/Rx switch is enabled (TXRXEN=1), RxD_out is routed to D_RxTx and D_TxRx is routed
to TxD_in. The output buffer enable, selected by RXDSEL[2:0], is routed to Da_obe.
If the RXDSELn[2:0] field for any port n is configured to select data from an internal port, the output buffer
enable is selected by RXDSELn[2:0] and is routed to Dan_obe / Dbn_obe. In the case when the
RXDSELn[2:0] field for port n is configured to select data from an external port, the output buffer enable
is always high and routed to Dan_obe / Dbn_obe, depending on the TXRXENn switch configuration.
AUDMUX BOUNDARY
Contact Interface Boundary
TXRXEN
Db_obe
RxD_obe
IOPAD
D_TxRx
Db_out
RxD_out
Db_in
Da_obe
IOPAD
Da_out
D_RxTx
Da_in
TxD_in
TX/RX SWITCH
Figure 13-18. Tx/Rx Switch
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Digital Audio Multiplexer (AUDMUX)
13.4.2.4
Timing Modes
The AUDMUX ports are constructed as 6-wire interfaces. However, they can be used either in synchronous
or asynchronous modes as determined by the SYN bit.
13.4.2.4.1
Synchronous Mode (4-Wire Interface)
In synchronous mode, the port has a 4-wire interface (that is, RxD, TxD, TxCLK, TxFS). The receive data
timing is determined by TxCLK and TxFS.
As shown in Figure 13-19, port n signals can be routed to port m, producing 6-wire to 4-wire port
connectivity.
TFS_in, RFS_in, TCLK_in, and RCLK_in are the input frame sync and bit clocks from the serial interface
(port n) with their corresponding output buffer enable signals (_obe). TFS_out, RFS_out, TCLK_out, and
RCLK_out are the frame sync and bit clocks that are transmitted to the serial interface from the other ports.
The TFS_out and TCLK_out are selected at port n by the TFSEL and TCSEL multiplexer settings,
respectively. RFS_out and RCLK_out are selected at port n by the RFSEL and RCSEL multiplexer
settings, respectively. Similarly, in the external direction, port m is configured as a 4-wire port; TFSEL
selects the FS_obe and FS_out signals. In this mode, the configuration of RFSEL and RCSEL is not used,
since the RFS_out and RCLK_out contacts at port m are not available.
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Digital Audio Multiplexer (AUDMUX)
AUDMUX Boundary
RFSELn[3:0]
TFSELm[3:0]
AUDMUX Boundary
Contact Boundary
Port m
Port n
TFS_obe
TFS_in
FS_obe
TFS_out
TxFS
FS_out
FS_in
RFS_obe
IOPAD
RFS_in
RFS_out
TFSELx[3:0]
TFSx_obe, TFSx_in, RFSx_obe,
RFSx_in and FSx_in to/from other ports
RCSELn[3:0]
TFSELm[3:0]
TCLK_obe
TCLK_in
CLK_obe
TCLK_out
TxCLK
CLK_out
CLK_in
RCLK_obe
IOPAD
RCLK_in
RCLK_out
TCSELx[3:0] TCLKx_obe, TCLKx_in, RCLKx_obe
RCLKx_in and CLKx_in
to/from other ports
Figure 13-19. Frame Sync and Clock Routing When External Port Is 4-Wire
13.4.2.4.2
Asynchronous Mode (6-Wire Interface)
In asynchronous mode, the port has a 6-wire interface (including RxD, TxD, TxCLK, TxFS, RxCLK, and
RxFS). This mode has additional receive clock (RxCLK) and frame sync (RxFS) signals as compared to
the synchronous or 4-wire interface.
As shown in Figure 13-20 and Figure 13-21, port n signals can be routed to port m, producing 6-wire to
6-wire port connectivity.
TFS_in, RFS_in, TCLK_in, and RCLK_in are input frame sync and bit clocks from the serial interface
(port n) with their corresponding output buffer enable signals (_obe). TFS_out, RFS_out, TCLK_out, and
RCLK_out are the frame sync and bit clocks that are transmitted to the serial interface from the other ports.
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Digital Audio Multiplexer (AUDMUX)
TFS_out and TCLK_out are selected by the TFSEL and TCSEL multiplexer settings, respectively.
RFS_out and RCLK_out are selected by the RFSEL and RCSEL multiplexer settings, respectively.
Similarly, in the external direction, the TFSEL selects the TxFS_obe and TxFS_out signals and TCSEL
selects the TxCLK_obe and TxClk_out signals. The RFSEL selects the RxFS_obe and RxFS_out signals
and RCSEL selects the RxCLK_obe and RxCLK_out signals.
NOTE
Since FS_in and CLK_in from external interfaces are also routed to the
TFSEL and TCSEL multiplexers of the external ports, respectively, these
signals do not have corresponding buffer enable signals. Consequently, their
corresponding inputs to the TFSEL and TCSEL multiplexer of the external
ports have to be tied high.
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Digital Audio Multiplexer (AUDMUX)
AUDMUX Boundary
RFSELn[3:0]
TFSELm[3:0]
AUDMUX Boundary
Contact Boundary
Port m
Port n
TFS_obe
TFS_in
TFS_obe
TFS_out
TxFS
TFS_out
TFS_in
RFS_obe
IOPAD
RFS_in
RFS_out
TFSELx[3:0]
TFSx_obe, TFSx_in, RFSx_obe,
RFSx_in and FSx_in to/from other ports
RFSELn[3:0]
RFSELm[3:0]
TFS_obe
TFS_in
RFS_obe
TFS_out
RxFS
RFS_out
RFS_in
RFS_obe
IOPAD
RFS_in
RFS_out
TFSELx[3:0] TFSx_obe, TFSx_in, RFSKx_obe
RFSx_in and FSx_in
to/from other ports
Figure 13-20. Frame Sync Routing When External Port is 6-Wire
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Digital Audio Multiplexer (AUDMUX)
AUDMUX Boundary
RCSELn[3:0]
TCSELm[3:0]
AUDMUX Boundary
Contact Boundary
Port m
Port n
TCLK_obe
TCLK_in
TCLK_obe
TCLK_out
TxCLK
TCLK_out
TCLK_in
RCLK_obe
IOPAD
RCLK_in
RCLK_out
TClkx_obe, TClkx_in, RClkx_obe,
RClkx_in and Clkx_in to/from other ports
RCSELn[3:0]
RCSELm[3:0]
TCLK_obe
TCLK_in
RCLK_obe
TCLK_out
RxCLK
RCLK_out
RCLK_in
RCLK_obe
IOPAD
RCLK_in
RCLK_out
TCSELx[3:0] TCLKx_obe, TCLKx_in, RCLKx_obe
RCLKx_in and CLKx_in
to/from other ports
Figure 13-21. Clock Routing When External Port is 6-Wire
13.4.3
AUDMUX Default Configuration
The AUDMUX reverts back to its default settings following a reset. Section 13.4.3.1, “Default Port
Configuration,” and Section 13.4.3.2, “Default CE Bus Configuration,” describes the default configuration
of the ports and CE Bus, respectively.
13.4.3.1
Default Port Configuration
After a reset, each port defaults to normal mode (PDCRn[MODE] = 00) with synchronous timing mode
(PTCRn[SYN] = 1) enabled.
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Digital Audio Multiplexer (AUDMUX)
The default port-to-port connections are as follows:
• Port 1 to Port 6
— Port 6 provides the clock and frame sync.
• Port 2 to Port 5
— Port 5 provides the clock and frame sync.
• Port 3 to Port 4
— Port 4 provides the clock and frame sync.
• Port 7 to Port 7 (in data loopback mode)
— Clock and frame syncs are inputs.
13.4.3.2
Default CE Bus Configuration
The default configuration of all the ports is to set the MODE field to normal mode (that is, no port selects
CE Bus network mode). Correspondingly, the default configuration of the CEN field in the CNMCR is
clear. To minimize AUDMUX setup for audio testing, the rest of the CNMCR fields default to the
following configuration:
• FSPOL is set.
• CLKPOL is set.
• CNTHI is set to 16.
• CNTLOW is set to 16.
This configuration uses a frame sync that is logic high when asserted.
The clock is driven by the transmitter on the rising edge and is sampled by the receiver on the falling edge.
The AUDMUX switches between devices on the rising edge; this provides a buffer of one-half clock period
between the moment data is sampled and when the AUDMUX switches between devices. See
Figure 13-16 for a timing diagram where FSPOL and CLKPOL are both set.
CNTHI and CNTLOW are set to 16 to allow CE Bus to drive data during timeslot 1 and the other device
to drive data during timeslots 0, 2, …, N-1 where N is the number of timeslots used and each timeslot has
16 bits.
13.4.4
Connectivity Between Ports
Four basic types of connections are provided by the AUDMUX:
• Internal port to external port
• External port to external port
• Internal port to internal port
• Loopback
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Digital Audio Multiplexer (AUDMUX)
13.4.4.1
Internal Port to External Port Connectivity
The internal port is connected to a processor’s serial interface. TxD_obe is the buffer enable signal from
the serial interface, TxD_in is the input transmit data from the serial interface to the AUDMUX, and
RxD_out is the receive data output from the AUDMUX to the serial interface.
RXDSEL[2:0] of the external port selects the buffer enable signal (TxD_obe) and transmit data output
(TxD_out) signal from the TxD_obe and RxD_in signals. RXDSEL[2:0] is a common signal to both
selection MUXes.
NOTE
Since buffer TxD_in signals from external interfaces do not have
corresponding buffer enable signals, their buffer enable signals into the
selection multiplexer are tied high. This ensures that selection of TxD_in, as
RxD_out also drives the RxD_obe output high.
Transmit Data from the serial interface goes into the RXDSEL data multiplexer and comes out as
RxD_out. RxD_out is routed to Da_TxRx when TXRXEN is disabled and to D_RxTx when TXRXEN is
enabled. Similarly, D_RxTx is routed to TxD_in when TXRXEN is disabled and D_TxRx is routed to
TxD_in when TXRXEN is enabled. The routing of frame syncs is shown in Figure 13-20 and the routing
of interface clocks is shown in Figure 13-21.
If internal network mode is disabled, then RXDSEL selects the TxD_in, which is sent from the AUDMUX
to the serial interface connected at port n. When the internal network mode is selected, RxD_out is
constructed by ANDing selected TxD_in signals from the ports (as determined by INMMASK).
If there is more than one device attached to the external port at D_TxRx and D_RxTx and one of the
devices is a network master, then following conditions must be observed:
1. When the external master is enabled in network mode, then the serial interface at port n must be
configured as a slave (normal or network mode). No Tx/Rx switching is required.
2. When the external master is disabled and the serial interface at port n and other slave devices must
communicate, then the serial interface at port n must be configured as a network mode master and
the Tx/Rx switch at port m must be enabled (TXRXEN=1). This ensures that the transmit and
receive paths are connected appropriately.
To communicate with more than one port, internal network mode can be enabled at port n. In internal
network mode, it is possible to communicate with any device attached to the other ports. Internal network
mode shall be enabled at the port that is the SSI network mode master.
It is also possible for a port to communicate with two (and only two) ports by enabling CE Bus network
mode at Port n. It is then possible to communicate with any device attached to two enabled ports; one of
which is Port 7 and the other is selected by RXDSELn[2:0]. CE Bus network mode is enabled at the port
that is the SSI network mode master.
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Digital Audio Multiplexer (AUDMUX)
13.4.4.2
External Port to External Port Connectivity
External ports can communicate with external ports directly. External ports can communicate together in
the following ways:
1. Each port’s receive logic is configured in normal mode (MODE = 00). Each port’s RXDSEL[2:0]
field is configured to select the other port’s transmit data. Bit fields associated with clock/frame
sync selection and direction are configured for each port. Either port can be the master.
2. One port is configured in internal network mode (MODE = 01). All desired data lines are combined
by the AND gate as determined by INMMASK[7:0]. Since an external port is being used as the
internal network mode master, all other devices on the same AUDMUX port as the internal network
mode master must be disabled. This configuration can be used with a combination of internal and
external ports. All external ports must have a pull-up resistor on its RxDATA pin. Bit fields
associated with clock/frame sync selection and direction are configured for each port. Any port can
be the master.
3. One port is configured in CE Bus network mode (MODE[0:1] = 10) to receive and/or transmit data
from and to the CE Bus connected to Port 7 and one other port. The ce_bus_dis signal is generated
by the AUDMUX depending upon the CNMCR register configuration. Bit fields associated with
clock/frame sync selection and direction are configured for each port. Any of the three ports can
be the master.
13.4.4.3
Internal Port to Internal Port Connectivity
Internal ports can communicate with other internal ports directly, thereby providing a means for
synchronous interprocessor communication. Internal ports can communicate together in three ways:
1. Each port’s receive logic is configured in normal mode (MODE = 00). Each port’s RXDSEL[2:0]
field is configured to select the other port’s transmit data. Bit fields associated with clock/frame
sync selection and direction are configured for each port. Either port can be the master.
2. One port is configured in internal network mode (MODE = 01). All desired data lines are combined
by the AND gate as determined by INMMASK[7:0]. This configuration can be used with a
combination of internal and external ports. All external ports must have a pull-up resistor on its
RxDATA pin. Bit fields associated with clock/frame sync selection and direction are configured for
each port. Any port can be the master.
3. One port is configured in CE Bus network mode (MODE[0:1] = 10) to receive and/or transmit data
from and to the CE Bus connected at Port 7 and one other port. The ce_bus_dis signal is generated
by the AUDMUX depending upon the CNMCR register configuration. Bit fields associated with
clock/frame sync selection and direction are configured for each port. Any of the three ports can
be the master.
13.4.4.4
Loopback Connectivity
AUDMUX ports can communicate with themselves in order to provide loopback functionality. Port n can
route its TxDATA signal to its own RxD_out signal by setting RXDSELn[2:0] to its own port number. This
is supported by all ports in the AUDMUX.
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Digital Audio Multiplexer (AUDMUX)
In addition, ports can provide loopback support in internal network mode as well as CE Bus network mode.
With internal network mode, the internal network mode master can loop its TxDATA signal (combined
with those of other ports, if desired) back into its RxD_out signal. Port n’s INMMASK must be set such
that bit (n - 1) is clear in order to enable the loopback.
With CE Bus network mode, the CE Bus network mode master can loop its TxDATA signal (combined
with CE Bus’s TxDATA) back into its RxD_in signal. RXDSELn[2:0] must be set to select port n.
13.4.5
AUDMUX Clocking
This section provides information about AUDMUX clocking including clock inputs and the clock
diagram.
13.4.5.1
AUDMUX Clock Inputs
The IP Bus read/write clock— peripheral clock—is an input to the AUDMUX. It is used for all AUDMUX
register accesses. It is driven only when there is an AUDMUX access on the IP bus.
The AUDMUX uses the selected Tx/Rx bit clock to drive the synchronous switching of the CE Bus
Network mode. Specifically, this clock is used to drive the ce_bus_dis signal generation logic. The bit
clock used for this function can come from either internal serial interfaces or external codecs. The clock
used for CE bus network mode is determined by PTCR7. See “ce_bus_dis Signal Generation” for more
details of the clock selection for CE bus network mode.
13.4.5.2
AUDMUX Clock Diagram
Figure 13-22 shows the clocking used in the AUDMUX.
ips_module_en_audmux
AIPS
AUDMUX
LPG
Low Power Gate
CCM
IP Interface
Clock
Gating
Registers
Peripheral clock
Cell
Peripheral clock
Figure 13-22. AUDMUX Clocking Scheme
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Digital Audio Multiplexer (AUDMUX)
13.4.5.3
Clocking Restrictions
Since the AUDMUX requires only peripheral clock, the AUDMUX places no restrictions on the bus
frequency. All registers in the AUDMUX are control registers so their values do not change frequently.
Their values are programmed when changing between use cases (not during use cases).
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Digital Audio Multiplexer (AUDMUX)
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Chapter 14
ARM926EJ-S Simple Interrupt Controller (ASIC)
14.1
Introduction
The ARM926EJ-S Simple Interrupt Controller (ASIC) is a 32-bit peripheral which collects interrupt
requests from up to 64 sources and provides an interface to the ARM926EJ-S core. The ASIC includes:
• Hardware acceleration of normal and fast interrupts
• Software-controlled priority levels for normal interrupts.
Figure 14-1 provides a block diagram of the ASIC.
14.1.1
Features
The ASIC module includes the following features:
•
•
•
•
•
•
•
•
•
Supports up to 64 interrupt sources
Supports fast and normal interrupts
Selects normal or fast interrupt request for any interrupt source
Indicates pending interrupt sources using a register for normal and fast interrupts
Indicates highest priority interrupt number using register (can be used a table index)
Independently enable or disable any interrupt source
Provides a mechanism for software to schedule an interrupt
Supports up to 16 software controlled priority levels for normal interrupts and priority masking
Single bit disabling of all normal interrupts and of all fast interrupts, used in enabling of secure
operations
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14-1
ARM926EJ-S Simple Interrupt Controller (ASIC)
avic_fiq_b
64
INTENABLE
fipend
64
intin_b
64
64
6
Priority
Encoder
avic_rise_arb
fivector
fiad
nivector
niad
FORCE
64
64
64
nipend
INTTYPE
Software
Priority
Encoder
6
avic_irq_b
Figure 14-1. ASIC Block Diagram
14.2
Overview
The interrupt controller consists of a set of control registers and associated logic to perform interrupt
masking, priority support, and hardware acceleration of normal interrupts.
The control registers are summarized as follows:
•
•
•
•
•
•
The interrupt source registers (INTSRCH and INTSRCL) reflect the status of up to 64 interrupt
sources.
The interrupt force registers (INTFRCH and INTFRCL) are used to assert interrupt requests
corresponding to the different interrupt sources.
The interrupt enable registers (INTENABLEH and INTENABLEL) allow individual bit masking
of the interrupt source registers.
The interrupt type registers (INTTYPEH and INTTYPEL) determine the interrupt type (normal or
fast) associated with each interrupt source.
The normal interrupt pending registers (NIPNDH and NIPNDL) indicate pending normal interrupt
requests. These registers are equivalent to the logical AND of the interrupt source and enable
registers (INTENABLEH / INTENABLEL), together with the NOT of the interrupt type registers.
(corresponding to the “nipend” signal in Figure 14-1) The NIPNDH and NIPNDL registers are
bitwise NORed together to form the nIRQ signal (avic_irq_b in Figure 14-1), which is routed to
the ARM926EJ-S core and is maskable by the normal interrupt disable bit in the processor status
register (CPSR). The normal interrupt vector register (NIVECSR) indicates the vector index of the
highest-priority pending normal interrupt.
The fast interrupt pending registers (FIPNDH and FIPNDL) play the same role with fast interrupts
as the normal interrupt pending registers do with normal interrupts. The bitwise nor of FIPNDH
and FIPNDL forms the nFIQ signal (avic_fiq_b in Figure 14-1), which is maskable by the fast
interrupt disable bit in the CPSR. The fast interrupt vector register (FIVECSR) indicates the vector
index of highest priority pending fast interrupt.
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ARM926EJ-S Simple Interrupt Controller (ASIC)
All interrupt controller registers are readable and writable in privileged mode only. Attempted writes to
read-only registers are ignored. These registers are all 32 bits wide, and can be only modified using 32-bit
writes.
Interrupt requests are prioritized in the following sequence:
1. Fast interrupt requests, in order of highest number
2. Normal interrupt requests, in order of highest priority level, then highest source number with the
same priority
The ASIC provides 16 software-controlled priority levels for normal interrupts. Any interrupt can be
placed in any priority level. The ASIC also provides a normal interrupt priority level mask (NIMASK),
which disables any interrupt with a priority level less than or equal to the mask. If a level-0 normal
interrupt and a level-1 normal interrupt are asserted at the same time, the level-1 normal interrupt is
selected assuming that NIMASK has not disabled level-1 normal interrupts. If two level-1 normal
interrupts are asserted at the same time the level-1 normal interrupt with the highest source number is
selected, also assuming that NIMASK has not disabled level 1 normal interrupts.
14.3
Interrupt Controller Programming Model
14.3.1
Register Summary
The ASIC module has 26 registers. All of these registers are single cycle access, as the ASIC sits on the
ARM926EJ-S platform slave port 3 AHB.
Table 14-1 summarizes the ASIC registers—for the module base address, see the system memory map.
Figure 14-2 is a key for the notations used in the table.
KEY:
Always
Reads
One
1
Always
Reads
Zero
Read/
Write
Bit
0
ReadOnly
Bit
bit
WriteOnly
Bit
bit
bit
Write 1 bit
to
Clear W1C
SelfClear
Bit
0
N/A
bit
Figure 14-2. Key to Register Summary
Table 14-1. ASIC Register Summary
Name (Base
Address Offset)
INTCNTL
(0x0000)
31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTENNUM
(0x0008)
W
INTENABLEL
(0x0014)
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 BYP_
0
NIDIS FIDIS
EN
W
INTENABLEH
(0x0010)
22
W
NIMASK
(0x0004)
INTDISNUM
(0x000C)
23
R 0 0 0 0 0 0 0
ENNUM
R 0 0 0 0 0 0 0
DISNUM
W
R
W
R
W
NIMASK
INTENABLE[63:32]
INTENABLE[31:0]
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ARM926EJ-S Simple Interrupt Controller (ASIC)
Table 14-1. ASIC Register Summary
Name (Base
Address Offset)
31 30 29 28 27 26 25 24
23
22
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INTTYPEH
(0x0018)
W
INTTYPEL
(0x001C)
W
INTTYPE[63:32]
R
R
NIPRIORITY7
(0x0020)
W
NIPRIORITY6
(0x0024)
W
R
R
NIPRIORITY5
(0x0028)
W
NIPRIORITY4
(0x002C)
W
R
R
NIPRIORITY3
(0x0030)
W
NIPRIORITY2
(0x0034)
W
R
R
NIPRIORITY1
(0x0038)
W
NIPRIORITY0
(0x003C)
W
R
R
NIVECSR
(0x0040)
W
FIVECSR
(0x0044)
W
R
R
INTSRCH
(0x0048)
W
INTSRCL
(0x004C)
W
R
R
INTFRCH
(0x0050)
W
INTFRCL
(0x0054)
W
R
R
NIPNDH
(0x0058)
W
NIPNDL
(0x005C)
W
R
R
FIPNDH
(0x0060)
W
FIPNDL
(0x0064)
W
R
INTTYPE[31:0]
NIPR63
NIPR62
NIPR61
NIPR60
NIPR59
NIPR58
NIPR57
NIPR56
NIPR55
NIPR54
NIPR53
NIPR52
NIPR51
NIPR50
NIPR49
NIPR48
NIPR47
NIPR46
NIPR45
NIPR44
NIPR43
NIPR42
NIPR41
NIPR40
NIPR39
NIPR38
NIPR37
NIPR36
NIPR35
NIPR34
NIPR33
NIPR32
NIPR31
NIPR30
NIPR29
NIPR28
NIPR27
NIPR26
NIPR25
NIPR24
NIPR23
NIPR22
NIPR21
NIPR20
NIPR19
NIPR18
NIPR17
NIPR16
NIPR15
NIPR14
NIPR13
NIPR12
NIPR11
NIPR10
NIPR9
NIPR8
NIPR7
NIPR6
NIPR5
NIPR4
NIPR3
NIPR2
NIPR1
NIPR0
NIVECTOR
NIPRILVL
FIVECTOR
INTIN[63:32]
INTIN[31:0]
FORCE[63:32]
FORCE[31:0]
NIPEND[63:32]
NIPEND[31:0]
FIPEND[63:32]
FIPEND[31:0]
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ARM926EJ-S Simple Interrupt Controller (ASIC)
14.3.2
Detailed Register Descriptions
14.3.2.1
Interrupt Control Register
The interrupt control register (INTCNTL) controls the hardware acceleration done by the ASIC. Both
normal interrupts and fast interrupts can be enabled to jump directly to the interrupt service routine.
This register is located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can only
be accessed in privileged mode. This register can only be modified using 32-bit writes.
Offset 0x0000 (INTCNTL)
Access: Privileged read/write
31
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
BYP_EN
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
22
21
NIDIS FIDIS
0
0
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
Figure 14-3. Interrupt Control Register
Table 14-2. Interrupt Control Register Field Descriptions
Field
31–24
Description
Reserved.
23
Bypass enable. This bit, when reset, disables propagation of asynchronous interrupts.
BYPASS_EN 0 Synchronized interrupts (reset value)
1 Asynchronous interrupts.(Backward compatibility.)
22
NIDIS
Normal Interrupt Disable. This bit, when set, disables the generation of the normal interrupt signal. This bit is
similar to the I bit of the ARM926EJ-S core. This bit along with the FIDIS bit is used to enable secure operations.
0 Does not affect the normal interrupt generation
1 Disable all normal interrupts
21
FIDIS
Fast Interrupt Disable. This bit, when set, disables the generation of the fast interrupt signal. This bit is similar
to the F bit of the ARM926EJ-S core. This bit along with the NIDIS bit is used to enable secure operations.
0 Does not affect the fast interrupt generation
1 Disable all fast interrupts
20–0
Reserved.
14.3.2.2
Normal Interrupt Mask Register (NIMASK)
The normal interrupt mask register (NIMASK) controls the normal interrupt mask level. All normal
interrupts with a priority level less than or equal to the value of the NIMASK field (in 2’s complement
notation) are disabled. The priority level of normal interrupts are determined by the normal interrupt
priority level registers NIPRIORITYn, n = 0…7.
Any setting with NIMASK[4] = 1 corresponds to a negative number in 2’s complement notation, and does
not disable any normal interrupt priority levels. The reset value of NIMASK is 0b1_1111 (corresponding
to –1, in 2’s complement notation), which does not disable any normal interrupts.
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14-5
ARM926EJ-S Simple Interrupt Controller (ASIC)
This hardware mechanism can be used to create reentrant normal interrupt routines by disabling lower
priority normal interrupts. Refer to Section 14.4.5, “Writing Reentrant Normal Interrupt Routines,” for
more details on the use of the NIMASK register.
This register is located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can only
be accessed in privileged mode. This register can be only modified using 32-bit writes.
Offset 0x0004 (NIMASK)
R
W
Reset
R
W
Reset
Access: Privileged read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NIMASK
0
0
0
Figure 14-4. Normal Interrupt Mask Register
Table 14-3. NIMASK Descriptions
Field
31–5
4–0
NIMASK
14.3.2.3
Description
Reserved.
Normal Interrupt Mask. Controls normal interrupt mask level. All normal interrupts of priority level lower than or
equal to the NIMASK are disabled.
00000 Disable priority level 0 normal interrupts
00001 Disable priority level 1 and lower normal interrupts
...
011111 Disable all normal interrupts
1nnnn Do not disable any normal interrupts.
Interrupt Enable Number Register (INTENNUM)
The interrupt enable number register (INTENNUM) provides a hardware-accelerated enabling of
interrupts. Any write to this register enables one interrupt source. If the ENNUM field is equal to
0b00_0000, then interrupt source 0 is enabled; if the ENNUM field equal 0b00_0001, then interrupt source
1 is enabled; and so forth. This register is decoded into a “one-hot mask is logically ORed with the
INTENABLEH / INTENABLEL register.
This hardware mechanism alleviates the need for an atomic read/modify/write sequence to enable an
interrupt source. For example, to enable interrupts 10 and 20 the software can perform two writes to the
ASIC: first write 10 to INTENNUM register, then write 20 to INTENNUM register (the order of the writes
is irrelevant).
This register is located on the ARM926EJ-S platform slave port 3 AHB. It is accessible in 1 cycle, and can
only be accessed in privileged mode. This register can be only modified using 32-bit writes. This register
always reads back all 0s.
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Offset 0x0008 (INTENNUM)
R
W
Reset
R
W
Reset
Access: Privileged write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENNUM
0
0
0
0
Figure 14-5. Interrupt Enable Number Register
Table 14-4. INTENNUM Register Field Descriptions
Field
31–6
5–0
ENNUM
14.3.2.4
Description
Reserved.
Interrupt Enable Number. Writing to this register enables the interrupt source associated with this value.
ENNUM bits are self-clearing.
0 Enable interrupt source 0
1 Enable interrupt source 1
...
63 Enable interrupt source 63
Interrupt Disable Number Register (INTDISNUM)
The interrupt disable number register (INTDISNUM) provides a hardware-accelerated disabling of
interrupts. Any write to this register disables one interrupt source. If the DISNUM field is equal 0b000000,
then interrupt source 0 is disabled; if the DISNUM = 0b000001, then interrupt source 1 is disabled; and so
forth. This register is decoded into a “one-hot” mask that is inverted and logically ANDed with the
INTENABLEH / INTENABLEL register.
This hardware mechanism alleviates the need for an atomic read/modify/write sequence to disable an
interrupt source. For instance, to disable interrupts 10 and 20, the software can write 10 to INTDISNUM
register, then write 20 to INTDISNUM register (the order of the writes is irrelevant).
This register is located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can only
be accessed in privileged mode. This register can be only modified using 32-bit writes. This register
always reads back all 0s.
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Freescale Semiconductor
14-7
Offset 0x000C (INTDISNUM)
R
W
Reset
R
W
Reset
Access: Privileged write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DISNUM
0
0
0
0
Figure 14-6. Interrupt Disable Number Register
Table 14-5. INTDISNUM Register Field Descriptions
Field
31 — 6
5–0
DISNUM
14.3.2.5
Description
Reserved.
Interrupt Disable Number. Writing to this register disables the interrupt source associated with this value. The
bits are self-clearing after they are written.
0 Disable interrupt source 0
1 Disable interrupt source 1
...
63 Disable interrupt source 63
Interrupt Enable Registers (INTENABLEH and INTENABLEL)
The interrupt enable register high (INTENABLEH) and the interrupt enable register low (INTENABLEL)
are used to enable pending interrupt requests to the core. Each bit in this register corresponds to an interrupt
source available in the system. The reset state of these registers are all interrupts masked.
This register can be updated by the following methods:
• Writing directly to the INTENABLEH / INTENABLEL registers,
• Setting bits with the INTENNUM register,
• Clearing bits with the INTDISNUM register.
These registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can
only be accessed in privileged mode. These registers can only be modified using 32-bit writes.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-8
Offset 0x0010 (INTENABLEH)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
INTENABLE[63:48]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTENABLE[47:32]
0
0
0
0
0
0
0
0
0
Figure 14-7. Interrupt Enable Register High
Offset 0x0014 (INTENABLEL)
31
R
W
Reset
R
W
Reset
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTENABLE[31:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTENABLE[15:0]
0
0
0
0
0
0
0
0
0
Figure 14-8. Interrupt Enable Register Low
f
Table 14-6. INTENABLEH / INTENABLEL Descriptions
Field
Description
63–0
Interrupt Enable. This bit enables the corresponding interrupt source to request a normal interrupt or a fast
INTENABLE interrupt. A reset operation clears this bit.
If an enable bit is set and the corresponding interrupt source is asserted, the interrupt controller asserts a
normal or a fast interrupt request depending on the associated INTTYPEH / INTTYPEL setting.
0 Interrupt disabled
1 Interrupt enabled and generates a normal or fast interrupt upon assertion
14.3.2.6
Interrupt Type Registers (INTTYPEH and INTTYPEL)
The interrupt type register high (INTTYPEH) and the interrupt type register low (INTTYPEL) are used to
select whether a pending interrupt source, when enabled with the INTENABLEH / INTENABLEL, will
cause a normal interrupt or a fast interrupt to the core. Each bit in this register corresponds to an interrupt
source available in the system. The reset state of these registers cause all enabled interrupt sources to
generate a normal interrupt.
These registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can
only be accessed in privileged mode. These registers can be only modified using 32-bit writes.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-9
Offset 0x0018 (INTTYPEH)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
INTTYPE[63:48]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTTYPE[47:32]
0
0
0
0
0
0
0
0
0
Figure 14-9. Interrupt Type Register High
Offset 0x001C (INTTYPEL)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
INTTYPE[31:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTTYPE[15:0]
0
0
0
0
0
0
0
0
0
Figure 14-10. Interrupt Type Register Low
Table 14-7. INTTYPEH / INTTYPEL Descriptions
Field
Description
63–0
INTTYPE
Interrupt type. This bit controls whether the corresponding interrupt source requests a normal interrupt or a fast
interrupt. If a INTTYPE bit is set and the corresponding interrupt source is asserted, the interrupt controller
asserts a fast interrupt request.
0 Interrupt source generates a normal interrupt (nIRQ)
1 Interrupt source generates a fast interrupt (nFIQ)
14.3.2.7
Normal Interrupt Priority Level Registers (NIPRIORITYn, n = 0…7)
The normal interrupt priority level registers NIPRIORITYn, (n = 0…7) provide a software-controllable
prioritization of normal interrupts. Normal interrupts with a higher priority level preempt normal interrupts
with a lower priority. The reset state of these registers forces all normal interrupts to the lowest priority
level.
If a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal
interrupt is selected assuming that NIMASK has not disabled level 1 normal interrupts. If two level 1
normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number
is selected, also assuming that NIMASK has not disabled level 1 normal interrupts.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-10
These registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can
only be accessed in privileged mode. These registers can be only modified using 32-bit writes.
Offset 0x0020 (NIPRIORITY7)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR63
26
25
24
23
NIPR62
22
21
20
19
NIPR61
18
17
16
NIPR60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR59
0
0
NIPR58
0
0
0
0
0
NIPR57
0
0
0
0
NIPR56
0
0
0
0
0
Figure 14-11. Normal Interrupt Priority Level Register 7
Offset 0x0024 (NIPRIORITY6)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR55
26
25
24
23
NIPR54
22
21
20
19
NIPR53
18
17
16
NIPR52
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR51
0
0
NIPR50
0
0
0
0
0
NIPR49
0
0
0
0
NIPR48
0
0
0
0
0
Figure 14-12. Normal Interrupt Priority Level Register 6
Offset 0x0028 (NIPRIORITY5)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR47
26
25
24
23
NIPR46
22
21
20
19
NIPR45
18
17
16
NIPR44
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR43
0
0
0
NIPR42
0
0
0
0
NIPR41
0
0
0
0
NIPR40
0
0
0
0
0
Figure 14-13. Normal Interrupt Priority Level Register 5
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-11
Offset 0x002C (NIPRIORITY4)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR39
26
25
24
23
NIPR38
22
21
20
19
NIPR37
18
17
16
NIPR36
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR35
0
0
NIPR34
0
0
0
0
0
NIPR33
0
0
0
0
NIPR32
0
0
0
0
0
Figure 14-14. Normal Interrupt Priority Level Register 4
Offset 0x0030 (NIPRIORITY3)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR31
26
25
24
23
NIPR30
22
21
20
19
NIPR29
18
17
16
NIPR28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR27
0
0
NIPR26
0
0
0
0
0
NIPR25
0
0
0
0
NIPR24
0
0
0
0
0
Figure 14-15. Normal Interrupt Priority Level Register 3
Offset 0x0034 (NIPRIORITY2)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR23
26
25
24
23
NIPR22
22
21
20
19
NIPR21
18
17
16
NIPR20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR19
0
0
0
NIPR18
0
0
0
0
NIPR17
0
0
0
0
NIPR16
0
0
0
0
0
Figure 14-16. Normal Interrupt Priority Level Register 2
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-12
Offset 0x0038 (NIPRIORITY1)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR15
26
25
24
23
NIPR14
22
21
20
19
NIPR13
18
17
16
NIPR12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR11
0
0
NIPR10
0
0
0
0
0
NIPR9
0
0
0
0
NIPR9
0
0
0
0
0
Figure 14-17. Normal Interrupt Priority Level Register 1
Offset 0x003C (NIPRIORITY0)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read/write
28
27
NIPR7
26
25
24
23
NIPR6
22
21
20
19
NIPR5
18
17
16
NIPR4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR3
0
0
NIPR2
0
0
0
0
0
NIPR1
0
0
0
0
NIPR0
0
0
0
0
0
Figure 14-18. Normal Interrupt Priority Level Register 1
Table 14-8. Normal Interrupt Priority Level Register 1 Field Descriptions
Field
31–0
NIPRn
(n = 63…0)
14.3.2.8
Description
Normal Interrupt Priority Level — Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
00 Lowest-priority normal interrupt (reset value)
…
15 Highest-priority normal interrupt
Normal Interrupt Vector and Status Register
The normal interrupt vector and status register (NIVECSR) provides the priority of the highest pending
normal interrupt and provides the vector index of the interrupt’s service routine. This hardware mechanism
replaces the previous necessity for core support of the FF1 command. This number can be directly used as
an index into a vector table to select the highest pending normal interrupt source.
This read-only register is located on the ARM926EJ-S platform slave port 3 AHB. It is accessible in 1
cycle, and can only be accessed in privileged mode.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-13
Offset 0x0040 (NIVECSR)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read
28
27
26
25
24
23
22
21
20
19
18
17
16
NIVECTOR
1
1
1
1
1
1
1
15
14
13
12
11
10
9
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
NIPRILVL
1
1
1
1
1
1
1
1
1
Figure 14-19. Normal Interrupt Vector and Status Register
Table 14-9. NIVECSR Register Field Descriptions
Field
31–16
NIVECTOR
15–0
NIPRILVL
14.3.2.9
Description
Normal Interrupt Vector — Indicates vector index for the highest pending normal interrupt.
…
–1 No normal interrupt request pending (reset value)
00 Interrupt 0 highest priority pending normal interrupt
01 Interrupt 1 highest priority pending normal interrupt
...
63 Interrupt 63 highest priority pending normal interrupt
64+ (not –1) = unused, does not occur
Normal Interrupt Priority Level — Indicates the priority level of the highest priority normal interrupt. This number
can be written to the NIMASK to disable the current priority normal interrupts to build a reentrant normal
interrupt system.
–1 No normal interrupt request pending (reset value)
00 Highest priority normal interrupt is level 0
01 Highest priority normal interrupt is level 1
...
15 Highest priority normal interrupt is level 15
16 (not –1) = unused, does not occur
Fast Interrupt Vector and Status Register
The fast interrupt vector and status register (FIVECSR) provides the vector index for the highest priority
active fast interrupt’s service routine (the higher the source number of the fast interrupt, the higher the
priority level). This hardware mechanism replaces the previous necessity for core support of the FF1
command. This number can be directly used as an index into a vector table to select the highest pending
fast interrupt source.
This read-only register is located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle,
and can only be accessed in privileged mode.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-14
Offset 0x0044 (FIVECSR)
31
R
W
Reset
R
W
Reset
30
29
Access: Privileged read only
28
27
26
25
24
23
22
21
20
19
18
17
16
FIVECTOR[31:16]
1
1
1
1
1
1
1
15
14
13
12
11
10
9
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
FIVECTOR[15:0]
1
1
1
1
1
1
1
1
1
Figure 14-20. Fast Interrupt Vector and Status Register
Table 14-10. FIVECSR Register Field Descriptions
Field
31–0
FIVECTOR
Description
Fast Interrupt Vector. Indicates vector index for the highest pending fast interrupt.
-01 No fast interrupt request pending
00 Interrupt 0 highest pending fast interrupt
01 Interrupt 1 highest pending fast interrupt
...
63 Interrupt 63 highest pending fast interrupt
64+ (not -1) = unused, does not occur
14.3.2.10 Interrupt Source Registers
The interrupt source register high (INTSRCH) and the interrupt source register low (INTSRCL) are each
32 bits wide. INTSRCH and INTSRCL reflect the status of all interrupt request inputs into the interrupt
controller. Unused bit positions always read zero (no request pending). The state of this register out of reset
is determined by the peripheral circuits generating the requests; normally, the requests would be inactive.
These read-only registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1
cycle, and can only be accessed in privileged mode. This read-only register should be accessed with 32 bit
reads only.
NOTE
The state of these registers out of reset is determined by the peripheral
circuits generating the requests. Normally, the requests would be inactive.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-15
Offset 0x0048 (INTSRCH)
31
R
W
Reset
30
29
Access: Privileged read only
28
27
26
25
24
23
22
21
20
19
18
17
16
INTIN[63:48]
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
W
Reset
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTIN[47:32]
0
0
0
0
0
0
0
0
0
Figure 14-21. Interrupt Source Register High
Offset 0x004C (INTSRCL)
31
R
W
Reset
30
29
Access: Privileged read only
28
27
26
25
24
23
22
21
20
19
18
17
16
INTIN[31:16]
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
W
Reset
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTIN[15:0]
0
0
0
0
0
0
0
0
0
Figure 14-22. Interrupt Source Register Low
Table 14-11. INTSRCH / INTSRCL Field Descriptions
Field
63
–0
INTIN
Description
Interrupt Source. Indicates the state of the corresponding hardware interrupt source.
0 Interrupt source negated
1 Interrupt source asserted
14.3.2.11 Interrupt Force Registers
The interrupt force register high (INTFRCH) and the interrupt force register low (INTFRCL) are each 32
bits wide. The interrupt force registers allow for software generation of interrupts for each of the possible
interrupt sources for functional or debug purposes. The system level design may reserve one or more
sources for software purposes to allow software to self-schedule interrupts by forcing one or more of these
“sources” in the appropriate interrupt force register(s).
These registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1 cycle, and can
only be accessed in privileged mode. These registers can be only modified using 32-bit writes.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-16
Offset 0x0050 (INTFRCH)
31
R
W
Reset
30
29
Access: Privileged read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
FORCE[63:48]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
W
Reset
FORCE[47:32]
0
0
0
0
0
0
0
0
0
Figure 14-23. Interrupt Force Register High
Offset 0x0054 (INTFRCL)
31
R
W
Reset
30
29
Access: Privileged read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
FORCE[31:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
W
Reset
FORCE[15:0]
0
0
0
0
0
0
0
0
0
Figure 14-24. Interrupt Force Register Low
Table 14-12. INTFRCH / INTFRCL Descriptions
Field
63–0
FORCE
Description
Interrupt Source Force Request. Used to force a request for the corresponding interrupt source.
0 Standard interrupt operation
1 Interrupt force asserted
14.3.2.12 Normal Interrupt Pending Registers
The normal interrupt pending register high (NIPNDH) and the normal interrupt pending register low
(NIPNDL) are 32-bit wide registers used to monitor the outputs of the enable and masking operations.
These registers are actually only a set of buffers; therefore, the reset state of these registers are determined
by the normal interrupt enable registers, the interrupt mask register, and the interrupt source registers. The
value reflected in these registers is unaffected by the value of the NIMASK register.
These read-only registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1
cycle, and can only be accessed in privileged mode.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
14-17
Offset 0x0058 (NIPNDH)
31
R
W
Reset
R
W
Reset
30
Access: Read only
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIPEND[63:48]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NIPEND[47:32]
0
0
0
0
0
0
0
0
0
Figure 14-25. Normal Interrupt Pending Register High
Offset 0x005C (NIPNDH)
31
R
W
Reset
R
W
Reset
30
Access: Read only
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIPEND[31:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NIPEND[15:0]
0
0
0
0
0
0
0
0
0
Figure 14-26. Normal Interrupt Pending Register High
NIPNDH
0x0058
BIT 31
30
29
28
27
26
25
r
0
r
0
r
0
r
0
r
0
r
0
r
0
BIT 15
14
13
12
11
10
9
r
0
r
0
r
0
r
0
r
0
r
0
r
0
TYPE
RESET
TYPE
RESET
24
23
NIPEND[63:48]
r
r
0
0
22
21
20
19
18
17
BIT 16
r
0
r
0
r
0
r
0
r
0
r
0
r
0
8
7
NIPEND[47:32]
r
r
0
0
6
5
4
3
2
1
BIT 0
r
0
r
0
r
0
r
0
r
0
r
0
r
0
Figure 14-27. Normal Interrupt Pending Register High
NIPNDL
TYPE
RESET
TYPE
RESET
0x005C
BIT 31
30
29
28
27
26
25
r
0
r
0
r
0
r
0
r
0
r
0
r
0
BIT 15
14
13
12
11
10
9
r
0
r
0
r
0
r
0
r
0
r
0
r
0
24
23
NIPEND[31:16]
r
r
0
0
22
21
20
19
18
17
BIT 16
r
0
r
0
r
0
r
0
r
0
r
0
r
0
8
7
NIPEND[15:0]
r
r
0
0
6
5
4
3
2
1
BIT 0
r
0
r
0
r
0
r
0
r
0
r
0
r
0
Figure 14-28. Normal Interrupt Pending Register Low
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Freescale Semiconductor
14-18
Table 14-13. NIPNDH / NIPNDL Descriptions
Field
Description
63–0
NIPEND
Normal Interrupt Pending Bit. If a normal interrupt enable bit is set and the corresponding interrupt source is
asserted, the interrupt controller asserts a normal interrupt request. The normal interrupt pending bits reflect
the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt.
0 No normal interrupt request
1 Normal interrupt request pending
14.3.2.13 Fast Interrupt Pending Registers (FIPNDH)
The fast interrupt pending register high (FIPNDH) and the fast interrupt pending register low (FIPNDL)
are 32-bit wide registers used to monitor the outputs of the enable and masking operations. These registers
are actually only a set of buffers; therefore, the reset state of these registers are determined by the fast
interrupt enable registers, the interrupt mask register, and the interrupt source registers.
These read-only registers are located on the ARM926EJ-S platform slave port 3 AHB, accessible in 1
cycle, and can only be accessed in privileged mode.
Offset 0x0060 (FIPNDH)
31
R
W
Reset
R
W
Reset
30
Access: Read only
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIPEND[63:48]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FIPEND[47:32]
0
0
0
0
0
0
0
0
0
Figure 14-29. Fast Interrupt Pending Register High
Offset 0x0064 (FIPNDL)
31
R
W
Reset
R
W
Reset
30
Access: Read only
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIPEND[31:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FIPEND[15:0]
0
0
0
0
0
0
0
0
0
Figure 14-30. Fast Interrupt Pending Register Low
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Freescale Semiconductor
14-19
Table 14-14. FIPNDH / FIPNDL Descriptions
Field
Description
63–0
FIPEND
14.4
14.4.1
Fast Interrupt Pending Bit. If a fast interrupt enable bit is set and the corresponding interrupt source is
asserted, the interrupt controller asserts a fast interrupt request. The fast interrupt pending bits reflect the
interrupt input lines which are asserted and are currently enabled to generate a fast interrupt.
0 No fast interrupt request
1 Fast interrupt request pending
ARM926EJ-S Interrupt Controller Operation
ARM926EJ-S Prioritization of Exception Sources
The ARM926EJ-S core imposes the following priority among the various exceptions:
• Reset (highest priority)
• Data Abort
• Fast Interrupt
• Normal Interrupt
• Prefetch Abort
• Undefined Instruction and SWI (lowest priority)
14.4.2
ASIC Prioritization of Interrupt Sources
The ASIC module prioritizes the various interrupt sources by source number where higher source numbers
have higher priority. Fast interrupt always have higher priority over normal interrupts.
The interrupt requests are prioritized in the following sequence:
1. Fast interrupt requests, in order of highest source number
2. Normal interrupt requests, in order of highest priority level, then in order of highest source
number with the same priority level
14.4.3
Assigning and Enabling Interrupt Sources
The interrupt controller provides for flexible assignment of any interrupt source to either of the two core
interrupt request inputs. This is done by setting the appropriate bits in the INTENABLEH / INTENABLEL
registers and the INTTYPEH / INTTYPEL registers. Usually, interrupt assignment is done once during
system initialization and does not affect interrupt latency.
Interrupt assignment is the first of three steps required to enable an interrupt source, and this is done at chip
integration. The second step is to program the source to generate interrupt requests. The final step is to
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Freescale Semiconductor
14-20
enable the interrupt inputs in the core by clearing the normal interrupt disable (I) and/or the fast interrupt
disable (F) bits in the program status register (CPSR).
14.4.4
Enabling Interrupts Sources
There are two methods of enabling or disabling interrupts in the ASIC:
• One method is to read the INTENABLEH / INTENABLEL registers, logically OR or BIT CLEAR
the read values with generated masks, then write back to the INTENABLEH / INTENABLEL
registers.
• A second method is to perform an atomic write to the source number in the INTENNUM register.
The ASIC decodes this 6-bit register, and enable one of the 64 interrupt sources. The ASIC
automatically generates a “one-hot” enable mask and logically OR this mask to the correct
INTENABLEH or INTENABLEL register. Interrupts are disabled in exactly the same way, except
the source number is written to the INTDISNUM register.
14.4.5
Writing Reentrant Normal Interrupt Routines
The ASIC can be used to create a reentrant normal interrupt system, as described below. This enables
preempting of lower priority level interrupts by higher priority level interrupts. This requires a small
amount of software support and overhead.
1.
2.
3.
4.
5.
Push the link register (LR_irq) on to the stack (SP_irq)
Push the saved status register (SPSR_irq) on to the stack
Read the current value of NIMASK and push this value on to the stack
Read current priority level using NIVECSR
Interrupts of the equal or lesser priority than the current priority level should be masked using the
NIMASK register by writing value from NIVECSR
6. Clear the I bit in the ARM926EJ-S core using a MSR / MRS command sequence (now a higher
priority normal interrupt can preempt a lower priority one)
Also change the operating mode of the core to System Mode from IRQ mode
7. Push System Mode link register (LR) on to the stack (SP_user)
8. The traditional interrupt service routine is now included
9. Pop System Mode link register (LR) from the stack (SP_user)
10. Set I bit in the ARM926EJ-S core using a MSR / MRS command sequence (thus disabling all
normal interrupts)
Also change the operating mode of the core to IRQ Mode from System mode
11. Pop the original value of normal interrupt mask and write to the NIMASK register
12. The saved status register should be popped from the stack (SP_irq)
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Freescale Semiconductor
14-21
13. The link register should be popped from the stack into the PC
14. Return from nIRQ
NOTE
Steps 1, 2, 13, and 14 are performed automatically by most C compilers, and
are included for completeness.
14.4.6
Low Power Entry Sequence
The following sequence is recommended to enter low-power mode, with respect to the ARM9 platform.
1. Mask interrupts in ARM core using core instructions
2. Program other low-power mode entry steps including programming the low power mode (LP CTL)
Bits in CCM
3. Program ASIC and external wake-up controller for same wake-up interrupts. Mask the
non-wakeable interrupts.
4. ARM platform does internal housekeeping tasks such as draining the L1 and L2 buffers, flushing
the caches, and so on.
5. Read the status of pending interrupts, if any wake-up interrupt is pending, service the pending
interrupt (after unmasking the interrupts in the core) and then restart the low power sequence (if
required)
6. If there is no pending wake-up interrupt, then execute WFI Instruction.
7. Core performs internal house keeping and asserts StandbyWFI. Based on StandbyWFI, the
platform asserts a9p_clk_off.
8. CCM sends out the MAX_HALT_REQUEST.
9. MAX_HALTED is received, CCM requests other modules (if programmed) to enter low-power
mode.
The following sequence is recommended for low-power exit:
1. Whenever a wake-up interrupt is detected by external wake-up controller or by the platform’s
ASICn (until the platform clocks are alive), CCM’s A926P_CLK_OFF is negated.
2. The system takes steps to exit low power mode. CCM restarts the core clocks.
3. The platform synchronize the pending interrupt and exit standby WFI mode.
4. Unmask/Enable the interrupts in the core by core instructions.
5. Core services the interrupt, and restarts execution from the previous stage.
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Freescale Semiconductor
14-22
ARM926EJ-S Simple Interrupt Controller (ASIC)
NOTE
In case the platform is programmed to bypass the interrupt synchronizers
(ASIC INTCNTL[23] = 1) in low power mode, then after step 3 of the
low-power exit sequence, the core has to wait for few hclk cycles till the
standby WFI signal has propagated through all the synchronizations flops
stages. So software needs to have enough nops or dummy instructions to
avoid these hclk cycles. By default, interrupt synchronizers are not
bypassed.
14.4.7
AHB Interface of ASIC
The ASIC is AHB-compatible. This means that IDLE or BUSY cycles that are presented to the ASIC
receive an avic_hready (as required by specification).
The ASIC reports a transfer error if the HPROT[3:1] bits are not equal to 001. This means that only
privileged accesses are allowed to the ASIC.
The ASIC reports a transfer error if non-32 bit writes are attempted. Any size read is allowed.
The ASIC reports a transfer error if address of the access is not within the range of one of the ASIC
registers.
The ASIC does not report a transfer error if writes are performed to read-only registers. These writes are
ignored and have no affect on the ASIC.
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Freescale Semiconductor
14-23
ARM926EJ-S Simple Interrupt Controller (ASIC)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
14-24
Freescale Semiconductor
Chapter 15
Clock Controller Module (CCM)
15.1
Introduction
The CCM performs the following functions:
• Controls the system frequency
• Distributes clocks to various parts of the chip
• Controls the reset mechanism of the chip
• Provides advanced low-power management
15.1.1
Overview
The CCM contains four functional parts:
• Clock control and gating logic
• Reset control logic
• Boot control logic
• Low-power control logic
Figure 15-1 shows a top-level block diagram of the CCM.
Clock Sources
Reset Sources
PLL outputs
Clock Control
Clock Select
& Gating
Clock Outputs
Reset
Clock for Reset
Reset Outputs
Controller
IP bus
PLL outputs
Boot address
Boot Pins
Low-Power signals
Low-Power
Controller
PMIC Control
Boot
Fuses
Boot Mode
Controller
Figure 15-1. CCM Block Diagram
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-1
Clock Controller Module (CCM)
15.1.2
Features
The CCM includes these distinctive features:
• Core PLL—supports seamless switching of the ARM Clock among 532/399/266/133 MHz
• Clock distributions with clock gating on each clock output—minimizes power consumption in the
clock tree
• Reset distributions with security check—helps with security of the chip
• Boot controller—provides different boot information to the chip based on BOOT pins
• Power manager—controls power modes and minimize power consumption using techniques such
as AWB, power gating, DPTC, and DVFS
• Registers—accessible using IP bus
15.1.3
Modes of Operation
There are three modes of operation:
• Normal operating mode
• Low-power mode
• Debug mode
15.1.3.1
Normal Operating Mode
The normal operating mode is run mode. The clocks are generated by PLLs.
15.1.3.2
Low-Power Modes
The low-power modes are actually system low-power modes. There are three low-power modes:
• Wait
• Doze
• Stop
NOTE
The DryIce module (which handles volatile key storage and supplies a
trusted time source) and its 32 KHz oscillator can be powered independently
during these low-power modes. See the DryIce chapter for more details.
15.2
External Signal Description
Table 15-1 describes all signals that connect off-chip.
Table 15-1. External Signal Properties
Name
Port
Function
I/O Reset
Pull Up
OSC24M_EXTAL
osc24m_clk
OSC24M external input
I
—
—
CLK_SEL
ipp_clk_sel
Clock mode select input
I
—
—
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15-2
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-1. External Signal Properties
Name
Port
BOOTIN[1:0]
ipp_boot_in
POR_B
RESET_IN_B
Function
I/O Reset
I
—
—
ipp_por_reset_in_b Power-on-reset signal from external pad
I
—
Active
ipp_reset_in_b
External reset signal. All modules are reset but the PLL, fuse
and CCM.
I
—
Active
OCSC32K_EXTAL ext32k_clk
OSC32K external input
I
—
—
CLKO
CKO clockout pin
O
0
—
15.3
ipp_clko
Boot mode pins
Pull Up
Memory Map and Register Definition
This section provides memory maps and detailed descriptions of all registers.
15.3.1
Memory Map
Table 15-2 shows the CCM memory map. For the base address of a particular module instantiation, see the
system memory map.
Table 15-2. CCM Memory Map
Base Address
Offset (Register
Abbreviation)
Register
Access
Reset Value
Section/Page
General Registers
0x0000 (MPCTL)
Core PLL Control Register (MPCTL)
R/W
0x800B_2C01
15.3.3.1/15-9
0x0004 (UPCTL)
USB PLL Control Register (UPCTL)
R/W
0x8400_2800
15.3.3.2/15-11
Clock Control Register (CCTL)
R/W
0x4003 0000
15.3.3.3/15-13
0x000C (CGCR0)
Clock Gating Control Register 0 (CGCR0)
R/W
0x028A_0100
15.3.3.4/15-15
0x0010 (CGCR1)
Clock Gating Control Register 1 (CGCR1)
R/W
0x0400_8100
15.3.3.5/15-17
0x0014 (CGCR2)
Clock Gating Control Register 2 (CGCR2)
R/W
0x0000_0438
15.3.3.6/15-17
0x0018 (PCDR0)
PER Clock Divider Register 0 (PCDR0)
R/W
0x0101_0101
15.3.3.7/15-19
0x001C (PCDR1)
PER Clock Divider Register 1 (PCDR1)
R/W
0x0101_0101
15.3.3.8/15-22
0x0020 (PCDR2)
PER Clock Divider Register 2 (PCDR2)
R/W
0x0101_0101
15.3.3.9/15-23
0x0024 (PCDR3)
PER Clock Divider Register 3 (PCDR3)
R/W
0x0101_0101
15.3.3.10/15-24
0x0028 (RCSR)
CCM Status Register (RCSR)
R/W
0x0000_0000
15.3.3.11/15-26
0x002C (CRDR)
CCM Reset and Debug Register (CRDR)
R/W
0x0000_0000
15.3.3.12/15-29
0x0030 (DCVR0)
DPTC Comparator Value Registers (DCVR0–DCVR3)
R/W
0x0000_0000
15.3.3.13/15-30
0x0034 (DCVR1)
DPTC Comparator Value Registers (DCVR0–DCVR3)
R/W
0x0000_0000
15.3.3.13/15-30
0x0038 (DCVR2)
DPTC Comparator Value Registers (DCVR0–DCVR3)
R/W
0x0000_0000
15.3.3.13/15-30
0x0008 (CCTL)
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Freescale Semiconductor
15-3
Clock Controller Module (CCM)
Table 15-2. CCM Memory Map (continued)
Base Address
Offset (Register
Abbreviation)
Access
Reset Value
Section/Page
DPTC Comparator Value Registers (DCVR0–DCVR3)
R/W
0x0000_0000
15.3.3.13/15-30
0x0040 (LTR0)
Load Tracking Register 0 (LTR0)
R/W
0x0000_0000
15.3.3.14/15-31
0x0044 (LTR1)
Load Tracking Register 1 (LTR1)
R/W
0x0000_0000
15.3.3.15/15-32
0x0048 (LTR2)
Load Tracking Register 2 (LTR2)
R/W
0x0000_0000
15.3.3.16/15-33
0x004C (LTR3)
Load Tracking Register 3 (LTR3)
R/W
0x0000_0000
15.3.3.17/15-34
0x0050 (LTBR0)
Load Tracking Buffer Register 0 (LTBR0)
R/W
0x0000_0000
15.3.3.18/15-35
0x0054 (LTBR1)
Load Tracking Buffer Register 1 (LTBR1)
R/W
0x0000_0000
15.3.3.19/15-36
0x0058 (PMCR0)
Power Management Control Register 0 (PMCR0)
R/W
0x002C_9828
15.3.3.20/15-37
0x005C (PMCR1)
Power Management Control Register 1 (PMCR1)
R/W
0x00A0_0000
15.3.3.21/15-39
0x0060 (PMCR2)
Power Management Control Register 2 (PMCR2)
R/W
0x0000_A030
15.3.3.22/15-41
0x0060 (PMCR2)
Power Management Control Register 2 (PMCR2)
R/W
0x0000_A030
15.3.3.22/15-41
Miscellaneous Control Register (MCR)
R/W
0x4300_0000
15.3.3.23/15-42
0x0068 (LPIMR0)
Low Power Interrupt Mask Registers (LPIMR0)
R/W
0x0000_0000
15.3.3.24/15-44
0x006C (LPIMR1)
Low Power Interrupt Mask Registers (LPIMR1)
R/W
0x0000_0000
15.3.3.25/15-44
0x003C (DCVR3)
0x0064 (MCR)
15.3.2
Register
Register Summary
The conventions in Figure 15-2 and Table 15-3 serve as a key for the register summary and individual
register diagrams.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 15-2. Key to Register Fields
Table 15-3 provides a key for register figures and tables and the register summary.
Table 15-3. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
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15-4
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-3. Register Conventions (continued)
Convention
w1c
Description
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
Reset value is determined by polarity of indicated signal.
Table 15-4 shows the CCM register summary table.
Table 15-4. CCM Register Summary
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R BRM
W O
0x0000
(MPCTL)
R
LOC
K
0
PD
MFD
MFI
MFN
PD
MFD
MFI
MFN
0
W
R BRM
W O
0x0004
(UPCTL)
R
LOC
K
0
0
W
R
CLK MUX
POST DIV
W
0x0008 (CCTL)
R
CG
W CTL
0
0
R
0
0
0
0
MPL UPL
L
L
RST RST
0
0
LP CTL
0
0
UPL
L
DIS
0
USB DIV
0
0
0
0
0
AHB Clock Gating
0x000C
(CGCR0)
W
R
PER Clock Gating
W
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15-5
Clock Controller Module (CCM)
Table 15-4. CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IPG Clock Gating[31:16]
0x0010
(CGCR1)
W
R
IPG Clock Gating[15:0]
W
R
0
0
0
0
0
0
0
0
IPG Clock Gating[51:48]
0x0014
(CGCR2)
W
R
IPG Clock Gating[47:32]
W
R
0
0
0
0
PER3 DIV
0x0018
(PCDR0)
PER2 DIV
W
R
0
0
0
0
PER1 DIV
PER0 DIV
W
R
0
0
0
0
PER7 DIV
0x001C
(PCDR1)
PER6 DIV
W
R
0
0
0
0
PER5 DIV
PER4 DIV
W
R
0
0
0
0
PER11 DIV
0x0020
(PCDR2)
PER10 DIV
W
R
0
0
0
0
PER9 DIV
PER8 DIV
W
R
0
0
0
0
PER15 DIV
0x0024
(PCDR3)
PER14 DIV
W
R
0
0
0
0
PER13 DIV
PER12 DIV
W
R MEM CTRL MEM TYPE PAGE SIZE
BUS
WIDTH
USB SRC
BT SRC
BT RES
EEP
RO MLC
M
SEL
CFG
RESTS
W
0x0028
(RCSR)
SOF NFC
R T_R _16b
ESE it_S
T
EL
W
0
NFC SPA BOO
CLK
NFC
BOOT REG
_FM RE
T
SEL
_4K
S SIZE INT
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Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-4. CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIG
D1
SIG
D0
R
BT UART SRC
0x002C
(CRDR)
W
R
0
0
0
W
R
ULV
0x0030
(DCVR0)
LLV
W
R
LLV
ELV
W
R
ULV
0x0034
(DCVR1)
LLV
W
R
LLV
ELV
W
R
ULV
0x0038
(DCVR2)
LLV
W
R
LLV
ELV
W
R
ULV
0x003C
(DCVR3)
LLV
W
R
LLV
ELV
W
R
0
0
DIV3CK
UPTHR
DNTHR
W
0x0040 (LTR0)
R
SIG
W D15
R
0
SIG
D14
SIG
D13
SIG
D12
SIG
D11
SIG
D10
SIG
D9
SIG
D8
0
0
0
0
0
0
0
W
0x0044 (LTR1)
SIG
D7
SIG
D6
SIG
D5
SIG
D4
LT_ LT_
BRS BRS
H
R
SIG
D3
SIG
D2
DNCNT
R
DNCNT
UPCNT
PNCTHR
W
R
WSW15
WSW14
WSW13
WSW12
W
WSW11
WS
W10
0x0048 (LTR2)
R
0
WSW10
WSW9
0
EMAC
W
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-7
Clock Controller Module (CCM)
Table 15-4. CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
WSW8
WSW7
WSW6
WSW5
WS
W3
WSW4
W
0x004C (LTR3)
R
0
WSW3
WSW2
WSW1
0
0
0
0
WSW0
W
R
0x0050
(LTBR0)
LTS7
LTS6
LTS5
LTS4
LTS3
LTS2
LTS1
LTS0
LTS15
LTS14
LTS13
LTS12
LTS11
LTS10
LTS9
LTS8
W
R
W
R
0x0054
(LTBR1)
W
R
W
R
0
0
0
0
0
DVSUP
0x0058
(PMCR0)
W
R
0x005C
(PMCR1)
W
FS
VAI
M
R
0
FSVAI
0
W
R
0
0
W
R
0
0
DVF
S_U
DVF DVFI LBM LBF
PD_
EV
S
I
L
FINI
SH
LBCF
DPV DPV WFI DRC DRC DRC DRC
DVF PTV
SCR
CR
V
M
E3
E2
E1
E0
EN AIM
CPE CPF
N_E A_E
MI
MI
CPSPA_EMI
CPE CPF
N
A
CPSPA
0
0
0
DPT
EN
0
DVGP
0
0
0
0
0
W
0x0060
(PMCR2)
R
0
ARM MEMON CNT
PTVAI
WBCN
0
0
DVF
PTVI S_S
S
TAR
T
ARM CLKON CNT
ARM
OSC
ME
VST 24M
M
BY _DO
DW
WN
N
0
DVF
S_R
EQ
DVF
S_A
CK
W
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-8
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-4. CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R USB
CLK
XTA
O
W LMU EN
X
0x0064 (MCR)
CLKO DIV
CLKO SEL
ESA
SSI2 SSI1 USB
I
CLK CLK CLK
CLK
MUX MUX MUX
MUX
R
PER CLK MUX
W
R
LPIM[31:16]
0x0068
(LPIMR0)
W
R
LPIM[15:0]
W
R
LPIM[63:48]
0x006C
(LPIMR1)
W
R
LPIM[47:32]
W
15.3.3
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number.
15.3.3.1
Core PLL (MPLL) Control Register (MPCTL)
This register contains parameters which determine the output frequency of the core PLL (MPLL), which
is given by FVCO in Equation 15-1.
MF N
MF I + -----------MF D
2xF ref x ------------------------------ = Fvco
PD
MPLL Output Frequency
Eqn. 15-1
Fref: MPLL reference clock (input frequency)
MFx: Multiplication factors defined by MPCTL register fields (see Table 15-5)
PD: Predivider factor, whose value is also set in the MPCTL register
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-9
Clock Controller Module (CCM)
Figure 15-3 shows the MPCTL fields that are described in Table 15-5.
NOTE
The absolute value of MFN/MFD must be smaller than 1. Changes in the
PD, MFD, MFI, and MFN fields take effect (and the PLL is relocked) only
after the MPLL_RST bit in the CCTL register is set.
Offset 0x0000 (MPCTL)
31
30
R BRM
W O
Reset
29
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
0
PD
MFD
1
0
0
0
0
0*
0
0
0
0
0
0
1
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
R LOCK
0
MFI
MFN
W
Reset
0
0
1
0
1
1
0
0
0
0
0
Figure 15-3. Core PLL Control Register (MPCTL)
Table 15-5. MPCTL Field Descriptions
Name
Description
31
BRMO
Binary rate multiplier (BRM) Order bit. Determines if the BRM is first or second order. The first-order BRM is used
if the MF fractional part is between 1/10 and 9/10, or if MFI > 13. Otherwise the second-order BRM is used. The
BRMO bit is cleared by a hardware reset.
1 BRM is second order.
0 BRM is first order.
30
29–26
PD
Reserved
Predivider factor. Defines the predivider factor (PD) applied to the PLL input frequency. as specified in
Equation 15-2. PD is an integer between 1and 16 (inclusive). PD is chosen to ensure that the resulting output
frequency remains within the specified range.
0000 1
0001 2
...
1111 16
Note: Changes in this field take effect (and the PLL is relocked) only after the MPLL_RST bit in the CCTL register
is set.
Note: The default value of PD is depends on the ipp_clk_sel boot up value. (PD=0x0 if ipp_clk_sel = 0; PD = 0x1
if ipp_clk_sel = 1).
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-10
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-5. MPCTL Field Descriptions (continued)
Name
Description
25–16
MFD
Multiplication factor denominator. Defines the denominator part of the BRM value for the MF, as specified
by Equation 15-2.
000000000 Denominator = 1
000000001 Denominator = 2
…
1111111111 Denominator = 1024
Note: Changes in this field take effect (and the PLL is relocked) only after the MPLL_RST bit in the CCTL register
is set.
15
LOCK
This bit shows if the PLL lock flag is set.
0 PLL lock flag is negated.
1 PLL lock flag is set.
14
Reserved
13–10
MFI
Multiplication factor integer part. Defines the integer part of the BRM value for the MF, as specified in
Equation 15-2. The MFI is encoded so that MFI < 5 results in MFI = 5.
0000–0101 MFI = 5
0110 MFI = 6
...
1111 MFI = 15
Note: Changes in this field take effect (and the PLL is relocked) only after the MPLL_RST bit in the CCTL register
is set.
9–0
MFN
Multiplication factor numerator. Defines the numerator of the BRM value for the MF, as specified in
Equation 15-2.This value is a 2’s complements number.
0000000000 0
0000000001 1
...
0111111111 511
1000000000 –512
...
1111111111 –1
Note: Changes in this field take effect (and the PLL is relocked) only after the MPLL_RST bit in the CCTL register
is set.
15.3.3.2
USB PLL Control Register (UPCTL)
This register contains parameters which determine the output frequency of the USB PLL (UPLL), which
is given by FVCO in Equation 15-2.
MF N
MF I + -----------MF D
2xF ref x ------------------------------ = Fvco
PD
UPLL Output Frequency
Eqn. 15-2
Fref: Reference clock (input frequency) of UPLL.
MFx: Various multiplication factors, whose value is set using the UPCTL register (see bit descriptions below).
PD: Predivider factor, whose value is also set in the UPCTL register.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-11
Clock Controller Module (CCM)
Figure 15-4 shows the UPCTL fields, which are described in Table 15-6.
NOTE
The MFN and MFD fields in UPCTL must satisfy the condition that the
absolute value of MFN/MFD be smaller than 1.
Offset 0x0004 (UPCTL)
31
30
R BRM
O
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
PD
MFD
W
Reset
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R LOCK
0
MFI
MFN
W
Reset
0
0
1
0
1
0
0
0
0
0
0
Figure 15-4. USB PLL Control Register (UPCTL)
Table 15-6. UPCTL Field Descriptions
Name
31
BRMO
30
Description
Binary rate multiplier order bit. Determines if the binary rate multiplier (BRM) is first or second order. The first
order BRM is used if a MF fractional part is between 1/10 and 9/10. In other cases, the second order BRM is
used. The BRMO bit is cleared by a hardware reset.
1 BRM is second order.
0 BRM is first order.
Reserved
29–26
PD
Predivider factor bits. These bits define the predivider factor (PD) applied to the PLL input frequency, as
specified in Equation 15-2. PD is an integer between 1and 16 (inclusive). PD is chosen to ensure that the
resulting output frequency remains within the specified range.The change in this field will not take effect, and the
PLL will be relocked by setting UPLL RST bit in CCTL register only.
0000 1
0001 2
...
1111 16
25–16
MFD
Multiplication factor (denominator part). Defines the denominator part of the BRM value for the MF. See
Equation 15-2. The change in this field will not take effect, and the PLL will be relocked by setting UPLL RST bit
in CCTL register only.
000000000 1
000000001 2
…
1111111111 1024
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-12
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-6. UPCTL Field Descriptions (continued)
Name
Description
15
LOCK
This bit shows if the PLL lock flag is set.
0 PLL lock flag is negated.
1 PLL lock flag is set.
14
Reserved
13–10
MFI
Multiplication factor (integer part). Defines the integer part of the BRM value for the MF. See Equation 15-2.
The MFI is encoded so that MFI < 5 results in MFI = 5. The change in this field will not take effect, and the PLL
will be relocked by setting UPLL RST bit in CCTL register only.
0000–0101 5
0110 6
...
1111 15
9–0
MFN
Multiplication factor (numerator part). Defines the numerator of the BRM value for the MF. See Equation 15-2.
The change in this field will not take effect, and the PLL will be relocked by setting UPLL RST bit in CCTL register
only. This value is a 2’s complements number.
0000000000 0
0000000001 1
...
0111111111 511
1000000000 –512
...
1111111111 –1
15.3.3.3
Clock Control Register (CCTL)
Offset 0x0008 (CCTL)
31
R
W
Reset
29
28
27
26
24
23
22
21
20
MPLL
UPLL
BYPA
DIS
SS
19
18
17
16
AHB CLK
DIV
0*
0*
0
1
0
0
0
0
0
0
0
0
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARM
SRC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CG
W CTL
0
MPLL UPLL
RST RST
25
ARM CLK
DIV
R
Reset
30
Access: User read-write
LP CTL
USB DIV
Figure 15-5. Clock Control Register (CCTL)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-13
Clock Controller Module (CCM)
Table 15-7. CCTL Field Descriptions
Field
Description
31–30
These bits control the ARM CLK DIV in the i.MX25 clock generation scheme (see Figure 15-28).
ARM CLK DIV 00 Divide by 1
01 Divide by 2
10 Divide by 3
11 Divide by 4
Note: The ARM CLK DIV default value depends on the ipp_clk_sel boot up value. If ipp_clk_sel = 0, then
ARM CLK DIV = 3; if ipp_clk_sel = 1, then ARM CLK DIV = 1)
29–28
These bits control the AHB CLK DIV in the i.MX25 clock generation scheme (see Figure 15-28).
AHB CLK DIV 00 Divide by 1
01 Divide by 2
10 Divide by 3
11 Divide by 4
27
MPLL RST
This bit controls the MPLL restart.
0 Don’t restart the MPLL.
1 Restart the MPLL, this bit will be cleared automatically.
26
UPLL RST
This bit controls the UPLL restart.
0 Don’t restart the UPLL.
1 Restart the UPLL, this bit will be cleared automatically.
25–24
LP CTL
These bits define the low power mode to be entered after a wait for interrupt (WFI) is executed.
00 Run mode—no clocks are shut down.
01 Wait mode—all clocks except for ARM clock are active, except for those disabled by CGCR registers’
settings.
10 Doze mode—all clocks except ARM Platform clock and ARM clock are active, except for those disabled by
CGCR register settings.
11 Stop mode—all PLLs and all clocks are shut down.
23
UPLL DIS
This bit disables/enables the UPLL.
0 UPLL is enabled.
1 UPLL is disabled.
22
MPLL
BYPASS
This bit controls whether to bypass MPLL and use the OSC24M clock as chip’s source clock.
0 No bypass
1 Bypass
21–16
USB DIV
These bits control the divider for USB clock (the source clock is from UPLL).
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
15
CG CTRL
This bit controls the clock gating mode of the CCM’s peripheral (PER) and USB clocks
0 All clock gating will be controlled by CG CTRL REGs.
1 All clock gating will be controlled by CG CTRL REGs and module clock enable signals.
14
ARM SRC
This bit controls the clock source used by the ARM Divider.
0 The clock source for the ARM Divider is 532 MHz
1 The clock source for the ARM Divider is 399 MHz
13–0
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-14
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.4
Clock Gating Control Register 0 (CGCR0)
Offset 0x000C (CGCR0)
R
31
30
29
0
0
0
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
AHB Clock Gating
W
Reset
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
PER Clock Gating
W
Reset
0
0
0
0
0
0
0
1
0
Figure 15-6. Clock Gating Control Register 0 (CGCR0)
Table 15-8. Clock Gating Control Register 0 Field Descriptions
Field
31–29
Description
Reserved
28–16
AHB Clock Gating
These bits control the clock gating of AHB clocks which are generated by CCM. Table 15-9 shows the
correspondence between the individual bits and the clocks
0 Disable the clock output.
1 Enable the clock output.
15–0
PER Clock Gating
These bits control the clock gating of peripheral (PER) clocks which are generated by CCM.
0 Disable the clock output.
1 Enable the clock output.
Table 15-9. AHB Clock Gating
Bit
Clock
AHB Clock Gating[12]
hclk_usbotg
AHB Clock Gating[11]
hclk_slcdc
AHB Clock Gating[10]
hclk_sdma
AHB Clock Gating[9]
hclk_rtic
AHB Clock Gating[8]
hclk_lcdc
AHB Clock Gating[7]
hclk_fec
AHB Clock Gating[6]
hclk_esdhc2
AHB Clock Gating[5]
hclk_esdhc1
AHB Clock Gating[4]
hclk_esai
AHB Clock Gating[3]
hclk_emi
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-15
Clock Controller Module (CCM)
Table 15-9. AHB Clock Gating (continued)
Bit
Clock
AHB Clock Gating[2]
hclk_csi
AHB Clock Gating[1]
Reserved
AHB Clock Gating[0]
hclk_ata
Table 15-10. PER Clock Gating
Bit
Clock
PER Clock Gating[15]
ipg_per_uart
PER Clock Gating[14]
ipg_per_ssi2
PER Clock Gating[13]
ipg_per_ssi1
PER Clock Gating[12]
ipg_per_sim2
PER Clock Gating[11]
ipg_per_sim1
PER Clock Gating[10]
ipg_per_pwm
PER Clock Gating[9]
ipg_per_owire
PER Clock Gating[8]
ipg_per_nfc
PER Clock Gating[7]
ipg_per_lcdc
PER Clock Gating[6]
ipg_per_i2c
PER Clock Gating[5]
ipg_per_gpt
PER Clock Gating[4]
ipg_per_esdhc2
PER Clock Gating[3]
ipg_per_esdhc1
PER Clock Gating[2]
ipg_per_esai
PER Clock Gating[1]
ipg_per_epit
PER Clock Gating[0]
ipg_per_csi
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-16
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.5
Clock Gating Control Register 1 (CGCR1)
Offset 0x0010 (CGCR1)
31
30
29
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IPG Clock Gating[31:16]
W
Reset
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
IPG Clock Gating[15:0]
W
Reset
1
0
0
0
0
0
0
1
0
0
Figure 15-7. Clock Gating Control Register 1 (CGCR1)
Table 15-11. Clock Gating Control Register 1 Field Descriptions
Field
Description
31–0
IPG Clock
Gating[31:0]
15.3.3.6
These bits control the clock gating of IPG clocks generated by CCM. Table 15-13 shows the
correspondence between clocks and individual bits.
0 Disable the clock output.
1 Enable the clock output.
Clock Gating Control Register 2 (CGCR2)
Offset 0x0014 (CGCR2)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
19
18
17
16
IPG Clock Gating[51:48]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
0
0
R
IPG Clock Gating[47:32]
W
Reset
0
0
0
0
0
1
0
0
0
0
Figure 15-8. Clock Gating Control Register 2 (CGCR2)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-17
Clock Controller Module (CCM)
Table 15-12. Clock Gating Control Register 1 Field Descriptions
Field
31–20
19–0
IPG Clock
Gating[51:32]
Description
Reserved
These bits control the clock gating of IPG clocks generated by CCM. Table 15-13 shows the
correspondence between clocks and individual bits.
0 Disable the clock output.
1 Enable the clock output.
Table 15-13. IPG Clock Gating
Bit
IPG Clock Gating[51]
Clock
Reserved
IPG Clock Gating[50]
ipg_clk_uart5
IPG Clock Gating[49]
ipg_clk_uart4
IPG Clock Gating[48]
ipg_clk_uart3
IPG Clock Gating[47]
ipg_clk_uart2
IPG Clock Gating[46]
ipg_clk_uart1
IPG Clock Gating[45]
ipg_clk_tsc
IPG Clock Gating[44]
ipg_clk_ssi2
IPG Clock Gating[43]
ipg_clk_ssi1
IPG Clock Gating[42]
ipg_clk_spba
IPG Clock Gating[41]
ipg_clk_slcdc
IPG Clock Gating[40]
ipg_clk_sim2
IPG Clock Gating[39]
ipg_clk_sim1
IPG Clock Gating[38]
ipg_clk_sdma
IPG Clock Gating[37]
ipg_clk_scc
IPG Clock Gating[36]
Reserved
IPG Clock Gating[35]
ipg_clk_rngb
IPG Clock Gating[34]
ipg_clk_pwm4
IPG Clock Gating[33]
ipg_clk_pwm3
IPG Clock Gating[32]
ipg_clk_pwm2
IPG Clock Gating[31]
ipg_clk_pwm1
IPG Clock Gating[30]
Reserved
IPG Clock Gating[29]
LCDC_EN
IPG Clock Gating[28]
Reserved
IPG Clock Gating[27]
Reserved
IPG Clock Gating[26]
ipg_clk_iim
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-18
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-13. IPG Clock Gating (continued)
15.3.3.7
Bit
Clock
IPG Clock Gating[25]
Reserved
IPG Clock Gating[24]
Reserved
IPG Clock Gating[23]
Reserved
IPG Clock Gating[22]
ipg_clk_gpt4
IPG Clock Gating[21]
ipg_clk_gpt3
IPG Clock Gating[20]
ipg_clk_gpt2
IPG Clock Gating[19]
ipg_clk_gpt1
IPG Clock Gating[18]
Reserved
IPG Clock Gating[17]
Reserved
IPG Clock Gating[16]
Reserved
IPG Clock Gating[15]
ipg_clk_fec
IPG Clock Gating[14]
ipg_clk_esdhc2
IPG Clock Gating[13]
ipg_clk_esdhc1
IPG Clock Gating[12]
Reserved
IPG Clock Gating[11]
ipg_clk_epit2
IPG Clock Gating[10]
ipg_clk_epit1
IPG Clock Gating[9]
ipg_clk_ect
IPG Clock Gating[8]
ipg_clk_dryice
IPG Clock Gating[7]
ipg_clk_cspi3
IPG Clock Gating[6]
ipg_clk_cspi2
IPG Clock Gating[5]
ipg_clk_cspi1
IPG Clock Gating[4]
ipg_clk_csi
IPG Clock Gating[3]
ipg_clk_can2
IPG Clock Gating[2]
ipg_clk_can1
IPG Clock Gating[1]
ipg_clk_ata
IPG Clock Gating[0]
Reserved
PER Clock Divider Register 0 (PCDR0)
This register, along with PCDR1–3 controls the frequency division for the different peripheral (PER)
clocks. Table 15-15 shows the correspondence between PER clocks and modules.
Figure 15-9 shows the PCDR0 register’s fields, which are described in Table 15-14.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-19
Clock Controller Module (CCM)
Offset 0x0018 (PCDR0)
R
31
30
0
0
29
Access: User read-write
28
27
26
25
24
23
22
0
0
21
20
PER3 DIV
19
18
17
16
PER2 DIV
W
Reset
R
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
PER1 DIV
PER0 DIV
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 15-9. PER Clock Divider Register 0 (PCDR0)
Table 15-14. PCDR0 Field Descriptions
Field
31–30
29–24
PER3 DIV
23–22
21–16
PER2 DIV
15–14
13–8
PER1 DIV
Description
Reserved
These bits control the divider for the PER3 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER2 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER1 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-20
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-14. PCDR0 Field Descriptions (continued)
Field
7–6
5–0
PER0 DIV
Description
Reserved
These bits control the divider for the PER0 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Table 15-15. PER Clock Distribution
PER Clock
Module
PER Clock 15
UART
PER Clock 14
SSI2
PER Clock 13
SSI1
PER Clock 12
SIM2
PER Clock 11
SIM1
PER Clock 10
PWM
PER Clock 9
OWIRE
PER Clock 8
NFC
PER Clock 7
LCDC
PER Clock 6
I2C
PER Clock 5
GPT
PER Clock 4
eSDHC2
PER Clock 3
eSDHC1
PER Clock 2
ESAI
PER Clock 1
EPIT
PER Clock 0
CSI
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-21
Clock Controller Module (CCM)
15.3.3.8
PER Clock Divider Register 1 (PCDR1)
Offset 0x001C (PCDR1)
R
31
30
0
0
Access: User read-write
29
28
27
26
25
24
23
22
0
0
21
20
PER7 DIV
19
18
17
16
PER6 DIV
W
Reset
R
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
PER5 DIV
PER4 DIV
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 15-10. PER Clock Divider Register 1 (PCDR1)
Table 15-16. PCDR1 Field Descriptions
Field
31–30
29–24
PER7 DIV
23–22
21–16
PER6 DIV
15–14
13–8
PER5 DIV
Description
Reserved
These bits control the divider for the PER7 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER6 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER5 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-22
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-16. PCDR1 Field Descriptions (continued)
Field
Description
7–6
Reserved
5–0
PER4 DIV
15.3.3.9
These bits control the divider for the PER4 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
PER Clock Divider Register 2 (PCDR2)
Offset 0x0020 (PCDR2)
R
31
30
0
0
Access: User read-write
29
28
27
26
25
24
23
22
0
0
21
20
PER11 DIV
19
18
17
16
PER10 DIV
W
Reset
R
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
PER9 DIV
PER8 DIV
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 15-11. PER Clock Divider Register 2 (PCDR2)
Table 15-17. PCDR2 Field Descriptions
Field
31–30
29–24
PER11 DIV
23–22
Description
Reserved
These bits control the divider for the PER11 clock. The PER clock is the source, and the default
frequency is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-23
Clock Controller Module (CCM)
Table 15-17. PCDR2 Field Descriptions (continued)
Field
Description
21–16
PER10 DIV
These bits control the divider for the PER10 clock. The PER clock is the source, and the default
frequency is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
15–14
Reserved
13–8
PER9 DIV
These bits control the divider for the PER9 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
7–6
Reserved
5–0
PER8 DIV
These bits control the divider for the PER8 clock. The PER clock is the source, and the default frequency
is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
15.3.3.10 PER Clock Divider Register 3 (PCDR3)
Offset 0x0024 (PCDR3)
R
31
30
0
0
29
Access: User read-write
28
27
26
25
24
23
22
0
0
21
20
PER15 DIV
19
18
17
16
PER14 DIV
W
Reset
R
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
PER13 DIV
PER12 DIV
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 15-12. PER Clock Divider Register 3 (PCDR3)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-24
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-18. PCDR3 Field Descriptions
Field
31–30
29–24
PER15 DIV
23–22
21–16
PER14 DIV
15–14
13–8
PER13 DIV
7–6
5–0
PER12 DIV
Description
Reserved
These bits control the divider for the PER15 clock. The PER clock is the source, and the default
frequency is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER14 clock. The PER clock is the source, and the default
frequency is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER13 clock. The PER clock is the source, and the default
frequency is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
Reserved
These bits control the divider for the PER12 clock. The PER clock is the source, and the default
frequency is133 MHz. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-25
Clock Controller Module (CCM)
15.3.3.11 CCM Status Register (RCSR)
Offset 0x0028 (RCSR)
31
30
Access: User read-write
29
R MEM CTRL
28
MEM TYPE
27
26
PAGE SIZE
25
24
BUS WIDTH
23
22
21
20
USB SRC
BT SRC
19
18
17
16
BT RES
W
Reset
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
CLK
SEL
0
0*
R
SOFT NFC_
_RES 16bit_
ET
SEL
SPAR
EEPR
BOOT
MLC
BOOT REG NFC_ NFC_
E
OM
INT
SEL
CFG
4K
FMS SIZE
RESTS
W
Reset
0
0*
0*
0*
0*
0*
0*
0*
0*
0*
0
0
0
0
Note: All reset values with “*” are depended on fuse value or GPIO value at boot up.
Figure 15-13. CCM Status Register (RCSR)
Table 15-19. RCSR Field Descriptions
Field
Description
31–30
MEM CTRL
These two bits show the MEM CTRL fuse/GPIO value (read only).
00 WEIM
01 NAND Flash
10 Reserved
11 Expansion Device (SD/MMC/MoviNAND/CE-ATA, I2C, SPI)
See the MEM TYPE field settings for details.
29–28
MEM TYPE
This bit shows the MEM TYPE fuse/GPIO value (read only)
If MEM CTRL = WEIM then
00 NOR
01 Reserved
10 OneNAND
11 Reserved
If MEM CTRL = NAND Flash
00 3 address cycles
01 4 address cycles
10 5 address cycles
11 Reserved
If MEM CTRL = Expansion Card Device
00 SD/MMC/MoviNAND/CE-ATA HDD
01 Reserved
10 Serial ROM using I2C
11 Serial ROM using SPI
27–26
PAGE SIZE
These two bits show the NAND Flash PAGE SIZE fuse/GPIO value (read only)
If MEM CTRL = NAND Flash then
00 512 bytes
01 2 Kbytes
10 4 Kbytes
11 Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-26
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-19. RCSR Field Descriptions (continued)
Field
25–24
BUS WIDTH
23–22
USB SRC
Description
These two bits show the BUS WIDTH fuse/GPIO value.(read only)
MEM CTRL[1:0] = NAND Flash
00 8-bit bus
01 16-bit bus
10 Reserved
11 Reserved
MEM CTRL[1:0] = WEIM (NOR)
00 16-bit address/data multiplexed interface
01 16-bit address/data unmultiplexed interface
10 Reserved
11 Reserved
MEM CTRL[1:0] = Expansion Device (SPI)
00 2-Address word SPI device (16-bit)
01 3-Address word SPI device (24-bit)
10 Reserved
11 Reserved
These bits show BOOT USB SRC fuse/GPIO value. (read only)
00 USB OTG Internal PHY
01 USB OTG External ULPI PHY
10 Reserved
11 Reserved
21–20
BT SRC
These bits show BOOT SRC fuse/GPIO value. (read only)
If MEM CTRL[1:0]==11 (Expansion card device) && BT_MEM_TYPE[1:0]=00
(SD/MMC/MoviNAND/CE-ATA) then
00 eSDHC1
01 eSDHC2
10 Reserved
11 Reserved
If MEM CTRL[1:0]==11 (Expansion card device) && BT_MEM_TYPE[1:0]=10 (Serial ROM using I2C),
then
00 I2C1
01 I2C2
10 I2C3
11 Reserved
If MEM CTRL[1:0]==11 (Expansion card device) && BT_MEM_TYPE[1:0]=11 (Serial ROM using SPI),
then
00 CSPI1
01 CSPI2
10 CSPI3
11 Reserved
Otherwise Reserved
19–16
BT RES
These bits show BOOT RES fuse/GPIO value. (read only)
They are reserved for boot options
15
SOFT RESET
14
NFC_16bit_SEL
When “1” is Written to this bit, peripherals are reset. This bit will be clear automatically.
1 Peripherals are in the process of being reset.
0 Peripherals are not in the process of being reset.
This bit is used to configure the NAND Flash width. It is used after boot from NAND.It can be active while
nf8_boot_b and nf16_boot_b are both high (negated).
0 8-bit width
1 16-bit width
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-27
Clock Controller Module (CCM)
Table 15-19. RCSR Field Descriptions (continued)
Field
13
12
CLK SEL
11–10
BOOT_REG
Description
Reserved
This bit shows value on CLK SEL pad.
0 CLK SEL is zero when it is latched by POR.
1 CLK SEL is one when it is latched by POR.
These two read-only bits show the boot mode from boot mode pin.
0+ Internal Boot
01 Function Test (including DTE mode)
10 External Boot
11 Boot Strap
9
NFC_4K
This bit is used to configure the NAND flash page size. It is defined by PAGE_SIZE during boot-up, and
can be configured by software after boot-up.
0 Not 4-Kbyte page
1 4-Kbyte page
8
NFC_FMS
This bit is used to configure the NAND flash page size. It is defined by PAGE_SIZE during boot-up, and
can be configured by software after boot-up.
0 Not 2-Kbyte page
1 2-Kbyte page
7
SPARE SIZE
6
BOOT INT
5
EEPROM CFG
4
MLC SEL
3–0
REST
This read-only bit shows the SPARE SIZE fuse/GPIO value.
0 128 bytes spare (Samsung: 4-bit ECC)
1 218 bytes spare (Micron, Toshiba: 8-bit ECC)
This read-only bit shows the BOOT INT value.
0 External Boot
1 Internal Boot
This read-only bit shows the EEPROM CFG fuse/GPIO value.
It selects whether EEPROM device is used for load of configuration DCD data, prior to boot from other
devices (not applicable when using EEPROM as boot device)
0 Use EEPROM DCD
1 Don’t use EEPROM DCD
This read-only bit shows the MLC SEL fuse/GPIO value.
0 SLC NAND device
1 MLC NAND device
Reset status bits. Shows what caused the most recent reset to the system.Otherwise, the last signal that
is released is honored.
0000 POR reset
0001 Reset In reset.
xx10 WDOG reset
x1x0 SOFT RESET
1xx0 JTAG SW RESET
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-28
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.12 CCM Reset and Debug Register (CRDR)
\
Offset 0x002C (CRDR)
31
30
Access: User read-write
29
28
27
26
R
BT UART SRC
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
BT LPB FREQ
W
Reset
R
0*
0*
0*
0*
0*
0*
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Note: All reset values with “*” depend on fuse values or GPIO values at boot-up.
Figure 15-14. CCM Debug Register (CDCR)
Table 15-20. CDCR Field Descriptions
Name
31–29
BT UART
SRC
28–26
BT LPB
FREQ
25–0
Description
These bits show BT UART SRC fuse/GPIO value. (read only)
000 UART-1
001 UART-2
010 UART-3
011 UART-4
100 UART-5
OthersReserved
These bits show LPB ARM core frequency fuse/GPIO value. (read only)
000 133 MHz (default)
001 24 MHz
010 55.33 MHz
011 66 MHz
100 83 MHz
101 166 MHz
110 266 MHz
111 Normal Boot frequency.
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-29
Clock Controller Module (CCM)
15.3.3.13 DPTC Comparator Value Registers (DCVR0–DCVR3)
These registers contain relevant DPTC lookup table values.
Offset 0x0030 (DCVR0)
0x0034 (DCVR1)
0x0038 (DCVR2)
0x003C (DCVR3)
31
30
29
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ULV
LLV
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
LLV
ELV
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-15. DPTC Comparator Value Register (DCVR0–DCVR3)
Table 15-21. DCVR0–DCVR3 Field Descriptions
Name
Description
31–22
ULV
Upper limit value. Upper performance limit of the reference circuit clock counter.
21–12
LLV
Lower limit value. Lower performance limit of the reference circuit clock counter.
11–2
ELV
Emergency limit value. Lower performance limit of the reference circuit clock counter. This serves as an
“emergency” lower limit, which indicates a critical value.
1–0
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-30
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.14 Load Tracking Register 0 (LTR0)
Offset 0x0040 (LTR0)
31
30
Access: User read-write
29
R SIGD SIGD SIGD
14
13
W 15
Reset
28
27
26
25
24
23
22
21
20
19
17
16
0
UPTHR
DNTHR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD
11
10
9
8
7
6
5
4
3
2
1
0
W 12
Reset
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIV3CK
0
0
0
Figure 15-16. Load Tracking Register 0 (LTR0)
Table 15-22. LTR0 Field Descriptions
Name
Description
31–30
SIGDn
SIGD15–14These two bits always use reset value which is logic 0.
1 Edge detection.
0 Level detection.
29
SIGDn
SIGD13
These bits define wheather the dvfs_w_sig[12:0] signals are detected using level of edge detection.
1 Edge detection.
0 Level detection.
28
Reserved
27–22
UPTHR
Upper threshold for load tracking.
21–16
DNTHR
Lower threshold for load tracking.
15–3
SIGDn
SIGD12–0
These bits define whether the dvfs_w_sig[12:0] signals are detected using level or edge detection.
1 Edge detection.
0 Level detection.
2–1
DIV3CK
0
Defines the division value of div_3_clk.
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-31
Clock Controller Module (CCM)
15.3.3.15 Load Tracking Register 1 (LTR1)
Offset 0x0044 (LTR1)
R
Access: User read-write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
W
Reset
23
22
21
20
LT
LT
BRSH BRSR
19
18
17
16
DNCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
DNCNT
UPCNT
PNCTHR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-17. Load Tracking Register 1 (LTR1)
Table 15-23. LTR1 Field Descriptions
Name
31–24
Description
Reserved
23
LTBRSH
Load tracking buffer shift
0 takes the original MSB of ld_add (ld_add[5:2])
1 takes a shift of ld_add (ld_add[4:1])
22
LTBRSR
Load tracking buffer source
0 pre_ld_add
1 ld_add
21–14
DNCNT
These bits define the number of consecutive times the lower frequency threshold is undershot (that is, the effective
frequency is lower than this threshold) in order to generate a dvfs_fdw signal. This signal causes a decrease of
the system frequency.
00000001 2
00000010 3
...
The value 00000000 is not allowed.
13–6
UPCNT
These bits define the number of consecutive times the upper frequency threshold must be exceeded (threshold
overcomes) in order to generate a dvfs_fup signal. This signal causes an increase of the system frequency.
00000001 2
00000010 3
...
The value 00000000 is not allowed.
5–0
PNCTHR
These bits define panic mode level threshold for load tracking.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-32
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.16 Load Tracking Register 2 (LTR2)
Offset 0x0048 (LTR2)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
R
WSW15
WSW14
WSW13
WSW12
WSW
10
WSW11
W
Reset
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
WSW10
WSW9
EMAC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-18. Load Tracking Register 2 (LTR2)
Table 15-24. LTR2 Field Descriptions
Name
31–29
WSW15
Description
These bits define the general purpose load tracking signals dvfs_w_sig[15:9]
28–26
WSW14
25–23
WSW13
22–20
WSW12
19–17
WSW11
16–14
WSW10
13–11
WSW9
10–9
8–0
EMAC
Reserved
These bits define the EMA configuration.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-33
Clock Controller Module (CCM)
15.3.3.17 Load Tracking Register 3 (LTR3)
Offset 0x004C (LTR3)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
R
WSW8
WSW7
WSW6
WSW5
WSW
3
WSW4
W
Reset
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
R
WSW3
WSW2
WSW1
WSW0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 15-19. Load Tracking Register 3 (LTR3)
Table 15-25. LTR3 Field Descriptions
Name
Description
31–29,
WSW8
These bit fields (each one in turn) define the weight of each of the general purpose load tracking signals
(dvfs_w_sig[8:0]). The total CPU load as a result of the dvfs_w_sig signal is defined as a sum of each of
the individual signal’s dvfs_w_sig[n] value multiplied by its weight, as defined by the corresponding
WSWn bit field.
28–26,
WSW7
25–23,
WSW6
22–20,
WSW5
19–17,
WSW4
16–14,
WSW3
13–11,
WSW2
10–8,
WSW1
7–5,
WSW0
4–0
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-34
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.18 Load Tracking Buffer Register 0 (LTBR0)
Offset 0x0050 (LTBR0)
31
30
R
Access: User read-write
29
28
27
26
LTS7
25
24
23
22
LTS6
21
20
19
18
LTS5
17
16
LTS4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
LTS3
LTS2
LTS1
LTS0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-20. Load Tracking Buffer Register 0 (LTBR0)
Table 15-26. LTBR0 Field Descriptions
Name
31–28,
LTS7
Description
These eight fields contain data from the last eight samples of load tracking.
27–24,
LTS6
23–20,
LTS5
19–16,
LTS4
15–12,
LTS3
11–8,
LTS2
7–4,
LTS1
3–0,
LTS0
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-35
Clock Controller Module (CCM)
15.3.3.19 Load Tracking Buffer Register 1 (LTBR1)
Offset 0x0054 (LTBR1)
31
R
30
Access: User read-write
29
28
27
LTS15
26
25
24
23
LTS14
22
21
20
19
LTS13
18
17
16
LTS12
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
LTS11
LTS10
LTS9
LTS8
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-21. Load Tracking Buffer Register 1 (LTBR1)
Table 15-27. LTBR1 Field Descriptions
Name
31–28
LTS15
Description
These eight fields contain data from the first eight samples of load tracking.
27–24
LTS14
23–20
LTS13
19–16
LTS12
15–12
LTS11
11–8
LTS10
7–4
LTS9
3–0
LTS8
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-36
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.20 Power Management Control Register 0 (PMCR0)
Offset 0x0058 (PMCR0)
31
30
Access: User read-write
29
28
27
26
25
R
Reset
22
21
20
19
18
17
16
DVFS
PTVI
_STA
S
RT
LBCF
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DRC
E2
DRC
E1
DRC
E0
SCR
0
0
0
1
R
FS
VAIM
W
Reset
23
DVFS
_UPD DVFE DVFI
LBMI LBFL
_FINI
V
S
SH
DVSUP
W
24
1
FSVAI
0
0
DRC
DPVC
DPVV WFIM
R
E3
1
1
0
0
DVFE PTVA
N
IM
0
1
PTVAI
0
0
DPTE
N
0
Figure 15-22. Power Management Control Register 0 (PMCR0)
Table 15-28. PMCR0 Field Descriptions
Name
Description
31–30
Reserved
29–28
DVSUP
These two bits define the voltage level.
00 DVS0=0 DVS1=0 (highest frequency/voltage level)
01 DVS0=0 DVS1=1
10 DVS0=1 DVS1=0
11 DVS0=1 DVS1=1 (lowest frequency/voltage level)
27–25
Reserved
24
This bit shows DVFS UPDATE finish by software
DVFS_UPD 0 Not finished
_FINISH
1 Finished
23
DVFEV
Always give a DVFS event.
0 Do not give an event always.
1 Always give event.
22
DVFIS
DVFS Interrupt select. These bits define destination of DVFS interrupts.
1 Core interrupt will be generated for DVFS events.
0 SDMA interrupt will be generated for DVFS events.
21
LBMI
Load buffer full mask interrupt. This bit masks the generation of this interrupt.
1 Load buffer full interrupt is masked.
0 Load buffer full interrupt is enabled.
20
LBFL
Load buffer full status bit. This bit indicates that log buffer registers are full. An interrupt will be generated if the
LBMI bit is cleared. Software can only write 0 to this bit.
1 Load buffer is full.
0 Load buffer is not full.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-37
Clock Controller Module (CCM)
Table 15-28. PMCR0 Field Descriptions (continued)
Name
Description
19–18
LBCF
DVFS load buffer programmable size
00 Load buffer size is 4
01 Load buffer size is 8
10 Load buffer size is 12
11 Load buffer size is 16
17
PTVIS
DPTC Interrupt select. These bits define destination of DPTC interrupts.
1 Core interrupts will be generated for DPTC events
0 SDMA interrupts will be generated for DPTC events.
16
DVFS update start bit, configured by software.Asserted when update is in progress.
DVFS_STA 0 DVFS update is not active
RT
1 DVFS update is in progress
15
FSVAIM
14–13
FSVAI[1:0]
12
DPVCR
DVFS Frequency adjustment interrupt mask. This bit masks the DVFS frequency adjustment interrupt. FSVAI
status bits will be still asserted in relevant cases.
1 interrupt is masked.
0 interrupt is enabled.
FSVAI
DVFS Frequency adjustment interrupt. These status bits indicate that the system frequency should be changed.
00 No interrupt
01 Frequency should be increased. Low priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked
if DVLV = 00 (highest frequency).
10 Frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if DVLV = 11 (lowest
frequency).
11 Frequency should be increased immediately. High priority interrupt. Interrupt is asserted, if FSVAIM=0.
Interrupt is masked if DVLV = 00 (highest frequency).
DPTC voltage change request
0 Disabled
1 Enabled
11
DPVV
DPTC voltage valid edge detect. Can be updated by SW. If written by SW, it is possible to assert it only after
DPVCR is asserted.
0 Voltage is not valid
1 Received a voltage valid acknowledge
10
WFIM
DVFS Wait for Interrupt mask bit
0 Wait for interrupt not masked
1 Wait for interrupt masked.
9
DRCE3
DPTC reference circuit3 enable bit. This bit defines if reference circuit3 is enabled during DPTC operation.
1 DPTC reference circuit3 enabled.
0 DPTC reference circuit3 disabled.
8
DRCE2
DPTC reference circuit2 enable bit. This bit defines if reference circuit2 is enabled during DPTC operation.
1 DPTC reference circuit2 enabled.
0 DPTC reference circuit2 disabled.
7
DRCE1
DPTC reference circuit1 enable bit. This bit defines if reference circuit1 is enabled during DPTC operation.
1 DPTC reference circuit1 enabled.
0 DPTC reference circuit1 disabled.
6
DRCE0
DPTC reference circuit0 enable bits. This bit defines if reference circuit0 is enabled during DPTC operation.
1 DPTC reference circuit0 enabled.
0 DPTC reference circuit0 disabled.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-38
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-28. PMCR0 Field Descriptions (continued)
Name
Description
5
SCR
DPTC counting range. This bit sets how many times the system clock may increment and the reference circuits
remain active (and their output signals are counted).
1 512 system clock count
0 256 system clock count
4
DVFEN
DVFS enable. This bit enables the DVFS block. Between disable and enable there has to be at least 3 cycles of
div_3_clk.
1 DVFS enabled.
0 DVFS disabled.
3
PTVAIM
DPTC Voltage adjustment interrupt mask. This bit masks the DPTC voltage adjustment interrupt. PTVAI status
bits will be still asserted in relevant case.
1 interrupt is masked.
0 interrupt is enabled.
2–1
PTVAI[1:0]
DPTC Voltage adjustment interrupt. These status bits indicate that the supply voltage should be changed.
00 No interrupt
01 Voltage should be decreased. Interrupt is asserted, if PTVAIM=0
10 Voltage should be increased. Low priority interrupt. Interrupt is asserted, if PTVAIM=0
11 Voltage should be increased immediately. High priority interrupt. Interrupt is asserted, if PTVAIM=0
0
DPTEN
DPTC enable. This bit enables the DPTC block and starts the reference circuit clock counting and compares this
to look-up table values.
1 DPTC enabled
0 DPTC disabled
15.3.3.21 Power Management Control Register 1 (PMCR1)
Offset 0x005C (PMCR1)
R
31
30
0
0
W
Reset
R
29
Access: User read-write
28
27
CPEN CPFA
_EMI _EMI
26
25
24
23
22
21
CPSPA_EMI
20
19
18
17
16
WBCN
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPEN
CPSPA
CPFA
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 15-23. Power Management Control Register 1 (PMCR1)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-39
Clock Controller Module (CCM)
Table 15-29. PMCR1 Field Descriptions
Name
31–30
Description
Reserved
29
CPEN_EMI
EMI well bias enable.
0 Disabled
1 Enabled
28
CPFA_EMI
EMI well bias frequency adjust.
0 The free-running oscillator is in reduced mode.(frequency is approximately 0.75 times the full frequency
(default)
1 The free-running oscillator is set to full mode.
27–24
This field controls the EMI back-bias level of n-wells. (CSPA_EM[1:0]) and p-wells (CSPA_EM[3:2]).
CPSPA_EMI CSPA_EM[1:0]:
00 Increased back bias applied to the n-wells (appropriate for system voltage of 1.0 V or less).
01 Moderate back bias applied to the n-wells (appropriate for system voltage of 1.1 V or less)
10 Decreased back bias applied to the n-wells (appropriate for system voltage of 1.2 V or less).
11 Minimum back bias applied to the n-wells (appropriate for system voltage of 1.2 V or less).
CSPA_EM[3:2]:
00 Increased back bias applied to the p-wells (appropriate for system voltage of 1.0 V or less).
01 Moderate back bias applied to the p-wells.(appropriate for system voltage of 1.1 V or less).
10 Decreased back bias applied to the p-wells (appropriate for system voltage of 1.2 V or less).
11 Minimum back bias applied to the p-wells (appropriate for system voltage of 1.2 V or less).
23–16
WBCN
Well bias counter. This field specifies the waiting period after exit from well bias mode, measured in CKIH
(24 MHz) clock cycles. After this period, the signals emi_wbcp_fbd_b and mcu_wbcp_fbd_b are negated
(preventing re-entry to well bias mode) and run mode is resumed.
According to well bias specifications, the waiting period should be at least 3 μs, which implies that the WBCN
value should be at least 72 (0b100_1000).
15–14
Reserved
13
CPEN
This bit enables/disables the ARM platform well bias.
0 ARM platform well bias is disabled.
1 ARM platform well bias is enabled.
12–9
CPSPA
This field controls the ARM platform back-bias level of n-wells (CSPA[1:0]) and the p-wells (CSPA[3:2]).
CSPA[1:0]:
00 Increased back bias applied to the n-wells (appropriate for system voltage of 1.0 V or less).
01 Moderate back bias applied to the n-wells (appropriate for system voltage of 1.1 V or less)
10 Decreased back bias applied to the n-wells (appropriate for system voltage of 1.2 V or less).
11 Minimum back bias applied to the n-wells (appropriate for system voltage of 1.2 V or less).
CSPA[3:2]:
00 Increased back bias applied to the p-wells (appropriate for system voltage of 1.0 V or less).
01 Moderate back bias applied to the p-wells.(appropriate for system voltage of 1.1 V or less).
10 Decreased back bias applied to the p-wells (appropriate for system voltage of 1.2 V or less).
11 Minimum back bias applied to the p-wells (appropriate for system voltage of 1.2 V or less).
8–7
6
CPFA
5–0
Reserved
ARM platform well bias frequency adjustment.
0 The free-running oscillator is in reduced mode.(frequency is approximately 0.75 times the full frequency
(default)
1 The free-running oscillator is set to full mode.
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-40
Freescale Semiconductor
Clock Controller Module (CCM)
15.3.3.22 Power Management Control Register 2 (PMCR2)
Offset 0x0060 (PMCR2)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
W
Reset
R
ARM MEMON CNT
18
17
16
ARM
OSC2
VSTB
MEM
4M_D
Y
DWN
OWN
ARM CLKON CNT
DVFS
DVFS _ACK
_REQ
W
Reset
1
0
1
0
0
0
0
0
0
0
1
1
0
0
Figure 15-24. Power Management Control Register 2 (PMCR2)
Table 15-30. PCMR2 Field Descriptions
31–19
18
ARM MEM
DWN
17
VSTBY
Reserved
This bit is used to control negation of arm_mem_on in doze and stop mode.
0 arm_mem_on and arm_mem_pwrdwn will be kept invalid in doze and stop mode.
1 arm_mem_on will be negated and arm_mem_pwrdwn will be asserted in doze and stop mode.
This bit controls whether or not the core voltage is lowered to 1.0 V in stop mode.
0 Core voltage is not lowered in stop mode.
1 Core voltage is lowered to 1.0 V in stop mode.
16
OSC24M_D
OWN
This bit controls the OSC24M power supply during stop mode.
0 OSC24M will not be powered off in stop mode.
1 OSC24M will be powered off in stop mode.
15–8
ARM
MEMON
CNT
This field controls the delay before arm_mem_on is asserted.
0 1 OSC24M clock cycle delay
1 2 OSC24M clock cycles delay.
...
255 256 OSC24M clock cycles delay.
7–4
ARM
MEMON
CNT
This field controls the delay between arm_mem_on and arm_clock_on.
0 1 OSC24M clock cycle delay
1 2 OSC24M clock cycles delay.
...
15 256 OSC24M clock cycles delay.
3–2
Reserved
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-41
Clock Controller Module (CCM)
Table 15-30. PCMR2 Field Descriptions (continued)
1
DVFS_REQ
This bit controls the dvfs_req signal (frequency change request) to EMI M3IF. This bit is automatically cleared
by the dvfs_ack signal.
0 no dvfs_req signal
1 dvfs_req signal asserted
0
DVFS_ACK
This read-only bit shows whether or not EMI has closed the access for SDRAM.
0 No ack received
1 Ack received
15.3.3.23 Miscellaneous Control Register (MCR)
Offset 0x0064 (MCR)
31
30
Access: User read-write
29
28
R USB
CLKO
XTAL
W MUX EN
Reset
27
26
25
24
23
CLKO DIV
22
21
20
19
18
ESAI SSI2
CLK CLK
MUX MUX
CLKO SEL
17
16
SSI1
CLK
MUX
USB
CLK
MUX
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
PER CLK MUX
W
Reset
0
0
0
0
0
0
0
0
0
Figure 15-25. Miscellaneous Control Register (MCR)
Table 15-31. MCR Field Descriptions
31
USB XTAL
MUX
This bit selects output of UXTAL1_CKIN.
0 External 24 MHz clock
1 24 MHz source is divided from the UPLL 240 MHz. (fixed divided by 10)
30
CLKO EN
This bit is used to enable/disable the CLKO debug function. When set to 1, the selected clock will be routed to
CLKO pad.
0 Disable
1 Enable
29–24
CLKO DIV
These bits control the divider for CLKO, the source clock selected by CLKO SEL. See Figure 15-28.
000000 Divide by 1
000001 Divide by 2
…
111110 Divide by 63
111111 Divide by 64
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-42
Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-31. MCR Field Descriptions
23–20
CLKO SEL
These bits select which clock is to be reflected on the clock output CKO
000032 kHz clock.
0001 Input 133 MHz clock for PLL reference
0010 Ungated arm_clk.
0011 Ungated ahb_clk.
0100 Ungated ipg_clk.
0101 per_clk_0 clock source.
0110 usb_clk clock source.
0111 Gated arm_clk.
1000 Gated ahb_clk.
1001 Gated ipg_clk.
1010 per_clk_0.
1011 per_clk_2.
1100 per_clk_13.
1101 per_clk_14.
1110 usb_clk.
1111 Reserved
19
ESAI CLK
MUX
This bit controls which divider will be selected for per_clk_2.
0 Normal divider, which is same as other per_clk except esai, ssi1, ssi2.
1 A dedicated divider which divides the 240 MHz UPLL clock output to 24.61 MHz.
18
SSI2 CLK
MUX
This bit controls which divider will be selected for per_clk_14.
0 Normal divider, which is same as other per_clk except ESAI, SSI1, SSI2.
1 A dedicated divider which divides the 240 MHz UPLL clock output to 24.61 MHz.
17
SSI1 CLK
MUX
This bit controls which divider will be selected for per_clk_13.
0 Normal divider, which is same as other per_clk except ESAI, SSI1, SSI2.
1 A dedicated divider which divides the 240 MHz UPLL clock output to 24.61 MHz.
16
USB CLK
MUX
This bit determines the clock source for usb_clk.
0 UPLL output
1 HCLK
15–0
PER CLK
MUX
These bits determine the clock source for each per_clk. That is, bit n determines the source for per_clk_n.
0 HCLK
1 UPLL output
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-43
Clock Controller Module (CCM)
15.3.3.24 Low Power Interrupt Mask Registers (LPIMR0)
Offset 0x0068 (LPIMR0)
31
30
29
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
R
LPIM[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
LPIM[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 15-26. Low Power Interrupt Mask Register 0 (LPIMR0)
Table 15-32. LPIMR0 Field Descriptions
31–0
LPIM
Low power interrupt mask. Each bit enables/disables the corresponding interrupt to CCM in low-power mode.
0 Interrupt is enabled.
1 Interrupt is masked in low-power mode.
15.3.3.25 Low Power Interrupt Mask Registers (LPIMR1)
Offset 0x006C (LPIMR1)
31
30
29
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
R
LPIM[63:48]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
LPIM[47:32]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 15-27. Low Power Interrupt Mask Register 1 (LPIMR1)
Table 15-33. LPIMR1 Field Descriptions
31–0
LPIM[63:32]
Low power interrupt mask. Each bit enables/disables the corresponding interrupt to CCM in low-power mode.
0 Interrupt is enabled.
1 Interrupt is masked in low-power mode.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
15-44
Freescale Semiconductor
Clock Controller Module (CCM)
The LPIMR0 and LPIMR1control 64 interrupt requests to wake-up CCM from low-power mode, and
resume clocks. Table 15-34 lists the wake-up interrupt sources.
Table 15-34. Wake-up Interrupt Sources
IRQ
Interrupt Source
Interrupt Description
0
CSPI3
—
1
GPT4
—
2
OWIRE
—
3
I2C1
—
4
I2C2
—
5
UART4
—
6
RTIC
—
7
ESAI
—
8
ESDHC2
—
9
ESDHC1
—
10
I2C3
—
11
SSI2
—
12
SSI1
—
13
CSPI2
—
14
CSPI1
—
15
ATA
—
16
GPIO3
17
CSI
—
18
UART3
—
19
IIM
—
20
SIM1
—
21
SIM2
—
22
RNGB
—
23
GPIO4
24
KPP
25
Dry-Ice
26
PWM
—
27
EPIT2
—
28
EPIT1
—
29
GPT3
—
30
POWER FAIL
Combined Interrupts - 1 Bit Int Or Of 32
Combined Interrupts - 1 Bit Int Or Of 32
Keypad Interrupt
Consolidated RTC Interrupt
power fail interrupt from external PAD
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Clock Controller Module (CCM)
Table 15-34. Wake-up Interrupt Sources (continued)
IRQ
Interrupt Source
Interrupt Description
31
CCM
—
32
UART2
—
33
NANDFC
34
SDMA
35
USB-HTG
—
36
PWM2
—
37
USB-OTG
—
38
SLCDC
—
39
LCDC
—
40
UART5
—
41
PWM3
—
42
PWM4
—
43
CAN1
—
44
CAN2
—
45
UART1
—
46
TSC
—
47
Reserved
—
48
ECT
—
49
SCC SCM
SCM interrupt
50
SCC SMN
SMN interrupt
51
GPIO2
Combined Interrupts - 1 Bit Int Or Of 32
52
GPIO1
Combined Interrupts - 1 Bit Int Or Of 32
53
GPT2
—
54
GPT1
—
55
WDOG
—
56
Dry-Ice
—
57
FEC
—
58
EXT_INT5
external interrupt for Pwr Management
using GPIO-1[5]
59
EXT_INT4
external interrupt for Temp
using GPIO-1[6]
60
EXT_INT3
external interrupt for Sensor
using GPIO-1[0]
Consolidated Nand Flash Controller Interrupt
“AND” of all 32 interrupts from all the channels
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Freescale Semiconductor
Clock Controller Module (CCM)
Table 15-34. Wake-up Interrupt Sources (continued)
15.4
IRQ
Interrupt Source
Interrupt Description
61
EXT_INT2
external interrupt for Sensor
using GPIO-1[1]
62
EXT_INT1
external interrupt for Watch-dog
using GPIO-1[2]
63
EXT_INT0
external interrupt for TV
using GPIO-1[3]
Functional Description
15.4.1
Clock Control and Gating
Figure 15-28 shows the overall clock generation scheme.
ARM SCLK
arm_src_sel
532MHz
OSC22M
MCU
DPLL
arm_clk_div
ahb_clk_div
2B
2B
DIV
DIV
ARMclock
AHBSCLK
CKGATE
DIVGEN
399MHz
266M
clk_sel
/2
IPGSCLK
16
54
16
133MHz
PCLK
6BDIV
EXT266M
AHB clock
IPGclock
PERclock
USB clock
240MHz
USB
DPLL
Figure 15-28. i.MX25 Clock Generation Scheme 1
1
This figure does not show scan multiplexer and clock gating. For the scan multiplexer refer to Section 15.4.1.4, “Scan Mode
Clock Multiplexers”
15.4.1.1
Clock Sources
There are two clock sources:
• 24 MHz external crystal
• 32 kHz clock input
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15-47
Clock Controller Module (CCM)
15.4.1.1.1
24 MHz External Crystal
An external 24 MHz crystal is required for the functioning of the internal oscillator. The 24 MHz signal is
used as a core PLL and peripheral PLL reference clock, and also serves as the reference frequency for
USBPHY.
The internal 24 MHz oscillator can be bypassed through the CLKMOD pins, so that the external 24 MHz
clk can enter the device directly.
Figure 15-28 describes these functions.
15.4.1.1.2
32 kHz Clock Input
The 32 kHz clock is input from the DryIce module. It is synched with the IPG clock, then sent to each
module.
15.4.1.2
Core PLL Domain Clock Generation
There are two DPLLs in the system that generate all high-frequency clocks for each module.
The MPLL is configured by the MPCTL register. Figure 15-28 shows the clock generation scheme. The
two ports generate edge-aligned clocks. The configuration of the clock switch is defined in the register
map. The ARM and AHB clock frequency ranges are 133–532 MHz and 66.5–133MHz, respectively.
Internal logic guarantees that the ARM/AHB clock switches concurrently at the ARM/AHB aligned rising
edge.
15.4.1.3
USB PLL (UPLL) Domain Clock Generation
The UPLL is configured by the UPCTL register, and has the same design as the MPLL. Its dpgdck port
generates a 240 MHz clock for USB/SSI/MSHC/UART/LCDC/CSI baud-rate clock generation. The
baud-rate clocks of these modules need not be synched with the AHB/IPG clock, since most are used to
generate data to communicate externally.
15.4.1.4
Scan Mode Clock Multiplexers
Scan mode clock multiplexers enable external sources of clocks (from I/O pins) to bypass the clock
generation scheme. This is useful in scan mode and reduces the number of sources to different subdomains
in transition scan mode. Figure 15-29 illustrates the scan mode clock multiplexer structure.
func_mode_clk
CG
clock
0
scan_mode_clk
ipp_tck
ipt_lch_mode
0
1
1
output_cntr
Figure 15-29. Scan Mode Clock Multiplexer Illustration
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Freescale Semiconductor
Clock Controller Module (CCM)
15.4.2
Reset Module
This section includes the following:
• A description of the reset module
• The reset negation sequence from POR
• A description of other reset events
15.4.2.1
Functional Description of the Reset Module
The reset module controls or distributes all of the system reset signals used by ti.MX25. Figure 15-30 gives
a simplified block diagram of the reset module. The reset signals shown in Figure 15-30 are described in
Table 15-35, and the timing parameters are described in Table 15-36.
Table 15-35. Reset Module Signals
Signal Name
ipp_por_b
Description
Resets OSC24M, which is input from external source
por_reset_b
Resets DPLLs, fusebox and IIM
emi_reset_b
Resets EMI module
scc_reset_b
Resets SCC and security modules
:
hreset_b
Resets ARM platform
per_reset
Resets peripheral modules
Table 15-36. Reset Module Timing Parameters
Timing Parameter
Description
t0
Time for the power-up sequence of all the supplies. After t0, OSC24M starts to work.
t1
t1 depends on boot mode:
• If boot mode is PROD mode (0b01) then t1 is 8 32-kHz cycles
• If boot mode is not PROD mode, then t1 is 256 32-kHz cycles
After t1, IIM, fusebox, and the DPLLs start to work
t2
4 32-kHz cycles+ 1 HCLK cycle. After t2, EMI starts to work.
t3
• For NAND boot, t3 is 32 32-kHz cycles + 1 HCLK cycle
• Otherwise t3 is 4 cycles 32-kHz + 1 HCLK cycle
After t3, the security modules and SCC start to work.
t4
• 1 HCLK cycle for hreset_b
• 1 ipg_clk cycle for per_reset_b
After t4, all other modules start to work
t5
Out of reset
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15-49
Clock Controller Module (CCM)
IIM &
F use
DP LL
US B
OS C2 4 M
Ot her
M o d ules
Secret
M o d ules
M CU
EM I
S CC
ARM
DP LL
Time
t0
t2
t1
t3
t4
t5
ipp_por_b
por_reset_b
emi_reset_b
scc_reset_b
hreset_b/per_reset_b
reset_in_b and wdog_reset_b
will be started here
Figure 15-30. Reset Module Clock Diagram
15.4.2.2
Other Reset Events
Other reset events include the following:
• Watchdog resets
• reset_in_b source
• JTAG software reset
These resets are described in the following subsections.
15.4.2.2.1
Watchdog Resets
There are two different watchdog reset events: time out event or software reset. For more information about
these events, refer to the watchdog specification.
A watchdog module reset, wdog_reset_b causes a reset of the chip, so that the CCM thereby generates a
reset pulse. When the core comes out of reset it can check the “reset source” bits in the CCM module.
15.4.2.2.2
reset_in_b Source
reset_in_b can trigger the EMI, peripheral and core resets, but does not reset the PLL, fusebox, or CCM.
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Clock Controller Module (CCM)
15.4.2.2.3
JTAG Software Reset
The device can be reset using software from a JTAG module, either by a signal or by a general-purpose bit.
15.4.3
Power Management
CCM supports several power management techniques that reduce active and static power consumption:
• Clock gating reduces the active power if the module is not active. CCM has low power mode
power gating to gate the source clocks, and has register control the clock gating of each module.
• Dynamic voltage frequency scaling (DVFS) reduces active power consumption by scaling
voltage and frequency accordingly to required MIPs.
• Dynamic process temperature compensation (DPTC) reduces active power consumption by
adjusting supply voltage according to specific process cases, the manner in which the chip was
fabricated, and the ambient temperature.
• Active well bias (AWB) reduces static power consumption by applying back bias on transistors.
AWB can be applied on ARM9P. ARM9P is not functional when AWB is applied.
15.4.3.1
Power Domains
The i.MX25 is partitioned into several power domains, but all digital logics are included in one common
power domain. Digital core logic can run at 133 MHz, 266 MHz, or 399 MHz while the voltage is above
1.1 V (worst case scenario).
15.4.3.2
Power Modes
The i.MX25 supports a versatile definition of power modes, including power and clock domains status and
applied power techniques. The power modes described in the following sections were defined taking into
account static and dynamic power consumption of blocks in different operational modes, the power
consumption of clock sources, and the time required to exit low power modes.
15.4.3.2.1
Run Mode
This is the normal/functional operating mode of ARM9. The ARM clock frequency can vary between fmax
(532 MHz) and fmin (133 MHz), and the voltage between Vmax (1.65 V) and Vmin (1.10 V).
15.4.3.2.2
Wait Mode
In wait mode, the processor clock is gated, but ARM9P MAX and all peripherals clocks are available. This
mode is entered by the core executing a STANDBY FOR INTERRUPT command. The arm_clk_off
output of ARM Platform is asserted and the clock to the processor arm_clk is gated by the CCM. The
processor exits the wait mode and enters the run mode when a negation of arm_clk_off signal is detected.
Clocks for specific modules can be gated off in wait mode by programming CGR registers.
Note some modules must trigger handshake processes in order to close the clock: this includes SDMA and
EMI. These processes are handled automatically by the CCM and the respective modules.
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Clock Controller Module (CCM)
The wait mode entry procedure is as follows:
1. The arm_clk_off signal is asserted from the ARM9P core by executing the instruction.
2. If the SDMA clock is configured to be gated in wait mode, then the CCM sends out the stby_req
signal to the corresponding modules.
3. If the EMI module is configured to be gated in wait mode, then the CCM sends out the sd_lpmd to
EMI.
4. Once all ack signals have been received from the modules listed above, then the 4-bit IPG clock
counter is started.
5. If the FlexCAN module is configured to remain open in wait mode, then the CCM sends the
doze_request signal to the FlexCAN module. Otherwise if the FlexCAN module is configured to
be gated in wait mode, then the CCM sends the stop_request signal to the FlexCAN module.
6. After the ack from the FlexCAN module is received and the 4-bit counter counts 9 IPG cycles, then
the lpm_sm signal is in WAIT_MODE.
Wait mode is exited by negating the arm_clk_off signal. The system then immediately returns to RUN
mode.
15.4.3.2.3
Doze Mode
In doze mode the processor and MAX clocks are gated. The clock source is still available, and peripherals
that do not require MAX and core functionality can be active.
Clocks for specific modules can be gated off in doze mode by programming the CGR register. Note some
modules (such as SDMA, IPU, and EMI) must trigger a handshake process while trying to close the clock:
this process is handled automatically by the modules and the CCM.
Doze mode is entered by programming the LP CTL field in the CCTL register to 0b10, then issuing a
standby for interrupt command (which asserts the arm_clk_off signal). The doze mode entry procedure is
as follows:
1. CCM sends out the stby_req to modules that are configured as clock-gated in doze mode.
2. CCM sends out the max_halt request.
3. Once stby ack from IPU/SDMA and max halt ack are received, then CCM sends out the
emi_lpm_sd req if EMI is configured as clock gated in doze mode.
4. Once all ack signals (SDMA/MAX/EMI) are received, then if FlexCAN is configured to keep
clock in doze mode the CCM will send out the can_doze request: otherwise if FlexCAN is
configured to gate clock in doze mode, then CCM will send out the can_stop request.
5. Once the ack signal is received from the FlexCAN module and the 4-bit counter finishes counting
nine IPG cycles, then lpm_sm changes into doze mode, and crm_int_holdoff is negated.
6. If the CPEN bit is set, then CCM asserts the mcu_wb_en, mcu_fbd_b, and mem_pwrdn signals to
the ARM9P core and negates the mem_on signal to the ARM9P core.
The doze mode exit process proceeds as follows:
1. If the CPEN bit is not set to 1, the system returns immediately to RUN mode.
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Clock Controller Module (CCM)
2. If the CPEN bit is set to 1, then the mcu_mem_pwrdn and mcu_wb_en signals are immediately
cleared. After the wb_counter_finished signal is asserted, then mcu_mem_on is asserted,
mcu_wbcp_fbd_b is negated, and the system returns to run mode.
15.4.3.2.4
Stop Mode
Stop mode stops the PLL and all clocks which are generated from PLL. If the VSTBY bit is set to 1, then
CCM informs the external PMIC to lower the core supply to 1.0 V after all PLLs are closed. If the
OSC24M_DOWN bit is set to 1, then the CCM powers down OSC24M to reduce the system power to
minimum.
Stop mode is entered by setting the LP CTL field in the CCTL register to 0b11, then issuing a standby for
interrupt command. The stop mode entry procedure is as follows:
1. SDMA, MAX, CAN, and EMI standby requests are sent out to those modules which are not clock
gated before stop mode.
2. After all ack signals are received CCM waits eight IPG clk cycles, then requests CKIL to switch
from IPG synched to not synched. sm_mode changes to stop, and the ARM clock is gated.
3. If the wb_en signal is asserted, then CCM asserts mcu_wb_en (emi_wb_en), mcu_fbd_b
(emi_fbd_b), mem_pwrdn for ARM9P and negates mem_on for ARM9P. This is the same as doze
mode.
4. If the PLL lock flag is negated, then crm_int_holdoff is negated to allow interrupt.
5. If the VSTBY bit is set to 1, then CCM sends out the vstby_pmic to PMIC through pad. This
requests the external PMIC to lower down core logic to 1.0 V for state retention.
6. If the OSC24M_PWRDN bit is set to 1, then CCM sends out the osc24m_pwr signal to power
down OSC24M (which also stops the internal 32 kHz clock, since it is divided from OSC24M).
This special mode (“static mode”) can be considered as a submode of stop mode.
State retention mode is exited by any internal or external interrupt.
The stop mode exit procedure is as follows:
1. The arm_clk_off signal is negated, and the FSM changes to the exit process.
2. If the system in state retention mode, then vstby_pmic is negated to request the external PMIC to
restore the voltage supply from 1.0 V to normal voltage.
3. If OSC24M is powered down, then the CCM negates the osc_pwr signal, causing the OSC24M to
power up. After power-up the CCM must wait for the 32 kHz clock counter to finish to ensure that
the OSC24M output is stable.
4. If system was configured in voltage reduce mode, the CCM waits for the 32 kHz clock counter to
finish or ipp_pmic_rdy signal ack from PMIC.
5. After the OSC24M is stable and PMIC is ready, the MPLL starts to relock.
6. If the wb_en bit is set to 1, then mcu_mem_pwrdn and mcu_wb_en (emi_wb_en) are immediately
negated and wb_en counter begins.
7. After the PLL is ready and the ARM clock begins, the chips returns to run mode.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
15-53
Clock Controller Module (CCM)
T
mcu_wb_en
wbcp_fbd
ccm_mcu_mem_pwrdn
ccm_mcu_mem_on
Figure 15-31. Well Bias Activation/Deactivation and ARM Core Power Gating for Kilobit Memories.
15.4.3.3
DVFS Support
The CCM allows simple software dynamic voltage frequency scaling. The frequency of the core clock
domain and the voltage of the chip can be changed on the fly while all modules (including the core)
continue their normal operation. The voltage of the chip can be changed by software through CSPI/I2C
port between the i.MX25 and the external PMIC. The frequency of the core clock domain can be changed
by configuring CCTL register.
The system bus frequency (AHB, IP) can also be changed according to core clock. The AHB frequency is
configured by AHB_DIV, and the IP frequency is fixed at half of the AHB frequency.
The i.MX25 DVFS scheme requires additional software configuration. Figure 15-32 shows the DVFS
software routine flow in i.MX25, after the triggering of a DVFS interrupt or DVFS DMA event.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
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Freescale Semiconductor
Clock Controller Module (CCM)
config dvfs_start bit
and mask interrupt
Check LBFL
==1
read LBCF
==0
read LBTR0 and LBTR1 and
write their values to mem buffer
according to LBCF register
write 0 to LBFL
check FSVAI
FSVAI==10
FSVAI==01||11
Frequency/voltage should
de decreased up_val = 0
Frequency/voltage should
be increased up_val = 1
write 0 to DPVCR
check DVSUP for
software decide voltage change or not
voltage need
no voltage
vol = 1
vol = 0
check up_val
up_val = 0
up_val = 1
1.config PMIC through SPI/I2C to increase the voltage
first check dpvv to confirm voltage is ready, or check the
PMIC to confirm.(this step is needed only while vol is 1)
2.write the new frequency to PDR0 to increase
frequency if needed.
1.write new frequency to PDR0 to lower down frequency if needed.
2.config PMIC through SPI/I2C to lower down the frequency.check
dpvv to confirm voltage is ready, or check the PMIC to confirm.(this
step is needed only while vol is 1)
update register DVSUP to new
frequency/voltage level.
unmask DVFS interrupt now. Config
dvfs_upd_finish bit in PMCR0
End
Figure 15-32. DVFS Frequency/Voltage Change Process
The DVFS load-tracking block allows hardware tracking on the core load and the generation of an
interrupt when a frequency change is requested.
15.4.3.4
Dynamic Process and Temperature Compensation (DPTC) Support
The DPTC module is a power management module. The purpose of the DPTC module is to detect the
minimum operation voltage for the IC, taking into account the worst-case values for processing activity
and ambient temperature for a given frequency. It inputs predefined values for process speed performance
measurement, and generates an interrupt if the value of the supply voltage must be updated.
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15-55
Clock Controller Module (CCM)
15.4.3.4.1
Synchronization Between DVFS and DPTC
In order to avoid a situation of DPTC trying to update events during voltage update done by DVFS a
synchronization scheme has been created.
The DPTC machine can work in case the DPTC is enabled and the voltage is valid (DPVV = 1) and there
is no voltage change request (DPVCR = 1).
15.4.3.5
Well Bias Support
Well bias is implemented with an on-chip charge pump. When well bias is activated, the voltage of wells
is pumped to optimal values to allow minimum leakage. Parameters of the charge pump can be controlled
in software by setting configuration bits in the PMCR1 register. The device has both ARM9P and EMI
well bias.
15.4.3.5.1
Well Bias Activation
EMI well bias is similar to ARM well bias, but it works in stop mode only.
In the ARM domain, well bias can be activated in doze or state retention modes by asserting the
mcu_wb_en signal and mcu_wbcp_fbd_b. The ARM platform contains memory blocks with standard
threshold voltage transistors, which have relatively high power leakage. Well bias eliminates this leakage
by power gating, so that there is no need for data saving or restoration. The interface to memory is power
gated by asserting the crm_mcu_mem_pwrdn signal and negating the crm_mcu_mem_on signal.
15.4.3.5.2
Well Bias Deactivation
When ARM negates the arm_clk_off signal, the CCM negates the mcu_wb_en signal. The clock is
provided to ARM9P after the well bias counter reaches the threshold defined by the WBCN field, or after
any other event that lasts longer than 10 ns. The ARM9P memories interface power supply is restored by
negation of the crm_mcu_mem_pwrdn signal, together with negation of mcu_wb_en and assertion of the
crm_mcu_mem_on and mcu_wbcp_fbd_b signals upon clock restoration.
EMI well bias also deactivates automatically.
15.4.3.6
State Retention Voltage Support
In STOP modes, the supply voltage of the i.MX25, can be reduced to a State Retention value, which allows
a reduction of chip leakage current while embedded memory state is dormant. Cores and modules using
embedded memory are not functional in this mode. Voltage will be reduced by PMIC after assertion of the
lpm_sm_vstby_pmic signal, which in turn asserts the VSTBY I/O pin. Voltage will be restored to previous
value upon negation of this signal. Valid voltage is indicated when the PMIC ready is asserted.
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Freescale Semiconductor
Chapter 16
ARM9 Platform Clock Control Module (CLKCTL)
16.1
Introduction
The CLKCTL module is used to enable or disable various peripherals on the platform. CLKCTL’s
registers interface with the AIPS module. The module also contains logic to determine when the ARM9’s
clock can be turned off. Figure 16-1 shows a general block diagram for the CLKCTL.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
16-1
ARM9 Platform Clock Control Module (CLKCTL)
ARM9 Platform
CLKCTL
ips_module_en
ips_addr [4:2]
ips_wdata [15:0]
CLKCTL
Registers
ips_byte_31_24
ips_byte_31_16
ips_byte_15_8
ips_rdata [31:0]
ips_xfr_wait
ips_xfr_err
arm9_active
ips_byte_7_0
ips_rwb
ips_supervisor_access
ARM9
Active
tapid [31:0]
IHTRANS[1]
DBGnTRST
jtag_trst_b
por
Generate
dbg_clear_b
any_scan_mode
jtag_tck
jtag_tms
jtag_tdi
JTAG Sync
dbgrq
ect_dbgrq
Debugger
Detection
etm_dbgrq
Individual
Module
Enables
any_scan_mode
any_test_mode
ipt_test_wrapper_clk_in[1:0]
dbg_clear_b
por_b
rtck
dbgtcken
dbgtms
dbgtdi
jtag_trst_b
TRST_B
DBGTCKEN
DBGTMS
DBGTDI
clkctl_dbgrq
dbgen
dbgack
Clock
Gating
nPORESETIN
EDBGRQ
DBGEN
DBGACK
Module
Gated
Clocks
ARM926EJ-S
Core
hclk_en
ARM9
Clock Off
irq_b
firq_b
standbywfi
avic_wakeup_b
ASIC
HCLK
CLK
External
CCM
a9p_clk_off
Figure 16-1. CLKCTL Block Diagram
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16-2
Freescale Semiconductor
ARM9 Platform Clock Control Module (CLKCTL)
16.2
Clock Gating
Table 16-1 shows the hardware clock gating control, based on the gated clocks’ scan enable and module
enable control signals.
Table 16-1. Hardware Clock Gating Control
Scan Enable
Module Enable
Gated Hclk
0
0
OFF
0
1
ON
1
0
ON
1
1
ON
Table 16-2 shows gated clocks and their corresponding control signals.
Table 16-2. Gated Clocks and Their Control Signals
Gated Clock
Module Enable
Scan Enable
Clock
etm_clk
dbgen
any_test_mode
clk_always
etb_clk
etb_clken
any_test_mode
clk_always
etb_hclk
etb_hclken
any_scan_mode
hclk
aape_hclk
aape_hclk_en
any_scan_mode
hclk
aape_reg_hclk
aape_module_en
any_scan_mode
hclk
aipsa_hclk
aipsa_hclk_en || aipsa_active
any_scan_mode
hclk
aipsb_hclk
aipsb_hclk_en || aipsb_active
any_scan_mode
hclk
asic_hclk
asic_hclk_en
any_scan_mode
hclk
asic_reg_hclk
asic_hclk_reg_en
any_scan_mode
hclk
max_reg_hclk
max_module_en
any_scan_mode
hclk
romc_hclk
romc_hclk_en
any_scan_mode
hclk
rompatch_hclk
rompatch_hclk_en
any_scan_mode
hclk
rompatch_reg_hclk
rompatch_hclk_reg_en
any_scan_mode
hclk
mbist_hclk
any_test_mode
any_test_mode
hclk
mbist_clk
any_test_mode
any_test_mode
clk
wrap_hclk
any_scan_mode
any_scan_mode
ipt_test_wrapper_clk_in[1]
wrap_clk
any_scan_mode
any_scan_mode
ipt_test_wrapper_clk_in[0]
tcu_hclk
any_scan_mode
any_scan_mode
hclk
tcu_clk
any_scan_mode
any_scan_mode
clk
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
16-3
ARM9 Platform Clock Control Module (CLKCTL)
In addition to the CLKCTL clock gating, each gated clock in Table 16-2 is controlled by a hardware
enable. Each hardware enable signal may be ORed from several enable source signals (some from outside
CLKCTL and some from within CLKCTL), and any one of the source signals can enable the gated clock.
16.3
Memory Map and Register Definition
This section includes the module memory map and detailed descriptions of all registers. For the base
address of a particular module instantiation, see the system memory map.
Table 16-3 is the module memory map.
Table 16-3. Module Memory Map
Base Address Offset
(Register Abbreviation)
1
Register
Access1
Reset Value
Section/Page
SR/SW
0x0000_0000
16.3.2.1/16-5
0x0000 (GP_CTRL)
General-purpose control register
0x0004 (GP_SER)
Set register
SW
0x0000_0000
16.3.2.2/16-6
0x0008 (GP_CER)
Clear register
SW
0x0000_0000
16.3.2.3/16-7
0x0010 (TAPID)
Tap ID register
SR
0x0000_0000
16.3.2.4/16-7
SR and SW denote supervisor read and supervisor write, respectively.
16.3.1
Register Summary
Table 16-4 is the register summary table.
Table 16-4. Module Register Summary
Offset (and Name
Abbreviation)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
(GP_CTRL)
W
R
GP_CTRL[11:0]
W
R
0x0004
(GP_SER)
W
R
W
R
0x0008
(GP_CER)
write 1 to set adjacent bit in GP_CTRL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
write 1 to clear adjacent bit in GP_CTRL
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16-4
Freescale Semiconductor
ARM9 Platform Clock Control Module (CLKCTL)
Table 16-4. Module Register Summary (continued)
Offset (and Name
Abbreviation)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Tapid[31:16]
W
0x0010 (TAPID)
R
Tapid[15:0]
W
16.3.2
Register Descriptions
The CLKCTL registers are all 32-bit and can only be accessed in supervisor mode. Reads in user mode
will return all zeros, and writes will cause an abort.
Only word-sized accesses are allowed. Half-word and byte accesses cause an abort.
16.3.2.1
General-Purpose Control Register (GP_CTRL)
Offset 0x0000 (GP_CTRL)
R
Access: Supervisor read / write
31
30
29
28
27
26
25
24
23
22
21
20
19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
GP_CTRL
0
[4]
0
0
0
0
0
0
0
0
0
W
Reset
R
0
0
0
0
GP_CTRL
[11]
0
0
0
0
0
GP_CTRL GP_CTRL
[6]
[7]
0
W
Reset
0
0
0
0
0
Figure 16-2. General Purpose Control Register
Table 16-5. General-Purpose Control Register Field Descriptions
Field
31–12
Description
Reserved.
11
This register bit drives the signal which enables the slave port sharing widget (SPSW) in the MAX.
GP_CTRL[11] 0 Slave port sharing disabled
1 Slave port sharing enabled
10–8
7
GP_CTRL[7]
Reserved.
When a9p_clk_off (ARM platform output) is asserted, the CCM starts the process to shut down the ARM
platform clock. If the ARM platform is shut down, no debug activity is available—so by default a9p_clk_off is
not allowed to be asserted if there is debug activity. Setting GP_CTL[7] to 1 overrides this restriction and
allows assertion of a9p_clk_off when debug activity is present.
0 a9p_clk_off signal assertion is not allowed during debug activity (default).
1 a9p_clk_off signal assertion is allowed during debug activity.
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Freescale Semiconductor
16-5
ARM9 Platform Clock Control Module (CLKCTL)
Table 16-5. General-Purpose Control Register Field Descriptions (continued)
6
GP_CTRL[6]
5
Enables/disables clocks to the embedded trace buffer (ETB)
0 ETB clocks disabled
1 ETB clocks enabled
Reserved.
4
GP_CTRL[4]
3–0
Enables/disables the peripheral bus time-out monitors.
0 time-out monitors disabled
1 time-out monitors enabled
Reserved.
WARNING
When slave port sharing is enabled (GP_CNTRL[11]), running locked
accesses to MAX Slave Port 1 and/or MAX Slave Port 0 can cause system
deadlock. If you wish to run locked accesses to this memory region do not
enable slave port sharing.
16.3.2.2
Set Control Register (GP_SER)
Offset 0x0004 (GP_SER)
R
Access: Supervisor write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
write 1 to set adjacent bit in GP_CTRL
0
0
0
0
0
Figure 16-3. Set Control Register
Table 16-6. Set Control Register Field Descriptions
Field
31–12
Description
Reserved.
11–0
To set a bit in the GP_CTRL register, write 1 to the corresponding bit in this field.
GP_SER[11:0]
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ARM9 Platform Clock Control Module (CLKCTL)
16.3.2.3
Clear Control Register (GP_CER)
Offset 0x0008 (GP_CER)
R
Access: Supervisor write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
write 1 to clear corresponding bit in GP_CTRL
W
Reset
0
0
0
0
0
0
Figure 16-4. Clear Control Register
Table 16-7. Clear Control Register Field Descriptions
Field
Description
31–12
Reserved.
11–0
GP_CER[11:0]
16.3.2.4
To clear a bit in the GP_CTRL register, write 1 to the corresponding bit in this field.
Tap ID Register (TAPID)
Offset 0x0010 (TAPID)
31
30
Access: Supervisor read
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
TAPID[31:16]
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
TAPID[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 16-5. TAPID Register
Table 16-8. Tap ID Register Field Descriptions
Field
31–0
TAPID
Description
Tap ID. This is the JTAG ID register, described in the ARM9 platform overview chapter.
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16-7
ARM9 Platform Clock Control Module (CLKCTL)
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Chapter 17
CMOS Sensor Interface (CSI)
This chapter presents the CMOS Sensor Interface (CSI) architecture, operation principles, and
programming model. The CSI enables the chip to connect directly to external CMOS image sensors.
CMOS image sensors are separated into two classes, dumb and smart. Dumb sensors are those that support
only traditional sensor timing (Vertical SYNC and Horizontal SYNC) and output only Bayer and statistics
data, while smart sensors support CCIR656 video decoder formats and perform additional processing of
the image (for example, image compression, image pre-filtering, and various data output formats).
The capabilities of the CSI include:
• Configurable interface logic to support most commonly available CMOS sensors.
• Support for CCIR656 video interface as well as traditional sensor interface.
• 8-bit data port for YCC, YUV, or RGB data input.
• 8-bit/10-bit/16-bit data port for Bayer data input.
• Full control of 8-bit/pixel, 10-bit/pixel or 16-bit/pixel data format to 32-bit receive FIFO packing.
• 128 × 32 FIFO to store received image pixel data.
• Receive FIFO overrun protection mechanism.
• Embedded DMA controllers to transfer data from receive FIFO or statistic FIFO through AHB bus.
• Support 2D DMA transfer from the receive FIFO to the frame buffers in the external memory.
• Support double buffering two frames in the external memory.
• Single interrupt source to interrupt controller from maskable interrupt sources: Start of Frame, End
of Frame, Change of Field, FIFO full, FIFO overrun, DMA transfer done, CCIR error and AHB
bus response error.
• Configurable master clock frequency output to sensor.
• Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the
camera (only for Bayer data and 8-bit/pixel format).
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17-1
CMOS Sensor Interface (CSI)
17.1
CSI Architecture
Figure 17-1 shows the block diagram of the CMOS Sensor Interface.
mma_sdg_sof
mma_line_strobe
mma_rx_fifo_full
mma_rx_fifo_full_level[2:0]
mma_rx_fifo_dataout[31:0]
FBUF PARA Reg
IMAGE PARA Reg
DMASA Reg FB1
IP BUS
DMASA Reg FB2
DMASA Reg SFF
DMA Controller for RxFIFO
DMATS Reg SFF
csi_int_b
Control Reg 3
Master Clock
Generator
Control Reg 1
CSI Status Reg
Interrupt
Control
RxFIFO(128x32)
csi_mclk
csi_pixclk
csi_vsync
Interface signal
Timing Logic
Control
csi_hsync
AHB Arbiter
Dummy Zero
Packing
8/10/16-bit to 32bit Data Packing
csi_d[15:0]
DMA Controller for StatFIFO
ABH lite to AHB Gasket
AHB BUS
16-bit Swap
csi_d[15:0]
Data sampling
Logic
csi_d[9:2]
Statistic Data
Generation
16-bit to 32-bit
Data Packing
CCIR656
Timing Decoder
csi_d[9:2]
StatFIFO(64x32)
Control Reg 2
Figure 17-1. CSI Block Diagram
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CMOS Sensor Interface (CSI)
17.2
CSI Interface Signal Description
Table 17-1 provides a listing of the input and output signals between the CSI module and an external
CMOS sensor.
Table 17-1. Signals Between CSI and Sensor
17.3
CSI Signals
Direction
Description
CSI_VSYNC
Input
Vertical Sync (Start Of Frame)
CSI_HSYNC
Input
Horizontal Sync (Blank Signal)
CSI_D[15:0]
Input
16-bit Sensor Data Bus (Bayer, YUV, YCrCb, RGB)
CSI_MCLK
Output
CSI_PIXCLK
Input
Sensor Master Clock
Pixel Clock
Principles of Operation
This section describes the modes of operation of the sensor interface.
The CSI is designed to support generic sensor interface timing as well as CCIR656 video interface timing.
Traditional CMOS sensors typically use VSYNC, HSYNC, and PIXCLK signals to output Bayer or YUV
data. Smart CMOS sensors, that come with on-chip imaging processing, usually support video mode
transfer. They use an embedded timing codec to replace the SOF and BLANK signal. The timing codec is
defined by the CCIR656 standard.
The CSI can support to connect with the sensor as below, one 8-bit sensor or one 10-bit sensor or one 16-bit
sensor. To connect with one 8-bit sensor, the data interfaces should be connected to DATA[9:2]. To connect
with one 10-bit sensor, the data interfaces should be connected to DATA[9:0]. To connect with one 16-bit
sensor, the data interfaces should be connected to DATA[15:0].
17.3.1
Data Transfer With The Embedded DMA Controllers
The CSI has two embedded DMA controllers, one for the receive FIFO and the other for the statistic FIFO.
The CSI supports 2D DMA transfer from the receive FIFO to the frame buffers in the external memory
and linear DMA transfer from the statistic FIFO.
To transfer data from the RxFIFO to the external memory, the user needs to set the start address in the
frame buffer registers for where the data is to be stored. Additionally the image size parameters need to be
set in the CSI registers for the DMA controller to determine how much data needs to be transferred to
trigger a DMA complete interrupt after each frame. Users can have two hardware controlled frame buffers
in the external memory. Each one stores a single frame image coming from the sensor. Initially the
embedded DMA controller writes the frame to buffer1 first and then the second frame to buffer2. These
two frame buffers are written in a circular fashion. When an entire frame is transferred, that triggers a DMA
complete interrupt and the start address pointer for the other buffer is loaded into the DMA engine for the
next frame. The start addresses should be word aligned and should be set in the CSIDMASA-FB1 and
CSIDMASA-FB2 registers. In the CSIFBUF_PARA register, user should set the stride of the frame buffer
to show how many words to skip before starting to write the next row of the image. In the
CSIIMAG_PARA register, user should set the width and height of the image coming from the sensor. This
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17-3
CMOS Sensor Interface (CSI)
parameter is essential for the DMA engine to determine how much data needs to be transferred for a
complete frame. The RxFF_LEVEL and DMA_REQ_EN_RFF bits in the CSICR3 registers also need to
be set before the data transfer starts, to enable when DMA transfers occur.
When the number of the words of data in the RxFIFO reaches the water-mark trigger level, a DMA request
is sent from the RxFIFO to the embedded DMA controller and a single burst of data is read out from the
RxFIFO and written through the AHB bus into the external frame buffers. No additional bursts of data are
transferred until the RxFIFO reaches the water-mark trigger level again. The DMA burst type for the
transfer can be INCR4, INCR8 and INCR16 by setting the DMA_BURST_TYPE_RFF bits in the CSICR2
register. After all data of a complete frame is transferred, the DMA_TSF_DONE_FB1 or
DMA_TSF_DONE_FB2 bit is set in the CSISR register and the interrupt is triggered if the corresponding
enable bit is set in the CSICR1 register.
The DMA_REFLASH_RFF bit in CSICR3 is used to activate or re-start the embedded DMA controller.
Setting the reflash bit resets the DMA engine by reloading the start address of CSIDMASA_FB1 and
reloading the image size parameters from the CSIIMAG_PARA register. If the image parameters from the
sensor ever change these registers should be updated accordingly and the DMA_REFLASH_RFF bit
should be set to re-initialize the DMA engine.
The RxFIFO has an overrun protection mechanism in case the RxFIFO is overrun during data transfer.
Overrun occurs if the RxFIFO is full and more data needs to be received during the data transfer. If this
occurs the RxFIFO is over-written continuously and all 128 words data in the RxFIFO before overrun
occurred, are discarded and the corresponding 128 words in the external memory space for the frame buffer
keep the previous values.
Similarly to transfer data from the statistic FIFO to the external memory, user need to set the start address
of the external memory for where the transferred data is to be stored and the total transfer size. The start
address and the transfer sizes are all word aligned and should be set in the CSIDMASA-STATFIFO and
CSIDMATS-STATFIFO registers. The STATFF_LEVEL and DMA_REQ_EN_SFF bits in the CSICR3
registers also need to be set before the data transfer starts. When the number of words of data in the
STATFIFO reaches the water-mark trigger level, a DMA request is sent from the STATFIFO to the
embedded DMA controller and a single burst of data is read out from the STATFIFO and written through
AHB bus into the external memory. The burst type for the transfer can be INCR4, INCR8 and INCR16 by
setting the DMA_BURST_TYPE_SFF bits in the CSICR2 register. After all expected data (defined by the
total transfer sizes) are transferred, the DMA_TSF_DONE_SFF bit is set in the CSISR register and an
interrupt is triggered if the SFF_DMA_DONE_INTEN is enabled in the CSICR1 register. The
DMA_REFLASH_SFF bit in CSICR3 can be used to activate or re-start the embedded DMA controller.
17.3.2
Gated Clock Mode
VSYNC, HSYNC, and PIXCLK signals are used in gated clock mode.
A frame starts with a rising edge on VSYNC, then HSYNC goes to HIGH and holds for the entire line.
The Pixel clock is valid as long as HSYNC is HIGH. Data is latched at the rising edge of the valid pixel
clocks. HSYNC goes to LOW at the end of line. Pixel clocks then become invalid and CSI stops receiving
data from the stream. For the next line the HSYNC timing repeats. For the next frame the VSYNC timing
repeats.
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CMOS Sensor Interface (CSI)
17.3.3
Non-Gated Clock Mode
In non-gated clock mode, only the VSYNC and PIXCLK signals are used; the HSYNC signal is ignored.
Figure 17-2 is the timing diagram for non-gated clock mode.
Start of Frame
nth Frame
(n+1)th Frame
VSYNC
PIXCLK
D(15:0)
invalid
invalid
Figure 17-2. Non-Gated Clock Mode Timing Diagram
The overall timing of non-gated mode is the same as the gated-clock mode, except for the HSYNC signal.
HSYNC signal is ignored by the CSI. All incoming pixel clocks are valid and cause data to be latched into
RxFIFO. The PIXCLK signal is inactive (states low) until valid data is ready to be transmitted over the bus.
Figure 17-2 shows the timing using a typical sensor, other sensors may have slightly different timing from
that shown. The CSI should be programed to support rising/falling-edge triggered VSYNC;
active-high/low HSYNC; and rising/falling-edge triggered PIXCLK.
17.3.4
CCIR656 Interlace Mode
In CCIR656 mode, only the PIXCLK and DATA[9:2] signals are used. The start of frame and blank signals
are replaced by a timing codec which is embedded in the data stream. Each active line starts with a SAV
code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code.
The CSI decodes and filters out the timing-coding from the data stream, thus recovering VSYNC and
HSYNC signals for internal use, such as statistical block control. Data is forwarded to the data receive and
packing block in a sequential manner without re-ordering—that is, field 1 followed by field 2. The fields
must be re-ordered in software to get back the original image.
Change Of Field interrupt (COF) is triggered upon every field change. The interrupt service routine reads
the status register to check for the current field.
According to the CCIR656 specification, the image must be in 625/50 PAL or 525/60 NTSC format. In
addition, the image is interlaced into odd and even fields, with vertical and horizontal blank data being
filled into certain lines. Data must be in YCC422 format, each pixel contains 2 bytes, either Y + Cr or Y
+ Cb. These requirements are set for TV systems. The CSI module supports PAL and NTSC format only.
Figure 17-3 shows the frame structure in PAL system, showing vertical blanking and horizontal blanking.
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17-5
CMOS Sensor Interface (CSI)
EAV
(H,V,F)
(1,1,1)
SOF
SAV
(H,V,F)
Blanking
Field 2
(F = 1)
(0,1,1)
(1,1,0)
(0,1,0)
(1,0,0)
(0,0,0)
Active Video 1
Field 1
(F = 0)
SOV1
(1,1,0)
(0,1,0)
(1,1,1)
(0,1,1)
(1,0,1)
Field 2
(F = 1)
(0,0,1)
Active Video 2
SOV2
4
4
268
1440 Bytes
Figure 17-3. CCIR656 Interlace Mode (PAL)
Figure 17-4 shows the general timing for a single line, showing SAV and EAV.
Start of Line
Next Line
Start of Active Pixel
F 0 0 X 8 1 8 1
F 0 0 Y 0 0 0 0
8 1 8 1 F 0 0 X C Y C Y
0 0 0 0 F 0 0 Y B
R
H-Blanking
EAV
C Y C Y
B
R
Pixel Data
SAV
Figure 17-4. CCIR656 General Line Timing
The coding tables recommended by the CCIR656 specification are shown in Table 17-2, Table 17-3 and
Table 17-4. It is used in the CCIR656 mode to decode the video stream. An interrupt is generated for SOF,
which is decoded from the embedded timing codec.
.
Table 17-2. Coding for SAV and EAV
Data Bit
Number
1st Byte
0xFF
2nd Byte
0x00
3rd Byte
0x00
4th Byte
0xXY
7 (MSB)
1
0
0
1
6
1
0
0
F
5
1
0
0
V
4
1
0
0
H
3
1
0
0
P3
2
1
0
0
P2
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CMOS Sensor Interface (CSI)
Table 17-2. Coding for SAV and EAV (continued)
Data Bit
Number
1st Byte
0xFF
2nd Byte
0x00
3rd Byte
0x00
4th Byte
0xXY
1
1
0
0
P1
0
1
0
0
P0
Table 17-3. Coding for Protection Bits
F
V
H
P3
P2
P1
P0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
1
0
0
0
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
1
1
0
0
0
1
Table 17-4. Representations by F-Bit
17.3.5
F-Bit
Representations
0
ODD FIELD (FIELD 1)
1
EVEN FIELD (FIELD 2)
CCIR656 Progressive Mode
For a CMOS camera system of VGA or CIF resolution, strict adherence to the interlace requirements stated
in the CIR standard is not required. The image is considered to have only 1 active field which is scanned
in a progressive manner. This active field is regarded as field 1 and the F-bit in the timing codec is ignored
by the decoder. Most sensors support CCIR timing in this mode (progressive) by default.
Figure 17-5 shows the typical flow of progressive mode.
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17-7
CMOS Sensor Interface (CSI)
EAV
EAV_B
Blanking
SAV
SAV_B
Blanking
EAV_B
Blanking
SAV_B
Blanking
EAV_B
Blanking
SAV_B
Blanking
EAV_A
Blanking
SAV_A
Data
EAV_A
Blanking
SAV_A
Data
EAV_A
Blanking
SAV_A
Data
Single
Line
Field 1
(F = 0)
SOF
4
Undefined
4
Configurable
Figure 17-5. CCIR656 Progressive Mode (General Case)
An interrupt is generated for SOF but not for COF. In the general case, when SOF information is retrieved
from the embedded coding, it is known as internal VSYNC mode. In other cases, when the VSYNC signal
is provided by the sensor, it is known as external VSYNC mode. The CSI can be operated in internal or
external VSYNC mode.
17.3.6
Error Correction for CCIR656 Coding
According to the algorithm for CCIR coding, protection bits in the SAV and EAV are encoded in the way
that allows a 1-bit error to be corrected, or a 2-bit error to be detected by the decoder. This feature is
supported by the CCIR decoder in CSI, for interlace mode only.
For the 1-bit error case, users can select the error to be corrected automatically, or simply shown as a status
flag instead. For the 2-bit error case, because the decoder is unable to make a correction, the error would
be shown as a status flag only.
An interrupt can be generated upon the detection of an error. This signal can be enabled or disabled without
affecting the operation of the status bit.
17.4
Interrupt Generation
This section describes CSI events that generate interrupts.
17.4.1
Start Of Frame Interrupt (SOF_INT)
The source of an SOF interrupt is dependent on the mode of operation.
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CMOS Sensor Interface (CSI)
In traditional mode, VSYNC signal is taken from sensor and SOF_INT is generated at the rising or falling
edge (programmable) of VSYNC.
In CCIR interlace mode, the SOF interrupt information is retrieved from the embedded coding and
SOF_INT is generated.
In CCIR progressive mode, there are two sources of an SOF interrupt:
• In internal VSYNC mode, SOF is retrieved from the embedded coding.
• In external VSYNC mode, VSYNC is taken from the sensor and SOF is generated at the rising edge
of VSYNC.
17.4.2
End Of Frame Interrupt (EOF_INT)
An EOF interrupt is generated when the frame ends and the complete frame data in RXFIFO is read.
The EOF event triggering works with the RX count register (CSIRXCNT). Software sets the RX count
register to the frame size (in words). The CSI RX logic then counts the number of pixel data being received
and compares it with the RX count. If the preset value is reached, then an EOF interrupt is generated. If an
SOF event is detected before this happens, then the EOF interrupt is not generated.
Users can trigger an EOF interrupt anywhere while the current frame is being transferred by setting the RX
count register to a value smaller than the actual frame size. However this would not be a true end of frame.
17.4.3
Change Of Field Interrupt (COF_INT)
The Change of Field interrupt is only valid in CCIR Interlace mode. The COF interrupt is generated when
the field toggles, either from field 1 to field 2, or field 2 to field 1.
Software should first check on COF_INT bit in the CSI Status Register (CSISTAT), before checking that
F1_INT or F2_INT is turned on.
In PAL systems, the field changes at the beginning of the frame and coincides with SOF. For the first field,
a COF interrupt is not generated, only an SOF is generated. The COF interrupt is generated for the second
field.
17.4.4
CCIR Error Interrupt (ECC_INT)
The CCIR Error Interrupt is only valid for CCIR Interlace mode. An ECC interrupt is generated when an
error is found on the SAV or EAV codes in the incoming stream. When this happens, the ECC_INT status
bit is set.
17.4.5
RxFIFO Full Interrupt (RxFF_INT)
A RxFIFO full interrupt is generated when the number of data in RXFIFO reaches the water mark defined
by RxFF_LEVEL in CSICR3.
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CMOS Sensor Interface (CSI)
17.4.6
Statistic FIFO Full Interrupt (STATFF_INT)
A StatFIFO full interrupt is generated when the number of data in STATFIFO reaches the water mark
defined by STATFF_LEVEL in CSICR3.
17.4.7
RxFIFO Overrun Interrupt (RFF_OR_INT)
A RxFIFO Overrun interrupt is generated when the RxFIFO has 128 words data and more data is being
written in.
17.4.8
Statistic FIFO Overrun Interrupt (SFF_OR_INT)
A StatFIFO Overrun interrupt is generated when the STATFIFO has 64 words data and more data is being
written in.
17.4.9
Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1)
A DMA transfer done interrupt of frame buffer1 is generated when one frame of data are transferred from
RxFIFO to the frame buffer1 in the external memory.
17.4.10 Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2)
A DMA transfer done interrupt of frame buffer2 is generated when one frame of data are transferred from
RxFIFO to the frame buffer2 in the external memory.
17.4.11 Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF)
A StatFIFO DMA transfer done interrupt is generated when all the data are transferred from StatFIFO to
the external memory. The transfer size is defined in the STATFIFO DMA transfer size register.
17.4.12 AHB Bus Response Error Interrupt (HRESP_ERR_INT)
An AHB Bus response error interrupt is generated when an hresponse error is detected on AHB bus.
17.5
Data Packing Style
Owing to different port sizes at different stages of the image capture path, the endianess of data is
important. To enable flexible packing of image data, the CSI module provides data swapping through the
PACK_DIR and the SWAP16_EN bits in CSI Control Register 1 (CSICR1) which enables data swapping
before it is presented to the FIFOs. The CSI module accepts 8-bit, 10-bit or 16-bit data format from the
sensor by configuring PIXEL_BIT bit in CSI Control Register 1 (CSICR1) and 16BIT_SENSOR bit in
CSI Control Register3 (CSICR3).
For 10-bit per pixel data format, each pixel is expanded to 16 bits by adding 6 bits zero from MSB. Then
data is packed from 8-bit or 16-bit to 32-bit according to the setting of PACK_DIR bit, and then put into
the RX FIFO according to the setting of the SWAP16_EN bit.
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CMOS Sensor Interface (CSI)
CSI can support 16-bit data format. The input data is packed from 16-bit to 32-bit according to the setting
of PACK_DIR bit, and then put into the RX FIFO according to the setting of the SWAP16_EN bit.
17.5.1
RX FIFO Path
Bayer data is a type of raw data from the image sensor. This byte-wide data must be converted to the RGB
space or YUV space by software. The data path for Bayer data is from the CSI to memory. If the system
is in little endian, then the PACK_DIR bit should be set to 0. For 8-bit/pixel data format from sensor, it is
packed to 32-bit as P3.P2.P1.P0, where P0 is the pixel coming in time slot 0 (first data), while P3 is the
pixel coming in time slot 3 (last data). When the data is addressed as bytes by software, P0 goes out first,
and ends up with P3. For 10-bit/pixel data format from sensor, it is packed to 32-bit as
000000.P1.000000.P0, where P0 is the 10-bit data coming in time slot 0 (first pixel), while P1 is the 10-bit
data coming in time slot 1 (second pixel). For 16-bit data format from sensor, it is packed to 32-bit as
P1.P0, where P0 is the 16-bit data coming in time slot 0, while P1 is the 16-bit data coming in time slot 1.
17.5.1.1
RGB565 Data
RGB565 data is processed data from the image sensor, which can be put directly into the display buffer.
The data is 16 bits wide. The data path is from CSI to memory, memory to LCDC. On the sensor side, data
must be output as P0 first, followed by P1, and so on. Within each pixel, either MSB or LSB will come out
first. This is controlled by the endian style of the sensor. Data is 16 bits wide with the MSB labeled RG,
and the LSB labeled GB. So for P0, it is represented as RG0, GB0, and so on for P1.
CSI receives data in one of the following sequence:
• RG0, GB0, RG1, GB1, while RG0 comes out at time slot 0 (first data), and GB1 comes out at time
slot 3 (last data), or
• GB0, RG0, GB1, RG1.
Using the first sequence as an example, and assuming the system is running in little endian the data is
presented as:
• 8-bit data from sensor: RG0, GB0, RG1, GB1, …
• 32-bit data before CSI RX FIFO (PACK_DIR bit = 1): RG0GB0RG1GB1
• 32-bit data in CSI RX FIFO (SWAP16_EN bit enabled): RG1GB1RG0GB0
• 32-bit transfer to system memory: RG1GB1RG0GB0
• 16-bit read by LCDC: RG0GB0, RG1GB1
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CMOS Sensor Interface (CSI)
17.5.1.2
RGB888 Data
This is another kind of processed data from image sensor, which can be used for further image processing
directly. Each of the data consist of 8-bit Red, 8-bit Green, and 8-bit Blue data. An example of a possible
timing scheme is shown in Figure 17-6.
Input Data Timing
Pixclk
FORMAT 1
Data[9:2]
R0
G0
B0
R1
G1
B1
FORMAT 2
Data[9:2]
B0
G0
R0
B1
G1
R1
Figure 17-6. Sample Timing Diagram for RGB888 Data
To improve the data transfer, an optional dummy byte packing scheme is provided. For every group of 3
bytes data, a dummy zero is packed to form a 32-bit word as shown in Figure 17-7. The dummy zero is
always packed at the LSB position.
FORMAT 1 with Pack direction = ‘1’ (MSB first)
FORMAT 2 with Pack Direction = ‘0’ (LSB first)
Output
Data Format
R0
G0
B0
Zero
R1
G1
B1
Zero
Figure 17-7. Optional Dummy Byte Packing Scheme
17.5.2
STAT FIFO Path
Statistics only works for Bayer data in 8-bit per pixel format. It generates 16-bit statistical output from the
8-bit Bayer input (DATA[9:2]). The outputs are Sum of Green (G), Sum of Red (R), Sum of Blue (B), and
Auto Focus (F). Each output is 16-bits wide.
The settings of PACK_DIR and SWAP16_EN bits in the CSICR1 register have no effect on the input path.
The PACK_DIR only controls how the 16-bit stat output is packed into the 32-bit STAT FIFO.
When the PACK_DIR bit = 1, the stat data is packed as:
First 32-bit: RG
Second 32-bit: BF
…
When the PACK_DIR bit = 0, the stat data is packed as:
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CMOS Sensor Interface (CSI)
First 32-bit GR
Second 32-bit: FB
…
17.6
Memory Map and Register Definition
All the 32-bit registers of the CSI module are summarized in Table 17-5. Table 17-7 summarizes the
registers and offset addresses.
17.6.1
CSI Memory Map
Table 17-5 shows the CSI memory map.
Table 17-5. CSI Memory Map
Address
Use
Access
Reset Value
Section/Page
0xBASE_0000 (CSICR1)
CSI Control Register 1
R/W
0x4000_0800
17.6.3/17-17
0xBASE_0004 (CSICR2)
CSI Control Register 2
R/W
0x0000_0000
17.6.4/17-21
0xBASE_0008 (CSICR3)
CSI Control Register 3
R/W
0x0000_0000
17.6.5/17-22
0xBASE_000C (CSISTATFIFO)
CSI Statistic FIFO Register
R
0x0000_0000
17.6.6/17-24
0xBASE_0010 (CSIRFIFO)
CSI RX FIFO Register
R
0x0000_0000
17.6.7/17-25
0xBASE_0014 (CSIRXCNT)
CSI RX Count Register
R/W
0x0000_9600
17.6.8/17-25
0xBASE_0018 (CSISR)
CSI Status Register
R/W
0x0000_4000
17.6.9/17-26
0xBASE_0020
(CSIDMASA-STATFIFO)
CSI DMA Start Address Register - for
STATFIFO
R/W
0x0000_0000
17.6.10/17-29
0xBASE_0024
(CSIDMATS-STATFIFO)
CSI DMA Transfer Size Register - for
STATFIFO
R/W
0x0000_0000
17.6.11/17-30
0xBASE_0028 (CSIDMASA-FB1)
CSI DMA Start Address Register - for
Frame Buffer1
R/W
0x0000_0000
17.6.12/17-30
0xBASE_002C (CSIDMASA-FB2)
CSI DMA Transfer Size Register - for
Frame Buffer2
R/W
0x0000_0000
17.6.13/17-31
0xBASE_0030 (CSIFBUF_PARA)
CSI Frame Buffer Parameter Register
R/W
0x0000_0000
17.6.14/17-32
0xBASE_0034 (CSIIMAG_PARA)
CSI Image Parameter Register
R/W
0x0000_0000
17.6.15/17-32
17.6.2
Register Summary
Figure 17-8 shows the key to the register fields, and Table 17-6 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT Writebit
only bit
only bit
Write 1 BIT Self-clear 0
to clear
bit
BIT
w1c
BIT
N/A
Figure 17-8. Key to Register Fields
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CMOS Sensor Interface (CSI)
Table 17-6. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing
bit
Writing a one has some effect on the module, but it always reads as zero.
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
Table 17-7 shows the CSI register summary.
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
CCIR_MODE
COF_INT_EN
SF_OR_INTEN
RF_OR_INTEN
HSYNC_POL
CCIR_EN
MCLKEN
FCC
W
MCLKDIV
R
PrP_IF_EN
EXT_VSYNC
W
EOF_INT_EN
R
SOF_INTEN
19
PIXEL_BIT
20
SOF_POL
21
REDGE
22
RxFF_INTEN
23
INV_PCLK
24
FB1_DMA_DONE_INTEN
25
INV_DATA
26
FB2_DMA_DONE_INTEN
27
GCLK_MODE
28
STATFF_INTEN
29
CLR_RxFIFO
30
SWAP16_EN
0xBASE_0000
(CSICR1)
31
PACK_DIR
Name
CLR_STATFIFO SFF_DMA_DONE_INTEN
Table 17-7. CSI Register Summary
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CMOS Sensor Interface (CSI)
Table 17-7. CSI Register Summary (continued)
Name
0xBASE_0004
(CSICR2)
R
W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
DMA_BUR DMA_BUR
ST_TYPE ST_TYPE
_RFF
_SFF
0
DR
M
SCE
AFS
BTS
LVRM
R
VSC
HSC
W
R
0xBASE_000C
(CSISTATFIFO)
R
ECC_AUTO_EN
ECC_INT_EN
ZERO_PACK_EN
16BIT_SENSOR
RxFF_LEVEL
DMA_REFLASH_SFF
W
STATFF_LEVEL
0
DMA_REQ_EN_SFF
0
DMA_REQ_EN_RFF
0
DMA_REFLASH_RFF
R
HRESP_ERR_EN
FRMCNT
W
FRMCNT_RST
0xBASE_0008
(CSICR3)
STAT
W
R
STAT
W
0xBASE_0010
(CSIRFIFO)
R
IMAGE
W
R
IMAGE
W
0xBASE_0014
(CSIRXCNT)
R
0
0
0
0
0
0
0
0
0
0
RXCNT
W
R
RXCNT
W
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CMOS Sensor Interface (CSI)
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DMA_TSF_DONE_FB2
DMA_TSF_DONE_FB1
RxFF_INT
w1c
w1c
0
0
W
0xBASE_0020
(CSIDMASA-STA
TFIFO)
COF_INT
F1_INT
F2_INT
R
0
0
0
w1c
w1c
HRESP_ERR_INT
W
RFF_OR_INT
R
0
0
w1c
w1c
0
0
0
w1c
SOF_INT
27
w1c
w1c
DRDY
28
EOF_INT
29
ECC_INT
30
SFF_OR_INT
0xBASE_0018
(CSISR)
31
STATFF_INT
Name
DMA_TSF_DONE_SFF
Table 17-7. CSI Register Summary (continued)
w1c
R
DMA_START_ADDR_SFF[31:16]
W
R
0
0
0
0
0
0
0
0
DMA_START_ADDR_SFF[15:2]
W
0xBASE_0024
(CSIDMATS-STAT
FIFO)
R
DMA_TSF_SIZE_SFF[31:16]
W
R
DMA_TSF_SIZE_SFF[15:0]
W
0xBASE_0028
(CSIDMASA-FB1)
R
DMA_START_ADDR_FB1[31:16]
W
R
DMA_START_ADDR_FB1[15:2]
W
0xBASE_002C
(CSIDMASA-FB2)
R
DMA_START_ADDR_FB2[31:16]
W
R
DMA_START_ADDR_FB2[15:2]
W
0xBASE_0030
(CSIFBUF_PARA)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
FBUF_STRIDE[15:0]
W
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CMOS Sensor Interface (CSI)
Table 17-7. CSI Register Summary (continued)
Name
0xBASE_0034
(CSIIMAG_PARA)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IMAGE_WIDTH[15:0]
W
R
IMAGE_HEIGHT[15:0]
W
17.6.3
CSI Control Register 1 (CSICR1)
This register, shown in Figure 17-9 and Table 17-8, controls the sensor interface timing and interrupt
generation. The interrupt enable bits in this register control the interrupt signals and the status bits. That
means status bits function only when the corresponding interrupt bits are enabled.
0xBASE_0000 (CSICR1)
W
STATFF_INTEN
FB2_DMA_DONE_INTEN
FB1_DMA_DONE_INTEN
RxFF_INTEN
SOF_POL
SOF_INTEN
Reset
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GCLK_MODE
INV_DATA
INV_PCLK
REDGE
PIXEL_BIT
0
CLR_RxFIFO
16
SFF_DMA_DONE_INTEN
17
CLR_STATFIFO
18
PACK_DIR
19
RF_OR_INTEN
20
FCC
21
SF_OR_INTEN
22
MCLKEN
23
COF_INT_EN
24
CCIR_EN
25
CCIR_MODE
26
HSYNC_POL
27
PrP_IF_EN
28
EOF_INT_EN
29
EXT_VSYNC
30
SWAP16_EN
31
Access: User read/write
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
R
MCLKDIV
R
W
Reset
Figure 17-9. CSPI Control Register 1 (CSICR1)
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CMOS Sensor Interface (CSI)
Table 17-8. CSI Control Register 1 Field Descriptions
Field
Description
31
SWAP16_EN
SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit
first (according to the setting of PACK_DIR and then swapped as 16-bit words before putting into the RX
FIFO. The action of the bit only affects the RX FIFO and has no affect on the STAT FIFO.
Note: Example of swapping enabled:
Data input to FIFO = 0x11223344
Data in RX FIFO = 0x 33441122
Note: Example of swapping disabled:
Data input to FIFO = 0x11223344
Data in RX FIFO = 0x11223344
0 Disable swapping
1 Enable swapping
30
EXT_VSYNC
External VSYNC Enable. This bit controls the operational VSYNC mode.
Note: This only works when the CSI is in CCIR progressive mode.
0 Internal VSYNC mode
1 External VSYNC mode
29
EOF_INT_EN
End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt.
0 EOF interrupt is disabled.
1 EOF interrupt is generated when RX count value is reached.
28
PrP_IF_EN
CSI—PrP Interface Enable. This bit controls the CSI to PrP bus. When enabled the RxFIFO is detached from
the AHB bus and connected to PrP. All CPU reads or DMA accesses to the RxFIFO register are ignored. All
CSI interrupts are also masked.
0 CSI to PrP bus is disabled
1 CSI to PrP bus is enabled
27
CCIR_MODE
CCIR Mode Select. This bit controls the CCIR mode of operation.
This bit only works in CCIR interface mode.
0 Progressive mode is selected
1 Interlace mode is selected
26
COF_INT_EN
Change Of Image Field (COF) Interrupt Enable. This bit enables the COF interrupt.
This bit works only in CCIR interlace mode which is when CCIR_EN = 1 and CCIR_MODE = 1.
0 COF interrupt is disabled
1 COF interrupt is enabled
25
STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt.
SF_OR_INTEN 0 STATFIFO overrun interrupt is disabled
1 STATFIFO overrun interrupt is enabled
24
RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt.
RF_OR_INTEN 0 RxFIFO overrun interrupt is disabled
1 RxFIFO overrun interrupt is enabled
23
22
SFF_DMA_DO
NE_INTEN
Reserved.
STATFIFO DMA Transfer Done Interrupt Enable. This bit enables the interrupt of STATFIFO DMA transfer
done.
0 STATFIFO DMA Transfer Done interrupt disable
1 STATFIFO DMA Transfer Done interrupt enable
21
STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt.
STATFF_INTEN 0 STATFIFO full interrupt disable
1 STATFIFO full interrupt enable
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CMOS Sensor Interface (CSI)
Table 17-8. CSI Control Register 1 Field Descriptions (continued)
Field
Description
Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA
20
FB2_DMA_DON transfer done.
0 Frame Buffer2 DMA Transfer Done interrupt disable
E_INTEN
1 Frame Buffer2 DMA Transfer Done interrupt enable
19
Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA
FB1_DMA_DON transfer done.
E_INTEN
0 Frame Buffer1 DMA Transfer Done interrupt disable
1 Frame Buffer1 DMA Transfer Done interrupt enable
18
RXFF_INTEN
17
SOF_POL
RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt.
0 RxFIFO full interrupt disable
1 RxFIFO full interrupt enable
SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt.
0 SOF interrupt is generated on SOF falling edge
1 SOF interrupt is generated on SOF rising edge
16
SOF_INTEN
Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt.
0 SOF interrupt disable
1 SOF interrupt enable
15–12
MCLKDIV
Sensor Master Clock (MCLK) Divider. This field contains the divisor MCLK.
The MCLK is derived from the PERCLK.
0000 Divided by 1
0001 Divided by 2
0010 Divided by 4
0011 Divided by 6
0100 Divided by 8
0101 Divided by 10
0110 Divided by 12
0111 Divided by 14
1000 Divided by 16
1001 Divided by 18
1010 Divided by 20
1011 Divided by 22
1100 Divided by 24
1101 Divided by 26
1110 Divided by 28
1111 Divided by 30
11
HSYNC_POL
HSYNC Polarity Select. This bit controls the polarity of HSYNC.
Note: This bit only works in gated-clock—that is, GCLK_MODE = 1 and CCIR_EN = 0.
0 HSYNC is active low
1 HSYNC is active high
10
CCIR_EN
CCIR656 Interface Enable. This bit selects the type of interface used. When the CCIR656 timing decoder is
enabled, it replaces the function of timing interface logic.
0 Traditional interface is selected. Timing interface logic is used to latch data.
1 CCIR656 interface is selected.
9
MCLKEN
Sensor Master Clock (MCLK) Enable. This bit enables or disables the MCLK input to the sensor.
0 MCLK disable
1 MCLK enable
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CMOS Sensor Interface (CSI)
Table 17-8. CSI Control Register 1 Field Descriptions (continued)
Field
Description
8
FCC
FIFO Clear Control. This bit determines how the RXFIFO and STATFIFO are cleared. When Synchronous
FIFO clear is selected the RXFIFO and STATFIFO are cleared, and STAT block is reset, on every SOF. FIFOs
and STAT block restarts immediately after reset. For information on the operation when Asynchronous FIFO
clear is selected, refer to the descriptions for the CLR_RXFIFO and CLR_STATFIFO bits.
0 Asynchronous FIFO clear is selected.
1 Synchronous FIFO clear is selected.
Note: FCC should only be used when CSI DMA burst size and FIFO water-mark fill level match. If they do
not match and FCC bit is set this may cause corrupted images.
7
PACK_DIR
Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO, and how
16-bit statistical data is packed into 32-bit STAT FIFO.
0 Pack from LSB first.
For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO.
For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
1 Pack from MSB first.
For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO.
For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
6
Asynchronous STATFIFO Clear. This bit clears the STATFIFO and Reset STAT block.
CLR_STATFIFO
Note: This bit works only in async FIFO clear mode—that is, FCC = 0. Otherwise this bit is ignored.
Writing 1 will clear STATFIFO and reset STAT block immediately, STATFIFO and STAT block then wait and
restart after the arrival of next SOF.
The bit is restored to 0 automatically after finish. Normally reads 0.
5
CLR_RXFIFO
Asynchronous RXFIFO Clear. This bit clears the RXFIFO.
This bit works only in async FIFO clear mode—that is, FCC = 0. Otherwise this bit is ignored.
Writing 1 clears the RXFIFO immediately, RXFIFO restarts immediately after that.
The bit is restore to 0 automatically after finish. Normally reads 0.
4
GCLK_MODE
Gated Clock Mode Enable. Controls if CSI is working in gated or non-gated mode.
Note: This bit works only in traditional mode—that is, CCIR_EN = 0. Otherwise this bit is ignored.
0 Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
1 Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
3
INV_DATA
Invert Data Input. This bit enables or disables internal inverters on the data lines.
0 CSI_D[7:0] data lines are directly applied to internal circuitry
1 CSI_D[7:0] data lines are inverted before applied to internal circuitry
2
INV_PCLK
Invert Pixel Clock Input. This bit determines if the Pixel Clock (CSI_PIXCLK) is inverted before it is applied to
the CSI module.
0 CSI_PIXCLK is directly applied to internal circuitry
1 CSI_PIXCLK is inverted before applied to internal circuitry
1
REDGE
0
PIXEL_BIT
Valid Pixel Clock Edge Select. Selects which edge of the CSI_PIXCLK is used to latch the pixel data.
0 Pixel data is latched at the falling edge of CSI_PIXCLK
1 Pixel data is latched at the rising edge of CSI_PIXCLK
Pixel Bit. This bit indicates the bayer data width for each pixel. This bit should be configured before activating
or re-starting the embedded DMA controller.
0 8-bit data for each pixel
1 10-bit data for each pixel
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Freescale Semiconductor
CMOS Sensor Interface (CSI)
17.6.4
CSI Control Register 2 (CSICR2)
This register, shown in Figure 17-10 and Table 17-9, provides the statistic block with data about which live
view resolution is being used, and the starting sensor pixel of the Bayer pattern. It also contains the
horizontal and vertical count used to determine the number of pixels to skip between the 64 × 64 blocks of
statistics when generating statistics on live view image that are greater than 512 × 384.
0xBASE_0004 (CSICR2)
31
30
29
Access: User read/write
28
27
R DMA_BURST DMA_BURST
W _TYPE_RFF _TYPE_SFF
Reset
26
25
24
23
22
21
0
0
0
DRM
AFS
20
SCE
19
18
BTS
17
16
LVRM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
VSC
HSC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-10. CSI Control Register 2 (CSICR2)
Table 17-9. CSI Control Register 2 Description
Field
Description
31–30
Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO.
DMA_BURST_TY 00 INCR8
PE_RFF
01 INCR4
10 INCR8
11 INCR16
Note: The optimal setting is INCR8 so that the CSI burst size matches the ESDRAMC burst size.
29–28
Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO.
DMA_BURST_TY 00 INCR8
PE_SFF
01 INCR4
10 INCR8
11 INCR16
Note: The optimal setting is INCR8 so that the CSI burst size matches the ESDRAMC burst size.
27
Reserved.
26
DRM
Double Resolution Mode. Controls size of statistics grid.
0 Stats grid of 8 × 6
1 Stats grid of 8 × 12
25–24
AFS
Auto Focus Spread. Selects which green pixels are used for auto-focus.
00 Abs Diff on consecutive green pixels
01 Abs Diff on every third green pixels
1x Abs Diff on every four green pixels
23
SCE
Skip Count Enable. Enables or disables the skip count feature.
0 Skip count disable
1 Skip count enable
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
17-21
CMOS Sensor Interface (CSI)
Table 17-9. CSI Control Register 2 Description (continued)
Field
Description
22–21
Reserved.
20–19
BTS
Bayer Tile Start. Controls the Bayer pattern starting point.
00 GR
01 RG
10 BG
11 GB
18–16
LVRM
Live View Resolution Mode. Selects the grid size used for live view resolution.
0 512 × 384
1 448 × 336
2 384 × 288
3 384 × 256
4 320 × 240
5 288 × 216
6 400 × 300
15–8
VSC
Vertical Skip Count. Contains the number of rows to skip.
SCE must be 1, otherwise VSC is ignored.
0–255 Number of rows to skip minus 1
7–0
HSC
Horizontal Skip Count. Contains the number of pixels to skip.
SCE must be 1, otherwise HSC is ignored.
0–255 Number of pixels to skip minus 1
17.6.5
CSI Control Register 3 (CSICR3)
This read/write register, shown in Figure 17-11 and Table 17-10, acts as an extension of the functionality
of the CSI Control register 1, adding control and features.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
17-22
Freescale Semiconductor
CMOS Sensor Interface (CSI)
0xBASE_0008 (CSICR3)
31
30
29
28
Access: User read/write
27
26
25
24
23
22
21
20
19
18
17
16
R
FRMCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
DMA_REQ_EN_RFF
DMA_REQ_EN_SFF
16BIT_SENSOR
ZERO_PACK_EN
ECC_INT_EN
ECC_AUTO_EN
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
RxFF_LEVEL
STATFF_LEVEL
W
HRESP_ERR_EN
0
DMA_REFLASH_SFF
R
0
DMA_REFLASH_RFF
Reset
FRMCNT_RST
W
0
0
0
Figure 17-11. CSI Control Register 3 (CSICR3)
Table 17-10. CSI Control Register 3 Field Descriptions
Field
31–16
FRMCNT
15
FRMCNT_RST
Description
Frame Counter. This is a 16-bit Frame Counter
(Wrap around automatically after reaching the maximum)
Frame Count Reset. Resets the Frame Counter.
0 Do not reset
1 Reset frame counter immediately
(Cleared automatically after reset is done)
14
Reflash DMA Controller for RxFIFO. This bit reflash the embedded DMA controller for RxFIFO. It should
DMA_REFLASH_RFF
be reflashed before the embedded DMA controller starts to work.
0 No reflashing
1 Reflash the embedded DMA controller
(Cleared automatically after reflashing is done)
13
Reflash DMA Controller for STATFIFO. This bit reflash the embedded DMA controller for STATFIFO. It
DMA_REFLASH_SFF
should be reflashed before the embedded DMA controller starts to work.
0 No reflashing
1 Reflash the embedded DMA controller
(Cleared automatically after reflashing is done)
12
DMA Request Enable for RxFIFO. This bit enables the DMA request from RxFIFO to the embedded
DMA_REQ_EN_RFF DMA controller.
0 Disable the DMA request
1 Enable the DMA request
11
DMA Request Enable for STATFIFO. This bit enables the DMA request from STATFIFO to the
DMA_REQ_EN_SFF embedded DMA controller.
0 Disable the DMA request
1 Enable the DMA request
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
17-23
CMOS Sensor Interface (CSI)
Table 17-10. CSI Control Register 3 Field Descriptions
Field
Description
10-8
STATFF_LEVEL
STATFIFO Full Level. When the number of data in STATFIFO reach this level, STATFIFO full interrupt is
generated, or STATFIFO DMA request is sent.
000 4 Words
001 8 Words
010 12 Words
011 16 Words
100 24 Words
101 32 Words
110 48 Words
111 not support
7
HRESP_ERR_EN
6-4
RxFF_LEVEL
Hresponse Error Enable. This bit enables the hresponse error interrupt.
0 Disable hresponse error interrupt
1 Enable hresponse error interrupt
RxFIFO Full Level. When the number of data in RxFIFO reach this level, a RxFIFO full interrupt is
generated, or an RXFIFO DMA request is sent.
000 4 Words
001 8 Words
010 16 Words
011 24 Words
100 32 Words
101 48 Words
110 64 Words
111 96 Words
3
16BIT_SENSOR
16-bit Sensor Mode. This bit indicates one 16-bit sensor is connected to the 16-bit data ports. This bit
should be configured before activating or re-starting the embedded DMA controller.
0 16-bit sensor is not connected.
1 16-bit sensor is connected.
2
ZERO_PACK_EN
Dummy Zero Packing Enable. This bit causes a dummy zero to be packed with every 3 incoming bytes,
forming a 32-bit word. The dummy zero is always packed to the LSB position. This packing function is
only available in 8-bit/pixel mode.
0 Zero packing disabled
1 Zero packing enabled
1
ECC_INT_EN
Error Detection Interrupt Enable. This bit enables and disables the error detection interrupt. This feature
only works in CCIR interlace mode.
0 No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
1 Interrupt is generated when error is detected.
0
ECC_AUTO_EN
Automatic Error Correction Enable. This bit enables and disables the automatic error correction. If an
error occurs and error correction is disabled only the ECC_INT status bit is set. This feature only works
in CCIR interlace mode.
0 Auto Error correction is disabled.
1 Auto Error correction is enabled.
17.6.6
CSI STATFIFO Register (CSISTATFIFO)
The StatFIFO, shown in Figure 17-12, is a read-only register containing statistic data from the sensor.
Writing to this register has no effect.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
17-24
Freescale Semiconductor
CMOS Sensor Interface (CSI)
0xBASE_000C (CSISTATFIFO)
31
30
29
28
Access: User read-0nly
27
26
25
24
R
23
22
21
20
19
18
17
16
STAT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
STAT
W
Reset
0
0
0
0
0
0
0
0
Figure 17-12. CSI STATFIFO Register (CSISTATFIFO)
17.6.7
CSI RxFIFO Register (CSIRFIFO)
This read-only register, shown in Figure 17-13, contains received image data. Writing to this register has
no effect.
0xBASE_0010 (CSIRFIFO)
31
30
29
28
Access: User read-0nly
27
26
25
24
R
23
22
21
20
19
18
17
16
IMAGE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
IMAGE
W
Reset
0
0
0
0
0
0
0
0
0
Figure 17-13. CSI RxFIFO Register (CSIRFIFO)
17.6.8
CSI RX Count Register (CSIRXCNT)
This register, shown in Figure 17-14 and Table 17-11, works for EOF interrupt generation. It should be set
to the number of words to receive that would generate an EOF interrupt.
There is an internal counter that counts the number of words read from the RX FIFO. Whenever the RX
FIFO is being read, by either the CPU or the embedded DMA controller, the counter value is updated and
compared with this register. If the values match, then an EOF interrupt is triggered. For example, one FIFO
word is 4 bytes, so for a picture of 640 × 480 using 2 bytes/pixel, RXCNT should be set to 640 × 480 × 2/4.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
17-25
CMOS Sensor Interface (CSI)
0xBASE_0014 (CSIRXCNT)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
21
20
19
18
17
16
RXCNT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
RXCNT
W
Reset
1
0
0
1
0
1
1
0
0
Figure 17-14. CSI RX Count Register (CSIRXCNT)
Table 17-11. CSI RX Count Register Field Descriptions
Field
31–22
21–0
RXCNT
17.6.9
Description
Reserved.
RxFIFO Count. This 22-bit counter for RXFIFO is updated each time the RXFIFO is read by CPU or DMA.This
counter should be set to the expected number of words to receive that would generate an EOF interrupt.
CSI Status Register (CSISR)
This read/write register, shown in Figure 17-15 and Table 17-12, indicates sensor interface status, and
which kind of interrupt is being generated. The corresponding interrupt bits must be set for the status bit
to function. Status bits should function normally even if the corresponding interrupt enable bits are not
enabled.
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17-26
Freescale Semiconductor
CMOS Sensor Interface (CSI)
26
25
24
23
0
0
0
0
0
0
0
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
DRDY
w1c
16
ECC_INT
w1c
17
HRESP_ERR_INT
RFF_OR_INT
18
0
R
W
Reset
w1c
19
COF_INT
w1c
20
F1_INT
Reset
w1c
21
F2_INT
W
SFF_OR_INT
R
22
SOF_INT
27
EOF_INT
28
RxFF_INT
29
DMA_TSF_DONE_FB1
30
DMA_TSF_DONE_FB2
31
STATFF_INT
Access: User read/write
DMA_TSF_DONE_SFF
0xBASE_0018 (CSISR)
w1c
0
1
0
w1c
0
0
0
0
0
0
w1c
0
0
0
0
0
0
0
Figure 17-15. CSI Status Register (CSISR)
Table 17-12. CSI Status Register Field Descriptions
Field
31–26
Description
Reserved.
25
SF_OR_INT
STATFIFO Overrun Interrupt Status. Indicates the overflow status of the STATFIFO register.
0 STATFIFO has not overflowed.
1 STATFIFO has overflowed.
(Cleared by writing 1)
24
RF_OR_INT
RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register.
0 RXFIFO has not overflowed.
1 RXFIFO has overflowed.
(Cleared by writing 1)
23
Reserved.
22
DMA Transfer Done from StatFIFO. Indicates that the DMA transfer from StatFIFO is completed. It can
DMA_TSF_DONE_ trigger an interrupt if the corresponding enable bit is set in CSICR1. This bit can be cleared by writing 1
SFF
or reflashing the StatFIFO DMA controller in CSICR3.
0 DMA transfer is not completed.
1 DMA transfer is completed.
(Cleared by writing 1)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
17-27
CMOS Sensor Interface (CSI)
Table 17-12. CSI Status Register Field Descriptions (continued)
Field
Description
21
STATFF_INT
STATFIFO Full Interrupt Status. Indicates the number of data in the STATFIFO reaches the trigger level.
0 STATFIFO is not full.
1 STATFIFO is full.
(this bit is cleared automatically by reading the STATFIFO)
20
DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is
DMA_TSF_DONE_ completed. It can trigger an interrupt if the corresponding enable bit is set in CSICR1. This bit can be
FB2
cleared by writing 1 or reflashing the RxFIFO DMA controller in CSICR3.
0 DMA transfer is not completed.
1 DMA transfer is completed.
(Cleared by writing 1)
19
DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is
DMA_TSF_DONE_ completed. It can trigger an interrupt if the corresponding enable bit is set in CSICR1. This bit can be
FB1
cleared by writing 1 or reflashing the RxFIFO DMA controller in CSICR3.
0 DMA transfer is not completed.
1 DMA transfer is completed.
(Cleared by writing 1)
18
RxFF_INT
RXFIFO Full Interrupt Status. Indicates the number of data in the RxFIFO reaches the trigger level.
0 RxFIFO is not full.
1 RxFIFO is full.
(this bit is cleared automatically by reading the RxFIFO)
17
EOF_INT
End of Frame (EOF) Interrupt Status. Indicates when EOF is detected.
0 EOF is not detected.
1 EOF is detected.
(Cleared by writing 1)
16
SOF_INT
Start of Frame Interrupt Status. Indicates when SOF is detected.
0 SOF is not detected.
1 SOF is detected.
(Cleared by writing 1)
15
F2_INT
CCIR Field 2 Interrupt Status. Indicates the presence of field 2 of video in CCIR mode.
Note: Only works in CCIR Interlace mode.
0 Field 2 of video is not detected
1 Field 2 of video is about to start
(Cleared automatically when current field does not match)
14
F1_INT
CCIR Field 1 Interrupt Status. Indicates the presence of field 1 of video in CCIR mode.
Note: Only works in CCIR Interlace mode.
0 Field 1 of video is not detected.
1 Field 1 of video is about to start.
(Cleared automatically when current field does not match)
13
COF_INT
12–8
Change Of Field Interrupt Status. Indicates that a change of the video field has been detected.
Only works in CCIR Interlace mode. Software should read this bit first and then dispatch the new field
from F1_INT and F2_INT.
0 Video field has no change.
1 Change of video field is detected.
(Cleared by writing 1)
Reserved.
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Freescale Semiconductor
CMOS Sensor Interface (CSI)
Table 17-12. CSI Status Register Field Descriptions (continued)
Field
Description
7
HRESP_ERR_INT
6– 2
Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected.
0 No hresponse error.
1 Hresponse error is detected.
(Cleared by writing 1)
Reserved.
1
ECC_INT
CCIR Error Interrupt. This bit indicates an error has occurred. This only works in CCIR Interlace mode.
0 No error detected
1 Error is detected in CCIR coding
(Cleared by writing 1)
0
DRDY
RXFIFO Data Ready. Indicates the presence of data that is ready for transfer in the RxFIFO.
0 No data (word) is ready
1 At least 1 data (word) is ready in RXFIFO.
(Cleared automatically by reading FIFO)
17.6.10 CSI STATFIFO DMA Start Address Register (CSIDMASA-STATFIFO)
This register, shown in Figure 17-16 and Table 17-13, provides the start address for the embedded DMA
controller of STATFIFO. The embedded DMA controller will read data from STATFIFO and write it to the
external memory from the start address. This register should be configured before activating or re-starting
the embedded DMA controller.
0xBASE_0020 (CSIDMASA-STATFIFO)
31
30
29
28
27
26
Access: User read/write
25
24
23
22
21
20
19
18
17
16
R
DMA_START_ADDR_SFF[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
DMA_START_ADDR_SFF[15:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-16. CSI STATFIFO DMA Start Address Register (CSIDMASA-STATFIFO)
Table 17-13. CSI STATFIFO DMA Start Address Register Field Descriptions
Field
Description
31–2
DMA Start Address for STATFIFO. Indicates the start address to write data.
DMA_START_ADDR_SFF The embedded DMA controller will read data from STATFIFO and write it from
this address through AHB bus. The address should be word aligned.
1-0
Reserved.
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Freescale Semiconductor
17-29
CMOS Sensor Interface (CSI)
17.6.11 CSI STATFIFO DMA Transfer Size Register (CSIDMATS-STATFIFO)
This register, shown in Figure 17-17 and Table 17-14, provides the total transfer size for the embedded
DMA controller of STATFIFO. This register should be configured before activating or re-starting the
embedded DMA controller.
0xBASE_0024 (CSIDMATS-STATFIFO)
31
30
29
28
27
Access: User read/write
26
25
24
23
22
21
20
19
18
17
16
R
DMA_TSF_SIZE_SFF[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
DMA_TSF_SIZE_SFF[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 17-17. CSI STATFIFO DMA Transfer Size Register (CSIDMATS-STATFIFO)
Table 17-14. CSI STATFIFO DMA Transfer Size Register Field Descriptions
Field
Description
31–0
DMA Transfer Size for STATFIFO. Indicates how many words to be transferred by the embedded DMA
DMA_TSF_SIZE_SFF controller. The size should be word aligned.
17.6.12 CSI Frame Buffer1 DMA Start Address Register (CSIDMASA-FB1)
This register, shown in Figure 17-18 and Table 17-15, provides the start address in the frame buffer1 for
the embedded DMA controller of RxFIFO. The embedded DMA controller will read data from RxFIFO
and write it to the frame buffer1 from the start address. This register should be configured before activating
or re-starting the embedded DMA controller.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
17-30
Freescale Semiconductor
CMOS Sensor Interface (CSI)
0xBASE_0028 (CSIDMASA-FB1)
31
30
29
28
27
Access: User read/write
26
25
24
23
22
21
20
19
18
17
16
R
DMA_START_ADDR_FB1[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
DMA_START_ADDR_FB1[15:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-18. CSI Frame Buffer1 DMA Start Address Register (CSIDMASA-FB1)
Table 17-15. CSI Frame Buffer1 DMA Start Address Register Field Descriptions
Field
Description
31–2
DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded
DMA_START_ADDR_FB1 DMA controller will read data from RxFIFO and write it from this address through AHB bus. The
address should be word aligned.
1-0
Reserved.
17.6.13 CSI Frame Buffer2 DMA Start Address Register (CSIDMASA-FB2)
This register, shown in Figure 17-19 and Table 17-16, provides the start address in the frame buffer2 for
the embedded DMA controller of RxFIFO. The embedded DMA controller will read data from RxFIFO
and write it to the frame buffer2 from the start address. This register should be configured before activating
or re-starting the embedded DMA controller.
0xBASE_002C (CSIDMASA-FB2)
31
30
29
28
27
Access: User read/write
26
25
24
23
22
21
20
19
18
17
16
R
DMA_START_ADDR_FB2[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
DMA_START_ADDR_FB2[15:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-19. CSI Frame Buffer2 DMA Start Address Register (CSIDMASA-FB2)
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CMOS Sensor Interface (CSI)
Table 17-16. CSI Frame Buffer2 DMA Start Address Register Field Descriptions
Field
Description
31–2
DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded
DMA_START_ADDR_FB2 DMA controller will read data from RxFIFO and write it from this address through AHB bus. The
address should be word aligned.
1-0
Reserved.
17.6.14 CSI Frame Buffer Parameter Register (CSIFBUF_PARA)
This register, shown in Figure 17-20 and Table 17-17, provides the stride of the frame buffer to show how
many words to skip before starting to write the next row of the image. The width of the frame buffer minus
the width of the image is the stride. This register should be configured before activating or re-starting the
embedded DMA controller.
0xBASE_0030 (CSIFBUF_PARA)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
W
Reset
R
FBUF_STRIDE[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 17-20. CSI Frame Buffer Parameter Register (CSIFBUF_PARA)
Table 17-17. CSI Frame Buffer Parameter Register Field Descriptions
Field
31-16
15–0
FBUF_STRIDE
Description
Reserved.
Frame Buffer Parameter. Indicates the stride of the frame buffer. The width of the frame buffer (in word) minus
the width of the image (in word) is the stride. The stride should be word aligned. The embedded DMA
controller will skip the stride before starting to write the next row of the image.
17.6.15 CSI Image Parameter Register (CSIIMAG_PARA)
This register, shown in Figure 17-21 and Table 17-18, provides the width and the height of the image from
the sensor. The width and height should be aligned in pixel. The width of the image multiplied by the
height is the total pixel size that will be transferred in a frame by the embedded DMA controller. This
register should be configured before activating or re-starting the embedded DMA controller.
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CMOS Sensor Interface (CSI)
0xBASE_0034 (CSIIMAG_PARA)
31
30
29
28
27
Access: User read/write
26
25
24
23
22
21
20
19
18
17
16
R
IMAGE_WIDTH[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
IMAGE_HEIGHT[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 17-21. CSI Image Parameter Register (CSIIMAG_PARA)
Table 17-18. CSI Image Parameter Register Field Descriptions
Field
Description
31–16
Image Width. Indicates how many pixels in a line of the image from the sensor.
IMAGE_WIDTH If the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 4 pixels.
If the input data from the sensor is 10-bit/pixel or 16-bit/pixel format, the IMAGE_WIDTH should be a multiple
of 2 pixels.
15–0
Image Height. Indicates how many pixels in a column of the image from the sensor.
IMAGE_HEIGHT
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CMOS Sensor Interface (CSI)
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Chapter 18
Configurable Serial Peripheral Interface (CSPI)
This chapter describes a module integrated into an SoC. The chapter is intended for a module driver
software developer. It describes module-level operation and programming. To understand how the module
is integrated at the SoC level, a system software developer should see discussions of the module in the
appropriate SoC-level chapter(s).
18.1
Overview
The Configurable Serial Peripheral Interface (CSPI) module is a full-duplex, synchronous, four-wire serial
communication module. The CSPI module contains an 8 × 32 receive buffer (RXFIFO) and an 8 × 32
transmit buffer (TXFIFO). With data FIFOs, the CSPI module allows rapid data communication with
fewer software interrupts. Figure 18-1 shows a block diagram of the CSPI.
Peripheral Bus Interface
TXDATA
RXDATA
STATREG
INTREG
DMAREG
PERIODREG
State Machine
TESTREG
Clock
Generator
CONREG
Low-Frequency
Reference Clock
Reference Clock
Interrupt Request
DMA Requests
SPI_RDY
SS[3:0]
SCLK
Shift Register
MISO
MOSI
Figure 18-1. CSPI Block Diagram
18.1.1
Features
Key features of the CSPI module include:
• Full-duplex synchronous serial interface
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18-1
Configurable Serial Peripheral Interface (CSPI)
•
•
•
•
•
•
•
Master/Slave configurable
Four Chip Select (SS) signals to support multiple peripherals
Transfer continuation function allows unlimited length data transfers
32-bit wide by 8-entry FIFO for both transmit and receive data
Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
Direct Memory Access (DMA) support
Max operation frequency up to one-quarter of the reference clock frequency.
18.1.2
Modes and Operations
The CSPI supports the modes described in the indicated sections:
• Section 18.4.1, “Operating Modes”:
— Section 18.4.1.1, “Master Mode”
— Section 18.4.1.2, “Slave Mode”
• Section 18.4.2, “Low Power Modes”
As described in Section 18.4.3, “Operations,” the CSPI supports the operations described in the indicated
sections:
• Section 18.4.3.1, “Typical Master Mode”:
— Section 18.4.3.1.1, “Master Mode with SPI_RDY”
— Section 18.4.3.1.2, “Master Mode with Wait States”
— Section 18.4.3.1.3, “Master Mode with SSCTL Control”
— Section 18.4.3.1.4, “Master Mode with Phase Control”
• Section 18.4.3.2, “Typical Slave Mode”
18.2
External Signals
Conventions: Table 18-1 lists conventions for representing signals.
Table 18-1. Module Signal Conventions
Category
Convention
Example(s)
Off-chip signal
Uppercase (all capital letters)
TXD
Internal signal1
Lowercase italics
core_int
Active low signal
_B (_b) suffix or overbar
RESET_EN_B or RESET_EN
Range of bussed or commonly named
signals
Beginning and end points of the range are:
• Separated by a colon.
• Surrounded by square brackets.
ADDR[31:0]
CSE_B[7:0] or CSE[7:0]
Individual signal in a range of bussed or
commonly named signals
Individual number in the range appears without ADDR31
a colon or square brackets
CSE0_B or CSE0
1
Internal signals are for reference only in descriptions of internal module or SoC functionality.
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Configurable Serial Peripheral Interface (CSPI)
Table 18-2 describes all CSPI signals that connect off-chip.
Table 18-2. Off-Chip Module Signals
Signal
I/O
Reset
State1
Pull-Up/
Down1
SS[3:0]
I/O
Chip selects
1
—
SCLK
I/O
SPI clock
0
Active
MISO
I/O
Master data in; slave data out
0
Passive
MOSI
I/O
Master data out; slave data in
0
—
I
Master data out; slave data in
0
Active
SPI_RDY
1
Description
The reset state values and pull-up/down requirements provided in this table are from the module-level perspective. To
understand how the module is integrated at the SoC level, the system software developer must see discussions of the module
in the appropriate SoC-level chapter(s). For example, a module signal that requires a pull-up could be integrated with a pull-up
option built into the SoC. In this case, the system software developer must ensure the proper programming at the SoC level.
Figure 18-2 shows the CSPI module in master mode connected to four external devices in a one-way
communication link.
CSPI
(Master)
External
External
External
External
Device 0
Device 1
Device 2
Device 3
SS[0]
SS[1]
SS[2]
SS[3]
SS[3:0]
SCLK
MOSI
Figure 18-2. Example Connection Diagram
18.3
Memory Map and Register Definition
This section includes the module memory map and detailed descriptions of all registers. For the base
address of a particular module instantiation, see the system memory map.
18.3.1
Memory Map
Table 18-3 is the module memory map.
Table 18-3. Module Memory Map
Base Address Offset
(Register Abbreviation)
Register
Access Reset Value
Section/Page
General Registers
0x0000 (RXDATA)
Receive Data Register (RXDATA)
R
0x0000_0000
18.3.3.1/18-6
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18-3
Configurable Serial Peripheral Interface (CSPI)
Table 18-3. Module Memory Map
Base Address Offset
(Register Abbreviation)
0x0004 (TXDATA)
Register
Access Reset Value
Transmit Data Register (TXDATA)
Section/Page
W
0x0000_0000
18.3.3.2/18-7
18.3.3.3/18-7
0x0008 (CONREG)
Control Register (CONREG)
R/W
0x0000_0000
0x000C (INTREG)
Interrupt Control Register (INTREG)
R/W
0x0000_0000 18.3.3.4/18-10
0x0010 (DMAREG)
DMA Control Register (DMAREG)
R/W
0x0000_0000 18.3.3.5/18-11
0x0014 (STATREG)
Status Register (STATREG)
R/W
0x0000_0003 18.3.3.6/18-12
Sample Period Control Register (PERIODREG)
R/W
0x0000_0000 18.3.3.7/18-13
Test Control Register (TESTREG)
R/W
0x0000_0000 18.3.3.8/18-14
0x0018 (PERIODREG)
0x001C (TESTREG)
18.3.2
Register Summary
Table 18-4 is the register summary table.
Table 18-4. Module Register Summary
Offset (and Name
Abbreviation)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0x0000
(RXDATA)
RXDATA[31:16]
W
R
RXDATA[15:0]
W
R
0x0004
(TXDATA)
0
0
0
0
0
0
0
W
R
0
0
TXDATA[31:16]
0
0
0
0
0
0
0
W
0
0
TXDATA[15:0]
R
0
BURST LENGTH
0x0008
(CONREG)
R
0
0
W
R
0x000C
(INTREG)
DATA RATE
W
CHIP
SELECT
0
0
DRCTL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSP SSC
PHA POL SMC XCH
OL
TL
0
0
0
0
0
0
MO
DE
EN
0
0
W
R
W
TCE ROE RFE RHE RRE TFE THE TEE
N
N
N
N
N
N
N
N
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Configurable Serial Peripheral Interface (CSPI)
Table 18-4. Module Register Summary (continued)
Offset (and Name
Abbreviation)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TC
RO
RF
RH
RR
TF
TH
TE
0
0
0
0
0
0
0
0
0
0
0
0
0
W
0x0010
(DMAREG)
R
W
R
0x0014
(STATREG)
R
R
w1c
0
0
0
0
0
0
0
W
0x0018
(PERIODREG) R
CSR
W C
R
18.3.3
TH
TE
DEN DEN
W
W
0x001C
(TESTREG)
RF
RH
DEN DEN
0
0
SAMPLE PERIOD[14:0]
0
0
0
0
0
0
0
0
0
0
0
0
W
R SWA
LBC
W P
—
RXCNT
TXCNT
Register Descriptions
This section provides detailed descriptions of the module’s registers.
Register conventions: Figure 18-3 and Table 18-5 explain conventions used in register diagrams and
tables.
Always
reads 1
1
Always
reads 0
0
R/W
Read- BIT WriteWrite 1 BIT
Read rtc Self-clear 0 N/A
bit BIT only bit
only bit BIT to clear w1c to clear BIT
bit BIT
Figure 18-3. Register Field Conventions
Table 18-5. General Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
BIT
Bit or field name. Its presence in the read or write row indicates that it can correspondingly be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
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18-5
Configurable Serial Peripheral Interface (CSPI)
Table 18-5. General Register Conventions (continued)
Convention
Description
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
rtc
Read to clear. A read-only status bit that is automatically cleared when read.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
Reset Values
0
Resets to 0 (zero).
1
Resets to 1 (one).
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
18.3.3.1
Reset value is determined by polarity of indicated signal.
Receive Data Register (RXDATA)
The Receive Data register (RXDATA) is a read-only register that forms the top word of the 8 × 32 receive
FIFO. This register holds the data received from an external SPI device during a data transaction. Only
word-sized read operations are allowed. Figure 18-4 shows the register. Table 18-6 describes the register
fields.
Offset 0x0000 (RXDATA)
31
30
29
Access: User read-only
28
27
26
25
R
24
23
22
21
20
19
18
17
16
RXDATA[31:16]
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RXDATA[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 18-4. RXDATA Register Diagram
Table 18-6. RXDATA Register Field Description
Field
Description
31–0
Receive Data. This register holds the top word of the receive data FIFO. The FIFO is advanced for each read of this
RXDATA register. The data read is undefined when the Receive Data Ready (RR) bit in the Interrupt Control/Status register
is cleared. Zeros are read when CSPI is disabled.
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Configurable Serial Peripheral Interface (CSPI)
18.3.3.2
Transmit Data Register (TXDATA)
The Transmit Data (TXDATA) register is a write-only data register that forms the bottom word of the
8 × 32 TXFIFO. The TXFIFO can be written to as long as it is not full, even when the SPI Exchange bit
(XCH) in CONREG is set. This allows software to write to the TXFIFO during a SPI data exchange
process. Writes to this register are ignored when the CSPI module is disabled (CONREG[EN] bit is
cleared). Figure 18-5 shows the register. Table 18-7 describes the register fields.
Offset 0x0004 (TXDATA)
R
Access: User write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
TXDATA[31:16]
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
TXDATA[15:0]
0
0
0
0
0
0
0
0
0
Figure 18-5. TXDATA Register Diagram
Table 18-7. TXDATA Register Field Description
Field
Description
31–0
Transmit Data. This register holds the top word of data loaded into the FIFO. Data written to this register must be a
TXDATA word operation. The number of bits actually transmitted is determined by the BURST_LENGTH field of the
corresponding SPI Control register. If this field contains more bits than the number specified by BURST_LENGTH,
the extra bits are ignored. For example, to transfer 10 bits of data, a 32-bit word must be written to this register. Bits
9-0 are shifted out and bits 31-10 are ignored. When the CSPI module is operating in Slave mode, zeros are shifted
out when the FIFO is empty. Zeros are read when CSPI is disabled.
18.3.3.3
Control Register (CONREG)
The Control Register (CONREG) allows software to enable the CSPI module, configure its operating
modes, specify the divider value, phase, and polarity of the clock, configure the Chip Select (SS) and
SPI_RDY control signal, and define the transfer length.
Figure 18-6 shows the register. Table 18-8 describes the register fields.
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18-7
Configurable Serial Peripheral Interface (CSPI)
Offset 0x0008 (CONREG)
31
30
29
Access: User read/write
28
27
R
R
24
23
22
21
20
19
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
CHIP
SELECT
0
0
0
0
0
0
0
0
DRCTL
0
18
0
0
W
Reset
25
BURST LENGTH
W
Reset
26
0
0
0
0
0
0
7
6
5
4
3
0
0
0
0
2
1
0
EN
0
POL
SMC
XCH
MOD
E
0
0
0
0
0
16
DATA RATE
0
SSPO SSCT
PHA
L
L
17
Figure 18-6. CONREG Register Diagram
Table 18-8. CONREG Register Field Description
Field
Description
31–20
BURST
LENGTH
Burst Length. This field defines the length of a SPI burst to be transferred. The Chip Select (SS) will remain
asserted until all bits in a SPI burst are shifted out. A maximum of 2^12 bits can be transferred in a single SPI burst.
In master mode, it controls the number of bits per SPI burst. Since the shift register always loads 32-bit data from
transmit FIFO, only the n least-significant (n = BURST LENGTH + 1) will be shifted out. The remaining bits will be
ignored.
In slave mode, only when SSCTL is cleared, this field will take effect in the transfer.
Number of Valid Bits in a SPI burst.
0x000 A SPI burst contains the 1 LSB in a word.
0x001 A SPI burst contains the 2 LSB in a word.
0x002 A SPI burst contains the 3 LSB in a word.
......
0x01F A SPI burst contains all 32 bits in a word.
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
......
0xFFE A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
0xFFF A SPI burst contains 2^7 words.
19
Reserved
18–16
DATA
RATE
SPI Data Rate Control. This field selects the baud rate of the SCLK based on a division of the reference clock.
These bits allow the CSPI to synchronize with different external SPI devices. The max frequency is one quarter of
the reference clock. The divide ratio is determined according to the following table using the equation: 2(n+2).
SPI Data Rate Control (Master Mode only)
000 Divide by 4.
001 Divide by 8.
010 Divide by 16.
011 Divide by 32.
100 Divide by 64.
101 Divide by 128.
110 Divide by 256.
111 Divide by 512.
15 –14
Reserved
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Configurable Serial Peripheral Interface (CSPI)
Table 18-8. CONREG Register Field Description (continued)
Field
Description
13 –12
CHIP
SELECT
CHIP SELECT. Select one of four external SPI Master/Slave Devices. In master mode, these two bits select the
external slave devices by asserting the Chip Select (SSn) outputs. Only the selected Chip Select (SSn) signal can
be active at a given time; the remaining three signals will be negated.
Chip Select
00 Chip Select 0 (SS0) will be asserted.
01 Chip Select 1 (SS1) will be asserted.
10 Chip Select 2 (SS2) will be asserted.
11 Chip Select 3 (SS3) will be asserted.
11–10
Reserved
9–8
DRCTL
SPI Data Ready Control. This field selects the utilization of the SPI_RDY signal in master mode. CSPI checks this
field before it starts an SPI burst.
00 The SPI_RDY signal is a don’t care.
01 Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
10 Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
11 Reserved.
7
SSPOL
SPI SS Polarity Select. In both Master and Slave modes, this bit selects the polarity of the Chip Select (SS) signal.
0 Active low.
1 Active high.
6
SSCTL
SPI SS Wave Form Select. In master mode, this bit controls the output wave form of the Chip Select (SS) signal
when SMC is cleared. The SSCTL bit will be ignored if the SMC (Start Mode Control) bit is set.
0 Only one SPI burst will be transmitted.
1 Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will
automatically stop when the TXFIFO is empty.
In slave mode, this bit controls when the SPI burst is completed.
0 A SPI burst is completed when the number of bits received in the shift register is equal to BURST LENGTH + 1.
Only n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits
subsequent to the first received word in RXFIFO are valid.
1 A SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising edge; SSPOL = 1: falling
edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge is detected or the shift register
contains 32-bits of valid data.
5
PHA
SPI Clock/Data Phase Control. This bit controls the clock/data phase relationship. See Figure 18-19 for more
information.
0 Phase 0 operation.
1 Phase 1 operation.
4
POL
SPI Clock Polarity Control. This bit controls the polarity of the SCLK signal. See Figure 18-19 for more information.
0 Active high polarity (0 = Idle).
1 Active low polarity (1 = Idle).
3
SMC
Start Mode Control. This bit applies only when the module is configured in Master mode (MODE = 1).
It controls how the CSPI starts a SPI burst, either through the SPI exchange bit, or immediately when the TXFIFO
is written to.
0 SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple
bursts. This is controlled by the SPI SS Wave Form Select (SSCTL) bit. Refer to XCH and SSCTL bit
descriptions.
1 Immediately starts a SPI burst when data is written in TXFIFO.
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Freescale Semiconductor
18-9
Configurable Serial Peripheral Interface (CSPI)
Table 18-8. CONREG Register Field Description (continued)
Field
Description
2
XCH
SPI Exchange Bit. This bit applies only when the module is configured in Master mode (MODE = 1).
If the Start Mode Control (SMC) bit is cleared, writing a 1 to this bit starts one SPI burst or multiple SPI bursts
according to the SPI SS Wave Form Select (SSCTL bit). The XCH bit remains set while either the data exchange
is in progress, or when the CSPI is waiting for an active input if SPIRDY is enabled through DRCTL. This bit is
cleared automatically when all data in the TXFIFO and the shift register has been shifted out.
0 Idle.
1 Initiates exchange (write) or busy (read).
1
MODE
SPI Function Mode Select. This bit selects the operating mode of the CSPI.
0 Slave mode.
1 Master mode.
0
EN
SPI Module Enable Control. This bit enables the CSPI module. This bit must be set before writing to other registers
or initiating an exchange. Writing zero to this bit disables the module and resets the internal logic with the exception
of the CONREG. The module’s internal clocks are gated off whenever the module is disabled.
0 Disable the module.
1 Enable the module.
18.3.3.4
Interrupt Control Register (INTREG)
The Interrupt Control Register (INTREG) enables the generation of interrupts to the host processor. If the
CSPI is disabled, this register reads zero. Figure 18-7 shows the register. Table 18-9 describes the register
fields.
Offset 0x000C (INTREG)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
ROE
RHE
TCEN
RFEN
N
N
0
0
0
RRE
TFEN THEN TEEN
N
0
0
0
0
0
Figure 18-7. INTREG Register Diagram
Table 18-9. INTREG Register Field Description
Field
Description
31–8
Reserved
7
TCEN
Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt.
0 Disable
1 Enable
6
ROEN
RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt.
0 Disable
1 Enable
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
18-10
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 18-9. INTREG Register Field Description (continued)
Field
Description
5
RFEN
RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt.
0 Disable
1 Enable
4
RHEN
RXFIFO Half Full Interrupt enable. This bit enables the RXFIFO Half Full Interrupt.
0 Disable
1 Enable
3
RREN
RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt.
0 Disable
1 Enable
2
TFEN
TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt.
0 Disable
1 Enable
1
THEN
TXFIFO Half Empty Interrupt enable. This bit enables the TXFIFO Half Empty Interrupt.
0 Disable
1 Enable
0
TEEN
TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt.
0 Disable
1 Enable
18.3.3.5
DMA Control Register (DMAREG)
The Direct Memory Access Control Register (DMAREG) provides software a way to use an on-chip DMA
controller for CSPI data. Internal DMA request signals enable direct data transfers between the CSPI
FIFOs and system memory. The CSPI sends out DMA requests when the appropriate FIFO conditions are
matched.
If the CSPI is disabled, this register is read as 0. Figure 18-8 shows the register. Table 18-10 describes the
register fields.
Offset 0x0010 (DMAREG)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
RF
DEN
RH
DEN
0
0
TH
DEN
TE
DEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 18-8. DMAREG Register Diagram
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-11
Configurable Serial Peripheral Interface (CSPI)
Table 18-10. DMAREG Register Field Description
Field
31–6
5
RFDEN
Description
Reserved
RXFIFO Full DMA Request Enable. This bit enables/disables the RXFIFO Full DMA Request.
0 Disable
1 Enable
4
RXFIFO Half Full DMA Request Enable. This bit enables/disables the RXFIFO Half Full DMA Request.
RHDEN 0 Disable
1 Enable
3–2
Reserved
1
THDEN
TXFIFO Half Empty DMA Request Enable. This bit enables/disables the TXFIFO Half Empty DMA Request.
0 Disable
1 Enable
0
TEDEN
TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request.
0 Disable
1 Enable
18.3.3.6
Status Register (STATREG)
The CSPI Status Register (STATREG) reflects the status of the CSPI module’s operating condition. If the
CSPI is disabled, this register reads 0x0000_0003. Figure 18-9 shows the register. Table 18-11 describes
the register fields.
Offset 0x0014 (STATREG)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TC
RO
RF
RH
RR
TF
TH
TE
0
0
0
0
0
1
1
W
Reset
R
W
Reset
w1c
0
0
0
0
0
0
0
0
0
Figure 18-9. STATREG Register Diagram
Table 18-11. STATREG Register Field Description
Field
31–8
7
TC
Description
Reserved
Transfer Completed Status bit. Writing 1 to this bit clears it.
0 Transfer in progress.
1 Transfer completed.
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18-12
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 18-11. STATREG Register Field Description (continued)
Field
Description
6
RO
RXFIFO Overflow. When set, this bit indicates that RXFIFO has overflowed.
0 RXFIFO has no overflow.
1 RXFIFO has overflowed.
5
RF
RXFIFO Full. This bit is set when the RXFIFO is full.
0 Not Full.
1 Full.
4
RH
RXFIFO Half Full. This bit is set when the RXFIFO reaches half full.
0 Less than 4 words are stored in RXFIFO.
1 Four or more words are available in RXFIFO.
3
RR
RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO.
0 No valid data in RXFIFO.
1 More than 1 word in RXFIFO.
2
TF
TXFIFO Full. This bit is set when if the TXFIFO is full.
0 TXFIFO is not Full.
1 TXFIFO is Full.
1
TH
TXFIFO Half empty. This bit is set when the TXFIFO reaches half empty.
0 TXFIFO holds more than 4 words.
1 TXFIFO holds 4 or fewer words.
0
TE
TXFIFO Empty. This bit is set if the TXFIFO is empty.
0 TXFIFO contains one or more words.
1 TXFIFO is empty.
18.3.3.7
Sample Period Control Register (PERIODREG)
The Sample Period Control Register (PERIODREG) provides software a way to insert delays (wait states)
between consecutive SPI transfers. Control bits in this register select the clock source for the sample period
counter and the delay count indicating the number of wait states to be inserted between data transfers.
The delay counts apply only when the module is configured in Master mode (CONREG[MODE] = 1).
Figure 18-10 shows the register. Table 18-12 describes the register fields.
Offset 0x0018 (PERIODREG)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
W
Reset
R CSR
W C
Reset
0
SAMPLE PERIOD
0
0
0
0
0
0
0
0
0
Figure 18-10. PERIODREG Register Diagram
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-13
Configurable Serial Peripheral Interface (CSPI)
Table 18-12. PERIODREG Register Field Description
Field
Description
31–16
Reserved
15
CSRC
Clock Source Control. This bit selects the clock source for the sample period counter.
0 SPI Clock (SCLK)
1 Low-Frequency Reference Clock (32.768 KHz)
14–0
Sample Period Control. These bits control the number of wait states to be inserted in data transfers. During the idle
SAMPLE clocks, the state of the SS output will operate according to the SSCTL control field in the CONREG register.
PERIOD 0x0000 0 wait states inserted
0x0001 1 wait state inserted
......
......
0x7FFE 32766 wait states inserted
0x7FFF 32767 wait states inserted
18.3.3.8
Test Control Register (TESTREG)
The Test Control Register (TESTREG) provides software a mechanism to internally connect the receive
and transmit devices of the CSPI module, swap the byte order for receive data, and monitor the contents
of the receive and transmit FIFO.
Figure 18-11 shows the register. Table 18-13 describes the register fields.
Offset 0x001C (TESTREG)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
W
Reset
R SWA
W P
Reset
0
LBC
0
—
0
0
RXCNT
0
0
0
0
0
TXCNT
0
0
0
0
0
Figure 18-11. TESTREG Register Diagram
Table 18-13. TESTREG Register Field Description
Field
Description
31–16
Reserved
15
SWAP
Data Swap. This bit is used to swap data as it is read from the RXFIFO. When this bit is set, data read from RXFIFO
is swapped. RXDATA[31:0] is swapped as follows: {RXDATA[7:0], RXDATA[15:8], RXDATA[23:16], RXDATA[31:24]}
0 Data read from RXFIFO is unchanged.
1 Data read from RXFIFO is swapped.
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18-14
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 18-13. TESTREG Register Field Description (continued)
Field
Description
14
LBC
Loop Back Control. This bit is used in Master mode only. When this bit is set, the CSPI module connects the
transmitter and receiver sections internally, and the data shifted out from the most-significant bit of the shift register
is looped back into the least-significant bit of the Shift register. In this way, a self-test of the complete transmit/receive
path can be made. The output pins are not affected, and the input pins are ignored.
0 Not connected.
1 Transmitter and receiver sections internally connected for Loopback.
13–12
Reserved
11–8
Reserved
7–4
RXCNT
RXFIFO Counter. These bits indicate the number of words in RXFIFO.
RXFIFO Counter
0000 0 word in RXFIFO
0001 1 word in RXFIFO
......
......
0111 7 words in RXFIFO
1000 8 words in RXFIFO
3–0
TXCNT
TXFIFO Counter. These bits indicate the number of words in TXFIFO.
TXFIFO Counter
0000 0 word in TXFIFO
0001 1 word in TXFIFO
......
......
0111 7 words in TXFIFO
1000 8 words in TXFIFO
18.4
Functional Description
This section provides a complete functional description of the CSPI. Figure 18-12 shows the relationship
of SCLK and data lines while CSPI has been configured with different POL and PHA settings.
(POL=1, PHA=1) SCLK
(POL=1, PHA=0) SCLK
(POL=0, PHA=1) SCLK
(POL=0, PHA=0) SCLK
MISO
MSB...
...
...
...
...
...
LSB
MOSI
MSB...
...
...
...
...
...
LSB
Figure 18-12. CSPI SCLK, MISO, and MOSI Relationship
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-15
Configurable Serial Peripheral Interface (CSPI)
18.4.1
Operating Modes
CSPI has two operating modes, master mode and slave mode. This section describes all functional
operation modes of the CSPI.
18.4.1.1
Master Mode
When the CSPI module is configured as a master, it uses a serial link to transfer data between the CSPI
and an external slave device. One of the Chip Select (SS) signals and the clock signal (SCLK) are used to
transfer data between two devices. If the external device is a transmit-only device, the CSPI master’s output
port can be ignored and used for other purposes. In order to use the internal TXFIFO and RXFIFO, two
auxiliary output signals, Chip Select (SS) and SPI_RDY, are used for data transfer rate control. Software
can also configure the sample period control register to a fixed data transfer rate.
18.4.1.2
Slave Mode
When the CSPI module is configured as a slave, software can configure the CSPI Control register to match
the external SPI master’s timing. In this configuration, Chip Select (SS) becomes an input signal, and is
used to control data transfers through the Shift register, as well as to load/store the data FIFO.
18.4.2
Low Power Modes
The CSPI module does not operate under low power mode. It holds its operation when its clock is gated
off in master mode. In slave mode, the CSPI module does not respond when its clock is gated off.
18.4.3
Operations
This section describes the CSPI’s operations.
18.4.3.1
Typical Master Mode
The CSPI master uses the Chip Select (SS) signal to enable an external SPI device, and uses the SCLK
signal to transfer data in and out of the Shift register. The SPI_RDY enables fast data communication with
fewer software interrupts. By programming the PERIODREG register accordingly, the CSPI can be used
for a fixed data transfer rate.
When the CSPI module is in Master mode the SS, SCLK, and MOSI are output signals, and the MISO
signal is an input. Figure 18-13 shows a typical SPI burst.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
18-16
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
SS
SCLK
MOSI
MISO
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
Figure 18-13. Typical SPI Burst (8-bit Transfer)
In Figure 18-13, the Chip Select (SS) signal enables the selected external SPI device, and the SCLK
synchronizes the data transfer. The MOSI and MISO signals change on rising edge of SCLK and the MISO
signal is latched on the falling edge of the SCLK. Figure 18-13 shows a data of 0xD2 is shifted out, and a
data of 0x66 is shifted in.
18.4.3.1.1
Master Mode with SPI_RDY
By default, the CSPI does not use the SPI_RDY signal in master mode (MODE =1). A SPI burst begins
when the following events happen:
• The CSPI is enabled, TXFIFO has data in it, and CONREG[XCH] bit or the CONREG[SMC] bit
is set.
• When the SPI Data Ready Control (CONREG[DRCTL]) bits contains either 01 or 10, the
SPI_RDY signal controls when a SPI burst starts.
A SPI burst is defined as a bus transaction that starts when the slave select is asserted and ends when the
slave select is negated. The Chip Select (SS) signal will remain asserted until all the bits in a SPI burst are
shifted out.
If CONREG[DRCTL] is set to 01, the SPI burst can be triggered only if a falling edge of the SPI_RDY
signal has been detected. Figure 18-14 shows the relationship between a SPI burst and the falling edge of
SPI_RDY signal.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-17
Configurable Serial Peripheral Interface (CSPI)
SS
SPI_RDY
SCLK
MOSI
MISO
Figure 18-14. Relationship Between a SPI Burst and SPI_RDY: Falling-Edge Triggered
A SPI burst does not start until the falling edge of the SPI_RDY signal is detected. The next SPI burst starts
when the next SPI_RDY falling edge is detected, after the last burst has finished.
If SPI Data Ready Control (CONREG[DRCTL]) is set to 10, the SPI burst can be triggered only if the
SPI_RDY signal is low. Figure 18-15 shows the relationship between a SPI burst and the SPI_RDY signal.
The SPI burst does not begin until the SPI_RDY signal goes low. The CSPI will keep transmitting SPI burst
if the SPI_RDY signal remains low.
SS
SPI_RDY
SCLK
MOSI
MISO
Figure 18-15. Relationship Between a SPI Burst and SPI_RDY: Low-Level Triggered
18.4.3.1.2
Master Mode with Wait States
Wait states can be inserted between SPI bursts. This provides a way for software to slow down the SPI burst
to meet the timing requirements of a slower SPI device. Figure 18-16 shows wait states inserted between
SPI bursts.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
18-18
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
SS
Wait States
SCLK
MOSI
MISO
Figure 18-16. SPI Bursts with Wait States
In this case, the number of wait states is controlled by PERIODREG[SAMPLE PERIOD] and the wait
states’ clock source is selected by PERIODREG[CSRC].
18.4.3.1.3
Master Mode with SSCTL Control
The SPI SS Control (SSCTL) bit controls whether the current operation is single burst or multiple bursts.
When the SPI SS Wave Form Select (SSCTL) bit is set, the current operation is multiple bursts transfer.
When the SPI SS Wave Form Select (SSCTL) bit is cleared, the current operation is single burst transfer.
A SPI burst can contains multiple words as defined in the BURST LENGTH field of the CONREG register.
Figure 18-17 shows one SPI burst while SSCTL is clear.
SS
Waiting for
software to
write data to
the TXFIFO
SCLK
MOSI
MISO
Figure 18-17. SPI Burst While SSCTL is Clear
In Figure 18-17, two 8-bit bursts in the TXFIFO have been combined and transmitted in one SPI burst. The
maximum length of a single SPI burst is defined in the BURST LENGTH field of the CONREG control
register. (Figure 18-17 corresponds to a BURST LENGTH of 8.) This provides a way for transferring a
longer SPI burst by writing data into TXFIFO while the CSPI is transmitting.
Figure 18-18 shows two SPI bursts are transmitted while SSCTL is set.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-19
Configurable Serial Peripheral Interface (CSPI)
SS
SCLK
MOSI
MISO
Figure 18-18. SPI Bursts While SSCTL is Set
In Figure 18-18, two FIFO entries are transmitted, one entry with each SPI burst. The CSPI will continue
to transmit SPI bursts until the TXFIFO is empty. When wait states can be inserted between SPI bursts, the
SS will negate between SPI bursts until the wait states finish.
18.4.3.1.4
Master Mode with Phase Control
The Phase Control (CONREG[PHA]) bit controls how the transmit data shifts out and the receive data
shifts in.
When the Phase control (CONREG[PHA]) bit is set, the transmit data will shift out on the rising edge of
SCLK, and the receive data is latched on the falling edge of SCLK. The most-significant bit is output on
the first rising SCLK edge.
When CONREG[PHA] is cleared, the transmit data is shifted out on the falling edge of SCLK and the
receive data is latched on the rising edge of SCLK. The MSB is output when the host processor loads the
transmitted data.
Inverting the SCLK polarity does not impact the edge-triggered operations because they are internal to the
serial peripheral interface master. Figure 18-19 shows a SPI burst using different POL and PHA
configurations.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
18-20
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
SS
POL=0, PHA=0
POL=1, PHA=0
SCLK
POL=0, PHA=1
POL=1, PHA=1
MOSI
MISO
Figure 18-19. SPI Burst with Different POL and PHA Configurations
18.4.3.2
Typical Slave Mode
When the CSPI module is configured as a slave (Mode = 0), software can configure the CSPI Control
register to match the external SPI master’s timing. In this configuration, SS becomes an input signal, and
is used to latch data in and out of the internal data Shift registers, as well as to advance the data FIFO.
The SS, SCLK, and MOSI are inputs and MISO is output. Most of the timing diagrams are similar to the
diagrams shown previously for the SPI in Master mode (Mode = 1), because the inputs come from a SPI
master device.
However, the timing is different when SS is used to advance the data FIFO. When the SSCTL is set while
the CSPI is configured in Slave mode, the data FIFO will advance on the rising edge of the SS signal. When
the polarity is reversed (SSPOL = 1), the data FIFO will advance on the falling edge of the SS signal.
Figure 18-20 shows a SPI burst in which the data FIFO is advanced by the rising edge of the SS signal.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-21
Configurable Serial Peripheral Interface (CSPI)
SS
SCLK
MOSI
MISO
Figure 18-20. Advancing the Data FIFO on the Rising Edge of SS
In the above case, only the most significant 7 bits are loaded to the RXFIFO.
18.4.4
Clocks
This section describes clocks and special clocking requirements of the module.
CSPI has the following clock inputs:
• Reference Clock is the reference clock.
• Low-Frequency Reference Clock is a 32KHz input clock optionally used for counting wait states.
18.4.5
Reset
Whenever a device reset occurs, a reset is performed on the CSPI module, resetting all registers to their
default values.
Software can reset the module using the CONREG[EN] bit; see Section 18.3.3.3, “Control Register
(CONREG).”
18.4.6
Interrupts
Interrupt control provides a way to manage the CSPI FIFOs:
• For transmitting data, software can enable the TXFIFO empty, TXFIFO half, and TXFIFO full
interrupts to maintain the TXFIFO using an interrupt service routine.
• For receiving data, software can enable the RXFIFO ready, RXFIFO half, and RXFIFO full
interrupts to retrieve data from the RXFIFO using an interrupt service routine.
Other interrupt sources can be used to control or debug the SPI bursts:
• The transfer-completed interrupt means that there is no data left in the TXFIFO and that the data
in the Shift register has been shifted out.
• The RXFIFO overflow interrupt means that the RXFIFO received more than 8 words and will not
accept any other words.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
18-22
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Figure 18-21 shows a program sequence of SPI bursts using interrupt control.
.
Enable CSPI
Enable interrupts
Fill TXFIFO using interrupt service routine
Enable XCH
Retrieve data using interrupt service routine
Wait until all needed data are transferred
TC interrupt
TC clear by writing 1
Done
Figure 18-21. Program Sequence of SPI Burst Using Interrupt Control
18.4.7
DMA
DMA control provides another method to utilize the FIFOs in the CSPI module. By using DMA request
and acknowledge signals, larger amounts of data can be transferred, and will reduce interrupts and host
processor loading. When the appropriate conditions are matched, the module will send out a DMA request,
and the DMA can deal with the following conditions:
• TXFIFO empty
• TXFIFO half
• RXFIFO half
• RXFIFO full
Figure 18-22 shows a program sequence of SPI bursts using DMA control.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
18-23
Configurable Serial Peripheral Interface (CSPI)
Enable CSPI
Enable DMA
Fill TXFIFO using DMA
Enable XCH
Wait until all needed data is transferred
Retrieve data using DMA
TC interrupt
Done
Figure 18-22. Program Sequence of SPI Burst Using DMA
18.4.8
Byte Order
Software can swap bytes for receive data using the TESTREG[SWAP] bit; see Section 18.3.3.8, “Test
Control Register (TESTREG).”
18.5
Initialization
This section provides initialization information for CSPI.
To initialize the module:
1. Clear the EN bit in CONREG to reset the module.
2. Enable the clocks for CSPI.
3. Set the EN bit in CONREG to put CSPI out of reset.
4. Configure corresponding IOMUX for CSPI external signals.
5. Configure registers of CSPI properly according to the specifications of the external SPI device.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
18-24
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
18.6
Applications
Figure 18-23 shows two flowcharts for the master and slave mode of operations supported by the CSPI
module.
Master Mode
Slave Mode
Configure CONREG
Configure CONREG
Configure INTREG (optional)
Fill TXFIFO
Configure DMAREG (optional)
Wait for RXFIFO Interrupt
(Ready, Half, Full)
Configure PERIODREG (optional)
Read Data from RXFIFO
Fill TXFIFO
Transfer Completed
Set XCH bit
Poll XCH bit
or wait for TC interrupt
Read Data from RXFIFO
Transfer Completed
Figure 18-23. Flowchart of the CSPI Operation
Example 18-1 shows example code of CSPI operation using ARM instructions.
Example 18-1. CSPI Operation using ARM Instructions
LDR R0, =CSPI_BASE_ADDRESS
; Load
CSPI
LDR R1, =0x01F00003
; Master Mode, 32-bit transaction
Base Address to R0
STR R1, [R0, #0x08]
LDR R1, =0x00000011
; Enable RXFIFO half and TXFIFO empty
STR R1, [R0, #0x0C]
; interrupt (Alternatively with DMA Mode)
LDR R1, =0x00000011
; Enable RXFIFO half and TXFIFO empty
STR R1, [R0, #0x10]
; DMA (Alternatively with interrupt)
LDR R5, =0x05
; R5 as number of words to be transferred.
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Configurable Serial Peripheral Interface (CSPI)
LDR R1, =0x11111111
; R1 as increment to generate the data.
LDR R2, =0x12345678
; R2 load the data to be transferred.
STR R2, [R2,#0x04]
; Store data into TXFIFO.
ADD R2, R2, R1
; Generating next data to be transferred.
SUB R5, R5, #1
; Decrease the R5.
CMP R5, #0x00
; Check R5 if it is zero.
BNE Loop_00
; Loop until R5 is zero.
LDR R1, =0x01F00007
; set XCH bit to start transaction.
Loop_00
STR R1, [R0, #0x08]
Loop_01
LDR R1, [R0, #0x08]
; check XCH bit if it is cleared.
LDR R2, =0x00000004
AND R1, R2, R1
CMP R1, #0x00
BEQ PASS_00
; if XCH bit is cleared then finish.
B Loop_01
; if it isn’t cleared then continue loop
LDR R1, [R0, #0x00]
; Read data from RXFIFO.
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Chapter 19
Embedded Cross Trigger (ECT)
19.1
Introduction
Embedded cross trigger (ECT) is a new IP for real-time debug purpose. It is a programmable matrix
allowing several sub-systems to interact with each other. ECT receives signals required for debugging
purpose (from cores, peripherals, busses, external inputs, etc.) and propagates them (propagation
programmed through software) to the different debug resources available within the SoC. Those debug
resources are: module with time stamping capability, module with profiling capability, real-time tracer,
debug interrupts, muxing at SoC level.
ECT allows sharing of debug resources between Cores and IPs from different domains.
ECT is based on a ARM. IP, delivered in the ETK11 kit. Note that information given into this document
are in part extracted from the Embedded Cross Trigger Technical Reference Manual [1] provided by ARM
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19-1
Embedded Cross Trigger (ECT)
Trigger
outputs
Trigger
inputs
IPS
interface
8
8
ECT
AHB IF
OR
EXTENDED_CTI 1
4
control reg
mapping
8 ECT_CTI
8
4
Channel interface 1
EXTENDED_CTI 2
CTM
IPS to AHB
IPS to AHB
WRAPPER
Trigger 8
outputs
8
4
ECT_CTI
8
mapping
OR
Channel interface 2
control reg
8
Channel interface 0
Trigger
inputs
IPS
interface
AHB IF
AHB IF
4
control reg
4
8 Trigger
8
ECT_CTI
4
OR
mapping
8
WRAPPER
IPS
interface
IPS to AHB
WRAPPER
inputs
8 Trigger
outputs
EXTENDED_CTI 0
Channel interface 3
4
4
AHB IF
8 ECT_CTI
WRAPPER
8
Trigger
outputs
8
Trigger
inputs
IPS to AHB
mapping
8
control reg
OR
ARM_CTI
IPS
interface
Figure 19-1. ECT Block Diagram
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Embedded Cross Trigger (ECT)
19.2
Overview
ECT is a key module in term of multi-cores and multi-IPs debug strategy:
•
multi-Cores: ECT can propagate an event from one core to another one
•
multi-IPs: all the IPs inside one domain can share the same debug resources (no need to duplicate
counters, real-time tracers, etc.)
Initially, ECT is a complete module delivered by ARM Ltd. and is made of one Cross Trigger Matrix
(CTM) and 2 Cross Trigger Interfaces (CTIs). But, as more trigger inputs/outputs were required for SoC
debugging, 4 cross trigger interfaces were needed.
Thus, in order to support all projects with a common ECT architecture and as ARM11 platform already
includes a CTI whereas ARM9 platform does not, ECT will have 3 Extended Cross Trigger Interfaces
(EXTENDED_CTI = extension of the CTI delivered by ARM Ltd) and 1 Cross Trigger Matrix (CTM),
as follows:
•
For projects using an ARM9 platform, a fourth CTI will be delivered as a stand-alone block and this
block will be plugged between ECT and ARM9 (reason why, in figure 1.1, ARM_CTI appears
outside the ECT),
•
For projects using an ARM11 platform, ECT will be directly plugged to the Cross Trigger Interface
that resides in ARM11 platform.
Thus, ECT is made of 3 Extended Cross Trigger Interfaces (EXTENDED_CTI) and 1 Cross Trigger
Matrix (CTM), a follows:
• EXTENDED_CTI includes the following:
— A WRAPPER used to synchronize/hold the trigger events coming from asynchronous clock
domains and to reformat the signals if necessary (pulse to level, inversion, etc.)
— ECT_CTI (IP delivered by ARM Ltd.). This block combines and maps the trigger requests and
broadcasts them to the CTM as channel events. The mapping of the 8 trigger inputs onto the 4
channel inputs and the mapping of the 4 channel outputs onto the 8 trigger outputs are
programmed through memory-mapped registers.
— an IPS to AHB bridge to interface with the AHB interface of ECT_CTI
• CTM includes:
— ECT_CTM (IP delivered by ARM Ltd.). This block is a matrix providing 4 channel interfaces
(4 channel inputs and 4 channel outputs per interface).
— A wrapper to handle the CTM clock gating and additional observability functions.
19.3
Features
ECT includes the following features:
• 3 trigger interfaces with 8 trigger inputs/8 trigger outputs each
• 1 channel interface with 4 channel inputs/4 channel outputs
• hand-shaking and synchronization interfaces that can be bypassed for lower latency in case of
synchronous sub-systems
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19-3
Embedded Cross Trigger (ECT)
•
•
•
•
•
19.4
trigger signals reformatting
application trigger: a trigger can be applied onto a channel by software
memory-mapped register control
secured register access
test registers for internal test and SoC integration test
Modes of Operation
ECT has the following modes of operation:
• Disabled mode: all the mapping trigger inputs to channel inputs and trigger outputs to channel
outputs is disabled.
• Enabled mode: the ECT receives trigger events and propagates those events to the selected trigger
outputs (propagation programmed through some memory-mapped registers).
Because the ECT is accessed as a memory-mapped device and as it can be used to generate intrusive debug
events, ECT should only be used during product development and its use in a production system should
be prevented.
The following mechanisms are implemented to protect the ECT from unwanted accesses:
• Debug enable: two enable signals must be set to enable the ECT. The first one is software
programmable through CTICONTROL register and the second one is an hardware input
(ect_dbg_en).
• Access: a suitable key (32-bit word) has to be presented to the CTILOCK register to allow write
access to the other EXTENDED_CTI registers.
• Privileged access: the CTIPROTECTION register restricts access to the configuration registers so
that only privileged (supervisor mode) code can access them. In protection mode, user access is
effectively masked, so any read from the ECT returns an inactive state.
19.5
Signals Description
19.6
Overview
ECT is a matrix that can receive signals (trigger inputs) from any point in SoC: cores, peripherals, busses,
external inputs, etc. In the same way, ECT can propagate signals (trigger outputs) anywhere: essentially to
debug resources but it could go to an external output through some I/O muxing. Indeed, one can assign
any ECT trigger input/output to any signals.
The list of SoC signals connected to ECT trigger inputs/outputs should be specified in each project debug
specification.
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Embedded Cross Trigger (ECT)
Table 19-1. ECT Signals
Signal
Type
Signal Name
Signal Description
EXTENDED_CTI_0
SYSTEM SIGNALS
ipg_clk_0
Input
Global functional clock
ipg_clk_s_0
Input
IP bus clock
cti_trig_in_clk_0[7:0]
Input
Trigger input clocks
cti_trig_out_clk_0[7:0]
Input
Trigger output clocks
ipg_hard_async_reset_b_0
Input
IP bus registers reset
cti_trig_in_0[7:0]
Input
Trigger inputs
cti_trig_out_0[7:0]
Output
Trigger outputs
CONTROL SIGNALS
cti_bus_if_sync_byp_0
Input
Bypass synchronization mechanism between the bus interface and the CTI
control registers
trig_in_if_sync_byp_0[7:0]
Input
Bypass trigger input interface synchronization (wrapper <-> CTI)
trig_out_if_sync_byp_0[7:0]
Input
Bypass trigger output interface synchronization (wrapper <-> CTI)
cti_chan_out_hs_byp_0[3:0]
Input
Disable CTI channel output holder (CTI-> CTM)
cti_trig_out_hs_byp_0[7:0]
Input
Disable CTI trigger output holder (CTI -> wrapper)
inv_trig_in_0[7:0]
Input
Enable trigger input inversion
samp_trig_in_0[7:0]
Input
Enable trigger input sampling
trig_in_pulse_sel_0[7:0]
Input
Enable trigger input reshaping into a pulse
wrp_trig_in_hs_byp_0[7:0]
Input
Disable trigger input holder (wrapper -> CTI)
inv_trig_out_0[7:0]
Input
Enable trigger output inversion
samp_trig_out_0[7:0]
Input
Enable trigger output sampling
trig_out_pulse_sel_0[7:0]
Input
Enable trigger output reshaping into a pulse
wrp_trig_out_ack_byp_0[7:0]
Input
Disable trigger output acknowledgement (wrapper -> CTI)
IP BUS LINE SIGNALS
ips_addr_0[11:2]
Input
IP bus address
ips_wdata_0[31:0]
Input
IP bus write data
ips_byte_31_24_0
Input
IP bus byte enable
ips_byte_23_16_0
Input
IP bus byte enable
ips_byte_15_8_0
Input
IP bus byte enable
ips_byte_7_0_0
Input
IP bus byte enable
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Embedded Cross Trigger (ECT)
Table 19-1. ECT Signals (continued)
Signal
Type
Signal Name
Signal Description
ips_rwb_0
Input
IP bus read/write control
ips_module_en_0
Input
IP bus device select
ips_supervisor_access_0
Input
IP bus supervisor access
ips_rdata_0[31:0]
Output
IP bus read data
ips_xfr_wait_0
Output
IP bus transfer wait signal
ips_xfr_error_0
Output
IP bus transfer error signal
EXTENDED_CTI_1
SYSTEM SIGNALS
ipg_clk_1
Input
Global functional clock
ipg_clk_s_1
Input
IP bus clock
cti_trig_in_clk_1[7:0]
Input
Trigger input clocks
cti_trig_out_clk_1[7:0]
Input
Trigger output clocks
ipg_hard_async_reset_b_1
Input
IP bus registers reset
cti_trig_in_1[7:0]
Input
Trigger inputs
cti_trig_out_1[7:0]
Output
Trigger outputs
CONTROL SIGNALS
cti_bus_if_sync_byp_1
Input
Bypass synchronization mechanism between the bus interface and the CTI
control registers
trig_in_if_sync_byp_1[7:0]
Input
Bypass trigger input interface synchronization (wrapper <-> CTI)
trig_out_if_sync_byp_1[7:0]
Input
Bypass trigger output interface synchronization (wrapper <-> CTI)
cti_chan_out_hs_byp_1[3:0]
Input
Disable CTI channel output holder (CTI-> CTM)
cti_trig_out_hs_byp_1[7:0]
Input
Disable CTI trigger output holder (CTI -> wrapper)
inv_trig_in_1[7:0]
Input
Enable trigger input inversion
samp_trig_in_1[7:0]
Input
Enable trigger input sampling
trig_in_pulse_sel_1[7:0]
Input
Enable trigger input reshaping into a pulse
wrp_trig_in_hs_byp_1[7:0]
Input
Disable trigger input holder (wrapper -> CTI)
inv_trig_out_1[7:0]
Input
Enable trigger output inversion
samp_trig_out_1[7:0]
Input
Enable trigger output sampling
trig_out_pulse_sel_1[7:0]
Input
Enable trigger output reshaping into a pulse
wrp_trig_out_ack_byp_1[7:0]
Input
Disable trigger output acknowledgement (wrapper -> CTI)
IP BUS LINE SIGNALS
ips_addr_1[11:2]
Input
IP bus address
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Embedded Cross Trigger (ECT)
Table 19-1. ECT Signals (continued)
Signal
Type
Signal Name
Signal Description
ips_wdata_1[31:0]
Input
IP bus write data
ips_byte_31_24_1
Input
IP bus byte enable
ips_byte_23_16_1
Input
IP bus byte enable
ips_byte_15_8_1
Input
IP bus byte enable
ips_byte_7_0_1
Input
IP bus byte enable
ips_rwb_1
Input
IP bus read/write control
ips_module_en_1
Input
IP bus device select
ips_supervisor_access_1
Input
IP bus supervisor access
ips_rdata_1[31:0]
Output
IP bus read data
ips_xfr_wait_1
Output
IP bus transfer wait signal
ips_xfr_error_1
Output
IP bus transfer error signal
EXTENDED_CTI_2
SYSTEM SIGNALS
ipg_clk_2
Input
Global functional clock
ipg_clk_s_2
Input
IP bus clock
cti_trig_in_clk_2[7:0]
Input
Trigger input clocks
cti_trig_out_clk_2[7:0]
Input
Trigger output clocks
ipg_hard_async_reset_b_2
Input
IP bus registers reset
cti_trig_in_2[7:0]
Input
Trigger inputs
cti_trig_out_2[7:0]
Output
Trigger outputs
CONTROL SIGNALS
cti_bus_if_sync_byp_2
Input
Bypass synchronization mechanism between the bus interface and the CTI
control registers
trig_in_if_sync_byp_2[7:0]
Input
Bypass trigger input interface synchronization (wrapper <-> CTI)
trig_out_if_sync_byp_2[7:0]
Input
Bypass trigger output interface synchronization (wrapper <-> CTI)
cti_chan_out_hs_byp_2[3:0]
Input
Disable CTI channel output holder (CTI-> CTM)
cti_trig_out_hs_byp_2[7:0]
Input
Disable CTI trigger output holder (CTI -> wrapper)
inv_trig_in_2[7:0]
Input
Enable trigger input inversion
samp_trig_in_2[7:0]
Input
Enable trigger input sampling
trig_in_pulse_sel_2[7:0]
Input
Enable trigger input reshaping into a pulse
wrp_trig_in_hs_byp_2[7:0]
Input
Disable trigger input holder (wrapper -> CTI)
inv_trig_out_2[7:0]
Input
Enable trigger output inversion
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Embedded Cross Trigger (ECT)
Table 19-1. ECT Signals (continued)
Signal
Type
Signal Name
Signal Description
samp_trig_out_2[7:0]
Input
Enable trigger output sampling
trig_out_pulse_sel_2[7:0]
Input
Enable trigger output reshaping into a pulse
wrp_trig_out_ack_byp_2[7:0]
Input
Disable trigger output acknowledgement (wrapper -> CTI)
IP BUS LINE SIGNALS
ips_addr_2[11:2]
Input
IP bus address
ips_wdata_2[31:0]
Input
IP bus write data
ips_byte_31_24_2
Input
IP bus byte enable
ips_byte_23_16_2
Input
IP bus byte enable
ips_byte_15_8_2
Input
IP bus byte enable
ips_byte_7_0_2
Input
IP bus byte enable
ips_rwb_2
Input
IP bus read/write control
ips_module_en_2
Input
IP bus device select
ips_supervisor_access_2
Input
IP bus supervisor access
ips_rdata_2[31:0]
Output
IP bus read data
ips_xfr_wait_2
Output
IP bus transfer wait signal
ips_xfr_error_2
Output
IP bus transfer error signal
CTM SIGNALS
SYSTEM SIGNALS
ctm_clk
Input
System clock
ctm_chan_in_3[3:0]
input
Channel input port from CTI 3 (ARM_CTI)
ctm_chan_out_ack_3[3:0]
Input
Channel output acknowledge from CTI 3 (ARM_CTI)
ctm_chan_out_3[3:0]
Output
Channel output port to CTI 3 (ARM_CTI)
ctm_chan_in_ack_3[3:0]
Output
Channel input acknowledge to CTI 3 (ARM_CTI)
ctm_lines[3:0]
Output
System lines
CONTROL SIGNALS
ctm_chan_out_hs_byp_0[3:0]
Input
Disable CTM channel output holder for port 0 (CTM->CTI0)
ctm_chan_out_hs_byp_1[3:0]
Input
Disable CTM channel output holder for port 1 (CTM->CTI1)
ctm_chan_out_hs_byp_2[3:0]
Input
Disable CTM channel output holder for port 2 (CTM->CTI2)
ctm_chan_out_hs_byp_3[3:0]
Input
Disable CTM channel output holder for port 3 (CTM->ARM_CTI)
ci_sync_byp_0
Input
Bypass channel interface synchronization for port 0 (CTI0 <-> CTM)
ci_sync_byp_1
Input
Bypass channel interface synchronization for port 1 (CTI1 <-> CTM)
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Embedded Cross Trigger (ECT)
Table 19-1. ECT Signals (continued)
Signal Name
Signal
Type
Signal Description
ci_sync_byp_2
Input
Bypass channel interface synchronization for port 2 (CTI2 <-> CTM)
ci_sync_byp_3
Input
Bypass channel interface synchronization for port 3 (ARM_CTI <-> CTM)
GLOBAL SIGNALS
ect_reset_b
Input
Global reset
ect_dbg_en
Input
Debug enable
ect_clk_en
Output
19.7
Functional clock enable
Detailed Signal Descriptions
19.7.1
19.7.1.1
EXTENDED_CTI_X signals (X = 0,1,2)
ipg_clk_X (input)
ipg_clk_X (input) is used to clock all EXTENDED_CTI_X registers except wrapper and bus interface,
which excludes IPS to AHB module, AHB interface block and wrapper registers.
19.7.1.2
ipg_clk_s_X (input)
ipg_clk_s_X (input) is used to clock all bus interface registers, which includes IPS to AHB module and
AHB interface block.
19.7.1.3
cti_trig_in_clk_X [7:0] (input)
cti_trig_in_clk_X [7:0] (input) is the clock of each trigger input, and is used to clock wrapper registers
related to each trigger input.
19.7.1.4
cti_trig_out_clk_X [7:0] (output)
cti_trig_out_clk_X [7:0] (output) is the clock of each trigger output, and is used to clock wrapper registers
related to each trigger output.
19.7.1.5
ipg_hard_async_reset_b_X (input)
ipg_hard_async_reset_b_X (input) is the asynchronous reset, active low, and is used to reset all bus
interface registers, which includes IPS to AHB module and AHB interface block.
19.7.1.6
cti_trig_in_X [7:0] (input)
cti_trig_in_X [7:0] (input) triggers inputs from the SoC.
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Embedded Cross Trigger (ECT)
19.7.1.7
cti_trig_out_X [7:0] (output)
cti_trig_out_X [7:0] (output) triggers outputs to the SoC.
19.7.1.8
cti_bus_if_sync_byp_X (input)
cti_bus_if_sync_byp_X (input) is the bypass synchronization between the bus interface (IPS to AHB +
AHB interface) and ECT_CTI control registers. Tie high when both sides of the interface are synchronous
to bypass the synchronization circuitry.
19.7.1.9
trig_in_if_sync_byp_X [7:0] (input)
Tie trig_in_if_sync_byp_X [7:0] (input) high when ipg_clk_X and trigger input clocks are synchronous to
bypass the synchronization circuitry.
19.7.1.10 trig_out_if_sync_byp_X [7:0] (input)
Tie trig_out_if_sync_byp_X [7:0] (input) high when ipg_clk_X and trigger output clocks are synchronous
to bypass the synchronization circuitry.
19.7.1.11 cti_chan_out_hs_byp_X [3:0] (input)
Tie cti_chan_out_hs_byp_X [3:0] (input) high to disable the holder circuitry on ECT_CTI channel output
going to CTM.
19.7.1.12 cti_trig_out_hs_byp_X [7:0] (input)
Tie cti_trig_out_hs_byp_X [7:0] (input) high to disable the holder circuitry on ECT_CTI trigger output
going to wrapper. When high, both hardware acknowledgement from wrapper and software
acknowledgement from CTIIINTACK register are disabled.
19.7.1.13 inv_trig_in_X [7:0] (input)
Tie inv_trig_in_X [7:0] (input) high to invert ECT trigger input.
19.7.1.14 samp_trig_in_X [7:0] (input)
Tie samp_trig_in_X [7:0] (input) high to sample ECT trigger input with its corresponding clock
(cti_trig_in_clk_X [7:0]).
19.7.1.15 trig_in_pulse_sel_X [7:0] (input)
Tie trig_in_pulse_sel_X [7:0] (input) high to convert ECT trigger input into a pulse.
19.7.1.16 wrp_trig_in_hs_byp_X [7:0] (input)
Tie wrp_trig_in_hs_byp_X [7:0] (input) high to disable the holder circuitry on the trigger input going out
from wrapper to ECT_CTI
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Embedded Cross Trigger (ECT)
19.7.1.17 inv_trig_out_X [7:0] (input)
Tie inv_trig_out_X [7:0] (input) high to invert ECT trigger output.
19.7.1.18 samp_trig_out_X [7:0] (input)
Tie samp_trig_out_X [7:0] (input) high to sample ECT trigger output with its corresponding clock
(cti_trig_out_clk_X [7:0]).
19.7.1.19 trig_out_pulse_sel_X [7:0] (input)
Tie trig_out_pulse_sel_X [7:0] (input) high to convert ECT trigger output into a pulse.
19.7.1.20 wrp_trig_out_ack_byp_X [7:0] (input)
Tie wrp_trig_out_ack_byp_X [7:0] (input) high to disable the hardware trigger output acknowledgement
going out from wrapper to ECT_CTI.
19.7.2
19.7.2.1
CTM signals (X= 0,1,2 / Y = 0,1,2,3)
ctm_clk (input)
ctm_clk (input) is the CTM clock, and is used to clock all CTM registers.
19.7.2.2
ctm_chan_in_3 [3:0] (input)
ctm_chan_in_3 [3:0] (input) is the channel input port from CTI 3 (ARM_CTI).
19.7.2.3
ctm_chan_out_ack_3 [3:0] (input)
ctm_chan_out_ack_3 [3:0] (input) is the channel output acknowledge from CTI 3 (ARM_CTI).
19.7.2.4
ctm_chan_out_3 [3:0] (output)
ctm_chan_out_3 [3:0] (output) is the channel output port to CTI 3 (ARM_CTI).
19.7.2.5
ctm_chan_in_ack_3 [3:0] (output)
ctm_chan_in_ack_3 [3:0] (output) is the channel input acknowledge to CTI 3 (ARM_CTI).
19.7.2.6
ctm_lines [3:0] (output)
Each bit reflects corresponding channel activity out of CTM. ctm_lines [3:0] (output) is routed to IOMUX
for debug purpose.
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Embedded Cross Trigger (ECT)
19.7.2.7
ctm_chan_out_hs_byp_Y [3:0] (input)
Tie ctm_chan_out_hs_byp_Y [3:0] (input) high to disable the holder circuitry on CTM channel output
going to EXTENDED_CTI_X/ ARM_CTI.
19.7.2.8
ci_sync_byp_Y (input)
ci_sync_byp_Y (input) is the bypass synchronization on the channel interface CTM <->
EXTENDED_CTI_X / ARM_CTI. Tie high when both sides of the channel interface are synchronous to
bypass the synchronization circuitry.
19.7.3
Global signals (X = 0,1,2)
19.7.3.1
ect_reset_b (input)
ect_reset_b (input) is the asynchronous reset, active low. Used to reset all CTM registers, all
EXTENDED_CTI_X registers except bus interface, which excludes IPS to AHB module & AHB interface
block.
19.7.3.2
ect_dbg_en (input)
ect_dbg_en (input) is the debug enable signal. When 0, the cross trigger interface is disabled, no trigger
can be generated or received and clocks should be disabled to avoid any power consumption (see
ect_clk_en signal). When 0, all trigger outputs and CTM system lines are gated off.
19.7.3.3
ect_clk_en (output)
ect_clk_en (output) is the clock enable signal. This signal is a copy of ect_dbg_en. It should go to the clock
reset module and should be used to enable or not EXTENDED_CTI_X clocks (ipg_clk_X), trigger input
clocks (cti_trig_in_clk_X [7:0]), trigger output clocks (cti_trig_out_clk_X [7:0]) and CTM clock
(ctm_clk).
Note that EXTENDED_CTI IP bus clocks (ipg_clk_s_X) should not be gated with this signal.
19.8
Memory Map/Register Definition
Only EXTENDED_CTI includes memory mapped registers; CTM cannot be configured by software.
The following subsections describe memory mapped registers for only one Extended_CTI. All
Extended_CTI have the same memory mapped register structure.
Because Extended_CTIs stand on different IP busses or have different base addresses on the same bus, all
register addresses are referenced with a $BASE<N><N> variable.
The following applies to all registers:
•
•
•
Reserved or unused bits of registers must be written to 0, an ignore on read
All registers bits are reset to 0 unless otherwise stated in the text
only word accesses are allowed; an IP xfr error is generated if any other size is attempted.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
19-12
Freescale Semiconductor
Embedded Cross Trigger (ECT)
All registers can be accessed even if EXTENDED_CTI is software disabled (GLBEN is low). However,
if ect_dbg_en is low and ect_clk_en is used for clock gating, ECT clocks will be off. In this case, neither
read nor write access is allowed, and any attempt will generate an ips_xfr_error.
19.9
Register Summary
KEY:
Always 1
Reads
One
Always 0
Reads
Zero
Read/
Write bit
Bit
Read- bit
Only
Bit
WriteOnly
Bit bit
Write bit
1 to
Clear w1c
Self- 0
Clear
Bit bit
N/A
Table 19-2. CTI Register Summary
Name
CTICONTROL
($BASE<N> +
0x000)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GLBE
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
CTISTATUS
($BASE<N> +
0x004)
R
W
R
DGBE LOCK
N
ED
W
CTILOCK
($BASE<N> +
0x008)
R
W
LOCKKEY[31:16]
R
W
LOCKKEY[15:0]
CTIPROTECTION R
($BASE<N>
W
+0x00C)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PROT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
CTIINTACK
($BASE<N> +
0x010)
R
W
R
W
CTIAPPSET
($BASE<N>
+0x014)
R
INTACK[7:0]
0
W
R
APPSET[3:0]
W
CTIAPPCLEAR R
($BASE<N>
W
+0x018)
0
0
0
0
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Freescale Semiconductor
19-13
Embedded Cross Trigger (ECT)
Table 19-2. CTI Register Summary (continued)
Name
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
APPCLEAR[3:0]
CTIAPPPULSE R
($BASE<N> +
W
0x01C)
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CTITRIGINSTA- R
TUS
($BASE<N>
W
+0x130)
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CTICHINSTATUS R
($BASE<N> +
W
0x138)
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
CTICHOUTSTA- R
TUS
($BASE<N> + W
0x13C)
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
CHOUTSTATUS[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
CTIINENn1
($BASE<N> +
0x020 + n*4)
R
0
0
APPPULSE[3:0]
0
0
0
0
W
R
TRIGINEN[3:0]
W
CTIOUTENn2
($BASE<N> +
0x0A0 + n*4)
0
R
0
0
0
0
W
R
TRIGOUTEN[3:0]
W
0
0
0
0
0
0
0
0
TRIGINSTATUS[7:0]
W
CTITRIGOUTSTATUS
($BASE<N> +
0x134)
R
0
0
0
0
0
0
W
R
TRIGOUTSTATUS[7:0]
W
0
0
CHINSTATUS[3:0]
W
0
0
0
W
CTIITCR
($BASE<N>
+0x200)
R
0
0
W
R
W
TEST_MOD
E[1:0]
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Freescale Semiconductor
Embedded Cross Trigger (ECT)
Table 19-2. CTI Register Summary (continued)
Name
CTIITIP0
($BASE<N> +
0x204)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
ECTTRIGIN[7:0]
W
CTIITIP1
($BASE<N> +
0x208)
R
0
W
R
CTICHIN[3:0]
W
CTIITIP2
($BASE<N> +
0x20C)
R
R
R
R
0
0
0
ECTCHOUTACK[3:0]
0
0
0
0
0
0
ECTTRIGOUT[7:0]
W
R
0
0
W
R
CTICHOUT[3:0]
W
R
0
0
0
0
0
0
W
R
ECTTRIGINACK[7:0]
W
CTITIOP3
($BASE<N> +
0x220)
0
W
R
CTITIOP2
($BASE<N> +
0x21C)
0
W
W
CTITIOP1
($BASE<N> +
0x218)
0
ECTTRIGOUTACK[7:0]
W
CTITIOP0
($BASE<N> +
0x214)
0
W
R
CTIITIP3
($BASE<N> +
0x210)
0
R
0
0
W
R
CTICHINACK[3:0]
W
CTIPERIPHID0 R
($BASE<N> +
W
0xFE0)
0
0
0
0
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Freescale Semiconductor
19-15
Embedded Cross Trigger (ECT)
Table 19-2. CTI Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
CTIPERIPHID1 R
($BASE<N> +
W
0xFE4)
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
CTIPERIPHID2 R
($BASE<N> +
W
0xFE8)
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
CTIPERIPHID3 R
($BASE<N> +
W
0xFEC)
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
Partnumber0[7:0]
W
0
0
0
0
0
Designer0[3:0]
Partnumber1[3:0]
W
0
0
0
0
0
Revision[3:0]
0
0
0
Designer1[3:0]
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Configuration[7:0]
W
CTIPCELLID0
($BASE<N> +
0xFF0)
R
0
0
0
0
0
W
R
CTIPCELLID0[7:0]
W
CTIPCELLID1
($BASE<N> +
0xFF4)
R
0
0
0
0
0
0
W
R
CTIPCELLID1[7:0]
W
CTIPCELLID2
($BASE<N> +
0xFF8)
R
0
0
0
0
0
0
W
R
CTIPCELLID2[7:0]
W
CTIPCELLID3
($BASE<N> +
0xFFC)
R
0
0
0
0
0
0
W
R
CTIPCELLID3[7:0]
W
1n
2
= 0-7
n = 0-7
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Freescale Semiconductor
Embedded Cross Trigger (ECT)
19.10 Register Descriptions
Table 19-3. Register Terms
Term
Description
Grey bit
Unimplemented bit; always reads as zero; writing has no effect.
Access
S
Supervisor mode only
-
Supervisor or user mode
Type
r
Read only. Writing to this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change a bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by hardware in some fashion other than reset.
w1c
A status bit that can be read and cleared by writing a logic 1.
slfclr
Self-clearing bit. Writing a 1 has some effect on module, but it always reads as a 0.
Reset
0
Resets to a logic 0.
1
Resets to a logic 1.
u
Unaffected by reset.
?
Reset state is unknown.
19.10.1 CTICONTROL Register
The CTICONTROL register, shown in Figure 19-2, enables the CTI.
Address $BASE<N> + 0x000
Wait State: >3
Access: Read/Write
31
R 0
1
0
0
0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0
GLBEN
All zeros
Figure 19-2. CTI Control Register (CTICONTROL)
Table 19-4 describes the CTICONTROL register.
Table 19-4. CTICONTROL Register Field Descriptions
Bits
31–1
0
GLBEN
Description
Reserved
Enables or Disables the ECT
0 Enabled
1 Disabled (When disabled, all cross triggering mapping logic functionality is disabled for this
processor)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
19-17
Embedded Cross Trigger (ECT)
19.10.2 CTISTATUS Register
The CTISTATUS register, shown in Figure 19-3, provides the locked and enable status of the CTI.
Address $BASE<N> + 0x004
Wait State: >3
Access: Read only
31
R 0
2
1
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DGBEN LOCKED
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0
?
1
Figure 19-3. CTI Status Register (CTISTATUS)
Table 19-5 describes the CTISTATUS register.
Table 19-5. CTISTATUS Register Field Descriptions
Field
31–2
Description
Reserved
1
Shows the status of TI enable—reset values depends on ECTDBGEN port
DGBEN 0 Interfaces are enabled
1 Interfaces are disabled (even if CTI is disabled, register may be read)
0
Enables or Disables the ECT
LOCKED 0 Access to CTI is not locked
1 Access to CTI is locked
19.10.3 CTILOCK Register
The CTILOCK register, shown in Figure 19-4, enables or disables all other register write access by
providing a LOCKED mode for the AHB interface. When the AHB interface is locked, write accesses to
the CTI registers except CTILOCK are ignored.
To allow write access, a LOCKKEY value, 0x0ACCE550, is written into CTILOCK. All other values lock
write access.
Address $BASE<N> + 0x008
Wait State: >3
Access: Write only
31
0
R
W
Reset
LOCKKEY
All zeros
Figure 19-4. CTI Lock Register (CTILOCK)
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
19-18
Freescale Semiconductor
Embedded Cross Trigger (ECT)
Table 19-6 describes the CTILOCK register.
Table 19-6. CTILOCK Register Field Descriptions
Bits
Name
31–0
Description
LOCKKEY Lock key
0x0ACCE550—Write Access to all other register is allowed
Else—Access locked
19.10.4 CTIPROTECTION Register
The CTIPROTECTION register, shown in Figure 19-5, enables or disables protected register access.
When enabled, only privileged mode (supervisor) accesses (read and write) can access CTI registers: that
is when HPROT[1] is set high for the current transfer. If an access is made in user mode, all registers return
0.
When disabled, both user and privileged mode can access CTI registers, except for CTIPROTECTION
register that can only be accessed in privileged mode.
Note that after reset, both user and supervisor access modes are allowed (except for CTIPROTECTION
register that can only be accessed in privileged mode).
Address $BASE<N> + 0x00C
Wait State: >3
Access: Read/Write
31
R 0
1
0
0
0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0
PROT
All zeros
Figure 19-5. CTI Protection Register (CTIPROTECTION)
Table 19-7 describes the CTILOCK register.
Table 19-7. CTIPROTECTION Register Field Descriptions
Field
Description
31–1
Reserved
0
PROT
Enables protected mode
0 Protection mode disabled (both supervisor and user access can read/write CTI registers)
1 Protection mode enabled (only supervisor access can read/write CTI registers)
19.10.5 CTIINTACK Register
Any bit written as 1 causes the CTITRIGOUT output to be acknowledged.
This feature should be used when trigger output is used as an interrupt. In this case, the trigger output stay
active until it is software acknowledged.
If trigger generator is still active, software acknowledge is kept active until trigger is off.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
19-19
Embedded Cross Trigger (ECT)
Figure 19-6 shows the CTIINTACK register.
Address $BASE<N> + 0x010
Wait State: >3
Access: Write only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
W
INTACK
Reset
All zeros
Figure 19-6. CTI Interrupt Acknowledge Register (CTIINTACK)
Table 19-8 describes the CTIPROTECTION register.
Table 19-8. CTIPROTECTION Register Field Descriptions
Field
31–8
Description
Reserved
7–0
Interrupt acknowledge
INTACK One bit of the register for each CTITRIGOUT
0 Nothing happens
1 CTITRIGOUT is acknowledged
19.10.6 CTIAPPSET Register
A write to the CTIAPPSET register, shown in Figure 19-7, causes a channel event to be raised,
corresponding to the bit written to.
Address $BASE<N> + 0x014
Wait State: >3
Access: Read/Write
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
3
2
1
0
APPSET
All zeros
Figure 19-7. CTI Application Trigger Set Register (CTIAPPSET)
Table 19-9 describes the CTIAPPSET register.
Table 19-9. CTIAPPSET Register Field Descriptions
Field
31–4
Description
Reserved
3–0
Setting a bit high generates a channel event for the selected channel
APPSET Read:
0 Application trigger inactive
1 Application trigger active
Write:
0 No effect
1 Generates channel event
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
19-20
Freescale Semiconductor
Embedded Cross Trigger (ECT)
19.10.7 CTIAPPCLEAR Register
A write to the CTIAPPCLEAR register, shown in Figure 19-8, causes a channel event to be cleared,
corresponding to the bit written to.
Address $BASE<N> + 0x018
Wait State: >3
Access: Write only
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
W
APPCLEAR
Reset
All zeros
Figure 19-8. CTI Application Trigger Clear Register (CTIAPPCLEAR)
Table 19-10 describes the CTIAPPCLEAR register.
Table 19-10. CTIAPPCLEAR Register Field Descriptions
Field
31–4
Description
Reserved
3–0
Clears corresponding bit in the APPSET register
APPCLE 0 No effect
AR
1 Application trigger disabled in the APPSET register
19.10.8 CTIAPPPULSE Register
A write to the CTIAPPPULSE register, shown in Figure 19-9, causes a channel event pulse (one clock
cycle length) to be generated, corresponding to the bit written to.
Address $BASE<N> + 0x01C
Wait State: >3
Access: Write only
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
0
0
3
0
0
APPPULSE
Reset
All zeros
Figure 19-9. CTI Application Pulse Register (CTIAPPPULSE)
Table 19-11 describes the CTIAPPPULSE register.
Table 19-11. CTIAPPPULSE Register Field Descriptions
Field
31–4
Description
Reserved
3–0
Setting a bit high generates a channel event pulse
APPPUL 0 No effect
SE
1 Channel event pulse, 1 clk cycle length
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
19-21
Embedded Cross Trigger (ECT)
19.10.9 CTIINEN0–7 Register
The CTIINEN0–7 registers, shown in Figure 19-10, enable the signalling of an event on (a) CTM
channel(s) when the core issues a trigger (ECTTRIGIN) to the CTI.
There is a register for each of the eight ECTTRIGIN inputs. Within each register, there is one bit for each
of the four channels implemented. These registers do not affect application trigger operations (APPSET
register).
Address $BASE<N> + 0x020+ n*41
Wait State: >3
Access: Read/Write
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
3
0
TRIGINEN
All zeros
Figure 19-10. CTI Trigger to Channel Enable Register 0–7 (CTIINEN0–7)
1
n = 0–7
Table 19-12 describes the CTIINEN0–7 registers.
Table 19-12. CTIINEN0–7 Register Field Descriptions
Field
31–4
Description
Reserved
3–0
Enable a cross trigger event to the corresponding channel when a ECTTRIGIN is activated
TRIGINE 0 Disable
N
1 Enable
Example 19-1.
When TRIGINEN[2] within CTIINEN5 register is set to 1, ECTTRIGIN[5] is mapped onto channel 2.
19.10.10 CTIOUTEN0–7 Register
The CTIOUTEN0–7 registers, shown in Figure 19-11, define which channel(s) can generate a
ECTTRIGOUT output.
There is a register for each of the eight ECTTRIGOUT outputs. Within each register, there is one bit for
each of the four channels implemented. These registers do not affect application trigger operations
(APPSET register).
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Embedded Cross Trigger (ECT)
Address $BASE<N> + 0x0A0 + n*41
Wait State: >3
Access: Read/Write
31
4
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
3
0
TRIGOUTEN
All zeros
Figure 19-11. CTI Channel to Trigger Register 0–7 (CTIOUTEN0–7)
1
n = 0–7
Table 19-13 describes the CTIOUTEN0–7 registers.
Table 19-13. CTIOUTEN0–7 Register Field Descriptions
Field
Description
31–4
Reserved
3–0
TRIGOUTEN
Enable a cross trigger event to the corresponding channel when a ECTTRIGOUT is activated
0 Disable
1 Enable
Example 19-2.
When TRIGINOUT[2] within CTIOUTEN5 register is set to 1, CTICHIN[2] is mapped onto
ECTTRIGOUT[5].
19.10.11 CTITRIGINSTATUS Register
The CTITRIGINSTATUS register, shown in Figure 19-12, provides the status of the ECTTRIGIN inputs.
Address $BASE<N> + 0x130
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
TRIGINSTATUS
W
Reset
All zeros
Figure 19-12. CTI Trigger In Status Register (CTITRIGINSTATUS)
Table 19-14 describes the CTITRIGINSTATUS register.
Table 19-14. CTITRIGINSTATUS Register Field Descriptions
Field
31–8
Description
Reserved
7–0
0 ECTTRIGIN is inactive
TRIGINSTATUS 1 ECTTRIGIN is active
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Embedded Cross Trigger (ECT)
19.10.12 CTITRIGOUTSTATUS Register
The CTITRIGOUTSTATUS register, shown in Figure 19-13, provides the status of the ECTTRIGOUT
outputs.
Address $BASE<N> + 0x134
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
TRIGOUTSTATUS
W
Reset
All zeros
Figure 19-13. CTI Trigger Out Status Register (CTITRIGOUTSTATUS)
Table 19-15 describes the CTITRIGOUTSTATUS register.
Table 19-15. CTITRIGOUTSTATUS Register Field Descriptions
Field
Description
31–8
Reserved
7–0
0 ECTTRIGOUT is inactive
TRIGOUTSTATUS 1 ECTTRIGOUT is active
19.10.13 CTICHINSTATUS Register
The CTICHINSTATUS register, shown in Figure 19-14, provides the status of the CTICHIN inputs.
Address $BASE<N> + 0x138
Wait State: >3
Access: Read only
31
R 0
4
0
0
0 0
0
0 0 0 0 0 0 0 0 0 0 0
0
3
0
0 0 0 0 0 0 0 0 0 0 CTICHINSTATUS
W
Reset
All zeros
Figure 19-14. CTI Channel In Status Register (CTICHINSTATUS)
Table 19-16 describes the CTICHINSTATUS register.
Table 19-16. CTICHINSTATUS Register Field Descriptions
Field
31–4
Description
Reserved
3–0
0 CTICHIN is inactive
CTICHINSTATUS 1 CTICHIN is active
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Embedded Cross Trigger (ECT)
19.10.14 CTICHOUTSTATUS Register
The CTICHOUTSTATUS register, shown in Figure 19-15, provides the status of the CTICHOUT outputs.
Address $BASE<N> + 0x13C
Wait State: >3
Access: Read only
31
4
R 0
0 0 0 0
0
3
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTICHOUTSTATUS
W
Reset
All zeros
Figure 19-15. CTI Channel Out Status Register (CTICHOUTSTATUS)
Table 19-17 describes the CTICHOUTSTATUS register.
Table 19-17. CTICHOUTSTATUS Register Field Descriptions
Field
Description
31–4
Reserved
3–0
CTICHOUTSTATUS
0 CTICHOUT is inactive
1 CTICHOUT is active
19.10.15 CTITCR Register
The CTITCR register, shown in Figure 19-16, is a test controller register to be used only in test mode. This
register controls the input and output test registers.
NOTE
This register is only used in test mode.
Address $BASE<N> + 0x200
Wait State: >3
Access: Read/Write
31
R 0
2
0
0
0 0
0
0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0
W
Reset
0
1
0
CTITCR
All zeros
Figure 19-16. CTI Test Control Register (CTITCR)
Table 19-18 describes the CTITCR register.
Table 19-18. CTITCR Register Field Descriptions
Field
31–2
Description
Reserved
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19-25
Embedded Cross Trigger (ECT)
Table 19-18. CTITCR Register Field Descriptions (continued)
Field
Description
1–0
Test Control Register
CTITCR 00 Normal mode1
01 ITEN2 = 1
10 soc_test3 = 1
11 internal_test4 = 1
Note:
1
Allows capture of all test registers (either input or output)
Forces test register values to be applied (both input and output)
3
Allows capture of all input test registers and forces output test register values to be applied on outputs for soc
integration testing
4
Forces input test register values to be applied on inputs and allows capture of all output test registers for internal
testing
2
19.10.16 CTIITIP0 Register
The CTIITIP0 register, shown in Figure 19-17, is used to control and read the values of the ECTTRIGIN
inputs.
NOTE
This register can only be used in test mode.
Address $BASE<N> + 0x204
Wait State: >3
Access: Read/Write
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
W
Reset
0
CTITIP0
All zeros
Figure 19-17. CTI Input Test Register 0 (CTIITIP0)
Table 19-19 describes the CTIITIP0 register.
Table 19-19. CTIITIP0 Register Field Descriptions
Field
31–8
Description
Reserved
7–0
Write: bypasses ECTTRIGIN input values with new value when ITEN or internal_test are high (cf.
CTITIP0 CTITCR register)
Read: reads its own value when ITEN or internal_test are high, else reads ECTTRIGIN values
19.10.17 CTIITIP1 Register
The CTIITIP1 register, shown in Figure 19-18, is used to control and read the values of the CTICHIN
inputs.
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Embedded Cross Trigger (ECT)
NOTE
This register can only be used in test mode.
Address $BASE<N> + 0x208
Wait State: >3
Access: Read/Write
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
3
0
CTIITIP1
All zeros
Figure 19-18. CTI Input Test Register 1 (CTIITIP1)
Table 19-20 describes the CTIITIP1 register.
Table 19-20. CTIITIP1 Register Field Descriptions
Field
Description
31–4
Reserved
3–0
Write: bypasses CTICHIN input values with new value when ITEN or internal_test are high (cf. CTITCR
CTIITIP1 register)
Read: reads its own value when ITEN or internal_test are high, else reads CTICHIN values
19.10.18 CTIITIP2 Register
The CTIITIP2 register, shown in Figure 19-19, is used to control and read the values of the
ECTTRIGOUTACK inputs.
NOTE
This register can only be used in test mode.
Address $BASE<N> + 0x20C
Wait State: >3
Access: Read/Write
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
W
Reset
0
CTIITIP2
All zeros
Figure 19-19. CTI Input Test Register 2 (CTIITIP2)
Table 19-21 describes the CTIITIP2 register.
Table 19-21. CTIITIP2 Register Field Descriptions
Field
31–8
Description
Reserved
7–0
Write: bypasses ECTTRIGOUTACK input values with new value when ITEN or internal_test are high (cf.
CTIITIP2 CTITCR register)
Read: reads its own value when ITEN or internal_test are high, else reads ECTTRIGOUTACK values
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Embedded Cross Trigger (ECT)
19.10.19 CTIITIP3 Register
The CTIITIP3 register, shown in Figure 19-20, is used to control and read the values of the
CTICHOUTACK inputs.
NOTE
This register can only be used in test mode.
Address $BASE<N> + 0x210
Wait State: >3
Access: Read/Write
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
3
0
CTIITIP3
All zeros
Figure 19-20. CTI Input Test Register 3 (CTIITIP3)
Table 19-22 describes the CTIITIP3 register.
Table 19-22. CTIITIP3 Register Field Descriptions
Field
Description
31–4
Reserved
3–0
Write: bypasses CTICHOUTACK input values with new value when ITEN or internal_test are high (cf.
CTIITIP3 CTITCR register)
Read: reads its own value when ITEN or internal_test are high, else reads CTICHOUTACK values
19.10.20 CTIITOP0 Register
The CTIITOP0 register, shown in Figure 19-21, is used to control and read the values of the
ECTTRIGOUT outputs
NOTE
This register can only be used in test mode.
Offset $BASE<N> + 0x214
Wait State: >3
Access: Read/Write
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
W
Reset
0
CTIITOP0
All zeros
Figure 19-21. CTI Output Test Register 0 (CTIITOP0)
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Embedded Cross Trigger (ECT)
Table 19-23 describes the CTIITOP0 register.
Table 19-23. CTIITOP0 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
CTIITOP0
Write: bypasses ECTTRIGOUT output values with new value when ITEN or soc_test are high (cf.
CTITCR register)
Read: reads its own value when ITEN or soc_test are high, else reads ECTTRIGOUT values
19.10.21 CTIITOP1 Register
The CTIITOP1 register, shown in Figure 19-22, is used to control and read the values of the CTICHOUT
outputs.
NOTE
This register can only be used in test mode.
Address $BASE<N> + 0x218
Wait State: >3
Access: Read/Write
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
3
0
CTIITOP1
All zeros
Figure 19-22. CTI Output Test Register 1 (CTIITOP1)
Table 19-24 describes the CTIITOP1 register.
Table 19-24. CTIITOP1 Register Field Descriptions
Field
31–4
3–0
CTIITOP1
Description
Reserved
Write: bypasses CTICHOUT output values with new value when ITEN or soc_test are high (cf. CTITCR
register)
Read: reads its own value when ITEN or soc_test are high, else reads CTICHOUT values
19.10.22 CTIITOP2 Register
The CTIITOP2 register, shown in Figure 19-23, is used to control and read the values of the
ECTTRIGINACK inputs
NOTE
This register can only be used in test mode.
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Embedded Cross Trigger (ECT)
Address $BASE<N> + 0x21C
Wait State: >3
Access: Read/Write
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
CTIITOP2
W
Reset
All zeros
Figure 19-23. CTI Output Test Register 2 (CTIITOP2)
Table 19-25 describes the CTIITOP2 register.
Table 19-25. CTIITOP2 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
CTIITOP2
Write: bypasses ECTTRIGINACK output values with new value when ITEN or soc_test are high (cf.
CTITCR register
Read: reads its own value when ITEN or soc_test are high, else reads ECTTRIGINACK values
19.10.23 CTIITOP3 Register
The CTIITOP3 register, shown in Figure 19-24, is used to control and read the values of the
CTICHINACK inputs.
NOTE
This register can only be used in test mode.
Address $BASE<N> + 0x220
Wait State: >3
Access: Read/Write
31
R 0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
3
0
CTIITOP3
All zeros
Figure 19-24. CTI Output Test Register 3 (CTIITOP3)
Table 19-26 describes the CTIITOP3 register.
Table 19-26. CTIITOP3 Register Field Descriptions
Field
31–4
3–0
CTIITOP3
Description
Reserved
Write: bypasses CTICHINACK output values with new value when ITEN or soc_test are high (cf.
CTITCR register)
Read: reads its own value when ITEN or soc_test are high, else reads CTICHINACK values
19.10.24 ARM Identification Registers
Extended_CTI have ARM dedicated registers for identification.
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Embedded Cross Trigger (ECT)
CTIPERIPHID (spread over CTIPERIPHID0–3 registers):
• Part Number [11:0]: identifies ARM peripheral. CTI is referenced as 0x900,
• Designer [7:0]: identifies designer of CTI. ARM Ltd. is referenced as 0x41,
• Revision Number [3:0],
• Configuration [7:0]: Configuration option for the design. Here it is 0x00.
CTIPCELLID (spread over CTIPCELLID0–3 registers):
• Standard Cross-Peripheral identification system, on 32 bits.
19.10.24.1 CTIPERIPHID0 Register
The CTIPERIPHID0 register, shown in Figure 19-25, is a read-only register that provide identifications
code for the peripheral.
Offset $BASE<N> + 0xFE0
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
Partnumber0
W
Reset
All zeros
Figure 19-25. CTI Peripheral Identification Register 0 (CTIPERIPHID0)
Table 19-27 describes the CTIPERIPHID0 register.
Table 19-27. CTIPERIPHID0 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
First part of peripheral identification
Partnumber0 Read back as 0x00.
19.10.24.2 CTIPERIPHID1 Register
The CTIPERIPHID1 register, shown in Figure 19-26, is a read-only register that provides identifications
code for the peripheral.
Offset $BASE<N> + 0xFE4
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
4
Designer0
3
0
Partnumber0
W
Reset 0
0
0
0
1
0
0
0
1
Figure 19-26. CTI Peripheral Identification Register 1 (CTIPERIPHID1)
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19-31
Embedded Cross Trigger (ECT)
Table 19-28 describes the CTIPERIPHID1 register.
Table 19-28. CTIPERIPHID1 Register Field Descriptions
Field
Description
31–8
Reserved
7–4
Designer0
First part of designer identification
read back as 0x1.
3–0
Partnumber1
Second part of peripheral identification
Read back as 0x9.
19.10.24.3 CTIPERIPHID2 Register
The CTIPERIPHID2 register, shown in Figure 19-27, is a read-only register that provides identifications
code for the peripheral.
Offset $BASE<N> + 0xFE8
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
4
Revision
3
0
Designer1
W
Reset 0
0
0
0
0
0
1
0
0
Figure 19-27. CTI Peripheral Identification Register 2 (CTIPERIPHID2)
Table 19-29 describes the CTIPERIPHID2 register.
Table 19-29. CTIPERIPHID2 Register Field Descriptions
Field
Description
31–8
Reserved
7–4
Revision
Revision number
read back as 0x0.
3–0
Designer1
Second part of designer identification
Read back as 0x4.
19.10.24.4 CTIPERIPHID3 Register
The CTIPERIPHID3 register, shown in Figure 19-28, is a read-only register that provides identifications
code for the peripheral.
Address $BASE<N> + 0xFEC
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
Configuration
W
Reset
All zeros
Figure 19-28. CTI Peripheral Identification Register 3 (CTIPERIPHID3)
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Embedded Cross Trigger (ECT)
Table 19-30 describes the CTIPERIPHID3 register.
Table 19-30. CTIPERIPHID3 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
Indicates the number of interrupts supported
Configuration read back as 0x00.
19.10.24.5 CTIPCELLID0 Register
The CTIPCELLID0 register, shown in Figure 19-29, is a read-only register that provides cross peripheral
identification.
Address $BASE<N> + 0xFF0
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
CTIPCELLID0
W
Reset 0
0
0
0
0
1
1
0
1
Figure 19-29. CTI Identification Register 0 (CTIPCELLID0)
Table 19-31 describes the CTIPCELLID0 register.
Table 19-31. CTIPCELLID0 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
Identification
CTIPCELLID0 Read back as 0x0D.
19.10.24.6 CTIPCELLID1 Register
The CTIPCELLID1 register, shown in Figure 19-30, is a read-only register that provides cross peripheral
identification.
Address $BASE<N> + 0xFF4
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
CTIPCELLID1
W
Reset 0
1
1
1
1
0
0
0
0
Figure 19-30. CTI Identification Register 1 (CTIPCELLID1)
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Embedded Cross Trigger (ECT)
Table 19-32 describes the CTIPCELLID1 register.
Table 19-32. CTIPCELLID1 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
Identification
CTIPCELLID1 Read back as 0xF0.
19.10.24.7 CTIPCELLID2 Register
The CTIPCELLID2 register, shown in Figure 19-31, is a read-only register that provides cross peripheral
identification.
Address $BASE<N> + 0xFF8
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
CTIPCELLID2
W
Reset 0
0
0
0
0
0
1
0
1
Figure 19-31. CTI Identification Register 2 (CTIPCELLID2)
Table 19-33 describes the CTIPCELLID2 register.
Table 19-33. CTIPCELLID2 Register Field Descriptions
Field
Description
31–8
Reserved
7–0
Identification
CTIPCELLID2 Read back as 0x05.
19.10.24.8 CTIPCELLID3 Register
The CTIPCELLID3 register, shown in Figure 19-32, is a read-only register that provides cross peripheral
identification.
Offset $BASE<N> + 0xFFC
Wait State: >3
Access: Read only
31
R 0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
CTIPCELLID3
W
Reset 0
1
0
1
1
0
0
0
1
Figure 19-32. CTI Identification Register 3 (CTIPCELLID3)
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Embedded Cross Trigger (ECT)
Table 19-34 describes the CTIPCELLID3 register.
Table 19-34. CTIPCELLID3 Register Field Descriptions
Field
31–8
Description
Reserved
7–0
Identification
CTIPCELLID3 Read back as 0xB1.
19.11 Functional Description
As explained in the overview, ECT is made of 3 EXTENDED_CTI and one CTM.
19.12 Extended Cross Trigger Interface (EXTENDED_CTI)
The EXTENDED_CTI is divided into the following sub-modules:
• a WRAPPER
• an ECT_CTI (IP delivered by ARM Ltd.)
• an IPS to AHB bridge to interface with ECT_CTI
EXTENDED_CTI
IPS
interface
IPS to AHB
AHB IF
8
WRAPPER
Trigger
outputs
control reg
8
8
4
ECT_CTI
8
Mapping
OR
4
Channel interface
Trigger
inputs
Figure 19-33. EXTENDED_CTI diagram
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Embedded Cross Trigger (ECT)
19.12.1 Wrapper
For a given EXTENDED_CTI, trigger inputs can emanate from asynchronous clock domains. Trigger
inputs can also behave differently, some might be active high, others might be active low whereas
ECT_CTI is only expecting events active high. For those reasons, trigger events have to pass through a
wrapper to adapt their behavior.
Thus, the wrapper is used to do the following:
• Reshape signals: for example, a trigger transmitted as a level active high can be converted into a
pulse or a trigger active low can be inverted.
• Sample trigger events: it can be useful to add a flip-flop on trigger inputs/outputs for timing
purpose as wrapper might be far from trigger source/destination.
• Synchronize events between ECT_CTI clock and trigger clocks
• Hold values from a faster clock domain: for instance, a trigger input must stay active until an
acknowledgement from the ECT_CTI is received
samp_trig
_in_0[0]
cti_trig_
in_0 [0]
inv_trig_
in_0 [0]
trig_in_if_sync
_byp_0 [0]
trig_in_pulse
_sel_0 [0]
Sample
Invert
Convert into
pulse
trigger input
1
0
SYNC
wrp_trig_in_
hs_byp_0 [0]
1
0
cti_trig_in_ack_0 [0]
SYNC
HOLDER
INPUT WRAPPER
ECT_CTI
cti_trig_in_
ipg_clk_0
clk_0 [0]
Figure 19-34. Input Wrapper and Hand-Shaking/Synchronization with ECT_CTI
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Embedded Cross Trigger (ECT)
trig_out_if_sync
_byp_0 [0]
samp_trig
_out_0[0]
ECT_CTI
trigger output
1
0
SYNC
trig_out_pulse
_sel_0 [0]
inv_trig_
out_0 [0]
- Sample
- Invert
- Convert into
pulse
- Gating off
cti_trig_
out_0[0]
1
0
SYNC
HOLDER
cti_trig_out
_ack_0 [0]
OUTPUT WRAPPER
software_ack
cti_trig_out_
ipg_clk_0
hs_byp_0 [0]
cti_trig_out
_clk_0 [0]
wrp_trig_out_ack
_byp_0 [0]
Figure 19-35. Output Wrapper and Hand-Shaking/Synchronization with ECT_CTI
All wrapper features such as sampling, inverter, reshaping, synchronization & holder can be activated or
bypassed as wrapper control signals are brought to ECT top level.
The same mechanisms of hand-shaking/synchronization are used for CTM <-> EXTENDED_CTI/ARM
CTI interfaces.
19.12.2 ECT_CTI
This block is the interface to CTM, it maps:
•
trigger inputs onto channels
•
channel onto trigger outputs.
ECT_CTI takes cross trigger event inputs from its associated subsystem, or from its own configuration
registers, and generates outputs on the appropriate channels as defined by the configuration registers.
Those ECT_CTI configuration registers are programmed by the sub-system connected to the ECT_CTI
using the bus interface.
ECT_CTI also includes handshaking / synchronization mechanism on the 8 trigger inputs, 8 trigger
outputs, 4 channel inputs and 4 channel outputs. All hand-shaking and synchronization mechanisms can
be bypassed as the bypass control signals are brought to ECT top level.
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Embedded Cross Trigger (ECT)
ECT_CTI
AHB Interface
CTI control registers
Enable Enable
Out
In
Status
8 trigger
inputs from
wrapper
HS &
SYNC
8
4
Control
4
CTI IN
mapping
HS &
SYNC
path1
APPTRIG
8 trigger
outputs to
wrapper
HS &
SYNC
8
CTI OUT
mapping
4 channels
to CTM
4
4
HS &
SYNC
4 channel
from CTM
path2
Figure 19-36. CTI Diagram
Note: The OR gate (in blue) is required because in the CTM, channel inputs are not routed back to their own channel outputs.
19.12.2.1 Mapping
On the wrapper side, ECT_CTI has 8 trigger inputs from the SoC and 8 trigger outputs to the SoC. On the
CTM side, ECT_CTI has 4 channel inputs from the CTM and 4 channel outputs to the CTM.
Each trigger input can be connected to any of the 4 channels going to the CTM (path1). Note that several
trigger inputs can be mapped to the same channel as actually, a channel input is an OR function of all
enabled trigger inputs. The mapping triggers to channels is fully programmable using the memory-mapped
registers CTIINEN (see Section 19.10.9, “CTIINEN0–7 Register”).
Each channel coming from the CTM can be mapped to any of the 8 trigger outputs of the ECT_CTI
(path2). Note that several channels can be mapped to the same trigger output as a trigger output is an OR
function of all the enabled channels. The mapping channels to triggers is fully programmable using the
memory-mapped registers CTIOUTEN (see Section 19.10.10, “CTIOUTEN0–7 Register”).
19.12.2.2 Application Trigger
ECT_CTI enables to raise an event on one of the channels by writing a 1 to CTIAPPSET register (see
Section 19.10.6, “CTIAPPSET Register”). To clear the application trigger, one has to assert to the
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Embedded Cross Trigger (ECT)
corresponding bit in CTIAPPCLEAR register (see Section 19.10.7, “CTIAPPCLEAR Register”). Each
register has one bit corresponding to each of the 4 channels.
A pulse can also be generated by writing to APPPULSE register (see Section 19.10.8, “CTIAPPPULSE
Register”).
19.12.3 IPS2AHB
This module is a bridge from the IP bus, where the EXTENDED_CTI stands, to the AHB (v2.0) interface
provided by Arm Ltd.
Only 32-bits accesses are allowed otherwise an IP xfr error is generated.
Even if the bus clock is running, if ECT clocks are gated off (ect_clk_en = 0), neither read nor write access
to memory mapped register are allowed and generates an ips_xfr_error if attempted.
19.13 Cross Trigger Matrix (CTM)
The Cross Trigger Matrix has 4 interfaces of 4 channel inputs and 4 channel outputs each.
To CTI0 From CTI0
4
4
4
interface #1
HS & SYNCHRO
4
To CTI3
HS & SYNCHRO
HS & SYNCHRO
From CTI3
4
interface #3
CTM
interface #0
To CTI1
4
From CTI1
HS & SYNCHRO
interface #2
4
4
From CTI2 To CTI2
Figure 19-37. CTM Diagram
Each channel input of each interface is propagated to the other corresponding channel output of the 3 other
interfaces so that when a channel input receives a signal, it is propagated to the channel output of the three
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Embedded Cross Trigger (ECT)
other ports. For example, the path in blue in the following figure shows the propagation of bit 0 of interface
2 (CHIN2[0]) to bit 0 of interfaces 0 (CHOUT0[0]), 1 (CHOUT1[0]), and 3 (CHOUT3[0]).
Moreover, each channel output of each interface is the logical OR of the 3 other channel inputs. For
example, as shown in red in the following figure, CHIN0[0], CHIN1[0], and CHIN3[0] are ORed together
to generate CHOUT2[0].
CHOUT0[0]
bit 0
Channel
Input
bit 0
CHIN0[0]
CTM
interface #0
bit 0
CHOUT3[0]
HS &
SYNCHRO
Channel
Output
HS &
SYNCHRO
CHIN3[0]
interface #3
0
HS &
SYNCHRO
Channel bit
Input
HS &
SYNCHRO
HS &
SYNCHRO
HS &
SYNCHRO
HS &
SYNCHRO
bit 0
interface #1
Channel
Output
Channel
Output
CHOUT1[0]
bit 0
Channel
Input
CHIN1[0]
HS &
SYNCHRO
interface #2
CHIN2[0]
bit 0
Channel
Input
bit 0
CHOUT2[0]
Channel
Output
Figure 19-38. CTM Detailed Implementation for Channel 0
Each channel input is synchronized and acknowledged if required. Each channel output can be held until
an acknowledgement is received.
All hand-shaking and synchronization mechanisms can be bypassed as the bypass control signals are
brought to the ECT top level.
Note that in the CTM, channel inputs are not routed back to their own channel outputs, so this need to be
performed in the ECT_CTI (OR gate in blue). Thus, a channel output is really a logical OR of the 4
corresponding channel inputs as shown below.
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CHOUT3[0]
1
HS &
SYNC
1
HS &
SYNC
ECT
ect_dbg_en
1
interface #3
CHIN3[0]
1
HS &
SYNCHRO
CTM
ECT_CTI
HS &
SYNCHRO
Embedded Cross Trigger (ECT)
CHIN0[0]
CHIN1[0]
CHIN2[0]
channel
channel
0
channel
1
channel
2
3
ctm_lines [3:0]
Figure 19-39. Channel Output and CTM Lines
Status of the 4 channels (0 to 3) can be observed through “ctm_lines[3:0]” that are brought to ECT top
level.
19.14 Initialization/Application Information
19.15 Initialization
By default (reset), ECT is inactive. To enable cross-triggering functionality, the following steps are
required:
1. Unlock AHB interface: to unlock AHB interface the correct 32-bit word (0x0ACCE550) has to
be written in the CTILOCK register,
2. Enable CTI logic: To enable CTI, GLBEN bit in CTICONTROL register has to be set to 1.
3. Enable mapping: By default no mapping is enable. As a consequence, no signals can be
propagated through CTI-CTM. To enable mapping following settings are needed:
a) Trigger to channel mapping: Wanted mapping has to be specified for each CTI in CTIINEN
registers,
b) Channel to triggers mapping: Wanted mapping has to be specified for each CTI in CTIOUTEN
registers.
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Embedded Cross Trigger (ECT)
4. Access mode: By default, both supervisor and user access modes are allowed for any read/write
access of CTI registers. To only allow supervisor accesses, PROT bit in CTIPROTECTION
register has to be set to 1(this operation need a supervisor write access).
NOTE
All those operations will be performed by software debug tools such as
RealView Debugger (RVD).
19.16 Application information
If the hand-shaking is not bypassed, events close to one another (multi-shot) on the same trigger input are
possibly merged into one event on an output trigger. Events arising from different interfaces and mapped
to the same channel might also be merged due to the hand-shaking hardware.
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Chapter 20
External Memory Interface (EMI)
The EMI provides the ability to connect the system to a wide variety of memory devices. This chapter
contains technical information about the operation and configuration of the chip’s EMI module, to allow
the designer to quickly integrate external memory devices into new and existing designs. The chapter
covers the following topics:
• Section 20.1, “Overview”
• Section 20.2, “EMI Input/Output Signals”
• Section 20.3, “Memory Map/Register Definition”
• Section 20.4, “Functional Description”
20.1
Overview
The EMI controls all IC external memory accesses (read/write/erase/program) from all the masters in the
system to different external memories. All accesses are arbitrated by the multi-master memory interface
(M3IF) submodule and controlled by the respective memory controller.
The EMI contains the following external memory controllers to support different types of memory
devices:
• Enhanced SDRAM/LPDDR memory controller (ESDRAMC, also known as
ESDRAMC/MDDRC, or ESDCTL/MDDRC). The ESDRAMC and ESDCTL mnemonics are
equivalent; for historical reasons they are alternately used throughout the document.
• NAND Flash memory controller (NFC).
• Wireless external interface module (WEIM), which supports SRAM, PSRAM, and NOR Flash
memory devices.
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1
External Memory Interface (EMI)
Figure 20-1 is a top-level diagram of the EMI that shows the functional organization of the block.
External Module Interface (EMI)
Multi Master
Memory Interface
EMI AHB MUX
M3IF
REGISTERS
#2
MPG
32 OR 64
DMA_ACCESS
WATERMARK_PORTS
8
SDRAM / LPDDR
NANDFLASH
32 OR 64
NANDFLASH
CONTROLLER
#4
MPG
32 OR 64
M3IF ARBITRATION (AMB + M3A)
#3
MPG
#1
MPG
32 OR 64
ESDRAMC/MDDRC
CONTROLLER
#0
MPG
32 OR 64
EMI I/O MUX
WM &
SNOOPING
32 OR 64
SRAM/PSRAM
FLASH
#6
MPG
32 OR 64
#5
MPG
WM_INT
WEIM
CONTROLLER
LOGIC
**INTERFACE SIZE WIDTH CAN BE 32 OR 64 DEPEND ON
SPECIFIC CONFIGURATION OF THE IC.
Figure 20-1. EMI System Block Diagram
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External Memory Interface (EMI)
20.1.1
Features
The EMI includes the following features:
• Multi master memory interface (M3IF)
— Supports multiple requests from up to 8 masters through input ports interface.
— Supports memory snooping: monitors a region of size 2 Kbytes–16 Mbytes in external memory
for write accesses.
— Supports memory watermark protection for up to 8 different chip selects for
hardware-preselected masters.
• Enhanced SDRAM controller (ESDRAMC) / LPDDR controller (MDDRC)
— Up to 2 chip selects (due to sharing of pins, 2 chip selects are supported only when the WEIM
CS2 and CS3 are not is use).
— Support x16 SDR SDRAM (up to 1-Gbit at133 MHz)
— Support x16 LPDDR SDRAM (up to 1-Gbit at 266 MHz)
• NAND Flash controller (NFC)
— Supports 8- and 16-bit NAND FLASH (up to 2 GB address space)
— Internal 4.5 Kbyte RAM buffer.
• Wireless external interface memory controller (WEIM)
— Up to five chip selects (due to sharing of pins, five chip selects are supported only when both
ESDCTL/MDDRC and NAND FLASH chip selects are not in use).
— Supports x16/x32 multiplexed/non-multiplexed mode for PSRAM and NOR Flash memory
devices.
• Different memory controllers are accessible using AHB
• Pins are shared among memory controllers using the EMI AHB multiplexer and the EMI I/O
multiplexer
20.2
EMI Input/Output Signals
Table 20-1 lists all of the EMI input and output signals. For the detailed description of each signal function,
see the relevant module chapter in this document.
Table 20-1. EMI Signal Properties
Name
Port
Function
Reset
State
AHB Interface Outputs
M3IF_HREADY_M0
O
AHB access completion strobe to master #0
1
M3IF_HREADY_M1
O
AHB access completion strobe to master #1
1
M3IF_HREADY_M2
O
AHB access completion strobe to master #2
1
M3IF_HREADY_M3
O
AHB access completion strobe to master #3
1
M3IF_HREADY_M4
O
AHB access completion strobe to master #4
1
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Reset
State
Name
Port
Function
M3IF_HREADY_M5
O
AHB access completion strobe to master #5
1
M3IF_HREADY_M6
O
AHB access completion strobe to master #6
1
M3IF_HREADY_M7
O
AHB access completion strobe to master #7
1
M3IF_HRESP_M0
O
AHB error response to master #0
0
M3IF_HRESP_M1
O
AHB error response to master #1
0
M3IF_HRESP_M2
O
AHB error response to master #2
0
M3IF_HRESP_M3
O
AHB error response to master #3
0
M3IF_HRESP_M4
O
AHB error response to master #4
0
M3IF_HRESP_M5
O
AHB error response to master #5
0
M3IF_HRESP_M6
O
AHB error response to master #6
0
M3IF_HRESP_M7
O
AHB error response to master #7
0
M3IF_HRDATA_M0
O
AHB read data bus to master #0 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M1
O
AHB read data bus to master #1 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M2
O
AHB read data bus to master #2 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M3
O
AHB read data bus to master #3 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M4
O
AHB read data bus to master #4 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M5
O
AHB read data bus to master #5 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M6
O
AHB read data bus to master #6 (bus size is determined by system
configuration)
0
M3IF_HRDATA_M7
O
AHB read data bus to master #7 (bus size is determined by system
configuration)
0
M3IF and ESDRAMC/MDDRC Outputs
IPP_DO_SDRC_SDCKE[1:0]
O
SDRAM/LPDDR clock enable
0
IPP_DO_EMI_DQM[3:0]
O
SDRAM data mask strobes. DQM0 corresponds to DQ0–DQ7, DQM1
corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and
DQM3 corresponds to DQ24–DQ31.
0
IPP_DO_DQS[3:0]
O
LPDDR data sample strobes for write accesses. DQS0 corresponds
to DQ0–DQ7, DQS1 corresponds to DQ8–DQ15, DQS2 corresponds
to DQ16–DQ23 and DQS3 corresponds to DQ24–DQ31.
0
IPP_OBE_DQS
O
DQS output enable strobe
0
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Function
Reset
State
Name
Port
IPP_DO_E M I _ADDR[25:0]
O
WEIM Address [25:0] multiplexed with SDR[13:0] (except for
SDR[10])
0
IPP_DO_SDBA[1:0]
O
SDRAM/LPDDR bank address bits
0
IPP_DO_M3IF_MA10
O
SDRAM/LPDDR address bit A10
0
IPP_DO_M3IF_CAS_B
O
SDRAM/LPDDR CAS strobe
1
IPP_DO_M3IF_RAS_B
O
SDRAM/LPDDR RAS strobe
1
IPP_DO_SDRC
O
SDRAM/LPDDR WE strobe
1
M3IF_CHOOSEN_MASTER[2:0]
O
M3IF arbitration chosen master (for debug)
3
IPP_DO_SDRC_SDCLK
O
SDRAM/LPDDR clock (up to 133MHz)
0
LPACK
O
Low power mode acknowledge; toward CCM
1
SDRC_SF_WACK
O
Memory wake-up acknowledge indication to WDOG
0
NFC Ouputs
IPI_INT_NFC_B
0
NFC interrupt (indicating an access completion)
1
IPP_NFC_ALE_OUT
O
NFC out NF_ALE
0
IPP_NFC_CE0_OUT
O
NFC out NF_CE0
0
IPP_NFC_CE1_OUT
O
NFC out NF_CE1
0
IPP_NFC_CE2_OUT
O
NFC out NF_CE2
0
IPP_NFC_CE3_OUT
O
NFC out NF_CE3
0
IPP_NFC_CLE_OUT
O
NFC out NF_CLE
0
IPP_NFC_RE_OUT
O
NFC out NF_RE
0
IPP_NFC_WE_OUT
O
NFC out NF_WE
0
IPP_NFC_WP_OUT
O
NFC out NF_WP
0
WEIM Outputs
IPP_DO_WEIM_CS_B0
O
WEIM CS0 chip select toward I/O multiplexer/pins
1
IPP_DO_WEIM_CS_B1
O
WEIM CS1 chip select toward I/O multiplexer/pins
1
IPP_DO_WEIM_CS_B2_CSD0
O
WEIM CS2 or ESDRAMC/MDDRC CSD0 chip select toward I/O
multiplexer/pins
1
IPP_DO_WEIM_CS_B3_CSD1
O
WEIM CS2 or ESDRAMC/MDDRC CSD1 chip select toward I/O
multiplexer/pins
1
IPP_DO_WEIM_CS_B4
O
WEIM CS4 chip select toward I/O multiplexer/pins
1
IPP_DO_WEIM_CS_B5
O
WEIM CS5 chip select toward I/O multiplexer/pins
1
IPP_DO_WEIM_BCLK
O
WEIM Burst Clock
0
IPP_DO_WEIM_LBA_B
O
WEIM Load Burst Address (LBA)
1
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Name
Port
IPP_DO_WEIM_RW_B
O
Reset
State
Function
WEIM read/write strobe
1
Global Ouputs
M3IF_DMA_ACCESS
O
Snooping detection indication toward IPU module
0
IPP_OBE_DDR_EN
O
LPDDR active indication to ESDRAMC/MDDRC DATA pins
0
IPP_DO_EMI_ADDR[25:0]
O
EMI address out toward I/O multiplexer/pins
0
IPP_DO_NFC_WEIM_IO_DATA_OU
T[15:0]
O
EMI WEIM/NFC data out toward I/O multiplexer/pins
0
IPP_DO_EMI_DATA[31:0]
O
EMI SDRAM/DDR data out toward I/O multiplexer/pins
0
IPP_OBE_EMI_DATA_DIR
O
EMI SDRAM/DDR data direction toward I/O multiplexer/pins
0
IPP_OBE_NFC_DIR_HIGH
O
EMI (NFC, WEIM) data direction toward I/O multiplexer/pins
0
IPP_OBE_NFC_DIR_LOW
O
EMI (NFC, WEIM) data direction toward I/O multiplexer/pins
0
IPP_DO_EMI_EB_B[1:0]
O
WEIM enable byte out toward I/O multiplexer/pins
0
IPP_DO_EMI_OE_B
O
EMI output enable toward I/O multiplexer/pins
0
IPP_OBE_IO_ADDR_DIR[1:0]
O
EMI output enable (dir) toward I/O ADDR/WEIM multiplexed DATA
multiplexer/pins
0
AHB Interface Inputs
M3IF_HADDR_M0[31:0]
I
AHB address bus from master #0
0
M3IF_HADDR_M1[31:0]
I
AHB address bus from master #1
0
M3IF_HADDR_M2[31:0]
I
AHB address bus from master #2
0
M3IF_HADDR_M3[31:0]
I
AHB address bus from master #3
0
M3IF_HADDR_M4[31:0]
I
AHB address bus from master #4
0
M3IF_HADDR_M5[31:0]
I
AHB address bus from master #5
0
M3IF_HADDR_M6[31:0]
I
AHB address bus from master #6
0
M3IF_HADDR_M7[31:0]
I
AHB address bus from master #7
0
M3IF_HWDATA_M0
I
AHB write data bus from master #0 (bus size is determined by system
configuration). In case this master is a read only-master this signal is
not routed as an EMI output.
0
M3IF_HWDATA_M1
I
AHB write data bus from master #1 (bus size is determined by system
configuration)
0
M3IF_HWDATA_M2
I
AHB write data bus from master #2 (bus size is determined by system
configuration)
0
M3IF_HWDATA_M3
I
AHB write data bus from master #3 (bus size is determined by system
configuration)
0
M3IF_HWDATA_M4
I
AHB write data bus from master #4 (bus size is determined by system
configuration)
0
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Reset
State
Name
Port
Function
M3IF_HWDATA_M5
I
AHB write data bus from master #5 (bus size is determined by system
configuration)
0
M3IF_HWDATA_M6
I
AHB write data bus from master #6 (bus size is determined by system
configuration)
0
M3IF_HWDATA_M7
I
AHB write data bus from master #7 (bus size is determined by system
configuration)
0
M3IF_HBURST_M0[2:0]
I
AHB burst size bus from master #0
0
M3IF_HBURST_M1[2:0]
I
AHB burst size bus from master #1
0
M3IF_HBURST_M2[2:0]
I
AHB burst size bus from master #2
0
M3IF_HBURST_M3[2:0]
I
AHB burst size bus from master #3
0
M3IF_HBURST_M4[2:0]
I
AHB burst size bus from master #4
0
M3IF_HBURST_M5[2:0]
I
AHB burst size bus from master #5
0
M3IF_HBURST_M6[2:0]
I
AHB burst size bus from master #6
0
M3IF_HBURST_M7[2:0]
I
AHB burst size bus from master #7
0
M3IF_HSIZE_M0[1:0]
I
AHB data transfer width bus from master #0
0
M3IF_HSIZE_M1[1:0]
I
AHB data transfer width bus from master #1
0
M3IF_HSIZE_M2[1:0]
I
AHB data transfer width bus from master #2
0
M3IF_HSIZE_M3[1:0]
I
AHB data transfer width bus from master #3
0
M3IF_HSIZE_M4[1:0]
I
AHB data transfer width bus from master #4
0
M3IF_HSIZE_M5[1:0]
I
AHB data transfer width bus from master #5
0
M3IF_HSIZE_M6[1:0]
I
AHB data transfer width bus from master #6
0
M3IF_HSIZE_M7[1:0]
I
AHB data transfer width bus from master #7
0
M3IF_HBSTRB_M0
I
Byte lane (8) bus from master #0 (bus size is determined by system
configuration)
0
M3IF_HBSTRB_M1
I
Byte lane (8) bus from master #1 (bus size is determined by system
configuration)
0
M3IF_HBSTRB_M2
I
Byte lane (4) bus from master #2 (bus size is determined by system
configuration)
0
M3IF_HBSTRB_M3
I
Byte lane (4) bus from master #3 (bus size is determined by system
configuration)
0
M3IF_HBSTRB_M4
I
Byte lane (4) bus from master #4 (bus size is determined by system
configuration)
0
M3IF_HBSTRB_M5
I
Byte lane (4) bus from master #5 (bus size is determined by system
configuration)
0
M3IF_HBSTRB_M6
I
Byte lane (4) bus from master #6 (bus size is determined by system
configuration)
0
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Reset
State
Name
Port
Function
M3IF_HBSTRB_M7
I
Byte lane (4) bus from master #7 (bus size is determined by system
configuration)
0
M3IF_HTRANS_M0[1:0]
I
AHB transfer state bus from master #0
0
M3IF_HTRANS_M1[1:0]
I
AHB transfer state bus from master #1
0
M3IF_HTRANS_M2[1:0]
I
AHB transfer state bus from master #2
0
M3IF_HTRANS_M3[1:0]
I
AHB transfer state bus from master #3
0
M3IF_HTRANS_M4[1:0]
I
AHB transfer state bus from master #4
0
M3IF_HTRANS_M5[1:0]
I
AHB transfer state bus from master #5
0
M3IF_HTRANS_M6[1:0]
I
AHB transfer state bus from master #6
0
M3IF_HTRANS_M7[1:0]
I
AHB transfer state bus from master #7
0
M3IF_HWRITE_M0
I
AHB read/write signal from master #0
0
M3IF_HWRITE_M1
I
AHB read/write signal from master #1
0
M3IF_HWRITE_M2
I
AHB read/write signal from master #2
0
M3IF_HWRITE_M3
I
AHB read/write signal from master #3
0
M3IF_HWRITE_M4
I
AHB read/write signal from master #4
0
M3IF_HWRITE_M5
I
AHB read/write signal from master #5
0
M3IF_HWRITE_M6
I
AHB read/write signal from master #6
0
M3IF_HWRITE_M7
I
AHB read/write signal from master #7
0
M3IF_HPROT_M0
I
AHB protection mode signal from master #0
0
M3IF_HPROT_M1
I
AHB protection mode signal from master #1
0
M3IF_HPROT_M2
I
AHB protection mode signal from master #2
0
M3IF_HPROT_M3
I
AHB protection mode signal from master #3
0
M3IF_HPROT_M4
I
AHB protection mode signal from master #4
0
M3IF_HPROT_M5
I
AHB protection mode signal from master #5
0
M3IF_HPROT_M6
I
AHB protection mode signal from master #6
0
M3IF_HPROT_M7
I
AHB protection mode signal from master #7
0
M3IF_HUNALIGN_M0
I
Unalign access signal from master #0
0
M3IF_HUNALIGN_M1
I
Unalign access signal from master #1
0
M3IF_HUNALIGN_M2
I
Unalign access signal from master #2
0
M3IF_HUNALIGN_M3
I
Unalign access signal from master #3
0
M3IF_HUNALIGN_M4
I
Unalign access signal from master #4
0
M3IF_HUNALIGN_M5
I
Unalign access signal from master #5
0
M3IF_HUNALIGN_M6
I
Unalign access signal from master #6
0
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Name
Port
M3IF_HUNALIGN_M7
I
Function
Unalign access signal from master #7
Reset
State
0
M3IF and ESDRAMC/MDDRC Inputs
M3IF_HCLK
I
M3IF AHB system clock up to 133MHz
0
HCLK32
I
32 KHz clock for ESDRAMC refresh counter
0
IPP_IND_SDRC_SDCLK_FB
I
SDRAM/LPDDR feedback clock (up to 133MHz)
0
LPMD
I
Low power mode indication signal, “0”=STOP, “1”=RUN.
1
IPP_IND_DQS[3:0]
I
LPDDR data sample strobes for read accesses. DQS0 corresponds
to DQ0–DQ7, DQS1 corresponds to DQ8–DQ15, DQS2 corresponds
to DQ16–DQ23 and DQS3 corresponds to DQ24–DQ31.
0
SDCTL_CSD0_SEL_B
I
SDRAM/LPDDR CSD0 select multiplexed with CS2 (configurable
using the system control register, FMCR)
0
SDCTL_CSD1_SEL_B
I
SDRAM/LPDDR CSD1 select multiplexed with CS3 (configurable
using the system control register, FMCR)
0
NFC Inputs
NF16_BOOT_B
I
Boot mode source is 16 bit NAND Flash memory.
Application
dependent
NF8_BOOT_B
I
Boot mode source is 8-bit NAND Flash memory.
Application
dependent
NF_16BIT_SEL
I
16-bit NAND Flash memory is use indication.
0
NFC_HCLK
I
NFC AHB input clock
0
NFC_RD_OE
I
NFC read output enable controls the direction of data bus
0
IPP_IND_FLASH_CLK
I
NAND Flash side clock with period of 40 nS
0
IPP_IND_NFC_RB_IN
I
NFC in NF_RB
0
WEIM Inputs
WEIM_BOOT_CFG[2:0]
I
WEIM boot mode select (from ccm)
For detailed boot description see the WEIM specification
Application
dependent
IPP_IND_WEIM_ECB_B
I
WEIM end current burst
1
WEIM_HCLK
I
WEIM AHB input clock
0
IPP_IND_WEIM_DTACK_B
I
External DTACK acknowledge
1
Global Inputs
IPP_IND_RESETB
I
Reset signal
1
IPP_IND_NFC_READ_DATA_IN[15:
0]
I
External memories (non SDRAM) read data in from I/O
multiplexer/pins
0
IPP_IND_EMI_DATA_IN[31:0]
I
EMI SDRAM/DDR data in from I/O multiplexer/pins
0
IPP_IND_ADDR_IN[15:0]
I
EMI WEIM multiplexed data in from I/O multiplexer/pins.
0
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Reset
State
Name
Port
M3IF_BIGEND_M0
I
Endian mode signal from master #0
Master
dependent
M3IF_BIGEND_M1
I
Endian mode signal from master #1
Master
dependent
M3IF_BIGEND_M2
I
Endian mode signal from master #2
Master
dependent
M3IF_BIGEND_M3
I
Endian mode signal from master #3
Master
dependent
M3IF_BIGEND_M4
I
Endian mode signal from master #4
Master
dependent
M3IF_BIGEND_M5
I
Endian mode signal from master #5
Master
dependent
M3IF_BIGEND_M6
I
Endian mode signal from master #6
Master
dependent
M3IF_BIGEND_M7
I
Endian mode signal from master #7
Master
dependent
WATERMARK_PORT[7:0]
I
Selects the watermark ports. If watermark is not enabled this port is
not routed as EMI port.
0
Watermark interrupt. If watermark is not enabled this port is not routed
as EMI port.
0
Warm reset indication. If ESDRAMC doesn’t support warm_reset,
than this port is not routed as EMI port.
0
IPI_INT_WATERMARK
Function
WARM_RESET
I
M3IF_HMASTLOCK_M0
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M1
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M2
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M3
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M4
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M5
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M6
—
Master arbitration locking signal
0
M3IF_HMASTLOCK_M7
—
Master arbitration locking signal
0
DMA_REQ
—
NFC DMA request
0
HRESET_B
—
Reset signal
1
HRESET_NEG_B
—
Reset signal
1
IPP_DO_EMI_OE_B
—
WEIM Data pads direction
0
IPP_IND_WEIM_BCLK_FB
—
WEIM feedback clock
0
IPT_MODE
—
Scan signal
0
IPT_MODE_BURNIN
—
Scan signal
0
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External Memory Interface (EMI)
Table 20-1. EMI Signal Properties (continued)
Reset
State
Name
Port
IPT_RAM_SE
—
Scan signal
0
IPT_SE
—
Scan signal
0
IPT_SE_ASYNC
—
Scan signal
0
IPT_SE_GATEDCLK
—
Scan signal
0
JTA_OR_IOB_BIST_BITMAPPING
—
NFC JTAG signal
0
JTAGC_BIST_NAND_CLOCK_DR
—
NFC JTAG signal
0
JTAGC_BIST_NAND_TDI
—
NFC JTAG signal
0
NAND_JTAGC_BIST_TDO
—
NFC JTAG signal
0
NFC_FMS
—
NFC 512-byte / 2-Kbyte page size
NF_4K
—
8-bit ECC signal
NF_BOOT_WITH_RESET
—
Flash memory is MLC type
EMI_SPARE_PORT_IN[9:0]
—
Spare inputs
0
EMI_SPARE_PORT_OUT[9:0]
—
spare outputs
0
IPT_SI[59:0]
—
Scan inputs
0
IPT_SO[59:0]
—
Scan outputs
0
DELAY_LINE_REF_CLK
—
Reference clock to the delay line
0
DVFS_REQ
—
DVFS request signal
0
DVFS_GRANT
—
DVFS acknowledge signal
0
VNW
—
WT_SHORT signal
0
VPW
—
WT_SHORT signal
0
WT_EN_DNW
—
WT_SHORT signal
0
WT_EN
—
WT_SHORT signal
0
NON_MOBILE_DDR_FUSE
—
DDR Type select
0
20.3
Function
Memory Map/Register Definition
Table 20-2 shows the address ranges for the four different controllers’ registers (M3IF plus three external
memory controllers). Refer to the separate memory controller chapters for detailed descriptions of the
memory controllers’ registers.
Table 20-2. EMI Registers Address Ranges
Address Range
Use
Access
0xB800_3000 – 0xB800_3FFF
M3IF registers space (4 Kbytes)
Read/write
0xB800_1000 – 0xB800_1FFF
ESDRAMC/MDDRC registers space (4 Kbytes)
Read/write
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External Memory Interface (EMI)
Table 20-2. EMI Registers Address Ranges (continued)
0xB800_2000 – 0xB800_2FFF
WEIM registers space (4 Kbytes)
Read/write
0xBB00_1E00 – 0xBB00_1EFF
NFC registers space (4 Kbytes)
Read/write
Table 20-3 shows the memory map, including memory spaces allocated to the three different external
controllers.
Table 20-3. EMI Memory Map
Address Range
Use
Access
ESDRAMC/MDDRC Memory Space
0x8000_0000 – 0x8FFF_FFFF
CSD0 SDRAM/LPDDR memory region (256 Mbytes)
Read/write
0x9000_0000 – 0x9FFF_FFFF
CSD1 SDRAM/LPDDR memory region (256 Mbytes)
Read/write
WEIM Memory Space
0xA000_0000 – 0xA7FF_FFFF
WEIM CS0 memory region1 (128 Mbytes)
Read/write
0xA800_0000 – 0xAFFF_FFFF
WEIM CS1 memory region (128 Mbytes)
Read/write
0xB000_0000 – 0xB1FF_FFFF
WEIM CS2 memory region (32 Mbytes)7
Read/write
0xB200_0000 – 0xB3FF_FFFF
WEIM CS3 memory region (32 Mbytes)
Read/write
0xB400_0000 – 0xB5FF_FFFF
WEIM CS4 memory region (32 Mbytes)
Read/write
0xB600_0000 – 0xB7FF_FFFF
WEIM CS5 memory region (32 Mbytes)
Read/write
NFC Memory Space
0xBB00_0000 – 0xBB00_11FF
NFC memory region1 (4.5 Kbytes, NAND Flash)
Read/write
1. Can be used as a boot memory region.
20.4
Functional Description
This section provides a functional description of the multi-master memory interface (M3IF), the three
external memory controllers, and the EMI’s AHB and I/O multiplexers.
20.4.1
Multi-Master Memory Interface (M3IF)
When a master requests a memory access, the access is immediately taken by the M3IF if no other access
is in progress. The M3IF forwards the access to the respective memory controller (slave). When the access
execution is completed, HREADY is asserted and a new request can be processed.
The interface between M3IF and ESDRAMC is optimized to reduce access latency by generating multiple
accesses through the dedicated ESDRAMC arbitration (MAB) module, which controls the access to/from
the ESDRAMC.
For the other memory interfaces, the M3IF receives masters’ requests through the master port gasket
(MPG) interfaces, performs arbitration, and forwards each request to the appropriate memory controller.
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Freescale Semiconductor
External Memory Interface (EMI)
20.4.2
NAND Flash Controller (NFC)
READ &
WRITE
RAM
BUFFER
ECC
CONTROL
BOOTLOADER
The NFC provides an interface between standard NAND Flash devices and the IC and hides the
complexities of accessing a NAND Flash memory device. It provides a glueless interface to 8- or 16-bit
SLC or MLC NAND Flash devices with different page size. Figure 20-2 is a simplified block diagram of
the NFC.
CLE
ALE
CE
HOST CONTROL
WE
DATA
OUTPUT
REGISTER
(COMMAN
D
ADDRESS
/ STATUS)
ADDRESS
CONTROL
NAND FLASH CONTROL
AHB BUS INTERFACE
AHB BUS
RE
WP
RB
DIN
DOUT
Figure 20-2. NAND Flash Controller Simplified Block Diagram
20.4.2.1
NFC Operation
Communication with a Flash memory device begins by the AHB host initiating a read from the NFC. This
is accomplished by configuring the NFC and then waiting for an interrupt from the Flash memory device
to be generated. When the NFC receives the interrupt, it inputs a page from the Flash memory device, and
upon completion generates an interrupt to the AHB host.
When the AHB host receives the NFC interrupt, it reads the content from the internal RAM buffer of the
NFC. To complete the operation the AHB host checks the status of the operation by reading the NFC status
registers.
Data that is exchanged with the Flash memory device is temporarily maintained in the RAM buffer. This
buffer is used as the boot RAM during a cold reset (if the IC is configured to boot from the NAND Flash
device). After the boot load completes, the RAM is available as buffer RAM for normal Flash memory
operations.
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External Memory Interface (EMI)
20.4.2.2
NFC Internal and External Communications
To ensure the greatest degree of flexibility, the NFC provides an internal interface to the AHB bus allowing
16-bit or 32-bit bus transfers, and a signal-selectable 8- or 16-bit interface to the external NAND Flash
memory device.
All communication between the NFC and the ARM11 platform passes through the AHB host. The host
configures and controls the NFC using the NFC registers.
Data integrity of the NAND Flash is maintained by the NFC. The NFC automatically generates the ECC
for verification during a read or program operation.
20.4.2.3
NFC Sharing of I/O Pins
The NFC provides necessary logic to share I/O pins with other memory controllers. For example, when
interfacing with a PSRAM, the 16 I/O signals of the NAND Flash controller share the same I/O pins with
the data signals of the wireless external interface module (WEIM).
When a request to free the pins is asserted, the NFC state machine halts and the NAND Flash signals when
it finishes the current transfer. The other memory controller is then able to gain control of the pins.
Since the NAND Flash memory accesses are typically long and relatively slow, priority is given to the
other memory controller sharing the pins. The NFC waits until the other memory controller is finished with
its operation and the pins are free before it continues its accesses.
20.4.3
Enhanced SDRAM Controller (ESDRAMC)
The ESDRAMC (equivalently denoted as ESDCTL) provides interface, configuration and control for
many different types of synchronous SDRAM and low power mobile DDR (LPDDR) memories.
Figure 20-3 shows the functional organization of the enhanced SDRAM controller.
The enhanced SDRAM controller consists of nine major blocks:
•
•
•
•
•
•
•
•
•
•
SDRAM command state machine controller,
Bank register (page and bank address comparators),
Row/column address multiplexer,
Configuration registers,
Refresh request counter,
Command sequencer,
Size logic (splitting access),
Data path (data aligner/multiplexer),
LPDDR interface
Power-down timer.
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Freescale Semiconductor
External Memory Interface (EMI)
#2
#1
AHB BUS
CONFIG &
CONTROL
REGISTER
n
HCLK(CCM)
RST
CS
ADDR(MAB)
32
CONFIG_REG
9
DECODER
AND ADDRESS
MUX
3
BA(SDRAM)
2
MA(SDRAM)
14
#2
#1
REFRESH
IPG_CLK_32K(CCM)
SEQUENCER
#8
#7
#6
#5
#4
#3
#2
#1
#2
#1
POWERDOWN
TIMER
8
15
COMMAND
4
BANK
MODEL
WACK(WDOG)
LPACK(CCM)
RAS(SDRAM)
TIMING & STATUS
CAS(SDRAM)
COMMAND
CONTROL
n
WE(SDRAM)
CSD(SDRAM)
2
DQM(SDRAM)
4
SD_CLK(SDRAM)
P_LPMD(CCM)
CKE(SDRAM)
CONFIG_REG
5
2
ACCESS_CTRL n
ADDR
MASTER
ARBITRATION
(MAB)
32
CONTROL n
NEXT_COMMAND
GET_NEW_COMMAND
GET_NEW_ACCESS
64
WR_DATA
BIGENDIAN
RD_ACK
RD_DATA
WR_ACK
64/32
n
COMMAND
SEQUENCER
CONTROL n
SIZE LOGIC
FB_CLK(I/O)
DATA PATH
32/16 RDATA(SDRAM)
LPDDR
INTERFACE
WDATA(SDRAM) 32
MDDR_SD_CLK_B(LPDDR)
DQS_OUT 4
DQS_IN
4
FB_CLK(I/O)
32/16
RDATA(SDRAM)
WDATA(SDRAM) 32
Figure 20-3. Enhanced SDR/LPDDR SDRAM Controller Block Diagram
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External Memory Interface (EMI)
20.4.4
EMI AHB Multiplexer
The EMI AHB multiplexer controls the traffic on the AHB bus (address and controls) between the memory
controllers and the internal peripherals (using the M3IF). The EMI uses several muxes/glue logic to control
the traffic on the AHB bus.
Only a few AHB signals/buses are routed through the EMI AHB multiplexer to the memory controllers.
Most of the AHB buses (data, address and controls) are directly routed from the M3IF to the memory
controllers.
20.4.4.1
Overview of EMI AHB Multiplexer Operation
Figure 20-4 illustrates the EMI AHB multiplexer block diagram. The interface is compatible with the
ARM 11 AMBA-AHB lite standard (for instance, it does not support RETRY and SPLIT transfers). All
AHB signals that are not shown in Figure 20-4 are directly routed between the M3IF and the relevant
memory controllers. For the entire list of AHB signals, see Table 20-1 and to the relevant memory
controller specification document.
The EMI AHB multiplexer generates the HSEL signals for all memory controllers, excluding the
ESDRAMC (which is generated within the M3IF due to latency-hiding logic).
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External Memory Interface (EMI)
HREADY_NFC
NANDFLASH
CONTROLLER
HRESP_NFC
HREADY
HADDR[31:12]
EMI AHB MUX
HSEL_WEIM_CS0
HSEL_WEIM_CS1
HSEL_WEIM_CS2
HSEL_WEIM_CS3
HSEL_WEIM_CS4
HSEL_WEIM_CS5
HSEL_WEIM_REG
HRESP0
WEIM
CONTROLLER
M3IF ARBITRATION (AMB + M3A)
HSEL_NFC
HREADY
HREADY_EIM
HRESP_EIM
Figure 20-4. EMI AHB Multiplexer Interface Diagram
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External Memory Interface (EMI)
20.4.5
EMI I/O Multiplexer
The EMI I/O multiplexer controls the traffic (data, address and control signals) between the memory
controllers and the external devices (using the IC IOMUX pins).
Figure 20-5 provides a top-level diagram of the EMI I/O multiplexer. Signals that share IC pins are routed
through the EMI I/O multiplexer to the external devices. Signals that have dedicated pins (such as control
signals) are not shown in Figure 20-5: these are directly routed from the memory controllers to the external
devices. For a complete list of signals, see Table 20-1 and the relevant memory controller section.
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SDRAM / LPDDR
DEVICE
ESDRAMC / MDDRC
CONTROLLER
External Memory Interface (EMI)
SDCTL_CSD0_SEL_B
SDCTL_CSD1_SEL_B
M3IF_MA
14
M3IF_CS_B
2
IPP_DO_E M I_EB_B
2
IPP_DO_E M I_OE_B
2
IPP_DO_WEIM_CS_B2_CSD0
IPP_NFC_WRITE_DATA_OUT 16
EMI I/O MUX
IPP_DO_WEIM_CS_B3_CSD1
IPP_DO_EMI_ADDR
26
NANDFLASH
DEVICE
NANDFLASH
CONTROLLER
IPP_OBE_IO_DATA_DIR
16
IC I / O M U X - Pins
ipp_do_nfc_write_data_out
IPP_DO_WEIM_RW_B
WEIM_ADDR_IN
WEIM
CONTROLLER
16
WEIM_ADDR
26
WEIM_DATA_OUT
16
WEIM_EB_B
2
IPP_DO_WEIM_CS_B
2
WEIM_RW_B
WEIM_WR_OE
4
SRAM / PSRAM
FLASH
WEIM_OE_B
SLAVE_SELECT(M3IF)
2
Figure 20-5. EMI I/O Multiplexer Interface Diagram
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External Memory Interface (EMI)
20.4.5.1
Overview of EMI I/O Multiplexer Operation
The active memory controller is determined by the SLAVE_SELECT[1:0] signal driven by the M3IF.
Table 20-4 lists the memory controllers associated with different SLAVE_SELECT values.
Table 20-4. SLAVE_SELECT Memory Controller Selection
SLAVE_SELECT Value
Selected Memory Controller
00
ESDRAMC/MDDRC
01
WEIM
10
Reserved
11
NFC
Table 20-5 summarizes the EMI outputs to IC pins, including dedicated pins and pins which are shared
between controllers.
Table 20-5. EMI Outputs to IC Pins
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
WEIM
NFC
IC Pin
Name
WEIM/ESDRAMC Address Multiplexing/WEIM Multiplexed Mode Data[15:0]
MA[0]
IPP_DO_WEIM_ADDR_
DATA_OUT[0]
—
IPP_IND_WEIM_ADDR_
DATA_IN[0]
MA[1]
IPP_DO_WEIM_ADDR_
DATA_OUT[1]
—
IPP_IND_WEIM_ADDR_
DATA_IN[1]
MA[2]
IPP_DO_WEIM_ADDR_
DATA_OUT[2]
—
IPP_IND_WEIM_ADDR_
DATA_IN[2]
MA[3]
IPP_DO_WEIM_ADDR_
DATA_OUT[3]
—
IPP_IND_WEIM_ADDR_
DATA_IN[3]
MA[4]
IPP_DO_WEIM_ADDR_
DATA_OUT[4]
—
IPP_IND_WEIM_ADDR_
DATA_IN[4]
—
IPP_DO_E M I
_ADDR [0]
A0
IPP_IND_ADDR_
IN [0]
—
IPP_DO_E M I
_ADDR [1]
A1
IPP_IND_ADDR_
IN [1]
—
IPP_DO_E M I
_ADDR [2]
A2
IPP_IND_ADDR_
IN [2]
—
IPP_DO_E M I
_ADDR [3]
A3
IPP_IND_ADDR_
IN [3]
—
IPP_DO_E M I
_ADDR [4]
A4
IPP_IND_ADDR_
IN [4]
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Freescale Semiconductor
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
WEIM
NFC
MA[5]
IPP_DO_WEIM_ADDR_
DATA_OUT[5]
—
—
IPP_IND_WEIM_ADDR_
DATA_IN[5]
MA[6]
IPP_DO_WEIM_ADDR_
DATA_OUT[6]
—
IPP_IND_WEIM_ADDR_
DATA_IN[6]
MA[7]
IPP_DO_WEIM_ADDR_
DATA_OUT[7]
—
IPP_IND_WEIM_ADDR_
DATA_IN[7]
MA[8]
IPP_DO_WEIM_ADDR_
DATA_OUT[8]
—
IPP_IND_WEIM_ADDR_
DATA_IN[8]
MA[9]
IPP_DO_WEIM_ADDR_
DATA_OUT[9]
—
IPP_IND_WEIM_ADDR_
DATA_IN[9]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[10]
—
IPP_IND_WEIM_ADDR_
DATA_IN[10]
MA[11]
IPP_DO_WEIM_ADDR_
DATA_OUT[11]
—
IPP_IND_WEIM_ADDR_
DATA_IN[11]
MA[12]
IPP_DO_WEIM_ADDR_
DATA_OUT[12]
—
IPP_IND_WEIM_ADDR_
DATA_IN[12]
MA[13]
IPP_DO_WEIM_ADDR_
DATA_OUT[13]
—
IPP_IND_WEIM_ADDR_
DATA_IN[13]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[14]
IPP_IND_WEIM_ADDR_
DATA_IN[14]
IPP_DO_E M I
_ADDR [5]
IC Pin
Name
A5
IPP_IND_ADDR_
IN [5]
—
IPP_DO_E M I
_ADDR [6]
A6
IPP_IND_ADDR_
IN [6]
—
IPP_DO_E M I
_ADDR [7]
A7
IPP_IND_ADDR_
IN [7]
—
IPP_DO_E M I
_ADDR [8]
A8
IPP_IND_ADDR_
IN [8]
—
IPP_DO_E M I
_ADDR [9]
A9
IPP_IND_ADDR_
IN [9]
—
IPP_DO_E M I
_ADDR [10]
A10
IPP_IND_ADDR_
IN [10]
—
IPP_DO_E M I
_ADDR [11]
A11
IPP_IND_ADDR_
IN [11]
—
IPP_DO_E M I
_ADDR [12]
A12
IPP_IND_ADDR_
IN [12]
—
IPP_DO_E M I
_ADDR [13]
A13
IPP_IND_ADDR_
IN [13]
—
IPP_DO_E M I
_ADDR [14]
A14
IPP_IND_ADDR_
IN [14]
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Freescale Semiconductor
21
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
—
WEIM
NFC
IPP_DO_WEIM_ADDR_
DATA_OUT[15]
—
IPP_IND_WEIM_ADDR_
DATA_IN[15]
IPP_DO_E M I
_ADDR [15]
IC Pin
Name
A15
IPP_IND_ADDR_
IN [15]
—
IPP_DO_WEIM_ADDR_
OUT[16]
—
IPP_DO_E M I
_ADDR [16]
A16
—
IPP_DO_WEIM_ADDR[1
7]
—
IPP_DO_E M I
_ADDR [17]
A17
—
IPP_DO_WEIM_ADDR[1
8]
—
IPP_DO_E M I
_ADDR [18]
A18
—
IPP_DO_WEIM_ADDR[1
9]
—
IPP_DO_E M I
_ADDR [19]
A19
—
IPP_DO_WEIM_ADDR[2
0]
—
IPP_DO_E M I
_ADDR [20]
A20
—
IPP_DO_WEIM_ADDR[2
1]
—
IPP_DO_E M I
_ADDR [21]
A21
—
IPP_DO_WEIM_ADDR[2
2]
—
IPP_DO_E M I
_ADDR [22]
A22
—
IPP_DO_WEIM_ADDR[2
3]
—
IPP_DO_E M I
_ADDR [23]
A23
—
IPP_DO_WEIM_ADDR[2
4]
—
IPP_DO_E M I
_ADDR [24]
A24
—
IPP_DO_WEIM_ADDR[2
5]
—
IPP_DO_E M I
_ADDR [25]
A25
Note:
ESDRAMC address bit M3IF_MA[10] has a dedicated pin MA10 (required due to precharge all during auto refresh commands)
ESDRAMC bank address bits have dedicated pins due to precharge bank during precharge timer timeout
WEIM CRE signal is driven on A23 in multiplexed mode operation.
M3IF_MA[10]
—
—
IPP_DO_M3IF
_MA10
MA10
BA[0]
—
—
SDBA0
BA[1]
—
—
IPP_DO_SDBA[1
:0]
SDBA1
Note: Since the SDBA pins are shared between the SDR/DDR SDRAM bank address CE‘, the ESDRAMC precharge timer
cannot be used.
SDRAM/LPDDR Dedicated Data Pins
WR_DATA[0]
RD_DATA[0]
—
—
IPP_DO_EMII_D
ATA [0]
SD0
IPP_IND_EMII_D
ATA_IN [0]
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Freescale Semiconductor
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
WR_DATA[1]
WEIM
NFC
—
—
RD_DATA[1]
WR_DATA[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD_DATA[10]
IPP_DO_EMII_D
ATA [5]
SD5
IPP_DO_EMII_D
ATA [6]
SD6
IPP_DO_EMII_D
ATA [7]
SD7
IPP_DO_EMII_D
ATA [8]
SD8
IPP_IND_EMII_D
ATA_IN [8]
—
—
RD_DATA[9]
WR_DATA[10]
SD4
IPP_IND_EMII_D
ATA_IN [7]
RD_DATA[8]
WR_DATA[9]
IPP_DO_EMII_D
ATA [4]
IPP_IND_EMII_D
ATA_IN [6]
RD_DATA[7]
WR_DATA[8]
SD3
IPP_IND_EMII_D
ATA_IN [5]
RD_DATA[6]
WR_DATA[7]
IPP_DO_EMII_D
ATA [3]
IPP_IND_EMII_D
ATA_IN [4]
RD_DATA[5]
WR_DATA[6]
SD2
IPP_IND_EMII_D
ATA_IN [3]
RD_DATA[4]
WR_DATA[5]
IPP_DO_EMII_D
ATA [2]
IPP_IND_EMII_D
ATA_IN [2]
RD_DATA[3]
WR_DATA[4]
SD1
IPP_IND_EMII_D
ATA_IN [1]
RD_DATA[2]
WR_DATA[3]
IPP_DO_EMII_D
ATA [1]
IC Pin
Name
IPP_DO_EMII_D
ATA [9]
SD9
IPP_IND_EMII_D
ATA_IN [9]
—
—
IPP_DO_EMII_D
ATA [10]
SD10
IPP_IND_EMII_D
ATA_IN [10]
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
23
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
WR_DATA[11]
WEIM
NFC
—
—
RD_DATA[11]
WR_DATA[12]
—
—
—
—
SD12
IPP_DO_EMII_D
ATA [13]
SD13
IPP_IND_EMII_D
ATA_IN [13]
—
—
RD_DATA[14]
WR_DATA[15]
IPP_DO_EMII_D
ATA [12]
IPP_IND_EMII_D
ATA_IN [12]
RD_DATA[13]
WR_DATA[14]
SD11
IPP_IND_EMII_D
ATA_IN [11]
RD_DATA[12]
WR_DATA[13]
IPP_DO_EMII_D
ATA [11]
IC Pin
Name
IPP_DO_EMII_D
ATA [14]
SD14
IPP_IND_EMII_D
ATA_IN [14]
—
—
RD_DATA[15]
IPP_DO_EMII_D
ATA [15]
SD15
IPP_IND_EMII_D
ATA_IN [15]
WEIM/NFC Data Multiplexing
—
—
—
IPP_DO_WEIM_ADDR_
DATA_OUT[16]
IPP_NFC_WRITE_DATA_OUT[0]
IPP_DO_NFC_W
RITE_
DATA_OUT [0]
IPP_IND_WEIM_ADDR_
DATA_IN[16]
IPP_NFC_READ_DATA_IN[0]
IPP_IND_NFC_R
EAD_ DATA_IN
[0]
IPP_DO_WEIM_ADDR_
DATA_OUT[17]
IPP_NFC_WRITE_DATA_OUT[1]
IPP_DO_NFC_W
RITE_
DATA_OUT [1]
IPP_IND_WEIM_ADDR_
DATA_IN[17]
IPP_NFC_READ_DATA_IN[1]
IPP_IND_NFC_R
EAD_ DATA_IN
[1]
IPP_DO_WEIM_ADDR_
DATA_OUT[18]
IPP_NFC_WRITE_DATA_OUT[2]
IPP_DO_NFC_W
RITE_
DATA_OUT [2]
IPP_IND_WEIM_ADDR_
DATA_IN[18]
IPP_NFC_READ_DATA_IN[2]
IPP_IND_NFC_R
EAD_ DATA_IN
[2]
D0
D1
D2
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Freescale Semiconductor
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
—
—
—
—
—
—
—
WEIM
NFC
IPP_DO_WEIM_ADDR_
DATA_OUT[19]
IPP_NFC_WRITE_DATA_OUT[3]
IPP_DO_NFC_W
RITE_
DATA_OUT [3]
IPP_IND_WEIM_ADDR_
DATA_IN[19]
IPP_NFC_READ_DATA_IN[3]
IPP_IND_NFC_R
EAD_ DATA_IN
[3]
IPP_DO_WEIM_ADDR_
DATA_OUT[20]
IPP_NFC_WRITE_DATA_OUT[4]
IPP_DO_NFC_W
RITE_
DATA_OUT [4]
IPP_IND_WEIM_ADDR_
DATA_IN[20]
IPP_NFC_READ_DATA_IN[4]
IPP_IND_NFC_R
EAD_ DATA_IN
[4]
IPP_DO_WEIM_ADDR_
DATA_OUT[21]
IPP_NFC_WRITE_DATA_OUT[5]
IPP_DO_NFC_W
RITE_
DATA_OUT [5]
IPP_IND_WEIM_ADDR_
DATA_IN[21
IPP_NFC_READ_DATA_IN[5]
IPP_IND_NFC_R
EAD_ DATA_IN
[5]
IPP_DO_WEIM_ADDR_
DATA_OUT[22]
IPP_NFC_WRITE_DATA_OUT[6]
IPP_DO_NFC_W
RITE_
DATA_OUT [6]
IPP_IND_WEIM_ADDR_
DATA_IN[22]
IPP_NFC_READ_DATA_IN[6]
IPP_IND_NFC_R
EAD_ DATA_IN
[6]
IPP_DO_WEIM_ADDR_
DATA_OUT[23]
IPP_NFC_WRITE_DATA_OUT[7]
IPP_DO_NFC_W
RITE_
DATA_OUT [7]
IPP_IND_WEIM_ADDR_
DATA_IN[23]
IPP_NFC_READ_DATA_IN[7]
IPP_IND_NFC_R
EAD_ DATA_IN
[7]
IPP_DO_WEIM_ADDR_
DATA_OUT[24]
IPP_NFC_WRITE_DATA_OUT[8]
IPP_DO_NFC_W
RITE_
DATA_OUT [8]
IPP_IND_WEIM_ADDR_
DATA_IN[24]
IPP_NFC_READ_DATA_IN[8]
IPP_IND_NFC_R
EAD_ DATA_IN
[8]
IPP_DO_WEIM_ADDR_
DATA_OUT[25]
IPP_NFC_WRITE_DATA_OUT[9]
IPP_DO_NFC_W
RITE_
DATA_OUT [9]
IPP_IND_WEIM_ADDR_
DATA_IN[25]
IPP_NFC_READ_DATA_IN[9]
IPP_IND_NFC_R
EAD_ DATA_IN
[9]
IC Pin
Name
D3
D4
D5
D6
D7
D8
D9
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Freescale Semiconductor
25
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
—
WEIM
IPP_DO_WEIM_ADDR_
DATA_OUT[26]
IPP_IND_WEIM_ADDR_
DATA_IN[26]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[27]
IPP_IND_WEIM_ADDR_
DATA_IN[27]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[28]
IPP_IND_WEIM_ADDR_
DATA_IN[28]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[29]
IPP_IND_WEIM_ADDR_
DATA_IN[29]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[30]
IPP_IND_WEIM_ADDR_
DATA_IN[30]
—
IPP_DO_WEIM_ADDR_
DATA_OUT[31]
IPP_IND_WEIM_ADDR_
DATA_IN[31
NFC
IPP_NFC_WRITE_DATA_OUT[10] IPP_DO_NFC_W
RITE_
DATA_OUT [10]
IPP_NFC_READ_DATA_IN[10]
D14
IPP_IND_NFC_R
EAD_ DATA_IN
[14]
IPP_NFC_WRITE_DATA_OUT[15] IPP_DO_NFC_W
RITE_
DATA_OUT [15]
IPP_NFC_READ_DATA_IN[15]
D13
IPP_IND_NFC_R
EAD_ DATA_IN
[13]
IPP_NFC_WRITE_DATA_OUT[14] IPP_DO_NFC_W
RITE_
DATA_OUT [14]
IPP_NFC_READ_DATA_IN[14]
D12
IPP_IND_NFC_R
EAD_ DATA_IN
[12]
IPP_NFC_WRITE_DATA_OUT[13] IPP_DO_NFC_W
RITE_
DATA_OUT [13]
IPP_NFC_READ_DATA_IN[13]
D11
IPP_IND_NFC_R
EAD_ DATA_IN
[11]
IPP_NFC_WRITE_DATA_OUT[12] IPP_DO_NFC_W
RITE_
DATA_OUT [12]
IPP_NFC_READ_DATA_IN[12]
D10
IPP_IND_NFC_R
EAD_ DATA_IN
[10]
IPP_NFC_WRITE_DATA_OUT[11] IPP_DO_NFC_W
RITE_
DATA_OUT [11]
IPP_NFC_READ_DATA_IN[11]
IC Pin
Name
D15
IPP_IND_NFC_R
EAD_ DATA_IN
[15]
Mask (Byte Enable) Multiplexing
—
—
IPP_DO_WEIM_EB_B[0]
—
—
—
IPP_DO_WEIM_EB_B[1]
—
IPP_DO_E M I
_IO_EB_B[1:0]
EB0
EB1
SDRAM/LPDDR Mask (Byte Enable)
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Freescale Semiconductor
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
SDRAMC
MDDRC
WEIM
NFC
DQM_X[0]
—
—
DQM_X[1]
—
—
IPP_DO_EMI_D
QM [3:0]
IC Pin
Name
DQM0
DQM1
Output Enable Multiplexing
—
—
IPP_DO_WEIM_OE_B
—
IPP_DO_EMI
_OE_B
OE
Chip Select Multiplexing
—
—
IPP_DO_WEIM_CS_B[0]
—
IPP_DO_WEIM_
CS_B0
CS0
—
—
IPP_DO_WEIM_CS_B[1]
—
IPP_DO_WEIM_
CS_B1
CS1
CS_B[0]
IPP_DO_WEIM_CS_B[2]
—
IPP_DO_WEIM_
CS_B2_CSD0
CS2
CS_B[1]
IPP_DO_WEIM_CS_B[3]
—
IPP_DO_WEIM_
CS_B3_CSD1
CS3
—
—
IPP_DO_WEIM_CS_B[4]
—
IPP_DO_WEIM_
CS_B4
CS4
—
—
IPP_DO_WEIM_CS_B[5]
—
IPP_DO_WEIM_
CS_B5
CS5
The chip select selectors are the system control register bits SDCTL_CSD0_SEL and SDCTL_CSD1_SEL respectively. THE
Default select for both chip selects is for the ESDRAMC/MDDRC.
Write Enable Multiplexing
—
—
IPP_DO_WEIM_RW_B
—
IPP_DO_WEIM_
RW_B
RW
SDRAM/LPDDR Command Dedicated Pins
RAS_B
—
—
IPP_DO_M3IF_R
AS_B
RAS
CAS_B
—
—
IPP_DO_M3IF_C
AS_B
CAS
WE_B
—
—
IPP_DO_SDRC_
SDWE
SDWE
CKE[1]
—
—
IPP_DO_SDRC_
SDCKE[1]
SDCKE
[1]
CKE[0]
—
—
IPP_DO_SDRC_
SDCKE[0]
SDCKE
[0]
SDCLK_OUT
—
—
IPP_DO_SDRC_
SDCLK
SDCLK
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
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27
External Memory Interface (EMI)
Table 20-5. EMI Outputs to IC Pins (continued)
Memory Controllers Outputs
EMI Output
IC Pin
Name
DQS[1]
SDRAMC
MDDRC
WEIM
NFC
—
DQS_OUT
[1]
—
—
IPP_DO_DQS[1]
—
DQS_IN [1]
—
—
IPP_IND_DQS[1]
—
DQS_OUT
[0]
—
—
IPP_DO_DQS[0]
—
DQS_IN [0]
—
—
IPP_IND_DQS[0]
DQS[0]
NFC Command Dedicated Pins
—
—
—
IPP_NFC_WE_OUT
IPP_NFC_WE_O NFWE_B
UT
—
—
—
IPP_NFC_WP_OUT
IPP_NFC_WP_O NFWP_B
UT
—
—
—
IPP_NFC_RE_OUT
IPP_NFC_RE_O
UT
NFRE_B
—
—
—
IPP_NFC_ALE_OUT
IPP_NFC_ALE_
OUT
NFALE
—
—
—
IPP_NFC_CLE_OUT
IPP_NFC_CLE_
OUT
NFCLE
—
—
—
IPP_NFC_CE0_OUT
IPP_NFC_CE0_
OUT
NFCE0_
B
—
—
—
IPP_NFC_CE1_OUT
IPP_NFC_CE1_
OUT
NFCE1_
B
—
—
—
IPP_NFC_CE2_OUT
IPP_NFC_CE2_
OUT
NFCE2_
B
—
—
—
IPP_NFC_CE3_OUT
IPP_NFC_CE3_
OUT
NFCE3_
B
—
—
—
IPP_NFC_RB_IN
IPP_IND_NFC_R
B_IN
NFRB
WEIM Command Dedicated Pins
—
—
IPP_DO_WEIM_LBA_B
—
IPP_DO_WEIM_
LBA_B
LBA_B
—
—
IPP_DO_WEIM_BCLK
—
IPP_DO_WEIM_
BCLK
BCLK
—
—
IPP_IND_WEIM_ECB_B
—
IPP_IND_WEIM_
ECB_B
ECB
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Freescale Semiconductor
Chapter 21
Enhanced Periodic Interrupt Timer (EPIT)
This chapter describes a module integrated into an SoC. The chapter is intended for a module driver
software developer. It describes module-level operation and programming. To understand how the module
is integrated at the SoC level, a system software developer should see discussions of the module in the
appropriate SoC-level chapter(s).
21.1
Overview
The enhanced periodic interrupt timer (EPIT) is a 32-bit set-and-forget timer that begins counting after the
EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal
processor intervention. Figure 21-1 illustrates the block diagram of the EPIT.
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
21-1
Enhanced Periodic Interrupt Timer (EPIT)
Clock off
Peripheral Clock
12 bit Prescaler
Low Frequency Reference Clock
1... 4096
High Frequency Reference Clock
Prescaled
Clock
Peripheral Bus
Counter Reload
32
Counter Register
32 bit
Load Register
ITIF
DO_EPITO
OM
CMP
ITIE
32 bit
interrupt
Compare Register
32 bit
Figure 21-1. Enhanced Periodic Interrupt Timer Block Diagram
21.1.1
Features
Key features of the EPIT include:
• 32-bit down counter with clock source selection
• 12-bit prescaler for division of input clock frequency
• Counter value can be programmed on the fly
• Can be programmed to be active during low-power modes
• Interrupt generation when counter reaches the Compare value
21.1.2
Modes and Operations
The EPIT supports the modes described in the indicated sections:
• Section 21.4.1, “Operating Modes”
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
21-2
Freescale Semiconductor
Enhanced Periodic Interrupt Timer (EPIT)
— Section 21.4.1.1, “Set-and-Forget Mode”
— Section 21.4.1.2, “Free-Running Mode”
The EPIT supports the operations as described in Section 21.4.2, “Operations.”
21.2
External Signals
Table 21-1 describes all EPIT signals that connect off-chip.
Table 21-1. Off-Chip Module Signals
Name
I/O
DO_EPITO
21.3
O
Description
Output pin at chip boundary for indication of occurrence of output
compare event through a specified transition.
Reset
State
Pull Up
0
—
Memory Map and Register Definitions
The EPIT module includes five user-accessible 32-bit registers. Table 21-2 summarizes these registers and
their addresses.
Peripheral bus write access to the EPIT control register (EPITCR) and the EPIT load register (EPITLR)
results in one cycle of wait state, while other valid peripheral bus accesses are with 0 wait state.
21.3.1
Memory Map
For the base address of a particular module instantiation, see the system memory map. Table 21-2 shows
the memory map for the EPIT registers.
Table 21-2. EPIT Memory Map
Base Address Offset
(Register Abbreviation)
Register
Access
Reset Value
Section/Page
0x0004 (EPITSR)
Control register
R/W
0x0000_0000
21.3.3.1/21-5
0x0004 (EPITSR)
Status register
R/W
0x0000_0000
21.3.3.2/21-7
0x0008 (EPITLR)
Load register
R/W
0xFFFF_FFFF
21.3.3.3/21-8
0x000C (EPITCMPR)
Compare register
R/W
0x0000_0000
21.3.3.4/21-9
0x0010 (EPITCNR)
Counter register
R
0xFFFF_FFFF
21.3.3.5/21-9
i.MX25 Multimedia Applications Processor Reference Manual, Rev. 2
Freescale Semiconductor
21-3
Enhanced Periodic Interrupt Timer (EPIT)
21.3.2
Register Summary
The EPIT registers are summarized in Table 21-3.
Table 21-3. EPIT Register Summary
Base Address
Offset (Register
Abbreviation)
R
0x0000 (EPITCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
W
R
0x0004 (EPITSR)
STOP
WAIT DBGE
RES
IOVW SWR
EN
EN
N
OM
PRESCALER[15:4]
W
R
CLKSRC
RLD
OCIE ENM
N
OD
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCIF
W
R
W
w1c
R
0x0008 (EPITLR)
LOAD[31:16]
W
R
LOAD[15:0]
W
R
COMPARE[31:16]
0x000C (EPITCMP W
R)
R
COMPARE[15:0]
W
COUNT[31:16]
R
0x0010 (EPITCNR)
W
R
COUNT[15:0]
W
21.3.3
Register Descriptions
This section provides detailed descriptions of the module’s registers. Figure 21-2 and Table 21-4 explain
conventions used in register diagrams and tables.
Always
reads 1
1
Always
reads 0
0
R/W
Read- BIT WriteWrite 1 BIT
Read rtc Self-clear 0 N/A
bit BIT only bit
only bit BIT to clear w1c to clear BIT
bit BIT
Figure 21-2. Register Field Conventions
Table 21-4. General Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
BIT
Bit or field name. Its presence in the read or write row indicates that it can correspondingly be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
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Enhanced Periodic Interrupt Timer (EPIT)
Table 21-4. General Register Conventions (continued)
Convention
W
Description
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
rtc
Read to clear. A read-only status bit that is automatically cleared when read.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
Reset Values
0
Resets to 0 (zero).
1
Resets to 1 (one).
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
21.3.3.1
Reset value is determined by polarity of indicated signal.
EPIT Control Register
The EPIT control register (EPITCR) is used to configure the operating settings of the EPIT. It contains the
clock division prescaler value and also the interrupt enable bit. Additionally it contains other control bit
which are outlined below.
Peripheral Bus Write access to EPIT Control Register (EPITCR) results in one cycle of the wait state,
while other valid peripheral bus accesses are with 0 wait state.
Figure 21-3 shows the register. Table 21-5 describes the register fields.
Offset 0x0000 (EPITCR)
R
Access: User read/write
31
30
29
28
27
26
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
W
Reset
R
24
23
CLKSRC
22
21
20
STOP
EN
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
OM
PRESCALAR[15:4]
W
Reset
25
0
0
0
0
0
0
0
19
RLD
0
0
0
0
18
17
16
WAIT DBG
IOVW SWR
EN
EN
0
0
OCIE ENM
N
OD
0
0
EN
0
Figure 21-3. EPIT Control Register
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Freescale Semiconductor
21-5
Enhanced Periodic Interrupt Timer (EPIT)
Table 21-5. EPIT Control Register Field Description
Field
31–26
Description
Reserved.
25–24 Select clock source
CLKSRC These bits determine which clock input is to be selected for running the counter. This field value should only be
changed when the EPIT is disabled by clearing the EN bit in this register. For other programming requirements while
changing clock source, refer to Section 21.5.1, “Change of Clock Source.”
00 Clock is off
01 Peripheral clock
10 High-frequency reference clock
11 Low-frequency reference clock
23–22
OM
EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
00 EPIT output is disconnected from pad
01 Toggle output pin
10 Clear output pin
11 Set output pin
21
EPIT stop mode enable. This read/write control bit enables the operation of the EPIT during stop mode. This bit is
STOPEN reset by a hardware reset and unaffected by software reset.
0 EPIT is disabled in stop mode
1 EPIT is enabled in stop mode
20
Reserved.
19
This read/write control bit enables the operation of the EPIT during wait mode. This bit is reset by a hardware reset.
WAITEN A software reset does not affect this bit.
0 EPIT is disabled in wait mode
1 EPIT is enabled in wait mode
18
DBGEN
This bit is used to keep the EPIT functional in debug mode. When this bit is cleared, the input clock is gated off in
debug mode.This bit is reset by hardware reset. A software reset does not affect this bit.
0 Inactive in debug mode
1 Active in debug mode
17
IOVW
EPIT counter overwrite enable. This bit controls the counter data when the modulus register is written. When this
bit is set, all writes to the load register overwrites the counter contents and the counter starts subsequently counting
down from the programmed value.
0 Write to load register does not result in counter value being overwritten.
1 Write to load register results in immediate overwriting of counter value.
16
SWR
Software reset. The EPIT module is reset when this bit is set to 1. It is a self clearing bit. This bit is set when the
module is in reset state and is cleared when the reset procedure is over. Setting this bit resets all the registers to
their reset values, except for the EN, ENMOD, STOPEN, WAITEN and DBGEN bits in this control register
0 EPIT is out of reset
1 EPIT is undergoing reset
15–4
Counter clock prescaler value. This bit field determines the prescaler value by which the clock is divided before it
PRESCA goes to the counter
LAR
0x000 Divide by 1
0x001 Divide by 2
…
0xFFFF Divide by 4096
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Enhanced Periodic Interrupt Timer (EPIT)
Table 21-5. EPIT Control Register Field Description (continued)
Field
3
RLD
Description
Counter reload control
This bit is cleared by hardware reset. It decides the counter functionality, whether to run in free-running mode or
set-and-forget mode.
0 When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode)
1 When the counter reaches zero it reloads from the modulus register (set-and-forget mode)
2
OCIEN
Output compare interrupt enable
This bit enables the generation of interrupt on occurrence of compare event.
0 Compare interrupt disabled
1 Compare interrupt enabled
1
EPIT enable mode
ENMOD When EPIT is disabled (EN=0), then both main counter and prescaler counter freeze their count at current count
values. ENMOD bit is a r/w bit that determines the counter value when the EPIT is enabled again by setting EN bit.
If ENMOD bit is set, then main counter is loaded with the load value (If RLD=1)/ 0xFFFF_FFFF (If RLD=0) and
prescaler counter is reset, when EPIT is enabled (EN=1). If ENMOD is programmed to 0 then both main counter
and prescaler counter restart counting from their frozen values when EPIT is enabled (EN=1). If EPIT is
programmed to be disabled in a low-power mode (STOP/WAIT/DEBUG), then both the main counter and the
prescaler counter freeze at their current count values when EPIT enters low-power mode. When EPIT exits the
low-power mode, both main counter and prescaler counter start counting from their frozen values irrespective of the
ENMOD bit. This bit is reset by a hardware reset. A software reset does not affect this bit.
0 Counter starts counting from the value it had when it was disabled.
1 Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0)
0
EN
This bit enables the EPIT. EPIT counter and prescaler value when EPIT is enabled (EN =1), is dependent upon
ENMOD and RLD bit as described for ENMOD bit. It is recommended that all registers be properly programmed
before setting this bit. This bit is reset by a hardware reset. A software reset does not affect this bit.
0 EPIT is disabled
1 EPIT is enabled
21.3.3.2
EPIT Status Register
The EPIT status register (EPITSR) has a single status bit for the output compare event. The bit is a
write 1 to clear bit.
Figure 21-4 shows the register. Table 21-6 describes the register fields.
Offset 0x0004 (EPITSR)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
w1c
0
Figure 21-4. EPIT Status Register
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Freescale Semiconductor
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Enhanced Periodic Interrupt Timer (EPIT)
Table 21-6. EPIT Status Register Field Description
Field
Description
31–1
Reserved.
0
OCIF
Output compare interrupt flag. This bit is the interrupt flag that is set when the content of counter equals the content
of the compare register (EPITCMPR). The bit is a write 1 to clear bit.
0 Compare event hasn’t occurred
1 Compare event occurred
21.3.3.3
EPIT Load Register
The EPIT load register (EPITLR) contains the value that is to be loaded into the counter when EPIT
counter reaches zero if the RLD bit in EPITCR is set. If the IOVW bit in the EPITCR is set then a write to
this register overwrites the value of the EPIT counter register in addition to updating this registers value.
This overwrite feature is active even if the RLD bit is not set.
Figure 21-5 shows the register. Table 21-7 describes the register fields.
Offset 0x0008 (EPITLR)
31
30
29
Access: User read/write
28
27
26
25
R
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
LOAD[15:0]
W
Reset
23
LOAD[31:16]
W
Reset
24
1
1
1
1
1
1
1
1
1
Figure 21-5. EPIT Load Register
Table 21-7. EPIT Load Register Field Description
Field
31–0
LOAD
Description
Load value. Value that is loaded into the counter at the start of each count cycle.
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Enhanced Periodic Interrupt Timer (EPIT)
21.3.3.4
EPIT Compare Register
The EPIT compare register (EPITCMPR) holds the value that determines when a compare event is
generated.
Figure 21-6 shows the register. Table 21-8 describes the register fields.
Offset 0x000C (EPITCMPR)
31
30
29
Access: User read/write
28
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
COMPARE[15:0]
W
Reset
23
COMPARE[31:16]
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 21-6. EPIT Compare Register
Table 21-8. EPIT Compare Register Field Description
Field
Description
31–0
Compare Value. When the counter value equals this bit field value a compare event is generated.
COMPARE
21.3.3.5
EPIT Counter Register
The EPIT counter register (EPITCNR) contains the current count value and can be read at any time without
disturbing the counter. This is a read-only register and any attempt to write into it generates a transfer error.
But if the IOVW bit in EPITCR is set, the value of this register can be overwritten with a write to EPITLR.
This change is reflected when this register is subsequently read.
Figure 21-7 shows the register. Table 21-9 describes the register fields.
.
Offset 0x0010 (EPITCNR)
31
30
29
Access: User read-only
28
27
26
25
R
24
23
22
21
20
19
18
17
16
COUNT[31:16]
W
Reset
1
1
1
1
1
1
1
15
14
13
12
11
10
9
R
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
COUNT[15:0]
W
Reset
1
1
1
1
1
1
1
1
1
Figure 21-7. EPIT Counter Register
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Freescale Semiconductor
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Enhanced Periodic Interrupt Timer (EPIT)
Table 21-9. EPIT Counter Register Field Description
Field
Description
31–0
COUNT
21.4
Counter value. This contains the current value of the counter.
Functional Description
This section provides a complete functional description of the module.
21.4.1
Operating Modes
This section describes all functional operation modes of the module. The EPIT can be programmed to
function in set-and-forget or free-running modes.
21.4.1.1
Set-and-Forget Mode
This mode of operation is selected when the RLD bit in control register (EPITCR) is set to a value of one.
The counter cannot be directly written from the module data bus. Instead, it gets its data from the load
register (EPITLR). Whenever the counter reaches a count of zero, the value in EPITLR is loaded into the
counter to be decremented toward zero. The counter can be directly initialized, without having to wait for
the count to reach zero, when the EPITLR is written while the IOVW bit in EPITCR is set to 1.
21.4.1.2
Free-Running Mode
This mode of operation is selected when the RLD bit is cleared. In this mode, the counter rolls over from
0x0000_0000 to 0xFFFF_FFFF without reloading from the modulus register and continues to count down.
In this mode when writing to EPITLR with the required initialization value after having set the IOVW bit,
the counter can also be directly initialized.
21.4.2
Operations
The EPIT has a single 32-bit down counter which starts counting when the module is enabled by software.
The start value of the counter is loaded from the EPIT load register which can be written to at any time by
the processor. The value in the compare register determines the time of occurrence of the interrupt.
When EPIT is disabled (EN=0), then both main counter and prescaler counter freeze their count at current
count values. ENMOD bit is a r/w bit which decides the counter value when the EPIT is enabled again by
setting EN bit. If ENMOD bit is set, then main counter is loaded with the load value (If RLD=1)/
0xFFFF_FFFF (If RLD=0) and prescaler counter is reset (0x000), when EPIT is enabled (EN=1). If
ENMOD is programmed to 0 then both main counter and prescaler counter restart counting from their
frozen values, when EPIT is enabled (EN=1). If EPIT is programmed to be disabled in a low-power mode
(STOP/WAIT), then both the main counter and the prescaler counter freeze at their current count values
when EPIT enters low-power mode. When EPIT exits the low-power mode, both main counter and
prescaler counter start counting from their frozen values irrespective of the ENMOD bit.
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Enhanced Periodic Interrupt Timer (EPIT)
A hardware reset resets all EPIT registers to their respective reset values. There is a software reset which
has the same effect on all registers except for the EN, ENMOD, STOPEN and WAITEN bits in the control
register. The state of these bits are not affected by software reset. A software reset can be asserted even
when the EPIT is disabled.
21.4.3
Clocks
The clock that feeds the prescaler can be selected from among the following sources:
• High-frequency reference clock
This clock is provided by the clock controller module (CCM). This clock remains on during
low-power mode when the peripheral clock is turned off, allowing EPIT to use this clock in
low-power mode. In normal mode, the CCM synchronizes this clock to ahb_clk; in low-power
mode, CCM switches to an unsynchronized version.
• Low-frequency reference clock
This 32 kHz reference clock is provided by the CCM. This clock remains on in low-power mode
when the peripheral clock is turned off, so EPIT can use this clock during low-power mode. In
normal mode, the CCM synchronizes this clock to ahb_clk; in low-power mode, CCM switches to
an unsynchronized version. This clock is derived from the external 32kHz crystal.
• Peripheral clock
This is the peripheral clock (PER Clock) which is provided (and optionally gated) by the CCM.
This clock is typically used in normal operations. In low-power modes, if the EPIT is programmed
to be disabled (using STOPEN or WAITEN), then the peripheral clock can be switched off.
The clock input source is determined by the CLKSRC field in the control register. The clock input to the
prescaler can also be disabled by setting CLKSRC to 0b00. This field value should only be changed after
first disabling the EPIT by clearing the EN bit in the EPITCR. For other programming requirements that
apply while changing clock source, refer section Section 21.5.1, “Change of Clock Source.”
The PRESCALER field in the control register is used to select the divide ratio of the input clock that drives
the main counter. The prescaler can divide the input clock by a value between 1 and 4096. A change in the
value of the PRESCALER field is immediately reflected on its output clock frequency. Figure 21-8 shows
the timing for a change in the prescaler value.
Clk
Prescaler Value
100
010
Prescaled Clk
Figure 21-8. Prescaler Value Change Diagram
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Freescale Semiconductor
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Enhanced Periodic Interrupt Timer (EPIT)
21.4.4
Compare Event
When the programmed value of EPITCMPR matches the value in EPITCNR a compare status flag is set,
and an interrupt is generated if the OCIEN bit is set in the control register. The compare output pin is set,
cleared, toggled, or not affected at all depending on the setting of the output mode (OM) bits in the control
register. If an interrupt is required at rollover (when the counter value reaches 0x0000_0000 and the new
value is loaded) then the compare register value should be set equal to the load register value in
set-and-forget mode, or equal to 0xFFFF_FFFF in free-running mode.
Figure 21-9 shows the timing for a compare event and interrupt.
Clk
Counter
0
4
3
2
1
0
4
3
Compare Value
2
Load Value
4
Output Mode
Output Signal
2
1
001
toggle
0
4
010
clear
3
2
1
0
011
set
Interrupt
Figure 21-9. Compare Event and Interrupt Timing Diagram
21.4.4.1
Counter Value Overwrite
The EPIT counter value can be overwritten to acquire a desired value at any point of time. The procedure
for this is to set the IOVW bit in the control register and then write the desired value into the load register.
This results in the load register acquiring that value and also the counter being overwritten with it. If the
EPIT is running the counter resumes counting from the overwritten value.
21.4.4.2
Low-Power Mode Behavior
The EPIT timer’s behavior in low-power modes depends on which clock source is being used. If the
selected clock source is available and the corresponding low-power enable bit is set, then the EPIT
continues to function in the low-power mode. If the EPIT is programmed to be disabled in a low-power
mode (STOP/WAIT), then main counter and the prescaler counter freeze at the current count values when
the EPIT enters low-power mode. When the EPIT exits the low-power mode, both main counter and
prescaler counter start counting from their frozen values irrespective of the ENMOD bit.
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Enhanced Periodic Interrupt Timer (EPIT)
21.4.4.3
Debug Mode Behavior
In debug mode, the user has the option to run or halt the EPIT timers. If the DBGEN bit is reset in the EPIT
control Register, the timer is halted. When debug mode is exited, the timer operation reverts to what it was
prior to entering debug mode.
21.5
21.5.1
Initialization/Application Information
Change of Clock Source
The CLKSRC field in EPITCR determines the clock source. This field value should be changed only after
disabling the EPIT (EN = 0). Below is the software sequence which must be followed while changing clock
source.
1. Disable the EPIT by setting EN=0 in EPITCR.
2. Program OM=00 in the EPITCR.
3. Disable the EPIT interrupts.
4. Program CLKSRC to desired clock source in EPITCR.
5. Clear the EPIT status register (EPITSR) i.e. (w1c).
6. Enable the EPIT interrupts.
7. Set ENMOD= 1 in the EPITCR, to bring the EPIT Counter to defined state (EPITLR value or
0xFFFF_FFFF).
8. Enable EPIT (EN=1) in the EPITCR.
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Enhanced Periodic Interrupt Timer (EPIT)
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Chapter 22
Enhanced Serial Audio Interface (ESAI)
22.1
Introduction
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication
with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other DSPs.
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator.
The ESAI block diagram is shown in Figure 22-1. The ESAI is named synchronous because all serial
transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word
frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The
network mode is similar in that it is also intended for periodic transfers; however, it supports up to
32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer
data serially at high speed when the data becomes available.
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Freescale Semiconductor
22-1
Enhanced Serial Audio Interface (ESAI)
TX
FIFO
RX
FIFO
IP Bus DMA Bus
TX0
RSMA
SDO0 [PC11]
RSMB
Shift Register
TSMA
TX1
TSMB
SDO1 [PC10]
Shift Register
RCCR
TX2
RCR
SDO2/SDI3 [PC9]
Shift Register
TCCR
RX3
TCR
TX3
SDO3/SDI2 [PC8]
SAICR
Shift Register
SAISR
RX2
TX4
TSR
SDO4/SDI1 [PC7]
Shift Register
RX1
Clock / Frame Sync
Generators
and
Control Logic
TX5
RCLK
SDO5/SDI0 [PC6]
Shift Register
[PC2] HCKR
[PC1] FSR
[PC0] SCKR
[PC5] HCKT
[PC4] FST
[PC3] SCKT
TCLK
RX0
Figure 22-1. ESAI Block Diagram
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Freescale Semiconductor
Enhanced Serial Audio Interface (ESAI)
22.1.1
•
•
•
•
•
•
•
•
•
Features
Independent (asynchronous mode) or shared (synchronous mode) transmit and receive sections
with separate or shared internal/external clocks and frame syncs, operating in Master or Slave
mode.
Up to 6 transmitters and 4 receivers with SDO2/SDI3, SDO3/SDI2, SDO4/SDI1 and SDO5/SDI0
pins shared by transmitters 2 to 5 and receivers 0 to 3. SDO0 and SDO1 pins are used by
transmitters 0 and 1 only.
Programmable data interface modes supported are I2S, LSB aligned, MSB aligned
Programmable word length (8, 12, 16, 20, or 24 bits)
Flexible selection between system clock or external oscillator as input clock source, programmable
internal clock divider and frame sync generation
AC97 support
Time Slot Mask Registers for reduced CPU overhead (both transmit and receive)
128-word Transmit FIFO shared by six transmitters
128-word Receive FIFO shared by four receivers
22.1.2
Modes of Operation
ESAI has three basic operating modes and many data/operation formats. ESAI operating mode are selected
by the ESAI control registers (TCCR, TCR, RCCR, RCR, and SAICR). The main operating modes are
described in the following paragraphs.
22.1.2.1
Normal/Network/On-Demand Mode Selection
Selecting between the normal mode and network mode is accomplished by clearing or setting the
TMOD0-TMOD1 bits in the TCR register for the transmitter section, as well as in the RMOD0-RMOD1
bits in the RCR register for the receiver section.
For normal mode, the ESAI functions with one data word of I/O per frame (per enabled transmitter or
receiver). The normal mode is typically used to transfer data to/from a single device.
For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0 to 32 data words
of I/O may be received/transmitted. In either case, the transfers are periodic. The frame sync signal
indicates the first time slot in the frame. Network mode is typically used in time division multiplexed
(TDM) networks of codecs, DSPs with multiple words per frame, or multi-channel devices.
Selecting the network mode and setting the frame rate divider to zero (DC=00000) selects the on-demand
mode. This special case does not generate a periodic frame sync. A frame sync pulse is generated only
when data is available to transmit. The on-demand mode requires that the transmit frame sync be internal
(output) and the receive frame sync be external (input). Therefore, for simplex operation, the synchronous
mode could be used; however, for full-duplex operation, the asynchronous mode must be used. Data
transmission that is data driven is enabled by writing data into each TX. Although the ESAI is double
buffered, only one word can be written to each TX, even if the transmit shift register is empty. The receive
and transmit interrupts function as usual using TDE and RDF; however, transmit underruns are impossible
for on-demand transmission and are disabled.
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22.1.2.2
Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESAI may be synchronous or asynchronous, that is, the transmitter
and receiver sections may use common clock and synchronization signals (synchronous operating mode),
or they may have their own separate clock and sync signals (asynchronous operating mode). The SYN bit
in the SAICR register selects synchronous or asynchronous operation. Since the ESAI is designed to
operate either synchronously or asynchronously, separate receive and transmit interrupts are provided.
When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are independent.
If SYN is set, the ESAI transmitter and receiver clocks and frame sync come from the transmitter section
(either external or internal sources).
Data clock and frame sync signals can be generated internally by the ARM-core or may be obtained from
external sources. If internally generated, the ESAI clock generator is used to derive high frequency clock,
bit clock and frame sync signals from the ARM-core internal system clock.
22.1.2.3
Frame Sync Selection
The frame sync can be either a bit-long or word-long signal. The transmitter frame format is defined by
the TFSL bit in the TCR register. The receiver frame format is defined by the RFSL bit in the RCR register.
1. In the word-long frame sync format, the frame sync signal is asserted during the entire word data
transfer period. This frame sync length is compatible with codecs, SPI serial peripherals, serial A/D
and D/A converters, shift registers and telecommunication PCM serial I/O.
2. In the bit-long frame sync format, the frame sync signal is asserted for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel and National
components, codecs and telecommunication PCM serial I/O.
The relative timing of the word length frame sync as referred to the data word is specified by the TFSR bit
in the TCR register for the transmitter section and by the RFSR bit in the RCR register for the receive
section. The word length frame sync may be generated (or expected) with the first bit of the data word, or
with the last bit of the previous word. TFSR and RFSR are ignored when a bit length frame sync is selected.
Polarity of the frame sync signal may be defined as positive (asserted high) or negative (asserted low). The
TFSP bit in the TCCR register specifies the polarity of the frame sync for the transmitter section. The
RFSP bit in the RCCR register specifies the polarity of the frame sync for the receiver section.
The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is set) only when the
previous frame is completed. If the frame sync goes high before the frame is completed (or before the last
bit of the frame is received in the case of a bit frame sync or a word length frame sync with RFSR set), the
current frame sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent, that is, a new frame sync does not have to immediately follow the
previous frame. Gaps of arbitrary periods can occur between frames. Enabled transmitters are tri-stated
during these gaps.
When operating in the synchronous mode (SYN=1), all clocks including the frame sync are generated by
the transmitter section.
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22.1.2.4
Shift Direction Selection
Some data formats, such as those used by codecs, specify MSB first while other data formats, such as the
AES-EBU digital audio interface, specify LSB first. The MSB/LSB first selection is made by
programming RSHFD bit in the RCR register for the receiver section and by programming the TSHFD bit
in the TCR register for the transmitter section.
22.2
External Signal Description
Three to twelve pins are required for operation, depending on the operating mode selected and the number
of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by transmitters 0 and 1 only. The
SDO2/SDI3, SDO3/SDI2, SDO4/SDI1 and SDO5/SDI0 pins are shared by transmitters 2 to 5 with
receivers 0 to 3. The actual mode of operation is selected under software control. All transmitters operate
fully synchronized under control of the same transmitter clock signals. All receivers operate fully
synchronized under control of the same receiver clock signals.
22.2.1
Serial Transmit 0 Data Pin (SDO0)
SDO0 is used for transmitting data from the TX0 serial transmit shift register. SDO0 is an output when
data is being transmitted from the TX0 shift register. In the on-demand mode with an internally generated
bit clock, the SDO0 pin becomes high impedance for a full clock period after the last data bit has been
transmitted, assuming another data word does not follow immediately. If a data word follows immediately,
there is no high-impedance interval.
SDO0 may be programmed as a disconnected pin (PC11) when the ESAI SDO0 function is not being used.
(See Table 22-38.)
22.2.2
Serial Transmit 1 Data Pin (SDO1)
SDO1 is used for transmitting data from the TX1 serial transmit shift register. SDO1 is an output when
data is being transmitted from the TX1 shift register. In the on-demand mode with an internally generated
bit clock, the SDO1 pin becomes high impedance for a full clock period after the last data bit has been
transmitted, assuming another data word does not follow immediately. If a data word follows immediately,
there is no high-impedance interval.
SDO1 can be programmed as a disconnected pin (PC10) when the ESAI SDO1 function is not being used.
(See Table 22-38.)
22.2.3
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3)
SDO2/SDI3 is used as the SDO2 for transmitting data from the TX2 serial transmit shift register when
programmed as a transmitter pin, or as the SDI3 signal for receiving serial data to the RX3 serial receive
shift register when programmed as a receiver pin. SDO2/SDI3 is an input when data is being received by
the RX3 shift register. SDO2/SDI3 is an output when data is being transmitted from the TX2 shift register.
In the on-demand mode with an internally generated bit clock, the SDO2/SDI3 pin becomes high
impedance for a full clock period after the last data bit has been transmitted, assuming another data word
does not follow immediately. If a data word follows immediately, there is no high-impedance interval.
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Enhanced Serial Audio Interface (ESAI)
SDO2/SDI3 may be programmed as a disconnected pin (PC9) when the ESAI SDO2 and SDI3 functions
are not being used. (See Table 22-38.)
22.2.4
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)
SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register
when programmed as a transmitter pin, or as the SDI2 signal for receiving serial data to the RX2 serial
receive shift register when programmed as a receiver pin. SDO3/SDI2 is an input when data is being
received by the RX2 shift register. SDO3/SDI2 is an output when data is being transmitted from the TX3
shift register. In the on-demand mode with an internally generated bit clock, the SDO3/SDI2 pin becomes
high impedance for a full clock period after the last data bit has been transmitted, assuming another data
word does not follow immediately. If a data word follows immediately, there is no high-impedance
interval.
SDO3/SDI2 may be programmed as a disconnected pin (PC8) when the ESAI SDO3 and SDI2 functions
are not being used. (See Table 22-38.)
22.2.5
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)
SDO4/SDI1 is used as the SDO4 signal for transmitting data from the TX4 serial transmit shift register
when programmed as transmitter pin, or as the SDI1 signal for receiving serial data to the RX1 serial
receive shift register when programmed as a receiver pin. SDO4/SDI1 is an input when data is being
received by the RX1 shift register. SDO4/SDI1 is an output when data is being transmitted from the TX4
shift register. In the on-demand mode with an internally generated bit clock, the SDO4/SDI1 pin becomes
high impedance for a full clock period after the last data bit has been transmitted, assuming another data
word does not follow immediately. If a data word follows immediately, there is no high-impedance
interval.
SDO4/SDI1 may be programmed as a disconnected pin (PC7) when the ESAI SDO4 and SDI1 functions
are not being used. (See Table 22-38.)
22.2.6
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)
SDO5/SDI0 is used as the SDO5 signal for transmitting data from the TX5 serial transmit shift register
when programmed as transmitter pin, or as the SDI0 signal for receiving serial data to the RX0 serial shift
register when programmed as a receiver pin. SDO5/SDI0 is an input when data is being received by the
RX0 shift register. SDO5/SDI0 is an output when data is being transmitted from the TX5 shift register. In
the on-demand mode with an internally generated bit clock, the SDO5/SDI0 pin becomes high impedance
for a full clock period after the last data bit has been transmitted, assuming another data word does not
follow immediately. If a data word follows immediately, there is no high-impedance interval.
SDO5/SDI0 may be programmed as a disconnected pin (PC6) when the ESAI SDO5 and SDI0 functions
are not being used. (See Table 22-38.)
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22.2.7
Receiver Serial Clock (SCKR)
SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI interface. The direction
of this pin is determined by the RCKD bit in the RCCR register.The SCKR operates as a clock input or
output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR
register. When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR
register, and the data in the OF0 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When this pin is configured as the input flag IF0, the data value at the
pin is stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the
slot in network mode.
SCKR may be programmed as a disconnected pin (PC0) when the ESAI SCKR function is not being used.
(See Table 22-38.)
NOTE
Although the external ESAI serial clocks can be independent of and
asynchronous to the internal 133 MHz ESAI system clock, the external
ESAI serial clock frequency cannot exceed 133MHz/4 = 33.25 MHz and
each external ESAI serial clock phase must exceed the minimum of 2 x
1/133MHz = 15.04ns.
For SCKR pin mode definitions, see Table 22-29.
Table 22-1 provides a list of asynchronous-mode receiver clock sources. For more information about
EXTAL/ESAI clocking control bits (ERI,ERO), see Table 22-8.
Table 22-1. Receiver Clock Sources (Asynchronous Mode Only)
RHCKD
RFSD
RCKD
ERI
ERO
Receiver
Bit Clock
Source
0
0
0
N/A
N/A
SCKR
0
0
1
N/A
N/A
HCKR
0
1
0
N/A
N/A
SCKR
FSR
0
1
1
N/A
N/A
HCKR
FSR
1
0
0
0
0
SCKR
HCKR
1
0
0
0
1
SCKR
HCKR
1
0
0
1
0
SCKR
HCKR
1
0
0
1
1
SCKR
HCKR
1
OUTPUTS
SCKR
SCKR
1
0
1
0
0
Fsys
HCKR
SCKR
1
0
1
0
1
Fsys
HCKR
SCKR
0
EXTAL2
HCKR
SCKR
1
0
1
1
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Table 22-1. Receiver Clock Sources (Asynchronous Mode Only) (Continued)
RHCKD
RFSD
RCKD
ERI
ERO
Receiver
Bit Clock
Source
1
0
1
1
1
EXTAL
HCKR
1
1
0
0
0
SCKR
HCKR
FSR
1
1
0
0
1
SCKR
HCKR
FSR
1
1
0
1
0
SCKR
HCKR
FSR
1
1
0
1
1
SCKR
HCKR
FSR
1
1
1
0
0
Fsys
HCKR
FSR
SCKR
1
1
1
0
1
Fsys
HCKR
FSR
SCKR
1
1
1
1
0
EXTAL
HCKR
FSR
SCKR
1
1
1
1
1
EXTAL
HCKR
FSR
SCKR
OUTPUTS
SCKR
Note:
1. Fsys = 133MHz for i.MX35.
2. EXTAL is the on-chip clock sources other than ESAI system 133MHz clock. It is the 24.576MHz EXTAL_AUDIO clock in i.MX35
system.
22.2.8
Transmitter Serial Clock (SCKT)
SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface. The direction
of this pin is determined by the TCKD bit in the TCCR register. The SCKT is a clock input or output used
by all the enabled transmitters in the asynchronous mode (SYN=0) or by all the enabled transmitters and
receivers in the synchronous mode (SYN=1).
Table 22-2 provides a list of asynchronous-mode transmitter clock sources.
Table 22-2. Transmitter Clock Sources (Asynchronous Mode Only)
THCKD
TFSD
TCKD
ETI
ETO
Transmitter
Bit Clock
Source
0
0
0
N/A
N/A
SCKT
0
0
1
N/A
N/A
HCKT
0
1
0
N/A
N/A
SCKT
FST
0
1
1
N/A
N/A
HCKT
FST
1
0
0
0
0
SCKT
HCKT
1
0
0
0
1
SCKT
HCKT
1
0
0
1
0
SCKT
HCKT
1
0
0
1
1
SCKT
HCKT
1
0
1
0
0
Fsys1
HCKT
OUTPUTS
SCKT
SCKT
SCKT
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Table 22-2. Transmitter Clock Sources (Asynchronous Mode Only) (Continued)
THCKD
TFSD
TCKD
ETI
ETO
Transmitter
Bit Clock
Source
1
0
1
0
1
Fsys
OUTPUTS
HCKT
SCKT
2
1
0
1
1
0
EXTAL
HCKT
SCKT
1
0
1
1
1
EXTAL
HCKT
SCKT
1
1
0
0
0
SCKR
HCKT
FST
1
1
0
0
1
SCKR
HCKT
FST
1
1
0
1
0
SCKR
HCKT
FST
1
1
0
1
1
SCKR
HCKT
FST
1
1
1
0
0
Fsys
HCKT
FST
SCKT
1
1
1
0
1
Fsys
HCKT
FST
SCKT
1
1
1
1
0
EXTAL
HCKT
FST
SCKT
1
1
1
1
1
EXTAL
HCKT
FST
SCKT
Note:
1. Fsys = 133MHz for i.MX35.
2. EXTAL is the on-chip clock sources other than ESAI system 133MHz clock. It is the 24.576MHz EXTAL_AUDIO clock in i.MX35
system.
SCKT may be programmed as a disconnected pin (PC3) when the ESAI SCKT function is not being used.
(See Table 22-38.)
For more information about EXTAL/ESAI clocking control bits (ETI, ETO), see Table 22-8.
NOTE
Although the external ESAI serial clock can be independent of and
asynchronous to the internal 133 MHz ESAI system clock, the external
ESAI serial clock frequency cannot exceed 133MHz/4 = 33.25MHz and
each external ESAI serial clock phase must exceed the minimum of 2 x
1/133MHz = 15.04ns.
22.2.9
Frame Sync for Receiver (FSR)
FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface. The direction
of this pin is determined by the RFSD bit in RCR register. In the asynchronous mode (SYN=0), the FSR
pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1). For FSR pin mode definitions, see Table 22-30; for receiver clock signals,
see Table 22-1.
When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR
register. When configured as the output flag OF1, this pin reflects the value of the OF1 bit in the SAICR
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register, and the data in the OF1 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When configured as the input flag IF1, the data value at the pin is stored
in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network
mode.
FSR may be programmed as a disconnected pin (PC1) when the ESAI FSR function is not being used. (See
Table 22-38.)
22.2.10 Frame Sync for Transmitter (FST)
FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the
synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0) (see
Table 22-2). The direction of this pin is determined by the TFSD bit in the TCR register. When configured
as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin
receives an external frame sync signal for the transmitters (and the receivers in synchronous mode).
FST may be programmed as a disconnected pin (PC4) when the ESAI FST function is not being used. (See
Table 22-38.)
22.2.11 High Frequency Clock for Transmitter (HCKT)
HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI interface. The
direction of this pin is determined by the THCKD bit in the TCCR register. In the asynchronous mode
(SYN=0), the HCKT pin operates as the high frequency clock input or output used by all enabled
transmitters. In the synchronous mode (SYN=1), it operates as the high frequency clock input or output
used by all enabled transmitters and receivers. When programmed as input this pin is used as an alternative
high frequency clock source to the ESAI transmitter rather than the ARM-core main clock. When
programmed as output it can serve as a high frequency sample clock (to external DACs for example) or as
an additional system clock (see Table 22-2).
HCKT may be programmed as a disconnected pin (PC5) when the ESAI HCKT function is not being used.
(See Table 22-38.)
22.2.12 High Frequency Clock for Receiver (HCKR)
HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI interface. The
direction of this pin is determined by the RHCKD bit in the RCCR register. In the asynchronous mode
(SYN=0), the HCKR pin operates as the high frequency clock input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as the serial flag 2 pin. For HCKR pin mode
definitions, see Table 22-31; for receiver clock signals, see Table 22-1.
When this pin is configured as serial flag pin, its direction is determined by the RHCKD bit in the RCCR
register. When configured as the output flag OF2, this pin reflects the value of the OF2 bit in the SAICR
register, and the data in the OF2 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When configured as the input flag IF2, the data value at the pin is stored
in the IF2 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network
mode.
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HCKR may be programmed as a disconnected pin (PC2) when the ESAI HCKR function is not being used.
(See Table 22-38.)
22.2.13 Serial I/O Flags
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in
the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR,
RCCR and SAICR registers.The output data bits (OF2, OF1 and OF0) and the input data bits (IF2, IF1 and
IF0) are double buffered to/from the HCKR, FSR and SCKR pins. Double buffering the flags keeps them
in sync with the TX and RX data lines.
Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by RCKD, RCKD=1 for
output and RCKD=0 for input. Flag 1 (FSR pin) is enabled when the pin is not configured as external
transmitter buffer enable (TEBE=0) and its direction is selected by RFSD, RFSD=1 for output and
RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by RHCKD, RHCKD=1 for output and
RHCKD=0 for input.
When programmed as input flags, the SCKR, FSR and HCKR logic values, respectively, are latched at the
same time as the first bit of the receive data word is sampled. Because the input was latched, the signal on
the input flag pin (SCKR, FSR or HCKR) can change without affecting the input flag until the first bit of
the next receive data word. When the received data words are transferred to the receive data registers, the
input flag latched values are then transferred to the IF0, IF1 and IF2 bits in the SAISR register, where they
may be read by software.
When programmed as output flags, the SCKR, FSR and HCKR logic values are driven by the contents of
the OF0, OF1 and OF2 bits in the SAICR register respectively, and they are driven when the transmit data
registers are transferred to the transmit shift registers. The value on SCKR, FSR and HCKR is stable from
the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word
is transmitted. Software may change the OF0-OF2 values thus controlling the SCKR, FSR and HCKR pin
values for each transmitted word. The normal sequence for setting output flags when transmitting data is
as follows: wait for TDE (transmitter empty) to be set; first write the flags, and then write the transmit data
to the transmit registers. OF0, OF1, and OF2 are double buffered so that the flag states appear on the pins
when the transmit data is transferred to the transmit shift register, that is, the flags are synchronous with
the data.
22.3
Memory Map and Register Definition
Section 22.3, “Memory Map and Register Definition” provides the detailed descriptions for all of the ESAI
registers.
22.3.1
Memory Map
For the base address of a particular module instantiation, see the system memory map. Table 22-3 shows
the ESAI memory map.
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Table 22-3. ESAI Memory Map
Base Address Offset
(Register Abbreviation)
Register
Access
Reset Value
Section/Page
0x4000 (ETDR)
ESAI Transmit Data Register
W
0x0000_0000
22.3.3.1/22-18
0x4004 (ERDR)
ESAI Receive Data Register
R
0x0000_0000
22.3.3.2/22-19
0x4008 (ECR)
ESAI Control Register
R/W
0x0000_0000
22.3.3.3/22-20
0x400C (ESR)
ESAI Status Register
R
0x0000_0000
22.3.3.4/22-21
0x4010 (TFCR)
Transmit FIFO Configuration Register
R/W
0x0000_0000
22.3.3.5/22-22
0x4014 (TFSR)
Transmit FIFO Status Register
R
0x0000_0000
22.3.3.6/22-24
0x4018 (RFCR)
Receive FIFO Configuration Register
R/W
0x0000_0000
22.3.3.7/22-25
0x401C (RFSR)
Receive FIFO Status Register
R
0x0000_0000
22.3.3.8/22-26
0x4020–0x407C
Reserved
R
0x0000_0000
0x4080–0x4094 (TX0 TX5)
Transmit Data Register 0
W
0x0000_0000
22.3.3.9/22-27
0x4084 (TX1)
Transmit Data Register 1
W
0x0000_0000
22.3.3.9/22-27
0x4088 (TX2)
Transmit Data Register 2
W
0x0000_0000
22.3.3.9/22-27
0x408C (TX3)
Transmit Data Register 3
W
0x0000_0000
22.3.3.9/22-27
0x4090 (TX4)
Transmit Data Register 4
W
0x0000_0000
22.3.3.9/22-27
0x4094 (TX5)
Transmit Data Register 5
W
0x0000_0000
22.3.3.9/22-27
0x4098 (TSR)
Transmit Slot Register
W
0x0000_0000
22.3.3.11/22-31
Reserved
R
0x0000_0000
R
0x0000_0000
22.3.3.12/22-31
0x409C
0x40A0–0x40AC (RX0 - Receive Data Register 0
RX3)
0x40A4 (RX1)
Receive Data Register 1
R