NXP i.MX516 Applications Processors - Multimedia, High Performance, Low Power, Connectivity, Arm® Cortex®-A8 Core Reference Manual

NXP i.MX516 Applications Processors - Multimedia, High Performance, Low Power, Connectivity, Arm® Cortex®-A8 Core Reference Manual
An errata for this document is available.
See Document ID#: IMX51RMAD.
MCIMX51 Multimedia
Applications Processor
Reference Manual
MCIMX51RM
Rev. 1
2/2010
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or
+1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
support.japan@freescale.com
surgical implant into the body, or other applications intended to support or sustain life,
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 010 5879 8000
support.asia@freescale.com
unintended or unauthorized use, even if such claim alleges that Freescale
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
+1-800 441-2447 or
+1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Document Number: MCIMX51RM
Rev. 1, 2/2010
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
Semiconductor was negligent regarding the design or manufacture of the part.
Freescale and the Freescale logo are trademarks or registered trademarks
of Freescale Semiconductor, Inc. in the U.S. and other countries. All other
product or service names are the property of their respective owners. ARM
is the registered trademark of ARM Limited. ARMnnn is the trademark of ARM Limited.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Contents
Paragraph
Number
Title
Page
Number
Contents
Audience .............................................................................................................................. I
Organization......................................................................................................................... I
Chapter 1
Introduction
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.4
1.5
1.6
Target Applications .......................................................................................................... 1-1
Features ............................................................................................................................ 1-1
Architectural Overview.................................................................................................... 1-4
Block Diagram............................................................................................................. 1-5
Major Subsystems........................................................................................................ 1-5
Architectural Partitioning ............................................................................................ 1-6
i.MX51 Modules List....................................................................................................... 1-8
Frequency Requirements ............................................................................................... 1-15
Memory Interfaces ......................................................................................................... 1-15
Chapter 2
Memory Map
2.1
2.2
CPU Memory Map........................................................................................................... 2-1
DMA Memory Map ......................................................................................................... 2-6
Chapter 3
Interrupts and DMA Events
3.1
3.2
3.3
Overview.......................................................................................................................... 3-1
AP Interrupts.................................................................................................................... 3-1
SDMA Event Mapping .................................................................................................... 3-5
Chapter 4
External Signals and Pin Multiplexing
4.1
4.1.1
4.1.2
External Signals ............................................................................................................... 4-1
I/O Configuration Parameters...................................................................................... 4-1
Daisy Chaining Settings........................................................................................... 4-113
Chapter 5
External Memories
5.1
5.2
Overview.......................................................................................................................... 5-1
External Memory Interface.............................................................................................. 5-1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
iii
Contents
Paragraph
Number
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
5.4.1
5.4.2
5.4.3
5.4.4
Title
Page
Number
EMI i.MX51 Masters................................................................................................... 5-2
Features........................................................................................................................ 5-2
M4IF Setup ...................................................................................................................... 5-3
Clock Domains ............................................................................................................ 5-3
Boot Scenarios ............................................................................................................. 5-4
Watermark Ports .......................................................................................................... 5-4
Drive Strength Settings................................................................................................ 5-5
M4IF I/O MUX............................................................................................................ 5-6
External Memory Controllers Preset Operation ............................................................ 5-13
NAND Flash Controller (NFC) Preset Operation...................................................... 5-13
WEIM Preset Operation............................................................................................. 5-14
ESDRAMC Preset Operation .................................................................................... 5-14
M4IF Preset Operation............................................................................................... 5-14
Chapter 6
Fuse Map
6.1
6.1.1
6.1.2
Overview.......................................................................................................................... 6-1
Fuse Locks ................................................................................................................... 6-1
Fuse Map...................................................................................................................... 6-1
Chapter 7
Clock Controller Module (CCM)
7.1
7.1.1
7.1.2
7.2
7.2.1
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
Overview.......................................................................................................................... 7-1
Features........................................................................................................................ 7-1
CCM Blocks ................................................................................................................ 7-2
Detailed Signal Descriptions ........................................................................................... 7-3
External Signals Description ....................................................................................... 7-3
Memory Map and Register Definition............................................................................. 7-5
Memory Map ............................................................................................................... 7-5
Register Summary........................................................................................................ 7-7
Register Descriptions................................................................................................. 7-13
CG(i) bits ................................................................................................................... 7-69
Functional Description................................................................................................... 7-77
External Low Frequency Clock—CKIL.................................................................... 7-77
External High Frequency Clock CKIH and Internal Oscillator................................. 7-77
DPLLs (Digital Phase-Locked Loops) and Reference Clocks .................................. 7-77
PLL Clock Selector.................................................................................................... 7-77
CLKSS Support ......................................................................................................... 7-78
CCM Internal Clock Generation................................................................................ 7-78
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
iv
Freescale Semiconductor
Contents
Paragraph
Number
7.4.7
7.4.8
Title
Page
Number
DVFS Support.......................................................................................................... 7-101
Power Modes ........................................................................................................... 7-107
Chapter 8
Debug Architecture
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
8.4.1
8.4.2
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
8.8
8.8.1
8.8.2
8.8.3
8.9
8.10
8.11
8.11.1
8.11.2
Overview.......................................................................................................................... 8-1
Introduction.................................................................................................................. 8-1
Debug Strategy ............................................................................................................ 8-1
System Secure Controller—SJC...................................................................................... 8-2
JTAG Topology............................................................................................................ 8-2
Secure JTAG Controller Main Feature ........................................................................ 8-2
SCJ TAP Port ............................................................................................................... 8-3
SJC Main Blocks ......................................................................................................... 8-3
SJC Features—JTAG Disable Mode ........................................................................... 8-3
SJC Registers Summary............................................................................................... 8-4
SJC Registers Description ........................................................................................... 8-9
CoreSight Design Kit..................................................................................................... 8-18
Memory Map and Register Definition....................................................................... 8-18
CoreSight Clock Enable............................................................................................. 8-19
CoreSight Debug Access Port (DAP) and DAP_SYS............................................... 8-19
Embedded Cross Trigger (ECT) ................................................................................ 8-19
CoreSight Trace Port Interface (TPIU)...................................................................... 8-25
ARM Cortex A8 Core and Platform .............................................................................. 8-25
ARM Cortex A8 Core Debug Support Features........................................................ 8-25
Additional Platform Debug Functionality ................................................................ 8-26
Smart DMA (SDMA) Core............................................................................................ 8-26
SDMA On Chip Emulation Module (OnCE) Feature Summary............................... 8-26
Other SDMA Debug Functionality............................................................................ 8-27
Embedded Cross Trigger Interface ............................................................................ 8-28
External Memory Interface (EMI) ................................................................................. 8-28
Debug Visibility—IOMUX ........................................................................................... 8-28
MCU Peripherals ........................................................................................................... 8-29
Image Processing Unit (IPU)..................................................................................... 8-29
Video Processing Unit (VPU).................................................................................... 8-29
Graphics Processing Unit (GPU)............................................................................... 8-30
Supported Tools ............................................................................................................. 8-30
Interrupt Visibility.......................................................................................................... 8-30
Miscellaneous ................................................................................................................ 8-30
SOC-level Bus Trace ................................................................................................. 8-30
Clock/Reset/Power..................................................................................................... 8-30
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
v
Contents
Paragraph
Number
Title
Page
Number
Chapter 9
System Boot
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.4.3
Introduction...................................................................................................................... 9-1
Boot Module Activation .................................................................................................. 9-1
Internal ROM /RAM Memory Map................................................................................. 9-3
Boot Modes...................................................................................................................... 9-4
Internal Boot (BMODE = 00)...................................................................................... 9-4
Internal Boot—ROM Select (BMODE = 10) .............................................................. 9-5
Serial Downloader (BMOD[1:0] = 11)...................................................................... 9-10
Chapter 10
Multimedia
10.1
10.1.1
10.2
Video Subsystem............................................................................................................ 10-1
Image Processing Unit (IPU)..................................................................................... 10-1
Video Processing Unit (VPU)........................................................................................ 10-8
Chapter 11
Power Management
11.1
11.1.1
11.1.2
11.2
11.2.1
11.3
11.4
11.4.1
11.4.2
11.4.3
11.5
11.6
11.7
Power Saving Methodology........................................................................................... 11-1
Active Power Savings................................................................................................ 11-1
Controlling Leakage .................................................................................................. 11-1
Power Gating Sequences ............................................................................................... 11-2
Power Gating Options................................................................................................ 11-2
Low-Power Modes......................................................................................................... 11-2
Module Specific Power Modes...................................................................................... 11-3
Power Down Sequence .............................................................................................. 11-4
Power Up Sequence ................................................................................................... 11-4
IPU Save and Restore Sequence................................................................................ 11-4
RAM Memory Supplies................................................................................................. 11-4
Fusebox Supplies ........................................................................................................... 11-5
Dynamic Voltage and Frequency Scaling ...................................................................... 11-5
Chapter 12
System Security
12.1
Introduction.................................................................................................................... 12-1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
vi
Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
Chapter 13
1-Wire Module (1-Wire)
13.1
13.1.1
13.1.2
13.2
13.3
13.3.1
13.3.2
13.4
13.4.1
13.4.2
13.4.3
13.4.4
Overview........................................................................................................................ 13-1
Features...................................................................................................................... 13-1
Modes of Operation ................................................................................................... 13-2
External Signals ............................................................................................................. 13-2
Memory Map and Register Definition........................................................................... 13-2
Memory Map ............................................................................................................. 13-2
Register Descriptions................................................................................................. 13-2
Functional Description................................................................................................... 13-5
Normal Operating Modes .......................................................................................... 13-5
Low Power Mode....................................................................................................... 13-6
Clocks ........................................................................................................................ 13-6
Reset........................................................................................................................... 13-6
Chapter 14
Cortex-A8 Platform
14.1
14.2
14.2.1
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.4
14.4.1
14.4.2
14.4.3
14.5
14.6
14.6.1
14.6.2
14.6.3
Overview........................................................................................................................ 14-1
Core Platform Sub-blocks.............................................................................................. 14-3
Cortex-A8n Processor................................................................................................ 14-3
Summary of Remaining Platform Components............................................................. 14-7
Platform Controller ................................................................................................... 14-7
Configuration ............................................................................................................. 14-9
Endian Modes ............................................................................................................ 14-9
Bus Interfaces ............................................................................................................ 14-9
Memory Map and Register Definition......................................................................... 14-10
Register Memory Map ............................................................................................. 14-10
Register Summary.................................................................................................... 14-11
Register Descriptions............................................................................................... 14-12
Platform Clocks ........................................................................................................... 14-24
Platform Power Management ...................................................................................... 14-24
Voltage and Frequency Scaling................................................................................ 14-24
Power Gating in the Cortex-A8n Core Platform ..................................................... 14-25
Modes of Operation ................................................................................................. 14-29
Chapter 15
Platform Debug
15.1
Introduction.................................................................................................................... 15-1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
vii
Contents
Paragraph
Number
15.1.1
15.1.2
15.1.3
15.2
15.2.1
15.2.2
15.2.3
15.2.4
Title
Page
Number
Overview.................................................................................................................... 15-1
ARM Debug Modules................................................................................................ 15-2
Modes of Operation ................................................................................................. 15-10
Memory Map and Register Definition......................................................................... 15-11
Register Summary.................................................................................................... 15-12
Clocks ...................................................................................................................... 15-24
Reset......................................................................................................................... 15-24
Endianness ............................................................................................................... 15-25
Chapter 16
Multi-Layer AHB Crossbar Switch (MAX)
16.1
16.1.1
16.1.2
16.2
16.2.1
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.4
16.4.1
16.4.2
16.4.3
16.4.4
16.5
16.6
16.6.1
16.6.2
16.6.3
Features .......................................................................................................................... 16-3
Limitations ................................................................................................................. 16-3
General Operation...................................................................................................... 16-3
MAX Interface Signals .................................................................................................. 16-4
MAX Signal Descriptions.......................................................................................... 16-4
Memory Map and Register Definition........................................................................... 16-5
Memory Map ............................................................................................................. 16-5
Register Summary...................................................................................................... 16-6
MAX Register Descriptions....................................................................................... 16-9
Coherency ................................................................................................................ 16-13
Detailed Functional Description .................................................................................. 16-14
Arbitration................................................................................................................ 16-14
Priority Assignment ................................................................................................. 16-15
Master Port Functionality ........................................................................................ 16-15
Slave Port Functionality........................................................................................... 16-19
Initialization/Application Information ......................................................................... 16-26
MAX Interface ............................................................................................................. 16-27
Overview.................................................................................................................. 16-27
Master Ports ............................................................................................................. 16-27
Slave Ports ............................................................................................................... 16-28
Chapter 17
Digital Audio Mux (AUDMUX)
17.1
17.1.1
17.1.2
17.1.3
17.2
Introduction.................................................................................................................... 17-4
Features...................................................................................................................... 17-4
Modes of Operation ................................................................................................... 17-4
Connectivity Between Ports..................................................................................... 17-18
External Signal Description ......................................................................................... 17-21
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
viii
Freescale Semiconductor
Contents
Paragraph
Number
17.2.1
17.3
17.3.1
17.3.2
17.3.3
17.4
17.4.1
17.4.2
17.4.3
17.5
Title
Page
Number
Overview.................................................................................................................. 17-22
Memory Map and Register Definition......................................................................... 17-22
Register Summary.................................................................................................... 17-23
Register Descriptions............................................................................................... 17-26
AUDMUX Default Configuration ........................................................................... 17-49
AUDMUX Clocking.................................................................................................... 17-49
AUDMUX Clock Inputs.......................................................................................... 17-49
AUDMUX Clock Diagram...................................................................................... 17-50
Clocking Restrictions............................................................................................... 17-50
Initialization/Application Information ......................................................................... 17-50
Chapter 18
Configurable Serial Peripheral Interface (CSPI)
18.1
18.1.1
18.1.2
18.2
18.3
18.3.1
18.3.2
18.3.3
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.5
Overview........................................................................................................................ 18-1
Features...................................................................................................................... 18-1
Modes of Operation ................................................................................................... 18-2
External Signal Description ........................................................................................... 18-2
Memory Map and Register Definition........................................................................... 18-3
Memory Map ............................................................................................................. 18-4
Register Summary...................................................................................................... 18-4
Register Descriptions................................................................................................. 18-6
Functional Description................................................................................................. 18-17
Master Mode ............................................................................................................ 18-17
Slave Mode .............................................................................................................. 18-21
Interrupt Control ...................................................................................................... 18-22
DMA Control........................................................................................................... 18-23
Initialization/Application Information ......................................................................... 18-25
Chapter 19
Clock Amplifier (CAMP)
19.1
19.1.1
19.1.2
19.2
19.2.1
19.2.2
19.2.3
Overview........................................................................................................................ 19-1
Features...................................................................................................................... 19-2
Modes of Operation ................................................................................................... 19-2
External Signal Description ........................................................................................... 19-2
Overview.................................................................................................................... 19-2
Detailed Signal Description ....................................................................................... 19-3
Memory Map/Register Definition ............................................................................. 19-3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
ix
Contents
Paragraph
Number
Page
Number
Title
Chapter 20
Central Security Unit (CSU)
20.1
20.1.1
Overview........................................................................................................................ 20-1
Features...................................................................................................................... 20-1
Chapter 21
Digital Phase Lock Loop (DPLL)
21.1
21.1.1
21.1.2
21.1.3
21.2
21.2.1
21.2.2
Introduction.................................................................................................................... 21-1
Overview.................................................................................................................... 21-2
Features...................................................................................................................... 21-2
Modes of Operation ................................................................................................... 21-3
External Signal Description ........................................................................................... 21-4
Overview.................................................................................................................... 21-4
Detailed Signal Descriptions ..................................................................................... 21-5
Chapter 22
DPLL-IP Interface (DPLL-IP)
22.1
22.1.1
22.1.2
22.2
22.2.1
22.2.2
22.3
22.3.1
22.3.2
22.3.3
22.3.4
22.4
Overview........................................................................................................................ 22-1
Feature Description.................................................................................................... 22-1
Modes of Operation ................................................................................................... 22-1
Memory Map/Register Definition ................................................................................. 22-2
Register Summary...................................................................................................... 22-2
Detailed Register Descriptions .................................................................................. 22-4
Functional Description................................................................................................. 22-16
Clock Muxing and Gating/div Circuitry.................................................................. 22-16
DVFS Support: HFS Mode...................................................................................... 22-17
DPLL Control and Port Updating............................................................................ 22-17
Multiple Options for DPLL Control ........................................................................ 22-19
Initialization/Application Information ......................................................................... 22-19
Chapter 23
Dynamic Process and Temperature Compensation (DPTC)
23.1
23.1.1
23.1.2
23.2
23.2.1
Introduction.................................................................................................................... 23-1
Features...................................................................................................................... 23-1
Debug Mode .............................................................................................................. 23-1
Memory Map and Register Definition........................................................................... 23-1
DPTC Memory Map .................................................................................................. 23-1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
x
Freescale Semiconductor
Contents
Paragraph
Number
23.2.2
23.2.3
23.2.4
Title
Page
Number
Register Summary...................................................................................................... 23-2
DPTC Register Summary........................................................................................... 23-3
Register Descriptions................................................................................................. 23-4
Chapter 24
Dynamic Voltage Frequency Scaling (DVFS)
24.1
24.1.1
24.1.2
24.2
24.2.1
24.2.2
24.2.3
24.3
24.4
24.4.1
24.4.2
24.4.3
24.4.4
24.4.5
24.4.6
24.4.7
24.4.8
24.4.9
24.5
24.5.1
24.6
Introduction.................................................................................................................... 24-1
Overview.................................................................................................................... 24-2
Features...................................................................................................................... 24-2
Memory Map and Register Definition........................................................................... 24-3
Memory Map ............................................................................................................. 24-3
Register Summary...................................................................................................... 24-3
Register Descriptions................................................................................................. 24-7
Functional Description of DVFS Core Load Tracking................................................ 24-20
Component Blocks Description ................................................................................... 24-21
dvfs_stdb_smpl block .............................................................................................. 24-21
dvfs_sig_wt block.................................................................................................... 24-21
dvfs_pre_avg block.................................................................................................. 24-22
dvfs_ld_add Block ................................................................................................... 24-25
dvfs_ema_avg Block................................................................................................ 24-25
dvfs_thres_cmp block.............................................................................................. 24-29
dvfs_thresh_count block .......................................................................................... 24-29
Load Tracking Buffer Register ................................................................................ 24-30
Frequency Pattern Generator ................................................................................... 24-31
DVFS Output Event/interrupt Configuration .............................................................. 24-32
Interrupts.................................................................................................................. 24-32
Initialization Information ............................................................................................. 24-32
Chapter 25
Dynamic Voltage Frequency Scaling for Peripherals (DVFS_PER)
25.1
25.1.1
25.2
25.2.1
25.2.2
25.2.3
25.3
Overview........................................................................................................................ 25-1
Features...................................................................................................................... 25-3
Memory Map and Register Definition........................................................................... 25-4
Memory Map ............................................................................................................. 25-4
Register Summary...................................................................................................... 25-4
Register Descriptions................................................................................................. 25-7
Functional Description of DVFS Core Load Tracking................................................ 25-15
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xi
Contents
Paragraph
Number
Page
Number
Title
Chapter 26
Enhanced Configurable Serial Peripheral Interface (eCSPI)
26.1
26.1.1
26.1.2
26.1.3
26.2
26.3
26.3.1
26.3.2
26.3.3
26.4
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.4.6
26.4.7
26.4.8
26.5
26.6
26.6.1
26.6.2
Introduction.................................................................................................................... 26-1
Overview.................................................................................................................... 26-1
Features...................................................................................................................... 26-1
Modes of Operation ................................................................................................... 26-2
External Signal Description ........................................................................................... 26-3
Memory Map and Register Definition........................................................................... 26-4
Memory Map ............................................................................................................. 26-5
Register Summary...................................................................................................... 26-5
Register Descriptions................................................................................................. 26-7
Functional Description................................................................................................. 26-20
Clocks ...................................................................................................................... 26-20
Reset......................................................................................................................... 26-20
Interrupts.................................................................................................................. 26-20
Endianness ............................................................................................................... 26-20
eCSPI Timing Diagram............................................................................................ 26-21
Master Mode ............................................................................................................ 26-21
Slave Mode .............................................................................................................. 26-26
Hardware Trigger Mode .......................................................................................... 26-27
Initialization Information ............................................................................................. 26-27
Application Information .............................................................................................. 26-29
Interrupt Control ...................................................................................................... 26-29
DMA Control........................................................................................................... 26-30
Chapter 27
External Memory Interface(EMI)
27.1
27.1.1
27.1.2
27.1.3
27.2
27.2.1
27.2.2
27.3
27.3.1
27.4
27.4.1
27.4.2
Introduction.................................................................................................................... 27-1
Overview.................................................................................................................... 27-1
Features...................................................................................................................... 27-2
Modes of Operation ................................................................................................... 27-3
Sharing of I/O Pins ........................................................................................................ 27-5
WEIM and NFC I/O Pin Sharing............................................................................... 27-5
WEIM/NFC Arbitration Logic .................................................................................. 27-6
External Signal Description ........................................................................................... 27-7
Detailed Signal Descriptions ................................................................................... 27-32
Memory Map and Register Definition......................................................................... 27-32
External/Internal Memory Map ............................................................................... 27-32
IPS Memory Map..................................................................................................... 27-33
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xii
Freescale Semiconductor
Contents
Paragraph
Number
27.4.3
27.4.4
27.5
27.5.1
27.5.2
27.5.3
27.5.4
27.5.5
27.6
27.7
27.7.1
27.7.2
27.7.3
27.7.4
27.7.5
27.8
Title
Page
Number
Register Summary.................................................................................................... 27-33
Register Descriptions............................................................................................... 27-34
Functional Description................................................................................................. 27-37
Clocks ...................................................................................................................... 27-38
Reset......................................................................................................................... 27-38
Interrupts.................................................................................................................. 27-39
Endianness ............................................................................................................... 27-39
IPS Interface ............................................................................................................ 27-39
Application Information .............................................................................................. 27-40
EMI Endianess ............................................................................................................. 27-40
AXI Endianess Support ........................................................................................... 27-40
AXI Master ×64 ....................................................................................................... 27-41
AXI Master ×32 ....................................................................................................... 27-43
EMI Endianess Support ........................................................................................... 27-45
M4IF Endianess Support ......................................................................................... 27-46
Data Storage Arrangement........................................................................................... 27-48
Chapter 28
Embedded Memory Periphery Power Gating Controller (EMPGC)
28.1
28.1.1
28.1.2
28.2
28.2.1
28.2.2
28.2.3
28.2.4
28.2.5
Introduction.................................................................................................................... 28-1
Features...................................................................................................................... 28-1
Modes of Operation ................................................................................................... 28-1
Memory Map and Register Definition........................................................................... 28-1
EMPG Controller Memory Map................................................................................ 28-1
Register Summary...................................................................................................... 28-2
Register Descriptions................................................................................................. 28-4
Power-down Sequence (EMPG Entry Sequence)...................................................... 28-6
Power-up Sequence (EMPG Exit Sequence)............................................................. 28-6
Chapter 29
Enhanced Periodic Interrupt Timer (EPIT)
29.1
29.1.1
29.1.2
29.1.3
29.2
29.3
29.3.1
29.3.2
Introduction.................................................................................................................... 29-1
Overview.................................................................................................................... 29-2
Features...................................................................................................................... 29-2
Modes of Operation ................................................................................................... 29-2
External Signal Description ........................................................................................... 29-2
Register Definition and Memory Map........................................................................... 29-3
Register Summary...................................................................................................... 29-3
Detailed Register Descriptions .................................................................................. 29-4
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xiii
Contents
Paragraph
Number
29.4
29.4.1
29.4.2
29.4.3
29.5
Title
Page
Number
Functional Description................................................................................................... 29-9
Operation ................................................................................................................... 29-9
Clocks ...................................................................................................................... 29-10
Compare Event ........................................................................................................ 29-11
Initialization/Application Information ......................................................................... 29-12
Chapter 30
Enhanced SDRAM Controller (eSDCTL)
30.1
30.2
30.3
30.3.1
30.3.2
30.4
30.5
30.6
30.7
30.7.1
30.8
30.8.1
30.8.2
30.8.3
30.8.4
30.8.5
30.9
30.9.1
30.9.2
30.9.3
Introduction.................................................................................................................... 30-1
Block Diagram ............................................................................................................... 30-2
Overview........................................................................................................................ 30-3
Features...................................................................................................................... 30-3
AXI Interface ............................................................................................................. 30-4
External Signal Description ........................................................................................... 30-5
Memory Map and Register Definition........................................................................... 30-9
Memory Map ................................................................................................................. 30-9
Register Summary........................................................................................................ 30-10
Register Descriptions............................................................................................... 30-14
Functional Description................................................................................................. 30-47
Enhanced SDRAM Controller Optimization Strategy............................................. 30-47
Refresh ..................................................................................................................... 30-51
Low-Power Operating Modes.................................................................................. 30-53
Command Encoding ................................................................................................ 30-62
ODT behavior .......................................................................................................... 30-66
Initialization Information ............................................................................................. 30-66
Memory Device Selection ....................................................................................... 30-66
CAS Latency............................................................................................................ 30-66
LPDDR/DDR2 Initialization Sequence ................................................................... 30-66
Chapter 31
Enhanced Secured Digital Host Controller (eSDHC)
31.1
31.1.1
31.1.2
31.2
31.2.1
31.2.2
31.3
31.3.1
Overview........................................................................................................................ 31-1
Features...................................................................................................................... 31-2
Modes of Operation—Data Transfer Modes ............................................................. 31-3
External Signals ............................................................................................................. 31-3
Overview.................................................................................................................... 31-3
Signal Descriptions .................................................................................................... 31-4
Memory Map and Register Definition........................................................................... 31-5
Memory Map ............................................................................................................. 31-6
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xiv
Freescale Semiconductor
Contents
Paragraph
Number
31.3.2
31.3.3
31.4
31.4.1
31.4.2
31.4.3
31.4.4
31.4.5
31.4.6
31.4.7
31.4.8
31.4.9
31.5
31.5.1
31.5.2
31.5.3
31.5.4
31.5.5
31.6
31.7
31.7.1
Title
Page
Number
Register Summary...................................................................................................... 31-7
Register Descriptions............................................................................................... 31-10
Functional Description................................................................................................. 31-53
Data Buffer .............................................................................................................. 31-53
DMA AHB Interface ............................................................................................... 31-59
Register Bank Access Via IP Bus Interface............................................................. 31-64
SD Protocol Unit...................................................................................................... 31-64
Clock and Reset Manager Submodule (CRM) ........................................................ 31-66
SD Clock Generator................................................................................................. 31-66
SDIO Card Interrupts............................................................................................... 31-67
Card Insertion and Removal Detection.................................................................... 31-68
Power Management and Wakeup Events................................................................. 31-69
Initialization/Application Information ......................................................................... 31-69
Command Send and Response Receive Basic Operation........................................ 31-70
Card Identification Mode......................................................................................... 31-70
Card Accesses .......................................................................................................... 31-76
Switch Function ....................................................................................................... 31-84
ADMA Operation .................................................................................................... 31-86
MMC/SD/SDIO/CE-ATA Card Commands ................................................................ 31-87
Software Restrictions ................................................................................................... 31-92
Initialization Active ................................................................................................. 31-92
Chapter 32
Fast Ethernet Controller (FEC)
32.1
32.2
32.2.1
32.3
32.3.1
32.3.2
32.3.3
32.3.4
32.4
32.5
32.5.1
32.5.2
32.5.3
32.5.4
32.5.5
32.5.6
Introduction.................................................................................................................... 32-1
Overview........................................................................................................................ 32-1
Features...................................................................................................................... 32-1
Modes of Operation ....................................................................................................... 32-2
Full- and Half-Duplex Operation............................................................................... 32-2
Interface Options........................................................................................................ 32-2
Address Recognition Options .................................................................................... 32-2
Internal Loopback...................................................................................................... 32-3
FEC Top-Level Functional Diagram ............................................................................. 32-3
Functional Description................................................................................................... 32-4
Initialization Sequence............................................................................................... 32-4
Network Interface Options......................................................................................... 32-6
FEC Frame Transmission .......................................................................................... 32-7
FEC Frame Reception................................................................................................ 32-8
Ethernet Address Recognition ................................................................................... 32-9
Hash Algorithm........................................................................................................ 32-11
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xv
Contents
Paragraph
Number
32.5.7
32.5.8
32.5.9
32.5.10
32.5.11
32.6
32.6.1
32.6.2
32.6.3
32.6.4
32.6.5
Title
Page
Number
Full-Duplex Flow Control ....................................................................................... 32-14
Interpacket Gap (IPG) Time .................................................................................... 32-15
Collision Handling................................................................................................... 32-15
Internal and External Loopback............................................................................... 32-15
Ethernet Error-Handling Procedure ......................................................................... 32-16
Programming Model .................................................................................................... 32-17
Top Level Module Memory Map............................................................................. 32-18
Detailed Memory Map (Control/Status Registers) .................................................. 32-18
MIB Block Counters Memory Map......................................................................... 32-19
Register Descriptions............................................................................................... 32-21
Buffer Descriptors.................................................................................................... 32-41
Chapter 33
Fast Infrared Interface (FIRI)
33.1
33.1.1
33.1.2
33.1.3
33.2
33.2.1
33.3
33.3.1
33.3.2
33.3.3
33.4
33.4.1
33.4.2
33.4.3
33.4.4
33.5
33.5.1
Overview........................................................................................................................ 33-2
Overview of IrDA Medium InfraRed and Fast InfraRed Standards.......................... 33-3
Features...................................................................................................................... 33-6
Modes of Operation ................................................................................................... 33-6
External Signal Description ........................................................................................... 33-6
Detailed Signal Descriptions ..................................................................................... 33-7
Memory Map and Register Definition........................................................................... 33-7
FIRI Memory Map..................................................................................................... 33-7
Register Summary...................................................................................................... 33-7
Register Descriptions................................................................................................. 33-9
Functional Description................................................................................................. 33-17
Transmitter Overview .............................................................................................. 33-17
Transmitter FIFO ..................................................................................................... 33-18
Receiver Overview .................................................................................................. 33-19
Receiver FIFO.......................................................................................................... 33-19
Initialization/Application Information ......................................................................... 33-20
Transmitter Programming Scenario......................................................................... 33-20
Chapter 34
General Power Controller (GPC)
34.1
34.1.1
34.2
34.2.1
34.2.2
Introduction.................................................................................................................... 34-1
Features...................................................................................................................... 34-2
Memory Map and Register Definition........................................................................... 34-2
Memory Map ............................................................................................................. 34-2
Register Summary...................................................................................................... 34-3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xvi
Freescale Semiconductor
Contents
Paragraph
Number
34.2.3
34.2.4
34.2.5
34.2.6
34.2.7
34.3
34.3.1
34.3.2
34.3.3
34.3.4
34.3.5
34.3.6
Title
Page
Number
CNTR Register Description....................................................................................... 34-5
PGR - Register Description ....................................................................................... 34-6
VCR Register Description ......................................................................................... 34-8
ALL_PU Register Description................................................................................... 34-9
NEON Register Description .................................................................................... 34-10
Functional Description................................................................................................. 34-10
DVFS - Dynamic Voltage & Frequency Scaling ..................................................... 34-11
DPTC—Dynamic Process and Temperature Compensation ................................... 34-11
DVFS and DPTC Change Request Sequence Diagrams ......................................... 34-13
Frequency / Voltage change Controller description................................................. 34-15
State Retention Power Gating (SRPG) .................................................................... 34-18
PMIC Interface Requirements for APM Support .................................................... 34-18
Chapter 35
General Purpose Input/Output (GPIO)
35.1
35.1.1
35.2
35.3
35.3.1
35.3.2
35.3.3
35.4
35.4.1
35.4.2
35.4.3
Overview........................................................................................................................ 35-1
Features...................................................................................................................... 35-3
External Signal Description ........................................................................................... 35-3
Memory Map and Register Definition........................................................................... 35-5
Memory Map ............................................................................................................. 35-5
Register Summary...................................................................................................... 35-5
Register Descriptions................................................................................................. 35-7
Functional Description................................................................................................. 35-14
GPIO Function......................................................................................................... 35-14
GPIO Programming ................................................................................................. 35-14
Interrupt Control Unit .............................................................................................. 35-15
Chapter 36
General Purpose Timer (GPT)
36.1
36.1.1
36.1.2
36.1.3
36.2
36.2.1
36.2.2
36.2.3
36.2.4
36.3
Introduction.................................................................................................................... 36-1
Overview.................................................................................................................... 36-2
Features...................................................................................................................... 36-2
Modes of Operation ................................................................................................... 36-2
Signal Description.......................................................................................................... 36-3
External Signals ......................................................................................................... 36-3
ipp_ind_clkin — External Clock Input...................................................................... 36-3
ipp_ind_capin1, ipp_ind_capin2 — Input Capture Trigger Signals.......................... 36-3
ipp_do_cmpout1, ipp_do_cmpout2, ipp_do_cmpout3—Output Compare Signals... 36-4
Register Definition and Memory Map........................................................................... 36-4
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xvii
Contents
Paragraph
Number
36.3.1
36.3.2
36.4
36.4.1
36.4.2
36.4.3
36.4.4
36.4.5
36.4.6
36.5
Title
Page
Number
Register Summary...................................................................................................... 36-5
Detailed Register Descriptions .................................................................................. 36-6
Functional Description................................................................................................. 36-15
Clocks ...................................................................................................................... 36-16
Input Capture ........................................................................................................... 36-17
Output Compare....................................................................................................... 36-17
Interrupts.................................................................................................................. 36-18
Low-Power Mode (LPM) Behavior......................................................................... 36-19
Debug Mode Behavior............................................................................................. 36-19
Initialization/Application Information ......................................................................... 36-19
Chapter 37
Graphics Processing Unit 2D (GPU2D)
37.1
37.2
37.2.1
37.2.2
37.3
37.4
37.5
37.6
37.7
37.8
37.8.1
37.8.2
Overview........................................................................................................................ 37-1
GPU Feature List ........................................................................................................... 37-1
Frame Buffer.............................................................................................................. 37-1
2D Bitmap Graphics (Separate 2D Unit)................................................................... 37-1
GPU2D Block Diagram ................................................................................................. 37-4
Modes of Operation ....................................................................................................... 37-4
Reset............................................................................................................................... 37-4
Interrupts ........................................................................................................................ 37-5
DMA .............................................................................................................................. 37-5
Memory Map ................................................................................................................. 37-5
AHB Slave Interface.................................................................................................. 37-5
AXI Master Memory Interface (EMI port)................................................................ 37-6
Chapter 38
3D Graphics Accelerator (GPU3D)
38.1
38.1.1
38.2
38.3
38.4
38.4.1
38.4.2
38.4.3
38.4.4
38.4.5
38.5
Overview........................................................................................................................ 38-1
IGPU3D Features....................................................................................................... 38-1
Capabilities and Performance ........................................................................................ 38-1
GPU3D Block Diagram ................................................................................................. 38-2
GPU3D SoC Interface ................................................................................................... 38-4
GPU3D SoC Integration Top Level Diagram............................................................ 38-4
SoC Interface Summary............................................................................................. 38-4
Memory Interface Detail............................................................................................ 38-5
DMI Interface Detail.................................................................................................. 38-8
Debug Bus and GPIO ................................................................................................ 38-9
Clocking Architecture.................................................................................................. 38-10
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xviii
Freescale Semiconductor
Contents
Paragraph
Number
38.5.1
38.5.2
38.6
38.7
38.8
Title
Page
Number
Clock input............................................................................................................... 38-10
Clock Gating ............................................................................................................ 38-10
Reset............................................................................................................................. 38-11
Interrupts ...................................................................................................................... 38-11
Memory Map ............................................................................................................... 38-11
Chapter 39
High Speed Inter IC (HS-I2C)
39.1
39.1.1
39.1.2
39.1.3
39.2
39.3
39.3.1
39.3.2
39.3.3
39.4
39.4.1
39.4.2
39.4.3
39.4.4
39.4.5
39.4.6
39.4.7
39.4.8
39.4.9
39.4.10
39.4.11
39.4.12
39.4.13
39.4.14
39.4.15
39.4.16
39.4.17
39.5
39.5.1
39.5.2
39.5.3
39.5.4
Introduction.................................................................................................................... 39-1
Overview.................................................................................................................... 39-3
Features...................................................................................................................... 39-3
Modes of Operation ................................................................................................... 39-4
External Signal Description ........................................................................................... 39-4
Memory Map and Register Definition........................................................................... 39-6
Memory Map ............................................................................................................. 39-6
Register Summary...................................................................................................... 39-6
Register Descriptions................................................................................................. 39-8
Functional Description................................................................................................. 39-24
HS_I2C System Configuration ................................................................................ 39-24
I2C Protocol ............................................................................................................. 39-24
Arbitration Procedure .............................................................................................. 39-26
Clock Synchronization............................................................................................. 39-27
Handshaking ............................................................................................................ 39-27
Clock Stretching ...................................................................................................... 39-27
High-Speed Mode Operation ................................................................................... 39-27
10-Bit Addressing.................................................................................................... 39-30
DMA Bus Interface.................................................................................................. 39-32
Receive and Transmit FIFOs ................................................................................... 39-34
FIFO Flush Operation.............................................................................................. 39-34
IP Bus Accesses ....................................................................................................... 39-34
Generation of Transfer Error on IP Bus................................................................... 39-34
Clocks ...................................................................................................................... 39-35
Reset......................................................................................................................... 39-35
Interrupts.................................................................................................................. 39-35
Endianness ............................................................................................................... 39-35
Initialization Information ............................................................................................. 39-35
Generation of START .............................................................................................. 39-36
Post-Transfer Software Response ............................................................................ 39-36
Generation of STOP................................................................................................. 39-36
Generation of Repeated START .............................................................................. 39-36
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xix
Contents
Paragraph
Number
39.5.5
39.5.6
39.6
39.6.1
39.6.2
39.6.3
Title
Page
Number
Slave Mode .............................................................................................................. 39-36
Arbitration Lost........................................................................................................ 39-37
Application Information .............................................................................................. 39-39
Programming Sequence: .......................................................................................... 39-39
Programming Restrictions ....................................................................................... 39-42
Timing Section......................................................................................................... 39-42
Chapter 40
Inter IC (I2C)
40.1
40.1.1
40.1.2
40.2
40.2.1
40.3
40.3.1
40.3.2
40.3.3
40.4
40.4.1
40.4.2
40.4.3
40.4.4
40.4.5
40.4.6
40.4.7
40.4.8
40.5
40.5.1
40.5.2
40.5.3
40.5.4
40.5.5
40.5.6
40.5.7
40.5.8
Introduction.................................................................................................................... 40-1
Overview.................................................................................................................... 40-2
Features...................................................................................................................... 40-2
External Signal Description ........................................................................................... 40-3
Detailed External Signal Descriptions....................................................................... 40-3
Memory Map and Register Definition........................................................................... 40-4
I2C Memory Map....................................................................................................... 40-4
Register Summary...................................................................................................... 40-4
Register Descriptions................................................................................................. 40-6
Functional Description................................................................................................. 40-11
I2C System Configuration........................................................................................ 40-11
I2C Protocol ............................................................................................................. 40-11
Arbitration Procedure .............................................................................................. 40-13
Clock Synchronization............................................................................................. 40-13
Handshaking ............................................................................................................ 40-14
Clock Stretching ...................................................................................................... 40-14
IP Bus Accesses ....................................................................................................... 40-14
Generation of Transfer Error on IP Bus................................................................... 40-14
Initialization/Application Information ......................................................................... 40-14
Generation of START .............................................................................................. 40-15
Post-Transfer Software Response ............................................................................ 40-15
Generation of STOP................................................................................................. 40-15
Generation of Repeated START .............................................................................. 40-16
Slave Mode .............................................................................................................. 40-16
Arbitration Lost........................................................................................................ 40-16
Timing Section......................................................................................................... 40-18
Software Restrictions............................................................................................... 40-18
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xx
Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
Chapter 41
IC Identification (IIM)
41.1
41.1.1
41.2
41.2.1
41.2.2
41.2.3
41.3
41.3.1
41.3.2
41.3.3
41.3.4
41.3.5
41.4
41.4.1
41.4.2
41.4.3
Overview........................................................................................................................ 41-1
Modes of Operation ................................................................................................... 41-1
Memory Map and Register Definition........................................................................... 41-1
Memory Map ............................................................................................................. 41-1
Register Summary...................................................................................................... 41-2
Register Descriptions................................................................................................. 41-4
Functional Description................................................................................................. 41-18
Signal Groups .......................................................................................................... 41-18
Fuse Box Signals ..................................................................................................... 41-22
Fuse Value Storage................................................................................................... 41-29
Fuse Protection ........................................................................................................ 41-30
Fuse Bank Operations.............................................................................................. 41-31
Initialization/Application Information ......................................................................... 41-35
Initialization ............................................................................................................. 41-35
Program.................................................................................................................... 41-36
Parameter Definition................................................................................................ 41-36
Chapter 42
Image Processing Unit 3
(IPUv3EX)
42.1
42.1.1
42.1.2
42.1.3
42.1.4
42.2
42.2.1
42.2.2
42.2.3
42.3
42.3.1
42.3.2
42.3.3
42.3.4
42.3.5
42.3.6
42.3.7
Introduction.................................................................................................................. 42-41
Overview.................................................................................................................. 42-41
Architecture ............................................................................................................. 42-42
Features And Functionality...................................................................................... 42-43
.Modes of Operation ................................................................................................ 42-57
Memory Map and Register Definition......................................................................... 42-58
Memory Map ........................................................................................................... 42-60
Register Summary.................................................................................................... 42-60
Register Descriptions............................................................................................... 42-61
Functional Description............................................................................................... 42-534
IPU Detailed Block Diagram ................................................................................. 42-534
Image DMA Controller (IDMAC)......................................................................... 42-536
Camera Sensor Interface (CSI) .............................................................................. 42-566
Sensor Multi FIFO Controller (SMFC) ................................................................. 42-573
Image Converter (IC)............................................................................................ 42-577
Display Port ........................................................................................................... 42-590
DC - Display Controller......................................................................................... 42-594
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxi
Contents
Paragraph
Number
42.3.8
42.3.9
42.3.10
42.3.11
42.3.12
42.3.13
Title
Page
Number
DMFC - Display Multi FIFO Controller ............................................................... 42-613
DP - Display Processor .......................................................................................... 42-616
Display Interface (DI)............................................................................................ 42-623
Video De Interlacing Module (VDI)...................................................................... 42-638
Control Module (CM)............................................................................................ 42-643
IPUv3EX Diagnostics Unit.................................................................................... 42-698
Chapter 43
Keypad Port (KPP)
43.1
43.2
43.2.1
43.2.2
43.3
43.3.1
43.3.2
43.4
43.4.1
43.4.2
43.4.3
43.5
43.5.1
43.5.2
43.5.3
43.5.4
43.5.5
43.5.6
43.5.7
43.6
43.6.1
43.6.2
43.6.3
Introduction.................................................................................................................... 43-1
Overview........................................................................................................................ 43-2
Features...................................................................................................................... 43-2
Modes of Operation ................................................................................................... 43-2
External Signal Description ........................................................................................... 43-2
Input Pins ................................................................................................................... 43-3
Output Pins ................................................................................................................ 43-3
Memory Map and Register Definition........................................................................... 43-3
KPP Memory Map ..................................................................................................... 43-4
Register Summary...................................................................................................... 43-4
Register Descriptions................................................................................................. 43-5
Functional Description................................................................................................... 43-9
Keypad Matrix Construction ..................................................................................... 43-9
Keypad Port Configuration........................................................................................ 43-9
Keypad Matrix Scanning ......................................................................................... 43-10
Keypad Standby...................................................................................................... 43-10
Glitch Suppression on Keypad Inputs ..................................................................... 43-10
Multiple Key Closures ............................................................................................. 43-11
3-Point Contact Keys Support ................................................................................. 43-14
Initialization/Application Information ......................................................................... 43-15
Typical Keypad Configuration and Scanning Sequence.......................................... 43-15
Key Press Interrupt Scanning Sequence .................................................................. 43-16
Additional Comments .............................................................................................. 43-16
Chapter 44
Multi Master Multi Memory Interface (i.MX51)
44.1
44.1.1
44.1.2
44.1.3
Introduction.................................................................................................................... 44-1
Overview.................................................................................................................... 44-1
Features...................................................................................................................... 44-3
Modes of Operation ................................................................................................... 44-4
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxii
Freescale Semiconductor
Contents
Paragraph
Number
44.2
44.2.1
44.2.2
44.2.3
44.3
44.3.1
44.3.2
44.3.3
44.3.4
44.3.5
44.3.6
44.3.7
44.3.8
44.3.9
44.3.10
44.3.11
44.3.12
44.3.13
44.3.14
44.3.15
44.3.16
44.3.17
44.3.18
44.3.19
44.3.20
44.3.21
44.3.22
44.3.23
44.3.24
Title
Page
Number
Memory Map and Register Definition........................................................................... 44-9
Memory Map ............................................................................................................. 44-9
Register Summary.................................................................................................... 44-10
Register Descriptions............................................................................................... 44-23
Functional Description................................................................................................. 44-97
Write Access Description ........................................................................................ 44-97
Read Access Description ......................................................................................... 44-98
AXI Port Gasket Functional Description................................................................. 44-98
Read/Write Buffer Functional Description .............................................................. 44-99
Fast Arbitration Module Functional Description - 1st Degree ................................ 44-99
Slow Arbitration Module Functional Description ................................................. 44-103
Internal 1 Memory Arbitration Module Functional Description ........................... 44-103
Internal 2 Memory Arbitration Module Functional Description ........................... 44-104
Arbitration Scheme when Masters are in Same Priority (Bus Division)............... 44-104
WEIM-NFC Downsizer......................................................................................... 44-107
Internal 1 Downsizer.............................................................................................. 44-108
Clocks .................................................................................................................... 44-108
Reset....................................................................................................................... 44-109
Interrupts................................................................................................................ 44-110
Endianness ..............................................................................................................44-111
AXI Interface Restrictions ......................................................................................44-111
IPS Interface .......................................................................................................... 44-113
WaterMark Functionality Overview ...................................................................... 44-113
Snooping Functionality Overview ......................................................................... 44-114
Debug Unit............................................................................................................. 44-115
Buffers Size Table.................................................................................................. 44-116
Synchronization ..................................................................................................... 44-118
Supporting 8/16 Bit Bursts .................................................................................... 44-118
Dead-Lock Prevention in Read Accesses .............................................................. 44-118
Chapter 45
NAND Flash Controller (NFC)
45.1
45.2
45.3
45.4
45.5
45.5.1
45.5.2
45.6
Introduction.................................................................................................................... 45-1
Overview........................................................................................................................ 45-1
Features .......................................................................................................................... 45-2
Restrictions .................................................................................................................... 45-2
External Signal Description ........................................................................................... 45-2
Overview.................................................................................................................... 45-3
Detailed Signal Descriptions ..................................................................................... 45-4
NFC Memory Map and Registers Definition ................................................................ 45-5
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxiii
Contents
Paragraph
Number
45.6.1
45.6.2
45.6.3
45.7
45.7.1
45.7.2
45.7.3
45.7.4
45.7.5
45.7.6
45.7.7
45.7.8
45.7.9
45.7.10
45.7.11
45.7.12
45.7.13
45.7.14
45.7.15
45.7.16
45.7.17
45.7.18
45.7.19
45.7.20
45.7.21
45.7.22
45.7.23
45.7.24
45.7.25
45.7.26
45.7.27
45.7.28
45.7.29
45.7.30
45.7.31
45.8
45.8.1
45.8.2
45.8.3
45.8.4
45.8.5
Title
Page
Number
Memory Map ............................................................................................................. 45-5
Internal RAM Address Space and Organization........................................................ 45-8
Register Summary.................................................................................................... 45-12
Register Descriptions ................................................................................................... 45-18
Nand Flash Command (NAND_CMD) ................................................................... 45-18
NAND Flash Address0 (NAND_ADD0) ................................................................ 45-19
NAND Flash Address1 (NAND_ADD1) ................................................................ 45-19
NAND Flash Address2 (NAND_ADD2) ................................................................ 45-20
NAND Flash Address3 (NAND_ADD3) ................................................................ 45-21
NAND Flash Address4 (NAND_ADD4) ................................................................ 45-21
NAND Flash Address5 (NAND_ADD5) ................................................................ 45-22
NAND Flash Address6 (NAND_ADD6) ................................................................ 45-23
NAND Flash Address7 (NAND_ADD7) ................................................................ 45-23
NAND Flash Address8 (NAND_ADD8) ................................................................ 45-24
NAND Flash Address9 (NAND_ADD9) ................................................................ 45-25
NAND Flash Address10 (NAND_ADD10) ............................................................ 45-25
NAND Flash Address11 (NAND_ADD11) ............................................................ 45-26
NFC Configuration (NFC_CONFIGURATION1) .................................................. 45-26
ECC Status and Result of Flash Operation (ECC_STATUS_RESULT) ................. 45-29
Status Summary (STATUS_SUM) .......................................................................... 45-32
Initiate a Nand Transaction (LAUNCH NFC)......................................................... 45-33
NAND Flash Write Protection (NF_WR_PROT) ................................................... 45-37
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD0)............... 45-41
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD1)............... 45-41
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD2)............... 45-42
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD3)............... 45-43
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD4)............... 45-43
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD5)............... 45-44
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD6)............... 45-45
Address to Unlock in Write Protection Mode (UNLOCK_BLK_ADD7)............... 45-45
NAND Flash Operation Configuration2 (NFC_CONFIGURATION2).................. 45-46
NAND Flash Operation Configuration3 (NFC_CONFIGURATION3).................. 45-48
NAND Flash IP control (NFC_IPC)........................................................................ 45-53
AXI Error Address (AXI_ERR_ADD).................................................................... 45-55
Delay-Line (NFC_DELAY_LINE) ......................................................................... 45-56
Functional Description................................................................................................. 45-57
Reset......................................................................................................................... 45-57
NAND Flash I/F Control ......................................................................................... 45-57
DMA Request Operation ......................................................................................... 45-60
Internal RAM........................................................................................................... 45-60
AXI Bus Interface.................................................................................................... 45-61
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxiv
Freescale Semiconductor
Contents
Paragraph
Number
45.8.6
45.8.7
45.9
45.9.1
45.9.2
45.9.3
45.9.4
45.9.5
45.9.6
45.9.7
45.9.8
45.10
45.11
Title
Page
Number
IP interface............................................................................................................... 45-61
I/O Pins Sharing....................................................................................................... 45-62
NFC Operation............................................................................................................. 45-63
Automatic Operations .............................................................................................. 45-63
Atomic Operations................................................................................................... 45-66
Atomic Operations Sequence................................................................................... 45-74
ECC Operation......................................................................................................... 45-77
Symmetric/Asymmetric Mode Operation................................................................ 45-79
Delay Line Operation............................................................................................... 45-81
Write Protection Operation ...................................................................................... 45-82
Delay Line Operation............................................................................................... 45-86
Memory Connectivity Examples ................................................................................. 45-91
Verified Nand Models.................................................................................................. 45-94
Chapter 46
Parallel Advanced Technology Attachment (P-ATA)
46.1
46.1.1
46.1.2
46.2
46.2.1
46.2.2
46.2.3
46.3
46.3.1
46.3.2
46.3.3
46.4
46.4.1
46.4.2
46.4.3
46.4.4
46.4.5
Overview........................................................................................................................ 46-1
Features...................................................................................................................... 46-3
Modes of Operation ................................................................................................... 46-3
External Signal Description ........................................................................................... 46-4
Detailed Signal Descriptions ..................................................................................... 46-4
Electrical Spec on the ATA Bus, Bus Buffers............................................................ 46-6
Timing on ATA bus.................................................................................................... 46-6
Memory Map and Register Definition......................................................................... 46-15
Memory Map ........................................................................................................... 46-15
Register Summary.................................................................................................... 46-17
Register Descriptions............................................................................................... 46-20
Functional Description................................................................................................. 46-36
Resetting ATA Bus................................................................................................... 46-36
Programming ATA Bus Timing and iordy_en ......................................................... 46-36
Access to ATA Bus in PIO Mode ............................................................................ 46-37
Using DMA Mode to Receive Data from ATA bus................................................. 46-37
Using DMA Mode to Transmit Data to ATA bus .................................................... 46-38
Chapter 47
Pulse-Width Modulator (PWM)
47.1
47.1.1
47.2
Signal Description.......................................................................................................... 47-2
External Signals ......................................................................................................... 47-2
Memory Map and Register Definition........................................................................... 47-2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxv
Contents
Paragraph
Number
47.2.1
47.2.2
47.3
47.3.1
Page
Number
Title
Register Summary...................................................................................................... 47-3
Register Descriptions................................................................................................. 47-5
Functional Description................................................................................................. 47-11
Operation ................................................................................................................. 47-11
Chapter 48
Run-Time Integrity Checker (RTIC)
48.1
48.1.1
48.2
Features .......................................................................................................................... 48-1
Modes of Operation ................................................................................................... 48-2
Initialization/Application Information ........................................................................... 48-2
Chapter 49
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA)
49.1
49.1.1
Features .......................................................................................................................... 49-2
Modes of Operation ................................................................................................... 49-3
Chapter 50
Security Controller (SCC)
50.1
Overview........................................................................................................................ 50-2
Chapter 51
Subscriber Identification Module (SIM)
51.1
51.1.1
51.1.2
51.1.3
51.1.4
51.1.5
51.1.6
51.1.7
51.1.8
51.1.9
51.2
51.2.1
51.2.2
51.3
51.3.1
Overview........................................................................................................................ 51-1
Modes of Operation ................................................................................................... 51-2
SIM Bus Interface Overview ..................................................................................... 51-2
SIM Clock Generator Overview ................................................................................ 51-3
SIM Transmitter Overview ........................................................................................ 51-3
SIM Receiver Overview ............................................................................................ 51-4
SIM Port Control Overview....................................................................................... 51-4
SIM General Purpose Counter Overview .................................................................. 51-5
SIM LRC Block Overview ........................................................................................ 51-5
SIM CRC Block Overview ........................................................................................ 51-5
External Signal Description ........................................................................................... 51-5
Overview.................................................................................................................... 51-5
Detailed Signal Descriptions ..................................................................................... 51-7
Memory Map and Register Definition........................................................................... 51-8
Memory Map ............................................................................................................. 51-8
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxvi
Freescale Semiconductor
Contents
Paragraph
Number
51.3.2
51.3.3
51.4
51.4.1
51.4.2
51.4.3
51.4.4
51.4.5
51.4.6
51.4.7
51.4.8
51.4.9
51.5
51.5.1
51.5.2
51.5.3
51.5.4
Title
Page
Number
Register Summary.................................................................................................... 51-10
Register Descriptions............................................................................................... 51-14
Functional Description................................................................................................. 51-46
SIM Bus Interface.................................................................................................... 51-48
SIM Clock Generator............................................................................................... 51-50
SIM Transmitter....................................................................................................... 51-52
SIM Receiver ........................................................................................................... 51-56
SIM Port Control ..................................................................................................... 51-62
SIM General Purpose Counter................................................................................. 51-64
SIM LRC Block ....................................................................................................... 51-65
SIM CRC Block....................................................................................................... 51-65
Module Interrupts .................................................................................................... 51-67
Initialization/Application Information ......................................................................... 51-67
Configuring SIM for Operation ............................................................................... 51-67
Using the SIM Receiver........................................................................................... 51-72
Using SIM Transmitter ............................................................................................ 51-76
Suggested “T=1” Compliant Programming Model ................................................. 51-79
Chapter 52
Smart Direct Memory Access (SDMA) Controller
52.1
52.1.1
52.1.2
52.2
52.3
52.3.1
52.3.2
52.3.3
52.4
52.4.1
52.4.2
52.4.3
52.4.4
52.5
52.5.1
52.6
52.6.1
52.6.2
52.7
52.7.1
Introduction.................................................................................................................... 52-1
Overview.................................................................................................................... 52-1
Features...................................................................................................................... 52-3
Functional Description................................................................................................... 52-4
SDMA Core ................................................................................................................... 52-5
SDMA Core Structure ............................................................................................... 52-6
Program Control Unit (PCU)..................................................................................... 52-8
SDMA Core Memory .............................................................................................. 52-11
Scheduler ..................................................................................................................... 52-11
Primary Functions.................................................................................................... 52-11
Channels and DMA Requests .................................................................................. 52-11
Scheduler Functional Description............................................................................ 52-12
Context Switching.................................................................................................... 52-23
Profiling Unit ............................................................................................................... 52-25
Profiling Sequence................................................................................................... 52-26
Functional Units........................................................................................................... 52-26
Burst DMA Unit ...................................................................................................... 52-27
Burst DMA2 Unit .................................................................................................... 52-30
SDMA Security Support .............................................................................................. 52-33
Locked Mode ........................................................................................................... 52-33
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxvii
Contents
Paragraph
Number
52.8
52.9
52.9.1
52.9.2
52.10
52.11
52.11.1
52.11.2
52.11.3
52.12
52.12.1
52.12.2
52.12.3
52.13
52.13.1
52.13.2
52.13.3
52.13.4
52.13.5
52.14
52.14.1
52.14.2
52.14.3
52.15
52.16
52.16.1
52.16.2
52.16.3
52.16.4
52.17
52.17.1
52.17.2
52.17.3
52.17.4
52.17.5
52.17.6
52.17.7
52.17.8
52.17.9
52.17.10
52.17.11
Title
Page
Number
OnCE and PCU Debug States...................................................................................... 52-34
SDMA Clocks and Low Power Modes........................................................................ 52-35
Clock Gating and Low Power Modes...................................................................... 52-36
Reset......................................................................................................................... 52-39
Software Interface........................................................................................................ 52-39
Initialization Information ............................................................................................. 52-39
Hardware Reset........................................................................................................ 52-39
Channel Script Execution ........................................................................................ 52-40
Initialization and Script Execution Setup Sequence ................................................ 52-40
AP Memory Map and Control Register Definitions .................................................... 52-41
AP Memory Map ..................................................................................................... 52-41
Register Summary.................................................................................................... 52-43
Register Descriptions............................................................................................... 52-48
SDMA Programming Model ....................................................................................... 52-76
State and Registers Per Channel .............................................................................. 52-76
General Purpose Registers ....................................................................................... 52-77
Functional Unit State ............................................................................................... 52-77
Context Switching.................................................................................................... 52-78
Address Space.......................................................................................................... 52-80
SDMA Internal (Core) Memory Map and Internal Register Definitions .................... 52-82
SDMA Internal (Core) Registers Memory Map ...................................................... 52-82
Register Summary.................................................................................................... 52-83
SDMA Core Register Descriptions.......................................................................... 52-88
SDMA Peripheral Registers....................................................................................... 52-109
SDMA Initialization .................................................................................................. 52-110
Hardware Reset...................................................................................................... 52-110
Standard Boot Sequence ........................................................................................ 52-110
User-Defined Boot Sequence................................................................................. 52-110
Script Loading and Context Initialization...............................................................52-111
Instruction Description ...............................................................................................52-111
Scheduling Instructions...........................................................................................52-111
Conditional Branch Instructions .............................................................................52-111
Unconditional Jump Instructions ........................................................................... 52-112
Subroutine Return Instructions .............................................................................. 52-112
Loop Instruction..................................................................................................... 52-112
Miscellaneous Instructions .................................................................................... 52-112
Logic Instructions .................................................................................................. 52-112
Arithmetic Instructions .......................................................................................... 52-113
Compare Instructions............................................................................................. 52-113
Test Instructions ..................................................................................................... 52-114
Byte Permutation Instructions ............................................................................... 52-114
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxviii
Freescale Semiconductor
Contents
Paragraph
Number
52.17.12
52.17.13
52.17.14
52.17.15
52.17.16
52.17.17
52.18
52.18.1
52.18.2
52.18.3
52.19
52.19.1
52.19.2
52.19.3
52.19.4
52.19.5
52.20
52.20.1
52.20.2
52.20.3
52.20.4
52.20.5
52.20.6
52.20.7
52.20.8
52.21
52.21.1
52.21.2
52.22
52.22.1
52.23
52.23.1
52.24
52.25
Title
Page
Number
Bit Shift Instructions.............................................................................................. 52-114
Bit Manipulation Instructions ................................................................................ 52-114
SDMA Memory Access Instructions..................................................................... 52-114
Functional Unit Instructions .................................................................................. 52-115
Illegal Instructions ................................................................................................. 52-115
Debug Instructions................................................................................................. 52-115
Functional Units Programming Model ...................................................................... 52-116
Burst DMA Unit .................................................................................................... 52-116
Burst DMA2 Unit .................................................................................................. 52-130
OnCE and Real-Time Debug ................................................................................. 52-143
The OnCE Controller................................................................................................. 52-144
OnCE Commands .................................................................................................. 52-144
Sending Commands to the OnCE Controller......................................................... 52-145
Executing a Command from the OnCE ................................................................. 52-147
Registers Descriptions ........................................................................................... 52-149
JTAG Interface Requirements................................................................................ 52-151
Using the OnCE ......................................................................................................... 52-153
Activating Clocks in Debug Mode ........................................................................ 52-153
Getting the Current Status...................................................................................... 52-154
Methods of Entering Debug Mode ........................................................................ 52-154
Executing Instructions in Debug Mode ................................................................. 52-155
Command Sequences Examples ............................................................................ 52-155
OnCE Event Detection Unit .................................................................................. 52-159
Clock Gating and Reset ......................................................................................... 52-160
Real Time Features ................................................................................................ 52-161
Instruction Set ............................................................................................................ 52-165
Instruction Encoding.............................................................................................. 52-165
SDMA Instruction Set ........................................................................................... 52-167
Software Restrictions ................................................................................................. 52-228
Unsupported Burst DMA Access Sequence .......................................................... 52-228
Application Notes ...................................................................................................... 52-228
Data Structures for Boot Code and Channel Scripts.............................................. 52-228
Definitions, Acronyms, Abbreviations ...................................................................... 52-237
References.................................................................................................................. 52-238
Chapter 53
Sony/Philips Digital Interface Transmitter (SPDIF Tx)
53.1
53.1.1
53.1.2
Introduction.................................................................................................................... 53-1
Overview.................................................................................................................... 53-1
Features...................................................................................................................... 53-2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxix
Contents
Paragraph
Number
53.2
53.3
53.3.1
53.3.2
53.3.3
53.4
Title
Page
Number
External Signal Description ........................................................................................... 53-2
Memory Map and Register Definition........................................................................... 53-3
Memory Map ............................................................................................................. 53-3
Register Summary...................................................................................................... 53-3
Register Descriptions................................................................................................. 53-7
Functional Description................................................................................................. 53-14
Chapter 54
System Reset Controller (SRC)
54.1
54.1.1
54.1.2
54.2
54.2.1
54.2.2
54.3
54.3.1
54.3.2
54.3.3
54.3.4
54.3.5
54.3.6
Introduction.................................................................................................................... 54-1
Overview.................................................................................................................... 54-1
Features...................................................................................................................... 54-2
Register Definition......................................................................................................... 54-2
Register Summary...................................................................................................... 54-3
Register Descriptions................................................................................................. 54-4
Functional Description................................................................................................. 54-12
Reset Control ........................................................................................................... 54-12
SJC_POR_RST_B Generation ................................................................................ 54-35
SRC_MEGAMIX_ISO Generation ......................................................................... 54-35
Parallel Reset Requests............................................................................................ 54-36
DFT Mux on Reset Outputs..................................................................................... 54-36
Boot Mode Control .................................................................................................. 54-37
Chapter 55
Secure Real Time Clock (SRTC)
55.1
55.1.1
55.1.2
55.1.3
55.1.4
Overview........................................................................................................................ 55-1
Low Power SRTC (SRTC LP) Description ............................................................... 55-1
High Power SRTC (SRTC HP) Description .............................................................. 55-2
Features...................................................................................................................... 55-4
Modes of Operations.................................................................................................. 55-5
Chapter 56
Synchronous Serial Interface (SSI)
56.1
56.1.1
56.1.2
56.2
56.2.1
Overview........................................................................................................................ 56-1
Features...................................................................................................................... 56-2
Modes of Operation ................................................................................................... 56-3
External Signal Description ......................................................................................... 56-20
Detailed Signal Descriptions ................................................................................... 56-20
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxx
Freescale Semiconductor
Contents
Paragraph
Number
56.3
56.3.1
56.3.2
56.3.3
56.4
56.4.1
56.4.2
56.4.3
56.4.4
56.4.5
56.4.6
56.5
Title
Page
Number
Memory Map and Register Definition......................................................................... 56-25
SSI Memory Map..................................................................................................... 56-25
Register Summary.................................................................................................... 56-27
Register Descriptions............................................................................................... 56-31
Functional Description................................................................................................. 56-69
SSI Architecture....................................................................................................... 56-70
SSI Clocking ............................................................................................................ 56-70
Receive Interrupt Enable Bit Description................................................................ 56-74
Transmit Interrupt Enable Bit Description .............................................................. 56-74
Internal Frame and Clock Shutdown ....................................................................... 56-75
IP Bus Interface ....................................................................................................... 56-76
Initialization/Application Information ......................................................................... 56-77
Chapter 57
TrustZone Interrupt Controller (TZIC)
57.1
57.1.1
57.1.2
57.2
57.3
57.3.1
57.3.2
57.3.3
57.4
57.4.1
57.4.2
57.4.3
57.4.4
57.4.5
57.4.6
57.4.7
57.4.8
57.4.9
57.5
Introduction.................................................................................................................... 57-1
Features...................................................................................................................... 57-2
Modes of Operation ................................................................................................... 57-2
External Signal Description ........................................................................................... 57-2
Memory Map and Register Definition........................................................................... 57-2
TZIC Register ..................................................................................... Memory Map57-2
Register Summary...................................................................................................... 57-4
Register Descriptions................................................................................................. 57-8
Functional Description................................................................................................. 57-27
Security Configurability .......................................................................................... 57-28
AXI Interface ........................................................................................................... 57-29
Register Block.......................................................................................................... 57-30
Interrupt Engine ....................................................................................................... 57-30
Auto-Vectored Interrupt Handling ........................................................................... 57-31
Integration Options .................................................................................................. 57-31
Clocks ...................................................................................................................... 57-32
Reset......................................................................................................................... 57-32
Endianness ............................................................................................................... 57-32
Initialization Information ............................................................................................. 57-32
Chapter 58
TV Encoder (TVE)
58.1
58.1.1
Introduction.................................................................................................................... 58-1
Features...................................................................................................................... 58-1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxxi
Contents
Paragraph
Number
58.1.2
58.1.3
58.1.4
58.2
58.2.1
58.3
58.3.1
58.3.2
58.3.3
Page
Number
Title
Overview.................................................................................................................... 58-5
Features.................................................................................................................... 58-12
Modes of Operation ................................................................................................. 58-15
External Signal Description ......................................................................................... 58-22
Interface Between the IPU and the TVE ................................................................. 58-30
Memory Map and Register Definition......................................................................... 58-31
Register Map............................................................................................................ 58-31
Register Summary.................................................................................................... 58-34
Register Descriptions............................................................................................... 58-43
Chapter 59
Universal Asynchronous Receiver/Transmitter (UART)
59.1
59.1.1
59.1.2
59.2
59.2.1
59.3
59.3.1
59.3.2
59.3.3
59.4
59.4.1
59.4.2
59.4.3
59.4.4
59.4.5
59.4.6
59.4.7
59.4.8
59.4.9
59.4.10
59.4.11
59.5
Overview........................................................................................................................ 59-1
Features...................................................................................................................... 59-2
Modes of Operation ................................................................................................... 59-2
External Signals ............................................................................................................. 59-3
Detailed Signal Descriptions ..................................................................................... 59-3
Memory Map and Register Definition........................................................................... 59-5
Memory Map ............................................................................................................. 59-6
Register Summary...................................................................................................... 59-6
Register Descriptions............................................................................................... 59-10
Functional Description................................................................................................. 59-33
Interrupts and DMA Requests ................................................................................. 59-33
Clocks ...................................................................................................................... 59-34
General UART Definitions ...................................................................................... 59-35
Transmitter............................................................................................................... 59-40
Receiver ................................................................................................................... 59-43
Binary Rate Multiplier (BRM) ................................................................................ 59-52
Infrared Interface ..................................................................................................... 59-53
Low Power Modes ................................................................................................... 59-59
Reset......................................................................................................................... 59-60
Transfer Error........................................................................................................... 59-60
Functional Timing.................................................................................................... 59-60
Initialization ................................................................................................................. 59-62
Chapter 60
Universal Serial Bus OTG HOST (USBOH3)
60.1
60.1.1
Introduction.................................................................................................................... 60-1
Features...................................................................................................................... 60-2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxxii
Freescale Semiconductor
Contents
Paragraph
Number
60.1.2
60.2
60.2.1
60.3
60.3.1
60.3.2
60.3.3
60.3.4
60.3.5
60.3.6
60.3.7
60.3.8
60.3.9
60.4
60.4.1
60.4.2
60.4.3
60.4.4
60.4.5
60.4.6
60.4.7
Title
Page
Number
Modes of Operation ................................................................................................... 60-3
Memory Map/Register Definition ................................................................................. 60-5
Register Descriptions................................................................................................. 60-9
Functional Description................................................................................................. 60-24
USB HOST Controller 1.......................................................................................... 60-24
USB Host Controller 2............................................................................................. 60-29
USB Host Controller 3............................................................................................. 60-34
USB OTG Controller ............................................................................................... 60-40
USB Power Control Module.................................................................................... 60-45
Transceiverless Link Logic (HS/FS-TLL) Module ................................................. 60-46
USB Bypass Mode................................................................................................... 60-56
ULPI/Serial MUX.................................................................................................... 60-59
Interrupts.................................................................................................................. 60-60
Initialization/Application Information ......................................................................... 60-60
Software Model........................................................................................................ 60-60
Register Interface..................................................................................................... 60-62
Host Data Structures .............................................................................................. 60-112
Host Operational Model ........................................................................................ 60-133
EHCI Deviation ..................................................................................................... 60-213
Device Data Structures .......................................................................................... 60-220
Device Operational Model..................................................................................... 60-226
Chapter 61
Video Processing Unit (VPU)
61.1
61.1.1
61.1.2
61.1.3
61.2
61.2.1
61.3
61.3.1
61.3.2
61.3.3
61.4
61.4.1
61.4.2
61.4.3
61.4.4
61.4.5
Introduction.................................................................................................................... 61-1
Overview.................................................................................................................... 61-1
Features...................................................................................................................... 61-2
Modes of Operation ................................................................................................... 61-4
External Signal Description ........................................................................................... 61-4
Detailed Signal Descriptions ..................................................................................... 61-6
Memory Map and Register Definition........................................................................... 61-7
Memory Map ............................................................................................................. 61-7
Register Summary...................................................................................................... 61-8
Register Descriptions............................................................................................... 61-10
Functional Description................................................................................................. 61-14
VPU Architecture .................................................................................................... 61-14
Clocks ...................................................................................................................... 61-17
Reset......................................................................................................................... 61-17
Interrupts.................................................................................................................. 61-18
Endianness ............................................................................................................... 61-18
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxxiii
Contents
Paragraph
Number
61.5
61.6
61.6.1
61.6.2
61.6.3
Title
Page
Number
Initialization Information ............................................................................................. 61-18
Application Information .............................................................................................. 61-19
Video Decoding Processing Control........................................................................ 61-20
Video Encoding Processing Control ........................................................................ 61-24
Video Codec Processing Buffer Requirement ......................................................... 61-26
Chapter 62
Watchdog Timer (WDOG)
62.1
62.2
62.3
62.4
62.4.1
62.4.2
62.5
62.5.1
62.5.2
62.5.3
62.5.4
62.5.5
62.6
62.6.1
62.6.2
62.6.3
62.6.4
62.6.5
62.6.6
62.7
62.7.1
62.7.2
Overview........................................................................................................................ 62-1
Features .......................................................................................................................... 62-3
External Signal Description ........................................................................................... 62-3
Memory Map and Register Definitions ......................................................................... 62-3
Watchdog Timer Memory Map.................................................................................. 62-3
Register Summary...................................................................................................... 62-4
Register Descriptions ..................................................................................................... 62-5
Watchdog Control Register (WCR) ........................................................................... 62-5
Watchdog Service Register (WSR)............................................................................ 62-7
Watchdog Reset Status Register (WRSR) ................................................................. 62-7
Watchdog Interrupt Control Register (WICR)........................................................... 62-8
Watchdog Miscellaneous Control Register (WMCR) ............................................... 62-9
Functional Description................................................................................................... 62-9
Timing Specifications ................................................................................................ 62-9
Watchdog During Reset ........................................................................................... 62-10
Watchdog After Reset .............................................................................................. 62-10
Low-Power and DEBUG Modes ............................................................................. 62-12
Watchdog Reset Control .......................................................................................... 62-12
ipp_wdog Operation ................................................................................................ 62-13
Initialization/Application Information ......................................................................... 62-14
Software Restrictions............................................................................................... 62-14
Flow Diagrams......................................................................................................... 62-15
Chapter 63
Wireless External Interface Module (WEIM)
63.1
63.2
63.2.1
63.2.2
63.2.3
63.2.4
Features .......................................................................................................................... 63-3
Modes of Operation ....................................................................................................... 63-3
Asynchronous Mode .................................................................................................. 63-4
Asynchronous Page Read Mode ................................................................................ 63-4
Multiplexed Address/Data Mode............................................................................... 63-4
Burst Clock Mode...................................................................................................... 63-5
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxxiv
Freescale Semiconductor
Contents
Paragraph
Number
63.2.5
63.2.6
63.3
63.3.1
63.3.2
63.4
63.4.1
63.4.2
63.4.3
63.5
63.5.1
63.5.2
63.5.3
63.5.4
63.5.5
63.5.6
63.5.7
63.5.8
63.5.9
63.5.10
63.5.11
63.5.12
63.5.13
63.5.14
63.5.15
63.5.16
63.5.17
63.5.18
63.5.19
63.5.20
63.5.21
63.6
63.6.1
63.6.2
63.7
63.7.1
63.7.2
63.7.3
63.7.4
63.7.5
63.7.6
Title
Page
Number
Low-Power Modes..................................................................................................... 63-5
Boot Mode ................................................................................................................. 63-5
External Signal Description ........................................................................................... 63-6
Overview.................................................................................................................... 63-6
Detailed Signal Descriptions ..................................................................................... 63-9
Memory Map and Register Definition......................................................................... 63-13
Memory Map ........................................................................................................... 63-14
Register Summary.................................................................................................... 63-17
Register Descriptions............................................................................................... 63-19
Functional Description................................................................................................. 63-37
Clocks ...................................................................................................................... 63-37
Bus Sizing Configuration......................................................................................... 63-37
WEIM Operational Modes....................................................................................... 63-38
Burst Mode (Synchronous) Memory Operation ...................................................... 63-39
Burst Clock Divisor (BCD) ..................................................................................... 63-39
Burst Clock Start (BCS) .......................................................................................... 63-40
Multiplexed Address/Data Mode............................................................................. 63-40
Mixed Master/Memory Burst Modes Support......................................................... 63-40
AXI (Master) Bus Cycles Support........................................................................... 63-40
WAIT_B Signal, RWSC, and WWSC Bit Fields Usage.......................................... 63-43
IPS Register Interface .............................................................................................. 63-43
MRS Set for PSRAM............................................................................................... 63-43
WEIM Access Termination ..................................................................................... 63-44
Error Conditions ...................................................................................................... 63-44
DTACK Mode.......................................................................................................... 63-44
RDY_INT Signal as Interrupt.................................................................................. 63-45
RDY_INT Signal as Ready After Reset Indication ................................................. 63-45
WEIM_GRANT/WEIM_BUSY Handshake Description ....................................... 63-45
LPMD/LPACK Handshake Description .................................................................. 63-45
Endianness ............................................................................................................... 63-46
Strobe Signal Use..................................................................................................... 63-47
Initialization Information ............................................................................................. 63-47
Active Chip Selects and Address Space Configuration........................................... 63-47
Booting from WEIM................................................................................................ 63-48
Application Note.......................................................................................................... 63-49
Access to AMD Flash.............................................................................................. 63-49
Access to Intel Sibley Flash..................................................................................... 63-50
Access to MDOC Device......................................................................................... 63-52
Access to Micron PSRAM....................................................................................... 63-53
Access to Samsung OneNAND ............................................................................... 63-53
Access to Samsung UtRAM .................................................................................... 63-55
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
xxxv
Contents
Paragraph
Number
63.7.7
63.7.8
63.8
63.8.1
63.8.2
63.8.3
63.8.4
63.8.5
63.8.6
63.8.7
63.8.8
63.8.9
63.8.10
63.8.11
Title
Page
Number
Access to Spansion Flash......................................................................................... 63-55
8-Bit Support............................................................................................................ 63-58
Booting from One NAND Devices.............................................................................. 63-58
Asynchronous Read Memory Accesses Timing Diagram ....................................... 63-59
Asynchronous Write Memory Accesses Timing Diagram ...................................... 63-60
Asynchronous Read/Write Memory Accesses Timing Diagram ............................. 63-61
Asynchronous Read/Write using RAL, WAL and CSREC ..................................... 63-63
Consecutive Asynchronous Write Memory Accesses Timing Diagram ................. 63-64
Consecutive Asynchronous Read Memory Accesses Timing Diagram .................. 63-65
Burst Read Memory Accesses Timing Diagram - BCD=0...................................... 63-67
Burst Read Memory Accesses Timing Diagram - BCD=1...................................... 63-68
Async. Page Mode Access....................................................................................... 63-69
DTACK Mode—AXI Single Access ....................................................................... 63-70
DTACK Mode—AXI Burst Access......................................................................... 63-73
Appendix A
IOMUX Controller (IOMUXC)
A.1
A.1.1
A.1.2
A.1.3
A.2
A.3
A.3.1
A.3.2
A.3.3
A.3.4
A.4
A.4.1
Introduction.................................................................................................................... 64-1
Overview.................................................................................................................... 64-1
Features...................................................................................................................... 64-3
Modes of Operation ................................................................................................... 64-3
External Signal Description ........................................................................................... 64-3
Functional Description................................................................................................... 64-3
ALT6 and ALT7 Extended Muxing Modes ............................................................... 64-6
SW Loopback through SION Bit............................................................................... 64-6
Daisy Chain—Multi Pads Ddriving Same Module Input Pin.................................... 64-6
Interrupts.................................................................................................................... 64-8
Memory Map and Register Definition........................................................................... 64-8
Registers Definition ................................................................................................... 64-8
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
xxxvi
Freescale Semiconductor
About This Book
The primary objective of this reference manual is to define the functionality of the MCIMX51 (i.MX51).
The i.MX51 is ideal for power-thirsty applications, such as video and audio media players. The i.MX51
processor includes leading power management, security management, digital rights management, video
and image processing technology, providing a formidable combination of the features OEMs desire to
drive high-performance video and audio content on wireless mobile devices. The processor is designed
with Freescale’s Smart Speed Technology, which enables ultra low-power consumption and performance
equivalent to processors with much higher MHz.
Audience
It is assumed that the reader understands operating systems, microprocessor system design, and the basic
principles of RISC processing.
Organization
Following is a summary and a brief description of the major parts of this reference manual:
Book I contains information that is unique to the i.MX51. The following chapters are included:
• Chapter 1, “Introduction” provides a high-level description of features and functionality of the
integrated host processor. It describes the MCIMX51, its interfaces, and its programming model.
The functional operation with emphasis on peripheral functions is also described.
• Chapter 2, “Memory Map” describes the memory map. An overview of the local address map is
followed by a description of how local access windows are used to define the local address map.
The inbound and outbound address translation mechanisms used to map to and from external
memory spaces are described next. Finally, the configuration, control, and status registers are
described, including a complete listing of all memory-mapped registers with cross references to the
sections detailing descriptions of each.
• Chapter 3, “Interrupts and DMA Events” provides a listing of the Interrupts and DMA Events. This
chapter also provides information on the assignments of interrupts and of the DMA events.
• Chapter 4, “External Signals and Pin Multiplexing” describes the external signals and pin
multiplexing. The input-output multiplexer (IOMUX) controls the pin multiplexing. The IOMUX
also configures other pin characteristics, such as voltage level, drive strength, and hysteresis. This
chapter organizes the signals by functional group (as defined by the top-level block diagrams) and
then by subgroups (interfaces) within each functional group.
• Chapter 5, “External Memories” describes the module that controls all i.MX51 external memory
accesses (read/write/erase/program) from all the masters in the system to different external
memories. All accesses are arbitrated by the Multi Master Multi Memory Interface (M4IF) module
and controlled by the respective memory controller. Because different modules require different
pad settings (like pull up, keeper, and others), the IOMUXC controls also the pad settings
parameters.
• Chapter 6, “Fuse Map” lists all fusable elements in the i.MX51.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
I
•
•
•
•
•
•
Chapter 7, “Clock Controller Module (CCM)” controls the clocks for the i.MX51 modules. This
module uses the available clock sources to generate the clock roots.
Chapter 8, “Debug Architecture” describes the hardware and software debug and application
development features and resources of i.MX51. There are core/platform-specific resources,
resources associated with some of the more complex IP blocks, and chip-wide resources.
Chapter 9, “System Boot” describes the system boot sequence of the i.MX51 application processor
and provides the details of boot options.1
Chapter 10, “Multimedia” contains descriptions of the major components of the Multimedia
module including the Video Processing Unit (VPU), Graphics Processing Unit (GPU): accelerating
2D/3D graphics, Image Processing Unit (IPU): providing connectivity to cameras and displays,
related processing, synchronization and control.
Chapter 11, “Power Management” describes the operation of the various power management
techniques supported by the i.MX51 and the registers used to configure and control them. These
power management techniques reduce active and static power consumption.
Chapter 12, “System Security” describes the security features designed into the i.MX51.
Book II contains chapters describing modules in the i.MX51 that are common to the MX generation of ICs.
The following chapters are included:
• Chapter 13, “1-Wire Module (1-Wire)” describes the 1-Wire module, which provides the
communication link to a generic 1-Kbit add-only memory. The module sends or receives one bit at
a time with an option for software to manage the data using bytes.
• Chapter 14, “Cortex-A8 Platform” provides an overview of the ARM Cortex-A8n platform, which
includes a NEON co-processor, an L1 cache, an L2 cache, an ETM and a CTI. The platform
includes the essential sub-blocks: platform control, test logic and the debug modules (CTM, ETB,
and a second CTI).
• Chapter 15, “Platform Debug” provides an overview of the ARM platform debug. It will cover the
modules inside the tigerp_gp_debug block and also the modules that support the platform debug
within the SOC, but external to the ARM platform
• Chapter 16, “Multi-Layer AHB Crossbar Switch (MAX)” provides an overview of the MAX
(Multi-Layer AHB Crossbar Switch). The purpose of the MAX is to concurrently support up to 4
simultaneous connections between master ports and slave ports.
• Chapter 17, “Digital Audio Mux (AUDMUX)” describes the AUDMUX, which provides a
programmable interconnect device for voice, audio, and synchronous data routing between host
serial interfaces (that is, SSI, SAP) and peripheral serial interfaces (that is, audio and voice
CODECs, also known as coder-decoders).
• Chapter 18, “Configurable Serial Peripheral Interface (CSPI)” describes the Configurable Serial
Peripheral Interface (CSPI) module, which allows rapid data communication with fewer software
interrupts than conventional serial communications.
• Chapter 19, “Clock Amplifier (CAMP)” describes the Clock Amplifier, which converts a square
wave/sinusoidal input of frequency range 8–40 MHz into a rail-to-rail square wave (CAMP supply
voltage).
1. Portions of this chapter are restricted. See your Freescale representative for details.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
II
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
Chapter 20, “Central Security Unit (CSU)” describes the Central Security Unit (CSU), which
enables software for setting comprehensive security policy within the platform and sharing secure
information between various secure modules.
Chapter 21, “Digital Phase Lock Loop (DPLL)” describes the three on-chip Digital Phase Lock
Loops (DPLLs), which provide clock generation in digital and mixed analog/digital chips designed
for wireless communication and other applicationsThis chapter provides an overview of the DPLL
opertation.
Chapter 22, “DPLL-IP Interface (DPLL-IP)” describes the DPLL-IP, which serves as an interface
to the DPLL module. It generates the control signals required for the DPLL operations. In other
MX ICs this used to be part of the SRC (System Reset Controller) module
Chapter 23, “Dynamic Process and Temperature Compensation (DPTC)” describes the DPTC
(Dynamic Process and Temperature Compensation) module, which is a power management
module. The purpose of the DPTC module is to detect the minimum operation voltage for the IC,
regarding process corner case and temperature for a given frequency
Chapter 24, “Dynamic Voltage Frequency Scaling (DVFS)” The DVFS allows simple dynamic
voltage frequency scaling. The frequency of the core clock domain and the voltage of the core
power domain can be changed on the fly while all modules (including the MCU) continue their
normal operation.
Chapter 25, “Dynamic Voltage Frequency Scaling for Peripherals (DVFS_PER)” Dynamic
Voltage and Frequency Scaling (DVFS) enables the frequency of the system and the voltage of the
power domain to be changed on the fly while all modules continue their normal operation on
reduced frequency.
Chapter 26, “Enhanced Configurable Serial Peripheral Interface (eCSPI)” The eCSPI module
allows rapid data communication with fewer software interrupts than conventional serial
communications methodologies.
Chapter 27, “External Memory Interface (EMI)” The EMI is a memory controller of memory
devices in the system, both internal and external. It provides a capability for the system to control
the external memory device, by preforming several type of accesses like read, write, program, and
erase as well as internal memories of the system.
Chapter 28, “Embedded Memory Periphery Power Gating Controller (EMPGC)”
Chapter 29, “Enhanced Periodic Interrupt Timer (EPIT)” The Enhanced Periodic Interrupt Timer
(EPIT) is a 32-bit set-and-forget timer which begins counting after the EPIT is enabled by software.
It is capable of providing precise interrupts at regular intervals with minimal processor
intervention.
Chapter 30, “Enhanced SDRAM Controller (eSDCTL)” The Enhanced SDRAM Controller
version 2 (eSDCTLV2) consists of nine major blocks, including the SDRAM command state
machine controller, bank register (page and bank address comparators), Row/Column Address
Multiplexer, configuration registers, refresh request counter, command sequencer, size logic
(splitting access), data path (data aligner/multiplexer), LPDDR interface, and the Power Down
timer.
Chapter 31, “Enhanced Secured Digital Host Controller (eSDHC)” The eSDHC provides the
interface between the host system and MMC/SD/SDIO/CE-ATA cards, including cards with
reduced size or mini cards.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
III
•
•
•
•
•
•
•
•
•
•
•
•
•
Chapter 32, “Fast Ethernet Controller (FEC)” This chapter provides a feature-set overview, a
functional block diagram, and transceiver connection information for both the 10 and 100 Mbps
Media Independent Interface (MII), as well as the 7-wire serial interface.
Chapter 33, “Fast Infrared Interface (FIRI)” The Fast Infrared Interface module (FIRI) is capable
of establishing any of the following links: 0.576 Mbit/s, 1.152 Mbit/s, or 4 Mbit/s half duplex
(using a LED and IR detector).
Chapter 34, “General Power Controller (GPC)” GPC module controls the following Advanced
Power Saving features:DVFS, DPTC, and all of the SRPG modules.
Chapter 35, “General Purpose Input/Output (GPIO)” The General Purpose Input/Output (GPIO)
module provides 32 bits of bidirectional, general-purpose input and output signals.
Chapter 36, “General Purpose Timer (GPT)” The General purpose timer (GPT) has a 32 bit
up-counter. The timer counter value can be captured in a register using an event on an external pin.
The capture trigger can be programmed to be a rising or/and falling edge.
Chapter 37, “Graphics Processing Unit 2D (GPU2D)” The GPU is an embedded 2D and vector
graphics accelerator targeting the OpenVG 1.1 graphics API and feature set. It accelerates 2D
bitmap graphics operations, such as BitBlt, fill and raster operations using a separate 2D graphics
acceleration unit. Vector graphics rendering is accelerated by a separate anti-aliasing polygon
rasterizer, which is connected to the 2D graphics acceleration unit.
Chapter 38, “3D Graphics Accelerator (GPU3D)” The GPU3D (3D graphics processing unit) is
based on the AMD Z430 (also known as ATI Yamato DX). The contains an embedded engine
capable of DirectX9 Shader Model 3.0+ program execution. The module focus is on accelerating
user level graphics APIs such as OpenGL ES 2.0 & 1.1, and Direct3D Mobile 1.2.
Chapter 39, “High Speed Inter IC (HS-I2C)” The High Speed Inter IC (HS-I2C) is bi-directional,
two wire, serial bus interface module. The HS_I2C is designed to be compatible with the standard
Philips I2C bus protocol version 2.1.
Chapter 40, “Inter IC (I2C)” The Inter IC (I2C) module provides functionality of a standard I2C
slave and master. The I2C module is designed to be compatible with the standard Philips I2C bus
protocol.
Chapter 42, “Image Processing Unit 3 (IPUv3EX)” The IPU is part of the video and graphics
subsystem in the i.MX51. It provides comprehensive support for the flow of data from an image
sensor and/or to a display device.
Chapter 43, “Keypad Port (KPP)” The Keypad Port (KPP) is a 16-bit peripheral that can be used
as a keypad matrix interface or as general purpose input/output (I/O).
Chapter 44, “Multi Master Multi Memory Interface (i.MX51)” The Multi-Master Multi Memory
Interface (M4IF) controls memory accesses (read/write/erase/program) from one or more masters
through different port interfaces to different external memory controllers ESDCTL, NFC, and
WEIM, as well as two internal memories in the system as well.
Chapter 45, “NAND Flash Controller (NFC)” Composed of various control logic units, a
4.5-Kbyte internal RAM buffer and an internal ECC mechanism, the NAND Flash Controller
(NFC) implements the interface to standard NAND Flash memory devices.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
IV
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
Chapter 46, “Parallel Advanced Technology Attachment (P-ATA)” The ATA block is an AT
attachment host interface. Its main use is to interface with hard disc drives and optical disc drives.
It interfaces with the ATA device over a number of ATA signals.
Chapter 47, “Pulse-Width Modulator (PWM)” The pulse-width modulator (PWM) has a 16-bit
counter, and is optimized to generate sound from stored sample audio images and it can also
generate tones. It uses 16-bit resolution and a 4 × 16 data FIFO to generate sound.
Chapter 48, “Run-Time Integrity Checker (RTIC)” The Run-Time Integrity Checker (RTIC)
function is to ensure the integrity of the peripheral memory contents, and assist with boot
authentication. The RTIC has the ability to verify the memory contents during system boot and
during run-time execution.
Chapter 49, “Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA)” The
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA) is a security co-processor
that can be used on cell phone baseband processors or wireless PDAs. It implements block
encryption algorithms, (AES, DES, and 3DES), hashing algorithms (MD5, SHA-1, SHA-224, and
SHA-256), stream cipher algorithm (ARC4), and a hardware random number generator.
Chapter 50, “Security Controller (SCC)” The Security Controller (SCC) is composed of two
sub-blocks, secure RAM and a security monitor.
Chapter 51, “Subscriber Identification Module (SIM)” The Subscriber Identification Module
(SIM) is designed to facilitate communication to SIM cards or Eurochip pre-paid phone cards. The
SIM module has two ports that can be used to interface with the various cards.
Chapter 52, “Smart Direct Memory Access (SDMA) Controller” The Smart Direct Memory
Access (SDMA) controller offers highly-competitive DMA features combined with
software-based virtual-DMA flexibility. It enables data transfers between peripheral I/O devices
and internal/external memories.
Chapter 53, “Sony/Philips Digital Interface Transmitter (SPDIF Tx)” The Sony/Philips Digital
Interface Transmitter (SPDIF Tx) audio module is a stereo transmitter that allows the processor to
transmit digital audio over it.
Chapter 56, “Synchronous Serial Interface (SSI)” The SSI is a full-duplex, serial port that allows
the chip to communicate with a variety of serial devices. These serial devices can be standard
CODer-DECoder (CODECs), Digital Signal Processors (DSPs), microprocessors, peripherals, and
popular industry audio CODECs that implement the inter-IC sound bus standard (I2S) and Intel
AC97 standard.
Chapter 58, “TV Encoder (TVE)” The TV Encoder (TVE) is designed to provide direct connection
between an Application Processor (AP) and a TV set via analog interfaces.
Chapter 59, “y Universal Asynchronous Receiver/Transmitter (UART)” The UART supports serial
RS-232 NRZ format, and IrDA.
Chapter 60, “Universal Serial Bus OTG HOST (USBOH3)” The USBOH3 module contains all of
the functionality required to support four independent USB ports which are compatible with the
USB 2.0 specification. Three of the USB host controllers are identical. In addition to the normal
USB functionality, the module also provides support for direct connections to on-board USB
peripherals using serial or ULPI protocol.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
V
•
•
•
•
Chapter 61, “Video Processing Unit (VPU)” Video Processing Unit of the i.MX51 is a high
performance multi-standard video processing unit which can perform H.264 BP/MP/HP, VC-1
SP/MP/AP, MPEG4 SP/ASP, Divx ,RV8/9,and MPEG2 MP decoding up to 1920x1088 resolution.
Chapter 62, “Watchdog Timer (WDOG)” The Watchdog (WDOG) timer module protects against
system failures by providing a method of escaping from unexpected events or programming errors.
Chapter 63, “Wireless External Interface Module (WEIM)” The Wireless External Interface
Module (IPU) handles the interface to devices external to the chip, including generation of chip
selects, clock and control for external peripherals and memory. It provides asynchronous access to
devices with SRAM-like interface and synchronous access to devices with NOR-Flash like or
PSRAM like interface.
Appendix A, “IOMUX Controller (IOMUXC)” The IOMUX controller (IOMUXC), together with
the IOMUX, enables the IC to share one BGA contact with several functional blocks. The sharing
is done by multiplexing the BGA contact input/output signals.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
VI
Freescale Semiconductor
MCIMX51 Reference Manual
Book I
Rev. 1
2/2010
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Book I -2
Freescale Semiconductor
Chapter 1
Introduction
This chapter introduces the architecture of the MCIMX51 (i.MX51) Multimedia Applications Processor.
The i.MX51 processor represents Freescale Semiconductor’s latest achievement in multimedia integrated
applications processors that are part of a growing family of multimedia-focused products offering high
performance processing optimized for lowest power consumption.
A high-level description of features and functionality of the integrated host processor are provided in this
chapter. The different modules are summarized and the interfaces are also described, along with the
respective programming model. Functional operation with emphasis on peripheral functions is also
included.
NOTE
Because the i.MX51 and i.MX51A are functionally identical, all references
to the i.MX51 in this reference manual also apply to the i.MX51A.
1.1
Target Applications
The flexibility of the architecture allows it to be used in a wide variety of applications. Regardless of
whether the customer is designing a smartphone, PDA, gaming console, portable media player (PMP),
portable navigation device (PND), web tablets, or other portable device, the i.MX51 processor provides
design with the power and flexibility necessary for today’s competitive marketplace.
1.2
Features
The i.MX51 processor is based on an ARM Cortex A8™ platform, which has the following features:
• ARM Cortex A8™ Processor (with TrustZone)
• 32 Kbyte L1 Instruction Cache
• 32 Kbyte L1 Data Cache
• 256 Kbyte L2 cache
• Neon coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32 × 64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
— Non-pipelined Vector Floating Point (VFP) co-processor (VFP)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-1
The maximum frequency of the core is:
• 800 MHz (consumer version)
• 600 MHz (automotive and extended temperature version)
See respective data sheet for details about frequency, voltage, and temperature ranges.
To boost the multimedia performance, the following hardware accelerators are integrated:
• VPU—Video Processing Unit
• IPU—Image Processing Unit
• GPU 3D—Graphics Processing Unit (OpenGL ES 2.0)
• GPU 2D—Graphics Processing Unit, 2D (OpenVG 1.1)
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—Secure JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features
• SRTC—Secure Real-Time Clock. Tamper resisted RTC with its own power domain and
mechanism to detects voltage and clock glitches
• RTIC—Real-Time Integrity Checker. RTIC type 1, enhanced with SHA-256 engine
• SAHARA Lite—Cryptographic accelerator that includes true random number generator (TRNG)
• SCC—security controller type 2. Improved SCC with AES engine, Secure/Non-Secure RAM and
support for multiple keys as well as TZ/non-TZ separation
• CSU—Central Security Unit. Enhancement for the IIM. Will be configured during boot and by
e-fuses and will determine the security level operation mode as well as the TZ policy
• A-HAB—Advanced High Assurance Boot – HAB with the next embedded enhancements:
SHA-256, 2048 bit RSA key, version control mechanism, warm boot, CSU and TZ initialization
The memory system consists of the following levels:
• Level 1 Cache
— Instruction (32 Kbyte)
— Data (32 Kbyte)
• Level 2 Cache
— Unified instruction and data (256 Kbyte)
• Level 2 Memory
— Boot ROM, including HAB (36 KB)
— Unified Internal RAM (128 KB), including Secure/Non-Secure RAM. Support flexible
allocation of secure/non-secure, at 8 KB blocks granularity. Controlled by SCC module.
The i.MX51 SoC is built around the following system buses:
• 64-bit AMBA AXI v1.0. It is referenced further as AXI and used by ARM Cortex A8™ Platform,
major multimedia accelerators (VPU, IPUEX), and EMI.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-2
Freescale Semiconductor
•
•
32-bit AMBA AHB 2.0. It is referenced further as AHB and used by most of the bus master
peripherals, such as SDMA, RTIC, SCC etc. (see block diagram for the complete list).
32-bit IP. It is used for control (and slow data traffic) of the most SoC peripheral devices.
The following interfaces are available for external devices (some are muxed and not available
simultaneously):
• Hard Disk Drives
— CE-ATA, up to 416 Mbps
— P-ATA, up to 66 MByte/s
• Displays
— Two display ports, each can drive displays using either (or both) of the following interfaces
– Parallel interface: up to 24-bit data bus, up to 100 MHz
– DSI fast serial interface: up to 2 data lanes, up to 1600 Mbps
— NTSC/PAL TV-Out interface via integrated video encoder.
— Pixel Color depth up to 24-bits
• Camera sensors
— Two camera ports (each can use either parallel or serial interface)
– Parallel Camera sensor (up to 16-bit, peak up to 120 Mpixels/sec)
• Expansion cards
— Four SD/MMC cards , The MMC card supports operation of 416 Mbps in 8-bit mode. The
SD/SDIO supports 1-bit and 4-bit modes up to 200 Mbps.
• External memory interfaces
— 32-bit DDR2, mobile DDR - both with 200 MHz clock
— 8/16-bit NAND SLC/MLC Flash, up to 50 MHz
— 16-bit NOR Flash. 32-bit width is supported in multiplexed Address/Data mode. All WEIM
pins are muxed on other interfaces (data with NFC pins). IO muxing logic selects WEIM port,
as primary muxing at system boot.
— PSRAM, Cellular RAM
— MDOC NAND Flash and OneNAND
— 32-bit is supported in Muxed mode
• USB
— USB 2.0 OTG, up to 480 Mbps
— Integrated High Speed USB Phy
— 3 USB 2.0 Hosts, up to 480 Mbps each
– Only OTG port supports overcurrent and PM signals.
— External HS/FS Transceivers, (ULPI / Serial), at expense of functionality, due to IO muxing
limitations.
• Low-Power Modes (LPM)
— Supporting DVFS and DPTC techniques for low power modes
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-3
—
—
—
—
•
•
•
1.3
Uses SRPG (State Retention Power Gating) for ARM and Neon
Power-gating for VPU, GPU and Save & Restore (S&R) Power gating for IPU.
Partial SRPG of EMI
Support for various levels of system power modes
– Peripherals are divided into 2 groups. One of the groups supports SRPG.
— Flexible clock gating control scheme
Miscellaneous IPs and interfaces:
— 1-Wire
— Three (3) I2S/SSI/AC97, up to 1.4 Mbps each
— Three (3) UART, up to 4.0 Mbps each
– One supports 8-bit and others supports 4-bit.
— One CSPI
— Two eCSPI, up to 52 Mbps each
— One HS-I2C, supports 3.4Mbps1
— Two (2) I2C, supports 400 kbps
— Fast Ethernet Controller, 10/100 Mbps
— Two Pulse Width Modulators (PWM)
— JTAG Controller (SJC)
— GPIO with interrupt capabilities
— Key Pad Port (KPP)
— One SIM, up to 33 Mbps
— Sony Phillips Digital Interface Transmitter (SPDIF)
Watchdog timers
Audio MUX
Architectural Overview
This section contains a simplified block diagram of the i.MX51.
1. Not recommended for use in new designs. See i.MX51 IC errata
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-4
Freescale Semiconductor
1.3.1
Block Diagram
NOR/Nand Battery Ctrl
Device
Flash
DDR
Memory
Digital
Audio
USB
Dev/Host
USB PHY
External
Memory I/F
Camera 1
Camera 2
LCD Display 1
LCD Display 2
TV-Out
Figure 1-1 shows a high-level block diagram of the i.MX51, providing a view of the major subsystems
(processor domains, shared peripherals domain, memories, etc.) and logical connectivity.
ATA HDD
Application Processor Domain (AP)
TV Encoder
Image Processing
Subsystem
USB OTG +
3 HS Ports
AP Peripherals
eCSPI (1 of 2)
CSPI
Ethernet
Smart DMA
(SDMA)
UART (3)
AUDMUX
GPS
Internal
RAM
(128 Kbytes)
SDMA Peripherals
eSDHC (4)
SSI
UART
eCSPI (1 of 2)
SPDIF Tx
Boot
ROM
SIM
P-ATA
RF/IF ICs
Security
SAHARA
Lite
RTIC
AXI and AHB Switch Fabric
SPBA
SCC
ARM Cortex A8
Platform
I2C(2),HSI 2C
ARM Cortex A8
PWM (2)
1-WIRE
Neon and VFP
IIM
L1 I/D cache
IOMUXC
L2 cache
KPP
ETM, CTI0,1
GPIOx32 (4)
SJC
SSI (3)
Video
Proc. Unit
(VPU)
FIRI
FEC
Graphics
Proc. Unit
SRTC
Debug
DAP
CSU
SIM
TPIU
TZIC
Fuse Box
CTI (2)
Graphics
Memory
(128 Kbytes)
Timers
WDOG (2)
Clock and Reset
PLL (3)
Audio/Power
Management
GPT
CCM
EPIT (2)
GPC
SRC
XTALOSC
CAMP (2)
JTAG
IrDA
XVR
Bluetooth
WLAN
USB-OTG
XVR
MMC/SDIO
Keypad
Access.
Conn.
Figure 1-1. i.MX51 Simplified Block Diagram
1.3.2
Major Subsystems
The i.MX51 consists of the following major subsystems:
• Core (ARM Cortex A8™) Platform, L1/L2 memories
• SDMA controller and the shared peripheral domain
• System Control—Boot Flow control, Clocks distribution, “Reset” control and Low Power logic
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-5
•
•
•
•
1.3.3
Multimedia
— Video Processor
— TV-Encoder (TVe-) for PAL/NTSC output
— Image Processor
— Graphics Processors
— Audio—connectivity interfaces in hardware, while codecs are performed in SW by ARM core.
Security
Connectivity peripherals
External Memory Interface
Architectural Partitioning
This paragraph defines how architecture supports the processing intensive tasks:
• ARM Cortex A8™ Platform is responsible for:
— Operating System
— User applications (including control over hardware accelerators and non-accelerated functions)
— TrustZone applications
• Smart DMA enables data transfer between non-mastering peripherals and external or internal
memories
• System Control is supported via:
— Clock Control Block (CCM)
— Three (3×) PLLs
— XTALOSC—Crystal oscillator source support
— Frequency Pre-multiplier (FPM)
— System Reset Controller (SRC)
— Global Power Controller (GPC)
— Two (2×) CAMPs—Clock Amplifier modules on the CKIH1 and CKIH2 inputs
• Multimedia is supported with:
— Image Processing Unit—IPUEX
– Connectivity to displays, display controllers, and auxiliary graphics co-processors
– Display Processing: video/graphics combining, image enhancement
– Image conversions: resizing, rotation/inversion, color conversion
– Synchronization and control capabilities, allowing autonomous operation
— Video Processing Unit (VPU) (Video codecs, all in hardware unless mentioned otherwise):
– MPEG-4 decode: 1280 × 720, 30 fps, Simple Profile and Advanced Simple Profile
– MPEG-4 encode: D1, Simple Profile
– H.263 decode: 1280 × 720, 30 fps, Profile 3
– H.263 encode: D1, Profile 3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-6
Freescale Semiconductor
•
•
– H.264 decode: 1280 × 720, 30 fps, Baseline, Main, and High Profile
– H.264 encode: D1, Baseline Profile
– MPEG-2 decode: 1280 × 720, 30 fps, MP-ML
– MPEG-2 encode: D1, MP-ML (in Software with Partial Acceleration in Hardware)
– VC-1 decode: 1280 × 720, 30 fps, Simple, Main, and Advanced Profile
– DivX decode: 1280 × 720, 30 fps Versions 3, 4, and 5
– RV10 decode: 1280 × 720, 30 fps
– MJPEG decode: 32 MPix/s
– MJPEG encode: 64 Mpix/s
— Graphics Processing Unit (GPU), 3D graphics processing compliant with the following:
– OpenGL ES Common Profile v1.0
– OpenGL ES Common Profile v1.1/Direct3D Mobile
– OpenGL ES Profile v2.0
– OpenVG 1.0
— Graphics Processing Unit (GPU2D), 2D graphics processing
— Audio
– Audio codecs are provided by software, which runs on ARM core
– 3 × SSIs
– Audio Mux
– SPDIF
Security is supported by:
— High Assurance Boot (HAB) System
— ARM TrustZone (TZ) Trusted Execution environment
— IC Identification Module (IIM) and Central Security Unit (CSU)
— On-chip One-Time programmable electrical fuse array (E-Fusebox)
— RTIC: Real-Time Integrity Checker
— SAHARA Lite (SAHARA-Lite) cryptographic acceleration engine
— SJC—Secured JTAG controller
— Secure Real Time Clock (SRTC)
— Security Controller (SCC) with secure RAM
— Tamper Detection
— TrustZone Watchdog (TZ WDOG)
Connectivity peripherals, timers, and External Memory Interface (EMI)
— Low-level communication protocols
— Embedded DMAs
— 3.3-V IO voltage for seamless integration
— USB 2.0 with integrated PHY/Transceiver, Serial FS (requires external transceiver)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-7
—
—
—
—
1.4
Video encoder with NTSC/PAL output
DDR, Nand Flash (MLC 4/8-bit ECC) memory interface via EMI
Timers: 2 × EPIT, GPT, and Watch Dog timer (WDOG)
Miscellaneous connectivity support—I2C, SPI, UART, PWM, and Keypad interface
i.MX51 Modules List
Table 1 lists the modules used by the various subsystems of the i.MX51.
Table 1. i.MX51 Digital and Analog Modules
Block
Mnemonic
1-WIRE
Block Name
1-Wire
Interface
Subsystem
Connectivity
Peripherals
Brief Description
1-Wire support provided for interfacing with an on-board EEPROM, and smart
battery interfaces, for example: Dallas DS2502.
ARM Cortex
A8™
ARM Cortex ARM
A8™ Platform
The ARM Cortex A8™ Core Platform consists of the ARM Cortex A8™
processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains
the Level 2 Cache Controller, 32-Kbyte L1 instruction cache, 32-Kbyte L1 data
cache, and a 256-Kbyte L2 cache. The platform also contains an Event Monitor
and Debug modules. It also has a NEON co-processor with SIMD media
processing architecture, register file with 32 × 64-bit general-purpose registers,
an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating
point execute pipeline (FADD, FMUL), load/store and permute pipeline and a
Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).
Audio
Subsystem
Audio
Subsystem
Multimedia
Peripherals
The elements of the audio subsystem are three Synchronous Serial Interfaces
(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).
See the specific interface listings in this table.
Digital Audio
Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports (three internal and four external) with identical
functionality and programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
AUDMUX
CCM
GPC
SRC
These modules are responsible for clock and reset distribution in the system,
Clock Control Clocks,
and also for system power management. The modules include three PLLs and
Resets, and
Module
Global Power Power Control a Frequency Pre-Multiplier (FPM).
Controller
System Reset
Controller
CSPI-1,
eCSPI-2
eCSPI-3
Configurable
SPI,
Enhanced
CSPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface, with data rate up to
66.5Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave
modes, four chip selects to support multiple peripherals.
CSU
Central
Security Unit
Security
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX51 platform, and for sharing security information
between the various security modules. The Security Control Registers (SCR) of
the CSU are set during boot time by the High Assurance Boot (HAB) code and
are locked to prevent further writing.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-8
Freescale Semiconductor
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
Debug
System
Debug
System
System
Control
The Debug System provides real-time trace debug capability of both instructions
and data. It supports a trace protocol that is an integral part of the ARM Real
Time Debug solution (RealView). Real-time tracing is controlled by specifying a
set of triggering and filtering resources, which include address and data
comparators, cross-system triggers, counters, and sequencers.
EMI
External
Memory
Interface
Connectivity
Peripherals
The EMI is an external and internal memory interface. It performs arbitration
between multi-AXI masters to multi-memory controllers, divided into four major
channels: fast memories (Mobile DDR, DDR2) channel, slow memories
(NOR-FLASH/PSRAM/NAND-FLASH etc.) channel, internal memory (RAM,
ROM) channel and graphical memory (GMEM) Channel.
In order to increase the bandwidth performance, the EMI separates the buffering
and the arbitration between different channels so parallel accesses can occur.
By separating the channels, slow accesses do not interfere with fast accesses.
EMI features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and what
type (Read or Write) was the last access
• Flexible bank interleaving
• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)
• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)
• Supports up to 2 Gbit Mobile DDR memories
• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async
operating modes), at slow frequency, for debugging purposes
• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow
frequencies for debugging purposes
• Supports 4/8-ECC, page sizes of 512 Bytes, 2 KBytes and 4 KBytes
• NAND-Flash (including MLC)
• Multiple chip selects
• Enhanced Mobile DDR memory controller, supporting access latency hiding
• Supports watermarking for security (Internal and external memories)
• Supports Samsung OneNAND™ (only in muxed I/O mode)
Enhanced
Periodic
Interrupt
Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is
enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for division
of input clock frequency to get the required time setting for the interrupts to occur,
and counter values can be programmed on the fly.
EPIT-1
EPIT-2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-9
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
eSDHC-1
eSDHC-2
eSDHC-3
Connectivity
Enhanced
Peripherals
Multi-Media
Card/
Secure Digital
Host
Controller
The features of the eSDHC module, when serving as host, include the following:
• Conforms to SD Host Controller Standard Specification version 2.0
• Compatible with the MMC System Specification version 4.2
• Compatible with the SD Memory Card Specification version 2.0
• Compatible with the SDIO Card Specification version 1.2
• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
Combo, MMC and MMC RS cards
• Configurable to work in one of the following modes:
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
• Full-/high-speed mode
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
eSDHC-4
(muxed with
P-ATA)
Connectivity
Enhanced
Peripherals
Multi-Media
Card/
Secure Digital
Host
Controller
Can be configured as eSDHC (see above) and is muxed with the P-ATA
interface.
FEC
Fast Ethernet Connectivity
Controller
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support both
10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media.
FIRI
Fast
Infra-Red
Interface
Connectivity
Peripherals
Fast Infra-Red Interface
General
Purpose I/O
Modules
System
Control
Peripherals
These modules are used for general purpose input/output to external ICs. Each
GPIO module supports up to 32 bits of I/O.
GPT
General
Purpose
Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event, and can be configured to trigger
a capture event on either the leading or trailing edges of an input pulse. When
the timer is configured to operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with minimal processor
intervention. The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on an external
clock or on an internal clock.
GPU
Graphics
Processing
Unit
Multimedia
Peripherals
The GPU provides hardware acceleration for 2D and 3D graphics
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720
resolution. It supports color representation up to 32 bits per pixel.
The GPU with its 128 KByte memory enables high performance mobile 3D and
2D vector graphics at rates up to 27 Mtriangles/sec, 166 M pixels/sec, 664
Mpixels/sec (Z).
GPIO-1
GPIO-2
GPIO-3
GPIO-4
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-10
Freescale Semiconductor
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
GPU2D
Multimedia
Graphics
Peripherals
Processing
Unit-2D Ver. 1
The GPU2D provides hardware acceleration for 2D graphic
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720 resolution.
I2C-1
I2C-2
HS-I2C
I2C Interface
Connectivity
Peripherals
I2C provides serial interface for controlling peripheral devices. Data rates of up
to 400 Kbps are supported by two of the I2C ports. Data rates of up to 3.4 Mbps
(I2C Specification v2.1) are supported by the HS-I2C.
Note: See the errata for the HS-I2C in the i.MX51 Chip Errata. The two standard
I2C modules have no errata.
IIM
IC
Identification
Module
Security
The IC Identification Module (IIM) provides an interface for reading,
programming, and/or overriding identification and control information stored in
on-chip fuse elements. The module supports electrically programmable poly
fuses (e-Fuses). The IIM also provides a set of volatile software-accessible
signals that can be used for software control of hardware elements not requiring
non-volatility. The IIM provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are unique
chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals requiring permanent
non-volatility. The IIM also provides up to 28 volatile control signals. The IIM
consists of a master controller, a software fuse value shadow cache, and a set
of registers to hold the values of signals visible outside the module.
IOMUX
Control
System
Control
Peripherals
This module enables flexible I/O multiplexing. Each I/O pad has default as well
as several alternate functions. The alternate functions are software configurable.
Image
Processing
Unit
Multimedia
Peripherals
IPU enables connectivity to displays and image sensors, relevant processing
and synchronization. It supports two display ports and two camera ports,
through the following interfaces.
• Legacy Interfaces
• Analog TV interfaces (through a TV encoder bridge)
IOMUXC
IPU
The processing includes:
• Support for camera control
• Image enhancement: color adjustment and gamut mapping, gamma
correction and contrast enhancement, sharpening and noise reduction
• Video/graphics combining
• Support for display backlight reduction
• Image conversion—resizing, rotation, inversion and color space conversion
• Synchronization and control capabilities, allowing autonomous operation.
• Hardware de-interlacing support
KPP
Keypad Port
Connectivity
Peripherals
The KPP supports an 8 × 8 external keypad matrix. The KPP features are as
follows:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-11
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
P-ATA (Muxed Parallel ATA
with
eSDHC-4
Subsystem
Brief Description
Connectivity
Peripherals
The P-ATA block is an AT attachment host interface. Its main use is to interface
with hard disc drives and optical disc drives. It interfaces with the ATA-5
(UDMA-4) compliant device over a number of ATA signals. It is possible to
connect a bus buffer between the host side and the device side. This is muxed
with eSDHC-4 interfaces.
PWM-1
PWM-2
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate tones.
The PWM uses 16-bit resolution and a 4x16 data FIFO to generate sound.
RAM
128 Kbytes
Internal RAM
Internal
Memory
Unified RAM, can be split between Secure RAM and Non-Secure RAM
ROM
36 Kbytes
Boot ROM
Internal
Memory
Supports secure and regular Boot Modes
RTIC
Real Time
Integrity
Checker
Security
Protecting read-only data from modification is one of the basic elements in
trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data
monitoring device responsible for ensuring that memory content is not corrupted
during program execution. The RTICv3 mechanism periodically checks the
integrity of code or data sections during normal OS run-time execution without
interfering with normal operation. The RTICv3’s purpose is to ensure the integrity
of the peripheral memory contents, protect against unauthorized external
memory elements replacement, and assist with boot authentication.
Security
SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a
security co-processor. It implements symmetric encryption algorithms, (AES,
DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1,
SHA-224, and SHA-256), and a hardware random number generator. It has a
slave IP bus interface for the host to write configuration and command
information, and to read status information. It also has a DMA controller, with an
AHB bus interface, to reduce the burden on the host to move the required data
to and from memory.
Security
The Security Controller is a security assurance hardware module designed to
safely hold sensitive data such as encryption keys, digital right management
(DRM) keys, passwords, and biometrics reference data. The SCC monitors the
system’s alert signal to determine if the data paths to and from it are
secure—that is, cannot be accessed from outside of the defined security
perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also
features a Key Encryption Module (KEM) that allows non-volatile (external
memory) storage of any sensitive data that is temporarily not in use. The KEM
utilizes a device-specific hidden secret key and a symmetric cryptographic
algorithm to transform the sensitive data into encrypted data.
SAHARA Lite SAHARA
security
accelerator
Lite
SCC
Security
Controller
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-12
Freescale Semiconductor
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
Smart Direct
Memory
Access
System
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system
performance by off loading various cores in dynamic data routing.
The SDMA features list is as follows:
• Powered by a 16-bit instruction-set micro-RISC engine
• Multi-channel DMA supports up to 32 time-division multiplexed DMA channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM Cortex A8™ and SDMA
• Very fast context-switching with two-level priority-based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement, and
no address changes on source and destination address)
• DMA ports can handle unit-directional and bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers for EMI
• Support of byte-swapping and CRC calculations
• A library of scripts and API are available
SIM
Subscriber
Identity
Module
Interface
Connectivity
Peripherals
The SIM is an asynchronous interface with additional features for allowing
communication with Smart Cards conforming to the ISO 7816 specification. The
SIM is designed to facilitate communication to SIM cards or pre-paid phone
cards.
SJC
Secure JTAG
Interface
System
Control
Peripherals
JTAG manipulation is a known hacker’s method of executing unauthorized
program code, getting control over secure applications, and running code in
privileged modes. The JTAG port provides a debug access to several hardware
blocks including the ARM processor and the system bus.
SDMA
The JTAG port must be accessible during platform initial laboratory bring-up,
manufacturing tests and troubleshooting, as well as for software debugging by
authorized entities. However, in order to properly secure the system,
unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access for manufacturing
tests and software debugging, the i.MX51 processor incorporates a mechanism
for regulating JTAG access. The i.MX51Secure JTAG Controller provides four
different JTAG security modes that can be selected via e-fuse configuration.
SPBA
Shared
Peripheral
Bus Arbiter
System
Control
Peripherals
SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus)
arbiter.
SPDIF
Sony Philips
Digital
Interface
Multimedia
Peripherals
A standard digital audio transmission protocol developed jointly by the Sony and
Philips corporations. Only the transmitter functionality is supported.
SRTC
Secure Real
Time Clock
Security
The SRTC incorporates a special System State Retention Register (SSRR) that
stores system parameters during system shutdown modes. This register and all
SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The
NVCC_SRTC_POW can be energized even if all other supply rails are shut
down. This register is helpful for storing warm boot parameters. The SSRR also
stores the system security state. In case of a security violation, the SSRR mark
the event (security violation indication).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-13
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
SSI-1
Block Name
Subsystem
Brief Description
I2S/SSI/AC97 Connectivity
Interface
Peripherals
The SSI is a full-duplex synchronous interface used on the i.MX51 processor to
provide connectivity with off-chip audio peripherals. The SSI supports a wide
variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to
24 bits per word), and clock/frame sync options.
Each SSI has two pairs of 8x24 FIFOs and hardware support for an external
DMA controller in order to minimize its impact on system performance. The
second pair of FIFOs provides hardware interleaving of a second audio stream,
which reduces CPU overhead in use cases where two timeslots are being used
simultaneously.
TVE
TV Encoder
Multimedia
The TVE is implemented in conjunction with the Image Processing Unit (IPU)
allowing handheld devices to display captured still images and
video directly on a TV or LCD projector. It supports the following analog video
outputs: composite, S-video, and component video up to HD720p/1080i.
TZIC
TrustZone
Aware
Interrupt
Controller
ARM/Control
The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all
i.MX51 sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
UART-1
UART-2
UART-3
UART
Interface
Connectivity
Peripherals
Each of the UART modules supports the following serial data transmit/receive
protocols and configurations:
• 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or
none)
• Programmable baud rates up to 4 MHz. This is a higher max baud rate relative
to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and previous
Freescale UART modules.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB
USB 2.0
High-Speed
OTG and 3x
Hosts
Connectivity
Peripherals
USB-OTG contains one high-speed OTG module, which is internally connected
to the on-chip HS USB PHY. There are an additional three high-speed host
modules that require external USB PHYs.
VPU
Video
Processing
Unit
Multimedia
Peripherals
A high-performing video processing unit (VPU), which covers many SD-level
video decoders and SD-level encoders as a multi-standard video codec engine
as well as several important video processing such as rotation and mirroring.
VPU Features:
• MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile
• MPEG-4 encode: D1, 25/30 fps, simple profile
• H.263 decode: 720p, 30 fps, profile 3
• H.263 encode: D1, 25/30 fps, profile 3
• H.264 decode: 720p, 30 fps, baseline, main, and high profile
• H.264 encode: D1, 25/30 fps, baseline profile
• MPEG-2 decode: 720p, 30 fps, MP-ML
• MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration
in hardware)
• VC-1 decode: 720p, 30 fps, simple, main, and advanced profile
• DivX decode: 720p, 30 fps versions 3, 4, and 5
• RV10 decode: 720p, 30 fps
• MJPEG decode: 32 Mpix/s
• MJPEG encode: 64 Mpix/s
SSI-2
SSI-3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-14
Freescale Semiconductor
Table 1. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
WDOG-1
Watch Dog
Timer
Peripherals
The Watch Dog Timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt to the
ARM core, and a second point evokes an external event on the WDOG line.
WDOG-2
(TZ)
Watch Dog
(TrustZone)
Timer
Peripherals
The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone
starvation by providing a method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the normal OS prevents
switching to the TZ mode. This situation should be avoided, as it can
compromise the system’s security. Once the TZ WDOG module is activated, it
must be serviced by TZ software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped
interrupt that forces switching to the TZ mode. If it is still not served, the TZ
WDOG asserts a security violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal mode SW.
XTALOSC
Crystal
Oscillator I/F
Clocking
The XTALOSC module allows connectivity to an external crystal.
1.5
Frequency Requirements
The i.MX51 datasheet lists the target system frequencies at different voltage conditions.
1.6
Memory Interfaces
The EMI supports the following memory interfaces:
• mDDR, DDR2, 32-bit, 200 MHz clock
• NAND (MLC/SLC) Flash, 8/16-bit, 40 MHz
• OneNAND, 1-2 Kbyte page size
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
1-15
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1-16
Freescale Semiconductor
Chapter 2
Memory Map
This chapter introduces the memory architecture of the i.MX51. The system memory high-level partition
is defined below:
• Level 1 Cache
— Instruction (32-Kbyte)
— Data (32-Kbyte)
• Level 2 Cache
— Unified instruction and data (256 Kbytes)
• Level 2 Memory
— Boot ROM, including HAB (36-Kbyte)
— Unified Internal RAM (128 Kbyte), can be split between Secure and Non-Secure RAM
• External memory interface
— 32-bit mDDR, up to 200 MHz clock
— 32-bit DDR2, up to 200 MHz clock
— 8/16-bit NAND SLC/MLC Flash, up to 40 MHz
— 8/16-bit NOR Flash.
2.1
CPU Memory Map
Table 2-1 shows the system memory map.
NOTE
User must not address reserved memory regions. Access to reserved
memory regions can cause unpredictable behavior.
Table 2-1. i.MX51 System Memory Map
AP
Size
Start Address
Region
End Address
On-Chip Memories (hardware connection via EMI)
0000_0000
0000_8FFF
36K
Boot ROM
0000_9000
1FFD_FFFF
512M (minus 164K)
Reserved for Internal ROM aliasing
1FFE_0000
1FFF_FFFF
128K
SCC RAM
2000_0000
2001_FFFF
128K
Graphics Memory of GPU
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
2-1
Table 2-1. i.MX51 System Memory Map (continued)
AP
Size
Start Address
End Address
2002_0000
2FFF_FFFF
256M (minus 128K)
Region
Reserved
On Chip AHB Accessed IPs
3000_0000
3FFF_FFFF
256M
GPU
4000_0000
5FFF_FFFF
512M
IPUEX
On Chip AHB Accessed IPs—Debug APB
6000_0000
6000_0FFF
4K
Debug ROM
6000_1000
6000_1FFF
4K
ETB
6000_2000
6000_2FFF
4K
ETM
6000_3000
6000_3FFF
4K
TPIU
6000_4000
6000_4FFF
4K
CTI0
6000_5000
6000_5FFF
4K
CTI1
6000_6000
6000_6FFF
4K
CTI2
6000_7000
6000_7FFF
4K
CTI3
6000_8000
6000_8FFF
4K
Cortex Debug Unit
6000_9000
6FFF_FFFF
256M (minus 36K)
Reserved
AIPS_TZ#1
AIPS_TZ#1- SPBA IPs, Mapped to global module enable 0
7000_0000
7000_3FFF
16K
Reserved
7000_4000
7000_7FFF
16K
ESDHC 1
7000_8000
7000_BFFF
16K
ESDHC 2
7000_C000
7000_FFFF
16K
UART 3
7001_0000
7001_3FFF
16K
eCSPI1
7001_4000
7001_7FFF
16K
SSI2
7001_8000
7001_BFFF
16K
Reserved
7001_C000
7001_FFFF
16K
Reserved for SDMA internal registers
7002_0000
7002_3FFF
16K
ESDHC 3
7002_4000
7002_7FFF
16K
ESDHC 4
7002_8000
7002_BFFF
16K
SPDIF
7002_C000
7002_FFFF
16K
Reserved
7003_0000
7003_3FFF
16K
PATA (PORT UDMA)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
2-2
Freescale Semiconductor
Table 2-1. i.MX51 System Memory Map (continued)
AP
Size
Region
Start Address
End Address
7003_4000
7003_7FFF
16K
SLM
7003_8000
7003_BFFF
16K
HSI2C
7003_C000
7003_FFFF
16K
SPBA
AIPS_TZ#1- Global Module Enables
7004_0000
71FF_FFFF
32M (minus 256K)
Reserved AIPS_TZ #1 off platform global module
enable #0
7200_0000
73EF_FFFF
31M
Reserved AIPS_TZ #1 off platform global module
enable #1
AIPS_TZ#1- On Platform
73F0_0000
73F7_FFFF
512K
Reserved AIPS_TZ #1 on platform slots
AIPS_TZ#1- Off Platform
73F8_0000
73F8_3FFF
16K
USBOH3 (PORT USB)
73F8_4000
73F8_7FFF
16K
GPIO1
73F8_8000
73F8_BFFF
16K
GPIO2
73F8_C000
73F8_FFFF
16K
GPIO3
73F9_0000
73F9_3FFF
16K
GPIO4
73F9_4000
73F9_7FFF
16K
KPP
73F9_8000
73F9_BFFF
16K
WDOG1
73F9_C000
73F9_FFFF
16K
WDOG2 (TZ)
73FA_0000
73FA_3FFF
16K
GPT
73FA_4000
73FA_7FFF
16K
SRTC
73FA_8000
73FA_BFFF
16K
IOMUXC
73FA_C000
73FA_FFFF
16K
EPIT1
73FB_0000
73FB_3FFF
16K
EPIT2
73FB_4000
73FB_7FFF
16K
PWM1
73FB_8000
73FB_BFFF
16K
PWM2
73FB_C000
73FB_FFFF
16K
UART 1
73FC_0000
73FC_3FFF
16K
UART 2
73FC_4000
73FC_7FFF
16K
USBOH3 (PORT PL301)
73FC_8000
73FC_BFFF
16K
Reserved
73FC_C000
73FC_FFFF
16K
Reserved
73FD_0000
73FD_3FFF
16K
SRC
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
2-3
Table 2-1. i.MX51 System Memory Map (continued)
AP
Size
Region
Start Address
End Address
73FD_4000
73FD_7FFF
16K
CCM
73FD_8000
73FD_BFFF
16K
GPC
73FD_C000
73FD_FFFF
16K
Reserved
73FE_0000
73FE_3FFF
16K
Reserved
73FE_4000
73FE_7FFF
16K
Reserved
73FE_8000
73FE_BFFF
16K
Reserved
73FE_C000
73FE_FFFF
16K
Reserved
73FF_0000
73FF_3FFF
16K
Reserved
73FF_4000
73FF_FFFF
48K
Reserved AIPS_TZ #1 off platform space.
7400_0000
7FFF_FFFF
448M
Reserved (Aliased to AIPS_TZ#1 slots)
AIPS_TZ#2- Global Module Enables
8000_0000
81FF_FFFF
32M
Reserved AIPS_TZ #1 off platform global module
enable #0
8200_0000
83EF_FFFF
31M
Reserved AIPS_TZ #1 off platform global module
enable #1
AIPS_TZ#2- On Platform
83F0_0000
83F7_FFFF
512K
Reserved AIPS_TZ #2 on platform slots
AIPS_TZ#2- Off Platform
83F8_0000
83F8_3FFF
16K
DPLLIP1
83F8_4000
83F8_7FFF
16K
DPLLIP2
83F8_8000
83F8_BFFF
16K
DPLLIP3
83F8_C000
83F8_FFFF
16K
Reserved
83F9_0000
83F9_3FFF
16K
Reserved
83F9_4000
83F9_7FFF
16K
AHBMAX
83F9_8000
83F9_BFFF
16K
IIM
83F9_C000
83F9_FFFF
16K
CSU
83FA_0000
83FA_3FFF
16K
TIGERP_PLATFORM_NE_32K_256K
83FA_4000
83FA_7FFF
16K
OWIRE
83FA_8000
83FA_BFFF
16K
FIRI
83FA_C000
83FA_FFFF
16K
eCSPI2
83FB_0000
83FB_3FFF
16K
SDMA (port IPS_HOST)
83FB_4000
83FB_7FFF
16K
SCC
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
2-4
Freescale Semiconductor
Table 2-1. i.MX51 System Memory Map (continued)
AP
Size
Region
Start Address
End Address
83FB_8000
83FB_BFFF
16K
ROMCP
83FB_C000
83FB_FFFF
16K
RTIC
83FC_0000
83FC_3FFF
16K
CSPI
83FC_4000
83FC_7FFF
16K
I2C2
83FC_8000
83FC_BFFF
16K
I2C1
83FC_C000
83FC_FFFF
16K
SSI1
83FD_0000
83FD_3FFF
16K
AUDMUX
83FD_4000
83FD_7FFF
16K
Reserved
83FD_8000
83FD_BFFF
16K
EMI1
83FE_0000
83FE_3FFF
16K
PATA (PORT PIO)
83FE_4000
83FE_7FFF
16K
SIM
83FE_8000
83FE_BFFF
16K
SSI3
83FE_C000
83FE_FFFF
16K
FEC
83FF_0000
83FF_3FFF
16K
TVE
83FF_4000
83FF_7FFF
16K
VPU
83FF_8000
83FF_BFFF
16K
SAHARA Lite
83FF_C000
83FF_FFFF
16K
Reserved
8400_0000
8FFF_BFFF
448M (minus 256K)
Reserved (aliased AIPS_TZ #2 slots)
On Chip AHB Accessed IPs
8FFF_C000
8FFF_FFFF
16K
Reserved
Off Chip Memories (HW connection via EMI)
9000_0000
9FFF_FFFF
256M
CSD0 DDR
A000_0000
AFFF_FFFF
256M
CSD1 DDR
B000_0000
B7FF_FFFF
128M
CS0 (Flash) 128M
B800_0000
BFFF_FFFF
128M
CS1 (Flash) 128M
C000_0000
C7FF_FFFF
128M
CS2 (Flash) 128M
C800_0000
CBFF_FFFF
64M
CS3 (Flash) 64MB
CC00_0000
CDFF_FFFF
32M
CS4 (SRAM) 32MB
CE00_0000
CFFE_FFFF
32M (minus 64K)
CS5 (SRAM) 32MB
CFFF_0000
CFFF_FFFF
64K
NAND FLASH (internal buffer)2
On Chip AHB Accessed IPs
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
2-5
Table 2-1. i.MX51 System Memory Map (continued)
AP
Size
Region
Start Address
End Address
D000_0000
DFFF_FFFF
256M
GPU2D (OpenVG)
E000_0000
E000_3FFF
16K
TZIC
ED00_4000
FFFF_FFFF
512M (minus 16K)
Reserved
1
The memory map of M4IF, ESDCTL, WEIM, and NFC is specified in the Section 27.4.1, External/Internal Memory Map, of
Chapter 27, “External Memory Interface (EMI).”
2
Also named as AXI_BASE in Section 45.6.1, Memory Map of Chapter 45, “NAND Flash Controller (NFC).”
2.2
DMA Memory Map
The Smart DMA’s memory map is defined in Table 2-2.
NOTE
User must not address reserved memory regions. Access to reserved
memory regions can produce unpredictable behavior.
Table 2-2. SDMA Peripheral Memory Map
Peripheral
Base Address
Size
Comments
Reserved for SDMA
internal memory
0x0000
4KB
—
ESDHC-1
0x1000
4KB
—
ESDHC-2
0x2000
4KB
—
UART 3
0x3000
4KB
—
eCSPI1
0x4000
4KB
—
SSI2
0x5000
4KB
—
Reserved
0x6000
4KB
Reserved
Reserved for SDMA
internal registers
0x7000
4KB
—
ESDHC-3 (CE-ATA)
0x8000
4KB
—
ESDHC-4
0x9000
4KB
—
SPDIF
0xA000
4KB
—
Reserved
0xB000
4KB
Reserved
PATA
0xC000
4KB
—
Reserved
0xD000
4KB
Reserved
HS-I2C
0xE000
4KB
—
SPBA Registers
0xF000
4KB
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
2-6
Freescale Semiconductor
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
2-7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
2-8
Freescale Semiconductor
Chapter 3
Interrupts and DMA Events
3.1
Overview
This chapter provides information about the assignments of interrupts in Section 3.2, AP Interrupts,” and
about the DMA events in Section 3.3, SDMA Event Mapping.”
3.2
AP Interrupts
The TrustZone interrupt controller (TZIC) collects up to 128 interrupt requests from all i.MX51 sources
and provides an interface to the core. Each interrupt can be configured as a normal or a secure interrupt.
Software force registers and software priority masking are also supported.
Table 3-2 describes the ARM interrupt sources.
Table 3-2. ARM Domain Interrupt Summary
IRQ
Interrupt
Source
0
Reserved
Reserved
1
eSDHC1
Enhanced SDHC Interrupt Request
2
eSDHC2
Enhanced SDHC Interrupt Request
3
eSDHC3
CE-ATA Interrupt Request based on eSDHC-3
4
eSDHC4
Enhanced SDHC Interrupt Request
5
DAP
6
SDMA
“AND” of all 48 interrupts from all the channels
7
IOMUX
POWER FAIL interrupt
8
EMI (NFC)
9
VPU
VPU Interrupt Request
10
IPUEX
IPUEX Error Interrupt
11
IPUEX
IPUEX Sync Interrupt
12
GPU3D
GPU3D Interrupt Request
13
Reserved
Reserved
14
USBOH3
USB Host 1
15
EMI
Interrupt Description
Power-up Request
nfc interrupt out
Consolidated EMI Interrupt
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
3-1
Table 3-2. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Source
16
USBOH3
USB Host 2
17
USBOH3
USB Host 3
18
USBOH3
USB OTG
19
SAHARA
Lite
SAHARA host 0 (TrustZone) Intr
20
SAHARA
Lite
SAHARA host 1 (non-TrustZone) Intr
21
SCC
Security Monitor High Priority Interrupt Request.
22
SCC
Secure (TrustZone) Interrupt Request.
23
SCC
Regular (Non-Secure) Interrupt Request.
24
SRTC
SRTC Consolidated Interrupt. Non TZ.
25
SRTC
SRTC Security Interrupt. TZ.
26
RTIC
RTIC (Trust Zone) Interrupt Request. Indicates that the RTIC has completed hashing the
selected memory block(s) during single-hash/boot mode.
27
CSU
CSU Interrupt Request 1. Indicates to the processor that one or more alarm inputs were
asserted
28
Reserved
29
SSI1
SSI-1 Interrupt Request
30
SSI2
SSI-2 Interrupt Request
31
UART 1
UART-1 ORed interrupt
32
UART 2
UART-2 ORed interrupt
33
UART 3
UART-3 ORed interrupt
34
Reserved
Reserved
35
Reserved
Reserved
36
eCSPI1
eCSPI1 interrupt request line to the core.
37
eCSPI2
eCSPI2 interrupt request line to the core.
38
CSPI
CSPI interrupt request line to the core.
39
GPT
“OR” of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and
3 Interrupt lines
40
EPIT1
EPIT1 output compare interrupt
41
EPIT2
EPIT2 output compare interrupt
42
GPIO1
Active HIGH Interrupt from INT7 from GPIO
43
GPIO1
Active HIGH Interrupt from INT6 from GPIO
44
GPIO1
Active HIGH Interrupt from INT5 from GPIO
Interrupt Description
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
3-2
Freescale Semiconductor
Table 3-2. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Source
45
GPIO1
Active HIGH Interrupt from INT4 from GPIO
46
GPIO1
Active HIGH Interrupt from INT3 from GPIO
47
GPIO1
Active HIGH Interrupt from INT2 from GPIO
48
GPIO1
Active HIGH Interrupt from INT1 from GPIO
49
GPIO1
Active HIGH Interrupt from INT0 from GPIO
50
GPIO1
Combined interrupt indication for GPIO1 signal 0 throughout 15
51
GPIO1
Combined interrupt indication for GPIO1 signal 16 throughout 31
52
GPIO2
Combined interrupt indication for GPIO2 signal 0 throughout 15
53
GPIO2
Combined interrupt indication for GPIO2 signal 16 throughout 31
54
GPIO3
Combined interrupt indication for GPIO3 signal 0 throughout 15
55
GPIO3
Combined interrupt indication for GPIO3 signal 16 throughout 31
56
GPIO4
Combined interrupt indication for GPIO4 signal 0 throughout 15
57
GPIO4
Combined interrupt indication for GPIO4 signal 16 throughout 31
58
WDOG1
Watchdog Timer reset
59
WDOG2
Watchdog Timer reset
60
KPP
61
PWM 1
62
I2C1
I2C-1 Interrupt
63
I2C2
I2C-2 Interrupt
64
HS-I2C
65
Reserved
Reserved
66
Reserved
Reserved
67
SIM
SIM interrupt composed of oef, xte, sdi1, and sdi0
68
SIM
SIM interrupt composed of tc, etc, tfe, and rdrf
69
IIM
Interrupt request to the processor. Indicates to the processor that program or explicit
sense cycle is completed successfully or in case of error. This signal is low-asserted.
70
PATA
Parallel ATA host controller interrupt request
71
CCM
CCM, Interrupt Request 1
72
CCM
CCM, Interrupt Request 2
73
GPC
GPC, Interrupt Request 1
74
GPC
GPC, Interrupt Request 2
75
SRC
SRC interrupt request
Interrupt Description
Keypad Interrupt
Cumulative interrupt line.“OR” of Rollover Interrupt line, Compare Interrupt line and FIFO
Waterlevel crossing interrupt line.
High Speed I2C Interrupt
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
3-3
Table 3-2. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Source
Interrupt Description
76
TIGERP_PLATFORM_ Neon Monitor Interrupt
NE_32K_256K
77
TIGERP_PLATFORM_ Performance Unit Interrupt
NE_32K_256K
78
TIGERP_PLATFORM_ CTI IRQ
NE_32K_256K
79
TIGERP_PLATFORM_ Debug Interrupt, from Cross-Trigger Interface 1
NE_32K_256K
80
TIGERP_PLATFORM_ Debug Interrupt, from Cross-Trigger Interface 1
NE_32K_256K
84
GPU2D
GPU2D (OpenVG) general interrupt
85
GPU2D
GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
86
Reserved
87
FEC
88
OWIRE
89
Reserved
Fast Ethernet Controller Interrupt request (OR of 13 interrupt sources)
1-Wire Interrupt Request
TIGERP_PLATFORM_ Debug Interrupt, from Cross-Trigger Interface 2
NE_32K_256K
90
SJC
—
91
SPDIF
—
92
TVE
—
93
FIRI
94
PWM 2
95
Reserved
96
SSI3
SSI-3 Interrupt Request
97
EMI
Boot sequence completed interrupt
98
FIRI Intr (OR of all 4 interrupt sources)
Cumulative interrupt line.“OR” of Rollover Interrupt line, Compare Interrupt line and FIFO
Waterlevel crossing interrupt line.
Reserved
TIGERP_PLATFORM_ Debug Interrupt, from Cross-Trigger Interface 3
NE_32K_256K
99
Reserved
Reserved
100
VPU
Idle interrupt from VPU (for S/W power gating)
101
EMI
Indicates all pages have been transferred to NFC during an auto program operation.
102
GPU3D
103_128
Reserved
Idle interrupt from GPU3D (for S/W power gating)
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
3-4
Freescale Semiconductor
3.3
SDMA Event Mapping
Table 3-3 shows the DMA request signals for peripherals.
Table 3-3. SDMA Event Mapping
Event
Number
DMA Source
0
VPU
VPU DMA request
1
GPC
Will be used for power management.
2
PATA
Rx FIFO of PATA
3
PATA
Tx FIFO of PATA
4
PATA
PATA Transfer End
5
Reserved
6
eCSPI1
DMA Rx request
7
eCSPI1
DMA Tx request
8
eCSPI2
DMA Rx request
9
eCSPI2
DMA Tx request
10
HS-I2C
HS I2C DMA Tx request
11
HS-I2C
HS I2C DMA Rx request
12
FIRI
DMA request of receiver FIFO
13
FIRI
DMA request of transmitter FIFO
14
IOMUX
External DMA request from BGA contact GPIO1_4
15
IOMUX
External DMA request from BGA contact GPIO1_5
16
UART2
Rx FIFO of UART 2
17
UART2
Tx FIFO of UART 2
18
UART1
Rx FIFO of UART 1
19
UART1
Tx FIFO of UART 1
Description
Reserved
20
esdhc1
I2C1
MMC/SDHC1 muxed with I2C1
21
esdhc2 I2C2
MMC/SDHC2 muxed with I2C2
22
SSI2
SSI #2 receive 2 DMA request
23
SSI2 SLM
SSI #2 transmit 2 DMA request
24
SSI2 SLM
SSI #2 receive 1 DMA request
25
SSI2 SLM
SSI #2 transmit 1 DMA request
26
SSI1
SSI #1 receive 2 DMA request
27
SSI1
SSI #1 transmit 2 DMA request
28
SSI1
SSI #1 receive 1 DMA request
29
SSI1
SSI #1 transmit 1 DMA request
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
3-5
Table 3-3. SDMA Event Mapping (continued)
Event
Number
DMA Source
30
EMI
Asserts every time NFC finishes reading a page
31
CTI2
CTI2 (SDMA_CTI) trigger_out[0] connected to SDMA event.
32
EMI
Asserts at the beginning of auto-program sequence, and every time the NFC finishes
transferring data from the RAM to the NAND (Meaning, the SDMA can write to the RAM the
next page).
33
CTI2
CTI2 (SDMA_CTI) trigger_out[1] connected to SDMA event.
34
EPIT2
EPIT2 DMA request
35
SSI3 SLM
36
IPUEX
37
SSI3 SLM
38
CSPI
DMA Rx request
39
CSPI
DMA Tx request
40
eSDHC3
MMC/SDHC3 DMA request
41
eSDHC4
MMC/SDHC4 DMA request
42
Reserved
Reserved
43
UART3
Rx FIFO of UART 3
44
UART3
Tx FIFO of UART 3
45
SPDIF
SPDIF DMA request
46
SSI3 SLM
SSI #3 receive 1 DMA request
47
SSI3 SLM
SSI #3 transmit 1 DMA request
Description
SSI #3 receive 2 DMA request
IPUEX DMA request
SSI #3 transmit 2 DMA request
As shown in the table, some of the events are an output of a mux of two signals or triggers. The select of
this mux is controlled by general purpose register 0 in IOMUXC.
For other shared connectivity peripherals that do not have dedicated DMA request signals, the AP interrupt
service routines have the option of programming the SDMA to move data between the peripheral and
memory.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
3-6
Freescale Semiconductor
Chapter 4
External Signals and Pin Multiplexing
Because the IC has a limited number of pins, most pins have multiple signal options. The input-output
multiplexer (IOMUX) controls the pin multiplexing. The IOMUX also configures other pin
characteristics, such as voltage level, drive strength, and hysteresis.
4.1
External Signals
Table 4-1 shows the external signals of the i.MX51. Table 4-2 shows an additional view of external signals
muxing. It presents the muxing options per module/instance. Table 4-3 shows IOMUX daisy chain
settings.
4.1.1
I/O Configuration Parameters
In the Pad Settings column, each I/O configuration parameter uses one of the two following notations:
• A CFG (value) notation, where ‘value’ is High, Disabled, Keep, and others. The CFG notation
indicates the parameter is configurable using the SW_PAD_CTL_PAD and SW_PAD_CTL_GRP
registers of Appendix A, “IOMUX Controller (IOMUXC).” The value shown is the default setting,
and the associated bits are shown in Appendix A, “IOMUX Controller (IOMUXC).”
• A value notation (with no CFG indicator) where ‘value’ is High, Disabled, Keep, and others
indicates the parameter is not configurable. The value shown is the default setting. However, the
associated bits shown in Appendix A, “IOMUX Controller (IOMUXC),” below the gray
bit-location boxes (read-only) are simply the values read from that particular location and do not
reflect the actual functional default.
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations
Pad Name
EIM_DA0
Mode
Instance
Port
ALT0
emi
EIM_DA[0]
ALT1
tpiu
TRACE[16]
Pad Settings
Drive Strength—CFG (High)
Hyst. Enable—Disabled
Pull/ Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—Regular
Open Drain Enable—Disabled
Pull/ Keep Enable—CFG (Enabled)
Slew Rate—CFG (FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-1
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_DA1
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA5
Mode
Instance
Port
ALT0
emi
EIM_DA[1]
ALT1
tpiu
TRACE[17]
ALT0
emi
EIM_DA[2]
ALT1
tpiu
TRACE[18]
ALT0
emi
EIM_DA[3]
ALT1
tpiu
TRACE[19]
ALT0
emi
EIM_DA[4]
ALT1
tpiu
TRACE[20]
ALT0
emi
EIM_DA[5]
ALT1
tpiu
TRACE[21]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/ Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/ Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-2
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_DA6
EIM_DA7
EIM_DA8
EIM_DA9
EIM_DA10
Mode
Instance
Port
ALT0
emi
EIM_DA[6]
ALT1
tpiu
TRACE[22]
ALT0
emi
EIM_DA[7]
ALT1
tpiu
TRACE[23]
ALT0
emi
EIM_DA[8]
ALT1
tpiu
TRACE[24]
ALT0
emi
EIM_DA[9]
ALT1
tpiu
TRACE[25]
ALT0
emi
EIM_DA[10]
ALT1
tpiu
TRACE[26]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-3
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_DA11
EIM_DA12
EIM_DA13
EIM_DA14
EIM_DA15
Mode
Instance
Port
ALT0
emi
EIM_DA[11]
ALT1
tpiu
TRACE[27]
ALT0
emi
EIM_DA[12]
ALT1
tpiu
TRACE[28]
ALT0
emi
EIM_DA[13]
ALT1
tpiu
TRACE[29]
ALT0
emi
EIM_DA[14]
ALT1
tpiu
TRACE[30]
ALT0
emi
EIM_DA[15]
ALT1
tpiu
TRACE[31]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-4
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_D16
EIM_D17
EIM_D18
EIM_D19
Mode
Instance
Port
ALT0
emi
WEIM_D[16]
ALT1
gpio2
GPIO[0]
ALT2
usboh3
USBH2_DATA0
ALT3
uart2
CTS
ALT4
i2c1
SDA
ALT5
audmux
AUD4_RXFS
ALT6
tpiu
TRACE[0]
ALT7
audmux
AUD5_TXD
ALT0
emi
WEIM_D[17]
ALT1
gpio2
GPIO[1]
ALT2
usboh3
USBH2_DATA1
ALT3
uart2
RXD_MUX
ALT4
uart3
CTS
ALT5
ipu
SISG[4]
ALT6
tpiu
TRACE[1]
ALT7
audmux
AUD5_RXD
ALT0
emi
WEIM_D[18]
ALT1
gpio2
GPIO[2]
ALT2
usboh3
USBH2_DATA2
ALT3
uart2
TXD_MUX
ALT4
uart3
RTS
ALT5
ipu
SISG[5]
ALT6
tpiu
TRACE[2]
ALT7
audmux
AUD5_TXC
ALT0
emi
WEIM_D[19]
ALT1
gpio2
GPIO[3]
ALT2
usboh3
USBH2_DATA3
ALT3
uart2
RTS
ALT4
i2c1
SCL
ALT5
audmux
AUD4_RXC
ALT6
tpiu
TRACE[3]
ALT7
audmux
AUD5_TXFS
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-5
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_D20
EIM_D21
EIM_D22
EIM_D23
Mode
Instance
Port
Pad Settings
ALT0
emi
WEIM_D[20]
ALT1
gpio2
ALT2
usboh3
ALT3
csu
ALT4
srtc
ALT5
audmux
ALT6
tpiu
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
GPIO[4]
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
USBH2_DATA4
Strength mode—4_level
CSU_INT_DEB
dse test—regular
Open Drain Enable—Disabled
SRTC_ALARM_DEB
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
AUD4_TXD
test_ts—Disabled
TRACE[4]
ALT7
usbphy
TXREADY
ALT0
emi
WEIM_D[21]
ALT1
gpio2
ALT2
usboh3
ALT3
srtc
ALT5
audmux
ALT6
tpiu
ALT7
usbphy
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
GPIO[5]
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
USBH2_DATA5
Strength mode—4_level
SRTC_ALARM_DEB dse test—regular
Open Drain Enable—Disabled
AUD4_RXD
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
TRACE[5]
test_ts—Disabled
RXVALID
ALT0
emi
WEIM_D[22]
ALT1
gpio2
GPIO[6]
ALT2
usboh3
USBH2_DATA6
ALT3
scc
FAIL_STATE
ALT5
audmux
AUD4_TXC
ALT6
tpiu
TRACE[6]
ALT7
usbphy
RXACTIVE
ALT0
emi
WEIM_D[23]
ALT1
gpio2
GPIO[7]
ALT2
usboh3
USBH2_DATA7
ALT3
scc
SEC_STATE
ALT4
spdif
OUT1
ALT5
audmux
AUD4_TXFS
ALT6
tpiu
TRACE[7]
ALT7
usbphy
RXERROR
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-6
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_D24
EIM_D25
EIM_D26
EIM_D27
Mode
Instance
Port
ALT0
emi
WEIM_D[24]
ALT1
gpio2
GPIO[8]
ALT2
usboh3
USBOTG_DATA0
ALT3
uart3
CTS
ALT4
i2c2
SDA
ALT5
audmux
AUD6_RXFS
ALT6
tpiu
TRACE[8]
ALT7
usbphy
SIECLOCK
ALT0
emi
WEIM_D[25]
ALT1
kpp
COL[6]
ALT2
usboh3
USBOTG_DATA1
ALT3
uart3
RXD_MUX
ALT4
uart2
CTS
ALT5
gpt
CMPOUT1
ALT6
tpiu
TRACE[9]
ALT7
usbphy
VBUSVALID
ALT0
emi
WEIM_D[26]
ALT1
kpp
COL[7]
ALT2
usboh3
USBOTG_DATA2
ALT3
uart3
TXD_MUX
ALT4
uart2
RTS
ALT5
gpt
CMPOUT2
ALT6
tpiu
TRACE[10]
ALT7
usbphy
AVALID
ALT0
emi
WEIM_D[27]
ALT1
gpio2
GPIO[9]
ALT2
usboh3
USBOTG_DATA3
ALT3
uart3
RTS
ALT4
i2c2
SCL
ALT5
audmux
AUD6_RXC
ALT6
tpiu
TRACE[11]
ALT7
usbphy
BVALID
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-7
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_D28
EIM_D29
EIM_D30
Mode
Instance
Port
ALT0
emi
WEIM_D[28]
ALT1
kpp
ROW[4]
ALT2
usboh3
USBOTG_DATA4
ALT3
elvis_observe OBSRV_INT_OUT0
_mux
ALT4
ipu
SISG[0]
ALT5
audmux
AUD6_TXD
ALT6
tpiu
TRACE[12]
ALT7
usbphy
ENDSESSION
ALT0
emi
WEIM_D[29]
ALT1
kpp
ROW[5]
ALT2
usboh3
USBOTG_DATA5
ALT3
elvis_observe OBSRV_INT_OUT1
_mux
ALT4
ipu
SISG[1]
ALT5
audmux
AUD6_RXD
ALT6
tpiu
TRACE[13]
ALT7
usbphy
IDDIG
ALT0
emi
WEIM_D[30]
ALT1
kpp
ROW[6]
ALT2
usboh3
USBOTG_DATA6
ALT3
elvis_observe OBSRV_INT_OUT2
_mux
ALT4
ipu
SISG[2]
ALT5
audmux
AUD6_TXC
ALT6
tpiu
TRACE[14]
ALT7
usbphy
HOSTDISCONNECT
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-8
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_D31
EIM_A16
Mode
Instance
ALT0
emi
WEIM_D[31]
ALT1
kpp
ROW[7]
ALT2
usboh3
USBOTG_DATA7
ALT3
elvis_observe OBSRV_INT_OUT3
_mux
ALT4
ipu
SISG[3]
ALT5
audmux
AUD6_TXFS
ALT6
tpiu
TRACE[15]
ALT0
emi
EIM_A[16]
ALT1
gpio2
GPIO[10]
ALT2
EIM_A17
EIM_A17
EIM_A18
Port
—
DATA_HS_OUT[0]
ALT7
src
OSC_FREQ_SEL[0]
ALT0
emi
EIM_A[17]
ALT1
gpio2
GPIO[11]
ALT2
—
DATA_HS_OUT[1]
ALT7
src
OSC_FREQ_SEL[1]
ALT0
emi
EIM_A[18]
ALT1
gpio2
GPIO[12]
ALT2
—
DATA_HS_OUT[2]
ALT7
src
BT_LPB[0]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-9
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_A19
EIM_A20
EIM_A20
EIM_A21
EIM_A22
EIM_A23
EIM_A23
Mode
Instance
Port
ALT0
emi
EIM_A[19]
ALT1
gpio2
GPIO[13]
ALT2
—
DATA_HS_OUT[3]
ALT7
src
BT_LPB[1]
ALT0
emi
EIM_A[20]
ALT1
gpio2
GPIO[14]
ALT2
—
DATA_HS_OUT[4]
ALT7
src
BT_UART_SRC[0]
ALT0
emi
EIM_A[21]
ALT1
gpio2
GPIO[15]
ALT2
—
DATA_HS_OUT[5]
ALT7
src
BT_UART_SRC[1]
ALT0
emi
EIM_A[22]
ALT1
gpio2
GPIO[16]
ALT2
—
DATA_HS_OUT[6]
ALT0
emi
EIM_A[23]
ALT1
gpio2
GPIO[17]
ALT2
—
DATA_HS_OUT[7]
ALT7
src
BT_HPN_EN
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-10
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_A24
EIM_A25
EIM_A25
EIM_A26
EIM_A27
Mode
Instance
Port
ALT0
emi
EIM_A[24]
ALT1
gpio2
GPIO[18]
ALT2
usboh3
USBH2_CLK
ALT0
emi
EIM_A[25]
ALT1
gpio2
GPIO[19]
ALT2
usboh3
USBH2_DIR
ALT6
ipu
DI1_PIN4
ALT0
emi
EIM_A[26]
ALT1
gpio2
GPIO[20]
ALT2
usboh3
USBH2_STP
ALT4
ipu
SISG[0]
ALT5
—
CSI1_DATA_EN
ALT6
ccm
DI2_EXT_CLK
ALT0
emi
EIM_A[27]
ALT1
gpio2
GPIO[21]
ALT2
usboh3
USBH2_NXT
ALT3
elvis_observe OBSRV_INT_OUT4
_mux
ALT4
ipu
SISG[1]
ALT5
—
CSI2_DATA_EN
ALT6
—
DI1_PIN1
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-11
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_EB0
EIM_EB1
EIM_EB2
EIM_EB3
Mode
Instance
Port
ALT0
emi
EIM_EB[0]
ALT2
—
DETECT_D
ALT0
emi
EIM_EB[1]
ALT2
—
DELAY_D
ALT0
emi
EIM_EB[2]
ALT1
gpio2
GPIO[22]
ALT2
tpiu
TRCTL
ALT3
fec
MDIO
ALT4
ipu
SISG[2]
ALT5
—
CSI1_D[2]
ALT6
audmux
AUD5_RXFS
ALT7
gpt
CMPOUT1
ALT0
emi
EIM_EB[3]
ALT1
gpio2
GPIO[23]
ALT2
tpiu
TRCLK
ALT3
fec
RDATA[1]
ALT4
ipu
SISG[3]
ALT5
—
CSI1_D[3]
ALT6
audmux
AUD5_RXC
ALT7
gpt
CMPOUT2
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-12
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_OE
EIM_CS0
EIM_CS1
EIM_CS2
EIM_CS2
Mode
Instance
Port
ALT0
emi
EIM_OE
ALT1
gpio2
GPIO[24]
ALT0
emi
EIM_CS0
ALT1
gpio2
GPIO[25]
ALT0
emi
EIM_CS1
ALT1
gpio2
GPIO[26]
ALT4
ipu
SISG[4]
ALT0
emi
EIM_CS2
ALT1
gpio2
GPIO[27]
ALT2
usboh3
USBOTG_STP
ALT3
fec
RDATA[2]
ALT4
ipu
SISG[5]
ALT5
—
CSI1_D[4]
ALT6
audmux
AUD5_TXD
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-13
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
EIM_CS3
EIM_CS4
EIM_CS5
EIM_DTACK
Mode
Instance
Port
ALT0
emi
EIM_CS3
ALT1
gpio2
GPIO[28]
ALT2
usboh3
USBOTG_NXT
ALT3
fec
RDATA[3]
ALT4
ccm
SSI_EXT2_CLK
ALT5
—
CSI1_D[5]
ALT6
audmux
AUD5_RXD
ALT0
emi
EIM_CS4
ALT1
gpio2
GPIO[29]
ALT2
usboh3
USBOTG_CLK
ALT3
fec
RX_ER
ALT4
ccm
SSI_EXT1_CLK
ALT5
—
CSI1_D[6]
ALT6
audmux
AUD5_TXC
ALT0
emi
EIM_CS5
ALT1
gpio2
GPIO[30]
ALT2
usboh3
USBOTG_DIR
ALT3
fec
CRS
ALT4
ccm
DI1_EXT_CLK
ALT5
—
CSI1_D[7]
ALT6
audmux
AUD5_TXFS
ALT0
emi
WEIM_DTACK_B
ALT1
gpio2
GPIO[31]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-14
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
Mode
Instance
Port
Pad Settings
EIM_WAIT
No Muxing
(ALT0)
emi
EIM_WAIT
Drive Strength—Low
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
EIM_LBA
ALT0
emi
EIM_LBA
ALT1
gpio3
GPIO[1]
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
EIM_BCLK
No Muxing
(ALT0)
emi
EIM_BCLK
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
EIM_RW
No Muxing
(ALT0)
emi
EIM_RW
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
EIM_CRE
ALT0
emi
EIM_CRE
—
ALT1
gpio3
GPIO[2]
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-15
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
Mode
Instance
Port
No Muxing
(ALT0)
emi
DRAM_A[0]
emi
DRAM_A[1]
No Muxing
(ALT0)
emi
DRAM_A[2]
emi
DRAM_A[3]
No Muxing
(ALT0)
emi
DRAM_A[4]
emi
DRAM_A[5]
No Muxing
(ALT0)
emi
DRAM_A[6]
emi
DRAM_A[7]
No Muxing
(ALT0)
emi
DRAM_A[8]
emi
DRAM_A[9]
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-16
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
EIM_SDBA1
EIM_SDBA0
DRAM_RAS
DRAM_CAS
DRAM_SDWE
Mode
No Muxing
(ALT0)
Instance
Port
emi
DRAM_A[10]
emi
DRAM_A[11]
emi
DRAM_A[12]
emi
DRAM_A[13]
No Muxing
(ALT0)
emi
DRAM_A[14]
emi
DRAM_SDBA[1]
No Muxing
(ALT0)
emi
DRAM_SDBA[0]
emi
DRAM_RAS
emi
DRAM_CAS
emi
DRAM_SDWE
No Muxing
(ALT0)
No Muxing
(ALT0)
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-17
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_SDCKE0
Mode
Instance
Port
Pad Settings
No Muxing
(ALT0)
emi
DRAM_SDCKE[0]
emi
DRAM_SDCKE[1]
No Muxing
(ALT0)
emi
DRAM_SDCLK
Drive Strength—CFG(High)
Hyst. Enable—NA
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_SDCLK_B
emi
DRAM_SDCLK_B
Drive Strength—Low
Hyst. Enable—NA
Pull/Keep Select—NA
Pull Up/ Down Config.—NA
dse test—regular
Pull/Keep Enable—NA
Slew Rate—NA
test_ts—Disabled
DRAM_SDQS0
emi
DRAM_SDQS[0]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PD)
dse test—regular
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_SDCKE1
DRAM_SDCLK
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-18
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_SDQS0_B
Mode
Port
Pad Settings
emi
DRAM_SDQS_B[0]
Drive Strength—NA
Hyst. Enable—NA
Pull/Keep Select—NA
Pull Up/ Down Config.—NA
dse test—NA
Pull/Keep Enable—NA
Slew Rate—NA
test_ts—Disabled
DRAM_SDQS1
emi
DRAM_SDQS[1]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PD)
dse test—regular
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_SDQS1_B
emi
DRAM_SDQS_B[1]
Drive Strength—NA
Hyst. Enable—NA
Pull/Keep Select—NA
Pull Up/ Down Config.—NA
dse test—NA
Pull/Keep Enable—NA
Slew Rate—NA
test_ts—Disabled
emi
DRAM_SDQS[2]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PD)
dse test—regular
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_SDQS2_B
emi
DRAM_SDQS_B[2]
Drive Strength—NA
Hyst. Enable—NA
Pull/Keep Select—NA
Pull Up/ Down Config.—NA
dse test—NA
Pull/Keep Enable—NA
Slew Rate—NA
test_ts—Disabled
DRAM_SDQS3
emi
DRAM_SDQS[3]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PD)
dse test—regular
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_SDQS2
No Muxing
(ALT0)
Instance
No Muxing
(ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-19
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_SDQS3_B
Mode
No Muxing
(ALT0)
Instance
Port
Pad Settings
emi
DRAM_SDQS_B[3]
Drive Strength—NA
Hyst. Enable—NA
Pull/Keep Select—NA
Pull Up/ Down Config.—NA
dse test—NA
Pull/Keep Enable—NA
Slew Rate—NA
test_ts—Disabled
emi
DRAM_CS0
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT0
emi
DRAM_CS1
ALT1
ccm
CLKO
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—Controlled by the DRAM_CS0 SRE
bit.
test_ts—Disabled
DRAM_D0
No Muxing
(ALT0)
emi
DRAM_D[0]
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_D1
No Muxing
(ALT0)
emi
DRAM_D[1]
emi
DRAM_D[2]
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_CS0
DRAM_CS1
DRAM_D2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-20
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
Mode
Instance
Port
No Muxing
(ALT0)
emi
DRAM_D[3]
emi
DRAM_D[4]
No Muxing
(ALT0)
emi
DRAM_D[5]
emi
DRAM_D[6]
No Muxing
(ALT0)
emi
DRAM_D[7]
emi
DRAM_D[8]
No Muxing
(ALT0)
emi
DRAM_D[9]
emi
DRAM_D[10]
emi
DRAM_D[11]
emi
DRAM_D[12]
No Muxing
(ALT0)
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-21
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
Mode
No Muxing
(ALT0)
No Muxing
(ALT0)
No Muxing
(ALT0)
No Muxing
(ALT0)
No Muxing
(ALT0)
Instance
Port
emi
DRAM_D[13]
emi
DRAM_D[14]
emi
DRAM_D[15]
emi
DRAM_D[16]
emi
DRAM_D[17]
emi
DRAM_D[18]
emi
DRAM_D[19]
emi
DRAM_D[20]
emi
DRAM_D[21]
emi
DRAM_D[22]
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-22
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_D23
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
Mode
No Muxing
(ALT0)
No Muxing
(ALT0)
No Muxing
(ALT0)
No Muxing
(ALT0)
Instance
Port
emi
DRAM_D[23]
emi
DRAM_D[24]
emi
DRAM_D[25]
emi
DRAM_D[26]
emi
DRAM_D[27]
emi
DRAM_D[28]
emi
DRAM_D[29]
emi
DRAM_D[30]
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-23
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DRAM_D31
Mode
No Muxing
(ALT0)
Instance
Port
Pad Settings
emi
DRAM_D[31]
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—CFG(50Ohm)
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
emi
DRAM_DQM[0]
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
No Muxing
(ALT0)
emi
DRAM_DQM[1]
emi
DRAM_DQM[2]
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DRAM_DQM3
No Muxing
(ALT0)
emi
DRAM_DQM[3]
NANDF_WE_B
ALT0
emi
NANDF_WE_B
ALT1
pata
ALT2
esdhc3
ALT3
gpio3
ALT4
sdma
DRAM_DQM0
DRAM_DQM1
DRAM_DQM2
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
DIOW
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
DAT0
Pull Up/ Down Config.—CFG(47 KΩ PU)
GPIO[3]
dse test—regular
Open Drain Enable—Disabled
DEBUG_EVT_CHN_
Pull/Keep Enable—CFG(Enabled)
LINES[0]
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-24
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_RE_B
Mode
Instance
Port
ALT0
emi
ALT1
pata
ALT2
esdhc3
ALT3
gpio3
ALT4
sdma
ALT0
emi
ALT1
pata
ALT3
gpio3
NANDF_ALE
ALT4
sdma
NANDF_CLE
ALT0
emi
ALT1
pata
ALT3
gpio3
ALT4
sdma
ALT0
emi
ALT1
pata
ALT2
esdhc3
ALT3
gpio3
ALT4
sdma
ALT0
emi
NANDF_RB0
ALT1
pata
DMARQ
ALT2
esdhc3
DAT3
ALT3
gpio3
GPIO[8]
ALT4
sdma
DEBUG_EVENT_C
HANNEL[4]
ALT5
ecspi2
SS1
NANDF_ALE
NANDF_WP_B
NANDF_WP_B
NANDF_RB0
Pad Settings
NANDF_RE_B
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
DIOR
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
DAT1
Pull Up/ Down Config.—CFG(47 KΩ PU)
GPIO[4]
dse test—regular
Open Drain Enable—Disabled
DEBUG_EVT_CHN_
Pull/Keep Enable—CFG(Enabled)
LINES[1]
test_ts—Disabled
NANDF_ALE
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
BUFFER_EN
Hyst. Enable—Disabled
Pull/Keep Select—Keep
GPIO[5]
Pull Up/ Down Config.—100 KΩ PU
DEBUG_EVT_CHN_ dse test—regular
LINES[2]
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
NANDF_CLE
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
PATA_RESET_B
Hyst. Enable—Disabled
Pull/Keep Select—Keep
GPIO[6]
Pull Up/ Down Config.—100 KΩ PU
DEBUG_EVT_CHN_ dse test—regular
LINES[3]
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
NANDF_WP_B
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
DMACK
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
DAT2
Pull Up/ Down Config.—CFG(100 KΩ PU)
GPIO[7]
dse test—regular
Open Drain Enable—Disabled
DEBUG_EVT_CHN_
Pull/Keep Enable—CFG(Enabled)
LINES[4]
test_ts—Disabled
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-25
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_RB1
Mode
Instance
Port
ALT0
emi
NANDF_RB1
ALT1
pata
IORDY
ALT2
ecspi2
RDY
ALT3
gpio3
GPIO[9]
ALT4
gpt
CMPOUT2
ALT5
esdhc4
CMD
ALT6
cspi
MOSI
NANDF_RB2
ALT0
emi
NANDF_RB2
NANDF_RB2
ALT1
fec
COL
ALT2
ecspi2
SCLK
ALT3
gpio3
GPIO[10]
ALT4
gpt
CMPOUT3
ALT5
—
DI2_WAIT
ALT6
usboh3
USBH3_NXT
ALT7
usboh3
H3_DP
ALT0
emi
NANDF_RB3
ALT1
fec
RX_CLK
ALT2
ecspi2
MISO
ALT3
gpio3
GPIO[11]
ALT4
dpllip1
TOG_EN
ALT5
—
DI1_WAIT
ALT6
usboh3
USBH3_CLK
ALT7
usboh3
H3_DM
No Muxing
(ALT0)
emi
DRAM_SDBA[2]
emi
DRAM_ODT1
NANDF_RB3
EIM_SDBA2
EIM_SDODT1
Pad Settings
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-26
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
Mode
Instance
Port
Pad Settings
EIM_SDODT0
No Muxing
(ALT0)
emi
DRAM_ODT0
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
odt—NA
Pull Up/ Down Config.—CFG(100 KΩ PU)
DDR / CMOS Input Mode—CFG(CMOS)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
GPIO_NAND
ALT0
gpio3
GPIO[12]
ALT1
pata
INTRQ
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
ALT0
emi
NANDF_CS0
ALT3
gpio3
GPIO[16]
ALT0
emi
NANDF_CS1
ALT3
gpio3
GPIO[17]
ALT4
sdma
DEBUG_EVENT_C
HANNEL[5]
ALT0
emi
NANDF_CS2
ALT1
pata
ALT2
fec
ALT3
gpio3
ALT4
sdma
ALT5
esdhc4
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
CS_0
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
TX_ER
Pull Up/ Down Config.—CFG(100 KΩ PU)
GPIO[18]
dse test—regular
Open Drain Enable—CFG(Disabled)
DEBUG_EVT_CHN_
Pull/Keep Enable—CFG(Enabled)
LINES[5]
test_ts—Disabled
CLK
ALT6
cspi
SCLK
ALT7
usboh3
H1_DP
NANDF_CS0
NANDF_CS1
NANDF_CS2
Drive Strength—CFG(High)
low/high output voltage—NA
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—NA
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-27
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_CS3
NANDF_CS4
NANDF_CS5
Mode
Instance
Port
Pad Settings
ALT0
emi
NANDF_CS3
ALT1
pata
ALT2
fec
ALT3
gpio3
ALT4
sdma
ALT5
esdhc4
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
CS_1
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
MDC
Pull Up/ Down Config.—CFG(100 KΩ PU)
GPIO[19]
dse test—regular
Open Drain Enable—CFG(Disabled)
DEBUG_EVT_CHN_
Pull/Keep Enable—CFG(Enabled)
LINES[6]
test_ts—Disabled
DAT0
ALT6
sim
PD0
ALT7
usboh3
H1_DM
ALT0
emi
NANDF_CS4
ALT1
pata
ALT2
fec
ALT3
gpio3
ALT4
sdma
ALT5
esdhc4
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
DA_0
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
TDATA[1]
Pull Up/ Down Config.—CFG(47 KΩ PU)
GPIO[20]
dse test—regular
Open Drain Enable—Disabled
DEBUG_EVT_CHN_
Pull/Keep Enable—CFG(Enabled)
LINES[7]
test_ts—Disabled
DAT1
ALT6
sim
CLK0
ALT7
usboh3
USBH3_STP
ALT0
emi
NANDF_CS5
ALT1
pata
DA_1
ALT2
fec
TDATA[2]
ALT3
gpio3
GPIO[21]
ALT4
sdma
DEBUG_EVENT_C
HANNEL[0]
ALT5
esdhc4
DAT2
ALT6
sim
RST0
ALT7
usboh3
USBH3_DIR
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-28
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_CS6
NANDF_CS7
NANDF_RDY_INT
NANDF_RDY_INT
NANDF_D15
Mode
Instance
Port
ALT0
emi
NANDF_CS6
ALT1
pata
DA_2
ALT2
fec
TDATA[3]
ALT3
gpio3
GPIO[22]
ALT4
sdma
DEBUG_EVENT_C
HANNEL[1]
ALT5
esdhc4
DAT3
ALT6
sim
VEN0
ALT7
cspi
SS3
ALT0
emi
NANDF_CS7
ALT1
fec
TX_EN
ALT3
gpio3
GPIO[23]
ALT4
sdma
DEBUG_EVENT_C
HANNEL[2]
ALT5
esdhc3
CLK
ALT6
sim
TX0
ALT0
emi
RDY
ALT1
fec
TX_CLK
ALT2
ecspi2
SS0
ALT3
gpio3
GPIO[24]
ALT4
sdma
DEBUG_EVENT_C
HANNEL[3]
ALT5
esdhc3
CMD
ALT6
sim
RX0
ALT0
emi
EIM_NFC_D[15]
ALT1
pata
PATA_DATA[15]
ALT2
ecspi2
MOSI
ALT3
gpio3
GPIO[25]
ALT4
sdma
DEBUG_PC[0]
ALT5
esdhc3
DAT7
ALT6
ipu
IPU_DIAG_BUS[0]
ALT7
gpu3d
GPU_DEBUG_OUT[
0]
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(360 KΩ PD)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(Low)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-29
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_D14
NANDF_D13
NANDF_D12
Mode
Instance
Port
ALT0
emi
EIM_NFC_D[14]
ALT1
pata
PATA_DATA[14]
ALT2
ecspi2
SS3
ALT3
gpio3
GPIO[26]
ALT4
sdma
DEBUG_PC[1]
ALT5
esdhc3
DAT6
ALT6
ipu
IPU_DIAG_BUS[1]
ALT7
gpu3d
GPU_DEBUG_OUT[
1]
ALT0
emi
EIM_NFC_D[13]
ALT1
pata
PATA_DATA[13]
ALT2
ecspi2
SS2
ALT3
gpio3
GPIO[27]
ALT4
sdma
DEBUG_PC[2]
ALT5
esdhc3
DAT5
ALT6
ipu
IPU_DIAG_BUS[2]
ALT7
gpu3d
GPU_DEBUG_OUT[
2]
ALT0
emi
EIM_NFC_D[12]
ALT1
pata
PATA_DATA[12]
ALT2
ecspi2
SS1
ALT3
gpio3
GPIO[28]
ALT4
sdma
DEBUG_PC[3]
ALT5
esdhc3
DAT4
ALT6
ipu
IPU_DIAG_BUS[3]
ALT7
gpu3d
GPU_DEBUG_OUT[
3]
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-30
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_D11
Mode
Instance
Port
ALT0
emi
EIM_NFC_D[11]
ALT1
pata
PATA_DATA[11]
ALT2
fec
RX_DV
ALT3
gpio3
GPIO[29]
ALT4
sdma
DEBUG_PC[4]
ALT5
esdhc3
DAT3
ALT6
ipu
IPU_DIAG_BUS[4]
ALT7
gpu3d
GPU_DEBUG_OUT[
4]
ALT0
emi
EIM_NFC_D[10]
ALT1
pata
PATA_DATA[10]
ALT3
gpio3
GPIO[30]
ALT4
sdma
DEBUG_PC[5]
ALT5
esdhc3
DAT2
ALT6
ipu
IPU_DIAG_BUS[5]
ALT7
gpu3d
GPU_DEBUG_OUT[
5]
NANDF_D9
ALT0
emi
EIM_NFC_D[9]
NANDF_D9
ALT1
pata
PATA_DATA[9]
ALT2
fec
RDATA[0]
ALT3
gpio3
GPIO[31]
ALT4
sdma
DEBUG_PC[6]
ALT5
esdhc3
DAT1
ALT6
ipu
IPU_DIAG_BUS[6]
ALT7
gpu3d
GPU_DEBUG_OUT[
6]
NANDF_D10
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-31
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_D8
Mode
Instance
Port
ALT0
emi
EIM_NFC_D[8]
ALT1
pata
PATA_DATA[8]
ALT2
fec
TDATA[0]
ALT3
gpio4
GPIO[0]
ALT4
sdma
DEBUG_PC[7]
ALT5
esdhc3
DAT0
ALT6
ipu
IPU_DIAG_BUS[7]
ALT7
gpu3d
GPU_DEBUG_OUT[
7]
ALT0
emi
EIM_NFC_D[7]
ALT1
pata
PATA_DATA[7]
ALT3
gpio4
GPIO[1]
ALT4
sdma
DEBUG_PC[8]
ALT5
usboh3
USBH3_DATA0
ALT6
ipu
IPU_DIAG_BUS[8]
ALT7
gpu3d
GPU_DEBUG_OUT[
8]
NANDF_D6
ALT0
emi
EIM_NFC_D[6]
NANDF_D6
ALT1
pata
PATA_DATA[6]
ALT2
esdhc4
LCTL
ALT3
gpio4
GPIO[2]
ALT4
sdma
DEBUG_PC[9]
ALT5
usboh3
USBH3_DATA1
ALT6
ipu
IPU_DIAG_BUS[9]
ALT7
gpu3d
GPU_DEBUG_OUT[
9]
NANDF_D7
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-32
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_D5
NANDF_D4
NANDF_D3
Mode
Instance
Port
ALT0
emi
EIM_NFC_D[5]
ALT1
pata
PATA_DATA[5]
ALT2
esdhc4
WP
ALT3
gpio4
GPIO[3]
ALT4
sdma
DEBUG_PC[10]
ALT5
usboh3
USBH3_DATA2
ALT6
ipu
IPU_DIAG_BUS[10]
ALT7
gpu3d
GPU_DEBUG_OUT[
10]
ALT0
emi
EIM_NFC_D[4]
ALT1
pata
PATA_DATA[4]
ALT2
esdhc4
CD
ALT3
gpio4
GPIO[4]
ALT4
sdma
DEBUG_PC[11]
ALT5
usboh3
USBH3_DATA3
ALT6
ipu
IPU_DIAG_BUS[11]
ALT7
gpu3d
GPU_DEBUG_OUT[
11]
ALT0
emi
EIM_NFC_D[3]
ALT1
pata
PATA_DATA[3]
ALT2
esdhc4
DAT4
ALT3
gpio4
GPIO[5]
ALT4
sdma
DEBUG_PC[12]
ALT5
usboh3
USBH3_DATA4
ALT6
ipu
IPU_DIAG_BUS[12]
ALT7
gpu3d
GPU_DEBUG_OUT[
12]
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-33
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
NANDF_D2
NANDF_D1
NANDF_D0
Mode
Instance
Port
Pad Settings
ALT0
emi
EIM_NFC_D[2]
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
ALT1
pata
PATA_DATA[2]
ALT2
esdhc4
DAT5
ALT3
gpio4
GPIO[6]
ALT4
sdma
DEBUG_PC[13]
ALT5
usboh3
USBH3_DATA5
ALT6
ipu
IPU_DIAG_BUS[13]
ALT7
gpu3d
GPU_DEBUG_OUT[
13]
ALT0
emi
EIM_NFC_D[1]
ALT1
pata
ALT2
esdhc4
ALT3
gpio4
ALT4
sdma
ALT5
usboh3
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
PATA_DATA[1]
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
DAT6
Pull Up/ Down Config.—CFG(100 KΩ PU)
GPIO[7]
dse test—regular
Open Drain Enable—Disabled
DEBUG_CORE_STA
Pull/Keep Enable—CFG(Enabled)
TE[0]
test_ts—Disabled
USBH3_DATA6
ALT6
ipu
IPU_DIAG_BUS[14]
ALT7
gpu3d
GPU_DEBUG_OUT[
14]
ALT0
emi
EIM_NFC_D[0]
ALT1
pata
ALT2
esdhc4
ALT3
gpio4
ALT4
sdma
ALT5
usboh3
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
PATA_DATA[0]
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
DAT7
Pull Up/ Down Config.—CFG(100 KΩ PU)
GPIO[8]
dse test—regular
Open Drain Enable—Disabled
DEBUG_CORE_STA
Pull/Keep Enable—CFG(Enabled)
TE[1]
test_ts—Disabled
USBH3_DATA7
ALT6
ipu
IPU_DIAG_BUS[15]
ALT7
gpu3d
GPU_DEBUG_OUT[
15]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-34
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CSI1_D8
CSI1_D9
CSI1_D10
CSI1_D11
CSI1_D12
CSI1_D13
CSI1_D14
CSI1_D15
Mode
Instance
Port
ALT0
—
CSI1_D[8]
ALT1
—
DETECT_Z
ALT3
gpio3
GPIO[12]
ALT0
—
CSI1_D[9]
ALT1
—
DELAY_Z
ALT3
gpio3
GPIO[13]
No Muxing
(ALT0)
—
CSI1_D[10]
—
CSI1_D[11]
No Muxing
(ALT0)
—
CSI1_D[12]
—
CSI1_D[13]
No Muxing
(ALT0)
—
CSI1_D[14]
—
CSI1_D[15]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-35
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CSI1_D16
CSI1_D17
CSI1_D18
CSI1_D19
CSI1_VSYNC
CSI1_HSYNC
Mode
Instance
Port
No Muxing
(ALT0)
—
CSI1_D[16]
—
CSI1_D[17]
No Muxing
(ALT0)
—
CSI1_D[18]
—
CSI1_D[19]
ALT0
—
CSI1_VSYNC
ALT1
—
TX_DDR_Q
ALT3
gpio3
GPIO[14]
ALT0
—
CSI1_HSYNC
ALT1
—
TX_DDR_I
ALT3
gpio3
GPIO[15]
Pad Settings
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-36
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CSI1_PIXCLK
Mode
No Muxing
(ALT0)
Instance
Port
Pad Settings
—
CSI1_PIXCLK
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—FAST
test_ts—Disabled
ccm
CSI1_MCLK
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT0
—
CSI2_D[12]
ALT1
—
LP_RX_E
ALT3
gpio4
GPIO[9]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT0
—
CSI2_D[13]
ALT1
—
RX_VALID_ESC_O
UT
ALT3
gpio4
GPIO[10]
CSI2_D13
ALT6
emi
EMI_DEBUG[45]
CSI2_D14
No Muxing
(ALT0)
—
CSI2_D[14]
—
CSI2_D[15]
CSI1_MCLK
CSI2_D12
CSI2_D13
CSI2_D15
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-37
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CSI2_D16
CSI2_D17
CSI2_D18
CSI2_D19
CSI2_VSYNC
Mode
Instance
Port
No Muxing
(ALT0)
—
CSI2_D[16]
—
CSI2_D[17]
ALT0
—
CSI2_D[18]
ALT1
—
HS_TX_E
ALT2
elvis_observe OBSRV_INT_OUT0
_mux
ALT3
gpio4
GPIO[11]
ALT4
sdma
DEBUG_RTBUFFE
R_WRITE
ALT6
emi
EMI_DEBUG[46]
ALT0
—
CSI2_D[19]
ALT1
—
LP_TX_E
ALT2
elvis_observe OBSRV_INT_OUT1
_mux
ALT3
gpio4
GPIO[12]
ALT4
sdma
DEBUG_YIELD
ALT6
emi
EMI_DEBUG[47]
ALT0
—
CSI2_VSYNC
ALT1
—
HS_RX_E
ALT2
elvis_observe OBSRV_INT_OUT2
_mux
ALT3
gpio4
GPIO[13]
ALT4
sdma
DEBUG_BUS_ERR
OR
ALT6
emi
EMI_DEBUG[48]
Pad Settings
Drive Strength—Low
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
Drive Strength—CFG(Low)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
Drive Strength—CFG(Low)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
Drive Strength—CFG(Low)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-38
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CSI2_HSYNC
Mode
Instance
Port
ALT0
—
CSI2_HSYNC
ALT1
—
TX_BYTE_CLK_HS
_OUT
ALT2
elvis_observe OBSRV_INT_OUT3
_mux
ALT3
gpio4
GPIO[14]
ALT6
emi
EMI_DEBUG[49]
CSI2_PIXCLK
ALT0
—
CSI2_PIXCLK
CSI2_PIXCLK
ALT1
—
RX_BYTE_CLK_HS
_OUT
ALT2
elvis_observe OBSRV_INT_OUT4
_mux
ALT3
gpio4
GPIO[15]
ALT6
emi
EMI_DEBUG[50]
ALT0
hsi2c
SCL
ALT3
gpio4
GPIO[16]
ALT0
hsi2c
SDA
ALT3
gpio4
GPIO[17]
ALT0
audmux
AUD3_TXD
ALT1
slm
DATA
ALT3
gpio4
GPIO[18]
ALT7
usbphy
DATAOUT[0]
I2C1_CLK
I2C1_DAT
AUD3_BB_TXD
Pad Settings
Drive Strength—CFG(Low)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(Low)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—NA
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—NA
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-39
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
AUD3_BB_RXD
AUD3_BB_RXD
AUD3_BB_CK
AUD3_BB_FS
CSPI1_MOSI
CSPI1_MOSI
CSPI1_MISO
Mode
Instance
Port
ALT0
audmux
AUD3_RXD
ALT1
uart3
RXD_MUX
ALT3
gpio4
GPIO[19]
ALT7
usbphy
DATAOUT[1]
ALT0
audmux
AUD3_TXC
ALT1
slm
CLK
ALT3
gpio4
GPIO[20]
ALT7
usbphy
DATAOUT[2]
ALT0
audmux
AUD3_TXFS
ALT1
uart3
TXD_MUX
ALT3
gpio4
GPIO[21]
ALT7
usbphy
DATAOUT[3]
ALT0
ecspi1
MOSI
ALT1
i2c1
SDA
ALT3
gpio4
GPIO[22]
ALT7
usbphy
DATAOUT[4]
ALT0
ecspi1
MISO
ALT1
audmux
AUD4_RXD
ALT3
gpio4
GPIO[23]
ALT7
usbphy
DATAOUT[5]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-40
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CSPI1_SS0
CSPI1_SS1
CSPI1_SS1
CSPI1_RDY
CSPI1_SCLK
UART1_RXD
UART1_RXD
Mode
Instance
Port
ALT0
ecspi1
SS0
ALT1
audmux
AUD4_TXC
ALT3
gpio4
GPIO[24]
ALT7
usbphy
DATAOUT[6]
ALT0
ecspi1
SS1
ALT1
audmux
AUD4_TXD
ALT3
gpio4
GPIO[25]
ALT7
usbphy
DATAOUT[7]
ALT0
ecspi1
RDY
ALT1
audmux
AUD4_TXFS
ALT3
gpio4
GPIO[26]
ALT7
usbphy
DATAOUT[8]
ALT0
ecspi1
SCLK
ALT1
i2c1
SCL
ALT3
gpio4
GPIO[27]
ALT7
usbphy
DATAOUT[9]
ALT0
uart1
RXD_MUX
ALT3
gpio4
GPIO[28]
ALT5
—
READY_ESC_OUT
ALT6
emi
EMI_DEBUG[12]
ALT7
usbphy
DATAOUT[10]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(Low)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-41
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
UART1_TXD
Mode
Instance
Port
ALT0
uart1
TXD_MUX
ALT1
pwm2
PWMO
ALT3
gpio4
GPIO[29]
ALT5
—
REQUEST_ESC_O
UT
ALT6
emi
EMI_DEBUG[13]
ALT7
usbphy
DATAOUT[11]
ALT0
uart1
RTS
ALT3
gpio4
GPIO[30]
ALT5
—
CLK_ESC_OUT
ALT6
emi
EMI_DEBUG[14]
ALT7
usbphy
DATAOUT[12]
UART1_CTS
ALT0
uart1
CTS
UART1_CTS
ALT3
gpio4
GPIO[31]
ALT5
—
READY_HS_OUT
ALT6
emi
EMI_DEBUG[15]
ALT7
usbphy
DATAOUT[13]
ALT0
uart2
RXD_MUX
ALT1
firi
TXD
ALT3
gpio1
GPIO[20]
ALT5
—
VALID_HS_OUT
ALT6
emi
EMI_DEBUG[16]
ALT7
usbphy
DATAOUT[14]
ALT0
uart2
TXD_MUX
ALT1
firi
RXD
ALT3
gpio1
GPIO[21]
ALT5
—
VALID_ESC_OUT
ALT6
emi
EMI_DEBUG[17]
ALT7
usbphy
DATAOUT[15]
UART1_RTS
UART2_RXD
UART2_TXD
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-42
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
UART3_RXD
Mode
Instance
Port
ALT0
uart1
DTR
ALT1
uart3
RXD_MUX
ALT2
—
CSI1_D[0]
ALT3
gpio1
GPIO[22]
ALT5
—
SYNC_HS_OUT
ALT6
emi
EMI_DEBUG[18]
ALT7
usbphy
LINESTATE[0]
ALT0
uart1
DSR
ALT1
uart3
TXD_MUX
ALT2
—
CSI1_D[1]
ALT3
gpio1
GPIO[23]
ALT5
—
REQUEST_HS_OU
T
ALT6
emi
EMI_DEBUG[19]
ALT7
usbphy
LINESTATE[1]
ALT0
owire
LINE
ALT3
gpio1
GPIO[24]
ALT5
tigerp_platfor
m_ne_32k_2
56k
CTI_TRIGOUT6
ALT6
spdif
OUT1
ALT7
src
SYSTEM_RST
KEY_ROW0
ALT0
kpp
ROW[0]
KEY_ROW0
ALT1
emi
DSTROBE
ALT2
—
TX_DDR_Q
ALT5
scc
RANDOM_V
ALT6
emi
EMI_DEBUG[20]
UART3_TXD
OWIRE_LINE
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—Pull
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-43
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
KEY_ROW1
Mode
Instance
Port
ALT0
kpp
ROW[1]
ALT1
rtic
RTIC_SEC_VIO
ALT2
—
TX_DDR_I
ALT5
scc
RANDOM
ALT6
emi
EMI_DEBUG[21]
ALT0
kpp
ROW[2]
ALT1
rtic
RTIC_DONE_INT
ALT2
—
TX_DDR_Q
ALT5
sjc
DONE
ALT6
emi
EMI_DEBUG[22]
KEY_ROW3
ALT0
kpp
ROW[3]
KEY_ROW3
ALT1
csu
CSU_ALARM_AUT[
0]
ALT2
—
TX_DDR_I
ALT5
sjc
FAIL
ALT6
emi
EMI_DEBUG[23]
ALT0
kpp
COL[0]
ALT1
csu
CSU_ALARM_AUT[
1]
ALT2
—
HS_TX_E0
ALT7
ccm
PLL1_BYP
ALT0
kpp
COL[1]
ALT1
csu
CSU_ALARM_AUT[
2]
ALT2
—
HS_TX_E1
ALT7
ccm
PLL2_BYP
KEY_ROW2
KEY_COL0
KEY_COL1
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-44
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
KEY_COL2
Mode
Instance
Port
ALT0
kpp
COL[2]
ALT1
ipu
SNOOP2
KEY_COL2
ALT7
ccm
PLL3_BYP
KEY_COL3
ALT0
kpp
COL[3]
ALT5
tigerp_platfor
m_ne_32k_2
56k
CTI_TRIGOUT7
ALT7
src
INT_BOOT
ALT0
kpp
COL[4]
ALT1
uart1
RI
ALT2
uart3
RTS
ALT3
i2c2
SCL
ALT4
ccm
SSI_EXT2_CLK
ALT5
tigerp_platfor
m_ne_32k_2
56k
CTI_TRIGIN_ACK7
ALT6
spdif
OUT1
ALT7
src
ANY_PU_RST
ALT0
kpp
COL[5]
ALT1
uart1
DCD
ALT2
uart3
CTS
ALT3
i2c2
SDA
ALT4
ccm
SSI_EXT1_CLK
ALT5
tigerp_platfor
m_ne_32k_2
56k
CTI_TRIGIN7
ALT6
—
MCT_EXT_ACT_TRI
G
ALT7
sjc
JTAG_ACT
KEY_COL4
KEY_COL4
KEY_COL5
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-45
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
JTAG_TCK
Mode
No Muxing
(ALT0)
JTAG_TMS
JTAG_TDI
JTAG_TDO
No Muxing
(ALT0)
Instance
Port
Pad Settings
sjc
TCK
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PD
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(SLOW)
test_ts—Disabled
sjc
TMS
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—47 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(SLOW)
test_ts—Disabled
sjc
TDI
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—47 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(SLOW)
test_ts—Disabled
sjc
TDO
Drive Strength—High
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—FAST
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-46
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
JTAG_TRSTB
Mode
No Muxing
(ALT0)
JTAG_DE_B
Instance
Port
Pad Settings
sjc
TRSTB
Drive Strength—Low
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—47 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(SLOW)
test_ts—Disabled
sjc
DE_B
Drive Strength—High
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—47 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Enabled
Pull/Keep Enable—Enabled
Slew Rate—FAST
test_ts—Disabled
JTAG_MOD
No Muxing
(ALT0)
sjc
MOD
Drive Strength—Low
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—CFG(SLOW)
test_ts—Disabled
USBH1_CLK
ALT0
usboh3
USBH1_CLK
ALT1
cspi
SCLK
ALT2
gpio1
GPIO[25]
ALT3
—
LPDT_ESC_OUT
ALT4
sdma
DEBUG_CORE_RU
N
ALT5
i2c2
SCL
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT6
emi
EMI_DEBUG[0]
ALT7
uart3
CTS
USBH1_CLK
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-47
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
USBH1_DIR
USBH1_STP
USBH1_NXT
USBH1_DATA0
Mode
Instance
Port
Pad Settings
ALT0
usboh3
USBH1_DIR
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT1
cspi
MOSI
ALT2
gpio1
GPIO[26]
ALT3
—
HS_RX_Z
ALT4
sdma
DEBUG_MODE
ALT5
i2c2
SDA
ALT6
emi
EMI_DEBUG[1]
ALT7
uart3
RTS
ALT0
usboh3
USBH1_STP
ALT1
cspi
RDY
ALT2
gpio1
GPIO[27]
ALT3
—
ACTIVE_HS_OUT
ALT4
sdma
DEBUG_EVENT_C
HANNEL_SEL
ALT5
uart3
RXD_MUX
ALT6
emi
EMI_DEBUG[2]
ALT7
usbphy
BISTOK
ALT0
usboh3
USBH1_NXT
ALT1
cspi
MISO
ALT2
gpio1
GPIO[28]
ALT3
—
RX_TERM_E
ALT4
sdma
DEBUG_BUS_RWB
ALT5
uart3
TXD_MUX
ALT6
emi
EMI_DEBUG[3]
ALT7
usbphy
ONBIST
ALT0
usboh3
USBH1_DATA0
ALT1
uart2
ALT2
gpio1
ALT3
—
ALT4
sdma
ALT6
emi
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
CTS
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
GPIO[11]
Strength mode—4_level
DATA_ESC_OUT[0]
dse test—regular
Open Drain Enable—Disabled
DEBUG_CORE_STA
Pull/Keep Enable—CFG(Enabled)
TE[2]
Slew Rate—CFG(FAST)
test_ts—Disabled
EMI_DEBUG[4]
ALT7
usbphy
VSTATUS[0]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-48
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
USBH1_DATA1
USBH1_DATA2
USBH1_DATA3
USBH1_DATA4
Mode
Instance
Port
Pad Settings
ALT0
usboh3
USBH1_DATA1
ALT1
uart2
ALT2
gpio1
ALT3
—
ALT4
sdma
ALT6
emi
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
RXD_MUX
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
GPIO[12]
Strength mode—4_level
DATA_ESC_OUT[1]
dse test—regular
Open Drain Enable—Disabled
DEBUG_CORE_STA
Pull/Keep Enable—CFG(Enabled)
TE[3]
Slew Rate—CFG(FAST)
test_ts—Disabled
EMI_DEBUG[5]
ALT7
usbphy
VSTATUS[1]
ALT0
usboh3
USBH1_DATA2
ALT1
uart2
TXD_MUX
ALT2
gpio1
GPIO[13]
ALT3
—
DATA_ESC_OUT[2]
ALT4
sdma
DEBUG_MATCHED
_DMBUS
ALT6
emi
EMI_DEBUG[6]
ALT7
usbphy
VSTATUS[2]
ALT0
usboh3
USBH1_DATA3
ALT1
uart2
RTS
ALT2
gpio1
GPIO[14]
ALT3
—
DATA_ESC_OUT[3]
ALT4
sdma
DEBUG_BUS_DEVI
CE[0]
ALT6
emi
EMI_DEBUG[7]
ALT7
usbphy
VSTATUS[3]
ALT0
usboh3
USBH1_DATA4
ALT1
cspi
SS0
ALT2
gpio1
GPIO[15]
ALT3
—
DATA_ESC_OUT[4]
ALT4
sdma
DEBUG_BUS_DEVI
CE[1]
ALT6
emi
EMI_DEBUG[8]
ALT7
usbphy
VSTATUS[4]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-49
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
USBH1_DATA5
USBH1_DATA6
USBH1_DATA7
DI1_PIN11
Mode
Instance
Port
ALT0
usboh3
USBH1_DATA5
ALT1
cspi
SS1
ALT2
gpio1
GPIO[16]
ALT3
—
DATA_ESC_OUT[5]
ALT4
sdma
DEBUG_BUS_DEVI
CE[2]
ALT6
emi
EMI_DEBUG[9]
ALT7
usbphy
VSTATUS[5]
ALT0
usboh3
USBH1_DATA6
ALT1
cspi
SS3
ALT2
gpio1
GPIO[17]
ALT3
—
DATA_ESC_OUT[6]
ALT4
sdma
DEBUG_BUS_DEVI
CE[3]
ALT6
emi
EMI_DEBUG[10]
ALT7
usbphy
VSTATUS[6]
ALT0
usboh3
USBH1_DATA7
ALT1
ecspi1
SS3
ALT2
gpio1
GPIO[18]
ALT3
—
DATA_ESC_OUT[7]
ALT4
sdma
DEBUG_BUS_DEVI
CE[4]
ALT5
ecspi2
SS3
ALT6
emi
EMI_DEBUG[11]
ALT7
usbphy
VSTATUS[7]
ALT0
ipu
DI1_PIN11
ALT1
—
READY_ESC_IN
ALT4
gpio3
GPIO[0]
ALT7
ecspi1
SS2
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-50
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DI1_PIN12
Mode
Instance
Port
ALT0
ipu
DI1_PIN12
ALT1
—
REQUEST_ESC_IN
DI1_PIN12
ALT4
gpio3
GPIO[1]
DI1_PIN13
ALT0
ipu
DI1_PIN13
ALT1
—
CLK_ESC_IN
ALT4
gpio3
GPIO[2]
ALT0
ipu
DI1_D0_CS
ALT1
—
LPDT_ESC_IN
DI1_D0_CS
ALT4
gpio3
GPIO[3]
DI1_D1_CS
ALT0
ipu
DI1_D1_CS
ALT1
—
READY_HS_IN
ALT2
ipu
DI1_PIN14
ALT3
ipu
DI1_PIN5
ALT4
gpio3
GPIO[4]
ALT0
ipu
DISPB2_SER_DIN
ALT1
—
VALID_HS_IN
ALT2
—
DI1_PIN1
ALT4
gpio3
GPIO[5]
DI1_D0_CS
DISPB2_SER_DIN
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-51
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISPB2_SER_DIO
Mode
Instance
Port
Pad Settings
ALT0
ipu
DISPB2_SER_DIO
ALT1
—
ACTIVE_HS_IN
ALT3
ipu
DI1_PIN6
ALT4
gpio3
GPIO[6]
ALT6
wdog1
WDOG_RST_B_DE
B
ipu
DISPB2_SER_CLK
ALT1
—
BYTE_CLK_HS_IN
ALT2
ipu
DI1_PIN17
ALT3
ipu
DI1_PIN7
ALT4
gpio3
GPIO[7]
ALT6
wdog2
WDOG_RST_B_DE
B
ALT0
ipu
DISPB2_SER_RS
ALT1
—
VALID_ESC_IN
ALT2
ipu
DI1_PIN16
ALT3
ipu
DI1_PIN8
ALT4
gpio3
GPIO[8]
DISP1_DAT0
No Muxing
(ALT0)
ipu
DISP1_DAT[0]
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DISP1_DAT1
No Muxing
(ALT0)
ipu
DISP1_DAT[1]
ipu
DISP1_DAT[2]
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DISPB2_SER_DIO
DISPB2_SER_CLK ALT0
DISPB2_SER_RS
DISP1_DAT2
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-52
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP1_DAT3
Mode
Instance
Port
Pad Settings
No Muxing
(ALT0)
ipu
DISP1_DAT[3]
ipu
DISP1_DAT[4]
DISP1_DAT5
No Muxing
(ALT0)
ipu
DISP1_DAT[5]
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DISP1_DAT6
ALT0
ipu
DISP1_DAT[6]
ALT7
src
BT_USB_SRC
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT0
ipu
DISP1_DAT[7]
ALT7
src
BT_EEPROM_CFG
ALT0
ipu
DISP1_DAT[8]
ALT7
src
BT_SRC[0]
DISP1_DAT4
DISP1_DAT7
DISP1_DAT8
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-53
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP1_DAT9
DISP1_DAT10
DISP1_DAT11
DISP1_DAT12
DISP1_DAT13
Mode
Instance
Port
ALT0
ipu
DISP1_DAT[9]
ALT7
src
BT_SRC[1]
ALT0
ipu
DISP1_DAT[10]
ALT7
src
BT_SPARE_SIZE
ALT0
ipu
DISP1_DAT[11]
ALT7
src
BT_LPB_FREQ[2]
ALT0
ipu
DISP1_DAT[12]
ALT7
src
BT_MLC_SEL
ALT0
ipu
DISP1_DAT[13]
ALT7
src
BT_MEM_CTL[0]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-54
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP1_DAT14
DISP1_DAT15
DISP1_DAT16
DISP1_DAT17
DISP1_DAT18
Mode
Instance
Port
ALT0
ipu
DISP1_DAT[14]
ALT7
src
BT_MEM_CTL[1]
ALT0
ipu
DISP1_DAT[15]
ALT7
src
BT_BUS_WIDTH
ALT0
ipu
DISP1_DAT[16]
ALT7
src
BT_PAGE_SIZE[0]
ALT0
ipu
DISP1_DAT[17]
ALT7
src
BT_PAGE_SIZE[1]
ALT0
ipu
DISP1_DAT[18]
ALT4
ipu
DI2_PIN5
ALT5
ipu
DI2_PIN11
ALT7
src
BT_WEIM_MUXED[
0]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-55
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP1_DAT19
DISP1_DAT20
DISP1_DAT20
DISP1_DAT21
DISP1_DAT22
Mode
Instance
Port
ALT0
ipu
DISP1_DAT[19]
ALT4
ipu
DI2_PIN6
ALT5
ipu
DI2_PIN12
ALT7
src
BT_WEIM_MUXED[
1]
ALT0
ipu
DISP1_DAT[20]
ALT4
ipu
DI2_PIN7
ALT5
ipu
DI2_PIN13
ALT7
src
BT_MEM_TYPE[0]
ALT0
ipu
DISP1_DAT[21]
ALT4
ipu
DI2_PIN8
ALT5
ipu
DI2_PIN14
ALT7
src
BT_MEM_TYPE[1]
ALT0
ipu
DISP1_DAT[22]
ALT3
tigerp_platfor
m_ne_32k_2
56k
ALT5
ipu
ALT6
ipu
ALT7
src
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
CTI_TRIGOUT_ACK Pull/Keep Select—CFG(Keep)
6
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
DISP2_DAT[16]
Open Drain Enable—Disabled
DI2_D0_CS
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
BT_LPB_FREQ[0]
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-56
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
Mode
Instance
Port
Pad Settings
DISP1_DAT23
ALT0
ipu
DISP1_DAT23
ALT3
tigerp_platfor
m_ne_32k_2
56k
ALT4
ipu
ALT5
ipu
ALT6
ipu
ALT7
src
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
CTI_TRIGOUT_ACK Pull/Keep Select—CFG(Keep)
7
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
SER_DISP2_CS
Open Drain Enable—Disabled
DISP2_DAT[17]
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
DI2_D1_CS
test_ts—Disabled
BT_LPB_FREQ[1]
ALT0
ipu
DI1_PIN3
ALT1
—
ALT6
emi
ALT7
sim
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
TX_DDR_Q
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
EMI_DEBUG[24]
Strength mode—4_level
SIM_TX_CLK_TEST dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DI1_DISP_CLK
No Muxing
(ALT0)
ipu
DI1_DISP_CLK
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DI1_PIN2
ALT0
ipu
DI1_PIN2
ALT1
—
TX_DDR_I
ALT6
emi
EMI_DEBUG[25]
ALT7
sim
SIM_RCV_CLK_TE
ST
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DI1_PIN3
DISP1_DAT[23]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-57
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
Mode
Instance
Port
Pad Settings
DI1_PIN15
No Muxing
(ALT0)
ipu
DI1_PIN15
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—Keep
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
DI_GP1
ALT0
ipu
DISPB1_SER_RS
ALT1
—
RX_VALID_ESC_IN
ALT2
ccm
DI1_EXT_CLK
ALT6
emi
EMI_DEBUG[26]
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
ALT0
ipu
DISPB1_SER_CLK
ALT1
—
SYNC_HS_IN
ALT2
—
DI2_WAIT
ALT6
emi
EMI_DEBUG[27]
ALT0
ipu
DISPB1_SER_DIO
ALT1
—
REQUEST_HS_IN
ALT2
fec
TX_ER
ALT3
—
CSI1_DATA_EN
ALT6
emi
EMI_DEBUG[28]
ALT0
ipu
DI2_PIN4
ALT1
—
DATA_HS_IN[0]
ALT2
fec
CRS
ALT3
—
CSI2_DATA_EN
ALT6
emi
EMI_DEBUG[29]
DI_GP2
DI_GP3
DI_GP3
DI2_PIN4
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-58
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DI2_PIN2
DI2_PIN3
DI2_PIN3
DI2_DISP_CLK
DI_GP4
DI_GP4
DISP2_DAT0
Mode
Instance
Port
ALT0
ipu
DI2_PIN2
ALT1
—
DATA_HS_IN[1]
ALT2
fec
MDC
ALT6
emi
EMI_DEBUG[30]
ALT0
ipu
DI2_PIN3
ALT1
—
DATA_HS_IN[2]
ALT2
fec
MDIO
ALT6
emi
EMI_DEBUG[31]
ALT0
ipu
DI2_DISP_CLK
ALT2
fec
RDATA[1]
ALT0
ipu
DISPB1_SER_DIN
ALT1
—
DATA_HS_IN[3]
ALT2
fec
RDATA[2]
ALT3
—
DI2_PIN1
ALT4
ipu
DI2_PIN15
ALT6
emi
EMI_DEBUG[32]
ALT0
ipu
DISP2_DAT[0]
ALT1
—
DATA_HS_IN[4]
ALT2
fec
RDATA[3]
ALT3
usboh3
USBH3_CLK
ALT4
kpp
COL[6]
ALT5
uart3
RXD_MUX
ALT6
emi
EMI_DEBUG[33]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—22 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(SLOW)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-59
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP2_DAT1
DISP2_DAT2
DISP2_DAT3
DISP2_DAT4
DISP2_DAT5
DISP2_DAT6
Mode
Instance
Port
ALT0
ipu
DISP2_DAT[1]
ALT1
—
DATA_HS_IN[5]
ALT2
fec
RX_ER
ALT3
usboh3
USBH3_DIR
ALT4
kpp
COL[7]
ALT5
uart3
TXD_MUX
ALT6
emi
EMI_DEBUG[34]
No Muxing
(ALT0)
ipu
DISP2_DAT[2]
ipu
DISP2_DAT[3]
No Muxing
(ALT0)
ipu
DISP2_DAT[4]
ipu
DISP2_DAT[5]
ALT0
ipu
DISP2_DAT[6]
ALT1
—
DATA_HS_IN[6]
ALT2
fec
TDATA[1]
ALT3
usboh3
USBH3_STP
ALT4
kpp
ROW[4]
ALT5
gpio1
GPIO[19]
ALT6
emi
EMI_DEBUG[35]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-60
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP2_DAT7
DISP2_DAT8
DISP2_DAT9
DISP2_DAT10
Mode
Instance
Port
ALT0
ipu
DISP2_DAT[7]
ALT1
—
DATA_HS_IN[7]
ALT2
fec
TDATA[2]
ALT3
usboh3
USBH3_NXT
ALT4
kpp
ROW[5]
ALT5
gpio1
GPIO[29]
ALT6
emi
EMI_DEBUG[36]
ALT0
ipu
DISP2_DAT[8]
ALT1
—
DATA_ESC_IN[0]
ALT2
fec
TDATA[3]
ALT3
usboh3
USBH3_DATA0
ALT4
kpp
ROW[6]
ALT5
gpio1
GPIO[30]
ALT6
emi
EMI_DEBUG[37]
ALT0
ipu
DISP2_DAT[9]
ALT1
—
DATA_ESC_IN[1]
ALT2
fec
TX_EN
ALT3
usboh3
USBH3_DATA1
ALT4
audmux
AUD6_RXC
ALT5
gpio1
GPIO[31]
ALT6
emi
EMI_DEBUG[38]
ALT0
ipu
DISP2_DAT[10]
ALT1
—
DATA_ESC_IN[2]
ALT2
fec
COL
ALT3
usboh3
USBH3_DATA2
ALT4
kpp
ROW[7]
ALT5
ipu
SER_DISP2_CS
ALT6
emi
EMI_DEBUG[39]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-61
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP2_DAT11
DISP2_DAT12
DISP2_DAT13
DISP2_DAT14
Mode
Instance
Port
ALT0
ipu
DISP2_DAT[11]
ALT1
—
DATA_ESC_IN[3]
ALT2
fec
RX_CLK
ALT3
usboh3
USBH3_DATA3
ALT4
audmux
AUD6_TXD
ALT6
emi
EMI_DEBUG[40]
ALT7
gpio1
GPIO[10]
ALT0
ipu
DISP2_DAT[12]
ALT1
—
DATA_ESC_IN[4]
ALT2
fec
RX_DV
ALT3
usboh3
USBH3_DATA4
ALT4
audmux
AUD6_RXD
ALT6
emi
EMI_DEBUG[41]
ALT0
ipu
DISP2_DAT[13]
ALT1
—
DATA_ESC_IN[5]
ALT2
fec
TX_CLK
ALT3
usboh3
USBH3_DATA5
ALT4
audmux
AUD6_TXC
ALT6
emi
EMI_DEBUG[42]
ALT0
ipu
DISP2_DAT[14]
ALT1
—
DATA_ESC_IN[6]
ALT2
fec
RDATA[0]
ALT3
usboh3
USBH3_DATA6
ALT4
audmux
AUD6_TXFS
ALT6
emi
EMI_DEBUG[43]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-62
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
DISP2_DAT15
SD1_CMD
SD1_CLK
SD1_DATA0
SD1_DATA1
Mode
Instance
Port
ALT0
ipu
DISP2_DAT[15]
ALT1
—
DATA_ESC_IN[7]
ALT2
fec
TDATA[0]
ALT3
usboh3
USBH3_DATA7
ALT4
audmux
AUD6_RXFS
ALT5
ipu
SER_DISP1_CS
ALT6
emi
EMI_DEBUG[44]
ALT0
esdhc1
CMD
ALT1
audmux
AUD5_RXFS
ALT2
cspi
MOSI
ALT0
esdhc1
CLK
ALT1
audmux
AUD5_RXC
ALT2
cspi
SCLK
ALT0
esdhc1
DAT0
ALT1
audmux
AUD5_TXD
ALT2
cspi
MISO
ALT0
esdhc1
DAT1
ALT1
audmux
AUD5_RXD
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Enabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-63
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
SD1_DATA2
SD1_DATA3
GPIO1_0
GPIO1_1
SD2_CMD
Mode
Instance
Port
ALT0
esdhc1
DAT2
ALT1
audmux
AUD5_TXC
ALT0
esdhc1
DAT3
ALT1
audmux
AUD5_TXFS
ALT2
cspi
SS1
ALT0
esdhc1
CD
ALT1
gpio1
GPIO[0]
ALT2
cspi
SS2
ALT0
esdhc1
WP
ALT1
gpio1
GPIO[1]
ALT2
cspi
MISO
ALT0
esdhc2
CMD
ALT1
i2c1
SCL
ALT2
cspi
MOSI
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(360 KΩ PD)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Enabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-64
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
SD2_CLK
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
Mode
Instance
Port
ALT0
esdhc2
CLK
ALT1
i2c1
SDA
ALT2
cspi
SCLK
ALT0
esdhc2
DAT0
ALT1
esdhc1
DAT4
ALT2
cspi
MISO
ALT0
esdhc2
DAT1
ALT1
esdhc1
DAT5
ALT2
usboh3
H2_DP
ALT0
esdhc2
DAT2
ALT1
esdhc1
DAT6
ALT2
usboh3
H2_DM
ALT0
esdhc2
DAT3
ALT1
esdhc1
DAT7
ALT2
cspi
SS2
Pad Settings
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(47 KΩ PU)
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
Drive Strength—CFG(High)
low/high output voltage—CFG(High)
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(360 KΩ PD)
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-65
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
GPIO1_2
GPIO1_3
RESET_IN_B
POR_B
BOOT_MODE1
BOOT_MODE0
Mode
Instance
Port
ALT0
gpio1
GPIO[2]
ALT1
pwm1
PWMO
ALT2
i2c2
SCL
ALT5
ccm
CCM_OUT_2
ALT6
dpllip1
TOG_EN
ALT7
ccm
PLL1_BYP
ALT0
gpio1
GPIO[3]
ALT1
pwm2
PWMO
ALT2
i2c2
SDA
ALT5
ccm
CLKO2
ALT6
gpt
CLKIN
ALT7
ccm
PLL2_BYP
No Muxing
(ALT0)
src
RESET_B
src
POR_B
No Muxing
(ALT0)
src
BOOT_MODE[1]
src
BOOT_MODE[0]
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—Enabled
Slew Rate—SLOW
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—100 KΩ PU
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—Enabled
Slew Rate—SLOW
test_ts—Disabled
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-66
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
PMIC_RDY
Mode
No Muxing
(ALT0)
Pad Settings
PMIC_RDY
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—Enabled
Slew Rate—SLOW
test_ts—Disabled
ccm
CKIL
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—Disabled
Slew Rate—SLOW
test_ts—Disabled
ccm
PMIC_VSTBY_REQ
Drive Strength—CFG(High)
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
srtc
SRTCALARM
Drive Strength—High
Hyst. Enable—Disabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—FAST
test_ts—Disabled
ALT0
tzic
PWRFAIL_INT
ALT1
tigerp_platfor
m_ne_32k_2
56k
PMU_IRQ_B
Drive Strength—CFG(High)
Hyst. Enable—CFG(Enabled)
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
No Muxing
(ALT0)
PMIC_ON_REQ
PMIC_INT_REQ
Port
gpc
CKIL
PMIC_STBY_REQ
Instance
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-67
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
CLK_SS
Mode
No Muxing
(ALT0)
GPIO1_5
GPIO1_6
Port
Pad Settings
ccm
CLKSS
camp1
CKIH
ALT0
gpio1
GPIO[4]
ALT1
sdma
ALT2
wdog1
ALT3
emi
ALT4
ccm
ALT6
gpt
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
SDMA_EXT_EVENT Pull/Keep Select—CFG(Keep)
[0]
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
WDOG_B
dse test—regular
RDY
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
DI2_EXT_CLK
Slew Rate—CFG(FAST)
test_ts—Disabled
CAPIN1
ALT7
dpllip1
TOG_EN
ALT0
gpio1
GPIO[5]
ALT1
sdma
ALT2
wdog2
ALT3
ipu
ALT5
ccm
ALT6
ccm
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
SDMA_EXT_EVENT Pull/Keep Select—CFG(Keep)
[1]
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
WDOG_B
dse test—regular
DI2_PIN16
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
CLKO
Slew Rate—CFG(FAST)
test_ts—Disabled
CSI2_MCLK
ALT0
gpio1
GPIO[6]
ALT1
ccm
ALT2
—
ALT3
ccm
ALT4
ipu
ALT5
epit2
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
SSI_EXT2_CLK
Pull/Keep Select—CFG(Keep)
MCT_EXT_ACT_TRI Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
G
dse test—regular
REF_EN_B
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
DI2_PIN17
Slew Rate—CFG(FAST)
test_ts—Disabled
EPITO
ALT6
gpt
CAPIN2
ALT7
csu
TD
CKIH1
GPIO1_4
Instance
Drive Strength—Low
Hyst. Enable—Enabled
Pull/Keep Select—CFG(Pull)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—NA
Pull/Keep Enable—Enabled
Slew Rate—SLOW
test_ts—Disabled
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-68
Freescale Semiconductor
Table 4-1. i.MX51 Signal Multiplexing and I/O Configurations (continued)
Pad Name
GPIO1_7
GPIO1_8
GPIO1_9
TEST_MODE
Mode
Instance
Port
ALT0
gpio1
GPIO[7]
ALT1
ccm
SSI_EXT1_CLK
ALT2
spdif
OUT1
ALT3
ccm
CCM_OUT_0
ALT5
epit1
EPITO
ALT6
esdhc2
WP
ALT7
dpllip1
TOG_EN
ALT0
gpio1
GPIO[8]
ALT1
usboh3
USB_PWR
ALT2
—
CSI2_DATA_EN
ALT4
ccm
CLKO2
ALT6
esdhc2
CD
ALT7
src
TESTER_ACK
ALT0
gpio1
GPIO[9]
ALT1
usboh3
USB_OC
ALT2
ipu
DI2_D1_CS
ALT3
ccm
CCM_OUT_1
ALT4
ccm
CLKO
ALT6
esdhc2
LCTL
ALT7
ipu
SER_DISP2_CS
No Muxing
(ALT0)
tcu
TEST_MODE
camp2
CKIH
CKIH2
Pad Settings
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PU)
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—CFG(High)
Hyst. Enable—CFG(Disabled)
Pull/Keep Select—CFG(Keep)
Pull Up/ Down Config.—CFG(100 KΩ PD)
Strength mode—4_level
dse test—regular
Open Drain Enable—CFG(Disabled)
Pull/Keep Enable—CFG(Enabled)
Slew Rate—CFG(FAST)
test_ts—Disabled
Drive Strength—Low
Hyst. Enable—Disabled
Pull/Keep Select—Pull
Pull Up/ Down Config.—100 KΩ PD
Strength mode—4_level
dse test—regular
Open Drain Enable—Disabled
Pull/Keep Enable—Enabled
Slew Rate—SLOW
test_ts—Disabled
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-69
Table 4-2 lists muxing options sorted by module/function.
Table 4-2. Muxing Options Sorted by Module
Instance
HSI2C
Port
Pad
Mode
SCL
I2C1_CLK
ALT0
SDA
I2C1_DAT
ALT0
TZIC
PWRFAIL_INT
PMIC_INT_REQ
ALT0
RTIC
RTIC_DONE_INT
KEY_ROW2
ALT1
RTIC_SEC_VIO
KEY_ROW1
ALT1
FAIL_STATE
EIM_D22
ALT3
RANDOM
KEY_ROW1
ALT5
RANDOM_V
KEY_ROW0
ALT5
SEC_STATE
EIM_D23
ALT3
SRTCALARM
PMIC_ON_REQ
No Muxing (ALT0)
SRTC_ALARM_DEB
EIM_D20
ALT4
EIM_D21
ALT3
SCC
SRTC
TCU
TEST_MODE
TEST_MODE
No Muxing (ALT0)
GPC
PMIC_RDY
PMIC_RDY
No Muxing (ALT0)
ECSPI1
MISO
CSPI1_MISO
ALT0
MOSI
CSPI1_MOSI
ALT0
RDY
CSPI1_RDY
ALT0
SCLK
CSPI1_SCLK
ALT0
SS0
CSPI1_SS0
ALT0
SS1
CSPI1_SS1
ALT0
SS2
DI1_PIN11
ALT7
SS3
USBH1_DATA7
ALT1
MISO
NANDF_RB3
ALT2
MOSI
NANDF_D15
ALT2
RDY
NANDF_RB1
ALT2
SCLK
NANDF_RB2
ALT2
SS0
NANDF_RDY_INT
ALT2
SS1
NANDF_D12
ALT2
NANDF_RB0
ALT5
SS2
NANDF_D13
ALT2
SS3
NANDF_D14
ALT2
USBH1_DATA7
ALT5
ECSPI2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-70
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
UART1
UART2
Port
Mode
CTS
UART1_CTS
ALT0
DCD
KEY_COL5
ALT1
DSR
UART3_TXD
ALT0
DTR
UART3_RXD
ALT0
RI
KEY_COL4
ALT1
RTS
UART1_RTS
ALT0
RXD_MUX
UART1_RXD
ALT0
TXD_MUX
UART1_TXD
ALT0
CTS
EIM_D16
ALT3
EIM_D25
ALT4
USBH1_DATA0
ALT1
EIM_D19
ALT3
EIM_D26
ALT4
USBH1_DATA3
ALT1
EIM_D17
ALT3
UART2_RXD
ALT0
USBH1_DATA1
ALT1
EIM_D18
ALT3
UART2_TXD
ALT0
USBH1_DATA2
ALT1
RTS
UART2
Pad
RXD_MUX
TXD_MUX
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-71
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
Port
UART3
CTS
ALT4
EIM_D24
ALT3
KEY_COL5
ALT2
USBH1_CLK
ALT7
EIM_D18
ALT4
EIM_D27
ALT3
KEY_COL4
ALT2
USBH1_DIR
ALT7
AUD3_BB_RXD
ALT1
DISP2_DAT0
ALT5
EIM_D25
ALT3
UART3_RXD
ALT1
USBH1_STP
ALT5
AUD3_BB_FS
ALT1
DISP2_DAT1
ALT5
EIM_D26
ALT3
UART3_TXD
ALT1
USBH1_NXT
ALT5
GPIO1_2
ALT6
GPIO1_4
ALT7
GPIO1_7
ALT7
NANDF_RB3
ALT4
CTI_TRIGIN7
KEY_COL5
ALT5
CTI_TRIGIN_ACK7
KEY_COL4
ALT5
CTI_TRIGOUT6
OWIRE_LINE
ALT5
CTI_TRIGOUT7
KEY_COL3
ALT5
CTI_TRIGOUT_ACK6
DISP1_DAT22
ALT3
CTI_TRIGOUT_ACK7
DISP1_DAT23
ALT3
PMU_IRQ_B
PMIC_INT_REQ
ALT1
WDOG_B
GPIO1_4
ALT2
WDOG_RST_B_DEB
DISPB2_SER_DIO
ALT6
WDOG_B
GPIO1_5
ALT2
WDOG_RST_B_DEB
DISPB2_SER_CLK
ALT6
RXD_MUX
TXD_MUX
TOG_EN
TIGERP_PLATFORM_NE_32K_25
6K
WDOG1
WDOG2
Mode
EIM_D17
RTS
DPLLIP1
Pad
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-72
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
EMI
Port
Pad
Mode
DRAM_A[0]
DRAM_A0
No Muxing (ALT0)
DRAM_A[10]
DRAM_A10
No Muxing (ALT0)
DRAM_A[11]
DRAM_A11
No Muxing (ALT0)
DRAM_A[12]
DRAM_A12
No Muxing (ALT0)
DRAM_A[13]
DRAM_A13
No Muxing (ALT0)
DRAM_A[14]
DRAM_A14
No Muxing (ALT0)
DRAM_A[1]
DRAM_A1
No Muxing (ALT0)
DRAM_A[2]
DRAM_A2
No Muxing (ALT0)
DRAM_A[3]
DRAM_A3
No Muxing (ALT0)
DRAM_A[4]
DRAM_A4
No Muxing (ALT0)
DRAM_A[5]
DRAM_A5
No Muxing (ALT0)
DRAM_A[6]
DRAM_A6
No Muxing (ALT0)
DRAM_A[7]
DRAM_A7
No Muxing (ALT0)
DRAM_A[8]
DRAM_A8
No Muxing (ALT0)
DRAM_A[9]
DRAM_A9
No Muxing (ALT0)
DRAM_CAS
DRAM_CAS
No Muxing (ALT0)
DRAM_CS0
DRAM_CS0
No Muxing (ALT0)
DRAM_CS1
DRAM_CS1
ALT0
DRAM_DQM[0]
DRAM_DQM0
No Muxing (ALT0)
DRAM_DQM[1]
DRAM_DQM1
No Muxing (ALT0)
DRAM_DQM[2]
DRAM_DQM2
No Muxing (ALT0)
DRAM_DQM[3]
DRAM_DQM3
No Muxing (ALT0)
DRAM_D[0]
DRAM_D0
No Muxing (ALT0)
DRAM_D[10]
DRAM_D10
No Muxing (ALT0)
DRAM_D[11]
DRAM_D11
No Muxing (ALT0)
DRAM_D[12]
DRAM_D12
No Muxing (ALT0)
DRAM_D[13]
DRAM_D13
No Muxing (ALT0)
DRAM_D[14]
DRAM_D14
No Muxing (ALT0)
DRAM_D[15]
DRAM_D15
No Muxing (ALT0)
DRAM_D[16]
DRAM_D16
No Muxing (ALT0)
DRAM_D[17]
DRAM_D17
No Muxing (ALT0)
DRAM_D[18]
DRAM_D18
No Muxing (ALT0)
DRAM_D[19]
DRAM_D19
No Muxing (ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-73
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
DRAM_D[1]
DRAM_D1
No Muxing (ALT0)
DRAM_D[20]
DRAM_D20
No Muxing (ALT0)
DRAM_D[21]
DRAM_D21
No Muxing (ALT0)
DRAM_D[22]
DRAM_D22
No Muxing (ALT0)
DRAM_D[23]
DRAM_D23
No Muxing (ALT0)
DRAM_D[24]
DRAM_D24
No Muxing (ALT0)
DRAM_D[25]
DRAM_D25
No Muxing (ALT0)
DRAM_D[26]
DRAM_D26
No Muxing (ALT0)
DRAM_D[27]
DRAM_D27
No Muxing (ALT0)
DRAM_D[28]
DRAM_D28
No Muxing (ALT0)
DRAM_D[29]
DRAM_D29
No Muxing (ALT0)
DRAM_D[2]
DRAM_D2
No Muxing (ALT0)
DRAM_D[30]
DRAM_D30
No Muxing (ALT0)
DRAM_D[31]
DRAM_D31
No Muxing (ALT0)
DRAM_D[3]
DRAM_D3
No Muxing (ALT0)
DRAM_D[4]
DRAM_D4
No Muxing (ALT0)
DRAM_D[5]
DRAM_D5
No Muxing (ALT0)
DRAM_D[6]
DRAM_D6
No Muxing (ALT0)
DRAM_D[7]
DRAM_D7
No Muxing (ALT0)
DRAM_D[8]
DRAM_D8
No Muxing (ALT0)
DRAM_D[9]
DRAM_D9
No Muxing (ALT0)
DRAM_ODT0
EIM_SDODT0
No Muxing (ALT0)
DRAM_ODT1
EIM_SDODT1
No Muxing (ALT0)
DRAM_RAS
DRAM_RAS
No Muxing (ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-74
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
DRAM_SDBA[0]
EIM_SDBA0
No Muxing (ALT0)
DRAM_SDBA[1]
EIM_SDBA1
No Muxing (ALT0)
DRAM_SDBA[2]
EIM_SDBA2
No Muxing (ALT0)
DRAM_SDCKE[0]
DRAM_SDCKE0
No Muxing (ALT0)
DRAM_SDCKE[1]
DRAM_SDCKE1
No Muxing (ALT0)
DRAM_SDCLK
DRAM_SDCLK
No Muxing (ALT0)
DRAM_SDCLK_B
DRAM_SDCLK_B
No Muxing (ALT0)
DRAM_SDQS[0]
DRAM_SDQS0
No Muxing (ALT0)
DRAM_SDQS[1]
DRAM_SDQS1
No Muxing (ALT0)
DRAM_SDQS[2]
DRAM_SDQS2
No Muxing (ALT0)
DRAM_SDQS[3]
DRAM_SDQS3
No Muxing (ALT0)
DRAM_SDQS_B[0]
DRAM_SDQS0_B
No Muxing (ALT0)
DRAM_SDQS_B[1]
DRAM_SDQS1_B
No Muxing (ALT0)
DRAM_SDQS_B[2]
DRAM_SDQS2_B
No Muxing (ALT0)
DRAM_SDQS_B[3]
DRAM_SDQS3_B
No Muxing (ALT0)
DRAM_SDWE
DRAM_SDWE
No Muxing (ALT0)
DSTROBE
KEY_ROW0
ALT1
EIM_A[16]
EIM_A16
ALT0
EIM_A[17]
EIM_A17
ALT0
EIM_A[18]
EIM_A18
ALT0
EIM_A[19]
EIM_A19
ALT0
EIM_A[20]
EIM_A20
ALT0
EIM_A[21]
EIM_A21
ALT0
EIM_A[22]
EIM_A22
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-75
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
EIM_A[23]
EIM_A23
ALT0
EIM_A[24]
EIM_A24
ALT0
EIM_A[25]
EIM_A25
ALT0
EIM_A[26]
EIM_A26
ALT0
EIM_A[27]
EIM_A27
ALT0
EIM_BCLK
EIM_BCLK
No Muxing (ALT0)
EIM_CRE
EIM_CRE
ALT0
EIM_CS0
EIM_CS0
ALT0
EIM_CS1
EIM_CS1
ALT0
EIM_CS2
EIM_CS2
ALT0
EIM_CS3
EIM_CS3
ALT0
EIM_CS4
EIM_CS4
ALT0
EIM_CS5
EIM_CS5
ALT0
EIM_DA[0]
EIM_DA0
ALT0
EIM_DA[10]
EIM_DA10
ALT0
EIM_DA[11]
EIM_DA11
ALT0
EIM_DA[12]
EIM_DA12
ALT0
EIM_DA[13]
EIM_DA13
ALT0
EIM_DA[14]
EIM_DA14
ALT0
EIM_DA[15]
EIM_DA15
ALT0
EIM_DA[1]
EIM_DA1
ALT0
EIM_DA[2]
EIM_DA2
ALT0
EIM_DA[3]
EIM_DA3
ALT0
EIM_DA[4]
EIM_DA4
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-76
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
EIM_DA[5]
EIM_DA5
ALT0
EIM_DA[6]
EIM_DA6
ALT0
EIM_DA[7]
EIM_DA7
ALT0
EIM_DA[8]
EIM_DA8
ALT0
EIM_DA[9]
EIM_DA9
ALT0
EIM_EB[0]
EIM_EB0
ALT0
EIM_EB[1]
EIM_EB1
ALT0
EIM_EB[2]
EIM_EB2
ALT0
EIM_EB[3]
EIM_EB3
ALT0
EIM_LBA
EIM_LBA
ALT0
EIM_NFC_D[0]
NANDF_D0
ALT0
EIM_NFC_D[10]
NANDF_D10
ALT0
EIM_NFC_D[11]
NANDF_D11
ALT0
EIM_NFC_D[12]
NANDF_D12
ALT0
EIM_NFC_D[13]
NANDF_D13
ALT0
EIM_NFC_D[14]
NANDF_D14
ALT0
EIM_NFC_D[15]
NANDF_D15
ALT0
EIM_NFC_D[1]
NANDF_D1
ALT0
EIM_NFC_D[2]
NANDF_D2
ALT0
EIM_NFC_D[3]
NANDF_D3
ALT0
EIM_NFC_D[4]
NANDF_D4
ALT0
EIM_NFC_D[5]
NANDF_D5
ALT0
EIM_NFC_D[6]
NANDF_D6
ALT0
EIM_NFC_D[7]
NANDF_D7
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-77
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
EIM_NFC_D[8]
NANDF_D8
ALT0
EIM_NFC_D[9]
NANDF_D9
ALT0
EIM_OE
EIM_OE
ALT0
EIM_RW
EIM_RW
No Muxing (ALT0)
EIM_WAIT
EIM_WAIT
No Muxing (ALT0)
EMI_DEBUG[0]
USBH1_CLK
ALT6
EMI_DEBUG[10]
USBH1_DATA6
ALT6
EMI_DEBUG[11]
USBH1_DATA7
ALT6
EMI_DEBUG[12]
UART1_RXD
ALT6
EMI_DEBUG[13]
UART1_TXD
ALT6
EMI_DEBUG[14]
UART1_RTS
ALT6
EMI_DEBUG[15]
UART1_CTS
ALT6
EMI_DEBUG[16]
UART2_RXD
ALT6
EMI_DEBUG[17]
UART2_TXD
ALT6
EMI_DEBUG[18]
UART3_RXD
ALT6
EMI_DEBUG[19]
UART3_TXD
ALT6
EMI_DEBUG[1]
USBH1_DIR
ALT6
EMI_DEBUG[20]
KEY_ROW0
ALT6
EMI_DEBUG[21]
KEY_ROW1
ALT6
EMI_DEBUG[22]
KEY_ROW2
ALT6
EMI_DEBUG[23]
KEY_ROW3
ALT6
EMI_DEBUG[24]
DI1_PIN3
ALT6
EMI_DEBUG[25]
DI1_PIN2
ALT6
EMI_DEBUG[26]
DI_GP1
ALT6
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-78
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
EMI_DEBUG[27]
DI_GP2
ALT6
EMI_DEBUG[28]
DI_GP3
ALT6
EMI_DEBUG[29]
DI2_PIN4
ALT6
EMI_DEBUG[2]
USBH1_STP
ALT6
EMI_DEBUG[30]
DI2_PIN2
ALT6
EMI_DEBUG[31]
DI2_PIN3
ALT6
EMI_DEBUG[32]
DI_GP4
ALT6
EMI_DEBUG[33]
DISP2_DAT0
ALT6
EMI_DEBUG[34]
DISP2_DAT1
ALT6
EMI_DEBUG[35]
DISP2_DAT6
ALT6
EMI_DEBUG[36]
DISP2_DAT7
ALT6
EMI_DEBUG[37]
DISP2_DAT8
ALT6
EMI_DEBUG[38]
DISP2_DAT9
ALT6
EMI_DEBUG[39]
DISP2_DAT10
ALT6
EMI_DEBUG[3]
USBH1_NXT
ALT6
EMI_DEBUG[40]
DISP2_DAT11
ALT6
EMI_DEBUG[41]
DISP2_DAT12
ALT6
EMI_DEBUG[42]
DISP2_DAT13
ALT6
EMI_DEBUG[43]
DISP2_DAT14
ALT6
EMI_DEBUG[44]
DISP2_DAT15
ALT6
EMI_DEBUG[45]
CSI2_D13
ALT6
EMI_DEBUG[46]
CSI2_D18
ALT6
EMI_DEBUG[47]
CSI2_D19
ALT6
EMI_DEBUG[48]
CSI2_VSYNC
ALT6
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-79
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
Port
Pad
Mode
EMI_DEBUG[49]
CSI2_HSYNC
ALT6
EMI_DEBUG[4]
USBH1_DATA0
ALT6
EMI_DEBUG[50]
CSI2_PIXCLK
ALT6
EMI_DEBUG[5]
USBH1_DATA1
ALT6
EMI_DEBUG[6]
USBH1_DATA2
ALT6
EMI_DEBUG[7]
USBH1_DATA3
ALT6
EMI_DEBUG[8]
USBH1_DATA4
ALT6
EMI_DEBUG[9]
USBH1_DATA5
ALT6
NANDF_ALE
NANDF_ALE
ALT0
NANDF_CLE
NANDF_CLE
ALT0
NANDF_CS0
NANDF_CS0
ALT0
NANDF_CS1
NANDF_CS1
ALT0
NANDF_CS2
NANDF_CS2
ALT0
NANDF_CS3
NANDF_CS3
ALT0
NANDF_CS4
NANDF_CS4
ALT0
NANDF_CS5
NANDF_CS5
ALT0
NANDF_CS6
NANDF_CS6
ALT0
NANDF_CS7
NANDF_CS7
ALT0
NANDF_RB0
NANDF_RB0
ALT0
NANDF_RB1
NANDF_RB1
ALT0
NANDF_RB2
NANDF_RB2
ALT0
NANDF_RB3
NANDF_RB3
ALT0
NANDF_RE_B
NANDF_RE_B
ALT0
NANDF_WE_B
NANDF_WE_B
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-80
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
EMI
IPU
Port
Pad
Mode
NANDF_WP_B
NANDF_WP_B
ALT0
RDY
GPIO1_4
ALT3
NANDF_RDY_INT
ALT0
WEIM_DTACK_B
EIM_DTACK
ALT0
WEIM_D[16]
EIM_D16
ALT0
WEIM_D[17]
EIM_D17
ALT0
WEIM_D[18]
EIM_D18
ALT0
WEIM_D[19]
EIM_D19
ALT0
WEIM_D[20]
EIM_D20
ALT0
WEIM_D[21]
EIM_D21
ALT0
WEIM_D[22]
EIM_D22
ALT0
WEIM_D[23]
EIM_D23
ALT0
WEIM_D[24]
EIM_D24
ALT0
WEIM_D[25]
EIM_D25
ALT0
WEIM_D[26]
EIM_D26
ALT0
WEIM_D[27]
EIM_D27
ALT0
WEIM_D[28]
EIM_D28
ALT0
WEIM_D[29]
EIM_D29
ALT0
WEIM_D[30]
EIM_D30
ALT0
WEIM_D[31]
EIM_D31
ALT0
DI1_D0_CS
DI1_D0_CS
ALT0
DI1_D1_CS
DI1_D1_CS
ALT0
DI1_DISP_CLK
DI1_DISP_CLK
No Muxing (ALT0)
DI1_PIN11
DI1_PIN11
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-81
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
IPU
Port
Pad
Mode
DI1_PIN12
DI1_PIN12
ALT0
DI1_PIN13
DI1_PIN13
ALT0
DI1_PIN14
DI1_D1_CS
ALT2
DI1_PIN15
DI1_PIN15
No Muxing (ALT0)
DI1_PIN16
DISPB2_SER_RS
ALT2
DI1_PIN17
DISPB2_SER_CLK
ALT2
DI1_PIN2
DI1_PIN2
ALT0
DI1_PIN3
DI1_PIN3
ALT0
DI1_PIN4
EIM_A25
ALT6
DI1_PIN5
DI1_D1_CS
ALT3
DI1_PIN6
DISPB2_SER_DIO
ALT3
DI1_PIN7
DISPB2_SER_CLK
ALT3
DI1_PIN8
DISPB2_SER_RS
ALT3
DI2_D0_CS
DISP1_DAT22
ALT6
DI2_D1_CS
DISP1_DAT23
ALT6
GPIO1_9
ALT2
DI2_DISP_CLK
DI2_DISP_CLK
ALT0
DI2_PIN11
DISP1_DAT18
ALT5
DI2_PIN12
DISP1_DAT19
ALT5
DI2_PIN13
DISP1_DAT20
ALT5
DI2_PIN14
DISP1_DAT21
ALT5
DI2_PIN15
DI_GP4
ALT4
DI2_PIN16
GPIO1_5
ALT3
DI2_PIN17
GPIO1_6
ALT4
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-82
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
IPU
Port
Pad
Mode
DI2_PIN2
DI2_PIN2
ALT0
DI2_PIN3
DI2_PIN3
ALT0
DI2_PIN4
DI2_PIN4
ALT0
DI2_PIN5
DISP1_DAT18
ALT4
DI2_PIN6
DISP1_DAT19
ALT4
DI2_PIN7
DISP1_DAT20
ALT4
DI2_PIN8
DISP1_DAT21
ALT4
DISP1_DAT[0]
DISP1_DAT0
No Muxing (ALT0)
DISP1_DAT[10]
DISP1_DAT10
ALT0
DISP1_DAT[11]
DISP1_DAT11
ALT0
DISP1_DAT[12]
DISP1_DAT12
ALT0
DISP1_DAT[13]
DISP1_DAT13
ALT0
DISP1_DAT[14]
DISP1_DAT14
ALT0
DISP1_DAT[15]
DISP1_DAT15
ALT0
DISP1_DAT[16]
DISP1_DAT16
ALT0
DISP1_DAT[17]
DISP1_DAT17
ALT0
DISP1_DAT[18]
DISP1_DAT18
ALT0
DISP1_DAT[19]
DISP1_DAT19
ALT0
DISP1_DAT[1]
DISP1_DAT1
No Muxing (ALT0)
DISP1_DAT[20]
DISP1_DAT20
ALT0
DISP1_DAT[21]
DISP1_DAT21
ALT0
DISP1_DAT[22]
DISP1_DAT22
ALT0
DISP1_DAT[23]
DISP1_DAT23
ALT0
DISP1_DAT[2]
DISP1_DAT2
No Muxing (ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-83
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
IPU
Port
Pad
Mode
DISP1_DAT[3]
DISP1_DAT3
No Muxing (ALT0)
DISP1_DAT[4]
DISP1_DAT4
No Muxing (ALT0)
DISP1_DAT[5]
DISP1_DAT5
No Muxing (ALT0)
DISP1_DAT[6]
DISP1_DAT6
ALT0
DISP1_DAT[7]
DISP1_DAT7
ALT0
DISP1_DAT[8]
DISP1_DAT8
ALT0
DISP1_DAT[9]
DISP1_DAT9
ALT0
DISP2_DAT[0]
DISP2_DAT0
ALT0
DISP2_DAT[10]
DISP2_DAT10
ALT0
DISP2_DAT[11]
DISP2_DAT11
ALT0
DISP2_DAT[12]
DISP2_DAT12
ALT0
DISP2_DAT[13]
DISP2_DAT13
ALT0
DISP2_DAT[14]
DISP2_DAT14
ALT0
DISP2_DAT[15]
DISP2_DAT15
ALT0
DISP2_DAT[16]
DISP1_DAT22
ALT5
DISP2_DAT[17]
DISP1_DAT23
ALT5
DISP2_DAT[1]
DISP2_DAT1
ALT0
DISP2_DAT[2]
DISP2_DAT2
No Muxing (ALT0)
DISP2_DAT[3]
DISP2_DAT3
No Muxing (ALT0)
DISP2_DAT[4]
DISP2_DAT4
No Muxing (ALT0)
DISP2_DAT[5]
DISP2_DAT5
No Muxing (ALT0)
DISP2_DAT[6]
DISP2_DAT6
ALT0
DISP2_DAT[7]
DISP2_DAT7
ALT0
DISP2_DAT[8]
DISP2_DAT8
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-84
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
IPU
Port
Pad
Mode
DISP2_DAT[9]
DISP2_DAT9
ALT0
DISPB1_SER_CLK
DI_GP2
ALT0
DISPB1_SER_DIN
DI_GP4
ALT0
DISPB1_SER_DIO
DI_GP3
ALT0
DISPB1_SER_RS
DI_GP1
ALT0
DISPB2_SER_CLK
DISPB2_SER_CLK
ALT0
DISPB2_SER_DIN
DISPB2_SER_DIN
ALT0
DISPB2_SER_DIO
DISPB2_SER_DIO
ALT0
DISPB2_SER_RS
DISPB2_SER_RS
ALT0
IPU_DIAG_BUS[0]
NANDF_D15
ALT6
IPU_DIAG_BUS[10]
NANDF_D5
ALT6
IPU_DIAG_BUS[11]
NANDF_D4
ALT6
IPU_DIAG_BUS[12]
NANDF_D3
ALT6
IPU_DIAG_BUS[13]
NANDF_D2
ALT6
IPU_DIAG_BUS[14]
NANDF_D1
ALT6
IPU_DIAG_BUS[15]
NANDF_D0
ALT6
IPU_DIAG_BUS[1]
NANDF_D14
ALT6
IPU_DIAG_BUS[2]
NANDF_D13
ALT6
IPU_DIAG_BUS[3]
NANDF_D12
ALT6
IPU_DIAG_BUS[4]
NANDF_D11
ALT6
IPU_DIAG_BUS[5]
NANDF_D10
ALT6
IPU_DIAG_BUS[6]
NANDF_D9
ALT6
IPU_DIAG_BUS[7]
NANDF_D8
ALT6
IPU_DIAG_BUS[8]
NANDF_D7
ALT6
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-85
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
IPU
Port
Mode
IPU_DIAG_BUS[9]
NANDF_D6
ALT6
SER_DISP1_CS
DISP2_DAT15
ALT5
SER_DISP2_CS
DISP1_DAT23
ALT4
DISP2_DAT10
ALT5
GPIO1_9
ALT7
EIM_A26
ALT4
EIM_D28
ALT4
EIM_A27
ALT4
EIM_D29
ALT4
EIM_D30
ALT4
EIM_EB2
ALT4
EIM_D31
ALT4
EIM_EB3
ALT4
EIM_CS1
ALT4
EIM_D17
ALT5
EIM_CS2
ALT4
EIM_D18
ALT5
SNOOP2
KEY_COL2
ALT1
DEBUG_BUS_DEVICE[0]
USBH1_DATA3
ALT4
DEBUG_BUS_DEVICE[1]
USBH1_DATA4
ALT4
DEBUG_BUS_DEVICE[2]
USBH1_DATA5
ALT4
DEBUG_BUS_DEVICE[3]
USBH1_DATA6
ALT4
DEBUG_BUS_DEVICE[4]
USBH1_DATA7
ALT4
DEBUG_BUS_ERROR
CSI2_VSYNC
ALT4
SISG[0]
SISG[1]
SISG[2]
SISG[3]
SISG[4]
SISG[5]
SDMA
Pad
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-86
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
SDMA
Port
Pad
Mode
DEBUG_BUS_RWB
USBH1_NXT
ALT4
DEBUG_CORE_RUN
USBH1_CLK
ALT4
DEBUG_CORE_STATE[0]
NANDF_D1
ALT4
DEBUG_CORE_STATE[1]
NANDF_D0
ALT4
DEBUG_CORE_STATE[2]
USBH1_DATA0
ALT4
DEBUG_CORE_STATE[3]
USBH1_DATA1
ALT4
DEBUG_EVENT_CHANNEL[0]
NANDF_CS5
ALT4
DEBUG_EVENT_CHANNEL[1]
NANDF_CS6
ALT4
DEBUG_EVENT_CHANNEL[2]
NANDF_CS7
ALT4
DEBUG_EVENT_CHANNEL[3]
NANDF_RDY_INT
ALT4
DEBUG_EVENT_CHANNEL[4]
NANDF_RB0
ALT4
DEBUG_EVENT_CHANNEL[5]
NANDF_CS1
ALT4
DEBUG_EVENT_CHANNEL_SEL USBH1_STP
ALT4
DEBUG_EVT_CHN_LINES[0]
NANDF_WE_B
ALT4
DEBUG_EVT_CHN_LINES[1]
NANDF_RE_B
ALT4
DEBUG_EVT_CHN_LINES[2]
NANDF_ALE
ALT4
DEBUG_EVT_CHN_LINES[3]
NANDF_CLE
ALT4
DEBUG_EVT_CHN_LINES[4]
NANDF_WP_B
ALT4
DEBUG_EVT_CHN_LINES[5]
NANDF_CS2
ALT4
DEBUG_EVT_CHN_LINES[6]
NANDF_CS3
ALT4
DEBUG_EVT_CHN_LINES[7]
NANDF_CS4
ALT4
DEBUG_MATCHED_DMBUS
USBH1_DATA2
ALT4
DEBUG_MODE
USBH1_DIR
ALT4
DEBUG_PC[0]
NANDF_D15
ALT4
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-87
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
SDMA
FEC
Port
Pad
Mode
DEBUG_PC[10]
NANDF_D5
ALT4
DEBUG_PC[11]
NANDF_D4
ALT4
DEBUG_PC[12]
NANDF_D3
ALT4
DEBUG_PC[13]
NANDF_D2
ALT4
DEBUG_PC[1]
NANDF_D14
ALT4
DEBUG_PC[2]
NANDF_D13
ALT4
DEBUG_PC[3]
NANDF_D12
ALT4
DEBUG_PC[4]
NANDF_D11
ALT4
DEBUG_PC[5]
NANDF_D10
ALT4
DEBUG_PC[6]
NANDF_D9
ALT4
DEBUG_PC[7]
NANDF_D8
ALT4
DEBUG_PC[8]
NANDF_D7
ALT4
DEBUG_PC[9]
NANDF_D6
ALT4
DEBUG_RTBUFFER_WRITE
CSI2_D18
ALT4
DEBUG_YIELD
CSI2_D19
ALT4
SDMA_EXT_EVENT[0]
GPIO1_4
ALT1
SDMA_EXT_EVENT[1]
GPIO1_5
ALT1
COL
DISP2_DAT10
ALT2
NANDF_RB2
ALT1
DI2_PIN4
ALT2
EIM_CS5
ALT3
DI2_PIN2
ALT2
NANDF_CS3
ALT2
DI2_PIN3
ALT2
CRS
MDC
MDIO
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-88
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
FEC
Port
Mode
MDIO
EIM_EB2
ALT3
RDATA[0]
DISP2_DAT14
ALT2
NANDF_D9
ALT2
DI2_DISP_CLK
ALT2
EIM_EB3
ALT3
DI_GP4
ALT2
EIM_CS2
ALT3
DISP2_DAT0
ALT2
EIM_CS3
ALT3
DISP2_DAT11
ALT2
NANDF_RB3
ALT1
DISP2_DAT12
ALT2
NANDF_D11
ALT2
DISP2_DAT1
ALT2
EIM_CS4
ALT3
DISP2_DAT15
ALT2
NANDF_D8
ALT2
DISP2_DAT6
ALT2
NANDF_CS4
ALT2
DISP2_DAT7
ALT2
NANDF_CS5
ALT2
DISP2_DAT8
ALT2
NANDF_CS6
ALT2
TX_CLK
DISP2_DAT13
ALT2
TX_CLK
NANDF_RDY_INT
ALT1
TX_EN
DISP2_DAT9
ALT2
NANDF_CS7
ALT1
DI_GP3
ALT2
NANDF_CS2
ALT2
RDATA[1]
RDATA[2]
RDATA[3]
RX_CLK
RX_DV
RX_ER
TDATA[0]
TDATA[1]
TDATA[2]
TDATA[3]
FEC
Pad
TX_ER
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-89
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
PATA
PATA
FIRI
Port
Pad
Mode
BUFFER_EN
NANDF_ALE
ALT1
CS_0
NANDF_CS2
ALT1
CS_1
NANDF_CS3
ALT1
DA_0
NANDF_CS4
ALT1
DA_1
NANDF_CS5
ALT1
DA_2
NANDF_CS6
ALT1
DIOR
NANDF_RE_B
ALT1
DIOW
NANDF_WE_B
ALT1
DMACK
NANDF_WP_B
ALT1
DMARQ
NANDF_RB0
ALT1
INTRQ
GPIO_NAND
ALT1
IORDY
NANDF_RB1
ALT1
PATA_DATA[0]
NANDF_D0
ALT1
PATA_DATA[10]
NANDF_D10
ALT1
PATA_DATA[11]
NANDF_D11
ALT1
PATA_DATA[12]
NANDF_D12
ALT1
PATA_DATA[13]
NANDF_D13
ALT1
PATA_DATA[14]
NANDF_D14
ALT1
PATA_DATA[15]
NANDF_D15
ALT1
PATA_DATA[1]
NANDF_D1
ALT1
PATA_DATA[2]
NANDF_D2
ALT1
PATA_DATA[3]
NANDF_D3
ALT1
PATA_DATA[4]
NANDF_D4
ALT1
PATA_DATA[5]
NANDF_D5
ALT1
PATA_DATA[6]
NANDF_D6
ALT1
PATA_DATA[7]
NANDF_D7
ALT1
PATA_DATA[8]
NANDF_D8
ALT1
PATA_DATA[9]
NANDF_D9
ALT1
PATA_RESET_B
NANDF_CLE
ALT1
RXD
UART2_TXD
ALT1
TXD
UART2_RXD
ALT1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-90
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
CCM
Port
Mode
CCM_OUT_0
GPIO1_7
ALT3
CCM_OUT_1
GPIO1_9
ALT3
CCM_OUT_2
GPIO1_2
ALT5
CKIL
CKIL
No Muxing (ALT0)
CLKO
DRAM_CS1
ALT1
GPIO1_5
ALT5
GPIO1_9
ALT4
GPIO1_3
ALT5
GPIO1_8
ALT4
CLKSS
CLK_SS
No Muxing (ALT0)
CSI1_MCLK
CSI1_MCLK
No Muxing (ALT0)
CSI2_MCLK
GPIO1_5
ALT6
DI1_EXT_CLK
DI_GP1
ALT2
EIM_CS5
ALT4
EIM_A26
ALT6
GPIO1_4
ALT4
GPIO1_2
ALT7
KEY_COL0
ALT7
GPIO1_3
ALT7
KEY_COL1
ALT7
PLL3_BYP
KEY_COL2
ALT7
PMIC_VSTBY_REQ
PMIC_STBY_REQ
No Muxing (ALT0)
REF_EN_B
GPIO1_6
ALT3
SSI_EXT1_CLK
EIM_CS4
ALT4
GPIO1_7
ALT1
KEY_COL5
ALT4
EIM_CS3
ALT4
GPIO1_6
ALT1
KEY_COL4
ALT4
CLKO2
CCM
Pad
DI2_EXT_CLK
PLL1_BYP
PLL2_BYP
SSI_EXT2_CLK
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-91
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPT
GPT
KPP
Port
Mode
CAPIN1
GPIO1_4
ALT6
CAPIN2
GPIO1_6
ALT6
CLKIN
GPIO1_3
ALT6
CMPOUT1
EIM_D25
ALT5
EIM_EB2
ALT7
EIM_D26
ALT5
EIM_EB3
ALT7
NANDF_RB1
ALT4
CMPOUT3
NANDF_RB2
ALT4
COL[0]
KEY_COL0
ALT0
COL[1]
KEY_COL1
ALT0
COL[2]
KEY_COL2
ALT0
COL[3]
KEY_COL3
ALT0
COL[4]
KEY_COL4
ALT0
COL[5]
KEY_COL5
ALT0
COL[6]
DISP2_DAT0
ALT4
EIM_D25
ALT1
DISP2_DAT1
ALT4
EIM_D26
ALT1
ROW[0]
KEY_ROW0
ALT0
ROW[1]
KEY_ROW1
ALT0
ROW[2]
KEY_ROW2
ALT0
ROW[3]
KEY_ROW3
ALT0
ROW[4]
DISP2_DAT6
ALT4
EIM_D28
ALT1
DISP2_DAT7
ALT4
EIM_D29
ALT1
DISP2_DAT8
ALT4
EIM_D30
ALT1
DISP2_DAT10
ALT4
EIM_D31
ALT1
CMPOUT2
COL[7]
ROW[5]
ROW[6]
KPP
Pad
ROW[7]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-92
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
I2C1
Port
SCL
ALT1
EIM_D19
ALT4
SD2_CMD
ALT1
CSPI1_MOSI
ALT1
EIM_D16
ALT4
SD2_CLK
ALT1
EIM_D27
ALT4
GPIO1_2
ALT2
KEY_COL4
ALT3
USBH1_CLK
ALT5
EIM_D24
ALT4
GPIO1_3
ALT2
KEY_COL5
ALT3
USBH1_DIR
ALT5
EIM_D23
ALT4
GPIO1_7
ALT2
KEY_COL4
ALT6
OWIRE_LINE
ALT6
GPIO[0]
GPIO1_0
ALT1
GPIO[10]
DISP2_DAT11
ALT7
GPIO[11]
USBH1_DATA0
ALT2
GPIO[12]
USBH1_DATA1
ALT2
SCL
SDA
SPDIF
GPIO1
Mode
CSPI1_SCLK
SDA
I2C2
Pad
OUT1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-93
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPIO1
GPIO1
Port
Pad
Mode
GPIO[13]
USBH1_DATA2
ALT2
GPIO[14]
USBH1_DATA3
ALT2
GPIO[15]
USBH1_DATA4
ALT2
GPIO[16]
USBH1_DATA5
ALT2
GPIO[17]
USBH1_DATA6
ALT2
GPIO[18]
USBH1_DATA7
ALT2
GPIO[19]
DISP2_DAT6
ALT5
GPIO[1]
GPIO1_1
ALT1
GPIO[20]
UART2_RXD
ALT3
GPIO[21]
UART2_TXD
ALT3
GPIO[22]
UART3_RXD
ALT3
GPIO[23]
UART3_TXD
ALT3
GPIO[24]
OWIRE_LINE
ALT3
GPIO[25]
USBH1_CLK
ALT2
GPIO[26]
USBH1_DIR
ALT2
GPIO[27]
USBH1_STP
ALT2
GPIO[28]
USBH1_NXT
ALT2
GPIO[29]
DISP2_DAT7
ALT5
GPIO[2]
GPIO1_2
ALT0
GPIO[30]
DISP2_DAT8
ALT5
GPIO[31]
DISP2_DAT9
ALT5
GPIO[3]
GPIO1_3
ALT0
GPIO[4]
GPIO1_4
ALT0
GPIO[5]
GPIO1_5
ALT0
GPIO[6]
GPIO1_6
ALT0
GPIO[7]
GPIO1_7
ALT0
GPIO[8]
GPIO1_8
ALT0
GPIO[9]
GPIO1_9
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-94
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPIO2
GPIO2
Port
Pad
Mode
GPIO[0]
EIM_D16
ALT1
GPIO[10]
EIM_A16
ALT1
GPIO[11]
EIM_A17
ALT1
GPIO[12]
EIM_A18
ALT1
GPIO[13]
EIM_A19
ALT1
GPIO[14]
EIM_A20
ALT1
GPIO[15]
EIM_A21
ALT1
GPIO[16]
EIM_A22
ALT1
GPIO[17]
EIM_A23
ALT1
GPIO[18]
EIM_A24
ALT1
GPIO[19]
EIM_A25
ALT1
GPIO[1]
EIM_D17
ALT1
GPIO[20]
EIM_A26
ALT1
GPIO[21]
EIM_A27
ALT1
GPIO[22]
EIM_EB2
ALT1
GPIO[23]
EIM_EB3
ALT1
GPIO[24]
EIM_OE
ALT1
GPIO[25]
EIM_CS0
ALT1
GPIO[26]
EIM_CS1
ALT1
GPIO[27]
EIM_CS2
ALT1
GPIO[28]
EIM_CS3
ALT1
GPIO[29]
EIM_CS4
ALT1
GPIO[2]
EIM_D18
ALT1
GPIO[30]
EIM_CS5
ALT1
GPIO[31]
EIM_DTACK
ALT1
GPIO[3]
EIM_D19
ALT1
GPIO[4]
EIM_D20
ALT1
GPIO[5]
EIM_D21
ALT1
GPIO[6]
EIM_D22
ALT1
GPIO[7]
EIM_D23
ALT1
GPIO[8]
EIM_D24
ALT1
GPIO[9]
EIM_D27
ALT1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-95
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPIO3
Port
Pad
Mode
GPIO[0]
DI1_PIN11
ALT4
GPIO[10]
NANDF_RB2
ALT3
GPIO[11]
NANDF_RB3
ALT3
GPIO[12]
CSI1_D8
ALT3
GPIO_NAND
ALT0
GPIO[13]
CSI1_D9
ALT3
GPIO[14]
CSI1_VSYNC
ALT3
GPIO[15]
CSI1_HSYNC
ALT3
GPIO[16]
NANDF_CS0
ALT3
GPIO[17]
NANDF_CS1
ALT3
GPIO[18]
NANDF_CS2
ALT3
GPIO[19]
NANDF_CS3
ALT3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-96
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPIO3
Port
GPIO[1]
Mode
DI1_PIN12
ALT4
EIM_LBA
ALT1
GPIO[20]
NANDF_CS4
ALT3
GPIO[21]
NANDF_CS5
ALT3
GPIO[22]
NANDF_CS6
ALT3
GPIO[23]
NANDF_CS7
ALT3
GPIO[24]
NANDF_RDY_INT
ALT3
GPIO[25]
NANDF_D15
ALT3
GPIO[26]
NANDF_D14
ALT3
GPIO[27]
NANDF_D13
ALT3
GPIO[28]
NANDF_D12
ALT3
GPIO[29]
NANDF_D11
ALT3
GPIO[2]
DI1_PIN13
ALT4
EIM_CRE
ALT1
GPIO[30]
NANDF_D10
ALT3
GPIO[31]
NANDF_D9
ALT3
GPIO[3]
DI1_D0_CS
ALT4
NANDF_WE_B
ALT3
DI1_D1_CS
ALT4
NANDF_RE_B
ALT3
DISPB2_SER_DIN
ALT4
NANDF_ALE
ALT3
DISPB2_SER_DIO
ALT4
NANDF_CLE
ALT3
DISPB2_SER_CLK
ALT4
NANDF_WP_B
ALT3
DISPB2_SER_RS
ALT4
NANDF_RB0
ALT3
NANDF_RB1
ALT3
GPIO[4]
GPIO[5]
GPIO[6]
GPIO3
Pad
GPIO[7]
GPIO[8]
GPIO[9]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-97
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPIO4
GPIO4
Port
Pad
Mode
GPIO[0]
NANDF_D8
ALT3
GPIO[10]
CSI2_D13
ALT3
GPIO[11]
CSI2_D18
ALT3
GPIO[12]
CSI2_D19
ALT3
GPIO[13]
CSI2_VSYNC
ALT3
GPIO[14]
CSI2_HSYNC
ALT3
GPIO[15]
CSI2_PIXCLK
ALT3
GPIO[16]
I2C1_CLK
ALT3
GPIO[17]
I2C1_DAT
ALT3
GPIO[18]
AUD3_BB_TXD
ALT3
GPIO[19]
AUD3_BB_RXD
ALT3
GPIO[1]
NANDF_D7
ALT3
GPIO[20]
AUD3_BB_CK
ALT3
GPIO[21]
AUD3_BB_FS
ALT3
GPIO[22]
CSPI1_MOSI
ALT3
GPIO[23]
CSPI1_MISO
ALT3
GPIO[24]
CSPI1_SS0
ALT3
GPIO[25]
CSPI1_SS1
ALT3
GPIO[26]
CSPI1_RDY
ALT3
GPIO[27]
CSPI1_SCLK
ALT3
GPIO[28]
UART1_RXD
ALT3
GPIO[29]
UART1_TXD
ALT3
GPIO[2]
NANDF_D6
ALT3
GPIO[30]
UART1_RTS
ALT3
GPIO[31]
UART1_CTS
ALT3
GPIO[3]
NANDF_D5
ALT3
GPIO[4]
NANDF_D4
ALT3
GPIO[5]
NANDF_D3
ALT3
GPIO[6]
NANDF_D2
ALT3
GPIO[7]
NANDF_D1
ALT3
GPIO[8]
NANDF_D0
ALT3
GPIO[9]
CSI2_D12
ALT3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-98
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
SJC
Port
Pad
Mode
DE_B
JTAG_DE_B
No Muxing (ALT0)
DONE
KEY_ROW2
ALT5
FAIL
KEY_ROW3
ALT5
JTAG_ACT
KEY_COL5
ALT7
MOD
JTAG_MOD
No Muxing (ALT0)
TCK
JTAG_TCK
No Muxing (ALT0)
TDI
JTAG_TDI
No Muxing (ALT0)
TDO
JTAG_TDO
No Muxing (ALT0)
TMS
JTAG_TMS
No Muxing (ALT0)
TRSTB
JTAG_TRSTB
No Muxing (ALT0)
CAMP1
CKIH
CKIH1
No Muxing (ALT0)
CAMP2
CKIH
CKIH2
No Muxing (ALT0)
CSPI
MISO
GPIO1_1
ALT2
SD1_DATA0
ALT2
SD2_DATA0
ALT2
USBH1_NXT
ALT1
NANDF_RB1
ALT6
SD1_CMD
ALT2
SD2_CMD
ALT2
USBH1_DIR
ALT1
RDY
USBH1_STP
ALT1
SCLK
NANDF_CS2
ALT6
SD1_CLK
ALT2
SD2_CLK
ALT2
USBH1_CLK
ALT1
SS0
USBH1_DATA4
ALT1
SS1
SD1_DATA3
ALT2
USBH1_DATA5
ALT1
GPIO1_0
ALT2
SD2_DATA3
ALT2
NANDF_CS6
ALT7
USBH1_DATA6
ALT1
MOSI
SS2
SS3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-99
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
SRC
SRC
SRC
Port
Pad
Mode
ANY_PU_RST
KEY_COL4
ALT7
BOOT_MODE[0]
BOOT_MODE0
No Muxing (ALT0)
BOOT_MODE[1]
BOOT_MODE1
No Muxing (ALT0)
BT_BUS_WIDTH
DISP1_DAT15
ALT7
BT_EEPROM_CFG
DISP1_DAT7
ALT7
BT_HPN_EN
EIM_A23
ALT7
BT_LPB[0]
EIM_A18
ALT7
BT_LPB[1]
EIM_A19
ALT7
BT_LPB_FREQ[0]
DISP1_DAT22
ALT7
BT_LPB_FREQ[1]
DISP1_DAT23
ALT7
BT_LPB_FREQ[2]
DISP1_DAT11
ALT7
BT_MEM_CTL[0]
DISP1_DAT13
ALT7
BT_MEM_CTL[1]
DISP1_DAT14
ALT7
BT_MEM_TYPE[0]
DISP1_DAT20
ALT7
BT_MEM_TYPE[1]
DISP1_DAT21
ALT7
BT_MLC_SEL
DISP1_DAT12
ALT7
BT_PAGE_SIZE[0]
DISP1_DAT16
ALT7
BT_PAGE_SIZE[1]
DISP1_DAT17
ALT7
BT_SPARE_SIZE
DISP1_DAT10
ALT7
BT_SRC[0]
DISP1_DAT8
ALT7
BT_SRC[1]
DISP1_DAT9
ALT7
BT_UART_SRC[0]
EIM_A20
ALT7
BT_UART_SRC[1]
EIM_A21
ALT7
BT_USB_SRC
DISP1_DAT6
ALT7
BT_WEIM_MUXED[0]
DISP1_DAT18
ALT7
BT_WEIM_MUXED[1]
DISP1_DAT19
ALT7
INT_BOOT
KEY_COL3
ALT7
OSC_FREQ_SEL[0]
EIM_A16
ALT7
OSC_FREQ_SEL[1]
EIM_A17
ALT7
POR_B
POR_B
No Muxing (ALT0)
RESET_B
RESET_IN_B
No Muxing (ALT0)
SYSTEM_RST
OWIRE_LINE
ALT7
TESTER_ACK
GPIO1_8
ALT7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-100
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
ELVIS_OBSERVE_MUX
Port
OBSRV_INT_OUT0
ALT2
EIM_D28
ALT3
CSI2_D19
ALT2
EIM_D29
ALT3
CSI2_VSYNC
ALT2
EIM_D30
ALT3
CSI2_HSYNC
ALT2
EIM_D31
ALT3
CSI2_PIXCLK
ALT2
EIM_A27
ALT3
CLK0
NANDF_CS4
ALT6
PD0
NANDF_CS3
ALT6
RST0
NANDF_CS5
ALT6
RX0
NANDF_RDY_INT
ALT6
SIM_RCV_CLK_TEST
DI1_PIN2
ALT7
SIM_TX_CLK_TEST
DI1_PIN3
ALT7
TX0
NANDF_CS7
ALT6
VEN0
NANDF_CS6
ALT6
TRACE[0]
EIM_D16
ALT6
TRACE[10]
EIM_D26
ALT6
TRACE[11]
EIM_D27
ALT6
TRACE[12]
EIM_D28
ALT6
OBSRV_INT_OUT2
OBSRV_INT_OUT3
OBSRV_INT_OUT4
TPIU
Mode
CSI2_D18
OBSRV_INT_OUT1
SIM
Pad
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-101
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
TPIU
TPIU
Port
Pad
Mode
TRACE[13]
EIM_D29
ALT6
TRACE[14]
EIM_D30
ALT6
TRACE[15]
EIM_D31
ALT6
TRACE[16]
EIM_DA0
ALT1
TRACE[17]
EIM_DA1
ALT1
TRACE[18]
EIM_DA2
ALT1
TRACE[19]
EIM_DA3
ALT1
TRACE[1]
EIM_D17
ALT6
TRACE[20]
EIM_DA4
ALT1
TRACE[21]
EIM_DA5
ALT1
TRACE[22]
EIM_DA6
ALT1
TRACE[23]
EIM_DA7
ALT1
TRACE[24]
EIM_DA8
ALT1
TRACE[25]
EIM_DA9
ALT1
TRACE[26]
EIM_DA10
ALT1
TRACE[27]
EIM_DA11
ALT1
TRACE[28]
EIM_DA12
ALT1
TRACE[29]
EIM_DA13
ALT1
TRACE[2]
EIM_D18
ALT6
TRACE[30]
EIM_DA14
ALT1
TRACE[31]
EIM_DA15
ALT1
TRACE[3]
EIM_D19
ALT6
TRACE[4]
EIM_D20
ALT6
TRACE[5]
EIM_D21
ALT6
TRACE[6]
EIM_D22
ALT6
TRACE[7]
EIM_D23
ALT6
TRACE[8]
EIM_D24
ALT6
TRACE[9]
EIM_D25
ALT6
TRCLK
EIM_EB3
ALT2
TRCTL
EIM_EB2
ALT2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-102
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
GPU3D
PWM1
Port
Pad
Mode
GPU_DEBUG_OUT[0]
NANDF_D15
ALT7
GPU_DEBUG_OUT[10]
NANDF_D5
ALT7
GPU_DEBUG_OUT[11]
NANDF_D4
ALT7
GPU_DEBUG_OUT[12]
NANDF_D3
ALT7
GPU_DEBUG_OUT[13]
NANDF_D2
ALT7
GPU_DEBUG_OUT[14]
NANDF_D1
ALT7
GPU_DEBUG_OUT[15]
NANDF_D0
ALT7
GPU_DEBUG_OUT[1]
NANDF_D14
ALT7
GPU_DEBUG_OUT[2]
NANDF_D13
ALT7
GPU_DEBUG_OUT[3]
NANDF_D12
ALT7
GPU_DEBUG_OUT[4]
NANDF_D11
ALT7
GPU_DEBUG_OUT[5]
NANDF_D10
ALT7
GPU_DEBUG_OUT[6]
NANDF_D9
ALT7
GPU_DEBUG_OUT[7]
NANDF_D8
ALT7
GPU_DEBUG_OUT[8]
NANDF_D7
ALT7
GPU_DEBUG_OUT[9]
NANDF_D6
ALT7
PWMO
GPIO1_2
ALT1
GPIO1_3
ALT1
PWM2
PWM2
PWMO
UART1_TXD
ALT1
OWIRE
LINE
OWIRE_LINE
ALT0
EPIT1
EPITO
GPIO1_7
ALT5
GPIO1_6
ALT5
EPIT2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-103
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
USBPHY
Port
Pad
Mode
AVALID
EIM_D26
ALT7
BISTOK
USBH1_STP
ALT7
BVALID
EIM_D27
ALT7
DATAOUT[0]
AUD3_BB_TXD
ALT7
DATAOUT[10]
UART1_RXD
ALT7
DATAOUT[11]
UART1_TXD
ALT7
DATAOUT[12]
UART1_RTS
ALT7
DATAOUT[13]
UART1_CTS
ALT7
DATAOUT[14]
UART2_RXD
ALT7
DATAOUT[15]
UART2_TXD
ALT7
DATAOUT[1]
AUD3_BB_RXD
ALT7
DATAOUT[2]
AUD3_BB_CK
ALT7
DATAOUT[3]
AUD3_BB_FS
ALT7
DATAOUT[4]
CSPI1_MOSI
ALT7
DATAOUT[5]
CSPI1_MISO
ALT7
DATAOUT[6]
CSPI1_SS0
ALT7
DATAOUT[7]
CSPI1_SS1
ALT7
DATAOUT[8]
CSPI1_RDY
ALT7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-104
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
USBPHY
CSU
CSU
Port
Pad
Mode
DATAOUT[9]
CSPI1_SCLK
ALT7
ENDSESSION
EIM_D28
ALT7
HOSTDISCONNECT
EIM_D30
ALT7
IDDIG
EIM_D29
ALT7
LINESTATE[0]
UART3_RXD
ALT7
LINESTATE[1]
UART3_TXD
ALT7
ONBIST
USBH1_NXT
ALT7
RXACTIVE
EIM_D22
ALT7
RXERROR
EIM_D23
ALT7
RXVALID
EIM_D21
ALT7
SIECLOCK
EIM_D24
ALT7
TXREADY
EIM_D20
ALT7
VBUSVALID
EIM_D25
ALT7
VSTATUS[0]
USBH1_DATA0
ALT7
VSTATUS[1]
USBH1_DATA1
ALT7
VSTATUS[2]
USBH1_DATA2
ALT7
VSTATUS[3]
USBH1_DATA3
ALT7
VSTATUS[4]
USBH1_DATA4
ALT7
VSTATUS[5]
USBH1_DATA5
ALT7
VSTATUS[6]
USBH1_DATA6
ALT7
VSTATUS[7]
USBH1_DATA7
ALT7
CSU_ALARM_AUT[0]
KEY_ROW3
ALT1
CSU_ALARM_AUT[1]
KEY_COL0
ALT1
CSU_ALARM_AUT[2]
KEY_COL1
ALT1
CSU_INT_DEB
EIM_D20
ALT3
TD
GPIO1_6
ALT7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-105
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
AUDMUX
Port
Pad
Mode
AUD3_RXD
AUD3_BB_RXD
ALT0
AUD3_TXC
AUD3_BB_CK
ALT0
AUD3_TXD
AUD3_BB_TXD
ALT0
AUD3_TXFS
AUD3_BB_FS
ALT0
AUD4_RXC
EIM_D19
ALT5
AUD4_RXD
CSPI1_MISO
ALT1
EIM_D21
ALT5
AUD4_RXFS
EIM_D16
ALT5
AUD4_TXC
CSPI1_SS0
ALT1
EIM_D22
ALT5
CSPI1_SS1
ALT1
EIM_D20
ALT5
CSPI1_RDY
ALT1
EIM_D23
ALT5
EIM_EB3
ALT6
SD1_CLK
ALT1
EIM_CS3
ALT6
EIM_D17
ALT7
SD1_DATA1
ALT1
EIM_EB2
ALT6
SD1_CMD
ALT1
EIM_CS4
ALT6
AUD4_TXD
AUD4_TXFS
AUD5_RXC
AUD5_RXD
AUD5_RXFS
AUD5_TXC
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-106
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
AUDMUX
Port
AUD5_TXC
ALT7
SD1_DATA2
ALT1
EIM_CS2
ALT6
EIM_D16
ALT7
SD1_DATA0
ALT1
EIM_CS5
ALT6
EIM_D19
ALT7
SD1_DATA3
ALT1
DISP2_DAT9
ALT4
EIM_D27
ALT5
DISP2_DAT12
ALT4
EIM_D29
ALT5
DISP2_DAT15
ALT4
EIM_D24
ALT5
DISP2_DAT13
ALT4
EIM_D30
ALT5
DISP2_DAT11
ALT4
EIM_D28
ALT5
DISP2_DAT14
ALT4
EIM_D31
ALT5
CD
GPIO1_0
ALT0
CLK
SD1_CLK
ALT0
CMD
SD1_CMD
ALT0
DAT0
SD1_DATA0
ALT0
DAT1
SD1_DATA1
ALT0
DAT2
SD1_DATA2
ALT0
DAT3
SD1_DATA3
ALT0
DAT4
SD2_DATA0
ALT1
DAT5
SD2_DATA1
ALT1
DAT6
SD2_DATA2
ALT1
DAT7
SD2_DATA3
ALT1
WP
GPIO1_1
ALT0
AUD5_TXFS
AUD6_RXC
AUD6_RXD
AUD6_RXFS
AUD6_TXC
AUD6_TXD
AUD6_TXFS
ESDHC1
Mode
EIM_D18
AUD5_TXD
ESDHC1
Pad
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-107
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
ESDHC2
ESDHC3
ESDHC3
Port
Pad
Mode
CD
GPIO1_8
ALT6
CLK
SD2_CLK
ALT0
CMD
SD2_CMD
ALT0
DAT0
SD2_DATA0
ALT0
DAT1
SD2_DATA1
ALT0
DAT2
SD2_DATA2
ALT0
DAT3
SD2_DATA3
ALT0
LCTL
GPIO1_9
ALT6
WP
GPIO1_7
ALT6
CLK
NANDF_CS7
ALT5
CMD
NANDF_RDY_INT
ALT5
DAT0
NANDF_D8
ALT5
NANDF_WE_B
ALT2
DAT1
NANDF_D9
ALT5
DAT1
NANDF_RE_B
ALT2
DAT2
NANDF_D10
ALT5
NANDF_WP_B
ALT2
NANDF_D11
ALT5
NANDF_RB0
ALT2
DAT4
NANDF_D12
ALT5
DAT5
NANDF_D13
ALT5
DAT6
NANDF_D14
ALT5
DAT7
NANDF_D15
ALT5
DAT3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-108
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
ESDHC4
SLM
Port
Pad
Mode
CD
NANDF_D4
ALT2
CLK
NANDF_CS2
ALT5
CMD
NANDF_RB1
ALT5
DAT0
NANDF_CS3
ALT5
DAT1
NANDF_CS4
ALT5
DAT2
NANDF_CS5
ALT5
DAT3
NANDF_CS6
ALT5
DAT4
NANDF_D3
ALT2
DAT5
NANDF_D2
ALT2
DAT6
NANDF_D1
ALT2
DAT7
NANDF_D0
ALT2
LCTL
NANDF_D6
ALT2
WP
NANDF_D5
ALT2
CLK
AUD3_BB_CK
ALT1
DATA
AUD3_BB_TXD
ALT1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-109
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
USBOH3
Port
Pad
Mode
H1_DM
NANDF_CS3
ALT7
H1_DP
NANDF_CS2
ALT7
H2_DM
SD2_DATA2
ALT2
H2_DP
SD2_DATA1
ALT2
H3_DM
NANDF_RB3
ALT7
H3_DP
NANDF_RB2
ALT7
USBH1_CLK
USBH1_CLK
ALT0
USBH1_DATA0
USBH1_DATA0
ALT0
USBH1_DATA1
USBH1_DATA1
ALT0
USBH1_DATA2
USBH1_DATA2
ALT0
USBH1_DATA3
USBH1_DATA3
ALT0
USBH1_DATA4
USBH1_DATA4
ALT0
USBH1_DATA5
USBH1_DATA5
ALT0
USBH1_DATA6
USBH1_DATA6
ALT0
USBH1_DATA7
USBH1_DATA7
ALT0
USBH1_DIR
USBH1_DIR
ALT0
USBH1_NXT
USBH1_NXT
ALT0
USBH1_STP
USBH1_STP
ALT0
USBH2_CLK
EIM_A24
ALT2
USBH2_DATA0
EIM_D16
ALT2
USBH2_DATA1
EIM_D17
ALT2
USBH2_DATA2
EIM_D18
ALT2
USBH2_DATA3
EIM_D19
ALT2
USBH2_DATA4
EIM_D20
ALT2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-110
Freescale Semiconductor
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
USBOH3
Port
Pad
Mode
USBH2_DATA5
EIM_D21
ALT2
USBH2_DATA6
EIM_D22
ALT2
USBH2_DATA7
EIM_D23
ALT2
USBH2_DIR
EIM_A25
ALT2
USBH2_NXT
EIM_A27
ALT2
USBH2_STP
EIM_A26
ALT2
USBH3_CLK
DISP2_DAT0
ALT3
NANDF_RB3
ALT6
DISP2_DAT8
ALT3
NANDF_D7
ALT5
DISP2_DAT9
ALT3
NANDF_D6
ALT5
DISP2_DAT10
ALT3
NANDF_D5
ALT5
DISP2_DAT11
ALT3
NANDF_D4
ALT5
DISP2_DAT12
ALT3
NANDF_D3
ALT5
DISP2_DAT13
ALT3
NANDF_D2
ALT5
DISP2_DAT14
ALT3
NANDF_D1
ALT5
DISP2_DAT15
ALT3
NANDF_D0
ALT5
USBH3_DATA0
USBH3_DATA1
USBH3_DATA2
USBH3_DATA3
USBH3_DATA4
USBH3_DATA5
USBH3_DATA6
USBH3_DATA7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-111
Table 4-2. Muxing Options Sorted by Module (continued)
Instance
USBOH3
Port
USBH3_DIR
Pad
Mode
DISP2_DAT1
ALT3
NANDF_CS5
ALT7
DISP2_DAT7
ALT3
NANDF_RB2
ALT6
DISP2_DAT6
ALT3
NANDF_CS4
ALT7
USBOTG_CLK
EIM_CS4
ALT2
USBOTG_DATA0
EIM_D24
ALT2
USBOTG_DATA1
EIM_D25
ALT2
USBOTG_DATA2
EIM_D26
ALT2
USBOTG_DATA3
EIM_D27
ALT2
USBOTG_DATA4
EIM_D28
ALT2
USBOTG_DATA5
EIM_D29
ALT2
USBOTG_DATA6
EIM_D30
ALT2
USBOTG_DATA7
EIM_D31
ALT2
USBOTG_DIR
EIM_CS5
ALT2
USBOTG_NXT
EIM_CS3
ALT2
USBOTG_STP
EIM_CS2
ALT2
USB_OC
GPIO1_9
ALT1
USB_PWR
GPIO1_8
ALT1
USBH3_NXT
USBH3_STP
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-112
Freescale Semiconductor
4.1.2
Daisy Chaining Settings
Table 4-3 shows the daisy chain settings.
Table 4-3. i.MX51 Daisy Chain Settings
Instance
AUDMUX
IN Pin
p4_input_da_amx
p4_input_db_amx
p4_input_txclk_amx
p4_input_txfs_amx
AUDMUX
p5_input_da_amx
p5_input_db_amx
p5_input_rxclk_amx
AUDMUX
p5_input_rxfs_amx
p5_input_txclk_amx
p5_input_txfs_amx
Module, Protocol, Port
Pad
Mode
Module: AUDMUX,
Protocol: AUD4_4W,
Port: AUD4_RXD
EIM_D21
ALT5
CSPI1_MISO
ALT1
Module: AUDMUX,
Protocol: AUD4_4W,
Port: AUD4_TXD
EIM_D20
ALT5
CSPI1_SS1
ALT1
Module: AUDMUX,
Protocol: AUD4_4W,
Port: AUD4_TXC
EIM_D22
ALT5
CSPI1_SS0
ALT1
Module: AUDMUX,
Protocol: AUD4_4W,
Port: AUD4_TXFS
EIM_D23
ALT5
CSPI1_RDY
ALT1
Module: AUDMUX,
Protocol: AUD5_4W,
Port: AUD5_RXD
EIM_D17
ALT7
EIM_CS3
ALT6
SD1_DATA1
ALT1
EIM_D16
ALT7
EIM_CS2
ALT6
SD1_DATA0
ALT1
Module: AUDMUX,
Protocol: AUD5_6W,
Port: AUD5_RXC
EIM_EB3
ALT6
SD1_CLK
ALT1
Module: AUDMUX,
Protocol: AUD5_6W,
Port: AUD5_RXFS
EIM_EB2
ALT6
SD1_CMD
ALT1
Module: AUDMUX,
Protocol: AUD5_4W,
Port: AUD5_TXC
EIM_D18
ALT7
EIM_CS4
ALT6
SD1_DATA2
ALT1
EIM_D19
ALT7
EIM_CS5
ALT6
SD1_DATA3
ALT1
Module: AUDMUX,
Protocol: AUD5_4W,
Port: AUD5_TXD
Module: AUDMUX,
Protocol: AUD5_4W,
Port: AUD5_TXFS
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-113
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
AUDMUX
IN Pin
p6_input_da_amx
p6_input_db_amx
p6_input_rxclk_amx
p6_input_rxfs_amx
AUDMUX
p6_input_txclk_amx
p6_input_txfs_amx
CCM
ipp_di0_clk
ipp_di1_clk
CCM
pll1_bypass_clk
pll2_bypass_clk
CSPI
ipp_cspi_clk_in
Module, Protocol, Port
Pad
Mode
Module: AUDMUX,
Protocol: AUD6_4W,
Port: AUD6_RXD
EIM_D29
ALT5
DISP2_DAT12
ALT4
Module: AUDMUX,
Protocol: AUD6_4W,
Port: AUD6_TXD
EIM_D28
ALT5
DISP2_DAT11
ALT4
Module: AUDMUX,
Protocol: AUD6_6W,
Port: AUD6_RXC
EIM_D27
ALT5
DISP2_DAT9
ALT4
Module: AUDMUX,
Protocol: AUD6_6W,
Port: AUD6_RXFS
EIM_D24
ALT5
DISP2_DAT15
ALT4
Module: AUDMUX,
Protocol: AUD6_4W,
Port: AUD6_TXC
EIM_D30
ALT5
DISP2_DAT13
ALT4
Module: AUDMUX,
Protocol: AUD6_4W,
Port: AUD6_TXFS
EIM_D31
ALT5
DISP2_DAT14
ALT4
Module: CCM,
Protocol: DISP1_SLAVE,
Port: DI1_EXT_CLK
EIM_CS5
ALT4
DI_GP1
ALT2
Module: CCM,
Protocol: DISP2_SLAVE,
Port: DI2_EXT_CLK
EIM_A26
ALT6
GPIO1_4
ALT4
Module: CCM,
Protocol: PLL1_BYP,
Port: PLL1_BYP
KEY_COL0
ALT7
GPIO1_2
ALT7
Module: CCM,
Protocol: PLL2_BYP,
Port: PLL2_BYP
KEY_COL1
ALT7
GPIO1_3
ALT7
Module: CSPI,
Protocol: MASTER,
Port: SCLK
NANDF_CS2
ALT6
USBH1_CLK
ALT1
SD1_CLK
ALT2
SD2_CLK
ALT2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-114
Freescale Semiconductor
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
CSPI
IN Pin
ipp_ind_miso
ipp_ind_mosi
CSPI
ipp_ind_ss1_b
ipp_ind_ss2_b
ipp_ind_ss3_b
DPLLIP1
DPLLIP1
ECSPI2
l1t_tog_en
l1t_tog_en
ipp_ind_ss_b[1]
ipp_ind_ss_b[3]
EMI
ipp_ind_rdy_int
Module, Protocol, Port
Pad
Mode
USBH1_NXT
ALT1
SD1_DATA0
ALT2
GPIO1_1
ALT2
SD2_DATA0
ALT2
NANDF_RB1
ALT6
USBH1_DIR
ALT1
SD1_CMD
ALT2
SD2_CMD
ALT2
Module: CSPI,
Protocol: MASTER,
Port: SS1
USBH1_DATA5
ALT1
SD1_DATA3
ALT2
Module: CSPI,
Protocol: MASTER,
Port: SS2
GPIO1_0
ALT2
SD2_DATA3
ALT2
Module: CSPI,
Protocol: MASTER,
Port: SS3
NANDF_CS6
ALT7
USBH1_DATA6
ALT1
Module: DPLLIP,
Protocol: DESENSE,
Port: TOG_EN
NANDF_RB3
ALT4
GPIO1_2
ALT6
Module: DPLLIP,
Protocol: DESENSE,
Port: TOG_EN
GPIO1_4
ALT7
GPIO1_7
ALT7
Module: ECSPI,
Protocol: MASTER,
Port: SS1
NANDF_RB0
ALT5
NANDF_D12
ALT2
Module: ECSPI,
Protocol: MASTER,
Port: SS3
NANDF_D14
ALT2
USBH1_DATA7
ALT5
Module: EMI,
Protocol: RDY,
Port: RDY
NANDF_RDY_INT
ALT0
GPIO1_4
ALT3
Module: CSPI,
Protocol: MASTER,
Port: MISO
Module: CSPI,
Protocol: MASTER,
Port: MOSI
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-115
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
ESDHC3
IN Pin
ipp_dat0_in
ipp_dat1_in
ipp_dat2_in
ipp_dat3_in
FEC
fec_col
fec_crs
fec_mdi
fec_rdata[0]
FEC
fec_rdata[1]
fec_rdata[2]
fec_rdata[3]
fec_rx_clk
Module, Protocol, Port
Pad
Mode
Module: ESDHCV2,
Protocol: CE_ATA,
Port: DAT0
NANDF_WE_B
ALT2
NANDF_D8
ALT5
Module: ESDHCV2,
Protocol: CE_ATA,
Port: DAT1
NANDF_RE_B
ALT2
NANDF_D9
ALT5
Module: ESDHCV2,
Protocol: CE_ATA,
Port: DAT2
NANDF_WP_B
ALT2
NANDF_D10
ALT5
Module: ESDHCV2,
Protocol: CE_ATA,
Port: DAT3
NANDF_RB0
ALT2
NANDF_D11
ALT5
Module: FEC,
Protocol: MII,
Port: COL
NANDF_RB2
ALT1
DISP2_DAT10
ALT2
Module: FEC,
Protocol: MII,
Port: CRS
EIM_CS5
ALT3
DI2_PIN4
ALT2
Module: FEC,
Protocol: MII,
Port: MDIO
EIM_EB2
ALT3
DI2_PIN3
ALT2
Module: FEC,
Protocol: MII,
Port: RDATA[0]
NANDF_D9
ALT2
DISP2_DAT14
ALT2
Module: FEC,
Protocol: MII,
Port: RDATA[1]
EIM_EB3
ALT3
DI2_DISP_CLK
ALT2
Module: FEC,
Protocol: MII,
Port: RDATA[2]
EIM_CS2
ALT3
DI_GP4
ALT2
Module: FEC,
Protocol: MII,
Port: RDATA[3]
EIM_CS3
ALT3
DISP2_DAT0
ALT2
Module: FEC,
Protocol: MII,
Port: RX_CLK
NANDF_RB3
ALT1
DISP2_DAT11
ALT2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-116
Freescale Semiconductor
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
FEC
IN Pin
fec_rx_dv
fec_rx_er
fec_tx_clk
GPIO3
GPIO3
ipp_ind_g_in[1]
ipp_ind_g_in[2]
ipp_ind_g_in[3]
ipp_ind_g_in[4]
ipp_ind_g_in[5]
GPIO3
ipp_ind_g_in[6]
ipp_ind_g_in[7]
ipp_ind_g_in[8]
ipp_ind_g_in[12]
I2C1
ipp_scl_in
ipp_sda_in
Module, Protocol, Port
Pad
Mode
Module: FEC,
Protocol: MII,
Port: RX_DV
NANDF_D11
ALT2
DISP2_DAT12
ALT2
Module: FEC,
Protocol: MII,
Port: RX_ER
EIM_CS4
ALT3
DISP2_DAT1
ALT2
Module: FEC,
Protocol: MII,
Port: TX_CLK
NANDF_RDY_INT
ALT1
DISP2_DAT13
ALT2
Module: GPIO,
Protocol: GPIO[1],
Port: GPIO[1]
EIM_LBA
ALT1
DI1_PIN12
ALT4
Module: GPIO,
Protocol: GPIO[2],
Port: GPIO[2]
EIM_CRE
ALT1
DI1_PIN13
ALT4
Module: GPIO,
Protocol: GPIO[3],
Port: GPIO[3]
NANDF_WE_B
ALT3
DI1_D0_CS
ALT4
Module: GPIO,
Protocol: GPIO[4],
Port: GPIO[4]
NANDF_RE_B
ALT3
DI1_D1_CS
ALT4
Module: GPIO,
Protocol: GPIO[5],
Port: GPIO[5]
NANDF_ALE
ALT3
DISPB2_SER_DIN
ALT4
Module: GPIO,
Protocol: GPIO[6],
Port: GPIO[6]
NANDF_CLE
ALT3
DISPB2_SER_DIO
ALT4
Module: GPIO,
Protocol: GPIO[7],
Port: GPIO[7]
NANDF_WP_B
ALT3
DISPB2_SER_CLK
ALT4
Module: GPIO,
Protocol: GPIO[8],
Port: GPIO[8]
NANDF_RB0
ALT3
DISPB2_SER_RS
ALT4
Module: GPIO,
Protocol: GPIO[12],
Port: GPIO[12]
GPIO_NAND
ALT0
CSI1_D8
ALT3
Module: I2C,
Protocol: I2C,
Port: SCL
EIM_D19
ALT4
CSPI1_SCLK
ALT1
SD2_CMD
ALT1
EIM_D16
ALT4
CSPI1_MOSI
ALT1
Module: I2C,
Protocol: I2C,
Port: SDA
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-117
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
IN Pin
Module, Protocol, Port
Pad
Mode
I2C1
ipp_sda_in
Module: I2C,
Protocol: I2C,
Port: SDA
SD2_CLK
ALT1
I2C2
ipp_scl_in
Module: I2C,
Protocol: I2C,
Port: SCL
EIM_D27
ALT4
KEY_COL4
ALT3
USBH1_CLK
ALT5
GPIO1_2
ALT2
EIM_D24
ALT4
KEY_COL5
ALT3
USBH1_DIR
ALT5
GPIO1_3
ALT2
DI_GP3
ALT0
DI_GP4
ALT0
DISPB2_SER_DIN
ALT0
Module: IPUV3E,
Protocol: SER_DISP2_BIDIR,
Port: DISPB2_SER_DIO
DISPB2_SER_DIO
ALT0
Module: KPP,
Protocol: KPP,
Port: COL[6]
EIM_D25
ALT1
DISP2_DAT0
ALT4
Module: KPP,
Protocol: KPP,
Port: COL[7]
EIM_D26
ALT1
ipp_sda_in
Module: I2C,
Protocol: I2C,
Port: SDA
I2C2
ipp_sda_in
Module: I2C,
Protocol: I2C,
Port: SDA
IPU
ipp_di_0_ind_dispb_sd_ Module: IPUV3E,
d
Protocol: SER_DISP1_BIDIR,
Port: DISPB1_SER_DIO
Module: IPUV3E,
Protocol: SER_DISP1_RS_UNIDIR,
Port: DISPB1_SER_DIN
ipp_di_1_ind_dispb_sd_ Module: IPUV3E,
d
Protocol: SER_DISP2_RS_UNIDIR,
Port: DISPB2_SER_DIN
KPP
ipp_ind_col[6]
ipp_ind_col[7]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-118
Freescale Semiconductor
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
IN Pin
Module, Protocol, Port
Pad
Mode
ipp_ind_col[7]
Module: KPP,
Protocol: KPP,
Port: COL[7]
DISP2_DAT1
ALT4
ipp_ind_row[4]
Module: KPP,
Protocol: KPP,
Port: ROW[4]
EIM_D28
ALT1
DISP2_DAT6
ALT4
Module: KPP,
Protocol: KPP,
Port: ROW[5]
EIM_D29
ALT1
DISP2_DAT7
ALT4
Module: KPP,
Protocol: KPP,
Port: ROW[6]
EIM_D30
ALT1
DISP2_DAT8
ALT4
ipp_ind_row[7]
Module: KPP,
Protocol: KPP,
Port: ROW[7]
EIM_D31
ALT1
KPP
ipp_ind_row[7]
Module: KPP,
Protocol: KPP,
Port: ROW[7]
DISP2_DAT10
ALT4
UART1
ipp_uart_rts_b
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
UART1_RTS
ALT0
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
UART1_CTS
ALT0
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
UART1_RXD
ALT0
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
UART1_TXD
ALT0
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
EIM_D16
ALT3
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
EIM_D19
ALT3
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
EIM_D25
ALT4
KPP
ipp_ind_row[5]
ipp_ind_row[6]
ipp_uart_rxd_mux
UART2
ipp_uart_rts_b
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-119
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
UART2
IN Pin
ipp_uart_rts_b
ipp_uart_rxd_mux
Module, Protocol, Port
Pad
Mode
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
EIM_D26
ALT4
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
USBH1_DATA0
ALT1
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
USBH1_DATA3
ALT1
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
EIM_D17
ALT3
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
EIM_D18
ALT3
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
UART2_RXD
ALT0
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
UART2_TXD
ALT0
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
USBH1_DATA1
ALT1
UART2
ipp_uart_rxd_mux
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
USBH1_DATA2
ALT1
UART3
ipp_uart_rts_b
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
EIM_D17
ALT4
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
EIM_D18
ALT4
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
EIM_D24
ALT3
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
EIM_D27
ALT3
KEY_COL4
ALT2
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: CTS
KEY_COL5
ALT2
USBH1_CLK
ALT7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-120
Freescale Semiconductor
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
UART3
UART3
USBOH3
IN Pin
Module, Protocol, Port
Pad
Mode
ipp_uart_rts_b
Module: UARTV2,
Protocol: DCE_MUX_FULL_ST,
Port: RTS
USBH1_DIR
ALT7
ipp_uart_rxd_mux
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
EIM_D25
ALT3
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
EIM_D26
ALT3
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
AUD3_BB_RXD
ALT1
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
AUD3_BB_FS
ALT1
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
UART3_RXD
ALT1
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
UART3_TXD
ALT1
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
USBH1_STP
ALT5
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
USBH1_NXT
ALT5
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: RXD_MUX
DISP2_DAT0
ALT5
Module: UARTV2,
Protocol: DCE_MUX_BASIC,
Port: TXD_MUX
DISP2_DAT1
ALT5
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_CLK
NANDF_RB3
ALT6
DISP2_DAT0
ALT3
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA0
NANDF_D7
ALT5
DISP2_DAT8
ALT3
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA1
NANDF_D6
ALT5
ipp_uart_rxd_mux
ipp_ind_uh3_clk
ipp_ind_uh3_data_0
ipp_ind_uh3_data_1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
4-121
Table 4-3. i.MX51 Daisy Chain Settings (continued)
Instance
USBOH3
IN Pin
Mode
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA1
DISP2_DAT9
ALT3
ipp_ind_uh3_data_2
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA2
NANDF_D5
ALT5
DISP2_DAT10
ALT3
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA3
NANDF_D4
ALT5
DISP2_DAT11
ALT3
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA4
NANDF_D3
ALT5
DISP2_DAT12
ALT3
ipp_ind_uh3_data_5
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA5
NANDF_D2
ALT5
ipp_ind_uh3_data_5
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA5
DISP2_DAT13
ALT3
ipp_ind_uh3_data_6
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA6
NANDF_D1
ALT5
DISP2_DAT14
ALT3
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DATA7
NANDF_D0
ALT5
DISP2_DAT15
ALT3
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_DIR
NANDF_CS5
ALT7
DISP2_DAT1
ALT3
ipp_ind_uh3_nxt
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_NXT
NANDF_RB2
ALT6
ipp_ind_uh3_nxt
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_NXT
DISP2_DAT7
ALT3
ipp_ind_uh3_stp
Module: USBOH3,
Protocol: ULPI,
Port: USBH3_STP
NANDF_CS4
ALT7
DISP2_DAT6
ALT3
ipp_ind_uh3_data_4
ipp_ind_uh3_data_7
ipp_ind_uh3_dir
USBOH3
Pad
ipp_ind_uh3_data_1
ipp_ind_uh3_data_3
USBOH3
Module, Protocol, Port
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
4-122
Freescale Semiconductor
Chapter 5
External Memories
5.1
Overview
The M4IF is the module that controls all external memory accesses (read/write/erase/program) from all
the masters in the system to different external memories. All accesses are arbitrated by the Multi Master
Multi Memory Interface (M4IF) module and controlled by the respective memory controller. The high
level block diagram is presented in Figure 5-1.
The Masters Interface to the EMI port is a full AXI interface with separated input bus for read and write
access, so master that handle separated buses for read and write access can access the EMI. The data width
can be 32 or 64 bits. All ports support 32 or 64-bit IF.
5.2
External Memory Interface
The M4IF provides the ability to connect to a wide variety of memory devices. This chapter contains the
technical information about the operation and configuration of the M4IF modules in the chip to allow the
designer to quickly integrate external memory devices into new and existing designs. Pin sharing is done
between the data bus of the WEIM and the Nand Flash Controller in order to reduce the total number of
pins needed for the M4IF.
The EMI is an External Memory Interface and arbitration between multi AXI masters to multi memory
controllers, divided into three major channels, fast memories (Mobile DDR SDRAM) channel, slow
memories (NOR-FLASH/PSRAM/NAND-FLASH etc.) channel, Internal Memory (RAM, ROM) channel
and Internal GMEM memory.
To increase the bandwidth performance, the EMI separates the buffering and the arbitration between
accesses to fast channel slow channel and Internal Memory channels, so parallel accesses can occur. By
separating the three channels, slow accesses do not interfere with fast accesses.
The M4IF contains the arbitration interface and different external memory controllers to support the
following memory devices:
• M4IF—Multi Master Multi Memory Interface
• ESDRAMC—Enhanced Mobile LPDDR SDRAM memory controller
• NFC—NAND Flash memory controller
• WEIM—SRAM/PSRAM/NOR Flash memory controller
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-1
5.2.1
EMI i.MX51 Masters
Table 5-1 provides details on EMI masters and the EMI port associated with each master.
Table 5-1. AMXI Bus Masters
Module
5.2.2
Direct Bus
Master Port
Buffered
Boundary Crossing
ARM Cortex-A8
AXI
3
Y
4K
SDMA (burst)
AHB via AHBS2AXI
4
N
1K
SDMA (non-burst)
AHB via AHBMAX
2
N
1K
IPUEX
AXI
0
Y
4K
VPU
AXI
1
Y
4K
GPU3D
AXI
5
Y
4K
RTIC
AHB via AHBMAX
2
N
1K
SCC
AHB via AHBMAX
2
N
1K
USBOH3
AXI
7
N
4K
GPU2D (OpenVG)
AXI
6
Y
4K
FEC
AHB via AHBMAX
2
N
1K
SAHARA
AHB via AHBMAX
2
N
1K
eSDHC 1
AHB via AHBMAX
2
N
1K
eSDHC 2
AHB via AHBMAX
2
N
1K
eSDHC 4
AHB via AHBMAX
2
N
1K
eSDHC 3 - CE-ATA
AHB via AHBMAX
2
N
1K
DAP
AHB via AHBMAX
2
N
1K
Features
Each of the EMI memory controller block guides specify detailed information about the supported
features, programming model. However, in i.MX51 some of those feature are disabled or not supported.
The M4IF in the i.MX51 includes these distinctive features:
• Multi Master Multi Memory Interface (M4IF)
— Supports multiple accesses from 8 masters through different input ports interfaces. Each port
can support either of the following two data width options:
– ×32 AXI port.
– ×64 AXI port.
— Supports different clock domain for each AXI port master
— Configurable memory “snooping”
— Configurable memory watermark protection per CS
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-2
Freescale Semiconductor
•
•
•
•
•
•
•
5.3
— Enhanced arbitration scheme for fast channel, consider page hit/miss, last access details
(read/write) and fixed priority configuration
Enhanced SDRAM Controller (ESDRAMC) or LPDDR Controller (LPDDRC)
— Up to 2 chip selects support up to 256 MBytes each
— ×64 AXI port
— Supports ×16/×32 LPDDR/Non-mobile DDR1 SDRAM at clock frequency up to 200 MHz
(DDR400)
— Supports ×16/×32 DDR2 memories up to 200 MHz (400 MHz data rate)
— Supports latency hiding logic
NANDFlash Controller (NFC)
— ×8/×16 NAND interface
— Up to 8 chip selects support up to 8 Gbit in 1/2K page mode, 64 Gbit in 2K page mode and
256 Gbit in 4K page mode each.
— 4.5K RAM Internal Buffer
— MLC and SLC memory support.
— Configurable operation mode—symmetric and asymmetric
— Configurable page mode, 1/2K, 2K, or 4K
— ECC support up to 8 bits
— Supports up to 8 mutually exclusive, yet interleaved NAND devices.
— Automatic Common Nand Operations
Wireless External Interface Memory Controller (WEIM)
— Up to 6 chip selects.
— Supports ×32/×16 PSRAM (up to 133 MHz).
— Supports ×32/×16 muxed mode PSRAM / NOR (up to 133 MHz).
— Supports ×32/×16 NOR (up to 133 MHz).
Supports DVFS, voltage and frequency change.
Supports watermark configuration.
Supports automatic shut-down (power saving features)
Enhanced debug capabilities (trace mode).
M4IF Setup
The following section describes i.MX51 specific requirements in order to use the M4IF module.
5.3.1
Clock Domains
The EMI contains the following clock domains:
• EMI IPS clock
• ESDCTL main clock (up to 200 MHz)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-3
•
•
•
•
•
•
5.3.2
Slow arbitration clock (up to 133 MHz)
Internal memory arbitration 1 and 2 clocks (up to 166 MHz)
8 × masters clocks, can be asynchronous to the EMI arbitration clocks (66 MHz–166 MHz)
NFC main clock—should be integer divided from slow arbitration clock (up to 50 MHz)
SDCLK—SDR/DDR clock to SDR/DDR SDRAM device
BCLK—NOR Flash/PSRAM clock WEIM in synchronous mode
Boot Scenarios
The M4IF memory controllers allow booting from the following memories: NOR Flash devices through
the WEIM and NAND Flash devices through the NAND Flash Controller. Special signals coming from
the SOC define the different booting options to those memories like the memory data width, memory page
size, and other specific parameters for the initial access of the boot. For more details refer to the memory
controllers detailed chapters and boot chapter.
5.3.3
Watermark Ports
Watermark regions are supported in the M4IF while the configuration is handled by the CSU module. The
external memory spaces have trust zone area’s that only trust zone accesses are able to reach. Non-trust
zone accesses are blocked. The CSU module has the registers that define those regions. It sends the
indication of the region and whether the specific access is trust zone or not to the M4IF. The EMI is also
capable of handling the special watermark zone for the BP domain, but this is not used for the i.MX51.
The watermark indication is dynamic and can change for each access.
For details on the watermark configuration ,refer to the CSU chapter.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-4
Freescale Semiconductor
5.3.4
Drive Strength Settings
The IOMUXC registers that controls the ESDRAMC relevant BGA contact drive strength are specified in
Table 5-2.
Table 5-2. Drive Strength Settings
Signal Group
Functional Group
DATA
BGA Contact
name
Registers
settings
DRAM_D[7:0]
Address
Value
DRAM_D[15:8]
Address
Value
DRAM_D[23:16]
Address
Value
DRAM_D[31:24]
Address
Value
DATA MASK
DRAM_DQM[0]
Address
Value
DRAM_DQM[1]
Address
Value
DRAM_DQM[2]
Address
Value
DRAM_DQM[3]
Address
Value
DATA QUALIFIERS
DRAM_SDQS[0]
Address
Value
DRAM_SDQS[1]
Address
Value
DRAM_SDQS[2]
Address
Value
DRAM_SDQS[3]
Address
Value
ADDRESS
DRAM_A[7:0]
Address
Value
DRAM_A[14:8],
SDBA[2:0]
Address
Value
Drive Strength Mode
MAX
HIGH
MEDIUM
LOW
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_GRP_DRAM_B0
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_GRP_DRAM_B1
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_GRP_DRAM_B2
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_GRP_DRAM_B4
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_GRP_DDR_A0
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_GRP_DDR_A1
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-5
Table 5-2. Drive Strength Settings (continued)
Signal Group
Functional Group
Drive Strength Mode
BGA Contact
name
Registers
settings
SDCLK
Address
CLOCKS
Value
CONTROLS
RAS
Address
Value
SDWE
Value
SDCKE0
Value
SDCKE1
Value
CS0
Value
CS1
Value
5.3.5
0x0000_0004
0x0000_0002
0x0000_0000
0x0000_0004
0x0000_0002
0x0000_0000
0x0000_0004
0x0000_0002
0x0000_0000
0x0000_0004
0x0000_0002
0x0000_0000
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0
0x0000_0006
Address
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1
0x0000_0006
Address
0x0000_0002
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0
0x0000_0006
Address
0x0000_0004
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE
0x0000_0006
Address
LOW
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
0x0000_0006
Address
MEDIUM
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
0x0000_0006
Address
HIGH
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK
0x0000_0006
Value
CAS
MAX
0x0000_0004
0x0000_0002
0x0000_0000
0xIOMUXC_BASE+IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1
0x0000_0006
0x0000_0004
0x0000_0002
0x0000_0000
M4IF I/O MUX
The M4IF provides the ability to mux some of its signals in the SOC to allow pin sharing between the
different memory controllers. Muxing is possible on the slow channel only because of timing limitations.
Only shared i.MX51 PADS signals/buses are routed through the I/O MUX toward the external devices.
Signals (mainly controls) that have dedicated PADS are directly routed from the memory controllers to the
external devices. Table 5-3 summarizes the EMI PADS definition in i.MX51.
Table 5-3. EMI IOMUX in i.MX51
EMI Port
Contact
Mode
DRAM_A[0]
DRAM_A0
No Muxing (ALT0)
DRAM_A[10]
DRAM_A10
No Muxing (ALT0)
DRAM_A[11]
DRAM_A11
No Muxing (ALT0)
DRAM_A[12]
DRAM_A12
No Muxing (ALT0)
DRAM_A[13]
DRAM_A13
No Muxing (ALT0)
DRAM_A[14]
DRAM_A14
No Muxing (ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-6
Freescale Semiconductor
Table 5-3. EMI IOMUX in i.MX51 (continued)
EMI Port
Contact
Mode
DRAM_A[1]
DRAM_A1
No Muxing (ALT0)
DRAM_A[2]
DRAM_A2
No Muxing (ALT0)
DRAM_A[3]
DRAM_A3
No Muxing (ALT0)
DRAM_A[4]
DRAM_A4
No Muxing (ALT0)
DRAM_A[5]
DRAM_A5
No Muxing (ALT0)
DRAM_A[6]
DRAM_A6
No Muxing (ALT0)
DRAM_A[7]
DRAM_A7
No Muxing (ALT0)
DRAM_A[8]
DRAM_A8
No Muxing (ALT0)
DRAM_A[9]
DRAM_A9
No Muxing (ALT0)
DRAM_CAS
DRAM_CAS
No Muxing (ALT0)
DRAM_CS0
DRAM_CS0
No Muxing (ALT0)
DRAM_CS1
DRAM_CS1
ALT0
DRAM_DQM[0]
DRAM_DQM0
No Muxing (ALT0)
DRAM_DQM[1]
DRAM_DQM1
No Muxing (ALT0)
DRAM_DQM[2]
DRAM_DQM2
No Muxing (ALT0)
DRAM_DQM[3]
DRAM_DQM3
No Muxing (ALT0)
DRAM_D[0]
DRAM_D0
No Muxing (ALT0)
DRAM_D[10]
DRAM_D10
No Muxing (ALT0)
DRAM_D[11]
DRAM_D11
No Muxing (ALT0)
DRAM_D[12]
DRAM_D12
No Muxing (ALT0)
DRAM_D[13]
DRAM_D13
No Muxing (ALT0)
DRAM_D[14]
DRAM_D14
No Muxing (ALT0)
DRAM_D[15]
DRAM_D15
No Muxing (ALT0)
DRAM_D[16]
DRAM_D16
No Muxing (ALT0)
DRAM_D[17]
DRAM_D17
No Muxing (ALT0)
DRAM_D[18]
DRAM_D18
No Muxing (ALT0)
DRAM_D[19]
DRAM_D19
No Muxing (ALT0)
DRAM_D[1]
DRAM_D1
No Muxing (ALT0)
DRAM_D[20]
DRAM_D20
No Muxing (ALT0)
DRAM_D[21]
DRAM_D21
No Muxing (ALT0)
DRAM_D[22]
DRAM_D22
No Muxing (ALT0)
DRAM_D[23]
DRAM_D23
No Muxing (ALT0)
DRAM_D[24]
DRAM_D24
No Muxing (ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-7
Table 5-3. EMI IOMUX in i.MX51 (continued)
EMI Port
Contact
Mode
DRAM_D[25]
DRAM_D25
No Muxing (ALT0)
DRAM_D[26]
DRAM_D26
No Muxing (ALT0)
DRAM_D[27]
DRAM_D27
No Muxing (ALT0)
DRAM_D[28]
DRAM_D28
No Muxing (ALT0)
DRAM_D[29]
DRAM_D29
No Muxing (ALT0)
DRAM_D[2]
DRAM_D2
No Muxing (ALT0)
DRAM_D[30]
DRAM_D30
No Muxing (ALT0)
DRAM_D[31]
DRAM_D31
No Muxing (ALT0)
DRAM_D[3]
DRAM_D3
No Muxing (ALT0)
DRAM_D[4]
DRAM_D4
No Muxing (ALT0)
DRAM_D[5]
DRAM_D5
No Muxing (ALT0)
DRAM_D[6]
DRAM_D6
No Muxing (ALT0)
DRAM_D[7]
DRAM_D7
No Muxing (ALT0)
DRAM_D[8]
DRAM_D8
No Muxing (ALT0)
DRAM_D[9]
DRAM_D9
No Muxing (ALT0)
DRAM_ODT0
EIM_SDODT0
No Muxing (ALT0)
DRAM_ODT1
EIM_SDODT1
No Muxing (ALT0)
DRAM_RAS
DRAM_RAS
No Muxing (ALT0)
DRAM_SDBA[0]
EIM_SDBA0
No Muxing (ALT0)
DRAM_SDBA[1]
EIM_SDBA1
No Muxing (ALT0)
DRAM_SDBA[2]
EIM_SDBA2
No Muxing (ALT0)
DRAM_SDCKE[0]
DRAM_SDCKE0
No Muxing (ALT0)
DRAM_SDCKE[1]
DRAM_SDCKE1
No Muxing (ALT0)
DRAM_SDCLK
DRAM_SDCLK
No Muxing (ALT0)
DRAM_SDCLK_B
DRAM_SDCLK_B
No Muxing (ALT0)
DRAM_SDQS[0]
DRAM_SDQS0
No Muxing (ALT0)
DRAM_SDQS[1]
DRAM_SDQS1
No Muxing (ALT0)
DRAM_SDQS[2]
DRAM_SDQS2
No Muxing (ALT0)
DRAM_SDQS[3]
DRAM_SDQS3
No Muxing (ALT0)
DRAM_SDQS_B[0]
DRAM_SDQS0_B
No Muxing (ALT0)
DRAM_SDQS_B[1]
DRAM_SDQS1_B
No Muxing (ALT0)
DRAM_SDQS_B[2]
DRAM_SDQS2_B
No Muxing (ALT0)
DRAM_SDQS_B[3]
DRAM_SDQS3_B
No Muxing (ALT0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-8
Freescale Semiconductor
Table 5-3. EMI IOMUX in i.MX51 (continued)
EMI Port
Contact
Mode
DRAM_SDWE
DRAM_SDWE
No Muxing (ALT0)
DSTROBE
KEY_ROW0
ALT1
EIM_A[16]
EIM_A16
ALT0
EIM_A[17]
EIM_A17
ALT0
EIM_A[18]
EIM_A18
ALT0
EIM_A[19]
EIM_A19
ALT0
EIM_A[20]
EIM_A20
ALT0
EIM_A[21]
EIM_A21
ALT0
EIM_A[22]
EIM_A22
ALT0
EIM_A[23]
EIM_A23
ALT0
EIM_A[24]
EIM_A24
ALT0
EIM_A[25]
EIM_A25
ALT0
EIM_A[26]
EIM_A26
ALT0
EIM_A[27]
EIM_A27
ALT0
EIM_BCLK
EIM_BCLK
No Muxing (ALT0)
EIM_CRE
EIM_CRE
ALT0
EIM_CS0
EIM_CS0
ALT0
EIM_CS1
EIM_CS1
ALT0
EIM_CS2
EIM_CS2
ALT0
EIM_CS3
EIM_CS3
ALT0
EIM_CS4
EIM_CS4
ALT0
EIM_CS5
EIM_CS5
ALT0
EIM_DA[0]
EIM_DA0
ALT0
EIM_DA[10]
EIM_DA10
ALT0
EIM_DA[11]
EIM_DA11
ALT0
EIM_DA[12]
EIM_DA12
ALT0
EIM_DA[13]
EIM_DA13
ALT0
EIM_DA[14]
EIM_DA14
ALT0
EIM_DA[15]
EIM_DA15
ALT0
EIM_DA[1]
EIM_DA1
ALT0
EIM_DA[2]
EIM_DA2
ALT0
EIM_DA[3]
EIM_DA3
ALT0
EIM_DA[4]
EIM_DA4
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-9
Table 5-3. EMI IOMUX in i.MX51 (continued)
EMI Port
Contact
Mode
EIM_DA[5]
EIM_DA5
ALT0
EIM_DA[6]
EIM_DA6
ALT0
EIM_DA[7]
EIM_DA7
ALT0
EIM_DA[8]
EIM_DA8
ALT0
EIM_DA[9]
EIM_DA9
ALT0
EIM_EB[0]
EIM_EB0
ALT0
EIM_EB[1]
EIM_EB1
ALT0
EIM_EB[2]
EIM_EB2
ALT0
EIM_EB[3]
EIM_EB3
ALT0
EIM_LBA
EIM_LBA
ALT0
EIM_NFC_D[0]
NANDF_D0
ALT0
EIM_NFC_D[10]
NANDF_D10
ALT0
EIM_NFC_D[11]
NANDF_D11
ALT0
EIM_NFC_D[12]
NANDF_D12
ALT0
EIM_NFC_D[13]
NANDF_D13
ALT0
EIM_NFC_D[14]
NANDF_D14
ALT0
EIM_NFC_D[15]
NANDF_D15
ALT0
EIM_NFC_D[1]
NANDF_D1
ALT0
EIM_NFC_D[2]
NANDF_D2
ALT0
EIM_NFC_D[3]
NANDF_D3
ALT0
EIM_NFC_D[4]
NANDF_D4
ALT0
EIM_NFC_D[5]
NANDF_D5
ALT0
EIM_NFC_D[6]
NANDF_D6
ALT0
EIM_NFC_D[7]
NANDF_D7
ALT0
EIM_NFC_D[8]
NANDF_D8
ALT0
EIM_NFC_D[9]
NANDF_D9
ALT0
EIM_OE
EIM_OE
ALT0
EIM_RW
EIM_RW
No Muxing (ALT0)
EIM_WAIT
EIM_WAIT
No Muxing (ALT0)
EMI_DEBUG[0]
USBH1_CLK
ALT6
EMI_DEBUG[10]
USBH1_DATA6
ALT6
EMI_DEBUG[11]
USBH1_DATA7
ALT6
EMI_DEBUG[12]
UART1_RXD
ALT6
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-10
Freescale Semiconductor
Table 5-3. EMI IOMUX in i.MX51 (continued)
EMI Port
Contact
Mode
EMI_DEBUG[13]
UART1_TXD
ALT6
EMI_DEBUG[14]
UART1_RTS
ALT6
EMI_DEBUG[15]
UART1_CTS
ALT6
EMI_DEBUG[16]
UART2_RXD
ALT6
EMI_DEBUG[17]
UART2_TXD
ALT6
EMI_DEBUG[18]
UART3_RXD
ALT6
EMI_DEBUG[19]
UART3_TXD
ALT6
EMI_DEBUG[1]
USBH1_DIR
ALT6
EMI_DEBUG[20]
KEY_ROW0
ALT6
EMI_DEBUG[21]
KEY_ROW1
ALT6
EMI_DEBUG[22]
KEY_ROW2
ALT6
EMI_DEBUG[23]
KEY_ROW3
ALT6
EMI_DEBUG[24]
DI1_PIN3
ALT6
EMI_DEBUG[25]
DI1_PIN2
ALT6
EMI_DEBUG[26]
DI_GP1
ALT6
EMI_DEBUG[27]
DI_GP2
ALT6
EMI_DEBUG[28]
DI_GP3
ALT6
EMI_DEBUG[29]
DI2_PIN4
ALT6
EMI_DEBUG[2]
USBH1_STP
ALT6
EMI_DEBUG[30]
DI2_PIN2
ALT6
EMI_DEBUG[31]
DI2_PIN3
ALT6
EMI_DEBUG[32]
DI_GP4
ALT6
EMI_DEBUG[33]
DISP2_DAT0
ALT6
EMI_DEBUG[34]
DISP2_DAT1
ALT6
EMI_DEBUG[35]
DISP2_DAT6
ALT6
EMI_DEBUG[36]
DISP2_DAT7
ALT6
EMI_DEBUG[37]
DISP2_DAT8
ALT6
EMI_DEBUG[38]
DISP2_DAT9
ALT6
EMI_DEBUG[39]
DISP2_DAT10
ALT6
EMI_DEBUG[3]
USBH1_NXT
ALT6
EMI_DEBUG[40]
DISP2_DAT11
ALT6
EMI_DEBUG[41]
DISP2_DAT12
ALT6
EMI_DEBUG[42]
DISP2_DAT13
ALT6
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-11
Table 5-3. EMI IOMUX in i.MX51 (continued)
EMI Port
Contact
Mode
EMI_DEBUG[43]
DISP2_DAT14
ALT6
EMI_DEBUG[44]
DISP2_DAT15
ALT6
EMI_DEBUG[45]
CSI2_D13
ALT6
EMI_DEBUG[46]
CSI2_D18
ALT6
EMI_DEBUG[47]
CSI2_D19
ALT6
EMI_DEBUG[48]
CSI2_VSYNC
ALT6
EMI_DEBUG[49]
CSI2_HSYNC
ALT6
EMI_DEBUG[4]
USBH1_DATA0
ALT6
EMI_DEBUG[50]
CSI2_PIXCLK
ALT6
EMI_DEBUG[5]
USBH1_DATA1
ALT6
EMI_DEBUG[6]
USBH1_DATA2
ALT6
EMI_DEBUG[7]
USBH1_DATA3
ALT6
EMI_DEBUG[8]
USBH1_DATA4
ALT6
EMI_DEBUG[9]
USBH1_DATA5
ALT6
NANDF_ALE
NANDF_ALE
ALT0
NANDF_CLE
NANDF_CLE
ALT0
NANDF_CS0
NANDF_CS0
ALT0
NANDF_CS1
NANDF_CS1
ALT0
NANDF_CS2
NANDF_CS2
ALT0
NANDF_CS3
NANDF_CS3
ALT0
NANDF_CS4
NANDF_CS4
ALT0
NANDF_CS5
NANDF_CS5
ALT0
NANDF_CS6
NANDF_CS6
ALT0
NANDF_CS7
NANDF_CS7
ALT0
NANDF_RB0
NANDF_RB0
ALT0
NANDF_RB1
NANDF_RB1
ALT0
NANDF_RB2
NANDF_RB2
ALT0
NANDF_RB3
NANDF_RB3
ALT0
NANDF_RE_B
NANDF_RE_B
ALT0
NANDF_WE_B
NANDF_WE_B
ALT0
NANDF_WP_B
NANDF_WP_B
ALT0
RDY
GPIO1_4
ALT3
NANDF_RDY_INT
ALT0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-12
Freescale Semiconductor
Table 5-3. EMI IOMUX in i.MX51 (continued)
5.4
EMI Port
Contact
Mode
WEIM_DTACK_B
EIM_DTACK
ALT0
WEIM_D[16]
EIM_D16
ALT0
WEIM_D[17]
EIM_D17
ALT0
WEIM_D[18]
EIM_D18
ALT0
WEIM_D[19]
EIM_D19
ALT0
WEIM_D[20]
EIM_D20
ALT0
WEIM_D[21]
EIM_D21
ALT0
WEIM_D[22]
EIM_D22
ALT0
WEIM_D[23]
EIM_D23
ALT0
WEIM_D[24]
EIM_D24
ALT0
WEIM_D[25]
EIM_D25
ALT0
WEIM_D[26]
EIM_D26
ALT0
WEIM_D[27]
EIM_D27
ALT0
WEIM_D[28]
EIM_D28
ALT0
WEIM_D[29]
EIM_D29
ALT0
WEIM_D[30]
EIM_D30
ALT0
WEIM_D[31]
EIM_D31
ALT0
External Memory Controllers Preset Operation
This section discusses the preset operations of the following:
• NAND Flash Controller
• WEIM
• ESDRAMC
• M4IF
5.4.1
NAND Flash Controller (NFC) Preset Operation
The NFC has several inputs that defines the initial operation of this module. This information is the page
size (0.5K, 2K, 4K), data size (8/16 bit), and NFC clock configuration. Those parameters are defined by
fuse programing.
For initialization examples, please refer to the Nand Flash Controller specific chapter.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-13
5.4.2
WEIM Preset Operation
The initial operation of the WEIM is defined by the memory data width, muxed/non-muxed memory,
address unshift, and merged CS0 and CS1 memory space. These inputs define how the WEIM operates
during direct boot to NOR Flash devices.
For an initialization example, please refer to the WEIM Controller specific chapter.
5.4.3
ESDRAMC Preset Operation
The ESDRAMC functionality depends on the register setup that defines the derive strength of the pads
related to it (see Table 5-2). For the detailed needs of the DDR delay line and options for frequency
changes, refer to the specific ESDCTL chapter.
Refer to the ESDCTL chapter for an example for ESDCTL initialization.
5.4.4
M4IF Preset Operation
Security levels, locking indications, and endianness define the way the M4IF works. Refer to the M4IF
specific chapter for a detailed description.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
5-14
Freescale Semiconductor
Chapter 6
Fuse Map
6.1
Overview
This chapter contains the fuse map for the i.MX51. There are four fuse banks. Many fuse rows may be be
locked by setting a single fuse.
6.1.1
Fuse Locks
Table 6-1 is a summary of the fuse locks used in the i.MX51.
Table 6-1. Fuse Lock Summary
Fuse Name
Fuse Bank
IMEI_LOCK
0
0860–087C
BOOT_LOCK
0
0804, 080C–0818, 0840–0844, 0854
MAC_ADDR_LOCK
1
0824–0838
SRK_LOCK
1
0C04
SJC_RESP_LOCK
1
0C08–0C20
TRIM_LOCK
1
0C24–0C7C
SRK_LOCK88
3
1404–142C
SRK_LOCK160
3
1430–147C
6.1.2
Rows Affected
Fuse Map
Table 6-2, beginning on page 6-2, is a complete listing of all user-accessible fuses.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
6-1
6-2
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Fuse Bank
Table 6-2. i.MX51 Fuse Map
7
0
0800
FBWP
0
0804
OSC_
FREQ_
SEL[1]
0
0808
0
080C
0
0810
0
0814
0
0818
0
6
5
4
3
2
1
0
FBOP
FBRP
Reserved
FBESP
Reserved
IMEI_
LOCK
BOOT_
LOCK
OSC_
FREQ_
SEL[0]
JTAG_
HEO
KTE
SEC_
JTAG_RE
JTAG_
SMODE
[1:0]
Freescale Internal Use
BT_
SRC[1:0]
Comment
0001 0000
—
—
JTAG_BP 0000 0000
BOOT_
LOCK
xxxx xxxx
BOOT_
LOCK
note2
note 3
—
note2
Freescale Semiconductor
BT_
DPLUS_
BYPASS
BT_USB_ 0000 0000
SRC
BOOT_
LOCK
HAB_
TYPE[2]
HAB_
TYPE[1]
0000 0001
BT_
EEPROM
_CFG
BOOT_
LOCK
DIR_BT_ 0000 0000
DIS
BOOT_
LOCK
HAB_CUS[7:0]
0000 0000
BOOT_
LOCK
—
081C
Freescale Internal Use
xxxx 0000
—
—
0
0820
Freescale Internal Use
xxxx xxxx
—
—
0
0824
Freescale Internal Use
xxxx xxxx
—
—
0
0828
Freescale Internal Use
xxxx xxxx
—
—
0
082C
Freescale Internal Use
xxxx xxxx
—
—
0
0830
Freescale Internal Use
xxxx xxxx
—
—
0
0834
Freescale Internal Use
xxxx xxxx
—
—
0
0838
Freescale Internal Use
xxxx xxxx
—
—
0
083C
Freescale Internal Use
xxxx xxxx
—
—
0
0840
BT_PAGE_SIZE[1:0]
BT_UART_SRC[1:0]
BT_WEIM_
MUXED[1:0]
Locked
by
BT_
SPARE_
SIZE
BT_
UNPROGR
AMMED
BT_
MLC_SEL
Burned
Value
BT_
EEPROM
_CFG
BT_MEM_TYPE[1:0]
SRTC_MCOUNT[2:0]
CMD_
DEFAULT
GPIO_
BT_SEL
BT_BUS_
WIDTH
BT_MEM_CTL[1:0]
BT_LPB[1:0]
SRTC_SECMODE[1:0 0000 0000
]
BOOT_
LOCK
note2
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Fuse Bank
Freescale Semiconductor
Table 6-2. i.MX51 Fuse Map (continued)
0
0844
0
0848
AP_BI_VER[15:8]
0000 0000
—
—
0
084C
AP_BI_VER[7:0]
0000 0000
—
—
0
0850
Freescale Internal Use
xxxx xxxx
—
—
0
0854
1000 0000
BOOT_
LOCK
—
0
0858
Freescale Internal Use
xxxx xxxx
—
—
0
085C
Freescale Internal Use
xxxx xxxx
—
—
0
0860
IMEI[63:56]
0000 0000
IMEI_
LOCK
—
0
0864
IMEI[55:48]
0000 0000
IMEI_
LOCK
—
0
0868
IMEI[47:40]
0000 0000
IMEI_
LOCK
—
0
086C
IMEI[39:32]
0000 0000
IMEI_
LOCK
—
0
0870
IMEI[31:24]
0000 0000
IMEI_
LOCK
—
0
0874
IMEI[23:16]
0000 0000
IMEI_
LOCK
—
0
0878
IMEI[15:8]
0000 0000
IMEI_
LOCK
—
0
087C
IMEI[7:0]
0000 0000
IMEI_
LOCK
—
7
6
BT_LPB_
FREQ[2:0]
Freescale
Internal
Use
SJC_DIS
ABLE
5
4
3
CSU_ FA_OUT[1:0]
2
1
CSU_AM_DIS[1:0]
Freescale Internal Use
0
CSU_
FA_
COUNT
Burned
Value
Locked
by
0000 0000
BOOT_
LOCK
Comment
note2
6-3
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
Fuse Bank
6-4
Table 6-2. i.MX51 Fuse Map (continued)
7
1
0C00
FBWP
1
0C04
SRK_HASH[255:248]
0000 0000
SRK_
LOCK
note4
1
0C08
SJC_RESP[55:48]
0000 0000
SJC_
RESP
note5
1
0C0C
SJC_RESP[47:40]
0000 0000
SJC_
RESP
1
0C10
SJC_RESP[39:32]
0000 0000
SJC_
RESP
1
0C14
SJC_RESP[31:24]
0000 0000
SJC_
RESP
1
0C18
SJC_RESP[23:16]
0000 0000
SJC_
RESP
1
0C1C
SJC_RESP[15:8]
0000 0000
SJC_
RESP
1
0C20
SJC_RESP[7:0]
0000 0000
SJC_
RESP
1
0C24
MAC_ADDR[47:40]
0000 0000
MAC_
ADDR_
LOCK
—
1
0C28
MAC_ADDR[39:32]
0000 0000
MAC_
ADDR_
LOCK
—
1
0C2C
MAC_ADDR[31:24]
0000 0000
MAC_
ADDR_
LOCK
—
1
0C30
MAC_ADDR[23:16]
0000 0000
MAC_
ADDR_
LOCK
—
6
5
4
3
2
1
0
FBOP
FBRP
MAC_
ADDR_
LOCK
FBESP
SRK_
LOCK
SJC_
RESP_
LOCK
SCC_
LOCK
Burned
Value
Locked
by
Comment
0000 0001
—
—
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Fuse Bank
Freescale Semiconductor
Table 6-2. i.MX51 Fuse Map (continued)
1
0C34
MAC_ADDR[15:8]
0000 0000
MAC_
ADDR_
LOCK
—
1
0C38
MAC_ADDR[7:0]
0000 0000
MAC_
ADDR_
LOCK
—
1
0C3C
Freescale Internal
TVDAC_GAIN1[5:0]
0000 0000
TRIM_
LOCK
—
1
0C40
Freescale Internal
TVDAC_GAIN2[5:0]
0000 0000
TRIM_
LOCK
—
1
0C44
Freescale Internal
TVDAC_GAIN3[5:0]
0000 0000
TRIM_
LOCK
—
1
0C48
1
0C4C
1
0C50
1
0C54
Freescale Internal
l1d_tch[2:0]
1
0C58
tlb_tc[1:0]
l1i_tch[2:0]
1
0C5C
1
7
6
5
4
3
2
1
0
Burned
Value
Locked
by
Comment
GDPTCV
_VALID
GDPTCV[3:0]
0000 0000
TRIM_
LOCK
—
LDPTCV_
VALID
LDPTCV[3:0]
0000 0000
TRIM_
LOCK
—
0000 0000
TRIM_
LOCK
—
l1d_tcs[2:0]
0000 0000
TRIM_
LOCK
—
l1i_tcs[2:0]
0000 0000
TRIM_
LOCK
—
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
0C60
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
1
0C64
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
1
0C68
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
PTC_VER[2:0]
MMU_EN
Freescale Internal
DVFS_DELAY_ADJUST[7:0]
6-5
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
Fuse Bank
6-6
Table 6-2. i.MX51 Fuse Map (continued)
1
0C6C
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
1
0C70
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
1
0C74
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
1
0C78
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
1
0C7C
Freescale Internal Use
xxxx xxxx
TRIM_
LOCK
—
2
1000
Freescale Internal Use
xxxx xxxx
—
2
1004
Freescale Internal Use
xxxx xxxx
—
2
1008
Freescale Internal Use
xxxx xxxx
—
2
100C
Freescale Internal Use
xxxx xxxx
—
2
1010
Freescale Internal Use
xxxx xxxx
—
2
1014
Freescale Internal Use
xxxx xxxx
—
2
1018
Freescale Internal Use
xxxx xxxx
—
2
101C
Freescale Internal Use
xxxx xxxx
—
2
1020
Freescale Internal Use
xxxx xxxx
—
2
1024
Freescale Internal Use
xxxx xxxx
—
2
1028
Freescale Internal Use
xxxx xxxx
—
2
102C
Freescale Internal Use
xxxx xxxx
—
2
1030
Freescale Internal Use
xxxx xxxx
—
2
1034
Freescale Internal Use
xxxx xxxx
—
2
1038
Freescale Internal Use
xxxx xxxx
—
2
103C
Freescale Internal Use
xxxx xxxx
—
7
6
5
4
3
2
1
0
Burned
Value
Locked
by
Comment
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Fuse Bank
Freescale Semiconductor
Table 6-2. i.MX51 Fuse Map (continued)
2
1040
Freescale Internal Use
xxxx xxxx
—
2
1044
Freescale Internal Use
xxxx xxxx
—
2
1048
Freescale Internal Use
xxxx xxxx
—
2
104C
Freescale Internal Use
xxxx xxxx
—
2
1050
Freescale Internal Use
xxxx xxxx
—
2
1054
Freescale Internal Use
xxxx xxxx
—
2
1058
Freescale Internal Use
xxxx xxxx
—
2
105C
Freescale Internal Use
xxxx xxxx
—
2
1060
Freescale Internal Use
xxxx xxxx
—
2
1064
Freescale Internal Use
xxxx xxxx
—
2
1068
Freescale Internal Use
xxxx xxxx
—
2
106C
Freescale Internal Use
xxxx xxxx
—
2
1070
Freescale Internal Use
xxxx xxxx
—
2
1074
Freescale Internal Use
xxxx xxxx
—
2
1078
Freescale Internal Use
xxxx xxxx
—
2
107C
Freescale Internal Use
xxxx xxxx
—
3
1400
3
1404
SRK_HASH[247:240]
3
1408
3
3
7
FBWP
6
FBOP
5
FBRP
4
TRIM_
LOCK
3
FBESP
2
Reserved for
customer
1
SRK_
LOCK88
0
Burned
Value
SRK_LOC 0000 0000
K160
Locked
by
Comment
6-7
—
—
0000 0000
SRK_
LOCK88
—
SRK_HASH[239:232]
0000 0000
SRK_
LOCK88
—
140C
SRK_HASH[231:224]
0000 0000
SRK_
LOCK88
—
1410
SRK_HASH[223:216]
0000 0000
SRK_
LOCK88
—
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
Fuse Bank
6-8
Table 6-2. i.MX51 Fuse Map (continued)
3
1414
SRK_HASH[215:208]
0000 0000
SRK_
LOCK88
—
3
1418
SRK_HASH[207:200]
0000 0000
SRK_
LOCK88
—
3
141C
SRK_HASH[199:192]
0000 0000
SRK_
LOCK88
—
3
1420
SRK_HASH[191:184]
0000 0000
SRK_
LOCK88
—
3
1424
SRK_HASH[183:176]
0000 0000
SRK_
LOCK88
—
3
1428
SRK_HASH[175:168]
0000 0000
SRK_
LOCK88
—
3
142C
SRK_HASH[167:160]
0000 0000
SRK_
LOCK88
—
3
1430
SRK_HASH[159:152]
0000 0000
SRK_
LOCK160
—
3
1434
SRK_HASH[151:144]
0000 0000
SRK_
LOCK160
—
3
1438
SRK_HASH[143:136]
0000 0000
SRK_
LOCK160
—
3
143C
SRK_HASH[135:128]
0000 0000
SRK_
LOCK160
—
3
1440
SRK_HASH[127:120]
0000 0000
SRK_
LOCK160
—
3
1444
SRK_HASH[119:112]
0000 0000
SRK_
LOCK160
—
3
1448
SRK_HASH[111:104]
0000 0000
SRK_
LOCK160
—
3
144C
SRK_HASH[103:96]
0000 0000
SRK_
LOCK160
—
7
6
5
4
3
2
1
0
Burned
Value
Locked
by
Comment
Address1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
1
Fuse Bank
Freescale Semiconductor
Table 6-2. i.MX51 Fuse Map (continued)
3
1450
SRK_HASH[95:88]
0000 0000
SRK_
LOCK160
—
3
1454
SRK_HASH[87:80]
0000 0000
SRK_
LOCK160
—
3
1458
SRK_HASH[79:72]
0000 0000
SRK_
LOCK160
—
3
145C
SRK_HASH[71:64]
0000 0000
SRK_
LOCK160
—
3
1460
SRK_HASH[63:56]
0000 0000
SRK_
LOCK160
—
3
1464
SRK_HASH[55:48]
0000 0000
SRK_
LOCK160
—
3
1468
SRK_HASH[47:40]
0000 0000
SRK_
LOCK160
—
3
146C
SRK_HASH[39:32]
0000 0000
SRK_
LOCK160
—
3
1470
SRK_HASH[31:24]
0000 0000
SRK_
LOCK160
—
3
1474
SRK_HASH[23:16]
0000 0000
SRK_
LOCK160
—
3
1478
SRK_HASH[15:8]
0000 0000
SRK_
LOCK160
—
3
147C
SRK_HASH[7:0]
0000 0000
SRK_
LOCK160
—
7
6
5
4
3
2
Address offset from bank base address
Shaded areas in the table indicate fuses that have corresponding GPIO pins
3 Controls JTAG debug operating modes
4 MSB (Most Significant Byte) of 256-bit of AP SRK HASH
5 SJC_RESP fuses that have being locked for read, explicit sense, override and writting.
2
1
0
Burned
Value
Locked
by
Comment
6-9
6-10
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
Chapter 7
Clock Controller Module (CCM)
The Clock Controller Module (CCM) controls the clocks for the i.MX51 modules. This module uses the
available clock sources to generate the clock roots. Figure 7-1 shows the CCM block diagram.
7.1
Overview
The Clock Controller Module controls the following functions in the i.MX51:
• Uses the available clock sources to generate clock roots to various parts of the SoC.
• Programable bits are used to control frequencies of the clock roots.
• Control of the low-power mechanism.
• Provides control signals to LPCG for gating clocks.
• Provides handshake with SRC for controlling clocks during reset.
• Provides handshake with GPC for support of DVFS, DPTC, and power gating operations.
7.1.1
Features
The CCM includes the following features:
• Clock switching module to generate three source clocks using three PLLs.
• Root clocks generation—provides root clock to the i.MX51’s modules based on three switchable
source clocks.
• ARM core root clock generated from a dedicated switchable source clock.
• Includes separate dividers to control generation of core and bus root clocks (axi’s, ahb, ipg).
• Includes separate dividers and clock sources selectors for each serial root clock.
• Option for external clock to bypass PLLs clocks.
• Selects which clocks are routed to the IOMUX signals CLKO and CLKO2 for observability.
• Controllable registers are accessible via IP bus.
• Manages the Low-Power Modes, namely RUN, WAIT, SCREEN REFRESH and STOP. The
gating of the peripheral clocks is programmable in RUN and WAIT modes.
• Manages frequency scaling procedure for ARM core clock by shifting between PLL sources,
without loss of clocks.
• Manages frequency scaling procedure for peripheral clock roots by programable divider. The
division occurs on the fly without loss of clock signals.
• Interface for the following modules:
— PLL_IP—Three PLL_IP interfaces for each PLL on the IC.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-1
— LPCG—Low-Power Clock Gating unit
— SRC—System Reset Controller
— GPC—Global Power Controller
7.1.2
CCM Blocks
The CCM includes the following submodules:
CCM_CLK_IGNITION
The purpose of this module it to manage the ignition process. This module
becomes active after the CCM comes out of reset. It manages the ignition
process by starting the Clock Amplifiers (CAMP), the Frequency
Pre-Multiplier (FPM), and the PLLs. The ignition process ends when stable
root clock outputs are available.
CCM_CLK_SWITCHER
This submodule receives the clock outputs of the three PLLs, together with
the bypass clocks for three PLLs, and generates three clock outputs
(pll1_sw_clk, pll2_sw_clk, pll3_sw_clk) for the ccm_clk_root_gen sub
module. The submodule can route any of the PLL inputs to any of the three
outputs.
CCM_CLK_ROOT_GEN
This sub module receives the three main clocks (pll1_sw_clk, pll2_sw_clk,
pll3_sw_clk) and generates the output root clocks. The module also includes
the programable clock dividers.
CCM_CLK_LOGIC
This sub-module generates the clock enables. It generates the clock enable
signals based on data from CCM_LPM and CCM_IP. The clock enables are
used by the Low-Power Clock Gating (LPCG) module to gate distributed
clocks on and off.
CCM_LPM
Manages the low-power modes of the IC and module handshaking associate
with low-power operation.
CCM_REGS
Manages the CCM memory map containing the programable registers and
the connectivity to the IP bus. This module is connected to all the sub
modules that need definition of programmable bits.
CCM_CLK_SRC_DIV
This sub-module directs various internal clocks which can be selected as
i.MX51 outputs (through IOMUX), CLKO and CLKO2, used for
observation and debug testing. These clocks are not optimized and therefore
may introduce a jitter and are not suitable for supplying a clock signal to
peripheral devices.
CCM_HND_SK
Manages the handshaking for those root clock dividers that require
handshaking and manages the frequency changes during DVFS events.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-2
Freescale Semiconductor
Figure 7-1 shows the submodules contained in the CCM.
i.MX51 CCM
CCM_LPM
CCM_REGS
CCM_CLK_LOGIC
clk
enable
signals
CCM_HND_SK
DPLL_IP1
Low-Power
Clock Gating
(LPCG)
DPLL1
pll1_sw_clk
pll2_sw_clk
DPLL_IP2
DPLL2
CCM_CLK_SWITCHER
CCM_CLK_
ROOT_GEN
clk_roots
pll3_sw_clk
DPLL_IP3
DPLL3
CKLO, CLKO2
control FPM,
CCM_CLK_SRC_DIV
CCM_CLK_IGNITION
CAMP, dpllip
SRPG
CONT.
DVFS
CONT.
DPTC
CONT.
RESET
GENERATOR
BOOT
DECODER
SRC
GPC
Figure 7-1. i.MX51 CCM Block Diagram
7.2
Detailed Signal Descriptions
7.2.1
External Signals Description
Table 7-1 describes the input/output signals of CCM module:
Table 7-1. CCM External Signals Description
Signal
I/O
Description
ipp_do_clko1
O
Clock observability 1 output
ccm_ipp_obe_clko1
O
BGA Contact output enable for Clock observability 1 output
ipp_do_clko2
O
Clock observability 2 output
ccm_ipp_obe_clko2
O
BGA Contact output enable for Clock observability 2 output
dptc_core1_clk_clko
I
DPTC core clock for observability
dptc_peripheral1_clk_clko
I
DPTC peripheral clock for observability
clko signals
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-3
Table 7-1. CCM External Signals Description (continued)
Signal
I/O
Description
obs_output_0
O
Observability output
obs_output_1
O
Observability output
obs_output_2
O
Observability output
usbphy_pll_out_480
I
480MHZ USB PHY PLL clock for observability
O
General purpose outputs
ipp_di_clk
I
Reserved
ipp_ind_ckil
I
CKIL clock input
ipp_ind_clkss
I
Selects DPLL reference clock during reset
pmic_vstby_req
O
Goes to PMIC_VSTBY_REQ pin, which notifies external power management IC to move
from functional voltage to standby voltage.
pmic_vfuncional_ready
I
Signal coming from PMIC to indicate that the voltage started to change as result of change
in pmic_vstby_req
I
FPM clock input
pll1_main_clk
I
PLL1 clock
pll2_main_clk
I
PLL2 clock
pll3_main_clk
I
PLL3 clock
pll1_reference_clk
I
PLL reference clock
pll1_bypass_clk
I
PLL1 bypass clock
pll2_bypass_clk
I
PLL2 bypass clock
pll3_bypass_clk
I
PLL3 bypass clock
pll_bypass_en1
I
Enable bypass of PLL 1 clock
pll_bypass_en2
I
Enable bypass of PLL 2 clock
pll_bypass_en3
I
Enable bypass of PLL 3 clock
pll_lvs
O
Goes to LVS input in DPLLIPs (switches frequencies)
pll_lrf_sticky1
I
Asserts when PLL1 output is stable (lock ready flag)
pll_lrf_sticky2
I
Asserts when PLL2 output is stable (lock ready flag)
pll_lrf_sticky3
I
Asserts when PLL3 output is stable (lock ready flag)
General purpose signals
cgpr_dout[31:0]
Input clocks from PADs
PMIC voltage control signals
FPM clock
fpm_clk
PLL signals
Ignition signals
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-4
Freescale Semiconductor
Table 7-1. CCM External Signals Description (continued)
Signal
I/O
fpm_lrf
I
FPM output is stable (lock ready flag)
ccm_fpm_en
O
Enable FPM
fpm_mult
O
0 - FPM multiply by 512
1 - FPM multiply by 1024
osc_clk
I
Internal oscillator clock input
cosc_en
O
Enable internal oscillator
cosc_pwrdown
O
Power down internal oscillator
ckih_CAMP1_clk
I
Input from the CKIH CAMP1
ckih2_CAMP2_clk
I
Input from the CKIH CAMP2
ccm_CAMP1_dis
O
Disable CKIH CAMP1
ccm_CAMP2_dis
O
Disable CKIH2 CAMP2
ref_clk_en_dpllip
O
Enable reference clock for DPLL
dpll_en_dpllip
O
Enable DPLLs
src_clock_ready
O
Notifies reset controller that the root clocks are ready
ccm_ref_en_b
O
Enable external reference clock (CKIH)
7.3
Description
Memory Map and Register Definition
7.3.1
Memory Map
See the system memory map for the complete listing of memory map offset addresses. Table 7-3 shows
the CCM memory map.
Table 7-3. CCM Memory Map
Base Address Offset
(Register Abbreviation)
Access
Reset Value
Section/Page
CCM Control Register (CCR)
R/W
0x0000_xx00
7.3.3.1/7-14
CCM Control Divider Register (CCDR)
R/W
0x0000_0000
7.3.3.2/7-15
CCM Status Register (CSR)
R/O
0x0000_0010
7.3.3.3/7-17
CCM Clock Switcher Register (CCSR)
R/W
0x0000_0000
7.3.3.4/7-18
73FD_4010 (CACRR)
CCM Arm Clock Root Register (CACRR)
R/W
0x0000_0000
7.3.3.5/7-20
73FD_4014 (CBCDR)
CCM Bus Clock Divider Register(CBCDR)
R/W
0x1923_9145
7.3.3.6/7-21
73FD_4018 (CBCMR)
CCM Bus Clock Multiplexer Register (CBCMR)
R/W
0x0000_20C0
7.3.3.7/7-24
73FD_4000 (CCR)
73FD_4004 (CCDR)
73FD_4008 (CSR)
73FD_400c (CCSR)
Register
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-5
Table 7-3. CCM Memory Map (continued)
Base Address Offset
(Register Abbreviation)
Register
Access
Reset Value
Section/Page
73FD_401c (CSCMR1)
CCM Serial Clock Multiplexer Register 1
(CSCMR1)
R/W
0xA6A2_A020
7.3.3.8/7-26
73FD_4020 (CSCMR2)
CCM Serial Clock Multiplexer Register 2
(CSCMR2)
R/W
0x02A5_A88A
7.3.3.9/7-29
73FD_4024 (CSCDR1)
CCM Serial Clock Divider Register 1 (CSCDR1)
R/W
0x00C3_0318
7.3.3.10/7-30
73FD_4028 (CS1CDR)
CCM SSI1 Clock Divider Register(CS1CDR)
R/W
0x0086_0041
7.3.3.11/7-34
73FD_402c (CS2CDR)
CCM SSI2 Clock Divider Register(CS2CDR)
R/W
0x0086_0041
7.3.3.12/7-35
73FD_4030 (CDCDR)
CCM DI Clock Divider Register(CDCDR)
R/W
0x0432_0DD2
7.3.3.13/7-37
73FD_4038 (CSCDR2)
CCM Serial Clock Divider Register 2(CSCDR2)
R/W
0x0209_0241
7.3.3.14/7-39
73FD_403c (CSCDR3)
CCM Serial Clock Divider Register 3(CSCDR3)
R/W
0x0001_0241
7.3.3.15/7-40
73FD_4040 (CSCDR4)
CCM Serial Clock Divider Register 4(CSCDR4)
R/W
0x0001_0241
7.3.3.16/7-42
CCM Wakeup Detector Register(CWDR)
R/W
0x0000_0000
7.3.3.17/7-43
73FD_4048 (CDHIPR)
CCM Divider Handshake In-Process
Register(CDHIPR)
R/O
0x0000_0000
7.3.3.18/7-45
73FD_404c (CDCR)
CCM DVFS Control Register(CDCR)
R/W
0x0000_0001
7.3.3.19/7-48
73FD_4050 (CTOR)
CCM Testing Observability Register (CTOR)
R/W
0x0000_0000
7.3.3.20/7-49
73FD_4054 (CLPCR)
CCM Low Power Control Register(CLPCR)
R/W
0x0000_0079
7.3.3.21/7-52
73FD_4058 (CISR)
CCM Interrupt Status Register(CISR)
W1C
0x0000_0000
7.3.3.22/7-55
73FD_405c (CIMR)
CCM Interrupt Mask Register(CIMR)
R/W
0xFFFF_FFFF
7.3.3.23/7-58
CCM Clock Output Source Register (CCOSR)
R/W
0x000A_0001
7.3.3.24/7-61
CCM General Purpose Register(CGPR)
R/W
0x0000_FE62
7.3.3.25/7-64
73FD_4068 (CCGR0)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_406c (CCGR1)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_4070 (CCGR2)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_4074 (CCGR3)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_4078 (CCGR4)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_407c (CCGR5)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_4080 (CCGR6)
CCM Clock Gating Register(CCGR)
R/W
0xFFFF_FFFF
7.3.3.26/7-66
73FD_4084 (CMEOR)
CCM Module Enable Override Register(CMEOR)
R/W
0xFFFF_FFFF
7.3.4.1/7-74
73FD_4044 (CWDR)
73FD_4060 (CCOSR)
73FD_4064 (CGPR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-6
Freescale Semiconductor
7.3.2
Register Summary
The conventions in Figure 7-2 and Table 7-4 serve as a key for the register summary and individual
register diagrams.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 7-2. Key to Register Fields
Table 7-4 provides a key for register figures and tables and the register summary.
Table 7-4. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
Reset value is determined by polarity of indicated signal.
Table 7-5 shows the register summary for the CCM.
Table 7-5. i.MX51 CCM Register Summary
Name
R
73FD_4000
(CCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
cam cam
fpm_
cosc fpm_
p2_e p1_e
en
_en mult
n
n
oscnt
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-7
Table 7-5. i.MX51 CCM Register Summary (continued)
Name
R
73FD_4004
(CCDR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
cosc
_rea
dy
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
ipu_ emi_
hs_ hs_
mas mas
k
k
W
R
W
73FD_4008
(CSR)
R
lvs_ cam cam fpm_
ref_
valu p2_r p1_r read
en_b
y
eady eady
e
W
R
0
0
0
0
0
W
73FD_400c
(CCSR)
R
lp_a
pm
W
R
73FD_4010
(CACRR)
pll1_ pll2_ pll3_
step_sel[1: pll2_div_po pll3_div_po sw_c sw_c sw_c
llk_s llk_s lk_s
0]
df[1:0]
df[1:0]
el
el
el
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
0
0
ARM_podf [2:0]
W
R
73FD_4014
(CBCDR)
0
W
ddr_
high
_fre
q_cl
k_se
l
ddr_clk_podf
perip
emi_
h_cl
clk_
k_se
sel
l
R
nfc_podf
ahb_podf [2:0]
ipg_podf
[1:0]
0
0
W
R
0
0
0
emi_slow_podf
0
0
0
perclk_pre
d1[1:0]
0
0
axi_b_podf
axi_a_podf
perclk_pred2 [2:0]
perclk_podf [2:0]
0
0
W
73FD_4018
(CBCMR)
R
vpu_axi_cl
W k_sel [1:0]
periph_ap
m_sel[1:0]
ddr_clk_sel arm_axi_cl
[1:0]
k_sel [1:0]
0
0
gpu2d_clk_
sel [1:0]
percl
percl
debug_apb k_lp
k_ip
ipu_hsp_cl gpu_clk_se
_ap
_clk_sel
g_se
k_sel [1:0]
l [1:0]
m_s
[1:0]
l
el
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-8
Freescale Semiconductor
Table 7-5. i.MX51 CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R ssi_ext2_cl ssi_ext1_cl
k_sel [1:0] k_sel [1:0]
0
W
73FD_401c
(CSCMR1)
esdh esdh
usb_
phy_ uart_clk_se usboh3_clk esdhc1_clk c3_c c4_c esdhc2_clk
_sel [1:0]
l [1:0]
_sel [1:0]
_sel [1:0] lk_s lk_s
clk_
el
el
sel
R
tve_
ssi3 vpu_
ssi_apm_cl
ssi1_clk_se ssi2_clk_se
clk_
_clk rclk_
k_sel
l [1:0]
l [1:0]
W
sel
_sel sel
R
di1_clk_sel[1:0]
73FD_4020
(CSCMR2)
W
R
hsi2c_clk_s firi_clk_sel sim_clk_sel
el [1:0]
[1:0]
[1:0]
W
R
73FD_4024
(CSCDR1)
0
0
0
0
0
0
csi_mclk2_ csi_mclk1_
clk_sel[1:0] clk_sel[1:0]
0
0
W
0
esdhc2_clk_pred
[2:0]
0
0
0
spdif spdif
spdif1_clk_ spdif0_clk_
0_
1_
sel [1:0]
sel [1:0]
com com
esdhc2_clk_podf[ esdhc1_mshc1_cl
2:0]
k_pred [2:0]
0
0
0
0
0
ssi_ext1_clk_pred
[2:0]
R
0
0
0
0
0
0
0
ssi1_clk_pred
[2:0]
ss1_clk_podf [5:0]
ssi_ext2_clk_pred
[2:0]
ssi_ext2_clk_podf [5:0]
ssi2_clk_pred
[2:0]
ss2_clk_podf [5:0]
0
0
0
0
0
0
0
W
R
0
0
0
0
0
0
0
W
R
0
tve_clk_pred [2:0]
W
R
spdif0_clk_pred
[2:0]
di_clk_pred [2:0]
W
R
0
W
R
0
0
0
ecspi_clk_pred[2:
0]
0
ssi_ext1_clk_podf [5:0]
spdif1_clk_pred
[2:0]
spdif0_clk_podf [5:0]
0
spdif1_clk_podf [5:0]
73FD_4038
(CSCDR2)
0
0
W
R
73FD_4030
(CDCDR)
0
0
ssi_
ext1
_co
m
0
W
73FD_402c
(CS2CDR)
0
0
ssi_
ext2
_co
m
R pgc_clk_po esdhc1_mshc1_cl usboh3_clk_pred[ usboh3_clk
uart_clk_pred[2:0] uart_clk_podf[2:0]
df[1:0]
k_podf[2:0]
2:0]
_podf[1:0]
W
R
73FD_4028
(CS1CDR)
di0_clk_sel[1:0]
tve_
ext_ cspi_clk_se spdif_xtal_
l [1:0]
clk_sel
clk_
sel
usb_phy_pred[2:0 usb_phy_podf[2:0
]
]
ecspi_clk_podf[5:0]
0
0
0
0
0
sim_clk_pred[2:0]
0
0
0
0
sim_clk_podf[5:0]
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-9
Table 7-5. i.MX51 CCM Register Summary (continued)
Name
R
73FD_403c
(CSCDR3)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
hsi2c_clk_pred[2:
0]
0
hsi2c_clk_podf[5:0]
firi_clk_pred[2:0]
firi_clk_podf[5:0]
W
R
73FD_4040
(CSCDR4)
0
0
0
0
0
0
0
0
0
0
0
0
W
R
0
csi_mclk1_clk_pr
ed[2:0]
csi_mclk2_clk_podf[5:0]
0
0
0
0
0
0
0
0
gpio1_9_
icr
gpio1_8_
icr
gpio1_7_
icr
gpio1_6_
icr
gpio1_5_
icr
gpio1_4_
icr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
periph_clk
_sel_busy
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
gpio gpio gpio gpio gpio gpio
1_9_ 1_8_ 1_7_ 1_6_ 1_5_ 1_4_
dir
dir
dir
dir
dir
dir
0
emi_clk_
sel_busy
0
csi_mclk1_clk_podf[5:0]
sw_periph_clk_
div_req_status
R
csi_mclk2_clk_pr
ed[2:0]
ddr_high_freq
_clk_sel_busy
W
73FD_4044
(CWDR)
0
W
0
0
R
arm
_pod
f_bu
sy
axi_a_podf_busy
axi_b_podf_busy
emi_slow_
podf_busy
ahb_podf_busy
nfc_podf_busy
R
ddr_podf_busy
W
73FD_4048
(CDHIPR)
R
0
0
0
0
0
arm_freq_shift_divider
W
0
0
W
w1c
periph_clk_
DVFS_podf[1:0]
R
software_DVFS_en
73FD_404c
(CDCR)
sw_periph_clk_div_req
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-10
Freescale Semiconductor
R
Freescale Semiconductor
sdhc1
_wakeup_det
kpp_wakeup_det
cosc_ready
CAMP2_ready
CAMP1_ready
fpm_ready
lrf_pll3
lrf_pll2
lrf_pll1
W w1c
sdhc2_
wakeup_det
bypass_emi_lpm_hs
bypass_ipu_lpm_hs
dis_ref_osc
SBYOS
ARM_clk_dis
_on_lpm
R
emi_clk_sel
_loaded
periph_clk_
sel_loaded
nfc_podf
_loaded
ahb_podf
_loaded
emi_slow_
podf_loaded
axi_b_podf
_loaded
axi_a_podf_loaded
dividers_loaded
W
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
obs_
en
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LPM[1:0]
0
bypass_pmic_
vfunctional_ready
0
bypass_sahara_lpm_hs
bypass_rtic_lpm_hs
bypass_sdma_lpm_hs
bypass_max_lpm_hs
bypass_scc_lpm_hs
obs_spare_output_0_sel
lpsr_clk_sel
stby_count
30
cosc_pwrdown
W
31
apm_sdma_clk
_gate_en_bit
VSTBY
W
ddr_clk_podf
_loaded
73FD_4054
(CLPCR)
ddr_high_freq_clk
_sel_loaded
W
arm_podf_loaded
R
gpio1_4_
wakeup_det
R
gpio1_5_
wakeup_det
73FD_4058
(CISR)
R
gpio1_6_
wakeup_det
73FD_4050
(CTOR)
gpio1_7_
wakeup_det
R
gpio1_8_
wakeup_det
Name
gpio1_9_
wakeup_det
Table 7-5. i.MX51 CCM Register Summary (continued)
obs_spare_output_1_sel obs_spare_output_2_sel
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-11
73FD_4064
(CGPR)
73FD_4068
(CCGR0)
73FD_406c
(CCGR1)
73FD_4070
(CCGR2)
7-12
R
W
R
W
0
0
0
0
0
0
0
arm_async_
ref_en
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
mask_ddr_high_freq
_clk_sel_loaded
mask_ddr_
podf__loaded
mask_emi_clk_
sel_loaded
mask_periph_clk
_sel_loaded
mask_nfc_
podf__loaded
mask_ahb_
podf_loaded
mask_emi_slow
_podf_loaded
mask_axi_b
_podf_loaded
mask_axi_a_podf
_loaded
mask_dividers
_loaded
mask_sdhc2
_wakeup_det
mask_sdhc1
_wakeup_det
mask_kpp_
wakeup_det
mask_cosc
_ready
mask_CAMP2
_ready
mask_CAMP1
_ready
mask_fpm
_ready
mask_lrf_pll3
mask_lrf_pll2
mask_lrf_pll1
0
0
0
0
0
0
0
cko2
_en
0
0
0
0
0
0
W
cko2_div[2:0}
cko1
_en
1
1
1
1
1
1
0
0
1
fpm_mux_select
0
efuse_prog_
supply_gate
0
overide_apm_emi_
int1_clock_gating
R
ARM_clk_
input_sel
73FD_4060
(CCOSR)
W
25
mask_arm_
podf_loaded
R
26
mask_gpio1_4
_wakeup_det
W
27
mask_gpio1_5
_wakeup_det
R
28
mask_gpio1_6
_wakeup_det
73FD_405c
(CIMR)
29
mask_gpio1_7
_wakeup_det
W
30
mask_gpio1_8
_wakeup_det
R
31
mask_gpio1_9
_wakeup_det
Name
arm_async
_ref_sel[5]
Table 7-5. i.MX51 CCM Register Summary (continued)
cko2_sel[4:0]
cko1_div[2:0}
cko1_sel[3:0]
arm_async_ref_sel
0
1
0
R
W
R
W
R
W
R
W
R
W
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
Table 7-5. i.MX51 CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
73FD_4074
(CCGR3)
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
R
W
R
73FD_4078
(CCGR4)
W
R
W
R
73FD_407c
(CCGR5)
W
R
W
R
73FD_4080
(CCGR6)
W
R
7.3.3
mod_en_ov|
_emi_m1
mod_en_ov
_emi_m0
1
mod_en_ov
_sahara
mod_en_ov
_dap
mod_en_ov
_vpu
mod_en_ov
_gpu2d
W
mod_en_ov
_emi_fast
R
mod_en_ov
_emi_slow
73FD_4084
(CMEOR)
mod_en_ov
_emi_int1
W
mod_en_ov_ mod_en_ov|
_emi_m2
owire
0
mod_en_ov_ mod_en_ov
_emi_m3
iim
0
mod_en_ov_ mod_en_ov
_emi_m4
esdhc
1
0
mod_en_ov
_emi_m5
1
mod_en_ov
_gpt
1
mod_en_ov
_emi_m6
1
mod_en_ov
_epit
1
mod_en_ov
_emi_m7
1
mod_en_ov
_gpu
R
mod_en_ov
_emi_garb
W
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-13
7.3.3.1
CCM Control Register (CCR)
Figure 7-3 represents the CCM Control Register (CCR), which contains bits to control general operation
of CCM. Table 7-6 provides its field descriptions.
73FD_4000 (CCR)
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
R
W
Reset
R
W
Reset
0
0
0
cosc_ fpm_ camp camp fpm_
en
mult 2_en 1_en
en
—
1
1
1
—
oscnt
1
1
1
1
Figure 7-3. CCM Control Register (CCR)
Table 7-6. CCR Field Descriptions
Field
31–13
Description
Reserved
12
cosc_en
On-chip oscillator enable bit - this bit value is reflected on the output cosc_en. The ignition process sets
this bit if the on-chip oscillator is selected as the clock source. The reset value of this bit is determined
during the ignition process based on CLKSS input.
In Run mode, the software controls the on-chip oscillator enable/disable through this bit. If this bit is
changed from ‘0’ to ‘1’ then the CCM enables the on-chip oscillator and after counting the oscnt CKIL
clock cycles it indicates the on-chip oscillator is ready by an interrupt cosc_ready and by the
cosc_ready status bit.
Note: The cosc_en bit should only be changed if the on-chip oscillator is not chosen as the clock source
by the DPLL_IPs.
0 Disable the on-chip oscillator
1 Enable the on-chip oscillator
11
FPM_MULT
fpm_mult - controls the multiplicand of FPM. This bit can be changed only in case FPM is not chosen as
the source of clock generation. FPM should be disabled (FPM_en=0) when changing this value.
Note: It multiplies the CKIL (32Khz) clock.
0 FPM multiply by 512
1 FPM multiply by 1024
10
CAMP2_EN
CAMP2 Enable bit - the ignition process always setS this bit. In run mode, software can control CAMP2
enable/disable using this bit. If this bit is changed from ‘0’ to ‘1’ then the CCM enables the CAMP2 and
after counting oscnt CKIL’s it will notify that CAMP2 is ready by the CAMP2_ready interrupt (if the
interrupt is not masked) and by the CAMP2_ready status bit.
Note: The CAMP2_en bit should only be changed when CAMP2 is not chosen as a clock source.
0 disable CAMP2
1 enable CAMP2
Note: CCM has an output ccm_CAMP2_dis. this signal is inverted from the CAMP2_en bit, for example,
when CAMP2_en bit is ‘1’ the ccm_CAMP2_dis signal is ‘0’.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-14
Freescale Semiconductor
Table 7-6. CCR Field Descriptions (continued)
Field
Description
9
CAMP1_EN
CAMP1 Enable bit - the ignition process will always set this bit. In run mode, software can control CAMP1
enable/disable through this bit. If this bit is changed from ‘0’ to ‘1’ then CCM will enable the CAMP1 and
after counting oscnt CKIL’s it will notify that CAMP1 is ready by a interrupt CAMP1_ready and by status
bit CAMP1_ready. The CAMP1_en bit should be changed only when CAMP1 is not chosen as a clock
source.
0 disable CAMP1
1 enable CAMP1
Note: CCM has an output ccm_CAMP1_dis. this signal will be inverted from the CAMP1_en bit, that is,
when CAMP1_en bit is ‘1’ the ccm_CAMP1_dis signal is ‘0’.
8
FPM_EN
FPM Enable bit - the ignition process will set this bit if the FPM is chosen as the clock source, that is, the
reset value of this bit is chosen from the ignition process based on CLKSS input. In run mode, software
can control FPM enable/disable through this bit. If this bit is changed from ‘0’ to ‘1’ then CCM will enable
FPM and after FPM lock ready flag is asserted it will notify that FPM is ready by a interrupt FPM_ready
and by status bit FPM_ready.
Note: The FPM_en bit should be changed only when FPM is not chosen as the clock source, that is, the
DPLL_ip’s are not choosing the FPM as the clock source.
0 disable FPM
1 enable FPM
7–0
OSCNT
Oscillator ready counter value. These bits define value of 32 KHz counter that serves as the counter for
oscillator lock time. This is used for both the on-chip oscillator lock time and the time that CAMP1 and
CAMP2 will be ready since the CAMPs receives the external oscillator clock. Current estimation is ~5ms.
This counter will be used in ignition sequence and in wake from STOP sequence if sbyos bit was set ,
to notify that the on-chip oscillator output is ready for the DPLL_ip to use and only then the gate in
DPLL_ip is enabled.
00000000 count 1 CKIL
11111111 count 256 CKIL’s (Default)
7.3.3.2
CCM Control Divider Register (CCDR)
Figure 7-4 represents the CCM Control Divider Register (CCDR). The only function of this register is to
control the masking of handshaking with some of the dividers.
Table 7-7 provides its field descriptions.
73FD_4004 (CCDR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
17
16
ipu_h emi_h
s_ma s_ma
sk
sk
W
Reset
Figure 7-4. CCM Control Divider Register (CCDR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-15
NOTE
The bits in the CCDR register can only be changed after a completion of the
handshake.
Table 7-7. CCDR Field Descriptions
Field
31–19
18
Description
Reserved
Reserved.
Note: Functionality is no longer supported. Bit must be set for better power saving - along with
configuration of CLPCR[23] and CCGR4[13:6] bits. Please refer to description of these bits
for the recommended values.
17
ipu_hs_mask
During load_dividers procedure1 this bit allows or masks the handshake with IPU module.
0 allow handshake with IPU module
1 mask handshake with IPU module
16
emi_hs_mask
During load_dividers procedure1 this bit allows or masks the handshake with EMI module.
0 allow handshake with EMI module
1 mask handshake with EMI module
15–0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-16
Freescale Semiconductor
7.3.3.3
CCM Status Register (CSR)
Figure 7-5 represents the CCM status Register (CSR). The status bits are read only bits. Table 7-8 provides
its field descriptions.
73FD_4008 (CSR)
R
Access: User read
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
camp camp
fpm_r ref_e
cosc_ lvs_v
2_rea 1_rea
eady n_b
ready alue
dy
dy
W
Reset
0
1
0
0
0
0
Figure 7-5. CCM Status Register (CSR)
Table 7-8. CSR Field Descriptions
Field
31–6
Description
Reserved
5
cosc_ready
Status indication of on-chip oscillator. This bit is asserted if the on-chip oscillator is enabled and the
on-chip oscillator is not powered down, and if the oscnt counter has finished counting.
0 - on-chip oscillator is not ready.
1- on-chip oscillator is ready.
4
lvs_value
Status of the value of pll_lvs output of the CCM. For more details about the pll_lvs see the DPLL IP
chapter.
0 - value of pll_lvs output is ‘0’
1- value of pll_lvs output is ‘1’
3
CAMP2_ready
Status indication of CAMP2. This is asserted if CAMP2 is enabled and if the oscnt counter has
finished counting.
0 - CAMP2 is not ready.
1- CAMP2 is ready.
2
CAMP1_ready
Status indication of CAMP1. This is asserted if CAMP1 was enabled and if oscnt counter has finished
counting.
0 - CAMP1 is not ready.
1- CAMP1 is ready.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-17
Table 7-8. CSR Field Descriptions (continued)
Field
Description
1
fpm_ready
Status indication of FPM. This will be asserted if FPM was enabled and FPM notified by asserting its
ready signal.
0 - FPM is not ready.
1- FPM is ready.
0
ref_en_b
7.3.3.4
Status of the value of ref_en_b output of ccm
0 - value of ref_en_b is ‘0’
1- value of ref_en_b is ‘1’
CCM Clock Switcher Register (CCSR)
Figure 7-6 represents the CCM Clock Switcher register (CCSR). The CCSR register contains bits to
control the switcher sub module dividers and multiplexers. Table 7-9 provides its field descriptions.
73FD_400c (CCSR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
pll1_s pll2_s pll3_s
lp_ap
pll2_div_podf pll3_div_pod
w_cllk w_cllk w_clk
step_sel[1:0]
m
[1:0]
f[1:0]
_sel _sel _sel
0
0
0
0
0
0
0
0
0
0
Figure 7-6. CCM Clock Switch Register (CCSR)
Table 7-9. CCSR Field Descriptions
Field
31–9
9
lp_apm
Description
Reserved
Selects the option to be chosen for the Low-Power Audio Playback source clock.
0 On-chip oscillator clock output
1 FPM clock output
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-18
Freescale Semiconductor
Table 7-9. CCSR Field Descriptions (continued)
Field
Description
8–7
step_sel [1:0]
Selects the option to be chosen for the step frequency when shifting ARM frequency. This bits controls
the step_clk.
00 clock source 4 - source for lp_apm. (default)
01 pll1 bypass clock
10 divided pll2 clock
11 divided pll3 clock
Note: The mux can only be switched while the output is not being used.
Note: To conserve power, Freescale recommends this mux not be set to the pll2 and pll3 options
when not being used. When PLL2 and PLL3 are running (but not selected), a small amount of
power is until consumed, but it does not enter the glitchless mux and hence less clock tree
power is consumed”.
6–5
pll2_div_podf [1:0]
Divider for PLL2 clock.
00 divide by 1
01 divide by 2
10 divide by 3
11 divide by 4
Note: This field can only be changed during the period that its output is not used.
4–3
pll3_div_podf [1:0]
Divider for PLL3 clock.
00 divide by 1
01 divide by 2
10 divide by 3
11 divide by 4
Note: This field can only be changed during the period that its output is not used.
2
pll1_sw_clk_sel
Selects source to generate pll1_sw_clk.
0 pll1_main_clk (default)
1 step_clk
Note: This bit is OR’d with the pll_bypass_en1 signal and DVFS_control signal. If one of the sources
requests to move to step_clk (pll1_sw_clk=1, or pll_bypass_en1=1, or DVFS_control=1) then
the source clock for pll1_sw_clk will be step_clk.
Only if both sources request pll1_main_clk (pll1_sw_clk=0, and pll_bypass_en1=0 and
DVFS_control=0) will the pll1_sw_clk source clock be pll1_main_clk.
1
pll2_sw_clk_sel
Selects source to generate pll2_sw_clk. This bit should only be used for testing purposes.
0 pll2_main_clk(Default)
1 pll2 bypass clock
Note: This bit is OR’d with pll_bypass_en2 signal. If one of the sources requests to move to pll2
bypass clk (pll2_sw_clk=1 or pll_bypass_en2=1) then the pll2_sw_clk will be pll2 bypass clk.
Only if both sources request pll2_main_clk (pll2_sw_clk=0 and pll_bypass_en2=0) then the
pll2_sw_clk will be pll2_main_clk.
0
pll3_sw_clk_sel
Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.
0 pll3_main_clk(Default)
1 pll3 bypass clock
Note: this bit is OR’d with pll_bypass_en3 signal. If one of the sources requests to move to pll3 bypass
clk (pll3_sw_clk=1 or pll_bypass_en3=1) then the pll3_sw_clk will be pll3 bypass clk. Only if both
sources request pll3_main_clk (pll3_sw_clk=0 and pll_bypass_en3=0) then the pll3_sw_clk will be
pll3_main_clk.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-19
7.3.3.5
CCM Arm Clock Root Register (CACRR)
Figure 7-7 represents the CCM Arm Clock Root register (CACRR). The CACRR register contains bits to
control the ARM clock root generation. Table 7-10 provides its field descriptions.
73FD_4010 (CACRR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
0
arm_podf [2:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-7. CCM ARM Clock Root Register (CACRR)
Table 7-10. CACRR Field Descriptions
Field
31–3
2–0
arm_podf [2:0]
Description
Reserved
Divider for ARM clock root. Note: if arm_freq_shift_divider is set to ‘1’ then any new write to arm_podf
will be held until arm_clk_switch_req signal is asserted.
000 divide by 1(default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-20
Freescale Semiconductor
7.3.3.6
CCM Bus Clock Divider Register(CBCDR)
Figure 7-8 represents the CCM Bus Clock Divider Register (CBCDR). The CBCDR register contains bits
to control the clock generation sub module dividers. Table 7-11 provides its field descriptions.
73FD_4014 (CBCDR)
31
30
0
ddr_h
igh_fr
eq_cl
k_sel
R
W
Reset
29
Access: User read-write
28
27
26
25
perip
emi_c
h_clk
lk_sel
_sel
ddr_clk_podf
24
23
22
21
emi_slow_podf
20
19
18
axi_b_podf
17
16
axi_a_podf
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ahb_podf [2:0]
ipg_podf
[1:0]
1
0
nfc_podf
W
Reset
1
0
0
0
0
1
perclk_pred1
[1:0]
0
perclk_pred2 [2:0]
1
0
0
0
perclk_podf [2:0]
1
0
1
Figure 7-8. CCM Bus Clock Divider Register (CBCDR)
Table 7-11. CBCDR Field Descriptions
Field
31
30
ddr_high_freq_clk_sel
29–27
ddr_clk_podf [2:0]
26
emi_clk_sel
Description
Reserved
Selector for DDR main clock.
0 derive clock from DDR mux clock source.
1 derive clock from divided PLL1 clock source.
Note: Any change of this multiplexer will involve handshake with EMI on the DDR part. The
handshake can be masked by setting CCDR[16] bit. See Section 7.3.3.18, CCM Divider
Handshake In-Process Register(CDHIPR) for details.
Divider for DDR podf.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4 (default)
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Any change of this divider might involve handshake with EMI. The handshake can be masked
by setting CCDR[16] bit. See Section 7.3.3.18, CCM Divider Handshake In-Process
Register(CDHIPR) for details,
Selector for EMI clock group
0 derive clock from DVFS divider
1 derive clock from AHB clock root
Note: Any change of this multiplexer might involve handshake with EMI and IPU. See
Section 7.3.3.18, CCM Divider Handshake In-Process Register(CDHIPR) register for the
handshake busy bits.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-21
Table 7-11. CBCDR Field Descriptions (continued)
Field
Description
25
periph_clk_sel
Selector for peripheral main clock.
0 derive clock from pll2_sw_clk clock source.
1 derive clock from periph_apm_clk clock source.
Note: Any change of this multiplexer will involve handshake with EMI and IPU - a similar handshake
to the one that is performed on peripheral DVFS. See Section 7.3.3.18, CCM Divider
Handshake In-Process Register(CDHIPR)
24–22
emi_slow_podf [2:0]
Divider for EMI slow podf.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5(default)
101 divide by 6
110 divide by 7
111 divide by 8
Note: Any change of this divider might involve handshake with EMI and IPU. See CDHIPR register for
the handshake busy bits. See Section 7.3.3.18, CCM Divider Handshake In-Process
Register(CDHIPR) for details.
21–19
axi_b_podf [2:0]
Divider for axi b podf.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6 (default)
110 divide by 7
111 divide by 8
Note: Any change of this divider might involve handshake with EMI and IPU. See CDHIPR register for
the handshake busy bits. See Section 7.3.3.18, CCM Divider Handshake In-Process
Register(CDHIPR) for details.
18–16
axi_a_podf [2:0]
Divider for axi a podf.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4 (default)
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Any change of this divider might involve handshake with EMI and IPU. See CDHIPR register for
the handshake busy bits. See Section 7.3.3.18, CCM Divider Handshake In-Process
Register(CDHIPR) for details.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-22
Freescale Semiconductor
Table 7-11. CBCDR Field Descriptions (continued)
Field
Description
15–13
nfc_podf [2:0]
Divider for nfc podf.
000 restricted
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5 (Default)
101 divide by 6
110 divide by 7
111 divide by 8
Note: Any change of this divider might involve handshake with EMI and IPU. See CDHIPR register for
the handshake busy bits. See Section 7.3.3.18, CCM Divider Handshake In-Process
Register(CDHIPR) for details.
12–10
ahb_podf [2:0]
Divider for ahb podf.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5 (Default)
101 divide by 6
110 divide by 7
111 divide by 8
Note: Any change of this divider might involve handshake with EMI and IPU. See CDHIPR register for
the handshake busy bits. See Section 7.3.3.18, CCM Divider Handshake In-Process
Register(CDHIPR) for details.
9 -8
ipg_podf [1:0]
Divider for ipg podf.
00 divide by 1
01 divide by 2 (Default)
10 divide by 3
11 divide by 4
7–6
perclk_pred1 [1:0]
Divider for perclk pred1
00 divide by 1
01 divide by 2 (default)
10 divide by 3
11 divide by 4
Note: Divider should be updated when output clock is gated.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-23
Table 7-11. CBCDR Field Descriptions (continued)
Field
Description
5–3
perclk_pred2 [2:0]
Divider for perclk pred2.
000 divide by 1(default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
2–0
perclk_podf [2:0]
Divider for perclk podf.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6(default)
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
7.3.3.7
CCM Bus Clock Multiplexer Register (CBCMR)
Figure 7-9 represents the CCM Bus Clock Multiplexer Register (CBCMR). The CBCMR register contains
bits to control the multiplexers that generate the bus clocks. Table 7-12 provides its field descriptions.
73FD_4018 (CBCMR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
17
16
gpu2d_clk_s
el [1:0]
perclk
perclk
vpu_axi_clk_ periph_apm_ ddr_clk_sel arm_axi_clk_ ipu_hsp_clk_ gpu_clk_sel debug_apb_ _lp_a
_ipg_
W
sel [1:0]
sel[1:0]
[1:0]
sel [1:0]
sel [1:0]
[1:0]
clk_sel [1:0] pm_s
sel
el
R
Reset
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
Figure 7-9. CCM Bus Clock Multiplexer Register (CBCMR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-24
Freescale Semiconductor
Table 7-12. CBCMR Field Descriptions
Field
31-18
Description
Reserved
17-16
gpu2d_clk_sel [1:0]
Selector for gpu2d clock multiplexer
00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root
15–14
vpu_axi_clk_sel [1:0]
Selector for VPU axi clock multiplexer
00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root
13–12
periph_apm_sel [1:0]
Selector for peripheral clock multiplexer
00derive clock from pll1_sw_clk
01 derive clock from pll3_sw_clk
10 lp_apm clock (default)
11 reserved
11–10
ddr_clk_sel [1:0]
Selector for DDR clock multiplexer
00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root
9–8
arm_axi_clk_sel [1:0]
Selector for ARM axi clock multiplexer
00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root
7–6
ipu_hsp_clk_sel [1:0]
Selector for IPU hsp clock multiplexer
00 derive clock from axi a
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root (Default)
5–4
gpu_clk_sel [1:0]
Selector for GPU clock multiplexer
00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root
3–2
Selector for debug apb clock multiplexer
debug_apb_clk_sel [1:0] 00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root
1
perclk_lp_apm_sel
0
perclk_ipg_sel
Controls if the root clock generation of perclk will be from peripherals main clock or lp_apm source.
0 generate perclk_root from peripherals main clock source.
1 generate perclk_root from lp_apm source.
Selector for perclk multiplexer - allows to select between ipg_clk or the division of chosen PLL.
0 select perclk generation from division of pll frequency
1 select perclk generation from ipg_clk
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-25
Note: Any change on the above multiplexer will have to be done while the module that its clock is affected
is not functional and the respective clock is gated in LPCG. If the change will be done during operation of
the module, then it is not guaranteed that the modules operation will not be harmed.
The change for arm_axi_clk_sel should be done through SDMA so that ARM will not use this clock during
the change and the clock will be gated in LPCG.
7.3.3.8
CCM Serial Clock Multiplexer Register 1 (CSCMR1)
Figure 7-10 represents the CCM Serial Clock Multiplexer Register 1 (CSCMR1). The CSCMR1 register
contains bits to control the multiplexers that generate the serial clocks. Table 7-13 provides its field
descriptions.
73FD_401c (CSCMR1)
31
30
R ssi_ext2_clk
_sel [1:0]
W
Reset
29
Access: User read-write
28
ssi_ext1_clk
_sel [1:0]
27
0
26
25
24
23
22
21
20
19
18
17
16
usb_p
esdhc esdhc
esdhc2_clk_
uart_clk_sel usboh3_clk_ esdhc1_clk_
hy_cl
3_clk 4_clk
sel [1:0]
[1:0]
sel [1:0]
sel [1:0]
k_sel
_sel _sel
1
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ssi1_clk_sel
[1:0]
W
Reset
1
0
ssi_e ssi_e
tve_e
ssi3_ vpu_r
cspi_clk_sel spdif_xtal_cl
ssi_apm_clk tve_cl
ssi2_clk_sel
xt2_c xt1_c
xt_clk
clk_s clk_s
[1:0]
k_sel
_sel
k_sel
[1:0]
om
om
_sel
el
el
1
0
0
0
0
0
0
0
1
0
0
0
0
0
Figure 7-10. CCM Serial Clock Multiplexer Register 1 (CSCMR1)
Table 7-13. CSCMR1 Field Descriptions
Field
Description
31–30
ssi_ext2_clk_sel [1:0]
Selector for ssi_ext2 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk (default)
11 derive clock from ssi_lp_apm_clk
29–28
ssi_ext1_clk_sel [1:0]
Selector for ssi_ext1 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 derive clock from ssi_lp_apm_clk
27
26
usb_phy_clk_sel
Reserved.
Selector for usb_phy clock multiplexer
0 derive clock from oscillator
1 derive clock from divided output of PLL3 (Default)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-26
Freescale Semiconductor
Table 7-13. CSCMR1 Field Descriptions (continued)
Field
Description
25–24
uart_clk_sel[1:0]
Selector for UART clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
23–22
usboh3_clk_sel [1:0]
Selector for USBOH3 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
21–20
esdhc1_clk_sel [1:0]
Selector for ESDHC1 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
19
esdhc3_clk_sel
Selector for ESDHC3 clock multiplexer
0 derive clock from esdhc1_clk_sel(Default)
1 derive clock from esdhc2_clk_sel
18
esdhc4_clk_sel
Selector for ESDHC4 clock multiplexer
0 derive clock from esdhc1_clk_sel(Default)
1 derive clock from esdhc2_clk_sel
17–16
esdhc2_clk_sel [1:0]
Selector for ESDHC2 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
15–14
ssi1_clk_sel [1:0]
Selector for SSI1 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 derive clock from ssi_lp_apm_clk
13–12
ssi2_clk_sel [1:0]
Selector for SSI2 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk (default)
11 derive clock from ssi_lp_apm_clk
11
ssi3_clk_sel
Selector for SSI3 clock multiplexer
0 derive clock from ssi1_clk_root(Default)
1 derive clock from ssi2_clk_root
10
vpu_rclk_sel
Selector for vpu_rclk clock multiplexer
0 derive clock from osc_clk (default)
1 derive clock from ckih_CAMP1_clk
9–8
ssi_apm_clk_sel
Controls the multiplexer for the ssi_lp_apm_clk clock generation.
00 CAMP1 of CKIH (default)
01 LP-APM clock selector output
10 CAMP2 of CKIH2
11 Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-27
Table 7-13. CSCMR1 Field Descriptions (continued)
Field
Description
7
tve_clk_sel
6
tve_ext_clk_sel
Controls the multiplexer for the TVE clock generation.
0 PLL3 divided clock
1 External clock source (either osc or CAMP1)
Controls the multiplexer for the TVE external clock input.
0 Oscillator output
1 CKIh through CAMP1
5–4
ecspi_clk_sel [1:0]
Selector for ECSPI clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
3–2
spdif_xtal_clk_sel
Controls the multiplexer for the spdif_xtal_clk clock generation.
00 Oscillator output (default)
01 CAMP1 of CKIH
10 CAMP2 of CKIH2
11 reserved
1
ssi_ext2_com
Controls the multiplexer to communize ssi_ext2 clock generation based on ssi2 clock root.
0 generate ssi_ext2_clk_root from dividers
1 generate ssi_ext2_clk_root from ssi2_clk_root.
0
ssi_ext1_com
Controls the multiplexer to communize ssi_ext1 clock generation based on ssi1 clock root.
0 generate ssi_ext1_clk_root from dividers
1 generate ssi_ext1_clk_root from ssi1_clk_root.
NOTE
Before any change can be made to the multiplexor ensure the clock being
switched is not being used and is gated off. Switching the clocks while they
are in use can produce unexpected results.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-28
Freescale Semiconductor
7.3.3.9
CCM Serial Clock Multiplexer Register 2 (CSCMR2)
Figure 7-11 represents the CCM Serial Clock Multiplexer Register 2 (CSCMR2). The CSCMR2 register
contains bits to control the multiplexers that generate the serial clocks. Table 7-14 provides its field
descriptions.
73FD_4020 (CSCMR2)
31
30
29
Access: User read-write
28
27
26
R
csi_mclk2_
clk_sel[1:0]
23
22
csi_mclk1_
clk_sel[1:0]
21
20
19
18
17
16
0
0
0
0
0
0
di0_clk_sel[1:0]
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
R hsi2c_clk_sel
[1:0]
W
Reset
24
di1_clk_sel[1:0]
W
Reset
25
1
0
firi_clk_sel
[1:0]
1
0
sim_clk_sel
[1:0]
1
0
spdif1 spdif0 spdif1_clk_s spdif0_clk_s
_com _com
el [1:0
el [1:0]
0
0
1
0
1
0
Figure 7-11. CCM Serial Clock Multiplexer Register 2 (CSCMR2)
Table 7-14. CSCMR2 Field Descriptions
Field
Description
31–29
di1_clk_sel [2:0]
Selector for DI1 clock multiplexer
000 derive clock from divided pll3. (Default)
001 derive clock from oscillator
010 derive clock from ckih CAMP1 clock.
011 derive clock from tve_di_clock - in this case TVE will supply the di clock. See the TVE chapter
for details.
100 derive clock from ipp_di1_clk - clock source will be generated from the IOMUX.
101 - 111 - reserved.
28–26
di0_clk_sel [2:0]
Selector for di0 clock multiplexer
000 derive clock from divided pll3. (Default)
001 derive clock from oscillator
010 derive clock from ckih CAMP1 clock.
011 derive clock from tve_di_clock - in this case tve will supply the di clock. See the TVE chapter for
details.
100 derive clock from ipp_di0_clk - clock source will be generated from the IOMUX.
101 - 111 - reserved.
25–16
15–14
hsi2c_clk_sel [1:0]
Reserved
Selector for hsi2c clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-29
Table 7-14. CSCMR2 Field Descriptions (continued)
Field
Description
13–12
firi_clk_sel [1:0]
Selector for FIRI clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
11–10
sim_clk_sel [1:0]
Selector for sim clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 lp_apm clock
9–4
Reserved
5
spdif1_com
Controlls the multiplexer configuration for spdif1 clock generation based on ssi2 clock root.
0 generate spdif1_clk_root from dividers
1 generate spdif1_clk_root from ssi2_clk_root.
4
spdif0_com
Controlls the multiplexer to configuration for spdif0 clock generation based on ssi1 clock root.
0 generate spdif0_clk_root from dividers
1 generate spdif0_clk_root from ssi1_clk_root.
3–2
spdif1_clk_sel [1:0]
Selector for spdif1 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 spdif_xtal_clk clock
1–0
spdif0_clk_sel [1:0]
Selector for spdif0 clock multiplexer
00 derive clock from pll1_sw_clk
01 derive clock from pll2_sw_clk
10 derive clock from pll3_sw_clk(Default)
11 spdif_xtal_clk clock
NOTE
Before any change can be made to the multiplexor ensure the clock being
switched is not being used and is gated off. Switching the clocks while they
are in use can produce unexpected results.
7.3.3.10
CCM Serial Clock Divider Register 1 (CSCDR1)
Figure 7-12 represents the CCM Serial Clock Divider Register 1 (CSCDR1). The CSCDR1 register
contains bits to control the clock generation sub module dividers. Table 7-15 provides its field
descriptions.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-30
Freescale Semiconductor
73FD_4024 (CSCDR1)
R
Access: User read-write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
esdhc2_clk_pred
[2:0]
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
23
22
R pgc_clk_podf esdhc1_clk_podf[2: usboh3_clk_pred[2: usboh3_clk_
[1:0]
0]
0]
podf[1:0]
W
Reset
0
0
0
0
0
0
1
1
0
0
21
20
19
esdhc2_clk_podf[2:
0]
uart_clk_pred[2:0]
0
1
1
18
17
16
esdhc1_clk_pred
[2:0]
uart_clk_podf[2:0]
0
0
0
Figure 7-12. CCM Serial Clock Divider Register 1(CSCDR1)
Table 7-15. CSCDR1 Field Descriptions
Field
31–25
Description
Reserved
24–22
esdhc2_clk_pred [2:0]
Divider for esdhc2 clock pred.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4(Default)
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
21–19
esdhc2_clk_podf[2:0]
Divider for esdhc2 clock podf.
000 divide by 1(Default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
18–16
esdhc1_clk_pred [2:0]
Divider for esdhc1 clock pred.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4(Default)
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-31
Table 7-15. CSCDR1 Field Descriptions (continued)
Field
Description
15–14
pgc_clk_podf[1:0]
Divider for pgc (power gating controller) clock podf.
00 divide by 1(Default)
01 divide by 2
10 divide by 4
11 divide by 8
Note: Divider should be updated when output clock is gated.
13–11
esdhc1_clk_podf[2:0]
Divider for esdhc1 clock podf.
000 divide by 1(Default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
10–8
usboh3_clk_pred[2:0]
Divider for usboh3 clock pred.
000 Restricted
001 divide by 2
010 divide by 3
011 divide by 4(Default)
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
7–6
usboh3_clk_podf[1:0]
Divider for usboh3 clock podf.
00 divide by 1(Default)
01 divide by 2
10 divide by 3
11 divide by 4
Note: Divider should be updated when output clock is gated.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-32
Freescale Semiconductor
Table 7-15. CSCDR1 Field Descriptions (continued)
Field
Description
5–3
uart_clk_pred[2:0]
Divider for uart clock pred.
000 divide by 1 001divide by 2
010 divide by 3
011 divide by 4(Default)
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
2–0
uart_clk_podf[2:0]
Divider for uart clock podf.
000 divide by 1(Default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
NOTE
Any change on the above dividers will have to be done while the module
that its clock is affected is not functional and the affected clock is gated. If
the change will be done during operation of the module, then it is not
guaranteed that the modules operation will not be harmed.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-33
7.3.3.11
CCM SSI1 Clock Divider Register(CS1CDR)
Figure 7-13 represents the CCM SSI1 Clock Divider Register (CS1CDR). The CS1CDR register contains
bits to control the ssi1 clock generation dividers. Table 7-16 provides its field descriptions.
73FD_4028 (CS1CDR)
R
Access: User read-write
31
30
29
28
27
26
25
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
W
Reset
R
24
23
22
21
ssi_ext1_clk_pred
[2:0]
20
19
18
17
16
ssi_ext1_clk_podf [5:0]
ssi1_clk_pred [2:0]
ss1_clk_podf [5:0]
W
Reset
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 7-13. CCM SSI1 Clock Divider Register(CS1CDR)
Table 7-16. CS1CDR Field Descriptions
Field
31-25
Description
Reserved
24–22
ssi_ext1_clk_pred[2:0]
Divider for ssi_ext1 clock pred.
000 restricted
001 divide by 2
010 divide by 3(Default)
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
21–16
ssi_ext1_clk_podf [5:0]
Divider for ssi_ext1 clock podf.
000000divide by 1
111111divide by 2^6
The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
15-9
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-34
Freescale Semiconductor
Table 7-16. CS1CDR Field Descriptions (continued)
Field
Description
8–6
ssi1_clk_pred[2:0]
Divider for ssi1 clock pred.
000 restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
5–0
ssi1_clk_podf [5:0]
Divider for ssi1 clock podf.
000000divide by 1
111111divide by 2^6
The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
7.3.3.12
CCM SSI2 Clock Divider Register(CS2CDR)
Figure 7-14 represents the CCM SSI2 Clock Divider Register (CS2CDR). The CS2CDR register contains
bits to control the ssi2 clock generation dividers. Table 7-17 provides its field descriptions.
73FD_402c (CS2CDR)
R
Access: User read-write
31
30
29
28
27
26
25
0
0
0
0
0
0
0
W
Reset
R
24
23
22
21
ssi_ext2_clk_pred
[2:0]
20
19
18
17
16
ssi_ext2_clk_podf [5:0]
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
ssi2_clk_pred [2:0]
ss2_clk_podf [5:0]
W
Reset
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 7-14. CCM SSI2 Clock Divider Register(CS2CDR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-35
Table 7-17. CS2CDR Field Descriptions
Field
31-25
Description
Reserved
24–22
ssi_ext2_clk_pred[2:0]
Divider for ssi_ext2 clock pred.
000 Restricted
001 divide by 2
010 divide by 3(Default)
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
21–16
ssi_ext2_clk_podf [5:0]
Divider for ssi_ext2 clock podf.
000000divide by 1
111111divide by 2^6
The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
15-9
Reserved
8–6
ssi2_clk_pred[2:0]
Divider for ssi2 clock pred.
000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
5–0
ssi2_clk_podf [5:0]
Divider for ssi2 clock podf.
000000divide by 1
111111divide by 2^6
The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-36
Freescale Semiconductor
7.3.3.13
CCM DI Clock Divider Register(CDCDR)
Figure 7-15 represents the CCM DI Clock Divider Register (CDCDR). The CDCDR register contains bits
to control the DI clock, tve clock and usb_phy generation dividers. Table 7-18 provides its field
descriptions.
73FD_4030 (CDCDR)
31
R
30
29
Access: User read-write
28
27
26
25
24
23
22
21
20
19
18
17
16
0
tve_clk_pred [2:0]
spdif0_clk_pred [2:0]
spdif0_clk_podf [5:0]
spdif1_clk_pred [2:0]
W
Reset
R
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
spdif1_clk_podf [5:0]
di_clk_pred [2:0]
usb_phy_pred[2:0]
usb_phy_podf[2:0]
W
Reset
0
0
0
0
1
1
0
1
1
1
0
1
0
0
1
0
Figure 7-15. CCM DI Clock Divider Register(CDCDR)
Table 7-18. CDCDR Field Descriptions
Field
31-1
Description
Reserved
30–28
tve_clk_pred[2:0]
Divider for tve clock pred.
000 divide by 1(Default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
27- 25
spdif0_clk_pred[2:0]
Divider for spdif0 clock pred.
000 restricted
001 divide by 2
010 divide by 3(Default)
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-37
Table 7-18. CDCDR Field Descriptions (continued)
Field
Description
24–19
spdif0_clk_podf [5:0]
Divider for spdif0 clock podf.
000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
18–16
spdif1_clk_pred[2:0]
Divider for spdif1 clock pred.
000 restricted
001 divide by 2
010 divide by 3(Default)
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
15
14–9
spdif1_clk_podf [5:0]
8–6
di_clk_pred[2:0]
Reserved
Divider for spdif1 clock podf.
000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
Divider for di clock pred.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8 (Default)
Note: Divider should be updated when output clock is gated.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-38
Freescale Semiconductor
Table 7-18. CDCDR Field Descriptions (continued)
Field
Description
5–3
usb_phy_pred[2:0]
Divider for usb_phy clock pred.
000 Restricted
001 divide by 2
010 divide by 3(Default)
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
2–0
usb_phy_podf[2:0]
Divider for usb_phy clock podf.
000 divide by 1
001 divide by 2
010 divide by 3(Default)
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
7.3.3.14
CCM Serial Clock Divider Register 2(CSCDR2)
Figure 7-16 represents the CCM Serial Clock Divider Register 2(CSCDR2). The CSCDR2 register
contains bits to control the clock generation sub module dividers. Table 7-19 provides its field
descriptions.
73FD_4038 (CSCDR2)
R
Access: User read-write
31
30
29
28
0
0
0
0
27
26
25
24
23
ecspi_clk_pred[2:0]
22
21
20
19
ecspi_clk_podf[5:0]
18
17
16
sim_clk_pred[2:0]
W
Reset
R
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
sim_clk_podf[5:0]
W
Reset
0
0
0
0
0
0
1
Figure 7-16. CCM Serial Clock Divider Register 2(CSCDR2)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-39
Table 7-19. CSCDR2 Field Descriptions
Field
31-28
Description
Reserved
27 -25
ecspi_clk_pred[2:0]
Divider for ecspi clock pred.
000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
24–19
ecspi_clk_podf [5:0]
Divider for ecspi clock podf.
000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
18 -16
sim_clk_pred[2:0]
15
Reserved
14–9
sim_clk_podf [5:0]
8-0
7.3.3.15
Divider for sim clock pred.
000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
Divider for sim clock podf.
000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
Reserved.
CCM Serial Clock Divider Register 3(CSCDR3)
Figure 7-16 represents the CCM Serial Clock Divider Register 3(CSCDR3). The CSCDR3 register
contains bits to control the clock generation sub module dividers. Table 7-19 provides its field
descriptions.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-40
Freescale Semiconductor
73FD_403c (CSCDR3)
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
R
18
17
16
hsi2c_clk_pred[2:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
0
hsi2c_clk_podf[5:0]
firi_clk_pred[2:0]
firi_clk_podf[5:0]
W
Reset
0
0
0
0
0
0
1
0
0
1
0
0
0
0
Figure 7-17. CCM Serial Clock Divider Register 3(CSCDR3)
Table 7-20. CSCDR3 Field Descriptions
Field
31-28
18 -16
hsi2c_clk_pred[2:0]
15
14–9
hsi2c_clk_podf [5:0]
Description
Reserved
Divider for sim clock pred.
000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
Reserved
Divider for sim clock podf.
000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-41
Table 7-20. CSCDR3 Field Descriptions (continued)
Field
Description
8–6
firi_clk_pred[2:0]
Divider for firi clock pred.
000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
5–0
firi_clk_podf [5:0]
Divider for firi clock podf.
000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
7.3.3.16
CCM Serial Clock Divider Register 4(CSCDR4)
Figure 7-16 represents the CCM Serial Clock Divider Register 4 (CSCDR4). The CSCDR4 register
contains bits to control the clock generation sub module dividers. Table 7-19 provides its field
descriptions.
73FD_4040 (CSCDR4)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
0
csi_mclk1_clk_pred[
2:0]
csi_mclk2_clk_podf[5:0]
W
Reset
0
0
0
0
0
0
1
0
0
1
18
17
16
csi_mclk2_clk_pred[
2:0]
csi_mclk1_clk_podf[5:0]
0
0
0
0
0
1
Figure 7-18. CCM Serial Clock Divider Register 4(CSCDR4)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-42
Freescale Semiconductor
Table 7-21. CSCDR4 Field Descriptions
Field
Description
31-28
Reserved
18 -16
Divider for csi mclk2 clock pred.
csi_mclk2_clk_pred[2:0] 000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
15
Reserved
14–9
Divider for csi mclk2 clock podf.
csi_mclk2_clk_podf [5:0] 000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
8–6
Divider for csi mclk1 clock pred.
csi_mclk1_clk_pred[2:0] 000 Restricted
001 divide by 2(Default)
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
Note: Divider should be updated when output clock is gated.
5–0
Divider for csi mclk1 clock podf.
csi_mclk1_clk_podf [5:0] 000000divide by 1
111111divide by 2^6
Note: Divider should be updated when output clock is gated.
Note: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
NOTE
Any change on the serial clock dividers (all dividers in the registers
CSCDR1, CECDR, CDCDR, CSCDR2) will have to be done while the
module that its clock is affected is not functional. If the change will be done
during operation of the module, then it is not guaranteed that the modules
operation will not be harmed.
7.3.3.17
CCM Wakeup Detector Register(CWDR)
Figure 7-19 represents the CCM Wakeup Detector Register (CWDR). The CWDR register contains bits to
control the functionality of the wakeup detector.Table 7-22 provides its field descriptions.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-43
73FD_4044 (CWDR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
gpio1_9_
icr
gpio1_8_
icr
gpio1_7_
icr
gpio1_6_
icr
gpio1_5_
icr
gpio1_4_
icr
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
0
0
21
20
19
18
17
16
gpio1 gpio1 gpio1 gpio1 gpio1 gpio1
_4_
_5_
_6_
_7_
_8_
_9_
dir
dir
dir
dir
dir
dir
0
0
0
0
Figure 7-19. CCM Register (CWDR)
Table 7-22. CWDR Field Descriptions
Field
31–22
Description
Reserved
21
gpio1_9_dir
Defines direction of gpio1_9. Software should program this value correspondingly to the settings in
the GPIO, so that the wakeup detector will be able to track the correct signals.
0 gpio configures as input
1 gpio configured as output
20
gpio1_8_dir
Defines direction of gpio 1_8. Software should program this value correspondingly to the setings in
the GPIO, so that the wakeup detector will be able to track the correct signals.
0 gpio configures as input
1 gpio configured as output
19
gpio1_7_dir
Defines direction of gpio 1_7. Software should program this value correspondingly to the setings in
the GPIO, so that the wakeup detector will be able to track the correct signals.
0 gpio configures as input
1 gpio configured as output
18
gpio1_6_dir
Defines direction of gpio 1_6. Software should program this value correspondingly to the setings in
the GPIO, so that the wakeup detector will be able to track the correct signals.
0 gpio configures as input
1 gpio configured as output
17
gpio1_5_dir
Defines direction of gpio 1_5. Software should program this value correspondingly to the setings in
the GPIO, so that the wakeup detector will be able to track the correct signals.
0 gpio configures as input
1 gpio configured as output
16
gpio1_4_dir
Defines direction of gpio 1_4. Software should program this value correspondingly to the setings in
the GPIO, so that the wakeup detector will be able to track the correct signals.
0 gpio configures as input
1 gpio configured as output
15–12
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-44
Freescale Semiconductor
Table 7-22. CWDR Field Descriptions (continued)
Field
Description
11–10
gpio1_9_
icr
Interrupt sensitivity configuration bits for gpio1_9. Software should program this value correspondingly
to the setings in the GPIO, so that the wakeup detector will be able to track the correct signals.
00 - The interrupt is low level sensitive
01 - The interrupt is high level sensitive
10 - The interrupt is rise edge sensitive
11 - The interrupt is fall edge sensitive
9–8
gpio1_8_
icr
Interrupt sensitivity configuration bits for gpio1_8. Software should program this value correspondingly
to the setings in the GPIO, so that the wakeup detector will be able to track the correct signals.
00 - The interrupt is low level sensitive
01 - The interrupt is high level sensitive
10 - The interrupt is rise edge sensitive
11 - The interrupt is fall edge sensitive
7–6
gpio1_7_
icr
Interrupt sensitivity configuration bits for gpio1_7. Software should program this value correspondingly
to the setings in the GPIO, so that the wakeup detector will be able to track the correct signals.
00 - The interrupt is low level sensitive
01 - The interrupt is high level sensitive
10 - The interrupt is rise edge sensitive
11 - The interrupt is fall edge sensitive
5–4
gpio1_6_
icr
Interrupt sensitivity configuration bits for gpio1_6. Software should program this value correspondingly
to the setings in the GPIO, so that the wakeup detector will be able to track the correct signals.
00 - The interrupt is low level sensitive
01 - The interrupt is high level sensitive
10 - The interrupt is rise edge sensitive
11 - The interrupt is fall edge sensitive
3–2
gpio1_5_
icr
Interrupt sensitivity configuration bits for gpio1_5. Software should program this value correspondingly
to the setings in the GPIO, so that the wakeup detector will be able to track the correct signals.
00 - The interrupt is low level sensitive
01 - The interrupt is high level sensitive
10 - The interrupt is rise edge sensitive
11 - The interrupt is fall edge sensitive
1–0
gpio1_4_
icr
Interrupt sensitivity configuration bits for gpio1_4. Software should program this value correspondingly
to the setings in the GPIO, so that the wakeup detector will be able to track the correct signals.
00 - The interrupt is low level sensitive
01 - The interrupt is high level sensitive
10 - The interrupt is rise edge sensitive
11 - The interrupt is fall edge sensitive
7.3.3.18
CCM Divider Handshake In-Process Register(CDHIPR)
Figure 7-20 represents the CCM Divider Handshake In-Process Register (CDHIPR). The CDHIPR
register contains read-only bits that indicate that ccm is in process of updating dividers or muxes that might
need handshake with modules.
Bit 16 corresponds to the arm_podf divider only if ARM DVFS operation is done through arm_podf
change (arm_freq_shift_divider = ‘1’). In this case, ARM divider will be updated only after assertion of
arm_clk_switch_req from GPC. During this period, bit 16 (arm_podf_busy) will assert to indicate that
arm_podf is during process of change. Software should not write new values to arm_podf during this
period. any reads of arm_podf during this period will result the next value of arm_podf and not the actual
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-45
dividers value. To read the actual dividers value, software should wait until arm_podf_busy deasserts.
Once the value of the indication bit changes from ‘1’ to ‘0’, ccm can also generate interrupt, if its not
masked (refer to CIMR). This bit will not assert if its not a ARM DVFS operation, for example, if
arm_freq_shift_divider = ‘0’. In this case, ARM divider will be updated once arm_podf register will be
written.
The dividers in the bits 8–0 group are axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf, ddr_clk_podf
and nfc_podf. The muxes control in this group are ddr_high_freq_clk_sel, periph_clk_sel and
emi_clk_sel.
For each of those dividers and muxes control, CDHIPR holds a busy indication bit. If this bit is equal to
1, then ccm is in process of updating the divider or mux. The corresponding bit will assert to ‘1’ once the
CBCDR register is updated and a handshake is indeed needed for the update. The corresponding bit will
deassert to ‘0’ once the handshake has completed and the divider or mux is loaded with the new values.
Software reads of the divider or mux control bits, during the time that these bits are 1, will represent the
next value of the divider or mux to be loaded. If software wants to read the actual divider value, it should
wait until the value of the indicator bit is equal 0. Once the value of the indication bit changes from ‘1’ to
‘0’, ccm can also generate interrupt, if its not masked (refer to CIMR). Table 7-23 provides its field
descriptions.
The handshake bypass should be used in case that a specific module that has a handshake is disabled - in
this case the module is not ready to answer for the handshake, and the handshake should be bypassed. In
case of a bypass, the CCM will generate the request to the module but will not wait for the acknowledge
signal.
73FD_4048 (CDHIPR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
arm_
podf_
busy
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
ddr_h ddr_p emi_c perip nfc_p ahb_ emi_s axi_b axi_a
igh_fr odf_b lk_sel h_clk odf_b podf_ low_p _podf _podf
eq_cl usy _busy _sel_ usy busy odf_b _busy _busy
usy
busy
k_sel
_busy
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-20. CCM Divider Handshake In Process Register(CDHIPR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-46
Freescale Semiconductor
Table 7-23. CDHIPRR Field Descriptions
Field
31–10
16
arm_podf_busy
15–9
Description
Reserved
Busy indicator for arm_podf. This bit corresponds to the arm_podf divider only if ARM DVFS operation
is done through arm_podf change (arm_freq_shift_divider = ‘1’).
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process. The value read in the divider represents the next value that
the divider will hold after the handshake with gpc (after assertion of arm_clk_switch_req and the
actual write to the divider).
Reserved
Busy indicator for ddr_high_freq_clk_sel mux control.
8
ddr_high_freq_clk_sel_b 0 mux is not busy and its value represents the actual division.
1 mux is busy with handshake process with module. The value read in the register represents the next
usy
value that the mux will hold after the handshake.
7
ddr_podf_busy
Busy indicator for ddr_podf.
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the regster represents the
next value that the divider will hold after the handshake.
6
emi_clk_sel_busy
Busy indicator for emi_clk_sel.
0 mux is not busy and its value represents the actual division.
1 mux is busy with handshake process with module. The value read in the divider represents the next
value that the divider will hold after the handshake.
5
periph_clk_sel_busy
Busy indicator for periph_clk_sel mux control.
0 mux is not busy and its value represents the actual division.
1 mux is busy with handshake process with module. The value read in the divider represents the next
value that the divider will hold after the handshake.
4
nfc_podf_busy
Busy indicator for nfc_podf.
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the divider represents the
next value that the divider will hold after the handshake.
3
ahb_podf_busy
Busy indicator for ahb_podf.
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the divider represents the
next value that the divider will hold after the handshake.
2
emi_slow_podf_busy
Busy indicator for emi_slow_podf.
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the divider represents the
next value that the divider will hold after the handshake.
1
axi_b_podf_busy
Busy indicator for axi_b_podf.
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the divider represents the
next value that the divider will hold after the handshake.
0
axi_a_podf_busy
Busy indicator for axi_a_podf.
0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the divider represents the
next value that the divider will hold after the handshake.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-47
7.3.3.19
CCM DVFS Control Register(CDCR)
Figure 7-21 represents the CCM DVFS Control Register (CDCR). The CDCR register contains bits to
control the DVFS operation.Table 7-24 provides its field descriptions.
73FD_404c (CDCR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
sw_p
eriph
_clk_
div_re
q_stat
us
0
0
W
Reset
R
W
sw_p softw
eriph are_D
_clk_ VFS_
div_re en
q
arm_f
periph_clk_D
req_s
VFS_podf[1:
hift_di
0]
vider
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Figure 7-21. CCM DVFS Control Register (CDCR)
Table 7-24. CDCR Field Descriptions
Field
31-8
Description
Reserved
Status bit defines the operation of DVFS driver in case of software control of DVFS divider.” Set this
7
bit to ‘1’ to clear - after a DVFS divider switch request it will be asserted and software should write
sw_periph_clk_div_req_
‘1’ to clear it and prepare it for the next DVFS divider switch request.
status
1 DVFS frequency switch operation finished.
0 DVFS frequency switch is not finished, or there is no frequency switch request.
6
sw_periph_clk_div_req
5
software_DVFS_en
Start DVFS frequency division operation. This bit will affect the DVFS divider only if
software_DVFS_en bit was set to ‘1’.
0 Remove DVFS divider operation - DVFS divider will divide by ‘1’.
1 enable DVFS divider operation. DVFS divider will divide by the value which is programmed in
periph_clk_DVFS_podf bits.
Defines if the DVFS operation will commence by software bit or by GPC signal “periph_clk_div_req”.
0 DVFS operation is started by GPC signal “periph_clk_div_req”
1 DVFS operation is started by software bit sw_periph_clk_div_req
4
reserved
Note: Functionality is no longer supported. Bit shouldn’t be altered and must remain in its default
value.
3
reserved
Note: Functionality is no longer supported. Bit shouldn’t be altered and must remain in its default
value.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-48
Freescale Semiconductor
Table 7-24. CDCR Field Descriptions (continued)
Field
Description
2
arm_freq_shift_divider
Define if next DVFS of ARM domain will be through podf change or pll relock.
0 Next ARM DVFS operation is done through PLL relock. The PLL relock process will start once
arm_clk_switch_req is asserted. (in this case any new writes to arm_podf will immediately change
the frequency, without waiting for arm_clk_switch_req).
1 Next ARM DVFS operation is done through arm_podf change. ccm will hold updates to arm_podf
until signal arm_clk_switch_req is asserted.
Divider value for next operation of peripheral DVFS. This defines the value of the dividers affecting
1–0
periph_clk_DVFS_podf[ main_bus_clk. Please refer to Figure 7-40 and Figure 7-41. This divider will take place only during
DVFS operation. Please refer to Section 7.4.7.2, Peripheral Clock Domain Frequency Shift for details.
1:0]
00restricted
01divide by 2(Default)
10divide by 3
11divide by 4
Note: IPU will not support DVFS operation of division by 3.
7.3.3.20
CCM Testing Observability Register (CTOR)
Figure 7-22 represents the CCM Testing Observability Register (CTOR). CCM includes three muxes to
mux between different critical signals for testing observability. The output of the three muxes is generated
on the three output signals obs_output_0, obs_output_1 and obs_output_2. Those three output signals can
be generated on the IC pads by configuring the IOMUXC. The CTOR register contains bits to control the
data generated for observability on the three output signals above. Table 7-25 provides its field
descriptions.
73FD_4050 (CTOR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
obs_e
n
0
0
0
W
Reset
R
W
Reset
obs_output_0_sel
0
0
0
0
obs_output_1_sel
0
0
0
0
obs_output_2_sel
0
0
0
0
0
Figure 7-22. CCM Testing Observability Register (CTOR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-49
Table 7-25. CTOR Field Descriptions
Field
Description
31–14
Reserved
13
obs_en
observability enable bit. this bit enables the output of the three observability muxes.
0 Observability mux disabled.
1 Observability mux enabled.
12–8
Selection of the signal to be generated on obs_output_0 (output of CCM) for observability on the pads.
obs_spare_output_0_sel 00000 ccm_system_in_stop_mode
00001lpm_current_state[0]
00010 hndsk_current_state[0]
00011shd_current_state[0]
00100 ccm_ipg_stop
00101ccm_pdn_4arm_req
00110emi_freq_change_req
00111ipu_freq_change_req
01000 Reserved
01001Reserved
01010 pll_lrf_sticky1
01011fpm_lrf
01100clk_src_on
01101ipu_lpsr_wakeup_ack
01110src_warm_DVFS_req
01111periph_clk_div_req
10000arm_clk_switch_req
10001ccm_clk_switch_ack
10010 ipu_clk_changed
10011emi_lpmd
10100emi_lpmd_fast
10101emi_lpmd_int1
10110emi_lpmd_slow
10111 Reserved
11000
11001
11010 obs_input_0
11011 obs_input_1
11100 obs_input_2
11101 obs_input_3
11110 obs_input_4
11111 obs_input_5
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-50
Freescale Semiconductor
Table 7-25. CTOR Field Descriptions (continued)
Field
Description
7–4
Selection of the signal to be generated on obs_output_1 (output of CCM) for observability on the pads.
obs_spare_output_1_sel 0000 ccm_system_in_wait_mode
0001 lpm_current_state[1]
0010 hndsk_current_state[1]
0011 ccm_fpm_en
0100 ccm_ipg_wait
0101 ccm_CAMP_dis
0110 dpll_en_dpllip
0111 ccm_pdn_4all_req
1000 emi_freq_change_ack
1001 ipu_freq_change_ack
1010 Reserved
1011Reserved
1100 arm_dsm_request
1101 ccm_lpsr_ipu
1110 gpc_pup_ack
1111 pll_lrf_sticky2
3–0
Selection of the signal to be generated on obs_output_2 (output of CCM) for observability on the pads.
obs_spare_output_2_sel 0000 ccm_int_mem_ipg_stop
0001 lpm_current_state[2]
0010 hndsk_current_state[2]
0011 shd_current_state[1]
0100 pll_lvs
0101 src_clock_ready
0110 ref_clk_en_dpllip
0111 ccm_pup_req
1000 emi_lpack
1001 emi_lpack_fast
1010 emi_lpack_slow
1011 emi_lpack_int1
1100 src_power_gating_reset_done
1101 tzic_dsm_wakeup
1110 gpc_pdn_ack
1111 pll_lrf_sticky3
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-51
7.3.3.21
CCM Low Power Control Register(CLPCR)
Figure 7-23 represents the CCM Low Power Control Register (CLPCR). The CLPCR register contains bits
to control the low power modes operation.Table 7-26 provides its field descriptions.
73FD_4054 (CLPCR)
Access: User read-write
31
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
W
Reset
R
W
Reset
0
0
0
apm_ cosc_
sdma pwrdo
_clk_ wn
gate_
en_bit
0
0
stby_count
0
0
22
21
20
19
18
0
16
bypas
bypas
bypas bypas bypas
bypas bypas
s_sah
s_sd
s_emi s_ipu s_rtic
s_scc s_ma
ara_l
ma_l
_lpm _lpm_ _lpm_
_lpm_ x_lpm
pm_h
pm_h
hs
hs
_hs
_hs
hs
s
s
bypas
s_pmi
ARM
c_vfu
VSTB dis_re SBYO _clk_
lpsr_clk_sel
nction
dis_o
Y
f_osc
S
al_re
n_lpm
ady
0
17
1
1
1
1
0
LPM[1:0]
0
1
Figure 7-23. CCM Low Power Control Register (CLPCR)
Table 7-26. CLPCR Field Descriptions
Field
31–24
23
Description
Reserved
Reserved
Note: Functionality is no longer supported. Bit must be set for better power saving - along with
configuration of CCDR[18] and CCGR4[13:6]. Please refer to description of these bits
for the recommended values.
22
bypass_scc_lpm_hs
Bypass handshake with scc on next entrance to STOP mode. CCM does not wait for the module’s
acknowledge.
0 handshake with SCC on next entrance to STOP mode will be performed. (default).
1 handshake with SCC on next entrance to STOP mode will be bypassed.
21
bypass_max_lpm_hs
Bypass handshake with max on next entrance to low power mode (wait or STOP mode). CCM does
not wait for the module’s acknowledge.
0 handshake with max on next entrance to low power mode will be performed. (default).
1 handshake with max on next entrance to low power mode will be bypassed.
20
bypass_sdma_lpm_hs
Bypass handshake with sdma on next entrance to low power mode (wait or STOP mode). CCM does
not wait for the module’s acknowledge.
0 handshake with sdma on next entrance to low power mode will be performed. (default).
1 handshake with sdma on next entrance to low power mode will be bypassed.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-52
Freescale Semiconductor
Table 7-26. CLPCR Field Descriptions (continued)
Field
Description
19
bypass_emi_lpm_hs
Bypass handshake with emi on next entrance to low power mode (wait or STOP mode). CCM does
not wait for the module’s acknowledge.
0 handshake with emi on next entrance to low power mode will be performed. (default).
1 handshake with emi on next entrance to low power mode will be bypassed.
18
bypass_ipu_lpm_hs
Bypass handshake with IPU on next entrance to low power mode (wait or STOP mode). CCM does
not wait for the module’s acknowledge.
0 handshake with IPU on next entrance to low power mode will be performed. (default).
1 handshake with IPU on next entrance to low power mode will be bypassed.
17
bypass_rtic_lpm_hs
Bypass handshake with rtic on next entrance to low power mode (wait or STOP mode). CCM does not
wait for the module’s acknowledge.
0 handshake with rtic on next entrance to low power mode will be performed. (default).
1 handshake with rtic on next entrance to low power mode will be bypassed.
16
Bypass handshake with SAHARA on next entrance to low power mode (wait or STOP mode). CCM
bypass_sahara_lpm_hs
does not wait for the module’s acknowledge.
0 handshake with SAHARA on next entrance to low power mode will be performed. (default).
1 handshake with SAHARA on next entrance to low power mode will be bypassed.
15–13
Reserved
This bit will allow the operation of automatic clock gating of SDMA - to be used in LP-APM mode.
12
apm_sdma_clk_gate_en 1 Enable automatic clock gating of SDMA clocks. For this feature to work, the CGR bits of SDMA
should be programmed to turn the clocks on in WAIT mode.
_bit
0 Disable automatic clock gating of SDMA clocks. In this case the sdma_clk_enable signal will operate
as indicated by the CGR bits.
11
cosc_pwrdown
In run mode, software can manually control powering down of the on-chip oscillator, that is, generating
‘1’ on cosc_pwrdown signal. If software manually powered down the on-chip oscillator, then sbyos
functionality for on-chip oscillator will be bypassed.
The manual closing of the on-chip oscillator should be performed only in case the reference oscilator
is not the source of all the clocks generation.
0 On chip oscillator will not be powered down, that is, cosc_pwrdown = ‘0’.(default)
1 On chip oscillator will be powered down, that is, cosc_pwrdown = ‘1’.
9–10
stby_count
Standby counter definition. These two bits define, in the case of STOP exit (if vstby bit was set), the
amount of time CCM will wait between PMIC_VSTBY_REQ negation and the check of assertion of
PMIC_VFUNCIONAL_READY. If the counter is used when the handshake is bypassed, then add this
here.
00 CCM will wait 2 CKIL clock cycles
01 CCM will wait 4 CKIL clock cycles
10 CCM will wait 8 CKIL clock cycles
11 CCM will wait 16 CKIL clock cycles
8
VSTBY
Voltage standby request bit. This bit defines if PMIC_VSTBY_REQ pin, which notifies external power
management IC to move from functional voltage to standby voltage, will be asserted in STOP mode.
0 voltage will not be changed to standby voltage after next entrance to STOP mode.
(PMIC_VSTBY_REQ will remain negated - ‘0’)
1 voltage will be requested to change to standby voltage after next entrance to STOP mode.
(PMIC_VSTBY_REQ will be asserted - ‘1’).
Note: When returning from STOP mode, the PMIC_VSTBY_REQ will be deasserted (if it was
asserted when entering STOP mode), and CCM will wait for indication that functional voltage is
ready (by sampling the assertion of pmic_vfuncional_ready) before continuing the process of
exiting from STOP mode. Please refer to stby_count bits.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-53
Table 7-26. CLPCR Field Descriptions (continued)
Field
Description
7
dis_ref_osc
dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock,
that is, generating ‘1’ on ref_en_b signal. If software closed manually the external reference clock,
then sbyos functionality will be bypassed.
The manual closing of external reference oscilator should be performed only in case the reference
oscilator is not the source of any clock generation.
0 external high frequency oscillator will be enabled, that is, ref_en_b = ‘0’.(default)
1 external high frequency oscillator will be disabled, that is, ref_en_b = ‘1’
6
SBYOS
Standby clock oscillator bit. This bit defines if REF_EN_B pin, which disables external high frequency
crystal, and cosc_pwrdown, which power down the on-chip oscillator, will be asserted in STOP mode.
This bit is discarded if dis_ref_osc = ‘1’ for external oscillator, and if cosc_pwrdown=’1’ for the on-chip
oscillator.
0 external high frequency oscillator will not be disabled and the on-chip oscillator will not be powered
down, after next entrance to STOP mode. (ref_en_b will remain asserted - ‘0’ and cosc_pwrdown
will remain de asserted - ‘0’)
1 external high frequency oscillator will be disabled and the on-chip oscillator will be powered down,
after next entrance to STOP mode. (ref_en_b will be deasserted - ‘1’ and cosc_pwrdown will be
asserted - ‘1’). (default). When returning from STOP mode, external oscillator will be enabled again,
the on-chip oscillator will return to oscillator mode, and after oscnt count ccm will continue with the
exit from STOP mode process.
5
ARM_clk_dis_on_lpm
Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait
mode. This is useful for debug mode, when the user wants to simulate entering wait mode and keep
ARM clock functioning.
0 ARM clock enabled on wait mode.
1 ARM clock disabled on wait mode. (default).
Note: software should not enable ARM power gating in wait mode if this bit is cleared.
4–3
lpsr_clk_sel
Controlls the mux to select the lpsr_clk_root generation. Refer to Figure 7-46 and to 7.4.8.4, “Low
Power Screen Refresh Mode (LPSR) for details.
00Reserved
01generate clock from FPM
10 generate clock from FPM/2
11 GND - to be set when LPSR is not used, (for power consumption considerations) (default).
By asserting this bit CCM will bypass waiting for pmic_vfunctional_ready signal when coming out of
2
STOP mode. This should be used for PMIC’s that don’t support the pmic_vfunctional_ready signal.
bypass_pmic_vfunctiona
0 Don’t bypass the pmic_vfunctional_ready signal - CCM will wait for it’s assertion during exit of low
l_ready
power mode if standby voltage was enabled.
1 bypass the pmic_vfunctional_ready signal - CCM will not wait for it’s assertion during exit of low
power mode if standby voltage was enabled.
1–0
LPM[1:0]
Setting the low power mode that system will enter on next assertion of dsm_request signal.
00 Remain in run mode
01 Transfer to wait mode
10 Transfer to STOP mode
11 Transfer to LPSR mode (Low Power Screen Refresh Mode).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-54
Freescale Semiconductor
7.3.3.22
CCM Interrupt Status Register(CISR)
Figure 7-24 represents the CCM Interrupt Status Register (CISR). This is a write one to clear register. Once
a interrupt is generated, software should write one to clear it. Table 7-27 provides its field descriptions.
73FD_4058 (CISR)
R
Access: User write one to
clear
31
30
29
28
27
0
0
0
0
0
26
arm_
podf_l
oade
d
W
Reset
24
23
22
21
20
19
18
17
16
ddr_h
emi_s
perip
axi_b axi_a
ahb_
igh_fr ddr_cl emi_c
divide
low_p
h_clk nfc_p
_podf _podf
podf_
eq_cl k_pod lk_sel
rs_loa
odf_l
_sel_l odf_lo
_load _load
loade
k_sel f_load _load
ded
oade
oade aded
ed
ed
d
ed
_load ed
d
d
ed
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
gpio1
_8_w
akeup
_det
gpio1
_7_w
akeup
_det
gpio1
_6_w
akeup
_det
gpio1
_5_w
akeup
_det
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R gpio1
_9_w
akeup
_det
W w1c
Reset
25
0
gpio1 sdhc2 sdhc1 kpp_
CAM CAM
fpm_r lrf_pll lrf_pll lrf_pll
_4_w _wak _wak wake cosc_
P2_re P1_re
eady
3
2
1
akeup eup_ eup_ up_d ready
ady
ady
et
det
det
_det
Figure 7-24. CCM Interrupt Status Register (CISR)
Table 7-27. CISR Field Descriptions
Field
31–27
26
arm_podf_loaded
Description
Reserved
Interrupt ipi_int_1 generation. due to frequency change of arm_podf. The interrupt will commence
only if arm_podf is loaded during a arm DVFS operation.
0 - interrupt is not genrerated due to frequency change of arm_podf. The frequency of arm_podf is
not changed, the values are changed which cause the frequency to change. The same is also
relevant for next fields and for description of the interrupt mask register.
1 - interrupt genrerated due to frequency change of arm_podf
Interrupt ipi_int_1 generation due to update of ddr_high_freq_clk_sel.
25
ddr_high_freq_clk_sel_l 0 - interrupt is not genrerated due to update of ddr_high_freq_clk_sel.
1 - interrupt genrerated due to update of ddr_high_freq_clk_sel.
oaded
24
ddr_clk_podf_loaded
Interrupt ipi_int_1 generation due to frequency change of ddr_podf
0 - interrupt is not genrerated due to frequency change of ddr_podf
1 - interrupt genrerated due to frequency change of ddr_podf
23
emi_clk_sel_loaded
Interrupt ipi_int_1 generation due to update of emi_clk_sel.
0 - interrupt is not genrerated due to update of emi_clk_sel.
1 - interrupt genrerated due to update of emi_clk_sel.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-55
Table 7-27. CISR Field Descriptions (continued)
Field
22
periph_clk_sel_loaded
Description
Interrupt ipi_int_1 generation due to update of periph_clk_sel.
0 - interrupt is not genrerated due to update of periph_clk_sel.
1 - interrupt genrerated due to update of periph_clk_sel.
21
nfc_podf_loaded
Interrupt ipi_int_1 generation due to frequency change of nfc_podf
0 - interrupt is not genrerated due to frequency change of nfc_podf
1 - interrupt genrerated due to frequency change of nfc_podf
20
ahb_podf_loaded
Interrupt ipi_int_1 generation due to frequency change of ahb_podf
0 - interrupt is not genrerated due to frequency change of ahb_podf
1 - interrupt genrerated due to frequency change of ahb_podf
19
emi_slow_podf_loaded
Interrupt ipi_int_1 generation due to frequency change of emi_slow_podf
0 - interrupt is not genrerated due to frequency change of emi_slow_podf
1 - interrupt genrerated due to frequency change of emi_slow_podf
18
axi_b_podf_loaded
Interrupt ipi_int_1 generation due to frequency change of axi_b_podf
0 - interrupt is not genrerated due to frequency change of axi_b_podf
1 - interrupt genrerated due to frequency change of axi_b_podf
17
axi_a_podf_loaded
Interrupt ipi_int_1 generation due to frequency change of axi_a_podf
0 - interrupt is not genrerated due to frequency change of axi_a_podf
1 - interrupt genrerated due to frequency change of axi_a_podf
16
dividers_loaded
Interrupt ipi_int_1 is generated due to frequency update which is cause by programming any of the
following: axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf, nfc_podf, periph_clk_sel,
emi_clk_sel.
0 - interrupt is not genrerated due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf,
nfc_podf, periph_clk_sel, emi_clk_sel.
1 - interrupt genrerated due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf,
nfc_podf, periph_clk_sel, emi_clk_sel.
15
gpio1_9_wakeup_det
Interrupt ipi_int_2 generation due to change of gpio1_9 input.
0 - interrupt is not genrerated due to change of gpio1_9 input
1 - interrupt genrerated due to change of gpio1_9 input
14
gpio1_8_wakeup_det
Interrupt ipi_int_2 generation due to change of gpio1_8 input.
0 - interrupt is not genrerated due to change of gpio1_8 input
1 - interrupt genrerated due to change of gpio1_8 input
13
gpio1_7_wakeup_det
Interrupt ipi_int_2 generation due to change of gpio1_7 input.
0 - interrupt is not genrerated due to change of gpio1_7 input
1 - interrupt genrerated due to change of gpio1_7 input
12
gpio1_6_wakeup_det
Interrupt ipi_int_2 generation due to change of gpio1_6 input.
0 - interrupt is not genrerated due to change of gpio1_6 input
1 - interrupt genrerated due to change of gpio1_6 input
11
gpio1_5_wakeup_det
Interrupt ipi_int_2 generation due to change of gpio1_5 input.
0 - interrupt is not genrerated due to change of gpio1_5 input
1 - interrupt genrerated due to change of gpio1_5 input
10
gpio1_4_wakeup_det
Interrupt ipi_int_2 generation due to change of gpio1_4 input.
0 - interrupt is not genrerated due to change of gpio1_4 input
1 - interrupt genrerated due to change of gpio1_4 input
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-56
Freescale Semiconductor
Table 7-27. CISR Field Descriptions (continued)
Field
Description
9
sdhc2_wakeup_det
Interrupt ipi_int_2 generation due to insertion of sdhc2 card.
0 - interrupt is not genrerated due to insertion of sdhc2 card
1 - interrupt genrerated due to insertion of sdhc2 card
8
sdhc1_wakeup_det
Interrupt ipi_int_2 generation due to insertion of sdhc1 card.
0 - interrupt is not genrerated due to insertion of sdhc1 card
1 - interrupt genrerated due to insertion of sdhc1 card
7
kpp_wakeup_det
6
cosc_ready
Interrupt ipi_int_2 generation due to key press detection.
0 - interrupt is not genrerated due to key press detection
1 - interrupt genrerated due to key press detection
Interrupt ipi_int_2 generation due to on-chip oscillator ready, that is, oscnt has finished counting.
0 - interrupt is not genrerated due to on-chip oscillator ready
1 - interrupt genrerated due to on-chip oscillator ready
5
CAMP2_ready
Interrupt ipi_int_2 generation due to CAMP2 ready, that is, oscnt has finished counting.
0 - interrupt is not genrerated due to CAMP2 ready
1 - interrupt genrerated due to CAMP2 ready
4
CAMP1_ready
Interrupt ipi_int_2 generation due to CAMP1 ready, that is, oscnt has finished counting.
0 - interrupt is not genrerated due to CAMP1 ready
1 - interrupt genrerated due to CAMP1 ready
3
fpm_ready
Interrupt ipi_int_2 generation due to fpm ready
0 - interrupt is not genrerated due to FPM ready
1 - interrupt genrerated due to FPM ready
2
lrf_pll3
Interrupt ipi_int_2 generation due to lock of pll3
0 - interrupt is not genrerated due to lock ready of pll_3
1 - interrupt genrerated due to lock ready of pll_3
1
lrf_pll2
Interrupt ipi_int_2 generation due to lock of pll2
0 - interrupt is not genrerated due to lock ready of pll_2
1 - interrupt genrerated due to lock ready of pll_2
0
lrf_pll1
Interrupt ipi_int_2 generation due to lock of pll1
0 - interrupt is not genrerated due to lock ready of pll_1
1 - interrupt genrerated due to lock ready of pll_1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-57
7.3.3.23
CCM Interrupt Mask Register(CIMR)
Figure 7-25 represents the CCM Interrupt Mask Register (CIMR). Table 7-28 provides its field
descriptions.
73FD_405c (CIMR)
R
Access: User read-write
31
30
29
28
27
1
1
1
1
1
W
Reset
25
24
23
22
21
20
19
18
17
16
mask
_arm
_podf
_load
ed
mask
_ddr_
high_f
req_cl
k_sel
_load
ed
mask
_ddr_
podf_
_load
ed
mask
_emi_
clk_s
el_loa
ded
mask
_peri
ph_cl
k_sel
_load
ed
mask
_nfc_
podf_
_load
ed
mask
_ahb
_podf
_load
ed
mask
_emi
_slow
_podf
_load
ed
mask
_axi_
b_po
df_loa
ded
mask
_axi_
a_po
df_loa
ded
mask
_divid
ers_lo
aded
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
mask
_gpio
1_8_
wake
up_d
et
mask
_gpio
1_7_
wake
up_d
et
mask
_gpio
1_6_
wake
up_d
et
mask
_gpio
1_5_
wake
up_d
et
mask
_gpio
1_4_
wake
up_d
et
mask
_sdhc
2
_wak
eup_
det
mask
_sdhc
1
_wak
eup_
det
1
1
1
1
1
1
1
R mask
_gpio
W 1_9_
wake
up_d
et
Reset
26
1
mask
mask mask mask mask
mask mask mask
_kpp_
_cosc _CA _CA _fpm
_lrf_pl _lrf_pl _lrf_pl
wake
_read MP2_ MP1_ _read
l1
l2
l3
up_d
y
ready ready
y
et
1
1
1
1
1
1
1
1
Figure 7-25. CCM Interrupt Mask Register (CIMR)
Table 7-28. CIMR Field Descriptions
Field
31–27
26
arm_podf_loaded
Description
Reserved
Mask interrupt generation due to frequency change of arm_podf
0 - don’t mask interrupt due to frequency change of arm_podf - interrupt will be created
1 - mask interrupt due to frequency change of mask_arm_podf_loaded”
mask interrupt generation due to update of ddr_high_freq_clk_sel.
25
mask_ddr_high_freq_clk 0 - don’t mask interrupt due to update of ddr_high_freq_clk_sel - interrupt will be created
1 - mask interrupt due to update of ddr_high_freq_clk_sel
_sel_loaded
24
mask interrupt generation due to frequency change of ddr_podf
mask_ddr_podf_loaded 0 - don’t mask interrupt due to frequency change of ddr_podf - interrupt will be created
1 - mask interrupt due to frequency change of ddr_podf
mask interrupt generation due to update of emi_clk_sel.
23
mask_emi_clk_sel_load 0 - don’t mask interrupt due to update of emi_clk_sel - interrupt will be created
1 - mask interrupt due to update of emi_clk_sel
ed
mask interrupt generation due to update of periph_clk_sel.
22
mask_periph_clk_sel_lo 0 - don’t mask interrupt due to update of periph_clk_sel - interrupt will be created
1 - mask interrupt due to update of periph_clk_sel
aded
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-58
Freescale Semiconductor
Table 7-28. CIMR Field Descriptions (continued)
Field
Description
21
mask interrupt generation due to frequency change of nfc_podf
mask_nfc_podf_loaded 0 - don’t mask interrupt due to frequency change of nfc_podf - interrupt will be created
1 - mask interrupt due to frequency change of nfc_podf
20
mask interrupt generation due to frequency change of ahb_podf
mask_ahb_podf_loaded 0 - don’t mask interrupt due to frequency change of ahb_podf - interrupt will be created
1 - mask interrupt due to frequency change of ahb_podf
mask interrupt generation due to frequency change of emi_slow_podf
19
mask_emi_slow_podf_lo 0 - don’t mask interrupt due to frequency change of emi_slow_podf - interrupt will be created
1 - mask interrupt due to frequency change of emi_slow_podf
aded
mask interrupt generation due to frequency change of axi_b_podf
18
mask_axi_b_podf_loade 0 - don’t mask interrupt due to frequency change of axi_b_podf - interrupt will be created
1 - mask interrupt due to frequency change of axi_b_podf
d
mask interrupt generation due to frequency change of axi_a_podf
17
mask_axi_a_podf_loade 0 - don’t mask interrupt due to frequency change of axi_a_podf - interrupt will be created
1 - mask interrupt due to frequency change of axi_a_podf
d
16
mask_dividers_loaded
mask interrupt generation due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf,
nfc_podf, ddr_podf, ddr_high_freq_clk_sel, periph_clk_sel, emi_clk_sel.
0 - don’t mask interrupt due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf,
nfc_podf, ddr_podf, ddr_high_freq_clk_sel, periph_clk_sel, emi_clk_sel.
1 - mask interrupt due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf, nfc_podf,
ddr_podf, ddr_high_freq_clk_sel, periph_clk_sel, emi_clk_sel.
Mask Interrupt generation due to change of gpio1_9 input.
15
mask_gpio1_9_wakeup 0 - don’t mask interrupt due to change of gpio1_9 input
1 - mask interrupt due to change of gpio1_9 input
_det
Mask Interrupt generation due to change of gpio1_8 input.
14
mask_gpio1_8_wakeup 0 -don’t mask interrupt due to change of gpio1_8 input
1 - mask interrupt due to change of gpio1_8 input
_det
Mask Interrupt generation due to change of gpio1_7 input.
13
mask_gpio1_7_wakeup 0 - don’t mask interrupt due to change of gpio1_7 input
1 -mask interrupt due to change of gpio1_7 input
_det
Mask Interrupt generation due to change of gpio1_6 input.
12
mask_gpio1_6_wakeup 0 - don’t mask interrupt due to change of gpio1_6 input
1 - mask interrupt due to change of gpio1_6 input
_det
Mask Interrupt generation due to change of gpio1_5 input.
11
mask_gpio1_5_wakeup 0 - don’t mask interrupt due to change of gpio1_5 input
1 - mask interrupt due to change of gpio1_5 input
_det
Mask Interrupt generation due to change of gpio1_4 input.
10
mask_gpio1_4_wakeup 0 - don’t mask interrupt due to change of gpio1_4 input
1 - mask interrupt due to change of gpio1_4 input
_det
Mask Interrupt generation due to insertion of sdhc2 card.
9
mask_sdhc2_wakeup_d 0 - don’t mask interrupt due to insertion of sdhc2 card
1 - mask interrupt due to insertion of sdhc2 card
et
Mask Interrupt generation due to insertion of sdhc1 card.
8
mask_sdhc1_wakeup_d 0 - don’t mask interrupt due to insertion of sdhc1 card
1 - mask interrupt due to insertion of sdhc1 card
et
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-59
Table 7-28. CIMR Field Descriptions (continued)
Field
Description
7
Mask interrupt generation due to key press detection.
mask_kpp_wakeup_det 0 - don’t mask interrupt due to key press detection
1 - mask interrupt due to key press detection
6
mask_cosc_ready
mask interrupt generation due to on-chip oscillator ready
0 - don’t mask interrupt due to on-chip oscillator ready - interrupt will be created
1 - mask interrupt due to on-chip oscillator ready
5
mask_CAMP2_ready
mask interrupt generation due to CAMP2 ready
0 - don’t mask interrupt due to CAMP2 ready - interrupt will be created
1 - mask interrupt due to CAMP2 ready
4
mask_CAMP1_ready
mask interrupt generation due to CAMP1 ready
0 - don’t mask interrupt due to CAMP1 ready - interrupt will be created
1 - mask interrupt due to CAMP1 ready
3
mask_fpm_ready
mask interrupt generation due to FPM ready
0 - don’t mask interrupt due to FPM ready - interrupt will be created
1 - mask interrupt due to FPM ready
2
mask_lrf_pll3
mask interrupt generation due to lrf of pll3
0 - don’t mask interrupt due to lrf of pll3 - interrupt will be created
1 - mask interrupt due to lrf of pll3
1
mask_lrf_pll2
mask interrupt generation due to lrf of pll2
0 - don’t mask interrupt due to lrf of pll2 - interrupt will be created
1 - mask interrupt due to lrf of pll2
0
mask_lrf_pll1
mask interrupt generation due to lrf of pll1
0 - don’t mask interrupt due to lrf of pll1 - interrupt will be created
1 - mask interrupt due to lrf of pll1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-60
Freescale Semiconductor
7.3.3.24
CCM Clock Output Source Register (CCOSR)
Figure 7-26 represents the CCM Clock Output Source Register (CCOSR). The CCOSR register contains
bits to control the clocks that will be generated on the output ipp_do_clko1 and ipp_do_clko2 (also named
as CLKO and CLKO2 signals that can selected on i.MX51 pins through IOMUX).Table 7-29 provides its
field descriptions.
73FD_4060 (CCOSR)
R
Access: User read-write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
cko2_
en
W
Reset
R
22
21
20
19
cko2_div[2:0}
18
17
16
cko2_sel[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
cko1_
en
W
Reset
23
0
0
0
0
0
0
0
0
0
cko1_div[2:0}
0
0
0
cko1_sel[3:0]
0
0
0
1
Figure 7-26. CCM Clock Output Source Register (CCOSR)
Table 7-29. CCOSR Field Descriptions
Field
31–25
24
cko2_en
23–21
cko2_div[2:0]
Description
Reserved
Enable of CKO2 clock
0 CKO2 disabled.
1 CKO2 enabled.
Setting the divider of CKO2
000 divide by 1(Default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-61
Table 7-29. CCOSR Field Descriptions (continued)
Field
20–16
cko2_sel[4:0]
15–8
7
cko1_en
Description
Selection of the clock to be generated on cko2
00000dptc_core (this is the ccm input dptc_core1_clk_clko generated to the clko2 BGA contact)
00001 dptc_periph (this is the ccm input dptc_peripheral1_clk_clko generated to the clko2 BGA
contact).
00010 Reserved
00011esdhc1_mshc1_clk_root
00100usboh3_clk_root
00101 wrck_clk _root
00110cspi_clk_root
00111pll1_ref_clk
01000 esdhc3_clk_root
01001ddr_clk_root
01010arm_axi_clk_root (Default)
01011 usbphy_pll_out_480
01100vpu_rclk_root
01101ipu_hsp_clk_root
01110 osc_clk
01111 ckih_CAMP1_clk
10000 fpm_clk
10001 esdhc2_clk_root
10010ssi1_clk_root
10011ssi2_clk_root
10100 Reserved
10101 reserved
10110lpsr_clk_root
10111 pgc_clk_root
11000 tve_ext_clk
11001usb_phy_clk_root
11010 tve_216_54_clk_root
11011lp_apm clock
11100 uart_clk_root
11101spdif0_clk_root
11110 spdif1_clk_root
11111spare_input_1 div 8 (connected in SOC to async ref clock for reference clock generation of
ARM) This clock source is always divided by 8 before supplying this clock to the cko2 mux.
Reserved
Enable of CKO1 clock
0 CKO1 disabled.
1 CKO1 enabled.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-62
Freescale Semiconductor
Table 7-29. CCOSR Field Descriptions (continued)
Field
Description
6–4
cko1_div[2:0]
Setting the divider of CKO1
000 divide by 1(Default)
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
3–0
cko1_sel[3:0]
Selection of the clock to be generated on cko1
0000 arm_clk_root
0001 pll1_sw_clk (Default)
0010 pll2_sw_clk
0011 pll3_sw_clk
0100 emi_core_clk_root
0101 Reserved
0110 enfc_clk_root
0111 Reserved
1000 di_clk_root
1001 Reserved
1010 Reserved
1011 ahb_clk_root
1100 ipg_clk_root
1101 perclk_root
1110 ckil_sync_clk_root
1111 reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-63
7.3.3.25
CCM General Purpose Register(CGPR)
Figure 7-27 represents the CCM General Purpose Register (CGPR). This is a regular read/write
implemented register, which can serve for future possible usage. the respective bits are connected to
cgpr_dout[31:0] output of ccm. Few bits are already in use, The other bits are free to be used in future
usage. Table 7-30 provides its field descriptions.
73FD_4064 (CGPR)
31
30
29
Access: User read-write
28
27
26
25
24
23
R
22
21
20
19
18
17
16
W
0
0
0
0
0
0
0
0
arm_
async
_ref_
en
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
1
0
arm_async_ref_sel
1
1
1
1
1
1
0
0
1
overid
e_ap
m_e
mi_int
1_clo
ck_ga
ting
1
1
1
1
1
1
0
0
1
1
R
W arm_
async
_ref_
sel[5]
Reset
1
efuse
_prog
FPM_
_sup
mux_
ply_g
select
ate
0
0
Figure 7-27. CCM Register (CGPR)
Table 7-30. CGPR Field Descriptions
Field
Description
31– 24
Reserved for future use. Those bits are connected to ccm output cgpr_dout[31-10]
23
arm_async_ref_en
Enable of ARM async ref circuit. This bit is connected to ccm output cgpr_dout[23].
0 - ARM async ref circuit disabled
1- ARM async ref circuit enabled
22
arm_async_ref_sel[7]
Bit 7 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 7 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
21
arm_async_ref_sel[6]
Bit 6 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 6 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
20
arm_async_ref_sel[4]
Bit 4 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 4 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-64
Freescale Semiconductor
Table 7-30. CGPR Field Descriptions (continued)
Field
Description
19
arm_async_ref_sel[3]
Bit 3 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 3 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
18
arm_async_ref_sel[2]
Bit 2 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 2 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
17
arm_async_ref_sel[1]
Bit 1of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 1 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
16
arm_async_ref_sel[0]
Bit 0 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 0 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
15
arm_async_ref_sel[5]
Bit 5 of frequency select of async reference circuit.
0 frequency of async reference circuit is defined by other arm_async_ref_sel bits
1 frequency of async reference circuit is reference number 5 (this is in case all other
arm_async_ref_sel are defined as ‘0’.
14–6
Reserved for future use. Those bits are connected to ccm output cgpr_dout[14-6]
Defines override of the automatic clock gating control of EMI clock: aclk_intr. If this bit is defined as
5
overide_apm_emi_intr_c ‘0’, there will not be an override, and the aclk_intr will be gated each time both m3_clk_gate_en and
m4_clk_gate_en are ‘0’. If this bit is ‘1’, then aclk_intr will not be gated based on the above two signals.
lock_gating
In APM, this feature will aid consuming less power since EMI aclk_intr will be gated each time there
is no access of ARM or SDMA.
1 override aclk_intr input of EMI.
0 don’t override the aclk_intr automatic control, that is, allow control of m3_clk_gate_en and
m4_clk_gate_en on aclk_intr.
4
Defines the value of the output signal cgpr_dout[4]. Gate of programming supply for efuse programing
efuse_prog_supply_gate
0 fuse programing supply voltage is gated off to the efuse module
1 allow fuse programing.
3
FPM_mux_select
2–0
FPM_mux_select - Defines the value of the output signal cgpr_dout[3] going to FPM. FPM uses this
signal to mux between FPM output and FPM internal oscilator. This functionality is used for testability
of FPM. Refer to FPM spec for further details.
0 fpm_mux_select output is 0
1 fpm_mux_select output is 1
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-65
NOTE
ARM_CLK_ROOT is muxed in top level between the ccm_arm_clock_root
output and the clock generated by reference circuit. The frequency of the
reference circuit is defined by 8 control frequency select bits of the async
reference circuit. Only one single select bit should equal to ‘1’ - all the other
select bits should equal to ‘0’. The frequency is defined by the next table:
Table 7-31. Async Reference Circuit Settings
Field
Description
arm_async_ref_sel[7:0] = 00000001
Frequency Option 0
arm_async_ref_sel[7:0] = 00000010
Frequency Option 1
arm_async_ref_sel[7:0] = 00000100
Frequency Option 2
arm_async_ref_sel[7:0] = 00001000
Frequency Option 3
arm_async_ref_sel[7:0] = 00010000
Frequency Option 4
arm_async_ref_sel[7:0] = 00100000
Frequency Option 5
arm_async_ref_sel[7:0] = 01000000
Frequency Option 6
arm_async_ref_sel[7:0] = 10000000
Frequency Option 7
7.3.3.26
CCM Clock Gating Register(CCGR)
Figure 7-28 through Figure 7-33 represents the CCM Clock Gating Register (CCGR). The clock gating
Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 7 CGR registers.
The number of registers required is according to the number of peripherals in the system. Table 7-32
through Table 7-38 provides its field descriptions.
73FD_4068 (CCGR0)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-28. CCM Clock Gating Register (CCGR0)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-66
Freescale Semiconductor
73FD_406c (CCGR1)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-29. CCM Clock Gating Register (CCGR1)
73FD_4070 (CCGR2)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-30. CCM Clock Gating Register (CCGR2)
73FD_4074 (CCGR3)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-31. CCM Clock Gating Register (CCGR3)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-67
73FD_4078 (CCGR4)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-32. CCM Clock Gating Register (CCGR4)
73FD_407c (CCGR5)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-33. CCM Clock Gating Register (CCGR5)
73FD_4080 (CCGR6)
31
30
Access: User read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 7-34. CCM Clock Gating Register (CCGR6)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-68
Freescale Semiconductor
7.3.4
CG(i) bits
This bits are used to turn on/off the clock to each module independently. Table 7-32 details the possible
clock activity conditions for each module.
Table 7-32. CG Bit Description
CGR value
Clock Activity Description
00
Clock is off during all modes. stop enter hardware handshake is disabled.
01
Clock is on in run mode, but off in WAIT and STOP modes
10
Not applicable (Reserved).
11
clock is on during all modes, except STOP mode.
Note: Stop the module before clearing its bits because clocks to the module will be stopped immediately.
The following tables show the register mappings for the different CGRs. The clock connectivity table
should be used to match the “CCM output affected” to the actual clocks going into the modules.
Table 7-33. CCGR0 Register Mapping
CG bit index
Controlled Clocks
Comments
CCM output affected
0
arm_bus
to control ipg bus of arm
arm_bus_clk_enable
1
arm_axi
to control arm_axi input clock
arm_axi_clk_enable
2
arm_debug
to control pclk and atclk busses of arm
arm_debug_clk_enable
3
tzic
to control tzic clocks
tzic_clk_enable
4
dap clocks
dap_clk_enable
5
tpiu clocks
tpiu_clk_enable
6
cti2 clocks
cti2_clk_enable
7
cti3 clocks
cti3_clk_enable
8
ahbmux1 clocks
ahbmux1_clk_enable
9
ahbmux2 clocks
ahbmux2_clk_enable
10
romcp clocks
11
rom clocks
12
aips_tz1 clocks
aips_tz1_clk_enable
13
aips_tz2 clocks
aips_tz2_clk_enable
14
ahb_max clocks
ahb_max_clk_enable
15
iim clocks
romcp_clk_enable
rom_clk_enable
affects also fusebox_poly_128_1,
fusebox_poly_256_1, fusebox_poly_256_2,
fusebox_poly_256_3
iim_clk_enable
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-69
Table 7-34. CCGR1 Register Mapping
MCG bit index
Controlled Clocks
Comments
CCM output affected
0
tmax1 clocks
tmax1_clk_enable
1
tmax2 clocks
tmax2_clk_enable
2
tmax3 clocks
tmax3_clk_enable
3
uart1_ipg_clk
affects ipg_clk input to uart1
uart1_clk_enable
4
uart1_perclk
affects ipg_perclk input to uart1
uart1_serial_clk_enable
5
uart2_ipg_clk
affects ipg_clk input to uart2
uart2_clk_enable
6
uart2_perclk
affects ipg_perclk input to uart2
uart2_serial_clk_enable
7
uart3_ipg_clk
affects ipg_clk input to uart3
uart3_clk_enable
8
uart3_perclk
affects ipg_perclk input to uart3
uart3_serial_clk_enable
9
i2c1 clocks
i2c1_serial_clk_enable
10
i2c2 clocks
i2c2_serial_clk_enable
11
hsi2c_ipg_clk
12
hs2ic_serial clock
13
firi ipg clock
14
firi serial clock
15
SCC clocks
affects hsi2c ipg clk
hsi2c_clk_enable
affects hsi2c ipg_hsi2c_clk (the serial clock)
hsi2c_serial_clk_enable
firi_clk_enable
firi_serial_clk_enable
scc_clk_enable
affects scc_clk_enable.
it is not possible to close SCC clocks during run
mode. writting ‘00’ to this cgr will not affect the
clocks of SCC.
Closing the clocks of SCC will eventually block
the access to the internal memory. In WAIT
mode the SCC clocks can be closed only if it is
guaranteed that no master will access the
internal memory during the time spend in
WAIT mode.
The SCC clocks will be closed in WAIT mode only
if SAHARA clocks were closed as well.
During WAIT mode, if SCC will assert either
hclk_en signal or ipg_clk_en signal, the CCM
will assert scc_clk_enable and will thus enable
the SCC clocks. The WAIT mode will not be
exited due to this assertion.
Table 7-35. CCGR2 Register Mapping
MCG bit index
Controlled Clocks
Comments
CCM output affected
0
usb phy clock
1
epit1_ipg_clk
affects ipg_clk input of epit1
epit1_clk_enable
2
epit1_highfreq
affects ipg_clk_highfreq input of epit1
epit1_serial_clk_enable
3
epit2_ipg_clk
affects ipg_clk input of epit2
epit2_clk_enable
usb_phy_clk_enable
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-70
Freescale Semiconductor
MCG bit index
Controlled Clocks
Comments
CCM output affected
4
epit2_highfreq
affects ipg_clk_highfreq input of epit2
epit2_serial_clk_enable
5
pwm1_ipg_clk
affects ipg_clk input of pwm1
pwm1_clk_enable
6
pwm1_highfreq
affects ipg_clk_highfreq input of pwm1
pwm1_serial_clk_enable
7
pwm2_ipg_clk
affects ipg_clk input of pwm2
pwm2_clk_enable
8
pwm2_highfreq
affects ipg_clk_highfreq input of pwm2
pwm2_serial_clk_enable
9
gpt_ipg_clk
affects ipg_clk input of gpt
gpt_clk_enable
10
gpt_highfreq
affects ipg_clk_highfreq input of gpt
gpt_serial_clk_enable
11
owire clocks
12
fec clocks
13
usboh3_ipg_ahb
14
usboh3_60M
15
tve clock
owire_serial_clk_enable
affects also csync_fec
fec_clk_enable
affects ipg_clk and ipg_ahb_clk inputs of
usboh3
usboh3_clk_enable
affects ipg_clk_60Mhz input of usboh3
usboh3_serial_clk_enable
tve_clk_enable
Table 7-36. CCGR3 Register Mapping
MCG bit index
Controlled Clocks
Comments
CCM output affected
0
esdhc1_ipg_hclk
1
esdhc1_perclk
2
esdhc2_ipg_hclk
3
esdhc2_perclk
4
esdhc3_ipg_hclk
5
esdhc3_perclk
6
esdhc4_ipg_hclk
7
esdhc4_perclk
8
ssi1_ipg
9
ssi1_ssi_clk
10
ssi2_ipg
11
ssi2_ssi_clk
12
ssi3_ipg
13
ssi3_ssi_clk
14
ssi_ext1
ssi_ext1_clk_enable
15
ssi_ext2
ssi_ext2_clk_enable
affects ipg_clk and hclk inputs of esdhc1
esdhc1_clk_enable
affects ipg_clk_perclk input of esdhc1
esdhc1_serial_clk_enable
affects ipg_clk and hclk inputs of esdehc2
esdhc2_clk_enable
affects ipg_clk_perclk input of esdhc2
esdhc2_serial_clk_enable
affects ipg_clk and hclk inputs of esdehc3
esdhc3_clk_enable
affects ipg_clk_perclk input of esdhc3
esdhc3_serial_clk_enable
affects ipg_clk and hclk inputs of esdehc4
esdhc4_clk_enable
affects ipg_clk_perclk input of esdhc4
esdhc4_serial_clk_enable
affects ipg_clk input of ssi1
ssi1_clk_enable
affects ccm_ssi_clk input of ssi1
ssi1_serial_clk_enable
affects ipg_clk input of ssi2
ssi2_clk_enable
affects ccm_ssi_clk input of ssi2
ssi2_serial_clk_enable
affects ipg_clk input of ssi3
ssi3_clk_enable
affects ccm_ssi_clk input of ssi3
ssi3_serial_clk_enable
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-71
Table 7-37. CCGR4 Register Mapping
MCG bit index
Controlled Clocks
Comments
CCM output affected
0
pata
1
sim ipg clock
2
sim serial clock
3
—
4
—
5
—
6
—
7
SAHARA
8
rtic clocks
it is not possible to close rtic clocks during run rtic_clk_enable
mode. writting ‘00’ to this cgr will not affect
the clocks of rtic.
9
ecspi1_ipg
affects ipg_clk input of ecspi1
ecspi1_clk_enable
10
ecspi1_perclk
affects ipg_clk_per input of ecspi1
ecspi1_serial_clk_enable
11
ecspi2_ipg
affects ipg_clk input of ecspi2
ecspi2_clk_enable
12
ecspi2_perclk
affects ipg_clk_per input of ecspi2
ecspi2_serial_clk_enable
13
cspi_ipg
affects ipg_clk input of cspi
cspi_clk_enable
14
srtc clocks
15
sdma clocks
pata_clk_enable
affects ipg_clk input to sim
sim_clk_enable
affects ipg_perclk input to sim
sim_serial_clk_enable
—
Note: These clocks are no longer supported.
For better power saving,
it is recommended to clear
CCGR4[13:6] bits - along with
configuration of CCDR[18] and
CLPCR[23] bits. Please refer to
description of these bits for the
recommended values.
—
—
—
sahara_clk_enable
srtc_clk_enable
affects also ahbs2axi1
sdma_clk_enable
Table 7-38. CCGR5 Register Mapping
MCG bit index
Controlled Clocks
Comments
CCM output affected
0
spba clocks
spba_clk_enable
1
GPU clocks
gpu_clk_enable
2
garb clocks
garb_clk_enable
3
vpu clocks
vpu_clk_enable
4
vpu reference clock
5
IPU clocks
vpu_serial_clk_enable
ipu_clk_enable
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-72
Freescale Semiconductor
MCG bit index
Controlled Clocks
Comments
CCM output affected
6
ipmux1, ipmux2
7
emi_fast
affects only fast clock of emi
emi_fast_clk_enable
8
emi_slow
affects only slow clock of emi
emi_slow_clk_enable
9
emi_int1
affects only int1 clock of emi
emi_int1_clk_enable
10
emi_enfc
affects only enfc clock of emi
emi_enfc_clk_enable
11
emi wrck clock
affects the wrck clock of emi
emi_clk_enable
12
gpc ipg clock
gpc_clk_enable
13
spdif0 clock
spdif0_clk_enable
14
spdif1 clock
spdif1_clk_enable
15
spdif ipg clock
spdif_clk_enable
Bit 12 affects ipmux1 via spare_output_1, and spare_output_1 and
spare_output_2.
Bit 13 affects ipmux2 via spare_output_2.
The default value of those bits is ‘11’ - for
the default case, CCM will generate ‘1’ for
both spare_output_1 and spare_output_2.
If either one of those bits will be set to ‘0’,
then the corresponding output will be set to
‘0’ when system enters WAIT mode. This
will allow system to turn off the IPMUX
clocks in WAIT mode and can be used in
LP-APM to preserve the IPMUX power if no
accesses are expected on the IP bus. In run
mode the IPMUX clocks will not be closed
and the settings of those bits will not affect
RUN mode.
Table 7-39. CCGR6 Register Mapping
MCG bit index
Controlled Clocks
Comments
CCM output affected
0
—
—
1
—
Note: These clocks are no longer supported.
For better power saving, it is
recommended to clear CCGR6[3:0]
bits.
2
CSI mclk1
Clock root gated internally in CCM- no
external clock enable output is generated.
3
CSI mclk2
Clock root gated internally in CCM - no
external clock enable output is generated.
4
emi_garb
affects only garb clock to emi
5
IPU di0 clock
ipu_di0_clk_enable
6
IPU di1 clock
ipu_di1_clk_enable
7
gpu2d clock
gpu2d_clk_enable
8
Reserved
—
emi_garb_clk_enable
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-73
MCG bit index
Controlled Clocks
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
7.3.4.1
Comments
CCM output affected
CCM Module Enable Override Register(CMEOR)
Figure 7-35 represents the CCM Module Enable Override Register (CMEOR). The CMEOR register
contains bits to override the clock enable signal from the module. This should be used in case that it is
decided to bypass the clock enable signals from the modules. In this case the word bypass is defined as the
clock remaining on, unless gated by the corresponding CCGR bit. This bit will be applicable only for
module that their clock enable signal is used provides its field descriptions.
73FD_4084 (CMEOR)
Access: User read-write
31
30
29
28
27
26
25
24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
mod_
en_ov
_saha
ra
1
1
R
W
Reset
R mod_
en_ov
W _emi_
int1
Reset
1
mod_ mod_ mod_
en_ov en_ov en_ov
_emi_ _emi_ _emi_
slow fast garb
1
1
1
1
1
23
22
21
20
mod_ mod_ mod_ mod_
en_ov en_ov en_ov en_ov
_emi_ _emi_ _emi_ _emi
_m4
m5
m6
m7
19
18
1
1
1
1
1
16
mod_ mod_ mod_ mod_
en_ov en_ov en_ov en_ov
_emi _emi_ _emi_ _emi_
m0
m1
m2
_m3
mod_
mod_
mod_
mod_
mod_ mod_ mod_ mod_ mod_
en_ov
en_ov
en_ov
en_ov
en_ov en_ov en_ov en_ov en_ov
_owir
_esd
_gpu
_iim
_vpu _dap _gpu _epit _gpt
e
hc
2d
1
17
1
1
1
Figure 7-35. CCM Module Enable Override Register (CMEOR)
Table 7-40. CMEOR Field Descriptions
Field
31–27
26
Description
Reserved
reserved
Note: Functionality is no longer supported. Bit shouldn’t be altered and must remain in its default
value.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-74
Freescale Semiconductor
Table 7-40. CMEOR Field Descriptions (continued)
Field
Description
25
reserved
Note: Functionality is no longer supported. Bit shouldn’t be altered and must remain in its default
value.
24
reserved
Note: Functionality is no longer supported. Bit shouldn’t be altered and must remain in its default
value.
23
mod_en_ov_emi_m7
overrides clock enable signal from emi_m7 - clock will not be gated based on emi’s signal
‘m7_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
22
mod_en_ov_emi_m6
overrides clock enable signal from emi_m6 - clock will not be gated based on emi’s signal
‘m6_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
21
mod_en_ov_emi_m5
overrides clock enable signal from emi_m5 - clock will not be gated based on emi’s signal
‘m5_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
20
mod_en_ov_emi_m4
overrides clock enable signal from emi_m4 - clock will not be gated based on emi’s signal
‘m4_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
19
mod_en_ov_emi_m3
overrides clock enable signal from emi_m3 - clock will not be gated based on emi’s signal
‘m3_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
18
mod_en_ov_emi_m2
overrides clock enable signal from emi_m2 - clock will not be gated based on emi’s signal
‘m2_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
17
mod_en_ov_emi_m1
overrides clock enable signal from emi_m1 - clock will not be gated based on emi’s signal
‘m1_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
16
mod_en_ov_emi_m0
overrides clock enable signal from emi_m0 - clock will not be gated based on emi’s signal
‘m0_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
15
mod_en_ov_emi_int1
overrides clock enable signal from emi_int1 - clock will not be gated based on emi’s signal
‘int1_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
14
mod_en_ov_emi_slow
overrides clock enable signal from emi_slow - clock will not be gated based on emi’s signal
‘slow_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-75
Table 7-40. CMEOR Field Descriptions (continued)
Field
Description
13
mod_en_ov_emi_fast
overrides clock enable signal from emi_fast - clock will not be gated based on emi’s signal
‘fast_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
12
mod_en_ov_emi_garb
overrides clock enable signal from emi_garb - clock will not be gated based on emi’s signal
‘garb_clk_gate_en’.
0 dont override module enable signal
1 override module enable signal
11
10
mod_en_ov_gpu2d
Reserved
overrides clock enable signal from gpu2d - clock will not be gated based on gpu2d’s signal
‘gpu2d_busy’.
0 dont override module enable signal
1 override module enable signal
9
mod_en_ov_vpu
overrides clock enable signal from vpu- clock will not be gated based on vpu’s signal ‘vpu_idle’.
0 dont override module enable signal
1 override module enable signal
8
mod_en_ov_dap
overrides clock enable signal from dap- clock will not be gated based on dap’s signal ‘dap_dbgen’.
0 dont override module enable signal
1 override module enable signal
7
mod_en_ov_gpu
overrides clock enable signal from GPU.
0 dont override module enable signal
1 override module enable signal
6
mod_en_ov_epit
overrides clock enable signal from epit - clock will not be gated based on epit’s signal
‘ipg_enable_clk’.
0 dont override module enable signal
1 override module enable signal
5
mod_en_ov_gpt
overrides clock enable signal from gpt - clock will not be gated based on gpt’s signal ‘ipg_enable_clk’.
0 dont override module enable signal
1 override module enable signal
4
mod_en_ov_esdhc
overrides clock enable signal from esdhc - clock will not be gated based on esdhc’s signals ‘hclk_en’,
‘ipg_clk_en’ and ‘ipg_per_clk_en’.
0 dont override module enable signal
1 override module enable signal
3
mod_en_ov_iim
2
mod_en_ov_owire
1
0
mod_en_ov_sahara
overrides clock enable signal from iim - clock will not be gated based on iim’s signal ‘iim_clk_en’.
0 dont override module enable signal
1 override module enable signal
overrides clock enable signal from owire - clock will not be gated based on owire’s signal
‘owire_clk_en’.
0 dont override module enable signal
1 override module enable signal
Reserved
overrides clock enable signal from SAHARA.
0 dont override module enable signal
1 override module enable signal
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-76
Freescale Semiconductor
7.4
Functional Description
This section describes clock generation.
7.4.1
External Low Frequency Clock—CKIL
The i.MX51 can use either a 32 kHz, 32.768 kHz, or a 38.4 kHz crystal as the external low frequency
source. Throughout this chapter, the low frequency crystal is referred to as the 32 kHz crystal. CMOS input
buffer with schmitt trigger feature is used as the receiver of 32 kHz clock. This clock source should be
active all the time the i.MX51 is powered on.
The 32 kHz entering the CCM is referred as CKIL. It is synchronized to ipg_clk and supplied to modules
that need it.
The 32 kHz clock also enters the FPM to produce the DPLL reference clock.
7.4.2
External High Frequency Clock CKIH and Internal Oscillator
An external crystal connected to the on-chip oscillator circuit is used to generate a reference for the three
on-chip PLLs. The oscillator circuit frequency range is 22 to 27 MHz. For flexibility, inputs CKIH1 and
CKIH2 may be used to supply special frequencies for the TV encoder, SPDIF, and others. as an alternate
to the PLL-generated clocks. Because CKIH1 and CKIH2 pass through the CAMP (Clock Amplifier)
modules, their frequency range is limited to the frequency range of the CAMP. See the Clock Amplifier
Parameters section of the data sheet for specifications.
7.4.3
DPLLs (Digital Phase-Locked Loops) and Reference Clocks
There are three DPLLs in the i.MX51 project, as follows:
• PLL1 (typical functional frequency 800 MHz)
• PLL2 (typical functional frequency 665 MHz)
• PLL3 (typical functional frequency 216 MHz)
Each DPLL is controlled by a PLL-IP interface module, which can use the following options as DPLL
reference clock:
• Output of OSC (typical functional frequency 24 MHz)
• Output of FPM (multiplied CKIL) (typical functional frequency 32.768 kHz)
7.4.4
PLL Clock Selector
A clock selector exists on each DPLL output of the 3 DPLLs. The clock selector is used to select between
the gated clock output of the DPLL (dpgdck) and the divided by 2 gated clock output of the DPLL
(dpgdck_2). Please refer to DPLL chapter for the description of the DPLL output and input pins.
The selection of dpgdck_2 is done by setting DPDCK02_EN bit (DPCTL[12]) in the corresponding
DPLL-IP interface module.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-77
When low range frequencies are required by the DPLL, such as 150Mhz, the divided output should be
selected.
PLL<n>
dpgdck
0
dpgdck_2
DPLLIP<n>:DPCTL:
pll<n>_main_clk
1
DPDCK02_EN
Figure 7-36. PLL clock selector
7.4.5
CLKSS Support
CLKSS input to the i.MX51 is internally connected to init_dp_ctl_dpllip[8] signal of each PLL-IP
interface. This signal defines the initialization configuration of clock source to be used by PLL-IP
interface:
• If CLKSS = 0, then OSC output is used as reference clock for all three DPLL_IPs.
• If CLKSS = 1, then FPM output is used as reference clock for all three DPLL_IPs.
During ignition process the value of clkss signal will be used in ccm to set either cosc_en bit or fpm_en
bit, depending on which is the selected reference clock. The CAMP1_en and CAMP2_en will always be
enabled when coming out of ignition process, no matter what was the value of clss. In run mode, software
can control cosc_en, CAMP1_en, CAMP2_en and fpm_en by reprograming those bits.
7.4.6
CCM Internal Clock Generation
The clock generation is comprised of three submodules, as follows:
• CCM_CLK_SWITCHER
• CCM_CLK_IGNITION
• CCM_CLK_ROOT_GEN
• CCM_CLK_SWITCHER
CCM_CLK_SWITCHER sub module receives the pll output clocks and the pll bypass clocks. It generates
the following three main switchable clocks to be delivered for CCM_CLK_ROOT_GEN:
• pll1_sw_clk (typical functional frequency 800Mhz - used to supply ARM platform)
• pll2_sw_clk (typical functional frequency 665Mhz - used to supply axi/ahb/ip buses clocks)
• pll3_sw_clk (typical functional frequency 216Mhz - used to supply serial clocks like usb, ssi, and
so on.)
Figure 7-37 describes the generation of the three switchable clocks. It also includes the frequency switch
control submodule that is responsible for the frequency change during DVFS scenario.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-78
Freescale Semiconductor
PLL_bypass_en1(from jtag)
CCM boundary
CCSR: pll1_sw_clk_sel
GPC
CLKSS
init_dp_ctl_dpllip [8]
CKIL
FPM
LFS
HFS
FREQUENCY
SWITCH
CONTROL
pll_lvs
pll_lrf_sticky
PLL-IP
Interface
1
PLL 1
(800M)
Periph
switch
pll1_ sw_clk
(800M)
pll1_main_clk
CS
0
PLL_bypass_en1(from jtag)
step
CCSR: step_sel[1:0] logic
OSC
1
1
CCSR: lp_apm
1
osc_clk
lp_apm clock
4
0
0
1
PLL1 bypass clk
1
0
burn_in_bist
step_clk
fpm_clk
2
pll2_div
default=1
CCSR: pll2_div_podf
pll3_div
default=1
3
CCSR: pll3_div_podf
PLL-IP
Interface
2
PLL 2
(665M)
CS
pll2_main_clk
burn_in_bist
pll1_ref_clk
PLL2 bypass clk
PLL_bypass_en2(from jtag)
pll2_sw_clk
(665M)
0
1
1
0
CCSR: pll2_sw_clk_sel
PLL-IP
Interface
3
PLL 3
(216M)
CS
PLL3 bypass clk
PLL_bypass_en3(from jtag)
fpm_clk
CS
2
pll3_main_clk
burn_in_bist
pll1_ref_clk
1
pll3_sw_clk
(216M)
0
3
1
0
CCSR: pll3_sw_clk_sel
- PLL Clock Selector
Figure 7-37. Switchable Clock Generation
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-79
7.4.6.1
PLL Bypass Procedure
CCM_CLK_SWITCHER sub module includes capability for each of the pll_main_clk’s to be bypassed
with an external bypass clk, and in this way supply to the three pll_sw_clk outputs a external bypass clock.
In burn_in_bist mode the PLL bypass clocks for all three PLLs will be supplied from pll1_ref_clk (the
output of DPLLIP1).
The decision to shift from pll_main_clk to pll_bypass_clk is done either by programable bits in CCSR or
by three pll_bypass_en signals which are driven from jtag module. Since the switch between the clocks is
done by a glitch less multiplexer, then both pll_main_clk and pll_bypass_clk should be running to
complete the shift glitchlessly. In case the selection is done in reset, then it is not needed that both clocks
will be available simultaneously.
NOTE
Since the bypass clock for pll1_sw_clk is generated from a multiplexer, the
software needs to set the bypass clock via CCSR:step_sel[1:0] before
shifting the glitchless mux via CCSR:pll1_sw_clk_sel. Similarly, when
returning from pll_bypass, the system should first change the glitchless mux
via CCSR:pll1_sw_clk_sel and only after that it is completed is change
allowed to the CCSR:step_sel[1:0].
If the shift to pll_bypass for pll1_sw_clk is done via pll_bypass_en1 signal, then the pll_bypass_en1 signal
should first set the step_select mux to prepare the bypass clock, and only after that to shift the glitch less
mux from pll1_main_clk to the step_sel multiplexer output. This is taken care of since shift of step_sel
mux is done faster than shift of the glitch less mux. When returning from pll_bypass to pll1_main_clk the
step_sel mux control should be delayed until the glitch less mux has shifted back to the pll1_main_clk.
This is taken care of in hardware by step_logic sub module.
7.4.6.2
Step Logic
The step logic allows the pll_bypass enable signal to bypass the step_sel bits and to set the 4x1 mux to the
pll1_bypass_clk option. This sub module also delays the step_sel mux as described in PLL bypass
procedure above.
7.4.6.3
DPLL-IP Reference Clock Connectivity
For all three DPLL-IPs, connections are as follows:
• The input clk2 is connected to on-chip oscillator clock output.
• The input clk3 is connected to FPM output (fpm_clkout).
• The input init_dp_ctl_dpllip [8] receives ccm_ipp_ind_clkss (this goes also to ccm).
• The input init_dp_ctl_dpllip [9] is connected to Vcc.
The above connections allows clkss to define in reset whether the FPM output or the on-chip oscillator
output is chosen.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-80
Freescale Semiconductor
7.4.6.4
PLL Reference Clock Change
If software wants to change the PLL reference for a specific PLL, between FPM and on-chip oscillator
outputs, or if software wants to stop a specific PLL, then software needs first to move all the clocks
generated from this PLL to another PLL which is not changed. This should be done via the glitchless
muxes for the clocks which cant be stopped (core and bus clocks). Then software should reprogram the
respective dpll_ip: first configure DP_CONFIG[1], so that it will allow auto restart of the PLL on next
update of the reference clock. Then software should change DP_CTL[8:9], to change the reference clock
mux. In this case the respective PLL will restart and once its locked it will generate lrf_sticky signal to
ccm. This signal can cause an interrupt from ccm (if configured in CIMR register). Based on this interrupt,
software can be notified that the PLL is ready with the new reference clocks. Software should also take
care of reprograming the PLL settings to match the new reference clock.At this point software can change
the glitch less muxes to supply clock from the respective PLL that was changed.
7.4.6.5
CCM_CLK_IGNITION
The responsibility of the ccm_clk_ignition sub module is to manage the wake up after reset of the FPM,
on-chip oscillator, CAMP1, CAMP2, dpll_ip and PLL modules. Its task starts with de-assertion of
early_reset from the Reset controller. Its task finishes with assertion signal src_clock_ready that notifies
reset controller that the root clocks are ready.
Figure 7-38 describes the connectivity of CCM clock ignition.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-81
CCM_CLK_IGNITION
clkss
CLKSS
init_dp_ctl_dpllip [8]
init_dp_ctl_dpllip [5]=1
CKIL
OSC
clk2
FPM
clk3
LFS
HFS
pll_lrf_sticky
PLL-IP
Interface
PLL 1
(800M)
ref_clk_en_dpllip
dpll_en_dpllip
src_clock_ready
ccm_fpm_en
cosc_en
init_dp_ctl_dpllip
pll_lrf_sticky
PLL-IP
Interface
PLL 2
(665M)
pll_lrf_sticky
init_dp_ctl_dpllip
PLL-IP
Interface
PLL 3
(216M)
Figure 7-38. CCM Clock Ignition Connectivity
CLKSS is entering the three PLL_IP’s to select upon reset which of the two clock sources to be used as
reference clock for the PLL’s. CLKSS is entering the init_dp_ctl_dpllip[8], while init_dp_ctl_dpllip[9] is
constantly connected to ‘1’. This allows DPLL IP to choose between option 10 and 11 for dp_ctl[9,8]. It
is not allowed to choose options 00 and 01 for dp_ctl[9,8], that is, it is not allowed to set dp_ctl[9] to ‘0’.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-82
Freescale Semiconductor
CLKSS is also entering the ccm_clk_ignition to notify which of the two sources (FPM or on-chip
oscillator) is chosen as PLL source.
If FPM is chosen, fpm_en signal is asserted to start FPM. Next, ccm_clk_ignition should wait until FPM
notifies by fpm_ready signal that its clock output is ready. In this stage CCM will assert the fpm_ready bit.
If the on-chip board is chosen, cosc_en signal will be asserted and cosc_pwrdown will remain deasserted
to start the on-chip oscillator. Next ccm_clk_ignition will count the default number of CKIL defined in
oscnt bits. Once the counter has elapsed, it is assumed that the clock output of on-chip oscillator is ready.
In this stage CCM will assert the cosc_ready bit.
In both of the above cases, no matter what clkss chooses, the external oscillator and CAMPs will be
enabled during ignition process: CAMP1_en=1, CAMP2_en=1 and ref_en_b=0 so that ckih_CAMP1 and
ckih2_CAMP2 clocks will be started. Next, ccm_clk_ignition will count the default number of CKIL
defined in oscnt bits. Once the counter has elapsed, it is assumed that the clock output of the CAMPs is
ready. In this stage CCM will assert the CAMP1_ready and CAMP2_ready bit.
In case clkss defines on using the on-chip oscillator, then both oscnt counts for on-chip oscillator and
external oscillator will be performed parallel, so that elapse of the count will notify that both oscillators
are ready. This is done to save time during ignition process. If FPM is chosen, then both procedures of
enabling FPM and counting oscnt value for the on-chip oscillator will start simultaneously.
Next, ccm_clk_ignition should assert ref_clk_en_dpllip so that reference clock to PLLs should be enabled.
Next, ccm_clk_ignition should assert dpll_en_dpllip so that dpllip_cpen will be generated by the DPLL-IP
to the corresponding DPLL.
Note: For this, initial value of UPEN should be asserted 1, that is init_dp_ctl_dpllip[5] for all PLLs should
be connected to 1.
Once the PLLs are locked, dpll_ip’s will generate pll_lrf_sticky signal to ccm_clk_ignition.
Upon assertion of all three pll_lrf_sticky signals, ccm_clk_ignition will generate src_clock_ready signal
for reset controller to indicate that PLL clocks are ready.
If pll_bypass_en is asserted, then src_clock_ready signal will be asserted as soon as exiting reset.
Upon arrival of src_clock_ready signal to reset controller, the reset sequence will continue. Please review
SRC spec for details on this sequence.
7.4.6.6
Reset Values for DPLL-IP
Reset values that are hard coded to dpll-ip initialization values are as follows:
• PLL1—initial value = 262.144 MHz
• PLL2—initial value = 262.144 MHz
• PLL3—initial value = 229.376 MHz
These frequencies correspond to the reference clock source of CKIL (32 kHz), which generates a DPLL
reference clock of 32.768 MHz (after multiplication of FPM by 1024).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-83
These frequencies will be lower if the on-chip oscillator (24 MHz) is chosen as the source of DPLL. In that
case the default frequencies generated are:
• PLL1—initial value = 208 MHz
• PLL2—initial value = 208 MHz
• PLL3—initial value = 182 MHz
7.4.6.7
CCM_CLK_ROOT_GEN
CCM_CLK_ROOT_GEN sub module generates the root clocks to be delivered to LPCG.
The following is a list of the root clocks generated by this module. The clocks are asynchronous unless
otherwise stated.
• ARM_CLK_ROOT —generated from pll1_sw_clk.
• EMI_SLOW_CLK_ROOT
• eNFC_CLK_ROOT—generated by division of EMI_SLOW_CLK_ROOT and balanced with it.
• VPU_RCLK_ROOT
• AHB_CLK_ROOT
• IPG_CLK_ROOT—generated by division of AHB_CLK_ROOT and balanced with it.
• PERCLK_ROOT—this clock is synchronized and balanced to AHB_CLK_ROOT. For the
synchronization process, perclk predivider and podf should generate clock 2.5 times lower than
ahb clock. In peripheral DVFS scenario, when ahb is reduced, perclk should be configured to be
lower 2.5 times the minimum value of ahb_clk (the DVFS value of ahb_clk).
• DDR_CLK_ROOT
• ARM_AXI_CLK_ROOT
• IPU_HSP_CLK_ROOT
• CKIL_SYNC_CLK_ROOT—CKIL clock synchronized to IPG_CLK_ROOT and balanced with
it, when not in STOP mode. Synchronizer is bypassed, when in STOP mode.
• USBOH3_CLK_ROOT
• ESDHC1_MSPRO1_CLK_ROOT
• ESDHC2_CLK_ROOT
• ESDHC3_CLK_ROOT
• UART_CLK_ROOT
• SSI1_CLK_ROOT
• SSI2_CLK_ROOT
• SSI_EXT1_CLK—connected to external BGA contact
• SSI_EXT2_CLK—connected to external BGA contact
• USB_PHY_CLK_ROOT
• TVE_216_54_CLK_ROOT
• DI_CLK_ROOT
• SPDIF0_CLK_ROOT
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-84
Freescale Semiconductor
•
•
•
•
•
SPDIF1_CLK_ROOT
CSPI_CLK_ROOT
WRCK_CLK_ROOT
LPSR_CLK_ROOT
PGC_CLK_ROOT—generated as division of ipg_clk and balanced to it.
7.4.6.7.1
Special Considerations for Configuring PERCLK
In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps
need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source.
To properly configure the PERCLK clock source, the following steps are required:
1. In the CCGR registers, gate the clocks to all PERCLK-dependent modules (see Table 7-41 for a
list of PERCLK-dependent modules).
2. Select the desired input clock for the PERCLK root clock (to be either source from the peripherals
main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel
bit.
3. Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer
to the CBCDR register for details.
4. In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks.
Table 7-41 lists the PERCLK-dependent module clocks and the associated CCGR register.
NOTE
When configuring the PERCLK clock source, these clocks must be gated,
however, other unused clock source may also be gated to minimize power
consumption.
Table 7-41. PERCLK-dependent Module Clock Sources
PERCLK-dependent Module Clocks
Associated CCGR Register
uart1_perclk
uart2_perclk
uart3_perclk
CCGR1
i2c1 clocks
i2c2 clocks
epit1_highfreq
epit2_highfreq
pwm1_highfreq
CCGR2
pwm2_highfreq
gpt_highfreq
owire clocks
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-85
Table 7-41. PERCLK-dependent Module Clock Sources (continued)
PERCLK-dependent Module Clocks
Associated CCGR Register
esdhc1_perclk
esdhc2_perclk
CCGR3
esdhc3_perclk
esdhc4_perclk
sim serial clock
ecspi1_perclk
CCGR4
ecspi2_perclk
The following figures describe clock generation described earlier in this section. The frequencies shown
in parentheses are the default typical frequencies. Glitchless muxes are indicated by muxes with thick line.
Figure 7-39 shows the ARMC_CLK_ROOT generation.
PLL 1
SWITCH
(800M)
1
3 bit divider
default=1
5
ARM_CLK_ROOT (800 MHz)
CACRR: ARM_podf
Figure 7-39. ARM_CLK_ROOT Generation
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-86
Freescale Semiconductor
1
lp_apm
2
0
4
3 bit divider
default=4
main_bus_clk
pll3_sw_clk
(216M)
3
periph_apm_clk
CBCMR:
periph_apm_sel
pll1_ sw_clk
(800M) 1
Periph
Switch
6
CBCDR: axi_a_podf
3 bit divider
default=5
axi_b (default 133Mhz)
7
CBCDR: axi_b_podf
1
2
pll2_sw_clk
(665M)
DVFS
0
axi_a (default 166Mhz)
EMI_SLOW_CLK_ROOT (default 133Mhz)
0
1
3 bit divider
default=5
8
ENFC_CLK_ROOT
CBCDR: emi_slow_podf
CBCDR:
periph_clk_sel
3 bit divider
default=5
CBCDR:
emi_clk_sel
CDCR:
periph_clk_
DVFS_podf
18
CBCDR: nfc_podf
3 bit divider
default=5
CBCDR: ahb_podf
9
AHB_CLK_ROOT (133Mhz)
2 bit divider
default=2
IPG_CLK_ROOT (66.5Mhz)
10
CBCDR: ipg_podf
CBCMR: perclk_lp_apm_sel
lp_apm
1
0
4
2 bit divider
default=2
1
3 bit divider
default=1
3 bit divider
default=6
Sync
0
11
PERCLK_ROOT
(54Mhz)
9
CBCDR: perclk_pred1
CBCDR: perclk_pred2 CBCDR: perclk_podf
CBCMR: perclk_ipg_sel
10
ckil
(32K)
CKIL_SYNC_CLK_ROOT (32Khz)
Sync
12
Figure 7-40. BUS clock generation
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-87
6
0
1
2
3
7
8
9
13
GPU2D_CLK_ROOT (166Mhz)
CBCMR: gpu2d_clk_sel
6
0
1
2
3
7
8
9
14
ARM_AXI_CLK_ROOT (166Mhz)
CBCMR:arm_axi_clk_sel
6
0
1
2
3
7
8
9
15
IPU_HSP_CLK_ROOT (133Mhz)
CBCMR: ipu_hsp_clk_sel
6
7
8
9
0
1
2
3
16 GPU_CLK_ROOT
(166Mhz)
CBCMR: gpu_clk_sel
6
7
8
9
0
1
2
3
17
VPU_AXI_CLK_ROOT (166Mhz)
CBCMR: vpu_axi_clk_sel
6
7
8
9
0
1
2
3
17a
DEBUG_APB_CLK_ROOT (166Mhz)
CBCMR: debug_apb_clk_sel
6
7
8
9
0
1
2
3
0
45
DDR_CLK_ROOT (166/200Mhz)
1
CBCMR: ddr_clk_sel
pll1_sw_clk (800M)
CBCDR: ddr_clk_podf
1
CBCDR:
ddr_high_freq_clk_sel
3 bit divider
default=4
Figure 7-41. AXI Clocks Generation
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-88
Freescale Semiconductor
PLL 1
SWITCH
(800M)
1
CSCDR1: usboh3_clk_pred
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
PLL 1
SWITCH
(800M)
1
PLL 2
SWITCH
(665M)
PLL 3
SWITCH
(216M)
PLL 1
SWITCH
(800M)
PLL 2
SWITCH
(665M)
PLL 3
SWITCH
(216M)
0
1
2
3
3 bit divider
default=4
CSCDR1: usboh3_clk_podf
2 bit divider
default=1
21 USBOH3_CLK_ROOT (54 MHz)
CSCMR1: usboh3_clk_sel
4
CSCDR1:
esdhc1_clk_pred
2
0
1
2
3
3 bit divider
default=4
CSCDR1:
esdhc1_clk_podf
3 bit divider
default=1
22 ESDHC1_CLK_ROOT (54 MHz)
0
CSCMR1:
esdhc1_clk_sel
3
23 ESDHC3_CLK_ROOT (54 MHz)
1
CSCMR1: esdhc3_clk_sel
4
0
CSCMR1:
esdhc2_clk_sel
1
2
0
1
2
3
24 ESDHC4_CLK_ROOT (54 MHz)
1
CSCMR1: esdhc4_clk_sel
3 bit divider
default=4
3 bit divider
default=1
CSCDR1:
esdhc2_clk_pred
25 ESDHC2_CLK_ROOT (54 MHz)
CSCDR1:
esdhc2_clk_podf
3
4
PLL 1
SWITCH
(800M)
1
CSCDR1: uart_clk_pred
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3
3 bit divider
default=4
CSCDR1: uart_clk_podf
3 bit divider
default=1
26
UART_CLK_ROOT
(54 MHz)
CSCMR1: uart_clk_sel
4
Figure 7-42. Serial Clock Generation (1 of 7)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-89
PLL 1
SWITCH
(800M)
1
CS1CDR: ssi1_clk_pred
PLL 1
SWITCH
(800M)
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3
3 bit divider
default=2
CS1CDR: ssi1_clk_podf
6 bit divider
default=2
CSCMR1: ssi1_clk_sel
27 SSI1_CLK_ROOT (54M)
0
1
42
28
SSI3_CLK_ROOT
(54 MHz)
1
CS2CDR: ssi2_clk_pred
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3
3 bit divider
default=2
CS2CDR: ssi2_clk_podf
6 bit divider
default=2
29
SSI2_CLK_ROOT (54 MHz)
CSCMR1: ssi2_clk_sel
42
PLL 1
SWITCH
(800M)
1
CS1CDR: ssi_ext1_clk_pred
PLL 2
SWITCH
(665M)
PLL 3
SWITCH
(216M)
PLL 1
SWITCH
(800M)
2
3
0
1
2
3
3 bit divider
default=3
SSI1_CLK_ROOT 27
CSCMR1: ssi_ext1_clk_sel
PLL 3
SWITCH
(216M)
CSCMR1: ssi_ext1_com
42
1
CS2CDR: ssi_ext2_clk_pred
PLL 2
SWITCH
(665M)
CS1CDR: ssi_ext1_clk_podf
SSI_EXT1_CLK
(10.2 MHz)
6 bit divider
0
30
default=7
1
2
3
0
1
2
3
3 bit divider
default=3
CS2CDR: ssi_ext2_clk_podf
6 bit divider
default=7
SSI_EXT2_CLK (10.2 MHz)
0
1
31
SSI2_CLK_ROOT 28
CSCMR1: ssi_ext2_clk_sel
CSCMR1: ssi_ext2_com
42
Figure 7-43. Serial Clock Generation (2 of 7)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-90
Freescale Semiconductor
0
PLL 3
SWITCH
(216M)
osc_clk
OSC
3 bit divider
default=3
3 bit divider
default=3
USB_PHY_CLK_ROOT(24M)
32
1
CSCMR1: usb_phy_clk_sel
CDCDR: usb_phy_pred
CDCDR: usb_phy_podf
3 bit divider
default=1
0
TVE_216_54_CLK_ROOT(216M)
74.25 MHz (297/4) for
33
720p case
0
1
1
CDCDR: tve_clk_pred
CSCMR1: tve_clk_sel
CSCMR1: tve_ext_clk_sel
CDCDR: di_clk_pred
ckih_CAMP1_clk
CSCMR2: di1_clk_sel
3 bit divider
default=8
0
DI1_CLK_ROOT
1
34
2
3
tve_di_clock from tve
4
ipp_di1_clk
CSCMR2: di0_clk_sel
0
DI0_CLK_ROOT
1
2
34a
3
4
ipp_di0_clk
CKIH
0
CAMP1
ckih_CAMP1_clk
1
CKIH2
CAMP2
35
CSCMR1: vpu_rclk_sel
CSCMR1: spdif_xtal_clk_sel
0 SPDIF_XTAL_CLK
43
1
VPU_RCLK_ROOT
0
4
1
SSI_LP_APM_CLK
42
2
2
ckih2_CAMP2_clk
CSCMR1: ssi_apm_clk_sel
Figure 7-44. Serial Clock Generation (3 of 7)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-91
PLL 1
SWITCH
(800M)
PLL 2
SWITCH
(665M)
PLL 3
SWITCH
(216M)
PLL 1
SWITCH
(800M)
1
CDCDR: spdif0_clk_pred
2
0
1
2
3
3 bit divider
default=3
6 bit divider
default=7
PLL 3
SWITCH
(216M)
SPDIF0_CLK_ROOT (10.3 MHz)
0
1
36
SSI1_CLK_ROOT 27
CSCMR2: spdif0_com
3
CSCMR2: spdif0_clk_sel
43
1
CDCDR: spdif1_clk_pred
PLL 2
SWITCH
(665M)
CDCDR: spdif0_clk_podf
2
3
0
1
2
3
3 bit divider
default=3
CDCDR: spdif1_clk_podf
6 bit divider
default=7
SPDIF1_CLK_ROOT (10.3 MHz)
0
1
37
SSI2_CLK_ROOT 28
CSCMR2: spdif1_clk_sel
CSCMR2: spdif1_com
43
Figure 7-45. Serial Clock Generation (4 of 7)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-92
Freescale Semiconductor
PLL 1
SWITCH
(800M)
1
CSCDR2: sim_clk_pred
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
PLL 1
SWITCH
(800M)
0
1
2
3
3 bit divider
default=2
6 bit divider
default=2
39 SIM_CLK_ROOT (54 MHz)
CSCMR2: sim_clk_sel
4
1
CSCDR3: firi_clk_pred
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
PLL 1
SWITCH
(800M)
CSCDR2: sim_clk_podf
0
1
2
3
3 bit divider
default=2
CSCDR3: firi_clk_podf
6 bit divider
default=2
40 FIRI_CLK_ROOT (54 MHz)
CSCMR2: firi_clk_sel
4
1
CSCDR3: hsi2c_clk_pred
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3
3 bit divider
default=2
CSCDR3: hsi2c_clk_podf
6 bit divider
default=2
41 HSI2C_CLK_ROOT (54 MHz)
CSCMR2: hsi2c_clk_sel
4
Figure 7-46. Serial Clock Generation (5 of 7)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-93
PLL 1
SWITCH
(800M)
1
CSCDR4: csi_mclk1_clk_pred CSCDR4: csi_mclk1_clk_podf
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3 bit divider
default=2
6 bit divider
default=2
47
CSI_MCLK1
CSCMR1: csi_mclk1_clk_sel
PLL 1
SWITCH
(800M)
1
CSCDR4: csi_mclk2_clk_pred CSCDR4: csi_mclk2_clk_podf
PLL 1
SWITCH
(800M)
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3 bit divider
default=2
6 bit divider
default=2
CSI_MCLK2
48
CSCMR1: csi_mclk2_clk_sel
1
CSCDR2: ecspi_clk_pred CSCDR2: ecspi_clk_podf
PLL 2
SWITCH
(665M)
2
PLL 3
SWITCH
(216M)
3
0
1
2
3
3 bit divider
default=2
6 bit divider
default=2
49 ECSPI_CLK_ROOT (54Mhz)
CSCMR1: ecspi_clk_sel
4
Figure 7-47. Serial Clock Generation (6 of 7)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-94
Freescale Semiconductor
sync
Memory_Repair_Mode
ahb_clk_root
div by 10
15
0
1
TCK
50 WRCK_CLK_ROOT
(13.3 MHz)
Bist_en_wrck
ipt_general_scan_mod
FPM_clk
divide by 2
0
1
2
3
51
LPSR_CLK_ROOT (0)
GND
CLPCR: lpsr_clk_sel
IPG_CLK_ROOT 16
1/2/4/8
52 PGC_CLK_ROOT (66.5 MHz)
CSCDR1: pgc_clk_podf
Figure 7-48. Serial Clock Generation (7 of 7)
NOTE
All 6-bit podf dividers in the previous figures are able to work on
frequencies lower than the clock speeds defined in the i.MX51 datasheet. It
is not allowed to insert the 6-bit divider a frequency higher than this
frequency.
The following predividers should use divider values larger than ‘1’. The
option ‘000’ is not allowed for them: usboh3_clk_pred, ssi1_clk_pred,
ssi2_clk_pred, ssi_ext1_clk_pred, ssi_ext2_clk_pred, cspi_clk_pred.
7.4.6.7.2
Initial Values Controlled by SJC
The initial values of the following dividers and muxes can be controlled by SJC. In regular functional
mode, the SJC will drive the reset values stated in the CCM register memory map. If SJC is progarmmed
to change those values, then the reset value for those dividers/muxes will be taken from the SJC
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-95
programability. Software can update the changed reset value after reset sequence. The control signals and
the dividers/muxes are listed below:
• init_perclk_pred1[1:0] to control reset value of perclk_pred1.
• init_perclk_pred2[2:0] to control reset value of perclk_pred2.
• init_perclk_podf[2:0] to control reset value of perclk_podf.
• init_ipg_podf[1:0] to control reset value of ipg_podf.
• init_ahb_podf[2:0] to control reset value of ahb_podf.
• init_axi_a_podf[2:0] to control reset value of axi_a_podf.
• init_axi_b_podf[2:0] to control reset value of axi_b_podf.
• init_emi_slow_podf[2:0] to control reset value of emi_slow_podf.
• init_nfc_podf[2:0] to control reset value of nfc_podf.
• init_periph_apm_sel[1:0] to control reset value of periph_apm_sel.
• init_periph_clk_sel to control reset value of periph_clk_sel.
• init_ssi_apm_clk_sel[1:0] to control reset value of ssi_apm_clk_sel.
7.4.6.7.3
Divider Change Handshake
Table 7-42 describes the dividers that may involve module handshake on every divider update. These
handshakes should be bypassed if the respective module is disabled.
Table 7-42. i.MX51 Divider Handshake Summary
Divider
Handshake with
module
Comment
emi_slow_podf
EMI
IPU
Handshake with IPU will exist if emi_slow_podf is chosen as source to ipu_hsp_clk.
Handshake with EMI will be through emi_DVFS_req_slow,
emi_DVFS_req_int1,emi_DVFS_req_int2, emi_DVFS_ack_slow,
emi_DVFS_ack_int1, emi_DVFS_ack_int2.
If emi_slow_podf is chosen as source of gpu_clk, that is, the change of
emi_slow_podf will affect gpu_clk then the handshake of emi_DVFS_req_garb,
emi_DVFS_ack_garb should also commence.
If this divider is chosen as source of ddr_clk,then the handshake of
emi_DVFS_req_fast, emi_DVFS_ack_fast should also commence.
nfc_podf
EMI
Handshake with EMI will be through emi_DVFS_req_slow, emi_DVFS_ack_slow.
axi_a_podf
EMI
IPU
Handshake with EMI will exist only if axi_a_podf is chosen as source to ddr_clk. In
this case handshake with EMI will be through emi_DVFS_req_fast,
emi_DVFS_ack_fast.
If axi_a_podf is chosen as source of gpu_clk, that is, the change of axi_a_podf will
affect gpu_clk then the handshake of emi_DVFS_req_garb, emi_DVFS_ack_garb
should also commence.Handshake with IPU will exist only if axi_a_podf is chosen as
source to ipu_hsp_clk.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-96
Freescale Semiconductor
Table 7-42. i.MX51 Divider Handshake Summary (continued)
Divider
Handshake with
module
Comment
axi_b_podf
EMI
IPU
Handshake with EMI will exist only if axi_b_podf is chosen as source to ddr_clk. In
this case handshake with EMI will be through emi_DVFS_req_fast,
emi_DVFS_ack_fast.
If axi_b_podf is chosen as source of gpu_clk, that is, the change of axi_b_podf will
affect gpu_clk then the handshake of emi_DVFS_req_garb, emi_DVFS_ack_garb
should also commence. Handshake with IPU will exist if axi_b_podf is chosen as
source to ipu_hsp_clk.
ahb_podf
EMI
IPU
Handshake with EMI will exist only if ahb_podf is chosen as source to ddr_clk. In this
case handshake with EMI will be through emi_DVFS_req_fast, emi_DVFS_ack_fast.
If ahb_podf is chosen as source of emi_slow_clk generation, then similar handshake
to the emi_slow_podf should take place.
If ahb_podf is chosen as source of gpu_clk, that is, the change of ahb_podf will affect
gpu_clk then the handshake of emi_DVFS_req_garb, emi_DVFS_ack_garb should
also commence.
Handshake with IPU will exist only if ahb_podf is chosen as source to ipu_hsp_clk.
ddr_clk_podf
EMI
Handshake is needed only if EMI’s DDR (fast) clock is derived from this divider.
ddr_high_freq_clk_
sel
EMI
Handshake of emi_DVFS_req_fast, emi_DVFS_ack_fast is needed.
Any update of CBCDR might involve handshake with modules based on the above table.
Once the CBCDR register is updated, CCM will check which of the above dividers was updated. For the
updated dividers, CCM will check if a handshake with the respective modules is needed. If the handshake
is needed, CCM will request acknowledge from the respective module for frequency change. Once the
acknowledge arrives, CCM will perform the actual frequency change, and will notify the module that the
frequency has changed by de asserting the request. IPU handshake also involves signal to notify it on the
frequency change. This signal (periph_DVFS_sw_ack) is held for two clock cycles of ipg_clk on each
change.
The handshake with the respective module will not be performed in case that the respective handshake is
masked through CCDR[bits18–16]. In this case the write to the respective divider will commence
immediately after the CBCDR register is updated.
Software has to make sure that the respective module is on and has the ability to acknowledge a request
from the CCM. If the respective module is disabled or its clocks are gated off, then it will not have ability
to support the handshake process and software should mask its handshake capability (through
CCDR[bits18–16]).
Interrupts can be generated for each of the above dividers change. Please refer to CISR register for details
on those interrupts.
In addition, CCM has divider handshake in process register (CDHIPR). This register has status bits for
each of the above dividers that are involved in the handshake process. When the respective bit is asserted,
it means that the respective dividers is being updated, and software should not attempt to write to this
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-97
divider until the respective bit is deasserted. Any reads of the respective divider during the time that the
CDHIPR respective bit is asserted, will read the next value to be loaded to the divider, and not the actual
dividers value. To make sure that software reads the actual dividers value, it should wait until the CDHIPR
bits are desasserted.
All selections of muxes that are not glitchless should be updated only when there are no modules using
their clocks, or the modules which use those clocks are disabled and their clocks are gated off.
Changing the periph_clk_sel bits in CBCDR will involve handshake with EMI and IPU - a similar
handshake to the one that is performed in load dividers for EMI and IPU dividers. Those handshakes will
be masked if configured to be masked in CCDR register”.
Changing the ddr_high_freq_clk_sel bits in CBCDR will involve handshake with EMI - a similar
handshake to the one that is performed in load dividers for EMI ddr. This handshake will be masked if
configured to be masked in CCDR register.
Changing the emi_clk_sel bits in CBCDR will involve handshake with EMI and IPU - a similar handshake
to the one that is performed in load dividers for EMI and IPU dividers. The IPU handshake will be
performed only if IPU_HSP clock uses the emi_core_clk_root.
NOTE
In case DVFS is enabled (through GPC), it is not allowed to do any
frequency changes, that is, the frequency of the system should be set prior
to DVFS enable, and once the DVFS scenario is enabled, no divider of the
above handshake group dividers should be changed “manually” by software
since this might corrupt the handshake process.
7.4.6.7.4
CKIL Synchronizing to ipg_clk
CKIL is synchronized to ipg_clk when system is in functional mode. When system is in STOP mode, that
is, when there is no ipg_clk, the CKIL synchronizer will be bypassed, and raw CKIL will be supplied to
the system.
functional clock X
0
root clock X
TCK_*
1
chopper clock enable X
Figure 7-49. Chopper Control on Root Clocks
7.4.6.8
PLL Disabling/Enabling
PLL disabling and enabling is done via DPLL-IP module. Software should first move all the clocks
generated from a specific PLL to another PLL, before disabling the PLL through DPLL-IP. This move of
clocks can be done via glitch less mux for clocks which are critical to the system, that is, bus clocks. For
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-98
Freescale Semiconductor
serial clocks, software should first disable the module and the clock generated to it, then move the mux
controlling the source of the clocks to another PLL, and start back the module and its clocks. Only then it
is safe to disable the PLL. The mux for the serial clocks is not glitch less hence the above procedure should
be followed.
7.4.6.9
Observability Output signals
CCM has three muxes that generate critical signals to the IO PADS for observability. The three MUX
outputs are connected to the three CCM outputs named obs_output_0, obs_output_1, obs_output_2. The
three muxes are controlled via CTOR register of CCM.
It is possible to generate also the obs_input_0, obs_input_1, obs_input_2, obs_input_3, obs_input_4 and
obs_input_5 to the external pads through the muxes controlled by CTOR. This allows to observe the
signals connected to those 6 CCM input pins. Below list describes the signals connected for observability
to those input pins:
• obs_input_0 connect to DPLLIP1 : dpllip_cpen
• obs_input_1 connect to DPLLIP1 : dpllip_cpres
• obs_input_2 connect to DPLLIP1 : dpllip_crstrt
• obs_input_3 connect to DPLLIP1 : dpllip_load_req
• obs_input_4 connect to DPLLIP2 : dpllip_cpen
• obs_input_5 connect to DPLLIP3 : dpllip_cpen
7.4.6.10
Low-Power Clock Gating (LPCG) Module
The LPCG module receives the root clocks and splits them to clock branches for each module. The clock
branches are gated clocks. The enables for those gates can come from the following five sources:
• Clock enable signal from CCM—This signal is generated by configuration of the cgr bits in CCM.
It is based on the low power mode.
• Clock enable signal from the module—This signal is generated by the module based on internal
logic of the module. For clock enable signals from the module, that are used, CCM will generate
override signal based on programable bit in CCM (CMEOR).
• Clock enable signal from Reset controller (SRC)—This signal will enable the clock during the
reset procedure. Please refer to SRC chapter for details on the clock enable signal during reset
procedure.
• Hard coded enable from fuse box.
• Enable or disable clock in BIST mode, based on bist_en signal. This will be applicable for clocks
that are not functional and needed only on memory repair or bist sequence (like sms_clk’s and
wrck).
The possible enable signals listed above are ANDed to generate the enable signal for the gating cell.
The enable signal for the gating cell is synchronized with the clock it needs to gate. This is done in order
to prevent glitches on the gated clock.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-99
Notifications are generated for the CCM, to indicate when to close and to open the clock roots. All
notifications that correspond to the same clock root will be ORed to generate one notification signal to ccm
for clock root gating.
Figure 7-50 describes the implementation for each gating cell:
Other notifications corresponding to the same clock root
Enable clock root
Module clock enable
Sample FF
Override module enable
CGR control enable
Sample
FF
Reset control enable
Module
Gating cell
Gated clock
bist_en
Fuse disable
Clock root
Split clock root
TE
ipt_se_gatedclk
Figure 7-50. Gating Cell Implementation
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-100
Freescale Semiconductor
Figure 7-51 describes the clock split inside LPCG module. It describes the case of two modules, one
module without enable signal and one with enable signal. (SRC enable signals and sync FFs are omitted
from this figure).
LPCG
CCM
enable module 1 clock
CGR
Module 1
Gated clock for module 1
Module1
clock_root
Module 2
CGR
enable module 2 clock
Gated clock for module 2
Module2
clock enable from module2
ov_clk_en
Module2
Figure 7-51. Clock Split in LPCG
7.4.7
DVFS Support
Frequency shift during DVFS procedure in the i.MX51 can be done on the following two domains:
• ARM clock domain frequency shift.
• Peripherals clock domain frequency shift (including buses).
The initiator of the frequency shift procedure is the GPC (Global Power Controller) module. It will initiate
only one frequency shift at a time. There is no option to commence both of the above frequency shifts
simultaneously. GPC will be aided by sdma and ccm to execute the frequency shift.
The next paragraphs explain the details of the above two frequency shift options.
7.4.7.1
ARM Clock Domain Frequency Shift
SDMA can request ARM frequency shift by using ARM clock divider or by relock of PLL1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-101
The following steps will be configured by SDMA, (this can also be performed by ARM, but to be able to
reduce load of ARM processing, it is preferable to perform it by SDMA):
1. SDMA can request ARM frequency shift by dividers, or by PLL1 relock. This request is written to
CCM’s arm_freq_shift_divider bit:
— arm_freq_shift_divider = 0: PLL1 relock shift is requested.
— arm_freq_shift_divider = 1: ARM_PODF divider shift is requested. In this case any new writes
to ARM_PODF will be held until arm_clk_switch_req signal is asserted by GPC. This signal
indicates that voltage is stable. The CCM holds a status bit to notify that the arm_podf divider
is being in process of writing, and software should wait until the write finishes before writing
any new value to arm_podf. Refer to CDHIPR register for details on the status bit. CCM can
also generate interrupt once the actual arm_podf has been taken into effect in DVFS scenario.
Please refer to CISR register for details.
2. Configure new ARM domain dividers (if arm_freq_shift_divider = 1: ARM_PODF divider shift is
requested)
SDMA continues with the next steps only if (arm_freq_shift_divider = 0: PLL1 relock shift is requested).
3. Check which frequency mode is active in DPLLIP1, HFS or LFS: DPLLIP bit HFSM of DP_CTL
register.
4. Configure the non active frequency mode (HFS or LFS) of DPLLIP1, with the new frequency
needed for PLL1 to relock on: DPLLIP1 registers DP_OP, DP_MFD, DP_MFN, DP_HFS_OP,
DP_HFS_MFD, DP_HFS_MFN.
5. Configure the step frequency divider: CCM CCSR register, bit pll2_div_podf or pll3_div_podf bits
(depending on the decision in the step mux in step 6).
6. Configure the step frequency mux: CCM bit step_sel of CCM_CNT register.
Once those configurations are done, SDMA notifies GPC to continue with the frequency shift procedure.
The actual shift starts by assertion of arm_clk_switch_req signal from GPC to CCM.
CCM commences the following steps upon assertion of arm_clk_switch_req signal: These are hardware
steps and do not require software involvement.
• If arm_freq_shift_divider = 1 dividers shift is requested):
a) Load the ARM domain new dividers.
b) After actual reloading of the dividers (all counters in 0), assert clk_switch_ack for 2 ipg cycles.
This is done so GPC will have indication that frequency has been updated.
• If arm_freq_shift_divider = 0 (PLL1 relock shift is requested):
a) Switch to the step frequency by a glitch less mux.
b) After the glitchless mux has changed to the step frequency, invert pll_lvs signal to DPLLIP1
so that PLL1 will lock on the new frequency.
c) On pll_lrf_sticky1 assertion move back to PLL1 that is locked on the new reloaded frequency
by the glitch less mux.
d) After actual shift of the mux assert clk_switch_ack for 2 ipg cycle. This is done so GPC will
have indication that frequency has been updated.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-102
Freescale Semiconductor
Upon clk_switch_ack assertion, GPC deasserts arm_clk_switch_req signals.
At this point, ARM has changed frequency and system is ready for a new frequency switch procedure.
See Figure 7-52 for an illustration.
SDMA
ccm_clk_switch_ack
arm_clk_switch_req
GPC
Register configuration
PLL_LVS
CCM
PLL_LRF_STICKY1
arm_freq_shift_dividers bit
DPLLIP1
LFS set
HFS set
arm_podf bit
CCM CCSR (step ferquency)
step_sel bit
Figure 7-52. ARM DVFS Connectivity
7.4.7.2
Peripheral Clock Domain Frequency Shift
CCM includes capability to divide by 2/3/4 the root of bus clocks (ahb, axi, ipg, int_mem, ddr_clk,
nfc_clk). The actual division factor is defined by bits in the ccm memory map, register CDCR [1–0]. The
software is expected to set those bits prior to enabling DVFS operation. The value written to the DVFS
register divider (CDCR[0–1]) will not be loaded immediately to the actual divider, but will wait until
peripheral DVFS procedure will commence.
During DVFS scenario, the root clocks which are not affected by DVFS divider should be generated from
a low frequency PLL. This frequency should not be higher than 240Mhz since the operating voltage is
lowered in DVFS mode. Software can use the PLL3 with frequency 216Mhz for this operation. The setting
for the serial clocks is done through CSCMR1 register.
The modules that their clock is about to change (IPU,EMI, and so on.) may need to be configured with
values that determine the frequency of the new clock prior to the clock switch operation. Please refer to
the respective module’s specification for clarification on the needed configuration.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-103
Divide by 2/3/4 procedure (lowering frequency):
Upon assertion of periph_clk_div_req signal from GPC to CCM, the actual division procedure will take
place. The periph_clk_div_req signal from GPC will remain asserted as long GPC requests a division of
the peripheral clocks. This signal will be deasserted only when GPC requests to multiply the frequency
and go back to the division by ‘1’.
Note: the DVFS operation can start also by software control using the sw_periph_clk_div_req. In that case
the GPC control will be ignored and the ccm_clk_switch_ack will not be asserted.
There is no need to synchronize the three dividers change since they work on async clock domains.
Prior to the actual division there is need for acknowledge from peripherals that are sensitive to the
frequency change. The modules sensitive to the frequency change are IPU and EMI. Those handshakes are
described below:
• IPU handshake
a) CCM asserts IPU_freq_change_req to request approval from IPU to commence the frequency
shift.
b) IPU asserts IPU_freq_change_ack to notify the time window that its ok from IPU point of view
to change the frequency.
Note that IPU does not support DVFS operation of division by 3.
• EMI handshake
a) CCM asserts EMI_freq_change_req to request approval from EMI to commence the frequency
shift.
b) EMI asserts EMI_freq_change_ack to notify the time window that its ok from EMI point of
view to change the frequency.
NOTE
Handshakes that are bypassed are not performed.
c) CCM commences the actual division once all of the acknowledges (IPU_freq_change_ack,
EMI_freq_change_ack) are asserted.
d) After completing the division, CCM will notify the GPC by assertion of ccm_clk_switch_ack
for 2 ipg cycles (rising on ipg_clk) and notify IPU by assertion of ipu_clk_changed for at least
2 hsp clock cycles (rising on the edge of the new hsp clock). CCM will also negate the
IPU_freq_change_req and EMI_freq_change_req.
Multiply by 2/3/4 procedure (raising frequency): Upon negation of periph_clk_div_req signal from GPC
to CCM, the actual multiplication procedure will take place by removing the division by 2/3/4 and
returning to division by ‘1’.
Note: the DVFS operation can be stopped also by software control using the sw_periph_clk_div_req. In
that case the GPC control will be ignored and the ccm_clk_switch_ack will not be asserted.
There is no need to synchronize the 3 dividers change since they work on async clock domains.
Prior to the actual frequency change there is need for acknowledge from peripherals that are sensitive to
the frequency change. Those handshakes are described below:
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-104
Freescale Semiconductor
•
•
IPU Handshake
a) CCM asserts IPU_freq_change_req.
b) IPU asserts IPU_freq_change_ack to notify the time window if it is acceptable from the
viewpoint of the IPU to change the frequency.
EMI handshake
a) CCM asserts EMI_freq_change_req.
b) EMI asserts EMI_freq_change_ack to notify the time window that its ok from EMI point of
view to change the frequency.
CCM performs the actual multiplication once both of the acknowledges are asserted.
After completing the frequency change, CCM notifies GPC by assertion of ccm_clk_switch_ack for 2 ipg
cycles and notifies IPU by assertion of ipu_clk_changed for at least 2 hsp clock cycles. CCM also negates
the IPU_freq_change_req and EMI_freq_change_req.
The following figure describes the connectivity.
ccm_clk_switch_ack
Periph_clk_div_req
GPC
IPU_FREQ_CHANGE_REQ
IPU
CCM
IPU_FREQ_CHANGE_ACK
IPU_CLK_CHANGED
EMI_FREQ_CHANGE_REQ
EMI
EMI_FREQ_CHANGE_ACK
Figure 7-53. Peripheral DVFS Connectivity
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-105
Figure 7-54. Peripheral DVFS Signals
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-106
Freescale Semiconductor
IPU_clk_changed
ccm_clk_switch_ack
EMI_freq_change_ack
EMI_freq_chnage_req
IPU_freq_change_ack
IPU_freq_chnage_req
Periph_clk_div_req
Clk
raise on hsp_clk for at least 2 hsp_clk
raise on ipg_clk for 2 ipg_clk
7.4.7.3
Peripherals Restrictions in DVFS Scenario
On DVFS scenario for peripherals, IPG and AHB clocks are divided from their nominal frequency. The
serial dividers in the low voltage case, should use a low frequency PLL input (below 300 Mhz) to work
correctly.
Table 7-43 describes restrictions that need to be followed to support the DVFS frequency shift:
Table 7-43. DVFS Restrictions
Module
Support
Restriction
UART
R1
Need to configure uart rate to be lowest ipg clock frequency/16.
Hence rates of 1.875M and 4M cannot be reached in DVFS scenario.
ESDHC
R
Need to configure card rate to be low_frequency_ahb_clk/2.
Hence rate of 52 Mhz for SD card cannot be reached in the DVFS scenario.
MSHC
R
Need to configure card rate to be low_ipg_clk.
Hence rated of 40M for card cannot be reach in DVFS scenario.
SSI
R
Master clock should be generated from ssi_ext1 and ssi_ext2 pads.
CSPI
R
Need to configure spi rate to be low ipg clk.
DDR memory
R
To be able to reach 200 Mhz on DDR, the clock can be generated from PLL1 that also
supplies clock to ARM. In that case, PLL1 will have to be programmed to a multiplication
of 200Mhz (200, 400, 600, 800) and the ARM DVFS should be enabled from divider
change only and not from PLL change. If 166 Mhz is accepted for DDR memory, then the
DDR clock should be generated from PLL2 (665 Mhz), and in that case ARM DVFS may
be enabled.
USB, USB_PHY
N2
Needs ipg_clk>60 Mhz. Hence will not work under DVFS scenario
FEC
N
Needs ipg_clk>50 Mhz. Hence will not work under DVFS scenario
TVE
N
Is not synthesized for frequency operation
SPDIF
N
Is not synthesized for frequency operation y
P-ATA
N
Needs ipg_clk to be fixed. In case ARM core manages DVFS scenario, it can work only in
times ipg_clk is fixed, that is, before and after DVFS scenario.
1
2
R= modules that will work with restriction
N = modules that will not work and need to be gated off if DVFS is used”
7.4.8
Power Modes
The i.MX51 supports four low-power modes: RUN mode, WAIT mode, STOP mode, LPSR (low power
screen refresh) mode.
7.4.8.1
Run Mode
This is the normal/functional operating mode. In this mode ARM runs in its normal operational mode. The
frequency and voltage can be changed upon DVFS scenario as described in Section 7.4.7, DVFS Support.”
Clocks to the modules can be gated by configuring the corresponding cgr bits.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-107
7.4.8.2
Wait Mode
In this mode the ARM clock is gated. All other clocks are functional and can be gated by programing their
CGR bits. Power gating can be done on ARM platform.
7.4.8.2.1
Wait Mode Procedure
The wait mode procedure is as follows:
1. ARM writes to the LPM bit to set it for WAIT mode.
2. ARM writes to DSM_INT_HOLDOFF bit in TZIC.
3. DSM_INT_HOLDOFF assertion forces the interrupt controller to stop the synchronizer clock for
incoming interrupts. Any interrupts that had previously been synchronized by the interrupt
controller will remain asserted.
4. If a wakeup event occurred or an interrupt was serviced or is pending, the CPU may abort the DSM
sequence by exiting the main shutdown code sequence and returning to the desired security mode.
5. If not, the software should execute the Wait For Interrupt (WFI) instruction.
6. Upon execution, the WFI instruction causes the ARM to drain its write buffers and enter a
quiescent state. At this point the ARM asserts the STANDBYWFI signal.
7. The ARM platform then waits until the L2 cache controller has become inactive. Once the L2 is
inactive and the CPU’s STANDBYWFI output is asserted, the ARM platform asserts the
ARM_DSM_REQUEST signal to the CCM.
8. The CCM continuously synchronizes both the ARM_DSM_REQUEST and
TZIC_DSM_WAKEUP inputs into the clock domain used by its internal state machine.
9. If TZIC_DSM_WAKEUP is negated and ARM_DSM_REQUEST is asserted, the CCM begins the
WAIT shutdown sequence:
10. CCM stops the ARM clock. (soc_mxclk input to ARM will be gated only if the respective CGR
defines to gate it in WAIT mode).
11. Stop of ARM clock takes place only if CLPCR[5]=1 and debug_arm_clk_off_on_lpm=0
(connected to sjc register sjc_gpucr3_reg bit 15). If either CLPCR[5]=0 or
debug_arm_clk_off_on_lpm=1 then ARM clocks will not be gated off and CCM will continue to
next step.
12. CCM generates ccm_ipg_wait to indicate that it started WAIT entrance procedure.
13. CCM requests an acknowledge to close clocks of SAHARA,RTIC, IPU, SDMA, SCC, EMI and
AHBMAX if their cgr bits indicate to close their clocks on WAIT mode and if their clocks was not
already closed in run mode. The request is issued if the handshake is not bypassed by programing
the CLPCR register bits 23–16. If the corresponding bits are set, the request signal is not issued to
the corresponding module and CCM does not wait for its acknowledge in the process of entering
low power mode. The requests commence via the following signals:
— SAHARA: sahara_ipg_stop_req
— RTIC: rtic_ipg_stop_req
— IPU: ipu_stop_clk_at_wait_req
— SDMA: sdma_ipg_stop_req
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-108
Freescale Semiconductor
— SCC: scc_ipg_stop_req
— EMI: emi_lpmd, emi_lpmd_fast, emi_lpmd_int1, emi_lpmd_slow, emi_lpmd_garb - these
requests will be asserted based on the definition of CCGRs. CCM will perform the appropriate
EMI handshake based on the programing of the corresponding CCGR bits.
NOTE
Since EMI needs the aclk_fast (ddr clock) to be running for it to answer with
emi_lpmd, then software should make sure to turn on the aclk_fast (ddr_clk)
before entering any low power mode that requests the emi_lpmd.
— AHBMAX: ahbmax_halt_req
14. Once the above modules finished their operation and are ready to enter low power mode, they
acknowledge CCM that its safe to turn of their clocks. The acknowledge signals are as follows:
— SAHARA: sahara_ipg_stop_ack
— RTIC: rtic_ipg_stop_ack
— IPU: ipu_stop_clk_ack
— SDMA: sdma_ipg_stop_ack
— SCC: scc_ipg_stop_ack
— EMI: emi_lpack, emi_lpack_fast, emi_lpack_int1, emi_lpack_slow, emi_lpack_garb
— AHBMAX: ahbmax_halt_ack
NOTE
The SCC clocks are closed in WAIT mode only if SAHARA clocks are also
closed, hence the SCC handshake is performed only if the SAHARA clocks
are programmed to be closed as well.
15. The requests are generated by CCM in stages. CCM continues from stage to stage once all the
acknowledgements of a present stages were received. The stages are the following:
— Stage 1: SAHARA, RTIC, IPU, SDMA
— Stage 2: SCC
— Stage 3: AHBMAX
— Stage 4: EMI
16. Once CCM receives all the acknowledge signals needed, and if at least 8 ipg_clk cycles have
elapsed since the assertion of ccm_ipg_wait signal, it enters WAIT mode and does the following:.
a) Closes the clocks to the modules which were defined to be shut at WAIT mode in the CCGR
bits.
b) Asserts system_in_wait_mode signal. This signal is connected to the IO pads for observability,
to indicate of a WAIT mode.
Once CCM is in WAIT mode, it checks whether TZIC_DSM_WAKEUP signal has asserted or
ARM_DSM_REQUEST has negated during the process of entering WAIT mode. If it has occurred, then
CCM exits WAIT mode.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-109
If TZIC_DSM_WAKEUP is not asserted and ARM_DSM_REQUEST is still asserted, the CCM moves to
state SRPG_ARM and generates a request to GPC to power down the ARM platform, IPU, VPU,GPU,
GPU2D and EMI by asserting signals ccm_pdn_4arm_req and ccm_pdn_4all_req. If in GPC those
modules are defined to be powered down on WAIT mode, then GPC commences powering down for them.
Please refer to CCM-GPC Connectivity diagram. The GPC sends a pdn_ack at the end of the power down
sequence.
CCM’s low power state machine remains in state “SRPG_ARM” until WAIT mode is exited.
Note that during WAIT mode, if SCC asserts either hclk_en signal or ipg_clk_en signal, the CCM asserts
scc_clk_enable, thus enabling the SCC clocks. The WAIT mode is not exited due to this assertion.
7.4.8.2.2
Wait Mode is Exited by the Following Procedure
As soon as the synchronized TZIC_DSM_WAKEUP signal is seen as asserted or the
ARM_DSM_REQUEST is negated, the CCM begins the process of exiting WAIT mode.
• Enable VPU, GPU2D and GPU clocks only.
a) CCM requests that GPC restores power. CCM asserts ccm_pup_req to request that GPC powers
up all the modules that were powered down if it was powered down on the entrance to WAIT
mode.
b) GPC notifies CCM by asserting signal PUP_ACK that power of ARM, VPU, IPU, and EMI is
back on, and it’s safe to exit from WAIT mode. Only then does CCM do the following:
– Once assertion of notification from src that the resets for the power gated modules has been
finished, (src_power_gating_reset_done is set) negate the low power request signals to all
modules and enable all modules clocks including ARM clocks and return to run mode. (the
clocks that their CCGR bits define not to be open in RUN mode will not be opened, and will
continued to be gated in RUN mode).
– Once system is in run mode, CCM will negate ccm_ipg_wait and system_in_wait_mode.
c) Once the interrupt propagates through all the synchronization logic, the ARM CPU recognizes
and services it. This forces the negation of the ARM_DSM_REQUEST output.
Prior to this point, ARM_DSM_REQUEST and TZIC_DSM_WAKEUP were simultaneously
asserted. Since TZIC_DSM_WAKEUP has top priority, the system is able to wake up.
d) Before the ARM exits the ISR, it clears the interrupt source. This causes the
TZIC_DSM_WAKEUP signal to be negated. At this point, the two low power control signals
(TZIC_DSM_WAKEUP and ARM_DSM_REQUEST) are negated, and the WAIT sequence
can be repeated at any time.
7.4.8.3
Stop Mode
In this mode all system clocks are stopped. PLLs are stopped. Power gating can be done on ARM platform,
IPU, VPU and EMI. Synchronization of the CKIL clock is bypassed.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-110
Freescale Semiconductor
7.4.8.3.1
Entering Stop Mode
Stop Mode is entered by the following procedure:
1. ARM writes to LPM bit to set it for STOP mode.
2. ARM writes to DSM_INT_HOLDOFF bit in TZIC.
3. DSM_INT_HOLDOFF assertion forces the interrupt controller to stop the synchronizer clock for
incoming interrupts. Any interrupts that had previously been synchronized by the interrupt
controller will remain asserted.
4. If a wakeup event occurred or an interrupt was serviced or is pending, the CPU may abort the DSM
sequence by exiting the main shutdown code sequence and returning to the desired security mode.
If not the software, should execute the Wait For Interrupt (WFI) instruction.
5. Upon execution, the WFI instruction causes the ARM to drain its write buffers and enter a
quiescent state. At this point the ARM asserts the STANDBYWFI signal.
6. The ARM platform waits until the L2 cache controller has become inactive. Once the L2 is inactive
and the CPU’s STANDBYWFI output is asserted, the ARM platform asserts the
ARM_DSM_REQUEST signal to the CCM.
7. The CCM continuously synchronizes both the ARM_DSM_REQUEST and
TZIC_DSM_WAKEUP inputs into the clock domain used by its internal state machine.
The only time when those signals are not synchronized is when PLLs are closed. In this case exiting
from STOP mode is done asynchronously (please refer to Section 7.4.8.3.2, Exiting Stop Mode”).
If TZIC_DSM_WAKEUP is negated and ARM_DSM_REQUEST is asserted, the CCM begins the
following STOP shutdown sequence:
1. CCM stops the ARM clock.
2. CCM generates ccm_ipg_stop and ccm_int_mem_ipg_stop to indicate that it started stop entrance
procedure.
3. CCM requests an acknowledge to close clocks of SAHARA, RTIC, IPU, SDMA, SCC, EMI and
AHBMAX if their clocks was not already closed in run mode. The request will be issued if the
handshake is not bypassed by programing the CLPCR register bits 23–16. If the corresponding bits
are set, then the request signal will not be issued to the corresponding module and CCM will not
wait for its acknowledge in the process of entering low power mode. The requests will commence
via the following signals:
— SAHARA: sahara_ipg_stop_req
— RTIC: rtic_ipg_stop_req
— IPU: ipu_stop_clk_at_stop_req
— SDMA: sdma_ipg_stop_req
— SCC: scc_ipg_stop_req
— EMI: emi_lpmd, emi_lpmd_fast, emi_lpmd_int1, emi_lpmd_slow, emi_lpmd_garb
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-111
NOTE
Since EMI needs the aclk_fast (ddr clock) to be running for it to answer with
emi_lpmd, then software should make sure to turn on the aclk_fast (ddr_clk)
before entering any low power mode that requests the emi_lpmd.
— AHBMAX: ahbmax_halt_req
Once the above modules finished their operation and are ready to enter low power mode, they
acknowledge CCM that its safe to turn of their clocks. The acknowledge signals are as follows:
• SAHARA: sahara_ipg_stop_ack
• RTIC: rtic_ipg_stop_ack
• IPU: ipu_stop_clk_ack
• SDMA: sdma_ipg_stop_ack
• SCC: scc_ipg_stop_ack
• EMI: emi_lpack, emi_lpack_fast, emi_lpack_int1, emi_lpack_slow, emi_lpack_garb
• AHBMAX: ahbmax_halt_ack
The requests will be generated by CCM in stages. CCM will continue from stage to stage once all the
acknowledges of a present stages were received. The stages are the following:
• Stage 1: SAHARA, RTIC, IPU, and SDMA
• Stage 2: SCC
• Stage 3: AHBMAX
• Stage 4: EMI
Once CCM receives all the acknowledge signals needed, and if at least 8 ipg_clk cycles has elapsed since
the assertion of ccm_ipg_stop signal, then it will enter STOP mode and do the following tasks in the order
they are written below:
1. * Close the system modules clocks, not including pgc_clk. The closing of clocks will include the
ckil_sync clocks of Megamix only if the indication from GPC is that Megamix is about to be
powered down (by spare_input_10 indication). The gating signal output for the CKIL sync gating
cells is spare_output_0).
2. Assert system_in_stop_mode signal. This signal is connected to the IO pads for observability, to
indicate of a STOP mode.
Once CCM is in STOP mode, it will check if TZIC_DSM_WAKEUP signal has asserted or if
ARM_DSM_REQUEST has negated during the process of entering STOP mode. If it has occurred, then
CCM will exit STOP mode.
If TZIC_DSM_WAKEUP is not asserted and ARM_DSM_REQUEST is asserted, then CCM will move
to state STOP_GPC and generate a request to GPC to power down the ARM platform, IPU, VPU, GPU,
GPU2D and EMI by asserting signals ccm_pdn_4arm_req and ccm_pdn_4all_req. If in GPC those
modules are defined to be powered down on STOP mode then GPC will commence powering down for
them.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-112
Freescale Semiconductor
After the GPC sends the pdn_ack signal, the following occurs:
1. Close PLLs and DPLL_ips by deasserting dpll_en_dpllip and ref_clk_en_dpllip.
2. After deassertion of lock ready flag from the PLL’s, close CAMPs and FPM by deasserting
ccm_CAMP1_en, ccm_CAMP2_en and ccm_fpm_en.
3. If sbyos bit was set, then de assert ref_en_b signal to close external oscillator and assert
cosc_pwrdown to put on-chip oscillator in power down mode. (if they were not already closed by
software. If one of them was already closed by software then discard the sbyos operation for it and
perform the sbyos operation only on the one that is working. If both of them were closed in run
mode, then discard sbyos operation for both of them).
If vstby bit was set, then assert pmic_vstby_req signal, to indicate power management IC to shift
voltage to standby voltage.
CCM’s low power state machine will remain in state STOP_GPC until STOP mode will be exited.
CCM
GPC
ccm_pdn_4arm_req
ccm_pdn_4all_req
gpc_pdn_ack
ccm_pup_req
gpc_pup_ack
Figure 7-55. CCM-GPC Connectivity
7.4.8.3.2
Exiting Stop Mode
As soon as the unsynchronized TZIC_DSM_WAKEUP signal is seen as asserted or
ARM_DSM_REQUEST is seen deasserted, the CCM exits STOP mode according to the following
procedure
1. If vstby bit was set, deassert pmic_vstby_req to notify power management IC to change voltage
from standby voltage to functional voltage.
If sbyos was set, and CCM closed either external oscillator or on-chip oscillator, then CCM will
start external oscillator and on-chip oscillator by asserting ref_en_b signal and deasserting
cosc_pwrdown signal respectively.
2. After amount of CKIL’s defined in stby_count bits, wait until pmic_vfunctional_ready signal is
asserted. pmic_vfunctional_ready is used if an internal counter is not used. This is the notification
from power management IC that the voltage is ready at its functional value. (Figure 7-58 describes
the pmic signals connectivity.) Only then will CCM continue with the next steps:
3. Start FPM or CAMPs (based on definition of CAMP1_EN, CAMP2_EN and FPM_EN bits)
4. If any CAMP or on-chip oscillator were started, wait until oscnt has finished its counting to make
sure that external oscillator, CAMPs output and on-chip oscillator are ready.
5. If FPM was selected, wait until assertion of fpm_lrf.
6. Start PLLs. Only the PLLs that were configured to be on prior to the entrance to STOP mode will
be started.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-113
7. Enable VPU, GPU2D, and GPU clocks only.
CCM will request GPC to restore power by GPC_PUP_REQ. If power was removed from the ARM
platform or IPU or VPU or GPU2D or GPU, GPC will notify CCM by asserting signal GPC_PUP_ACK
that power to ARM, VPU, IPU, GPU2D, GPU and EMI is back on, and its safe to exit from STOP mode.
Only then CCM will do the following:
1. Once assertion of notification from SRC that the resets for the power gated modules has been
finished, (src_power_gating_reset_done is set) negate the low power request signals to all modules
and enable all modules clocks including ARM clocks and CKIL sync of Megamix (if it was turned
off), and return to run mode. (the clocks that their CCGR bits define not to be open in RUN mode
will not be opened, and will continued to be gated in RUN mode).
2. Once system is in run mode, negate signals ccm_ipg_stop and system_in_stop_mode.
Once the interrupt propagates through all the synchronization logic, the ARM CPU will recognize and
service it. This will force the negation of the ARM_DSM_REQUEST output. Prior to this point,
ARM_DSM_REQUEST and TZIC_DSM_WAKEUP were simultaneously asserted. Since
TZIC_DSM_WAKEUP has top priority, the system is able to wake up.
Before the ARM exits the ISR, it will clear the interrupt source. This will cause the
TZIC_DSM_WAKEUP signal to be negated. At this point, the two low power control signals are negated,
and the STOP sequence can be repeated at any time.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-114
Freescale Semiconductor
Figure 7-56 describes the connectivity of ARM, CCM and TZIC.
CCM
ARM_CLK
SYSTEM_BUS_CLK
STATE MACHINE
AND REGISTERS
SYNC
DFF FF
Q
SYNC
Q
FF FFD
IP BUS
Separate wakeup
DSM_REQUEST
interrupt masking
AXI BUS
DSM_WAKEUP
L2 CACHE
CTLR.
SYNC
D
FF FF
Q
STBYWFI
Q
DFF
DSM_INT_HOLDOFF
SYNC
register bit
Q FFD
FF
ARM CPU
FIQSYNC
Q FFD
FF
FIQ
IRQSYNC
Q FFD
FF
IRQ
ARM HARD MACRO
Standard interrupt
masking logic
.
.
.
SYNC
Q
FF FFD
INT[127]
.
.
.
INT[0]
INTERRUPT CONTROLLER
(TZIC)
Figure 7-56. ARM Low Power Request
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-115
Figure 7-57 describes CCM’s low-power state machine:
~arm_dsm_request | ~(lpm=01 | lpm=10) | tzic_dsm_wakeup
RUN
lpm=01 & arm_dsm_request &
~tzic_dsm_wakeup
lpm=10 & arm_dsm_request &
~tzic_dsm_wakeup
~system_in_stop_mode
STOP
(~arm_dsm_request |
tzic_dsm_wakeup) &
system_in_stop_mode
~system_in_wait_mode
(~arm_dsm_request |
tzic_dsm_wakeup) &
system_in_wait_mode
WAIT
(arm_dsm_request&
~tzic_dsm_wakeup)&
system_in_stop_mode
(arm_dsm_request&
~tzic_dsm_wakeup)&
system_in_wait_mode
gpc_pup_ack
gpc_pup_ack
STOP_GPC
SRPG_ARM
~gpc_pup_ack
~gpc_pup_ack
Figure 7-57. CCM Low Power State Machine
7.4.8.3.3
PMIC Signal Description
stby_count value should be larger than t1 - larger than the amount of time that it takes between CCM’s
negation of pmic_vstby_req, and the negation of pmic_vfuncional_ready (the signal coming back from
PMIC to indicate that the voltage started to change).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-116
Freescale Semiconductor
stop enter
stop exit
t1
pmic_vstby_req
t2
pmic_
vfuncional_ready
voltage
(1.2 V)
(0.8 V)
stby_count
Figure 7-58. PMIC Signal Description
Note: Software should configure the IOMUXC so that pmic_vstby_req and pmic_vfuncional_ready will
be operating in the correct ALT mode, so that they will be connected between CCM and the pads.
7.4.8.4
Low Power Screen Refresh Mode (LPSR)
The following section describes the solution for the low-power screen refresh support for the i.MX51. This
allows the IPU to refresh the screen by reading the data from the internal RAM (incorporated in SCC
module), while the system is in low-power mode by running from a low frequency clock. The low
frequency clock source can be chosen from three possible options. LPSR is similar to STOP mode with
the distinction that IPU can continue to access internal memory. For this capability, the clock to IPU,
internal memory system, and emi master 0 should continue to function. All other clocks will be closed,
including PLLs. When entering this mode, it is not allowed to configure IPU and emi to power gating /
SRPG.
To be able to supply the above clocks, ccm generates lpsr_clk_root. This clock is generated from the
following options:
• FPM clock output
• FPM clock output divided by 2
• GND. To reserve power, this option is to be chosen when LPSR is not used.
The lpsr_clk_root is connected to LPCG. The above clocks that need to continue to function in LPSR will
have a mux in LPCG to shift between their functional clock to the lpsr_clk_root. The control of the mux
comes from ccm and is named LPSR_mode_clk_en.When this signal is ‘0’ the mux will choose the
functional clock for the above modules. When this signal is ‘1’ the mux will choose the lpsr_clk_root as
the fed clock for the above modules. Figure 7-59 describes the LPCG part implemented for those clocks:
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-117
Other notifications corresponding to the same clock root
Enable clock root
Module clock enable
Override module enable
CGR control enable
Sample FF
Reset control enable
Module
Gating cell
Gated clock
bist_en
Fuse disable
Clock root
Split clock root
0
1
lpsr_clk_root
lpsr_mode_clk_en
Figure 7-59. LPCG Part Implementation
Note: the IPU module expects specific configuration prior entering LPSR mode—please refer to IPU
chapter for details.
7.4.8.4.1
LPSR Mode
LPSR mode uses the following procedure:
1. ARM will write to LPM bit to set it for LPSR mode.
2. ARM will write to DSM_INT_HOLDOFF bit in TZIC.
3. DSM_INT_HOLDOFF assertion forces the interrupt controller to stop the synchronizer clock for
incoming interrupts. Any interrupts that had previously been synchronized by the interrupt
controller will remain asserted.
4. If a wakeup event occurred or an interrupt was serviced or is pending, the CPU may abort the DSM
sequence by exiting the main shutdown code sequence and returning to the desired security mode.
If no wakeup event has occurred the software should execute the Wait For Interrupt (WFI)
instruction.
5. Upon execution, the WFI instruction will cause the ARM to drain its write buffers and enter a
quiescent state. At this point the ARM will assert the STANDBYWFI signal.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-118
Freescale Semiconductor
6. The ARM platform will then wait until the L2 cache controller has become inactive. Once the L2
is inactive and the CPU’s STANDBYWFI output is asserted, the ARM platform will assert the
ARM_DSM_REQUEST signal to the CCM.
7. The CCM will continuously synchronize both the ARM_DSM_REQUEST and
TZIC_DSM_WAKEUP inputs into the clock domain used by its internal state machine.The only
time when those signals will not be synchronized is, when PLLs will be closed. In this case the
exiting from LPSR mode will be done asynchronously (please refer to the section below describing
the exiting from STOP mode).
8. If TZIC_DSM_WAKEUP is negated and ARM_DSM_REQUEST is asserted, the CCM will begin
the LPSR shutdown sequence:
a) CCM will prepare the LPSR root clock - if FPM was chosen, it will start FPM and wait until
FPM_lrf is asserted.
b) CCM will stop ARM clock. ARM clock can be stopped even before FPM_lrf is asserted.
c) CCM will assert ccm_ipg_stop and ccm_int_mem_ipg_stop to indicate that it has started the
STOP entrance procedure.
9. CCM will request an acknowledge to close clocks of SAHARA, RTIC, IPU, SDMA, SCC, EMI
and AHBMAX if their clocks was not already closed in run mode. The requests will commence via
the following signals:
— SAHARA: sahara_ipg_stop_req
— RTIC: rtic_ipg_stop_req
— IPU: ipu_stop_clk_at_stop_req
— SDMA: sdma_ipg_stop_req
— SCC : scc_ipg_stop_req
— EMI: emi_lpmd, emi_lpmd_fast, emi_lpmd_int1, emi_lpmd_slow, emi_lpmd_garb
NOTE
Since EMI needs the aclk_fast (ddr clock) to be running for it to answer with
emi_lpmd, software should make sure to turn on the aclk_fast (ddr_clk)
before entering any low power mode that requests the emi_lpmd.
— AHBMAX: ahbmax_halt_req
10. Once the above modules finished their operation and are ready to enter low power mode, they
acknowledge CCM that its safe to turn of their clocks. The acknowledge signals are as follows:
— SAHARA: sahara_ipg_stop_ack
— RTIC: rtic_ipg_stop_ack
— IPU: ipu_stop_clk_ack
— SDMA: sdma_ipg_stop_ack
— SCC: scc_ipg_stop_ack
— EMI: emi_lpack, emi_lpack_fast, emi_lpack_int1, emi_lpack_slow, emi_lpmd_garb
— AHBMAX: ahbmax_halt_ack
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-119
11. The requests will be generated by CCM in stages. CCM will continue from stage to stage once all
the acknowledges of a present stages were received. The stages are as follows:
— Stage 1: SAHARA, RTIC, IPU, SDMA
— Stage 2: SCC
— Stage 3: AHBMAX
— Stage 4: EMI
Once CCM receives all the acknowledge signals needed, and if at least 8 ipg_clk cycles has elapsed since
the assertion of ccm_ipg_stop signal, then it will enter STOP mode and does the following tasks in the
order they are written below:
1. Close the system modules clocks, not including pgc_clk.
2. Assert system_in_stop_mode signal.
Once CCM is in STOP mode, it will check if TZIC_DSM_WAKEUP signal has asserted or if
ARM_DSM_REQUEST has negated during the process of entering STOP mode. If it has occurred, then
CCM will exit STOP mode.
If TZIC_DSM_WAKEUP is not asserted and ARM_DSM_REQUEST is asserted, then CCM will move
to state STOP_GPC and generate a request to GPC to power down the ARM platform, GPU, GPU2D and
VPU by asserting signals ccm_pdn_4arm_req and ccm_pdn_4all_req. If in GPC those modules are defined
to be powered down on STOP mode then GPC will commence powering down for them.
NOTE
IPU is not allowed to be powered down in LPSR mode. When finished, the
GPC sends the pdn_ack signal.
In parallel to the request to GPC to power down the needed modules, the following takes place:
1. Assert lpsr_mode_clock_en to shift the lpcg mux to the lpsr_clk_root.
2. Open the clocks of the modules involved in LPSR, that is, IPU and emi aclk_m3 (ipu_clk_enable),
emi (emi_int1_clk_enable), downsizer, axi2ahb, regslice, ahbmux (ahbmux2_clk_enable), scc
(scc_clk_enable).
3. Deassert ccm_int_mem_ipg_stop and scc_ipg_stop_req (connected to scc to notify it to exit STOP
mode).
4. Deassert emi_lpmd, emi_lpmd_int1 (connected to emi to notify it to exit low power mode on int1
and on master side).
5. Assert ccm_lpsr_ipu to notify IPU to enter LPSR mode.
After the GPC sends the pdn_ack signal, the following takes place:
1. Close PLLs and dpll_ips by deasserting dpll_en_dpllip and ref_clk_en_dpllip.
2. Close CAMPs and FPM (only if FPM is not the source for lpsr_clk_root) by de asserting
ccm_CAMP1_en, ccm_CAMP2_en and ccm_fpm_en.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-120
Freescale Semiconductor
3. If sbyos bit was set, then de assert ref_en_b signal to close external oscillator and assert
cosc_pwrdown to put on-chip oscillator in power down mode. (if they were not already closed by
software. If one of them was already closed by software then discard the sbyos operation for it and
perform the sbyos operation only on the one that is working. If both of them were closed in run
mode, then discard sbyos operation for both of them).
4. If vstby bit was set, then assert pmic_vstby_req signal, to indicate power management IC to shift
voltage to standby voltage.
CCM’s low power state machine will remain in state “STOP_GPC” until LPSR mode is exited.
7.4.8.4.2
Exiting LPSR Mode
As soon as the unsynchronized TZIC_DSM_WAKEUP signal is seen as asserted or the
ARM_DSM_REQUEST is negated, the CCM begins the process of exiting LPSR mode, according to the
following procedure:
1. If vstby bit was set, deassert pmic_vstby_req to notify power management IC to change voltage
from standby voltage to functional voltage.
If sbyos was set and CCM closed either external oscillator or on-chip oscillator, the CCM will start
external oscillator depending on the configuration of the on-chip oscillator by asserting ref_en_b
signal and deasserting cosc_pwrdown signal respectively.
2. After amount of CKILs defined in stby_count bits, wait until pmic_vfunctional_ready signal is
asserted. This is the notification from power management IC that the voltage is ready at its
functional value. (Figure 7-58 describes the pmic signals connectivity.) Only then will CCM
continue with the next steps.
3. Start FPM (if not already working) or CAMPs (based on definition of CAMP1_EN, CAMP2_EN
and FPM_EN bits).
4. If any CAMP or on-chip oscillator were started, wait until oscnt has finished its counting to make
sure that external oscillator, CAMPs output and on-chip oscillator are ready.
5. If FPM was selected, wait until assertion of fpm_lrf (if its not already working).
6. Start PLLs. Only the PLLs that were configured to be on prior to the entrance to LPSR mode will
be started.
7. Enable VPU, GPU2d and GPU clocks only.
CCM requests that GPC restores power by GPC_PUP_REQ. If power was removed from the ARM
platform or IPU, VPU, GPU2D, GPU, GPC notifies CCM by asserting signal GPC_PUP_ACK that power
to ARM, IPU, VPU, GPU2D, GPU and EMI is back on, and it is safe to exit from LPSR mode. Only then
does CCM do the following:
1. Once assertion of notification from src that the resets for the power gated modules has been
finished, (src_power_gating_reset_done is set) deassert ccm_lpsr_ipu.
2. Once ipu_lpsr_wakeup_ack is asserted, assert emi_lpmd, emi_lpmd_int1 (connected to EMI to
notify it to enter low power mode on int1 and on master side), and ccm_int_mem_ipg_stop and
scc_ipg_stop_req (connected to scc to notify it to enter STOP mode).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-121
3. Once emi_lpack_int1 and scc_ipg_stop_ack are received, close the clocks of the modules involved
in LPSR, that is, IPU and emi aclk_m3 (ipu_clk_enable), emi (emi_int1_clk_enable), downsizer,
axi2ahb, regslice, ahbmux (ahbmux2_clk_enable), scc (scc_clk_enable). emi_lpack is ignored
since it willl not be received - the fast clock is not available in this state, hence emi will not be able
to generate the emi_lpack. The emi_lpack_int is an enough indication that emi has finished its
function, since IPU has already stopped.
4. Deassert lpsr_mode_clock_en to shift the lpcg mux from the lpsr_clk_root to the functional root
clock.
5. Enable all modules clocks including ARM clocks and return to run mode.
6. Once system is in run mode, negate signals ccm_ipg_stop and system_in_stop_mode and all low
power requests (emi_lpmd, emi_lpmd_int1, emi_lpmd_fast, emi_lpmd_slow, scc_ipg_stop_req,
and so on.).
Once the interrupt propagates through all the synchronization logic, the ARM CPU will recognize and
service it. This will force the negation of the ARM_DSM_REQUEST output. Prior to this point,
ARM_DSM_REQUEST and TZIC_DSM_WAKEUP were simultaneously asserted. Since
TZIC_DSM_WAKEUP has top priority, the system is able to wake up.
Before the ARM exits the ISR, it will clear the interrupt source. This will cause the
TZIC_DSM_WAKEUP signal to be negated. At this point, the two low power control signals are negated,
and the STOP sequence can be repeated at any time
7.4.8.5
LPMD Request from SRC (Reset Controller)
SRC generates a signal named emi_DVFS_req. This signal will be asserted in case of WARM reset to
request emi to enter sdram into selfrefresh. Since CCM is also a generator for the request to emi for
entering sdram to selfrefresh, then the SRC request will be connected to CCM, and CCM will generate one
common request to emi for sdram selfrefresh. This common request will assert either if CCM is the
originator of the request or if the SRC is the originator of the request. The SRC request (named
emi_DVFS_req) is connected to CCM’s input src_warm_DVFS_req. CCM generates the request to EMI
via DVFS request signal. This signal generation will be combined with the signal coming from SRC
(src_warm_DVFS_req) to generate one DVFS request signal to EMI.
The acknowledge from emi regarding the self-refresh of EMI is connected to both CCM and SRC.
7.4.8.6
Low Power Audio Playback Mode (LP-APM)
Low Power Audio Playback mode (APM) defines special low power mode, dedicated for Audio only
playback mode. It involves PLL on/off and frequency settings, as well as voltage and clock gating aspects,
to enable lowest possible power consumption.
This section covers APM, as well as assumptions, and enter/exit flows from the APM mode.
7.4.8.6.1
Low Power APM Mode Definition
APM can be entered by DVFS settings or by manual clock configuration.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-122
Freescale Semiconductor
Only one PLL of i.MX51 is running—ARM PLL. This PLL is set to the maximal frequency that ARM can
run at that lowest point, while still ensuring ARM and bus system processing needs. .
The peripherals will also work on low voltage. The peripherals work on a frequency suitable for this low
voltage (about third of the nominal frequency). For information regarding voltages at low performance
operating mode, please refer to the i.MX51 Datasheet.
For i.MX51 used as master on SSI clocks, the MCU PLL frequency must be set to an integer multiplication
of SSI clock
7.4.8.6.2
LP-APM Mode Restrictions
The following restrictions apply to LP-APM mode restrictions.
• Enter and exist to/from Low Power APM mode has effect on Display and SSI clocks. If i.MX51 is
master on SSI clocks, audio playback will be interrupted during the switch, and as such - it is not
recommended to switch modes during audio playback.
• Due to impact to Display controller clock, switch to/from LP-APM, SW should take that into
consideration. This is not applicable when using Smart Display.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-123
Figure 7-60 describes the sequence to be performed to switch from a high power settings (3 PLLs, high
voltage) to the low power APM.
Initial state
3 PLLs.
ARM high voltage (1.0 V)/532 Mhz
Peripherals high voltage (1.2 V)/665 PLL
Serial clocks 216 PLL
Playback triggered, to be played in low power APM
DVFS switch of ARM from 532 at 1 V to 200 at 0.81 V.
This DVFS switch should be triggered by ARM This switch will be performed by regular DVFS on ARM,
that is, switch to step frequency , lock PLL to 200 and
switch back to the locked PLL—then GPC will reduce voltage.
Indication that the switch finished
CCM addition: This stage should be done
via handshake with the peripherals
Also, need
to follow restrictions for some peripherals
as listed
Switch bus clock roots to ARM PLL (200) and close two other
PLLs. In this stage the frequencies of the busses will be low:
ddr=200/4=50 Mhz
ahb=200/5=40 Mhz
ipg=200/10=20 Mhz
Indication that the glitchless mux has switched
Change of the bus dividers so that frequencies are close to 133/66.5
ddr=ahb=200/2=100
ipg=200/4=50
Perform DVFS on Peripherals to divide peripherals clock roots
by 3, and to lower peripherals voltage to 1.0v.
On this stage the playback can be started.
Figure 7-60. Flow of Entering Low Power APM on i.MX51
Table 7-44 shows the LP-APM flow frequencies.
Table 7-44. LP-APM Flow Frequencies
Stage
Farm
[Mhz]
Varm
[v]
Fahb
[Mhz]
Initial state
Fipg
[Mhz[
Vper
[v]
532
1.0
133
66.5
1.2
run system from 3 PLLs:
ARM PLL = 532 Mhz supplying ARM
PERIPH PLL = 665 Mhz supplying busses (ahb, ipg).
Serial PLL = 216 Mhz supplying USB, TVE, and so on.
DVFS on ARM
200
0.81
133
66.5
1.2
GPC operation triggered by software
Switch bus clocks to
ARM PLL
200
0.81
40
20
1.2
Peripheral dividers are not changed during the shift.
The shift should involve EMI handshake
Change bus dividers
200
0.81
100
50
1.2
—
Comments
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-124
Freescale Semiconductor
Table 7-44. LP-APM Flow Frequencies
Stage
Farm
[Mhz]
Varm
[v]
Fahb
[Mhz]
DVFS on peripherals
DVFS on peripherals
Fipg
[Mhz[
Vper
[v]
200
0.81
50
25
1.0
DVFS on peripherals with div=2
200
0.81
33.3
16.66
1.0
DVFS on peripherals with div=3
Comments
Figure 7-62 shows the frequency and voltage flow
f/v
Glitchless mux switch:
532 MHz
EMI handshake supported
IPU not supported.
f ARM
200 MHz
133 MHz
f-ARM / 2
100 MHz
f-ARM / 4
DVFS div-2
50 MHz
f AHB
f IPG = AHB/2
50 MHz
1.2 V
Vperiph
1.0 V
Varm
t
Initial
State
DVFS
on ARM
Switch to single
PLL source
DVFS
on Periph.
Figure 7-61. Frequency and Voltage Flow
7.4.8.7
SDMA Clock Gating in APM Scenario
In LP-APM scenario, SDMA accesses EMI through master 4. Once EMI notifies that master 4 is idle
(based on auto clock gating of EMI), then we can assume that all the data needed was transferred to
SDMA, and SDMa clocks can be gated off. The SDMA clocks should be turned on, once SSI requests the
next data from SDMA. Between those two indications, SDMA clocks can be gated off, by using
sdma_clk_enable output of CCM. All this operation will be masked by apm_sdma_clk_gate_en_bit. If this
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-125
bit is not enabled, then the SDMA clock gating operation will not be based on m4_clk_gate signal.
Figure 7-62 describes the design implementation.
m4_clk_gate_en
spare_input_17
CCM
EMI
0 - bus idle
sdma_clk_enable
apm_sdma_clk_gate_en_bit
LPCG
SIPMIX
1 - clock enable
0 - clock disable
spare_input_11-16
SSI1/2/3
ipd_ssi_tx_0/1_dma_req_b
0 - dma req
CCM logic:
EMI bus idle → sdma_clk_enable = 0 (disable SDMA clock).
Upon SSI request (any of ipd_ssi_* = 0) → sdma_clk_enable = 1 (enable SDMA clock).
Wait for EMI bus idle to assert (m4_clk_gate_en = 1) → start from begining to look for bus idle.
The above should be masekd if the apm_sdma_clk_gate_en_bit is deasserted, (sdma clk enable).
Figure 7-62. Design Implementation Scheme
7.4.8.8
Wake Up Detector
When the MEGAMIX is in SRPG mode, all the modules in the MEGAMIX do not receive clock and
power; hence they cannot wake up the system from external interrupts. The Wake Up Detector allows the
reception of the following external interrupts when the MEGAMIX is SRPGed:
• KPP
• SDHC 1/2 Detection
• GPIO1_4, GPIO1_5, GPIO1_6, GPIO1_7, GPIO1_8, GPIO1_9
The Wake Up detector catches interrupts only when the clocks are stopped, that is, upon dpll_en_dpllip
signal deassertion. In order to receive an interrupt, a corresponding pin has to be configured at IOMUX
controller as described below.
7.4.8.8.1
KPP Interrupt
Interrupt occurs when key pressed. To enable the interrupt set corresponding bit at CCM_CIMR register
to zero.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-126
Freescale Semiconductor
7.4.8.8.2
SDHC Interrupts
Interrupt occurs when SD card is inserted. To enable the interrupt set corresponding bit at CCM_CIMR
register to zero. Each SD has separate enable and status bit.
7.4.8.8.3
GPIO Interrupts
The i.MX51 can wake up from STOP mode with MEGAMIX at SRPG state by one of the six GPIO
interrupt described above.
Each interrupt can be masked at CCM_CIMR register. GPIO direction and interrupt type have to be
configured for each GPIO at CCM_CR2 register, as it is configured at GPIO module.
7.4.8.9
Recommendations for Using Low Power Consumption from CCM
In addition to using APM mode for low power, here are the recommendations for configuring CCM so that
it consumes less power. These recommendations should be followed when applicable:
•
•
•
•
•
•
•
•
Use the AHB clock source as the source of all AXI buses and VPU core clkin - this case the power
of the AXI dividers will be preserved.
Work from one PLL and disable the other two PLLs.
Generate SSI external clocks from SSI clock roots—in this case the SSI external clocks dividers
power will be preserved.
Generate SPDIF clocks from SSI clock roots—in this case the SPDIF clocks dividers power will
be preserved. Gate debug clocks (arm debug clock, CTIs, DAP,...) and functional clocks that are
not required for operation by CCGR registers. If a whole root clock is not required and gated by
CCGR bits, it will gate the clock entering the divider.
Shut external oscillator when not required.
Lower the voltage and frequency (DVFS) when possible.
Enable dynamic clock gating (enables from modules) so the clocks will be gated automatically
when not used.
Use the lowest possible frequencies of the PLLs to generate low frequencies that will enter the
clock dividers and as a result save power consumed by the CCM.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-127
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
7-128
Freescale Semiconductor
Chapter 8
Debug Architecture
8.1
Overview
This chapter describes the debug architecture.
8.1.1
Introduction
This chapter describes the hardware and software debug and application development features and
resources of i.MX51. There are core/platform-specific resources, resources associated with some of the
more complex IP blocks, and chip-wide resources. Also discussed is the interface to external debug and
development tools.
The debug architecture of i.MX51 is based on that of previous members of the i.MX application processor
family.
An overview of the primary debug capabilities and features includes:
• JTAG-based access (control, monitoring), built around the Secure Controller (SJC)
• Trace Port
• Real-time and Halt-mode debug and profiling capabilities of the Cortex-A8 core platform
• Real-time and Halt-mode debug capabilities of the SDMA core
• An SOC-wide cross-trigger system built around ARM’s Embedded Cross Trigger (ECT)
• Visibility of pre-selected critical internal signals via pin muxing
• External memory interface/controller arbitration profiling
Each of these features will be described in detail in the following sections of this chapter. The i.MX51 also
supports ARM CoreSight architecture for system debug and trace capabilities.
8.1.2
Debug Strategy
The following features form the building blocks of the i.MX51 Debug design:
• Software debug (MSFT kernel)
• Trace the CPU activity via ETM trace port or ETB (ARM only)
• Control and monitor via JTAG
• Monitor preselected critical internal signals via pin muxing - scope
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-1
8.2
System Secure Controller—SJC
The SJC module is the bridge between external development and test instrumentation and the internal
JTAG-accessible debug and test resources. It implements and manages the daisy-chained topology
consisting of it’s own TAP and those of the SDMA, the ARM core, and the ARM Debug Access Port
(DAP). The ARM core is not part of a daisy chain.
8.2.1
JTAG Topology
Figure 8-1 shows a high level block diagram of the i.MX51 JTAG connectivity.
ETM, CTI
SDMA
APB
ARM
DAP
TDI TDO
TDO
TDI
OnCE
TDI
TDO
Cortex-A8
ICE
SJC
SDMA
TAP Ctlr
TDI
TDO
SJC TAP Ctlr
TDI
Extra Debug Registers
i.MX51 I/O PINS
TRST TCK TMS TDI TDO
JTAG PORT
Figure 8-1. JTAG Connectivity
8.2.2
Secure JTAG Controller Main Feature
The secure JTAG controller main features are as follows:
• IEEE 1149.1 (standard JTAG) interface to off-chip test and development equipment
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-2
Freescale Semiconductor
•
•
•
•
•
8.2.3
— Includes an SJC-only mode for true IEEE 1149.1 compliance, used primarily for board-level
implementation of boundary scan.
Debug-related control and status, such as putting selected cores into reset and/or debug mode and
the ability to monitor individual core status signals via JTAG.
System status, such as the state of the PLLs (locked or not locked)
Generic status and control, defined on a per-SOC basis by the architecture team
Factory test related control/status such as PLL bypass and memory BIST
Four levels of security, ranging from no security to no JTAG accessibility to the chip.
SCJ TAP Port
The SJC in the i.MX51 supports the following standard JTAG pins: TRSTB, TDI, TDO, TCK, and TMS.
8.2.4
•
•
•
•
•
•
•
•
8.2.5
SJC Main Blocks
Interface to the outside world via the standard JTAG pins
Interface to the external Debug_Event pin
A master TAP controller, which implements the standard JTAG state machine.
Implementation of the mandatory and optional IEEE P1149.1 (JTAG) instructions
— Mandatory: “EXTEST”, “SAMPLE/PRELOAD,” and “BYPASS”
— Optional: “ID_CODE” (SOC JTAG ID register), “HIGHZ”
Supports the SDMA’s DR-path-only JTAG architecture by implementing the controller portion of
its TAP (including “BYPASS” as the default state) within the SJC
Provides the serial interfaces to various DSP-domain JTAG resources (not implemented on
i.MX51)
The ExtraDebug registers, which implement a variety of control and status features
— Three 32-bit insecure general purpose status registers
— Two 32-bit secure status registers - one predefined, one general purpose.
— Control and status registers for debug, core, charge pump, PLL, and BIST related functions
— Control bits for memory timing control (not used on i.MX51)
Four levels of fuse-defined security, ranging from no security to no access.
SJC Features—JTAG Disable Mode
In addition to four different JTAG security modes that are implemented internally in the Secure JTAG
Controller (SJC), there is an option to disable the SJC functionality by e-FUSE configuration. This creates
an additional JTAG mode, JTAG Disabled, with the highest level of JTAG protection. In this mode, all
JTAG features are disabled. Specifically, the following debug features are disabled in addition to the
features that were already disabled in “No Debug” JTAG mode:
•
•
Memory BIST
Boundary scan register (BSR)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-3
•
•
•
Non-Secure JTAG control registers (PLL configuration, Deterministic Reset, PLL bypass)
Non-Secure JTAG status registers (Core status)
Chip Identification Code (IDCODE)
8.2.6
SJC Registers Summary
The following is a summary of the SJC registers.
KEY:
Always
Reads
One
1
Always
Reads
Zero
Read/
Write
Bit
0
ReadOnly
Bit
bit
bit
WriteOnly
Bit
bit
Write 1 bit
to
Clear W1C
SelfClear
Bit
0
N/A
bit
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL1_lrf
0
0
A_WFI
A_DBG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ccm_pdn_4all_req
ccm_pdn_4arm_req
system_in_stop_mode
system_in_wait_mode
ccm_ipg_stop
ccm_ipg_wait
R
S_STAT[1:0]
30
PLL2_lrf
GPUSR1
R
($BASE + 0x00) W
31
ccm_ref_en_b
Name
PLL3_lrf
Table 8-1. SJC Registers Summary
W
GPUSR2
R
($BASE + 0x01) W
R
0
0
sdma_debug_core_state[3:0
]
W
GPUSR3
R
($BASE + 0x02) W
R
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-4
Freescale Semiconductor
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
iim_fuse_latched
0
~src_int_boot
ipt_secur_block
ft
bsf
rsf
ebg
ebf
swe
swf
kta
ktf
dpdck0_2_en_pll3
Name
jtag_sw_rst
Table 8-1. SJC Registers Summary (continued)
SSR
R
($BASE + 0x05)
W
R
RSSTAT
sjm
~pdf_pll2[0]
mfi_pll1[3:0]
pll_bypass_en3
PLLBYPASS
PLLBPEN
sjc_cpen_pll1
sjc_cpen_pll2
sjc_cpen_pll3
sjc_cpres_pll1
sjc_cpres_pll3
0
sjc_cpres_pll2
sjc_crstrt_pll1
0
sjc_control_sel_pll1
W
0
pll2_by
pll_by pll_byp
pass_
pass_ ass_en
alterna
1
en2
tive
sjc_control_sel_pll2
0
0
0
sjc_control_sel_pll3
R
sjc_crstrt_pll2
GPUCR1
R efuse
($BASE + 0x09) W _pro
g_su
pply_
gate
sjc_crstrt_pll3
W
pll1_bypass_alternative
PLLBR
R
($BASE + 0x08) W sjc_ac_scan_cpd_pll3[ sjc_ac_scan_cpd_pll2[3: sjc_ac_scan_cpd_pll1[3:0
3:0]
0]
]
R
pdf_pll2[3:1]
dpdck0_2_en_pll2
0
ref_clk_div_pll1
~pdf_pll1[0]
pdf_pll1[3:1]
mfi_pll3[3:0]
ref_clk_div_pll3
~pdf_pll3[0]
dpdck0_2_en_pll1
mfi_pll2[3:0]
W
ref_clk_div_pll2
R
pdf_pll3[3:1]
W
GPCCR
R
($BASE + 0x07) W
0
0
0
0
0
0
0
0
0
0
usbphy
_sourc
e_sel
0
ipt_sjc_test_ ipt_sjc_lch_mode[
mode[1:0]
2:0]
0
0
0
0
0
0
0
0
ipt_bi
pg_tdi
en
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-5
GPUCR3
R
($BASE + 0x0B) W
W
R
BISTCR1
R
($BASE + 0x0F) W
BISTCR2
R
($BASE + 0x10) W
8-6
0
0
0
0
0
R
gbist
W gbist_mode[2:0] _rese
t
0
0
0
0
R mcu_rom_gbist_addr[3: 0
0]
W
0
0
0
0
0
0
0
0
0
0
0
0
0
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
init_perclk_podf[1]
~init_perclk_podf[0] ~init_emi_slow_podf[2]
0
0
0
0
0
0
sdma_rom_gbist_addr[9:0]
0
0
~init_axi_b_podf[0]
~init_perclk_pred1[0]
0
0
0
0
0
sjc_interrupt
init_axi_b_podf[1]
init_emi_slow_podf[1:0]
0
sjc_ipt_io_tail_bypass init_perclk_pred1[1]
0
~init_axi_b_podf[2]
init_perclk_pred2[2:0]
~init_perclk_podf[2]
0
init_nfc_podf[1:0]
~init_nfc_podf[2]
~init_ipg_podf[0]
~init_periph_apm_sel[1]
init_periph_clk_sel
0
axi_a_clk_bypass
27
0
emi_slow_clk_bypass
28
0
ahb_clk_bypass
sjc_dse0
sjc_dse1
sjc_dse_en
29
init_ssi_apm_clk_sel
30
init_periph_apm_sel[0]
init_ahb_podf[1:0]
~init_ahb_podf[2]
~init_axi_a_podf[1:0]
31
init_ipg_podf[1]
0
sjc_sr_slow
0
sjc_sr_fast
0
sjc_sre
0
smart_bypass
W
en_tester_cntl
R
owire_line_alt7_hard_en
GPUCR2
R
($BASE + 0x0A) W
init_axi_a_podf[2]
Name
arm_clk_off_on_lpm
Table 8-1. SJC Registers Summary (continued)
0
gbist_r
owfast
sdma
mcu_g
releas
_gbist
invoke
bist_se
e_en
_selec
lect
t
mcu_rom_gbist_addr[13:4]
0
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
sel_jpc_wir
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L2cache_fail_sms
ETB_fail_sms
SIPMIX_star_fail_sms
SIPMIX_asap_fail_sms
LPMIX_reg_fail_sms
Freescale Semiconductor
0
0
0
pg_m
pg_m
pg_cntl_vpu ode_ pg_cntl_ipu ode_i
vpu
pu
0
0
0
0
0
0
0
0
0
0
EMI_fail_sms
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
GPU_reg_fail_sms
24
0
GPU_star_fail_sms
25
0
IPU_asap_fail_sms
26
tigerp_vl_bist_en
ETB_bist_clkdiv[2:1]
~L2Cache_bist_clkdiv[1:0]
L2Cache_bist_clkdiv[2]
L2Data_bist_clkdiv[1:0]
27
VPU_bist_en_sms_clk
sel_jpc_wdr
0
28
~ETB_bist_clkdiv[0]
sel_sms_wir
0
29
~L2Data_bist_clkdiv[2]
sel_sms_wdr
0
L2data_fail_sms
bist_
en_w
rck
30
bist_en_rom_36k_gbist
EMI_bist_en_sms_clk
0
VPU_asap_fail_sms
BISTCR4
R
($BASE + 0x12) W
31
bist_en_sms_clk_tve
Name
gpu2d_bist_clk_en
GPU_bist_en_sms_clk
R
0
VPU_reg_fail_sms
W
0
GPU2D_asap_fail_sms
MBISTPASSR1 R
($BASE + 0x16)
IPU_bist_en_sms_clk
W
BISTCR5
R
($BASE + 0x13) W
GPU2D_reg_fail_sms
R
megamix_bist_en_sms_clk
W
SDMA_rom_bist_failed
Table 8-1. SJC Registers Summary (continued)
releas
e_en
0
releas
e_en
TVE_a GBIST
sap_fai _rom_f
l_sms ailed
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-7
8-8
VPU_asap_ready_sms
L2data_ready_sms
L2cache_ready_sms
ETB_ready_sms
SIPMIX_star_ready_sms
SIPMIX_asap_ready_sms
LPMIX_reg_ready_sms
IPU_asap_ready_sms
0
0
0
0
0
0
0
0
0
0
0
0
0
TVE_asap_bist_mask
GBIST_rom_mask
VPU_asap_bist_mask
L2data_bist_mask
L2cache_bist_mask
ETB_bist_mask
SIPMIX_star_bist_mask
SIPMIX_asap_bist_mask
LPMIX_reg_bist_mask
IPU_asap_bist_mask
0
GPU_star_bist_mask
GPU_reg_bist_mask
EMI_bist_mask
W
0
0
0
0
0
0
0
0
0
0
0
0
0
EMI_ready_sms
GPU_reg_ready_sms
0
GPU_star_ready_sms
VPU_reg_ready_sms
R
0
VPU_reg_bist_mask
W
GPU2D_asap_ready_sms
W
0
GPU2D_asap_bist_mask
MBISTMASKR1 R
($BASE + 0x1A)
GPU2D_reg_ready_sms
R
GPU2D_reg_bist_mask
MBISTDONER1 R
($BASE + 0x18)
SDMA_rom_bist_done
Name
SDMA_rom_bist_mask
Table 8-1. SJC Registers Summary (continued)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TVE_a
GBIST
sap_re
_rom_
ady_s
done
ms
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8.2.7
SJC Registers Description
The following registers are accessed using the extra debug register.
8.2.7.1
General Purpose Unsecured Status Registers 1,2,3 (Three Registers)
The General Purpose Unsecured Status Register 1 is a read-only register used to check the status of the
different cores and the PLL. The rest of its bits are for general purpose use.
GPUSR1
Addr
$BASE + 0x00
General Purpose Unsecured Status Register 1
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE:
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
A_WFI
A_DBG
PLL PLL
PLL
3_lr 2_lr
1_lrf
f
f
0
0
0
0
0
0
TYPE:
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-2. General Purpose Unsecured Status Register 1
Table 8-2. General Purpose Unsecured Control Register Description
Name
31:10
GPUSR1 Bits
Description
Settings
reserved
9
PLL3_lrf
status bit indicating if dpll3 is locked
0 = PLL not locked
1 = PLL lock
8
PLL2_lrf
status bit indicating if dpll2 is locked
0 = PLL not locked
1 = PLL lock
7
PLL1_lrf
status bit indicating if dpll1 is locked
0 = PLL not locked
1 = PLL lock
6:2
GPUSR1 Bits
reserved
1:0
GPUSR1 Bits
SJC internal register - see SJC guide
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-9
GPUSR2
Addr
$BASE + 0x01
General Purpose Unsecured Status Register 2
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
TYPE:
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
0
0
0
0
0
0
sdma_debug_core_state[3:0]
TYPE:
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-3. General Purpose Unsecured Control Register 2 Description
Table 8-3. General Purpose Unsecured Control Register 2 Description
Name
Description
31:4
GPUSR2 Bits
Settings
reserved
SDMA core status (ipc_cstatus[3:0]). For whole bus value 0000 - PGM
3:0
0001 - DATA
sdma_debug_c see GPUSR2 register.
0010 - Change Flow
ore_state[3:0]
0011 - Set Wakeup
0100 - DEBUG
0101 - FU Bus
0110 - SLEEP
... See SDMA spec for more details,
GPUSR3
Addr
$BASE + 0x02
General Purpose Unsecured Status Register 3
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE:
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
ccm_
pdn_
4arm
_req
syste
m_in
_stop
_mo
de
0
0
0
0
0
0
0
ccm
_ref
_en
_b
0
0
ccm_
pdn_
4all_r
eq
syste
m_in
ccm_ipg ccm_ipg
_wait
_stop
_wait
_mo
de
TYPE:
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-4. General Purpose Unsecured Control Register 3 Description
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-10
Freescale Semiconductor
Table 8-4. General Purpose Unsecured Control Register 3 Description
Name
Description
Settings
31:9
GPUSR3 Bits
Reserved
—
8
ccm_ref_en_b
indicates if external oscillator is enabled
0 = external oscillator disabled
1 = external oscillator is enabled
7:6
GPUSR3 Bits
reserved
—
indicates a request to GPC to power down all units
5
ccm_pdn_4all_r
eq
0 = no power down request to GPC
1 = power down request sent to GPC
indicates a request to GPC to power down ARM
4
ccm_pdn_4arm
_req
0 = no power down request to GPC
1 = power down request sent to GPC
indicates system is in stop mode
3
system_in_stop
_mode
0 = system not in stop mode
1 = system in stop mode
indicates system is in wait mode
2
system_in_wait
_mode
0 = system not in stop mode
1 = system in stop mode
1
ccm_ipg_stop
indicates CCM started stop entrance procedure
0 = CCM did not start stop entrance
procedure
1 = CCM started stop entrance procedure
0
ccm_ipg_wait
indicates CCM started wait entrance procedure
0 = CCM did not start wait entrance
procedure
1 = CCM started wait entrance procedure
8.2.7.1.1
Security Status Register
This register is used to reflect IC security status and is accessible in all the security modes. The assumption
is that the information contained in this register does not pose any security breach for the system.
SSR
TYPE:
RESET:
Addr
$BASE + 0x06
Security Status Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
iim_fuse
_latched
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
FT
BSF
RSF
EBG
EBF
KTA
KTF
0
ipt_s
~src
ecur
_int_
_bloc
boot
k
RSSTAT
SJM
SWE SWF
TYPE:
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-5. Security Status Register
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-11
Table 8-5. Security Status Register Description
Name
31:17
SSR Bits
16
iim_fuse_latched
15
SSR Bit
14
~src_int_boot
13
ipt_secur_block
12:0
SSR Bits
Description
Settings
Reserved
—
Indicates that fuse values have been latched
0 = fuses have not yet been latched
1 = fuses have been latched
Reserved
—
SRC internal boot
—
Indicates if invasive/non-invasive debug can be done to 0 = invasive and non-invasive debug cannot
the ARM
be done
1= invasive and non-invasive debug can be
done
SJC internal registers reserved—see SJC guide
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-12
Freescale Semiconductor
8.2.7.2
General Purpose Clocks Control Register
This register is used to configure clock related modes in the i.MX51. These bits are directly connected to
JTAG outputs.
GPCCR
TYPE:
Addr
$BASE + 0x07
General Purpose Clocks Control Register
BIT 31
30
jtag_s
w_rst
dpdc
k0_2
_en_
pll3
29
28
27
pdf_pll3[3:1]
26
25
24
ref_
~pdf
clk_
_pll
div_
3[0]
pll3
23
22
21
20
19
dpdc
k0_2
_en_
pll2
mfi_pll3[3:0]
18
17
BIT 16
~pdf_pll
2[0]
pdf_pll2[3:1]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note:
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
dpd
ck0
_2_
en_
pll1
pdf_pll1[3:1]
ref_clk
_div_pl
l2
mfi_pll2[3:0]
~pdf ref_cl
_pll1[ k_div
0]
_pll1
mfi_pll1[3:0]
SCLKR
TYPE:
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-6. General Purpose Clocks Control Register
Table 8-6. General Purpose Clocks Control Register Description
Name
31
jtag_sw_rst
Description
provides software reset to SRC
Settings
—
enables double frequency clock for dpllip3
30
dpdck0_2_en
_pll3
0 = double frequency clock disabled
1= double frequency clock enabled
29:27
pdf_pll3[3:1]
0001 - PDF = 1
0000 - PDF = 2
0011 - PDF = 3
0010 - PDF = 4
0101 - PDF = 5
0100 - PDF = 6
0111 - PDF = 7
0110 - PDF = 8
1001 - PDF = 9
1000 - PDF = 10
1011 - PDF = 11
1010 - PDF = 12
1101 - PDF = 13
1100 - PDF = 14
1111 - PDF = 15
1110 - PDF = 16
26
~pdf_pll3[0]
pre division factor for dpllip3
Note: This is the actual value of the pre-division factor.
(after the PLL adds 1)
See DPLL(IP) config spec for more details
divides pll3 reference clock for dpllip3
25
ref_clk_div_pl
l3
0 = reference clock not divided by 2
1 = reference clock divided by 2
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-13
Table 8-6. General Purpose Clocks Control Register Description (continued)
Name
24:21
mfi_pll3[3:0]
Description
Settings
0000 = MFI is 5
multiplication factor for dpllip3
If MFI is written a value less than 5, it will be defaulted to 5 0001 = MFI is 5
...
This is also valid for ac scan mode
0101 = MFI is 5
0110 = MFI is 6
0111 = MFI is 7
...
enables double frequency clock for dpllip2
20
dpdck0_2_en
_pll2
0 = double frequency clock disabled
1= double frequency clock enabled
19:17
pdf_pll2[3:1]
see above bits 29:26
pre division factor for dpllip2
16
~pdf_pll2[0]
divides pll2 reference clock for dpllip2
15
ref_clk_div_pl
l2
14:11
mfi_pll2[3:0]
0 = reference clock not divided by 2
1 = reference clock divided by 2
0000 = MFI is 5
multiplication factor for dpllip2
If MFI is written a value less than 5, it will be defaulted to 5 0001 = MFI is 5
...
This is also valid for ac scan mode
0101 = MFI is 5
0110 = MFI is 6
0111 = MFI is 7
...
enables double frequency clock for dpllip1
10
dpdck0_2_en
_pll1
0 = double frequency clock disabled
1= double frequency clock enabled
9:7
pdf_pll1[3:1]
see above bits 29:26
pre division factor for dpllip1
6
~pdf_pll1[0]
divides pll1 reference clock for dpllip1
5
ref_clk_div_pl
l1
4:1
mfi_pll1[3:0]
0
SCLKR
0 = reference clock not divided by 2
1 = reference clock divided by 2
0000 = MFI is 5
multiplication factor for dpllip1
If MFI is written a value less than 5, it will be defaulted to 5 0001 = MFI is 5
...
This is also valid for ac scan mode
0101 = MFI is 5
0110 = MFI is 6
0111 = MFI is 7
...
SJC internal register - see SJC guide
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-14
Freescale Semiconductor
8.2.7.2.1
General Purpose Unsecured Control Registers 1,2,3 (Three Registers)
These registers are used to configure WMSG IEEE 1149.1 JTAG for special test or debug modes (see the
test guide for more information). These registers are not secured (accessible in all JTAG security modes).
The bits of these registers are directly connected to SJC outputs.
GPUCR1
TYPE:
RESET:
Addr
$BASE + 0x09
General Purpose Unsecured Control Register
BIT 31
30
29
28
27
26
efuse_
prog_s
upply_
gate
0
0
0
0
ipt_sjc_te
ipt_sjc_lch_mode
st_mode[
[2:0]
1:0]
rw
rw
rw
rw
rw
rw
25
rw
24
rw
23
rw
22
rw
21
20
19
18
17
BIT 16
0
0
0
0
0
0
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
0
0
0
ipt_bi
pg_t
dien
0
0
0
0
usbphy_
source_
sel
0
TYPE:
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-7. General Purpose Unsecured Control Register
Table 8-7. General Purpose Unsecured Control Register 1 Description
Name
31
efuse_prog_supply_gate
30:27
GPUCR1 Bits
Description
Supply gating for eFUSE programing
Settings
0 = fuse programing supply voltage is
gated off to the efuse module
1 = allow fuse programing
reserved
26:25
ipt_sjc_test_mode[1:0]
These bits determine the type of burn_in mode
00 = BI_BIST
01 = BI_LCH_ALL
24:22
ipt_sjc_lch_mode[2:0]
Long Chain configuration
000 = ALL_LONCHAIN
001 = ARM_LONG_CHAIN
010 = APU_LONG_CHAIN
100 = MIXES_LONG_CHAIN
101 = BIPG_ONLY_LONG_CHAIN
110 = NO_LONG_CHAIN
21:11
GPUCR1 Bits
reserved
6
ipt_bipg_tdien
This bit enables tdi for BURN IN mode
5:2
GPUCR1 Bits
reserved
0 = tdi not enabled in BURN IN mode
1 = tdi enabled in BURN IN mode
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-15
Table 8-7. General Purpose Unsecured Control Register 1 Description
Name
Description
1
usbphy_source_sel
Selects USBPHY input source
0
GPUCR1 Bits
0 = USBOH3
1 = external source through gpio
reserved
GPUCR2
BIT 31
Settings
Addr
$BASE + 0x0A
General Purpose Unsecured Control Register 2
30
29
28
27
init_
peri
init_ssi_ap
ph_
m_clk_sel
clk_
sel
26
25
~init
_pe
riph
_ap
m_s
el[1]
init_
peri
ph_
ap
m_s
el[0]
24
23
22
21
20
19
18
17
BIT 16
~init_
~ini
~init_
init_axi_ ~init_axi
emi_
t_nf
init_emi_slo axi_b
init_nfc_po
b_podf[ _b_podf
slow
c_p
w_podf[1:0] _pod
df[1:0]
[0]
1]
_pod
odf[
f[2]
f[2]
2]
0
0
TYPE:
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
~ini
~init
init_
t_ip
_ah
init_axi
init_ahb_p ipg_
~init_axi_a_
g_p
b_p
_a_po
odf[1:0] pod
podf[1:0]
odf[
odf[
df[2]
f[1]
0]
2]
~init
init_p ~init_
init_perc ~init_per
_per
erclk percl init_perclk_pred2[2:
lk_pred1 clk_pred
clk_
0]
_pod k_po
1[0]
[1]
podf
f[1] df[0]
[2]
TYPE:
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-8. General Purpose Unsecured Control Register 2
Table 8-8. General Purpose Unsecured Control Register 2 Description
Name
31:30
GPUCR2 Bits
29:0
Description
Settings
reserved
These bits connected to CCM (clock manager). They
define initialization values to various clock MUX selects
and clock dividers, thus defining initial system clocks
frequencies. See CCM guide for more details.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-16
Freescale Semiconductor
GPUCR3
Addr
$BASE + 0x0B
General Purpose Unsecured Control Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE:
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
0
0
eim_
arm_cl
sma
d15_ en_t
k_off_
rt_b
alt7_ ester
on_lp
ypa
hard _cntl
m
ss
_en
0
17
BIT 16
sjc_ipt_i
sjc_inter
o_tail_b
rupt
ypass
emi_
axi_a
sjc_
ahb_
slow
sjc_
sjc_
_clk_
sr_
sjc_
sjc_d sjc_d clk_b
_clk_
sr_f
dse
bypa
slo
sre
se1
se0 ypas
bypa
ast
_en
ss
w
s
ss
TYPE:
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-9. General Purpose Unsecured Control Register 3
Table 8-9. General Purpose Unsecured Control Register 3 Description
Name
31:18
GPUCR3 Bits
Description
Reserved
Bypasses the FF at the output to the BGA contact
17
sjc_ipt_io_tail_bypa
ss
16
sjc_interrupt
15
arm_clk_off_on_lp
m
Settings
—
0 = Flip flop at BGA contact output not
bypassed
1 = Flip flop at BGA contact output bypassed
This interrupt allows the system to exit stop mode while the —
chip is in debug mode
Gates arm clock
alt7_hard_en for IOMUX cell EIM_D15
14
eim_d15_alt7_hard
_en
0 = ARM clock not gated
1 = ARM clock gated
0 = EIM_D15 BGA contact is not hard_en in
alt7
1 = EIM_D15 BGA contact is hard_en in alt7
13
en_tester_cntl
Allows tester to receive determinism of reset seq
0 = Tester cannot receive determinism of
reset sequence
1 = Tester receives determinism of reset
sequence
12
smart_bypass
Memory repair bypass during POR - functional mode
0 = Memory Repair is not bypassed
1 = Memory Repair is bypassed
Reserved
—
sjc slew rate controller for IOMUXC
0 = Slow slew rate
1 = Fast slew rate
sjc slew rate fast for IORING - this bit must be in
coordination with sjc_sre
0 = Fast slew rate not enabled
1 = Fast slew rate enabled
11
GPUCR3 Bit
10
sjc_sre
9
sjc_sr_fast
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-17
Table 8-9. General Purpose Unsecured Control Register 3 Description (continued)
Name
Description
Settings
8
sjc_sr_slow
sjc slew rate slow for IORING - this bit must be in
coordination with sjc_sre
0 = Slow slew rate not enabled
1 = Slow slew rate enabled
7
sjc_dse_en
sjc BGA contact strength enable
0 = Drive Strength value does not come from
SJC
1= Drive Strength value comes from SJC
6
sjc_dse1
sjc BGA contact strength
5
sjc_dse0
sjc BGA contact strength
00 = Low Drive Strength
01 = Medium Drive Strength
10 = High Drive Strength
11 = Max Drive Strength
4
ahb_clk_bypass
Use bypass clock for AHB root in CCM
Use bypass clock for EMI_SLOW root in CCM
3
emi_slow_clk_bypa
ss
2
axi_a_clk_bypass
1:0
GPUCR3 Bits
8.2.7.3
0 = regular
1 = bypass from BGA contact
0 = regular
1 = bypass from BGA contact
Use bypass clock for AXI_A root in CCM
0 = regular
1 = bypass from BGA contact
Reserved
—
Product ID and JTAG ID
i.MX51 PROD_ID = 11110010 and JTAG_ID = 0x0190_C01D. Product revision (hw_rev[7:4] in IIM)
is = 4’b0000 accordingly.
8.3
CoreSight Design Kit
The i.MX51 includes an ARM CoreSight component for multicore debug and trace solution. CoreSight
component can be found in the following hierarchy levels: ARM core, ARM platform, and top level.
• ARM core—include the following CoreSight components: ETM, CTI0
• ARM platform—include the following CoreSight components: ETB, ATB Replicator, CTI1, CTM
• Top level—include the following CoreSight components: DAP, CTI2, CTI3, TPIU
8.3.1
Memory Map and Register Definition
Each CSDK component has a 4 Kbyte location block in the CoreSight memory map. The base address of
the CoreSight location block is not fixed but the address offsets are fixed. Each CSDK component has a
4-Kbyte memory map, that is, 1 Kbyte words.
Components connected to the DAP internal bus appear as part of a memory mapped structure with parallel
address and two data buses, read data and write data. The bus master, JTAG-DP, uses normal bus
transactions to control the various APs, in this structure the slaves. The JTAG-DP reads and writes
registers within this bus.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-18
Freescale Semiconductor
8.3.2
CoreSight Clock Enable
By default the CoreSight component clocks are enabled when the system exists from reset with all clocks
enabled. The CoreSight clocks’ gating is controlled by programmable CCM registers and DBGEN. The
CCM allows control of each CoreSight component separately (by default) and the DBGEN controls all
debug clocks. DBGEN is raised when detecting activity on JTAG ports (TMS) and descend on reset (by
dap_sys) or controlled by ARM. Only if both CCM registers bits and DBGEN are high the clock will be
propagate to CoreSight component.
8.3.3
CoreSight Debug Access Port (DAP) and DAP_SYS
ARM’s Debug Access Port (DAP) has several functions. DAP_SYS is a wrapper around DAP and is the
FSL block that is actually instantiated in a design (DAP is contained within DAP_SYS). The following list
summarizes the features provided by DAP_SYS.
• Enables debug-related communication between various parts of the system
— It is a modular block.
— It has slave-side support for JTAG and APB (ARM Peripheral Bus) protocols.
— The Debug master can access many debug resources in real time without having to halt the
core.
— It can enable system access to anything connected to the Debug-APB via the APB multiplexor.
• ROM Table provides a list of memory locations of CoreSight components connected to the Debug
APB. Visible from both tools and system access.
• AHB to APB gasket to translate System AHB accesses to APB (input as system APB to the DAP).
• APB Decode to issue select signals to CoreSight components on APB, and handle the PSLVERR
and PREADY signals from the components to the DAP.
• AHB-Lite to AHB converter, to translate DAP’s AHB-lite accesses to system’s AHB protocol.
Debug and Reset logic generate DBGEN signal and reset signals. The CoreSight components that reside
on the Debug-APB include all Embedded Cross Trigger blocks, the ETM, and the ETB.
8.3.4
Embedded Cross Trigger (ECT)
System events, such as a debug request, a core entering or exiting debug mode, the occurrence of a
breakpoint or watchpoint, the occurrence of a particular error, the state of a buffer, etc., can be useful or
even essential for debugging or profiling system performance. Whatever the source of the event, the
embedded cross trigger implements a flexible, programmable mechanism to transport these events from a
source to one or multiple destinations. This includes handling handshake requirements with both the
source and the destination as needed and synchronization of signals from different clock domains. The end
result is that events of interest that occur in one domain, such as in the Cortex-A8 domain, can be
recognized and responded to be a destination domain, such as the SDMA.
The i.MX51 uses the CoreSight ECT (provided by ARM as part of their full CoreSight Debug Support
package) and a custom wrapper to accommodate the various necessary interface scenarios. The ECT (as
delivered by ARM) consists of two major blocks—a central Cross Trigger Matrix (CTM) and a Cross
Trigger Interface (CTI) block. A Freescale-custom wrapper is added to the CTI to accommodate a variety
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-19
of different input and output interface scenarios. The wrapped CTI is called the Extended CTI and is
configured on a signal by signal basis with port tie-off’s.
i.MX51’s ECT architecture consists of a single CTM and three wrapped CTI’s covering three basic groups
of functionality as follows:
• CTI0 is in the ARM Cortex A8 core.
• CTI1 is in the Cortex-A8 core platform, with two triggers in and two triggers out used by the
platform and the others by the device peripherals.
• CTI2 is in the SOC level and is SDMA.
• CTI3 is in the SOC level and is used by MCU peripherals (IPU, GPU, VPU).
A detailed CTI pin assignment can be found in on page 8-21.
Figure 8-10 is a simple illustration of the relationship between the two processor domains, the SJC and
peripherals, and the ARM CoreSight DAP. APB is an AMBA bus used for debugging. It defines what
debug and trace components are required and how they are connected. The DAP is the Debug-APB master
for the following debug units: ETM, ETB, TPIU, and the ARM Cortex A8 debug unit, which are four CTI
blocks. The Debug-APB bus differs from system-level APBs in that it can be directly accessed via JTAG
as well as from the ARM core. Module selects for each slave module on the Debug-APB are generated by
the DAP_SYS.
APB
SJC, Various
Peripherals
Debug-APB
EMBEDDED
CROSS-TRIGGER
TrigIO
TrigIO
TrigIO
ARM
DAP
ETM
System-APB
SDMA
Cortex-A8
OnCE
TDI
TDO
JTAG Interface
ICE
TDI
TDI
TDO
TDO
JTAG Interface
TDI
TDO
JTAG Interface
Figure 8-10. Embedded Cross Trigger Topology
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-20
Freescale Semiconductor
Figure 8-11 illustrates the connectivity between the CTM and CTIO components of the CoreSight ECT.
Tiger
Cortex-A8
Chan in/out
8
Trigger Out Trigger In
CTI0
Chan in/out
4
4
4
CTI3
Trigger In Trigger Out
8
IPU, GPU, VPU
8
8
4
4
4
Chan in/out
CTI1
Trigger Out Trigger In
2
2
Chan in/out
4
CTI2
Trigger In Trigger Out
4
CTM
SDMA
8
8
6
6
IOMUX, EPIT
Figure 8-11. Embedded Cross Trigger - Basic Architecture
8.3.4.1
CoreSight CTM
The CTM (Cross Trigger Matrix) is provided by ARM. The CTM is a relatively simple block with no
programmability. On i.MX51, it is configured to have four input and four output channels. Whatever
comes in on an input channel is routed to all corresponding output channels. For instance, if a trigger input
comes in on input channel 0 from CTI0, it is routed to output channel 0 to CTI1, CTI2, and CTI3. All
selection of drivers and receivers for an event is done in the individual CTI blocks.
The final feature provided by the CTM is handshake with each CTI. This insures that as trigger signals
cross different clock domain boundaries, they will not be lost due to slower downstream sampling
frequencies. It is a simple mechanism in which a CTI holds an output until it receives the
acknowledgement from the CTM. Handshake is also implemented in the reverse direction, insuring that a
trigger signal propagating from the CTM to a CTI is not missed by the CTI.
8.3.4.2
CoreSight CTI
The CTI (Cross Trigger Interface) is also provided by ARM. A summary description of the CTI is provided
here, but please refer to ARM documentation for detailed information. As mentioned earlier, there are
three CTIs. Each of these has eight trigger inputs and eight trigger outputs that connect to logic in the
domain to be debugged or profiled. Each CTI also includes a 4-channel interface to the CTM (four inputs
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-21
and four outputs). The CTIs are wrapped with additional logic to from the Extended CTI, which is
described in the next section.
“
Table 8-10. CTI 1 Input Assignments
Trigger
input
Debug
Resource
Name
0
1
Clock1
Channel Function
SYNC
(dbg_atclk)
Active
ack
TBD
lpcg_ahb_clk
_tzic
Configured interrupt
No
High
No
TBD
lpcg_ahb_clk
_tzic
Configured interrupt
No
High
No
—
TRACING
—
—
—
2–3
1
4
TBD
lpcg_ahb_clk
_tzic
Configured interrupt
No
High
No
5
TBD
lpcg_ahb_clk
_tzic
Configured interrupt
No
High
No
6
TBD
lpcg_ahb_clk
_tzic
Configured interrupt
No
High
No
7
cti_in[7]
—
Debug
—
—
Yes
Comment
ARM
IOMUX
The “Clocks” column specifies the associated clock that needs to be running for the event to propagate.
“
Table 8-11. CTI 1 Output Assignments
1
Trigger
Output
Debug Resource
Name
Clock1
Channel
Function
SYNC
(dbg_atclk)
0
intin_b
lpcg_ahb_clk_tzic
General Purpose
No
—
No
Allows creating
interrupts
1
intin_b
lpcg_ahb_clk_tzic
General Purpose
No
—
No
Allows creating
interrupts
2
intin_b
lpcg_ahb_clk_tzic
General Purpose
No
—
No
Allows creating
interrupts
3
intin_b
lpcg_ahb_clk_tzic
General Purpose
No
—
No
Allows creating
interrupts
4–5
—
arm_clk
—
—
—
—
ARM
6
cti_out[6]
—
Debug
No
—
—
IOMUX
7
cti_out[7]
—
Debug
No
—
—
IOMUX
Active ack
Comment
The “Clocks” column specifies the associated clock which need to be running for the event to propagate.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-22
Freescale Semiconductor
Table 8-12. CTI 2 Input Assignments
Debug Resource
Name
Clock1
0
debug_mode
ipg_clk_spba
Debug
Acknowledge
1
debug_core_run
ipg_clk_spba
2
evt_chn_lines[0]
3
1
Active
ack
Comment
Yes
High
No
SDMA
debug
Yes
High
No
SDMA
ipg_clk_spba
debug
Yes
High
No
SDMA
evt_chn_lines[1]
ipg_clk_spba
debug
Yes
High
No
SDMA
4
evt_chn_lines[2]
ipg_clk_spba
debug
Yes
High
No
SDMA
5
req_ma
ipg_clk_spba
debug
Yes
High
No
SPBA
6
req_mb
ipg_clk_spba
debug
Yes
High
No
SPBA
7
req_mc
ipg_clk_spba
debug
Yes
High
No
SPBA
The “Clocks” column specifies the associated clock which need to be running for the event to propagate.
“
1
SYNC
Channel Function (debug_apb_clk)
Trigger
Input
Table 8-13. CTI 2 Output Assignments
Trigger
Input
Debug Resource
Name
Clock1
0
events[31]
1
Channel
Function
SYNC
(debug_apb_clk)
Active
ack
Comment
ipg_clk_sdma
Yes
High
No
SDMA
sdma_dreq_i
ipg_clk_sdma
Yes
High
No
SDMA
2
FLUSHIN
lpcg_debug_clk_tpi
u
No
High
Yes
TPIU,
FLUSHINACK
3
TRIGIN
lpcg_debug_clk_tpi
u
No
High
Yes
TPIU, TRIGINACK
4
system_debug
GND/tck
Yes
High
No
SJC
5
emi_spare_ports_in[0]
GND
Yes
High
No
EMI
6
Not used
7
Not used
The “Clocks” column specifies the associated clock which need to be running for the event to propagate.
“
Table 8-14. CTI 3 Input Assignments
Trigger
Input
Debug Resource
Name
Clock1
0
ipi_int_epit_oc
ipg_clk_epit1
1
ipi_int_ipu_func
2
3
Channel
Function
SYNC
(debug_apb_clk Active
)
ack
Comment
TRACING
Yes
High
No
EPIT
hsp_clk
debug
Yes
High
No
IPU general interrupt
ipi_int_ipu_err
hsp_clk
debug
Yes
High
No
IPU error interrupt
—
—
—
—
—
—
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-23
Table 8-14. CTI 3 Input Assignments (continued)
1
Channel
Function
SYNC
(debug_apb_clk Active
)
Trigger
Input
Debug Resource
Name
Clock1
4
gpu_use_bufid
ack_gpu
debug
Yes
5
gpu_int_b
ack_gpu
debug
6
vpu_idle
cclk
7
vpu_underrun
cclk
ack
Comment
High
No
GPU - OR output of the
bus 3 bits
Yes
Low
No
gpu genral perpose
interrupt
Trace
Yes
High
No
VPU Idle
debug
Yes
High
No
VPU Underrun
The “Clocks” column specifies the associated clock which need to be running for the event to propagate.
Table 8-15. CTI 3 Output Assignments
Trigger
input
Debug
Resource
Name
Clock
SYNC
Channel Function (debug_apb_clk
)
0
—
—
—
1
—
—
2
—
3
Active
ack
—
—
—
Not used
—
—
—
—
Not used
—
—
—
—
—
Not used
—
—
—
—
—
—
Not used
4
—
—
—
—
—
—
Not used
6
—
—
—
—
—
—
Not used
7
—
—
—
—
—
—
Not used
8.3.4.3
Comment
Extended CTI (CTI Wrapper)
This wrapper consists of additional logic for each input and each output trigger to implement several
features that can be selected or enabled with hard tie-off’s on the module’s boundary. It is combined with
ARM’s CTI block to form the CTI_Extended block. A summary of the extended input features
implemented by logic in the wrapper is as follows:
• Invert the incoming signal
— The ARM CTI assumes all inputs are active-high. An active-low input must first be inverted
before going into the ARM CTI
• Sample the incoming trigger signal with a clock synchronous to the incoming signal
— Samples the incoming trigger with its own clock
• Convert the incoming signal to a pulse
— Used when an input trigger has a long assertion time. Destinations may be sensitive to a long
assertion time and may see it as multiple input triggers.
• Implement holding logic to insure that the ARM CTI captures and acknowledges the incoming
signal. The holding logic clock must be synchronous to the clock that generated the input trigger.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-24
Freescale Semiconductor
•
8.3.5
Provides a synchronized or asynchronous acknowledge signal back to the origin of the trigger.
— If the asynchronous trigger source requires an ACK signal back from the CTI, but a clock from
that source is not available to the CTI, the source must first synchronize the received ACK
before using it in the trigger source logic.
CoreSight Trace Port Interface (TPIU)
The TPIU is one of the CoreSight trace sink components it acts as a bridge between the on-chip trace data
to a data stream that is then driven out the trace port. ATB interface is used by the TPIU accepts trace data
from a trace source, either direct from a trace source or using a Trace Funnel. The TPIU has 32 bit
connected to the chip BGA contact. The APB interface is the programming interface for the TPIU
configuration.
8.4
ARM Cortex A8 Core and Platform
ARM Cortex A8 Debug architecture includes support for TrustZone and CoreSight. The memory-mapped
external debug interface replaces the coprocessor interface defined in the previous version of the Debug
architecture. A full access to the processor debug capability available by ARM Cortex A8 debug register
map through the Advanced Peripheral Bus (APB) slave port. The core includes Processor Debug Unit
allow: stop program execution, examine and alter processor and coprocessor state, examine and alter
memory and input/output peripheral state, and restart the processor core.
8.4.1
ARM Cortex A8 Core Debug Support Features
The ARM Cortex A8 core debug support features are as follows:
• CoreSight Embedded Trace Macro (ETM11)—trace generator for the ARM Cortex A8 core
• Support for a TrustZone-relateyd 3-level debug scheme:
— Debug everywhere
— Debug in Non-Secure privileged and user and Secure user
— Debug in Non-Secure only
• EmbeddedICE-RT logic
— Support for both monitor-mode and halt-mode debugging.
— Core run/halt control, debug status/control
— Breakpoint/watchpoint control
— Core- and memory-mapped resource examination/modification
• Data communication channel between ARM core and host debugger via JTAG
• PMU—Performance Metrics Unit used for system profiling and debug.
• CP15 register for debugging the MMU, I and D L1 cache, and TLB
• EVTMON-L2 Event Monitor—Supports debug and profiling of the ARM’s L2 cache activity
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-25
8.4.2
•
•
•
8.5
Additional Platform Debug Functionality
CoreSight Embedded Trace Buffer (ETB11)—4-Kbyte RAM array to be used for on-chip capture
of trace data output from the ETM11
ATB Replicator to connect the trace data to TPIU (Trace Port Interface) and ETB (Embedded Trace
Buffer).
Debug Visibility—select critical signals routed to the I/O pads as alternate outputs for external
visibility
Smart DMA (SDMA) Core
The SDMA is a dedicated, programmable DMA engine. It is an integration of a 32-bit RISC core and
DMA-specific hardware, and it includes ports for the AP domain and a peripheral domain, along with a
burst-capable port for direct external memory access. The SDMA and its integration in the i.MX51 is
unchanged from previous SOCs.
The main SDMA debug features are as follows:
• OnCEOn Chip Emulator, provides the following capabilities:
— SDMA core control - run/halt/single-step
— SDMA core register/memory-map access
— Event detection, watchpoints, and hardware breakpoints
— Real time buffer and PC trace buffer capability
• Trace buffer
— Contains information to identify the 32 last changes of flow detected during a program
execution
• Context dump
— include information about all the channel dump activity
— Current contents of SDMA RAM
• ROMPATCH
8.5.1
SDMA On Chip Emulation Module (OnCE) Feature Summary
The SDMA debug features are primarily defined by the OnCE portion of its design, which are summarized
as follows:
• Memory And Register Access—dedicated logic enables user-access to SDMA memory and
register locations. These accesses are supported only when the processor is in debug mode.
• Event Detection Unit—watches signals from the data memory bus (DMBus) which is used by the
RISC core to access its RAM, ROM, and memory-mapped registers
• Watchpoints—one output signal is available to watch event matching conditions at the chip level.
Match conditions are defined by programming memory-mapped registers.
• Hardware Breakpoint—a counter is decremented after an event detection. A debug request is sent
to the SDMA core only when the counter reaches the value of zero. It is possible to program the
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-26
Freescale Semiconductor
•
•
•
8.5.2
initial value of the counter or to disable the use of the counter if a debug request must be generated
after each event detection.
Real Time Buffer—The Real Time Buffer Register (RTB) is a single 32-bit memory-mapped
register which can be accessed as a regular memory location during program execution. It is used
to store and retrieve run time information without putting the SDMA in debug mode. Each write
to this register causes an event. This register is, in fact, located in the OnCE. Executing through
JTAG, a buffer command exports the content of this register through the JTAG port.
Core Control (Core Status/Single Stepping)—Commands are provided to monitor and control
processor activity. The commands can halt the core, rerun the core from another address location,
and get processor status.
Trace Buffer—a 32 × 32 buffer that records the last 32 changes of flow during program execution.
The buffer stores data in a modulo fashion (i.e. the 33rd instruction change replaces the 1st).
Captured trace information is retrieved via reads to the Trace Buffer Register.
Other SDMA Debug Functionality
Other SDMA debug functionalisty is as follows:
• Core Trace—basic core trace capability is available through debug visibility functionality only.
ETM/Nexus trace capability does not exist.
• ROM Patch—can be accomplished by manipulating the CHN0ADDR register through JTAG or
via the MCU’s ability to write to SDMA OnCE registers. This must be done right after reset and
before the SDMA core is enabled to begin processing events.
• Additional debug control/status interaction with the SJC module
— SJC-controlled Debug Request
— SJC-readable Debug Acknowledge (in debug mode)
— Debug clock control - allows SJC to force clocks on for debug purposes
— Debug core state (SDMA RISC Core State) - 4 bits accessible from the SJC via JTAG
• Debug Visibility—observable outputs as alternate (programmable) output functions of I/O pins
— Debug Request, Debug Mode
— Debug Yield
— Debug Event Channel[5:0] (indicates requesting event or channel being processed)
— Debug PC [13:0] (for SDMA core trace)
— Debug core state [3:0]
— Debug Real-time Buffer write
— Debug Addr/Data match
— Debug bus error
— Debug bus device
— Debug bus r/w
— Debug Event Channels[7:0]
— Debug Core Run (active when core is running)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-27
8.5.3
Embedded Cross Trigger Interface
Please refer to the Embedded Cross Trigger section of this chapter for detailed information about the
SDMA interface to that subsystem.
8.6
External Memory Interface (EMI)
The second-generation EMI contains an arbitration profiling unit. This can be used to monitor and profile
the dynamic arbitration behavior during operation. Several internal signals would be routed out by EMI
debug unit to give SoC the capability to track the internal logic mainly for the arbitration mechanism and
memory served accesses. In addition, the debug unit gives the ability to profile a master connected to EMI
and get the bus performance of the arbitration.
Signals routed to 51 bit ipp_do_emi_debug bus are routed to the BGA contact.
The Profiling unit includes the following:
•
•
•
•
•
•
•
A register that saves the maximal time that a selected master was pending without getting the bus
(MDSR0)
The maximum value of the dynamic priority which was selected (MDSR0)
Counters to record the number of access that each master performed through each channel
(MDSR2–5)
Counter of the total number of accesses a specific request (or type of request) has accessed the bus
can be fast, slow or intr (MDSR6)
A register that sums of "time for bus" the time it took a specified request (or type of request) to get
the bus (MDSR7)
A register that sums the time it took each access to get the bus (pending time) (MDSR8)
Ability to reset all the counters
The EMI profiling logic includes a START signal, which comes from the ECT. Thus, any definable ECT
condition can be used to initiate profiling.
8.7
Debug Visibility—IOMUX
Certain predefined, internal signals can be viewed at the package pins. The BGA contact logic for most
pins includes an IOMUX, allowing that BGA contact to be shared across multiple functions. Each BGA
contact has a primary function that is selected at reset. The alternate functions, such as displaying the state
of an internal signal for debug purposes, is selected by reprogramming the IOMUX.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-28
Freescale Semiconductor
Table 8-16 shows the debug visibility.
Table 8-16. Debug Visibility
Module
8.8
Signals
SDMA
debug_mode,
debug_bus_error,
debug_bus_device[4:0],
debug_bus_rwb,
debug_matched_dmbus,
debug_rtbuffer_write,
debug_evt_chn_lines[7:0]
EMI
ipp_do_emi_debug[50:0]
IPU
ipu_diagbus[15:0]
GPU
SYS_GC_debug_out[16:0]
TPIU
TRACEDATA[31:0]
MCU Peripherals
This section discusses the following MCU peripherals:
• Section 8.8.1, Image Processing Unit (IPU)”
• Section 8.8.2, Video Processing Unit (VPU)”
• Section 8.8.3, Graphics Processing Unit (GPU)”
8.8.1
Image Processing Unit (IPU)
The IPU include debug unit that allow routing of its signals to the SoC level. The signals muxing to be
routed to top are controlled by DP Debug Control register (DP_DEBUG_CNT) and are connected to 16
bit diagnostic bus (ipu_diagbus). The IPU also include status register (DP_DEBUG_STAT) that can be
used for debug.
The IPU can enter the system into debug mode by the cross trigger system. Three of the IPU signals are
input to ETC: IPU general interrupt, IPU error interrupt, and IPU end of frame. These inputs can trigger
the system to enter debug mode.
More details on signal muxing and IPU debug registers can be found in IPU chapter.
8.8.2
Video Processing Unit (VPU)
The VPU can enter the system into debug mode by the cross trigger system. Three of the VPU signals are
input to ETC: VPU idle, VPU interrupt, and VPU underrun. Those signals can trigger the system to enter
debug mode.
VPU internal register can access the AHB bus for further analysis.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-29
8.8.3
Graphics Processing Unit (GPU)
The GPU supports propagating debug information from the core over a 32-bit wide debug bus. The debug
outputs are directed to only 16 visible ports. GPU includes debug control bus SYS_GC_gpio[15:0] that
selects which debug signals are exposed on the debug out bus GC_SYS_debug_out[31:0].
GPU can enter the system into debug mode by the cross trigger system. Two of the GPU signals are input
to ETC: GPU error interrupt and GPU end of frame. Those signals can trigger the system to enter debug
mode.
8.9
Supported Tools
The i.MX51 supports RealView™ ARM Debugger, the debugger should be connect to i.MX51 from host
by RealView ICE protocol converter.
8.10
Interrupt Visibility
Similar to debug visibility, the i.MX51 includes multiplexors that allow users to view selected internal
interrupts. Up to five pads support this as alternate BGA contact output functions, allowing the user to view
up to five different interrupt sources simultaneously. These five signals also route to ECT inputs, allowing
them to generate ECT trigger events as desired.
8.11
Miscellaneous
This section discusses the SOC-level bus trace and clock/reset/power block interactions.
8.11.1
SOC-level Bus Trace
There is no SOC-level bus trace capability on i.MX51
8.11.2
Clock/Reset/Power
The interactions between the debug system and the system clock, reset, and power control blocks include
enhancements to insure that status of critical system components can be monitored at all times and that a
debugger can insure that all critical clocks and power are enabled when needed. Specifically, a master
signal coming from an SJC control bit and going to the Clock/PLL logic is implemented for each major
clock domain. The same is done for each power domain. Historically, JTAG based operations have not
been possible under certain system conditions. For the i.MX51, the debugger must have the ability to
determine the status of all critical system elements and to override any condition that would prevent the
desired debug resources from operating properly.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
8-30
Freescale Semiconductor
Chapter 9
System Boot
9.1
Introduction
The i.MX51 allows the user to configure a wide variety of boot configurations for both engineering
development and production. The boot ROM logic supports features such as booting from various external
memory devices, support for downloading code through a serial downloader, boot device configuration,
and secure boot. This chapter describes how the boot process works and how to program it.
The boot process begins at Power On Reset (POR). The boot ROM logic reads hardware inputs such as
the boot pins on the IC, eFUSEs, and/or GPIO settings to determine the boot flow behavior of the i.MX51.
The default out-of-reset boot sequence is a High Assurance Boot (HAB) secure boot environment. The
HAB is a combination of hardware and software combined with a PKI (Public Key Infrastructure) protocol
to protect the system from executing unauthorized images or programs. Before the HAB allows the user’s
boot code to execute, the code must be signed by the private key holder, which is then compared with the
public key on i.MX51. The HAB library in the i.MX51 boot ROM also provides a number of API functions
allowing the user to authenticate any defined region and signature at run-time.
For non-secure operations and testing, the i.MX51 also allows the HAB to be bypassed while reading the
internal ROM or using a direct external boot allowing the processor to boot directly from external memory,
as done by traditional microprocessors.
The boot ROM logic also allows the downloading of and the ability to flash new ROM code via a serial
connection. Typically, the serial downloader application is downloaded to internal RAM, which facilitates
the ROM Flash programming. The download uses either a high-speed USB in nonstream mode or a UART
connection.
The boot capabilities can differ substantially depending on the HAB type security configuration being
employed and the other boot configuration settings.
The i.MX51 supports two general configuration environments. Full boot flexibility is supported in the
development (or engineering) configuration but in the production (or secure) configuration significant
limitations on the boot process exist. The remainder of this chapter provides the details about how to
configure and use the boot features of the i.MX51.
9.2
Boot Module Activation
The i.MX51 boot logic affects up to 17 different hardware modules, which are activated and play a vital
role in the boot flow. The processor configures and uses the following modules (listed in alphabetical
order) during the boot process:
• CCM—Clock Control Module
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CSU—Central Security Unit. The Security Control Registers (SCR) of the CSU are set during boot
time by the High Assurance Boot (HAB) code and are locked to prevent further writing.
eCSPI—enhanced Configurable Serial Peripheral Interface
EMI1 (WEIM/NFC/ESDCTL)—External Memory Interface
eSDHC—enhanced Secure Digital Host Controller
HS-I2C—High Speed Inter IC
I2C—Inter IC
IIM—IC Identification Module. The IIM contains the eFUSEs.
IOMUX—I/O Multiplexor allows using the GPIO to override eFUSE boot settings.
PLL—Phase Locked Loop. Also called Digital Phase Locked Loop (DPLL)
RTIC—Run Time Integrity Checker. The RTIC’s purpose is to ensure the integrity of the peripheral
memory contents, protect against unauthorized external memory elements replacement, and assist
with boot authentication.
SAHARA—Symmetric/Asymmetric Hash And Random Accelerator
SCC—Security Controller
SRC—System Reset Controller. The SRTC incorporates a special System State Retention Register
(SSRR) that stores system parameters during system shutdown modes including the value of the
BMOD pins
SRTC—Secure Real Time Clock
UART and USB—used for serial download of new ROM code to Flash the Boot ROM
WDOG—Watchdog Timer
1. Only used for booting from an external memory device using the WEIM, NFC, or eSDCTL.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
9-2
Freescale Semiconductor
9.3
Internal ROM /RAM Memory Map
Figure 9-1 shows the internal ROM/RAM memory map.
Figure 9-1. Internal ROM and RAM Memory Map
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-3
9.4
Boot Modes
The i.MX51 has four boot modes (one is reserved for internal use) that are selected by the two boot mode
contacts on the IC package (BOOT_MODE0/1]). The settings of these two contacts are sampled upon exit
of reset and stored in the BMOD[1:0] field of the SRC Boot Mode Register (SBMR) register in the SRC
(System Reset Controller) module. Connecting the Boot Mode contacts to GND reads as a logic 0. For
logic 1, Freescale recommends tying the contact to NVCC_PER3
The boot modes are: internal, internal boot with fuses, and serial boot via USB/UART. Refer to Table 9-1
for settings.
Table 9-1. Boot Mode Contact Settings
9.4.1
BMOD[1:0]
Boot Type
00
Internal Boot
01
Reserved
10
Internal Boot – ROM Select
11
Serial Downloader
Internal Boot (BMODE = 00)
Internal boot mode is selected by a value of ‘00’ on the BMOD[1:0] pins, at device power up. In this mode
the processor boots from internal ROM. The boot code performs HW initialization, application image
validation using the HAB library, and then jumps to an address derived from the application image. If any
error occurs during internal boot the boot code jumps to the serial downloader. Internal boot mode is the
only mode in which a secure boot of the i.MX51 is possible.
When set to Internal Boot (BMOD[1:0] = 00) the boot flow is controlled by a combination of eFUSE
settings with the option of overriding the fuse setting using GPIO. The selection between these two boot
modes is controlled by the GPIO Boot Select (GPIO_BT_SEL) fuse.
T
•
•
If the GPIO_BT_SEL fuse is blown, all boot options are controlled by the eFUSEs described in
Table 9-2 on page 9-5. The boot ROM software may read the value of BMOD[1:0] in theSBMR,
or read the eFUSEs directly via the IIM module.
If the GPIO_BT_SEL fuse is intact, the boot options are determined by the settings of the SBMR
register. Some fuse options can be overridden in this mode. The fuses that can be overridden in
GPIO mode are indicated by a YES in the GPIO column. See Table 9-4 on page 9-10 for details
about the boot GPIO pins. In this mode the options’ values can only be read from the SBMR
register.
The use of GPIO overrides is intended for development board work because those pads are used for other
purposes in normal mode. Freescale recommends controlling the boot configuration by eFUSEs
(GPIO_BT_SEL fuse blown) for deployed products and reserve the use of the GPIO mode
(GPIO_BT_SEL fuse intact) for testing purposes. On production board GPIOs are not required—the
customer can burn the fuses and not use the GPIO signals.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
9-4
Freescale Semiconductor
9.4.2
Internal Boot—ROM Select (BMODE = 10)
Internal boot (from only boot fuses) is selected by driving value of ‘10’ on the BOOT_MODE[1:0] pins,
at device power up. This mode is equivalent to the Internal boot BOOT_MODE[1:0] = 00, with the only
difference being that GPIO boot override pins are ignored, regardless of the BT_GPIO_SEL setting. The
boot program only uses the boot eFUSE settings. This allows the user to burn fuses on the closed
production device, with no external muxes on BOOT_MODE, pull ups/pull downs, and with no
uncertainty that the serial downloader will be invoked by unknown boot pin values during the initial boot
of the product device.
If set to Internal Boot ROM Select, the boot flow can be redirected if the BT_BLANK fuse is not blown
(indicating that the ROM has not yet been programmed). This causes the boot flow to jump to the serial
downloader. If the BT_BLANK fuse is blown the boot flow is normal and controlled by the eFUSE
settings.
The first time a boad is used, when no fuses have been burnt yet, the device connected to BT GPIO pads
can drive some values that will be incorrectly interpreted by ROM code. In such case the ROM code may
try performing boot from not existing device. This may cause electrical/logic violation on some pads.
Internal Mode—ROM Select (BMOD = 10) solves this problem. The first time the BT_BLANK fuse is
encountered it is not burnt and therefore the ROM code jumps to the serial downloader. The next time
BT_BLANK is burnt and therefore ROM code will perform internal boot according to the fuse settings.
The user can set BOOT_MODE[1:0] = 10 on a production device and burn fuses on the same device (by
falling back to serial downloader), without changing value of BOOT_MODE[1:0] or pull ups/pull downs
on the boot pins.
For cleaner jumping to serial downloader during initial fuse burning, the BT_BLANK fuse was
introduced. If BOOT_MODE[1:0] = 10 and BT_BLANK = 0, then the ROM code jumps directly to the
serial downloader, without trying other interfaces. BT_BLANK is designed to be blown by the user during
initial fuse burning.
Table 9-2 shows the boot eFUSE descriptions.
Table 9-2. Boot eFUSE Descriptions
Fuse
Config
DIR_BT_DIS
OEM
BT_MEM_CTL[1:0]
OEM
Definition
Direct External Memory Boot
Disabled
Boot Memory Control Type
used to select one of the following:
• EIM (NOR, OneNAND)
• NAND flash
• Expansion devices such as
SD/MMC or EEPROM.
GPIO1
NA
Yes
Settings2
0 Direct boot to external memory is
allowed
1 Direct boot to external memory is not
allowed
00
01
10
11
WEIM
NAND Flash
Reserved
Expansion Device (SD/MMC, support
high storage, EEPROMs. The fuse
BT_MEM_TYPE[1:0] defines
Expansion Device settings.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-5
Table 9-2. Boot eFUSE Descriptions (continued)
Fuse
Config
Definition
GPIO1
BT_PAGE_SIZE[1:0]
OEM
NAND Flash Page Size. This field is
used in conjunction with the
BT_MEM_CTL[1:0] setting to set
page size of NAND flash device.3
Note: BT_MEM_CTL must be set
to NAND Flash for these
settings to be used.
Yes
00
01
10
11
BT_SPARE_SIZE
OEM
Specifies the size of spare bytes for
4Kbyte page size NAND Flash
devices.
Note: The spare size setting is only
applicable when used with
4Kbyte page size devices.
This fuse can also be used as a
“fast boot” mode indication for use
with eSD 2.10 protocol devices.
Yes
0 128 bytes spare (Samsung)
1 218 bytes spare (Micron, Toshiba)
NAND/NOR Bus Width.
Yes
BT_BUS_WIDTH[1:0]
OEM
Settings2
512 bytes
2 Kbytes
4 Kbytes
Reserved
If the bootable device is SD then:
0 “FAST_BOOT” bit 29 in ACMD41
argument is 0
1 “FAST_BOOT” bit 29 in ACMD41
argument is 1
Note: OneNAND devices can only
use a 16-bit bus width,
BT_MEM_CTL[1:0] = NAND Flash
00 8-bit
01 16-bit
BT_MEM_CTL[1:0] = WEIM (NOR)
00 16-bit data bus
01 32-bit data bus
BT_MEM_CTL[1:0] = Expansion Device
(SPI)
00 2-Address word SPI device (16-bit)
01 3-Address word SPI device (24-bit)
BT_MEM_TYPE[1:0]
OEM
Boot Memory Type.
Selects memory card options.
Available settings are defined by
the memory type selected using
BT_MEM_CTL
Yes
BT_MEM_CTL = 00 (WEIM)
00 NOR
01 Reserved
10 OneNand
11 Reserved
BT_MEM_CTL = 01 (NAND Flash)
00 3 address cycles
01 4 address cycles
10 5 address cycles
11 reserved
BT_MEM_CTL = 11 (Expansion Card)
00 SD/MMC/eMMC/eSD
01 Reserved
10 Serial ROM via I2C
11 Serial ROM via SPI
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
9-6
Freescale Semiconductor
Table 9-2. Boot eFUSE Descriptions (continued)
Fuse
Config
Definition
GPIO1
BT_SRC[1:0]
OEM
Boot Source - This fuse selects one
of the following Expansion card
device types.
• eSDHC 1/2/3/4
• I2C1/2, HS-I2C
• CSPI, eCSPI1/2
Yes
Settings2
BT_MEM_TYPE = 00
(SD/MMC/eMMC/eSD)
00 eSDHC-1
01 eSDHC-2
10 eSDHC-34
11 eSDHC-42
BT_MEM_TYPE = 10 (Serial ROM via I2C)
00 I2C-1
01 I2C-2
10 HS-I2C
11 Reserved
Note: BT_MEM_CTL[1:0] must be
set to 11 (Expansion Card
Device) to use these settings
BT_MEM_TYPE = 11 (Serial ROM via SPI)
00 eCSPI1
01 eCSPI2
10 CSPI
11 Reserved
BT_WEIM_MUXED[1:0]
OEM
Selects WEIM muxed mode.
Yes
BT_MEM_CTL[1:0]=00 (WEIM [NOR])
00 Not muxed, not multiplexed with NAND,
16-bit data (high half) NOR interface.
01 Muxed, not multiplexed with NAND,
16-bit data (low half) NOR interface.
10 muxed, multiplexed with NAND data
bus, 16-bit data (low half) NOR
interface.
11 Muxed, multiplexed with NAND data
bus, 32-bit data NOR interface.
BT_UART_SRC[1:0]
OEM
Selects the specific UART controller
used for serial downloads.
Yes
00
01
10
11
BT_MLC_SEL
OEM
SLC/MLC NAND device select or
FAST BOOT enable/disabled for
eMMC device
Yes
If BT_MEM_CTL[1:0] = NAND
0 SLC NAND device
1 MLC NAND device
If all of the following conditions are met:
• BT_MEM_CTL[1:0] = Expansion Device
• BT_MEM_TYPE[1:0] = 00
• The bootable device is an MMC
0
1
UART1
UART2
UART3
Reserved
eMMC fast boot mode disabled.
eMMC fast boot mode enabled
BT_EEPROM_CFG
OEM
Selects whether EEPROM device is
used for loading configuration DCD
data prior to booting from other
devices (not applicable when using
EEPROM as boot device)
Yes
0 Use EEPROM DCD
1 Do not use EEPROM DCD
BT_USB_SRC
OEM
USB PHY selection is based on this
fuse setting.
Yes
0 USB-OTG internal UTMI PHY
1 USB-OTG external ULPI PHY
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-7
Table 9-2. Boot eFUSE Descriptions (continued)
Fuse
Config
Definition
GPIO1
OSC_FREQ_SEL[1:0]
OEM
CKIH Frequency Select. It is used
by boot code for PLL programming.
Yes
00
01
10
11
Freescale GPIO Boot Select. Determines,
whether the boot settings indicated
by a Yes in the GPIO column are
controlled by GPIO pins or eFUSE
settings in the IIM:
Note: This feature requires BMOD
= 00 to operate.
NA
0 Select bits of SBMR are updated by
GPIO.
1 Specific bits of SBMR are updated by IIM
eFUSE settings.
GPIO_BT_SEL
Settings2
CKIH
CKIH
CKIH
CKIH
Frequency is 26 MHz
Frequency is 19.2 MHz
Frequency is 27 MHz
Frequency is 24 MHz
HAB_TYPE[2:0]
OEM
Security Types as defined in
Section 9.4
Note: In Engineering mode if CSF
and SRK is not provided it
must set to NULL in
application header.
NA
001 Engineering (allows any code to be
flashed and executed, even if it has no
valid signature)
100 Security Disabled (For internal/testing
use)
OthersProduction (Security On)
SRK_HASH[255:0]
OEM
Most significant byte of 256-bit hash
value of super root key
(SRK_HASH)
NA
Settings vary –used by HAB
HAB_CUS[7:0]
OEM
HAB Customer Code — Selects
customer code, as input to HAB.
NA
Settings vary –used by HAB
DIE-X-CORDINATE[7:0] Freescale Device Unique ID, 64-bit UID.
DIE-Y-CORDINATE[7:0]
WAFER_NO[4:0]
LOT_NO_ENC[42:40]
LOT_NO_ENC[39:32]
LOT_NO_ENC[31:24]
LOT_NO_ENC[23:16]
LOT_NO_ENC[15:8]
LOT_NO_ENC[7:0]
NA
Settings vary –used by HAB
SRTC_SECMODE[1:0]
OEM
Security Mode for Secure RTC.
Determines the level of security of
the Secure Real Time Clock
(SRTC) module
No
00
01
10
11
BT_LPB_FREQ[2:0]
OEM
Low-Power Boot Mode (LPBM)
ARM core frequency.
Yes
000
001
010
011
100
101
110
111
BT_BLANK
OEM
Indicates that the boot area has not
yet been burned.
Note: This fuse is only read when
BOOT_MODE[1:0]=10
No
0 BOOT area is unprogrammed. Boot flow
jumps to serial downloader.
1 BOOT area is programmed. Regular
boot flow is performed.
Low Security
Medium Security
High Security
Reserved
192 MHz (Default - out of reset),
133 Mhz
55.33 MHz
200 MHz
220 MHz
166 MHz
266 MHz
Normal boot frequency (400 MHz)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
9-8
Freescale Semiconductor
Table 9-2. Boot eFUSE Descriptions (continued)
Fuse
Config
Definition
GPIO1
Settings2
MMU_EN
OEM
MMU/d-cache enable bit used by
boot ROM for fast HAB processing
No
0 MMU/d-cache is disabled by ROM
during the boot
1 MMU/d-cache is enabled by ROM
during the boot
BT_LPB[1:0]
OEM
Options for Low-Power Boot Mode
(LPBM).
No
00 LPBM disabled
01 Generic PMIC and one GPIO input
(Low battery)
10 Generic PMIC and two GPIO inputs
(Low battery and Charger detect)
11 Atlas AP Power Management IC.
1
Setting can be overridden by GPIO settings when GPIO_BT_SEL fuse is intact. See Table 9-4 for corresponding GPIO pin.
0 = intact fuse and 1= blown fuse
3 The Page-Per-Block settings may not always exhibit a “one to one” relationship to the block size; however, most devices exhibit
the relationships listed in Table 9-3:
4 eMMC4.3 fastboot is supported
2
Table 9-3. Page-Per-Block Relationships
9.4.2.1
Page Size
Page-per-Block
512 Bytes
32
2 Kbytes SLC
64
2 Kbytes MLC
128
4 Kbytes
128
GPIO Boot Overrides
Table 9-4 on page 9-10 provides a listing of GPIO boot overrides. These input pins are sampled at boot
and can be used to override corresponding fuse values, depending on the setting of the GPIO_BT_SEL
fuse. The boot GPIO override options are only in effect when GPIO_BT_SEL is ‘0’ (intact fuse) and
BOOTM[1:] = 10.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-9
Table 9-4. GPIO Override Contact Assignments
Contact
DISP1_DAT[21:20]
Details
BT_MEM_TYPE[1:0]
DISP1_DAT[11,23,22]
GPIO Boot pin
BT_WEIM_MUXED[1:0] overrides fuse
settings if the
BT_PAGE_SIZE[1:0]
following conditions
BT_BUS_WIDTH
apply:
• Internal Boot
BT_MEM_CTL[1:0]
mode
(BMODE[0:1]=00)
BT_MLC_SEL
• GPIO_BT_SEL =
BT_LPB_FREQ[2:0]
0
DISP1_DAT[10]
BT_SPARE_SIZE
DISP1_DAT[9:8]
BT_SRC[1:0]
DISP1_DAT[7]
BT_EEPROM_CFG
DISP1_DAT[6]
BT_USB_SRC
EIM_A[23]
BT_HPN_EN
EIM_A[21:20]
BT_UART_SRC[1:0]
EIM_A[19:18]
BT_LPB[1:0]
EIM_A[17:16]
OSC_FREQ_SEL[1:0]
DISP1_DAT[19:18]
DISP1_DAT[17:16]
DISP1_DAT[15]
DISP1_DAT[14:13]
DISP1_DAT[12]
9.4.3
eFUSE
Serial Downloader (BMOD[1:0] = 11)
The serial downloader is invoked if the external Flash device is not programmed, when a failure is
encountered during the boot flow process or any of the following conditions are met:
• BMOD[1:0] = 11 (serial downloader mode)
• BMOD[1:0] = 10 (internal boot with fuses) and the eFUSE BT_BLANK = 0
• BMOD[1:0] = 10 (internal boot with fuses) but the fuses are not set properly.
• BMOD[1:0] = 00 or 10 (internal or internal boot with fuses) and there is not a valid image in the
Flash device
• Security hardware failure
• Runtime exception occurs
• Error returned by the HAB functions while in production mode. Errors are ignored in engineering
mode)
To determine the active serial port, either UART or USB, the processor ROM program polls the UART
and USB status register for approximately 32 seconds. If there is no activity on either port within the
predefined polling time, the ROM program powers down the IC using WDOG. When the serial
downloader is active, the WDOG is serviced periodically. If the communication between the serial host
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
9-10
Freescale Semiconductor
and the i.MX51 hangs for more than 32 seconds or the processor enters an endless loop, the WDOG
expires and powers down the device.
NOTE
For detailed information about the boot module contact your Freescale
representative.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-11
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
9-12
Freescale Semiconductor
Chapter 10
Multimedia
10.1
Video Subsystem
The video subsystem includes the following dedicated modules:
• Video Processing Unit (VPU): a multi-standard video
• Image Processing Unit (IPU): providing connectivity to displays, related processing,
synchronization, and control
• TV encoder (TVE) bridge: providing optional translation from the digital display interface
supported by the IPU to SDTV analog and some HDTV interfaces
These modules are connected to the other parts of the system as follows:
• IPU has two display ports, used to connect to relevant external devices.
• The VPU and IPU have a master AXI port, providing access to system memory. The IPU provides
different IDs for accesses related to real-time and non-real-time flows (real-time flows being screen
refresh) to allow allocating a higher priority to the real-time flows, reducing the risk of their
starvation.
• All modules have a host interface, used to configure and control them (by the ARM MCU or the
SDMA). For the VPU and the TVE, this is a slave IP port. For the IPU, this is a slave AHB port.
• The slave AHB port of the IPU also provides direct access from the ARM MCU and SDMA to an
external display controller or graphics accelerator, connected to the display port.
10.1.1
Image Processing Unit (IPU)
Table 10-1 shows the IPU IP parametric table.
Table 10-1. IPU IP Parametric Table
Name
IPU
Function
Connectivity to displays; related processing; synchronization and control
External I/O Pins
Parallel Display port:
32 bit data, ~18 clocks and controls.
Regular CMOS IO type, 133 MHz max.
May be also connected to the TVE internal connectivity bridge.
Notes:
This is the pinout of the IPU module
At chip level, some of the pins are muxed
and some are omitted.
Additional GPIO pins are required to
construct the connection. This is not
included in this list.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
10-1
Table 10-1. IPU IP Parametric Table (continued)
Name
IPU
SoC Buses
AXI master—for accessing the memory
AHB slave—for programming, control and direct access of the MCU to the display
Interrupts
Two interrupts: functional and error
DMA Requests
Includes an integral DMA controller, with an AXI master port
Also one DMA request to the SDMA
Number of instantiations
1
Clock sources and range
HSP_CLK—Internal high-speed processing clock: up to 133 MHz
DI_CLK—Display interface clock: up to 80 MHz
The goal of the IPU is to provide comprehensive support for the flow of data to a display device. This
support covers all aspects of these activities:
• Connectivity to relevant devices—displays, graphics accelerators, TV encoders
• Related image processing and manipulation: image enhancements and conversions, etc.
• Synchronization and control capabilities (for example, to avoid tearing artifacts)
This integrative approach leads to several significant advantages:
• Automation
The involvement of the MCU (Main Control Unit) in image management is minimized. In
particular, display refresh/update can be performed completely autonomously. The resulting
benefits are reducing the overhead due to software-hardware synchronization, freeing the MCU to
perform other tasks and reduced power consumption (when the MCU is idle and can be powered
down).
• Optimal data path
Access to system memory is minimized. In particular, significant processing can be performed
on-the-fly while sending data to a display. System memory is used essentially only when a change
in pixel order or frame rate is needed. The resulting benefits are reduced load on the system bus
and further reduction of power consumption.
• Resource sharing
Maximal hardware reuse for different applications, resulting with the support of a wide range of
requirements with minimal hardware
The hardware reuse mentioned above is enabled by a sophisticated configurability of each hardware block.
This configurability also allows the support of a wide range of external devices, data formats and operation
modes. The resulting flexibility is important because the support requirements are evolving significantly;
expected future changes need to be anticipated and accounted for.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
10-2
Freescale Semiconductor
10.1.1.1
External Ports
The IPU has the following ports:
• Two display ports—each controlled by a DI module—providing a connection to displays and
related devices.
• Memory port—AXI (AHB V3.0) master, controlled by the IDMAC—providing connection to the
system memory.
• AHB-lite slave port, providing connection to the ARM MCU (and to any other master connected
to the ARM’s cross-bar switch)
• Additional ports for control and debug
10.1.1.1.1
Display Ports
The role of these ports is to communicate with a display device, either directly or through a controller (for
example, graphics accelerator) or a bridge (for example, TV encoder).
Two access modes are supported: synchronous access and asynchronous access.
In synchronous access mode, the IPU transfers a two-dimensional block of pixels to the display device, in
synchronization with the screen refresh cycle.
This mode has a dual role:
• For a RAM-less display or a TV screen, this mode is used to perform the screen refresh process
from a display buffer in system memory.
• For a “smart” display, this mode is used to transfer a rectangular block of pixels to the display’s
screen and, in some cases, also to the display buffer
In both cases, the IPU sends to the display all the synchronization signals controlling the screen refresh
and the block transfer is synchronized with these signals. This synchronization means that tearing effects
are avoided when using this mode.
Asynchronous access is the main mode used for communicating with an external display controller
(possibly in a smart display or a graphics accelerator). In this mode, the IPU performs random
access—read/write—to the memory and registers of controller.
The following access types are provided:
• Data transfer to the external device, after on-the-fly processing in the IPU.
• Data transfer (DMA)—read/write—between the host’s system memory and the external device,
through the IPU’s memory port (controlled by the IDMAC); for example, transfer of a rectangular
block of pixels (possibly full screen).
• Host access—read/write—to an external device, through the AHB-slave port
— Access types
– Direct access—emulating a directly-addressed access (see below)
This includes burst access (incremental; up to 8 words/burst)
– Low-level access—leaving to the host the explicit generation of the access protocol
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
10-3
— The possible accessing modules include the MCU and the system DMA controller (as well as
any other AHB master connected to the MCU’s cross-bar switch).
Asynchronous access requires the specification of an address. The display interface uses indirect
addressing, meaning there is no address bus and the address, control commands, and configuration
commands, are embedded in the data stream. The access procedure, including writing addresses and
commands, can be managed autonomously by the interface, using an access template generated by the
MCU.
10.1.1.1.2
The Interface
The display interface is very flexible and supports a wide variety of devices from major manufacturers.
The following interface types are provided (in each of the two display ports).
• A parallel video interface (for synchronous access)—up to 24-bit data bus.
• A parallel bidirectional bus interface (for asynchronous access)—up to 32-bit data bus.
The supported formats for pixel data are: RGB and YUV 4:2:2 (for TV encoder).
The transfer rate supported is at least 100 MHz (for all interfaces)
• For synchronous access with one cycle/pixel, this enables, e.g (including 35% blocking intervals)
— XGA (1024 × 768) at 100 fps
— 720p (1280 × 720) at 60 fps
— 1080i (1920 × 1080) at 30 fps
• When two (or more) display devices are used simultaneously, the total rate supported is as above.
Simultaneous functionality of the above devices is possible in each of the following ways:
• Two devices can be accessed independently, each through a different port.
• Two devices can time-share asynchronous accesses, using the CS signals.
• An asynchronous access can be performed during vertical blanking intervals of a synchronous
access.
10.1.1.2
Processing
The IPU processes rectangular blocks of pixels. The processing is performed in modules: DP, IC, and IRT.
Several time-shared data flows are supported, as described in Table 10-2.
Table 10-2. Time-Shared Data Flows Through The IPU
Name
Display Refresh/
Update
Number
5 flows (at
most two of
them of type
DS1)
1 flow
Type
Flow
Target
Restrictions
DS1 Fmem → DP → Display
Synchronous Access (for
example, display refresh;
controlled by the DI)
—
DS2 Fmem → DP → Display
Asynchronous Access (for
example, display update)
—
DS3 Fmem ↔ Display
Generic Data Transfer
—
DS4 MCU ↔ Display
Direct Access
—
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
10-4
Freescale Semiconductor
Table 10-2. Time-Shared Data Flows Through The IPU (continued)
Name
Video Playback
Number
flow
Graphic Overlays 2 flows
2 flows
Type
Flow
Target
PL1
Bmem → IC → Bmem →
IRT → Fmem
+ DSx
PL2
Fmem → IRT→ Bmem → IC Low power
→ DP
(branching to DSx, as a
video plane)
GF1 Fmem → IC
GF2 Fmem → DP
Restrictions
Main option
—
Large enough window
No other video flows
(combining with the main
flow)
—
—
Comments
• System memory usage–legend
— Fmem: frame double-buffer (page-flip) in system memory (typically external)
— Bmem: two possibilities
– A frame double buffer, as above
– A band (4–256 rows) double-buffer (page-flip) in system memory (could be internal)
— Direct arrow between two processing stages represents an internal pipelining
• Time-sharing
— DP can time-share one DS1 flow and a one DS2 flow (each with different destinations and
independent processing parameters)
— Direct access to display (DS4) time-shares tightly the display port with other active DSx flows.
— Other time-sharing (between PLx, between DS2 and DS3, in IRT) is frame-by-frame
Any of the processing stages in the above flows can be skipped.
10.1.1.2.1
Display Processor (DP)
The display processor performs processing required for output to a display:
• Combining two video/graphics planes
• Overlaying a simple hardware cursor
32 × 32 pixels, uniform color, may be combined logically with the background.
• Color conversion/correction—linear (multiplicative and additive)
Programmable; including:
— YUV ↔ RGB, YUV ↔ YUV conversions
where YUV stands for any one of the color formats defined in the MPEG-4 standard
— Adjustments: brightness, contrast, color saturation...
— Special effects: gray-scale, color inversion, sepia, blue-tone...
— Hue-preserving clipping, for gamut mapping
— Applied to the output of combining or to one of the inputs
• Gamma correction and contrast stretching—programmable piecewise-linear map
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
10-5
The DP processes a single data flow at any given time, but it supports up to three data flows, by time
sharing, one of them may be synchronous.
The data throughput is up to 110M pixels/sec (peak; including blanking intervals)
10.1.1.2.2
Image Converter (IC)
The Image Converter performs various operations on a video stream. The operations performed are:
• Resizing
— Fully flexible resizing ratio
Maximal downsizing ratio: 8:1
Subject to this limitation, any N→M resizing can be performed
— Independent horizontal and vertical resizing ratios.
• Color conversion/correction - linear (multiplicative and additive)
Programmable; including:
— YUV ↔ RGB, YUV ↔ YUV conversions
where YUV stands for any one of the color formats defined in the MPEG-4 standard
— Adjustments: brightness, contrast, color saturation...
— Special effects: gray-scale, color inversion, sepia, blue-tone
• Combining with a graphics plane (for example, application-specific overlay)
• Horizontal inversion
The IC supports three time-shared data flows share a common input).
The frame resolution supported is up to 4096 × 4096 for input and up to 1024 × 1024 for output. Wider
frames can be processed by the IC by splitting them to vertical stripes.
The data throughput is up to 100 M pixels/sec for input and up to 50 M pixels/sec for output.
10.1.1.2.3
Image Rotator (IRT)
The Image Rotator performs any combination of the following:
• 90-degree rotation
• Horizontal inversion
• Vertical inversion
The data throughput is up to 50 M pixels/sec.
10.1.1.3
Automatic Procedures
The IPU is equipped with powerful control and synchronization capabilities to perform its tasks with
minimal involvement of ARM and minimal use of memory. In particular, it includes the following:
• An integrated DMA controller with an AXI master port, allowing autonomous access to the system
memory
• An integrated display controller, performing screen refresh of a RAM-less display.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
10-6
Freescale Semiconductor
•
•
A page-flip double buffering mechanism, synchronizing read and write access to system memory,
to prevent tearing effects.
Internal synchronization
As a result, in most cases, the MCU is involved only when it also performs part of the processing (for
example, video coding). In particular, the following procedures are performed by the IPU completely
autonomously:
• Screen refresh for RAM-less displays
• Update of the (foreground) display buffer used for screen refresh (located either in system memory
or in an external display controller, for example, of a smart display or graphics accelerator) when
the content is generated in a different (background) buffer.
Typically, there are extended periods of time in which there is no other activity in the system. The MCU
being idle can be put into a low-power mode, reducing the power consumption and significantly extending
the battery life.
The IPU supports the following techniques that further reduce the power consumption of the display
system:
• Optimized update of the display buffer, using a snooping signal from the ISM (IPU Snooping
Module), indicating a modification of the source buffer.
• Dynamic backlight control, with low-light compensation by image enhancement (contrast and
brightness adjustment)
Further features and capabilities of the automatic procedures include the following:
• Automatic display of a changing image (animation) or moving image (scrolling).
• The timing of the display update can be adjusted to avoid tearing.
The IPUE supports direct frame synchronization with the GPU, using either two or three frames, as
follows:
• The GPU instructs the IPU which frame should be transferred to the display.
• The IPU notifies the GPU which frame is currently transferred to the display.
• The IPU provides to the GPU an end-of-frame trigger (after which it switches to the frame
indicated by the GPU).
This mechanism is provided for the main plane of the primary flow to the DP.
The clock sources received by the IPU are listed in Table 10-3.
Table 10-3. IPU Clock Sources
Name
Symbol
Source
Rate
High-Speed
Processing Clock
HSP_CLK
Clock control Module
Up to 133 MHz
Display Interface
Clock
DI_CLK
Clock control Module
or an external PLL
up to 80 MHz
Comments
—
Optional
For example, for synchronization with a TV
encoder
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
10-7
10.2
Video Processing Unit (VPU)
The VPU is a multistandard video codec (encoder/decoder) capable of handling up to four simultaneous
multiple streams using time multiplexing. The VPU is a very flexible block consisting of hardwired
accelerators surrounding a programmable core. The VPU presents to system a register mapped interface
that is controlled by the embedded processor. Because this interface can be updated by the firmware, it is
not documented in this document. Instead, the designer should consult the documentation released with
the firmware used. End users should only interface with the VPU using the API that is also released with
each firmware release. This API isolates the user from possible changes in the register level interface.
Table 10-4 shows a summary of the VPU specs. The VPU has its own DMA driven AXI masters that allow
it to retrieve the required data directly from system memory. The load in the host is negligible because it
only needs to interact with the VPU at the frame level.
Table 10-4. A Brief Summary of VPU Specification
Name
VPU
Function
Decode video streams including optional video processing such as rotation,
deringing and mirroring.
Supported encoders
MPEG-4 SP
H.263 V2 + Annex J, K (RS = 0 and ASO = 0), and T
H.264 BP
MJPEG Baseline
Supported decoders
MPEG-2 MP
VC-1 SP, MP, HP
MPEG-4 SP, ASP
H.263 V2 + Annex J, K (RS = 0 and ASO = 0), and T
H.264 BP, MP, HP
DivX v3,4,5
Real Video 10
MJPEG Baseline
External I/O Pins (List, Type, Schmidt
Trigger, Speed)
No external I/O pins are needed
SoC Buses (List, Type, Bandwidth)
64 bit AXI master for accessing the system memory and search RAM
IPBus slave for host control
Interrupts
one interrupt
DMA Requests
Integrated DMA controller on the AXI master port
Endianness
64 and 32 bit BE/LE
Number of instantiations
1
Clock sources and range
Core clock: up to 133 MHz
AXI bus clock: up to 166 MHz
IP bus clock: up to 66.5 MHz
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
10-8
Freescale Semiconductor
Chapter 11
Power Management
The i.MX51 supports several power management techniques to reduce active and static power
consumption. This chapter describes the operation of these features and the registers used to configure and
control them.
11.1
Power Saving Methodology
This section discusses active power savings and leakage power savings.
11.1.1
Active Power Savings
Active power saving methods include the following:
• Dynamic voltage frequency scaling (DVFS)
This reduces active power consumption by scaling voltage and frequency. There are two DVFS
engines in the i.MX51: one is used by the peripherals and the other by the ARM platform.
• Dynamic process temperature compensation (DPTC)
This reduces active power consumption by adjusting supply voltage according to the individual
device’s characteristics and ambient temperature. There are two DPTC engines: one is used by the
peripherals and the other by the ARM platform.
• Clock gating
This reduces active power consumption by gating the clock to each module while the module is in
idle state. The i.MX51 implements three levels of clock gating as follows:
— Clock tree roots in the Clock Control Module (CCM)
— Clock tree branches in the Low Power Clock Gating unit (LPCG)
— Clock tree leaf nodes in the individual modules
11.1.2
Controlling Leakage
The primary leakage control mechanisms are reduced voltage (STOP mode) and power gating. There are
three types of power gating, as follows:
• State retention power gating (SRPG)
• Power gating (PG)
• PG with Save and Restore
The three types of power gating work in the following ways. When SRPG is applied, the state of the flip
flops is preserved to internal switch cells (powered by a continuously powered supply) at the time the
combinatorial logic between the flip flops is powered down. Using PG removes power from the selected
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
11-1
module, resulting in the loss of all data in three affected modules: the VPU, GPU2D, and GPU3D. When
PG with Save and Restore is used, the state of the block is saved into its constantly powered memory
before the power to the block is removed. Once power is reapplied, the state of the block is reloaded from
memory, and the block continues in the same state as it was in before it was powered down. This type of
power gating is accomplished by hardware in the IC. IPUEX supports PG with Save and Restore.
11.2
Power Gating Sequences
The following order is recommended when powering up the modules in the i.MX51:
1. SoG—After the SoG has powered up, move to the next power-up stage.
2. IPUEX—After the IPUEX has powered up, move to the next power-up stage.
3. VPU—After the VPU has powered up, move to the next power-up stage.
4. GPU3D—After the GPU3D has powered up, move to the next power-up stage.
5. GPU2D—After the GPU2D has powered up, move to the next power-up stage.
6. EMI—After the EMI has powered up, an acknowledgement the power-up is complete is generated.
11.2.1
Power Gating Options
The sequence of power gating is controlled by the Global Power Controller (GPC) modules on the i.MX51.
The following power gating options exist:
• SRPG of the Cortex_A8 platform in WAIT mode.
• SRPG of the Cortex_A8 platform in STOP mode.
• SRPG of the NEON floating unit when it’s not needed, by software control.
• Partial SRPG of the EMI block during WAIT mode.
• Partial SRPG of the EMI block during STOP mode.
• Power gating of one or more of the following blocks during WAIT mode: VPU, GPU3D and
GPU2D.
• Power gating of one or more of the following blocks during STOP mode: VPU, GPU3D and
GPU2D.
• Power gating of one or more of the following blocks during RUN mode: VPU, GPU3D and
GPU2D.
• Power gating with PG with Save and Restore of IPUEX during WAIT.
• Power gating with PG with Save and Restore of IPUEX during STOP.
11.3
Low-Power Modes
The i.MX51 can operate in several different low-power modes. Some low-power modes are module
specific. The four low-power modes as follows:
• RUN
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
11-2
Freescale Semiconductor
•
•
•
11.4
The ARM core is active; its clocks are on; and the peripheral modules needed for a specific task
are active. Software is used to gate off clocks from modules that are not in use. The CCM can
enable power gating of the modules described above.
WAIT
The ARM core is disabled; its clocks are gated off; and the bus clocks to peripherals are gated on
as required. The power gating modes PG and SRPG can be applied to Cortex_A8 and the different
blocks as described in Chapter 7, “Clock Controller Module (CCM),” Section 11.4, Module
Specific Power Modes.”
STOP
The ARM core is disabled; peripherals are disabled; bus clocks are off; and clock PLLs are off. The
power gating modes PG and SRPG can be applied to Cortex_A8 and the different blocks as
described in Chapter 7, “Clock Controller Module (CCM),” Section 11.4, Module Specific Power
Modes.”
LPSR—Low Power Screen Refresh
This is a subset of the STOP mode. The ARM core is disabled; all peripherals but the ones needed
for LPSR are disabled; and clock PLLs are off. PG and SRPG can be applied to the Cortex_A8 and
the peripherals that are not needed for LPSR. In this mode, the clocks are supplied by either FPM
or CKIH. The peripherals that are required for LPSR mode are as follows:
— IPU EX
— EMI—only the internal memory arbitration is needed.
— SCC and its internal memory
— All translators between the EMI to the SCC.
Module Specific Power Modes
The power modes of the individual modules are as follows:
• Active—Operational with clocks on.
• Idle—Not operational but the clocks are on.
• Disabled—Not operational and the clocks are off.
The module modes can be mapped onto the domain modes as shown in Table 11-1
Table 11-1. Low-Power Modes
Mode
ARM Platform
Modules
PLL
CKIH/FPM
CKIL
RUN
Active
Active, Idle, or Disabled1
On
On
On
WAIT
Disabled
Active, Idle, or Disabled1
On
On
On
STOP
Disabled
Disabled2
Off
Off
On
LPSR
Disabled
Disabled3
Off
On
On4
1
During RUN and WAIT modes, the peripherals can be active, but not all must be active. The modules that are not needed can
be Idle or Disabled in the RUN and WAIT modes.
2
Some modules can operate using CKIL in STOP mode.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
11-3
3
4
Some blocks need to operate using CKIH or FPM in LPSR mode.
If the FPM is selected then CKIL needs to be left on.
11.4.1
Power Down Sequence
The power-down sequence is as follows:
1. The software configures the LPM bits in the CCM (see CCM chapter) as well as the power gate
bits in the GPC. The information (if a peripheral or the ARM platform can be power gated) is stored
in the GPC module.
2. The ARM platform starts the LPM sequence, resulting in the CCM raising a power-down request
for ARM and the peripherals.
3. The power-down sequence occurs in parallel on all peripherals and the ARM platform.
4. A combined power-down acknowledge signal is issued to the CCM from the GPC module.
11.4.2
Power Up Sequence
The power-up sequence is as follows:
1. After an interrupt is received and the clocks resume operation, a power-up request signal is issued
from the CCM to the GPC.
2. The power-up of the ARM core and the other peripherals occur in parallel.
3. The power-up of the peripherals is done one after the other in order to prevent excessive current
drain during the power up.
4. The power-up request of the CCM module is connected to the power-up request of the first PGC
block and its power-up acknowledge is connected to the power-up request of the next PGC blocks.
5. Each of the PGC modules sends a reset request to the SRC module. This initiates the reset sequence
to the needed module as described in the SRC chapter.
11.4.3
IPU Save and Restore Sequence
The IPU save and restore sequence is as follows:
1. If the power gating bit of the IPU EX is selected, a signal (gpc_ipu_stat_pg) stating that IPU EX
will be power gated in the next LPM is sent to the IPU EX.
2. In the process of entering low power mode, the IPU EX needs to approve the entrance to LPM
(refer to the CCM chapter). If it sees the gpc_ipu_stat_pg, it goes through the process of Save in
the IPU EX memories so that their arrays will always be powered. Only after the Save is complete
does it return an acknowledge of the power-down to the CCM. The CCM then continues the LPM
sequence.
3. In the process of exiting low-power mode, the IPU EX checks to see if the gpc_ipu_pg_event signal
is active (meaning a power gate has occurred). Then the IPU EX restores all the required data from
the memories.
4. The IPU EX sends a signal called ipu_stby_ack indicating it has completed the process. This signal
clears the gpc_ipu_pg_event signal in the GPC.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
11-4
Freescale Semiconductor
11.5
RAM Memory Supplies
Refer to the Operating Ranges table in the i.MX51 data sheet.
11.6
Fusebox Supplies
Refer to the Operating Ranges table in the i.MX51 data sheet.
11.7
Dynamic Voltage and Frequency Scaling
The i.MX51 uses DVFS as one of its active power saving methodologies. The ARM core (VDDGP) and
peripheral core (VCC) supply voltage ranges are stated in the Operating Ranges table of the i.MX51 data
sheet.
DVFS is supported on both the ARM platform and the peripherals using the following two different load
monitors:
• DVFS_Core
— Monitors by weighing signals relevant to the ARM platform
— Affects only the ARM platform.
• DVFS_Per
— Monitors by weighing signal relevant to the i.MX51 peripherals
— Affects only the peripherals.
— While in DVFS mode each clock is divided by 2, 3, or 4 across all of the peripheral domain,
depending on the configuration in the CCM.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
11-5
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
11-6
Freescale Semiconductor
Chapter 12
System Security
12.1
Introduction
Security is an increasingly important feature of handheld devices such as cell phones, ultra-portable
computers, and integrated media players. Instances of hackers and pirates breaking into portable devices
and stealing private information or copyrighted content are becoming more and more common. As such,
security is a high priority for the i.MX51.
To address the potential security risks and to provide an extensible platform for addressing future security
needs, the i.MX51 incorporates the following advanced hardware blocks and architectural features:
• High Assurance Boot (HAB) System
• Memory Management Unit (MMU)
• Trusted Execution Environment (ARM’s TrustZone, Virtualization)
• TrustZone Interrupt Controller (TZIC) and TrustZone Watchdog (TZ WDOG)
• EMI WaterMark (WM) mechanism
• Central Security Unit (CSU)
• IC Identification Module (IIM) with On-chip One Time Programmable Electrical Fuse Array
• Security Controller (SCC) with 128KByte of secure RAM
• Cryptographic Accelerator (SAHARA4LT)
• Run-Time Integrity Checker (RTIC)
• Secure JTAG Controller (SJC)
• Secure Real Time Clock (SRTC)
• Physical Tamper Detectors
• Security Services and Protocols
For detailed information about the operation of the security features, contact your Freescale representative.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
12-1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
12-2
Freescale Semiconductor
MCIMX51 Reference Manual
Book II
Rev. 1
2/2010
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Book I -2
Freescale Semiconductor
Chapter 13
1-Wire Module (1-Wire)
13.1
Overview
The 1-Wire module provides the communication link to a generic 1-Kbit add-only memory. The module
sends or receives one bit at a time. The required protocol for accessing the generic 1-Wire device is defined
by Maxim. The generic 1-Wire device holds battery characteristics information.
Figure 13-2 shows a block diagram of the 1-Wire module.
to Host
Peripheral Bus
to Registers
Interrupt
Interrupt Generation
1-Wire Bus Protocol Functions
Reset/Presence-Detect
(for byte and SRA transfers only)
Bit Transfers
OWDAT
Clock Divider
Main Clock
Byte Transfers
Time Base
(1 MHz)
Search ROM Accelerator (SRA)
Figure 13-1. 1-Wire Module Block Diagram
13.1.1
Features
The 1-Wire module includes the following features:
• Performs the 1-Wire bus protocol to communicate with an external 1-Wire device.
• Provides a clock divider to generate a 1-Wire bus reference clock (derived from the main clock
provided internally to the module).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-1
13.1.2
Modes of Operation
The 1-Wire module supports the following operations:
• Normal Operating Modes (See Section 13.4.1, Normal Operating Modes”)
— Bit Transfers
— Reset/Presence-detect Pulse
• Low-Power Mode (See Section 13.4.2, Low Power Mode”)
13.2
External Signals
Table 13-1 shows the signal that interfaces with a generic 1-Wire device.
Table 13-1. 1-Wire Module Signal
Signal
I/O
OWDAT
I/O
13.3
Function
1-Wire bus
Requires an external pull-up resistor. The recommended resistor value is specified by the generic 1-Wire
device used in a given system.
Memory Map and Register Definition
This section provides the module memory map and detailed descriptions of all registers.
13.3.1
Memory Map
Table 13-2 shows the 1-Wire memory map.
Table 13-2. 1-Wire Memory Map
Base Address
0x83FA_4000 (CONTROL)
0x83FA_4002 (TIME_DIVIDER)
0x83FA_4004 (RESET)
13.3.2
Register
Access
Reset Value
Section/Page
Control register
R/W
0x0000
13.3.2.1/13-2
Time Divider register
R/W
0x0000
13.3.2.2/13-4
Reset register
R/W
0x0000
13.3.2.3/13-4
Register Descriptions
This section provides the detailed descriptions for the registers. All registers are byte-addressable.
13.3.2.1
Control Register (CONTROL)
The control register is used to initiate the reset/presence-detect sequence and bit transfers. The register also
provides the presence-detect status and bit-read status.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
13-2
Freescale Semiconductor
Figure 13-2 shows the register. Table 13-3 describes the register fields.
Address 0x83FA_4000 (CONTROL)
R
Access: User read/write
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
WR0
WR1
0
0
PST
RPP
3
2
1
0
RDST
0
0
0
0
0
0
0
W
RESET
0
0
0
0
0
0
0
0
0
0
Figure 13-2. Control Register
Table 13-3. Control Register Field Descriptions
Field
Description
15–8
Reserved
7
RPP
Reset/Presence-detect Pulse. This bit is self-clearing and is cleared after the presence or absence of an
external device is determined. See Section 13.4.1.1, Reset/Presence-detect Pulse.”
When writing:
0 Do nothing.
1 Generate Reset Pulse and sample the bus for the presence pulse from the external device.
When reading:
0 Reset pulse complete.
1 Sequence not complete.
6
PST
Presence Status. This bit is valid after the RPP bit is self-cleared.
0 Device is not present.
1 Device is present.
5
WR0
Write 0. This bit is self-clearing and is cleared when the write of the bit is complete. See Section 13.4.1.2.1,
Write-0 Sequence.”
When writing:
0 Do nothing.
1 Write a 0 bit to the interface.
When reading:
0 Write sequence complete.
1 Sequence not complete.
4
WR1
Write 1/Read. This bit is self-clearing and is cleared when the write sequence is complete. See
Section 13.4.1.2.2, Write-1/Read Sequence.”
When writing:
0 Do nothing
1 Write a 1 bit to the interface and sample the bus.
When reading:
0 Sequence complete.
1 Sequence not complete.
3
RDST
2–0
Read Status. This bit is valid after the WR1 bit is self cleared.
0 A 0 has been sampled.
1 A 1 has been sampled.
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-3
13.3.2.2
Time Divider Register (TIME_DIVIDER)
The time divider register is used for dividing the main clock (ipg_clk) input down to 1 MHz to generate
the module’s time base.
Figure 13-3 shows the register. Table 13-4 describes the register fields.
Address 0x83FA_4002 (TIME_DIVIDER)
Access: User read/write
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R
7
6
5
4
3
2
1
0
0
0
0
0
DVDR
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-3. Time Divider Register
Table 13-4. Time Divider Register Field Descriptions
Field
Description
15–8
Reserved
7–0
DVDR
Divider Factor. The internal clock divider uses this field to generate the required time base for the module.
See Section 13.4.3, Clocks.”
0x00 1 (default)
0x01 2
…
…
0xFF 256
13.3.2.3
Reset Register (RESET)
The reset register is used to perform a software reset of the 1-Wire module. Figure 13-4 shows the register.
Table 13-5 describes the register fields.
Address 0x83FA_4004 (RESET)
R
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RST
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-4. Reset Register
Table 13-5. Reset Register Field Descriptions
Field
Description
15–1
Reserved
0
RST
Software Reset. See Section 13.4.4.2, Software Reset.”
0 Do not perform a software reset.
1 Initiate a software reset and hold the module in the software-reset state.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
13-4
Freescale Semiconductor
13.4
Functional Description
The 1-Wire module interfaces with a generic 1-Kbit add-only memory, through a simple 1-bit bus.
Software uses the 1-Wire bus to program and read the 1-Kbyte memory.
The protocol involves first issuing one of four ROM function commands before the EPROM is accessible:
• Read ROM
• Match ROM
Through the 1-Wire bus, the host software interfaces with the generic 1-Wire device and allows the
required commands to be issued to control the EPROM of a generic 1-Wire device. The host (through the
1-Wire interface) is the bus master, and the generic 1-Wire device(s) are the slave(s).
13.4.1
Normal Operating Modes
The 1-Wire module supports the following 1-Wire bus protocol functions:
• Reset/Presence-detect pulse using the control register (See Section 13.4.1.1, Reset/Presence-detect
Pulse”)
• Bit Transfers using the control register (See Section 13.4.1.2, Bit Transfers”)
13.4.1.1
Reset/Presence-detect Pulse
The 1-Wire module provides for an automated initialization sequence for the 1-Wire bus. Software initiates
the initialization sequence by setting CONTROL[RPP]. The automated initialization sequence is as
follows:
1. Generate a reset pulse.
2. Listen for a response from an external device by sampling for the 1-Wire device presence bit.
3. After an amount of time determined by the 1-Wire standard, latch the presence bit (true or false) in
CONTROL[PST].
If an external device is detected (PST = 1), software can begin communications on the 1-Wire bus.
The presence pulse is used by the 1-Wire to determine if at least one generic 1-Wire device is connected.
Software determines if more than one generic 1-Wire device exists.
13.4.1.2
Bit Transfers
After the initialization sequence (see Section 13.4.1.1, Reset/Presence-detect Pulse”), software can write
and read one bit at a time using the control register.
13.4.1.2.1
Write-0 Sequence
The Write-0 sequence writes a zero bit to the generic 1-Wire device. Setting the CONTROL[WR0]
initiates the Write-0 pulse sequence. Once the write is complete, the WR0 bit is automatically cleared.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-5
13.4.1.2.2
Write-1/Read Sequence
The Write-1 sequence writes a one bit to the generic 1-Wire device. Setting the CONTROL[WR1] bit
initiates the Write-1 pulse sequence. Once the write is complete, the WR1 bit is automatically cleared.
Because the Write-1 and Read timings are identical, this sequence also reads a bit from the bus. The
sampled value is stored in the read status bit CONTROL[RDST] and is valid after the WR1 bit is
self-cleared.
The host transmits the 16-byte search value based on the last ROM value found. These 16 bytes are 0x00
for the first run. The 16 bytes returned contain the new ROM code and are also used to generate the next
16 bytes to transmit. This process is repeated until serial numbers duplicate to find all devices.
13.4.2
Low Power Mode
The 1-Wire module automatically goes into low-power mode whenever it is not communicating with a
generic 1-Wire device. The main clock is gated off in low-power mode.
As soon as software writes to any register, the 1-Wire module exits low-power mode.
13.4.3
Clocks
The 1-Wire module takes a main clock as a module input and passes it through a clock divider. (See the
block diagram in Figure 13-1.) Software must program the divider factor to generate a 1-MHz clock that
is used as an internal time base for the module, as given by Equation 13-1.
Eqn. 13-1
time_base = main_clock ÷ (TIME_DIVIDER[DVDR] + 1)
For example, if the main clock frequency is 30 MHz, the value to write to the divider register is 29. If the
main clock input frequency is not an integer, the programmer must ensure the time base frequency is within
the range given by Equation 13-2.
Eqn. 13-2
0.98 MHz ≤ time_base ≤ 1.02 MHz
NOTE
A main clock frequency below 10 MHz causes improper function of the
module.
13.4.4
Reset
The 1-Wire module supports two levels of reset: hardware and software.
13.4.4.1
Hardware Reset
Whenever a device reset occurs, a hard reset is performed on the 1-Wire module, clearing all values written
to all registers.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
13-6
Freescale Semiconductor
13.4.4.2
Software Reset
Software initiates a software reset by setting the reset bit RESET[RST]. A software reset clears all data
written to the registers.
Note that the reset register (RESET) itself is not cleared during a software reset. Software must clear the
RST bit to release the software reset.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-7
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
13-8
Freescale Semiconductor
Chapter 14
Cortex-A8 Platform
14.1
Overview
A block diagram of the Cortex-A8n Core Platform is shown in Figure 14-1. The platform consists of the
ARM Ltd. Cortex-A8n processor which includes a NEON co-processor, an L1 cache, an L2 cache, an
ETM, and a CTI. The platform includes the essential sub-blocks: platform control, test logic, and the debug
modules (CTM, ETB, and a second CTI).
The Cortex-A8n processor instruction and data read/write AXI master port is connected from the non-CPU
side of the Level 2 Cache. The L2 can in turn can access L3 memory via this port.
The core platform supports static debug through the debug logic to SOC. This includes the capability of
real time trace via ARM’s Coresight ETM, ETB, and CTM modules. The second CTI module allows cross
triggering of internal and external trigger sources.
The Cortex-A8n platform has two power domains (LP and GP), which are separated by level shifters. The
LP power domain serves as an interface to the rest of the SoC. The GP power domain is completely
contained within the platform and allows the Cortex-A8n core and subsystem to run at much higher
frequencies than the rest of the SoC.
The boundary of the two power domains is also an asynchronous boundary between the Cortex-A8n
platform and the rest of the SoC. Synchronizers in both the GP and LP power domains of the platform
allow the Cortex-A8n core and subsystem to run asynchronously from the rest of the SoC.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-1
tigerp_platform_ne_32k_256k
tigerp_gp_domain
tigerp_lp_domain
tigerp_gp_core
tigerp_lp_async
& tigerp_lvl_shift
FIQn & IRQn
S
CortexA8_ne_32k_256k
32k I$
MMU
tigerp_gp
_async
32k D$
ipg_clk_lp (IPS clk)
aclk_lp (AXI clk)
dbg_pclk_lp (APB)
dbg_atclk_lp (ATB)
IRQ/FIQ
L2
Data Memory
256 kB
NEON
64-bit
ETM
Debug
Unit
S_gp
S_lp
S_gp
S_lp
S_gp
S_lp
AXI Bus
CTI0
plat_ctrl
CTMCHOUT0
APB
CTMCHIN0
Synchronized Resets
& Internal Clocks
IP Bus
arm_clk
soc_reset_b
& debug reset
CTMCHOUT2
CTMCHIN2
tigerp_gp_debug
CTMCHIN1
CTMCHOUT1
CTM
APB Debug Bus
CTI1_TRIGOUTS
CTI1_TRIGINS
CTI1
S_gp
S_lp
APB Debug Bus
S_gp
S_lp
to TPIU
ATB
ETB
ATB
ATB
ATB
Replicator
tigerp_gp_test
tigerp_lp_test
GP
LP
Level Shifter
S
Synchronizer
S_gp
Split synchronizer on GP side
S_lp
Split synchronizer on LP side
Figure 14-1. Cortex-A8n Core Platform Block Diagram
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-2
Freescale Semiconductor
14.2
Core Platform Sub-blocks
This section discusses the core platform sub-blocks.
14.2.1
Cortex-A8n Processor
The information presented in this section focuses on design aspects of the Cortex-A8n Processor in the AP
subsystem. The Cortex-A8n Processor is ARM’s first superscalar processor featuring technology for
enhanced code density and performance, NEON technology for multimedia and signal processing, and
Jazelle RRCT (Runtime Compilation Target) technology for efficient support of ahead-of-time and
just-in-time compilation of Java and other bytecode languages.
The Cortex-A8n Processor incorporates an integer core that implements the ARMv7-A architecture
instruction set. It supports the ARMv7 and Thumb-2 instruction sets. A NEON module is included to
accelerate the performance of multimedia applications. The included Vector Floating Point v3 architecture
complies with the IEEE 754 standard. The processor includes an AMBAR 3 AXI high-performance 64-bit
SoC interconnect.
14.2.1.1
Features
The following list discusses the main features.
•
•
•
•
The ARM Cortex-A8n Processor’s sophisticated pipeline architecture is based on dual, symmetric,
in-order issue, 13-stage pipelines with advanced dynamic branch prediction achieving 2.0
DMIPS/MHz. The instruction execute unit consists of two symmetric Arithmetic Logical Unit
(ALU) pipelines and the multiply pipeline.
— In-order, dual-issue, superscalar microprocessor core
— 13-stage main integer pipeline
— 10-stage NEON media pipeline for executing NEON and VFP instruction sets
— Dedicated L2 cache with programmable wait states
— Global history based branch prediction
Works in conjunction with a power optimized load store pipeline to deliver 2.0 DMIPS/MHz for
power sensitive applications
ARMv7 architecture compliant including:
— ThumbR-2 technology for greater performance, energy efficiency, and code density
— NEON signal processing extensions to accelerate media codecs such as H.264 and MP3
— Jazelle RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic
Adaptive Compilation (DAC), and reduce memory footprint by up to three times
— TrustZone™ technology for secure transactions and Digital Rights Management (DRM)
Integrated Level 2 Cache
— Built using standard compiled LP RAMs
— Sized at 256 Kb
— Programmable delay
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-3
•
•
•
•
•
•
Optimized Level 1 Caches
— Customized design for performance and power optimization
— Sized at 32 Kb Instruction and 32 Kb Data
— Combine minimal access latency with hash way determination to maximize performance and
minimize power consumption.
Dynamic Branch Prediction
— Enabled by branch target and global history buffers
— Achieves 95% accuracy across industry benchmarks.
— Replay mechanism minimizes miss-predict penalty
Memory System
— Single-cycle load-use penalty for access to the L1 cache
— Hash array in the L1 cache limits activation of the memories to when they are likely to be
needed.
— Direct interface between the integrated, configurable L2 cache and the NEON media unit for
data streaming
— Banked L2 cache design that enables only one bank at a time
Memory Management Unit (MMU) and separate instruction and data Translation Look-aside
Buffers (TLBs) of 32 entries each
Embedded Trace Macrocell (ETM) support for non-intrusive debug
ARMv7 debug with watchpoint and breakpoint registers and a 32-bit Advanced Peripheral Bus
(APB) interface to the CoreSight debug system.
14.2.1.2
Instruction Fetch
The instruction fetch unit predicts the instruction stream, fetches instructions from the L1 instruction
cache, and places the fetched instructions into a buffer for consumption by the decode pipeline. The
instruction fetch unit also includes the L1 instruction cache.
14.2.1.3
Instruction Decode
The instruction decode unit decodes and sequences all ARM and Thumb-2 instructions including the
debug control coprocessor, CP14, and the system control coprocessor, CP15 instructions.
The instruction decode unit handles the sequencing of the following:
• Exceptions
• Debug events
• Reset initialization
• Memory Built-In Self Test (MBIST) for L1 cache
• Wait-for-interrupt
• Other unusual events
• Instruction Cycle Timing
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-4
Freescale Semiconductor
14.2.1.4
Instruction Execute
The instruction execute unit consists of two symmetric Arithmetic Logical Unit (ALU) pipelines and the
multiply pipeline. The execute pipelines also perform register write back.
The instruction execute unit performs the following tasks:
• Executes all integer ALU and multiply operations including flag generation
• Generates the virtual addresses for loads and stores and the base write-back value, when required
• Supplies formatted data for stores and also forwards data and flags
• Processes branches and other changes of instruction stream and evaluates instruction condition
codes.
14.2.1.5
Load/Store
The load/store unit encompasses the entire L1 data side memory system and the integer load/store pipeline.
This includes the following:
• L1 data cache
• Data side TLB
• Integer store buffer
• NEON store buffer
• Integer load data alignment and formatting
• Integer store data alignment and formatting.
The pipeline accepts one load or store per cycle that can be present in either pipeline 0 or pipeline 1. This
gives the processor flexibility when scheduling load and store instructions.
14.2.1.6
L2 Cache
The L2 cache unit includes the L2 cache and the Buffer Interface Unit (BIU). It services L1 cache misses
from both the instruction fetch unit and the load/store unit.
14.2.1.7
NEON
The NEON unit includes the full 10-stage NEON pipeline that decodes and executes the NEON media
instruction set. The NEON unit includes the following:
• NEON instruction queue
• NEON load data queue
• Two pipelines of NEON decode logic
• Three execution pipelines for NEON integer instructions
• Two execution pipelines for NEON floating-point instructions
• One execution pipeline for NEON and VFP load/store instructions
• VFP engine for full execution of the VFPv3 data-processing instruction set.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-5
14.2.1.8
Processor Debug Unit
The processor debug unit assists in debugging software running on the processor. In combination with a
software debugger program, the debug unit enables debugging the following:
• Application software
• Operating systems
• Hardware systems based on an ARM processor
The debug unit enables the following:
• Stopping program execution
• Examining and altering processor and coprocessor states
• Examining and altering memory and input/output peripheral states
• Restarting the processor core
14.2.1.9
Embedded Trace Macrocell (ETM)
The ETMv3.3 unit is a nonintrusive trace macrocell that filters and compresses an instruction and data
trace for use in system debugging and system profiling. The ETM unit has an external interface outside of
the processor called the Advanced Trace Bus (ATB) interface.
The Cortex-A8n Processor ETM provides real time instruction trace for the Cortex-A8n Processor. It is
designed to be used with the CoreSight Design Kit. Unlike previous versions of the ARM platforms, this
ETM is embedded inside the Processor Core.
Real time tracing is controlled by specifying a set of filtering and triggering resources which include
address and data comparators, counters and sequencers. Note that although data trace cannot be enabled,
the ETM can still trigger based on data values. Also, the ETM can trace data address values.
The Cortex-A8n Processor ETM contains the following main components:
• Core interface
• Trace generation
• Filtering and triggering resources
• Main FIFO
• AMBA 3 ATB interface
• AMBA 3 APB interface
14.2.1.10 Cross Trigger Interface 0 (CTI0)
This block controls the Trigger Interface (TI). The CTI combines and maps the trigger requests, and
broadcasts them to all other interfaces on the ECT as channel events. When the CTI receives a channel
event it maps this onto a trigger output. This enables subsystems to cross trigger with each other. The
receiving and transmitting of triggers is performed through the TI.
Each CTI has eight trigger inputs, eight trigger outputs, and four sets of 4-channel I/O(s).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-6
Freescale Semiconductor
14.3
Summary of Remaining Platform Components
This section provides a summary of the platform components that have not been previously discussed.
14.3.1
Platform Controller
The Platform Control contains all the miscellaneous logic required for the platform. The main purpose of
the Platform Control module within the Cortex-A8n Core Platform is to implement a set of control and/or
status registers and associated logic for the management of certain platform functions such as internally
generated clocks, debug enable/status, low-power control, platform version ID, and others.
The Platform Control Module provides these main features:
• Simple IPbus interface with TrustZone type security to all registers.
• Internal clock generation with the ability to programatically set the frequency (divide-by) for each
clock independently.
• Ability to force (down-counter) preload for any one or more clocks at anytime independent of
preload set.
• Provides a gated clock for the IPbus asynchronous bridge for power savings.
• Provides 16 bits of General Purpose register bits for routing out to Platform boundary.
• Provides 8 bits of Platform Internal Control register bits for external Platform (SoC) use.
• Provides a set of Low Power control and status bits.
• Control bit to enable Debug along with Debug active status bit.
• NEON activity monitor which can be used in determining when to disable NEON thus saving
power.
14.3.1.1
Debug Sub-Blocks
The Cortex-A8n Core Platform debug blocks are part of the overall Coresight debug system, which
includes the ETB, CTM, CTI1, ATB replicator, and APB address decode. It is expected that a DAP module
and one or more additional CTI will be included at the SoC level. This section gives a brief overview of
the modules that are implemented within the Cortex-A8n Core Platform platform. For details of the full
Coresight debug subsystem, please refer to the SoC debug section.
14.3.1.1.1
Embedded Trace Buffer (ETB)
The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts trace data from the
Cortex-A8n ETM via an ATB port (passing through a replicator in between). Providing an on-chip buffer
alleviates the pin count, bandwidth, and pad design requirements associated with sending trace data to a
debugger directly through package pins in a real-time fashion.
The features are as follows:
• 4kB compiled memory for the trace buffer and optionally can be used as a general purpose memory
• Only 32-bit accesses to the 4kB buffer is supported
• AMBA Peripheral Bus programming interface for configuration and memory access
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-7
14.3.1.1.2
AMBA Trace Bus (ATB) Replicator
The ATB Replicator enables two trace sinks (ETB and an off platform port generally connected to a Trace
Port Interface Unit—TPIU) to be wired together and receive ATB trace data from the same trace source
(ETM). There are no programmable registers. It takes incoming trace data from a single source (ETM) and
replicates it as multiple masters.
The CSREPLICATOR is part of the ARM platform. Two output master ports are required for this
design—one for the on-platform ETB and one for the off-platform TPIU. Placing the TPIU off platform
allows future debug trace sources to connect to the TPIU via a FUNNEL without the need to modify the
ARM platform.
14.3.1.1.3
Cross Trigger Interface 1 (CTI1)
This block controls the Trigger Interface (TI). The CTI combines and maps the trigger requests as well as
broadcasts them to all other interfaces on the ECT as channel events. When the CTI receives a channel
event, it maps this onto a trigger output. This enables subsystems to cross trigger with each other. The
receiving and transmitting of triggers is performed through the TI.
Each CTI has eight trigger inputs, eight trigger outputs, and four sets of 4-channel I/O(s).
14.3.1.1.4
Cross Trigger Matrix—CTM
The CTM controls the distribution of channel events. It provides channel interfaces to the CTIs. The CTM
can also connect to another CTM via a channel interface. This allows multiple CTMs to be connected.
The Cortex-A8n Core Platform has one CTM inside the platform to handle events between the platform’s
CTI, the processor’s CTI and the rest of the ECT system outside the platform. Placing a CSCTM on
platform minimizes the event cycle time between the ETB and the ETM. The handshaking between the
CTIs on-platform and the on-platform CTM are not enabled. This requires the Cortex-A8n’s CTI, the
on-platform CTI1, and the on-platform CTM to all be in the same clock domain. The on-platform CTM
connects to the ECT system via an off-platform CTM and the respective channels require synchronizing
and handshaking enabled.
14.3.1.1.5
Advanced Peripheral Bus—APB Debug Bus
The APB originates off platform generally from a Debug Access Port—DAP block. This bus allows access
to the registers in all of the debug modules that have addressable registers.
14.3.1.2
Asynchronous Wrapper
The Cortex-A8n Core Platform hard macro contains synchronizers for most signals into and out of the
platform where synchronization is required. This means the Cortex-A8n Core Platform can function
asynchronously from the rest of the SoC.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-8
Freescale Semiconductor
14.3.2
Configuration
There are several configuration options associated with the Cortex-A8n Processor. These are determined
at the platform level and selected as follows:
• The L1 cache size is 32 Kb instruction and 32 Kb data
• There is parity on the L1 cache
• There is no error correction on the L1 cache
• The L2 cache size is 256 Kb
• There is no parity on the L2 cache
• There is no error correction on the L2 cache
• There are 2 L2 tag banks and 4 data banks per tag bank
• The AXI data bus width out of the platform is 64-bit
14.3.3
Endian Modes
The Cortex-A8n Core Platform only supports little-endian mode.
14.3.4
Bus Interfaces
This section discusses the major bus interfaces of the Cortex-A8n Core Platform. The Cortex-A8n
Processor has the following bus interfaces:
• AMBA AXI interface
• APB CoreSight interface
• ATB CoreSight interface
• Peripheral Interface (IP Bus)
14.3.4.1
AMBA AXI Interface
The AXI bus interface is the main interface to the system bus. It performs L2 cache fills and non-cacheable
accesses for both instructions and data. The AXI interface utilizes a 64-bit wide input and output data
buses. It also supports multiple outstanding requests on the AXI bus. The AXI bus is allowed to be
asynchronous between the platform and SoC domains. This provides maximum flexibility at the SoC level.
14.3.4.2
APB CoreSight Interface
The APB is an AMBA bus used for debugging. The CoreSight interface is the ARM architecture for
multi-processor trace and debug. It defines what debug and trace components are required and how they
are connected. The platform Debug APB should be connected to the SoC Debug Access Port (DAP) APB
mux. The APB is allowed to be asynchronous between the platform and SoC domains. This provides
maximum flexibility at the SoC level.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-9
14.3.4.3
ATB CoreSight interface
The ATB is a trace output bus used for debugging. The CoreSight components are programmed with the
Debug Access Port (DAP) using the APB programming bus. Trace is output over the ATB trace bus. The
ATB is allowed to be asynchronous between the platform and SoC domains. This provides maximum
flexibility at the SoC level.
14.3.4.4
Peripheral Interface (IP Bus)
The IP Bus interface to the platform connects the on-chip registers to the memory map and internal buses
at the SoC level. Location (addresses of the registers) is determined at the SoC level. The platform acts as
a slave to an SoC-based IP Bus controller.
14.4
Memory Map and Register Definition
This section provides a register memory map and register summary.
14.4.1
Register Memory Map
The memory map for Cortex-A8n Core Platform specific registers is shown in Table 14-1. This does not
include the co-processor registers contained in the ARM Cortex-A8n Processor or the ARM Coresight
Debug. For documentation of registers contained in those modules, please refer to the appropriate
technical reference manual.
This register block address space uses 5 address lines which are fully decoded. The space includes 9
registers and 23 unimplemented locations. The unimplemented locations return an error if they are
accessed. Depending on how the SoC decodes the register block, the entire 32-word register block could
alias in the larger memory space.
Table 14-1. Block Memory Map
Address
Register
Acce
ss
Reset Value
Section/Page
R/
0x????_????
14.4.3.1/14-13
General Registers
0xBASE_0000
(PVID)
Platform Version ID
0xBASE_0004
(GPC)
General Purpose Control
R/W
0x0000_FF00
14.4.3.2/14-14
0xBASE_0008
(PIC)
Platform Internal Control
R/W
0x0000_00F0
14.4.3.3/14-16
0xBASE_000C
(LPC)
Low Power Control
R/W
0x0000_0000
14.4.3.4/14-16
0xBASE_0010
(LPC)
NEON Low Power Control
R/W
0x0000_0000
14.4.3.5/14-18
0xBASE_0014
(ICGC)
Internal Clock Generation Control
R/W
0x0000_7777
14.4.3.6/14-18
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-10
Freescale Semiconductor
Table 14-1. Block Memory Map (continued)
Address
Register
Acce
ss
Reset Value
Section/Page
0xBASE_0018
(AMC)
ARM Memory Configuration
R/W
0x0000_0003
14.4.3.7/14-21
0xBASE_0020
(NMC)
NEON Monitor Control
R/W
0x000F_F000
14.4.3.8/14-22
0xBASE_0024
(NMS)
NEON Monitor Status
R/W
0x0000_0000
14.4.3.9/14-23
14.4.2
Register Summary
The conventions in Figure 14-2 and Table 14-2 serve as a key for the register summary and individual
register diagrams.
Always
reads 1
1
Always
reads 0
0
Write 1 BIT Self-clear 0
R/W BIT Read- BIT Writebit BIT
bit
only bit
only bit BIT to clear w1c
N/A
Figure 14-2. Key to Register Fields
Table 14-2. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
?
Unknown at publication time and subject to change.
[signal_name]
Reset value is determined by polarity of indicated signal.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-11
14.4.3
Register Descriptions
Table 14-3 shows the core platform register summary.
Table 14-3. Core Platform Register Summary
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0xBASE_0000
(PVID)
SPEC[31:24]
IMPL[23:16]
MINOR[15:8]
ECO[7:0]
W
R
W
R
0xBASE_0004
(GPC)
DBG
ACT
IVE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NO
AT DBG
CLK
RDY EN
STP
W
R
W
R
0xBASE_0008
(PIC)
W
R
PIC[7:0]
W
R
0xBASE_000C
(LPC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NEO
N
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
0xBASE_0010
(NLPC)
DBG
DSM
DSM
W
R
W
R
W
0xBASE_0014
(ICGC)
R
W
DT_
PRL
D
0
DP_CLK_DIVR
[2:0]
ACL
K_P
RLD
0
ACLK_DIVR[2:0]
IPG
_PR
LD
IPG_CLK_DIVR
[2:0]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-12
Freescale Semiconductor
Table 14-3. Core Platform Register Summary (continued)
Name
R
0xBASE_0018
(AMC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ALP
EN
W
R
W
R
0
IE
0xBASE_0020
(NMC)
0
0
0
0
0
0
0
0
ALP[2:0]
0
NME
PL[19:16]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
PL[15:12]
W
0xBASE_0024
(NMS)
R
NI
W
w1c
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
NOTE
All registers are zero wait-state and all accesses must use a 32-bit word size.
Any other transaction sizes produce a zero wait-state error response.
14.4.3.1
Platform Version ID Register
The platform version ID register (PVID) contains a 32-bit version ID which can be used to link the silicon
to a specific version of the platform database. The version ID should match our release label applied to the
platform database.
The release label uses the following convention:
TIGERP.C65GP.XX.XX.XX.XX.
This register can be accessed by a 32-bit secure/non-secure, user/supervisor, read transaction. Writes
return an error.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-13
0xBASE_0000 (PVID)
31
30
29
R
Access: User/Supv,
Secure/non-Secure
Read
28
27
26
25
24
23
22
21
SPEC[31:24]
20
19
18
17
16
IMPL[23:16]
W
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
?
?
?
R
MINOR[15:8]
ECO[7:0]
W
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
Figure 14-3. Platform Version ID Register
Table 14-4. PVID Field Descriptions
Field
Description
31–24
SPEC[31:24] = Major architectural or significant spec changes
The reset value is unknown at publication of this document and is also subject to change.
23–16
IMPL[23:16] = Implementation changes
The reset value is unknown at publication of this document and is also subject to change.
15–8
MINOR[15:8] = Minor changes (bug fixes, I/O changes)
The reset value is unknown at publication of this document and is also subject to change.
7–0
ECO[7:0] = ECO changes
The reset value is unknown at publication of this document and is also subject to change.
14.4.3.2
General Purpose Control Register
This register contains 16 bits of general purpose control which drive core platform outputs that can be used
within the SoC for general purpose control. This register also contains the DBG_ACTIVE status bit and
DBG_EN control bit for entering Debug mode via a software access to this register.
This register can only be accessed by 32-bit secure supervisor transactions.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-14
Freescale Semiconductor
0xBASE_0004 (GPC)
31
Access: Secure, Privileged
Read-Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
NO
CLK
STP
AT
RDY
DBG
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R DBG
ACTI
VE
W
Reset
R
W
Reset
Figure 14-4. General Purpose Control Register
Table 14-5. GPC Field Descriptions
Field
Description
31
DBGACTIVE - This bit indicates the status of debug. This allows the user to determine if debug has been
enabled either from off platform, via the external DAP_SYS JTAG interface (dbgen_in platform input), or
via software accesses to the DBGEN bit in this register.
If 0, debug is not enabled. Debug clocks are off and debug registers are inaccessible.
If 1, debug is enabled. Debug clocks are on and the debug system is ready to be used.
30–19
Reserved
18
NOCLKSTP - This bit is used to control clock-gating within the CORTEX-A8n. Note that this is distinctly
different than the higher-level (platform-level) clock-gating/low-power control afforded by the other Plat_Ctrl
low-power functionality (i.e. dsm_request along with the DSM and DBG_DSM control bits within the Low
Power Control register).
If 1 (reset state), then all normal clock-gating activity (WFI, NEON, etc.) is overridden and no clock gating
occurs within the CORTEX-A8n. NOCLKSTP, however, has no affect on the higher-level platform
clock-gating, and the low-power functions discussed in the LPC register work as architected.
if 0, then clock-gating within the CORTEX-A8n is enabled. This is the recommended setting in order to
reduce run mode power consumed by the clocking network within the Integer core as well as the Neon
co-processor.
17
ATRDY - If 1, this bit disables the platform boundary ATB interface. In most SoCs, this is connected to a
TPIU. This prevents traces to the ETB from stalling due to the ASYNCATB FIFO overflowing.
If 0, this bit allows the platform boundary ATB interface to be active. In this case, traces to the ETB could
stall due to ASYNCATB FIFO becoming full. This may cause the ETM data loss.
16
DBGEN - Debug enable. This allows the user to manually activate clocks within the debug system.
This register bit directly controls the platform’s dbgen_out output signal which connects to the DAP_SYS
to enable all debug clocks. Once enabled, the clocks cannot be disabled except by asserting the
disable_trace input of the DAP_SYS.
15-0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-15
14.4.3.3
Platform Internal Control Register
This register contains eight bits that drive internal signals which can be used within the platform for
general purpose control. Currently, none of the PIC bits are being utilized.
This register can only be accessed by 32-bit secure supervisor transactions.
0xBASE_0008 (PIC)
R
Access: Secure, Privileged
Read-Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
PIC[7:0]
W
Reset
0
0
0
0
0
0
0
0
1
1
1
1
0
Figure 14-5. Platform Internal Control Register
14.4.3.4
Low-Power Control Register
This register is used to control entry to low-power mode and can only be accessed by 32-bit secure
supervisor transactions.
There exists a platform output, dsm_request, that when asserted, requests the SoC to turn off clocks to
the platform, and optionally deactivate one or more power supplies. DSM can only be entered after the
CPU has executed a WFI instruction, completed all outstanding bus transactions, and all activity at the L2
level has completed. Assertion of either irq_b, fiq_b, or dbg_edbgrq platform inputs cause the CPU
to complete the WFI instruction and result in the negation of dsm_request.
The DSM bit configures the platform to either: block deep sleep mode entry (default), or allow DSM entry
when requested.
The DBG_DSM bit configures the platform to block deep sleep mode entry when debug mode is enabled
(dbgen_in platform input is asserted high). This allows the user to ensure deep sleep mode is not entered
when debug is enabled.
The NEON_RST bit is used for placing the Cortex-A8n NEON processor into, or releasing it from, reset.
This register can only be accessed by 32-bit secure supervisor transactions.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-16
Freescale Semiconductor
0xBASE_000C (LPC)
R
Access: Secure, Privileged
Read-Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DBG
DSM
DSM
0
0
W
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-6. Low-Power Control Register
Table 14-6. LPC Field Descriptions
Field
31–2
Description
Reserved
1
DBGDSM - Debug Deep Sleep Mode Enable
If 1, DSM can be entered (dsm_request will not be blocked) regardless if debug is enabled or not.
If 0, DSM can NOT be entered (dsm_request will be blocked) if debug is enabled
0
DSM - Deep Sleep Mode Enable is used to gate the platform’s dsm_request signal, therefore preventing
the platform from issuing a deep sleep mode request.
If 1, DSM can be entered (dsm_request will not be blocked).
If 0, DSM can NOT be entered (dsm_request will be blocked).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-17
14.4.3.5
NEON Low-Power Control Register
This register is used to place the Cortex-A8n NEON processor into, or release it from, reset. Refer to
Table 14-7 for a description of this control bit.
This register can only be accessed by 32-bit secure supervisor transactions.
0xBASE_0010 (NLPC)
R
Access: Secure, Privileged
Read-Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
NEON
RST
W
Reset
0
0
Figure 14-7. Low Power Control Register
Table 14-7. NLPC Field Descriptions
Field
31-1
0
14.4.3.6
Description
Reserved
NEONRST - Hold the Cortex-A8n NEON in it’s reset state in preparation for a low-power mode.
• If 1, the ARESETNEONn input to the Cortex-A8n is driven low - placing NEON into reset.
• If 0, the ARESETNEONn input to the Cortex-A8n is driven high - releasing NEON from reset.
Internal Clock Generation Control Register
This register is used to control the clock generation circuitry for all derived clocks used within the ARM
platform (ipg_clk, aclk, dbg_atclk, and dbg_pclk). The dbg_pclk clock is generated as a straight
divide-by-2 of dbg_atclk.
NOTE
At reset, all generated clocks are edge aligned and are generated at 8:1. The
dbg_pclk signal requires 1 dbg_atclk clock cycle before it begins clocking
as a divided dbg_atclk.
This register can only be accessed by 32-bit secure supervisor transactions.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-18
Freescale Semiconductor
0xBASE_0014 (ICGC)
Access: Secure, Privileged
Read-Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
W
Reset
R
ACLK
DT_ DT_CLK_DIVR[2:0]
_PRL
PRLD
D
W
Reset
0
1
1
1
0
0
0
1
1
1
0
ACLK_DIVR[2:0]
1
1
1
IPG_ IPG_CLK_DIVR[2:0]
PRLD
0
1
1
1
Figure 14-8. Internal Clock Generation Control Register
Table 14-8. ICGC Field Descriptions
Field
31-12
Description
Reserved
11
DT_PRLD - Debug AMBA Trace Bus Clock Down Counter Preload
Reads always return 0
A write of 0 has no effect. If preload is 0 during a write of a new divide ratio, the down counteris not loaded
with the new value until it reaches 0 (i.e. rolls over).
A write of 1 forces the DBG_ATCLK down counter to preload on the next arm_clk.
10-8
DT_CLK_DIVR[2:0] - Debug AMBA Trace Bus Clock Divide Ratio
These bits control the clock divide ratio for the debug AMBA trace bus (ATB) and GP async interface clocks.
The ATB bus is used to transfer trace messages from the ETM to the ETB or TPIU.
When ETM trace data is being transferred over the ATB to the embedded trace buffer (ETB), the ATB is
capable of running up to half the CPU frequency. However, when ETM trace data is being transferred to
the TPIU to be sent out the trace port, the ATB should be slowed to some appropriate SoC frequency.
DT_CLK_DIVR[2:0] = 0b000 results in
DT_CLK_DIVR[2:0] = 0b001 results in
DT_CLK_DIVR[2:0] = 0b010 results in
DT_CLK_DIVR[2:0] = 0b011 results in
DT_CLK_DIVR[2:0] = 0b100 results in
DT_CLK_DIVR[2:0] = 0b101 results in
DT_CLK_DIVR[2:0] = 0b110 results in
DT_CLK_DIVR[2:0] = 0b111 results in
7
a 1:1 clock ratio
a 2:1 clock ratio
a 3:1 clock ratio
a 4:1 clock ratio
a 5:1 clock ratio
a 6:1 clock ratio
a 7:1 clock ratio
a 8:1 clock ratio
ACLK_PRLD - AXI Master Port Clock Down Counter Preload
Reads always return 0
A write of 0 has no effect. If preload is 0 during a write of a new divide ratio, the down counter is not loaded
with the new value until it reaches 0 (i.e. rolls over).
A write of 1 forces the ACLK down counter to preload on the next arm_clk.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-19
Table 14-8. ICGC Field Descriptions (continued)
Field
6-4
Description
ACLK_DIVR[2:0] - AXI Master Port Clock Divide Ratio
Controls the clock divide ratio for the Tiger CPU AXI bus and GP AXI async interface clocks and clock
enable.
The ratio of clock cycles generated for arm_clk to aclk is: ACLK[2:0] +1 : 1
ACLK_DIVR[2:0] = 0b000 results in a 1:1 clock ratio
ACLK_DIVR[2:0] = 0b001 results in a 2:1 clock ratio
ACLK_DIVR[2:0] = 0b010 results in a 3:1 clock ratio
ACLK_DIVR[2:0] = 0b011 results in a 4:1 clock ratio
ACLK_DIVR[2:0] = 0b100 results in a 5:1 clock ratio
ACLK_DIVR[2:0] = 0b101 results in a 6:1 clock ratio
ACLK_DIVR[2:0] = 0b110 results in a 7:1 clock ratio
ACLK_DIVR[2:0] = 0b111 results in a 8:1 clock ratio
3
2-0
IPG_PRLD - Platform IP-Bus Port Clock Down Counter Preload
Reads always return 0
A write of 0 has no effect. If preload is 0 during a write of a new divide ratio, the down counter is not loaded
with the new value until it reaches 0 (i.e. rolls over).
A write of 1 forces the IPG_CLK down counter to preload on the next arm_clk.
IPG_CLK_DIVR[2:0] - Platform IP-Bus Port Clock Divide Ratio
Controls the clock divide ratio for the Platform Controller and GP async IP-Bus clock and clock enable.
The ratio of clock cycles generated for arm_clk to ipg_clk is: IPG_CLK[2:0] +1 : 1
IPG_CLK_DIVR[2:0] = 0b000 results in a 1:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b001 results in a 2:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b010 results in a 3:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b011 results in a 4:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b100 results in a 5:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b101 results in a 6:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b110 results in a 7:1 clock ratio
IPG_CLK_DIVR[2:0] = 0b111 results in a 8:1 clock ratio
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-20
Freescale Semiconductor
14.4.3.7
ARM Memory Configuration Register
This register is used to configure the ALP inputs to the ARM platform memories. These bits are used to
set the leakage configuration bits on the memories.
This register can only be accessed by 32-bit secure supervisor transactions.
0xBASE_0018 (AMC)
Access: Secure, Privileged
Read-Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
ALPEN
ALP[2:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Figure 14-9. ARM Memory Configuration Register
Table 14-9. AMC Field Descriptions
Field
31-4
3
2-0
Description
Reserved
ALPEN - ALP Enable is used to activate the ALP bits in this register to override the default memory leakage
configuration setting.
If 1, the ALP bits of the memory are over-written with the ALP bits of this register.
If 0, the ALP bits of the memory are driven to the default (reset) value of 3’b011.
ALP[2:0] - Memory leakage configuration bits
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-21
14.4.3.8
NEON Monitor Control Register
This register is used to control the NEON monitor.
This register can only be accessed by 32-bit secure/non-secure supervisor transactions.
0xBASE_0020 (NMC)
Access: Secure, Privileged
Read-Write
31
30
IE
NME
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
19
18
17
16
PL[19-16]
W
Reset
R
PL[15-12]
W
Reset
1
1
1
1
Figure 14-10. NEON Monitor Control Register
Table 14-10. AMC Field Descriptions
Field
Description
31
IE - Interrupt Enable
If 1, the monitor interrupt output is enabled and plat_ctrl_nm_irq_b is asserted when the monitor counter
expires.
If 0, the monitor interrupt output is disabled.
30
NME - NEON Monitor Enable
29-20
Reserved
19-12
PL[19:12] - Preload value for the upper 8 bits of the 16 bit NEON activity counter.
11-0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-22
Freescale Semiconductor
14.4.3.9
NEON Monitor Status Register
This register is used to read the status of the NEON monitor.
This register can only be accessed by 32-bit secure/non-secure supervisor transactions.
0xBASE_0024 (NMS)
R
Access: Secure, Privileged
Read-Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
W w1c
Reset
R
W
Reset
Figure 14-11. NEON Monitor Status Register
Table 14-11. AMC Field Descriptions
Field
Description
31
NI - NEON Idle Status
• 1 - Indicates that the NEON activity counter has expired. plat_ctrl_nm_irq_b asserts if the IE bit is set.
• 0 - Indicates that the NEON activity counter has not expired.
30-0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-23
14.5
Platform Clocks
The clocking strategy of the Cortex-A8n Core Platform can be summarized as follows:
• The Cortex-A8n Core Platform receives one functional clock from the CCM, arm_clk, and several
SoC clocks for boundary synchronization purposes (arm_clk can be completely asynchronous
from any other SoC clocks).
• The Cortex-A8n Core Platform, in conjunction with an external Clock Control Module (CCM),
supports dynamic clock frequency scaling.
• Divided clocks based on arm_clk are generated within the platform for clocking buses which
cannot operate at the high arm_clk frequencies. These divided clock ratios can be configured by
on-platform registers.
— Derived Clocks:
– ipg_clk: This clock is used for IP bus logic.
– aclk: This clock is used for AXI bus logic.
– dbg_atclk: This clock is used for the Debug AMBA Trace logic.
– dbg_pclk: This clock is used for the Debug synchronizer logic.
• Two-level clock gating is employed.
— Module level clock gating is used when possible. A specific module’s clock is gated off when
the module is not in use.
— Register level clock gating is used throughout the platform via power design tools.
• arm_clk may be turned off for various low-power use cases by an external clock control module
that monitors the DSM_request output.
14.6
Platform Power Management
The Cortex-A8n Core Platform contains low voltage logic elements, an asynchronous and level shifted
interface, state retention latches, low leakage power switches, and floating node isolation circuits. These
elements each serves a specific purpose in the power management scheme implemented in the Cortex-A8n
Core Platform. The power management capabilities of the Cortex-A8n Core Platform are summarized in
this section.
14.6.1
Voltage and Frequency Scaling
The Cortex-A8n Core Platform contains structures necessary for the independent voltage scaling of the GP
supply. Voltage and frequency scaling control systems are implemented at the chip level with the
Cortex-A8n Core Platform acting as an object of the control. Asynchronous Interface Logic and
Level-shifting between SOC-logic and ARM-logic have been implemented in the Cortex-A8n Core
Platform to support the voltage and frequency scaling capabilities of the integrated system.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-24
Freescale Semiconductor
14.6.1.1
Asynchronous Interface Logic
Voltage and frequency scaling is most effective when there is a continuum of available frequencies at
which the Cortex-A8n Processor may be clocked. Asynchronous Interface Logic removes the clock ratio
dependencies between the Cortex-A8n Processor and the system in which it operates.
14.6.1.2
Level Shifting between SOC-logic and ARM-logic
Independent voltage scaling of the Cortex-A8n Processor requires a distinct power supply for the GP logic.
Level shifters exist at the interface of the SOC logic and the ARM logic to allow independent voltage
control of the SOC power supply and the ARM power supply.
14.6.2
Power Gating in the Cortex-A8n Core Platform
To reduce standby leakage power consumption, the Cortex-A8n Core Platform contains internal power
supplies that may be completely power gated during wait for interrupt modes. Entry and exit sequences of
power gating modes are completely controlled by programmed operation of the General Power Controller,
so this section only describes what is possible in terms of how the Cortex-A8n Core Platform may be
powered down during wait for interrupt modes.
14.6.2.1
Isolation Circuitry at the Cortex-A8n Core Platform Interface
To power down digital logic correctly, a special interface must exist that protects the system from floating
signals. Such isolation circuitry has been carefully designed in order to allow glitch-free power down
modes of the Cortex-A8n Core Platform.
14.6.2.2
Power Gating the Memory Peripheries
Once the STANDBYWFI mode has been invoked, all of the Cortex-A8n Core Platform memory
peripheries may be power gated by the assertion of both the l1_pwrdwn and the l2_pwrdwn signals. This
significantly reduces the amount of leakage from the GP supply.
14.6.2.3
Retaining the State of the Cortex-A8n Core Platform Registers
The Cortex-A8n Core Platform has been implemented using State Retention Power Gating (SRPG)
register elements. In order to safely enter a power gated mode that includes power gating of the
Cortex-A8n Core Platform high performance logic gates, a sequenced assertion of the srpg_pgrst and
srpg_pg{0-17} signals must occur. Similarly, a sequenced deassertion is necessary when emerging from
power gated states. The required sequences are automatically provided to the Cortex-A8n Core Platform
by the General Power Controller.
14.6.2.4
Power Gating the Cortex-A8n Core Platform High Performance Logic
Gates
Once the STANDBYWFI mode has been invoked, the Cortex-A8n Core Platform high performance logic
gates may be power gated by the assertion of the cpu_powerdown signal and the negation of the
vdd_short_b signal. This turns off a portion of the leakage from the GP supply.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-25
14.6.2.5
Power Gating the L2 Bit Arrays
If the L2 cache has been flushed, the L2 bit array may be power gated during the subsequent
STANDBYWFI mode. Once the STANDBYWFI mode has been invoked, the L2 memory bit arrays may
be power gated by the assertion of the l2bits_powerdown signal. This turns off a portion of the leakage
from the LP supply.
14.6.2.6
Controlling Power Gating using the General Power Controller (GPC)
Specific details concerning the power gating entry and exit sequence may be obtained from the block guide
of the General Power Controller (GPC). This high level summary is intended to provide some overview.
Code must be formed that takes advantage of low workloads by putting the Cortex-A8n Core Platform into
a STANDBYWFI state whenever possible. Prior to entering the STANDBYWFI state, the code should
assess several things about the workload and the battery conservation requirements:
• What is the maximum acceptable interrupt service latency?
• What is the expected time to be spent in STANDBYWFI?
Once these time requirements are understood, then Table 14-12 can be used to determine the appropriate
STANDBYWFI mode to invoke. The GPC registers can be programmed with the appropriate values to
invoke the appropriate STANDBYWFI mode. After GPC programming is complete, the code should
execute the STANDBYWFI instruction.
The GPC enforces the appropriate sequence for entering and exiting the programmed power gated modes.
14.6.2.7
Power Gating the NEON Block
The NEON co-processor in the Cortex-A8n Processor can be put into a state retention mode and powered
down to reduce current consumption when it is not needed. The sequence is shown in the flow diagram of
Figure 14-12. Each box in the diagram is numbered to correspond to the following more thorough
description:
1. User Selects NEON to be Powered Down
The NEON Coprocessor is enabled out of reset and remains powered up unless the user decides
to power it down. This method power downs NEON after a user programmable time of NEON
inactivity. The current state of the NEON is held in SRPG flops. To select this operation:
a) The user code programs the amount of time that the NEON needs to be inactive before
power down in the NEON Monitor Control Register. Effectively, the user programs the
upper 8 bits of a 20-bit counter. This counter runs at the arm_clk rate and so the user can
program a timeout from 4K to 1M arm_clk rising edges.
b) In the same register, the user code enables the NEON Monitor and enables the NEON
Monitor Interrupt.
2. Pre-Set Timer Count
The timer is loaded (automatically by hardware) with the count value chosen by the user.
3. Decision: NEON Instruction Encountered?
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-26
Freescale Semiconductor
If a NEON instruction is encountered the sequence is aborted until the NEON is no longer in
use. As long as NEON Instructions are executing, the NEON status bit will remain in the active
state and the counter gets forced with the pre-set count.
4. Decrement Timer
When no NEON instructions are encountered, the timer counts towards the timeout.
5. Decision: Timed Out?
If the user selected time has lapsed without any NEON activity, then the hardware generates an
interrupt.
6. Exception Sequence: Power Down NEON
The interrupt service routine disables the NEON module with the following sequence:
a) Software must disable access to the NEON unit using the Coprocessor Access Control
Register, see c1, Coprocessor Access Control Register on page 3-64 of the Cortex-A8n
TRM. All outstanding NEON instructions retire and all subsequent NEON instruction cause
an Undefined instruction exception.
MRC p15, 0, <Rd>, c1, c0, 2; Read Coprocessor Access Control Register
BIC <Rd>, <Rd>, #0xF00000; Disable access to CP10 and CP11
MCR p15, 0, <Rd>, c1, c0, 2; Write Coprocessor Access Control Register
b)
c)
d)
e)
Activate the NEON output clamps.
Place NEON into state retention.
Prepare the NEON memory for power down keeping the state of it’s bits.
Separate the NEON power supplies so that the ones that retain state can continue to have
power.
f) Remove power from the NEON power domain.
7. Decision: NEON Instruction Attempted
The part continues running regular CPU instructions with the NEON in low power state as long
as no NEON instructions are attempted. When a NEON instruction is attempted, an
unimplemented instruction exception occurs.
8. Exception Sequence: Power Up NEON
An exception is taken when a NEON instruction is attempted with the NEON is disabled. The
exception routine determines that this is indeed what occurred, enables the NEON module, and
waits for the NEON to power up. Returning from the exception causes the NEON instruction
to be restarted and run successfully. This is a more detailed description of the sequence:
a) Power is turned on to the NEON power domain.
b) Reconnect the NEON power supplies together.
c) Restore the NEON memory power maintaining the state of it’s saved bits.
d) Reload the flops with the SRPG saved contents.
e) Release the NEON output clamps.
f) Software must enable access to the NEON unit using the Coprocessor Access Control
Register, see c1, Coprocessor Access Control Register on page 3-64 of the Cortex-A8n
TRM.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-27
MRC p15, 0, <Rd>, c1, c0, 2; Read Coprocessor Access Control Register
ORR <Rd>, <Rd>, #0xF00000; Enable access to CP10 and CP11
MCR p15, 0, <Rd>, c1, c0, 2; Write Coprocessor Access Control Register
g) Return from the exception causing the NEON instruction to be reloaded and executed.
1. User Selects NEON to be
Powered Down
2. Pre-set Timer Count
3. NEON
Instruction
Yes
No
4. Decrement Timer
No
5. Timed
Out?
Yes
6. Exception Sequence:
Power Down NEON
7. NEON
Instruction
No
Yes
8. Exception Sequence:
Power Up NEON
Figure 14-12. Flow Diagram of NEON Power Down Sequence
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-28
Freescale Semiconductor
14.6.3
Modes of Operation
There are several basic low-power modes of the Cortex-A8n Core Platform, as presented in Table 14-12.
Table 14-12. Modes of Operation of the Cortex-A8n Core Platform
MODE
Description
RUN
ARM_CLK running, code executing
CLOCKED_WAIT
ARM_CLK running, STANDBYWFI=TRUE
UNCLOCKED_WAIT
ARM_CLK off, STANDBYWFI=TRUE
STOP1
UNCLOCKED_WAIT plus L1 and L2 peripheries power gated
STOP2
UNCLOCKED_WAIT plus L1 and L2 peripheries power gated, ARM_HiP_logic power
gated
STOP3
UNCLOCKED_WAIT plus L1 and L2 peripheries power gated, ARM_HiP_logic power
gated, L2 cache flushed, and L2 bit arrays power gated
There are several combinations of reduced power in which one of more portions of the platform are in a
power saving mode. This is shown in Table 13.
Table 13. Platform Power Modes
Core and Platform
NEON
L1
L2
Powered Up
Powered Up
Powered Up
Powered Up
Powered Up
Reset (ARM Mode)
Powered Up
Powered Up
State Retention
State Retention
State Retention
State Retention
State Retention
State Retention
Powered Down
State Retention
State Retention
State Retention
State Retention
Powered Down
State Retention
State Retention
Powered Down
Powered Down
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
14-29
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
14-30
Freescale Semiconductor
Chapter 15
Platform Debug
15.1
Introduction
This chapter provides an overview of the ARM platform debug. It covers the modules inside the
tigerp_gp_debug block and the modules that support the platform debug within the SOC, but external to
the ARM platform.
Debug for the ARM platform uses ARM’s DK11 CoreSight Debug Kit. The following CoreSight modules
are used: DAP, ETM, CSREPLICATOR, CSTPIU, CSETB, CSCTI, and the CSCTM. This introduction
provides a brief description of each module. For more in-depth information, please refer to the
CoreSight_DK_TRM and other relative documentation from ARM.
15.1.1
Overview
ARM’s CoreSight Design Kit (CSDK) provides a single solution for multi core and bus trace. The CSDK
provides the following capabilities for system-wide trace:
• Debug and trace visibility of the entire system
• Cross-triggering support between SOC subsystems
• Multisource trace in a single stream
• Higher data compression than previous solutions
• Standard programmer’s models for standard tools solutions
The CoreSight Design Kit comprises the following main components: control and access, sources, links,
and sinks.
• Control and access components configure, access, and control the generation of trace. They neither
generate nor process trace data. Examples include the DAP (debug access port) and the ECT
(embedded cross trigger interface).
• Source components generate trace data. Example source components are the ETM (embedded
trace macrocell) and the future XTM (AXI trace macrocell).
• Link components provide connection, triggering and flow of trace data. Link examples include the
ATB replicator and the CoreSight Trace funnel.
• Sink components are the end point for trace data on an SOC. Example sinks are the TPIU (trace
port interface unit) and the ETB (embedded trace buffer).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-1
Figure 15-1. shows the ARM Platform debug block diagram. Further detail of the modules shown in the
diagram are given in the next sections.
I
To System AHB
ARM PLATFORM
LITE2AHBI
JTAG
PAD
Ahb2Apb
AHB Access
DAP
AHB
JTAG
AP
DP
JTAG
AP
Decoder APB
AP
Cortex A8N Platform
Debug Unit
ETM
ATB
APB multiplexer
CTI
From System AHB
Amba Peripheral Bus for Debug
APB Debug Bus
Async
APB
APB Debug Bus
ATB
Trigger
In/Out
APBI/F
ETB
CTI...
Channel
Control
HandshakingRegs
APBI/F
CTM
CTM
CTI1
ATB
ATB
Replicator
Control
Channel Bus To CTM Channel
HandshakingRegs
Channel Bus From CTM
Mapping
32-bit
Trigger
Handshaking
Mapping
32-bit
Trigger
Handshaking
Async
ATB
Trigger I/O
TPIU
TRACE PORT
TRACECLKIN
TRACECLK
TRACEDATA[M
TRACECTL
APB
Figure 15-1. ARM Platform Debug Block Diagram
15.1.2
ARM Debug Modules
This section provides an overview of the Debug modules used in the ARM platform and also the modules
outside the platform that are included in the CoreSight debug system.
The following modules are included in the ARM platform debug block: CSETB, CSCTI, CSCTM,
CSREPLICATOR, and APB address decode logic.
The following modules are part of the ARM platform, outside the debug block: ETMv3.3 (embedded in
the Cortex), CTI (also embedded in the Cortex), the Processor Debug Unit, and two asynchronous bridges:
the asyncapb and the asyncatb.
Also included in this block guide is an overview of the DAP and TPIU that reside outside the ARM
platform, yet are key components to the debug system.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-2
Freescale Semiconductor
15.1.2.1
Processor Debug Unit
The processor debug unit assists in debugging software running on the processor. In combination with a
software debugger program, the debug unit enables debugging the following:
• Application software
• Operating systems
• Hardware systems based on an ARM processor
The debug unit enables the following:
• Stopping program execution
• Examining and altering processor and coprocessor states
• Examining and altering memory and input/output peripheral states
• Restarting the processor core
There are three ways to debug software running on the processor, as follows:
• Halt debug-mode debugging
• Monitor debug-mode debugging
• Trace debugging (ETM) (covered in a different section)
15.1.2.1.1
Halting Debug Mode Debugging
Halting debug-mode debugging is invasive. The processor halts when a debug event, such as a break point,
occurs. An external debugger can examine and modify the processor state via the APB while the processor
is halted.
15.1.2.1.2
Monitor Debug Mode Debugging
When a debug event occurs during monitor debug-mode debugging, instead of halting the processor, the
processor takes an exception. Special software can then take control to examine or alter the processor state.
When execution of a monitor target starts, the state of the processor is preserved in the same manner as all
ARM exceptions.
15.1.2.1.3
Programming the Debug Unit
The processor unit is programmed using the APB slave port. Features that can be accessed using the
memory-mapped APB registers are as follows:
• Instruction address comparators for triggering break points
• Data address comparators for triggering watchpoints
• A bidirectional Debug Communication Channel (DCC)
• All other state information associated with the debug unit
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-3
15.1.2.2
ARM Platform ETM
The ETM provides real time instruction trace for the Cortex A8N processor. It is designed to be used with
the CoreSight Design Kit. Unlike previous versions of the ARM platforms, this ETM is embedded inside
the Core.
Real time tracing is controlled by specifying a set of filtering and triggering resources which include
address and data comparators, counters, and sequencers. Note that although data trace cannot be enabled,
the ETM can still trigger based on data values. Also, the ETM can trace data address values.
The ETM contains the following main components:
• Core interface
• Trace generation
• Filtering and triggering resources
• Main FIFO
• AMBA 3 ATB interface
• AMBA 3 APB interface
The ETM provides a number of configurations. Table 15-1 shows the options implemented in the ETM.
Table 15-1. ETMv3.3 Configurations
Resource Description
Configuration
Instruction trace
Yes
Data address trace
Yes
Data value trace
No
Jazelle trace
-
Address comparator pairs
2
Data comparator
4
Context ID comparators
1
Sequencer
Yes
Start/stop block
Yes
Embedded ICE comparators
0
External inputs
4
External outputs
2
Extended external inputs
49
Extended external input selectors
2
Instrumentation resources
4
FIFO full
No
FIFO full level setting
N/A
Branch broadcasting
Yes
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-4
Freescale Semiconductor
15.1.2.3
Resource Description
Configuration
ASIC control register (bits)
8
Data suppression
Yes
Software access to registers
Memory
Readable registers
Yes
FIFO size
128 bytes
Minimum port size
32
Maximum port size
32
Port modes
Dynamic
Asynchronous ATB
Yes
Load pc first
No
Fetch comparisons
No
CSETB
The ETB provides on chip storage of trace data. The ARM platform implements a 32-bit 4K RAM.
The ETB accepts trace data from a CoreSight replicator via an ATB write port. The ETB is configurable
through an APB port.
Features are as follows:
• 4-Kbyte compiled memory for the trace buffer. Note: It can no longer be used as a general purpose
memory.
• Only 32-bit accesses to the 4-Kbyte buffer is supported (Note: RAM size is 4K “bytes”— i.e.
1K × 32)
• Amba Peripheral Bus interface for configuration and memory access
15.1.2.4
CSREPLICATOR
The ATB Replicator enables two trace sinks (TPIU and ETB) to be wired together and receive ATB trace
data from the same trace source (ETM). There are no programmable registers. It takes incoming trace data
from a single source (ETM) and replicates it to two master ports.
The CSREPLICATOR is part of the tigerp_gp_debug block. Two output master ports are required for this
design: one for the on-platform ETB and one for the off-platform TPIU. Placing the TPIU off platform
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-5
allows future debug trace sources to connect to the TPIU via a FUNNEL, without the need to modify the
ARM platform. Figure 15-2 shows a block diagram for the CSREPLICATOR.
Figure 15-2. CSREPLICATOR Block Diagram
ATB Output
Master Port 0
ATB Input
Slave Port
ATB Output
Master Port 1
15.1.2.5
CSTPIU
The TPIU acts as a bridge between on-chip trace data, ID distinguishable, and a TPA. It receives ATB trace
data and sends it off chip via ARM’s standard trace signals TRACECLK, TRACEDATA, and
TRACECTL. The following submodules are included in the TPIU (see Figure 15-3): ATB interface, APB
interface, Formatter, Asynchronous FIFO, Register bank, Trace out serializer, and a Pattern generator.
Further information on the TPIU can be found in ARM’s technical reference manuals.
The TPIU is not on the ARM platform and is configurable via the APB.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-6
Freescale Semiconductor
ATCLK domain
TPIU
ATB slave
port
APB slave
port
ATB
i/f
Formatter
APB
i/f
Asynchronous
FIFO
Register bank
Trace out
TRACECLKIN
TRACECLK
TRACEDATA[MPS:0]
(serializer)
TRACECTL
Pattern
generator
PCLK domain
Trigger Flush EXTCTL
control control
Bus
Figure 15-3. TPIU Block Diagram
All signal paths to the pads are subject to wire delays. Special consideration should be taken to re-balance
the paths, removing the relative skews between the signals. An extra delay must be added on the
TRACECLK path to ensure its rising and falling edge are during the stable part of TRACEDATA and
TRACECTL.
15.1.2.6
CSCTI
The CSCTI is the CoreSight Cross Trigger Interface component of a ECT (Embedded Cross Trigger)
system. The CSCTI combines and maps trigger requests and broadcast them to all other interfaces on the
ECT as channel events. This enables subsystems to cross trigger with each other.
Each CTI has eight trigger inputs, eight trigger outputs, and four sets of 4-channel I/O(s). There are also
acknowledge signals, configurable on/off, for the trigger and channel outputs. The channels connect to a
CSCTM (CoreSight Cross Trigger Matrix). The CSCTM is off platform so special consideration should
be taken for enabling the synchronizers and handshaking features on both the CSCTI and the CSCTM.
The platform requires one CTI module in addition to the embedded CTI in the ARM core. CTI0 resides in
the Core and handles triggers/events from the CSETM and the CORE. Where as CTI1 handles the
trigger/events for the TPIU (off platform) and the CSETB. Because the TPIU is outside the platform
(asynchronous), the TRIGIN synchronizers are enabled and handshaking is turned on.
The on-platform CTI1 is synchronous and at the same clock speed as the on-platform CTM. This allows
the channel handshaking and channel synchronizers to be bypassed.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-7
Figure 15-4 shows the recommended connections for CSCTI1
Figure 15-4. CSCTI1 Connections
SOC
ARM Platform
CTMCH3
CSETB
CSCTI1
ACQCOMP
FULL
FLUSHIN
FLUSHINACK
TRIGIN
TRIGINACK
TRIGIN[3]
TRIGIN[2]
TRIGOUT[4]
TRIGOUTACK[4]
TRIGOUT[5]
TRIGOUTACK[5]
CTICHOUT
CTICHOUTACK
CTICHIN
8’b00001100
8’b00110000
8’b00000000
1’b1
4’b0
1’b1
TISBYPASSIN
TISBYPASSACK
TIHSBYPASS
CISBYPASS
CIHSBYPASS
CSCTM
CTMCHOUT2
CTMCHOUTACK2
CTMCHIN2
CTMCHINACK2
Note: CTMCH0 connects
to Cortex CTI channel
interface - no HS
CTMCHIN1
CTMCHINACK1
CTMCHOUT1
CTMCHOUTACK1
Note: Hand shaking (HS) is only enabled for
CTMCH2 and CTMCH3
CSCTM
CTMCHIN0
CTMCHINACK0
CTMCHOUT0
CTMCHOUTACK0
CTMCH1-3 to be used
with remaining SOC
cross-trigger components
If only 2 CTIs are
required in the external
SOC, this CTM is opttional.
CSTPIU
Trace Port
CTIAPBSBYPASS
TRIGOUT[2]
TRIGOUTACK[2]
TRIGOUT[3]
TRIGOUTACK[3]
FLUSHIN
FLUSHINACK
TRIGIN
TRIGINACK
The SOC CTIs require additional logic to support asynchronous trigger source/destinations. The
cscti_extended module includes logic, in addition to the CSCTI module, to support triggering across
asynchronous boundaries where the source/destination might not have the necessary logic to support
asynchronous boundaries.
15.1.2.7
CSCTM
This block controls the distribution of channel events. It provides channel interfaces to the CSCTIs. The
CSCTM can also connect to another CSCTM via a channel interface. This allows multiple CSCTMs to be
connected.
The platform has one CSCTM inside the platform to handle events between the platform’s CSCTIs and
the rest of the ECT system outside the platform. Placing a CSCTM on platform minimizes the event cycle
time between the ETB and the ETM. The handshaking between the CTIs on-platform and the on-platform
CTM are not enabled. This requires the Cortex’s CTI, the on-platform CTI1 and the on-platform CTM to
all be in the same clock domain. The on-platform CTM connects to the ECT system via an off-platform
CTM and the respective channels require synchronizing and handshaking enabled.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-8
Freescale Semiconductor
If only two CTIs are required in the SOC, they can be connected directly to the on-platform CTM
eliminating the need for a CTM outside the platform.
More information on the CoreSight ECT system can be found in ARM’s Technical Reference manuals.
15.1.2.8
DAP
The DAP provides multiple master driving ports, all accessible via a single external interface port.
Components that access the DAP are called Debug Ports (DP) and components that access internal
interfaces are called Access Ports (AP).
The DAP provides real-time access for the debugger without halting the core to the following:
• All debug configuration registers
• AMBA system memory and peripheral registers.
The DAP enables debug access to the complete SOC via a number of access ports. Access to the CoreSight
Debug APB is enabled through the APB access port (APB-AP). System access can be accomplished via
an AHB access port (AHB-AP). An APB multiplexor allows system accesses to debug CoreSight
components connected to the APB.
There is also a JTAG access port (JTAG-AP) providing accesses to on-chip JTAG components. The DAP
acts as a JTAG master. This feature is not used for the ARM platform because the core’s debug logic is
now accessible via the APB.
Figure 15-5 shows a block diagram of the DAP.
System
AHB Access
DAP
Decoder
System Access to
Debug APB
DAPSEL0
AHB Access Port (AHB-AP)
JTAG
JTAG Interface
DAPCLK
DAPSEL1
HCLK
APB Access Port (APB-AP)
APB
Multiplexer
DAPCLK
Debug
APB
ROM
Table
DEVICEEN
DAPSEL2
JTAG Access Port (JTAG-AP)
JTAG
Scan Chains
DAPCLK
Figure 15-5. DAP Block Diagram
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-9
15.1.2.8.1
DAP_SYS
The DAP also requires decode logic for the CoreSight component PSEL signals, an AHB to APB bridge,
an AHB lite to AHB bridge, detect logic to enable debug and reset synchronization logic. The dap_sys
module wraps these components with the DAP. Figure 15-6 shows a block diagram of the DAP_SYS.
DBGEN
System AHB
DAP_SYS
rst and dbg detect
jtag_tms
DBGEN
TMS Detect Logic
APB
Decode
AHB
TO
APB
PSLVERR(s)
PREADY(s)
PSEL(s)
APB
DAP
PADDRDBG
JTAG
APB
nTRST
nDBGPORST
JTAG_TRESET_B
VDD
AHBLite
1
0
LITE
TO
AHB
nDBGRESET
POTRST
R
AHB
R
dap_ao_clock
CSJTAG
any_scan_mode
nDBGRESET
nDBGPORST
DAPCLKao
TCK
HCLK
PCLKDBG
PCLKSYS
Figure 15-6. DAP_SYS Block Diagram
15.1.3
15.1.3.1
Modes of Operation
ARM Invasive Debug Mode
ARM Invasive Debug mode is usually entered via the JTAG port. Inside the dap_sys there is logic to assert
DBGEN high when jtag_tms is active. The user can also invoke DBGEN by writing to a register inside the
tiger plat_ctrl module.
It is required that NIDEN is asserted while DBGEN is asserted. Otherwise, CTI functionality is limited
when TINIDENSEL is tied to 0. Due to this requirement, NIDEN into the Core and the Debug block is a
combination of dbg_niden ored with dbgen_in.
15.1.3.2
ARM Non-Invasive Debug Mode (Real-Time Trace)
There are two methods to enter non-invasive debug mode: through JTAG or via memory mapped accesses.
For memory mapped accesses, non-invasive debug can be enabled by writing to two secure supervisor
registers, one within the CSU and one within the ARM platform.
15.1.3.3
Normal-Operating Modes
During normal operating mode, debug is not enabled.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-10
Freescale Semiconductor
15.1.3.4
Low-Power Modes
During deep sleep mode (DSM) all debug is disabled. The platform_ctl module has a bit allocated to
overriding DSM when debug is enabled. This bit currently resets to a state disabling DSM while debug is
enabled. For more information, refer to the platform control block guide.
The core has an input, DBGNOCLKSTOP, allowing the core’s debug clocks to stay on while in WFI. The
same bit used to override DSM should be connected to DBGNOCLKSTOP (inverted).
15.2
Memory Map and Register Definition
Each CoreSight component has an allocated 4K. CoreSight components are part of either CoreSight Class
or ROM Class. Figure shows the CoreSight class layout for a 4-Kbyte block.
{
Address
Offset
0x000
CoreSight component-specific
registers
4-Kbyte Block
0xEFC
0xF00
0xFCC
0xFD0
CoreSight Management Registers
}
PrimeCell Identifiers
0xFFC
Figure 15-7. CoreSight Component Memory Map
Table 15-2 shows an example Debug memory map. The most significant half word of the address changes
based on the chip-level memory map.
Table 15-2. Block Memory Map
Start Address
End Address
Size
Target IP
Comments
B0C00000
B0C00FFF
4K
Debug ROM
Located inside DAP
B0C01000
B0C01FFF
4K
ETB
—
B0C02000
B0C02FFF
4K
ETM
—
B0C03000
B0C03FFF
4K
TPIU
—
B0C04000
B0C04FFF
4K
CTI0
On platform
B0C05000
B0C05FFF
4K
CTI1
On platform
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-11
Table 15-2. Block Memory Map (continued)
Start Address
End Address
Size
Target IP
Comments
B0C06000
B0C06FFF
4K
CTI2
Off platform
B0C07000
B0C07FFF
4K
CTI3
Off platform
15.2.1
Register Summary
This section summarizes the CoreSight Component registers in a table format. The tables are divided by
Components. For a more detailed description of each register, refer to the CoreSight_DK_TRM.
The conventions in Table 15-3 serve as a key for the register summary.
Table 15-3. Register Conventions
Register Field Types
RO
Read only. Writing this bit has no effect.
WO
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
RAZ
Read-as-zero
WI
Writes ignored
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
15.2.1.1
DAP JTAG DP Registers
Accessing a JTAG DP register depends on both the instruction register (IR) value of the DAP access and
the address field of the DAP access.
Table 15-4 shows a register summary table for the DAP DP. Detailed register descriptions can be found
inside the CoreSight_DK_TRM provided by ARM.
Table 15-4. DAP JTAG DP Registers
1
Address Field
IR Contents
Type
Register Name
1
IDCODE
RO
Identification Control Register
0x0
DAPACC
RAZ/WI
Reserved
0x4
DAPACC
R/W3
DP Control/Status Register
0x8
DAPACC
R/W
Select Register
0x0
ABORT
WO 2
DAP Abort Register
0x4-0xC
ABORT
2
Reserved
There is no address associated with the ID code register. For more information, see the CoreSight_DK_TRM.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-12
Freescale Semiconductor
2
The value read on the abort scan chain is unpredictable. The result of accessing the abort scan chain without the address set
to 0x0 is unpredictable.
15.2.1.2
DAP ROM Register Summary
The ROM table stores the locations of components on the debug APB. The DAP ROM is read only and
configurable through the DAPROM.v and DapRomDefs.v RTL files. Writes are ignored.
Table 15-5 shows a register summary table for the DAP Rom. Detailed descriptions can be found inside
the CoreSight_DK_TRM provided by ARM.
Table 15-5. DAP ROM Registers
Offset
Name
Type
Description
0xFD0
Peripheral ID4
RO
See CoreSight_DK_TRM
0xFD4
Peripheral ID5
RAZ
Reserved
0xFD8
Peripheral ID6
RAZ
Reserved
0xFDC
Peripheral ID7
RAZ
Reserved
0xFE0
Peripheral ID0
RO
See CoreSight_DK_TRM
0xFE4
Peripheral ID1
RO
See CoreSight_DK_TRM
0xFE8
Peripheral ID2
RO
See CoreSight_DK_TRM
0xFEC
Peripheral ID3
RO
See CoreSight_DK_TRM
0xFF0
Component ID0
RO
Set to 0x0D
0xFF4
Component ID1
RO
Set to 0x10
0xFF8
Component ID2
RO
Set to 0x05
0xFFC
Component ID3
RO
Set to 0xB1
15.2.1.3
Processor Debug Unit Register Summary
Most of the debug unit registers are accessible through the APB. There are some registers that can also be
accessed through the coprocessor interface CP14.
By default, CP14 registers can be accessed from a non-privileged mode. However, the processor can be
programmed to disable user access modes using bit [12] of the Debug Status and Control Register (DSCR).
For more information on the DSCR and access to CP14 registers, refer to the CortexA8 TRM document.
15.2.1.3.1
Coprocessor Registers Summary
Table 15-6 shows the valid debug instructions for accessing the debug registers.
Table 15-6. CP14 Debug Registers Summary
Instruction
Mnemonic
Description
MRC p14, 0, <Rd>, c0, c0, 0
DIDR
Debug Identification Register
MRC p14, 0, <Rd>, c1, c0, 0
DRAR
Debug ROM Address Register
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-13
Table 15-6. CP14 Debug Registers Summary
Instruction
Mnemonic
Description
MRC p14, 0, <Rd>, c2, c0, 0
DSAR
Debug Self Address Register
MRC p14, 0, <Rd>, c0, c5, 0
STC p14, c5, <addressing mode>
DTRRX
Data Transfer Register - Receive
MCR p14, 0, <Rd>, c0, c5, 0
LDC p14, c5, <addressing mode>
DTRTX
Data Transfer Register - Transmit
MRC p14, 0, <Rd>, c0, c1, 0
MRC p14, 0, PC, c0, c1, 0
DSCR
Debug Status and Control Register
15.2.1.3.2
Memory-Mapped Registers Summary
Table 15-7 shows a complete list of memory mapped registers accessible using the APB slave port.
Table 15-7. Debug Unit APB Accessible Registers Summary
Offset
Register Number
Mnemonic
Type
Description
0x000
c0
DIDR
R
CP14 c0, Debug ID Register
0x004–0x014
c1–c5
—
R
RAZ
0x018
c6
WFAR
R/W
Watchpoint Fault Address Register
0x01C
c7
VCR
R/W
Vector Catch Register
0x020
c8
—
R
RAZ
0x024
c9
ECR
R/W
Event Catch Register
0x028
c10
DSCCR
R/W
Debug State Cache Control Register
0x02C
c11
—
R
RAZ
0x030–0x07C
c12–c31
—
R
RAZ
0x080
c32
DTRRX
R/W
Data Transfer Register—Receive
0x084
c33
ITR
W
Instruction Transfer Register
0x088
c34
DSCR
R/W
CP14 c1, Debug Status and Control Register
0x08C
c35
DTRTX
R/W
Data Transfer Register—Transmit
0x090
c36
DRCR
W
Debug Run Control Register
0x094–0x09C
c37–c63
—
R
RAZ
0x100–0x114
c64–c69
BVR
R/W
Breakpoint Value Registers
0x118–0x13c
c70–c79
—
R
RAZ
0x140–0x154
c80–c85
BCR
R/W
Breakpoint Control Register
0x158–0x17C
c86–c95
—
R
RAZ
0x180–0x184
c96–c97
WVR
R/W
Watchpoint Value Register
0x188–0x1BC
c97–c111
—
R
RAZ
0x1C0–0x1C4
c112–c113
WCR
R/W
Watchpoint Control Registers
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-14
Freescale Semiconductor
Table 15-7. Debug Unit APB Accessible Registers Summary (continued)
Offset
Register Number
Mnemonic
Type
Description
0x1C8-0x1FC
c114-c127
—
R
RAZ
0x200-0x2FC
c128-c191
—
R
RAZ
0x300
c192
OSLAR
W
Operating System Lock Access Register
0x304
c193
OSLSR
R
Operating System Lock Status Register
0x308
c194
OSSRR
R/W
Operating System Save and Restore Register
0x30C
c195
—
R
RAZ
0x310
c196
PRCR
R/W
Device Power Down and Reset Control Register
0x314
c197
PRSR
R
Device Power Down and Reset Status Register
0x318-0x7FC
c198-c511
—
R
RAZ
0x800-0x8FC
c512-575
—
R
RAZ
0x900-0xCFC
c576-c831
—
R
RAZ
0xD00-0xFFC
c832-c1023
—
-
Management Register
15.2.1.4
ETB Register Summary
The ETB registers are summarized in Table 15-8. Detailed information can be found in ARM’s
CoreSight_DK_TRM document.
Table 15-8. ETB Registers
Offset
Name
Type
Description
0x004
RAM Depth Register, RDP
RO
See CoreSight_DK_TRM
0x010
RAM Read Data Register, RRD
RO
See CoreSight_DK_TRM
0x014
RAM Read Pointer Register, RRP
R/W
See CoreSight_DK_TRM
0x00C
Status Register, STS
RO
See CoreSight_DK_TRM
0x018
RAM Write Pointer Register, RWP
R/W
See CoreSight_DK_TRM
0x01C
Trigger Counter, TRG
R/W
See CoreSight_DK_TRM
0x020
Control Register, CTL
R/W
See CoreSight_DK_TRM
0x024
RAM Write Data, RWD
WO
See CoreSight_DK_TRM
0x300
Formatter and Flush Status
FFSR
RO
See CoreSight_DK_TRM
0x304
Formatter and Flush Control
FFCR
R/W
See CoreSight_DK_TRM
0xEE0
Integration Register
ITMISCOP0
WO
See CoreSight_DK_TRM
0xEE4
Integration Register
ITTRFLINACK
WO
See CoreSight_DK_TRM
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-15
Table 15-8. ETB Registers (continued)
Offset
Name
Type
Description
0xEE8
Integration Register
ITTRFLIN
RO
See CoreSight_DK_TRM
0xEEC
Integration Register
ITATBDATA0
RO
See CoreSight_DK_TRM
0xEF0
Integration Register
ITATBCTR2
WO
See CoreSight_DK_TRM
0xEF4
Integration Register
ITATBCTR1
RO
See CoreSight_DK_TRM
0xEF8
Integration Register
ITATBCTR0
RO
See CoreSight_DK_TRM
0xF00
Integration Mode Control
Register
R/W
See CoreSight_DK_TRM
0xFA0
Claim Tag Set Register
R/W
See CoreSight_DK_TRM
0xFA4
Claim Tag Clear Register
R/W
See CoreSight_DK_TRM
0xFB0
Lock Access Register
WO
See CoreSight_DK_TRM
0xFB4
Lock Status Register
RO
See CoreSight_DK_TRM
0xFB8
Authentication Status
Register
RO
See CoreSight_DK_TRM
0xFC8
Device ID
RO
See CoreSight_DK_TRM
0xFCC
Device Type Identifier
Register
RO
See CoreSight_DK_TRM
0xFD0
Peripheral ID4
RO
See CoreSight_DK_TRM
0xFD4
Peripheral ID5
RAZ
Reserved
0xFD8
Peripheral ID6
RAZ
Reserved
0xFDC
Peripheral ID7
RAZ
Reserved
0xFE0
Peripheral ID0
RO
See CoreSight_DK_TRM
0xFE4
Peripheral ID1
RO
See CoreSight_DK_TRM
0xFE8
Peripheral ID2
RO
See CoreSight_DK_TRM
0xFEC
Peripheral ID3
RO
See CoreSight_DK_TRM
0xFF0
Component ID0
RO
Set to 0x0D
0xFF4
Component ID1
RO
Set to 0x10
0xFF8
Component ID2
RO
Set to 0x05
0xFFC
Component ID3
RO
Set to 0xB1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-16
Freescale Semiconductor
15.2.1.5
ETM Register Summary
The ETM registers are described in Table 15-9. A more detailed description of the ETM registers can be
found in ARM’s ETM_ARCHITECTURE_SPEC document.
Table 15-9. ETM Register Summary
Offset
Name
Type
Description
0x00
ETM Control
R/W
See ETMv3.3 Architecture Specification
0x04
ETM Configuration Control
RO
See ETMv3.3 Architecture Specification
0x08
Trigger Event
WO 33
See ETMv3.3 Architecture Specification
0x0C
ASIC Control
WO3
See ETMv3.3 Architecture Specification
0x10
ETM Status
R/W
See ETMv3.3 Architecture Specification
0x14
System Configuration
RO
See ETMv3.3 Architecture Specification
0x18
Trace Start/Stop Resource Control
WO3
See ETMv3.3 Architecture Specification
0x1C
Trace Enable Control 2
WO3
See ETMv3.3 Architecture Specification
0x20
TraceEnable
WO3
See ETMv3.3 Architecture Specification
0x24
TraceEnable Control 1
WO3
See ETMv3.3 Architecture Specification
0x30
ViewData Event
WO3
See ETMv3.3 Architecture Specification
0x34
ViewData Control 1
WO3
See ETMv3.3 Architecture Specification
0x38
ViewData Control 2
WO3
See ETMv3.3 Architecture Specification
0x3C
ViewData Control 3
WO3
See ETMv3.3 Architecture Specification
0x40–0x7C
Address Comparator
Value 1–16
WO3
See ETMv3.3 Architecture Specification
0x80–0xBC
Address Access
Type 1–16
WO3
See ETMv3.3 Architecture Specification
0xC0–0xFC
Data Comparator
Value 1–16
WO3
See ETMv3.3 Architecture Specification
0x40–0x4F
Data Comparator
Mask 1–16
WO3
See ETMv3.3 Architecture Specification
0x50–0x53
Counter Reload
Value 1–4
WO3
See ETMv3.3 Architecture Specification
0x54–0x57
Counter Enable 1–4
WO3
See ETMv3.3 Architecture Specification
0x58–0x5B
Counter Reload
Event 1–4
WO3
See ETMv3.3 Architecture Specification
0x5C–0x5F
Counter Value 1–4
R/W
See ETMv3.3 Architecture Specification
0x60–0x65
Sequencer State
Transition Event
WO3
See ETMv3.3 Architecture Specification
0x66
—
—
Reserved
0x67
Current Sequencer
State
R/W
See ETMv3.3 Architecture Specification
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-17
Table 15-9. ETM Register Summary (continued)
Offset
Name
Type
Description
0x68–0x6B
External Output
Event 1–4
WO3
See ETMv3.3 Architecture Specification
0x6C–0x6E
Context ID
Comparator Value
WO3
See ETMv3.3 Architecture Specification
0x6F
Context ID
Comparator Mask
WO3
See ETMv3.3 Architecture Specification
0x70–0x77
Implementation specific
WO3
See ETMv3.3 Architecture Specification
0x78
Synchronization
Frequency
WO3
See ETMv3.3 Architecture Specification
0x79
ETM ID
RO
See ETMv3.3 Architecture Specification
0x7A
Configuration Code
Extension
RO
See ETMv3.3 Architecture Specification
0x7B
Extended External
Input Selection
WO3
See ETMv3.3 Architecture Specification
0x7C
Trace Start/Stop
Embedded ICE
Control
WO3
See ETMv3.3 Architecture Specification
0x7D
Embedded ICE
Behavior Control
WO3
See ETMv3.3 Architecture Specification
0x7E–0x7F
—
—
Reserved
0x080
CoreSight Trace ID
R/W
See ETMv3.3 Architecture Specification
0x81–0xBF
—
—
Reserved
0xC0
OS Lock Access
WO
See ETMv3.3 Architecture Specification
0xC1
OS Lock Status
RO
See ETMv3.3 Architecture Specification
0xC2
OS Save/Restore
R/W
See ETMv3.3 Architecture Specification
0xC3–0xCF
—
—
Reserved
0x380–
0x3BF
Integration registers
—
Reserved for Implementation-defined topology
detection
and integration registers.
0xF00
Integration Mode
Control
R/W
See ETMv3.3 Architecture Specification
0xFA0
Claim Tag Set
R/W
See ETMv3.3 Architecture Specification
0xFA4
Claim Tag Clear
R/W
See ETMv3.3 Architecture Specification
0xFB0
Lock Access
WO
See ETMv3.3 Architecture Specification
0xFB4
Lock Status
RO
See ETMv3.3 Architecture Specification
0xFB8
Authentication
Status
RO
See ETMv3.3 Architecture Specification
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-18
Freescale Semiconductor
Table 15-9. ETM Register Summary (continued)
3
Offset
Name
Type
Description
0xFC8
Device
Configuration
RO
See ETMv3.3 Architecture Specification
0xFCC
Device Type
RO
See ETMv3.3 Architecture Specification
0xFD0
Peripheral ID4
RO
See ETMv3.3 Architecture Specification
0xFD4
Peripheral ID5
RO
See ETMv3.3 Architecture Specification
0xFD8
Peripheral ID6
RO
See ETMv3.3 Architecture Specification
0xFDC
Peripheral ID7
RO
See ETMv3.3 Architecture Specification
0xFE0
Peripheral ID0
RO
See ETMv3.3 Architecture Specification
0xFE4
Peripheral ID1
RO
See ETMv3.3 Architecture Specification
0xFE8
Peripheral ID2
RO
See ETMv3.3 Architecture Specification
0xFEC
Peripheral ID3
RO
See ETMv3.3 Architecture Specification
0xFF0
Component ID0
RO
See ETMv3.3 Architecture Specification
0xFF4
Component ID1
RO
See ETMv3.3 Architecture Specification
0xFF8
Component ID2
RO
See ETMv3.3 Architecture Specification
0xFFC
Component ID3
RO
See ETMv3.3 Architecture Specification
In ETMv3.1 and later, register is read/write if bit [11] of the ETM Configuration Code Extension Register (0x7A) is set to b1.
15.2.1.6
CSCTI Register Summary
The CSCTI registers are described in Table 15-10. A more detailed description of the CSCTI registers can
be found in ARM’s CoreSight_DK_TRM document.
Table 15-10 describes the location by an offset.
Table 15-10. CSCTI Register Summary
Offset
Name
Type
Width
Reset Value
Description
0x000
CTICONTROL
R/W
1
0x0
See ARM
CoreSight_DK_TRM
0x010
CTIINTACK
WO
8
—
See ARM
CoreSight_DK_TRM
0x014
CTIAPPSET
R/W
4
0x0
See ARM
CoreSight_DK_TRM
0x018
CTIAPPCLEAR
WO
?
0x0
See ARM
CoreSight_DK_TRM
0x01C
CTIAPPPULSE
WO
4
0x0
See ARM
CoreSight_DK_TRM
0x020–0x03C
CTIINEN
R/W
4
0x00
See ARM
CoreSight_DK_TRM
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-19
Table 15-10. CSCTI Register Summary (continued)
Offset
Name
Type
Width
Reset Value
Description
0x0A0–0x0BC
CTIOUTEN
R/W
4
0x00
See ARM
CoreSight_DK_TRM
0x130
CTITRIGINSTATUS
RO
8
—
See ARM
CoreSight_DK_TRM
0x134
CTITRIGOUTSTATUS
RO
8
0x00
See ARM
CoreSight_DK_TRM
0x138
CTICHINSTATUS
RO
4
—
See ARM
CoreSight_DK_TRM
0x13C
CTICHOUTSTATUS
RO
4
0x0
See ARM
CoreSight_DK_TRM
0x140
Channel gate
R/W
4
0xF
See ARM
CoreSight_DK_TRM
0x144
External multiplexor control
R/W
8
0x00
See ARM
CoreSight_DK_TRM
0xEDC
ITCHINACK
WO
4
0x0
See ARM
CoreSight_DK_TRM
0xEE0
ITTRIGINACK
WO
8
0x00
See ARM
CoreSight_DK_TRM
0xEE4
ITCHOUT
WO
4
0x0
See ARM
CoreSight_DK_TRM
0xEE8
ITTRIGOUT
WO
8
0x00
See ARM
CoreSight_DK_TRM
0xEEC
ITCHOUTACK
RO
4
0x0
See ARM
CoreSight_DK_TRM
0xEF0
ITTRIGOUTACK
RO
8
0x00
See ARM
CoreSight_DK_TRM
0xEF4
ITCHIN
RO
4
0x0
See ARM
CoreSight_DK_TRM
0xEF8
ITTRIGIN
RO
8
0x00
See ARM
CoreSight_DK_TRM
0xEFC–
0xF7C
—
—
—
—
See ARM
CoreSight_DK_TRM
0xF00
ITCTRL
R/W
1
0x0
See ARM
CoreSight_DK_TRM
0xFA0
Claim Tag Set
R/W
4
0xF
See ARM
CoreSight_DK_TRM
0xFA4
Claim Tag Clear
R/W
4
0x0
See ARM
CoreSight_DK_TRM
0xFB0
Lock Access Register
WO
32
—
See ARM
CoreSight_DK_TRM
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-20
Freescale Semiconductor
Table 15-10. CSCTI Register Summary (continued)
Offset
Name
Type
Width
Reset Value
Description
0xFB4
Lock Status Register
RO
2
0x3
See ARM
CoreSight_DK_TRM
0xFB8
Authentication Status
RO
4
0xA
See ARM
CoreSight_DK_TRM
0xFC0–0xFC4
—
—
—
—
See ARM
CoreSight_DK_TRM
0xFC8
Device ID
RO
20
0x40800
See ARM
CoreSight_DK_TRM
0xFCC
Device Type Identifier
RO
8
0x14
See ARM
CoreSight_DK_TRM
0xFD0
PeripheralID4
RO
8
0x04
See ARM
CoreSight_DK_TRM
0xFD4
PeripheralID5
—
—
—
See ARM
CoreSight_DK_TRM
0xFD8
PeripheralID6
—
—
—
See ARM
CoreSight_DK_TRM
0xFDC
PeripheralID7
—
—
—
See ARM
CoreSight_DK_TRM
0xFE0
PeripheralID0
RO
8
0x06
See ARM
CoreSight_DK_TRM
0xFE4
PeripheralID1
RO
8
0xB9
See ARM
CoreSight_DK_TRM
0xFE8
PeripheralID2
RO
8
0x0B
See ARM
CoreSight_DK_TRM
0xFEC
PeripheralID3
RO
8
0x00
See ARM
CoreSight_DK_TRM
0xFF0
Component ID0
RO
8
0x0D
See ARM
CoreSight_DK_TRM
0xFF4
Component ID1
RO
8
0x90
See ARM
CoreSight_DK_TRM
0xFF8
Component ID2
RO
8
0x05
See ARM
CoreSight_DK_TRM
0xFFC
Component ID3
RO
8
0xB1
See ARM
CoreSight_DK_TRM
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-21
15.2.1.7
TPIU Register Summary
The TPIU (Trace Port Interface Unit) registers are described in Table 15-11. A more detailed description
of the TPIU registers can be found in ARM’s CoreSight_DK_TRM document. These registers can be
accessed via the APB port and are memory map accessible.
Table 15-11. TPIU Register Summary
Offset
Name
Type
Width
Reset value
Description
0x000
Supported port sizes
RO
32
0xFFFF_FFFF See ARM
CoreSight_DK_TRM
0x004
Current port size
R/W
32
0x0000_0001 See ARM
CoreSight_DK_TRM
0x100
Supported trigger modes
RO
18
0x11F
See ARM
CoreSight_DK_TRM
0x104
Trigger counter value
R/W
8
0x00
See ARM
CoreSight_DK_TRM
0x108
Trigger multiplier
R/W
5
0x00
See ARM
CoreSight_DK_TRM
0x200
Supported test
pattern/modes
RO
18
0x3000F
See ARM
CoreSight_DK_TRM
0x204
Current test pattern/mode
RO
18
0x00000
See ARM
CoreSight_DK_TRM
0x208
Test pattern repeat counter
R/W
8
0x00
See ARM
CoreSight_DK_TRM
0x300
Formatter flush and status
RO
3
0x6
See ARM
CoreSight_DK_TRM
0x304
Fomatter flush and control
R/W
14
0x1000
See ARM
CoreSight_DK_TRM
0x308
Formatter synchronization
counter
R/W
12
0x040
See ARM
CoreSight_DK_TRM
0x400
EXTCTL In Port
RO
8
Undefined
See ARM
CoreSight_DK_TRM
0x408
EXTCTL Out Port
R/W
8
0x00
See ARM
CoreSight_DK_TRM
0xEE4
Integration Register,
ITTRFLINACK
WO
2
—
See ARM
CoreSight_DK_TRM
0xEE8
Integration Register,
ITTRFLIN
WO
2
Undefined
See ARM
CoreSight_DK_TRM
0xEEC
Integration Register,
ITATBDATA0
WO
5
Undefined
See ARM
CoreSight_DK_TRM
0xEF0
Integration Register,
ITATBCTR2
WO
2
—
See ARM
CoreSight_DK_TRM
0xEF4
Integration Register,
ITATBCTR1
RO
7
Undefined
See ARM
CoreSight_DK_TRM
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-22
Freescale Semiconductor
Table 15-11. TPIU Register Summary (continued)
Offset
Name
Type
Width
Reset value
Description
0xEF8
Integration Register,
ITATBCTR0
RO
10
Undefined
See ARM
CoreSight_DK_TRM
0xF00
Integration Register,
ITATBCTR0
R/W
1
0x0
See ARM
CoreSight_DK_TRM
0xFA0
Claim Tag Set Register
R/W
4
0xF
See ARM
CoreSight_DK_TRM
0xFA4
Claim Tag Clear Register
R/W
4
0x0
See ARM
CoreSight_DK_TRM
0xFB0
Lock Access Register
WO
32
—
See ARM
CoreSight_DK_TRM
0xFB4
Lock Status Register
RO
3
0x3
See ARM
CoreSight_DK_TRM
0xFB8
Authentication Status
Register
RO
8
0x00
See ARM
CoreSight_DK_TRM
0xFC8
Device ID
RO
32
0x00
See ARM
CoreSight_DK_TRM
0xFCC
Device Type Identifier
Register
RO
8
0x21
See ARM
CoreSight_DK_TRM
0xFD0
Peripheral ID4
RO
8
0x04
See ARM
CoreSight_DK_TRM
0xFD4
Peripheral ID5
RO
8
0x00
(reserved)
See ARM
CoreSight_DK_TRM
0xFD*
Peripheral ID6
RO
8
0x00
(reserved)
See ARM
CoreSight_DK_TRM
0xFDC
Peripheral ID7
RO
8
0x00
(reserved)
See ARM
CoreSight_DK_TRM
0xFE0
Peripheral ID0
RO
8
0x07
See ARM
CoreSight_DK_TRM
0xFE4
Peripheral ID1
RO
8
0xB9
See ARM
CoreSight_DK_TRM
0xFE8
Peripheral ID2
RO
8
0x0B
See ARM
CoreSight_DK_TRM
0xFEC
Peripheral ID3
RO
8
0x00
See ARM
CoreSight_DK_TRM
0xFF0
Component ID0
RO
8
0x0D
See ARM
CoreSight_DK_TRM
0xFF4
Component ID1
RO
8
0x90
See ARM
CoreSight_DK_TRM
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-23
Table 15-11. TPIU Register Summary (continued)
Offset
Name
Type
Width
Reset value
0xFF8
Component ID2
RO
8
0x05
See ARM
CoreSight_DK_TRM
0xFFC
Component ID3
RO
8
0xB1
See ARM
CoreSight_DK_TRM
15.2.2
Description
Clocks
The list below describes the Debug clocks within the ARM platform.
• ATCLK
This is the AMBA Trace Bus (ATB) clock. This clock is also used to clock the on-platform
CTICLK and on-platform CTMCLK. ATCLK needs to be synchronous (equivalent or faster) to
PCLKDBG.
• CTICLK
This is the main clock for the CTI module. The current platform configuration requires this clock
to be synchronous to the on-platform CTM clock.
• PCLKDBG
This is the Debug APB clock. It must be synchronous (equivalent or slower) to the ATCLK.
• TRACECLKIN
This is the Trace Port Interface Unit trace clock input. Since the trace port pads are limited to 133
MHz, TRACECLKIN is pad limited to less than or equal to 266 MHz.
• TRACECLK
This is the clock for the external trace port. It is a DDR clock and runs at ½ the speed of
TRACECLKIN.
The platform control module generates the debug clocks from the arm clock. The requirement above states
that the PCLKDBG needs to be synchronous to the ATCLK. When configuring the divide by settings,
make sure this requirement is followed. PCLKDBG is a divide by two of ATCLK.
15.2.3
Reset
All debug resets are derived from JTAG_TRST_B and POR. These two resets go into the DAP_SYS to be
combined and de-asserted synchronously to the DAPCLKao (always on clock). They also go into the
platform, being synchronously de-asserted inside the plat_cntrl module, generating resets for the debug
logic inside the platform. Debug resets that do not require synchronous de-assertion are routed directly to
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-24
Freescale Semiconductor
their destination, such as por for the Core and ETM. Figure 15-8 shows a diagram of the platform debug
reset strategy.
SOC
soc_reset_b (async reset from soc)
tigerp_gp_core
Cortex
tigerp_gp_debug
1 sync_dbg_reset_b
0
por
R
nDBGPORST
HRESETn
dbg_reset_b
plat_cntrl
VDD
dbg_trst_b
R
arm_clk
any_scan_mode
nCSTRST
DAP_SYS
DAP
nTRST
nDBGPORST
CTM
rst and dbg detect
VDD
1
0
JTAG_TRST_B
nDBGRESET
nCTMRESET
POTRST
R
R
CTI
dap_ao_clock
any_scan_mode
nCTIRESET
PRESETDBGn
POR
DAPCLKao
TCK
HCLK
PCLKDBG
PCLKSYS
Other SOC Debug components
Figure 15-8. Platform Debug Reset Strategy
15.2.4
Endianness
Little endianness is supported; big endianness is not supported.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-25
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
15-26
Freescale Semiconductor
Chapter 16
Multi-Layer AHB Crossbar Switch (MAX)
This chapter provides an overview of the MAX (Multi-Layer AHB Crossbar Switch). The purpose of the
MAX is to concurrently support up to 4 simultaneous connections between master ports and slave ports.
The MAX supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports. A
simplified block diagram is shown in Figure 16-1.
NOTE
The MAX implements a 7 master by 4 slave configuration.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-1
Master Port 0
IP cntrl
Slave Port 0
IP wdata
IP rdata
Mstr addr
Mstr port(s) addr
Mstr Port request
Mstr port(s) cntrl
Mstr control
Mstr Port addr
Mstr port(s) wdata
Mstr Port cntrl
Hready to mstr(s)
Mstr hready
Slv port hready(s)
Mstr hresp
Slv port hresp(s)
Mstr read data
Mstr port(s) request
IP term
Slv port hrdata(s)
Master 0 write data
Hresp to mstr(s)
IP cntrl
Slv addr
IP wdata
Slv cntrl
Slv wdata
IP rdata
IP term
Slv hready
Slv hresp
halt request
Master Port 6
halt grant
IP cntrl
Slave 0 read data
IP wdata
IP rdata
IP term
Mstr addr
Mstr Port request
Mstr control
Slave Port 3
Mstr Port addr
Mstr Port cntrl
Mstr port(s) request
Mstr hready
Slv port hready(s)
Mstr port(s) addr
Mstr hresp
Slv port hresp(s)
Mstr port(s) cntrl
Slv port hrdata(s)
Mstr read data
Mstr port(s) wdata
Hready to mstr(s)
Master 6 write data
Max halt request
General Purpose Logic
Hresp to mstr(s)
IP cntrl
Slv addr
IP wdata
Slv cntrl
Slv wdata
IP cntrl
Slv IP cntrl
IP rdata
IP wdata
IP wdata(s)
IP term
IP rdata
IP rdata(s)
IP term
IP term(s)
Max_halted
Slv hready
Slv hresp
halt request
halt grant
halt grant(s)
Slave 3 read data
Figure 16-1. MAX Block Diagram
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-2
Freescale Semiconductor
16.1
Features
The MAX has the ability to gain control of all the slave ports and prevent any masters from making
accesses to the slave ports. This feature is useful when the user wishes to turn off the clocks to the system
and needs to ensure that no bus activity is interrupted.
The MAX can put each slave port into a low-power park mode so that the slave port does not dissipate any
power transitioning address, control, or data signals when not being actively accessed by a master port.
Each slave port can also support multiple master priority schemes. Each slave port has a hardware input
which selects the master priority scheme so the user can dynamically change master priority levels on a
slave port by slave port basis.
The MAX allows concurrent transactions to occur from any master port to any slave port. It is possible for
four master ports and all slave ports to be in use at the same time as a result of independent master requests.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grant it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions.
16.1.1
Limitations
The MAX routes bus transactions initiated on the master ports to the appropriate slave ports. There is no
provision included to route transactions initiated on the slave ports to other slave ports or to master ports.
Simply put, the slave ports do not support the bus request/bus grant protocol, the MAX assumes it is the
sole master of each slave port.
Because the MAX does not support the bus request/bus grant protocol, an external arbiter needs to be used
if multiple masters are to be connected to a single master port. In the case of a single master connecting to
a master port, the single master’s bus grant signal must be tied off in the asserted state.
Each master and slave port is fully AHB-Lite + AMBA V6 extensions compliant. The ports are not fully
AHB compliant because the MAX does not support SPLITs or RETRYs.
16.1.2
General Operation
When a master makes an access to the MAX, the access is immediately taken by the MAX. If the targeted
slave port of the access is available, the access is immediately presented on the slave port. It is possible to
make single clock (zero wait state) accesses through the MAX. If the targeted slave port of the access is
busy or parked on a different master port, the requesting master simply sees wait states inserted (hready
held negated) until the targeted slave port can service the master’s request. The latency in servicing the
request depends on each master’s priority level and the responding peripheral’s access time.
Since the MAX appears to be just another slave to the master device, the master device has no knowledge
of whether or not it actually owns the slave port it is targeting. While the master does not have control of
the slave port it is targeting, it is simply wait stated.
A master is given control of the targeted slave port only after a previous access to a different slave port has
completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
occurring when a master has an outstanding request to one slave port that has a long response time, has a
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-3
pending access to a different slave port, and a lower priority master is also making a request to the same
slave port as the pending access of the higher priority master.
Once the master has control of the slave port it is targeting the master remains in control of that slave port
until it gives up the slave port by running an IDLE cycle or by leaving that slave port for its next access.
The master could also lose control of the slave port if another higher priority master makes a request to the
slave port; however, if the master is running a locked or fixed length burst transfer it retains control of the
slave port until that transfer is completed. Based on the AULB bit in the MGPCR (Master General Purpose
Control Register) the master either retains control of the slave port when doing undefined length
incrementing burst transfers or loses the bus to a higher priority master.
The MAX terminates all master IDLE transfers (as opposed to allowing the termination to come from one
of the slave busses). Additionally, when no master is requesting access to a slave port the MAX drives
IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port.
When the MAX is controlling the slave bus (i.e. during low power park or halt mode) the hmaster field
indicates 4’b0000.
When a slave bus is being IDLEd by the MAX, it can park the slave port on the master port indicated by
the PARK bits in the SGPCR (Slave General Purpose Control Register). This can be done in an attempt to
save the initial clock of arbitration delay that would otherwise be seen if the master had to arbitrate to gain
control of the slave port. The slave port can also be put into low power park mode in attempt to save power.
16.2
MAX Interface Signals
This section provides information on MAX interface signals, including AHB master and slave interface
signals as well as IP bus interface signals.
16.2.1
MAX Signal Descriptions
Please reference the AMBA Specification Rev 2.0 for a description of the AHB signals in the MAX and
the IP Bus Specification Rev 2.0 for a description of the IP Bus signals in the MAX.
16.2.1.1
max_halt_request
This input signal is a request to halt all slave port bus activity (run MAX originated IDLE cycles on each
slave port bus, blocking all master port accesses). This signal can be used to gracefully shut down the
MAX so the system clock can be stopped for low power mode. This signal is captured by a flop inside the
MAX before use.
Once the MAX is halted, it remains halted until max_halt_request is negated.
16.2.1.2
max_halted
This output is asserted once the MAX is in control and running IDLE cycles on each slave port.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-4
Freescale Semiconductor
16.3
Memory Map and Register Definition
There are four registers that reside in each slave port of the MAX and one register that resides in each
master port of the MAX. These registers are IP bus compliant registers. Read and write transfers both
require two IP bus clock cycles. The registers can only be read from and written to in supervisor mode.
Additionally, these registers can only be read from or written to by 32-bit accesses. Section 16.3.3, MAX
Register Descriptions,” provides the detailed descriptions for all of the MAX registers.
The registers are fully decoded and an error response is returned if an unimplemented location is accessed
within the MAX.
The slave registers also feature a bit, which when written with a 1 prevents the registers from being written
to again. The registers are still readable, but future write attempts have no effect on the registers and will
be terminated with an error response.
16.3.1
Memory Map
Table 16-1 shows the MAX memory map.
Table 16-1. MAX Memory Map
Offset
Register
Access
Reset Value
Section/Page
R/W
0x0054_3210
16.3.3.1/16-9
RW
0x000_000
16.3.3.2/16-10
R/W
0x0054_3210
16.3.3.1/16-9
RW
0x000_000
16.3.3.2/16-10
R/W
0x0054_3210
16.3.3.1/16-9
RW
0x000_000
16.3.3.2/16-10
R/W
0x0054_3210
16.3.3.1/16-9
General Registers
0x43F0_4000(MP Master Priority Register for Slave port 0
R0)
0x43F0_4010
(SGPCR0)
General Purpose Control Register for Slave port 0
0x43F0_4100(MP Master Priority Register for Slave port 1
R1)
0x43F0_4110
(SGPCR1)
General Purpose Control Register for Slave port 1
0x43F0_4200(MP Master Priority Register for Slave port 2
R2)
0x43F0_4210
(SGPCR2)
General Purpose Control Register for Slave port 2
0x43F0_4300(MP Master Priority Register for Slave port 3
R3)
0x43F0_4310
(SGPCR3)
General Purpose Control Register for Slave port 3
RW
0x000_000
16.3.3.2/16-10
0x43F0_4800
(MGPCR0)
General Purpose Control Register for Master port 0
R/W
0x0000_0000
16.3.3.3/16-12
0x43F0_4900
(MGPCR1)
General Purpose Control Register for Master port 1
R/W
0x0000_0000
16.3.3.3/16-12
0x43F0_4A00
(MGPCR2)
General Purpose Control Register for Master port 2
R/W
0x0000_0000
16.3.3.3/16-12
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-5
Table 16-1. MAX Memory Map (continued)
Offset
Register
Access
Reset Value
Section/Page
0x43F0_4B00
(MGPCR3)
General Purpose Control Register for Master port 3
R/W
0x0000_0000
16.3.3.3/16-12
0x43F0_4C00
(MGPCR4)
General Purpose Control Register for Master port 4
R/W
0x0000_0000
16.3.3.3/16-12
0x43F0_4D00
(MGPCR5)
General Purpose Control Register for Master port 5
R/W
0x0000_0000
16.3.3.3/16-12
0x43F0_4E00
(MGPCR6)
General Purpose Control Register for Master port 6
R/W
0x0000_0000
16.3.3.3/16-12
16.3.2
Register Summary
Figure 16-2 shows the key to the register fields and Table 16-2 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
Write 1 BIT Self-clear 0
R/W BIT Read- BIT Writebit BIT
bit
only bit
only bit BIT to clear w1c
N/A
Figure 16-2. Key to Register Fields
Table 16-2. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
slfclr
Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero.
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-6
Freescale Semiconductor
Table 16-3 shows the MAX register summary.
Table 16-3. MAX Detailed Register Summary
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x43F0_4000( R
MPR0)
W
0
0
0
0
0
MSTR_6
0
MSTR_5
0
MSTR_4
R
0
0
MSTR_2
0
MSTR_1
0
MSTR_0
0
MSTR_6
0
MSTR_5
0
MSTR_4
0
MSTR_2
0
MSTR_1
0
MSTR_0
0
MSTR_6
0
MSTR_5
0
MSTR_4
0
MSTR_2
0
MSTR_1
0
MSTR_0
0
MSTR_6
0
MSTR_5
0
MSTR_4
0
MSTR_2
0
MSTR_1
0
MSTR_0
MSTR_3
W
0x43F0_4100( R
MPR1)
W
0
R
0
0
0
0
MSTR_3
W
0x43F0_4200( R
MPR2)
W
0
R
0
0
0
0
MSTR_3
W
0x43F0_4300( R
MPR3)
W
0
R
0
0
0
0
MSTR_3
W
W
0x43F0_4010 R RO
(SGPCR0) W
HLP
0
0
0
0
0
0
0
0
0
HLP
0
0
0
0
0
0
0
0
0
HLP
0
0
0
0
0
0
0
0
0
HLP
0
0
0
0
0
0
0
0
0
0
0x43F0_4800 R
(MGPCR0) W
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ARB
0
0
PCTL
0
0
0
0
0
PARK
W
0x43F0_4110 R RO
(SGPCR1) W
R
0
0
0
ARB
0
0
PCTL
0
0
0
0
0
PARK
W
0x43F0_4210 R RO
(SGPCR2) W
R
0
0
0
ARB
0
0
PCTL
0
0
0
0
0
PARK
W
0x43F0_4310 R RO
(SGPCR3) W
R
0
0
ARB
0
0
PCTL
0
0
0
0
0
PARK
W
0
0
0
AULB
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-7
Table 16-3. MAX Detailed Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x43F0_4900 R
(MGPCR1) W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0x43F0_4A00 R
(MGPCR2) W
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0x43F0_4B00 R
(MGPCR3) W
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0x43F0_4C00 R
(MGPCR4) W
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0x43F0_4D00 R
(MGPCR5) W
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0x43F0_4E00 R
(MGPCR6) W
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
AULB
W
0
0
0
AULB
W
0
0
0
AULB
W
0
0
0
AULB
W
0
0
0
AULB
W
0
0
0
AULB
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-8
Freescale Semiconductor
16.3.3
MAX Register Descriptions
This section contains the detailed register descriptions for the MAX registers.
16.3.3.1
Master Priority Register (MPR0-MPR3)
The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and
resides in each slave port. See Figure 16-3 for illustration of valid bits in the MPR and Table 16-4 for
description of the bit fields.
Access: Supervisor
read-write
0x43F0_4000(MPR0)
0x43F0_4100(MPR1)
0x43F0_4200(MPR2)
0x43F0_4300(MPR3)
R
31
30
29
28
27
26
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
25
24
MSTR_6
23
22
0
21
20
MSTR_5
19
18
0
17
16
MSTR_4
W
Reset
R
0
MSTR_3
0
1
0
9
8
MSTR_2
0
1
7
6
0
0
1
5
4
MSTR_1
0
1
3
2
0
0
0
1
0
MSTR_0
W
Reset
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Figure 16-3. Master Priority Register (MPR0 - MPR3)
Table 16-4. Master Priority Register Descriptions
Field
Description
31–27
Reserved. They are read as zero and should be written with zero for upward compatibility.
26–24
MSTR_6
Master 6Priority. These bits set the arbitration priority for master port 6 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
23
Reserved. They are read as zero and should be written with zero for upward compatibility.
22–20
MSTR_5
Master 5 Priority. These bits set the arbitration priority for master port 5 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
19
Reserved. They are read as zero and should be written with zero for upward compatibility.
18–16
MSTR_4
Master 4 Priority. These bits set the arbitration priority for master port 4 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
15
Reserved. They are read as zero and should be written with zero for upward compatibility.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-9
Table 16-4. Master Priority Register Descriptions (continued)
Field
14–12
MSTR_3
Description
Master 3 Priority. These bits set the arbitration priority for master port 3 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
11
Reserved. They are read as zero and should be written with zero for upward compatibility.
10–8
MSTR_2
Master 2 Priority. These bits set the arbitration priority for master port 2 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
7
Reserved. They are read as zero and should be written with zero for upward compatibility.
6–4
MSTR_1
Master 1 Priority. These bits set the arbitration priority for master port 1 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
3
Reserved. They are read as zero and should be written with zero for upward compatibility.
2–0
MSTR_0
Master 0 Priority. These bits set the arbitration priority for master port 0 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111This master has the lowest priority when accessing the slave port.
The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO
(Read Only) bit has been set in the Slave General Purpose Control Register, the Master Priority Register
can only be read from. Attempts to write to it have no effect on the MPR and result in an error response.
Additionally, no two available master ports may be programmed with the same priority level. Attempts to
program two or more available masters with the same priority level results in an error response, and the
MPR is not updated.
16.3.3.2
Slave General Purpose Control Register (SGPCR0-SGPCR3)
The Slave General Purpose Control Register (SGPCR) controls several features of each slave port.
The Read Only (RO) bit prevents any registers associated with this slave port from being written to once
set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only a
reset condition allows it to be written again.
The Halt Low Priority (HLP) bit sets the priority of the max_halt_request input to the lowest possible
priority for initial arbitration of the slave ports. By default it is the highest priority. Please note, setting this
bit does not affect the max_halt_request from attaining highest priority once it has control of the slave
ports.
The PCTL bits determine how the slave port parks when no master is actively making a request. The
available options are to park on the master defined by the PARK bits, park on the last master to use the
slave port, or go into a low-power park mode that forces all the outputs of the slave port to inactive states
when no master is requesting an access. The low-power park feature can result in an overall power savings
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-10
Freescale Semiconductor
if a the slave port is not saturated; however, it forces an extra clock of latency whenever any master tries
to access it when it is not in use because it is not parked on any master.
The PARK bits determine which master the slave parks on when no master is making an active request and
the max_halt_request input is negated. Please use caution to only select master ports that are actually
present in the design. If the user programs the PARK bits to a master not present in the current design
implementation, undefined behavior results.
See Figure 16-4 for illustration of valid bits in the SGPCR, and Table 16-5 for description of the bit fields.
0x43F0_4010 (SGPCR0)
0x43F0_4110 (SGPCR1)
0x43F0_4210 (SGPCR2)
0x43F0_4310 (SGPCR3)
31
R
W
Reset
R
30
Access: Supervisor
read-write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
RO
HLP
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
ARB
W
Reset
0
0
7
6
0
0
0
0
PCTL
0
0
0
0
PARK
0
0
0
Figure 16-4. Slave General Purpose Control Register n
Table 16-5. Slave General Purpose Control Register Descriptions
Field
Description
31
RO
Read Only
This bit is used to force all of a slave port’s registers to be read only. Once written to 1 it can only be cleared
by hardware reset.
This bit is initialized by hardware reset.
0 All this slave port’s registers can be written.
1 All this slave port’s registers are read only and cannot be written (attempted writes have no effect and result
in an error response).
30
HLP
Halt Low Priority
This bit is used to set the initial arbitration priority of the max_halt_request input.
This bit is initialized by hardware reset.
0 The max_halt_request input has the highest priority for arbitration on this slave port
1 The max_halt_request input has the lowest initial priority for arbitration on this slave port.
29–10
Reserved. They read as zero and should be written with zero for upward compatibility.
9–8
ARB
Arbitration Mode
These bits are used to select the arbitration policy for the slave port.
These bits are initialized by hardware reset.
00 Fixed Priority.
01 Round Robin (rotating) Priority.
10 Reserved
11 Reserved
7–6
Reserved. They read as zero and should be written with zero for upward compatibility.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-11
Table 16-5. Slave General Purpose Control Register Descriptions (continued)
Field
Description
5–4
PCTL
Parking Control
These bits determine the parking control used by this slave port.
These bits are initialized by hardware reset.
00 When no master is making a request, the arbiter parks the slave port on the master port defined by the
PARK bit field.
01 When no master is making a request, the arbiter parks the slave port on the last master to be in control of
the slave port.
10 When no master is making a request, the arbiter parks the slave port on no master and will drive all outputs
to a constant safe state.
11 Reserved
3
Reserved. They read as zero and should be written with zero for upward compatibility.
2–0
PARK
PARK
These bits are used to determine which master port this slave port parks on when no masters are actively
making requests and the PCTL bits are set to 00.
These bits are initialized by hardware reset.
000 Park on Master Port 0
001 Park on Master Port 1
010 Park on Master Port 2
011 Park on Master Port 3
100 Park on Master Port 4
101 Park on Master Port 5
110 Park on Master Port 6
111 Reserved
The SGPCR can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only) bit
has been set in the SGPCR the SGPCR can only be read, attempts to write to it have no effect on the
SGPCR and result in an error response.
16.3.3.3
Master General Purpose Control Register
The Master General Purpose Control Register (MGPCR) presently controls only whether or not the
master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be
broken by requests from higher priority masters.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-12
Freescale Semiconductor
The AULB (Arbitrate on Undefined Length Bursts) bit field determines whether (and when) the MAX
arbitrates away the slave port the master owns when the master is performing undefined length burst
accesses.
Access: Supervisor
read-write
0x43F0_4800 (MGPCR0)
0x43F0_4900 (MGPCR1)
0x43F0_4A00 (MGPCR2)
0x43F0_4B00 (MGPCR3)
0x43F0_4C00 (MGPCR4)
0x43F0_4D00 (MGPCR5)
0x43F0_4E00 (MGPCR6)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
AULB
W
Reset
0
0
0
Figure 16-5. Master General Purpose Control Register n
Table 16-6. Master General Purpose Control Register Descriptions
Name
Description
31 - 3
Reserved. They read as zero and should be written with zero for upward compatibility.
2-0
AULB
Arbitrate on Undefined Length Bursts. These bits are used to select the arbitration policy during undefined
length bursts by this master.
These bits are initialized by hardware reset.
000 No arbitration is allowed during an undefined length burst.
001 Arbitration is allowed at any time during an undefined length burst.
010 Arbitration is allowed after four beats of an undefined length burst.
011 Arbitration is allowed after eight beats of an undefined length burst.
100 Arbitration is allowed after 16 beats of an undefined length burst.
101 Reserved
110 Reserved
111 Reserved
The MGPCR can only be accessed in supervisor mode with 32-bit accesses.
16.3.4
Coherency
Since the content of the registers has a real time effect on the operation of the MAX it is important for the
user to understand that any register modifications take effect as soon as the register is written. The values
of the registers do not track with slave port related AHB accesses but instead track only with IP bus
accesses.
The exception to this rule are the AULB bits in the MGPCR. The update of these bits is only recognized
when the master on that master port runs an IDLE cycle, even though the IP bus cycle to write them will
have long since terminated successfully. If the AULB bits in the MGPCR are written in between two burst
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-13
accesses, the new AULB encodings does not take effect until an IDLE cycle has been initiated by the
master on that master port.
16.4
Detailed Functional Description
This section describes the functionality of the MAX in greater detail.
16.4.1
Arbitration
The MAX supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a simple
round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave
port.
16.4.1.1
Arbitration During Undefined Length Bursts
Arbitration points during an undefined length burst are defined by the current master’s MGPCR AULB
field setting. When a defined length is imposed on the burst via the AULB bits, the undefined length burst
is treated as a single or series of single back to back fixed length burst accesses. For example, a master runs
an undefined length burst and the AULB bits in the MGPCR indicate arbitration occurs after the fourth
beat of the burst. The master runs two sequential beats and then starts a 12-beat, undefined length burst
access to a new address within the same slave port region as the previous access. The MAX does not allow
an arbitration point until the fourth overall access (second beat of the second burst). At that point all
remaining accesses are open for arbitration until the master loses control of the slave port.
Assume the master loses control of the slave port after the fifth beat of the second burst. Once the master
regains control of the slave port, no arbitration point will be available until after the master has run four
more beats of its burst. After the fourth beat of the (now continued) burst (ninth beat of the second burst
from the master’s perspective) is taken, all beats of the burst will once again be open for arbitration until
the master loses control of the slave port.
Assume the master again loses control of the slave port on the fifth beat of the third (now continued) burst
(10th beat of the second burst from the master’s perspective). Once the master regains control of the slave
port, it will be allowed to complete its final two beats of its burst without facing arbitration.
Note that fixed-length burst accesses arenot be affected by the AULB bits. All fixed- length burst accesses
lock out arbitration until the last beat of the fixed-length burst.
16.4.1.2
Fixed Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level in the MPR (Master
Priority Register). If two masters both request access to a slave port, the master with the highest priority
in the selected priority register gains control over the slave port.
Any time a master makes a request to a slave port, the slave port checks to see if the new requesting
master’s priority level is higher than that of the master that currently has control over the slave port (unless
the slave port is in a parked state). The slave port does an arbitration check at every clock edge to ensure
that the proper master (if any) has control of the slave port.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-14
Freescale Semiconductor
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port the new requesting master is granted control over the slave port at the next clock edge. The
exception to this rule is if the master that currently has control over the slave port is running a fixed length
burst transfer or a locked transfer. In this case the new requesting master must wait until the end of the
burst transfer or locked transfer before it will be granted control of the slave port. If the master is running
an undefined length burst transfer the new requesting master must wait until an arbitration point for the
undefined length burst transfer before it will be granted control of the slave port. Arbitration points for an
undefined length burst are defined in the MGPCR for each master.
If the new requesting master’s priority level is lower than that of the master that currently has control of
the slave port, the new requesting master is forced to wait until the master that currently has control of the
slave port either runs an IDLE cycle or runs a non IDLE cycle to a location other than the current slave port.
16.4.1.3
Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master
number. This relative priority is compared to the ID of the last master to perform a transfer on the slave
bus. The highest priority requesting master becomes owner of the slave bus as the next transfer boundary
(accounting for locked and fixed-length burst transfers). Priority is based on how far ahead the ID of the
requesting master is to the ID of the last master (ID is defined by master port number, not the hmaster
field).
Once granted access to a slave port, a master may perform as many transfers as desired to that port until
another master makes a request to the same slave port. The next master in line is granted access to the slave
port at the next assertion of sX_hready, or possibly on the next clock cycle if the current master has no
pending access request.
As an example of arbitration in round-robin mode, assume the MAX is implemented with master ports 0,
1, 2, 3, 4 and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous
requests, (master ports 2 and 3 make no requests), they are serviced in the order 4, 5, and then 0.
Parking may still be used in a round-robin mode, but does not affect the round-robin pointer unless the
parked master actually performs a transfer. Handoff to the next master in line occurs after one cycle of
arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at
master port 0, giving it the highest priority.
16.4.2
Priority Assignment
Each master port needs to be assigned a unique 3 bit priority level. If an attempt is made to program
multiple master ports with the same priority level within a register (MPR), the MAX responds with an error
and the registers are not updated.
16.4.3
Master Port Functionality
This section discusses the master port functionality.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-15
16.4.3.1
General
Each master port consists of two decoders, a capture unit, a register slice, a mux, and a small state machine.
The first decoder is used to decode the haddr and control signals coming directly from the master, telling
the state machine where the master’s next access will be and if it is in fact a legal access. The second
decoder gets its input from the capture unit, so it may be looking directly at the signals coming from the
master or it may be looking at captured signals coming from the master, depending entirely on the state of
the targeted slave port. The second decoder is then used to generate the access requests that go to the slave
ports.
The capture unit is used to capture the address and control information coming from the master in the event
that the targeted slave port cannot immediately service the master. The capture unit is controlled by outputs
from the state machine which tell it to either pass through the original master signals or the captured
signals.
The register slice contains the registers associated with the specific master port. The registers have a
quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine.
The mux is used simply to select which slave’s read data is sent back to the master. The mux is controlled
by the state machine.
The state machine controls all aspects of the master port. It knows which slave port the master wants to
make a request to and controls when that request is made. It also has knowledge of each slave port,
knowing whether or not the slave port is ready to accept an access from the master port. This determines
whether or not the master may immediately have its request taken by the slave port or whether the master
port must capture the master’s request and queue it at the slave port boundary.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-16
Freescale Semiconductor
For a block diagram of a master port see Figure 16-6.
Capture Unit
Addr/Cntrl
Addr/Cntrl
Async/Flopped_sel
Decoder
Addr/Cntrl
Slave_port_rqst[4:0]
Request_enable
Decoder
Addr/Cntrl
Next_slave_port[4:0]
Illegal_access
State Machine
Next_slave_port[4:0]
Async/Flopped_sel
Illegal_access
Request_enable
Hready_in
Slv_hready[4:0]
Hready_out
Slv_hresp[4:0]
Hresp
Slv_is_mine[4:0]
Rdata_sel
Control_bits
Registers
Read_sel
Write_sel
Wdata
Control_bits
Xfr_wait
Xfr_error
Rdata
Mux
Sel
Hrdata
Slv_hrdata[4:0]
Figure 16-6. MAX Master Port Block Diagram
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-17
16.4.3.2
Master Port Decoders
The decoders are very simple as they ensure an access request is allowed to be made and that the slave port
targeted is actually present in the design. The decoders feeding the state machine are always enabled. The
decoders that select the slave are enabled only when the master port controlling state machine wants to
make a request to a slave port. This is necessary so that if a master port is making an access to a slave port
and is being wait stated, and its next access is to a different slave port, the request to the second slave port
can be held off until the access to the first slave port is terminated.
The decoders also output a “hole decode” or illegal access signal which tells the state machine that the
master is trying to access a slave port that does not exist.
16.4.3.3
Master Port Capture Unit
The capture unit simply captures the state of the master’s address and control signals if the MAX cannot
immediately pass the master’s request through to the proper slave port. The capture unit consists of a set
of flops and a mux which selects either the asynchronous path from address and control or the flopped
(captured) address and control information.
16.4.3.4
Master Port Registers
The registers in the master port are only those registers associated with this particular master port. The read
and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level
because not all the IP bus signals are routed this deep in the design.
There is a register control block at the same level of the master port and slave port instantiations in the
MAX. This control block ensures that all accesses are 32-bit supervisor accesses before passing them on
to the master ports.
The register outputs are connected directly to the state machine.
16.4.3.5
Master Port State Machine
This section describes the master port state machine states and state swapping.
16.4.3.5.1
Master Port State Machine States
The master side state machine’s main function is to monitor the activities of the master port. The state
machine has six states: busy, idle, stalled, steady state, first cycle error response and second cycle error
response.
The busy state is used when the master runs a BUSY cycle to the master port. The master port maintains
its request to the slave port if it currently owns the slave port; however, if it loses control of the slave port
it no longer maintains its request. If the master port loses control of the slave port, it is not allowed to make
another request to the slave port until it runs a NSEQ or SEQ cycle.
The idle state is used when the master runs a valid IDLE cycle to the master port. The master port makes
no requests to the slave ports (disables the slave port decoder) and terminates the IDLE cycle.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-18
Freescale Semiconductor
The stalled state is used when the master makes a request to a slave port that is not immediately ready to
receive the request. In this case the state machine directs the capture unit to send out the captured address
and control signals and enables the slave port decoder to indicate a pending request to the appropriate slave
port.
The steady state is used when the master port and slave port are in fully asynchronous mode, making the
MAX completely transparent in the access. The state machine selects the appropriate slave’s hresp0,
hready and hrdata to pass back to the master.
The first cycle error response and second cycle error response states are self explanatory. The MAX
responds with an error response to the master if the master tries to access an unimplemented memory
location through the MAX (i.e. a slave port that does not exist).
16.4.3.5.2
Master Port State Machine Slave Swapping
The design of the master side state machine is fairly straight forward. The one real decision to be made is
how to handle the master moving from one slave port access to another slave port access. The approach
that was taken was to minimize or eliminate, when possible, any bubbles that would get inserted into the
access due to switching slave ports.
The state machine does not allow the master to request access to another slave port until the current access
being made is terminated. This prevents a single master from owning two slave ports at the same time (the
slave port it is currently accessing and the slave port it wishes to access next).
The state machine also maintains watch on the slave port the master is accessing as well as the slave port
the master wishes to switch to. If the new slave port is parked on the master, the master is able to make the
switch without incurring any delays. The termination of the current access also acts as the launch of the
new access on the new slave port. If the new slave port is not parked on the master, the master incurs a
minimum one-clock delay before it can launch its access on the new slave port.
This is the same for switching from the busy or idle state to actively accessing a slave port. If the slave
port is parked on the master, the state machine goes to the steady state and the access begins immediately.
If the slave port is not parked on the master (serving another master, parked on another master or in low
power park mode), the state machine transitions to the stalled state and at least a one-clock penalty is paid.
16.4.4
Slave Port Functionality
This section discusses the slave port functionality.
16.4.4.1
General
Each slave port consists of a register slice, a bank of muxes and a state machine.
The register slice contains the registers associated with the specific slave port. The registers have a
quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine.
The muxes are a series of 6 to 1 muxes that take in all the address, control and write data information from
each of the master ports and then pass the correct master’s signals to the slave port. The state machine
controls all the muxes.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-19
The state machine is where the main slave port arbitration occurs, it decides which master is in control of
the slave port and which master will be in control of the slave port in the next bus cycle.
For a block diagram of a slave port see Figure 16-7.
Registers
Read_sel
Write_sel
Wdata
Control_bits
Xfr_wait
Xfr_error
Rdata
State Machine
Control_bits
Master_requests[5:0]
Slv_hready
halt_request
Slv_hresp
slave_halted
Master_sel[5:0]
Current_master[5:0]
Force_idle
Master_hready[5:0]
Force_nseq
Master_hresp[5:0]
Muxes
Force_nseq
Force_idle
Master_addr[5:0]
Master_sel[5:0]
Master_cntrl[5:0]
Slv_addr_signals
Master_wdata[5:0]
Slv_cntrl_signals
Slv_wdata
Figure 16-7. MAX Slave Port Block Diagram
16.4.4.2
Slave Port Muxes
The block diagram (Figure 16-7) shows only one block for all the muxes. In reality that block instantiates
many 6 to 1 muxes, one for each master-to-slave signal in fact. All the muxes are designed in an AND-OR
fashion, so that if no master is selected, the output of the muxes is zero. (This is an important feature for
low-power park mode.)
The muxes also have an override signal which is used by the slave port to asynchronously force IDLE
cycles onto the slave bus. When the state machine forces an IDLE cycle it zeros out htrans and hmastlock,
making sure the slave bus sees a valid IDLE cycle being run by the MAX.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-20
Freescale Semiconductor
The enable to the mux controlling htrans also contains an additional control signal from the state machine
so that a NSEQ transaction can be forced. This is done any time the slave port switches masters to ensure
that no IDLE-SEQ, BUSY-SEQ or NSEQ-SEQ transactions are seen on the slave port when they should
not be. If the state machine indicates to run both an IDLE and an NSEQ cycle, the IDLE directive has
priority.
NOTE
IDLE-SEQ is in fact an illegal access, but a possible scenario given the
multimaster environment in the MAX unless corrected by the MAX.
16.4.4.3
Slave Port Registers
There is a register control block at the same level of the master port and slave port instantiations in the
MAX. This control block ensures that all accesses are 32-bit supervisor accesses before passing them on
to the master and slave ports.
The registers in the slave port are only those registers associated with this particular slave port. The read
and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level
because not all the IP bus signals are routed this deep in the design.
The register outputs are connected directly to the slave state machine. The registers can be read from an
unlimited number of times. The registers can only be written to as long as the RO bit is written to 0 in the
SGPCR, once it is written to a 1 only a hardware reset allows the registers to be written again.
16.4.4.4
Slave Port State Machine
This section discusses the slave port state machine states, arbitration, master handoff, machine parking,
and halt mode.
16.4.4.4.1
Slave Port State Machine States
At the heart of the slave port is the state machine. The state machine is simplicity itself, requiring only four
states - steady state, transition state, transition hold state, and hold state. Either the slave port is owned
by the same master it was in the last clock cycle (either by active use or by parking), it is transitioning to
a new master (either for active use or parking), it is transitioning to a new master during wait states or it is
being held on the same master pending a transition to a new master.
16.4.4.4.2
Slave Port State Machine Arbitration
The real work in the state machine is determining which master port will be in control of the slave port in
the next clock cycle, the arbitration. Each master is programmed with a fixed 3 bit priority level. The MAX
uses these bits in determining priority levels when programmed for fixed priority mode of operation.
Arbitration always occurs on a clock edge, but only occurs on edges when a change in mastership will not
violate AHB-Lite protocols. Valid arbitrations points include any clock cycle in which sX_hready is
asserted (provide the master is not performing a burst or locked cycle) and any wait state in which the
master owning the bus indicates a transfer type of IDLE (provided the master is not performing a locked
cycle).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-21
Since arbitration can occur on every clock cycle the slave port masks off all master requests if the current
master is performing a locked transfer or a protected burst transfer, guaranteeing that no matter how low
its priority level, it will be allowed to finish its locked or protected portion of a burst sequence.
16.4.4.4.3
Slave Port State Machine Master Handoff
The only times the slave port switches masters when programmed for fixed priority mode of operation is
when a higher priority master makes a request or when the current master is the highest priority and it gives
up the slave port by either running and IDLE cycle to the slave port or running a valid access to a location
other than the slave port.
If the current master loses control of the slave port because a higher priority master takes it away, the slave
port does not incur any wasted cycles. The current master has its current cycle terminated by the slave port
at the same time as the new master’s address and control information is recognized by the slave port. This
looks like a seamless transition on the slave port.
If the current master is being wait stated when the higher priority master makes its request, the current
master is allowed to make one more transaction on the slave bus before giving it up to the new master.
Figure 16-8 illustrates the effect of a higher priority master taking control of the bus when the slave port
is programmed for a fixed priority mode of operation.
1
2
3
4
5
6
7
8
9
10
hclk
m2 request
m3 request
m4 request
m5 request
Highest
Priority
Requester
Master 5 Master 5 Master 4 Master 3 Master 2
Master 3
Master 4
Master 3 Master 4
Address/Cntrl
owner
MAX
Master 5
Master 5
Master 2
htrans
IDLE
NSEQ
NSEQ
NSEQ
NSEQ
None
NSEQ
MAX
IDLE
hready
Figure 16-8. Low to High Priority Mastership Change
If the current master is the highest priority master and it gives up the slave port by running an IDLE cycle
or by running a valid cycle to another location other than the slave port, the next highest priority master
gains control of the slave port. If the current access incurs any wait states, the transition is seamless and
no bandwidth will be lost. However, if the current transaction is terminated without wait states, one IDLE
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-22
Freescale Semiconductor
cycle is forced onto the slave bus by the MAX before the new master is able to take control of the slave
port. If no other master is requesting the bus, IDLE cycles are run by the MAX. However, no bandwidth
is truly lost because no master is making a request.
Figure 16-9 illustrates the effect of a higher priority master giving up control of the bus.
1
2
3
4
5
6
7
8
9
hclk
m0 request
m2 request
m4 request
Highest
Priority
Requester
Master 0
Master 2
None
Master 4
None
Address/Cntrl
owner
MAX
Master 0
MAX
Master 2
MAX
Master 4
MAX
htrans
IDLE
NSEQ
IDLE
NSEQ
IDLE
NSEQ
IDLE
hready
Figure 16-9. High to Low Priority Mastership Change
When the slave port is programmed for round-robin mode of arbitration, the slave port switches masters
any time there is more than one master actively making a request to the slave port. This happens because
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-23
any master other than the one which presently owns the bus is considered to have higher priority.
Figure 16-10 shows an example of round-robin mode of operation.
1
2
3
4
5
6
7
8
9
10
hclk
m0 request
m1 request
m4 request
m5 request
Highest
Priority
Requester
Address/Cntrl
owner
htrans
Master 1 Master 4
Master 5
Master 0
Master 4
Master 5
Master 4 Master 5
MAX
Master 1
Master 4
Master 5
Master 0
IDLE
NSEQ
NSEQ
NSEQ
NSEQ
NSEQ
None
NSEQ
MAX
IDLE
hready
Figure 16-10. Round-Robin Mastership Change
16.4.4.4.4
Slave Port State Machine Parking
If no master is currently making a request to the slave port, the slave port parks in one of four places as
dictated by the PCTL and PARK bits in the SGPCR and the locked state of the last master to access it.
If the last master to access the slave port ran a locked cycle and continues to run locked cycles even after
leaving the slave port, the slave port parks on that master without regard to the bit settings in the SGPCR
and without regard to pending requests from other masters. This is done so a master can run a locked
transfer to the slave port, leave it, return to it, and be guaranteed that no other master has had access to it
(provided the master maintains all transfers are locked transfers). If locking is not an issue for parking, the
SGPCR bits dictate the parking method.
If the PCTL bits are set for low-power park mode, the slave port enters low-power park mode. It does not
recognize any master as being in control of it, and it does not select any master’s signals to pass through
to the slave bus. In this case all slave bus activity effectively halts because all slave bus signals being driven
from the MAX are 0. This of course can save quite a bit of power if the slave port is not in use for some
time. The down side is that when a master does make a request to the slave port, it is delayed by one clock
because it has to arbitrate to acquire ownership of the slave port.
If the PCTL bits are set to “park on last” mode, the slave port parks on the last master to access it, passing
all that masters signals through to the slave bus. The MAX asynchronously forces htrans[1:0],
hmaster[3:0], hburst[2:0], and hmastlock to 0 for all access that the master does not run to the slave port.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-24
Freescale Semiconductor
When that master accesses the slave port again, it does not pay any arbitration penalty; however, if any
other master wishes to access the slave port, a one-clock arbitration penalty will be imposed.
If the PCTL bits are set to use PARK mode, the slave port parks on the master designated by the PARK
bits. The behavior here is the same as for the park on last mode with the exception that a specific master
is parked on instead of the last master to access the slave port. If the master designated by the PARK bits
tries to access the slave port, it does not pay an arbitration penalty while any other master pays a one-clock
penalty. Figure 16-11 illustrates parking on a specific master.
1
2
3
4
5
6
7
8
9
hclk
m0 request
m2 request
m4 request
Master 2
Park
Highest
Priority
Requester
Master 0
None
Master 2
None
Master 4
None
Master 2
None
Address/Cntrl
owner
MAX
Master 0
Master 2
MAX
MAX
Master 4
Master 2
MAX
htrans
IDLE
NSEQ
NSEQ
IDLE
IDLE
NSEQ
NSEQ
IDLE
hready
Figure 16-11. Parking on a Specific Master
Figure 16-12 illustrates parking on the last master. Note that in cycle 6 simultaneous requests are made by
master 2 and master 4. Although master 2 has higher priority, the slave bus is parked on master 4 so master
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-25
4’s access is taken first. The slave port parks on master 2 once it has given control to master 2. This same
situation can occur when parking on a specific master as well.
1
2
3
4
5
6
7
8
9
hclk
m0 request
m2 request
m4 request
Park
Last Master
Highest
Priority
Requester
Master 0
Master 0
None
Master 4
Master 4
Master 2
None
Master 2
None
Address/Cntrl
owner
MAX
Master 0
MAX
Master 4
MAX
Master 4
Master 2
MAX
htrans
IDLE
NSEQ
IDLE
NSEQ
IDLE
NSEQ
NSEQ
IDLE
hready
Figure 16-12. Parking on Last Master
16.4.4.4.5
Slave Port State Machine Halt Mode
If the max_halt_request input is asserted, the slave port eventually halts all slave bus activity and go into
halt mode, which is almost identical to low power park mode. The HLP bit in the SGPCR controls the
priority level of the max_halt_request in the arbitration algorithm. If the HLP bit is cleared, the
max_halt_request has the highest priority of any master and gains control of the slave port at the next
arbitration point (most likely the next bus cycle, unless the current master is running a locked or fixed
length burst transfer). If the HLP bit is set, the slave port waits until no masters are actively making
requests before moving to halt mode.
Regardless of the state of the HLP bit, once the slave port has gone into halt mode as a result of
max_halt_request being asserted, it remains in halt mode until max_halt_request is negated, regardless
of the priority level of any masters that may make requests.
In halt mode no master is selected to own the slave port so all the outputs of the slave port are set to 0.
16.5
Initialization/Application Information
No initialization is required by or for the MAX. Hardware reset ensures all the register bits used by the
MAX are properly initialized.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-26
Freescale Semiconductor
16.6
MAX Interface
This section provides information on the MAX interface.
16.6.1
Overview
The main goal of the MAX is to increase overall system performance by allowing multiple masters to
communicate in parallel with multiple slaves. In order to maximize data throughput it is essential to keep
arbitration delays to a minimum.
This section examines data throughput from the point of view of masters and slaves, detailing when the
MAX stalls the masters or inserts bubbles on the slave side.
16.6.2
Master Ports
Master accesses receive one of four responses from the MAX. They are either terminated, taken, stalled,
or responded to with an error.
16.6.2.1
Terminated Accesses
A master access is terminated if the transfer type is IDLE. The MAX terminates the access, so it is not
allowed to pass through the MAX.
16.6.2.2
Taken Accesses
A master access is taken if the transfer type is non IDLE and the slave port to which the access decodes is
either currently servicing the master or is parked on the master. In this case the MAX is completely
transparent, the master’s access is immediately seen on the slave bus, and no arbitration delays are
incurred.
16.6.2.3
Stalled Accesses
A master access is stalled if the transfer type is non IDLE and the access decodes to a slave port that is
busy serving another master, parked on another master or is in low power park mode. The MAX indicates
to the master that the address phase of the access has been taken but then queues the access to the
appropriate slave port to enter into arbitration for access to that slave port.
If the slave port is currently parked on another master or is in low power park mode and no other master
is requesting access to the slave port then only one clock of arbitration is incurred. If the slave port is
currently serving another master of a lower priority and the master has a higher priority than all other
requesting masters then the master gains control over the slave port as soon as the data phase of the current
access is completed (burst and locked transfers excluded). If the slave port is currently servicing another
master of a higher priority then the master gains control of the slave port once the other master releases
control of the slave port if no other higher priority master is also waiting for the slave port.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-27
16.6.2.4
Error Response Terminated Accesses
A master access is responded to with an error if the transfer type is non-IDLE and the access decodes to a
location not occupied by a slave port. Please refer to Section 16.6.3, Slave Ports,” for information on
locations that are not occupied by a slave port.
16.6.3
Slave Ports
The goal of the MAX with respect to the slave ports is to keep them 100% saturated when masters are
actively making requests. In order to do this the MAX must not insert any bubbles onto the slave bus unless
absolutely necessary.
There is only one instance when the MAX forces a bubble onto the slave bus when a master is actively
making a request. This occurs when a higher priority master has control of the slave port and is running
single clock (zero wait state) accesses while a lower priority master is stalled waiting for control of the
slave port. When the higher priority master either leaves the slave port or runs an IDLE cycle to the slave
port the MAX takes control of the slave bus and run a single IDLE cycle before giving the slave port to
the lower priority master that was waiting for control of the slave port.
The only other times the MAX has control of the slave port is when the MAX is halting or when no masters
are making access requests to the slave port and the MAX is forced to either park the slave port on a
specific master or put the slave port into low power park mode.
In most instances when the MAX has control of the slave port, it indicates IDLE for the transfer type,
negates all control signals, and indicates ownership of the slave bus via the hmaster encoding of 4’b0000.
One exception to this rule is when a master running locked cycles has left the slave port but continues to
run locked cycles. In this case the MAX controls the slave port and indicate sIDLE for the transfer type
but it does not affect any other signals.
NOTE
When a master runs a locked cycle through the MAX, the master is
guaranteed ownership of all slave ports it accesses while running locked
cycles for one cycle beyond when the master finishes running locked cycles.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
16-28
Freescale Semiconductor
Chapter 17
Digital Audio Mux (AUDMUX)
The Digital Audio Mux (AUDMUX) provides a programmable interconnect device for voice, audio, and
synchronous data routing between host serial interfaces (that is, SSI) and peripheral serial interfaces (that
is, audio and voice codecs, also known as coder-decoders).
The AUDMUX allows the audio system connectivity to be modified through programming (as opposed to
altering the PCB schematics of the system). Figure 17-1 and Figure 17-2 show the block diagram of the
AUDMUX (Figure 17-2 is an extension of Figure 17-1).
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-1
Fsn,Clkn
TxDn,RxDn
TFS7,TCLK7
TFS1,TCLK1
TFSEL7[3:0]
TFS7
TCSEL7[3:0]
TCLK7
TFSEL1[3:0]
TFS1
RFS7,RCLK7
TCSEL1[3:0]
TCLK1
RFS1,RCLK1
Port 1
RFSEL7[3:0]
RFS7
RCSEL7[3:0]
RCLK7
RFSEL1[3:0]
RFS1
RCSEL1[3:0]
Port 7
TXRXEN7
RxD7_out
RCLK1
Da7
TXRXEN1
X
RxD1_out
Da1
X
Db1
MODE1[1:0]
RXDSEL2[3:0]
TxD1_in
Db7
MODE7[1:0]
RXDSEL7[3:0]
TxD7_in
TFS2,TCLK2
TFSEL2[3:0]
TFS6,TCLK6
TFS2
TCSEL2[3:0]
TCLK2
RFS2,RCLK2
Port 2
RFSEL2[3:0]
RFS2
RCSEL2[3:0]
RCLK2
TXRXEN2
TFS6
TCSEL6[3:0]
TCLK6
RFS6,RCLK6
RFSEL6[3:0]
RFS6
RCSEL6[3:0]
RCLK6
RxD2_out
Da2
Db2
TFSEL6[3:0]
X
RXDSEL2[3:0]
MODE2[1:0]
TxD2_in
Port 6
TXRXEN6
RxD6_out
Da6
X
Db6
MODE6[1:0]
RXDSEL6[3:0]
TxD6_in
Figure 17-1. AUDMUX Block Diagram A
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-2
Freescale Semiconductor
Fsn,Clkn
TxDn,RxDn
TFS5,TCLK5
TFSEL5[3:0]
TFS5
TCSEL5[3:0]
TCLK5
RFS5,RCLK5
RFSEL5[3:0]
RFS5
RCSEL5[3:0]
RCLK5
Port 5
TXRXEN5
TFS3,TCLK3
RxD5_out
Da5
TFSEL3[3:0]
X
TFS3
RXDSEL5[3:0] MODE5[1:0]
RFS3,RCLK3
RFSEL3[3:0]
Port 3
Db5
TCSEL3[3:0]
TCLK3
TxD5_in
RFS3
RCSEL3[3:0]
RCLK3
TXRXEN3
RxD3_out
Da3
Db3
TFS4,TCLK4
X
MODE3[1:0]
RXDSEL3[3:0]
TFSEL4[3:0]
TFS4
TxD3_in
TCSEL4[3:0]
TCLK4
RFS4,RCLK4
RFSEL4[3:0]
RFS4
RCSEL4[3:0]
RCLK4
Port 4
TXRXEN4
RxD4_out
X
Da4
Db4
RXDSEL4[3:0] MODE4[1:0]
TxD4_in
Figure 17-2. AUDMUX Block Diagram B
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-3
17.1
Introduction
With the AUDMUX, resources do not need to be hard-wired and can be effectively shared in different
configurations. The AUDMUX interconnections allow multiple, simultaneous audio/voice/data flows
between the ports in point-to-point or point-to-multipoint configurations.
The AUDMUX includes two types of interfaces. Internal ports connect to the processor serial interfaces
and external ports connect to off-chip audio devices and serial interfaces of other processors. A desired
connectivity is achieved by configuring the appropriate internal and external ports.
17.1.1
•
•
•
•
•
•
Features
Four external ports
Full 6-wire SSI interfaces for asynchronous receive and transmit
Configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interfaces
Independent Tx/Rx Frame sync and clock direction selection for host or peripheral
Each host interface’s capability to connect to any other host or peripheral interface in a
point-to-point or point-to-multipoint (network mode)
Transmit and Receive Data switching to support external network mode
17.1.2
Modes of Operation
Figure 17-1 and Figure 17-2 show the AUDMUX block diagram.
All the ports are basically identical. The major difference is whether a port is connected to an on-chip serial
interface (for example, SSI) or connected to the chip’s pads to connect to off-chip serial devices (that is,
any 4-wire or 6-wire external SSI, voice, I2S, or AC97 CODEC).
Port 7 can be physically connected to any of the peripherals previously mentioned. There is no functional
difference among Ports 1 through 7.
All ports can be configured as four- or six-wire interfaces. When configured as a six-wire interface, the
additional RFS and RCLK signals of the interface enable the serial interface to be used in asynchronous
mode with separate receive and transmit clocks.
All ports have a Tx/Rx switch to provide flexibility in supporting network mode configurations. The
Tx/Rx switch enables the transmit and receive data lines to be swapped so that mastership of the serial bus
can be passed among multiple external devices connected to a single port.
All ports, in addition to supporting the default external network mode, support —internal network mode.
With internal network mode, a point-to-multipoint network configuration with an arbitrary number of
slaves can be supported if the external slaves are put into the high-impedance state (as defined in the SSI
network mode protocol) and have pull-up resistors on their TxD pins. (Alternatively, this can be viewed
as requiring a pull-up resistor on the corresponding AUDMUX RxD pin.)
Bit clock direction selection enables each port to be configured as a master or slave in the flow.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-4
Freescale Semiconductor
Possible scenarios include:
• SSI1 (internal port) drives a voice CODEC and a BT CODEC (both on external Port 6) and the
Bottom Connector (on external Port 7) simultaneously using network mode. SSI1 is the master.
• An external processor (external port - Port 5) drives a voice CODEC and a BT CODEC (both on
external Port 6) and the Bottom Connector (on Port 7) simultaneously using network mode. SAP
is the master.
NOTE
SSI1 (internal port), which is the master, drives a voice CODEC and a BT
CODEC (both on external Port 6) and the bottom connector (on external
Port 7) simultaneously using network mode.
An external processor (external port - Port 5), which is the master, drives a
voice CODEC and a BT CODEC (both on external Port 6) and the bottom
connector (on Port 7) simultaneously using network mode.
17.1.2.1
Port Receive Data Modes
Each port has logic to select which data lines are used to create the RxD line for the corresponding host
interface. Figure 17-3 shows the logic used to create the RxD line for Port 1. This logic has the following
modes of operation (as determined by MODE0):
• Normal
• Internal network mode
The subsequent sections describe the various modes of the port receive data logic. The following terms are
used to define the operation of the AUDMUX:
Network mode— Time-Division Multiplexed protocol for sending unique data to multiple devices
on a serial bus.
Internal network mode—Physical bus configuration where multiple serial buses are effectively
connected within the AUDMUX via digital logic to create point-to-multipoint connectivity. An
arbitrary number of devices are supported. Devices must be put into the high-impedance state as
specified by the network mode protocol. TxDATA lines of devices must be pulled high.
External network mode—Physical bus configuration where multiple serial buses are electrically
connected together on a printed circuit board (that is, external to the AUDMUX). Devices must put
their TxDATA lines into the high-impedance state as specified by the network mode protocol.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-5
Internal network
mode selection
matrix
1
0
1
TxD_in
INMMASK[n]
AUDMUX boundary
INMMASK[7:0]
1
RxD
(Port x)
0
MODE
RXDSEL[2:0]
TxD1_in
TxD2_in
TxD3_in
TxD4_in
TxD5_in
TxD6_in
TxD7_in
Figure 17-3. Receive Data Logic for Port x
17.1.2.1.1
Normal Mode
In normal mode (MODE0=0), the port is connected in a point-to-point configuration (as a master or a
slave) and the RXDSEL[2:0] setting selects the transmit signal from any port. In normal mode, any data
format can be used (that is, SSI normal mode, SSI network mode, AC-97, and others.
17.1.2.1.2
Internal Network Mode
In internal network mode (MODE0 = 1), the output of the AND gate is routed (via the output of the port)
to the RxD signal of the corresponding host interface. The INMMASK bit vector selects the transmit
signals of the ports that are to be connected in network mode. The transmit signals received at the
AUDMUX ports (TxDn_in) are ANDed together to form the output. In internal network mode, only one
device can be transmitting in its predesignated timeslot and all other transmit signals must remain high (be
in high-impedance state and pulled-up). Therefore, non-active signals in the selection will be high and do
not influence the output of the AND gate.
Network mode is a protocol where a master SSI is connected to more than one slave SSI device and
communication occurs on a time-slotted frame. Though network mode can allow master-slave and
slave-slave communication, internal network mode supports only master-slave communication.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-6
Freescale Semiconductor
There are two scenarios where internal network mode can be used with external network mode:
1. Slave-only devices are attached to an external port.
2. A master device is attached to an external port and all slave devices connected to the same external
port are disabled.
NOTE
When internal network mode is enabled at an external port, RXDSEL[3:0]
for RxDn_obe selection is ignored and RxD_obe is always driven high (that
is, asserted for all timeslots). All slave devices connected to the same port
must be disabled.
Internal Network Mode Example 1
SSI1 and SSI2 are used with Port 4 in internal network mode as shown in Figure 17-4. No pull-up resistors
are required, since all the interfaces combined in internal network mode are on-chip interfaces. The
on-chip interfaces drive a logic ‘1’ when their output enables are logic ‘0’.
AUDMUX
Port 4
SSI 1
Device
Port 1
Port 5
KEY
SSI 2
Port x
Internal
Network Mode
Enabled
Port x
Active
Port x
Inactive
Port 2
Port 6
Port 3
Port 7
Figure 17-4. Block Diagram For Example 1
See Figure 17-5 for the timing diagram of Example 1. The clock and frame sync signals show the bit and
frame timing for the serial bus. The vertical dashed lines divide the frame into four timeslots.
The data lines for SSI1 and SSI2 (as well as their output enables) are shown. Note that the SSI transmits
a logic ‘1’ when its corresponding output enable is a logic ‘0’. The combined TxDATA line, which is the
logical AND of SSI1 and SSI2’s TxDATA lines, is used for Port 4’s TxDATA line.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-7
...
CLK
...
...
...
FS
SSI1 TxD
T0 (SSI LEFT)
T1 (SSI RIGHT)
T2
T3
SSI1 OE
SSI2 TxD
T0
T1
T2 (SSI2 LEFT)
T3 (SSI2 RIGHT)
T2 (SSI2 LEFT)
T3 (SSI2 RIGHT)
SSI2 OE
Combined TxD
(Port 4 RxD)
T0 (SSI LEFT)
T1 (SSI RIGHT)
Figure 17-5. Example Using All Internal Ports For Transmit Data
Internal Network Mode Example 2
The SSI, Port 4, and Port 5 are used with Port 6 in internal network mode, as shown in Figure 17-6. Note
that Port 4 and Port 5 are external ports. Therefore, pull-up resistors are required on the Port 4 RxDATA
and Port 5 RxDATA pins. This example shows the timing associated with using adjacent timeslots for the
SSI, Port 4, and Port 5.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-8
Freescale Semiconductor
Pull-up Resistor On
TxDATA Required
AUDMUX
Port 4
SSI
Device
Pull-up Resistor On
TxDATA Required
Port 1
Port 5
Device
KEY
Port 2
Port 6
Device
Port 3
Port x
Internal
Network Mode
Enabled
Port x
Active
Port x
Inactive
Port 7
Figure 17-6. Block Diagram For Example 2
The resistance value of the pull-up resistors must be sufficiently high such that a value of ‘0’ can be pulled
up to logic ‘1’ within half of a period of the bitclock. The required resistance must be no larger than:
Rmax = 1 ÷ (2 × fbc × C) where:
fbc is the frequency of the bitclock
C is the total system capacitance (ICs, board traces, and so on)
Figure 17-7 shows the timing diagram for this example. The clock and frame sync signals show the bit and
frame timing for the serial bus. The vertical dashed lines divide the frame into four timeslots.
The data lines for the SSI, Port 4, and Port 5 are shown. Note that the SSI transmits a logic ‘1’ when its
corresponding output enable is a logic ‘0’. The data lines from Port 4 and Port 5 at the pad are pulled high
by pull-up resistors when they are in the high-impedance state. The data lines from Port 4 and Port 5 at the
AUDMUX are pure digital signals and are constantly driven. The combined TxDATA line, which is the
logical AND of the SSI, Port 4, and Port 5’s TxDATA lines, is used for Port 6’s TxDATA line.
Note the highlighted areas in Figure 17-7. This shows the transition time that occurs while a TxDATA line
is being pulled high. In this example, this transition time is a maximum of 1/2 the period of the serial
bitclock. This prevents corruption of the first data bit of the next timeslot. It is critical that the pull-up
resistance is sufficient for the given bitclock frequency and system capacitance.
Note that hysteresis should be enabled at Port 4’s RxDATA pad and Port 5’s RxDATA pad to prevent the
digital signals created by the pad from toggling rapidly during the pull-up period. The pads typically
require a transition within 25 ns unless hysteresis is enabled. Instead of using hysteresis, one could select
a pull-up resistor sufficiently high to pull-up the signal at the pad within 25 ns; however, that would result
in a higher resistance value and higher current drain.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-9
...
CLK
...
...
...
FS
SSI TxD
T0
T1
T2
T3
HiZ
T3
SSI OE
1/2 Bit
Port 4 TxD
(At SoC Pin)
1/2 Bit
HiZ
Port 4 TxD
(At AUDMUX)
T1
T1
T3
1/2 Bit
Port 5 TxD
(At SoC Pin)
HiZ
HiZ
HiZ
T2
Port 5 TxD
(At AUDMUX)
Combined TxD
(Port 6 RxD)
T2
T0
T1
T2
T3
Figure 17-7. Example Using External Ports for Transmit Data in Consecutive Timeslots
Internal Network Mode Example 3
The SSI and Port 4 are used with Port 6 in internal network mode as shown in Figure 17-8. Note that Port
4 is an external port. Therefore, a pull-up resistor is required on the Port 4 TxDATA pin. This example
shows the timing associated with inserting empty timeslots after the timeslots have been used by external
ports.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-10
Freescale Semiconductor
Pull-up Resistor On
TxDATA Required
AUDMUX
Port 4
SSI
Device
Port 1
Port 5
KEY
Port 2
Port 6
Device
Port 3
Port x
Internal
Network Mode
Enabled
Port x
Active
Port x
Inactive
Port 7
Figure 17-8. Block Diagram For Example 3
The resistance value of the pull-up resistors must be sufficiently high such that a value of ‘0’ can be pulled
up to logic ‘1’ by the time that the next occupied timeslot occurs. This allows a much weaker pull-up to
be used as compared to Example 2. The required resistance must be no larger than:
Rmax = (4 × n + 1) ÷ (2 × fbc × C) where:
n is the number of bits per timeslot
fbc is the frequency of the bitclock
C is the total system capacitance (ICs, board traces, and so on)
Figure 17-9 shows the timing diagram for this example. The clock and frame sync signals show the bit and
frame timing for the serial bus. The vertical dashed lines divide the frame into four timeslots.
The data lines for the SSI and Port 4 are shown. Note that the SSI transmits a logic ‘1’ when its
corresponding output enable is a logic ‘0’. The data line from Port 4 at the pad is pulled high by a pull-up
resistor when they are in the high-impedance state. The data line from Port 4 at the AUDMUX is a pure
digital signal and is constantly driven. The combined TxDATA line, which is the logical AND of the SSI
and Port 4’s TxDATA lines, is used for Port 6’s RxDATA line.
Note the highlighted area in Figure 17-9. This shows the transition time that occurs while Port 4’s
TxDATA line is being pulled high. In this example, this transition time is a maximum of two timeslots plus
1/2 the period of the serial bitclock. This prevents corruption of the first data bit of the next timeslot. It is
critical that the pull-up resistance is sufficient for the given bitclock frequency and system capacitance.
Note that hysteresis must be enabled at Port 4’s RxDATA pad to prevent the digital signal created by the
pad from toggling rapidly during the extended pull-up period. The pads typically require a transition within
25 ns unless hysteresis is enabled.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-11
...
CLK
...
...
...
FS
SSI TxD
T0
T1
T2
T3
HiZ
T1
HiZ
HiZ
SSI OE
1/2 Bit
Port 4 TxD
(At SoC Pin)
Port 4 TxD
(At AUDMUX)
Combined TxD
(Port 6 RxD)
T1
T0
T1
Figure 17-9. Example Using External Ports For Transmit Data In Nonconsecutive Timeslots
17.1.2.1.3
Transmit Data Output Enable Assertion
The TxDATA line from the internal network mode master (connected at any internal port) is put into the
high-impedance state at the pad depending upon the assertion or deassertion of TxD_obe, its
corresponding output enable generated by the network mode master.
In the case of an external network mode master (connected at an external port), the corresponding
TxD_obe is always asserted after the port data register configuration.
17.1.2.2
Tx/Rx Switch and External Network Mode
External network mode is the traditional network mode connection. It is called external network mode to
differentiate from the internal network mode. In external network mode, devices are connected to a single
external port in a star or multi-drop configuration.
In network mode, there can be only one master (driving the frame sync and clock source) with the other
devices configured in normal slave mode or network slave mode. Unlike internal network mode, both
master-slave and slave-slave communication can take place in external network mode. CODEC devices
transmit on a single timeslot while processor serial interfaces (that is, SSI, SAP) can process more than
one timeslot of data while in network master or slave mode.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-12
Freescale Semiconductor
Figure 17-10 shows the Tx/Rx data switch. RxD_obe is the output buffer enable signal and RxD_out is the
data transmit signal from the serial interface. The TxD_in signal is the receive data signal going towards
the RXDSEL muxes of all ports.
D_TxRx is the data pin which serves as the chip-level transmit data pin when the TxRx switch is not
enabled. D_RxTx is the data pin which serves as the chip-level receive data pin when the TxRx switch is
not enabled. The roles of these pins are reversed when the TxRx switch is enabled.
When TXRXEN is disabled (TXRXEN = 0), RxD_out is routed to D_TxRx and D_RxTx is routed to
TxD_in. The output buffer enable, selected by RXDSEL[2:0], is routed to Db_obe.
When the Tx/Rx switch is enabled (TXRXEN = 1), RxD_out is routed to D_RxTx and D_TxRx is routed
to TxD_in. The output buffer enable, selected by RXDSEL[2:0], is routed to Da_obe.
If the RXDSELn[2:0] field for any Port n is configured to select data from an internal port, the output
buffer enable is selected by RXDSELn[2:0] and is routed to Dan_obe/Dbn_obe. In the case when the
RXDSELn[2:0] field for Port n is configured to select data from an external port, the output buffer enable
is always high and routed to Dan_obe/Dbn_obe, depending on the TXRXENn switch configuration.
AUDMUX boundary
Pin Interface Boundary
TXRXEN
RxD_obe
0
Db_obe
1
IOPAD
D_TxRx
RxD_out
0
1
Db_out
Db_in
Da_obe
IOPAD
Da_out
TxD_in
0
D_RxTx
Da_in
1
TX/RX SWITCH
Figure 17-10. Tx/Rx Switch
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-13
17.1.2.3
Timing Modes
The AUDMUX ports are constructed as 6-wire interfaces. However, they can be used either in
synchronous or asynchronous modes as determined by the SYN bit.
17.1.2.3.1
Synchronous Mode (4-wire Interface)
In Synchronous mode, the port has a 4-wire interface (that is, RxD, TxD, TxCLK, TxFS). The receive data
timing is determined by TxCLK and TxFS.
As shown in Figure 17-11, Port x signals can be routed to Port y, producing 6-wire to 4-wire port
connectivity.
TFS_in, RFS_in, TCLK_in, and RCLK_in are the input frame sync and bit clocks from the serial interface
(Port x) with their corresponding output buffer enable signals (_obe). TFS_out, RFS_out, TCLK_out, and
RCLK_out are the frame sync and bit clocks that are transmitted to the serial interface from the other ports.
The TFS_out and TCLK_out are selected at Port x by the TFSEL and TCSEL mux settings, respectively.
RFS_out and RCLK_out are selected at Port x by the RFSEL and RCSEL mux settings, respectively.
Similarly, in the external direction, Port y is configured as a 4-wire port; TFSEL selects the FS_obe and
FS_out signals. In this mode, the configuration of RFSEL and RCSEL is not used, since the RFS_out and
RCLK_out pins at Port y are not available.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-14
Freescale Semiconductor
TFSELy[3:0]
AUDMUX Boundary
AUDMUX Boundary
Pin Boundary
Port y
Port x
TFS_obe
TFS_in
FS_obe
TFS_out
TxFS
FS_out
FS_in
IOPAD
TFSELx[3:0]
RFS_obe
RFS_in
RFS_out
RFSELx[3:0]
TFSn_obe, TFSn_in, RFSn_obe,
RFSn_in and FSn_in to/from other ports
TFSELy[3:0]
TCLK_obe
TCLK_in
CLK_obe
TCLK_out
TxCLK
CLK_out
CLK_in
IOPAD
TCSELx[3:0]
RCLK_obe
RCLK_in
RCLK_out
RCSELx[3:0]
TCLKn_obe, TCLKn_in, RCLKn_obe
RCLKn_in and CLKn_in
to/from other ports
Figure 17-11. Frame Sync and Clock Routing When External Port Is 4-wire
17.1.2.3.2
Asynchronous Mode (6-wire Interface)
In Asynchronous mode, the port has a 6-wire interface (meaning RxD, TxD, TxCLK, TxFS, RxCLK,
RxFS). This mode has additional receive clock (RxCLK) and frame sync (RxFS) signals as compared to
the synchronous or 4-wire interface.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-15
As shown in Figure 17-12 and Figure 17-13, Port x signals can be routed to Port y, producing 6-wire to
6-wire port connectivity.
TFS_in, RFS_in, TCLK_in, and RCLK_in are input frame sync and bit clocks from the serial interface
(Port x) with their corresponding output buffer enable signals (_obe). TFS_out, RFS_out, TCLK_out, and
RCLK_out are the frame sync and bit clocks that are transmitted to the serial interface from the other ports.
TFS_out and TCLK_out are selected by the TFSEL and TCSEL mux settings, respectively. RFS_out and
RCLK_out are selected by the RFSEL and RCSEL mux settings, respectively. Similarly, in the external
direction, the TFSEL selects the TxFS_obe and TxFS_out signals and TCSEL selects the TxCLK_obe and
TxClk_out signals. The RFSEL selects the RxFS_obe and RxFS_out signals and RCSEL selects the
RxCLK_obe and RxCLK_out signals.
NOTE
Since FS_in and CLK_in from external interfaces are also routed to the
TFSEL and TCSEL muxes of the external ports, respectively, these signals
do not have corresponding buffer enable signals. Consequently, their
corresponding inputs to the TFSEL and TCSEL mux of the external ports
have to be tied high.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-16
Freescale Semiconductor
TFSELy[3:0]
AUDMUX Boundary
AUDMUX Boundary
Pin Boundary
PORT y
PORT x
TFS_obe
TFS_in
TFS_obe
TFS_out
TxFS
TFS_out
TFS_in
IOPAD
TFSELx[3:0]
RFS_obe
RFS_in
RFS_out
RFSELx[3:0]
TFSn_obe, TFSn_in, RFSn_obe,
RFSn_in and FSn_in to/from other ports
RFSELy[3:0]
TFS_obe
TFS_in
RFS_obe
TFS_out
RxFS
RFS_out
RFS_in
IOPAD
TFSELx[3:0]
RFS_obe
RFS_in
RFS_out
RFSELx[3:0]
TFSn_obe, TFSn_in, RFSn_obe
RFSn_in and FSn_in
to/from other ports
Figure 17-12. Frame Sync Routing When External Port Is 6-wire
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-17
TCSELy[3:0]
AUDMUX Boundary
AUDMUX Boundary
Pin Boundary
PORT y
PORT x
TCLK_obe
TCLK_in
TCLK_obe
TCLK_out
TxCLK
TCLK_out
TCLK_in
IOPAD
TCSELx[3:0]
RCLK_obe
RCLK_in
RCLK_out
RCSELx[3:0]
TClkn_obe, TClkn_in, RClkn_obe,
RClkn_in and Clkn_in to/from other ports
RCSELy[3:0]
TCLK_obe
TCLK_in
RCLK_obe
TCLK_out
RxCLK
RCLK_out
RCLK_in
IOPAD
TCSELx[3:0]
RCLK_obe
RCLK_in
RCLK_out
RCSELx[3:0]
TCLKn_obe, TCLKn_in, RCLKn_obe
RCLKn_in and CLKn_in
to/from other ports
Figure 17-13. Clock Routing When External Port Is 6-wire
17.1.3
Connectivity Between Ports
Four basic types of connections are provided by the AUDMUX:
• Internal port to external port
• External port to external port
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-18
Freescale Semiconductor
•
•
Internal port to internal port
Loopback
The corresponding data connections are described in the following sections.
17.1.3.1
Internal Port to External Port Connectivity
Figure 17-14 shows the data path connections between an internal port and an external port. The internal
port is connected to a processor’s serial interface. TxD_obe is the buffer enable signal from the serial
interface, TxD_in is the input transmit data from the serial interface to the AUDMUX, and RxD_out is the
receive data output from the AUDMUX to the serial interface.
RXDSEL[2:0] of the external port selects the buffer enable signal (TxD_obe) and transmit data output
(TxD_out) signal from the TxD_obe and RxD_in signals. RXDSEL[2:0] is a common signal to both
selection muxes.
NOTE
Since buffer TxD_in signals from external interfaces do not have
corresponding buffer enable signals, their buffer enable signals into the
selection mux are tied high. This will ensure that selection of TxD_in, as
RxD_out will also drive the RxD_obe output high.
Transmit Data from the serial interface goes into the RXDSEL data mux and comes out as RxD_out.
RxD_out is routed to Da_TxRx when TXRXEN is disabled and to D_RxTx when TXRXEN is enabled.
Similarly, D_RxTx is routed to TxD_in when TXRXEN is disabled and D_TxRx is routed to TxD_in when
TXRXEN is enabled. The routing of frame syncs is shown in Figure 17-12 and the routing of interface
clocks is shown in Figure 17-13.
If internal network mode is disabled, then RXDSEL selects the TxD_in, which is sent from the AUDMUX
to the serial interface connected at Port x. When the internal network mode is selected, RxD_out is
constructed by ANDing selected TxD_in signals from the ports (as determined by INMMASK).
If there is more than one device attached to the external port at D_TxRx and D_RxTx and one of the
devices is a network master, then two conditions must be noted:
1. When the external master is enabled in network mode, then the serial interface at Port x must be
configured as a slave (normal or network mode). No Tx/Rx switching is required.
2. When the external master is disabled and the serial interface at Port x and other slave devices must
communicate, then the serial interface at Port x must be configured as a network mode master and
the Tx/Rx switch at Port y must be enabled (TXRXEN = 1). This will ensure that the transmit and
receive paths are connected appropriately.
To communicate with more than one port, internal network mode can be enabled at Port x. In internal
network mode, it is possible to communicate with any device attached to the other ports. Internal network
mode shall be enabled at the port that is the SSI network mode master.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-19
Figure 17-14. Internal to External Port Interconnection
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-20
Freescale Semiconductor
RxD_out
TxD_in
TxD_obe
Db_in
Da_in
Da_out
Db_out
AUDMUX Boundary
to/from other ports
1
0
1
0
1
0
TXRX SWITCH
RxD_out
RxD_obe
MODEy[1:0]
TxD_in
RXDSELy[3:0]
1’b1
Da_in
Da_out
Db_in
Da_obe
Db_out
Db_obe
AUDMUX Boundary
TXRXENy
PORTy
MODEy[1:0]
RXDSELy[3:0]
INMASKy[7:0]
TxDn_in, TxDn_obe
RXDSELx[3:0]
INMASKx[7:0]
MODEx[1:0]
TxD_in
RxD_out
TXRX SWITCH
1
0
1
0
TXRXENx
TxD_obe
PORTx
IOPAD
IOPAD
D_RxTx
D_TxRx
Pin Boundary
17.1.3.2
External Port to External Port Connectivity
External ports can communicate with external ports directly. External ports can communicate together in
three ways:
1. Each port’s receive logic is configured in normal mode (MODE[0:1] = 00). Each port’s
RXDSEL[2:0] field is configured to select the other port’s transmit data. Bit fields associated with
clock/frame sync selection and direction are configured for each port. Either port can be the master.
2. One port is configured in internal network mode (MODE[0:1] = 01). All desired data lines are
combined by the AND gate as determined by INMMASK[7:0]. Since an external port is being used
as the internal network mode master, all other devices on the same AUDMUX port as the internal
network mode master must be disabled. This configuration can be used with a combination of
internal and external ports. All external ports must have a pull-up resistor on its RxDATA pin. Bit
fields associated with clock/frame sync selection and direction are configured for each port. Any
port can be the master.
17.1.3.3
Internal Port to Internal Port Connectivity
Internal ports can communicate with other internal ports directly. Internal ports can communicate together
in three ways:
1. Each port’s receive logic is configured in normal mode (MODE[0:1] = 00). Each port’s
RXDSEL[2:0] field is configured to select the other port’s transmit data. Bit fields associated with
clock/frame sync selection and direction are configured for each port. Either port can be the master.
2. One port is configured in internal network mode (MODE[0:1] = 01). All desired data lines are
combined by the AND gate as determined by INMMASK[7:0]. This configuration can be used
with a combination of internal and external ports. All external ports must have a pull-up resistor on
its RxDATA pin. Bit fields associated with clock/frame sync selection and direction are configured
for each port. Any port can be the master.
17.1.3.4
Loopback Connectivity
AUDMUX ports can communicate with themselves in order to provide loopback functionality. Port x can
route its TxDATA signal to its own RxD_out signal by setting RXDSELx[2:0] to its own port number. This
is supported by all ports in the AUDMUX.
In addition, ports can provide loopback support in internal network mode. With internal network mode,
the internal network mode master can loop its TxDATA signal (combined with those of other ports, if
desired) back into its RxD_out signal. Port x’s INMMASK should be set such that bit (x - 1) is clear in
order to enable the loopback.
17.2
External Signal Description
The following section provides the external signal descriptions for AUDMUX.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-21
17.2.1
Overview
Table 17-1 lists pad-level signals of the AUDMUX for the external ports, where Pn is P, to P7 and m = n
-.The port is configured as an external port by a static system level signal input pn_int_ext_select.
Table 17-1. Signal Properties
Name
Port
I/O
Function
Reset State
Pull-up
ADm_TXD
Pn
I/O
Transmitted Data from Pn
1
Active
ADm_RXD
Pn
I/O
Received Data at Pn
1
Active
ADm_TXC
Pn
I/O
Transmit Clock input/output at Pn
1
-
ADm_RXC
Pn
I/O
Receive Clock input/output at Pn
1
-
ADm_TXFS
Pn
I/O
Transmit Frame sync input/output at Pn
1
-
ADm_RXFS
Pn
I/O
Receive Frame sync input/output at Pn
1
-
17.3
Memory Map and Register Definition
The AUDMUX memory map is shown in Table 17-2.
Table 17-2. AUDMUX Memory Map
Address
Register
Access
Reset Value
Section/Page
0x53FC_4000 (PTCR1)
Port Timing Control Register 1 (PTCR1)
RW
0xAD40_0800
17.3.2.1/17-2
6
0x53FC_4004 (PDCR1)
Port Data Control Register 1 (PDCR1)
RW
0x0000_A000
17.3.2.2/17-2
8
0x53FC_4008 (PTCR2)
Port Timing Control Register 2 (PTCR2)
RW
0xA500_0800
17.3.2.3/17-2
9
0x53FC_400C (PDCR2)
Port Data Control Register 2 (PDCR2)
RW
0x0000_8000
17.3.2.4/17-3
1
0x53FC_4010 (PTCR3)
Port Timing Control Register 3 (PTCR3)
RW
0x9CC0_0800
17.3.2.5/17-3
3
0x53FC_4014 (PDCR3)
Port Data Control Register 3 (PDCR3)
RW
0x0000_6000
17.3.2.6/17-3
5
0x53FC_4018 (PTCR4)
Port Timing Control Register 4 (PTCR4)
RW
0x0000_0800
17.3.2.7/17-3
6
0x53FC_401C (PDCR4)
Port Data Control Register 4 (PDCR4)
RW
0x0000_4000
17.3.2.8/17-3
8
0x53FC_4020 (PTCR5)
Port Timing Control Register 5 (PTCR5)
RW
0x0000_0800
17.3.2.9/17-4
0
0x53FC_4024 (PDCR5)
Port Data Control Register 5 (PDCR5)
RW
0x0000_2000
17.3.2.10/1742
0x53FC_4028 (PTCR6)
Port Timing Control Register 6 (PTCR6)
RW
0x0000_0800
17.3.2.11/1743
0x53FC_402C (PDCR6)
Port Data Control Register 6 (PDCR6)
RW
0x0000_0000
17.3.2.12/1745
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-22
Freescale Semiconductor
Table 17-2. AUDMUX Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x53FC_400x30 (PTCR7)
Port Timing Control Register 7 (PTCR7)
RW
0x0000_0800
17.3.2.13/1746
0x53FC_4034 (PDCR7)
Port Data Control Register 7 (PDCR7)
RW
0x0000_C000
17.3.2.14/1748
17.3.1
Register Summary
Table 17-4 shows the control register and address mapping for the AUDMUX. Figure 17-5 shows the
register fields key. Table 17-3 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 17-15. Key to Register Fields
Table 17-3. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
slfclr
Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero.
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-23
Table 17-4. Register Summary
Address
R
W
0x53FC_4000 (PTCR1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TF
S
DI
R
R
0
0
RCL
KDI
R
RFSEL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MOD
E
W
0
RFS
DIR
TCSEL[3:0]
SY
N
RCSEL[3:0]
R
TCL
KDI
R
TFSEL[3:0]
W
0x53FC_4004 (PDCR1)
R
RXDSEL[2:0]
W
R
W
0x53FC_4008 (PTCR2)
TF
S
DI
R
R
0
0
RCL
KDI
R
RFSEL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MOD
E
W
0
RFS
DIR
TCSEL[3:0]
SY
N
RCSEL[3:0]
R
TCL
KDI
R
TFSEL[3:0]
INMMASK[7:0]
W
0x53FC_400C (PDCR2)
R
RXDSEL[2:0]
W
R
W
0x53FC_4010 (PTCR3)
TF
S
DI
R
R
0
0
RCL
KDI
R
RFSEL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MOD
E
W
0
RFS
DIR
TCSEL[3:0]
SY
N
RCSEL[3:0]
R
TCL
KDI
R
TFSEL[3:0]
INMMASK[7:0]
W
0x53FC_4014 (PDCR3)
R
RXDSEL[2:0]
W
INMMASK[7:0]
W
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-24
Freescale Semiconductor
Table 17-4. Register Summary (continued)
Address
R
W
0x53FC_4018 (PTCR4)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TF
S
DI
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MO
DE
W
0
0
RCL
KDI
R
RFSEL[3:0]
0
RCSEL[3:0]
0
RFS
DIR
TCSEL[3:0]
SY
N
R
R
TCL
KDI
R
TFSEL[3:0]
W
0x53FC_401C (PDCR4)
R
RXDSEL[2:0]
W
R
W
0x53FC_4020 (PTCR5)
TF
S
DI
R
R
0
0
RCL
KDI
R
RFSEL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MO
DE
W
0
RFS
DIR
TCSEL[3:0]
SY
N
RCSEL[3:0]
R
TCL
KDI
R
TFSEL[3:0]
INMMASK[7:0]
W
0x53FC_4024 (PDCR5)
R
RXDSEL[2:0]
W
R
W
0x53FC_4028 (PTCR6)
TF
S
DI
R
R
0
0
RCL
KDI
R
RFSEL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MO
DE
W
0
RFS
DIR
TCSEL[3:0]
SY
N
RCSEL[3:0]
R
TCL
KDI
R
TFSEL[3:0]
INMMASK[7:0]
W
0x53FC_402C (PDCR6)
R
RXDSEL[2:0]
W
INMMASK[7:0]
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-25
Table 17-4. Register Summary (continued)
Address
R
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TF
S
DI
R
W
0x53FC_400x30
(PTCR7)
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX
RX
EN
0
0
0
MO
DE
W
0
0
RCL
KDI
R
RFSEL[3:0]
0
RCSEL[3:0]
0
RFS
DIR
TCSEL[3:0]
SY
N
R
R
TCL
KDI
R
TFSEL[3:0]
W
0x53FC_4034 (PDCR7)
R
RXDSEL[2:0]
W
INMMASK[7:0]
W
17.3.2
Register Descriptions
There are two configuration registers for each port. There are a total of 15 configuration registers.
17.3.2.1
Port Timing Control Register 1 (PTCR1)
PTCR1 is the Port Timing Control Register for Port 1.
0x53FC_4000 (PTCR1)
31
R
30
Access: User read/write
29
28
27
26
25
TCLK
DIR
24
23
22
21
20
18
17
16
W
TFS
DIR
Reset
1
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFSEL[3:0]
R
RCSEL[3:0]
RFS
DIR
19
TCSEL[3:0]
RCL
KDIR
RFSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-16. Port Timing Control Register for Port 1
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-26
Freescale Semiconductor
Table 17-5. Register Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as
an output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the
TFSEL settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
21
RFS DIR
20–17
RFSEL[3:0]
16
RCLKDIR
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output
or input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL
settings determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as
an output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the
RFSEL settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be
sourced from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output
or input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL
settings determine the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-27
Table 17-5. Register Field Descriptions (continued)
Field
Description
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced
from TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the transmit
and receive sections use common clock and frame sync signals (that is, the port is a 4-wire interface).
When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are
used for the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
17.3.2.2
Port Data Control Register 1 (PDCR1)
PDCR1 is the Port Data Control Register for Port 1.
0x53FC_4004 (PDCR1)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
1
0
1
0
0
0
0
0
0
0
0
Figure 17-17. Port Data Control Register for Port 1 (PDCR1)
Table 17-6. PDCR (Port 1) Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
Description
Reserved
Receive Data Select. Selects the source port for the RxD data. RXDSEL is ignored if MODE[1:0] is
2’b01 (that is, Internal Network Mode is enabled).
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-28
Freescale Semiconductor
Table 17-6. PDCR (Port 1) Field Descriptions (continued)
Field
Description
12
TXRXEN
Transmit/Receive Switch Enable. Swaps the transmit and receive signals.
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
11-9
Reserved
8
MODE
Mode Select. This field selects the mode in which the port is to operate. The modes of operation
include the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDed together. RXDSEL is ignored.
INMMASK determines which RxD signals are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
17.3.2.3
Internal Network Mode Mask. Bit mask that selects the ports from which the RxD signals are to be
ANDed together for internal network mode. Bit 6 represents RxD from Port 7 and bit 0 represents RxD
from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
Port Timing Control Register 2 (PTCR2)
PTCR2 is the Port Timing Control Register for Port 2.
0x53FC_4008
(PTCR2)
31
Access: User Read/Write
30
R TFS
W DIR
Reset
29
28
27
26
25
TCLK
DIR
TFSEL[3:0]
24
23
22
21
20
RFS
DIR
TCSEL[3:0]
19
18
17
16
RCL
KDIR
RFSEL[3:0]
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
RCSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-18. Port Timing Control Register 2 (PTCR2)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-29
Table 17-7. PTCR2 Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the
TxFS pin of the interface as an output or input. When set as an input, the
TFSEL settings are ignored. When set as an output, the TFSEL settings
determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
Transmit Frame Sync Select. Selects the source port from which TxFS is
sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
26
TCLKDIR
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin
of the interface as an output or input. When set as an input, the TCSEL
settings are ignored. When set as an output, the TCSEL settings determine
the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
25–22
TCSEL[3:0]
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
21
RFS DIR
Receive Frame Sync Direction Control. This bit sets the direction of the
RxFS pin of the interface as an output or input. When set as an input, the
RFSEL settings are ignored. When set as an output, the RFSEL settings
determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
20–17
RFSEL
RFSEL - Receive Frame Sync Select
Selects the source port from which RxFS is sourced. RxFS can be sourced
from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
16
RCLKDIR
Receive Clock Direction Control. This bit sets the direction of the RxClk pin
of the interface as an output or input. When set as an input, the RCSEL
settings are ignored. When set as an output, the RCSEL settings determine
the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-30
Freescale Semiconductor
Table 17-7. PTCR2 Field Descriptions (continued)
17.3.2.4
Field
Description
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced.
RxClk can be sourced from TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
SYN—Synchronous/Asynchronous Select. When SYN is set, synchronous
mode is chosen and the transmit and receive sections use common clock
and frame sync signals (that is, the port is a 4-wire interface). When SYN is
cleared, asynchronous mode is chosen and separate clock and frame sync
signals are used for the transmit and receive sections (that is, the port is a
6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
Port Data Control Register 2 (PDCR2)
PDCR2 is the Port Data Control Register for Port 2.
0x53FC_400C
(PDCR2)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
1
0
0
0
0
0
0
0
0
0
0
Figure 17-19. Port Data Control Register 2 (PDCR2)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-31
Table 17-8. PDCR2 Field Descriptions
Field
31–16
Description
Reserved
15–13
RXDSEL[2:0]
Receive Data Select. Selects the source port for the RxD data. RXDSEL is
ignored if MODE[1:0] is 01 (that is, Internal Network mode is enabled).
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
12
TXRXEN
Transmit/Receive Switch Enable. Swaps the transmit and receive signals.
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
11-9
Reserved
8
MODE
Mode Select. This field selects the mode in which the port is to operate. The
modes of operation include the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is
routed to the port.
• Internal Network mode in which RxD from other ports are ANDED
together. RXDSEL is ignored. INMMASK determines which RxD signals
are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which of
the RxD signals are to be ANDed together for internal network mode. Bit 6
represents RxD from Port 7 and bit0 represents RxD from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-32
Freescale Semiconductor
17.3.2.5
Port Timing Control Register 3 (PTCR3)
PTCR3 is the Port Timing Control Register for Port 3.
0x53FC_4010
(PTCR3)
31
R
Access: User Read/Write
30
29
28
27
26
25
TCLK
DIR
24
23
22
21
20
18
17
16
W
TFS
DIR
Reset
1
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFSEL[3:0]
R
RCSEL[3:0]
RFS
DIR
19
TCSEL[3:0]
RCL
KDIR
RFSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-20. Port Timing Control Register 3 (PTCR3)
Table 17-9. PTCR3 Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as
an output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the
TFSEL settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output
or input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL
settings determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects RxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-33
Table 17-9. PTCR3 Field Descriptions (continued)
Field
Description
21
RFS DIR
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as an
output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the
RFSEL settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
20–17
RFSEL[3:0]
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be
sourced from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
16
RCLKDIR
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output
or input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL
settings determine the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced from
TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
SYN—Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the
transmit and receive sections use common clock and frame sync signals (that is, the port is a 4-wire
interface). When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync
signals are used for the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-34
Freescale Semiconductor
17.3.2.6
Port Data Control Register 3 (PDCR3)
PDCR3 is the Port Data Control Register for Port 3.
0x53FC_4014
(PDCR3)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
0
1
1
0
0
0
0
0
0
0
0
Figure 17-21. Port Data Control Register 3 (PDCR3)
Table 17-10. PDCR3 Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
12
TXRXEN
11-9
Description
Reserved
Receive Data Select. Selects the source port for the RxD data. RXDSEL is ignored if MODE[1:0] is 01
(that is, Internal Network Mode is enabled).
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
Transmit/Receive Switch Enable. Swaps the transmit and receive signals.
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-35
Table 17-10. PDCR3 Field Descriptions (continued)
Field
Description
8
MODE
Mode Select. This field selects the mode in which the port is to operate. The modes of operation include
the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDed together. RXDSEL is ignored.
INMMASK determines which RxD signals are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which of the RxD signals are to be
ANDed together for internal network mode. Bit 6 represents RxD from Port 7 and bit0 represents RxD
from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
17.3.2.7
Port Timing Control Register 4 (PTCR4)
PTCR4 is the Port Timing Control Register for Port 4.
Access: User Read/Write
0x53FC_4018
(PTCR4)
31
R
30
29
28
27
26
25
TCLK
DIR
24
23
22
21
20
18
17
16
W
TFS
DIR
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFSEL[3:0]
R
RCSEL[3:0]
RFS
DIR
19
TCSEL[3:0]
RCL
KDIR
RFSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-22. Port Timing Control Register 4 (PTCR4)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-36
Freescale Semiconductor
Table 17-11. PTCR4 Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as
an output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the
TFSEL settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
21
RFS DIR
20–17
RFSEL[3:0]
16
RCLKDIR
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output
or input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL
settings determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects RxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as an
output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the
RFSEL settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be
sourced from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output
or input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL
settings determine the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-37
Table 17-11. PTCR4 Field Descriptions (continued)
Field
Description
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced from
TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
SYN—Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the
transmit and receive sections use common clock and frame sync signals (that is, the port is a 4-wire
interface). When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync
signals are used for the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
17.3.2.8
Port Data Control Register 4 (PDCR4)
PDCR4 is the Port Data Control Register for Port 4.
0x53FC_401C (PDCR4)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
0
1
0
0
0
0
0
0
0
0
0
Figure 17-23. Port Data Control Register 4 (PDCR4)
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-38
Freescale Semiconductor
Table 17-12. PDCR4 Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
12
TXRXEN
11-9
Description
Reserved
Receive Data Select. Selects the source port for the RxD data. RXDSEL is ignored if MODE[1:0] is 01
(that is, Internal Network Mode is enabled).
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
Transmit/Receive Switch Enable. Swaps the transmit and receive signals
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
Mode Select. This field selects the mode in which the port is to operate.The modes of operation include
the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDED together. RXDSEL is ignored.
INMMASK determines which RxD signals are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which of the RxD signals are to be
ANDed together for internal network mode. Bit 6 represents RxD from Port 7 and bit0 represents RxD
from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-39
17.3.2.9
Port Timing Control Register 5 (PTCR5)
PTCR5 is the Port Timing Control Register for Port 5.
0x53FC_4020
(PTCR5)
31
R
Access: User Read/Write
30
29
28
27
26
25
TCLK
DIR
24
23
22
21
20
18
17
16
W
TFS
DIR
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFSEL[3:0]
R
RCSEL[3:0]
RFS
DIR
19
TCSEL[3:0]
RCL
KDIR
RFSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-24. Port Timing Control Register 5 (PTCR5)
Table 17-13. PTCR5 Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as
an output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the
TFSEL settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output
or input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL
settings determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects RxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-40
Freescale Semiconductor
Table 17-13. PTCR5 Field Descriptions (continued)
Field
Description
21
RFS DIR
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as
an output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the
RFSEL settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
20–17
RFSEL[3:0]
16
RCLKDIR
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be
sourced from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output
or input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL
settings determine the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced
from TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
SYN—Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the
transmit and receive sections use common clock and frame sync signals (that is, the port is a 4-wire
interface). When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync
signals are used for the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-41
17.3.2.10 Port Data Control Register 5 (PDCR5)
0x53FC_4024
(PDCR5)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
0
0
1
0
0
0
0
0
0
0
0
Figure 17-25. Port Data Control Register 5 (PDCR5)
Table 17-14. PDCR5 Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
12
TXRXEN
11-9
Description
Reserved
Receive Data Select. Selects the source port for the RxD data. RXDSEL is ignored if MODE[1:0] is 01
(that is, Internal Network Mode is enabled).
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
Transmit/Receive Switch Enable. Swaps the transmit and receive signals
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
8
MODE
Mode Select. This field selects the mode in which the port is to operate.The modes of operation include
the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDED together. RXDSEL is ignored.
INMMASK determines which RxD signals are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which of the RxD signals are to be
ANDed together for internal network mode. Bit 6 represents RxD from Port 7 and bit0 represents RxD
from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-42
Freescale Semiconductor
17.3.2.11 Port Timing Control Register 6 (PTCR6)
PTCR6 is the Port Timing Control Register for Port 6.
0x53FC_4028 (PTCR6)
31
R
30
Access: User Read/Write
29
28
27
26
25
TCLK
DIR
24
23
22
21
20
18
17
16
W
TFS
DIR
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFSEL[3:0]
R
RCSEL[3:0]
RFS
DIR
19
TCSEL[3:0]
RCL
KDIR
RFSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-26. Port Timing Control Register 6 (PTCR6)
Table 17-15. PTCR6 Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as
an output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the
TFSEL settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output
or input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL
settings determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects RxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-43
Table 17-15. PTCR6 Field Descriptions (continued)
Field
Description
21
RFS DIR
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as
an output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the
RFSEL settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
20–17
RFSEL[3:0]
16
RCLKDIR
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be
sourced from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output
or input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL
settings determine the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced
from TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
SYN—Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the
transmit and receive sections use common clock and frame sync signals (that is, the port is a 4-wire
interface). When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync
signals are used for the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-44
Freescale Semiconductor
17.3.2.12 Port Data Control Register 6 (PDCR6)
PDCR6 is the Port Data Control Register for Port 6.
0x53FC_402C (PDCR6)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 17-27. Port Data Control Register 6 (PDCR6)
Table 17-16. PDCR6 Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
12
TXRXEN
11–9
Description
Reserved
Receive Data Select. Selects the source port for the RxD data.
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
Transmit/Receive Switch Enable. Swaps the transmit and receive signals
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
8
MODE
Mode Select. This field selects the mode in which the port is to operate.The modes of operation include
the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDed together. RXDSEL is ignored.
INMMASK determines which RxD signals are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which of the RxD signals are to be
ANDed together for internal network mode. Bit 6 represents RxD from Port 7 and bit0 represents RxD
from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-45
17.3.2.13 Port Timing Control Register 7 (PTCR7)
PTCR7 is the Port Timing Control Register for Port 7.
0x53FC_400x30 (PTCR7)
31
R
30
Access: User Read/Write
29
28
27
26
25
TCLK
DIR
24
23
22
21
20
18
17
16
W
TFS
DIR
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFSEL[3:0]
R
RCSEL[3:0]
RFS
DIR
19
TCSEL[3:0]
RCL
KDIR
RFSEL[3:0]
SYN
W
Reset
0
0
0
0
1
Figure 17-28. Port Timing Control Register 7 (PTCR7)
Table 17-17. PTCR7 Field Descriptions
Field
Description
31
TFS DIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as an
output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the
TFSEL settings determine the source port of the frame sync.
0 TxFS is an input.
1 TxFS is an output.
30–27
TFSEL[3:0]
26
TCLKDIR
25–22
TCSEL[3:0]
Transmit Frame Sync Select. Selects the source port from which TxFS is sourced.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as an output
or input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL
settings determine the source port of the clock.
0 TxClk is an input.
1 TxClk is an output.
Transmit Clock Select. Selects the source port from which TxClk is sourced.
0xxx Selects RxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-46
Freescale Semiconductor
Table 17-17. PTCR7 Field Descriptions (continued)
Field
Description
21
RFS DIR
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as an
output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the
RFSEL settings determine the source port of the frame sync.
0 RxFS is an input.
1 RxFS is an output.
20–17
RFSEL[3:0]
Receive Frame Sync Select. Selects the source port from which RxFS is sourced. RxFS can be
sourced from TxFS and RxFS from other ports.
0xxx Selects TxFS from port.
1xxx Selects RxFS from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
16
RCLKDIR
Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as an output
or input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL
settings determine the source port of the clock.
0 RxClk is an input.
1 RxClk is an output.
15–12
RCSEL[3:0]
Receive Clock Select. Selects the source port from which RxClk is sourced. RxClk can be sourced from
TxClk and RxClk from other ports.
0xxx Selects TxClk from port.
1xxx Selects RxClk from port.
x000 Port 1
...
x110 Port 7
x111 Reserved
11
SYN
Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the transmit
and receive sections use common clock and frame sync signals (that is, the port is a 4-wire interface).
When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are
used for the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
10–0
Reserved
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-47
17.3.2.14 Port Data Control Register 7 (PDCR7)
PDCR7 is the Port Data Control Register for Port 7.
0x53FC_4034 (PDCR7)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXR
XEN
0
0
0
MOD
E
0
0
0
0
0
W
Reset
R
RXDSEL[2:0]
INMMASK[7:0]
W
Reset
1
1
0
0
0
0
0
0
0
0
0
Figure 17-29. Port Data Control Register 7 (PDCR7)
Table 17-18. PDCR7 Field Descriptions
Field
31–16
15–13
RXDSEL[2:0]
12
TXRXEN
11–9
Description
Reserved
Receive Data Select. Selects the source port for the RxD data.
xxx Port number for RxD
000 Port 1
...
110 Port 7
111 Reserved
Transmit/Receive Switch Enable. Swaps the transmit and receive signals
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
8
MODE
Mode Select. This field selects the mode in which the port is to operate. The modes of operation include
the following:
• Normal mode, in which the RxD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RxD from other ports are ANDed together. RXDSEL is ignored.
INMMASK determines which RxD signals are ANDed together.
0 Normal mode
1 Internal Network mode
7–0
INMMASK[7:0]
Internal Network Mode Mask. Bit mask that selects the ports from which of the RxD signals are to be
ANDed together for internal network mode. Bit 6 represents RxD from Port 7 and bit0 represents RxD
from Port 1.
0 Includes RxDn for ANDing
1 Excludes RxDn from ANDing
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-48
Freescale Semiconductor
17.3.3
AUDMUX Default Configuration
The AUDMUX reverts back to its default settings following a reset. Section 17.3.3.1, Default Port
Configuration,” describe the default configuration of the ports.
17.3.3.1
Default Port Configuration
The AUDMUX’s default port configuration after reset is as follows:
• Port 1 connected to Port 6
— Port 6 provides the clock and frame sync.
— Synchronous mode is enabled.
— Normal mode is selected.
• Port 2 connected to Port 5
— Port 5 provides the clock and frame sync.
— Synchronous mode is enabled.
— Normal mode is selected.
• Port 3 connected to Port 4
— Port 4 provides the clock and frame sync.
— Synchronous mode is enabled.
— Normal mode is selected.
• Port 7 in data loopback mode
— Clock and frame syncs are inputs.
— Synchronous mode is enabled.
— Normal mode is selected.
17.4
AUDMUX Clocking
This section provides information about AUDMUX clocking including clock inputs and the clock
diagram.
17.4.1
AUDMUX Clock Inputs
The IP Bus read/write clock—ipg_clk_s—is an input to the AUDMUX. It is used for all AUDMUX
register accesses. It is driven only when there is an AUDMUX access on the IP Bus.
) or external CODECs. The clock used for CE Bus Network mode is determined by PTCR7. Refer to
Section Section , “CE_Bus_dis Signal Generation,” for more details of the clock selection for CE Bus
Network mode.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-49
17.4.2
AUDMUX Clock Diagram
Figure 17-30 shows the clocking used in the AUDMUX.
AUDMUX
ips_module_en_audmux
AIPS
LPG
Low Power Gate
ipg_clk_s
Clock
ipg_clk
IP Interface
Registers
Gating
Cell
Figure 17-30. AUDMUX Clocking Scheme
17.4.3
•
•
17.5
Clocking Restrictions
Since the AUDMUX requires only ipg_clk_s, the AUDMUX places no restrictions on the bus
frequency.
All registers in the AUDMUX are control registers so their values will not change frequently. Their
values will be programmed when changing between use cases (not during use cases).
Initialization/Application Information
This section provides initialization and application information for AUDMUX.
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
17-50
Freescale Semiconductor
Chapter 18
Configurable Serial Peripheral Interface (CSPI)
The Configurable Serial Peripheral Interface (CSPI) module allows rapid data communication with fewer
software interrupts than conventional serial communications. The i.MX51 module contains one 8 × 32
receive buffer (RXFIFO) and one 8 × 32 transmit buffer (TXFIFO). Figure 18-1 shows the i.MX51 block
diagram.
IP Bus Interface
TXFIFO
RXFIFO
Clock
Generator
SPI_RDY
Control
SS[3:0]
SCLK
MISO
Shift Register
MOSI
Figure 18-1. i.MX51 Block Diagram
18.1
Overview
The i.MX51 is equipped with data FIFOs and is a master/slave configurable serial peripheral interface
module, capable of interfacing to both SPI master and slave devices. The i.MX51 Ready (SPI_RDY) and
Chip Select (SS) control signals enable fast data communication with fewer software interrupts.
This chapter describes the configuration and operation of the CSPI. Information such as base addresses
and features that are unique to the multiple devices is described as appropriate.
18.1.1
Features
The i.MX51 is used for fast data communication with fewer software interrupts. It includes the following
features:
• Full-duplex synchronous serial interface
• Master/Slave configurable
• Four chip selects to support multiple peripherals
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
Freescale Semiconductor
18-1
•
•
•
•
Transfer continuation function allows unlimited length data transfers
32-bit wide by 8-entry FIFO for both transmit and receive data
Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
DMA support
18.1.2
Modes of Operation
This module can be configured for master and slave modes. The details of each mode are as follows:
• Master Mode
When the CSPI module is configured as a master, it uses a serial link to transfer data between the
CSPI and an external device. A chip-enable signal and a clock signal are used to transfer data
between these two devices. If the external device is a transmit-only device, the CSPI master’s
output port can be ignored and used for other purposes. In order to use the internal TXFIFO and
RXFIFO, two auxiliary output signals, SS and SPI_RDY, are used for data transfer rate control.
The user can also program the sample period control register to a fixed data transfer rate.
• Slave Mode
When the CSPI module is configured as a slave, the user can configure the CSPI Control register
to match the external SPI master’s timing. In this configuration, SS becomes an input signal and is
used to control data transfers through the Shift register as well as to load/store the data FIFO.
18.2
External Signal Description
The following signals shown in Table 18-1 are used to control the serial peripheral interface.
Table 18-1. CSPI Signal Properties
Name
I/O
Reset
Pull-up
Chip selects
I/O
1
—
SCLK
SPI clock
I/O
0
Active
MISO
Master data in; slave data out
I/O
0
Passive
MOSI
Master data out; slave data in
I/O
0
—
I
1
Active
SS[3:0]
SPI_RDY
Function
SPI data ready in Master mode
i.MX51 Multimedia Applications Processor Reference Manual, Rev. 1
18-2
Freescale Semiconductor
Table 18-2 provides a detailed description of the CSPI signals.
Table 18-2. CSPI – Detailed Signal Descriptions
Signal
I/O
Description
MOSI
I/O Master Out Slave In. In Master