NXP i.MX534, i.MX535, i.MX537 Reference manual

NXP i.MX534, i.MX535, i.MX537 Reference manual
An addendum, titled Addendum to Rev. 2 of
the i.MX53 Applications Processor Reference
Manual (Rev. 2.1) has been added at the end
of this document.
i.MX53 Multimedia Applications
Processor Reference Manual
Document Number: iMX53RM
Rev. 2.1, 06/2012
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
2
Freescale Semiconductor, Inc.
Contents
Section Number
Title
Page
Chapter 1
Introduction
1.1
About This Document...................................................................................................................................................181
1.1.1
Audience....................................................................................................................................................182
1.1.2
Organization...............................................................................................................................................182
1.1.3
Suggested Reading.....................................................................................................................................182
1.1.3.1
General Information...............................................................................................................182
1.1.3.2
Related Documentation..........................................................................................................183
1.1.4
Conventions...............................................................................................................................................183
1.1.5
Register Diagram Field Access Type Legend............................................................................................185
1.1.6
Signal Conventions....................................................................................................................................185
1.1.7
Acronyms and Abbreviations.....................................................................................................................185
1.2
Overview.......................................................................................................................................................................187
1.3
Target Applications.......................................................................................................................................................187
1.4
Features.........................................................................................................................................................................187
1.5
Architectural Overview.................................................................................................................................................190
1.5.1
Simplified Block Diagram.........................................................................................................................190
1.5.2
Major Subsystems......................................................................................................................................191
1.5.3
Architectural Partitioning...........................................................................................................................192
1.5.4
Endianness Support....................................................................................................................................194
1.6
Block List......................................................................................................................................................................194
1.7
Memory Interfaces........................................................................................................................................................205
Chapter 2
Memory Map
2.1
ARM Platform System Memory Map...........................................................................................................................207
2.2
DMA Memory Map......................................................................................................................................................212
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Section Number
Title
Page
Chapter 3
Interrupts and SDMA Events
3.1
Overview.......................................................................................................................................................................213
3.2
ARM Platform Interrupts..............................................................................................................................................213
3.3
SDMA Event Mapping.................................................................................................................................................217
Chapter 4
External Signals and Pin Multiplexing
4.1
Overview.......................................................................................................................................................................221
4.2
Controlling Pin Multiplexing........................................................................................................................................221
4.3
4.2.1
Multiplexing and Pad Control....................................................................................................................222
4.2.2
Daisy Chain Control...................................................................................................................................372
Special Package Pins.....................................................................................................................................................399
Chapter 5
External Memory
5.1
Overview.......................................................................................................................................................................401
5.2
External Memory Interface - i.MX53 Specific Configuration......................................................................................403
5.3
5.4
5.2.1
EXTMC - AXI Bus Masters......................................................................................................................403
5.2.2
Features......................................................................................................................................................404
EXTMC Setup..............................................................................................................................................................406
5.3.1
Clock Domains...........................................................................................................................................406
5.3.2
Boot Scenarios...........................................................................................................................................406
5.3.3
Watermark Ports........................................................................................................................................407
5.3.4
EXTMC I/O Multiplexing.........................................................................................................................407
5.3.5
External Interface Module (EIM) boot configuration................................................................................413
External Memory Controller (EXTMC) Restrictions...................................................................................................414
5.4.1
Exclusive Access Support..........................................................................................................................414
5.4.2
Software LPMD.........................................................................................................................................414
5.4.3
Data Paths..................................................................................................................................................414
5.4.4
NAND Flash Restrictions/Limitations.......................................................................................................415
5.4.5
OneNAND Restrictions/Limitations..........................................................................................................416
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Section Number
Title
Page
Chapter 6
System Debug
6.1
6.2
6.3
Overview.......................................................................................................................................................................417
6.1.1
Introduction................................................................................................................................................417
6.1.2
Debug Strategy...........................................................................................................................................418
System JTAG Controller - SJC.....................................................................................................................................418
6.2.1
JTAG Topology.........................................................................................................................................418
6.2.2
System JTAG Controller Main Feature.....................................................................................................419
6.2.3
SJC TAP Port.............................................................................................................................................419
6.2.4
SJC Main Blocks........................................................................................................................................420
6.2.5
i.MX53 Specific SJC Features...................................................................................................................420
6.5
JTAG Disable Mode..............................................................................................................420
6.2.5.2
PROD ID and JTAG ID.........................................................................................................421
CoreSight Design Kit....................................................................................................................................................421
6.3.1
Memory Map and Register Definition.......................................................................................................421
6.3.2
CoreSight Clock Enable ............................................................................................................................422
6.3.3
CoreSight DAP and DAP_SYS.................................................................................................................422
6.3.4
Embedded Cross Trigger (ECT)................................................................................................................423
6.3.5
6.4
6.2.5.1
6.3.4.1
CoreSight CTM......................................................................................................................425
6.3.4.2
CoreSight CTI........................................................................................................................425
6.3.4.3
Extended CTI (CTI Wrapper)................................................................................................428
CoreSight Trace Port Interface (TPIU) .....................................................................................................428
Cortex A8 Core and Platform.......................................................................................................................................429
6.4.1
Cortex A8 Core Debug Support Features..................................................................................................429
6.4.2
Embedded Cross Trigger Interface............................................................................................................429
6.4.3
Additional Platform Debug Functionality..................................................................................................430
Smart Direct Memory Access (SDMA) Core...............................................................................................................430
6.5.1
SDMA On Chip Emulation Module (OnCE) Feature Summary...............................................................430
6.5.2
Other SDMA Debug Functionality............................................................................................................431
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Section Number
6.5.3
Title
Page
Embedded Cross Trigger Interface (SDMA).............................................................................................432
6.6
External Memory Controller (EXTMC).......................................................................................................................432
6.7
Debug Visibility - IOMUX...........................................................................................................................................433
6.8
ARM Platform Peripherals...........................................................................................................................................433
6.8.1
Image Processing Unit (IPU).....................................................................................................................433
6.8.2
Video Processing Unit (VPU)....................................................................................................................434
6.8.3
GPU3D.......................................................................................................................................................434
6.9
Supported Tools............................................................................................................................................................434
6.10
Interrupt Visibility .......................................................................................................................................................435
6.11
Miscellaneous...............................................................................................................................................................435
6.12
6.11.1
SoC-level Bus Trace..................................................................................................................................435
6.11.2
Clock / Reset / Power.................................................................................................................................435
6.11.3
RVI connection Settings............................................................................................................................435
System Debug SJC Memory Map/Register Definition.................................................................................................436
6.12.1
General Purpose Unsecured Status Register 1 (SJC_GPUSR1)................................................................438
6.12.2
General Purpose Unsecured Status Register 2 (SJC_GPUSR2)................................................................440
6.12.3
General Purpose Unsecured Status Register 3 (SJC_GPUSR3)................................................................441
6.12.4
General Purpose Secured Status Register (SJC_GPSSR)..........................................................................442
6.12.5
Debug Control Register (Secured) (SJC_DCR).........................................................................................442
6.12.6
Security Status Register (SJC_SSR)..........................................................................................................444
6.12.7
Charge Pump Configuration Register (SJC_CPCR)..................................................................................446
6.12.8
General Purpose Clocks Control Register (SJC_GPCCR)........................................................................446
6.12.9
PLL Bypass Register (SJC_PLLBR).........................................................................................................448
6.12.10
General Purpose Unsecured Control Register 1 n (SJC_GPUCR1)..........................................................450
6.12.11
General Purpose Unsecured Control Register 2 n (SJC_GPUCR2)..........................................................452
6.12.12
General Purpose Unsecured Control Register 3 n (SJC_GPUCR3)..........................................................453
6.12.13
General Purpose Secured Control Register (SJC_GPSCR).......................................................................456
6.12.14
Test Register (SJC_TESTREG).................................................................................................................456
6.12.15
Serial Access Select Register (SJC_SASR)...............................................................................................457
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Section Number
Title
Page
6.12.16
BIST Configuration Register 1 (SJC_BISTCR1)......................................................................................457
6.12.17
BIST Configuration Register 2 (SJC_BISTCR2)......................................................................................459
6.12.18
BIST Configuration Register 3 (SJC_BISTCR3)......................................................................................460
6.12.19
BIST Configuration Register 4 n (SJC_BISTCR4)...................................................................................461
6.12.20
BIST Configuration Register 5 (SJC_BISTCR5)......................................................................................463
6.12.21
Bist Configuration Register 6 (SJC_BISTCR6)........................................................................................464
6.12.22
Bist Configuration Register 7 (SJC_BISTCR7)........................................................................................464
6.12.23
Memory BIST Pass-Fail Register 1 (reserved for Test) (SJC_MBISTPASSR1)......................................465
6.12.24
Memory BIST Pass-Fail Register 2 (SJC_MBISTPASSR2).....................................................................467
6.12.25
Memory BIST Done Register 1 (SJC_MBISTDONER1).........................................................................468
6.12.26
Memory BIST Done Register 2 (SJC_MBISTDONER2).........................................................................470
6.12.27
Memory BIST Mask Register 2 (SJC_MBISTMASKR2)........................................................................470
6.12.28
BIST Pass-Fail Register (SJC_BISTPASSR)............................................................................................471
6.12.29
BIST Done Register (SJC_BISTDONER)................................................................................................471
6.12.30
Monitor BIST Select Register (SJC_MONBISTSELR)............................................................................472
6.12.31
RVAL/WVAL Control Register (SJC_RWVALCR)................................................................................472
Chapter 7
System Boot
7.1
Introduction...................................................................................................................................................................473
7.2
Boot Modes...................................................................................................................................................................474
7.3
7.2.1
Boot Mode Pin Settings.............................................................................................................................474
7.2.2
High Level Boot Sequence........................................................................................................................475
7.2.3
Internal Boot (BOOT_MODE[1:0] = 0b00)..............................................................................................476
7.2.4
Boot From Fuses (BOOT_MODE[1:0] = 0b10)........................................................................................476
7.2.5
Mode: Serial Downloader (BOOT_MODE[1:0] = 0b11)..........................................................................477
7.2.6
Boot Security Settings................................................................................................................................478
Device Configuration....................................................................................................................................................478
7.3.1
Boot eFUSE Descriptions..........................................................................................................................479
7.3.2
GPIO Boot Overrides.................................................................................................................................481
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Section Number
7.3.3
7.4
7.5
Title
Page
Device Configuration Data........................................................................................................................481
Device Initialization......................................................................................................................................................482
7.4.1
Internal ROM /RAM Memory Map...........................................................................................................482
7.4.2
Boot Block Activation ..............................................................................................................................483
7.4.3
Clocks at Boot Time..................................................................................................................................484
7.4.4
Enabling MMU and Caches.......................................................................................................................488
7.4.5
Exception Handling....................................................................................................................................488
7.4.6
Interrupt Handling During Boot.................................................................................................................489
7.4.7
Persistent Bits.............................................................................................................................................489
Boot Devices (Internal Boot)........................................................................................................................................490
7.5.1
7.5.2
7.5.3
7.5.4
NOR Flash/OneNand using EIM Interface................................................................................................490
7.5.1.1
NOR Flash Boot Operation....................................................................................................491
7.5.1.2
OneNAND Flash Boot Operation..........................................................................................491
7.5.1.3
IOMUX Configuration for EIM Devices...............................................................................492
NAND Flash..............................................................................................................................................493
7.5.2.1
NAND eFUSE Configuration................................................................................................493
7.5.2.2
NAND Flash Boot Flow........................................................................................................495
7.5.2.3
Bad Block Marker Swapping.................................................................................................498
7.5.2.4
IOMUX Configuration for NAND........................................................................................499
Expansion Device......................................................................................................................................500
7.5.3.1
Expansion Device eFUSE Configuration..............................................................................500
7.5.3.2
MMC and eMMC Boot..........................................................................................................502
7.5.3.3
SD and eSD............................................................................................................................507
7.5.3.4
IOMUX Configuration for SD/MMC....................................................................................507
7.5.3.5
Redundant Boot Support for Expansion Device....................................................................508
Hard Disk and SSD....................................................................................................................................509
7.5.4.1
Hard Disk and SSD eFUSE Configuration............................................................................509
7.5.4.2
IOMUX Configuration for PATA..........................................................................................510
7.5.4.3
IOMUX Configuration for SATA..........................................................................................511
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Section Number
7.5.4.4
7.5.5
Title
Redundant Boot Support for Hard Disk and SSD..................................................................511
Serial ROM through SPI and I2C..............................................................................................................513
7.5.5.1
Serial ROM eFUSE Configuration........................................................................................513
7.5.5.2
I2C Boot.................................................................................................................................514
7.5.5.2.1
7.5.5.3
I2C IOMUX Pin Configuration......................................................................515
CSPI Boot..............................................................................................................................515
7.5.5.3.1
7.6
Page
ECSPI/CSPI IOMUX Pin Configuration........................................................517
Program Image..............................................................................................................................................................518
7.6.1
7.6.2
Image Vector Table and Boot Data............................................................................................................518
7.6.1.1
Image Vector Table Structure................................................................................................519
7.6.1.2
Boot Data Structure................................................................................................................520
Device Configuration Data (DCD)............................................................................................................520
7.6.2.1
Write Data Command............................................................................................................521
7.6.2.2
Check Data Command...........................................................................................................523
7.6.2.3
NOP Command......................................................................................................................525
7.7
Plugin Image.................................................................................................................................................................525
7.8
Serial Downloader (BOOT_MODE[1:0] = 0b11)........................................................................................................526
7.8.1
7.8.2
USB............................................................................................................................................................527
7.8.1.1
USB Configuration Details....................................................................................................527
7.8.1.2
IOMUX Configuration for USB............................................................................................528
UART.........................................................................................................................................................528
7.8.2.1
7.8.3
IOMUX Configuration for UART.........................................................................................528
Serial Download Protocol..........................................................................................................................529
7.8.3.1
Get Status...............................................................................................................................529
7.8.3.2
Read Memory.........................................................................................................................530
7.8.3.3
Write Memory........................................................................................................................530
7.8.3.4
Re-enumerate.........................................................................................................................531
7.8.3.5
Write File...............................................................................................................................531
7.8.3.6
Completed..............................................................................................................................532
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Section Number
Title
Page
7.9
Watchdog Reset Boot Mode.........................................................................................................................................533
7.10
High Assurance Boot (HAB)........................................................................................................................................533
7.11
7.10.1
ROM Vector Table Addresses...................................................................................................................534
7.10.2
SRTC Initialization....................................................................................................................................535
Examples.......................................................................................................................................................................535
7.11.1
NAND eFuse Configuration Example.......................................................................................................535
7.11.2
DCD Example............................................................................................................................................535
Chapter 8
Multimedia
8.1
The Video/Graphics Sub-System..................................................................................................................................539
8.2
Image Processing Unit (IPU)........................................................................................................................................542
8.2.1
External Ports-IPU.....................................................................................................................................545
8.2.1.1
Camera Port............................................................................................................................545
8.2.1.2
Display Ports..........................................................................................................................546
8.2.1.2.1
8.2.1.2.2
Access Modes.................................................................................................546
8.2.1.2.1.1
Synchronous Access...............................................................546
8.2.1.2.1.2
Asynchronous Access ............................................................547
The Interface...................................................................................................547
8.2.1.2.2.1
8.2.2
8.2.3
8.3
Connecting To Display Devices.............................................548
Processing-IPU...........................................................................................................................................548
8.2.2.1
Display Processor (DP)..........................................................................................................550
8.2.2.2
Video Deinterlacer (VDIC)....................................................................................................551
8.2.2.3
Image Converter (IC).............................................................................................................552
8.2.2.4
Image Rotator (IRT)...............................................................................................................552
Automatic Procedures................................................................................................................................553
LVDS Display Bridge (LDB).......................................................................................................................................554
8.3.1
External Ports-LDB....................................................................................................................................557
8.3.1.1
Input Parallel Display Ports...................................................................................................557
8.3.1.2
Output LVDS Ports................................................................................................................558
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Section Number
8.3.2
Title
8.3.1.3
Control Signals.......................................................................................................................558
8.3.1.4
Clock Sources........................................................................................................................558
Processing-LDB.........................................................................................................................................559
8.3.2.1
LDB Data Input Logic...........................................................................................................559
8.3.2.1.1
8.3.2.1.2
8.4
Page
Mapping of Input Data Busses........................................................................559
8.3.2.1.1.1
Channel Mapping...................................................................559
8.3.2.1.1.2
Input Bus Split........................................................................560
Bit Mapping....................................................................................................560
8.3.2.2
LDB Control .........................................................................................................................560
8.3.2.3
LDB Tx Clock .......................................................................................................................561
8.3.2.4
PHY........................................................................................................................................561
Video Processing Unit (VPU).......................................................................................................................................562
8.4.1
Basic Structure...........................................................................................................................................563
8.4.2
Feature Summary.......................................................................................................................................564
8.4.3
Other Features of VPU...............................................................................................................................565
8.4.4
Architectural Overview..............................................................................................................................565
8.4.5
Interfaces....................................................................................................................................................566
8.4.6
Operating Frequencies...............................................................................................................................567
8.4.7
Architectural Features................................................................................................................................568
8.4.8
Memory Requirements ..............................................................................................................................568
8.4.9
Internal Memory (iRAM)...........................................................................................................................568
8.4.10
External Memory (SDRAM).....................................................................................................................569
8.4.11
VPU Integration into SoC..........................................................................................................................570
8.4.12
External Bus Connection...........................................................................................................................570
8.4.13
Other Signals Connection..........................................................................................................................571
8.4.14
Clocking Architecture................................................................................................................................571
8.4.15
Power Management....................................................................................................................................572
8.4.16
Interrupt......................................................................................................................................................572
8.4.17
Reset...........................................................................................................................................................573
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Section Number
8.5
8.5.1
GPU3D Overview......................................................................................................................................574
8.5.2
GPU3D Features........................................................................................................................................574
Capabilities.............................................................................................................................575
8.5.3
GPU3D Block Diagram.............................................................................................................................576
8.5.4
GPU3D Performance.................................................................................................................................580
8.5.4.1
8.5.5
GPU3D Memory Accesses....................................................................................................581
GPU3D Clocking.......................................................................................................................................582
8.5.5.1
GPU3D Clock Gating ...........................................................................................................582
8.5.6
GPU3D Resets...........................................................................................................................................583
8.5.7
GPU3D Interrupts......................................................................................................................................583
8.5.8
Debug.........................................................................................................................................................583
8.5.9
Software.....................................................................................................................................................583
Graphics Processing Unit 2D (GPU2D).......................................................................................................................584
8.6.1
GPU2D Overview......................................................................................................................................584
8.6.2
GPU2D Features........................................................................................................................................585
8.6.2.1
2D Bitmap Graphics (Separate 2D unit)................................................................................585
8.6.2.2
Vector Graphics.....................................................................................................................586
8.6.3
GPU2D Block Diagram.............................................................................................................................587
8.6.4
GPU2D Performance.................................................................................................................................588
8.6.4.1
8.6.5
GPU2D Memory Accesses....................................................................................................588
GPU2D Clocking.......................................................................................................................................589
8.6.5.1
8.7
Page
OpenGL/ES Graphics Processing Unit 3D (GPU3D)..................................................................................................574
8.5.2.1
8.6
Title
GPU2D Clock Gating............................................................................................................589
8.6.6
GPU2D Resets...........................................................................................................................................589
8.6.7
GPU2D Interrupts......................................................................................................................................589
Audio Subsystem..........................................................................................................................................................589
8.7.1
Overview....................................................................................................................................................590
8.7.2
Audio Subsystem Block Diagram..............................................................................................................591
8.7.2.1
Standard Serial Interface Controller (SSI).............................................................................591
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8.7.2.2
Title
Page
Digital Audio MUX (AUDMUX)..........................................................................................592
8.7.3
Enhanced Serial Audio Interface (ESAI)...................................................................................................594
8.7.4
Sony/Philips Digital Interface (SPDIF).....................................................................................................594
8.7.5
Asynchronous Sample Rate Converter (ASRC)........................................................................................595
Chapter 9
Power Management
9.1
Overview.......................................................................................................................................................................599
9.2
Power Saving Methodology..........................................................................................................................................600
9.2.1
Active Power Savings................................................................................................................................600
9.2.2
Leakage Power Savings.............................................................................................................................600
9.3
Block Connectivity for Low Power Modes..................................................................................................................601
9.4
Low Power Modes........................................................................................................................................................602
9.4.1
Low Power Mode Inputs to Blocks in i.MX53..........................................................................................603
9.4.2
Power Down Sequence..............................................................................................................................603
9.4.3
Power Up Sequence...................................................................................................................................604
9.5
RAM Memory Supply Connections ............................................................................................................................604
9.6
Dynamic Voltage and Frequency Scaling (DVFS) ......................................................................................................605
Chapter 10
System Security
10.1
Introduction...................................................................................................................................................................607
Chapter 11
ARM Cortex A8 Platform (ARM Platform)
11.1
Introduction...................................................................................................................................................................611
11.2
Overview.......................................................................................................................................................................611
11.2.1
Core Platform Sub-Blocks.........................................................................................................................614
11.2.1.1
ARM platform........................................................................................................................614
11.2.1.2
Instruction Fetch....................................................................................................................615
11.2.1.3
Instruction Decode.................................................................................................................615
11.2.1.4
Instruction Execute................................................................................................................616
11.2.1.5
Load/Store..............................................................................................................................616
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Section Number
11.2.2
Page
11.2.1.6
L2 Cache................................................................................................................................616
11.2.1.7
NEON.....................................................................................................................................617
11.2.1.8
Processor Debug Unit............................................................................................................617
11.2.1.9
Embedded Trace Marcocell (ETM).......................................................................................617
11.2.1.10
Cross Trigger Interface 0 (CTI0)...........................................................................................618
Summary of Remaining Platform Components.........................................................................................618
11.2.2.1
Platform Controller ...............................................................................................................618
11.2.2.2
Debug Sub-Blocks.................................................................................................................619
11.2.2.3
11.3
Title
11.2.2.2.1
Embedded Trace Buffer (ETB).......................................................................619
11.2.2.2.2
AMBA Trace Bus (ATB) Replicator..............................................................619
11.2.2.2.3
Cross Trigger Interface 1 (CTI1)....................................................................620
11.2.2.2.4
Cross Trigger Matrix - CTM...........................................................................620
11.2.2.2.5
Advanced Peripheral Bus - APB Debug Bus..................................................620
Asynchronous Wrapper..........................................................................................................620
11.2.3
Configuration.............................................................................................................................................621
11.2.4
Endian Modes............................................................................................................................................621
11.2.5
Bus Interfaces.............................................................................................................................................621
11.2.5.1
AMBA AXI Interface............................................................................................................621
11.2.5.2
APB CoreSight Interface.......................................................................................................621
11.2.5.3
ATB CoreSight Interface.......................................................................................................622
11.2.5.4
Peripheral Interface (IP Bus)..................................................................................................622
Memory Map and Register Definition..........................................................................................................................622
11.3.1
Platform Version ID (ARM_PVID)...........................................................................................................623
11.3.2
General Purpose Control (ARM_GPC).....................................................................................................624
11.3.3
Low Power Control (ARM_LPC)..............................................................................................................625
11.3.4
NEON Low Power Control (ARM_NLPC)...............................................................................................626
11.3.5
Internal Clock Generation Control (ARM_ICGC)....................................................................................627
11.3.6
ARM Memory Configuration (ARM_AMC)............................................................................................629
11.3.7
NEON Monitor Control (ARM_NMC).....................................................................................................630
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Section Number
11.3.8
Title
Page
NEON Monitor Status (ARM_NMS)........................................................................................................631
11.4
Platform Clocks............................................................................................................................................................631
11.5
Platform Power Management.......................................................................................................................................632
11.5.1
11.5.2
11.5.3
Voltage and Frequency Scaling.................................................................................................................632
11.5.1.1
Asynchronous Interface Logic...............................................................................................632
11.5.1.2
Level Shifting between SoC-logic and ARM-logic...............................................................633
Power Gating in the ARM platform...........................................................................................................633
11.5.2.1
Isolation Circuitry at the ARM platform Interface................................................................633
11.5.2.2
Power Gating the Memory Peripheries..................................................................................633
11.5.2.3
Retaining the State of the ARM platform Registers..............................................................633
11.5.2.4
Power Gating the ARM platform High Performance Logic Gates........................................634
11.5.2.5
Power Gating the L2 Bit Arrays............................................................................................634
11.5.2.6
Controlling Power Gating using the General Power Controller (GPC) ................................634
11.5.2.7
Power Gating the NEON Block.............................................................................................635
Modes of Operation...................................................................................................................................639
Chapter 12
ARM Platform Debug
12.1
Introduction ..................................................................................................................................................................641
12.1.1
Overview....................................................................................................................................................641
12.1.2
ARM Debug Blocks...................................................................................................................................642
12.1.2.1
Processor Debug Unit............................................................................................................643
12.1.2.1.1
Halting Debug-Mode Debugging...................................................................643
12.1.2.1.2
Monitor Debug-Mode Debugging..................................................................643
12.1.2.1.3
Programming the Debug Unit.........................................................................643
12.1.2.2
ARM embedded trace macrocell (ARM ETM).....................................................................644
12.1.2.3
CoreSight Embedded Trace Buffer (CSETB)........................................................................645
12.1.2.4
CoreSight Replicator (CSREPLICATOR).............................................................................646
12.1.2.5
CoreSight trace port interface unit (CSTPIU)........................................................................647
12.1.2.6
CoreSight cross trigger interface (CSCTI).............................................................................647
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12.1.2.7
CoreSight Cross Trigger Matrix (CSCTM)...........................................................................649
12.1.2.8
Debug Access Port (DAP).....................................................................................................650
12.1.2.8.1
12.1.3
12.2
Page
DAP_SYS.......................................................................................................651
Modes of Operation...................................................................................................................................652
12.1.3.1
ARM Invasive Debug Mode..................................................................................................652
12.1.3.2
ARM Non-Invasive Debug Mode (Real-time Trace)............................................................652
12.1.3.3
Normal Operating Modes.......................................................................................................653
12.1.3.4
Low Power Modes.................................................................................................................653
Memory Map and Register Definition..........................................................................................................................653
12.2.1
Register Summary......................................................................................................................................654
12.2.1.1
DAP JTAG DP Registers.......................................................................................................655
12.2.1.2
DAP ROM Register Summary...............................................................................................656
12.2.1.3
Processor Debug Unit Register Summary.............................................................................656
12.2.1.3.1
Coprocessor Registers Summary....................................................................656
12.2.1.3.2
Memory Mapped Registers Summary............................................................657
12.2.1.4
ETB Register Summary.........................................................................................................658
12.2.1.5
ETM Register Summary........................................................................................................660
12.2.1.6
CSCTI Register Summary.....................................................................................................662
12.2.1.7
TPIU Register Summary........................................................................................................664
12.2.2
Clocks.........................................................................................................................................................667
12.2.3
Reset...........................................................................................................................................................667
Chapter 13
Multi-Layer AHB Crossbar Switch (AHBMAX)
13.1
Overview.......................................................................................................................................................................669
13.2
System Connectivity.....................................................................................................................................................671
13.3
Features.........................................................................................................................................................................671
13.3.1
Limitations.................................................................................................................................................672
13.3.2
General Operation......................................................................................................................................672
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Title
Page
AHBMAX Interface Signals.........................................................................................................................................673
13.4.1
AHBMAX Signal Descriptions.................................................................................................................673
13.4.1.1
max_halt_request...................................................................................................................673
13.4.1.2
max_halted.............................................................................................................................674
13.5
Coherency.....................................................................................................................................................................674
13.6
Detailed Functional Description...................................................................................................................................674
13.6.1
Arbitration..................................................................................................................................................674
13.6.1.1
Arbitration During Undefined Length Bursts........................................................................675
13.6.1.2
Fixed Priority Operation........................................................................................................675
13.6.1.3
Round-Robin Priority Operation............................................................................................676
13.6.2
Priority Assignment...................................................................................................................................677
13.6.3
Master Port Functionality...........................................................................................................................677
13.6.4
13.6.3.1
Master Port General Information...........................................................................................677
13.6.3.2
Master Port Decoders.............................................................................................................679
13.6.3.3
Master Port Capture Unit.......................................................................................................679
13.6.3.4
Master Port Registers.............................................................................................................679
13.6.3.5
Master Port State Machine.....................................................................................................679
13.6.3.5.1
Master Port State Machine States...................................................................679
13.6.3.5.2
Master Port State Machine Slave Swapping...................................................680
Slave Port Functionality.............................................................................................................................681
13.6.4.1
Slave Port General Information.............................................................................................681
13.6.4.2
Slave Port Muxes...................................................................................................................682
13.6.4.3
Slave Port Registers...............................................................................................................683
13.6.4.4
Slave Port State Machine.......................................................................................................683
13.6.4.4.1
Slave Port State Machine States.....................................................................683
13.6.4.4.2
Slave Port State Machine Arbitration.............................................................684
13.6.4.4.3
Slave Port State Machine Master Handoff......................................................684
13.6.4.4.4
Slave Port State Machine Parking...................................................................687
13.6.4.4.5
Slave Port State Machine Halt Mode..............................................................690
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13.7
Initialization/Application Information..........................................................................................................................691
13.8
AHBMAX Interface......................................................................................................................................................691
13.8.1
AHBMAX Interface Overview..................................................................................................................691
13.8.2
Master Ports-AHBMAX Interface.............................................................................................................691
13.8.3
13.9
13.8.2.1
Terminated Accesses..............................................................................................................691
13.8.2.2
Taken Accesses......................................................................................................................691
13.8.2.3
Stalled Accesses.....................................................................................................................692
13.8.2.4
Error Response Terminated Accesses....................................................................................692
Slave Ports-AHBMAX Interface...............................................................................................................692
Programmable Registers...............................................................................................................................................693
13.9.1
Master Priority Register for Slave port n (AHBMAX_MPRn).................................................................694
13.9.2
General Purpose Control Register for Slave port n (AHBMAX_SGPCRn).............................................696
13.9.3
General Purpose Control Register for Master port n (AHBMAX_MGPCRn)..........................................698
Chapter 14
AHB to IP Bridge (AIPSTZ)
14.1
Introduction...................................................................................................................................................................701
14.1.1
14.2
14.3
Features......................................................................................................................................................701
General Operation.........................................................................................................................................................701
14.2.1
AIPSTZ Registers......................................................................................................................................702
14.2.2
Overview....................................................................................................................................................702
14.2.3
Control Registers........................................................................................................................................703
Register Descriptions....................................................................................................................................................704
14.3.1
Master Privilege Registers.........................................................................................................................704
14.3.2
Off-Platform Peripheral Access Control Registers (AIPSTZ_OPACRs)..................................................705
14.4
Functional Description..................................................................................................................................................708
14.5
Access Protections........................................................................................................................................................709
14.6
Access Support..............................................................................................................................................................709
14.7
Initialization Information..............................................................................................................................................709
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Chapter 15
Asynchronous Sample Rate Converter (ASRC)
15.1
Introduction ..................................................................................................................................................................711
15.1.1
Overview....................................................................................................................................................713
15.1.2
Features......................................................................................................................................................714
15.1.3
Modes of Operation...................................................................................................................................714
15.1.3.1
15.1.3.2
Data Transfer Schemes..........................................................................................................715
15.1.3.1.1
Data Input Modes............................................................................................715
15.1.3.1.2
Data Output Modes.........................................................................................716
Word Alignment Supported...................................................................................................717
15.1.3.2.1
Input Data Alignment Modes..........................................................................717
15.1.3.2.2
Output Data Alignment Modes.......................................................................717
15.2
Interrupts.......................................................................................................................................................................718
15.3
DMA requests...............................................................................................................................................................719
15.4
Functional Description..................................................................................................................................................719
15.4.1
Algorithm Description...............................................................................................................................719
15.4.1.1
Signal Processing Flow..........................................................................................................719
15.4.1.2
Operation of the Filter............................................................................................................722
15.4.1.2.1
Support of Physical Clocks.............................................................................722
15.5
Startup Procedure..........................................................................................................................................................724
15.6
Programmable Registers...............................................................................................................................................728
15.6.1
ASRC Control Register (ASRC_ASRCTR)..............................................................................................731
15.6.2
ASRC Interrupt Enable Register (ASRC_ASRIER).................................................................................733
15.6.3
ASRC Channel Number Configuration Register (ASRC_ASRCNCR)....................................................734
15.6.4
ASRC Filter Configuration Status Register (ASRC_ASRCFG)...............................................................736
15.6.5
ASRC Clock Source Register (ASRC_ASRCSR).....................................................................................738
15.6.6
ASRC Clock Divider Register 1 (ASRC_ASRCDR1)..............................................................................742
15.6.7
ASRC Clock Divider Register 2 (ASRC_ASRCDR2)..............................................................................743
15.6.8
ASRC Status Register (ASRC_ASRSTR).................................................................................................744
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15.6.9
ASRC Parameter Register n (ASRC_ASRPMnn).....................................................................................747
15.6.10
ASRC ASRC Task Queue FIFO Register 1 (ASRC_ASRTFR1).............................................................748
15.6.11
ASRC Channel Counter Register (ASRC_ASRCCR)...............................................................................749
15.6.12
ASRC Data Input Register for Pair x (ASRC_ASRDIn)...........................................................................750
15.6.13
ASRC Data Output Register for Pair x (ASRC_ASRDOn).......................................................................750
15.6.14
ASRC Ideal Ratio for Pair A-High Part (ASRC_ASRIDRHA)................................................................751
15.6.15
ASRC Ideal Ratio for Pair A -Low Part (ASRC_ASRIDRLA)................................................................751
15.6.16
ASRC Ideal Ratio for Pair B-High Part (ASRC_ASRIDRHB).................................................................752
15.6.17
ASRC Ideal Ratio for Pair B-Low Part (ASRC_ASRIDRLB)..................................................................752
15.6.18
ASRC Ideal Ratio for Pair C-High Part (ASRC_ASRIDRHC).................................................................753
15.6.19
ASRC Ideal Ratio for Pair C-Low Part (ASRC_ASRIDRLC)..................................................................753
15.6.20
ASRC 76kHz Period in terms of ASRC processing clock (ASRC_ASR76K)..........................................754
15.6.21
ASRC 56kHz Period in terms of ASRC processing clock (ASRC_ASR56K)..........................................755
15.6.22
ASRC Misc Control Register for Pair A (ASRC_ASRMCRA)................................................................756
15.6.23
ASRC FIFO Status Register for Pair A (ASRC_ASRFSTA)....................................................................758
15.6.24
ASRC Misc Control Register for Pair B (ASRC_ASRMCRB)................................................................759
15.6.25
ASRC FIFO Status Register for Pair B (ASRC_ASRFSTB)....................................................................761
15.6.26
ASRC Misc Control Register for Pair C (ASRC_ASRMCRC)................................................................762
15.6.27
ASRC FIFO Status Register for Pair C (ASRC_ASRFSTC)....................................................................764
15.6.28
ASRC Misc Control Register 1 for Pair X (ASRC_ASRMCR1n)............................................................765
Chapter 16
Digital Audio Multiplexer (AUDMUX)
16.1
Overview.......................................................................................................................................................................767
16.1.1
Features......................................................................................................................................................769
16.1.2
Modes and Operations...............................................................................................................................769
16.2
External Signal Description..........................................................................................................................................769
16.3
Default Register Configuration.....................................................................................................................................770
16.3.1
Default Port Configuration.........................................................................................................................770
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Page
Functional Description..................................................................................................................................................770
16.4.1
Operating Modes........................................................................................................................................770
16.4.1.1
16.4.2
16.4.3
16.5
Title
Port Receive Data Modes.......................................................................................................771
16.4.1.1.1
Normal Mode..................................................................................................773
16.4.1.1.2
Internal Network Mode...................................................................................774
16.4.1.1.3
Transmit Data Output Enable Assertion.........................................................786
16.4.1.2
Tx/Rx Switch and External Network Mode...........................................................................786
16.4.1.3
Timing Modes........................................................................................................................787
16.4.1.3.1
Synchronous Mode (4-Wire Interface)...........................................................787
16.4.1.3.2
Asynchronous Mode (6-Wire Interface).........................................................789
Connectivity Between Ports.......................................................................................................................792
16.4.2.1
Internal Port to External Port Connectivity............................................................................793
16.4.2.2
External Port to External Port Connectivity..........................................................................794
16.4.2.3
Internal Port to Internal Port Connectivity.............................................................................794
16.4.2.4
Loopback Connectivity..........................................................................................................795
AUDMUX Clocking..................................................................................................................................795
16.4.3.1
AUDMUX Clock Inputs........................................................................................................795
16.4.3.2
AUDMUX Clock Diagram....................................................................................................795
16.4.3.3
Clocking Restrictions.............................................................................................................796
Programmable Registers...............................................................................................................................................796
16.5.1
Port Timing Control Register 1 (AUDMUX_PTCR1)..............................................................................797
16.5.2
Port Timing Control Register 2 (AUDMUX_PTCR2)..............................................................................799
16.5.3
Port Timing Control Register 3 (AUDMUX_PTCR3)..............................................................................801
16.5.4
Port Timing Control Register n (AUDMUX_PTCRn)..............................................................................803
Chapter 17
Clock Amplifier (CAMP)
17.1
Introduction...................................................................................................................................................................807
17.1.1
Overview....................................................................................................................................................808
17.1.2
Features......................................................................................................................................................808
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17.2
Title
Page
Modes of Operation...................................................................................................................................808
17.1.3.1
Normal Mode.........................................................................................................................808
17.1.3.2
Power Down Mode................................................................................................................808
17.1.3.3
Test Mode (Fault Bypass or Scan).........................................................................................808
External Signal Description..........................................................................................................................................808
17.2.1
Signals Overview.......................................................................................................................................809
17.2.2
Detailed Signal Description.......................................................................................................................809
17.2.2.1
CKIH - External Clock Input.................................................................................................809
17.2.2.2
VDD - Power supply..............................................................................................................809
17.2.2.3
VSS - Ground.........................................................................................................................809
17.2.2.4
IPT_SCAN_MODE - Scan Signal.........................................................................................809
17.2.2.5
PWD - Power Down Signal...................................................................................................810
17.2.2.6
FAULT_BYP - Control Signal for Test Mode......................................................................810
17.2.2.7
CAMP_OUT - Clock Output from CAMP............................................................................810
17.3
Memory Map/Register Definition.................................................................................................................................810
17.4
Functional Description..................................................................................................................................................810
17.4.1
17.4.2
17.5
CAMP Sub-Blocks.....................................................................................................................................810
17.4.1.1
Main Clock Amplifier............................................................................................................811
17.4.1.2
Output Buffer.........................................................................................................................811
17.4.1.3
Level Shifter...........................................................................................................................811
CAMP Modes of Operation.......................................................................................................................811
17.4.2.1
Normal Mode.........................................................................................................................811
17.4.2.2
Power Down Mode................................................................................................................811
17.4.2.3
Test Mode..............................................................................................................................812
Initialization/Application Information..........................................................................................................................812
Chapter 18
Clock Control Module (CCM)
18.1
Overview.......................................................................................................................................................................813
18.1.1
Features......................................................................................................................................................813
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18.2
Title
Page
CCM Block Diagram.................................................................................................................................814
Functional Description..................................................................................................................................................816
18.2.1
Clock Generation.......................................................................................................................................816
18.2.1.1
External Low Frequency Clock - CKIL.................................................................................816
18.2.1.2
External High Frequency Clock - CKIH and internal oscillator............................................817
18.2.1.3
DPLL reference clock............................................................................................................817
18.2.1.4
CCM Internal Clock Generation............................................................................................817
18.2.1.4.1
DPLL Bypass Procedure.................................................................................820
18.2.1.4.2
Step Logic.......................................................................................................820
18.2.1.4.3
DPLLC Reference Clock Connectivity..........................................................820
18.2.1.4.4
DPLL Clock Change.......................................................................................820
18.2.1.4.5
CCM_CLK_IGNITION..................................................................................821
18.2.1.4.6
Reset Values for DPLLC................................................................................822
18.2.1.4.7
CCM_CLK_ROOT_GEN...............................................................................822
18.2.1.4.8
Initial Values Controlled by SJC....................................................................829
18.2.1.4.9
Divider Change Handshake............................................................................830
18.2.1.4.10
CKIL Synchronizing to ipg_clk......................................................................833
18.2.1.4.11
Special Considerations for Configuring PERCLK.........................................833
18.2.1.5
DPLL's Disabling / Enabling.................................................................................................834
18.2.1.6
Low Power Clock Gating Module (LPCG)...........................................................................834
18.2.2
Creation of Sync Signal for IEEE_RTC Module.......................................................................................836
18.2.3
System clocks connectivity........................................................................................................................836
18.2.4
....................................................................................................................................................................843
18.2.5
DVFS Support............................................................................................................................................844
18.2.5.1
ARM Clock Domain Frequency Shift:..................................................................................844
18.2.5.2
Peripheral Clock Domain Frequency Shift:...........................................................................846
18.2.5.3
Peripherals Restrictions in DVFS Scenario...........................................................................851
18.2.5.4
CCM Handshake with the ESDCTL......................................................................................852
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Section Number
18.2.6
Page
Power Modes..............................................................................................................................................852
18.2.6.1
Run Mode...............................................................................................................................852
18.2.6.2
Wait Mode..............................................................................................................................853
18.2.6.3
18.2.6.2.1
Wait Mode is Entered by the Following Procedure:.......................................853
18.2.6.2.2
Wait mode is Exited by the Following Procedure..........................................854
Stop Mode..............................................................................................................................855
18.2.6.3.1
Stop Mode is Entered by the Following Procedure:.......................................855
18.2.6.3.2
Stop Mode is Exited by the Following Procedure:.........................................857
18.2.6.3.3
PMIC Signal Description:...............................................................................859
18.2.6.4
LPMD Request from SRC (Reset Controller).......................................................................860
18.2.6.5
Low Power Audio Playback Mode (LP-APM)......................................................................861
18.2.6.6
18.3
Title
18.2.6.5.1
Low Power APM Mode Definition.................................................................861
18.2.6.5.2
LP-APM Mode Restrictions...........................................................................861
Recommendations for using low power consumption from CCM........................................864
Programmable Registers...............................................................................................................................................864
18.3.1
CCM Control Register (CCM_CCR).........................................................................................................866
18.3.2
CCM Control Divider Register (CCM_CCDR).........................................................................................868
18.3.3
CCM Status REgister (CCM_CSR)...........................................................................................................869
18.3.4
CCM Clock Swither Register (CCM_CCSR)............................................................................................870
18.3.5
CCM Arm Clock Root Register (CCM_CACRR).....................................................................................872
18.3.6
CCM Bus Clock Divider Register (CCM_CBCDR).................................................................................873
18.3.7
CCM Bus Clock Multiplexer Register (CCM_CBCMR)..........................................................................876
18.3.8
CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)..................................................................878
18.3.9
CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)..................................................................881
18.3.10
CCM Serial Clock Divider Register 1 (CCM_CSCDR1)..........................................................................884
18.3.11
CCM SSI1 Clock Divider Register (CCM_CS1CDR)..............................................................................887
18.3.12
CCM SSI2 Clock Divider Register (CCM_CS2CDR)..............................................................................888
18.3.13
CCM D1 Clock Divider Register (CCM_CDCDR)..................................................................................890
18.3.14
CCM HSC Clock Divider Register (CCM_CHSCCDR)...........................................................................892
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18.3.15
CCM Serial Clock Divider Register 2 (CCM_CSCDR2)..........................................................................893
18.3.16
CCM Serial Clock Divider Register 3 (CCM_CSCDR3)..........................................................................895
18.3.17
CCM Serial Clock Divider Register 4 (CCM_CSCDR4)..........................................................................895
18.3.18
CCM Divider Handshake In-Process Register (CCM_CDHIPR).............................................................897
18.3.19
CCM DVFS Control Register (CCM_CDCR)...........................................................................................899
18.3.20
CCM Low Power Control Register (CCM_CLPCR)................................................................................901
18.3.21
CCM Interrupt Status Register (CCM_CISR)...........................................................................................905
18.3.22
CCM Interrupt Mask Register (CCM_CIMR)...........................................................................................907
18.3.23
CCM Clock Output Source Register (CCM_CCOSR)..............................................................................909
18.3.24
CCM General Purpose Register (CCM_CGPR)........................................................................................912
18.3.25
CCM Clock Gating Register 0 (CCM_CCGR0)........................................................................................913
18.3.26
CCM Clock Gating Register 1 (CCM_CCGR1)........................................................................................914
18.3.27
CCM Clock Gating Register 2 (CCM_CCGR2)........................................................................................915
18.3.28
CCM Clock Gating Register 3 (CCM_CCGR3)........................................................................................916
18.3.29
CCM Clock Gating Register 4 (CCM_CCGR4)........................................................................................917
18.3.30
CCM Clock Gating Register 5 (CCM_CCGR5)........................................................................................919
18.3.31
CCM Clock Gating Register 6 (CCM_CCGR6)........................................................................................920
18.3.32
CCM Clock Gating Register 7 (CCM_CCGR7)........................................................................................921
18.3.33
CCM Module Enable Overide Register (CCM_CMEOR)........................................................................923
Chapter 19
Configurable Serial Peripheral Interface (CSPI)
19.1
Overview.......................................................................................................................................................................927
19.1.1
Features......................................................................................................................................................928
19.1.2
Modes and Operations...............................................................................................................................928
19.2
External Signals............................................................................................................................................................929
19.3
Functional Description..................................................................................................................................................930
19.3.1
Operating Modes........................................................................................................................................931
19.3.1.1
Master Mode..........................................................................................................................931
19.3.1.2
Slave Mode............................................................................................................................932
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Section Number
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19.3.2
Low Power Modes.....................................................................................................................................932
19.3.3
Operations..................................................................................................................................................932
19.3.3.1
19.3.3.2
Typical Master Mode.............................................................................................................932
19.3.3.1.1
Master Mode with SPI_RDY..........................................................................933
19.3.3.1.2
Master Mode with Wait States........................................................................935
19.3.3.1.3
Master Mode with SSCTL Control.................................................................935
19.3.3.1.4
Master Mode with Phase Control...................................................................937
Typical Slave Mode...............................................................................................................937
19.3.4
Clocks.........................................................................................................................................................938
19.3.5
Reset...........................................................................................................................................................939
19.3.6
Interrupts....................................................................................................................................................939
19.3.7
DMA .........................................................................................................................................................940
19.3.8
Byte Order..................................................................................................................................................941
19.4
Initialization..................................................................................................................................................................941
19.5
Applications..................................................................................................................................................................942
19.6
Programmable Registers...............................................................................................................................................944
19.6.1
Receive Data Register (CSPI_RXDATA).................................................................................................944
19.6.2
Transmit Data Register (CSPI_TXDATA)................................................................................................945
19.6.3
Control Register (CSPI_CONREG)...........................................................................................................946
19.6.4
Interrupt Control Register (CSPI_CSPI_INTREG)...................................................................................949
19.6.5
DMA Control Register (CSPI_CSPI_DMAREG).....................................................................................950
19.6.6
Status Register (CSPI_CSPI_STATREG).................................................................................................951
19.6.7
Sample Period Control Register (CSPI_PERIODREG)............................................................................952
19.6.8
Test Control Register (CSPI_TESTREG)..................................................................................................953
Chapter 20
Central Security Unit (CSU)
20.1
Overview.......................................................................................................................................................................955
20.2
Features.........................................................................................................................................................................955
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Title
Page
Functional Description..................................................................................................................................................956
20.3.1
Peripheral Access Policy............................................................................................................................956
Chapter 21
DPLL Controller (DPLLC)
21.1
21.2
Overview.......................................................................................................................................................................959
21.1.1
Feature Description....................................................................................................................................960
21.1.2
Modes and Operation.................................................................................................................................960
Functional Description..................................................................................................................................................960
21.2.1
21.2.2
21.3
Operating Modes........................................................................................................................................961
21.2.1.1
Normal Mode.........................................................................................................................961
21.2.1.2
DPLL Desense Mode.............................................................................................................961
21.2.1.3
DVFS Support: HFS Mode....................................................................................................963
Operations..................................................................................................................................................963
21.2.2.1
DPLLC_DP_CTL, DPLLC_DP_OP, DPLLC_DP_MFD Register Update..........................963
21.2.2.2
DP_MFN Register Update.....................................................................................................964
21.2.2.3
Multiple Options for DPLL Control......................................................................................965
21.2.2.4
Calculating the Output Frequency.........................................................................................966
Programmable Registers...............................................................................................................................................966
21.3.1
DPLLC Memory Map/Register Definition................................................................................................966
21.31.1
DPLLC Control Register (DPLLCx_CTL)............................................................................969
21.31.2
DPLLC Configuration Register (DPLLCx_CONFIG)..........................................................972
21.31.3
DPLLC Operation Register (DPLLCx_OP)..........................................................................973
21.31.4
DPLLC Multiplication Factor Denominator Register (DPLLCx_MFD)...............................974
21.31.5
DPLLC Multiplication Factor Numerator Register (DPLLCx_MFN)..................................975
21.31.6
DPLLC Multiplication Factor Numerator PLUS/MINUS Registers (DPLLCx_MFNn)......976
21.31.7
DPLLC High Frequency Support, Operation Register (DPLLCx_HFS_OP)........................977
21.31.8
DPLLC High Frequency Support Multiplication Factor Denominator Register
(DPLLCx_HFS_MFD)...........................................................................................................978
21.31.9
DPLLC High Frequency Support Multiplication Factor Numerator Register
(DPLLCx_HFS_MFN)...........................................................................................................978
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21.31.10
Page
DPLLC Multiplication Factor Numerator Toggle Control Register
(DPLLCx_MFN_TOGC).......................................................................................................979
21.31.11
DPLLC Desense Status Register (DPLLCx_DESTAT)........................................................981
Chapter 22
Dynamic Voltage and Frequency Scaling Core (DVFSC)
22.1
Introduction ..................................................................................................................................................................983
22.1.1
Overview....................................................................................................................................................983
22.1.2
Features......................................................................................................................................................984
22.2
Functional Description of DVFS Load Tracking..........................................................................................................985
22.3
Component Blocks Description....................................................................................................................................985
22.4
22.3.1
dvfs_stdb_smpl Block................................................................................................................................985
22.3.2
dvfs_sig_wt Block......................................................................................................................................985
22.3.3
dvfs_pre_avg Block...................................................................................................................................986
22.3.4
dvfs_ld_add Block.....................................................................................................................................989
22.3.5
dvfs_ema_avg Block..................................................................................................................................989
22.3.6
dvfs_thres_cmp Block................................................................................................................................993
22.3.7
dvfs_thresh_count Block............................................................................................................................994
22.3.8
Load Tracking Buffer Register..................................................................................................................995
22.3.9
Frequency Pattern Generator.....................................................................................................................996
DVFS Output Event/interrupt Configuration................................................................................................................997
22.4.1
Interrupts....................................................................................................................................................997
22.5
Initialization Information..............................................................................................................................................997
22.6
Programmable Registers...............................................................................................................................................998
22.6.1
DVFSC Thresholds (DVFSC_THRS).......................................................................................................999
22.6.2
DVFSC Counters thresholds (DVFSC_COUN)........................................................................................999
22.6.3
DVFSC general purpose bits weight (DVFSC_SIG1)...............................................................................1000
22.6.4
DVFSC general purpose bits weight (DVFSC_SIG0)...............................................................................1001
22.6.5
DVFSC general purpose bit 0 weight counter (DVFSC_GPC0)...............................................................1002
22.6.6
DVFSC general purpose bit 1 weight counter (DVFSC_GPC1)...............................................................1003
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22.6.7
DVFSC general purpose bits enables (DVFSC_GPBT)............................................................................1004
22.6.8
DVFSC EMAC settings (DVFSC_EMAC)...............................................................................................1005
22.6.9
DVFSC Control (DVFSC_CNTR)............................................................................................................1005
22.6.10
DVFSC Load Tracking Register 0, portion 0 (DVFSC_LTR0_0)............................................................1008
22.6.11
DVFSC Load Tracking Register 0, portion 1 (DVFSC_LTR0_1)............................................................1009
22.6.12
DVFSC Load Tracking Register 1, portion 0 (DVFSC_LTR1_0)............................................................1010
22.6.13
DVFS Load Tracking Register 3, portion 1 (DVFSC_LTR1_1)...............................................................1011
22.6.14
DVFSC pattern 0 length (DVFSC_PT0)...................................................................................................1011
22.6.15
DVFSC pattern 1 length (DVFSC_PT1)...................................................................................................1012
22.6.16
DVFSC pattern 2 length (DVFSC_PT2)...................................................................................................1013
22.6.17
DVFSC pattern 3 length (DVFSC_PT3)...................................................................................................1013
Chapter 23
Dynamic Voltage and Frequency Scaling for Peripherals (DVFSP)
23.1
Introduction ..................................................................................................................................................................1015
23.1.1
Overview....................................................................................................................................................1015
23.1.2
Features......................................................................................................................................................1017
23.2
Functional Description of DVFSP Core Load Tracking...............................................................................................1018
23.3
Component Blocks Description ...................................................................................................................................1018
23.4
23.3.1
dvfs_stdb_smpl Block................................................................................................................................1018
23.3.2
dvfs_sig_wt Block......................................................................................................................................1019
23.3.3
dvfs_pre_avg Block...................................................................................................................................1019
23.3.4
dvfs_ld_add Block.....................................................................................................................................1020
23.3.5
dvfs_ema_avg Block..................................................................................................................................1021
23.3.6
dvfs_thres_cmp Block................................................................................................................................1025
23.3.7
dvfs_thresh_count Block............................................................................................................................1026
23.3.8
Load Tracking Buffer Register..................................................................................................................1026
DVFSP Output Event/Interrupt Configuration.............................................................................................................1027
23.4.1
Interrupts....................................................................................................................................................1027
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23.5
Title
Page
Programmable Registers...............................................................................................................................................1027
23.5.1
DVFSP Load Tracking Register 0 (DVFSP_LTR0)..................................................................................1028
23.5.2
DVFSP Load Tracking Register 1 (DVFSP_LTR1)..................................................................................1030
23.5.3
DVFSP Load Tracking Register 2 (DVFSP_LTR2)..................................................................................1031
23.5.4
DVFSP Load Tracking Register 3 (DVFSP_LTR3)..................................................................................1032
23.5.5
LTBR0 (DVFSP_LTBR0).........................................................................................................................1032
23.5.6
LTBR1 (DVFSP_LTBR1).........................................................................................................................1033
23.5.7
PMCR0 (DVFSP_PMCR0).......................................................................................................................1034
23.5.8
PMCR1 (DVFSP_PMCR1).......................................................................................................................1036
Chapter 24
Enhanced Configurable SPI (ECSPI)
24.1
Overview.......................................................................................................................................................................1037
24.1.1
Features......................................................................................................................................................1038
24.1.2
Modes and Operations...............................................................................................................................1038
24.2
External Signals............................................................................................................................................................1039
24.3
Functional Description..................................................................................................................................................1040
24.3.1
Master Mode..............................................................................................................................................1041
24.3.2
Slave Mode................................................................................................................................................1041
24.3.3
Hardware Trigger (HT) Mode....................................................................................................................1042
24.3.4
Low Power Modes.....................................................................................................................................1042
24.3.5
Operations..................................................................................................................................................1042
24.3.5.1
24.3.5.2
Typical Master Mode.............................................................................................................1042
24.3.5.1.1
Master Mode with SPI_RDY..........................................................................1043
24.3.5.1.2
Master Mode with Wait States........................................................................1045
24.3.5.1.3
Master Mode with SS_CTL[3:0] Control.......................................................1045
24.3.5.1.4
Master Mode with Phase Control...................................................................1046
Typical Slave Mode...............................................................................................................1047
24.3.6
Clocks.........................................................................................................................................................1048
24.3.7
Reset...........................................................................................................................................................1048
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Page
24.3.8
Interrupts....................................................................................................................................................1049
24.3.9
DMA .........................................................................................................................................................1050
24.3.10
Byte Order..................................................................................................................................................1051
24.4
Initialization..................................................................................................................................................................1051
24.5
Applications..................................................................................................................................................................1052
24.6
Programmable Registers...............................................................................................................................................1053
24.6.1
Receive Data Register (ECSPIx_RXDATA).............................................................................................1054
24.6.2
Transmit Data Register (ECSPIx_TXDATA)............................................................................................1055
24.6.3
Control Register (ECSPIx_CONREG)......................................................................................................1056
24.6.4
Config Register (ECSPIx_CONFIGREG).................................................................................................1058
24.6.5
Interrupt Control Register (ECSPIx_INTREG).........................................................................................1060
24.6.6
DMA Control Register (ECSPIx_DMAREG)...........................................................................................1061
24.6.7
Status Register (ECSPIx_STATREG).......................................................................................................1063
24.6.8
Sample Period Control Register (ECSPIx_PERIODREG)........................................................................1064
24.6.9
Test Control Register (ECSPIx_TESTREG).............................................................................................1065
24.6.10
Message Data Register (ECSPIx_MSGDATA).........................................................................................1066
Chapter 25
External Interface Module (EIM)
25.1
Overview.......................................................................................................................................................................1068
25.2
Features.........................................................................................................................................................................1069
25.3
Modes of Operation......................................................................................................................................................1069
25.4
25.3.1
Asynchronous Mode..................................................................................................................................1070
25.3.2
Asynchronous Page Read Mode................................................................................................................1070
25.3.3
Multiplexed Address/Data Mode...............................................................................................................1070
25.3.4
Burst Clock Mode......................................................................................................................................1071
25.3.5
Low Power Modes.....................................................................................................................................1072
25.3.6
Boot Mode..................................................................................................................................................1072
External Signal Description..........................................................................................................................................1072
25.4.1
Signals Overview.......................................................................................................................................1072
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25.4.2
Detailed Signal Descriptions .....................................................................................................................1073
25.4.3
Other Important Block I/O Signals Internal to the SoC.............................................................................1074
25.5
Chip Select Memory Map.............................................................................................................................................1075
25.6
Functional Description..................................................................................................................................................1075
25.6.1
Clocks.........................................................................................................................................................1075
25.6.2
Bus Sizing Configuration...........................................................................................................................1076
25.6.2.1
8 BIT PORT SUPPORT........................................................................................................1076
25.6.2.1.1
MOTOROLA 68000.......................................................................................1076
25.6.2.1.2
INTEL 386......................................................................................................1077
25.6.3
EIM Operational Modes.............................................................................................................................1077
25.6.4
Burst Mode (Synchronous) Memory Operation........................................................................................1077
25.6.5
Burst Clock Divisor (BCD)........................................................................................................................1078
25.6.6
Burst Clock Start (BCS).............................................................................................................................1079
25.6.7
Multiplexed Address/Data Mode Support.................................................................................................1079
25.6.8
Mixed Master/Memory Burst Modes Support...........................................................................................1079
25.6.9
AXI (Master) Bus Cycles Support.............................................................................................................1080
25.6.10
WAIT_B Signal, RWSC and WWSC bit fields Usage..............................................................................1082
25.6.11
IPS Register Interface................................................................................................................................1082
25.6.12
MRS Set for PSRAM.................................................................................................................................1083
25.6.13
EIM Access Termination ..........................................................................................................................1083
25.6.14
Error Conditions.........................................................................................................................................1083
25.6.15
DTACK Mode............................................................................................................................................1084
25.6.16
RDY_INT Signal as Interrupt....................................................................................................................1084
25.6.17
RDY_INT Signal as Ready After Reset Indication...................................................................................1085
25.6.18
EIM_GRANT / EIM_BUSY Handshake Description...............................................................................1085
25.6.19
LPMD / LPACK Handshake Description..................................................................................................1085
25.6.20
Endianness.................................................................................................................................................1086
25.6.21
Strobe Signal Use.......................................................................................................................................1087
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Page
Initialization Information..............................................................................................................................................1087
25.7.1
25.8
Title
Booting from EIM......................................................................................................................................1087
Application Note...........................................................................................................................................................1088
25.8.1
25.8.2
25.8.3
25.8.4
25.8.5
25.8.6
25.8.7
Access to AMD Flash................................................................................................................................1088
25.8.1.1
AMD Flash Asynchronous Mode Configuration...................................................................1088
25.8.1.2
AMD Flash Utility.................................................................................................................1089
Access to Intel Sibley Flash.......................................................................................................................1089
25.8.2.1
Intel Sibley Flash Asynchronous Mode Configuration..........................................................1090
25.8.2.2
Intel Sibley Flash Synchronous Mode Configuration............................................................1090
25.8.2.3
Intel Sibley Flash Utility........................................................................................................1090
Access to MDOC Device...........................................................................................................................1091
25.8.3.1
MDOC Device Boot...............................................................................................................1091
25.8.3.2
MDOC Device Asynchronous Mode Configuration.............................................................1091
25.8.3.3
MDOC Device Utility............................................................................................................1091
Access to Micron PSRAM ........................................................................................................................1091
25.8.4.1
Micron PSRAM Asynchronous Mode Configuration...........................................................1091
25.8.4.2
Micron PSRAM Synchronous Mode Configuration..............................................................1092
Access to Samsung OneNAND ................................................................................................................1092
25.8.5.1
Samsung OneNAND Boot.....................................................................................................1092
25.8.5.2
Samsung OneNAND Asynchronous Mode Configuration....................................................1093
25.8.5.3
Samsung OneNAND Synchronous Mode Configuration......................................................1093
25.8.5.4
Samsung OneNAND Utility..................................................................................................1093
Access to Samsung UtRAM .....................................................................................................................1094
25.8.6.1
Samsung UtRAM Asynchronous Mode Configuration.........................................................1094
25.8.6.2
Samsung UtRAM Synchronous Mode Configuration...........................................................1094
Access to Spansion Flash ..........................................................................................................................1094
25.8.7.1
Spansion Flash Asynchronous Mode Configuration.............................................................1094
25.8.7.2
Spansion Flash Synchronous Mode Configuration................................................................1095
25.8.7.3
Spansion Flash Utility............................................................................................................1095
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Section Number
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25.9
Title
Page
8 bit support...............................................................................................................................................1096
Booting from OneNAND and NOR Flash devices.......................................................................................................1097
25.9.1
Asynchronous Read Memory Accesses Timing Diagram.........................................................................1097
25.9.2
Asynchronous Write Memory Accesses Timing Diagram........................................................................1098
25.9.3
Asynchronous Read/Write Memory Accesses Timing Diagram...............................................................1099
25.9.4
Asynchronous Read/Write Using RAL, WAL and CSREC......................................................................1101
25.9.5
Consecutive Asynchronous Write Memory Accesses Timing Diagram...................................................1102
25.9.6
Consecutive Asynchronous Read Memory Accesses Timing Diagram....................................................1105
25.9.7
Async. Page Mode Access.........................................................................................................................1107
25.9.8
DTACK Mode - AXI Single Access..........................................................................................................1108
25.9.9
DTACK Mode - AXI Single Write Access...............................................................................................1111
25.9.10
DTACK Mode - AXI Burst Access...........................................................................................................1112
25.10 Programmable Registers...............................................................................................................................................1114
25.10.1
EIM Memory Map/Register Definition.....................................................................................................1114
25.101.1
Chip Select n General Configuration Register 1 (EIM_CSnGCR1)......................................1116
25.101.2
Chip Select n General Configuration Register 2 (EIM_CSnGCR2)......................................1120
25.101.3
Chip Select n Read Configuration Register 1 (EIM_CSnRCR1)..........................................1122
25.101.4
Chip Select n Read Configuration Register 2 (EIM_CSnRCR2)..........................................1124
25.101.5
Chip Select n Write Configuration Register 1 (EIM_CSnWCR1)........................................1126
25.101.6
Chip Select n Write Configuration Register 2 (EIM_CSnWCR2)........................................1129
25.101.7
EIM Configuration Register (EIM_WCR)............................................................................1129
25.101.8
EIM IP Access Register (EIM_WIAR).................................................................................1131
25.101.9
Error Address Register (EIM_EAR)......................................................................................1132
Chapter 26
Enhanced Periodic Interrupt Timer (EPIT)
26.1
26.2
Overview.......................................................................................................................................................................1134
26.1.1
Features......................................................................................................................................................1134
26.1.2
Modes and Operations...............................................................................................................................1135
External Signals............................................................................................................................................................1135
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26.3
Operating Modes........................................................................................................................................1135
26.3.1.1
Set-and-Forget Mode.............................................................................................................1135
26.3.1.2
Free-Running Mode...............................................................................................................1136
26.3.2
Operations..................................................................................................................................................1136
26.3.3
Clocks.........................................................................................................................................................1137
26.3.4
Compare Event...........................................................................................................................................1138
26.3.4.1
Counter Value Overwrite.......................................................................................................1138
26.3.4.2
Low-Power Mode Behavior...................................................................................................1139
26.3.4.3
Debug Mode Behavior...........................................................................................................1139
Initialization/ Application Information.........................................................................................................................1139
26.4.1
26.5
Page
Functional Description..................................................................................................................................................1135
26.3.1
26.4
Title
Change of Clock Source............................................................................................................................1139
Programmable Registers...............................................................................................................................................1140
26.5.1
Control register (EPITx_EPITCR).............................................................................................................1141
26.5.2
Status register (EPITx_EPITSR)................................................................................................................1143
26.5.3
Load register (EPITx_EPITLR).................................................................................................................1144
26.5.4
Compare register (EPITx_EPITCMPR).....................................................................................................1144
26.5.5
Counter register (EPITx_EPITCNR).........................................................................................................1145
Chapter 27
Enhanced Serial Audio Interface (ESAI)
27.1
Introduction ..................................................................................................................................................................1147
27.1.1
Overview....................................................................................................................................................1147
27.1.2
Features......................................................................................................................................................1149
27.1.3
Modes of Operation...................................................................................................................................1149
27.1.3.1
Normal/Network/On-Demand Mode Selection.....................................................................1149
27.1.3.2
Synchronous/Asynchronous Operating Modes......................................................................1150
27.1.3.3
Frame Sync Selection.............................................................................................................1150
27.1.3.4
Shift Direction Selection........................................................................................................1151
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Section Number
27.2
27.3
27.4
27.5
Title
Page
External Signal Description..........................................................................................................................................1152
27.2.1
Serial Transmit 0 Data Pin (SDO0)...........................................................................................................1152
27.2.2
Serial Transmit 1 Data Pin (SDO1)...........................................................................................................1152
27.2.3
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3).................................................................................1152
27.2.4
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2).................................................................................1153
27.2.5
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1).................................................................................1153
27.2.6
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0).................................................................................1154
27.2.7
Receiver Serial Clock (SCKR)..................................................................................................................1154
27.2.8
Transmitter Serial Clock (SCKT)..............................................................................................................1156
27.2.9
Frame Sync for Receiver (FSR).................................................................................................................1157
27.2.10
Frame Sync for Transmitter (FST).............................................................................................................1158
27.2.11
High Frequency Clock for Transmitter (HCKT).......................................................................................1158
27.2.12
High Frequency Clock for Receiver (HCKR)............................................................................................1158
27.2.13
Serial I/O Flags..........................................................................................................................................1159
Functional Description..................................................................................................................................................1160
27.3.1
ESAI After Reset.......................................................................................................................................1160
27.3.2
ESAI Interrupt Requests............................................................................................................................1160
27.3.3
ESAI DMA Requests from the FIFOs.......................................................................................................1162
27.3.4
ESAI Transmit and Receive Shift Registers..............................................................................................1162
27.3.4.1
ESAI Transmit Shift Registers...............................................................................................1162
27.3.4.2
ESAI Receive Shift Registers................................................................................................1165
Initialization Information..............................................................................................................................................1165
27.4.1
ESAI Initialization.....................................................................................................................................1165
27.4.2
ESAI Initialization Examples.....................................................................................................................1166
27.4.2.1
Initializing the ESAI using Personal Reset............................................................................1166
27.4.2.2
Initializing the ESAI Transmitter Section..............................................................................1167
27.4.2.3
Initializing the ESAI Receiver Section..................................................................................1167
Programmable Registers...............................................................................................................................................1168
27.5.1
ESAI Transmit Data Register (ESAI_ETDR)...........................................................................................1170
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Page
27.5.2
ESAI Receive Data Register (ESAI_ERDR).............................................................................................1170
27.5.3
ESAI Control Register (ESAI_ECR).........................................................................................................1171
27.5.4
ESAI Status Register (ESAI_ESR)............................................................................................................1172
27.5.5
Transmit FIFO Configuration Register (ESAI_TFCR).............................................................................1173
27.5.6
Transmit FIFO Status Register (ESAI_TFSR)..........................................................................................1175
27.5.7
Receive FIFO Configuration Register (ESAI_RFCR)...............................................................................1176
27.5.8
Receive FIFO Status Register (ESAI_RFSR)............................................................................................1177
27.5.9
Transmit Data Register n (ESAI_TXn).....................................................................................................1178
27.5.10
ESAI Transmit Slot Register (ESAI_TSR)................................................................................................1179
27.5.11
Receive Data Register n (ESAI_RXn).......................................................................................................1180
27.5.12
Serial Audio Interface Status Register (ESAI_SAISR).............................................................................1181
27.5.13
Serial Audio Interface Control Register (ESAI_SAICR)..........................................................................1183
27.5.14
Transmit Control Register (ESAI_TCR)...................................................................................................1186
27.5.15
Transmit Clock Control Register (ESAI_TCCR)......................................................................................1194
27.5.16
Receive Control Register (ESAI_RCR).....................................................................................................1198
27.5.17
Receive Clock Control Register (ESAI_RCCR).......................................................................................1202
27.5.18
Transmit Slot Mask Register A (ESAI_TSMA)........................................................................................1205
27.5.19
Transmit Slot Mask Register B (ESAI_TSMB)........................................................................................1206
27.5.20
Receive Slot Mask Register A (ESAI_RSMA).........................................................................................1207
27.5.21
Receive Slot Mask Register B (ESAI_RSMB)..........................................................................................1208
27.5.22
Port C Direction Register (ESAI_PRRC)..................................................................................................1209
27.5.23
Port C Control Register (ESAI_PCRC).....................................................................................................1209
Chapter 28
Enhanced SDRAM Controller (ESDCTL)
28.1
Introduction...................................................................................................................................................................1211
28.2
Overview.......................................................................................................................................................................1212
28.3
Features.........................................................................................................................................................................1212
28.3.1
ESDCTL Logic Features............................................................................................................................1212
28.3.2
PHY Features.............................................................................................................................................1213
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Title
Page
28.4
AXI Restrictions...........................................................................................................................................................1213
28.5
Functional Description..................................................................................................................................................1213
28.6
28.7
28.5.1
Address Decoding .....................................................................................................................................1214
28.5.2
Address Mirroring .....................................................................................................................................1216
28.5.3
MIF3 - Optimization Strategy....................................................................................................................1217
28.5.4
Auto Refresh Behavior...............................................................................................................................1217
28.5.5
Initialization Information...........................................................................................................................1218
28.5.6
LPMD/DVFS requests...............................................................................................................................1219
28.5.7
Writing to ESDCTL configuration registers..............................................................................................1220
28.5.8
Warm reset.................................................................................................................................................1220
28.5.9
Software reset.............................................................................................................................................1221
28.5.10
Power Saving modes..................................................................................................................................1221
28.5.11
Burst Length options..................................................................................................................................1222
ZQ calibration ..............................................................................................................................................................1222
28.6.1
PHY ZQ SW calibration sequence.............................................................................................................1223
28.6.2
Memory ZQ calibration sequence..............................................................................................................1223
Delay line......................................................................................................................................................................1223
28.7.1
28.8
28.9
Delay line Calibration................................................................................................................................1223
28.7.1.1
Read Delay Line Calibration..................................................................................................1224
28.7.1.2
Write Delay line Calibration..................................................................................................1225
Write leveling................................................................................................................................................................1226
28.8.1
SW write leveling.......................................................................................................................................1226
28.8.2
HW write leveling......................................................................................................................................1226
Write fine tuning...........................................................................................................................................................1227
28.10 Read fine tuning............................................................................................................................................................1227
28.11 DQS Gating...................................................................................................................................................................1228
28.11.1
SW DQS gating training............................................................................................................................1228
28.11.2
HW DQS Gating........................................................................................................................................1228
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Page
28.12 Programmable Registers...............................................................................................................................................1229
28.12.1
ESDCTL Memory Map/Register Definition..............................................................................................1229
28.121.1
ESDCTL Control Register (ESDCTL_ESDCTL).................................................................1233
28.121.2
ESDCTL Power Down Control Register (ESDCTL_ESDPDC)...........................................1234
28.121.3
ESDCTL ODT Timing Control Register (ESDCTL_ESDOTC)...........................................1237
28.121.4
ESDCTL Logic Timing Configuration Register 0 (ESDCTL_ESDCFG0)...........................1239
28.121.5
ESDCTL Timing Configuration Register 1 (ESDCTL_ESDCFG1).....................................1240
28.121.6
ESDCTL Timing Configuration Register 2 (ESDCTL_ESDCFG2).....................................1243
28.121.7
ESDCTL Timing Miscellaneous Register (ESDCTL_ESDMISC).......................................1244
28.121.8
ESDCTL Special Command Register (ESDCTL_ESDSCR)................................................1247
28.121.9
ESDCTL Refresh Control Register (ESDCTL_ESDREF)....................................................1249
28.121.10
ESDCTL Logic Write Command Counter - Debug (ESDCTL_ESDWCC).........................1252
28.121.11
ESDCTL Read Command Counter - Debug (ESDCTL_ESDRCC).....................................1253
28.121.12
ESDCTL Read/Write Command Delay (ESDCTL_ESDRWD)...........................................1253
28.121.13
ESDCTL Out of Reset Delays (ESDCTL_ESDOR).............................................................1255
28.121.14
ESDCTL MRR DATA Register (ESDCTL_ESDMRR).......................................................1257
28.121.15
ESDCTL Timing Configuration Register 3 (ESDCTL_ESDCFG3_LP)..............................1257
28.121.16
ESDCTL MR4 Derating Register (ESDCTL_ESDMR4).....................................................1258
28.121.17
PHY ZQ HW Control Register (ESDCTL_ZQHWCTRL)...................................................1260
28.121.18
PHY ZQ SW Control Register (ESDCTL_ZQSWCTRL)....................................................1262
28.121.19
PHY Write Leveling General Control Register (ESDCTL_WLGCR)..................................1263
28.121.20
PHY Write Leveling Delay Control Register 0 (ESDCTL_WLDECTRL0).........................1265
28.121.21
PHY Write Leveling Delay Control Register 1 (ESDCTL_WLDECTRL1).........................1267
28.121.22
PHY Write Leveling Delay Line Status Register (ESDCTL_WLDLST).............................1268
28.121.23
PHY ODT Control Register (ESDCTL_ODTCTRL)............................................................1269
28.121.24
PHY Read DQ Byte0 Delay Register (ESDCTL_RDDQBY0DL).......................................1271
28.121.25
PHY Read DQ Byte1 Delay Register (ESDCTL_RDDQBY1DL).......................................1274
28.121.26
PHY Read DQ Byte2 Delay Register (ESDCTL_RDDQBY2DL).......................................1277
28.121.27
PHY Read DQ Byte3 Delay Register (ESDCTL_RDDQBY3DL).......................................1279
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Section Number
Title
Page
28.121.28
PHY Write DQ Byte0 Delay Register (ESDCTL_WRDQBY0DL).....................................1282
28.121.29
PHY Write DQ Byte1 Delay Register (ESDCTL_WRDQBY1DL).....................................1284
28.121.30
PHY Write DQ Byte2 Delay Register (ESDCTL_WRDQBY2DL).....................................1285
28.121.31
PHY Write DQ Byte3 Delay Register (ESDCTL_WRDQBY3DL).....................................1287
28.121.32
PHY DQS Gating Control Register0 (ESDCTL_DGCTRL0)..............................................1289
28.121.33
PHY DQS Gating Control Register1 (ESDCTL_DGCTRL1)..............................................1291
28.121.34
PHY DQS Gating Delay Line Status Register (ESDCTL_DGDLST)..................................1292
28.121.35
PHY Read Delay Lines Configuration Register (ESDCTL_RDDLCTL).............................1293
28.121.36
PHY Read Delay Lines Status Register (ESDCTL_RDDLST).............................................1294
28.121.37
PHY Write Delay Lines Configuration Register (ESDCTL_WRDLCTL)...........................1295
28.121.38
PHY Write Delay Lines Status Register (ESDCTL_WRDLST)...........................................1297
28.121.39
PHY SDCLK Control Register (ESDCTL_SDCTRL)..........................................................1298
28.121.40
ZQ LPDDR2 HW Control Register (ESDCTL_ZQLP2CTL)...............................................1298
28.121.41
PHY RD DL HW Calibration Control Register (ESDCTL_RDDLHWCTL).......................1300
28.121.42
PHY WR DL HW Calibration Control Register (ESDCTL_WRDLHWCTL).....................1301
28.121.43
PHY RD DL HW Calibration Status Register 0 (ESDCTL_RDDLHWST0).......................1302
28.121.44
PHY RD DL HW Calibration Status Register 1 (ESDCTL_RDDLHWST1).......................1303
28.121.45
PHY WR DL HW Calibration Status Register 0 (ESDCTL_WRDLHWST0).....................1304
28.121.46
PHY WR DL HW Calibration Status Register 1 (ESDCTL_WRDLHWST1).....................1305
28.121.47
PHY Write Leveling HW Error Register (ESDCTL_WLHWERR).....................................1306
28.121.48
PHY DQS Gating HW Status Register 0 (ESDCTL_DGHWST0).......................................1306
28.121.49
PHY DQS Gating HW Status Register 1 (ESDCTL_DGHWST1).......................................1307
28.121.50
PHY DQS Gating HW Status Register 2 (ESDCTL_DGHWST2).......................................1307
28.121.51
PHY DQS Gating HW Status Register 3 (ESDCTL_DGHWST3).......................................1308
28.121.52
PHY Pre-defined Compare Register 1 (ESDCTL_PDCMPR1)............................................1309
28.121.53
PHY Pre-defined Compare Register 2 (ESDCTL_PDCMPR2)............................................1309
28.121.54
PHY SW Dummy Access Register (ESDCTL_SWDAR).....................................................1311
28.121.55
PHY SW Dummy Read Data Register n (ESDCTL_SWDRDRn)........................................1312
28.121.56
PHY Measure Unit Register (ESDCTL_MUR).....................................................................1313
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28.121.57
Page
Write CA Delay Line controller (ESDCTL_WRCADL)......................................................1314
Chapter 29
Enhanced Secured Digital Host Controller (eSDHCv2)
29.1
Overview ......................................................................................................................................................................1317
29.1.1
Features .....................................................................................................................................................1319
29.1.2
Modes and Operations...............................................................................................................................1320
29.1.2.1
29.2
29.3
Data transfer Modes ..............................................................................................................1320
External Signals............................................................................................................................................................1320
29.2.1
Signals Overview ......................................................................................................................................1321
29.2.2
Ports Table ................................................................................................................................................1321
Functional Description..................................................................................................................................................1322
29.3.1
29.3.2
Data Buffer.................................................................................................................................................1322
29.3.1.1
Write Operation Sequence.....................................................................................................1325
29.3.1.2
Read Operation Sequence......................................................................................................1325
29.3.1.3
Data Buffer and Block Size...................................................................................................1326
29.3.1.4
Dividing Large Data Transfer................................................................................................1327
29.3.1.5
External DMA Request..........................................................................................................1328
DMA AHB Interface..................................................................................................................................1329
29.3.2.1
Internal DMA Request...........................................................................................................1330
29.3.2.2
DMA Burst Length................................................................................................................1330
29.3.2.3
AHB Master Interface............................................................................................................1331
29.3.2.4
ADMA Engine.......................................................................................................................1331
29.3.2.4.1
ADMA Concept and Descriptor Format.........................................................1332
29.3.2.4.2
ADMA Interrupt.............................................................................................1335
29.3.2.4.3
ADMA Error-DMA........................................................................................1335
29.3.3
Register Bank with IP Bus Interface..........................................................................................................1335
29.3.4
SD Protocol Unit........................................................................................................................................1336
29.3.4.1
SD Transceiver.......................................................................................................................1337
29.3.4.2
SD Clock and Monitor...........................................................................................................1337
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Section Number
Page
29.3.4.3
Command Agent....................................................................................................................1337
29.3.4.4
Data Agent.............................................................................................................................1338
29.3.5
Clock and Reset Manager..........................................................................................................................1338
29.3.6
Clock Generator ........................................................................................................................................1339
29.3.7
SDIO Card Interrupt...................................................................................................................................1339
29.3.7.1
Interrupts in 1-bit Mode.........................................................................................................1339
29.3.7.2
Interrupt in 4-bit Mode...........................................................................................................1339
29.3.7.3
Card Interrupt Handling.........................................................................................................1340
29.3.8
Card Insertion and Removal Detection......................................................................................................1341
29.3.9
Power Management and Wake Up Events.................................................................................................1342
29.3.9.1
29.3.10
29.4
Title
Setting Wake Up Events........................................................................................................1343
MMC Fast Boot ........................................................................................................................................1343
29.3.10.1
Boot Operation.......................................................................................................................1343
29.3.10.2
Alternative Boot Operation....................................................................................................1344
Initialization/Application of ESDHC............................................................................................................................1345
29.4.1
Command Send and Response Receive Basic Operation..........................................................................1345
29.4.2
Card Identification Mode...........................................................................................................................1346
29.4.3
29.4.2.1
Card Detect............................................................................................................................1346
29.4.2.2
Reset.......................................................................................................................................1348
29.4.2.3
Voltage Validation.................................................................................................................1349
29.4.2.4
Card Registry.........................................................................................................................1350
Card Access................................................................................................................................................1351
29.4.3.1
29.4.3.2
Block Write............................................................................................................................1352
29.4.3.1.1
Normal Write..................................................................................................1352
29.4.3.1.2
Write with Pause.............................................................................................1353
Block Read.............................................................................................................................1354
29.4.3.2.1
Normal Read...................................................................................................1354
29.4.3.2.2
Read with Pause..............................................................................................1355
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29.4.3.3
Title
Suspend Resume....................................................................................................................1356
29.4.3.3.1
29.4.5
29.4.6
Resume............................................................................................................1357
29.4.3.4
ADMA1 Usage......................................................................................................................1357
29.4.3.5
Transfer Error.........................................................................................................................1358
29.4.3.6
29.4.4
Page
29.4.3.5.1
CRC Error.......................................................................................................1358
29.4.3.5.2
Internal DMA Error........................................................................................1358
29.4.3.5.3
ADMA Error-Card Access.............................................................................1359
29.4.3.5.4
Auto CMD12 Error.........................................................................................1359
Card Interrupt.........................................................................................................................1360
Switch Function.........................................................................................................................................1360
29.4.4.1
Query, Enable and Disable SDIO High Speed Mode............................................................1361
29.4.4.2
Query, Enable and Disable SD High Speed Mode................................................................1361
29.4.4.3
Query, Enable and Disable MMC High Speed Mode............................................................1362
29.4.4.4
Set MMC Bus Width..............................................................................................................1362
ADMA Operation......................................................................................................................................1362
29.4.5.1
ADMA1 Operation................................................................................................................1362
29.4.5.2
ADMA2 Operation................................................................................................................1363
Fast Boot Operation...................................................................................................................................1363
29.4.6.1
Normal fast boot flow ...........................................................................................................1363
29.4.6.2
Alternative fast boot flow .....................................................................................................1364
29.4.6.3
Fast boot application case (in DMA mode) ..........................................................................1365
29.5
Commands for MMC/SD/SDIO ..................................................................................................................................1367
29.6
Software Restrictions....................................................................................................................................................1372
29.6.1
Initialization Active....................................................................................................................................1372
29.6.2
Softeware Polling Procedure......................................................................................................................1373
29.6.3
Suspend Operation.....................................................................................................................................1373
29.6.4
Data Length Setting...................................................................................................................................1373
29.6.5
(A)DMA Address Setting..........................................................................................................................1373
29.6.6
Data Port Access........................................................................................................................................1373
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Section Number
29.7
Title
Page
29.6.7
Change Clock Frequency...........................................................................................................................1374
29.6.8
Multi-block Read.......................................................................................................................................1374
Programmable Registers...............................................................................................................................................1374
29.7.1
DMA System Address (ESDHCV2x_DSADDR)......................................................................................1378
29.7.2
Block Attributes (ESDHCV2x_BLKATTR).............................................................................................1379
29.7.3
Command Argument (ESDHCV2x_CMDARG).......................................................................................1380
29.7.4
Command Transfer Type (ESDHCV2x_XFERTYP)................................................................................1381
29.7.5
Command Response 0 (ESDHCV2x_CMDRSP0)....................................................................................1385
29.7.6
Command Response 1 (ESDHCV2x_CMDRSP1)....................................................................................1386
29.7.7
Command Response 2 (ESDHCV2x_CMDRSP2)....................................................................................1386
29.7.8
Command Response 3 (ESDHCV2x_CMDRSP3)....................................................................................1386
29.7.9
Data Buffer Access Port (ESDHCV2x_DATPORT).................................................................................1388
29.7.10
Present State (ESDHCV2x_PRSSTAT)....................................................................................................1389
29.7.11
Protocol Control (ESDHCV2x_PROCTL)................................................................................................1394
29.7.12
System Control (ESDHCV2x_SYSCTL)..................................................................................................1398
29.7.13
Interrupt Status (ESDHCV2x_IRQSTAT).................................................................................................1401
29.7.14
Interrupt Status Enable (ESDHCV2x_IRQSTATEN)...............................................................................1407
29.7.15
Interrupt Signal Enable (ESDHCV2x_IRQSIGEN)..................................................................................1410
29.7.16
Auto CMD12 Status (ESDHCV2x_AUTOC12ERR)................................................................................1412
29.7.17
Host Controller Capabilities (ESDHCV2x_HOSTCAPBLT)...................................................................1415
29.7.18
Watermark Level (ESDHCV2x_WML)....................................................................................................1417
29.7.19
Force Event (ESDHCV2x_FEVT).............................................................................................................1418
29.7.20
ADMA Error Status Register (ESDHCV2x_ADMAES)...........................................................................1420
29.7.21
ADMA System Address (ESDHCV2x_ADSADDR)................................................................................1422
29.7.22
Vendor Specific Register (ESDHCV2x_VENDOR).................................................................................1423
29.7.23
MMC Boot Register (ESDHCV2x_MMCBOOT).....................................................................................1424
29.7.24
Host Controller Version (ESDHCV2x_HOSTVER).................................................................................1425
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Section Number
Title
Page
Chapter 30
Enhanced Secured Digital Host Controller (eSDHCv3)
30.1
Overview ......................................................................................................................................................................1427
30.1.1
Features .....................................................................................................................................................1429
30.1.2
Modes and Operations...............................................................................................................................1430
30.1.2.1
30.2
30.3
Data transfer Modes ..............................................................................................................1430
External Signals............................................................................................................................................................1431
30.2.1
Signals Overview ......................................................................................................................................1431
30.2.2
Ports Table ................................................................................................................................................1431
Functional Description..................................................................................................................................................1432
30.3.1
30.3.2
Data Buffer.................................................................................................................................................1432
30.3.1.1
Write Operation Sequence.....................................................................................................1435
30.3.1.2
Read Operation Sequence......................................................................................................1436
30.3.1.3
Data Buffer and Block Size...................................................................................................1436
30.3.1.4
Dividing Large Data Transfer................................................................................................1437
30.3.1.5
External DMA Request..........................................................................................................1438
DMA AHB Interface..................................................................................................................................1439
30.3.2.1
Internal DMA Request...........................................................................................................1440
30.3.2.2
DMA Burst Length................................................................................................................1440
30.3.2.3
AHB Master Interface............................................................................................................1441
30.3.2.4
ADMA Engine.......................................................................................................................1441
30.3.2.4.1
ADMA Concept and Descriptor Format.........................................................1442
30.3.2.4.2
ADMA Interrupt.............................................................................................1445
30.3.2.4.3
ADMA Error-DMA........................................................................................1445
30.3.3
Register Bank with IP Bus Interface..........................................................................................................1445
30.3.4
SD Protocol Unit........................................................................................................................................1446
30.3.4.1
SD Transceiver.......................................................................................................................1447
30.3.4.2
SD Clock and Monitor...........................................................................................................1447
30.3.4.3
Command Agent....................................................................................................................1447
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Section Number
30.3.4.4
Page
Data Agent.............................................................................................................................1448
30.3.5
Clock and Reset Manager..........................................................................................................................1448
30.3.6
Clock Generator ........................................................................................................................................1449
30.3.7
SDIO Card Interrupt...................................................................................................................................1449
30.3.7.1
Interrupts in 1-bit Mode.........................................................................................................1449
30.3.7.2
Interrupt in 4-bit Mode...........................................................................................................1449
30.3.7.3
Card Interrupt Handling.........................................................................................................1450
30.3.8
Card Insertion and Removal Detection......................................................................................................1451
30.3.9
Power Management and Wake Up Events.................................................................................................1452
30.3.9.1
30.3.10
30.4
Title
Setting Wake Up Events........................................................................................................1453
MMC Fast Boot ........................................................................................................................................1453
30.3.10.1
Boot Operation.......................................................................................................................1453
30.3.10.2
Alternative Boot Operation....................................................................................................1454
Initialization/Application of ESDHC............................................................................................................................1455
30.4.1
Command Send and Response Receive Basic Operation..........................................................................1455
30.4.2
Card Identification Mode...........................................................................................................................1456
30.4.3
30.4.2.1
Card Detect............................................................................................................................1456
30.4.2.2
Reset.......................................................................................................................................1458
30.4.2.3
Voltage Validation.................................................................................................................1459
30.4.2.4
Card Registry.........................................................................................................................1460
Card Access................................................................................................................................................1461
30.4.3.1
30.4.3.2
Block Write............................................................................................................................1462
30.4.3.1.1
Normal Write..................................................................................................1462
30.4.3.1.2
DDR Write .....................................................................................................1463
30.4.3.1.3
Write with Pause.............................................................................................1463
Block Read.............................................................................................................................1465
30.4.3.2.1
Normal Read...................................................................................................1465
30.4.3.2.2
DDR Read ......................................................................................................1466
30.4.3.2.3
Read with Pause..............................................................................................1466
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Section Number
Title
30.4.3.2.4
30.4.3.3
30.4.6
Resume............................................................................................................1469
30.4.3.4
ADMA1 Usage......................................................................................................................1469
30.4.3.5
Transfer Error.........................................................................................................................1470
30.4.3.6
30.4.5
DLL (Delay Line) in Read Path .....................................................................1467
Suspend Resume....................................................................................................................1468
30.4.3.3.1
30.4.4
Page
30.4.3.5.1
CRC Error.......................................................................................................1470
30.4.3.5.2
Internal DMA Error........................................................................................1470
30.4.3.5.3
ADMA Error-Card Access.............................................................................1471
30.4.3.5.4
Auto CMD12 Error.........................................................................................1471
Card Interrupt.........................................................................................................................1472
Switch Function.........................................................................................................................................1472
30.4.4.1
Query, Enable and Disable SDIO High Speed Mode............................................................1473
30.4.4.2
Query, Enable and Disable SD High Speed Mode................................................................1473
30.4.4.3
Query, Enable and Disable MMC High Speed Mode............................................................1474
30.4.4.4
Set MMC Bus Width..............................................................................................................1474
ADMA Operation......................................................................................................................................1474
30.4.5.1
ADMA1 Operation................................................................................................................1474
30.4.5.2
ADMA2 Operation................................................................................................................1475
Fast Boot Operation...................................................................................................................................1475
30.4.6.1
Normal fast boot flow ...........................................................................................................1475
30.4.6.2
Alternative fast boot flow .....................................................................................................1476
30.4.6.3
Fast boot application case (in DMA mode) ..........................................................................1477
30.5
Commands for MMC/SD/SDIO ..................................................................................................................................1479
30.6
Software Restrictions....................................................................................................................................................1484
30.6.1
Initialization Active....................................................................................................................................1485
30.6.2
Softeware Polling Procedure......................................................................................................................1485
30.6.3
Suspend Operation.....................................................................................................................................1485
30.6.4
Data Length Setting...................................................................................................................................1485
30.6.5
(A)DMA Address Setting..........................................................................................................................1485
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Section Number
30.7
Title
Page
30.6.6
Data Port Access........................................................................................................................................1486
30.6.7
Change Clock Frequency...........................................................................................................................1486
30.6.8
Multi-block Read.......................................................................................................................................1486
Programmable Registers...............................................................................................................................................1487
30.7.1
DMA System Address (ESDHCV3x_DSADDR)......................................................................................1488
30.7.2
Block Attributes (ESDHCV3x_BLKATTR).............................................................................................1489
30.7.3
Command Argument (ESDHCV3x_CMDARG).......................................................................................1490
30.7.4
Command Transfer Type (ESDHCV3x_XFERTYP)................................................................................1491
30.7.5
Command Response n (ESDHCV3x_CMDRSPn)....................................................................................1495
30.7.6
Data Buffer Access Port (ESDHCV3x_DATPORT).................................................................................1497
30.7.7
Present State (ESDHCV3x_PRSSTAT)....................................................................................................1497
30.7.8
Protocol Control (ESDHCV3x_PROCTL)................................................................................................1502
30.7.9
System Control (ESDHCV3x_SYSCTL)..................................................................................................1506
30.7.10
Interrupt Status (ESDHCV3x_IRQSTAT).................................................................................................1510
30.7.11
Interrupt Status Enable (ESDHCV3x_IRQSTATEN)...............................................................................1515
30.7.12
Interrupt Signal Enable (ESDHCV3x_IRQSIGEN)..................................................................................1518
30.7.13
Auto CMD12 Status (ESDHCV3x_AUTOC12ERR)................................................................................1520
30.7.14
Host Controller Capabilities (ESDHCV3x_HOSTCAPBLT)...................................................................1523
30.7.15
Watermark Level (ESDHCV3x_WML)....................................................................................................1525
30.7.16
Force Event (ESDHCV3x_FEVT).............................................................................................................1526
30.7.17
ADMA Error Status Register (ESDHCV3x_ADMAES)...........................................................................1528
30.7.18
ADMA System Address (ESDHCV3x_ADSADDR)................................................................................1530
30.7.19
DLL (Delay Line) Control (ESDHCV3x_DLLCTRL)..............................................................................1531
30.7.20
DLL Status (ESDHCV3x_DLLSTS).........................................................................................................1532
30.7.21
Vendor Specific Register (ESDHCV3x_VENDOR).................................................................................1533
30.7.22
MMC Boot Register (ESDHCV3x_MMCBOOT).....................................................................................1534
30.7.23
Host Controller Version (ESDHCV3x_HOSTVER).................................................................................1535
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Section Number
Title
Page
Chapter 31
External Memory Controller (EXTMC)
31.1
General Introduction ....................................................................................................................................................1537
31.1.1
31.2
AXI Port Gasket.....................................................................................................................1539
31.1.1.2
Dedicated Write Buffers Module...........................................................................................1539
31.1.1.3
Read Shared Buffers Module.................................................................................................1539
31.1.1.4
Fast Arbitration Module.........................................................................................................1540
31.1.1.5
Slow and Intr Arbitration Modules........................................................................................1540
31.1.1.6
Memory Controller Modules.................................................................................................1540
31.1.1.7
IPS Interface unit...................................................................................................................1540
31.1.1.8
Debug Unit.............................................................................................................................1540
Features......................................................................................................................................................1541
31.1.3
Modes of Operation...................................................................................................................................1542
31.1.3.1
Low Power Modes.................................................................................................................1542
31.1.3.2
Debug Mode...........................................................................................................................1542
31.1.3.3
Dynamic Voltage and Frequency Scaling (DVFS) support...................................................1542
31.1.3.4
Power Saving Mode...............................................................................................................1543
Sharing of I/O Pins........................................................................................................................................................1543
EIM and NFC IO pin sharing ....................................................................................................................1544
Memory Map and Register Definition..........................................................................................................................1545
31.3.1
31.4
31.1.1.1
31.1.2
31.2.1
31.3
Overview....................................................................................................................................................1539
IP Bus Memory Map..................................................................................................................................1545
Functional Description..................................................................................................................................................1546
31.4.1
Clocks.........................................................................................................................................................1546
31.4.2
Reset...........................................................................................................................................................1547
31.4.2.1
Cold Reset..............................................................................................................................1547
31.4.2.2
Warm Reset............................................................................................................................1547
31.4.3
Interrupts....................................................................................................................................................1547
31.4.4
Endianness.................................................................................................................................................1548
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Section Number
31.4.5
31.5
Page
IP Bus Interface..........................................................................................................................................1548
Application Information................................................................................................................................................1549
31.5.1
Buffers Size ...............................................................................................................................................1549
31.5.2
Master to Slave Paths - Restrictions..........................................................................................................1549
31.5.3
EXTMC Endianness .................................................................................................................................1549
31.5.4
31.6
Title
31.5.3.1
Introduction to Endianness.....................................................................................................1549
31.5.3.2
AXI Endianness Support........................................................................................................1549
31.5.3.3
AXI master x64......................................................................................................................1549
31.5.3.4
AXI master x32......................................................................................................................1550
31.5.3.5
EXTMC Endianness support.................................................................................................1551
31.5.3.6
M4IF Endianess support........................................................................................................1551
31.5.3.6.1
M4IF behavior for x64 arbitration..................................................................1551
31.5.3.6.2
M4IF behavior for x32 arbitration..................................................................1551
Data Storage Arrangement.........................................................................................................................1553
Programmable Registers...............................................................................................................................................1555
31.6.1
IP Lock register (EXTMC_EXTMC_IPLCK)...........................................................................................1556
31.6.2
Interrupt control and Status register (EXTMC_EXTMC_EICS)..............................................................1557
Chapter 32
Fast Ethernet Controller (FEC)
32.1
Overview.......................................................................................................................................................................1561
32.1.1
32.2
Features......................................................................................................................................................1563
Modes of Operation......................................................................................................................................................1564
32.2.1
Full- and Half-Duplex Operation...............................................................................................................1564
32.2.2
Interface Options........................................................................................................................................1564
32.2.2.1
10-Mbps and 100-Mbps Media Independent Interface (MII)................................................1564
32.2.2.2
10 Mbps and 100 Mbps RMII Interface.................................................................................1565
32.2.2.3
10-Mbps 7-Wire Interface Operation.....................................................................................1565
32.2.3
Address Recognition Options....................................................................................................................1565
32.2.4
Internal Loopback......................................................................................................................................1565
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Title
Functional Description..................................................................................................................................................1566
32.3.1
Network Interface Options.........................................................................................................................1566
32.3.2
FEC Frame Transmission...........................................................................................................................1568
32.3.3
32.3.2.1
Transmit Inter-Packet Gap (IPG) Time.................................................................................1569
32.3.2.2
Collision Handling.................................................................................................................1569
32.3.2.3
Transmission Error Handling.................................................................................................1569
32.3.2.3.1
Transmitter Underrun .....................................................................................1570
32.3.2.3.2
Retransmission Attempts Limit Expired ........................................................1570
32.3.2.3.3
Late Collision .................................................................................................1570
32.3.2.3.4
Heartbeat ........................................................................................................1570
FEC Frame Reception................................................................................................................................1570
32.3.3.1
Receive Inter-Packet Gap (IPG) Time...................................................................................1572
32.3.3.2
Ethernet Address Recognition...............................................................................................1572
32.3.3.2.1
32.3.3.3
32.4
Page
Hash Algorithm...............................................................................................1575
Reception Error Handling......................................................................................................1578
32.3.3.3.1
Overrun ..........................................................................................................1578
32.3.3.3.2
Non-Octet (Dribbling Bits) ............................................................................1578
32.3.3.3.3
CRC ...............................................................................................................1579
32.3.3.3.4
Frame Length Violation..................................................................................1579
32.3.3.3.5
Truncation.......................................................................................................1579
32.3.4
Full-Duplex Flow Control..........................................................................................................................1579
32.3.5
Internal and External Loopback.................................................................................................................1581
Initialization/Application Information..........................................................................................................................1581
32.4.1
Initialization Sequence...............................................................................................................................1581
32.4.1.1
Hardware Controlled Initialization........................................................................................1581
32.4.1.2
User Initialization (Prior to Asserting FEC_ECR[ETHER_EN])..........................................1582
32.4.1.3
Microcontroller Initialization.................................................................................................1583
32.4.1.4
User Initialization (after asserting FEC_ECR[ETHER_EN])...............................................1583
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Title
Buffer Descriptors......................................................................................................................................1584
32.4.2.1
Driver/DMA Operation with Buffer Descriptors...................................................................1584
32.4.2.2
Ethernet Transmit Buffer Descriptor (TxBD)........................................................................1585
32.4.2.2.1
Driver/DMA Operation with Transmit Buffer Descriptors............................1586
32.4.2.2.1.1
32.4.2.3
Transmit Frame in Multiple Buffers.......................................1586
Ethernet Receive Buffer Descriptor (RxBD).........................................................................1587
32.4.2.3.1
32.5
Page
Driver/DMA Operation with Receive Buffer Descriptors..............................1589
Programmable Registers...............................................................................................................................................1590
32.5.1
Top Level Block Memory Map.................................................................................................................1590
32.5.2
Message Information Block (MIB) Counters Memory Map.....................................................................1590
32.5.3
MIIGSK Registers Memory Map..............................................................................................................1593
32.5.4
Ethernet interrupt event register (FEC_EIR).............................................................................................1595
32.5.5
Ethernet interrupt mask register (FEC_EIMR)..........................................................................................1597
32.5.6
Receive descriptor active register (FEC_RDAR)......................................................................................1599
32.5.7
Transmit descriptor active register (FEC_TDAR).....................................................................................1600
32.5.8
Ethernet control register (FEC_ECR)........................................................................................................1601
32.5.9
MII management frame register (FEC_MMFR)........................................................................................1602
32.5.10
MII speed control register (FEC_MSCR)..................................................................................................1604
32.5.11
MIB control register (FEC_MIBC)............................................................................................................1606
32.5.12
Receive control register (FEC_RCR)........................................................................................................1607
32.5.13
Transmit control register (FEC_TCR).......................................................................................................1608
32.5.14
Physical address low register (FEC_PALR)..............................................................................................1609
32.5.15
Physical address upper register (FEC_PAUR)..........................................................................................1610
32.5.16
Opcode and pause duration register (FEC_OPDR)...................................................................................1611
32.5.17
Descriptor individual address upper register (FEC_IAUR).......................................................................1611
32.5.18
Descriptor individual address lower register (FEC_IALR).......................................................................1612
32.5.19
Descriptor group address upper register (FEC_GAUR)............................................................................1612
32.5.20
Descriptor group address lower register (FEC_GALR)............................................................................1613
32.5.21
Transmit FIFO watermark register (FEC_TFWR)....................................................................................1613
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Page
32.5.22
FIFO receive bound register (FEC_FRBR)...............................................................................................1614
32.5.23
FIFO receive FIFO start registers (FEC_FRSR)........................................................................................1614
32.5.24
Receive buffer descriptor ring start register (FEC_ERDSR).....................................................................1615
32.5.25
Transmit buffer descriptor ring start register (FEC_ETDSR)...................................................................1616
32.5.26
Maximum receive buffer size register (FEC_EMRBR)............................................................................1616
Chapter 33
Fast Infrared Interface (FIRI)
33.1
Overview.......................................................................................................................................................................1619
33.1.1
33.2
33.1.1.1
MIR Packet Structure.............................................................................................................1622
33.1.1.2
FIR Packet Structure..............................................................................................................1623
33.1.1.3
MIR CRC...............................................................................................................................1624
33.1.1.4
FIR CRC................................................................................................................................1624
33.1.1.5
MIR Modulation ...................................................................................................................1624
33.1.1.6
FIR Modulation......................................................................................................................1625
33.1.2
Features......................................................................................................................................................1625
33.1.3
Modes of Operation...................................................................................................................................1625
External Signal Description..........................................................................................................................................1626
33.2.1
33.3
Overview of IrDA Medium Infrared and Fast Infrared Standards.............................................................1622
Detailed Signal Descriptions......................................................................................................................1626
33.2.1.1
IPP_DO_TXD........................................................................................................................1626
33.2.1.2
IPP_IND_RXD......................................................................................................................1626
Programmable Registers...............................................................................................................................................1627
33.3.1
FIRI Transmit Control Register (FIRI_TCR)............................................................................................1627
33.3.2
FIRI Transmit Count Register (FIRI_TCTR)............................................................................................1629
33.3.3
FIRI Receive Control Register (FIRI_RCR).............................................................................................1630
33.3.4
FIRI Transmit Status Register (FIRI_TSR)...............................................................................................1632
33.3.5
FIRI Receive Status Register (FIRI_RSR)................................................................................................1633
33.3.6
FIRI Control Register (FIRI_CR)..............................................................................................................1634
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Page
Functional Description..................................................................................................................................................1635
33.4.1
Transmitter Overview................................................................................................................................1635
33.4.1.1
MIR Mode-Transmitter..........................................................................................................1636
33.4.1.2
FIR Mode-Transmitter...........................................................................................................1636
33.4.1.3
Serial Infrared Interaction Pulse............................................................................................1636
33.4.1.4
Software Packet Assembly Mode..........................................................................................1637
33.4.2
Transmitter FIFO.......................................................................................................................................1637
33.4.3
Receiver Overview.....................................................................................................................................1637
33.4.4
33.5
Title
33.4.3.1
MIR Mode-Receiver..............................................................................................................1637
33.4.3.2
FIR Mode-Receiver................................................................................................................1638
33.4.3.3
Software Packet Disassembly Mode......................................................................................1638
Receiver FIFO............................................................................................................................................1638
Initialization/Application Information..........................................................................................................................1639
33.5.1
Examples of FIRI Programming................................................................................................................1639
33.5.1.1
Transmitter Programming Scenario.......................................................................................1639
33.5.1.2
Receiver Programming Scenario...........................................................................................1640
Chapter 34
Flexible Controller Area Network (FLEXCAN)
34.1
34.2
34.3
Introduction...................................................................................................................................................................1641
34.1.1
General Overview......................................................................................................................................1642
34.1.2
FLEXCAN Block Features........................................................................................................................1643
34.1.3
Modes of Operation...................................................................................................................................1644
External Signal Description..........................................................................................................................................1645
34.2.1
Signals Overview.......................................................................................................................................1645
34.2.2
Signal Descriptions....................................................................................................................................1645
34.2.2.1
CAN Rx .................................................................................................................................1645
34.2.2.2
CAN Tx .................................................................................................................................1645
Buffers...........................................................................................................................................................................1646
34.3.1
Standard/Extended Message Buffer (MB0) Memory Map........................................................................1646
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34.4
Message Buffer Structure...........................................................................................................................1646
34.3.3
Rx FIFO Structure......................................................................................................................................1650
Functional Description..................................................................................................................................................1652
34.4.1
Overview....................................................................................................................................................1652
34.4.2
Transmit Process........................................................................................................................................1652
34.4.3
Arbitration process.....................................................................................................................................1653
34.4.4
Receive Process..........................................................................................................................................1654
34.4.5
Matching Process.......................................................................................................................................1656
34.4.6
Data Coherence..........................................................................................................................................1658
34.4.6.1
Transmission Abort Mechanism............................................................................................1658
34.4.6.2
Message Buffer Deactivation.................................................................................................1659
34.4.6.3
Message Buffer Lock Mechanism.........................................................................................1660
34.4.7
Rx FIFO.....................................................................................................................................................1661
34.4.8
CAN Protocol Related Features.................................................................................................................1662
34.4.10
34.4.8.1
Overload Frames....................................................................................................................1662
34.4.8.2
Time Stamp............................................................................................................................1662
34.4.8.3
Protocol Timing.....................................................................................................................1663
34.4.8.4
Arbitration and Matching Timing..........................................................................................1665
Modes of Operation Details.......................................................................................................................1666
34.4.9.1
Freeze Mode...........................................................................................................................1666
34.4.9.2
Block Disable Mode...............................................................................................................1666
34.4.9.3
Stop Mode..............................................................................................................................1667
Interrupts....................................................................................................................................................1668
Initialization/Application Information..........................................................................................................................1669
34.5.1
34.6
Page
34.3.2
34.4.9
34.5
Title
FLEXCAN Initialization Sequence...........................................................................................................1669
Programmable Registers...............................................................................................................................................1670
34.6.1
Module Configuration Register (FLEXCANx_MCR)...............................................................................1673
34.6.2
Control Register (FLEXCANx_CTRL).....................................................................................................1677
34.6.3
Free Running Timer (FLEXCANx_TIMER).............................................................................................1679
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34.6.4
Rx Global Mask (FLEXCANx_RXGMASK)...........................................................................................1680
34.6.5
Rx 14 Mask (FLEXCANx_RX14MASK).................................................................................................1681
34.6.6
Rx 15 Mask (FLEXCANx_RX15MASK).................................................................................................1681
34.6.7
Error Counter Register (FLEXCANx_ECR).............................................................................................1682
34.6.8
Error and Status Register (FLEXCANx_ESR)..........................................................................................1684
34.6.9
Interrupt Masks 2 Register (FLEXCANx_IMASK2)................................................................................1686
34.6.10
Interrupt Masks 1 Register (FLEXCANx_IMASK1)................................................................................1687
34.6.11
Interrupt Flags 2 Register (FLEXCANx_IFLAG2)...................................................................................1688
34.6.12
Interrupt Flags 1 Register (FLEXCANx_IFLAG1)...................................................................................1688
34.6.13
Glitch Filter Width Register (FLEXCANx_GFWR).................................................................................1689
34.6.14
Rx Individual Mask Registers (FLEXCANx_RXnIMR)...........................................................................1690
Chapter 35
Electrical Fuse Array (FUSEBOX)
35.1
Introduction ..................................................................................................................................................................1691
35.1.1
Overview....................................................................................................................................................1692
35.1.2
Modes of Operation...................................................................................................................................1694
35.1.2.1
35.2
35.4
35.1.2.1.1
Word Read......................................................................................................1695
35.1.2.1.2
Bit Program.....................................................................................................1697
35.1.2.2
Bypass FUSEBOX.................................................................................................................1700
35.1.2.3
Low Power Modes.................................................................................................................1700
External Signal Description..........................................................................................................................................1701
35.2.1
35.3
Normal Operating Modes.......................................................................................................1694
Detailed Signal Descriptions .....................................................................................................................1701
Functional Description..................................................................................................................................................1701
35.3.1
Clocks.........................................................................................................................................................1702
35.3.2
Reset...........................................................................................................................................................1702
35.3.3
Interrupts....................................................................................................................................................1702
Initialization Information..............................................................................................................................................1702
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Title
Page
Chapter 36
General Power Controller (GPC)
36.1
36.2
36.3
Introduction ..................................................................................................................................................................1703
36.1.1
Overview....................................................................................................................................................1703
36.1.2
Features......................................................................................................................................................1704
Functional Description..................................................................................................................................................1704
36.2.1
DVFS - Dynamic Voltage & Frequency Scaling.......................................................................................1705
36.2.2
DVFS Change Request Sequence Diagrams.............................................................................................1706
36.2.3
Frequency / Voltage Change Controller Description.................................................................................1708
36.2.3.1
GPC Controller Description...................................................................................................1708
36.2.3.2
Clock Control Module Frequency Update Controller Description........................................1710
36.2.4
State Retention Power Gating (SRPG)......................................................................................................1712
36.2.5
PMIC Interface Requirements for APM Support......................................................................................1712
Programmable Registers...............................................................................................................................................1716
36.3.1
Interface Control Register (GPC_CNTR)..................................................................................................1716
36.3.2
Voltage Counter Register (GPC_VCR).....................................................................................................1718
36.3.3
NEON register (GPC_NEON)...................................................................................................................1719
Chapter 37
General Purpose Input/Output (GPIO)
37.1
Introduction...................................................................................................................................................................1721
37.2
General Overview.........................................................................................................................................................1722
37.2.1
37.3
Features......................................................................................................................................................1724
GPIO Functional Description.......................................................................................................................................1724
37.3.1
GPIO Function...........................................................................................................................................1724
37.3.2
GPIO Programming...................................................................................................................................1725
37.3.3
37.3.2.1
GPIO Read Mode...................................................................................................................1725
37.3.2.2
GPIO Write Mode..................................................................................................................1725
Interrupt Control Unit................................................................................................................................1726
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37.4
Title
Page
Programmable Registers...............................................................................................................................................1726
37.4.1
GPIO data register (GPIOx_DR)...............................................................................................................1729
37.4.2
GPIO direction register (GPIOx_GDIR)....................................................................................................1731
37.4.3
GPIO pad status register (GPIOx_PSR).....................................................................................................1732
37.4.4
GPIO interrupt configuration register1 (GPIOx_ICR1).............................................................................1733
37.4.5
GPIO interrupt configuration register2 (GPIOx_ICR2).............................................................................1737
37.4.6
GPIO interrupt mask register (GPIOx_IMR).............................................................................................1741
37.4.7
GPIO interrupt status register (GPIOx_ISR).............................................................................................1742
37.4.8
GPIO edge select register (GPIOx_EDGE_SEL)......................................................................................1743
Chapter 38
General Purpose Timer (GPT)
38.1
38.2
38.3
Overview.......................................................................................................................................................................1745
38.1.1
Features......................................................................................................................................................1747
38.1.2
Modes and Operation.................................................................................................................................1747
External Signals............................................................................................................................................................1748
38.2.1
External Clock Input: IND_CLKIN...........................................................................................................1748
38.2.2
Input Capture Trigger Signals: IND_CAPIN1, IND_CAPIN2.................................................................1748
38.2.3
Output Compare Signals: DO_CMPOUT1, DO_CMPOUT2, DO_CMPOUT3.......................................1749
Functional Description..................................................................................................................................................1749
38.3.1
38.3.2
Operating Modes........................................................................................................................................1749
38.3.1.1
Restart Mode..........................................................................................................................1749
38.3.1.2
Free-Run Mode......................................................................................................................1749
Operation....................................................................................................................................................1750
38.3.2.1
Clocks.....................................................................................................................................1750
38.3.2.2
Input Capture..........................................................................................................................1752
38.3.2.3
Output Compare.....................................................................................................................1753
38.3.2.4
Interrupts................................................................................................................................1754
38.3.2.5
Low Power Mode Behavior...................................................................................................1755
38.3.2.6
Debug Mode Behavior...........................................................................................................1755
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38.4
Title
Page
Programmable Registers...............................................................................................................................................1755
38.4.1
GPT Control Register (GPT_CR)..............................................................................................................1757
38.4.2
GPT Prescaler Register (GPT_PR)............................................................................................................1760
38.4.3
GPT Status Register (GPT_SR).................................................................................................................1761
38.4.4
GPT Interrupt Register (GPT_IR)..............................................................................................................1762
38.4.5
GPT Output Compare Register 1 (GPT_OCR1)........................................................................................1763
38.4.6
GPT Output Compare Register 2 (GPT_OCR2)........................................................................................1764
38.4.7
GPT Output Compare Register 3 (GPT_OCR3)........................................................................................1764
38.4.8
GPT Input Capture Register 1 (GPT_ICR1)..............................................................................................1765
38.4.9
GPT Input Capture Register 2 (GPT_ICR2)..............................................................................................1765
38.4.10
GPT Counter Register (GPT_CNT)...........................................................................................................1766
Chapter 39
2D Graphics Processing Unit (GPU2D)
39.1
Overview.......................................................................................................................................................................1767
39.2
GPU2D Feature List.....................................................................................................................................................1767
39.2.1
Frame Buffer..............................................................................................................................................1767
39.2.2
2D Bitmap Graphics (Separate 2D Unit)...................................................................................................1768
39.2.3
Vector Graphics.........................................................................................................................................1769
39.3
GPU2D Block Diagram................................................................................................................................................1770
39.4
GPU SoC Interface.......................................................................................................................................................1770
39.4.1
GPU2D Top Level Diagram......................................................................................................................1770
39.4.2
SoC Bus Connection..................................................................................................................................1771
39.5
Other Signals Connection.............................................................................................................................................1772
39.6
Clocking Architecture...................................................................................................................................................1772
39.7
Power Management......................................................................................................................................................1772
39.8
Modes of Operation......................................................................................................................................................1773
39.9
Reset..............................................................................................................................................................................1773
39.10 Interrupts.......................................................................................................................................................................1774
39.11 DMA.............................................................................................................................................................................1774
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Section Number
Title
Page
39.12 Memory Map................................................................................................................................................................1774
39.12.1
AHB Slave Interface..................................................................................................................................1774
39.12.2
AXI Master Memory Interface (EXTMC Port).........................................................................................1775
Chapter 40
3D Graphics Processing Unit (GPU3D)
40.1
Overview.......................................................................................................................................................................1777
40.2
GPU3D Features Overview..........................................................................................................................................1777
40.3
Capabilities and Performance.......................................................................................................................................1778
40.4
GPU3D Block Diagram................................................................................................................................................1778
40.5
GPU3D Interface..........................................................................................................................................................1779
40.6
40.5.1
GPU3D Top Level Diagram......................................................................................................................1779
40.5.2
SoC Interface Summary.............................................................................................................................1780
40.5.3
Memory Interface Detail............................................................................................................................1781
40.5.3.1
Access Type ..........................................................................................................................1781
40.5.3.2
Memory Management ...........................................................................................................1782
40.5.4
DMI Interface Detail..................................................................................................................................1785
40.5.5
Debug Bus and GPIO.................................................................................................................................1785
40.5.5.1
Debug Bus..............................................................................................................................1786
40.5.5.2
GPIO Register........................................................................................................................1786
Clocking Architecture...................................................................................................................................................1787
40.6.1
Clock Input.................................................................................................................................................1787
40.6.2
Clock Gating..............................................................................................................................................1787
40.7
Reset..............................................................................................................................................................................1788
40.8
Interrupts.......................................................................................................................................................................1789
40.9
Memory Map................................................................................................................................................................1789
Chapter 41
I2C Controller (I2C)
41.1
Overview.......................................................................................................................................................................1791
41.1.1
Features......................................................................................................................................................1793
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41.1.2
Title
Page
Modes and Operations...............................................................................................................................1794
41.1.2.1
Standard Mode.......................................................................................................................1794
41.1.2.2
Fast Mode...............................................................................................................................1794
41.2
External Signals............................................................................................................................................................1794
41.3
Functional Description..................................................................................................................................................1795
41.4
41.3.1
I2C System Configuration.........................................................................................................................1795
41.3.2
I2C Protocol...............................................................................................................................................1795
41.3.2.1
START Signal........................................................................................................................1796
41.3.2.2
Slave Address Transmission..................................................................................................1796
41.3.2.3
Data Transfer..........................................................................................................................1796
41.3.2.4
STOP Signal ..........................................................................................................................1797
41.3.2.5
Repeat Start............................................................................................................................1797
41.3.3
Arbitration Procedure.................................................................................................................................1798
41.3.4
Clock Synchronization...............................................................................................................................1798
41.3.5
Handshaking...............................................................................................................................................1799
41.3.6
Clock Stretching.........................................................................................................................................1799
41.3.7
Peripheral Bus Accesses............................................................................................................................1800
41.3.8
Generation of Transfer Error on IP Bus.....................................................................................................1800
41.3.9
Clocks.........................................................................................................................................................1800
41.3.10
Reset...........................................................................................................................................................1800
41.3.11
Interrupts....................................................................................................................................................1800
41.3.12
Byte Order..................................................................................................................................................1801
Initialization..................................................................................................................................................................1801
41.4.1
Initialization Sequence...............................................................................................................................1801
41.4.2
Generation of START................................................................................................................................1801
41.4.3
Post-Transfer Software Response..............................................................................................................1802
41.4.4
Generation of STOP...................................................................................................................................1802
41.4.5
Generation of Repeated START................................................................................................................1803
41.4.6
Slave Mode................................................................................................................................................1803
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Title
Page
Arbitration Lost..........................................................................................................................................1803
41.5
Software Restriction......................................................................................................................................................1812
41.6
Programmable Registers...............................................................................................................................................1812
41.6.1
I2C Memory Map/Register Definition.......................................................................................................1812
41.61.1
I2C Address Register (I2Cx_IADR)......................................................................................1813
41.61.2
I2C Frequency Divider Register (I2Cx_IFDR)......................................................................1814
41.61.3
I2C Control Register (I2Cx_I2CR)........................................................................................1815
41.61.4
I2C Status Register (I2Cx_I2SR)...........................................................................................1817
41.61.5
I2C Data I/O Register (I2Cx_I2DR)......................................................................................1818
Chapter 42
IC Identification Module (IIM)
42.1
Overview.......................................................................................................................................................................1821
42.1.1
42.2
Modes of Operation...................................................................................................................................1821
Functional Description..................................................................................................................................................1821
42.2.1
42.2.2
Signal Groups.............................................................................................................................................1821
42.2.1.1
System JTAG Control............................................................................................................1822
42.2.1.2
Fuse Bank 0............................................................................................................................1823
42.2.1.3
Fuse Bank 1............................................................................................................................1823
42.2.1.4
Fuse Bank 2............................................................................................................................1823
42.2.1.4.1
SCC Key Format.............................................................................................1823
42.2.1.4.2
SCC Key Checking.........................................................................................1824
42.2.1.5
Fuse Bank 3............................................................................................................................1825
42.2.1.6
Fuse Bank 4............................................................................................................................1825
42.2.1.7
Software-Controllable Volatile Signals.................................................................................1825
FUSEBOX Signals.....................................................................................................................................1826
42.2.2.1
FUSEBOX Operations...........................................................................................................1829
42.2.2.1.1
Word Read......................................................................................................1829
42.2.2.1.2
Bit Program.....................................................................................................1831
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42.2.3
42.2.4
42.2.5
42.3
42.4
Title
Page
Fuse Value Storage....................................................................................................................................1835
42.2.3.1
Software Fuse Value Shadow Cache.....................................................................................1835
42.2.3.2
Hardware-Visible Fuse Shadow Cache..................................................................................1835
Fuse Protection...........................................................................................................................................1836
42.2.4.1
FUSEBOX Bank Protection Fuse..........................................................................................1836
42.2.4.2
Scan Out Protection...............................................................................................................1836
Fuse Bank Operations................................................................................................................................1837
42.2.5.1
Read Sequence.......................................................................................................................1837
42.2.5.2
Explicit Sense Sequence........................................................................................................1839
42.2.5.3
Programming Sequence.........................................................................................................1840
42.2.5.4
Override Sequence.................................................................................................................1842
Initialization/Application Information..........................................................................................................................1842
42.3.1
Initialization...............................................................................................................................................1842
42.3.2
Program......................................................................................................................................................1843
Programmable Registers...............................................................................................................................................1843
42.4.1
Status register (IIM_STAT).......................................................................................................................1844
42.4.2
Status IRQ Mask register (IIM_STATM)..................................................................................................1845
42.4.3
Module Errors register (IIM_ERR)............................................................................................................1846
42.4.4
Error IRQ Mask register (IIM_EMASK)...................................................................................................1847
42.4.5
Fuse Control register (IIM_FCTL)............................................................................................................1848
42.4.6
Upper Address register (IIM_UA).............................................................................................................1849
42.4.7
Lower Address register (IIM_LA).............................................................................................................1850
42.4.8
Explicit Sense Data register (IIM_SDAT).................................................................................................1850
42.4.9
Product Revision register (IIM_PREV).....................................................................................................1851
42.4.10
Silicon Revision register (IIM_SREV)......................................................................................................1851
42.4.11
Program Protection register (IIM_PREG_P).............................................................................................1852
42.4.12
Software-Controllable Signals register 0 (IIM_SCS0)..............................................................................1852
42.4.13
Software-Controllable Signals register 2 (IIM_SCS2)..............................................................................1853
42.4.14
Software-Controllable Signals register 3 (IIM_SCS3)..............................................................................1854
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Chapter 43
IOMUX Controller (IOMUXC)
43.1
Introduction ..................................................................................................................................................................1857
43.1.1
Overview....................................................................................................................................................1857
43.1.2
Features......................................................................................................................................................1859
43.1.3
Modes of Operation...................................................................................................................................1859
43.2
External Signal Description..........................................................................................................................................1859
43.3
Programmable Registers...............................................................................................................................................1860
43.3.1
General Purpose Register 0 (IOMUXC_GPR0)........................................................................................1890
43.3.2
General Purpose Register 1 (IOMUXC_GPR1)........................................................................................1893
43.3.3
General Purpose Register 2 (IOMUXC_GPR2)........................................................................................1894
43.3.4
OBSERVE_MUX 0 Register (IOMUXC_OMUX0).................................................................................1896
43.3.5
OBSERVE_MUX 1 Register 1 (IOMUXC_OMUX1)..............................................................................1898
43.3.6
OBSERVE_MUX 2 Register (IOMUXC_OMUX2).................................................................................1900
43.3.7
OBSERVE_MUX 3 Register (IOMUXC_OMUX3).................................................................................1901
43.3.8
OBSERVE_MUX 4 Register (IOMUXC_OMUX4).................................................................................1902
43.3.9
IOMUXC_SW_MUX_CTL_PAD_GPIO_19 (IOMUXC_GPIO_19)......................................................1904
43.3.10
IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 (IOMUXC_KEY_COL0)............................................1905
43.3.11
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 (IOMUXC_KEY_ROW0)..........................................1906
43.3.12
IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 (IOMUXC_KEY_COL1)............................................1906
43.3.13
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 (IOMUXC_KEY_ROW1)..........................................1907
43.3.14
IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 (IOMUXC_KEY_COL2)............................................1908
43.3.15
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 (IOMUXC_KEY_ROW2)..........................................1909
43.3.16
IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 (IOMUXC_KEY_COL3)............................................1910
43.3.17
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 (IOMUXC_KEY_ROW3)..........................................1911
43.3.18
IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 (IOMUXC_KEY_COL4)............................................1912
43.3.19
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 (IOMUXC_KEY_ROW4)..........................................1912
43.3.20
IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK (IOMUXC_DI0_DISP_CLK)...............................1913
43.3.21
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 (IOMUXC_DI0_PIN15)...............................................1914
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43.3.22
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN2 (IOMUXC_DI0_PIN2)...................................................1915
43.3.23
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN3 (IOMUXC_DI0_PIN3)...................................................1915
43.3.24
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN4 (IOMUXC_DI0_PIN4)...................................................1916
43.3.25
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT0 (IOMUXC_DISP0_DAT0).......................................1917
43.3.26
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT1 (IOMUXC_DISP0_DAT1).......................................1918
43.3.27
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT2 (IOMUXC_DISP0_DAT2).......................................1918
43.3.28
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT3 (IOMUXC_DISP0_DAT3).......................................1919
43.3.29
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT4 (IOMUXC_DISP0_DAT4).......................................1920
43.3.30
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT5 (IOMUXC_DISP0_DAT5).......................................1921
43.3.31
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT6 (IOMUXC_DISP0_DAT6).......................................1921
43.3.32
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT7 (IOMUXC_DISP0_DAT7).......................................1922
43.3.33
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT8 (IOMUXC_DISP0_DAT8).......................................1923
43.3.34
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT9 (IOMUXC_DISP0_DAT9).......................................1924
43.3.35
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT10 (IOMUXC_DISP0_DAT10)...................................1924
43.3.36
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT11 (IOMUXC_DISP0_DAT11)...................................1925
43.3.37
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT12 (IOMUXC_DISP0_DAT12)...................................1926
43.3.38
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT13 (IOMUXC_DISP0_DAT13)...................................1927
43.3.39
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT14 (IOMUXC_DISP0_DAT14)...................................1927
43.3.40
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT15 (IOMUXC_DISP0_DAT15)...................................1928
43.3.41
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT16 (IOMUXC_DISP0_DAT16)...................................1929
43.3.42
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT17 (IOMUXC_DISP0_DAT17)...................................1930
43.3.43
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT18 (IOMUXC_DISP0_DAT18)...................................1931
43.3.44
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT19 (IOMUXC_DISP0_DAT19)...................................1932
43.3.45
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT20 (IOMUXC_DISP0_DAT20)...................................1933
43.3.46
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT21 (IOMUXC_DISP0_DAT21)...................................1933
43.3.47
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT22 (IOMUXC_DISP0_DAT22)...................................1934
43.3.48
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT23 (IOMUXC_DISP0_DAT23)...................................1935
43.3.49
IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK (IOMUXC_CSI0_PIXCLK)...................................1936
43.3.50
IOMUXC_SW_MUX_CTL_PAD_CSI0_MCLK (IOMUXC_CSI0_MCLK).........................................1937
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43.3.51
IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN (IOMUXC_CSI0_DATA_EN)...........................1937
43.3.52
IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC (IOMUXC_CSI0_VSYNC).....................................1938
43.3.53
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT4 (IOMUXC_CSI0_DAT4)............................................1939
43.3.54
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT5 (IOMUXC_CSI0_DAT5)............................................1939
43.3.55
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT6 (IOMUXC_CSI0_DAT6)............................................1940
43.3.56
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT7 (IOMUXC_CSI0_DAT7)............................................1941
43.3.57
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT8 (IOMUXC_CSI0_DAT8)............................................1942
43.3.58
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT9 (IOMUXC_CSI0_DAT9)............................................1943
43.3.59
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT10 (IOMUXC_CSI0_DAT10)........................................1944
43.3.60
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT11 (IOMUXC_CSI0_DAT11)........................................1944
43.3.61
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT12 (IOMUXC_CSI0_DAT12)........................................1945
43.3.62
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT13 (IOMUXC_CSI0_DAT13)........................................1946
43.3.63
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT14 (IOMUXC_CSI0_DAT14)........................................1947
43.3.64
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT15 (IOMUXC_CSI0_DAT15)........................................1948
43.3.65
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT16 (IOMUXC_CSI0_DAT16)........................................1948
43.3.66
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT17 (IOMUXC_CSI0_DAT17)........................................1949
43.3.67
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT18 (IOMUXC_CSI0_DAT18)........................................1950
43.3.68
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT19 (IOMUXC_CSI0_DAT19)........................................1951
43.3.69
IOMUXC_SW_MUX_CTL_PAD_EIM_A25 (IOMUXC_EIM_A25)....................................................1951
43.3.70
IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 (IOMUXC_EIM_EB2)....................................................1952
43.3.71
IOMUXC_SW_MUX_CTL_PAD_EIM_D16 (IOMUXC_EIM_D16)....................................................1953
43.3.72
IOMUXC_SW_MUX_CTL_PAD_EIM_D17 (IOMUXC_EIM_D17)....................................................1954
43.3.73
IOMUXC_SW_MUX_CTL_PAD_EIM_D18 (IOMUXC_EIM_D18)....................................................1954
43.3.74
IOMUXC_SW_MUX_CTL_PAD_EIM_D19 (IOMUXC_EIM_D19)....................................................1955
43.3.75
IOMUXC_SW_MUX_CTL_PAD_EIM_D20 (IOMUXC_EIM_D20)....................................................1956
43.3.76
IOMUXC_SW_MUX_CTL_PAD_EIM_D21 (IOMUXC_EIM_D21)....................................................1957
43.3.77
IOMUXC_SW_MUX_CTL_PAD_EIM_D22 (IOMUXC_EIM_D22)....................................................1958
43.3.78
IOMUXC_SW_MUX_CTL_PAD_EIM_D23 (IOMUXC_EIM_D23)....................................................1958
43.3.79
IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 (IOMUXC_EIM_EB3)....................................................1959
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43.3.80
IOMUXC_SW_MUX_CTL_PAD_EIM_D24 (IOMUXC_EIM_D24)....................................................1960
43.3.81
IOMUXC_SW_MUX_CTL_PAD_EIM_D25 (IOMUXC_EIM_D25)....................................................1961
43.3.82
IOMUXC_SW_MUX_CTL_PAD_EIM_D26 (IOMUXC_EIM_D26)....................................................1962
43.3.83
IOMUXC_SW_MUX_CTL_PAD_EIM_D27 (IOMUXC_EIM_D27)....................................................1962
43.3.84
IOMUXC_SW_MUX_CTL_PAD_EIM_D28 (IOMUXC_EIM_D28)....................................................1963
43.3.85
IOMUXC_SW_MUX_CTL_PAD_EIM_D29 (IOMUXC_EIM_D29)....................................................1964
43.3.86
IOMUXC_SW_MUX_CTL_PAD_EIM_D30 (IOMUXC_EIM_D30)....................................................1965
43.3.87
IOMUXC_SW_MUX_CTL_PAD_EIM_D31 (IOMUXC_EIM_D31)....................................................1966
43.3.88
IOMUXC_SW_MUX_CTL_PAD_EIM_A24 (IOMUXC_EIM_A24)....................................................1966
43.3.89
IOMUXC_SW_MUX_CTL_PAD_EIM_A23 (IOMUXC_EIM_A23)....................................................1967
43.3.90
IOMUXC_SW_MUX_CTL_PAD_EIM_A22 (IOMUXC_EIM_A22)....................................................1968
43.3.91
IOMUXC_SW_MUX_CTL_PAD_EIM_A21 (IOMUXC_EIM_A21)....................................................1968
43.3.92
IOMUXC_SW_MUX_CTL_PAD_EIM_A20 (IOMUXC_EIM_A20)....................................................1969
43.3.93
IOMUXC_SW_MUX_CTL_PAD_EIM_A19 (IOMUXC_EIM_A19)....................................................1970
43.3.94
IOMUXC_SW_MUX_CTL_PAD_EIM_A18 (IOMUXC_EIM_A18)....................................................1970
43.3.95
IOMUXC_SW_MUX_CTL_PAD_EIM_A17 (IOMUXC_EIM_A17)....................................................1971
43.3.96
IOMUXC_SW_MUX_CTL_PAD_EIM_A16 (IOMUXC_EIM_A16)....................................................1972
43.3.97
IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 (IOMUXC_EIM_CS0)....................................................1972
43.3.98
IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 (IOMUXC_EIM_CS1)....................................................1973
43.3.99
IOMUXC_SW_MUX_CTL_PAD_EIM_OE (IOMUXC_EIM_OE).......................................................1974
43.3.100
IOMUXC_SW_MUX_CTL_PAD_EIM_RW (IOMUXC_EIM_RW).....................................................1974
43.3.101
IOMUXC_SW_MUX_CTL_PAD_EIM_LBA (IOMUXC_EIM_LBA)..................................................1975
43.3.102
IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 (IOMUXC_EIM_EB0)....................................................1976
43.3.103
IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 (IOMUXC_EIM_EB1)....................................................1977
43.3.104
IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 (IOMUXC_EIM_DA0)..................................................1977
43.3.105
IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 (IOMUXC_EIM_DA1)..................................................1978
43.3.106
IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 (IOMUXC_EIM_DA2)..................................................1979
43.3.107
IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 (IOMUXC_EIM_DA3)..................................................1979
43.3.108
IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 (IOMUXC_EIM_DA4)..................................................1980
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43.3.109
IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 (IOMUXC_EIM_DA5)..................................................1981
43.3.110
IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 (IOMUXC_EIM_DA6)..................................................1981
43.3.111
IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 (IOMUXC_EIM_DA7)..................................................1982
43.3.112
IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 (IOMUXC_EIM_DA8)..................................................1983
43.3.113
IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 (IOMUXC_EIM_DA9)..................................................1983
43.3.114
IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 (IOMUXC_EIM_DA10)..............................................1984
43.3.115
IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 (IOMUXC_EIM_DA11)..............................................1985
43.3.116
IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 (IOMUXC_EIM_DA12)..............................................1985
43.3.117
IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 (IOMUXC_EIM_DA13)..............................................1986
43.3.118
IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 (IOMUXC_EIM_DA14)..............................................1987
43.3.119
IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 (IOMUXC_EIM_DA15)..............................................1988
43.3.120
IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (IOMUXC_NANDF_WE_B)...............................1988
43.3.121
IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (IOMUXC_NANDF_RE_B)..................................1989
43.3.122
IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT (IOMUXC_EIM_WAIT).............................................1990
43.3.123
IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK (IOMUXC_EIM_BCLK).............................................1990
43.3.124
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX3_P (IOMUXC_LVDS1_TX3_P).................................1991
43.3.125
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX2_P (IOMUXC_LVDS1_TX2_P).................................1992
43.3.126
IOMUXC_SW_MUX_CTL_PAD_LVDS1_CLK_P (IOMUXC_LVDS1_CLK_P)...............................1992
43.3.127
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX1_P (IOMUXC_LVDS1_TX1_P).................................1993
43.3.128
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX0_P (IOMUXC_LVDS1_TX0_P).................................1994
43.3.129
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX3_P (IOMUXC_LVDS0_TX3_P).................................1994
43.3.130
IOMUXC_SW_MUX_CTL_PAD_LVDS0_CLK_P (IOMUXC_LVDS0_CLK_P)...............................1995
43.3.131
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX2_P (IOMUXC_LVDS0_TX2_P).................................1996
43.3.132
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX1_P (IOMUXC_LVDS0_TX1_P).................................1996
43.3.133
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX0_P (IOMUXC_LVDS0_TX0_P).................................1997
43.3.134
IOMUXC_SW_MUX_CTL_PAD_GPIO_10 (IOMUXC_GPIO_10)......................................................1998
43.3.135
IOMUXC_SW_MUX_CTL_PAD_GPIO_11 (IOMUXC_GPIO_11)......................................................1998
43.3.136
IOMUXC_SW_MUX_CTL_PAD_GPIO_12 (IOMUXC_GPIO_12)......................................................1999
43.3.137
IOMUXC_SW_MUX_CTL_PAD_GPIO_13 (IOMUXC_GPIO_13)......................................................1999
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Section Number
Title
Page
43.3.138
IOMUXC_SW_MUX_CTL_PAD_GPIO_14 (IOMUXC_GPIO_14)......................................................2000
43.3.139
IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (IOMUXC_NANDF_CLE)......................................2000
43.3.140
IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (IOMUXC_NANDF_ALE)......................................2001
43.3.141
IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (IOMUXC_NANDF_WP_B)................................2002
43.3.142
IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (IOMUXC_NANDF_RB0)......................................2002
43.3.143
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (IOMUXC_NANDF_CS0).......................................2003
43.3.144
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (IOMUXC_NANDF_CS1).......................................2004
43.3.145
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (IOMUXC_NANDF_CS2).......................................2004
43.3.146
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (IOMUXC_NANDF_CS3).......................................2005
43.3.147
IOMUXC_SW_MUX_CTL_PAD_FEC_MDIO (IOMUXC_FEC_MDIO).............................................2006
43.3.148
IOMUXC_SW_MUX_CTL_PAD_FEC_REF_CLK (IOMUXC_FEC_REF_CLK)...............................2007
43.3.149
IOMUXC_SW_MUX_CTL_PAD_FEC_RX_ER (IOMUXC_FEC_RX_ER).........................................2008
43.3.150
IOMUXC_SW_MUX_CTL_PAD_FEC_CRS_DV (IOMUXC_FEC_CRS_DV)...................................2008
43.3.151
IOMUXC_SW_MUX_CTL_PAD_FEC_RXD1 (IOMUXC_FEC_RXD1).............................................2009
43.3.152
IOMUXC_SW_MUX_CTL_PAD_FEC_RXD0 (IOMUXC_FEC_RXD0).............................................2010
43.3.153
IOMUXC_SW_MUX_CTL_PAD_FEC_TX_EN (IOMUXC_FEC_TX_EN).........................................2011
43.3.154
IOMUXC_SW_MUX_CTL_PAD_FEC_TXD1 (IOMUXC_FEC_TXD1)..............................................2011
43.3.155
IOMUXC_SW_MUX_CTL_PAD_FEC_TXD0 (IOMUXC_FEC_TXD0)..............................................2012
43.3.156
IOMUXC_SW_MUX_CTL_PAD_FEC_MDC (IOMUXC_FEC_MDC)................................................2013
43.3.157
IOMUXC_SW_MUX_CTL_PAD_PATA_DIOW (IOMUXC_PATA_DIOW)......................................2014
43.3.158
IOMUXC_SW_MUX_CTL_PAD_PATA_DMACK (IOMUXC_PATA_DMACK)..............................2014
43.3.159
IOMUXC_SW_MUX_CTL_PAD_PATA_DMARQ (IOMUXC_PATA_DMARQ)..............................2015
43.3.160
IOMUXC_SW_MUX_CTL_PAD_PATA_BUFFER_EN (IOMUXC_PATA_BUFFER_EN)...............2016
43.3.161
IOMUXC_SW_MUX_CTL_PAD_PATA_INTRQ (IOMUXC_PATA_INTRQ)...................................2017
43.3.162
IOMUXC_SW_MUX_CTL_PAD_PATA_DIOR (IOMUXC_PATA_DIOR)........................................2017
43.3.163
IOMUXC_SW_MUX_CTL_PAD_PATA_RESET_B (IOMUXC_PATA_RESET_B)..........................2018
43.3.164
IOMUXC_SW_MUX_CTL_PAD_PATA_IORDY (IOMUXC_PATA_IORDY)..................................2019
43.3.165
IOMUXC_SW_MUX_CTL_PAD_PATA_DA_0 (IOMUXC_PATA_DA_0)........................................2020
43.3.166
IOMUXC_SW_MUX_CTL_PAD_PATA_DA_1 (IOMUXC_PATA_DA_1)........................................2020
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69
Section Number
Title
Page
43.3.167
IOMUXC_SW_MUX_CTL_PAD_PATA_DA_2 (IOMUXC_PATA_DA_2)........................................2021
43.3.168
IOMUXC_SW_MUX_CTL_PAD_PATA_CS_0 (IOMUXC_PATA_CS_0)..........................................2022
43.3.169
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA14
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA14)............................................................................2023
43.3.170
IOMUXC_SW_MUX_CTL_PAD_PATA_CS_1 (IOMUXC_SW_MUX_CTL_PAD_PATA_CS_1)...2023
43.3.171
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA0
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA0)..............................................................................2024
43.3.172
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA1
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA1)..............................................................................2025
43.3.173
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA2
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA2)..............................................................................2026
43.3.174
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA3
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA3)..............................................................................2026
43.3.175
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA4
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA4)..............................................................................2027
43.3.176
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA5
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA5)..............................................................................2028
43.3.177
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA6
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA6)..............................................................................2029
43.3.178
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA7
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA7)..............................................................................2029
43.3.179
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA8
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA8)..............................................................................2030
43.3.180
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA9
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA9)..............................................................................2031
43.3.181
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA10
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA10)............................................................................2032
43.3.182
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA11
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA11)............................................................................2032
43.3.183
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA12
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA12)............................................................................2033
43.3.184
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA13
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA13)............................................................................2034
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Section Number
43.3.185
Title
Page
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA15
(IOMUXC_SW_MUX_CTL_PAD_PATA_DATA15)............................................................................2035
43.3.186
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0). 2035
43.3.187
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1). 2036
43.3.188
IOMUXC_SW_MUX_CTL_PAD_SD1_CMD (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD).........2037
43.3.189
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2). 2038
43.3.190
IOMUXC_SW_MUX_CTL_PAD_SD1_CLK (IOMUXC_SW_MUX_CTL_PAD_SD1_CLK)............2038
43.3.191
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3). 2039
43.3.192
IOMUXC_SW_MUX_CTL_PAD_SD2_CLK (IOMUXC_SW_MUX_CTL_PAD_SD2_CLK)............2040
43.3.193
IOMUXC_SW_MUX_CTL_PAD_SD2_CMD (IOMUXC_SW_MUX_CTL_PAD_SD2_CMD).........2041
43.3.194
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3). 2041
43.3.195
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2). 2042
43.3.196
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1). 2043
43.3.197
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0). 2044
43.3.198
IOMUXC_SW_MUX_CTL_PAD_GPIO_0 (IOMUXC_SW_MUX_CTL_PAD_GPIO_0)...................2045
43.3.199
IOMUXC_SW_MUX_CTL_PAD_GPIO_1 (IOMUXC_SW_MUX_CTL_PAD_GPIO_1)...................2045
43.3.200
IOMUXC_SW_MUX_CTL_PAD_GPIO_9 (IOMUXC_SW_MUX_CTL_PAD_GPIO_9)...................2046
43.3.201
IOMUXC_SW_MUX_CTL_PAD_GPIO_3 (IOMUXC_SW_MUX_CTL_PAD_GPIO_3)...................2047
43.3.202
IOMUXC_SW_MUX_CTL_PAD_GPIO_6 (IOMUXC_SW_MUX_CTL_PAD_GPIO_6)...................2048
43.3.203
IOMUXC_SW_MUX_CTL_PAD_GPIO_2 (IOMUXC_SW_MUX_CTL_PAD_GPIO_2)...................2049
43.3.204
IOMUXC_SW_MUX_CTL_PAD_GPIO_4 (IOMUXC_SW_MUX_CTL_PAD_GPIO_4)...................2050
43.3.205
IOMUXC_SW_MUX_CTL_PAD_GPIO_5 (IOMUXC_SW_MUX_CTL_PAD_GPIO_5)...................2050
43.3.206
IOMUXC_SW_MUX_CTL_PAD_GPIO_7 (IOMUXC_SW_MUX_CTL_PAD_GPIO_7)...................2051
43.3.207
IOMUXC_SW_MUX_CTL_PAD_GPIO_8 (IOMUXC_SW_MUX_CTL_PAD_GPIO_8)...................2052
43.3.208
IOMUXC_SW_MUX_CTL_PAD_GPIO_16 (IOMUXC_SW_MUX_CTL_PAD_GPIO_16)...............2053
43.3.209
IOMUXC_SW_MUX_CTL_PAD_GPIO_17 (IOMUXC_SW_MUX_CTL_PAD_GPIO_17)...............2054
43.3.210
IOMUXC_SW_MUX_CTL_PAD_GPIO_18 (IOMUXC_SW_MUX_CTL_PAD_GPIO_18)...............2055
43.3.211
IOMUXC_SW_PAD_CTL_PAD_GPIO_19 (IOMUXC_SW_PAD_CTL_PAD_GPIO_19)..................2056
43.3.212
IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 (IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)........2058
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71
Section Number
Title
Page
43.3.213
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0).....2060
43.3.214
IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 (IOMUXC_SW_PAD_CTL_PAD_KEY_COL1)........2062
43.3.215
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1).....2064
43.3.216
IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 (IOMUXC_SW_PAD_CTL_PAD_KEY_COL2)........2066
43.3.217
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2).....2068
43.3.218
IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 (IOMUXC_SW_PAD_CTL_PAD_KEY_COL3)........2070
43.3.219
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3).....2072
43.3.220
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 (IOMUXC_SW_PAD_CTL_PAD_KEY_COL4)........2074
43.3.221
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4).....2076
43.3.222
IOMUXC_SW_PAD_CTL_PAD_NVCC_KEYPAD
(IOMUXC_SW_PAD_CTL_PAD_NVCC_KEYPAD)............................................................................2078
43.3.223
IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK
(IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK)..............................................................................2079
43.3.224
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15)...........2081
43.3.225
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN2 (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN2)...............2083
43.3.226
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN3 (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN3)...............2085
43.3.227
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN4 (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN4)...............2087
43.3.228
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT0 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT0)...2089
43.3.229
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT1 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT1)...2091
43.3.230
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT2 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT2)...2093
43.3.231
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT3 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT3)...2095
43.3.232
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT4 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT4)...2097
43.3.233
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT5 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT5)...2099
43.3.234
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT6 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT6)...2101
43.3.235
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT7 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT7)...2103
43.3.236
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT8 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT8)...2105
43.3.237
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT9 (IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT9)...2107
43.3.238
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT10
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT10)................................................................................2109
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Section Number
43.3.239
Title
Page
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT11
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT11)................................................................................2111
43.3.240
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT12
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT12)................................................................................2113
43.3.241
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT13
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT13)................................................................................2115
43.3.242
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT14
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT14)................................................................................2117
43.3.243
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT15
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT15)................................................................................2119
43.3.244
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT16
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT16)................................................................................2121
43.3.245
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT17
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT17)................................................................................2123
43.3.246
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT18
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT18)................................................................................2125
43.3.247
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19)................................................................................2127
43.3.248
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT20
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT20)................................................................................2129
43.3.249
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT21
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT21)................................................................................2131
43.3.250
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT22
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT22)................................................................................2133
43.3.251
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT23
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT23)................................................................................2135
43.3.252
IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK
(IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK).................................................................................2137
43.3.253
IOMUXC_SW_PAD_CTL_PAD_CSI0_MCLK (IOMUXC_SW_PAD_CTL_PAD_CSI0_MCLK).....2139
43.3.254
IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN
(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN).............................................................................2141
43.3.255
IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC (IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC). 2143
43.3.256
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT4 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT4)........2145
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73
Section Number
Title
Page
43.3.257
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT5 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT5)........2147
43.3.258
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT6 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT6)........2149
43.3.259
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT7 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT7)........2151
43.3.260
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT8 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT8)........2153
43.3.261
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT9 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT9)........2155
43.3.262
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT10 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT10)....2157
43.3.263
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT11 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT11)....2159
43.3.264
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT12 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT12)....2161
43.3.265
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT13 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT13)....2163
43.3.266
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT14 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT14)....2165
43.3.267
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT15 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT15)....2167
43.3.268
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT16 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT16)....2169
43.3.269
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT17 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT17)....2171
43.3.270
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT18 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT18)....2173
43.3.271
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT19 (IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT19)....2175
43.3.272
IOMUXC_SW_PAD_CTL_PAD_NVCC_CSI__0
(IOMUXC_SW_PAD_CTL_PAD_NVCC_CSI__0)................................................................................2177
43.3.273
IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS (IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS)........2178
43.3.274
IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD (IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD)......2180
43.3.275
IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB (IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB) 2182
43.3.276
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI (IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI)............2184
43.3.277
IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK (IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK).........2186
43.3.278
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO (IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO)........2188
43.3.279
IOMUXC_SW_PAD_CTL_PAD_EIM_A25 (IOMUXC_SW_PAD_CTL_PAD_EIM_A25)................2190
43.3.280
IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 (IOMUXC_SW_PAD_CTL_PAD_EIM_EB2)................2192
43.3.281
IOMUXC_SW_PAD_CTL_PAD_EIM_D16 (IOMUXC_SW_PAD_CTL_PAD_EIM_D16)................2194
43.3.282
IOMUXC_SW_PAD_CTL_PAD_EIM_D17 (IOMUXC_SW_PAD_CTL_PAD_EIM_D17)................2196
43.3.283
IOMUXC_SW_PAD_CTL_PAD_EIM_D18 (IOMUXC_SW_PAD_CTL_PAD_EIM_D18)................2198
43.3.284
IOMUXC_SW_PAD_CTL_PAD_EIM_D19 (IOMUXC_SW_PAD_CTL_PAD_EIM_D19)................2200
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Section Number
Title
Page
43.3.285
IOMUXC_SW_PAD_CTL_PAD_EIM_D20 (IOMUXC_SW_PAD_CTL_PAD_EIM_D20)................2202
43.3.286
IOMUXC_SW_PAD_CTL_PAD_EIM_D21 (IOMUXC_SW_PAD_CTL_PAD_EIM_D21)................2204
43.3.287
IOMUXC_SW_PAD_CTL_PAD_EIM_D22 (IOMUXC_SW_PAD_CTL_PAD_EIM_D22)................2206
43.3.288
IOMUXC_SW_PAD_CTL_PAD_EIM_D23 (IOMUXC_SW_PAD_CTL_PAD_EIM_D23)................2208
43.3.289
IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 (IOMUXC_SW_PAD_CTL_PAD_EIM_EB3)................2210
43.3.290
IOMUXC_SW_PAD_CTL_PAD_EIM_D24 (IOMUXC_SW_PAD_CTL_PAD_EIM_D24)................2212
43.3.291
IOMUXC_SW_PAD_CTL_PAD_EIM_D25 (IOMUXC_SW_PAD_CTL_PAD_EIM_D25)................2214
43.3.292
IOMUXC_SW_PAD_CTL_PAD_EIM_D26 (IOMUXC_SW_PAD_CTL_PAD_EIM_D26)................2216
43.3.293
IOMUXC_SW_PAD_CTL_PAD_EIM_D27 (IOMUXC_SW_PAD_CTL_PAD_EIM_D27)................2218
43.3.294
IOMUXC_SW_PAD_CTL_PAD_EIM_D28 (IOMUXC_SW_PAD_CTL_PAD_EIM_D28)................2220
43.3.295
IOMUXC_SW_PAD_CTL_PAD_EIM_D29 (IOMUXC_SW_PAD_CTL_PAD_EIM_D29)................2222
43.3.296
IOMUXC_SW_PAD_CTL_PAD_EIM_D30 (IOMUXC_SW_PAD_CTL_PAD_EIM_D30)................2224
43.3.297
IOMUXC_SW_PAD_CTL_PAD_EIM_D31 (IOMUXC_SW_PAD_CTL_PAD_EIM_D31)................2226
43.3.298
IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__1
(IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__1)...............................................................................2228
43.3.299
IOMUXC_SW_PAD_CTL_PAD_EIM_A24 (IOMUXC_SW_PAD_CTL_PAD_EIM_A24)................2229
43.3.300
IOMUXC_SW_PAD_CTL_PAD_EIM_A23 (IOMUXC_SW_PAD_CTL_PAD_EIM_A23)................2231
43.3.301
IOMUXC_SW_PAD_CTL_PAD_EIM_A22 (IOMUXC_SW_PAD_CTL_PAD_EIM_A22)................2233
43.3.302
IOMUXC_SW_PAD_CTL_PAD_EIM_A21 (IOMUXC_SW_PAD_CTL_PAD_EIM_A21)................2235
43.3.303
IOMUXC_SW_PAD_CTL_PAD_EIM_A20 (IOMUXC_SW_PAD_CTL_PAD_EIM_A20)................2237
43.3.304
IOMUXC_SW_PAD_CTL_PAD_EIM_A19 (IOMUXC_SW_PAD_CTL_PAD_EIM_A19)................2239
43.3.305
IOMUXC_SW_PAD_CTL_PAD_EIM_A18 (IOMUXC_SW_PAD_CTL_PAD_EIM_A18)................2241
43.3.306
IOMUXC_SW_PAD_CTL_PAD_EIM_A17 (IOMUXC_SW_PAD_CTL_PAD_EIM_A17)................2243
43.3.307
IOMUXC_SW_PAD_CTL_PAD_EIM_A16 (IOMUXC_SW_PAD_CTL_PAD_EIM_A16)................2245
43.3.308
IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 (IOMUXC_SW_PAD_CTL_PAD_EIM_CS0)................2247
43.3.309
IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 (IOMUXC_SW_PAD_CTL_PAD_EIM_CS1)................2249
43.3.310
IOMUXC_SW_PAD_CTL_PAD_EIM_OE (IOMUXC_SW_PAD_CTL_PAD_EIM_OE)...................2251
43.3.311
IOMUXC_SW_PAD_CTL_PAD_EIM_RW (IOMUXC_SW_PAD_CTL_PAD_EIM_RW).................2253
43.3.312
IOMUXC_SW_PAD_CTL_PAD_EIM_LBA (IOMUXC_SW_PAD_CTL_PAD_EIM_LBA)..............2255
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6/2012
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75
Section Number
43.3.313
Title
Page
IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__4
(IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__4)...............................................................................2257
43.3.314
IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 (IOMUXC_SW_PAD_CTL_PAD_EIM_EB0)................2258
43.3.315
IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 (IOMUXC_SW_PAD_CTL_PAD_EIM_EB1)................2260
43.3.316
IOMUXC_SW_PAD_CTL_PAD_EIM_DA0 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA0)..............2262
43.3.317
IOMUXC_SW_PAD_CTL_PAD_EIM_DA1 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA1)..............2264
43.3.318
IOMUXC_SW_PAD_CTL_PAD_EIM_DA2 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA2)..............2266
43.3.319
IOMUXC_SW_PAD_CTL_PAD_EIM_DA3 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA3)..............2268
43.3.320
IOMUXC_SW_PAD_CTL_PAD_EIM_DA4 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA4)..............2270
43.3.321
IOMUXC_SW_PAD_CTL_PAD_EIM_DA5 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA5)..............2272
43.3.322
IOMUXC_SW_PAD_CTL_PAD_EIM_DA6 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA6)..............2274
43.3.323
IOMUXC_SW_PAD_CTL_PAD_EIM_DA7 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA7)..............2276
43.3.324
IOMUXC_SW_PAD_CTL_PAD_EIM_DA8 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA8)..............2278
43.3.325
IOMUXC_SW_PAD_CTL_PAD_EIM_DA9 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA9)..............2280
43.3.326
IOMUXC_SW_PAD_CTL_PAD_EIM_DA10 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA10)..........2282
43.3.327
IOMUXC_SW_PAD_CTL_PAD_EIM_DA11 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA11)..........2284
43.3.328
IOMUXC_SW_PAD_CTL_PAD_EIM_DA12 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA12)..........2286
43.3.329
IOMUXC_SW_PAD_CTL_PAD_EIM_DA13 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA13)..........2288
43.3.330
IOMUXC_SW_PAD_CTL_PAD_EIM_DA14 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA14)..........2290
43.3.331
IOMUXC_SW_PAD_CTL_PAD_EIM_DA15 (IOMUXC_SW_PAD_CTL_PAD_EIM_DA15)..........2292
43.3.332
IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B
(IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B)...............................................................................2294
43.3.333
IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B
(IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B)................................................................................2296
43.3.334
IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT (IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT).........2298
43.3.335
IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK (IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK)........2300
43.3.336
IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__7
(IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__7)...............................................................................2302
43.3.337
IOMUXC_SW_PAD_CTL_PAD_GPIO_10 (IOMUXC_SW_PAD_CTL_PAD_GPIO_10)..................2303
43.3.338
IOMUXC_SW_PAD_CTL_PAD_GPIO_11 (IOMUXC_SW_PAD_CTL_PAD_GPIO_11)..................2305
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6/2012
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Section Number
Title
Page
43.3.339
IOMUXC_SW_PAD_CTL_PAD_GPIO_12 (IOMUXC_SW_PAD_CTL_PAD_GPIO_12)..................2307
43.3.340
IOMUXC_SW_PAD_CTL_PAD_GPIO_13 (IOMUXC_SW_PAD_CTL_PAD_GPIO_13)..................2309
43.3.341
IOMUXC_SW_PAD_CTL_PAD_GPIO_14 (IOMUXC_SW_PAD_CTL_PAD_GPIO_14)..................2311
43.3.342
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3)................................................................................2313
43.3.343
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3)...............................................................................2315
43.3.344
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1)............................................................................2317
43.3.345
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2)................................................................................2319
43.3.346
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1)............................................................................2321
43.3.347
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2)...............................................................................2323
43.3.348
IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET)...............................................................................2325
43.3.349
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1)..........................................................................2327
43.3.350
IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS (IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS).....2329
43.3.351
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0)..........................................................................2331
43.3.352
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0)...............................................................................2333
43.3.353
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0)............................................................................2335
43.3.354
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0)................................................................................2337
43.3.355
IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS (IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS).....2339
43.3.356
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0)............................................................................2341
43.3.357
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1)...............................................................................2343
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6/2012
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77
Section Number
43.3.358
Title
Page
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1)................................................................................2345
43.3.359
IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ
(IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ)..............................................................................2347
43.3.360
IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ
(IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ).........................................................................2349
43.3.361
IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE)..2351
43.3.362
IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE). 2353
43.3.363
IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B
(IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B)...............................................................................2355
43.3.364
IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0). .2357
43.3.365
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0)...2359
43.3.366
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1)...2361
43.3.367
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2)...2363
43.3.368
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3)...2365
43.3.369
IOMUXC_SW_PAD_CTL_PAD_NVCC_NANDF
(IOMUXC_SW_PAD_CTL_PAD_NVCC_NANDF)..............................................................................2367
43.3.370
IOMUXC_SW_PAD_CTL_PAD_FEC_MDIO (IOMUXC_SW_PAD_CTL_PAD_FEC_MDIO)........2368
43.3.371
IOMUXC_SW_PAD_CTL_PAD_FEC_REF_CLK
(IOMUXC_SW_PAD_CTL_PAD_FEC_REF_CLK)...............................................................................2370
43.3.372
IOMUXC_SW_PAD_CTL_PAD_FEC_RX_ER (IOMUXC_SW_PAD_CTL_PAD_FEC_RX_ER)....2372
43.3.373
IOMUXC_SW_PAD_CTL_PAD_FEC_CRS_DV
(IOMUXC_SW_PAD_CTL_PAD_FEC_CRS_DV).................................................................................2374
43.3.374
IOMUXC_SW_PAD_CTL_PAD_FEC_RXD1 (IOMUXC_SW_PAD_CTL_PAD_FEC_RXD1).........2376
43.3.375
IOMUXC_SW_PAD_CTL_PAD_FEC_RXD0 (IOMUXC_SW_PAD_CTL_PAD_FEC_RXD0).........2378
43.3.376
IOMUXC_SW_PAD_CTL_PAD_FEC_TX_EN (IOMUXC_SW_PAD_CTL_PAD_FEC_TX_EN)....2380
43.3.377
IOMUXC_SW_PAD_CTL_PAD_FEC_TXD1 (IOMUXC_SW_PAD_CTL_PAD_FEC_TXD1).........2382
43.3.378
IOMUXC_SW_PAD_CTL_PAD_FEC_TXD0 (IOMUXC_SW_PAD_CTL_PAD_FEC_TXD0).........2384
43.3.379
IOMUXC_SW_PAD_CTL_PAD_FEC_MDC (IOMUXC_SW_PAD_CTL_PAD_FEC_MDC)............2386
43.3.380
IOMUXC_SW_PAD_CTL_PAD_NVCC_FEC (IOMUXC_SW_PAD_CTL_PAD_NVCC_FEC)........2388
43.3.381
IOMUXC_SW_PAD_CTL_PAD_PATA_DIOW (IOMUXC_SW_PAD_CTL_PAD_PATA_DIOW)..2389
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6/2012
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Section Number
43.3.382
Title
Page
IOMUXC_SW_PAD_CTL_PAD_PATA_DMACK
(IOMUXC_SW_PAD_CTL_PAD_PATA_DMACK)..............................................................................2391
43.3.383
IOMUXC_SW_PAD_CTL_PAD_PATA_DMARQ
(IOMUXC_SW_PAD_CTL_PAD_PATA_DMARQ)..............................................................................2393
43.3.384
IOMUXC_SW_PAD_CTL_PAD_PATA_BUFFER_EN
(IOMUXC_SW_PAD_CTL_PAD_PATA_BUFFER_EN)......................................................................2395
43.3.385
IOMUXC_SW_PAD_CTL_PAD_PATA_INTRQ
(IOMUXC_SW_PAD_CTL_PAD_PATA_INTRQ).................................................................................2397
43.3.386
IOMUXC_SW_PAD_CTL_PAD_PATA_DIOR (IOMUXC_SW_PAD_CTL_PAD_PATA_DIOR)....2399
43.3.387
IOMUXC_SW_PAD_CTL_PAD_PATA_RESET_B
(IOMUXC_SW_PAD_CTL_PAD_PATA_RESET_B)............................................................................2401
43.3.388
IOMUXC_SW_PAD_CTL_PAD_PATA_IORDY
(IOMUXC_SW_PAD_CTL_PAD_PATA_IORDY)................................................................................2403
43.3.389
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_0 (IOMUXC_SW_PAD_CTL_PAD_PATA_DA_0)....2405
43.3.390
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_1 (IOMUXC_SW_PAD_CTL_PAD_PATA_DA_1)....2407
43.3.391
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_2 (IOMUXC_SW_PAD_CTL_PAD_PATA_DA_2)....2409
43.3.392
IOMUXC_SW_PAD_CTL_PAD_PATA_CS_0 (IOMUXC_SW_PAD_CTL_PAD_PATA_CS_0)......2411
43.3.393
IOMUXC_SW_PAD_CTL_PAD_PATA_CS_1 (IOMUXC_SW_PAD_CTL_PAD_PATA_CS_1)......2413
43.3.394
IOMUXC_SW_PAD_CTL_PAD_NVCC_PATA__2
(IOMUXC_SW_PAD_CTL_PAD_NVCC_PATA__2)............................................................................2415
43.3.395
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA0
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA0)................................................................................2416
43.3.396
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA1
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA1)................................................................................2418
43.3.397
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA2
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA2)................................................................................2420
43.3.398
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA3
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA3)................................................................................2422
43.3.399
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA4
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA4)................................................................................2424
43.3.400
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA5
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA5)................................................................................2426
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79
Section Number
43.3.401
Title
Page
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA6
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA6)................................................................................2428
43.3.402
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA7
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA7)................................................................................2430
43.3.403
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA8
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA8)................................................................................2432
43.3.404
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA9
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA9)................................................................................2434
43.3.405
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA10
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA10)..............................................................................2436
43.3.406
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA11
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA11)..............................................................................2438
43.3.407
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA12
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA12)..............................................................................2440
43.3.408
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA13
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA13)..............................................................................2442
43.3.409
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA14
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA14)..............................................................................2444
43.3.410
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA15
(IOMUXC_SW_PAD_CTL_PAD_PATA_DATA15)..............................................................................2446
43.3.411
IOMUXC_SW_PAD_CTL_PAD_NVCC_PATA__0
(IOMUXC_SW_PAD_CTL_PAD_NVCC_PATA__0)............................................................................2448
43.3.412
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0)....2449
43.3.413
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1)....2451
43.3.414
IOMUXC_SW_PAD_CTL_PAD_SD1_CMD (IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)............2453
43.3.415
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2)....2455
43.3.416
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK (IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)..............2457
43.3.417
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3)....2459
43.3.418
IOMUXC_SW_PAD_CTL_PAD_NVCC_SD1 (IOMUXC_SW_PAD_CTL_PAD_NVCC_SD1)........2461
43.3.419
IOMUXC_SW_PAD_CTL_PAD_SD2_CLK (IOMUXC_SW_PAD_CTL_PAD_SD2_CLK)..............2462
43.3.420
IOMUXC_SW_PAD_CTL_PAD_SD2_CMD (IOMUXC_SW_PAD_CTL_PAD_SD2_CMD)............2464
43.3.421
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3)....2466
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Section Number
Title
Page
43.3.422
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2)....2468
43.3.423
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1)....2470
43.3.424
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0)....2472
43.3.425
IOMUXC_SW_PAD_CTL_PAD_NVCC_SD2 (IOMUXC_SW_PAD_CTL_PAD_NVCC_SD2)........2474
43.3.426
IOMUXC_SW_PAD_CTL_PAD_GPIO_0 (IOMUXC_SW_PAD_CTL_PAD_GPIO_0)......................2475
43.3.427
IOMUXC_SW_PAD_CTL_PAD_GPIO_1 (IOMUXC_SW_PAD_CTL_PAD_GPIO_1)......................2477
43.3.428
IOMUXC_SW_PAD_CTL_PAD_GPIO_9 (IOMUXC_SW_PAD_CTL_PAD_GPIO_9)......................2479
43.3.429
IOMUXC_SW_PAD_CTL_PAD_GPIO_3 (IOMUXC_SW_PAD_CTL_PAD_GPIO_3)......................2481
43.3.430
IOMUXC_SW_PAD_CTL_PAD_GPIO_6 (IOMUXC_SW_PAD_CTL_PAD_GPIO_6)......................2483
43.3.431
IOMUXC_SW_PAD_CTL_PAD_GPIO_2 (IOMUXC_SW_PAD_CTL_PAD_GPIO_2)......................2485
43.3.432
IOMUXC_SW_PAD_CTL_PAD_GPIO_4 (IOMUXC_SW_PAD_CTL_PAD_GPIO_4)......................2487
43.3.433
IOMUXC_SW_PAD_CTL_PAD_GPIO_5 (IOMUXC_SW_PAD_CTL_PAD_GPIO_5)......................2489
43.3.434
IOMUXC_SW_PAD_CTL_PAD_GPIO_7 (IOMUXC_SW_PAD_CTL_PAD_GPIO_7)......................2491
43.3.435
IOMUXC_SW_PAD_CTL_PAD_GPIO_8 (IOMUXC_SW_PAD_CTL_PAD_GPIO_8)......................2493
43.3.436
IOMUXC_SW_PAD_CTL_PAD_GPIO_16 (IOMUXC_SW_PAD_CTL_PAD_GPIO_16)..................2495
43.3.437
IOMUXC_SW_PAD_CTL_PAD_GPIO_17 (IOMUXC_SW_PAD_CTL_PAD_GPIO_17)..................2497
43.3.438
IOMUXC_SW_PAD_CTL_PAD_GPIO_18 (IOMUXC_SW_PAD_CTL_PAD_GPIO_18)..................2499
43.3.439
IOMUXC_SW_PAD_CTL_PAD_NVCC_GPIO (IOMUXC_SW_PAD_CTL_PAD_NVCC_GPIO)....2501
43.3.440
IOMUXC_SW_PAD_CTL_PAD_POR_B (IOMUXC_SW_PAD_CTL_PAD_POR_B)........................2502
43.3.441
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1
(IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1)...............................................................................2504
43.3.442
IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B (IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B). .2506
43.3.443
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0
(IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0)...............................................................................2508
43.3.444
IOMUXC_SW_PAD_CTL_PAD_TEST_MODE (IOMUXC_SW_PAD_CTL_PAD_TEST_MODE)..2510
43.3.445
IOMUXC_SW_PAD_CTL_GRP_ADDDS (IOMUXC_SW_PAD_CTL_GRP_ADDDS).....................2511
43.3.446
IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL)............................................................................2512
43.3.447
IOMUXC_SW_PAD_CTL_GRP_DDRPKE (IOMUXC_SW_PAD_CTL_GRP_DDRPKE).................2513
43.3.448
IOMUXC_SW_PAD_CTL_GRP_DDRPK (IOMUXC_SW_PAD_CTL_GRP_DDRPK)......................2513
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Section Number
Title
Page
43.3.449
IOMUXC_SW_PAD_CTL_GRP_DDRHYS (IOMUXC_SW_PAD_CTL_GRP_DDRHYS)................2514
43.3.450
IOMUXC_SW_PAD_CTL_GRP_DDRMODE (IOMUXC_SW_PAD_CTL_GRP_DDRMODE)........2515
43.3.451
IOMUXC_SW_PAD_CTL_GRP_B0DS (IOMUXC_SW_PAD_CTL_GRP_B0DS).............................2515
43.3.452
IOMUXC_SW_PAD_CTL_GRP_B1DS (IOMUXC_SW_PAD_CTL_GRP_B1DS).............................2516
43.3.453
IOMUXC_SW_PAD_CTL_GRP_CTLDS (IOMUXC_SW_PAD_CTL_GRP_CTLDS)........................2516
43.3.454
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE (IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE)........2517
43.3.455
IOMUXC_SW_PAD_CTL_GRP_B2DS (IOMUXC_SW_PAD_CTL_GRP_B2DS).............................2518
43.3.456
IOMUXC_SW_PAD_CTL_GRP_B3DS (IOMUXC_SW_PAD_CTL_GRP_B3DS).............................2518
43.3.457
IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT).......................................................2519
43.3.458
IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT).......................................................2519
43.3.459
IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT)...............................................2520
43.3.460
IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT)...................................................2520
43.3.461
IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT)................................................2521
43.3.462
IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT)...................................................2521
43.3.463
IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT).......................................................2522
43.3.464
IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT).......................................................2522
43.3.465
IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT)...............................................2523
43.3.466
IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT)...................................................2523
43.3.467
IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT)................................................2524
43.3.468
IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT
(IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT)...................................................2524
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Section Number
43.3.469
Title
Page
IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT
(IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT).....................................................................2525
43.3.470
IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT
(IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT).....................................................................2525
43.3.471
IOMUXC_CCM_IPP_ASRC_EXT_SELECT_INPUT
(IOMUXC_CCM_IPP_ASRC_EXT_SELECT_INPUT).........................................................................2526
43.3.472
IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT
(IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT).............................................................................2526
43.3.473
IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT
(IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT).................................................................2527
43.3.474
IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT
(IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT).................................................................2527
43.3.475
IOMUXC_CCM_PLL3_BYPASS_CLK_SELECT_INPUT
(IOMUXC_CCM_PLL3_BYPASS_CLK_SELECT_INPUT).................................................................2528
43.3.476
IOMUXC_CCM_PLL4_BYPASS_CLK_SELECT_INPUT
(IOMUXC_CCM_PLL4_BYPASS_CLK_SELECT_INPUT).................................................................2528
43.3.477
IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
(IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT).....................................................................2529
43.3.478
IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
(IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT)...........................................................................2529
43.3.479
IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
(IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT)...........................................................................2530
43.3.480
IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT
(IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT)..........................................................................2531
43.3.481
IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
(IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT)..........................................................................2531
43.3.482
IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
(IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT)..........................................................................2532
43.3.483
IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT
(IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT)..........................................................................2532
43.3.484
IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT).................................................................2533
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Section Number
43.3.485
Title
Page
IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT).......................................................................2533
43.3.486
IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT).......................................................................2534
43.3.487
IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT)...................................................................2535
43.3.488
IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT)...................................................................2535
43.3.489
IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT)...................................................................2536
43.3.490
IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT
(IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT)...................................................................2536
43.3.491
IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT
(IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT).................................................................2537
43.3.492
IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT
(IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT).......................................................................2537
43.3.493
IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT
(IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT).......................................................................2538
43.3.494
IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT
(IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT)...................................................................2538
43.3.495
IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT
(IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT)...................................................................2539
43.3.496
IOMUXC_ESAI1_IPP_IND_FSR_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_FSR_SELECT_INPUT)...........................................................................2539
43.3.497
IOMUXC_ESAI1_IPP_IND_FST_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_FST_SELECT_INPUT)............................................................................2540
43.3.498
IOMUXC_ESAI1_IPP_IND_HCKR_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_HCKR_SELECT_INPUT).......................................................................2540
43.3.499
IOMUXC_ESAI1_IPP_IND_HCKT_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_HCKT_SELECT_INPUT)........................................................................2541
43.3.500
IOMUXC_ESAI1_IPP_IND_SCKR_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SCKR_SELECT_INPUT)........................................................................2541
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Section Number
43.3.501
Title
Page
IOMUXC_ESAI1_IPP_IND_SCKT_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SCKT_SELECT_INPUT)........................................................................2542
43.3.502
IOMUXC_ESAI1_IPP_IND_SDO0_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SDO0_SELECT_INPUT).........................................................................2542
43.3.503
IOMUXC_ESAI1_IPP_IND_SDO1_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SDO1_SELECT_INPUT).........................................................................2543
43.3.504
IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT)..............................................................2543
43.3.505
IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT)..............................................................2544
43.3.506
IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT)..............................................................2544
43.3.507
IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT
(IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT)..............................................................2545
43.3.508
IOMUXC_ESDHC1_IPP_WP_ON_SELECT_INPUT
(IOMUXC_ESDHC1_IPP_WP_ON_SELECT_INPUT)..........................................................................2545
43.3.509
IOMUXC_FEC_FEC_COL_SELECT_INPUT (IOMUXC_FEC_FEC_COL_SELECT_INPUT).........2546
43.3.510
IOMUXC_FEC_FEC_MDI_SELECT_INPUT (IOMUXC_FEC_FEC_MDI_SELECT_INPUT)..........2546
43.3.511
IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT
(IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT)..............................................................................2547
43.3.512
IOMUXC_FIRI_IPP_IND_RXD_SELECT_INPUT
(IOMUXC_FIRI_IPP_IND_RXD_SELECT_INPUT).............................................................................2547
43.3.513
IOMUXC_GPC_PMIC_RDY_SELECT_INPUT (IOMUXC_GPC_PMIC_RDY_SELECT_INPUT)...2548
43.3.514
IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT (IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT) 2548
43.3.515
IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT
(IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT)................................................................................2549
43.3.516
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT (IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT) 2549
43.3.517
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
(IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT)................................................................................2550
43.3.518
IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT (IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT) 2550
43.3.519
IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT
(IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT)................................................................................2551
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Section Number
43.3.520
Title
Page
IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT
(IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT).....................................................2551
43.3.521
IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT
(IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT).....................................................2552
43.3.522
IOMUXC_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT
(IOMUXC_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT).......................................................2552
43.3.523
IOMUXC_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT
(IOMUXC_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT)............................................................2553
43.3.524
IOMUXC_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT
(IOMUXC_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT)............................................................2553
43.3.525
IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
(IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT)..........................................................................2554
43.3.526
IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
(IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT)..........................................................................2554
43.3.527
IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
(IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT)..........................................................................2555
43.3.528
IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
(IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT).........................................................................2555
43.3.529
IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
(IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT).........................................................................2556
43.3.530
IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
(IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT).........................................................................2556
43.3.531
IOMUXC_MLB_MLBCLK_IN_SELECT_INPUT
(IOMUXC_MLB_MLBCLK_IN_SELECT_INPUT)...............................................................................2557
43.3.532
IOMUXC_MLB_MLBDAT_IN_SELECT_INPUT
(IOMUXC_MLB_MLBDAT_IN_SELECT_INPUT)...............................................................................2557
43.3.533
IOMUXC_MLB_MLBSIG_IN_SELECT_INPUT
(IOMUXC_MLB_MLBSIG_IN_SELECT_INPUT)................................................................................2558
43.3.534
IOMUXC_OWIRE_BATTERY_LINE_IN_SELECT_INPUT
(IOMUXC_OWIRE_BATTERY_LINE_IN_SELECT_INPUT).............................................................2558
43.3.535
IOMUXC_SDMA_EVENTS_14_SELECT_INPUT
(IOMUXC_SDMA_EVENTS_14_SELECT_INPUT).............................................................................2559
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Section Number
43.3.536
Title
Page
IOMUXC_SDMA_EVENTS_15_SELECT_INPUT
(IOMUXC_SDMA_EVENTS_15_SELECT_INPUT).............................................................................2559
43.3.537
IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT
(IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT)................................................................................2560
43.3.538
IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
(IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT).................................................................2560
43.3.539
IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
(IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT).........................................................2561
43.3.540
IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
(IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT).................................................................2561
43.3.541
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
(IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT).........................................................2562
43.3.542
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
(IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT).................................................................2562
43.3.543
IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
(IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT).........................................................2563
43.3.544
IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT
(IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT).................................................................2564
43.3.545
IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
(IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT).........................................................2564
43.3.546
IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
(IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT).................................................................2565
43.3.547
IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
(IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT).........................................................2565
43.3.548
IOMUXC_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT
(IOMUXC_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT)..............................................................2566
43.3.549
IOMUXC_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT
(IOMUXC_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT)...............................................................2566
43.3.550
IOMUXC_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT
(IOMUXC_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT)...............................................................2567
43.4
Functional Description..................................................................................................................................................2567
43.4.1
ALT6 and ALT7 Extended Muxing Modes...............................................................................................2570
43.4.2
SW Loopback through SION Bit...............................................................................................................2570
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Section Number
Title
Page
43.4.3
Daisy Chain - Multi Pads Driving same Block Input Pin..........................................................................2570
43.4.4
Interrupts....................................................................................................................................................2572
Chapter 44
IEEE 1588 Precision Time Protocol Assist (IPTP)
44.1
Introduction...................................................................................................................................................................2573
44.2
IPTP Block Diagram.....................................................................................................................................................2574
44.3
Time Stamp Unit (TSU) Key Features.........................................................................................................................2575
44.4
IPTP Real Time Clock (RTC) Key Features................................................................................................................2576
44.5
IPTP Implementation Assumptions..............................................................................................................................2577
44.6
Modes of Operation......................................................................................................................................................2577
44.7
Time Stamp Unit (TSU)................................................................................................................................................2578
44.7.1
44.8
44.9
PTP Event Interrupts..................................................................................................................................2579
IPTP Real Time Clock (RTC).......................................................................................................................................2580
44.8.1
RTC Clock Sources....................................................................................................................................2582
44.8.2
Prescale Output Clock and Pulse per Second Edge Alignment.................................................................2583
PTP Frame Reception...................................................................................................................................................2583
44.9.1
Out-of-Band Mode.....................................................................................................................................2583
44.10 PTP Frame Transmission..............................................................................................................................................2584
44.11 Cycle Delay from Time Stamp Location......................................................................................................................2584
44.12 Initialization Sequence .................................................................................................................................................2584
44.12.1
RTC Mode Registers..................................................................................................................................2584
44.12.1.1
Enable Sequence....................................................................................................................2585
44.13 Programmable Registers...............................................................................................................................................2585
44.13.1
Timer Control Register (IPTP_TMR_CTRL)............................................................................................2588
44.13.2
Timer Events Register (IPTP_TMR_TEVENT)........................................................................................2590
44.13.3
Timer Mask Register (IPTP_TMR_TEMASK).........................................................................................2592
44.13.4
Timer Counter Low Register (IPTP_TMR_CNT_L)................................................................................2593
44.13.5
Timer Counter High Register (IPTP_TMR_CNT_H)...............................................................................2594
44.13.6
Timer Addend Register (IPTP_TMR_ADD).............................................................................................2595
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Section Number
Title
Page
44.13.7
Timer Accumulator Register (IPTP_TMR_ACC).....................................................................................2596
44.13.8
Timer Prescale Register (IPTP_TMR_PRSC)...........................................................................................2596
44.13.9
Timer Offset Low Register (IPTP_TMR_OFF_L)....................................................................................2597
44.13.10
Timer Offset High Register (IPTP_TMR_OFF_H)...................................................................................2597
44.13.11
Alarm 1 Time Low Register (IPTP_TMR_ALARM1_L).........................................................................2598
44.13.12
Alarm 1 Time High Register (IPTP_TMR_ALARM1_H)........................................................................2598
44.13.13
Alarm 2 Time Low Register (IPTP_TMR_ALARM2_L).........................................................................2599
44.13.14
Alarm 2 Time High Register (IPTP_TMR_ALARM2_H)........................................................................2599
44.13.15
Timer Fixed Interval Period 1 Regtister (IPTP_TMR_FIPER1)...............................................................2600
44.13.16
Timer Fixed Interval Period 2 Regtister (IPTP_TMR_FIPER2)...............................................................2601
44.13.17
Timer Fixed Interval Period 3 Regtister (IPTP_TMR_FIPER3)...............................................................2602
44.13.18
External Trigger Time Stamp 1 Low Register (IPTP_TMR_ETTS1_L)..................................................2603
44.13.19
External Trigger Time Stamp 1 High Register (IPTP_TMR_ETTS1_H).................................................2603
44.13.20
External Trigger Time Stamp 2 Low Register (IPTP_TMR_ETTS2_L)..................................................2604
44.13.21
External Trigger Time Stamp 2 High Register (IPTP_TMR_ETTS2_H).................................................2604
44.13.22
FIPER Start Low Register (IPTP_TMR_FSV_L).....................................................................................2605
44.13.23
FIPER Start High Register (IPTP_TMR_FSV_H)....................................................................................2605
44.13.24
Time Stamp Unit Parsing Definitons Register 1 (IPTP_PTP_TSPDR1)..................................................2605
44.13.25
Time Stamp Unit Parsing Definitons Register 2 (IPTP_PTP_TSPDR2)..................................................2606
44.13.26
Time Stamp Unit Parsing Definitons Register 3 (IPTP_PTP_TSPDR3)..................................................2607
44.13.27
Time Stamp Unit Parsing Definitons Register 4 (IPTP_PTP_TSPDR4)..................................................2608
44.13.28
Time Stamp Unit Parsing Offset Values (IPTP_PTP_TSPOV)................................................................2609
44.13.29
Time Stamp Unit Mode Register (IPTP_PTP_TSMR)..............................................................................2611
44.13.30
Timer PTP Event Register (IPTP_PTP_TMR_PEVENT).........................................................................2613
44.13.31
Timer PTP Mask Register (IPTP_PTP_TMR_PEMASK)........................................................................2616
44.13.32
Timer Stamp Unit Receiver TIme High (IPTP_TMR_UC_RXTS_H).....................................................2618
44.13.33
Timer Stamp Unit Receiver TIme Low (IPTP_TMR_UC_RXTS_L).......................................................2619
44.13.34
Time Stamp Unit Transmitter Time High (IPTP_TMR_UC_TXTS_H)...................................................2619
44.13.35
Time Stamp Unit Transmitter Time Low (IPTP_TMR_UC_TXTS_L)....................................................2620
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Page
44.13.36
Time Stamp Unit Parsing Definitons Register 5 (IPTP_PTP_TSPDR5)..................................................2620
44.13.37
Time Stamp Unit Parsing Definitons Register 6 (IPTP_PTP_TSPDR6)..................................................2621
44.13.38
Time Stamp Unit Parsing Definitons Register 7 (IPTP_PTP_TSPDR7)..................................................2622
44.13.39
1588_ACC_PTP_Event Register (IPTP_1588_ACC_PTP_Event)...........................................................2623
44.13.40
1588_ACC_PTP_Mask Register (IPTP_1588_ACC_PTP_Mask)...........................................................2626
Chapter 45
Image Processing Unit (IPU)
45.1
Overview.......................................................................................................................................................................2629
45.2
Architecture...................................................................................................................................................................2630
45.3
Features And Functionality...........................................................................................................................................2631
45.3.1
External Ports.............................................................................................................................................2631
45.3.1.1
Camera Ports..........................................................................................................................2631
45.3.1.2
Display Ports..........................................................................................................................2634
45.3.1.2.1
45.3.1.3
Memory Port..........................................................................................................................2638
45.3.1.4
Processing..............................................................................................................................2640
45.3.1.5
45.3.1.6
45.4
Access Modes.................................................................................................2634
45.3.1.4.1
Processing flows.............................................................................................2640
45.3.1.4.2
Display Processor (DP)...................................................................................2642
Video De-Interlacer or Combiner (VDIC)Video De-Interlacer (VDI)..................................2643
45.3.1.5.1
De interlacing in the VDIC.............................................................................2643
45.3.1.5.2
Combining in the VDIC..................................................................................2644
45.3.1.5.3
Image Converter (IC)......................................................................................2644
45.3.1.5.4
Image Rotator (IRT).......................................................................................2645
Automatic Procedures............................................................................................................2645
45.3.1.6.1
Screen Refresh................................................................................................2646
45.3.1.6.2
Update Of The Display Buffer........................................................................2646
45.3.1.6.3
Camera Preview..............................................................................................2647
Functional Description..................................................................................................................................................2647
45.4.1
IPU detailed block diagram........................................................................................................................2647
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Section Number
45.4.2
Title
Image DMA Controller (IDMAC).............................................................................................................2649
45.4.2.1
IDMAC's channels ................................................................................................................2651
45.4.2.2
IBIW & IBIR - Internal bus interface for write and read.......................................................2653
45.4.2.3
FCW & FCR - Format converter write and read...................................................................2653
45.4.2.4
Buffering units.......................................................................................................................2656
45.4.2.4.1
Handling real time channels............................................................................2657
45.4.2.5
AXIW - AXI Write and AXIR - AXI Read...........................................................................2657
45.4.2.6
CC_W & CC_R - Channel Control Write and Read.............................................................2657
45.4.2.6.1
45.4.2.7
45.4.2.8
Locking the arbitration and reordering the AXI bursts...................................2658
AAU_W & AAU_R- Address Arithmetic Unit for Write and Read.....................................2659
45.4.2.7.1
Scrolling support.............................................................................................2661
ATC - Alpha Transparency Controller..................................................................................2661
45.4.2.8.1
Conditional read..............................................................................................2663
45.4.2.9
LUT- Look Up Table.............................................................................................................2663
45.4.2.10
CPMEM - Channel Parameter Memory.................................................................................2664
45.4.2.11
45.4.3
Page
45.4.2.10.1
CPMEM's words' structure for non interleaved mode....................................2665
45.4.2.10.2
CPMEM's words' structure for interleaved mode...........................................2670
45.4.2.10.3
Accessing the CPMEM for programming......................................................2679
45.4.2.10.4
Alternate IDMAC settings..............................................................................2680
IDMAC's modes of operation................................................................................................2680
45.4.2.11.1
Rotation modes...............................................................................................2680
45.4.2.11.2
Frame size.......................................................................................................2681
45.4.2.12
IDMAC's restriction...............................................................................................................2683
45.4.2.13
IDMAC's Endianness support................................................................................................2683
45.4.2.14
IDMAC's internal events........................................................................................................2684
Camera Sensor Interface (CSI)..................................................................................................................2684
45.4.3.1
CSI Block Diagram................................................................................................................2684
45.4.3.2
CSI Interface..........................................................................................................................2685
45.4.3.2.1
Parallel interface.............................................................................................2685
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Section Number
45.4.4
45.4.5
45.4.6
Title
Page
45.4.3.3
TEST MODE.........................................................................................................................2686
45.4.3.4
Sensor Image Frame Relations..............................................................................................2687
45.4.3.5
Timing/Data mode protocols.................................................................................................2688
45.4.3.5.1
gated mode......................................................................................................2688
45.4.3.5.2
non-gated mode...............................................................................................2689
45.4.3.5.3
BT.656 mode...................................................................................................2689
45.4.3.5.4
BT.1120 mode.................................................................................................2690
45.4.3.6
Packing to memory................................................................................................................2691
45.4.3.7
Skipping frames.....................................................................................................................2692
45.4.3.8
16 bit camera support.............................................................................................................2692
45.4.3.9
CSI Restrictions.....................................................................................................................2693
Sensor Multi FIFO Controller (SMFC).....................................................................................................2693
45.4.4.1
SMFC's Features....................................................................................................................2694
45.4.4.2
SMFC's Functional description..............................................................................................2694
45.4.4.2.1
SMFC Master interface...................................................................................2696
45.4.4.2.2
Restrictions.....................................................................................................2697
Image Converter ........................................................................................................................................2697
45.4.5.1
IC Block Diagram..................................................................................................................2697
45.4.5.2
Processing tasks.....................................................................................................................2698
45.4.5.3
Downsizing Section...............................................................................................................2700
45.4.5.4
Main Processing Section........................................................................................................2701
45.4.5.5
Rotation Section.....................................................................................................................2704
45.4.5.6
IC Task Parameter Memory...................................................................................................2706
45.4.5.7
IC's DMA channels................................................................................................................2711
45.4.5.8
IC restrictions.........................................................................................................................2711
45.4.5.9
IC bridge................................................................................................................................2711
Display port................................................................................................................................................2712
45.4.6.1
Display ports channels...........................................................................................................2713
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Section Number
45.4.6.2
Page
Supported display interfaces..................................................................................................2714
45.4.6.2.1
Synchronous Interfaces...................................................................................2714
45.4.6.2.2
Asynchronous Parallel Interfaces...................................................................2715
45.4.6.2.3
Asynchronous Serial Interfaces......................................................................2715
45.4.6.3
Display port's bandwidth........................................................................................................2715
45.4.6.4
Display Dual Mode................................................................................................................2716
45.4.6.5
Display Errors .......................................................................................................................2716
45.4.6.6
45.4.7
Title
45.4.6.5.1
Data starvation errors......................................................................................2716
45.4.6.5.2
Anti tearing errors...........................................................................................2717
Display port's restrictions.......................................................................................................2717
DC - Display Controller.............................................................................................................................2718
45.4.7.1
45.4.7.2
45.4.7.3
45.4.7.4
Channels flow control............................................................................................................2720
45.4.7.1.1
New Frame control.........................................................................................2720
45.4.7.1.2
Antitearing control..........................................................................................2720
45.4.7.1.3
User command mode control..........................................................................2721
Arbitration Unit......................................................................................................................2721
45.4.7.2.1
Access request generator.................................................................................2721
45.4.7.2.2
DI arbiter.........................................................................................................2721
45.4.7.2.3
Source arbiter..................................................................................................2721
Microcode processing unit.....................................................................................................2722
45.4.7.3.1
Channels address control................................................................................2722
45.4.7.3.2
General purpose Data oriented events counters..............................................2722
45.4.7.3.3
Microcode address generator..........................................................................2722
45.4.7.3.4
Template's Memory Access Arbiter...............................................................2723
DC's Template structure.........................................................................................................2723
45.4.7.4.1
45.4.7.5
DC template's memory map............................................................................2723
Display controls' generator.....................................................................................................2734
45.4.7.5.1
Bus Mapping Unit...........................................................................................2734
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Section Number
45.4.8
DP and DC read channels......................................................................................................2741
45.4.8.1.1
FIFO allocation to channels............................................................................2741
45.4.8.1.2
Arbitration between channels.........................................................................2742
45.4.8.1.3
Watermark.......................................................................................................2742
45.4.8.2
IC interface.............................................................................................................................2743
45.4.8.3
DC write channel and AHB accesses.....................................................................................2743
DP - Display Processor..............................................................................................................................2743
45.4.9.1
The DP programming model..................................................................................................2744
45.4.9.2
Displayed Planes....................................................................................................................2744
45.4.9.3
Combining Unit......................................................................................................................2745
45.4.9.4
Cursor Generator....................................................................................................................2746
45.4.9.5
Color Space Conversion unit - CSC......................................................................................2746
45.4.9.5.1
45.4.10
Page
DMFC - Display Multi FIFO Controller....................................................................................................2740
45.4.8.1
45.4.9
Title
Gamut mapping...............................................................................................2748
45.4.9.6
Gamma correction..................................................................................................................2749
45.4.9.7
DC interface...........................................................................................................................2750
45.4.9.8
DP's flows management.........................................................................................................2751
45.4.9.9
DP debug unit.........................................................................................................................2753
45.4.9.10
Restriction..............................................................................................................................2753
Display Interface (DI)................................................................................................................................2753
45.4.10.1
DC interface, data accumulator and clock domain synchronizer...........................................2755
45.4.10.2
Parallel interface data synchronizer and data oriented interface............................................2755
45.4.10.3
Timing generator....................................................................................................................2755
45.4.10.4
45.4.10.3.1
Waveform concatenation................................................................................2757
45.4.10.3.2
The basic counter............................................................................................2758
45.4.10.3.3
Counter number 9...........................................................................................2761
45.4.10.3.4
DI's active window..........................................................................................2761
Waveform settings for asynchronous interface pins..............................................................2762
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Section Number
45.4.10.5
Title
Serial display interface...........................................................................................................2764
45.4.10.5.1
45.4.11
45.4.12
Page
Waveform settings for serial interface pins....................................................2765
45.4.10.6
Low Level Access - LLA.......................................................................................................2768
45.4.10.7
Using a mask channel............................................................................................................2768
Video De Interlacing or Combining Block (VDIC)...................................................................................2768
45.4.11.1
VDIC FeaturesVDI Features..................................................................................................2771
45.4.11.2
De interlacer (DI) sub-block..................................................................................................2771
45.4.11.2.1
Vertical Filter Block (di_vfilt)........................................................................2771
45.4.11.2.2
Motion Calculator Block (di_mcalc)..............................................................2772
45.4.11.2.3
Spatial Motion Filter (di_sfilt)........................................................................2773
45.4.11.2.4
Interpolated Pixel Calculator Block (di_interp)..............................................2773
45.4.11.2.5
Median Filter Block (di_med)........................................................................2773
45.4.11.2.6
Soft Switch Block (di_sswitch)......................................................................2773
45.4.11.3
DMA only Mode....................................................................................................................2774
45.4.11.4
Real Time Mode.....................................................................................................................2774
45.4.11.5
CSI only Mode.......................................................................................................................2774
45.4.11.6
Using Combining in the VDIC .............................................................................................2774
45.4.11.7
VDIC Restrictions .................................................................................................................2775
Control Module (CM)................................................................................................................................2775
45.4.12.1
Block Diagram.......................................................................................................................2776
45.4.12.2
Frame Synchronization Unit..................................................................................................2777
45.4.12.2.1
General Description........................................................................................2777
45.4.12.2.2
Frame Synchronization Flow .........................................................................2777
45.4.12.2.3
FSU's fundamentals........................................................................................2778
45.4.12.2.4
IPU main flows...............................................................................................2781
45.4.12.2.5
Sub-Frame Double-Buffering (Band Mode)...................................................2789
45.4.12.2.6
Snooping.........................................................................................................2790
45.4.12.2.7
Automatic Window Refresh...........................................................................2790
45.4.12.2.8
Auto-refresh and snooping..............................................................................2791
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Section Number
Title
45.4.12.2.9
Page
Synchronization with A Video/Graphics source.............................................2791
45.4.12.3
Interrupt Generator.................................................................................................................2792
45.4.12.4
SDMA event generator..........................................................................................................2799
45.4.12.5
General Configuration Registers............................................................................................2799
45.4.12.6
Shadow Registers Module (SRM).........................................................................................2799
45.4.12.6.1
Switching between 2 flows.............................................................................2800
45.4.12.6.2
Updating parameters between frames.............................................................2800
45.4.12.6.3
Updating the memory.....................................................................................2800
45.4.12.6.4
SRM priority...................................................................................................2802
45.4.12.6.5
SRM entries mapping.....................................................................................2802
45.4.12.7
Memory Access Unit.............................................................................................................2821
45.4.12.8
SISG - Still Image Synchronization Generator......................................................................2821
45.4.12.9
Clock Change procedure........................................................................................................2823
45.4.12.10 Low Power Modes - Stop, PG and LPSR modes...................................................................2824
45.4.12.10.1 STOP Mode....................................................................................................2825
45.4.12.10.2 Power Gating..................................................................................................2826
45.4.12.10.3 Low Power Screen Refresh mode - LPSR......................................................2827
45.4.13
45.5
IPU diagnostics unit...................................................................................................................................2829
Programmable Registers...............................................................................................................................................2833
45.5.1
IPU Memory Map/Register Definition......................................................................................................2833
45.51.1
Configuration Register (IPU_CONF)....................................................................................2855
45.51.2
SISG Control 0 Register (IPU_SISG_CTRL0).....................................................................2858
45.51.3
SISG Control 1 Register (IPU_SISG_CTRL1).....................................................................2859
45.51.4
SISG Set<i> Register (IPU_SISG_SET_i)............................................................................2859
45.51.5
SISG Clear <i> Register (IPU_SISG_CLR_i).......................................................................2860
45.51.6
Interrupt Control Register 1 (IPU_INT_CTRL_1)................................................................2860
45.51.7
Interrupt Control Register 2 (IPU_INT_CTRL_2)................................................................2864
45.51.8
Interrupt Control Register 3 (IPU_INT_CTRL_3)................................................................2867
45.51.9
Interrupt Control Register 4 (IPU_INT_CTRL_4)................................................................2871
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Page
45.51.10
Interrupt Control Register 5 (IPU_INT_CTRL_5)................................................................2873
45.51.11
Interrupt Control Register 6 (IPU_INT_CTRL_6)................................................................2878
45.51.12
Interrupt Control Register 7 (IPU_INT_CTRL_7)................................................................2881
45.51.13
Interrupt Control Register 8 (IPU_INT_CTRL_8)................................................................2883
45.51.14
Interrupt Control Register 9 (IPU_INT_CTRL_9)................................................................2885
45.51.15
Interrupt Control Register 10 (IPU_INT_CTRL_10)............................................................2886
45.51.16
Interrupt Control Register 11 (IPU_INT_CTRL_11)............................................................2889
45.51.17
Interrupt Control Register 12 (IPU_INT_CTRL_12)............................................................2891
45.51.18
Interrupt Control Register 13 (IPU_INT_CTRL_13)............................................................2893
45.51.19
Interrupt Control Register 14 (IPU_INT_CTRL_14)............................................................2897
45.51.20
Interrupt Control Register15 (IPU_INT_CTRL_15).............................................................2900
45.51.21
SDMA Event Control Register 1 (IPU_SDMA_EVENT_1)................................................2904
45.51.22
SDMA Event Control Register 2 (IPU_SDMA_EVENT_2)................................................2908
45.51.23
SDMA Event Control Register 3 (IPU_SDMA_EVENT_3)................................................2910
45.51.24
SDMA Event Control Register 4 (IPU_SDMA_EVENT_4)................................................2915
45.51.25
SDMA Event Control Register 7 (IPU_SDMA_EVENT_7)................................................2918
45.51.26
SDMA Event Control Register 8 (IPU_SDMA_EVENT_8)................................................2920
45.51.27
SDMA Event Control Register 11 (IPU_SDMA_EVENT_11)............................................2921
45.51.28
SDMA Event Control Register 12 (IPU_SDMA_EVENT_12)............................................2924
45.51.29
SDMA Event Control Register 13 (IPU_SDMA_EVENT_13)............................................2926
45.51.30
SDMA Event Control Register 14 (IPU_SDMA_EVENT_14)............................................2930
45.51.31
Shadow Registers Memory Priority 1 Register (IPU_SRM_PRI1).......................................2932
45.51.32
Shadow Registers Memory Priority 2 Register (IPU_SRM_PRI2).......................................2933
45.51.33
FSU Processing Flow 1 Register (IPU_FS_PROC_FLOW1)...............................................2935
45.51.34
FSU Processing Flow 2 Register (IPU_FS_PROC_FLOW2)...............................................2939
45.51.35
FSU Processing Flow 3 Register (IPU_FS_PROC_FLOW3)...............................................2942
45.51.36
FSU Displaying Flow 1 Register (IPU_FS_DISP_FLOW1).................................................2944
45.51.37
FSU Displaying Flow 2 Register (IPU_FS_DISP_FLOW2).................................................2948
45.51.38
SKIP Register (IPU_SKIP)....................................................................................................2950
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Page
45.51.39
Display General Control Register (IPU_DISP_GEN)...........................................................2951
45.51.40
Display Alternate Flow Control Register 1 (IPU_DISP_ALT1)...........................................2954
45.51.41
Display Alternate Flow Control Register 2 (IPU_DISP_ALT2)...........................................2955
45.51.42
Display Alternate Flow Control Register 3 (IPU_DISP_ALT3)...........................................2956
45.51.43
Display Alternate Flow Control Register 4 (IPU_DISP_ALT4)...........................................2958
45.51.44
Autorefresh and Snooping Control Register (IPU_SNOOP).................................................2959
45.51.45
Memory Reset Control Register (IPU_MEM_RST).............................................................2960
45.51.46
Power Modes Control Register (IPU_PM)............................................................................2961
45.51.47
General Purpose Register (IPU_GPR)...................................................................................2964
45.51.48
Channel Double Buffer Mode Select 0 Register (IPU_CH_DB_MODE_SEL0)..................2966
45.51.49
Channel Double Buffer Mode Select 1 Register (IPU_CH_DB_MODE_SEL1)..................2970
45.51.50
Alternate Channel Double Buffer Mode Select 0 Register
(IPU_ALT_CH_DB_MODE_SEL0).....................................................................................2972
45.51.51
Alternate Channel Double Buffer Mode Select1 Register
(IPU_ALT_CH_DB_MODE_SEL1).....................................................................................2974
45.51.52
Alternate Channel Triple Buffer Mode Select 0 Register
(IPU_ALT_CH_TRB_MODE_SEL0)...................................................................................2975
45.51.53
Interrupt Status Register 1 (IPU_INT_STAT_1)...................................................................2978
45.51.54
Interrupt Status Register2 (IPU_INT_STAT_2)....................................................................2982
45.51.55
Interrupt Status Register 3 (IPU_INT_STAT_3)...................................................................2985
45.51.56
Interrupt Status Register 5 (IPU_INT_STAT_5)...................................................................2989
45.51.57
Interrupt Status Register 6 (IPU_INT_STAT_6)...................................................................2994
45.51.58
Interrupt Status Register7 1 (IPU_INT_STAT_7).................................................................2997
45.51.59
Interrupt Status Register 8 (IPU_INT_STAT_8)...................................................................2999
45.51.60
Interrupt Status Register 9 (IPU_INT_STAT_9)...................................................................3001
45.51.61
Interrupt Status Register 10 (IPU_INT_STAT_10)...............................................................3003
45.51.62
Interrupt Status Register 11 (IPU_INT_STAT_11)...............................................................3005
45.51.63
Interrupt Status Register 12 (IPU_INT_STAT_12)...............................................................3009
45.51.64
Interrupt Status Register 13 (IPU_INT_STAT_13)...............................................................3011
45.51.65
Interrupt Status Register 14 (IPU_INT_STAT_14)...............................................................3016
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Title
Page
45.51.66
Interrupt Status Register 15 (IPU_INT_STAT_15)...............................................................3019
45.51.67
Current Buffer Register 0 (IPU_CUR_BUF_0).....................................................................3023
45.51.68
Current Buffer Register 1 (IPU_CUR_BUF_1).....................................................................3027
45.51.69
Alternate Current Buffer Register 0 (IPU_ALT_CUR_0).....................................................3029
45.51.70
Alternate Current Buffer Register 1 (IPU_ALT_CUR_1).....................................................3031
45.51.71
Shadow Registers Memory Status Register (IPU_SRM_STAT)..........................................3033
45.51.72
Processing Status Tasks Register (IPU_PROC_TASKS_STAT)..........................................3035
45.51.73
Display Tasks Status Register (IPU_DISP_TASKS_STAT)................................................3036
45.51.74
Triple Current Buffer Register 0 (IPU_TRIPLE_CUR_BUF_0)..........................................3037
45.51.75
Triple Current Buffer Register 1 (IPU_TRIPLE_CUR_BUF_1)..........................................3039
45.51.76
IPU Channels Buffer 0 Ready 0 Register (IPU_CH_BUF0_RDY0)....................................3041
45.51.77
IPU Channels Buffer 0 Ready 1 Register (IPU_CH_BUF0_RDY1)....................................3044
45.51.78
IPU Channels Buffer 1 Ready 0 Register (IPU_CH_BUF1_RDY0)....................................3046
45.51.79
IPU Channels Buffer 1 Ready 1Register (IPU_CH_BUF1_RDY1).....................................3049
45.51.80
IPU Alternate Channels Buffer 0 Ready 0 Register (IPU_ALT_CH_BUF0_RDY0)...........3052
45.51.81
IPU Alternate Channels Buffer 0 Ready 1 Register (IPU_ALT_CH_BUF0_RDY1)...........3053
45.51.82
IPU Alternate Channels Buffer1 Ready 0 Register (IPU_ALT_CH_BUF1_RDY0)............3054
45.51.83
IPU Alternate Channels Buffer 1 Ready 1 Register (IPU_ALT_CH_BUF1_RDY1)...........3055
45.51.84
IPU Channels Buffer 2 Ready 0 Register (IPU_CH_BUF2_RDY0)....................................3056
45.51.85
IPU Channels Buffer 2 Ready 1 Register (IPU_CH_BUF2_RDY1)....................................3058
45.51.86
Interrupt Status Register 4 (IPU_INT_STAT_4)...................................................................3059
45.51.87
IDMAC Configuration Register (IPU_IDMAC_CONF)......................................................3062
45.51.88
IDMAC Channel Enable 1 Register (IPU_IDMAC_CH_EN_1)..........................................3063
45.51.89
IDMAC Separate Alpha Indication Register (IPU_IDMAC_SEP_ALPHA)........................3067
45.51.90
IDMAC Alternate Separate Alpha Indication Register
(IPU_IDMAC_ALT_SEP_ALPHA).....................................................................................3069
45.51.91
IDMAC Channel Priority 1 Register (IPU_IDMAC_CH_PRI_1)........................................3071
45.51.92
IDMAC Channel Priority 2 Register (IPU_IDMAC_CH_PRI_2)........................................3074
45.51.93
IDMAC Channel Watermark Enable 1 Register (IPU_IDMAC_WM_EN_1)......................3076
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45.51.94
IDMAC Channel Watermark Enable 2 Register (IPU_IDMAC_WM_EN_2)......................3078
45.51.95
IDMAC Channel Lock Enable 1Register (IPU_IDMAC_LOCK_EN_1).............................3079
45.51.96
IDMAC Scroll Coordinations Register 1 (IPU_IDMAC_SC_CORD_1).............................3081
45.51.97
IDMAC Channel Busy 1 Register (IPU_IDMAC_CH_BUSY_1)........................................3082
45.51.98
IDMAC Channel Busy 2 Register (IPU_IDMAC_CH_BUSY_2)........................................3087
45.51.99
DP Debug Control Register (IPU_DP_DEBUG_CNT)........................................................3090
45.51.100
DP Debug Status Register (IPU_DP_DEBUG_STAT).........................................................3091
45.51.101
IC Configuration Register (IPU_IC_CONF).........................................................................3092
45.51.102
IC Preprocessing Encoder Resizing Coefficients Register (IPU_IC_PRP_ENC_RSC).......3095
45.51.103
IC Preprocessing View-Finder Resizing Coefficients Register (IPU_IC_PRP_VF_RSC)...3096
45.51.104
IC Postprocessing Encoder Resizing Coefficients Register (IPU_IC_PP_RSC)..................3097
45.51.105
IC Combining Parameters Register 1 (IPU_IC_CMBP_1)...................................................3098
45.51.106
IC Combining Parameters Register 2 (IPU_IC_CMBP_2)...................................................3098
45.51.107
IC IDMAC Parameters 1 Register (IPU_IC_IDMAC_1)......................................................3099
45.51.108
IC IDMAC Parameters 2 Register (IPU_IC_IDMAC_2)......................................................3102
45.51.109
IC IDMAC Parameters 3Register (IPU_IC_IDMAC_3).......................................................3103
45.51.110
IC IDMAC Parameters 4 Register (IPU_IC_IDMAC_4)......................................................3103
45.51.111
CSI0 Sensor Configuration Register (IPU_CSI0_SENS_CONF).........................................3104
45.51.112
CSI0 Sense Frame Size Register (IPU_CSI0_SENS_FRM_SIZE).......................................3107
45.51.113
CSI0 Actual Frame Size Register (IPU_CSI0_ACT_FRM_SIZE).......................................3107
45.51.114
CSI0 Output Control Register (IPU_CSI0_OUT_FRM_CTRL)...........................................3108
45.51.115
CSIO Test Control Register (IPU_CSI0_TST_CTRL).........................................................3109
45.51.116
CSIO CCIR Code Register 1 (IPU_CSI0_CCIR_CODE_1).................................................3110
45.51.117
CSIO CCIR Code Register 2 (IPU_CSI0_CCIR_CODE_2).................................................3111
45.51.118
CSIO CCIR Code Register 3 (IPU_CSI0_CCIR_CODE_3).................................................3112
45.51.119
CSI0 Data Identifier Register (IPU_CSI0_DI)......................................................................3112
45.51.120
CSI0 SKIP Register (IPU_CSI0_SKIP)................................................................................3113
45.51.121
CSI0 Compander Control Register (IPU_CSIO_CPD_CTRL).............................................3114
45.51.122
CSI0 Red Component Compander Constants Register <i> (IPU_CSIO_CPD_RC_i)..........3115
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45.51.123
CSI0 Red Component Compander SLOPE Register <i> (IPU_CSIO_CPD_RS_i)..............3116
45.51.124
CSI0 GR Component Compander Constants Register <i> (IPU_CSIO_CPD_GRC_i)........3116
45.51.125
CSI0 GR Component Compander SLOPE Register <i> (IPU_CSIO_CPD_GRS_i)............3117
45.51.126
CSI0 GB Component Compander Constants Register <i> (IPU_CSIO_CPD_GBC_i)........3118
45.51.127
CSI0 GB Component Compander SLOPE Register <i> (IPU_CSIO_CPD_GBS_i)............3118
45.51.128
CSI0 Blue Component Compander Constants Register <i> (IPU_CSIO_CPD_BC_i)........3119
45.51.129
CSI0 Blue Component Compander SLOPE Register <i> (IPU_CSIO_CPD_BS_i)............3120
45.51.130
CSI0 Compander Offset Register 1 (IPU_CSI0_CPD_OFFSET1).......................................3120
45.51.131
CSI0 Compander Offset Register 2 (IPU_CSI0_CPD_OFFSET2).......................................3121
45.51.132
CSI1 Sensor Configuration Register (IPU_CSI1_SENS_CONF).........................................3122
45.51.133
CSI1 Sense Frame Size Register (IPU_CSI1_SENS_FRM_SIZE).......................................3124
45.51.134
CSI1 Actual Frame Size Register (IPU_CSI1_ACT_FRM_SIZE).......................................3125
45.51.135
CSI1 Output Control Register (IPU_CSI1_OUT_FRM_CTRL)...........................................3126
45.51.136
CSI1 Test Control Register (IPU_CSI1_TST_CTRL)..........................................................3127
45.51.137
CSI1 CCIR Code Register 1 (IPU_CSI1_CCIR_CODE_1)..................................................3128
45.51.138
CSI1 CCIR Code Register 2 (IPU_CSI1_CCIR_CODE_2)..................................................3129
45.51.139
CSI1 CCIR Code Register 3 (IPU_CSI1_CCIR_CODE_3)..................................................3130
45.51.140
CSI1 Data Identifier Register (IPU_CSI1_DI)......................................................................3130
45.51.141
CSI1 SKIP Register (IPU_CSI1_SKIP)................................................................................3131
45.51.142
CSI1 Compander Control Register (IPU_CSI1_CPD_CTRL)..............................................3132
45.51.143
CSI1 Red Component Compander Constants Register <i> (IPU_CSI1_CPD_RC_i)..........3133
45.51.144
CSI1 Red Component Compander SLOPE Register <i> (IPU_CSI1_CPD_RS_i)..............3133
45.51.145
CSI1 GR Component Compander Constants Register <i> (IPU_CSI1_CPD_GRC_i)........3134
45.51.146
CSI1 GR Component Compander SLOPE Register <i> (IPU_CSI1_CPD_GRS_i)............3135
45.51.147
CSI1 GB Component Compander Constants Register <i> (IPU_CSI1_CPD_GBC_i)........3135
45.51.148
CSI1 GB Component Compander SLOPE Register <i> (IPU_CSI1_CPD_GBS_i)............3136
45.51.149
CSI1 Blue Component Compander Constants Register <i> (IPU_CSI1_CPD_BC_i).........3137
45.51.150
CSI1 Blue Component Compander SLOPE Register <i> (IPU_CSI1_CPD_BS_i).............3137
45.51.151
CSI1 Compander Offset Register 1 (IPU_CSI1_CPD_OFFSET1).......................................3138
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45.51.152
CSI1 Compander Offset Register 2 (IPU_CSI1_CPD_OFFSET2).......................................3139
45.51.153
DI0 General Register (IPU_DI0_GENERAL)......................................................................3140
45.51.154
DI0 Base Sync Clock Gen 0 Register (IPU_DI0_BS_CLKGEN0).......................................3142
45.51.155
DI0 Base Sync Clock Gen 1 Register (IPU_DI0_BS_CLKGEN1).......................................3143
45.51.156
DI0 Sync Wave Gen 1 Register 0 (IPU_DI0_SW_GEN0_1)................................................3143
45.51.157
DI0 Sync Wave Gen 2 Register 0 (IPU_DI0_SW_GEN0_2)................................................3145
45.51.158
DI0 Sync Wave Gen 3 Register 0 (IPU_DI0_SW_GEN0_3)................................................3146
45.51.159
DI0 Sync Wave Gen 4 Register 0 (IPU_DI0_SW_GEN0_4)................................................3147
45.51.160
DI0 Sync Wave Gen 5 Register 0 (IPU_DI0_SW_GEN0_5)................................................3149
45.51.161
DI0 Sync Wave Gen 6 Register 0 (IPU_DI0_SW_GEN0_6)................................................3150
45.51.162
DI0 Sync Wave Gen 7 Register 0 (IPU_DI0_SW_GEN0_7)................................................3151
45.51.163
DI0 Sync Wave Gen 8 Register 0 (IPU_DI0_SW_GEN0_8)................................................3152
45.51.164
DI0 Sync Wave Gen 9 Register 0 (IPU_DI0_SW_GEN0_9)................................................3154
45.51.165
DI0 Sync Wave Gen 1 Register 1 (IPU_DI0_SW_GEN1_1)................................................3155
45.51.166
DI0 Sync Wave Gen 2 Register 1 (IPU_DI0_SW_GEN1_2)................................................3157
45.51.167
DI0 Sync Wave Gen 3 Register 1 (IPU_DI0_SW_GEN1_3)................................................3159
45.51.168
DI0 Sync Wave Gen 4 Register 1 (IPU_DI0_SW_GEN1_4)................................................3161
45.51.169
DI0 Sync Wave Gen 5 Register 1 (IPU_DI0_SW_GEN1_5)................................................3163
45.51.170
DI0 Sync Wave Gen 6 Register 1 (IPU_DI0_SW_GEN1_6)................................................3165
45.51.171
DI0 Sync Wave Gen 7 Register 1 (IPU_DI0_SW_GEN1_7)................................................3167
45.51.172
DI0 Sync Wave Gen 8 Register 1 (IPU_DI0_SW_GEN1_8)................................................3169
45.51.173
DI0 Sync Wave Gen 9 Register 1 (IPU_DI0_SW_GEN1_9)................................................3171
45.51.174
DI0 Sync Assistance Gen Register (IPU_DI0_SYNC_AS_GEN)........................................3172
45.51.175
DI0 Data Wave Gen <i> Register (IPU_DI0_DW_GEN_i)..................................................3173
45.51.176
DI0 Data Wave Set 0 <i> Register (IPU_DI0_DW_SET0_i)...............................................3176
45.51.177
DI0 Data Wave Set 1 <i> Register (IPU_DI0_DW_SET1_i)...............................................3176
45.51.178
DI0 Data Wave Set 2 <i> Register (IPU_DI0_DW_SET2_i)...............................................3177
45.51.179
DI0 Data Wave Set 3 <i> Register (IPU_DI0_DW_SET3_i)...............................................3178
45.51.180
DI0 Step Repeat <i> Registers (IPU_DI0_STP_REP_i).......................................................3178
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45.51.181
DI0 Step Repeat 9 Registers (IPU_DI0_STP_REP_9)..........................................................3179
45.51.182
DI0 Serial Display Control Register (IPU_DI0_SER_CONF)..............................................3180
45.51.183
DI0 Special Signals Control Register (IPU_DI0_SSC).........................................................3182
45.51.184
DI0 Polarity Register (IPU_DI0_POL)..................................................................................3184
45.51.185
DI0 Active Window 0 Register (IPU_DI0_AW0).................................................................3186
45.51.186
DI0 Active Window 1 Register (IPU_DI0_AW1).................................................................3186
45.51.187
DI0 Screen Configuration Register (IPU_DI0_SCR_CONF)...............................................3187
45.51.188
DI0 Status Register (IPU_DI0_STAT)..................................................................................3188
45.51.189
DI1General Register (IPU_DI1_GENERAL).......................................................................3189
45.51.190
DI1 Base Sync Clock Gen 0 Register (IPU_DI1_BS_CLKGEN0).......................................3191
45.51.191
DI1 Base Sync Clock Gen 1 Register (IPU_DI1_BS_CLKGEN1).......................................3192
45.51.192
DI1 Sync Wave Gen 1 Register 0 (IPU_DI1_SW_GEN0_1)................................................3192
45.51.193
DI1 Sync Wave Gen 2 Register 0 (IPU_DI1_SW_GEN0_2)................................................3194
45.51.194
DI1 Sync Wave Gen 3 Register 0 (IPU_DI1_SW_GEN0_3)................................................3195
45.51.195
DI1 Sync Wave Gen 4 Register 0 (IPU_DI1_SW_GEN0_4)................................................3196
45.51.196
DI1 Sync Wave Gen 5 Register 0 (IPU_DI1_SW_GEN0_5)................................................3198
45.51.197
DI1 Sync Wave Gen 6 Register 0 (IPU_DI1_SW_GEN0_6)................................................3199
45.51.198
DI1 Sync Wave Gen 7 Register 0 (IPU_DI1_SW_GEN0_7)................................................3200
45.51.199
DI1 Sync Wave Gen 8 Register 0 (IPU_DI1_SW_GEN0_8)................................................3201
45.51.200
DI1Sync Wave Gen 9 Register 0 (IPU_DI1_SW_GEN0_9).................................................3203
45.51.201
DI1 Sync Wave Gen 1 Register 1 (IPU_DI1_SW_GEN1_1)................................................3204
45.51.202
DI1 Sync Wave Gen 2 Register 1 (IPU_DI1_SW_GEN1_2)................................................3206
45.51.203
DI1 Sync Wave Gen 3 Register 1 (IPU_DI1_SW_GEN1_3)................................................3208
45.51.204
DI1 Sync Wave Gen 4 Register 1 (IPU_DI1_SW_GEN1_4)................................................3210
45.51.205
DI1 Sync Wave Gen 5 Register 1 (IPU_DI1_SW_GEN1_5)................................................3212
45.51.206
DI1 Sync Wave Gen 6 Register 1 (IPU_DI1_SW_GEN1_6)................................................3214
45.51.207
DI1Sync Wave Gen 7 Register 1 (IPU_DI1_SW_GEN1_7).................................................3216
45.51.208
DI1 Sync Wave Gen 8 Register 1 (IPU_DI1_SW_GEN1_8)................................................3218
45.51.209
DI1 Sync Wave Gen 9 Register 1 (IPU_DI1_SW_GEN1_9)................................................3220
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45.51.210
DI1 Sync Assistance Gen Register (IPU_DI1_SYNC_AS_GEN)........................................3221
45.51.211
DI1 Data Wave Gen <i> Register (IPU_DI1_DW_GEN_i)..................................................3222
45.51.212
DI1 Data Wave Set 0 <i> Register (IPU_DI1_DW_SET0_i)...............................................3225
45.51.213
DI1 Data Wave Set 1 <i> Register (IPU_DI1_DW_SET1_i)...............................................3225
45.51.214
DI1 Data Wave Set 2 <i> Register (IPU_DI1_DW_SET2_i)...............................................3226
45.51.215
DI1 Data Wave Set 3 <i> Register (IPU_DI1_DW_SET3_i)...............................................3227
45.51.216
DI1 Step Repeat <i> Registers (IPU_D1_STP_REP_i)........................................................3227
45.51.217
DI1Step Repeat 9 Registers (IPU_DI1_STP_REP_9)...........................................................3228
45.51.218
DI1 Serial Display Control Register (IPU_DI1_SER_CONF)..............................................3229
45.51.219
DI1 Special Signals Control Register (IPU_DI1_SSC).........................................................3231
45.51.220
DI1 Polarity Register (IPU_DI1_POL)..................................................................................3233
45.51.221
DI1Active Window 0 Register (IPU_DI1_AW0)..................................................................3235
45.51.222
DI1 Active Window 1 Register (IPU_DI1_AW1).................................................................3235
45.51.223
DI1 Screen Configuration Register (IPU_DI1_SCR_CONF)...............................................3236
45.51.224
DI1 Status Register (IPU_DI1_STAT)..................................................................................3237
45.51.225
SMFC Mapping Register (IPU_SMFC_MAP)......................................................................3238
45.51.226
SMFC Watermark Control Register (IPU_SMFC_WMC)....................................................3239
45.51.227
SMFC Burst Size Register (IPU_SMFC_BS).......................................................................3240
45.51.228
DC Read Channel Configuration Register (IPU_DC_READ_CH_CONF)..........................3242
45.51.229
DC Read Channel Start Address Register (IPU_DC_READ_SH_ADDR)...........................3243
45.51.230
DC Routine Link Register 0 Channel 0 (IPU_DC_RL0_CH_0)...........................................3244
45.51.231
DC Routine Link Register 1 Channel 0 (IPU_DC_RL1_CH_0)...........................................3245
45.51.232
DC Routine Link Registe3 Channel 0 (IPU_DC_RL3_CH_0).............................................3246
45.51.233
DC Routine Link Register 4 Channel 0 (IPU_DC_RL4_CH_0)...........................................3247
45.51.234
DC Write Channel 1 Configuration Register (IPU_DC_WR_CH_CONF_1).......................3248
45.51.235
DC Routine Link Register2 Channel 0 (IPU_DC_RL2_CH_0)............................................3249
45.51.236
DC Write Channel 1 Address Configuration Register (IPU_DC_WR_CH_ADDR_1)........3250
45.51.237
DC Routine Link Register 0 Channel 1 (IPU_DC_RL0_CH_1)...........................................3251
45.51.238
DC Routine Link Register 1 Channel 1 (IPU_DC_RL1_CH_1)...........................................3252
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45.51.239
DC Routine Link Register 2 Channel 2 (IPU_DC_RL2_CH_2)...........................................3253
45.51.240
DC Routine Link Register 2 Channel 1 (IPU_DC_RL2_CH_1)...........................................3254
45.51.241
DC Routine Link Register 3 Channel 1 (IPU_DC_RL3_CH_1)...........................................3255
45.51.242
DC Routine Link Register 4 Channel 1 (IPU_DC_RL4_CH_1)...........................................3256
45.51.243
DC Write Channel 2 Configuration Register (IPU_DC_WR_CH_CONF_2).......................3257
45.51.244
DC Write Channel 2 Address Configuration Register (IPU_DC_WR_CH_ADDR_2)........3258
45.51.245
DC Routine Link Register 0 Channel 2 (IPU_DC_RL0_CH_2)...........................................3259
45.51.246
DC Routine Link Register 1 Channel 2 (IPU_DC_RL1_CH_2)...........................................3260
45.51.247
DC Routine Link Register 3 Channel 2 (IPU_DC_RL3_CH_2)...........................................3261
45.51.248
DC Routine Link Register 4 Channel 2 (IPU_DC_RL4_CH_2)...........................................3262
45.51.249
DC Command Channel 3 Configuration Register (IPU_DC_CMD_CH_CONF_3)............3263
45.51.250
DC Command Channel 4 Configuration Register (IPU_DC_CMD_CH_CONF_4)............3264
45.51.251
DC Write Channel 5Configuration Register (IPU_DC_WR_CH_CONF_5)........................3265
45.51.252
DC Write Channel 5Address Configuration Register (IPU_DC_WR_CH_ADDR_5).........3266
45.51.253
DC Routine Link Register 0 Channel 5 (IPU_DC_RL0_CH_5)...........................................3267
45.51.254
DC Routine Link Register 1 Channel 5 (IPU_DC_RL1_CH_5)...........................................3268
45.51.255
DC Routine Link Register 2 Channel 5 (IPU_DC_RL2_CH_5)...........................................3269
45.51.256
DC Routine Link Register3 Channel 5 (IPU_DC_RL3_CH_5)............................................3270
45.51.257
DC Routine Link Register 4 Channel 5 (IPU_DC_RL4_CH_5)...........................................3271
45.51.258
DC Write Channel 6 Configuration Register (IPU_DC_WR_CH_CONF_6).......................3272
45.51.259
DC Write Channel 6 Address Configuration Register (IPU_DC_WR_CH_ADDR_6)........3273
45.51.260
DC Routine Link Register 0Channel 6 (IPU_DC_RL0_CH_6)............................................3273
45.51.261
DC Routine Link Register 1 Channel 6 (IPU_DC_RL1_CH_6)...........................................3275
45.51.262
DC Routine Link Register 2 Channel 6 (IPU_DC_RL2_CH_6)...........................................3276
45.51.263
DC Routine Link Register 3 Channel 6 (IPU_DC_RL3_CH_6)...........................................3277
45.51.264
DC Routine Link Register 4 Channel 6 (IPU_DC_RL4_CH_6)...........................................3278
45.51.265
DC Write Channel 8 Configuration 1Register (IPU_DC_WR_CH_CONF1_8)...................3279
45.51.266
DC Write Channel 8 Configuration 2 Register (IPU_DC_WR_CH_CONF2_8)..................3280
45.51.267
DC Routine Link Register 1 Channel 8 (IPU_DC_RL1_CH_8)...........................................3280
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45.51.268
DC Routine Link Register 2 Channel 8 (IPU_DC_RL2_CH_8)...........................................3281
45.51.269
DC Routine Link Register 3 Channel 8 (IPU_DC_RL3_CH_8)...........................................3282
45.51.270
DC Routine Link Register 4 Channel 8 (IPU_DC_RL4_CH_8)...........................................3283
45.51.271
DC Routine Link Register 5 Channel 8 (IPU_DC_RL5_CH_8)...........................................3283
45.51.272
DC Routine Link Register 6 Channel 8 (IPU_DC_RL6_CH_8)...........................................3284
45.51.273
DC Write Channel 9 Configuration 1Register (IPU_DC_WR_CH_CONF1_9)...................3285
45.51.274
DC Write Channel 9Configuration 2Register (IPU_DC_WR_CH_CONF2_9)....................3286
45.51.275
DC Routine Link Register 1 Channel 9 (IPU_DC_RL1_CH_9)...........................................3286
45.51.276
DC Routine Link Register 2 Channel 9 (IPU_DC_RL2_CH_9)...........................................3287
45.51.277
DC Routine Link Register 3Channel 9 (IPU_DC_RL3_CH_9)............................................3288
45.51.278
DC Routine Link Register 4 Channel 9 (IPU_DC_RL4_CH_9)...........................................3289
45.51.279
DC Routine Link Register 5 Channel 9 (IPU_DC_RL5_CH_9)...........................................3289
45.51.280
DC Routine Link Register 6 Channel 9 (IPU_DC_RL6_CH_9)...........................................3290
45.51.281
DC General Register (IPU_DC_GEN)..................................................................................3291
45.51.282
DC Display Configuration 1 Register 0 (IPU_DC_DISP_CONF1_0)..................................3292
45.51.283
DC Display Configuration 1 Register 1 (IPU_DC_DISP_CONF1_1)..................................3294
45.51.284
DC Display Configuration 1 Register 2 (IPU_DC_DISP_CONF1_2)..................................3295
45.51.285
DC Display Configuration 1 Register 3 (IPU_DC_DISP_CONF1_3)..................................3296
45.51.286
DC Display Configuration 2 Register 0 (IPU_DC_DISP_CONF2_0)..................................3297
45.51.287
DC Display Configuration 2 Register 2 (IPU_DC_DISP_CONF2_2)..................................3298
45.51.288
DC Display Configuration 2 Register 3 (IPU_DC_DISP_CONF2_3)..................................3298
45.51.289
DC DI0Configuration Register 1 (IPU_DC_DI0_CONF_1).................................................3299
45.51.290
DC DI0Configuration Register 2 (IPU_DC_DI0_CONF_2).................................................3299
45.51.291
DC DI1Configuration Register 1 (IPU_DC_DI1_CONF_1).................................................3299
45.51.292
DC DI1Configuration Register 2 (IPU_DC_DI1_CONF_2).................................................3300
45.51.293
DC Mapping Configuration Register 0 (IPU_DC_MAP_CONF_0).....................................3300
45.51.294
DC Mapping Configuration Register 1 (IPU_DC_MAP_CONF_1).....................................3301
45.51.295
DC Mapping Configuration Register 2 (IPU_DC_MAP_CONF_2).....................................3302
45.51.296
DC Mapping Configuration Register 3 (IPU_DC_MAP_CONF_3).....................................3303
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45.51.297
DC Mapping Configuration Register 4 (IPU_DC_MAP_CONF_4).....................................3304
45.51.298
DC Mapping Configuration Register 5 (IPU_DC_MAP_CONF_5).....................................3304
45.51.299
DC Mapping Configuration Register 6 (IPU_DC_MAP_CONF_6).....................................3305
45.51.300
DC Mapping Configuration Register 7 (IPU_DC_MAP_CONF_7).....................................3306
45.51.301
DC Mapping Configuration Register 8 (IPU_DC_MAP_CONF_8).....................................3307
45.51.302
DC Mapping Configuration Register 9 (IPU_DC_MAP_CONF_9).....................................3308
45.51.303
DC Mapping Configuration Register 10 (IPU_DC_MAP_CONF_10).................................3309
45.51.304
DC Mapping Configuration Register 11 (IPU_DC_MAP_CONF_11).................................3310
45.51.305
DC Mapping Configuration Register 12 (IPU_DC_MAP_CONF_12).................................3311
45.51.306
DC Mapping Configuration Register 13 (IPU_DC_MAP_CONF_13).................................3312
45.51.307
DC Mapping Configuration Register 14 (IPU_DC_MAP_CONF_14).................................3313
45.51.308
DC Mapping Configuration Register 15 (IPU_DC_MAP_CONF_15).................................3314
45.51.309
DC Mapping Configuration Register 16 (IPU_DC_MAP_CONF_16).................................3315
45.51.310
DC Mapping Configuration Register 17 (IPU_DC_MAP_CONF_17).................................3316
45.51.311
DC Mapping Configuration Register 18 (IPU_DC_MAP_CONF_18).................................3316
45.51.312
DC Mapping Configuration Register 19 (IPU_DC_MAP_CONF_19).................................3317
45.51.313
DC Mapping Configuration Register 20 (IPU_DC_MAP_CONF_20).................................3318
45.51.314
DC Mapping Configuration Register 21 (IPU_DC_MAP_CONF_21).................................3318
45.51.315
DC Mapping Configuration Register 22 (IPU_DC_MAP_CONF_22).................................3319
45.51.316
DC Mapping Configuration Register 23 (IPU_DC_MAP_CONF_23).................................3320
45.51.317
DC Mapping Configuration Register 24 (IPU_DC_MAP_CONF_24).................................3320
45.51.318
DC Mapping Configuration Register 25 (IPU_DC_MAP_CONF_25).................................3321
45.51.319
DC Mapping Configuration Register 26 (IPU_DC_MAP_CONF_26).................................3322
45.51.320
DC User General Data Event 0 Register 0 (IPU_DC_UGDE0_0)........................................3323
45.51.321
DC User General Data Event 0 Register 1 (IPU_DC_UGDE0_1)........................................3324
45.51.322
DC User General Data Event 0 Register2 (IPU_DC_UGDE0_2).........................................3325
45.51.323
DC User General Data Event 0 Register 3 (IPU_DC_UGDE0_3)........................................3325
45.51.324
DC User General Data Event 1Register0 (IPU_DC_UGDE1_0)..........................................3326
45.51.325
DC User General Data Event 1 Register 1 (IPU_DC_UGDE1_1)........................................3327
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45.51.326
DC User General Data Event 1Register 2 (IPU_DC_UGDE1_2).........................................3328
45.51.327
DC User General Data Event 1Register 3 (IPU_DC_UGDE1_3).........................................3328
45.51.328
DC User General Data Event 2 Register 0 (IPU_DC_UGDE2_0)........................................3329
45.51.329
DC User General Data Event 2 Register 1 (IPU_DC_UGDE2_1)........................................3330
45.51.330
DC User General Data Event 2Register 2 (IPU_DC_UGDE2_2).........................................3331
45.51.331
DC User General Data Event 2Register 3 (IPU_DC_UGDE2_3).........................................3331
45.51.332
DC User General Data Event 3Register 0 (IPU_DC_UGDE3_0).........................................3332
45.51.333
DC User General Data Event 3Register 1 (IPU_DC_UGDE3_1).........................................3333
45.51.334
DC User General Data Event 3Register 2 (IPU_DC_UGDE3_2).........................................3334
45.51.335
DC User General Data Event 3Register 2 (IPU_DC_UGDE3_3).........................................3334
45.51.336
DC Low Level Access Control Register 0 (IPU_DC_LLA0)...............................................3335
45.51.337
DC Low Level Access Control Register 1 (IPU_DC_LLA1)...............................................3335
45.51.338
DC Read Low Level Read Access Control Register 0 (IPU_DC_R_LLA0)........................3336
45.51.339
DC Read Low Level Read Access Control Register1 (IPU_DC_R_LLA1).........................3336
45.51.340
DC Write Channel 5 Configuration Register (IPU_DC_WR_CH_ADDR_5_ALT)............3337
45.51.341
DC Status Register (IPU_DC_STAT)...................................................................................3338
45.51.342
DC Display Configuration 2 Register 1 (IPU_DC_DISP_CONF2_1)..................................3339
45.51.343
DMFC Read Channel Register (IPU_DMFC_RD_CHAN)..................................................3340
45.51.344
DMFC Write Channel Register (IPU_DMFC_WR_CHAN)................................................3341
45.51.345
DMFC Write Channel Definition Register (IPU_DMFC_WR_CHAN_DEF).....................3344
45.51.346
DMFC Display Processor Channel Register (IPU_DMFC_DP_CHAN)..............................3346
45.51.347
DMFC Display Processor Channel Definition Register (IPU_DMFC_DP_CHAN_DEF)...3349
45.51.348
DMFC General 1 Register (IPU_DMFC_GENERAL_1).....................................................3351
45.51.349
DMFC General 2 Register (IPU_DMFC_GENERAL_2).....................................................3353
45.51.350
DMFC IC Interface Control Register (IPU_DMFC_IC_CTRL)...........................................3354
45.51.351
DMFC Write Channel Alternate Register (IPU_DMFC_WR_CHAN_ALT).......................3355
45.51.352
DMFC Write Channel Definition Alternate Register
(IPU_DMFC_WR_CHAN_DEF_ALT)................................................................................3356
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Title
Page
DMFC MFC Display Processor Channel Alternate Register
(IPU_DMFC_DP_CHAN_ALT)...........................................................................................3357
45.51.354
DMFC Display Channel Definition Alternate Register
(IPU_DMFC_DP_CHAN_DEF_ALT).................................................................................3360
45.51.355
DMFC General 1 Alternate Register (IPU_DMFC_GENERAL1_ALT)..............................3361
45.51.356
DMFC Status Register (IPU_DMFC_STAT)........................................................................3363
45.51.357
VDI Field Size Register (IPU_VDI_FSIZE).........................................................................3364
45.51.358
VDI Control Register (IPU_VDI_C).....................................................................................3365
45.51.359
VDI Control Register 2 (IPU_VDI_C2_)..............................................................................3367
45.51.360
VDI Combining Parameters Register 1 (IPU_VDI_CMDP_1).............................................3368
45.51.361
VDI Combining Parameters Register 2 (IPU_VDI_CMDP_2).............................................3368
45.51.362
VDI Plane Size Register 1 (IPU_VDI_PS_1)........................................................................3369
45.51.363
VDI Plane Size Register 2 (IPU_VDI_PS_2)........................................................................3370
45.51.364
VDI Plane Size Register 3 (IPU_VDI_PS_3)........................................................................3370
45.51.365
VDI Plane Size Register 4 (IPU_VDI_PS_4)........................................................................3371
45.51.366
IDMAC Channel Enable 2 Register (IPU_IDMAC_CH_EN_2)..........................................3372
45.51.367
IDMAC Channel Lock Enable 2Register (IPU_IDMAC_LOCK_EN_2).............................3374
45.51.368
IDMAC Channel Alternate Address 0 Register (IPU_IDMAC_SUB_ADDR_0)................3375
45.51.369
IDMAC Channel Alternate Address 2 Register (IPU_IDMAC_SUB_ADDR_2)................3376
45.51.370
IDMAC Channel Alternate Address 3 Register (IPU_IDMAC_SUB_ADDR_3)................3377
45.51.371
IDMAC Channel Alternate Address 4 Register (IPU_IDMAC_SUB_ADDR_4)................3378
45.51.372
IDMAC Band Mode Enable 1 Register (IPU_IDMAC_BNDM_EN_1)..............................3379
45.51.373
IDMAC Channel Alternate Address 1 Register (IPU_IDMAC_SUB_ADDR_1)................3382
45.51.374
DP Common Configuration Sync Flow Register (IPU_DP_COM_CONF_SYNC).............3383
45.51.375
DP Graphic Window Control Sync Flow Register
(IPU_DP_Graph_Wind_CTRL_SYNC)................................................................................3385
45.51.376
DP Partial Plane Window Position Sync Flow Register (IPU_DP_FG_POS_SYNC).........3386
45.51.377
DP Cursor Position and Size Sync Flow Register (IPU_DP_CUR_POS_SYNC)................3386
45.51.378
DP Color Cursor Mapping Sync Flow Register (IPU_DP_CUR_MAP_SYNC)..................3387
45.51.379
DP Gamma Constants Sync Flow Register i (IPU_DP_GAMMA_C_SYNC_i)..................3388
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45.51.380
DP Gamma Correction Slope Sync Flow Register i (IPU_DP_GAMMA_S_SYNC_i).......3388
45.51.381
DP Color Space Conversion Control Sync Flow Registers (IPU_DP_CSCA_SYNC_i)......3389
45.51.382
DP Color Conversion Control Sync Flow Register 0 (IPU_DP_SCS_SYNC_0).................3390
45.51.383
DP Color Conversion Control Sync Flow Register 1 (IPU_DP_SCS_SYNC_1).................3390
45.51.384
DP Cursor Position and Size Alternate Register (IPU_DP_CUR_POS_ALT).....................3391
45.51.385
DP Common Configuration Async 0 Flow Register (IPU_DP_COM_CONF_ASYNC0)...3392
45.51.386
DP Graphic Window Control Async 0 Flow Register
(IPU_DP_GRAPH_WIND_CTRL_ASYNC0).....................................................................3394
45.51.387
DP Partial Plane Window Position Async 0 Flow Register
(IPU_DP_FG_POS_ASYNC0).............................................................................................3395
45.51.388
DP Cursor Position and Size Async 0 Flow Register (IPU_DP_CUR_POS_ASYNC0)......3395
45.51.389
DP Color Cursor Mapping Async 0 Flow Register (IPU_DP_CUR_MAP_ASYNC0)........3396
45.51.390
DP Gamma Constant Async 0 Flow Register i (IPU_DP_GAMMA_C_ASYNC0_i).........3397
45.51.391
DP Gamma Correction Slope Async 0 Flow Register i
(IPU_DP_GAMMA_S_ASYNC0_i).....................................................................................3398
45.51.392
DP Color Space Conversion Control Async 0 Flow Register i
(IPU_DP_CSCA_ASYNC0_i)..............................................................................................3398
45.51.393
DP Color Conversion Control Async 0 Flow Register 0 (IPU_DP_CSC_ASYNC0_0).......3399
45.51.394
DP Color Conversion Control Async 1 Flow Register (IPU_DP_CSC_ASYNC_1)............3400
45.51.395
DP Common Configuration Async 1 Flow Register (IPU_DP_COM_CONF_ASYNC1)...3401
45.51.396
DP Graphic Window Control Async 1 Flow Register
(IPU_DP_GRAPH_WIND_CTRL_ASYNC1).....................................................................3403
45.51.397
DP Partial Plane Window Position Async 1 Flow Register
(IPU_DP_FG_POS_ASYNC1).............................................................................................3404
45.51.398
DP Cursor Postion and Size Async 1 Flow Register (IPU_DP_CUR_POS_ASYNC1).......3404
45.51.399
DP Color Cursor Mapping Async 1 Flow Register (IPU_DP_CUR_MAP_ASYNC1)........3405
45.51.400
DP Gamma Constants Async 1 Flow Register i (IPU_DP_GAMMA_C_ASYNC1_i)........3406
45.51.401
DP Gamma Correction Slope Async 1 Flow Register i (IPU_DP_GAMMA_S_ASYN1_i)3407
45.51.402
DP Color Space Converstion Control Async 1 Flow Register i
(IPU_DP_CSCA_ASYNC1_i)..............................................................................................3407
45.51.403
DP Color Conversion Control Async 1 Flow Register 0 (IPU_DP_CSC_ASYNC1_0).......3408
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45.51.404
DP Color Conversion Control Async 1 Flow Register 1 (IPU_DP_CSC_ASYNC1_1).......3409
45.51.405
IDMAC Band Mode Enable 2 Register (IPU_IDMAC_BNDM_EN_2)..............................3410
45.51.406
IDMAC Scroll Coordinations Register (IPU_IDMAC_SC_CORD)....................................3411
Chapter 46
Keypad Port (KPP)
46.1
46.2
Overview ......................................................................................................................................................................3413
46.1.1
Features......................................................................................................................................................3414
46.1.2
Modes and Operations...............................................................................................................................3415
External Signals............................................................................................................................................................3415
46.2.1
46.3
External Signals Overview.........................................................................................................................3415
46.2.1.1
Input Pins...............................................................................................................................3415
46.2.1.2
Output Pins.............................................................................................................................3416
46.2.1.3
Generation of Transfer Error Signal on Peripheral Bus.........................................................3416
Functional Description..................................................................................................................................................3417
46.3.1
Keypad Matrix Construction......................................................................................................................3417
46.3.2
Keypad Port Configuration........................................................................................................................3417
46.3.3
Keypad Matrix Scanning...........................................................................................................................3417
46.3.4
Keypad Standby.........................................................................................................................................3418
46.3.5
Glitch Suppression on Keypad Inputs........................................................................................................3418
46.3.6
Multiple Key Closures...............................................................................................................................3420
46.3.6.1
46.3.7
46.4
46.5
Ghost Key Problem and Correction.......................................................................................3422
3-Point Contact Keys Support....................................................................................................................3424
Initialization/Application Information..........................................................................................................................3425
46.4.1
Typical Keypad Configuration and Scanning Sequence............................................................................3425
46.4.2
Key Press Interrupt Scanning Sequence....................................................................................................3426
46.4.3
Additional Comments................................................................................................................................3426
Programmable Registers...............................................................................................................................................3427
46.5.1
Keypad Control Register (KPP_KPCR)....................................................................................................3427
46.5.2
Keypad Status Register (KPP_KPSR).......................................................................................................3428
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Page
46.5.3
Keypad Data Direction Register (KPP_KDDR)........................................................................................3430
46.5.4
Keypad Data Register (KPP_KPDR).........................................................................................................3430
Chapter 47
LVDS Display Bridge (LDB)
47.1
Introduction...................................................................................................................................................................3433
47.2
External Ports................................................................................................................................................................3436
47.2.1
Input Parallel Display Ports.......................................................................................................................3436
47.2.2
Output LVDS Ports....................................................................................................................................3436
47.3
Clock Sources...............................................................................................................................................................3437
47.4
Processing.....................................................................................................................................................................3437
47.5
47.4.1
Mapping of Input Data Busses...................................................................................................................3438
47.4.2
Bit Mapping...............................................................................................................................................3438
Programmable Registers...............................................................................................................................................3439
47.5.1
LDB Control Register (LDB_CTRL)........................................................................................................3439
Chapter 48
Low-Dropout Regulator (LDO)
48.1
Introduction...................................................................................................................................................................3443
48.1.1
Overview....................................................................................................................................................3443
48.2
Features.........................................................................................................................................................................3444
48.3
1.2 V Regulator (plldig) Specifications........................................................................................................................3444
48.4
1.8 V Regulator (pllana) Specification.........................................................................................................................3444
48.5
Register Definition........................................................................................................................................................3445
Chapter 49
Multi Master Multi Memory Interface (M4IF)
49.1
Introduction ..................................................................................................................................................................3447
49.1.1
Overview....................................................................................................................................................3447
49.1.1.1
AXI Port Gasket.....................................................................................................................3447
49.1.1.2
Dedicated Write Buffers........................................................................................................3448
49.1.1.3
Read Shared Buffers..............................................................................................................3448
49.1.1.4
Fast Arbiter............................................................................................................................3448
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49.1.1.5
Slow Arbiter...........................................................................................................................3448
49.1.1.6
Internal 1 Memory Arbiter.....................................................................................................3449
49.1.1.7
Internal 2 Memory Arbiter.....................................................................................................3449
49.1.1.8
Debug Unit-Overview............................................................................................................3449
49.1.2
Features......................................................................................................................................................3450
49.1.3
Modes of Operation...................................................................................................................................3451
49.1.3.1
Normal Operating Modes.......................................................................................................3452
49.1.3.2
Low Power Modes.................................................................................................................3452
49.1.3.3
Debug Mode...........................................................................................................................3455
49.1.3.3.1
Step By Step Mode.........................................................................................3455
49.1.3.3.2
Debug Unit - Functional Description..............................................................3455
49.1.3.3.3
Debug Signals.................................................................................................3455
49.1.3.4
Dynamic Voltage and Frequency Scaling (DVFS)................................................................3457
49.1.3.5
Power Saving Mode...............................................................................................................3457
49.1.3.6
49.2
Title
49.1.3.5.1
Arbitration Power Saving...............................................................................3457
49.1.3.5.2
Gasket Power Saving......................................................................................3457
49.1.3.5.3
SW Power Saving...........................................................................................3458
Error Handling And Interrupts...............................................................................................3459
49.1.3.6.1
LEN > 8..........................................................................................................3459
49.1.3.6.2
Watermark.......................................................................................................3459
Functional Description..................................................................................................................................................3459
49.2.1
Write Access Description...........................................................................................................................3459
49.2.2
Read Access Description...........................................................................................................................3460
49.2.3
AXI Port Gasket Functional Description...................................................................................................3460
49.2.4
Read/Write Buffer Functional Description................................................................................................3461
49.2.5
Fast Arbiter Functional Description - 1st Degree......................................................................................3462
49.2.5.1
Page Hit / Miss.......................................................................................................................3462
49.2.5.2
Last Access Details................................................................................................................3463
49.2.5.3
Basic Priority Configuration..................................................................................................3463
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49.2.5.4
Priority Calculation................................................................................................................3463
49.2.5.5
2nd Degree Arbitration (M4IF)..............................................................................................3465
49.2.5.5.1
M4IF Bypass...................................................................................................3465
49.2.5.5.2
Guarding Mechanism......................................................................................3466
49.2.5.5.3
Prediction........................................................................................................3466
49.2.6
Slow Arbiter Functional Description.........................................................................................................3466
49.2.7
Internal 1 Memory Arbiter Functional Description...................................................................................3466
49.2.8
Internal 2 Memory Arbiter Functional Description...................................................................................3467
49.2.9
Arbitration Scheme when Masters have Same Priority (Bus Division).....................................................3467
49.2.10
EIM-NFC Downsizer.................................................................................................................................3470
49.2.10.1
49.2.11
Internal 1 Downsizer..................................................................................................................................3471
49.2.11.1
49.2.12
Endianess In Downsizing (Internal 1 Downsizer).................................................................3471
Clocks - i.MX53 Specific...........................................................................................................................3472
49.2.12.1
49.2.13
Endianess In Downsizing (EIM-NFC Downsizer)................................................................3470
Clock Ratios...........................................................................................................................3472
Reset...........................................................................................................................................................3472
49.2.13.1
Software Reset.......................................................................................................................3473
49.2.13.2
Warm Reset............................................................................................................................3473
49.2.13.3
EXTMC Programing Sequence After Warm Reset...............................................................3473
49.2.14
Interrupts....................................................................................................................................................3474
49.2.15
Endianness.................................................................................................................................................3475
49.2.16
AXI Interface Restrictions.........................................................................................................................3475
49.2.16.1
General Interface Limitations................................................................................................3475
49.2.16.2
Atomic Accesses....................................................................................................................3476
49.2.16.3
49.2.16.2.1
AXI Locked Accesses ....................................................................................3476
49.2.16.2.2
Exclusive Accesses.........................................................................................3477
Write Data Interleaving..........................................................................................................3477
49.2.17
IPS Interface...............................................................................................................................................3477
49.2.18
WaterMark Functionality Overview..........................................................................................................3478
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49.2.19
Page
Debug Unit.................................................................................................................................................3480
49.2.19.1
Visibility Unit........................................................................................................................3480
49.2.19.2
Profiling Units........................................................................................................................3480
49.2.20
Buffers Size Table......................................................................................................................................3482
49.2.21
Synchronization.........................................................................................................................................3482
49.2.21.1
49.3
Title
Synchronization Table...........................................................................................................3483
49.2.22
Supporting 8/16 bit Bursts.........................................................................................................................3484
49.2.23
Dead-Lock Prevention in Read Accesses..................................................................................................3484
Programmable Registers...............................................................................................................................................3485
49.3.1
Power Saving Masters 0 (M4IF_PSM0)....................................................................................................3488
49.3.2
Power Saving Masters 1 (M4IF_PSM1)....................................................................................................3490
49.3.3
General Purpose Register (M4IF_GPR)....................................................................................................3492
49.3.4
Debug Status Register 6 (M4IF_DSR6)....................................................................................................3493
49.3.5
Debug Status Register 7 (M4IF_DSR7)....................................................................................................3493
49.3.6
Debug Status Register 8 (M4IF_DSR8)....................................................................................................3494
49.3.7
Debug Status Register 0 (M4IF_DSR0)....................................................................................................3494
49.3.8
Debug Status Register 1 (M4IF_DSR1)....................................................................................................3495
49.3.9
Debug Status Register 2 (M4IF_DSR2)....................................................................................................3495
49.3.10
Debug Status Register 3 (M4IF_DSR3)....................................................................................................3496
49.3.11
Debug Status Register 4 (M4IF_DSR4)....................................................................................................3496
49.3.12
Debug Status Register 5 (M4IF_DSR5)....................................................................................................3497
49.3.13
F_Basic Priority Reg 0 (M4IF_F_BPR0)..................................................................................................3498
49.3.14
F_Basic Priority Reg 1 (M4IF_F_BPR1)..................................................................................................3500
49.3.15
Control Register (M4IF_CR).....................................................................................................................3502
49.3.16
I2_Unit_Level_Arbitration_ Register (M4IF_I2_ULAR).........................................................................3503
49.3.17
Int. 2 Memory Arbitration Control Register (M4IF_I2MACR)................................................................3504
49.3.18
Internal 2 Control Register (M4IF_I2CR).................................................................................................3505
49.3.19
Step By Step Address (M4IF_SSA)...........................................................................................................3506
49.3.20
Step By Step Address Controls (M4IF_SSAC).........................................................................................3507
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49.3.21
Control Register 0 (M4IF_CR0)................................................................................................................3508
49.3.22
Control Register 1 (M4IF_CR1)................................................................................................................3511
49.3.23
Debug Control Register (M4IF_DCR)......................................................................................................3513
49.3.24
Fast Arbitration Control Register (M4IF_FACR).....................................................................................3516
49.3.25
F_Priority Weighting Configuration Register (M4IF_F_PWCR).............................................................3516
49.3.26
Slow Arbitration Control Register (M4IF_SACR)....................................................................................3518
49.3.27
Power Saving Masters 2 (M4IF_PSM2)....................................................................................................3519
49.3.28
Int. Memory Arbitration Control Register (M4IF_IMACR).....................................................................3521
49.3.29
Power Saving Masters 3 (M4IF_PSM3)....................................................................................................3521
49.3.30
F_Unit_Level_Arbitration_ Register (M4IF_F_ULAR)...........................................................................3524
49.3.31
S_Unit_Level_Arbitration_ Register (M4IF_S_ULAR)...........................................................................3525
49.3.32
I_Unit_Level_Arbitration_ Register (M4IF_I_ULAR).............................................................................3526
49.3.33
Fast_Dynamic_Priority_Status Register (M4IF_FDPSR).........................................................................3527
49.3.34
Fast_Dynamic_Priority_Control Register (M4IF_FDPCR)......................................................................3528
49.3.35
Master Len Interrupt (M4IF_MLI)............................................................................................................3530
49.3.36
Watermark Start ADDR_0 Register n (M4IF_WMSA0_n)......................................................................3532
49.3.37
Watermark End ADDR_0 Register (M4IF_WMEA0_n)..........................................................................3532
49.3.38
Watermark Interrupt and Status 0 Register (M4IF_WMIS0)....................................................................3533
49.3.39
Watermark Violation Address 0 Register (M4IF_WMVA0)....................................................................3534
49.3.40
Watermark Start ADDR_1 Register n (M4IF_WMSA1_n)......................................................................3535
49.3.41
Watermark End ADDR_1 Register (M4IF_WEAR1_n)...........................................................................3535
49.3.42
Watermark Interrupt and Status 1 Register (M4IF_WISR1).....................................................................3537
49.3.43
Watermark Violation Address 1 Register (M4IF_WMVA1)....................................................................3538
Chapter 50
Media Local Bus (MediaLB) Block (MLB)
50.1
Introduction ..................................................................................................................................................................3539
50.1.1
Overview....................................................................................................................................................3539
50.1.2
Features......................................................................................................................................................3541
50.1.3
Logic Blocks..............................................................................................................................................3541
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50.1.4
50.2
50.4
Page
Modes of Operation...................................................................................................................................3542
External Signal Description..........................................................................................................................................3542
50.2.1
50.3
Title
Detailed Signal Descriptions .....................................................................................................................3542
Programmable Registers...............................................................................................................................................3543
50.3.1
Device Control Configuration Register (MLB_DCCR)............................................................................3548
50.3.2
System Status Configuration Register (MLB_SSCR)...............................................................................3550
50.3.3
System Data Configuration Register (MLB_SDCR).................................................................................3552
50.3.4
System Mask Configuration Register (MLB_SMCR)...............................................................................3552
50.3.5
Version Control Configuration Register (MLB_VCCR)...........................................................................3553
50.3.6
Synchronous Base Address Configuration Register (MLB_SBCR)..........................................................3554
50.3.7
Asynchronous Base Address Configuration Register (MLB_ABCR).......................................................3554
50.3.8
Control Base Address Configuration Register (MLB_CBCR)..................................................................3555
50.3.9
Isochronous Base Address Configuration Register (MLB_IBCR)............................................................3555
50.3.10
Channel Interrupt Configuration Register (MLB_CICR)..........................................................................3556
50.3.11
Channel n Entry Configuration Register (MLB_CECRn).........................................................................3557
50.3.12
Channel n Status Configuration Register (MLB_CSCRn)........................................................................3560
50.3.13
Channel n Current Buffer Configuration Register (MLB_CCBCRn).......................................................3563
50.3.14
Channel n Next Buffer Configuration Register (MLB_CNBCRn)...........................................................3564
50.3.15
Local Channel n Buffer Configuration Register (MLB_LCBCRn)...........................................................3565
Functional Description..................................................................................................................................................3565
50.4.1
Local Channel Buffer RAM.......................................................................................................................3565
50.4.1.1
Local Buffer Start Address....................................................................................................3567
50.4.1.2
Local Channel Buffer Depth..................................................................................................3567
50.4.2
Streaming Channel Frame Synchronization..............................................................................................3568
50.4.3
Loop-Back Test Mode...............................................................................................................................3569
Chapter 51
NAND Flash Controller (NFC)
51.1
Introduction...................................................................................................................................................................3571
51.2
Overview.......................................................................................................................................................................3572
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51.3
Features.........................................................................................................................................................................3573
51.4
Restrictions...................................................................................................................................................................3573
51.5
Signals Overview..........................................................................................................................................................3574
51.6
Detailed Signal Descriptions.........................................................................................................................................3574
51.7
Memory Map and Register Definition..........................................................................................................................3576
51.7.1
51.8
51.9
Internal RAM Address Space and Organization........................................................................................3576
AXI Memory Map........................................................................................................................................................3581
51.8.1
NAND Flash command (NFC_NAND_CMD)..........................................................................................3582
51.8.2
NAND Flash address0 (NFC_NAND_ADD0)..........................................................................................3582
51.8.3
NAND address1 (NFC_NAND_ADD1)...................................................................................................3583
51.8.4
NAND address2 (NFC_NAND_ADD2)...................................................................................................3583
51.8.5
NAND address3 (NFC_NAND_ADD3)...................................................................................................3584
51.8.6
NAND address4 (NFC_NAND_ADD4)...................................................................................................3585
51.8.7
NAND address5 (NFC_NAND_ADD5)...................................................................................................3585
51.8.8
NAND address6 (NFC_NAND_ADD6)...................................................................................................3586
51.8.9
NAND address7 (NFC_NAND_ADD7)...................................................................................................3586
51.8.10
NAND address8 (NFC_NAND_ADD8)...................................................................................................3587
51.8.11
NAND address9 (NFC_NAND_ADD9)...................................................................................................3587
51.8.12
NAND address10 (NFC_NAND_ADD10)...............................................................................................3588
51.8.13
NAND address11 (NFC_NAND_ADD11)...............................................................................................3588
51.8.14
NFC configuration (NFC_CONFIGURATION1).....................................................................................3589
51.8.15
ECC status result (NFC_ECC_STATUS_RESULT)................................................................................3592
51.8.16
status sum (NFC_STATUS_SUM)............................................................................................................3595
51.8.17
Initiate an NFC operation (NFC_LAUNCH_NFC)...................................................................................3595
Programmable Registers...............................................................................................................................................3599
51.9.1
NAND Flash Write Protection (NFC_WR_PROTECT)...........................................................................3599
51.9.2
NFC Operation Configuration2 (NFC_CONFIGURATION2).................................................................3600
51.9.3
NFC Operation Configuration3 (NFC_CONFIGURATION3).................................................................3603
51.9.4
NFC IP Control (NFC_IPC)......................................................................................................................3608
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51.9.5
AXI error address (NFC_AXI_ERR_ADD)..............................................................................................3610
51.9.6
Delay line parameters (NFC_DELAY_LINE)..........................................................................................3610
51.10 Functional Description..................................................................................................................................................3611
51.10.1
Reset...........................................................................................................................................................3611
51.10.2
NAND Flash I/F Control............................................................................................................................3612
51.10.3
DMA Request Operation...........................................................................................................................3615
51.10.4
Internal RAM ............................................................................................................................................3615
51.10.4.1
LPMD/ DVFS........................................................................................................................3617
51.10.4.2
Burst Access Support.............................................................................................................3617
51.10.5
Block interface...........................................................................................................................................3617
51.10.6
I/O Pins Sharing.........................................................................................................................................3618
51.11 NFC Operation..............................................................................................................................................................3618
51.11.1
51.11.2
Automatic Operations................................................................................................................................3619
51.11.1.1
Automatic program operation................................................................................................3619
51.11.1.2
Automatic Read Operation.....................................................................................................3620
51.11.1.3
Automatic erase operation.....................................................................................................3620
51.11.1.4
AutoMatic Copy-back Operation...........................................................................................3621
51.11.1.5
Automatic Status-read Operation...........................................................................................3622
Atomic Operations.....................................................................................................................................3622
51.11.2.1
Preset Operation.....................................................................................................................3622
51.11.2.2
NAND Flash Atomic Command Input Operation.................................................................3622
51.11.2.3
NAND Flash Atomic Address Input Operation.....................................................................3623
51.11.2.4
NAND Flash Atomic Data Input Operation..........................................................................3624
51.11.2.5
NAND Flash Atomic Data Output Operation........................................................................3626
51.11.2.6
Read NAND Flash Atomic ID Read Operation.....................................................................3628
51.11.2.6.1
51.11.2.7
51.11.3
NAND Flash ID Data Formats.......................................................................3629
NAND Flash Atomic Status Read Operation........................................................................3629
Atomic Operations Sequence.....................................................................................................................3631
51.11.3.1
Atomic Read Sequence Operation.........................................................................................3631
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Page
51.11.3.2
Atomic Program Sequence Operation....................................................................................3633
51.11.3.3
Atomic Erase Sequence Operation........................................................................................3635
ECC Operation...........................................................................................................................................3635
51.11.4.1
ECC Normal Operation..........................................................................................................3636
51.11.4.2
ECC Bypass Operation..........................................................................................................3637
51.11.4.3
How to Operate the ECC.......................................................................................................3638
51.11.5
Symmetric/Asymmetric Mode Operation..................................................................................................3638
51.11.6
Delay Line Operation.................................................................................................................................3640
51.11.6.1
Delay line background...........................................................................................................3640
51.11.6.2
Delay Line and Flash Clock Settings.....................................................................................3641
51.12 Memory Connectivity Examples..................................................................................................................................3643
51.13 Verified NAND Models................................................................................................................................................3646
Chapter 52
On-Chip RAM Memory Controller (OCRAM)
52.1
Overview.......................................................................................................................................................................3647
52.2
Basic Functions.............................................................................................................................................................3647
52.3
52.4
52.2.1
Read/Write Arbitration..............................................................................................................................3647
52.2.2
TrustZone...................................................................................................................................................3647
Advanced Features........................................................................................................................................................3648
52.3.1
Read Data Wait State.................................................................................................................................3648
52.3.2
Read Address Pipeline...............................................................................................................................3648
52.3.3
Write Data Pipeline....................................................................................................................................3649
52.3.4
Write Address Pipeline..............................................................................................................................3649
Programmable Registers...............................................................................................................................................3649
Chapter 53
1-Wire Block (OWIRE)
53.1
Overview.......................................................................................................................................................................3651
53.1.1
Features......................................................................................................................................................3651
53.1.2
Modes of Operation...................................................................................................................................3652
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53.2
External Signals............................................................................................................................................................3652
53.3
Functional Description..................................................................................................................................................3652
53.3.1
53.3.1.1
Reset/Presence-detect Pulse...................................................................................................3653
53.3.1.2
Bit Transfers ..........................................................................................................................3653
53.3.1.2.1
Write-0 Sequence............................................................................................3653
53.3.1.2.2
Write-1 / Read Sequence................................................................................3654
53.3.1.3
Byte Transfers........................................................................................................................3654
53.3.1.4
Search ROM Accelerator Mode.............................................................................................3655
53.3.2
Low Power Mode.......................................................................................................................................3655
53.3.3
Clocks.........................................................................................................................................................3655
53.3.4
Reset...........................................................................................................................................................3656
53.3.5
53.4
Normal Operating Modes...........................................................................................................................3653
53.3.4.1
Hardware Reset......................................................................................................................3656
53.3.4.2
Software Reset.......................................................................................................................3656
Interrupts....................................................................................................................................................3656
Programmable Registers...............................................................................................................................................3657
53.4.1
Control register (OWIRE_CONTROL).....................................................................................................3658
53.4.2
Time Divider register (OWIRE_TIME_DIVIDER)..................................................................................3659
53.4.3
Reset register (OWIRE_RESET)...............................................................................................................3659
53.4.4
Command Register (OWIRE_COMMAND).............................................................................................3660
53.4.5
Transmit/Receive Register (OWIRE_TX/RX)..........................................................................................3661
53.4.6
Interrupt Register (OWIRE_INTERRUPT)...............................................................................................3661
53.4.7
Interrupt Enable Register (OWIRE_INTERRUPT_EN)...........................................................................3663
Chapter 54
Parallel Advanced Technology Attachment (PATA)
54.1
Overview.......................................................................................................................................................................3665
54.1.1
Features......................................................................................................................................................3666
54.1.2
Modes of Operation...................................................................................................................................3666
54.1.2.1
PIO Mode...............................................................................................................................3666
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54.2
54.2.2
54.4
Page
DMA Mode............................................................................................................................3667
External Signal Description..........................................................................................................................................3667
54.2.1
54.3
Title
Signal Descriptions....................................................................................................................................3668
54.2.1.1
pata_reset_b (out)...................................................................................................................3668
54.2.1.2
pata_dior (out)........................................................................................................................3668
54.2.1.3
pata_diow (out)......................................................................................................................3668
54.2.1.4
pata_cs0, pata_cs1, pata_da2, pata_da1, pata_da0 (out)........................................................3668
54.2.1.5
pata_dmarq (in)......................................................................................................................3669
54.2.1.6
pata_dmack (out)....................................................................................................................3669
54.2.1.7
pata_intrq (in).........................................................................................................................3669
54.2.1.8
pata_iordy (in)........................................................................................................................3669
54.2.1.9
pata_data[15:0] (in/out-tristate).............................................................................................3669
54.2.1.10
pata_buffer_en.......................................................................................................................3669
PATA Bus Timing.....................................................................................................................................3670
54.2.2.1
Timing Parameters.................................................................................................................3670
54.2.2.2
PIO Mode Timing..................................................................................................................3671
54.2.2.2.1
PIO Read Mode Timing..................................................................................3671
54.2.2.2.2
PIO Write Mode Timing.................................................................................3672
54.2.2.3
Timing in Multi-word DMA (MDMA) Mode.......................................................................3673
54.2.2.4
Timing for Ultra DMA (UDMA) Data In-Transfers..............................................................3674
54.2.2.5
Timing for UDMA Data Out-transfers..................................................................................3676
Functional Description..................................................................................................................................................3678
54.3.1
Resetting the PATA Bus............................................................................................................................3678
54.3.2
Programming PATA Bus Timing and iordy_en........................................................................................3678
54.3.3
Access to PATA Bus in PIO Mode............................................................................................................3679
54.3.4
Receiving Data from PATA Bus in DMA Mode.......................................................................................3679
54.3.5
Transmitting Data to PATA Bus in DMA Mode.......................................................................................3681
Initialization and Application of PATA........................................................................................................................3682
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Title
Page
Programmable Registers...............................................................................................................................................3682
54.5.1
Time Off register (PATA_TIME_OFF)....................................................................................................3685
54.5.2
Time On register (PATA_TIME_ON).......................................................................................................3685
54.5.3
Time 1register (PATA_TIME_1)..............................................................................................................3686
54.5.4
Time 2W register (PATA_TIME_2W)......................................................................................................3686
54.5.5
Time 2R register (PATA_TIME_2R)........................................................................................................3686
54.5.6
Time AX register (PATA_TIME_AX)......................................................................................................3687
54.5.7
Time PIO RDX register (PATA_TIME_PIO_RDX).................................................................................3687
54.5.8
Time 4 register (PATA_TIME_4).............................................................................................................3688
54.5.9
Time 9 register (PATA_TIME_9).............................................................................................................3688
54.5.10
Time M register (PATA_TIME_M)..........................................................................................................3688
54.5.11
Time JN register (PATA_TIME_JN)........................................................................................................3689
54.5.12
Time D register (PATA_TIME_D)............................................................................................................3689
54.5.13
Time K register (PATA_TIME_K)............................................................................................................3690
54.5.14
Time ACK register (PATA_TIME_ACK)................................................................................................3690
54.5.15
Time ENV register (PATA_TIME_ENV).................................................................................................3690
54.5.16
Time RPX register (PATA_TIME_RPX)..................................................................................................3691
54.5.17
Time ZAH register (PATA_TIME_ZAH).................................................................................................3691
54.5.18
Time MLIX register (PATA_TIME_MLIX).............................................................................................3692
54.5.19
Time DVH register (PATA_TIME_DVH)................................................................................................3692
54.5.20
Time DZFS register (PATA_TIME_DZFS)..............................................................................................3692
54.5.21
Time DVS register (PATA_TIME_DVS).................................................................................................3693
54.5.22
Time CVH register (PATA_TIME_CVH)................................................................................................3693
54.5.23
Time SS register (PATA_TIME_SS)........................................................................................................3694
54.5.24
Time CYC register (PATA_TIME_CYC).................................................................................................3694
54.5.25
FIFO Data register 32-bit (PATA_FIFO_DATA_32)...............................................................................3694
54.5.26
FIFO Data register 16-bit (PATA_FIFO_DATA_16)...............................................................................3695
54.5.27
FIFO FILL register (PATA_FIFO_FILL).................................................................................................3695
54.5.28
PATA interface control register (PATA_CONTROL)..............................................................................3696
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54.5.29
Interrupt pending register (PATA_INTERRUPT_PENDING).................................................................3697
54.5.30
Interrupt enable register (PATA_INTERRUPT_ENABLE).....................................................................3698
54.5.31
Interrupt clear register (PATA_INTERRUPT_CLEAR)...........................................................................3698
54.5.32
FIFO ALARM register (PATA_FIFO_ALARM).....................................................................................3699
54.5.33
Drive Registers Connected to PATA Bus..................................................................................................3699
Chapter 55
Power Fail Detector (PFD)
55.1
Introduction ..................................................................................................................................................................3701
55.1.1
Overview....................................................................................................................................................3701
55.1.1.1
55.2
55.3
Assumptions ..........................................................................................................................3702
55.1.2
Features......................................................................................................................................................3702
55.1.3
Modes of Operation...................................................................................................................................3702
Functional Description..................................................................................................................................................3705
55.2.1
Resistance Ladder......................................................................................................................................3705
55.2.2
Detection Inverter......................................................................................................................................3705
55.2.3
Brown-Out Detection.................................................................................................................................3705
55.2.4
Pulse Stretcher/Output Buffer....................................................................................................................3706
55.2.5
DSM Circuitry............................................................................................................................................3706
Initialization/Application Information..........................................................................................................................3706
Chapter 56
PL301 4x1 AXI Arbiter (PLARB1)
56.1
Overview.......................................................................................................................................................................3707
56.1.1
System Connectivity..................................................................................................................................3708
56.1.2
Features......................................................................................................................................................3708
56.1.3
Modes and Operations...............................................................................................................................3709
56.2
External Signals............................................................................................................................................................3709
56.3
Programmable Registers...............................................................................................................................................3709
56.3.1
PLARB1 AR Programmable RR Arbitration Configuration for MI0 (PLARB1_RAC_MI0)..................3710
56.3.2
PLARB1 AW Programmable RR Arbitration Configuration for MI0 (PLARB1_WAC_MI0)................3711
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Title
Page
56.3.3
PLARB1 Configuration Register 0 (PLARB1_CR)..................................................................................3712
56.3.4
PLARB1 Configuration Register 1 (PLARB1_CR)..................................................................................3713
56.3.5
PLARB1 Configuration Register n (PLARB1_CRn)................................................................................3713
56.3.6
PLARB1 Peripheral ID Register 0 (PLARB1_PID0)................................................................................3714
56.3.7
PLARB1 Peripheral ID Register 1 (PLARB1_PID1)................................................................................3714
56.3.8
PLARB1 Peripheral ID Register 2 (PLARB1_PID2)................................................................................3715
56.3.9
PLARB1 Peripheral ID Register 3 (PLARB1_PID3)................................................................................3715
56.3.10
PLARB1 ID Register 0 (PLARB1_ID0)...................................................................................................3716
56.3.11
PLARB1 ID Register 1 (PLARB1_ID1)...................................................................................................3716
56.3.12
PLARB1 ID Register 2 (PLARB1_ID2)...................................................................................................3716
56.3.13
PLARB1 ID Register 3 (PLARB1_ID3)...................................................................................................3717
Functional Description..................................................................................................................................................3717
56.4.1
Normal Mode.............................................................................................................................................3717
56.4.2
Operations..................................................................................................................................................3717
56.4.2.1
Sparse Connect.......................................................................................................................3718
56.4.2.2
Memory region mapping........................................................................................................3719
56.4.2.3
Cyclic Dependency Avoidance Scheme (CDAS)..................................................................3719
56.4.2.3.1
56.4.2.4
Arbitration Scheme................................................................................................................3720
56.4.2.5
Arbitration Options Specific to the PLARB1 Arbiter............................................................3720
56.4.2.5.1
56.4.3
Single Slave Scheme.......................................................................................3719
Programmable Round Robin (Prog_RR) Scheme..........................................3721
Various Configuration Options..................................................................................................................3722
56.4.3.1
SI Configuration.....................................................................................................................3722
56.4.3.2
MI Configuration...................................................................................................................3722
56.4.4
Clocks.........................................................................................................................................................3722
56.4.5
Interrupts....................................................................................................................................................3723
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Chapter 57
PL301 2x2 Arbiter (PLARB2)
57.1
Overview.......................................................................................................................................................................3725
57.1.1
Features......................................................................................................................................................3726
57.1.2
Modes and Operations...............................................................................................................................3726
57.2
External Signals............................................................................................................................................................3727
57.3
Programmable Registers...............................................................................................................................................3727
57.4
57.3.1
PLARB2 AR Programmable RR Arbitration Configuration for MI0 (PLARB2_RAC_MI0)..................3728
57.3.2
PLARB2 AW Programmable RR Arbitration Configuration for MIn (PLARB2_WAC_MIn)................3729
57.3.3
PLARB2 AR Programmable RR Arbitration Configuration for MI1 (PLARB2_RAC_MI1)..................3730
57.3.4
PLARB2 Configuration Register 0 (PLARB2_CR0)................................................................................3730
57.3.5
PLARB2 Configuration Register 1 (PLARB2_CR0)................................................................................3731
57.3.6
PLARB2 Configuration Register n (PLARB2_CRn)................................................................................3732
57.3.7
PLARB2 Peripheral ID Register 0-3 (PLARB2_PID0-3).........................................................................3733
57.3.8
PLARB2 ID Registers 0-3 (PLARB2_ID0-3)...........................................................................................3733
Functional Description..................................................................................................................................................3734
57.4.1
Normal Mode.............................................................................................................................................3734
57.4.2
Low Power Modes.....................................................................................................................................3734
57.4.3
Operations..................................................................................................................................................3734
57.4.3.1
Sparse Connect.......................................................................................................................3734
57.4.3.2
Memory Region Mapping......................................................................................................3735
57.4.3.3
Cyclic Dependency Avoidance Scheme (CDAS)..................................................................3736
57.4.3.3.1
57.4.3.4
Arbitration Scheme................................................................................................................3737
57.4.3.5
Arbitration Options Specific to the PLARB2 Arbiter............................................................3737
57.4.3.5.1
57.4.4
Single Slave Scheme.......................................................................................3736
Programmable Round Robin (Prog_RR) Scheme..........................................3738
Various Configuration Options..................................................................................................................3739
57.4.4.1
SI Configuration.....................................................................................................................3739
57.4.4.2
MI Configuration...................................................................................................................3739
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Title
Page
57.4.5
Clocks.........................................................................................................................................................3739
57.4.6
Interrupts....................................................................................................................................................3740
Chapter 58
Power On Reset (POR)
58.1
Overview.......................................................................................................................................................................3741
58.2
Features.........................................................................................................................................................................3742
58.3
Mode of Operation........................................................................................................................................................3742
58.4
External Signal Description..........................................................................................................................................3743
58.5
58.6
58.4.1
Detailed Signal Descriptions......................................................................................................................3743
58.4.2
por_b - Power On Reset Signal..................................................................................................................3743
58.4.3
VDD - Power Supply.................................................................................................................................3743
58.4.4
VSS - Power Ground .................................................................................................................................3743
Functional Description..................................................................................................................................................3745
58.5.1
Recognition Circuit ...................................................................................................................................3745
58.5.2
Pulse Latch.................................................................................................................................................3745
58.5.3
Brown-Out Detector...................................................................................................................................3745
58.5.4
POR Pulse Stretcher...................................................................................................................................3746
58.5.5
Output Buffer.............................................................................................................................................3746
Initialization/Application Information..........................................................................................................................3746
Chapter 59
Pulse Width Modulation (PWM)
59.1
Overview.......................................................................................................................................................................3747
59.2
Signal Description.........................................................................................................................................................3749
59.2.1
59.3
External Signals.........................................................................................................................................3749
Functional Description..................................................................................................................................................3749
59.3.1
Operation....................................................................................................................................................3749
59.3.1.1
Clocks.....................................................................................................................................3750
59.3.1.2
FIFO.......................................................................................................................................3750
59.3.1.3
Rollover and Compare Event.................................................................................................3751
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Title
Page
59.3.1.4
Low Power Mode Behavior...................................................................................................3751
59.3.1.5
Debug Mode Behavior...........................................................................................................3752
Programmable Registers...............................................................................................................................................3752
59.4.1
PWM Control Register (PWMx_PWMCR)...............................................................................................3753
59.4.2
PWM Status Register (PWMx_PWMSR)..................................................................................................3755
59.4.3
PWM Interrupt Register (PWMx_PWMIR)..............................................................................................3756
59.4.4
PWM Sample Register (PWMx_PWMSAR)............................................................................................3757
59.4.5
PWM Period Register (PWMx_PWMPR).................................................................................................3758
59.4.6
PWM Counter Register (PWMx_PWMCNR)...........................................................................................3758
Chapter 60
ROM Controller with Patch (ROMC)
60.1
Introduction ..................................................................................................................................................................3761
60.1.1
Overview....................................................................................................................................................3761
60.1.2
Features......................................................................................................................................................3762
60.1.3
Modes of Operation...................................................................................................................................3762
60.1.3.1
60.2
Memory Map................................................................................................................................................................3763
60.2.1
60.3
Low Power Modes.................................................................................................................3763
ROM Memory Map in detail.....................................................................................................................3764
Functional Description..................................................................................................................................................3765
60.3.1
60.3.2
ROM Controller (ROMC) Functional Description....................................................................................3765
60.3.1.1
Functionality overview..........................................................................................................3765
60.3.1.2
ROMC Architecture Diagram................................................................................................3765
ROMC Functional Description..................................................................................................................3766
60.3.2.1
ROMC Disabling...................................................................................................................3766
60.3.2.2
ROMC Event Priority............................................................................................................3766
60.3.2.3
Data Fixing.............................................................................................................................3767
60.3.2.4
Opcode Patching....................................................................................................................3767
60.3.2.4.1
60.3.2.5
Typical Software Response to Opcode Patch.................................................3769
External Boot Feature............................................................................................................3770
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60.3.2.6
60.4
Title
Page
Alternate Masters and ROMC................................................................................................3770
Programmable Registers...............................................................................................................................................3770
60.4.1
ROMC Data Registers (ROMC_ROMPATCHnD)...................................................................................3772
60.4.2
ROMC Control Register (ROMC_ROMPATCHCNTL)..........................................................................3773
60.4.3
ROMC Enable Register High (ROMC_ROMPATCHENH).....................................................................3774
60.4.4
ROMC Enable Register Low (ROMC_ROMPATCHENL)......................................................................3775
60.4.5
ROMC Address Registers (ROMC_ROMPATCHnA).............................................................................3776
60.4.6
ROMC Status Register (ROMC_ROMPATCHSR)..................................................................................3777
Chapter 61
Run-Time Integrity Checker (RTIC)
61.1
Overview.......................................................................................................................................................................3779
61.2
Features.........................................................................................................................................................................3779
61.2.1
Modes of Operation...................................................................................................................................3779
Chapter 62
SAHARA Security Accelerator (SAHARA)
62.1
Overview.......................................................................................................................................................................3781
62.2
Features.........................................................................................................................................................................3782
62.2.1
Modes of Operation...................................................................................................................................3783
62.2.1.1
BATCH Mode-Overview.......................................................................................................3783
62.2.1.2
DEDICATED Mode-Overview.............................................................................................3783
62.2.1.3
DEBUG Mode-Overview......................................................................................................3784
Chapter 63
Serial Advanced Technology Attachment Controller (SATA)
63.1
63.2
Introduction...................................................................................................................................................................3785
63.1.1
Features......................................................................................................................................................3785
63.1.2
System Overview.......................................................................................................................................3786
Block Overview............................................................................................................................................................3786
63.2.1
Block Diagram...........................................................................................................................................3786
63.2.2
SATA Block Transfer Hierarchy...............................................................................................................3788
63.2.3
Standards Compliance................................................................................................................................3789
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Section Number
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Title
Page
Architecture...................................................................................................................................................................3789
63.3.1
Architecture Overview...............................................................................................................................3789
63.3.2
Bus Interface Unit......................................................................................................................................3790
63.3.2.1
AHB Slave Bus GIF Interface...............................................................................................3791
63.3.2.2
Register Read Multiplexer.....................................................................................................3792
63.3.2.3
AHB Master Bus/GIF Interface.............................................................................................3792
63.3.2.4
DMA Arbiter..........................................................................................................................3794
63.3.3
Generic Registers (GCSR).........................................................................................................................3794
63.3.4
Port.............................................................................................................................................................3794
63.3.4.1
Port DMA...............................................................................................................................3795
63.3.4.2
Port Registers.........................................................................................................................3796
63.3.4.3
Transport Layer......................................................................................................................3796
63.3.4.4
63.3.4.5
63.3.4.3.1
Transport Layer FIS Reception.......................................................................3798
63.3.4.3.2
Transport Layer FIS Transmission.................................................................3798
63.3.4.3.3
Error Handling................................................................................................3799
63.3.4.3.4
Receive/Transmit FIFO (Rx/TxFIFO)............................................................3800
Transport Check (TCHK)......................................................................................................3801
63.3.4.4.1
Transport State Machine (TSM).....................................................................3802
63.3.4.4.2
Sync Module (APP_ASIC).............................................................................3803
Link Layer..............................................................................................................................3803
63.3.4.5.1
Link Layer Features........................................................................................3806
63.3.4.5.2
User-Defined Status and Control....................................................................3806
63.3.4.5.3
PHY Initialization Details...............................................................................3807
63.3.4.5.4
63.3.4.6
63.3.4.5.3.1
Link Layer Tx OOB Initialization Sequence Details.............3808
63.3.4.5.3.2
Link Layer Tx OOB Sequence Generation............................3811
63.3.4.5.3.3
Link Layer Rx OOB Sequence Detection..............................3813
Link Layer Power Management Details.........................................................3814
Port Power Control Module...................................................................................................3816
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63.3.5
Title
Page
Operation Details.......................................................................................................................................3820
63.3.5.1
Data Transfer..........................................................................................................................3820
63.3.5.1.1
ATA DMA Read.............................................................................................3820
63.3.5.1.2
ATA DMA Write............................................................................................3821
63.3.5.1.3
Native Queued Command (NCQ) Transfers...................................................3821
63.3.5.1.4
PIO Transfer....................................................................................................3822
63.3.5.1.5
Transfer Size...................................................................................................3822
63.3.5.2
Power Management Operations.............................................................................................3822
63.3.5.3
Hot Plug.................................................................................................................................3823
63.3.5.3.1
Native Hot Plug...............................................................................................3824
63.3.5.4
Port Multiplier Support..........................................................................................................3824
63.3.5.5
Interrupts................................................................................................................................3824
63.3.5.5.1
First Tier (SATA_IS Register)........................................................................3825
63.3.5.5.2
Second Tier (SATA_P 0IS Registers)............................................................3825
63.3.5.6
PHY and Link Control...........................................................................................................3826
63.3.5.7
Reset Conditions....................................................................................................................3826
63.3.5.7.1
63.3.5.8
System Reset...................................................................................................3826
Global Reset...........................................................................................................................3826
63.3.5.8.1
Port Reset (COMRESET)...............................................................................3827
63.3.5.8.2
Software Reset................................................................................................3828
63.3.5.9
Interface Speed Support.........................................................................................................3828
63.3.5.10
Staggered Spin-up..................................................................................................................3828
63.3.5.11
Asynchronous Notification....................................................................................................3829
63.3.5.12
BIST Operation......................................................................................................................3830
63.3.5.13
Loopback Responder..............................................................................................................3831
63.3.5.13.1
Loopback Initiator...........................................................................................3832
63.3.5.13.1.1 Far-end retimed......................................................................3833
63.3.5.13.1.2 Far-end analog........................................................................3834
63.3.5.13.1.3 Near-end analog......................................................................3834
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Page
63.3.5.13.1.4 Far-end transmit only.............................................................3834
63.3.5.14
63.4
63.5
63.6
Programming.................................................................................................................................................................3836
63.4.1
Firmware Specific Initialization.................................................................................................................3836
63.4.2
System software Specific Initialization......................................................................................................3837
Software Manipulation of Port DMA...........................................................................................................................3838
63.5.1
Start (SATA_P 0CMD[ST])......................................................................................................................3839
63.5.2
FIS Receive Enable (SATA_P 0CMD[FRE])...........................................................................................3839
Register Descriptions....................................................................................................................................................3840
63.6.1
63.7
Command Completion Coalescing........................................................................................3835
Register Overview......................................................................................................................................3840
63.6.1.1
Register Basics:......................................................................................................................3840
63.6.1.2
Reserved Locations................................................................................................................3840
Programmable Registers...............................................................................................................................................3841
63.7.1
HBA Capabilites Register (SATA_CAP)..................................................................................................3843
63.7.2
Global HBA Control Register (SATA_GHC)...........................................................................................3845
63.7.3
Interrupt Status Register (SATA_IS).........................................................................................................3846
63.7.4
Ports Implemented Register (SATA_PI)...................................................................................................3846
63.7.5
AHCl Version Register (SATA_VS).........................................................................................................3847
63.7.6
Command Completion Coalescing Control (SATA_CCC_CTL).............................................................3848
63.7.7
Command Completion Coalescing Ports (SATA_CCC_PORTS).............................................................3849
63.7.8
HBA Capabilities Extended Register (SATA_CAP2)...............................................................................3850
63.7.9
BIST Activate FIS Register (SATA_BISTAFR).......................................................................................3850
63.7.10
BIST Control Register (SATA_BISTCR).................................................................................................3852
63.7.11
BIST FIS Count Register (SATA_BISTFCTR)........................................................................................3855
63.7.12
BIST Status Register (SATA_BISTSR)....................................................................................................3855
63.7.13
OOB Register (SATA_OOBR)..................................................................................................................3856
63.7.14
General Purpose Control Register (SATA_GPCR)...................................................................................3857
63.7.15
General Purpose Status Register (SATA_GPSR)......................................................................................3857
63.7.16
Timer 1-ms Register (SATA_TIMER1MS)..............................................................................................3858
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Page
63.7.17
Global Parameter 1 Register (SATA_GPARAM1R)................................................................................3859
63.7.18
Global Parameter 1 Register (SATA_GPARAM2R)................................................................................3861
63.7.19
Port Parameter Register (SATA_PPARAMR)..........................................................................................3862
63.7.20
Test Register (SATA_TESTR)..................................................................................................................3863
63.7.21
Version Register (SATA_VERSIONR).....................................................................................................3865
63.7.22
Port0 Command List Base Address Register (SATA_P0CLB).................................................................3865
63.7.23
Port0 FIS Base Address Register (SATA_P0FB)......................................................................................3866
63.7.24
Port0 Interrupt Status Register (SATA_P0IS)...........................................................................................3867
63.7.25
Port0 Interrupt Enable Register (SATA_P0IE).........................................................................................3870
63.7.26
Port0 Command Register (SATA_P0CMD)..............................................................................................3873
63.7.27
Port0 Task File Data Register (SATA_P0TFD)........................................................................................3877
63.7.28
Port0 Signature Register (SATA_P0SIG)..................................................................................................3877
63.7.29
Port0 Serial ATA Status Register (SATA_P0SSTS).................................................................................3878
63.7.30
Port0 Serial ATA Control {SControl} Register (SATA_P0SCTL)...........................................................3879
63.7.31
Port0 Serial ATA Error Register (SATA_P0SERR).................................................................................3880
63.7.32
Port0 Serial ATA Active Register (SATA_P0SACT)...............................................................................3882
63.7.33
Port0 Command Issue Register (SATA_P0CI).........................................................................................3883
63.7.34
Port0 Serial ATA Notification Register (SATA_P0SNTF).......................................................................3884
63.7.35
Port0 DMA Control Register (SATA_P0DMACR)..................................................................................3884
63.7.36
Port0 PHY Control Register (SATA_P0PHYCR).....................................................................................3886
63.7.37
Port0 PHY Status Register (SATA_P0PHYSR)........................................................................................3887
Chapter 64
Serial Advanced Technology Attachment PHY (SATA PHY)
64.1
Overview.......................................................................................................................................................................3889
64.1.1
General Product Description......................................................................................................................3889
64.1.1.1
64.1.2
64.2
System Overview...................................................................................................................3889
Features......................................................................................................................................................3889
Architecture...................................................................................................................................................................3891
64.2.1
Block Diagram...........................................................................................................................................3891
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64.2.2
64.3
Title
Page
Block Descriptions.....................................................................................................................................3892
Functional Description..................................................................................................................................................3895
64.3.1
Power Controls...........................................................................................................................................3895
64.3.1.1
Tx Power Controls.................................................................................................................3895
64.3.1.2
Rx Power Controls.................................................................................................................3896
64.3.1.3
Clock Module Power Controls...............................................................................................3897
64.3.1.4
Power-Up Sequences.............................................................................................................3897
64.3.1.5
64.3.1.4.1
Powering Up the Chip (Initial Power-Up)......................................................3898
64.3.1.4.2
Powering Up the Clock Module.....................................................................3898
64.3.1.4.3
Powering Up the Tx........................................................................................3899
64.3.1.4.4
Powering Up the Rx........................................................................................3899
Power-Down Sequences........................................................................................................3899
64.3.1.5.1
Powering Down the Rx...................................................................................3899
64.3.1.5.2
Powering Down the Tx...................................................................................3899
64.3.1.5.3
Powering Down the Clock Module.................................................................3900
64.3.2
Clock Module Operations..........................................................................................................................3900
64.3.3
Clock Inputs to the SATA2 PHY...............................................................................................................3902
64.3.4
64.3.3.1
mpll_prescale[1:0].................................................................................................................3902
64.3.3.2
Valid refclk Range and Formulaic MPLL Settings...............................................................3903
64.3.3.3
Clock Module Power Control................................................................................................3905
64.3.3.4
Presence of refclk Signal........................................................................................................3905
64.3.3.5
Power-On Reset.....................................................................................................................3905
64.3.3.6
Resistor Calibration................................................................................................................3906
Tx Operations.............................................................................................................................................3906
64.3.4.1
Recommended Tx Settings....................................................................................................3906
64.3.4.2
Tx Amplitude Control............................................................................................................3907
64.3.4.3
Tx Boost Control....................................................................................................................3907
64.3.4.4
Tx Far-End Amplitude...........................................................................................................3908
64.3.4.5
Tx Edge Rate Control............................................................................................................3908
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Section Number
64.3.5
64.4
64.6
Page
Rx Operations............................................................................................................................................3908
64.3.5.1
Recommended Rx Settings....................................................................................................3909
64.3.5.2
Loss of Signal Detection........................................................................................................3909
64.3.5.3
rx_dpll_mode[2:0].................................................................................................................3911
64.3.5.4
Rx Equalizer Settings.............................................................................................................3912
Control Registers..........................................................................................................................................................3913
64.4.1
64.5
Title
Register Fields............................................................................................................................................3913
64.4.1.1
Field Properties......................................................................................................................3914
64.4.1.2
Field Names...........................................................................................................................3914
64.4.1.3
Read/Modify/Write Operations..............................................................................................3914
Signal Descriptions.......................................................................................................................................................3915
64.5.1
Signal Descriptions Overview...................................................................................................................3915
64.5.2
Signal Descriptions Information................................................................................................................3917
64.5.2.1
Power Supply Signals............................................................................................................3917
64.5.2.2
Package I/O Signals...............................................................................................................3918
64.5.2.3
Per-Transceiver Control and Status Signals...........................................................................3920
64.5.2.4
Per-Transceiver Datapath Signals..........................................................................................3926
64.5.2.5
Common Signals....................................................................................................................3928
64.5.2.6
JTAG Interface Signals..........................................................................................................3938
64.5.2.7
Parallel CR Control Port Signals...........................................................................................3939
Timing and Specifications............................................................................................................................................3940
64.6.1
SATA2 PHY Implementation-Specific Timing.........................................................................................3940
64.6.1.1
Synchronous Tx Inputs..........................................................................................................3941
64.6.1.2
Synchronous Rx Outputs.......................................................................................................3942
64.6.1.3
Asynchronous Tx and Rx I/O................................................................................................3943
64.6.1.4
Control Register Bus Interface...............................................................................................3943
64.6.1.5
JTAG Interface Timing..........................................................................................................3944
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64.6.2
Title
Page
Silicon Testing...........................................................................................................................................3945
64.6.2.1
Boundary Scan Port...............................................................................................................3945
64.6.2.1.1
64.6.2.2
64.6.2.3
64.6.2.4
Per-Lane Block Diagram................................................................................3945
JTAG Interface Silicon Testing.............................................................................................3947
64.6.2.2.1
Interface Options.............................................................................................3947
64.6.2.2.2
Resets..............................................................................................................3947
64.6.2.2.3
IR Codes..........................................................................................................3947
64.6.2.2.4
ID Code...........................................................................................................3948
64.6.2.2.5
USER Code.....................................................................................................3948
64.6.2.2.6
Control Register Operations...........................................................................3948
64.6.2.2.7
JTAG Override Register (jtag_ovrd)..............................................................3949
Parallel CR Control Port Testing...........................................................................................3950
64.6.2.3.1
Addressing......................................................................................................3951
64.6.2.3.2
Register Write.................................................................................................3951
64.6.2.3.3
Register Read..................................................................................................3952
Diagnostic Features................................................................................................................3953
64.6.2.4.1
Loopback Functions........................................................................................3954
64.6.2.4.1.1
Rx-to-Tx Parallel Data Loopback..........................................3955
64.6.2.4.1.2
Tx-to-Rx Digital Serial Data Loopback.................................3955
64.6.2.4.1.3
Tx-to-Rx Serial Analog Loopback.........................................3955
64.6.2.4.1.4
Full Analog Loopback for In-Package ATE Test...................3956
64.6.2.4.2
Asynchronous Operation................................................................................3956
64.6.2.4.3
Byte Error Rate Tester....................................................................................3956
64.6.2.4.4
64.6.2.4.3.1
BERT Pattern Generator.........................................................3957
64.6.2.4.3.2
BERT Pattern Matcher and Error Counter.............................3957
Margining........................................................................................................3958
64.6.2.4.4.1
64.6.2.4.5
Phase Margining.....................................................................3959
Scope Function................................................................................................3961
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Section Number
Title
64.6.2.4.6
64.6.2.5
64.7
Page
Analog DC Test Capabilities..........................................................................3961
64.6.2.4.6.1
Analog Test Bus.....................................................................3962
64.6.2.4.6.2
10-Bit DAC............................................................................3964
64.6.2.4.6.3
10-Bit ADC............................................................................3964
64.6.2.4.7
Limit Testing...................................................................................................3964
64.6.2.4.8
Integrated Test Modes.....................................................................................3965
64.6.2.4.8.1
IDDQ Test Mode....................................................................3965
64.6.2.4.8.2
Bypass Test Mode..................................................................3966
64.6.2.4.8.3
Burn-In Test Mode.................................................................3966
64.6.2.4.9
Burn-In Test Requirements.............................................................................3966
64.6.2.4.10
Temperature Sensor........................................................................................3966
ATE Testing...........................................................................................................................3968
clock Memory Map/Register Definition.......................................................................................................................3968
64.7.1
Creg Compare Upper Limit Register (clock_CRCMP_LT_LIMIT).........................................................3970
64.7.2
Creg Compare Lower Limit Register (clock_CRCMP_GT_LIMIT)........................................................3970
64.7.3
Creg Compare Mask Register (clock_CRCMP_MASK)..........................................................................3971
64.7.4
Creg Compare Control Register (clock_CRCMP_CTL)...........................................................................3971
64.7.5
Creg Compare Status Register (clock_CRCMP_STAT)...........................................................................3972
64.7.6
Scope Sample Count Register (clock_SCOPE_SAMPLES).....................................................................3973
64.7.7
Scope Count Result Register (clock_SCOPE_COUNT)...........................................................................3973
64.7.8
DAC Control Register (clock_DAC_CTL)...............................................................................................3974
64.7.9
Resistor Tuning Control Register (clock_RTUNE_CTL).........................................................................3975
64.7.10
ADC Output Register (clock_ADC_OUT)................................................................................................3976
64.7.11
Spread Spectrum Phase Register (clock_SS_PHASE)..............................................................................3976
64.7.12
JTAG Chip ID (High Bits) Register (clock_CHIP_ID_HI).......................................................................3977
64.7.13
JTAG Chip ID (Low Bits) Register (clock_CHIP_ID_LOW)..................................................................3977
64.7.14
Frequency Status Register (clock_FREQ_STAT).....................................................................................3978
64.7.15
Control Status Register (clock_CTL_STAT)............................................................................................3979
64.7.16
Level Status Register (clock_LVL-STAT)................................................................................................3980
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Title
Page
64.7.17
Creg Status Register (clock_CREG_STAT)..............................................................................................3980
64.7.18
Frequency Override Register (clock_FREW_OVRD)..............................................................................3981
64.7.19
Control Override Register (clock_CTL_OVRD).......................................................................................3982
64.7.20
Level Override Register (clock_LVL_OVRD)..........................................................................................3983
64.7.21
Creg Override Register (clock_CREG_OVRD)........................................................................................3984
64.7.22
MPLL Control Register (clock_MPLL_CTL)...........................................................................................3985
64.7.23
MPLL Test Register (clock_MPLL_TEST)..............................................................................................3986
64.7.24
Spread Spectrum Frequency Register (clock_SS_FREQ).........................................................................3987
64.7.25
Clock Select Status Register (clock_SEL_STAT).....................................................................................3988
64.7.26
Clock Select Override Register (clock_SEL_OVRD)...............................................................................3989
64.7.27
Reset Register (clock_RESET)..................................................................................................................3989
lanej Memory Map/Register Definition........................................................................................................................3990
64.8.1
Transmit Input Status Register (lane0_TX_STAT)...................................................................................3993
64.8.2
Receiver Input Status Register (lane0_RX_STAT)...................................................................................3994
64.8.3
Output Status Register (lane0_OUT_STAT).............................................................................................3995
64.8.4
Transmit Input Override Register (lane0_TX_OVRD).............................................................................3996
64.8.5
Receive Input Override Register (lane0_RX_OVRD)...............................................................................3997
64.8.6
Output Override Register (lane0_OUT_OVRD).......................................................................................3998
64.8.7
Debug Control Register (lane0_DBG_CTL).............................................................................................3998
64.8.8
Pattern Generator Control Register (lane0_PG_CTL)...............................................................................4000
64.8.9
Pattern Matcher Control Register (lane0_PM_CTL).................................................................................4001
64.8.10
Pattern Matcher Error Register (lane0_PM_ERR)....................................................................................4002
64.8.11
DPLL Phase Register (lane0_DPLL_PHASE)..........................................................................................4002
64.8.12
DPLL Frequency Register (lane0_DPLL_FREQ).....................................................................................4003
64.8.13
Scope Control Register (lane0_SCOPE_CTL)..........................................................................................4004
64.8.14
Receiver Control Register (lane0_RX_CTL)............................................................................................4004
64.8.15
Receiver Debug Register (lane0_RX_DBG).............................................................................................4005
64.8.16
Receive Analog Control Register (lane0_RX_ANA_CONTROL)...........................................................4007
64.8.17
Receive ATB Register (lane0_RX_ANA_ATB).......................................................................................4007
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Section Number
Title
Page
64.8.18
Rx PLL Programming 2 Register (lane0_PLL_PRG2).............................................................................4008
64.8.19
Rx PLL Programming 1 Register (lane0_PLL_PRG1).............................................................................4009
64.8.20
Rx PLL Measurement Register (lane0_PLL_PRG3).................................................................................4010
64.8.21
Transmit ATB 1 Control Register (lane0_TX_ANA_ATBSEL1)............................................................4011
64.8.22
Transmit ATB 2 Control Register (lane0_TX_ANA_ATBSEL2)............................................................4012
64.8.23
Transmit Analog Control Register (lane0_TX_ANA_CONTROL)..........................................................4013
Chapter 65
Security Controller (SCC)
65.1
Introduction ..................................................................................................................................................................4015
65.1.1
Overview....................................................................................................................................................4015
65.1.2
Features......................................................................................................................................................4017
Chapter 66
Smart Direct Memory Access Controller (SDMA)
66.1
Introduction...................................................................................................................................................................4019
66.1.1
Overview....................................................................................................................................................4019
66.1.2
Features......................................................................................................................................................4021
66.2
Functional Description..................................................................................................................................................4023
66.3
SDMA Core..................................................................................................................................................................4025
66.3.1
SDMA Core Structure................................................................................................................................4025
66.3.2
Program Control Unit (PCU).....................................................................................................................4028
66.3.3
66.4
66.3.2.1
Instruction Types....................................................................................................................4028
66.3.2.2
PCU States.............................................................................................................................4029
SDMA Core Memory.................................................................................................................................4032
Scheduler.......................................................................................................................................................................4032
66.4.1
Primary Functions......................................................................................................................................4032
66.4.2
Channels and DMA Requests....................................................................................................................4033
66.4.2.1
Channels.................................................................................................................................4033
66.4.2.2
DMA Requests.......................................................................................................................4033
66.4.2.3
Mapping from DMA Requests to Channels and Priorities....................................................4033
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66.4.3
66.4.4
66.5
Title
Page
Scheduler Functional Description..............................................................................................................4033
66.4.3.1
Scheduler Overview...............................................................................................................4033
66.4.3.2
DMA Requests Scanning.......................................................................................................4035
66.4.3.3
Mapping DMA Requests to Pending Channels.....................................................................4035
66.4.3.4
Channel Overflow..................................................................................................................4039
66.4.3.5
Runnable Channels Evaluation..............................................................................................4039
66.4.3.6
Next Channel Decision Tree..................................................................................................4041
66.4.3.7
Scheduler State Diagram........................................................................................................4043
66.4.3.8
Scheduler Pipeline Timing Diagram......................................................................................4045
66.4.3.9
Channel-DMA Request Mapping..........................................................................................4045
66.4.3.10
Examples: How to Start a Channel........................................................................................4045
Context Switching......................................................................................................................................4046
66.4.4.1
Context Switch Modes...........................................................................................................4047
66.4.4.2
Context Switch Procedure......................................................................................................4048
66.4.4.3
Context Map in Memory........................................................................................................4049
Functional Units............................................................................................................................................................4049
66.5.1
66.5.2
CRC Calculation Unit................................................................................................................................4049
66.5.1.1
CRC Structure........................................................................................................................4050
66.5.1.2
CRC Data Processing.............................................................................................................4050
66.5.1.3
CRC Registers........................................................................................................................4051
66.5.1.4
CRC Summary.......................................................................................................................4051
Burst DMA Unit.........................................................................................................................................4052
66.5.2.1
Burst DMA Structure.............................................................................................................4053
66.5.2.2
Burst DMA Registers.............................................................................................................4054
66.5.2.3
Burst DMA Data Transfers....................................................................................................4055
66.5.2.3.1
Data Retrieval from the ARM platform Memory...........................................4055
66.5.2.3.2
Storing Data Into the ARM platform Memory...............................................4056
66.5.2.3.3
Transferring Data Between Two ARM platform Memory Locations-Burst
DMA Unit.......................................................................................................4056
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66.5.3
Title
Page
Peripheral DMA Unit.................................................................................................................................4056
66.5.3.1
Peripheral DMA Structure.....................................................................................................4057
66.5.3.2
Peripheral DMA Registers.....................................................................................................4058
66.5.3.3
Peripheral DMA Data Transfers............................................................................................4059
66.5.3.3.1
Data Retrieval from the ARM platform Memory or Peripheral.....................4059
66.5.3.3.2
Storing Data into the ARM platform Memory or Peripheral..........................4059
66.5.3.3.3
Transferring Data Between Two ARM platform Memory LocationsPeripheral DMA Unit......................................................................................4060
66.6
SDMA Security Support...............................................................................................................................................4060
66.6.1
Locked Mode.............................................................................................................................................4060
66.7
OnCE and PCU Debug States.......................................................................................................................................4061
66.8
SDMA Clocks and Low Power Modes.........................................................................................................................4063
66.8.1
Clock Gating and Low Power Modes........................................................................................................4064
66.8.1.1
Coarse Clock Gating..............................................................................................................4064
66.8.1.2
Refined Clock Gating.............................................................................................................4065
66.8.1.3
Low Power Modes and User Control.....................................................................................4065
66.8.1.4
66.8.2
66.9
66.8.1.3.1
SLEEP Mode..................................................................................................4066
66.8.1.3.2
RUN Mode......................................................................................................4066
66.8.1.3.3
DEBUG Mode................................................................................................4067
Stop Mode Response..............................................................................................................4067
Reset...........................................................................................................................................................4067
Software Interface.........................................................................................................................................................4067
66.10 Initialization Information..............................................................................................................................................4068
66.10.1
Hardware Reset..........................................................................................................................................4068
66.10.2
Channel Script Execution...........................................................................................................................4069
66.10.3
Initialization and Script Execution Setup Sequence..................................................................................4069
66.11 SDMA Programming Model.........................................................................................................................................4070
66.11.1
State and Registers Per Channel................................................................................................................4070
66.11.2
General Purpose Registers.........................................................................................................................4071
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66.11.3
Title
Page
Functional Unit State.................................................................................................................................4071
66.11.3.1
Program Counter Register (PC).............................................................................................4071
66.11.3.2
Flags.......................................................................................................................................4071
66.11.3.3
Return Program Counter (RPC).............................................................................................4072
66.11.3.4
Loop Mode Start Program Counter (SPC).............................................................................4072
66.11.3.5
Loop Mode End Program Counter (EPC)..............................................................................4073
66.11.4
Context Switching-Programming..............................................................................................................4073
66.11.5
Address Space............................................................................................................................................4074
66.11.5.1
Instruction Memory Map.......................................................................................................4075
66.11.5.2
Data Memory Map.................................................................................................................4075
66.12 SDMA Initialization......................................................................................................................................................4077
66.12.1
Hardware Reset-SDMA.............................................................................................................................4077
66.12.2
Standard Boot Sequence............................................................................................................................4078
66.12.3
User-Defined Boot Sequence.....................................................................................................................4078
66.12.4
Script Loading and Context Initialization..................................................................................................4078
66.13 Instruction Description..................................................................................................................................................4079
66.13.1
Scheduling Instructions..............................................................................................................................4079
66.13.2
Conditional Branch Instructions................................................................................................................4080
66.13.3
Unconditional Jump Instructions...............................................................................................................4080
66.13.4
Subroutine Return Instructions..................................................................................................................4080
66.13.5
Loop Instruction.........................................................................................................................................4081
66.13.6
Miscellaneous Instructions.........................................................................................................................4081
66.13.7
Logic Instructions......................................................................................................................................4081
66.13.8
Arithmetic Instructions..............................................................................................................................4082
66.13.9
Compare Instructions.................................................................................................................................4082
66.13.10
Test Instructions.........................................................................................................................................4082
66.13.11
Byte Permutation Instructions....................................................................................................................4083
66.13.12
Bit Shift Instructions..................................................................................................................................4083
66.13.13
Bit Manipulation Instructions....................................................................................................................4083
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66.13.14
SDMA Memory Access Instructions.........................................................................................................4083
66.13.15
Functional Unit Instructions.......................................................................................................................4084
66.13.16
Illegal Instructions......................................................................................................................................4084
66.13.17
Debug Instructions.....................................................................................................................................4085
66.14 Functional Units Programming Model.........................................................................................................................4085
66.14.1
Burst DMA Unit Programming..................................................................................................................4086
66.14.1.1
Memory Source Address Register (MSA).............................................................................4087
66.14.1.2
Memory Destination Address Register (MDA).....................................................................4087
66.14.1.3
Memory Data Buffer Register (MD).....................................................................................4088
66.14.1.4
State Register (MS)................................................................................................................4088
66.14.1.5
Burst DMA Write (stf)...........................................................................................................4090
66.14.1.6
Burst DMA Read (ldf)...........................................................................................................4093
66.14.1.7
Prefetch/Flush and Auto-Flush Management-Burst DMA Unit............................................4094
66.14.1.8
Data Alignment and Endianness-Burst DMA Unit................................................................4096
66.14.1.9
66.14.1.8.1
Burst DMA in Read Mode..............................................................................4096
66.14.1.8.2
Burst DMA in Write Mode.............................................................................4097
66.14.1.8.3
Endianness-Burst DMA Unit..........................................................................4099
Burst DMA Unit Copy Mode.................................................................................................4099
66.14.1.10 Burst DMA Unit Error Management.....................................................................................4100
66.14.1.11 Conditional Yielding-Burst DMA Unit.................................................................................4102
66.14.2
Peripheral DMA Unit Programming..........................................................................................................4103
66.14.2.1
Peripheral Source Address Register (PSA)............................................................................4104
66.14.2.2
Peripheral Destination Address Register (PDA)....................................................................4105
66.14.2.3
Peripheral Data Register (PD)................................................................................................4105
66.14.2.4
Peripheral State Register (PS)................................................................................................4106
66.14.2.5
Peripheral DMA Write (stf)-Write Mode..............................................................................4107
66.14.2.6
Peripheral DMA Read (ldf)-Read Mode................................................................................4110
66.14.2.7
Peripheral DMA Unit Copy Mode.........................................................................................4111
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66.14.2.8
66.14.2.9
66.14.3
66.14.4
Title
Page
Error Management.................................................................................................................4111
66.14.2.8.1
Immediate Errors............................................................................................4112
66.14.2.8.2
Data Transfer Errors.......................................................................................4112
66.14.2.8.3
Read Error (First Phase)..................................................................................4113
66.14.2.8.4
Write Error and Read Error (Second Phase)...................................................4113
66.14.2.8.5
Copy Mode Errors...........................................................................................4114
66.14.2.8.6
Error Check Example......................................................................................4114
Peripheral DMA Unit Prefetch/Flush Management...............................................................4115
CRC Unit....................................................................................................................................................4115
66.14.3.1
Polynomial Register (CA)......................................................................................................4115
66.14.3.2
Accumulator Register (CS)....................................................................................................4116
66.14.3.3
Write Instruction (stf).............................................................................................................4117
66.14.3.4
Read Instruction (ldf).............................................................................................................4117
66.14.3.5
Operating Mode.....................................................................................................................4118
OnCE and Real-Time Debug.....................................................................................................................4119
66.14.4.1
Memory and Register Access................................................................................................4119
66.14.4.2
Hardware Breakpoints............................................................................................................4119
66.14.4.3
Watchpoints...........................................................................................................................4119
66.14.4.4
Software Breakpoints.............................................................................................................4120
66.14.4.5
Core Control...........................................................................................................................4120
66.15 The OnCE Controller....................................................................................................................................................4120
66.15.1
OnCE Commands......................................................................................................................................4120
66.15.2
Sending Commands to the OnCE Controller.............................................................................................4121
66.15.3
66.15.2.1
Using the JTAG Interface......................................................................................................4121
66.15.2.2
Using the ARM platform.......................................................................................................4122
66.15.2.3
Conflicts Between the JTAG and the ARM platform Accesses............................................4123
Executing a Command from the OnCE.....................................................................................................4124
66.15.3.1
Nature of the Commands.......................................................................................................4124
66.15.3.2
Execution Request..................................................................................................................4124
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66.15.4
66.15.5
Title
Page
Command Execution..............................................................................................................4125
Registers Descriptions................................................................................................................................4127
66.15.4.1
Event Cell Counter Register (ECOUNT)...............................................................................4127
66.15.4.2
Event Cell Address Registers (EAA or EAB).......................................................................4127
66.15.4.3
Event Cell Address Mask Register (EAM)............................................................................4128
66.15.4.4
Event Cell Data Register (ED)...............................................................................................4128
66.15.4.5
Event Cell Data Mask Register (EDM).................................................................................4128
66.15.4.6
Real Time Buffer Register (RTB)..........................................................................................4128
66.15.4.7
Event Control Register (ECTL).............................................................................................4129
66.15.4.8
Trace Buffer (TB)..................................................................................................................4129
66.15.4.9
OnCE Status Register (OSTAT)............................................................................................4129
JTAG Interface Requirements...................................................................................................................4130
66.15.5.1
TCK Speed Limitation...........................................................................................................4130
66.15.5.2
Synchronization Implementation...........................................................................................4130
66.15.5.3
JTAG Controller Start-Up Recommended Procedure...........................................................4132
66.16 Using the OnCE............................................................................................................................................................4132
66.16.1
Activating Clocks in Debug Mode.............................................................................................................4132
66.16.2
Getting the Current Status..........................................................................................................................4133
66.16.3
Methods of Entering Debug Mode.............................................................................................................4133
66.16.3.1
External Debug Request During Reset..................................................................................4133
66.16.3.2
Debug Request During Normal Activity...............................................................................4134
66.16.3.3
Software Breakpoint Instruction............................................................................................4134
66.16.3.4
Event Detection Unit Matching Condition............................................................................4134
66.16.4
Executing Instructions in Debug Mode.....................................................................................................4134
66.16.5
Command Sequences Examples................................................................................................................4135
66.16.5.1
Getting the SDMA Status......................................................................................................4135
66.16.5.2
Saving the Context.................................................................................................................4136
66.16.5.3
Restoring the Context.............................................................................................................4137
66.16.5.4
Accessing the Memory...........................................................................................................4138
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66.16.5.5
Resuming Program Execution...............................................................................................4138
66.16.5.6
Single Stepping in RAM........................................................................................................4139
66.16.5.7
Single Stepping in ROM........................................................................................................4139
66.16.6
OnCE Event Detection Unit.......................................................................................................................4140
66.16.7
Clock Gating and Reset..............................................................................................................................4141
66.16.8
66.16.7.1
Clocks.....................................................................................................................................4141
66.16.7.2
Resets.....................................................................................................................................4142
Real Time Features....................................................................................................................................4142
66.16.8.1
Trace Buffer...........................................................................................................................4142
66.16.8.2
Real Time Buffer...................................................................................................................4144
66.16.8.3
Emulation Pin.........................................................................................................................4144
66.16.8.4
Real-Time Debug Outputs.....................................................................................................4144
66.17 Instruction Set...............................................................................................................................................................4148
66.17.1
Instruction Encoding..................................................................................................................................4148
66.17.2
SDMA Instruction Set................................................................................................................................4150
66.17.2.1
ADD (Addition).....................................................................................................................4153
66.17.2.2
ADDI (Add with Immediate Value)......................................................................................4154
66.17.2.3
AND (Logical AND).............................................................................................................4155
66.17.2.4
ANDI (Logical AND with Immediate Value).......................................................................4156
66.17.2.5
ANDN (Logical AND NOT).................................................................................................4157
66.17.2.6
ANDNI (Logical AND with Negated Immediate Value)......................................................4158
66.17.2.7
ASR1 (Arithmetic Shift Right by 1 Bit)................................................................................4159
66.17.2.8
BCLRI1 (Bit Clear Immediate)..............................................................................................4159
66.17.2.9
BDF (Conditional Branch if Destination Fault).....................................................................4160
66.17.2.10 BF (Conditional Branch if False)...........................................................................................4161
66.17.2.11 BSETI (Bit Set Immediate)....................................................................................................4163
66.17.2.12 BSF (Conditional Branch if Source Fault).............................................................................4164
66.17.2.13 BT (Conditional Branch if True)...........................................................................................4165
66.17.2.14 BTSTI (Bit Test immediate)..................................................................................................4166
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66.17.2.15 CLRF (Clear ARM platform flags)........................................................................................4167
66.17.2.16 CMPEQ (Compare for Equal)................................................................................................4167
66.17.2.17 CMPEQI (Compare with Immediate for Equal)....................................................................4168
66.17.2.18 CMPHS (Compare for Higher or Same)................................................................................4169
66.17.2.19 CMPLT (Compare for Less Than).........................................................................................4170
66.17.2.20 cpShReg (Update Context of PCU Registers and Flag)........................................................4171
66.17.2.21 DONE (DONE, Yield) ..........................................................................................................4171
66.17.2.22 ILLEGAL (ILLEGAL Instruction)........................................................................................4173
66.17.2.23 JMP (Unconditional Jump Immediate)..................................................................................4174
66.17.2.24 JMPR (Unconditional Jump).................................................................................................4175
66.17.2.25 JSR (Unconditional Jump to Subroutine Immediate)............................................................4175
66.17.2.26 JSRR (Unconditional Jump to Subroutine)............................................................................4176
66.17.2.27 LD (Load Register)................................................................................................................4177
66.17.2.28 LDF (Load Register from Functional Unit)...........................................................................4178
66.17.2.29 LDI (Load Register with Immediate Value)..........................................................................4180
66.17.2.30 LDRPC (Load from RPC to Register)...................................................................................4181
66.17.2.31 LOOP (Hardware Loop)........................................................................................................4182
66.17.2.32 LSL1 (Logical Shift Left by 1 Bit)........................................................................................4185
66.17.2.33 LSR1 (Logical Shift Right by 1 Bit)......................................................................................4185
66.17.2.34 MOV (Logical Move)............................................................................................................4186
66.17.2.35 NOTIFY (Notify to ARM platform)......................................................................................4187
66.17.2.36 OR (Logical OR)....................................................................................................................4188
66.17.2.37 ORI (Logical OR with Immediate Value)..............................................................................4189
66.17.2.38 RET (Return from Subroutine)..............................................................................................4190
66.17.2.39 REVB (Reverse Byte Order)..................................................................................................4191
66.17.2.40 Reverse Low Order Bytes(REVBLO)...................................................................................4192
66.17.2.41 ROR1 (Rotate Right by 1 Bit)................................................................................................4192
66.17.2.42 RORB (Rotate Right by 1 Byte)............................................................................................4193
66.17.2.43 SOFTBKPT (Software Breakpoint).......................................................................................4194
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66.17.2.44 ST (Store Register).................................................................................................................4194
66.17.2.45 STF (Store Register in Functional Unit)................................................................................4196
66.17.2.46 SUB (Subtract).......................................................................................................................4199
66.17.2.47 SUBI (Subtract with Immediate)...........................................................................................4200
66.17.2.48 TST (Test with Zero).............................................................................................................4201
66.17.2.49 TSTI (Test Immediate)...........................................................................................................4202
66.17.2.50 XOR (Logical Exclusive OR)................................................................................................4203
66.17.2.51 XORI (Exclusive OR with Immediate)..................................................................................4204
66.17.2.52 YIELD, YIELDGE (DONE, Yield).......................................................................................4205
66.18 Software Restrictions....................................................................................................................................................4205
66.18.1
Unsupported Burst DMA Access Sequence..............................................................................................4205
66.19 Application Notes.........................................................................................................................................................4206
66.19.1
66.19.2
Data Structures for Boot Code and Channel Scripts..................................................................................4206
66.19.1.1
Buffer Descriptor Format.......................................................................................................4207
66.19.1.2
Buffer Descriptor Commands for Bootload scripts...............................................................4210
66.19.1.3
Example of Buffer Descriptors for Channel 0.......................................................................4212
66.19.1.4
Channel Context.....................................................................................................................4215
Typical Data Transfer Supported by SDMA DMA Units.........................................................................4217
66.19.2.1
External Memory to External Memory..................................................................................4218
66.19.2.2
Peripheral to Peripheral Transfer...........................................................................................4219
66.19.2.3
66.19.2.4
66.19.2.2.1
Source and Destination Target Have the Same Data Path Width...................4219
66.19.2.2.2
Source and Destination Target Have a Different Data Path Width................4220
Transfer Between Peripheral and External Memory..............................................................4221
66.19.2.3.1
Peripheral to External Memory Transfer........................................................4221
66.19.2.3.2
External Memory to Peripheral Transfer........................................................4223
Transfer Between External Memory and Internal Memory...................................................4224
66.19.2.4.1
Internal Memory to Internal Memory.............................................................4224
66.19.2.4.2
Transfer Between Peripheral and Internal Memory........................................4224
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Page
66.20 ARM Platform Memory Map and Control Register Definitions..................................................................................4225
66.20.1
ARM platform Channel 0 Pointer (SDMAARM_MC0PTR)....................................................................4230
66.20.2
Channel Interrupts (SDMAARM_INTR)..................................................................................................4231
66.20.3
Channel Stop/Channel Status (SDMAARM_STOP_STAT).....................................................................4231
66.20.4
Channel Start (SDMAARM_HSTART)....................................................................................................4231
66.20.5
Channel Event Override (SDMAARM_EVTOVR)..................................................................................4232
66.20.6
Channel BP Override (SDMAARM_DSPOVR).......................................................................................4232
66.20.7
Channel ARM platform Override (SDMAARM_HOSTOVR).................................................................4233
66.20.8
Channel Event Pending (SDMAARM_EVTPEND).................................................................................4233
66.20.9
Reset Register (SDMAARM_RESET)......................................................................................................4234
66.20.10
DMA Request Error Register (SDMAARM_EVTERR)...........................................................................4234
66.20.11
Channel ARM platform Interrupt Mask (SDMAARM_INTRMASK).....................................................4235
66.20.12
Schedule Status (SDMAARM_PSW)........................................................................................................4235
66.20.13
DMA Request Error Register (SDMAARM_EVTERRDBG)..................................................................4236
66.20.14
Configuration Register (SDMAARM_CONFIG)......................................................................................4237
66.20.15
SDMA LOCK (SDMAARM_SDMA_LOCK).........................................................................................4238
66.20.16
OnCE Enable (SDMAARM_ONCE_ENB)..............................................................................................4239
66.20.17
OnCE Data Register (SDMAARM_ONCE_DATA)................................................................................4239
66.20.18
OnCE Instruction Register (SDMAARM_ONCE_INSTR)......................................................................4240
66.20.19
OnCE Status Register (SDMAARM_ONCE_STAT)...............................................................................4240
66.20.20
OnCE Command Register (SDMAARM_ONCE_CMD).........................................................................4242
66.20.21
Illegal Instruction Trap Address (SDMAARM_ILLINSTADDR)............................................................4242
66.20.22
Channel 0 Boot Address (SDMAARM_CHN0ADDR)............................................................................4243
66.20.23
DMA Requests (SDMAARM_EVT_MIRROR).......................................................................................4244
66.20.24
DMA Requests 2 (SDMAARM_EVT_MIRROR2)..................................................................................4244
66.20.25
Cross-Trigger Events Configuration Register 1 (SDMAARM_XTRIG_CONF1)...................................4245
66.20.26
Cross-Trigger Events Configuration Register 2 (SDMAARM_XTRIG_CONF2)...................................4246
66.20.27
Channel Priority Registers (SDMAARM_SDMA_CHNPRIn).................................................................4247
66.20.28
Channel Enable RAM (SDMAARM_SDMA.CHNENBLn)....................................................................4248
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66.21 BP Memory Map and Control Register Definitions.....................................................................................................4248
66.21.1
Channel 0 Pointer (SDMABP_DC0PTR)..................................................................................................4249
66.21.2
Channel Interrupts (SDMABP_INTR)......................................................................................................4249
66.21.3
Channel Stop/Channel Status (SDMABP_STOP_STAT).........................................................................4250
66.21.4
Channel Start (SDMABP_DSTART)........................................................................................................4250
66.21.5
DMA Request Error Register (SDMABP_EVTERR)...............................................................................4251
66.21.6
Channel DSP Interrupt Mask (SDMABP_INTRMASK)..........................................................................4251
66.21.7
DMA Request Error Register (SDMABP_EVTERRDBG).......................................................................4252
66.22 SDMA Internal (Core) Memory Map and Internal Register Definitions.....................................................................4252
66.22.1
ARM platform Channel 0 Pointer (SDMACORE_MC0PTR)..................................................................4253
66.22.2
Current Channel Pointer (SDMACORE_CCPTR)....................................................................................4254
66.22.3
Current Channel Register (SDMACORE_CCR).......................................................................................4254
66.22.4
Highest Pending Channel Register (SDMACORE_NCR)........................................................................4255
66.22.5
External DMA Requests Mirror (SDMACORE_EVENTS).....................................................................4256
66.22.6
Current Channel Priority (SDMACORE_CCPRI)....................................................................................4257
66.22.7
Next Channel Priority (SDMACORE_NCPRI).........................................................................................4257
66.22.8
OnCE Event Cell Counter (SDMACORE_ECOUNT)..............................................................................4258
66.22.9
OnCE Event Cell Control Register (SDMACORE_ECTL)......................................................................4258
66.22.10
OnCE Event Address Register A (SDMACORE_EAA)...........................................................................4260
66.22.11
OnCE Event Cell Address Register B (SDMACORE_EAB)....................................................................4260
66.22.12
OnCE Event Cell Address Mask (SDMACORE_EAM)...........................................................................4261
66.22.13
OnCE Event Cell Data Register (SDMACORE_ED)................................................................................4261
66.22.14
OnCE Event Cell Data Mask (SDMACORE_EDM)................................................................................4261
66.22.15
OnCE Real-Time Buffer (SDMACORE_RTB)........................................................................................4262
66.22.16
OnCE Trace Buffer (SDMACORE_TB)...................................................................................................4262
66.22.17
OnCE Status (SDMACORE_OSTAT)......................................................................................................4263
66.22.18
Channel 0 Boot Address (SDMACORE_MCHN0ADDR).......................................................................4265
66.22.19
ENDIAN Status Register (SDMACORE_ENDIANNESS)......................................................................4266
66.22.20
Lock Status Register (SDMACORE_SDMA_LOCK)..............................................................................4267
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Title
Page
External DMA Requests Mirror #2 (SDMACORE_EVENTS2)..............................................................4267
66.23 SDMA Peripheral Registers..........................................................................................................................................4268
Chapter 67
System JTAG Controller (SJC)
67.1
Introduction...................................................................................................................................................................4269
67.1.1
Overview....................................................................................................................................................4270
67.2
Modes of Operation......................................................................................................................................................4271
67.3
TAP Selection Block (TSB)..........................................................................................................................................4273
67.3.1
67.4
Select Mode Using Software......................................................................................................................4273
External Signal Description..........................................................................................................................................4274
67.4.1
External Signal Overview..........................................................................................................................4274
67.4.2
TAP Controller...........................................................................................................................................4276
67.4.3
Accessing ExtraDebug Registers...............................................................................................................4278
67.5
Boundary Scan Register (BSR)....................................................................................................................................4281
67.6
SoC JTAG Instruction Register (SJIR).........................................................................................................................4281
67.7
67.6.1
ID_CODE Instruction (IDCODE).............................................................................................................4282
67.6.2
SAMPLE/PRELOAD Instruction..............................................................................................................4283
67.6.3
EXTEST Instruction..................................................................................................................................4283
67.6.4
HIGHZ Instruction.....................................................................................................................................4284
67.6.5
BYPASS Instruction..................................................................................................................................4284
67.6.6
ENABLE_ExtraDebug Instruction............................................................................................................4284
67.6.7
ENTER_DEBUG instruction.....................................................................................................................4285
67.6.8
TAP Select Instruction...............................................................................................................................4285
Security.........................................................................................................................................................................4286
67.7.1
JTAG Security Modes................................................................................................................................4287
67.7.1.1
Mode 1: No Debug - Maximum Security..............................................................................4287
67.7.1.2
Mode 2: Secure JTAG - High Security..................................................................................4287
67.7.1.2.1
67.7.1.3
Challenge/Response Mechanism in System JTAG Mode..............................4288
Mode 3: JTAG Enabled - Low Security................................................................................4289
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67.8
67.9
Title
Page
67.7.2
Software Enabled JTAG............................................................................................................................4289
67.7.3
Kill Trace...................................................................................................................................................4290
67.7.4
SJC Disable Fuse.......................................................................................................................................4291
Functional Description..................................................................................................................................................4292
67.8.1
Static Core Debug......................................................................................................................................4292
67.8.2
Reset Mechanism.......................................................................................................................................4292
Initialization/Application Information..........................................................................................................................4294
67.10 Programmable Registers...............................................................................................................................................4294
67.10.1
General Purpose Unsecured Status Register 1 (SJC_GPUSR1)................................................................4295
67.10.2
General Purpose Unsecured Status Register 2 (SJC_GPUSR2)................................................................4296
67.10.3
General Purpose Unsecured Status Register 3 (SJC_GPUSR3)................................................................4297
67.10.4
General Purpose Secured Status Register (SJC_GPSSR)..........................................................................4297
67.10.5
Debug Control Register (SJC_DCR).........................................................................................................4298
67.10.6
Security Status Register (SJC_SSR)..........................................................................................................4299
67.10.7
General Purpose Clocks Control Register (SJC_GPCCR)........................................................................4301
67.10.8
General Purpose Unsecured Control Register n (SJC_GPUCR)...............................................................4302
67.10.9
General Purpose Secured Control Register (SJC_GPSCR).......................................................................4302
Chapter 68
Shared Peripheral Bus Arbiter (SPBA)
68.1
Introduction...................................................................................................................................................................4303
68.2
General Overview.........................................................................................................................................................4306
68.3
Features.........................................................................................................................................................................4306
68.4
Modes of Operation......................................................................................................................................................4306
68.5
Functional Description..................................................................................................................................................4307
68.5.1
68.6
Masters Arbitration....................................................................................................................................4307
Resource Ownership Control........................................................................................................................................4310
68.6.1
Access Control ..........................................................................................................................................4310
68.6.1.1
Peripheral Access...................................................................................................................4310
68.6.1.2
Peripheral Right Register Access...........................................................................................4311
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68.6.2
Owner Election..........................................................................................................................................4312
68.6.3
Ending Ownership......................................................................................................................................4312
68.6.3.1
68.6.4
68.7
Title
Software Controlled Ownership Ending................................................................................4312
The Un-owned State...................................................................................................................................4313
Memory Map/Register Definition.................................................................................................................................4313
68.7.1
SPBA Register Definition..........................................................................................................................4314
68.7.1.1
Peripheral Right Register (SPBA_PRRn)..............................................................................4317
Chapter 69
Sony/Philips Digital Interface (SPDIF)
69.1
Introduction ..................................................................................................................................................................4321
69.1.1
Overview....................................................................................................................................................4323
69.2
External Signal Description..........................................................................................................................................4324
69.3
Functional Description..................................................................................................................................................4324
69.3.1
SPDIF Receiver..........................................................................................................................................4324
69.3.1.1
Audio Data Reception............................................................................................................4325
69.3.1.1.1
69.3.1.2
Channel Status Reception......................................................................................................4328
69.3.1.2.1
69.3.2
Application Note.............................................................................................4327
Channel Status Interrupt.................................................................................4328
69.3.1.3
User Bit Reception.................................................................................................................4328
69.3.1.4
Validity Flag Reception.........................................................................................................4330
69.3.1.5
SPDIF Receiver Interrupt Exception Definition....................................................................4331
69.3.1.6
Standards Compliance............................................................................................................4331
69.3.1.7
SPDIF PLOCK Detection and Rxclk Output.........................................................................4332
69.3.1.8
Measuring Frequency of SPDIF_RxClk................................................................................4332
SPDIF Transmitter.....................................................................................................................................4333
69.3.2.1
Audio Data Transmission.......................................................................................................4333
69.3.2.2
Channel Status Transmission.................................................................................................4334
69.3.2.3
Validity Flag Transmission....................................................................................................4334
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Title
Page
Programmable Registers...............................................................................................................................................4335
69.4.1
SPDIF Configuration Register (SPDIF_SCR)...........................................................................................4336
69.4.2
CDText Control Register (SPDIF_SRCD)................................................................................................4338
69.4.3
PhaseConfig Register (SPDIF_SRPC).......................................................................................................4339
69.4.4
InterruptEn Register (SPDIF_SIE)............................................................................................................4340
69.4.5
InterruptStat Register (SPDIF_SIS)...........................................................................................................4342
69.4.6
InterruptClear Register (SPDIF_SIC)........................................................................................................4344
69.4.7
SPDIFRxLeft Register (SPDIF_SRL).......................................................................................................4345
69.4.8
SPDIFRxRight Register (SPDIF_SRR).....................................................................................................4346
69.4.9
SPDIFRxCChannel_h Register (SPDIF_SRCSH).....................................................................................4346
69.4.10
SPDIFRxCChannel_l Register (SPDIF_SRCSL)......................................................................................4347
69.4.11
UchannelRx Register (SPDIF_SRU).........................................................................................................4347
69.4.12
QchannelRx Register (SPDIF_SRQ).........................................................................................................4348
69.4.13
SPDIFTxLeft Register (SPDIF_STL)........................................................................................................4348
69.4.14
SPDIFTxRight Register (SPDIF_STR).....................................................................................................4349
69.4.15
SPDIFTxCChannelCons_h Register (SPDIF_STCSCH)..........................................................................4349
69.4.16
SPDIFTxCChannelCons_l Register (SPDIF_STCSCL)...........................................................................4350
69.4.17
FreqMeas Register (SPDIF_SRFM)..........................................................................................................4350
69.4.18
SPDIFTxClk Register (SPDIF_STC)........................................................................................................4351
Chapter 70
System Reset Controller (SRC)
70.1
70.2
Introduction ..................................................................................................................................................................4353
70.1.1
Overview....................................................................................................................................................4353
70.1.2
Features......................................................................................................................................................4354
Programmable Registers...............................................................................................................................................4355
70.2.1
SRC Control Register (SRC_SCR)............................................................................................................4355
70.2.2
SRC Boot Mode Register (SRC_SBMR)..................................................................................................4357
70.2.3
SRC Reset Status Register (SRC_SRSR)..................................................................................................4358
70.2.4
SRC Interrupt Status Register (SRC_SISR)..............................................................................................4360
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70.2.5
70.3
Title
Page
SRC Interrupt Mask Register (SRC_SIMR)..............................................................................................4361
Functional Description..................................................................................................................................................4362
70.3.1
Reset Control..............................................................................................................................................4362
70.3.1.1
Reset Inputs and Outputs.......................................................................................................4362
70.3.1.2
Reset Handling.......................................................................................................................4365
70.3.1.2.1
Reset Qualification..........................................................................................4365
70.3.1.2.2
Reset Sequence and Deassertion.....................................................................4366
70.3.1.2.3
SMS sub-block................................................................................................4373
70.3.1.2.4
SRTC_RST_B generation...............................................................................4375
70.3.2
SJC_POR_RST_B Generation...................................................................................................................4376
70.3.3
Parallel Reset Requests..............................................................................................................................4376
70.3.4
DFT Mux on Reset Outputs.......................................................................................................................4377
70.3.5
Boot Mode Control....................................................................................................................................4378
70.3.5.1
BOOT_MODE Pin Latching.................................................................................................4378
70.3.5.2
Correspondence Table between SRC SBMR bit/signal Names and Fuse Names.................4380
70.3.5.3
Boot Output Signals ..............................................................................................................4380
Chapter 71
State Retention Power Gating Controller (SRPGC)
71.1
71.2
Introduction...................................................................................................................................................................4383
71.1.1
Features......................................................................................................................................................4383
71.1.2
Modes of Operation...................................................................................................................................4383
71.1.2.1
Functional Mode....................................................................................................................4383
71.1.2.2
Debug Mode...........................................................................................................................4384
Power Gating Cells.......................................................................................................................................................4384
71.2.1
Power Supply Switch Cells........................................................................................................................4384
71.2.2
Power Supply Shorting Cells.....................................................................................................................4385
71.2.3
State Retention Power Gating (SRPG) Cell...............................................................................................4387
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Page
SRPGC Interface...........................................................................................................................................................4390
71.3.1
Power-Down Sequence (SRPG Entry Sequence)......................................................................................4390
71.3.1.1
71.3.2
Power-Down Sequence Timing Waveforms..........................................................................4391
Power-Up Sequence (SRPG Exit Sequence).............................................................................................4392
71.3.2.1
71.4
Title
Power-up Sequence Timing Waveforms...............................................................................4392
Programmable Registers...............................................................................................................................................4393
71.4.1
SPRGC Control Register (SRPGCx_SRPGCR)........................................................................................4394
71.4.2
Power-up Sequence Control Register (SRPGCx_PUPSCR).....................................................................4395
71.4.3
Power-down Sequence Control Register (SRPGCx_PDNSCR)................................................................4395
71.4.4
SPRGC Status Register (SRPGCx_SRPGSR)...........................................................................................4396
71.4.5
SPRGC Debug Register (SRPGCx_SRPGDR).........................................................................................4397
Chapter 72
Secure Real Time Clock (SRTC)
72.1
Overview ......................................................................................................................................................................4399
72.1.1
Low Power SRTC (SRTC LP) Overview..................................................................................................4399
72.1.2
High Power SRTC (SRTC HP) Overview.................................................................................................4400
72.1.3
Features......................................................................................................................................................4402
72.1.4
Modes of Operations..................................................................................................................................4403
72.2
External Signal Description..........................................................................................................................................4403
72.3
Functional Description..................................................................................................................................................4404
72.3.1
Power and Clock Source............................................................................................................................4404
72.3.1.1
72.3.2
Clocks.....................................................................................................................................4405
High Power SRTC (SRTC HP) Description..............................................................................................4405
72.3.2.1
SRTC HP nonsecured Counter..............................................................................................4405
72.3.2.1.1
72.3.3
SRTC HP Counter Calibration.......................................................................4406
72.3.2.2
SRTC HP nonsecured Counter Alarm...................................................................................4406
72.3.2.3
SRTC HP Periodic Alarm......................................................................................................4407
Low Power SRTC (SRTC LP) Description...............................................................................................4408
72.3.3.1
SRTC LP Behavior during System Power Down and POR...................................................4408
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Title
Page
SRTC LP Secured Counter....................................................................................................4409
72.3.3.2.1
SRTC LP Counter Calibration........................................................................4409
72.3.3.3
SRTC LP Secured Counter Alarm.........................................................................................4410
72.3.3.4
Monotonic Counter................................................................................................................4410
72.3.3.4.1
Monotonic Counter Roll-Over Protection Mechanism...................................4411
72.3.3.5
General Purpose Always-Powered Registers.........................................................................4414
72.3.3.6
SRTC LP Monitor..................................................................................................................4414
72.3.3.6.1
SRTC State Machine.......................................................................................4414
72.3.3.6.2
Power Supply Glitch Detector (PGD).............................................................4415
72.3.3.6.3
Clock Tampering Detector (CTD)..................................................................4416
72.3.3.6.4
Voltage Level Tampering Detector................................................................4417
72.3.3.6.5
Power Fail Detector (PFD).............................................................................4417
72.4
SRTC Reset and System Power-Up .............................................................................................................................4418
72.5
SRTC Interrupts and Alarms........................................................................................................................................4418
72.6
Initialization Information/Application Information......................................................................................................4419
72.6.1
Flow Chart of SRTC LP Operation............................................................................................................4419
72.6.2
Flow Chart of SRTC HP Operation...........................................................................................................4420
72.7
Software Restrictions....................................................................................................................................................4421
72.8
Programmable Registers...............................................................................................................................................4422
72.8.1
LP Secure Counter MSB Register (SRTC_LPSCMR)..............................................................................4424
72.8.2
LP Secure Counter LSB Register (SRTC_LPSCLR)................................................................................4424
72.8.3
LP Secure Alarm Register (SRTC_LPSAR).............................................................................................4425
72.8.4
LP Secure Monotonic Counter Register (SRTC_LPSMCR).....................................................................4425
72.8.5
LP Control Register (SRTC_LPCR)..........................................................................................................4426
72.8.6
LP Status Register (SRTC_LPSR).............................................................................................................4429
72.8.7
LP Power Supply Glitch Detector Register (SRTC_LPPDR)...................................................................4432
72.8.8
LP General Purpose Register (SRTC_LPGR)...........................................................................................4432
72.8.9
HP Counter MSB Register (SRTC_HPCMR)...........................................................................................4433
72.8.10
HP Counter LSB Register (SRTC_HPCLR).............................................................................................4434
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Page
72.8.11
HP Alarm MSB Register (SRTC_HPAMR)..............................................................................................4434
72.8.12
HP Alarm LSB Register (SRTC_HPALR)................................................................................................4435
72.8.13
HP Control Register (SRTC_HPCR).........................................................................................................4435
72.8.14
HP Interrupt Status Register (SRTC_HPISR)...........................................................................................4437
72.8.15
HP Interrupt Enable Register (SRTC_HPIENR).......................................................................................4440
Chapter 73
Synchronous Serial Interface (SSI)
73.1
73.2
Overview.......................................................................................................................................................................4443
73.1.1
Features......................................................................................................................................................4444
73.1.2
Modes of Operation...................................................................................................................................4445
External Signal Description..........................................................................................................................................4445
73.2.1
Signals Overview.......................................................................................................................................4445
73.3
SSI Transmit FIFO 0 & 1 Registers..............................................................................................................................4449
73.4
SSI Transmit Shift Register (TXSR)............................................................................................................................4449
73.5
SSI Receive FIFO 0 and 1 Registers.............................................................................................................................4452
73.6
SSI Receive Shift Register (RXSR)..............................................................................................................................4452
73.7
Functional Description..................................................................................................................................................4454
73.7.1
Operating Modes........................................................................................................................................4454
73.7.1.1
73.7.1.2
Normal Mode.........................................................................................................................4456
73.7.1.1.1
Normal Mode Transmit...................................................................................4456
73.7.1.1.2
Normal Mode Receive....................................................................................4457
Network Mode.......................................................................................................................4459
73.7.1.2.1
Network Mode Transmit.................................................................................4460
73.7.1.2.2
Network Mode Receive..................................................................................4461
73.7.1.3
Gated Clock Mode.................................................................................................................4463
73.7.1.4
I2S Mode................................................................................................................................4466
73.7.1.5
AC97 Mode............................................................................................................................4468
73.7.1.5.1
AC97 Fixed Mode (SSI.SACNT[1]=0)..........................................................4470
73.7.1.5.2
AC97 Variable Mode (SSI.SACNT[1]=1).....................................................4470
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73.7.2
Page
External Frame and Clock Operation.........................................................................................................4471
73.7.2.1
Data Alignment Formats Supported......................................................................................4471
73.7.3
SSI Architecture.........................................................................................................................................4472
73.7.4
SSI Clocking..............................................................................................................................................4473
73.7.4.1
SSI Clock and Frame Sync Generation..................................................................................4474
73.7.4.2
DIV2, PSR and PM Bit Description......................................................................................4475
73.7.5
Receive Interrupt Enable Bit Description..................................................................................................4477
73.7.6
Transmit Interrupt Enable Bit Description.................................................................................................4478
73.7.7
Internal Frame and Clock Shutdown.........................................................................................................4479
73.7.8
Peripheral Bus Interface.............................................................................................................................4481
73.7.9
73.8
Title
73.7.8.1
Transfer Lengths Supported...................................................................................................4481
73.7.8.2
Transfer Bus Errors................................................................................................................4481
73.7.8.3
Clock Rate..............................................................................................................................4482
Reset...........................................................................................................................................................4482
Programmable Registers...............................................................................................................................................4482
73.8.1
SSI Transmit Data Register n (SSIx_SSI_STXn)......................................................................................4486
73.8.2
SSI Receive Data Register n (SSIx_SSI_SRXn).......................................................................................4486
73.8.3
SSI Control Register (SSIx_SSI_SCR)......................................................................................................4487
73.8.4
SSI Interrupt Status Register (SSIx_SSI_SISR)........................................................................................4489
73.8.5
SSI Interrupt Enable Register (SSIx_SIER)...............................................................................................4494
73.8.6
SSI Transmit Configuration Register (SSIx_SSI_STCR)..........................................................................4496
73.8.7
SSI Receive Configuration Register (SSIx_SSI_SRCR)...........................................................................4498
73.8.8
SSI Transmit Clock Control Register (SSIx_SSI_STCCR).......................................................................4500
73.8.9
SSI Receive Clock Control Register (SSIx_SRCCR)................................................................................4502
73.8.10
SSI FIFO Control/Status Register (SSIx_SSI_SFCSR).............................................................................4503
73.8.11
SSI AC97 Control Register (SSIx_SSI_SACNT)......................................................................................4507
73.8.12
SSI AC97 Command Address Register (SSIx_SSI_SACADD)................................................................4508
73.8.13
SSI AC97 Command Data Register (SSIx_SSI_SACDAT)......................................................................4509
73.8.14
SSI AC97 Tag Register (SSIx_SATAG)...................................................................................................4509
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Section Number
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Page
73.8.15
SSI Transmit Time Slot Mask Register (SSIx_SSI_STMSK)...................................................................4510
73.8.16
SSI Receive Time Slot Mask Register (SSIx_SSI_SRMSK)....................................................................4510
73.8.17
SSI AC97 Channel Status Register (SSIx_SSI_SACCST)........................................................................4511
73.8.18
SSI AC97 Channel Enable Register (SSIx_SSI_SACCEN)......................................................................4511
73.8.19
SSI AC97 Channel Disable Register (SSIx_SSI_SACCDIS)....................................................................4512
Chapter 74
Television Encoder (TVEv2)
74.1
74.2
74.3
Introduction ..................................................................................................................................................................4513
74.1.1
Overview....................................................................................................................................................4518
74.1.2
Operation in VGA Mode-Introduction......................................................................................................4526
74.1.3
Features......................................................................................................................................................4527
74.1.4
Modes of Operation...................................................................................................................................4531
74.1.4.1
Operation in TV Mode...........................................................................................................4531
74.1.4.2
Operation in VGA Mode........................................................................................................4533
74.1.4.3
Standby Mode........................................................................................................................4533
74.1.4.4
Cable Detection Modes..........................................................................................................4534
External Signal Description..........................................................................................................................................4536
74.2.1
Detailed Signal Descriptions .....................................................................................................................4536
74.2.2
Interface between the IPU and the TVE....................................................................................................4543
74.2.3
Software Recommendations......................................................................................................................4544
74.2.3.1
PLL configuration..................................................................................................................4544
74.2.3.2
HSYNC and VSYNC in VGA Mode.....................................................................................4545
Programmable Registers...............................................................................................................................................4545
74.3.1
Common Configuration Register (TVE_COM_CONF_REG)..................................................................4548
74.3.2
Luma Filter Control Register 0 (TVE_LUMA_FILT_CONT_REG_0)....................................................4550
74.3.3
Luma Filter Control Register 1 (TVE_LUMA_FILT_CONT_REG_1)....................................................4552
74.3.4
Luma Filter Control Register 2 (TVE_LUMA_FILT_CONT_REG_2)....................................................4553
74.3.5
Luma Filter Control Register 3 (TVE_LUMA_FILT_CONT_REG_3)....................................................4554
74.3.6
Luma Statistic Analysis Control Register 0 (TVE_LUMA_SA_CONT_REG_0)....................................4556
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74.3.7
Luma Statistic Analysis Control Register 1 (TVE_LUMA_SA_CONT_REG_1)....................................4557
74.3.8
Luma Statistic Analysis Status Register 0 (TVE_LUMA_SA_STAT_REG_0).......................................4557
74.3.9
Luma Statistic Analysis Status Register 1 (TVE_LUMA_SA_STAT_REG_1).......................................4558
74.3.10
Chroma Control Register (TVE_CHROMA_CONT_REG).....................................................................4559
74.3.11
TVDAC 0 Control Register (TVE_TVDAC_0_CONT_REG).................................................................4560
74.3.12
TVDAC 1 Control Register (TVE_TVDAC_1_CONT_REG).................................................................4561
74.3.13
TVDAC 2 Control Register (TVE_TVDAC_2_CONT_REG).................................................................4562
74.3.14
Cable Detection Control Register (TVE_CD_CONT_REG)....................................................................4563
74.3.15
VBI Data Control Register (TVE_VBI_DATA_CONT_REG)................................................................4565
74.3.16
VBI Data Register 0 (TVE_VBI_DATA_REG_0)...................................................................................4567
74.3.17
VBI Data Register 1 (TVE_VBI_DATA_REG_1)...................................................................................4567
74.3.18
VBI Data Register 2 (TVE_VBI_DATA_REG_2)...................................................................................4568
74.3.19
VBI Data Register 3 (TVE_VBI_DATA_REG_3)...................................................................................4568
74.3.20
VBI Data Register 4 (TVE_VBI_DATA_REG_4)...................................................................................4568
74.3.21
VBI Data Register 5 (TVE_VBI_DATA_REG_5)...................................................................................4569
74.3.22
VBI Data Register 6 (TVE_VBI_DATA_REG_6)...................................................................................4569
74.3.23
VBI Data Register 7 (TVE_VBI_DATA_REG_7)...................................................................................4570
74.3.24
VBI Data Register 8 (TVE_VBI_DATA_REG_8)...................................................................................4570
74.3.25
VBI Data Register 9 (TVE_VBI_DATA_REG_9)...................................................................................4570
74.3.26
Interrupt Control Register (TVE_INT_CONT_REG)...............................................................................4571
74.3.27
Status Register (TVE_STAT_REG)..........................................................................................................4573
74.3.28
Test Mode Register (TVE_TST_MODE_REG)........................................................................................4576
74.3.29
User Mode Control Register (TVE_USER_MODE_CONT_REG)..........................................................4578
74.3.30
SD Timing User Control Register 0 (TVE_SD_TIMING_USR_CONT_REG_0)...................................4579
74.3.31
SD Timing User Control Register 1 (TVE_SD_TIMING_USR_CONT_REG_1)...................................4579
74.3.32
SD Timing User Control Register 2 (TVE_SD_TIMING_USR_CONT_REG_2)...................................4580
74.3.33
HD Timing User Control Register 0 (TVE_HD_TIMING_USR_CONT_REG_0)..................................4581
74.3.34
HD Timing User Control Register 1 (TVE_HD_TIMING_USR_CONT_REG_1)..................................4582
74.3.35
HD Timing User Control Register 2 (TVE_HD_TIMING_USR_CONT_REG_2)..................................4583
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Title
Page
74.3.36
Luma User Control Register 0 (TVE_LUMA_USR_CONT_REG_0).....................................................4583
74.3.37
Luma User Control Register 1 (TVE_LUMA_USR_CONT_REG_1).....................................................4584
74.3.38
Luma User Control Register 2 (TVE_LUMA_USR_CONT_REG_2).....................................................4584
74.3.39
Luma User Control Register 3 (TVE_LUMA_USR_CONT_REG_3).....................................................4585
74.3.40
Color Space Conversion User Control Register 0 (TVE_CSC_USR_CONT_REG_0)............................4585
74.3.41
Color Space Conversion User Control Register 1 (TVE_CSC_USR_CONT_REG_1)............................4586
74.3.42
Color Space Conversion User Control Register 2 (TVE_CSC_USR_CONT_REG_2)............................4587
74.3.43
Blanking Level User Control Register (TVE_BLANK_USR_CONT_REG)...........................................4588
74.3.44
SD Modulation User Control Register (TVE_SD_MOD_USR_CONT_REG)........................................4588
74.3.45
VBI Data User Control Register 0 (TVE_VBI_DATA_USR_CONT_REG_0).......................................4589
74.3.46
VBI Data User Control Register 1 (TVE_VBI_DATA_USR_CONT_REG_1).......................................4590
74.3.47
VBI Data User Control Register 2 (TVE_VBI_DATA_USR_CONT_REG_2).......................................4590
74.3.48
VBI Data User Control Register 3 (TVE_VBI_DATA_USR_CONT_REG_3).......................................4591
74.3.49
VBI Data User Control Register 4 (TVE_VBI_DATA_USR_CONT_REG_4).......................................4592
74.3.50
Drop Compensation User Control Register (TVE_DROP_COMP_USR_CONT_REG).........................4592
Chapter 75
TrustZone Aware Interrupt Controller (TZIC)
75.1
Overview.......................................................................................................................................................................4595
75.2
Features.........................................................................................................................................................................4596
75.3
External Signal Description..........................................................................................................................................4597
75.4
Functional Description..................................................................................................................................................4597
75.4.1
Security Configurability.............................................................................................................................4597
75.4.1.1
75.5
TrustZone and Interrupt Priority............................................................................................4597
75.4.2
AXI Interface.............................................................................................................................................4599
75.4.3
Interrupt Engine.........................................................................................................................................4599
75.4.4
Auto-Vectored Interrupt Handling.............................................................................................................4600
75.4.5
Reset...........................................................................................................................................................4601
Initialization Information..............................................................................................................................................4601
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75.6
Title
Page
Programmable Registers...............................................................................................................................................4602
75.6.1
Control Register (TZIC_INTCTRL)..........................................................................................................4607
75.6.2
Interrupt Controller Type Register (TZIC_INTTYPE).............................................................................4609
75.6.3
Priority Mask Register (TZIC_PRIOMASK)............................................................................................4610
75.6.4
Synchronizer Control (TZIC_SYNCCTRL)..............................................................................................4611
75.6.5
DSM Interrupt Holdoff (TZIC_DSMINT)................................................................................................4612
75.6.6
Interrupt Security (FIQ) Register: Irq 0 to 31 (TZIC_INTSECn).............................................................4613
75.6.7
Enable Set Register: Irq 0 to 31 (TZIC_ENSETn)....................................................................................4614
75.6.8
Enable Clear Register: Irq 0 to 31 (TZIC_ENCLEARn)...........................................................................4615
75.6.9
Source Set Register: Irq 0 to 31 (TZIC_SRCSETn)..................................................................................4616
75.6.10
Source Clear Register: Irq 0 to 31 (TZIC_SRCCLEARn)........................................................................4617
75.6.11
Priority Register: Irq 0 to 3 (TZIC_PRIORITYn).....................................................................................4618
75.6.12
Pending Register: Irq 0 to 31 (TZIC_PNDn).............................................................................................4620
75.6.13
High Priority Pending Register: Irq 0 to 31 (TZIC_HIPNDn)..................................................................4621
75.6.14
Wakeup Config Register: Irq 0 to 31 (TZIC_WAKEUPn).......................................................................4622
75.6.15
Software Interrupt Trigger Register (TZIC_SWINT)................................................................................4623
Chapter 76
Universal Asynchronous Receiver/Transmitter (UART)
76.1
76.2
Overview.......................................................................................................................................................................4625
76.1.1
Features......................................................................................................................................................4626
76.1.2
Modes of Operation...................................................................................................................................4627
76.1.3
UART I/O Configuration in DTE and DCE Modes..................................................................................4627
External Signals............................................................................................................................................................4628
76.2.1
Detailed Signal Descriptions......................................................................................................................4629
76.2.1.1
76.2.1.2
Serial/IrDA Signals................................................................................................................4629
76.2.1.1.1
RXD - Data Receive.......................................................................................4629
76.2.1.1.2
TXD - Data Transmit......................................................................................4629
Modem Control Signals.........................................................................................................4629
76.2.1.2.1
CTS - Clear To Send ......................................................................................4629
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Section Number
76.2.1.3
Title
76.2.1.2.2
RTS - Request To Send...................................................................................4630
76.2.1.2.3
DSR - Data Set Ready.....................................................................................4630
76.2.1.2.4
DCD - Data Carrier Detected..........................................................................4630
76.2.1.2.5
DTR - Data Terminal Ready...........................................................................4630
76.2.1.2.6
RI - Ring Indicator..........................................................................................4630
Interrupt Signals.....................................................................................................................4630
76.2.1.3.1
76.2.1.4
76.2.1.5
76.2.1.6
76.3
Page
interrupt_uart - UART Interrupt.....................................................................4630
DMA Request Signals............................................................................................................4631
76.2.1.4.1
dma_req_rx - Receiver DMA Request...........................................................4631
76.2.1.4.2
dma_req_tx - Transmitter DMA Request.......................................................4631
Clock Signals.........................................................................................................................4631
76.2.1.5.1
peripheral_clock - Peripheral Clock ..............................................................4631
76.2.1.5.2
module_clock - Module Clock .......................................................................4631
Special Signals.......................................................................................................................4631
76.2.1.6.1
stop_req - Stop Mode......................................................................................4631
76.2.1.6.2
doze_req - Doze Mode....................................................................................4631
76.2.1.6.3
debug_req - Debug Mode...............................................................................4631
Functional Description..................................................................................................................................................4632
76.3.1
Interrupts and DMA Requests....................................................................................................................4632
76.3.2
Clocks.........................................................................................................................................................4633
76.3.3
76.3.2.1
Clock requirements................................................................................................................4633
76.3.2.2
Maximum Baud Rate.............................................................................................................4634
76.3.2.3
Clocking in Low-Power Modes.............................................................................................4634
General UART Definitions........................................................................................................................4635
76.3.3.1
RTS - UART Request To Send..............................................................................................4636
76.3.3.2
RTS Edge Triggered Interrupt...............................................................................................4636
76.3.3.3
DTR - Data Terminal Ready .................................................................................................4637
76.3.3.4
DSR - Data Set Ready............................................................................................................4637
76.3.3.5
DTR/DSR Edge Triggered Interrupt......................................................................................4638
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Section Number
76.3.4
76.3.5
Title
76.3.3.6
DCD - Data Carrier Detect.....................................................................................................4638
76.3.3.7
RI - Ring Indicator.................................................................................................................4639
76.3.3.8
CTS - Clear To Send..............................................................................................................4639
76.3.3.9
Programmable CTS Deassertion............................................................................................4639
76.3.3.10
TXD - UART Transmit..........................................................................................................4639
76.3.3.11
RXD - UART Receive...........................................................................................................4640
Transmitter.................................................................................................................................................4641
76.3.4.1
Transmitter FIFO Empty Interrupt Suppression....................................................................4642
76.3.4.2
Transmitting a Break Condition.............................................................................................4644
Receiver.....................................................................................................................................................4644
76.3.5.1
Idle Line Detect......................................................................................................................4645
76.3.5.2
Aging Character Detect..........................................................................................................4646
76.3.5.3
Receiver Wake.......................................................................................................................4647
76.3.5.4
Receiving a BREAK Condition.............................................................................................4648
76.3.5.5
Vote Logic..............................................................................................................................4648
76.3.5.6
Baud Rate Automatic Detection Logic..................................................................................4650
76.3.5.6.1
Baud Rate Automatic Detection Protocol.......................................................4651
76.3.5.6.2
New Baud Rate Determination.......................................................................4651
76.3.5.6.2.1
76.3.6
Page
New Autobaud Counter Stopped bit and Interrupt.................4652
Escape Sequence Detection.......................................................................................................................4652
76.4
Binary Rate Multiplier (BRM)......................................................................................................................................4654
76.5
Infrared Interface..........................................................................................................................................................4656
76.5.1
Generalities-Infrared..................................................................................................................................4656
76.5.2
Inverted Transmission and Reception bits (INVT & INVR).....................................................................4657
76.5.3
InfraRed Special Case (IRSC) Bit.............................................................................................................4657
76.5.4
IrDA interrupt............................................................................................................................................4658
76.5.5
Conclusion about IrDA..............................................................................................................................4659
76.5.6
Programming IrDA Interface.....................................................................................................................4660
76.5.6.1
High Speed.............................................................................................................................4660
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Section Number
76.5.6.2
76.6
Title
Page
Low Speed..............................................................................................................................4660
Low Power Modes........................................................................................................................................................4661
76.6.1
UART Operation in System Doze Mode...................................................................................................4662
76.6.2
UART Operation in System Stop Mode....................................................................................................4662
76.6.3
Power Saving Method in UART................................................................................................................4662
76.7
UART Operation in System Debug State.....................................................................................................................4663
76.8
Reset..............................................................................................................................................................................4663
76.9
76.8.1
Hardware reset...........................................................................................................................................4663
76.8.2
Software reset.............................................................................................................................................4664
Transfer Error................................................................................................................................................................4664
76.10 Functional Timing.........................................................................................................................................................4664
76.10.1
RS-232/RS-485 Mode................................................................................................................................4664
76.10.2
IrDA Mode.................................................................................................................................................4665
76.11 Initialization..................................................................................................................................................................4666
76.11.1
Programming the UART in RS-232 mode.................................................................................................4666
76.12 References.....................................................................................................................................................................4668
76.13 UART Memory Map/Register Definition.....................................................................................................................4668
76.13.1
UART Receiver Register (UARTx_URXD)..............................................................................................4673
76.13.2
UART Transmitter Register (UARTx_UTXD).........................................................................................4675
76.13.3
UART Control Register 1 (UARTx_UCR1)..............................................................................................4676
76.13.4
UART Control Register 2 (UARTx_UCR2)..............................................................................................4678
76.13.5
UART Control Register 3 (UARTx_UCR3)..............................................................................................4681
76.13.6
UART Control Register 4 (UARTx_UCR4)..............................................................................................4683
76.13.7
UART FIFO Control Register (UARTx_UFCR).......................................................................................4685
76.13.8
UART Status Register 1 (UARTx_USR1).................................................................................................4687
76.13.9
UART Status Register 2 (UARTx_USR2).................................................................................................4689
76.13.10
UART Escape Character Register (UARTx_UESC).................................................................................4692
76.13.11
UART Escape Timer Register (UARTx_UTIM).......................................................................................4692
76.13.12
UART BRM Incremental Register (UARTx_UBIR).................................................................................4693
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Section Number
Title
Page
76.13.13
UART BRM Modulator Register (UARTx_UBMR).................................................................................4693
76.13.14
UART Baud Rate Count Register (UARTx_UBRC).................................................................................4694
76.13.15
UART One Millisecond Register (UARTx_ONEMS)..............................................................................4695
76.13.16
UART Test Register (UARTx_UTS).........................................................................................................4696
Chapter 77
Universal Serial Bus Controller (USB)
77.1
Overview.......................................................................................................................................................................4699
77.2
Features.........................................................................................................................................................................4700
77.2.1
77.3
Modes of Operation...................................................................................................................................4701
77.2.1.1
Normal Mode.........................................................................................................................4701
77.2.1.2
Low Power Mode...................................................................................................................4702
Functional Description..................................................................................................................................................4703
77.3.1
USB Host Controller 1...............................................................................................................................4703
77.3.1.1
77.3.2
USB Host Controller 2...............................................................................................................................4704
77.3.3
USB Host Controller 3...............................................................................................................................4704
77.3.4
USB OTG Controller.................................................................................................................................4704
77.3.5
77.3.6
77.4
Pins Used for Host Controller 1.............................................................................................4703
77.3.4.1
Host Mode..............................................................................................................................4704
77.3.4.2
Peripheral (Device) Mode......................................................................................................4705
77.3.4.3
Pins Used for OTG.................................................................................................................4705
Interrupts....................................................................................................................................................4705
77.3.5.1
USB Core Interrupts...............................................................................................................4705
77.3.5.2
USB Wake-Up Interrupts.......................................................................................................4706
USB Clock System.....................................................................................................................................4706
USB Operation Model..................................................................................................................................................4708
77.4.1
Register Interface.......................................................................................................................................4708
77.4.1.1
Configuration, Control and Status Register Set.....................................................................4709
77.4.1.2
Identification Registers..........................................................................................................4711
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Section Number
77.4.1.3
77.4.2
Title
Page
OTG Operations.....................................................................................................................4711
77.4.1.3.1
Register Bits....................................................................................................4711
77.4.1.3.2
Hardware Assist .............................................................................................4712
77.4.1.3.2.1
Auto-Reset .............................................................................4713
77.4.1.3.2.2
Data-Pulse ..............................................................................4713
77.4.1.3.2.3
B-Disconnect to A-Connect...................................................4713
Host Data Structures..................................................................................................................................4714
77.4.2.1
Periodic Frame List................................................................................................................4715
77.4.2.2
Asynchronous List Queue Head Pointer................................................................................4717
77.4.2.3
Isochronous (High-Speed) Transfer Descriptor (iTD)...........................................................4718
77.4.2.4
77.4.2.5
77.4.2.6
77.4.2.3.1
Next Link Pointer-Host Data Structures.........................................................4719
77.4.2.3.2
iTD Transaction Status and Control List........................................................4720
77.4.2.3.3
iTD Buffer Page Pointer List (Plus)................................................................4721
Split Transaction Isochronous Transfer Descriptor (siTD)....................................................4722
77.4.2.4.1
Next Link Pointer............................................................................................4723
77.4.2.4.2
siTD Endpoint Capabilities/Characteristics....................................................4723
77.4.2.4.3
siTD Transfer State.........................................................................................4724
77.4.2.4.4
siTD Buffer Pointer List (plus).......................................................................4725
77.4.2.4.5
siTD Back Link Pointer..................................................................................4726
Queue Element Transfer Descriptor (qTD)............................................................................4726
77.4.2.5.1
Next qTD Pointer............................................................................................4728
77.4.2.5.2
Alternate Next qTD Pointer............................................................................4728
77.4.2.5.3
qTD Token......................................................................................................4729
77.4.2.5.4
qTD Buffer Page Pointer List.........................................................................4731
Queue Head............................................................................................................................4732
77.4.2.6.1
Queue Head Horizontal Link Pointer.............................................................4733
77.4.2.6.2
Queue Head Endpoint Capabilities/Characteristics........................................4733
77.4.2.6.3
Transfer Overlay-Queue Head........................................................................4735
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Section Number
77.4.2.7
77.4.3
Title
Page
Periodic Frame Span Traversal Node (FSTN) ......................................................................4737
77.4.2.7.1
FSTN Normal Path Pointer ............................................................................4738
77.4.2.7.2
FSTN Back Path Link Pointer .......................................................................4738
Host Operational Model ............................................................................................................................4739
77.4.3.1
Host Controller Initialization ................................................................................................4739
77.4.3.2
Port Routing and Control ......................................................................................................4740
77.4.3.3
77.4.3.2.1
Port Routing Control through EHCI Configured (CF) Bit ............................4742
77.4.3.2.2
Port Routing Control through PortOwner and Disconnect Event ..................4743
77.4.3.2.3
Example Port Routing State Machine ............................................................4745
EHCI HC Owner ...................................................................4745
77.4.3.2.3.2
Companion HC Owner ..........................................................4746
77.4.3.2.4
Port Power ......................................................................................................4746
77.4.3.2.5
Port Reporting Over-Current .........................................................................4747
Suspend/Resume-Host Operational Model ...........................................................................4748
77.4.3.3.1
77.4.3.4
77.4.3.2.3.1
Port Suspend/Resume ....................................................................................4749
Schedule Traversal Rules ......................................................................................................4751
77.4.3.4.1
Example - Preserving Micro-Frame Integrity ................................................4753
77.4.3.4.1.1
Transaction Fit - A Best-Fit Approximation Algorithm ........4754
77.4.3.5
Periodic Schedule Frame Boundaries vs Bus Frame Boundaries .........................................4756
77.4.3.6
Periodic Schedule ..................................................................................................................4758
77.4.3.7
Managing Isochronous Transfers Using iTDs ......................................................................4760
77.4.3.7.1
Host Controller Operational Model for iTDs .................................................4761
77.4.3.7.2
Software Operational Model for iTDs ...........................................................4762
77.4.3.7.2.1
77.4.3.8
Periodic Scheduling Threshold...............................................4765
Asynchronous Schedule ........................................................................................................4766
77.4.3.8.1
Adding Queue Heads to Asynchronous Schedule..........................................4767
77.4.3.8.2
Removing Queue Heads from Asynchronous Schedule ................................4768
77.4.3.8.3
Empty Asynchronous Schedule Detection .....................................................4770
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Section Number
Title
77.4.3.8.4
Page
Restarting Asynchronous Schedule Before EOF ...........................................4771
77.4.3.8.4.1
Example Method for Restarting Asynchronous Schedule
Traversal ................................................................................4772
77.4.3.9
Async Sched Not Active .......................................................4773
77.4.3.8.4.3
Async Sched Active ..............................................................4773
77.4.3.8.4.4
Async Sched Sleeping ...........................................................4774
77.4.3.8.4.5
Example Derivation for AsyncSchedSleepTime....................4774
77.4.3.8.5
Asynchronous Schedule Traversal: Start Event..............................................4775
77.4.3.8.6
Reclamation Status Bit (USBSTS Register) ..................................................4775
Operational Model for Nak Counter......................................................................................4775
77.4.3.9.1
77.4.3.10
77.4.3.8.4.2
Nak Count Reload Control .............................................................................4777
77.4.3.9.1.1
Wait for List Head .................................................................4778
77.4.3.9.1.2
Do Reload ..............................................................................4778
77.4.3.9.1.3
Wait for Start Event ...............................................................4778
Managing Control/Bulk/Interrupt Transfers through Queue Heads......................................4779
77.4.3.10.1
Fetch Queue Head ..........................................................................................4781
77.4.3.10.2
Advance Queue ..............................................................................................4781
77.4.3.10.3
Execute Transaction .......................................................................................4782
77.4.3.10.3.1 Interrupt Transfer Pre-condition Criteria ...............................4783
77.4.3.10.3.2 Asynchronous Transfer Pre-operations and Pre-condition
Criteria ...................................................................................4783
77.4.3.10.3.3 Transfer Type Independent Pre-operations............................4783
77.4.3.10.3.4 Halting a Queue Head ...........................................................4786
77.4.3.10.3.5 Asynchronous Schedule Park Mode ......................................4787
77.4.3.10.4
Write Back qTD .............................................................................................4789
77.4.3.10.5
Follow Queue Head Horizontal Pointer .........................................................4789
77.4.3.10.6
Buffer Pointer List Use for Data Streaming with qTDs ................................4790
77.4.3.10.7
Adding Interrupt Queue Heads to the Periodic Schedule ..............................4792
77.4.3.10.8
Managing Transfer Complete Interrupts from Queue Heads ........................4792
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Section Number
Title
Page
77.4.3.11
Ping Control...........................................................................................................................4793
77.4.3.12
Split Transactions ..................................................................................................................4794
77.4.3.12.1
Split Transactions for Asynchronous Transfers .............................................4795
77.4.3.12.1.1 Asynchronous - Do Start Split................................................4796
77.4.3.12.1.2 Asynchronous - Do Complete Split .......................................4796
77.4.3.12.2
Split Transaction Interrupt .............................................................................4797
77.4.3.12.2.1 Split Transaction Scheduling Mechanisms for Interrupt .......4798
77.4.3.12.2.2 Host Controller Operational Model for FSTNs......................4801
77.4.3.12.2.3 Software Operational Model for FSTNs................................4804
77.4.3.12.2.4 Tracking Split Transaction Progress for Interrupt Transfers .4805
77.4.3.12.2.5 Split Transaction Execution State Machine for Interrupt ......4806
77.4.3.12.2.6 Rebalancing the Periodic Schedule .......................................4812
77.4.3.12.3
Split Transaction Isochronous ........................................................................4813
77.4.3.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous . 4813
77.4.3.12.3.2 Tracking Split Transaction Progress for Isochronous
Transfers.................................................................................4818
77.4.3.12.3.3 Split Transaction Execution State Machine for Isochronous 4820
77.4.3.12.3.4 Periodic Isochronous - Do Start Split ....................................4821
77.4.3.12.3.5 Periodic Isochronous - Do Complete Split ............................4823
77.4.3.12.3.6 Complete-Split for Scheduling Boundary Cases 2a, 2b ........4826
77.4.3.12.3.7 Split Transaction for Isochronous - Processing Examples ....4828
77.4.3.13
Host Controller Pause............................................................................................................4830
77.4.3.14
Port Test Modes -Host Operational Model............................................................................4831
77.4.3.15
Interrupts-Host Operational Model........................................................................................4831
77.4.3.15.1
Transfer/Transaction Based Interrupts ...........................................................4833
77.4.3.15.1.1 Transaction Error ...................................................................4833
77.4.3.15.1.2 Serial Bus Babble...................................................................4833
77.4.3.15.1.3 Data Buffer Error ...................................................................4834
77.4.3.15.1.4 USB Interrupt (Interrupt on Completion (IOC)) ...................4835
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77.4.3.15.1.5 Short Packet............................................................................4835
77.4.3.15.2
Host Controller Event Interrupts ....................................................................4835
77.4.3.15.2.1 Port Change Events ...............................................................4836
77.4.3.15.2.2 Frame List Rollover ...............................................................4836
77.4.3.15.2.3 Interrupt on Async Advance ..................................................4836
77.4.3.15.2.4 Host System Error .................................................................4836
77.4.4
EHCI Deviation..........................................................................................................................................4838
77.4.4.1
Embedded Transaction Translator Function..........................................................................4838
77.4.4.1.1
Capability Registers........................................................................................4838
77.4.4.1.2
Operational Registers......................................................................................4839
77.4.4.1.3
Discovery-EHCI Deviation.............................................................................4839
77.4.4.1.4
Data Structures................................................................................................4839
77.4.4.1.5
Operational Model..........................................................................................4840
77.4.4.1.5.1
Micro- frame Pipeline.............................................................4840
77.4.4.1.5.2
Split State Machines...............................................................4841
77.4.4.1.5.3
Asynchronous Transaction Scheduling and Buffer
Management...........................................................................4842
77.4.4.1.5.4
USB 2.0 - 11.17.3...................................................................4842
77.4.4.1.5.5
USB 2.0 - 11.17.4...................................................................4842
77.4.4.1.5.6
Periodic Transaction Scheduling and Buffer Management....4842
77.4.4.1.5.7
USB 2.0 - 11.18.6.[1-2]..........................................................4842
77.4.4.1.5.8
USB 2.0 - 11.18.[7-8].............................................................4842
77.4.4.1.5.9
Multiple Transaction Translators...........................................4843
77.4.4.2
Device Operation...................................................................................................................4843
77.4.4.3
USB.USBMODE Register.....................................................................................................4843
77.4.4.4
77.4.4.3.1
Non-Zero Fields the Register File...................................................................4843
77.4.4.3.2
SOF Interrupt..................................................................................................4844
Embedded Design Interface...................................................................................................4844
77.4.4.4.1
Frame Adjust Register....................................................................................4844
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Title
Miscellaneous variations from EHCI.....................................................................................4844
77.4.4.5.1
Programmable Physical Interface Behaviour..................................................4844
77.4.4.5.2
Discovery........................................................................................................4845
77.4.4.5.3
77.4.5
77.4.4.5.2.1
Port Reset................................................................................4845
77.4.4.5.2.2
Port Speed Detection..............................................................4845
Port Test Mode................................................................................................4845
Device Data Structures...............................................................................................................................4846
77.4.5.1
77.4.5.2
77.4.6
Page
Endpoint Queue Head (dQH).................................................................................................4847
77.4.5.1.1
Endpoint Capabilities/Characteristics.............................................................4848
77.4.5.1.2
Transfer Overlay-Endpoint Queue Head........................................................4849
77.4.5.1.3
Current dTD Pointer.......................................................................................4849
77.4.5.1.4
Set-up Buffer...................................................................................................4850
Endpoint Transfer Descriptor (dTD)......................................................................................4850
Device Operational Model.........................................................................................................................4852
77.4.6.1
Device Controller Initialization.............................................................................................4852
77.4.6.2
Port State and Control............................................................................................................4854
77.4.6.2.1
Bus Reset........................................................................................................4856
77.4.6.2.2
Suspend/Resume.............................................................................................4857
77.4.6.2.2.1
Suspend...................................................................................4857
77.4.6.2.2.2
Resume...................................................................................4858
77.4.6.2.2.3
Port Test Modes......................................................................4858
77.4.6.2.3
Managing Endpoints.......................................................................................4858
77.4.6.2.4
Endpoint Initialization....................................................................................4859
77.4.6.2.5
Stalling............................................................................................................4860
77.4.6.2.6
Data Toggle ....................................................................................................4861
77.4.6.2.6.1
Data Toggle Reset..................................................................4861
77.4.6.2.6.2
Data Toggle Inhibit.................................................................4861
77.4.6.2.6.3
Priming Transmit Endpoints...................................................4862
77.4.6.2.6.4
Priming Receive Endpoints....................................................4862
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Title
Operational Model For Packet Transfers...............................................................................4863
77.4.6.3.1
Interrupt/Bulk Endpoint Operational Model...................................................4863
77.4.6.3.1.1
77.4.6.3.2
77.4.6.3.3
77.4.6.4
77.4.6.5
77.4.6.6
77.5
Page
Interrupt/Bulk Endpoint Bus Response Matrix......................4865
Control Endpoint Operation Model................................................................4865
77.4.6.3.2.1
Setup Phase.............................................................................4865
77.4.6.3.2.2
Data Phase..............................................................................4867
77.4.6.3.2.3
Status Phase............................................................................4868
77.4.6.3.2.4
Control Endpoint Bus Response Matrix.................................4868
Isochronous Endpoint Operational Model......................................................4869
77.4.6.3.3.1
Isochronous Pipe Synchronization.........................................4871
77.4.6.3.3.2
Isochronous Endpoint Bus Response Matrix.........................4871
Managing Queue Heads.........................................................................................................4871
77.4.6.4.1
Queue Head Initialization...............................................................................4872
77.4.6.4.2
Operational Model For Setup Transfers.........................................................4873
Managing Transfers with Transfer Descriptors.....................................................................4874
77.4.6.5.1
Software Link Pointers...................................................................................4874
77.4.6.5.2
Building a Transfer Descriptor.......................................................................4874
77.4.6.5.3
Executing A Transfer Descriptor....................................................................4875
77.4.6.5.4
Transfer Completion.......................................................................................4876
77.4.6.5.5
Flushing/De-priming an Endpoint..................................................................4876
77.4.6.5.6
Device Error Matrix........................................................................................4877
Servicing Interrupts................................................................................................................4878
77.4.6.6.1
High-Frequency Interrupts..............................................................................4878
77.4.6.6.2
Low-Frequency Interrupts..............................................................................4878
77.4.6.6.3
Error Interrupts................................................................................................4879
USB Non-Core Memory Map/Register Definition.......................................................................................................4879
77.5.1
USB Control Register 0 (USB_USB_CTRL_0)........................................................................................4881
77.5.2
USB OTG UTMI PHY Control Register 0 (USB_USB_OTG_PHY_CTRL_0)......................................4883
77.5.3
USB OTG UTMI PHY Control Register 1 (USB_USB_OTG_PHY_CTRL_1)......................................4885
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Title
Page
77.5.4
USB Control Register 1 (USB_USB_CTRL_1)........................................................................................4888
77.5.5
USB Host2 Control Register (USB_USB_UH2_CTRL)...........................................................................4890
77.5.6
USB Host3 Control Register (USB_USB_UH3_CTRL)...........................................................................4892
77.5.7
USB Host1 UTMI PHY Control Register 0 (USB_USB_UH1_PHY_CTRL_0).....................................4895
77.5.8
USB Host1 UTMI PHY Control Register 1 (USB_USB_UH1_PHY_CTRL_1).....................................4897
77.5.9
USB Clock on/off control Register (USB_USB_CLKONOFF_CTRL)...................................................4899
USB Core Memory Map/Register Definition...............................................................................................................4901
77.6.1
Identification register (USB_n_ID)...........................................................................................................4907
77.6.2
Hardware General (USB_n_HWGENERAL)............................................................................................4908
77.6.3
Host Hardware Parameters (USB_n_HWHOST)......................................................................................4909
77.6.4
Device Hardware Parameters (USB_UOG_HWDEVICE).......................................................................4910
77.6.5
TX Buffer Hardware Parameters (USB_n_HWTXBUF)..........................................................................4911
77.6.6
RX Buffer Hardware Parameters (USB_n_HWRXBUF)..........................................................................4911
77.6.7
General Purpose Timer #0 Load (USB_n_GPTIMER0LD)......................................................................4912
77.6.8
General Purpose Timer #0 Controller (USB_n_GPTIMER0CTRL).........................................................4913
77.6.9
General Purpose Timer #1 Load (USB_n_GPTIMER1LD)......................................................................4914
77.6.10
General Purpose Timer #1 Controller (USB_n_GPTIMER1CTRL).........................................................4915
77.6.11
System Bus Config (USB_n_SBUSCFG).................................................................................................4916
77.6.12
Capability Register Length (USB_n_CAPLENGTH)...............................................................................4917
77.6.13
Host Controller Interface Version (USB_n_HCIVERSION)....................................................................4917
77.6.14
Host Controller Structural Parameters (USB_n_HCSPARAMS).............................................................4918
77.6.15
Host Controller Capability Parameters (USB_n_HCCPARAMS)............................................................4920
77.6.16
Device Controller Interface Version (USB_UOG_DCIVERSION)..........................................................4921
77.6.17
Device Controller Capability Parameters (USB_UOG_DCCPARAMS)..................................................4922
77.6.18
USB Command Register (USB_n_USBCMD)..........................................................................................4922
77.6.19
USB Status Register (USB_n_USBSTS)...................................................................................................4926
77.6.20
Interrupt Enable Register (USB_n_USBINTR).........................................................................................4929
77.6.21
USB Frame Index (USB_n_FRINDEX)....................................................................................................4931
77.6.22
Frame List Base Address (USB_n_PERIODICLISTBASE).....................................................................4932
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77.6.23
Device Address (USB_UOG_DEVICEADDR)........................................................................................4933
77.6.24
Next Asynch. Address (USB_n_ASYNCLISTADDR).............................................................................4934
77.6.25
Endpoint List Address (USB_UOG_ENDPTLISTADDR).......................................................................4935
77.6.26
Programmable Burst Size (USB_n_BURSTSIZE)....................................................................................4935
77.6.27
TX FIFO Fill Tuning (USB_n_TXFILLTUNING)...................................................................................4936
77.6.28
IC_USB enable and voltage negotiation (USB_n_IC_USB).....................................................................4938
77.6.29
Endpoint NAK (USB_UOG_ENDPTNAK)..............................................................................................4939
77.6.30
Endpoint Nake Enable (USB_UOG_ENDPTNAKEN)............................................................................4939
77.6.31
Port Status & Control (USB_n_PORTSC1)..............................................................................................4940
77.6.32
On-The-Go Status & control (USB_UOG_OTGSC).................................................................................4947
77.6.33
USB Device Mode (USB_n_USBMODE)................................................................................................4950
77.6.34
Endpoint Setup Status (USB_UOG_ENDPTSETUPSTAT).....................................................................4951
77.6.35
Endpoint Initialization (USB_UOG_ENDPTPRIME)..............................................................................4952
77.6.36
Endpoint De-Initialize (USB_UOG_ENDPTFLUSH)..............................................................................4953
77.6.37
Endpoint Status (USB_UOG_ENDPTSTAT)...........................................................................................4953
77.6.38
Endpoint Complete (USB_UOG_ENDPTCOMPLETE)..........................................................................4954
77.6.39
Endpoint Control0 (USB_UOG_ENDPTCTRL0).....................................................................................4955
77.6.40
Endpoint Controln (USB_UOG_ENDPTCTRLn).....................................................................................4956
77.6.41
ULPI Viewport (USB_n_ULPIVIEW)......................................................................................................4959
Chapter 78
Video Processing Unit (VPU)
78.1
Introduction ..................................................................................................................................................................4963
78.1.1
Overview....................................................................................................................................................4964
78.1.2
Features......................................................................................................................................................4964
78.1.3
Modes of Operation...................................................................................................................................4966
78.1.3.1
Normal Operating Mode........................................................................................................4966
78.1.3.2
Low Power Mode...................................................................................................................4966
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78.2
Title
Page
Functional Description..................................................................................................................................................4967
78.2.1
VPU Architecture.......................................................................................................................................4967
78.2.1.1
Embedded BIT processor.......................................................................................................4967
78.2.1.2
Video CODEC Hardware.......................................................................................................4968
78.2.1.2.1
Inter-Predictor.................................................................................................4968
78.2.1.2.2
AC/DC and Intra-Predictor.............................................................................4968
78.2.1.2.3
Inverse transform/Inverse quantization...........................................................4968
78.2.1.2.4
De-blocking/Overlap-smoothing filter............................................................4968
78.2.1.2.5
Coefficient buffer interface.............................................................................4969
78.2.1.2.6
Macroblock controller.....................................................................................4969
78.2.1.2.7
Rotation/Mirroring .........................................................................................4970
78.2.2
Clocks.........................................................................................................................................................4971
78.2.3
Reset...........................................................................................................................................................4972
78.2.4
Interrupts....................................................................................................................................................4973
78.2.5
Endianness.................................................................................................................................................4973
78.3
Initialization Information..............................................................................................................................................4973
78.4
Application Information................................................................................................................................................4974
78.4.1
78.4.2
Video Decoding Processing Control..........................................................................................................4975
78.4.1.1
Video Decoding Process Flow...............................................................................................4975
78.4.1.2
Video Decoding Process Command......................................................................................4977
78.4.1.3
Video Decoding Process Finish Detection.............................................................................4978
78.4.1.4
Video Decoding Process Flow Example................................................................................4979
Video Encoding Processing Control..........................................................................................................4981
78.4.2.1
78.4.3
The Pipeline for Encoding.....................................................................................................4981
Video Codec Processing Buffer Requirement...........................................................................................4983
78.4.3.1
Memory Map Types of Frame Buffer....................................................................................4984
78.4.3.2
Frame Buffer..........................................................................................................................4985
78.4.3.3
BIT Processor Program Buffer..............................................................................................4988
78.4.3.4
Working Buffer......................................................................................................................4989
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Title
Page
78.4.3.5
Bitstream Buffer.....................................................................................................................4990
78.4.3.6
Parameter Buffer....................................................................................................................4990
78.4.3.7
Search RAM...........................................................................................................................4991
78.4.3.8
Buffer Requirement Summary...............................................................................................4991
Programmable Registers...............................................................................................................................................4992
78.5.1
BIT Processor run start (VPU_CodeRun)..................................................................................................4994
78.5.2
BIT Boot Code Download Data register (VPU_CodeDown)....................................................................4994
78.5.3
Host Interrupt Request to BIT (VPU_HostIntReq)....................................................................................4995
78.5.4
BIT Interrupt Clear (VPU_BitIntClear).....................................................................................................4996
78.5.5
BIT Interrupt Status (VPU_BitIntSts)........................................................................................................4997
78.5.6
BIT Code Reset (VPU_BitCodeReset)......................................................................................................4998
78.5.7
BIT Current PC (VPU_BitCurPc)..............................................................................................................4999
78.5.8
BIT CODEC Busy (VPU_BitCodecBusy)................................................................................................5000
Chapter 79
Watchdog Timer (WDOG-1)
79.1
Introduction...................................................................................................................................................................5001
79.2
Overview.......................................................................................................................................................................5001
79.2.1
Features......................................................................................................................................................5002
79.2.2
Modes and Operations...............................................................................................................................5003
79.3
External Signals............................................................................................................................................................5003
79.4
Functional Description..................................................................................................................................................5003
79.4.1
Time-Out Event..........................................................................................................................................5003
79.4.1.1
Servicing WDOG-1 To Reload The Counter.........................................................................5004
79.4.2
Interrupt Event...........................................................................................................................................5004
79.4.3
Power-Down Counter Event......................................................................................................................5005
79.4.4
Low Power Modes.....................................................................................................................................5005
79.4.5
79.4.4.1
STOP and DOZE Mode.........................................................................................................5005
79.4.4.2
WAIT Mode...........................................................................................................................5005
Debug Mode...............................................................................................................................................5006
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79.4.6
Title
Page
Operations..................................................................................................................................................5006
79.4.6.1
Watchdog Reset Generation...................................................................................................5006
79.4.6.2
WDOG_B Generation............................................................................................................5006
79.4.7
Clocks.........................................................................................................................................................5008
79.4.8
Reset...........................................................................................................................................................5009
79.4.9
Interrupt......................................................................................................................................................5009
79.4.10
Flow Diagrams...........................................................................................................................................5009
79.5
Initialization..................................................................................................................................................................5013
79.6
Programmable Registers...............................................................................................................................................5014
79.6.1
Watchdog Control Register (WDOG_WCR)............................................................................................5014
79.6.2
Watchdog Service Register (WDOG_WSR).............................................................................................5016
79.6.3
Watchdog Reset Status Register (WDOG_WRSR)...................................................................................5017
79.6.4
Watchdog Interrupt Control Register (WDOG_WICR)............................................................................5018
79.6.5
Watchdog Miscellaneous Control Register (WDOG_WMCR).................................................................5019
Chapter 80
Crystal Oscillator 24 MHz (XTALOSC)
80.1
Introduction...................................................................................................................................................................5021
80.1.1
Interface Specification...............................................................................................................................5021
80.1.2
Crystal Operating Frequency ....................................................................................................................5022
80.1.3
Power Supply.............................................................................................................................................5022
80.1.4
Operating Temperature .............................................................................................................................5023
80.1.5
Input Clock in Bypass Mode .....................................................................................................................5023
80.1.6
Input Control Signal...................................................................................................................................5023
80.1.7
Output Clock .............................................................................................................................................5023
80.2
External Signals............................................................................................................................................................5023
80.3
Operation Modes ..........................................................................................................................................................5023
80.3.1
Crystal Osc Mode.......................................................................................................................................5024
80.3.2
Bypass Mode..............................................................................................................................................5024
80.3.3
Low Power Mode.......................................................................................................................................5024
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Title
Page
Oscillator Safety Margin Requirements.....................................................................................................5024
Chapter 81
Crystal Oscillator 32K (XTALOSC32K)
81.1
Introduction...................................................................................................................................................................5025
81.2
Features.........................................................................................................................................................................5025
81.3
External Signals............................................................................................................................................................5026
81.4
Memory Map/Register Definition.................................................................................................................................5027
81.5
Functional Description..................................................................................................................................................5027
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Chapter 1
Introduction
1.1 About This Document
This reference manual describes the functionality of the i.MX53 multimedia applications
processor. The i.MX53 is Freescale Semiconductor's latest addition to a growing family
of multimedia-focused products offering high performance processing optimized for
lowest power consumption. The i.MX53 processors feature Freescale's advanced
implementation of the ARM®Cortex™-A8 core, which operates at speeds as high as 1.2
GHz and interfaces with DDR2-800, LVDDR2-800 and DDR3-800 DRAM memory
devices. This product is suitable for applications such as:
•
•
•
•
•
•
•
Automotive navigation and entertainment
High-end Mobile Internet Devices and high-end PDAs
Netbooks
Nettops
High-end portable media players with HD video capability
Portable navigation devices
Gaming Consoles
The i.MX53 is a system on a chip (SoC) which integrates on one integrated circuit a
complete microcomputer platform based on the ARM Cortex-A8 including an integrated
NEON coprocessor, a vector floating point unit, an Execution Trace Module (ETM),
separate 32 Kbyte instruction and data L1 caches and a unified 256 Kbyte L2 cache.
Supporting the ARM Platform are a large array of system-level components such as
system RAM, processor code ROM, Smart DMA controller (SDMA) and system control
devices such as a power-on reset controller, voltage regulators, power management, onboard fuse array (FUSEBOX) and clock generation circuitry. Coprocessors including two
Graphics Processing Units (GPUs), an Image Processin Unit (IPU), Video Processing
Unit (VPU) and Asynchronous Sample Rate Converter (ASRC) accelerate
computationally intensive tasks offloading the ARM Platform.
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Included in the SoC are I/O devices such as USB controllers, UARTs, Ethernet
controllers, General Purpose I/O (GPIO), Multimedia processor, , general purpose and
special purpose timers, and system security devices. An integrated memory controller
supports the attachment of external DRAM. A Flash controller supports both NAND and
NOR Flash devices. Integrated external storage controllers support devices such as SATA
hard disks and SD/SDIO/MMC/eMMC memory cards.
1.1.1 Audience
This manual is intended to be used by board-level product designers and product software
developers. This manual assumes that the reader has a background in computer
engineering and/or software engineering and understands concepts of digital system
design, microprocessor architecture, Input / Output (I/O) devices and industry standard
communication and device interface protocols.
1.1.2 Organization
This document is organized in two main sections called Book I and Book II.
Book I covers the i.MX53 at a system level and provides an architectural overview. Also
covered are system memory map, system-level interrupt events, external pins and pin
multiplexing, external memory, system debug, system boot, multimedia subsystem,
power management, and system security.
Book II describes the ARM Platform, ARM Platform debug, and an array of internal
functional blocks.
1.1.3 Suggested Reading
This section lists additional reading that provides background for the information in this
manual as well as general information about the architecture.
1.1.3.1 General Information
The following documentation provides useful background information about the ARM
processor and computer architecture in general:
• For information about the ARM Cortex-A8 processor see http://www.arm.com/
products/processors/cortex-a/cortex-a8.php
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Chapter 1 Introduction
• Computer Architecture: A Quantitative Approach, Fourth Edition, by John L.
Hennessy and David A. Patterson
• Computer Organization and Design: The Hardware/Software Interface, Second
Edition, by David A. Patterson and John L. Hennessy
1.1.3.2 Related Documentation
Freescale documentation is available from the sources listed on the back cover of this
manual; the document order numbers are included in parentheses for ease in ordering:
For a current list of documentation, refer to www.freescale.com.
1.1.4 Conventions
This document uses the following notational conventions:
cleared / set
When a bit takes the value zero, it is said to be cleared; when it takes a value of one, it
is said to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold
italics
Italics indicate variable command parameters, for example, bcctrx
Book titles in text are set in italics
15
An integer in decimal
0x
Prefix to denote hexadecimal number
0b
Prefix to denote binary number. Binary 0 and 1 are written without the prefix.
n'H4000CA00
n-bit Hexadecimal number
BLK_REG_NAME
Register names are all uppercase. The block mnemonic is prepended with an
underscore delimiter (_).
BLK_REG[FIELD]
Fields within registers appear in brackets. For example, ESR[RLS] refers to the
Receive Last Slot field of the ESAI Status Register.
BLK_REG[ n]
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Bit number n within register BLK.REG. Bit numbering is little endian.
BLK_REG[ l:r]
Register bit ranges. Ranges are indicated by the left-most bit number l and the rightmost bit number r separated by a colon (:). For example, ESR[15:0] refers to the lower
half word in the ESAI Status Register.
x, U
In some contexts, such as signal encodings, an unitalicized x indicates a don't care or
uninitialized. The binary value could be 1 or 0.
x
An italicized x indicates an alphanumeric variable
n, m
Italicized n or m represent integer variables
!
Binary logic operator NOT
&&
Binary logic operator AND
||
Binary logic operator OR
^ or <O+>
Binary logic operator XOR
|
Bit-wise OR. For example, 0b0001 | 0b1000 yields the value 0b1001.
&
Bit-wise AND. For example, 0b0001 & 0b1000 yields the value 0b0000.
{A,B}
Concatenation, where the n-bit value A is prepended to the m-bit value B to form an (n
+m)-bit value. For example, {0, REGm [14:0]} yeilds a 16-bit value with 0 in the most
significant bit.
- or grey fill
Indicates a reserved bit field in an register. Although these bits can be written to as
ones or zeros, they are always read as zeros.
>>
Shift right logical one position
<<
Shift left logical one posiiton
= <left arrow>
Assignment
==
Compare equal
!=
Compare not equal
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Chapter 1 Introduction
>
Greater than
<
Less than
1.1.5 Register Diagram Field Access Type Legend
The following figure provides the interpretation of the notation used in register diagrams
for a number of common field access types.
R
0
1
Reserved
W returns 1
on read
Reserved
returns 0
on read
Fld
Read-only
field
rtc
Fld
Fld
R/W
field
Write-only
field
Fld
Write 1
to clear
w1c
Read
to clear
Fld
0
Selfclear bit
Reserved
Fld
Figure 1-1. Register Field Conventions
NOTE
For reserved register fields, software should mask off the data
in the field after read (software can not rely on the contents of
data read from a reserved field) and always write all zeros.
1.1.6 Signal Conventions
_b, _B
When appended to a signal name, indicates that a signal is active-low
NEG_ACTIVE
Overbar also denotes a negative active signal
UPPERCASE
Package pin names, Block I/O signals
lowercase
Lowercase is used to indicate internal signals
1.1.7 Acronyms and Abbreviations
Table 1- contains acronyms and abbreviations used in this document.
Acronyms and Abbreviated Terms
Term
Meaning
BIST
Built-in self test
DDR
Double data rate (of Dynamic RAM)
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About This Document
Term
Meaning
FIFO
First In / First Out (of a queue)
DMA
Direct memory access
DPLL
Digital phase-locked loop
DRAM
Dynamic random access memory
EPROM
Erasable programmable read-only memory
GPIO
General-purpose I/O
GPR
General-purpose register
GPU
Graphicd Processing Unit
I2C or I2C
Inter-integrated circuit
IEEE
Institute of Electrical and Electronics Engineers
IrDA
Infrared Data Association
JTAG
Joint Test Action Group (a serial bus protocol usually used for test purposes)
LIFO
Last-in-first-out
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
MSB
Most-significant byte
msb
Most-significant bit
PCI
Peripheral Component Interconnect
PCI-X
PCI extended
PCIe
PCI enhanced
PCMCIA
Personal Computer Memory Card International Association
PIC
Programmable interrupt controller
POR
Power-on reset
RISC
Reduced instruction set computing
RTOS
Real-time operating system
Rx
Receive
SDLC
Synchronous data link control
SDMA
Serial DMA
SPDIF
Sony Phillips Digital Interface
SPI
Serial peripheral interface
SRAM
Static random access memory
Tx
Transmit
UART
Universal asynchronous receiver/transmitter
USB
Universal serial bus
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Chapter 1 Introduction
1.2 Overview
This chapter introduces the architecture of the i.MX53 Multimedia Applications
Processor. The i.MX53 processor represents Freescale Semiconductor's latest
achievement in multimedia integrated applications processors that are part of a growing
family of multimedia-focused products offering high performance processing optimized
for lowest power consumption.
1.3 Target Applications
The primary market focus of the i.MX53 applications processor is high-end Mobile
Internet Devices (MIDs) and Automotive Infotainment. A secondary focus is High End
Portable Multimedia Players (PMPs) with HD video capability, as well as markets with
similar requirements in terms of package type, thermal limits and I/O. The flexibility of
the i.MX53 architecture permits in a wide variety of other applications. The i.MX53
processor provides all of the interfaces for connecting peripherals such as WLAN,
Bluetooth, GPS, camera sensors, and dual displays.
The i.MX53 application processor is a follow-on to the i.MX51 with improved
performance, power efficiency and multimedia capabilities.
1.4 Features
The i.MX53 ARM Platform (AP) is based on the ARM Cortex A8™ Architecture, which
has the following features:
•
•
•
•
•
•
ARM Cortex A8™ Processor (with TrustZone)
32 Kbyte L1 instruction cache
32 Kbyte L1 data cache
256 Kbyte unified instruction and data L2 cache
A range of core processor clock speeds (up to 1.2 GHz) based on part number.
Neon coprocessor
• SIMD Media Processing Architecture
• NEON register file with 32x64-bit general-purpose registers
• NEON Integer execute pipeline (ALU, Shift, MAC)
• NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
• NEON load/store and permute pipeline
• Non-pipelined Vector Floating Point (VFP) coprocessor (VFPv3)
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The i.MX53 makes use of dedicated hardware (H/W) accelerators in order to meet
specific targeted multimedia performance requirements. The use of H/W accelerators is
key factor in obtaining high performance at low power consumption while leaving the
ARM platform core relatively free for performing other tasks.
The i.MX53 incorporates the following hardware accelerators:
•
•
•
•
•
VPU-Video Processing Unit
IPU-Image Processing Unit, version 3M
GPU3D-3D Graphics Processing Unit (OpenGL ES 2.0), version 3
GPU2D-2D Graphics accelerator, (OpenVG 1.1), version 1
ASRC-Asynchronous Sample Rate Converter
Security features are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory
mapping, etc.)
• SJC-System JTAG Controller. Protects JTAG from debug port attacks by regulating
or blocking access to the system debug features
• SRTC-Secure Real-Time Clock (RTC). Tamper resisted RTC with it's own power
domain and mechanism to detect voltage and clock glitches
• RTIC-Real-Time Integrity Checker, version 3, RTIC type 1, enhanced with SHA-256
engine
• SAHARA-Cryptographic accelerator that includes true random number generator
(TRNG)
• SCC-Security Controller, type 2. Improved SCC v1 with AES engine, Secure/NonSecure RAM and support for multiple keys as well as TZ/non-TZ separation
• CSU-Central Security Unit. Enhancement for the IC Identification Module (IIM)
configured during boot using e-fuses. Determines the security level operation mode
as well as the TZ policy
• AHAB-Advanced High Assurance Boot, with the next embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU and TZ
initialization
Integrated memory system:
• Boot ROM, including High Assurance Boot (HAB) (64 KB)
• Internal multimedia / shared, fast access RAM (128 KB)
• Secure/non-secure RAM (16 KB)
The i.MX53 SoC is built around the following System buses:
• 64-bit AMBA AXI v1.0 (AXI). Provides high-bandwidth, low-latency connectivity
for the ARM Platform, major multimedia accelerators (VPU, IPU, GPU3D, GPU2D)
and the External Memory Controller (EXTMC)
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• 32-bit AMBA AHB 2.0 (AHB). Provides connectivity for bus master peripherals,
such as SDMA, RTIC, SCC, and SAHARA. (See block diagram for the complete
list.)
• 32-bit Internal Peripheral (IP) Bus. Provides control and data communication for
lower speed integrated peripheral devices.
The i.MX53 enables following interfaces to external devices (some of which are not
available simultaneously):
• Hard Disk Drives
• PATA, supports U-DMA mode 5 at transfer rates up to 100 MByte/sec.
• SATA II protocol with a peak transfer rate of 3.0 Gbits per second.
• Displays
• 5 interfaces available. Total rate of all interfaces is up to 180 Mpixels/sec, 24 bits
per pixel. Up to two interfaces may be active at once.
• Two Parallel 24-bit display ports supporting up to 165 Mpixels/sec (UXGA @
60Hz)
• LVDS serial ports: One port up to 165 Mpixels/sec or two ports up to 85
Mpixels/sec (WXGA @ 60Hz) each
• One TV-out/VGA port up to 150 Mpixels/sec (1080p at 60 Hz)
• Camera sensors
• Two parallel camera ports
• Primary port only: up to 20 bits/pixel, up to 180 MHz peak pixel clock rate
• Simultaneous use: 8-bit primary and 8-bit secondary.
• Expansion cards
• Four SD/MMC card ports:
• Two of which support 208 Mbps (4-bit)
• One 416 Mbits/sec
• One enhanced port - supports 832 Mbps, (8-bit, eMMC 4.4).
• External memory interfaces
• 16/32-bit DDR2-800, LV-DDR2-800 and DDR3-800
• 8/16-bit NAND SLC/MLC Flash, 4/8/14/16-bit ECC.
• Supports Samsung OneNAND™ (in muxed I/O mode)
• 8/16/32-bit NOR Flash (8-bit is not supported at byte D[23:16]). Interface is
provided via the External Interface Module (EIM), all EIM pins are muxed with
other interfaces (data with NAND Flash Controller (NFC) pins). I/O muxing
logic selects the EIM port as primary muxing at system boot.
• 8/16/32-bit Pseudostatic RAM (PSRAM), Cellular RAM.
• USB
• High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
• Three USB 2.0 (480 Mbps) hosts:
• HS host, with integrated High Speed Phy.
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• HS host for external HS/FS Transceivers via ULPI / Serial, supports IC-USB
• HS host for external HS/FS Transceivers via ULPI / Serial, supports IC-USB
• Low Power modes
• Supporting DVFS techniques for low power modes
• Uses SRPG (State Retention Power Gating) for ARM and Neon
• Support for various levels of system power modes
• Flexible clock gating control scheme
• Other interfaces:
• OWIRE
• Three I2S/SSI/AC97, up to 1.4 Mbps each connected to Audio Multiplexer
(AUDMUX) providing four external ports
• Enhanced Serial Audio Interface (ESAI), up to 1.4 Mbps each channel
• Five UART, up to 4.0 Mbps each
• One of the five supports 8-wire (uart1) while others four supports 4-wire.
• One CSPI; refer to the data sheet for performance parameters.
• Two eCSPI (enhanced CSPI); refer to the data sheet for performance parameters.
• Three I2C, supports 400 Kbps
• Fast Ethernet Controller (FEC) IEEE1588 compliant, 10/100 Mbps
• Two Pulse Width Modulators (PWM)
• JTAG Controller (SJC)
• GPIO with interrupt capabilities
• Key Pad Port (KPP)
• Sony Phillips Digital Interface (SPDIF), Rx and Tx
• Two Controller Area Network (FLEXCAN), 1 Mbps each
• Two Watchdog timers (WDOG)
• Media Local Bus controller (MLB) provides interface to Media Oriented
Systems Transport (MOST) Networks (50Mbps)
1.5 Architectural Overview
This section contains i.MX53 architectural details.
A simplified block diagram is provided in the following section.
1.5.1 Simplified Block Diagram
A high-level block diagram of the i.MX53 is shown in Figure 1-2. It provides a view of
the major sub-systems (processor domains, shared peripherals domain, memories, etc.)
and logical connectivity.
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Figure 1-2. i.MX53 Simplified Block Diagram
1.5.2 Major Subsystems
i.MX53 consists of the following major subsystems:
• Core (ARM Cortex A8) Platform, L1/L2 memories
• SDMA controller and the shared peripheral domain
• System Control-Boot Flow control, Clocks distribution, "Reset" control and Low
Power logic
• Multimedia
• Security
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• Connectivity peripherals and timers
• External Memory Interface
1.5.3 Architectural Partitioning
The i.MX53 Architecture may be functionally organized in terms of five sub-systems.
These are:
• The ARM Platform is the central processing unit for the SoC and runs the following
software:
• Power-on-Reset (POR) boot code
• Boot-strap loader
• Operating system and application program loader
• User applications (including control over hardware accelerators and nonaccelerated functions)
• TrustZone applications
• Smart DMA enables data transfer between non-mastering (slave) peripherals and
external or internal memories
• System Control
• Clock Control Block (CCM)
• Four PLLs
• XTALOSC- 24MHz Crystal oscillator source support
• XTALOSC32k- 32k Crystal oscillator support
• System Reset Controller (SRC)
• Global Power Controller (GPC)
• Two Clock Amplifier (CAMP) blocks on CKIH and CKIH2 pins
• Temperature Sensor, for monitoring and acting on high temperature situations.
NOTE
Refer to SATA Temperature Sensor application note
(AN4380) for more details regarding programming and
its usage.
• Multimedia
• Image Processing Unit-IPU
• Connectivity to displays, display controllers, cameras and auxiliary graphics
coprocessors.
• Display Processing: video/graphics combining, image enhancement
• Image conversions: resizing, rotation/inversion, color conversion,
deinterlacing
• Synchronization and control capabilities, allowing autonomous operation
• Video Processing Unit (VPU):
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• Various decoding/encoding formats in HW
• Up to 1080i/p resolution (H.264, VC1, RV10, DivX)
• Up to 720p encode (MPEG4, H.264)
• TV-Encoder (TVE) for HD720p/1080p, PAL/NTSC or VGA output
• Graphics Processing Unit (GPU3D), 3D graphics processing compliant with the
following:
• OpenGL ES Common Profile v1.0
• OpenGL ES Common Profile v1.1/Direct3D Mobile
• OpenGL ES Profile v2.0
• Graphics Processing Unit (GPU2D), 2D graphics processing:
• OpenVG 1.1
• Audio
• Audio codecs are provided by SW, which runs on ARM core, supporting
(but not limited to) MP3, WMA, AAC, HE-AAC and Pro10
• 3x SSIs
• ESAI
• SPDIF Tx/Rx
• Audio Mux
• ASRC (for sample rate conversion)
• Security
• High Assurance Boot (HAB) System
• ARM TrustZone (TZ) Trusted Execution environment
• IC Identification Module (IIM) and Central Security Unit (CSU)
• On-chip One-Time programmable electrical fuse array (FUSEBOX)
• RTIC: Real-Time Integrity Checker
• SAHARA Version 4 Lite (SAHARA) cryptographic acceleration engine
• System JTAG controller (SJC)
• Secure Real Time Clock (SRTC)
• Security Controller version 2 (SCC) with 16KByte of secure/non-secure RAM
• Tamper Detection
• TrustZone Watchdog (WDOG-2)
• Connectivity peripherals and timers
• Low level communication protocols
• Embedded DMAs
• 3.3V IO voltage for seamless integration
• Four USB 2.0 ports, including two integrated PHYs
• TV-Out Video codecs for HD, NTSC/PAL or VGA output
• DDR2/3, LPDDR2 (PoP package), Nand (MLC 4/8/14/16-bit ECC) and NOR
Flash memory interface via EMC
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Block List
• Timers: 2xEPIT, GPT and Watch Dog timer (WDOG)
• Miscellaneous connectivity support-I2C, SPI, UART, PWM and Keypad
interface
• External Memory Controller (EXTMC)
• External Memory Interface
• Integrated DRAM controller
• Support for DDR2, DDR3, LV-DDR and LPDRAM
• Other external storage devices
• Support for NAND and NOR Flash
• Support for PSRAM and Cellular RAM
1.5.4 Endianness Support
i.MX53 supports Little Endian mode only.
1.6 Block List
Table 1-1 provides listing of the blocks used by the various subsystems of the i.MX53.
Table 1-1. Digital and Analog Blocks
Block Mnemonic
Block Name
Subsystem
Brief Description
ARM Platform
ARM Cortex A8™
Platform
ARM
The ARM Platform consists of the ARM Cortex A8™
processor and its essential sub-blocks, the Level 2 Cache
Controller and memory, event monitor, and debug blocks.
7x4 AHB MAX
7x4 AHB MAX
Data Path
7x4 AHB Cross-Bar Switch
AIPSTZ-1
AHB to IP Bridge
Data Path
AHB to IP Bridge (TrustZone)
ASRC
Asynchronous
Sample Rate
Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC) converts
the sampling rate of a signal associated to an input clock into
a signal associated to a different output clock.The ASRC
supports concurrent sample rate conversion of up to 10
channels. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling
rates.The ASRC supports up to 3 sampling rate pairs.
AUDMUX
Digital Audio Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice,
audio, and synchronous data routing between host serial
interfaces (for example, SSI1, SSI2, and SSI3) and
peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports with identical functionality and
programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
AIPSTZ-2
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Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
CAMP-1
Block Name
Subsystem
Brief Description
Clock Amplifier
Clocks, Resets,
and Power Control
Clock Amplifier
Clock Control
Module, General
Power Controller,
System Reset
Controller, State
Retention Power
Gate Control
Clocks, Resets,
and Power Control
These blocks are responsible for clock and reset distribution
in the system, and also for the system power management.
The blocks include four PLLs.
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface (SSI),
with data rate up to 26/52Mbit/s (CSPI/ECSPI). It is
configurable to support Master/Slave modes, four chip
selects to support multiple peripherals.
CSU
Central Security
Unit
Security
The Central Security Unit (CSU) is responsible for setting
comprehensive security policy within the i.MX53 platform and
for sharing security information between the various security
blocks. The Security Control Registers (SCR) of the CSU are
set during boot time by the HAB and are locked to prevent
further writing.
DPLLC-1
Digital PhaseLocked Loop
Controller
System Control
Peripherals
This chapter describes DPLLC. The chapter is intended for a
block driver software developer. It describes block-level
operation and programming.
Dynamic Voltage
and Frequency
Scaling for Core
and Peripherals
System Control
Peripherals
The DVFS/DVFSP allows simple dynamic voltage frequency
scaling. The frequency of the clock and the voltage of the
power domain can be changed on the fly while all blocks
continue their normal operation.
EIM
External Interface
Module
System Control
Peripherals
The EIM handles the interface to devices external to the chip,
including generation of chip selects, clock and control for
external peripherals and memory. It provides asynchronous
access to devices with SRAM-like interface and synchronous
access to devices with Nor-Flash like or PSRAM like
interface.
EPIT-1
Enhanced Periodic Timer Peripherals
Interrupt Timer
CAMP-2
CCM
GPC
SRC
SRPGC
CSPI
ECSPI-1
ECSPI-2
DPLLC-2
DPLLC-3
DPLLC-4
DVFSC
DVFSP
EPIT-2
Each EPIT is a 32-bit "set and forget" timer that starts
counting after the EPIT is enabled by software. It is capable
of providing precise interrupts at regular intervals with
minimal processor intervention. It has a 12-bit prescaler for
division of input clock frequency to get the required time
setting for the interrupts to occur, and counter value can be
programmed on the fly.
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Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
ESAI
Block Name
Enhanced Serial
Audio Interface
Subsystem
Connectivity
Peripherals
Brief Description
The Enhanced Serial Audio Interface (ESAI) provides a fullduplex serial port for serial communication with a variety of
serial devices, including industry-standard codecs, SPDIF
transceivers, and other processors.
The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator. All serial
transfers are synchronized to a clock. Additional
synchronization signals are used to delineate the word
frames. The normal mode of operation is used to transfer
data at a periodic rate, one word per period. The network
mode is also intended for periodic transfers; however, it
supports up to 32 words (time slots) per period. This mode
can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for
non-periodic transfers of data and to transfer data serially at
high speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection to
external devices.
ESDCTL
Enhanced SDRAM Memory Control
Controller
The ESDCTL is a configurable high performance and
optimized SDRAM controller that supports DDR2, DDR3, and
so on.
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Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
ESDHCV2-1
ESDHCV2-2
ESDHCV2-4
Block Name
Subsystem
Enhanced MultiConnectivity
Media Card /
Periphera
Secure Digital Host
Controller
Brief Description
i.MX53 specific SoC characteristics:
• Ports 1, 2, and 4 are Compatible with the "MMC
System Specification" version 4.3, full support.
• In i.MX53 SoC, ports 1 and 2 are limited to 4-bit data
width interface.
The generic features of the eSDHC block (ESDHCv2), when
serving as SD/MMC host, include the following:
• Conforms to "SD Host Controller Standard
Specification" version 2.0, full support.
• Compatible with the SD Memory Card Specification
version 1.1
• Compatible with the SDIO Card Specification version
1.2
• Designed to work with SD Memory, miniSD Memory,
SDIO, miniSDIO, SD Combo, MMC and MMC RS
cards
• Configurable to work in one of the following modes:
- SD/SDIO 1-bit, 4-bit
- MMC 1-bit, 4-bit, 8-bit (possibly restricted per SoC
integration)
• Full/High speed mode
• Host clock frequency variable between 32kHz to 52
MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using
4 parallel data lines
• Up to 416 Mbps data transfer for MMC cards using 8
parallel data lines for MMC 4.3, and 832Mbps for
eMMC 4.4 cards.
• eSDHC-2 is limited to bus width of 4-bits, so not
recommended for HD use. See separate section below.
• Can be configured either as SD/MMC controller
• Support eSD and eMMC standard, for SD/MMC
embedded type cards
ESDHCV3-3
(EMMC 4.4)
Ultra-High-Speed
eMMC/SD host
controller.
Connectivity
Peripherals
Ultra High-Speed eSDHC, enhanced to support eMMC 4.4
standard specification, for 832 MBps. Block is backward
compatible to eSDHCv2. See complete features listing in
eSDHCv2 entry below.
i.MX53 SoC specific characteristics:
• Port 3 - enhanced, to support eMMC 4.4 specification,
for double data rate (832Mbps, 8-bit port).
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Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
EXTMC
Block Name
External Memory
Controller
Subsystem
Connectivity
Peripherals
Brief Description
The EXTMC is an external and internal memory interface. It
performs arbitration between multi-AXI masters to multimemory controllers, divided into four major channels, fast
memories (DDR2/DDR3/LPDDR2) channel, slow memories
(NOR-FLASH / PSRAM / NAND-FLASH etc.) channel,
Internal Memory (RAM, ROM) channel and Graphical
Memory (GMEM) channel.
In order to increase the bandwidth performance, the EXTMC
separates the buffering and the arbitration between different
channels, preventing interference between slow and fast
accesses.
EXTMC Features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel,
including dynamic master priority, and taking into
account which pages are open or closed and what type
(Read or Write) was the last access
• Flexible bank interleaving
• Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2
• Support up to 2 GByte DDR memories
• Support NFC, EIM signal muxing scheme
• Support 8/16/32-bit Nor-Flash/PSRAM memories (sync
and async operating modes), at slow frequency, (8bit is
not supported on D[23]-D[16])
• Support 4/8/14/16-bit ECC, page sizes of 512B, 2KB
and 4KB Nand-Flash (including MLC)
• Multiple chip selects (up to 4)
• Enhanced DDR memory controller, supporting access
latency hiding
• Support Watermark for security (Internal and External
memories)
FEC
Fast Ethernet
Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is designed to
support both 10 and 100 Mbps Ethernet/IEEE 802.3
networks. An external transceiver interface and transceiver
function are required to complete the interface to the media.
The i.MX53 also consists of HW assist for IEEE1588
standard. Refer to IEEE1588 section for more details.
FIRI
Fast Infra-Red
Interface
Connectivity
Peripherals
Fast Infra-Red Interface
FLEXCAN-1
Flexible Controller
Area Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed to be
used as a vehicle serial data bus, meeting the specific
requirements of this field: real-time processing, reliable
operation in the EXTMC environment of a vehicle, costeffectiveness and required bandwidth. The FLEXCAN is a full
implementation of the CAN protocol specification, Version 2.0
B, which supports both standard and extended message
frames.
Electrical Fuse
Array
Security
Electrical Fuse Array (splitted to banks). Enables to setup
Boot Modes, Security Levels, Security Keys and many other
system parameters.
FLEXCAN-2
FUSEBOX
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Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
GPIO-1
Block Name
Subsystem
Brief Description
General Purpose I/ System Control
O
Peripherals
Used for general purpose input/output to external ICs. Each
GPIO block supports 32 bits of I/O. The AP side has four
GPIO blocks supporting up to 128 GPIO functions.
GPT
General Purpose
Timer
Timer Peripherals
Each GPT is a 32-bit "free-running" or "set and forget" mode
timer with programmable prescaler and compare and capture
register. A timer counter value can be captured using an
external event and can be configured to trigger a capture
event on either the leading or trailing edges of an input pulse.
When the timer is configured to operate in "set and forget"
mode, it is capable of providing precise interrupts at regular
intervals with minimal processor intervention. The counter
has output compare logic to provide the status and interrupt
at comparison. This timer can be configured to run either on
an external clock or on an internal clock.
GPU2D
Graphics
Processing
Unit-2D, ver 1
Multimedia
Peripherals
The GPU provides hardware acceleration for 2D graphics
algorithms with sufficient processor power to run desk-top
quality interactive graphics applications on displays up to
HD1080 resolution.
GPU3D
Graphics
Processing Unit,
ver.3
Multimedia
Peripherals
The GPU provides hardware acceleration for 2D and 3D
graphics algorithms with sufficient processor power to run
desk-top quality interactive graphics applications on displays
up to HD1080 resolution. It supports color representation up
to 32 bits per pixel. GPUv3 enables High Performance Mobile
3D and 2D Vector Graphics at rates up to 33 M triangles/sec,
200 Mpixels/sec, 800 MPixels/sec (Z) (as per IP vendor).
I2C-1
I2C Interface
Connectivity
Peripherals
I2C provide serial interface for external devices. Data rates of
up to 400 kbps are supported.
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
I2C-2
I2C-3
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Block List
Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
IIM
IC Identification
Module
Security
The IC Identification Module (IIM) provides an interface for
reading, programming and/or overriding identification and
control information stored in on-chip fuse elements. The
block supports electrically-programmable poly fuses (eFuses) or Laser Fuses (L-fuses). The IIM also provides a set
of volatile software-accessible signals which can be used for
software control of hardware elements, not requiring nonvolatility. The IIM provides the primary user-visible
mechanism for interfacing with on-chip fuse elements.
Among the uses for the fuses are unique chip identifiers,
mask revision numbers, cryptographic keys, JTAG secure
mode, boot characteristics and various control signals
requiring permanent non-volatility. The IIM also provides up
to 28 volatile control signals. The IIM consists of a master
controller, a software fuse value shadow cache, and a set of
registers to hold the values of signals visible outside the
block
IOMUXC
IOMUX Controller
System Control
Peripherals
This block enables flexible IO multiplexing. Each IO pad has
default and several alternate functions. The alternate
functions are software configurable.
IPTP
IEEE1588 HW
Assist to Ethernet
controller (FEC).
Connectivity
Peripherals
The IEEE 1588-2002 standard defines a Precision Time
Protocol (PTP) - which is a time-transfer protocol that
enables synchronization of networks (e.g., Ethernet), to a
high degree of accuracy and precision.
The IEEE1588 hardware assist, is composed of the two IPs TSU (Time Stamp Unit) and CE_RTC (Real Time Clock),
which provides the time stamping protocol's functionality.
(generating / reading) the needed timestamps.
The hardware-assisted implementations deliver more precise
clock synchronization, at significantly lower CPU load, than
pure SW implementation.
IPU
Image Processing
Unit, ver.3M
Multimedia
Peripherals
IPUv3M enables connectivity to displays, relevant processing
and synchronization. It supports two display ports and two
camera ports, through the following interfaces.
• Legacy Parallel Interfaces
• Single/dual channel LVDS display interface
• Analog TV or VGA interfaces
The processing includes
• Image enhancement: color adjustment and gamut
mapping, gamma correction and contrast enhancement
• Video/graphics combining
• Support for display backlight reduction
• Image conversion-resizing, rotation, inversion and color
space conversion
• Hardware de-interlacing support
• Synchronization and control capabilities, allowing
autonomous operation.
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Chapter 1 Introduction
Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
KPP
Block Name
Key Pad Port
Subsystem
Connectivity
Peripherals
Brief Description
KPP Supports 8 x 8 external key pad matrix. KPP features
are:
•
•
•
•
LDB
LVDS Display
Bridge
Connectivity
Peripherals
Open drain design
Glitch suppression circuit design
Multiple keys detection
Standby key press detection
LVDS Display Bridge is used to connect the IPU (Image
Processing Unit) to External LVDS Display Interface. LDB
supports two channels; each channel has following signals:
• 1 clock pair
• 4 data pairs
Each signal pair contains - LVDS special differential pad
(PadP, PadM).
LDO
Low-Dropout
Regulator
Clocks, Resets
and Power Control
LDO is an integrated 1.8 V/1.2 V linear regulator.
M4IF
Multi Master Multi
Memory Interface
Memory Control
M4IF controls memory accesses from one or more masters
through different port interfaces to different external memory
controllers ESDCTL, NFC, and EIM, and to some 2 internal
memories in the system as well.
MLB
Media Local Bus
Controller
Connectivity /
Multimedia
Peripherals
The MLB interface block provides a link to a MOST® data
network, using the standardized MediaLB protocol (up to 50
Mbps)
NFC
NAND Flash
Controller
Memory Control
NFC is composed of various control logic units, a 4.5-Kbyte
internal RAM and an internal ECC engine. The NFC can
interface standard NAND Flash memory devices.
OCRAM
On-Chip Memory
controller
Data Path
The On-Chip Memory controller (OCRAM) block, is designed
as an interface between the system's AXI bus, to the internal
(on-chip) SRAM memory block.
In i.MX53, the OCRAM is used for controlling the 128KB
multimedia RAM, via a 64-bit AXI bus.
OWIRE
One-Wire Interface Connectivity
Peripherals
OWIRE support provided for interfacing with an on board
EEPROM, and smart battery interfaces, for example: Dallas
DS2502
PATA
Parallel ATA
Connectivity
Peripherals
The P-ATA block is a AT attachment host interface. Its main
use is to interface with hard disc drives and optical disc
drives. It interfaces with the ATA-6 compliant device over a
number of ATA signals. It is possible to connect a bus buffer
between the host side and the device side.
PFD
Power Fail
Detector
Clocks, Resets,
and Power Control
PFD circuit generates a reset signal till its supply vdd reaches
a predetermined voltage level.The PFD circuit works only
when the chip is in the Non-DSM mode
PLARB2
PL301 Arbiter
Data Path
PLARB1
(2x2) and (4x1)
ARM (Ltd.) PL301 AXI arbiters to bridge between several AXI
masters accessing several AXI slaves.
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Block List
Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
POR
Power on Reset
Clocks, Resets,
and Power Control
The POR is designed for use in SoC applications which
require low voltage, low power consumption. POR circuit
generates a reset signal till its supply VDD reaches a
predetermined voltage level.
PWM-1
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is
optimized to generate sound from stored sample audio
images and it can also generate tones. It uses 16-bit
resolution and a 4x16 data FIFO to generate sound.
ROMC
ROM Controller
with Patch
Data Path
ROM Controller with ROM Patch support
RTIC
Run Time Integrity
Checker
Security
Protecting read only data from modification is one of the
basic elements in trusted platforms. The Run-Time Integrity
Checker (RTIC), is a data monitoring device responsible for
ensuring that memory content is not corrupted during
program execution. The RTICv3 mechanism periodically
checks the integrity of code or data sections during normal
OS run-time execution without interfering with normal
operation. The purpose of the RTIC is to ensure the integrity
of the peripheral memory contents, protect against
unauthorized external memory elements replacement and
assist with boot authentication.
SAHARA
SAHARA security
accelerator
Security
SAHARA (Symmetric/Asymmetric Hashing and Random
Accelerator) version 4 is a security coprocessor. It
implements symmetric encryption algorithms, (AES, DES,
3DES, RC4 and C2), hashing algorithms (MD5, SHA-1,
SHA-224 and SHA-256), and a hardware true random
number generator. It has a slave IPBus interface for the host
to write configuration and command information, and to read
status information. It also has a DMA controller, with an AHB
bus interface, to reduce the burden on the host to move the
required data to and from memory.
SATA
Serial ATA
Connectivity
Peripherals
The SATA controller and PHY is a complete mixed-signal
block solution designed to implement SATA HDD connectivity
in a i.MX53 design.
SCC
Security Controller
Security
The SCC-AES is the second generation of the Security
Controller. It implements secure RAM that can be used either
as general-purpose memory for storing data and software, or
as special confidentiality-preserving memory that protects
disclosure-sensitive data such as cryptographic keys,
passwords, code, or PIN numbers. It also incorporates
cryptographic logic and a DMA engine that can be used to
safely export the data stored within a partition to external
RAM or non-volatile memory
PWM-2
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Chapter 1 Introduction
Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
SDMA
Block Name
Subsystem
Smart Direct
Memory Access
System Control
Peripherals
Brief Description
The SDMA is multi-channel flexible DMA engine. It helps in
maximizing system performance by off-loading the various
cores in dynamic data routing.
Features List:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
• 48 events with total flexibility to trigger any combination
of channels
• Memory accesses including linear, FIFO, and 2D
addressing
• Shared peripherals betweenARM Cortex A8™ and
SDMA
• Very fast Context-Switching with 2-level priority based
preemptive multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
• DMA ports can handle unidirectional and bidirectional
flows (copy mode)
• Up to 8-word buffer for configurable burst transfers for
EXTMC
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
System JTAG
Interface
System Control
Peripherals
JTAG manipulation is one of the known hackers' ways of
executing unauthorized program code, getting control over
secure applications and running code in privileged modes.
The JTAG port provides a debug access to several hardware
blocks including the ARM processor and the system bus.
The JTAG port must be accessible during platform initial
laboratory bring-up, manufacturing tests and troubleshooting,
as well as for software debugging by authorized entities.
However, in order to properly secure the system,
unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access
for manufacturing tests and software debugging, i.MX53
incorporates a mechanism for regulating JTAG access.
i.MX53 System JTAG Controller provides four different JTAG
security modes that can be selected via e-fuse configuration.
SPBA
Shared Peripheral
Bus Arbiter
System Control
Peripherals
SPBA (Shared Peripheral Bus Arbiter) is a three-to-one IP
Bus interfaces (IP Bus) arbiter.
SPDIF
Sony Phillips
Digital Interface
Multimedia
Peripherals
A standard audio file transfer format. Developed jointly by the
Sony and Phillips corporations. Transmitter and Receiver
functionality.
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Block List
Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SRTC
Secure Real Time
Clock
Security
The SRTC incorporates a special System State Retention
Register (SSRR) that stores system parameters during
system shut down modes. This register (as all SRTC
counters) is power backed up by a coin-cell backup battery.
This register is helpful for storing warm boot parameters. The
SSRR also stores the system security state. In case of a
security violation, the SSRR will mark the event (security
violation indication).
SSI-1
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface which is used
on the AP to provide connectivity with off-chip audio
peripherals. The SSI supports a wide variety of protocols
(SSI normal, SSI network, I2S, and AC-97), bit depths (up to
24 bits per word), and clock / frame sync options.
SSI-2
SSI-3
The SSI has two pairs of 8x24 FIFOs and hardware support
for an external DMA controller in order to minimize its impact
on system performance. The second pair of FIFOs provides
hardware interleaving of a second audio stream which
reduces CPU overhead in use cases where two time slots
are being used simultaneously.
TVE
TV-Encoder Ver
2.1
TZIC
TrustZone Aware
ARM/Control
Interrupt Controller
The TrustZone Interrupt Controller (TZIC) collects interrupt
requests from all i.MX53 sources and routes them to the
ARM core. Each interrupt can be configured as a normal or a
secure interrupt. Software Force Registers and software
Priority Masking are also supported.
UART-1
UART Interface
Each of the UART supports the following serial data transmit/
receive protocols and configurations:
UART-2
UART-3
UART-4
UART-5
Multimedia
Connectivity
Peripherals
The TVEv2.1 which consists of the Digital Video Encoder
(DVE) and a Triple Video Digital-to-Analog Converter
(TVDAC); supports HD720p/1080p, PAL/NTSC or VGA
output for direct connection to TV or LCD projector
• 7 or 8 bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 4 MHz. This is a higher
max baud rate relative to the 1.875 MHz which is
stated by the TIA/EIA-232-F standard and the i.MX53
UART.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE or DTE.
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Chapter 1 Introduction
Table 1-1. Digital and Analog Blocks (continued)
Block Mnemonic
USB
Block Name
USB 2.0 High
Speed OTG and
3x HS Hosts
Subsystem
Connectivity
Peripherals
Brief Description
USBO HS (2.0 480MHz) contains one hi-speed OTG block,
which is internally connected to the HS USB PHY, while still
equipped with Transceiver-Less Logic to enable on-board
USB connectivity without USB TransceiversUSBOH3
contains:
• One high-speed OTG block with integrated HS USB
PHY
• One high-speed Host block with integrated HS USB
PHY
• Two identical high-speed Host blocks
All the USB ports are equipped with standard digital
interfaces (ULPI, HS IC-USB) and Transceiver-Less Logic to
enable on-board USB connectivity without USB Transceivers.
VPU
Video Processing
Unit
Multimedia
Peripherals
A high-performing video processing unit (VPU), which covers
many SD-level and HD-level video decoders and SD-level
encoders as a multi-standard video codec engine as well as
several important video processing such as rotation and
mirroring.
Refer to Table 9-2 for complete list of VPU's decoding/
encoding capabilities.
WDOG-1
Watch Dog
XTALOSC
Crystal Oscillator I/ Clocking
F
The XTALOSC is 24 MHz crystal oscillator and
XTALOSC_32K is a 32.768 kHz crystal oscillator.
Internal RAM
Internal RAM, shared with VPU
XTALOSC_32K
RAM
Timer Peripherals
Internal Memory
The Watch Dog Timer supports 2 comparison points during
each counting period. Each of the comparison points is
configurable to evoke an interrupt to the ARM core, and a
second point evokes an external event on the WDOG line.
128 KB
RAM
16 KB
ROM
Secure/non-secure Secured Internal
RAM
Memory
Secure/non-secure Internal RAM, controlled by SCC
Boot ROM
Supports secure and regular Boot Modes
Internal Memory
64 KB
1.7 Memory Interfaces
i.MX53 EXTMC supports the following memory interfaces:
• DDR2/LV-DDR2-800, 16/32 -bit, 400 MHz clock
• DDR3-800, 16/32 -bit, 400 MHz clock
• LPDDR2, 32bit on PoP package only, 400 MHz clock
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Memory Interfaces
• NAND (MLC/SLC) Flash, 8-bit/16-bit
• NOR Flash, SRAM and PSRAM, 8/16/32-bit (8-bit is not supported at byte D[23]D[16])
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Chapter 2
Memory Map
2.1 ARM Platform System Memory Map
The table below shows the system memory map.
Table 2-1. System Memory Map
ARM Platform
Start Address
Size (bytes)
Region
End Address
On Chip Memories [HW connection via External Memory Interface (EXTMC) ]
0000_0000
0000_FFFF
64K
Boot ROM
0001_0000
00FF_FFFF
16M-64K
Boot ROM Aliasing
0100_0000
06FF_FFFF
96M
Reserved
0700_0000
0700_3FFF
16K
Security Controller RAM
0700_4000
07FF_FFFF
16M-16K
SCC RAM Aliasing
0800_0000
0FFF_BFFF
128M
Reserved
0FFF_C000
0FFF_FFFF
16K
Trust Zone Aware Interrupt Control (TZIC)
1000_0000
1000_3FFF
16K
Serial ATA (SATA)
1000_4000
13FF_FFFF
64M-16K
SATA Aliasing
1400_0000
17FF_FFFF
64M
Reserved
1800_0000
1FFF_FFFF
128M
Image Processing Unit (IPU)
2000_0000
2FFF_FFFF
256M
2D Graphics Processing Unit (GPU2D)
3000_0000
3FFF_FFFF
256M
3D Graphics Processing Unit (GPU3D)
On Chip AHB Accessed IPs-Debug APB
4000_0000
4000_0FFF
4K
Debug ROM
4000_1000
4000_1FFF
4K
ETB
4000_2000
4000_2FFF
4K
ETM
4000_3000
4000_3FFF
4K
TPIU
4000_4000
4000_4FFF
4K
CTI0
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ARM Platform System Memory Map
Table 2-1. System Memory Map (continued)
ARM Platform
Start Address
Size (bytes)
Region
End Address
4000_5000
4000_5FFF
4K
CTI1
4000_6000
4000_6FFF
4K
CTI2
4000_7000
4000_7FFF
4K
CTI3
4000_8000
4000_8FFF
4K
ARM Debug Unit
4000_9000
4FFF_FFFF
256M-36K
Reserved
AIPSTZ-1
AIPSTZ-1- SPBA IPs, Mapped to global block enable 0
5000_0000
5000_3FFF
16K
Reserved
5000_4000
5000_7FFF
16K
ESDHC1
5000_8000
5000_BFFF
16K
ESDHC2
5000_C000
5000_FFFF
16K
UART-3
5001_0000
5001_3FFF
16K
ECSPI-1
5001_4000
5001_7FFF
16K
SSI-2
5001_8000
5001_BFFF
16K
ESAI-1
5001_C000
5001_FFFF
16K
Reserved for Smart Direct Memory
Access (SDMA) internal registers
5002_0000
5002_3FFF
16K
ESDHCV3-3
5002_4000
5002_7FFF
16K
ESDHCV2-4
5002_8000
5002_BFFF
16K
SPDIF
5002_C000
5002_FFFF
16K
Asynchronous Sample Rate Converter
(ASRC)
5003_0000
5003_3FFF
16K
Parallel ATA (PATA) (PORT UDMA)
5003_4000
5003_7FFF
16K
Reserved
5003_8000
5003_BFFF
16K
Reserved
5003_C000
5003_FFFF
16K
SPBA
AIPSTZ-1- Global Module Enables
5004_0000
51FF_FFFF
32M (minus 256K)
Reserved AIPSTZ-1 off platform global
module enable #0
5200_0000
53EF_FFFF
31M
Reserved AIPSTZ-1 off platform global
module enable #1
53F7_FFFF
512K
Reserved AIPSTZ-1 on platform slots
53F8_0000
53F8_3FFF
16K
USB 2.0 High Speed OTG and 3x HS
Hosts (USB) (PORT USB)
53F8_4000
53F8_7FFF
16K
GPIO-1
AIPSTZ-1- On Platform
53F0_0000
AIPSTZ-1- Off Platform
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Chapter 2 Memory Map
Table 2-1. System Memory Map (continued)
ARM Platform
Start Address
Size (bytes)
Region
End Address
53F8_8000
53F8_BFFF
16K
GPIO-2
53F8_C000
53F8_FFFF
16K
GPIO-3
53F9_0000
53F9_3FFF
16K
GPIO-4
53F9_4000
53F9_7FFF
16K
Key Pad Port (KPP)
53F9_8000
53F9_BFFF
16K
WDOG1
53F9_C000
53F9_FFFF
16K
WDOG2
53FA_0000
53FA_3FFF
16K
General Purpose Timer (GPT)
53FA_4000
53FA_7FFF
16K
Secure Real Time Clock (SRTC)
53FA_8000
53FA_BFFF
16K
IOMUX Control (IOMUXC)
53FA_C000
53FA_FFFF
16K
EPIT-1
53FB_0000
53FB_3FFF
16K
EPIT-2
53FB_4000
53FB_7FFF
16K
PWM-1
53FB_8000
53FB_BFFF
16K
PWM-2
53FB_C000
53FB_FFFF
16K
UART-1
53FC_0000
53FC_3FFF
16K
UART-2
53FC_4000
53FC_7FFF
16K
USB (PORT PL301)
53FC_8000
53FC_BFFF
16K
FLEXCAN-1
53FC_C000
53FC_FFFF
16K
FLEXCAN-2
53FD_0000
53FD_3FFF
16K
System Reset Controller (SRC)
53FD_4000
53FD_7FFF
16K
Clock Control Module (CCM)
53FD_8000
53FD_BFFF
16K
Global Power Controller (GPC)
53FD_C000
53FD_FFFF
16K
GPIO-5
53FE_0000
53FE_3FFF
16K
GPIO-6
53FE_4000
53FE_7FFF
16K
GPIO-7
53FE_8000
53FE_BFFF
16K
PATA (PORT PIO)
53FE_C000
53FE_FFFF
16K
I2C-3
53FF_0000
53FF_3FFF
16K
UART-4
53FF_4000
53FF_FFFF
48K
Reserved AIPSTZ-1 off platform space.
5400_0000
5FFF_FFFF
448M
Reserved (Aliased to AIPSTZ-1 slots)
AIPSTZ-2- Global Module Enables
6000_0000
61FF_FFFF
32M
Reserved AIPSTZ-1 off platform global
module enable #0
6200_0000
63EF_FFFF
31M
Reserved AIPSTZ-1 off platform global
module enable #1
AIPSTZ-2- On Platform
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ARM Platform System Memory Map
Table 2-1. System Memory Map (continued)
ARM Platform
Start Address
63F0_0000
Size (bytes)
Region
End Address
63F7_FFFF
512K
Reserved AIPSTZ-2 on platform slots
63F8_0000
63F8_3FFF
16K
DPLLC-1
63F8_4000
63F8_7FFF
16K
DPLLC-2
63F8_8000
63F8_BFFF
16K
DPLLC-3
63F8_C000
63F8_FFFF
16K
DPLLC-4
63F9_0000
63F9_3FFF
16K
UART-5
63F9_4000
63F9_7FFF
16K
AHBMAX
63F9_8000
63F9_BFFF
16K
IC Identification Module (IIM)
63F9_C000
63F9_FFFF
16K
Central Security Unit (CSU)
63FA_0000
63FA_3FFF
16K
ARM Platform
63FA_4000
63FA_7FFF
16K
One-Wire Interface (OWIRE)
63FA_8000
63FA_BFFF
16K
Fast Infrared Interface (FIRI)
63FA_C000
63FA_FFFF
16K
ECSPI-2
63FB_0000
63FB_3FFF
16K
SDMA (port IPS_HOST)
63FB_4000
63FB_7FFF
16K
SCC
63FB_8000
63FB_BFFF
16K
ROM Controller with Patch (ROMC)
63FB_C000
63FB_FFFF
16K
Real Time Integrity Checker, ver.2 (RTIC)
63FC_0000
63FC_3FFF
16K
Configurable SPI (CSPI)
63FC_4000
63FC_7FFF
16K
I2C-2
63FC_8000
63FC_BFFF
16K
I2C-1
63FC_C000
63FC_FFFF
16K
SSI-1
63FD_0000
63FD_3FFF
16K
Digital Audio Multiplexer (AUDMUX)
63FD_4000
63FD_7FFF
16K
RTC
63FD_8000
63FD_BFFF
16K
EXTMC (mapped block's register base
address)
AIPSTZ-2- Off Platform
0x63FD_8000 - M4IF
0x63FD_9000 - ESDCTL
0x63FD_A000 - EIM
0x63FD_B000 - NFC
0x63FD_BF00 - EXTMC
63FD_C000
63FD_FFFF
16K
apb2ip_pl301_2x2
63FE_0000
63FE_3FFF
16K
apb2ip_pl301_4x1
63FE_4000
63FE_7FFF
16K
MLB
63FE_8000
63FE_BFFF
16K
SSI-3
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Chapter 2 Memory Map
Table 2-1. System Memory Map (continued)
ARM Platform
Start Address
Size (bytes)
Region
End Address
63FE_C000
63FE_FFFF
16K
Fast Ethernet Controller (FEC)
63FF_0000
63FF_3FFF
16K
TV-Encoder Ver 2.1 (TVE)
63FF_4000
63FF_7FFF
16K
Video Processing Unit (VPU)
63FF_8000
63FF_BFFF
16K
SAHARA
63FF_C000
63FF_FFFF
16K
PTP
6400_0000
6FFF_BFFF
256M (minus 512K)
Reserved (aliased slots)
16K
Reserved
On Chip AHB Accessed IPs
6FFF_C000
6FFF_FFFF
Off Chip Memories (HW connection via EXTMC)
7000_0000
AFFF_FFFF
1G
CSD0 DDR
B000_0000
EFFF_FFFF
1G
CSD1 DDR
F000_0000
F7FE_FFFF
128M-64K
F000_0000
F3FF_FFFF
64M
CS0 (128M NOR/SRAM) - Default
Configuration
F400_0000
F7FE_FFFF
64M-64k
CS1, CS2, CS3 - Not Active.
In case of 2 active CS.
CS0(64M)
CS1(64M)
Via IOMUXC (GPRR1) register, 4CS of
32M are supported. The sum of all CS
spaces must equal 128M, and can be
splitted between maximum 4 CSs. The
biggest region is CS0. No holes are
supported.
The supported configurations are:
CS0(128M), CS1 (0M), CS2 (0M),
CS3(0M)
CS0(64M), CS1(64M), CS2(0M), CS3(0M)
CS0(64M), CS1(32M), CS2(32M),
CS3(0M)
CS0(32M), CS1(32M), CS2(32M),
CS3(32M)
On Chip Memories (HW connection via EXTMC)
F7FF_0000
F7FF_FFFF
64K
NAND FLASH (internal buffer)
F800_0000
F801_FFFF
128K
iRAM (OCRAM)
F802_0000
F805_FFFF
256K
GPU3D GMEM
F806_0000
FFFF_FFFF
128M-384K
Reserved
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DMA Memory Map
NOTE
User should not address reserved memory regions. Access to
reserved memory regions can cause unpredictable behavior.
2.2 DMA Memory Map
The Smart DMA memory map is defined in Table 2-2.
Table 2-2. SDMA Peripheral Memory Map
Peripheral
Base Address
Size
Comments
Reserved for SDMA internal
memory
0x0000
4KB
Reserved
ESDHCv2-1
0x1000
4KB
ESDHCv2-2
0x2000
4KB
UART-3
0x3000
4KB
ECSPI-1
0x4000
4KB
SSI-2
0x5000
4KB
Enhanced Serial Audio Interface
(ESAI)
0x6000
4KB
Reserved for SDMA internal
registers
0x7000
4KB
ESDHCv2-3 (CE-ATA)
0x8000
4KB
ESDHCv2-4
0x9000
4KB
SPDIF
0xA000
4KB
ASRC
0xB000
4KB
PATA
0xC000
4KB
Reserved
0xD000
4KB
Reserved
Reserved
0xE000
4KB
Reserved
SPBA Registers
0xF000
4KB
Reserved
NOTE
User should not address reserved memory regions. Access to
reserved memory regions can cause unpredictable behavior.
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Chapter 3
Interrupts and SDMA Events
3.1 Overview
The Interrupts and SDMA Events chapter provides information on the assignments of the
interrupts of the ARM platform domain in ARM Platform Interrupts and of the DMA
events in SDMA Event Mapping.
3.2 ARM Platform Interrupts
The TrustZone Aware Interrupt Controller (TZIC) collects up to 128 interrupt requests
from all MCIMX53 sources and provides an interface to the core. Each interrupt can be
configured as a normal or a secure interrupt. Software force registers and software
priority masking are also supported. Table 3-1 details the ARM Cortex A8tm Platform
(ARM) interrupt sources.
Table 3-1. ARM Domain Interrupt Summary
IRQ
Interrupt
Interrupt Description
Source
0
Reserved
Reserved
1
ESDHCV2-1
Enhanced SDHC Interrupt Request
2
ESDHCV2-2
Enhanced SDHC Interrupt Request
3
ESDHCV3-3
CE-ATA Interrupt Request based on ESDHCV3-3
4
ESDHCV2-4
Enhanced SDHC Interrupt Request
5
DAP
6
SDMA
AND of all 48 interrupts from all the channels
7
IOMUXC
POWER FAIL interrupt. This is a power fail indicator
interrupt from on board power management IC via
GPIO_16 PAD on ALT2, PWRFAIL_INT signal.
Table continues on the next page...
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ARM Platform Interrupts
Table 3-1. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Interrupt Description
Source
8
EXTMC
NFC interrupt
9
VPU
VPU Interrupt Request
10
IPU
IPU Error Interrupt
11
IPU
IPU Sync Interrupt
12
GPU3D
GPU Interrupt Request
13
UART-4
UART-4 ORed interrupt
14
USB
USB Host 1
15
EXTMC
Consolidated EXTMC Interrupt
16
USB
USB Host 2
17
USB
USB Host 3
18
USB
USB OTG
19
SAHARA
SAHARA Interrupt for Host 0
20
SAHARA
SAHARA Intr for Host 1
21
SCC
Security Monitor High Priority Interrupt Request.
22
SCC
Secure (TrustZone) Interrupt Request.
23
SCC
Regular (Non-Secure) Interrupt Request.
24
SRTC
SRTC Consolidated Interrupt. Non TZ.
25
SRTC
SRTC Security Interrupt. TZ.
26
RTIC
RTIC (Trust Zone) Interrupt Request. Indicates that
the RTIC has completed hashing the selected
memory block(s) during single-hash/boot mode.
27
CSU
CSU Interrupt Request 1. Indicates to the processor
that one or more alarm inputs were asserted
28
SATA
SATA interrupt request
29
SSI-1
SSI-1 Interrupt Request
30
SSI-2
SSI-2 Interrupt Request
31
UART-1
UART-1 ORed interrupt
32
UART-2
UART-2 ORed interrupt
33
UART-3
UART-3 ORed interrupt
34
IPTP
RTC (IEEE1588) interrupt request
35
IPTP
PTP (IEEE1588) interrupt request
36
ECSPI-1
ECSPI-1 interrupt request line to the core.
37
ECSPI-2
ECSPI-2 interrupt request line to the core.
38
CSPI
CSPI interrupt request line to the core.
Table continues on the next page...
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Chapter 3 Interrupts and SDMA Events
Table 3-1. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Interrupt Description
Source
39
GPT
OR of GPT Rollover interrupt line, Input Capture 1 &
2 lines, Output Compare 1, 2 &3 Interrupt lines
40
EPIT-1
EPIT-1 output compare interrupt
41
EPIT-2
EPIT-2 output compare interrupt
42
GPIO-1
Active HIGH Interrupt from INT7 from GPIO
43
GPIO-1
Active HIGH Interrupt from INT6 from GPIO
44
GPIO-1
Active HIGH Interrupt from INT5 from GPIO
45
GPIO-1
Active HIGH Interrupt from INT4 from GPIO
46
GPIO-1
Active HIGH Interrupt from INT3 from GPIO
47
GPIO-1
Active HIGH Interrupt from INT2 from GPIO
48
GPIO-1
Active HIGH Interrupt from INT1 from GPIO
49
GPIO-1
Active HIGH Interrupt from INT0 from GPIO
50
GPIO-1
Combined interrupt indication for GPIO-1 signal 0
throughout 15
51
GPIO-1
Combined interrupt indication for GPIO-1 signal 16
throughout 31
52
GPIO-2
Combined interrupt indication for GPIO-2 signal 0
throughout 15
53
GPIO-2
Combined interrupt indication for GPIO-2 signal 16
throughout 31
54
GPIO-3
Combined interrupt indication for GPIO-3 signal 0
throughout 15
55
GPIO-3
Combined interrupt indication for GPIO-3 signal 16
throughout 31
56
GPIO-4
Combined interrupt indication for GPIO-4 signal 0
throughout 15
57
GPIO-4
Combined interrupt indication for GPIO-4 signal 16
throughout 31
58
WDOG-1
Watchdog Timer reset
59
WDOG-2
TrustZone Watchdog Timer reset
60
KPP
Keypad Interrupt
61
PWM-1
Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line.
62
I2C-1
I2C-1 Interrupt
63
I2C-2
I2C-2 Interrupt
64
I2C-3
I2C-3 Interrupt
65
MLB
NOR of all interrupts, mlb_cint and mlb_sint
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ARM Platform Interrupts
Table 3-1. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Interrupt Description
Source
66
ASRC
ASRC Interrupt for core 1
67
SPDIF
SPDIF Tx interrupt OR SPDIF Rx interrupt
68
Reserved
Reserved
69
IIM
Interrupt request to the processor. Indicates to the
processor that program or explicit sense cycle is
completed successfully or in case of error. This
signal is low-asserted.
70
PATA
Parallel ATA host controller interrupt request
71
CCM
CCM, Interrupt Request 1
72
CCM
CCM, Interrupt Request 2
73
GPC
GPC, Interrupt Request 1
74
GPC
GPC, Interrupt Request 2
75
SRC
SRC interrupt request
76
P_PLATFORM_NE_32K_256K
Neon Monitor Interrupt
77
P_PLATFORM_NE_32K_256K
Performance Unit Interrupt (nPMUIRQ). This is an
interrupt generated by the ARMCORE and used for
system profiling and debug. GPIO_16 PAD in ALT3
mode acts as nPMUIRQ signal (also named
PMU_IRQ_B signal).
78
P_PLATFORM_NE_32K_256K
CTI IRQ
79
P_PLATFORM_NE_32K_256K
Debug Interrupt, from Cross-Trigger 1 Interface 1
80
P_PLATFORM_NE_32K_256K
Debug Interrupt, from Cross-Trigger 1 Interface 0
81
ESAI
ESAI interrupt
82
FLEXCAN-1
NOR of all interrupts; ipi_int_mbor, ipi_int_wakein,
ipi_int_busoff and ipi_int_error.
83
FLEXCAN-2
NOR of all interrupts; ipi_int_mbor, ipi_int_wakein,
ipi_int_busoff and ipi_int_error.
84
OPENVG
General Interrupt
85
OPENVG
Busy signal (for S/W power gating feasibility)
86
UART-5
UART-5 ORed interrupt
87
FEC
Fast Interrupt Request (OR of 13 interrupt sources)
88
OWIRE
1-Wire Interrupt Request
89
P_PLATFORM_NE_32K_256K
Debug Interrupt, from Cross-Trigger 1 Interface 2
90
SJC
91
Reserved
92
TVE
93
FIRI
Reserved
FIRI Intr (OR of all 4 interrupt sources)
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Chapter 3 Interrupts and SDMA Events
Table 3-1. ARM Domain Interrupt Summary (continued)
IRQ
Interrupt
Interrupt Description
Source
94
PWM-2
Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line.
95
Reserved
Reserved for SLM
96
SSI-3
SSI-3 Interrupt Request
97
Reserved
98
P_PLATFORM_NE_32K_256K
Debug Interrupt, from Cross-Trigger 1 Interface 3
99
Reserved
Was belong to SLM
100
VPU
Idle interrupt from VPU (for S/W power gating)
101
EXTMC
Indicates all pages have been transferred to NFC
during an auto_prog operation
102
GPU3D
Idle interrupt from GPU (for S/W power gating)
103
GPIO-5
Combined interrupt indication for GPIO-5 signal 0
throughout 15
104
GPIO-5
Combined interrupt indication for GPIO-5 signal 16
throughout 31
105
GPIO-6
Combined interrupt indication for GPIO-6 signal 0
throughout 15
106
GPIO-6
Combined interrupt indication for GPIO-6 signal 16
throughout 31
107
GPIO-7
Combined interrupt indication for GPIO-7 signal 0
throughout 15
108
GPIO-7
Combined interrupt indication for GPIO-7 signal 16
throughout 31
109_128
Reserved
Reserved
3.3 SDMA Event Mapping
Table 3-2 shows the DMA request signals for peripherals in i.MX53.
Table 3-2. SDMA Event Mapping
Event
Number
DMA Source
Description
0
VPU
VPU DMA request
1
GPC
Will be used for power management.
2
UART-4 PATA
UART-4RX muxed with PATA RX (selector IOMUXC GPR0 register bit
[7]).
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SDMA Event Mapping
Table 3-2. SDMA Event Mapping (continued)
Event
Number
DMA Source
Description
3
UART-4 PATA
UART-4TX muxed with PATA TX (selector IOMUXC GPR0 register bit
[8]).
4
PATA
PATA Transfer End
5
IPU
IPU DMA Event
6
ECSPI
DMA Rx request
7
ECSPI-1
DMA Tx request
8
ECSPI-2
DMA Rx request
9
ECSPI-2
DMA Tx request
10
I2C-3 ESDHCV3-3
I2C-3 muxed with ESDHCV3-3
11
ESDHCV2-4 CTI2
ESDHC4 muxed with CTI2 (SDMA_CTI) trigger_out[0] connected to
SDMA event.
12
UART-2 FIRI
UART-2RX muxed with FIRI REQ[0] (selector IOMUXC GPR0 register bit
[9]).
13
UART-2 FIRI
UART-2TX muxed with FIRI REQ[1] (selector IOMUXC GPR0 register bit
[10]).
14
SPDIF IOMUXC
SPDIF RX DMA request Muxed with External DMA request #0 from PAD
DISP0_DAT16 or GPIO_17 (using daisy chain selector). The event
selector is in IOMUXC GPR0 register bit [4].
15
SPDIF
SPDIF TX DMA request
16
UART-5
Rx FIFO of UART-5
17
UART-5
Tx FIFO of UART-5
18
UART-1
Rx FIFO of UART-1
19
UART-1
Tx FIFO of UART-1
20
I2C-1 ESDHCV2-1
I2C-1 muxed with ESDHCV2-1
21
I2C-2 ESDHCV2-2
I2C-2 muxed with ESDHCV2-2
22
SSI-2
SSI-2 receive 2 DMA request
23
SSI-2
SSI-2 transmit 2 DMA request
24
SSI-2
SSI-2 receive 1 DMA request
25
SSI-2
SSI-2 transmit 1 DMA request
26
SSI-1
SSI-1 receive 2 DMA request
27
SSI-1
SSI-1 transmit 2 DMA request
28
SSI-1
SSI-1 receive 1 DMA request
29
SSI-1
SSI-1 transmit 1 DMA request
30
EXTMC
Asserts every time NFC finishes reading a page
31
EXTMC
Asserts at the beginning of auto-program sequence, and every time the
NFC finishes transferring data from the RAM to the NAND (Meaning, the
SDMA can write to the RAM the next page).
Table continues on the next page...
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Chapter 3 Interrupts and SDMA Events
Table 3-2. SDMA Event Mapping (continued)
Event
Number
DMA Source
Description
32
ASRC
ASRC dma1 request (Pair A input Request)
33
ASRC
ASRC dma2 request (Pair B input Request)
34
ASRC
ASRC dma3 request (Pair C input Request)
35
ASRC
ASRC dma4 request (Pair A output Request)
36
ASRC
ASRC dma5 request (Pair B output Request)
37
ASRC
ASRC dma6 request (Pair C output Request)
38
CSPI EPIT-2
CSPI DMA Rx request Muxed with EPIT-2 DMA request
39
CSPI IOMUXC
CSPI DMA Tx request Muxed with External DMA request #1 from PAD
DISP0_DAT17 or GPIO_18 (using daisy chain selector). The event
selector is in IOMUXC GPR0 register bit [6].
40
ESAI
ESAI Rx FIFO DMA request
41
ESAI
ESAI Tx FIFO DMA request
42
UART-3
Rx FIFO of UART-3
43
UART-3
Tx FIFO of UART-3
44
SSI-3
SSI-3 receive 2 DMA request
45
SSI-3
SSI-3 transmit 2 DMA request
46
SSI-3
SSI-3 receive 1 DMA request
47
SSI-3
SSI-3 transmit 1 DMA request
As shown in the table, some of the events are shared through a multiplexer. The select of
shared DMA event sources is controlled by DMAREQ_MUX_SELn fields of the
IOMUXC.IOMUXC_GPRO Register.
For other shared connectivity peripherals that do not have dedicated DMA request
signals, the ARM platform interrupt service routines have the option to program the
SDMA to move data between the peripheral and memory.
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Chapter 4
External Signals and Pin Multiplexing
4.1 Overview
Internal signals are connected to external components via package-level electrical
connections. In this document, these physical connections will be referred to as pins even
though in specific products they may be implemented as solder balls or some other
package specific means. Pins, in turn, are connected internally to SoC driver / receiver
circuitry called pads.
The i.MX53 contains a number of functional blocks that present input / output signals
(block I/Os) that are suitable for connection to components external to the SoC. There are
many more block I/Os than there are package pins. To provide flexibility in routing block
I/Os to external pins, the Input-Output Multiplexer Controller (IOMUXC) block provides
a number of software configurable multiplexers that allow different internal block I/O
signals to be routed to the available pins.
In addition to this function, IOMUXC allows software to configure pad electrical
characteristics, such as output/output function, voltage level, drive strength, and
hysteresis. Not all voltage and ground pins are considered here. For information on these
pins, consult the appropriate data sheet for the specific product.
4.2 Controlling Pin Multiplexing
Some block I/Os are routed to dedicated package pins, but the majority of block I/O
signals are routed through the IOMUXC. This allows internal blocks to share pins to
drive or receive signals. Block I/Os are selected for routing to and from external package
pins via the MUX_MODE field in the MUX_CTL registers. These selections are called
ALT modes.
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Some block input signals can be driven from alternate pins. This function is called a daisy
chain. SELECT_INPUT registers allow software to chose between two to six different
pins to provide input signals to some blocks.
Drive strength and direction (input or output) of many package pins may be selected by
fields within PAD_CTL registers. Some pins have dedicated PAD_CTL_PAD registers.
Most pins that are used in their default mode to interface to external DRAM are
configured for drive strength and direction by PAD_CTL_GRP register although some
have PAD_CTL_PAD registers as well.
Multiplexing and Pad Control below lists those registers used to control package pin
drive characteristics and pin to internal block I/O connections.
Daisy Chain Control below lists registers involved in controlling daisy chaining.
See the IOMUXC chapter for more details.
4.2.1 Multiplexing and Pad Control
This section covers the multiplexing and pad control regitsters.
Table 4-1 shows the multiplexing control register and pad driver control register(s) for
each package pin.
Table 4-1. Pin Control Registers
Pin Name
Mux Control
Pad / Group Control
GPIO_19
IOMUXC_SW_MUX_CTL_PAD_GPIO_19
IOMUXC_SW_PAD_CTL_PAD_GPIO_19
KEY_COL0
IOMUXC_SW_MUX_CTL_PAD_KEY_COL0
IOMUXC_SW_PAD_CTL_PAD_KEY_COL0
KEY_
ROW0
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0
KEY_COL1
IOMUXC_SW_MUX_CTL_PAD_KEY_COL1
IOMUXC_SW_PAD_CTL_PAD_KEY_COL1
KEY_
ROW1
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1
KEY_COL2
IOMUXC_SW_MUX_CTL_PAD_KEY_COL2
IOMUXC_SW_PAD_CTL_PAD_KEY_COL2
KEY_
ROW2
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2
KEY_COL3
IOMUXC_SW_MUX_CTL_PAD_KEY_COL3
IOMUXC_SW_PAD_CTL_PAD_KEY_COL3
KEY_
ROW3
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3
KEY_COL4
IOMUXC_SW_MUX_CTL_PAD_KEY_COL4
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4
KEY_
ROW4
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
NVCC_
KEYPAD
Pad / Group Control
IOMUXC_SW_PAD_CTL_PAD_NVCC_KEYPAD
DI0_DISP_
CLK
IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK
IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK
DI0_PIN15
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15
DI0_PIN2
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN2
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN2
DI0_PIN3
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN3
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN3
DI0_PIN4
IOMUXC_SW_MUX_CTL_PAD_DI0_PIN4
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN4
DISP0_
DAT0
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT0
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT0
DISP0_
DAT1
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT1
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT1
DISP0_
DAT2
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT2
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT2
DISP0_
DAT3
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT3
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT3
DISP0_
DAT4
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT4
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT4
DISP0_
DAT5
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT5
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT5
DISP0_
DAT6
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT6
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT6
DISP0_
DAT7
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT7
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT7
DISP0_
DAT8
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT8
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT8
DISP0_
DAT9
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT9
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT9
DISP0_
DAT10
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT10
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT10
DISP0_
DAT11
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT11
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT11
DISP0_
DAT12
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT12
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT12
DISP0_
DAT13
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT13
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT13
DISP0_
DAT14
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT14
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT14
DISP0_
DAT15
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT15
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT15
DISP0_
DAT16
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT16
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT16
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Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
DISP0_
DAT17
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT17
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT17
DISP0_
DAT18
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT18
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT18
DISP0_
DAT19
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT19
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19
DISP0_
DAT20
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT20
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT20
DISP0_
DAT21
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT21
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT21
DISP0_
DAT22
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT22
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT22
DISP0_
DAT23
IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT23
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT23
CSI0_
PIXCLK
IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK
IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK
CSI0_
MCLK
IOMUXC_SW_MUX_CTL_PAD_CSI0_MCLK
IOMUXC_SW_PAD_CTL_PAD_CSI0_MCLK
CSI0_
DATA_EN
IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN
IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN
CSI0_
VSYNC
IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC
IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC
CSI0_DAT4 IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT4
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT4
CSI0_DAT5 IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT5
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT5
CSI0_DAT6 IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT6
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT6
CSI0_DAT7 IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT7
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT7
CSI0_DAT8 IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT8
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT8
CSI0_DAT9 IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT9
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT9
CSI0_
DAT10
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT10
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT10
CSI0_
DAT11
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT11
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT11
CSI0_
DAT12
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT12
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT12
CSI0_
DAT13
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT13
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT13
CSI0_
DAT14
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT14
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT14
CSI0_
DAT15
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT15
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT15
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
CSI0_
DAT16
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT16
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT16
CSI0_
DAT17
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT17
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT17
CSI0_
DAT18
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT18
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT18
CSI0_
DAT19
IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT19
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT19
NVCC_
CSI__0
IOMUXC_SW_PAD_CTL_PAD_NVCC_CSI__0
JTAG_TMS
IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS
JTAG_MOD
IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD
JTAG_
TRSTB
IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB
JTAG_TDI
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI
JTAG_TCK
IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK
JTAG_TDO
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO
EIM_A25
IOMUXC_SW_MUX_CTL_PAD_EIM_A25
IOMUXC_SW_PAD_CTL_PAD_EIM_A25
EIM_EB2
IOMUXC_SW_MUX_CTL_PAD_EIM_EB2
IOMUXC_SW_PAD_CTL_PAD_EIM_EB2
EIM_D16
IOMUXC_SW_MUX_CTL_PAD_EIM_D16
IOMUXC_SW_PAD_CTL_PAD_EIM_D16
EIM_D17
IOMUXC_SW_MUX_CTL_PAD_EIM_D17
IOMUXC_SW_PAD_CTL_PAD_EIM_D17
EIM_D18
IOMUXC_SW_MUX_CTL_PAD_EIM_D18
IOMUXC_SW_PAD_CTL_PAD_EIM_D18
EIM_D19
IOMUXC_SW_MUX_CTL_PAD_EIM_D19
IOMUXC_SW_PAD_CTL_PAD_EIM_D19
EIM_D20
IOMUXC_SW_MUX_CTL_PAD_EIM_D20
IOMUXC_SW_PAD_CTL_PAD_EIM_D20
EIM_D21
IOMUXC_SW_MUX_CTL_PAD_EIM_D21
IOMUXC_SW_PAD_CTL_PAD_EIM_D21
EIM_D22
IOMUXC_SW_MUX_CTL_PAD_EIM_D22
IOMUXC_SW_PAD_CTL_PAD_EIM_D22
EIM_D23
IOMUXC_SW_MUX_CTL_PAD_EIM_D23
IOMUXC_SW_PAD_CTL_PAD_EIM_D23
EIM_EB3
IOMUXC_SW_MUX_CTL_PAD_EIM_EB3
IOMUXC_SW_PAD_CTL_PAD_EIM_EB3
EIM_D24
IOMUXC_SW_MUX_CTL_PAD_EIM_D24
IOMUXC_SW_PAD_CTL_PAD_EIM_D24
EIM_D25
IOMUXC_SW_MUX_CTL_PAD_EIM_D25
IOMUXC_SW_PAD_CTL_PAD_EIM_D25
EIM_D26
IOMUXC_SW_MUX_CTL_PAD_EIM_D26
IOMUXC_SW_PAD_CTL_PAD_EIM_D26
EIM_D27
IOMUXC_SW_MUX_CTL_PAD_EIM_D27
IOMUXC_SW_PAD_CTL_PAD_EIM_D27
EIM_D28
IOMUXC_SW_MUX_CTL_PAD_EIM_D28
IOMUXC_SW_PAD_CTL_PAD_EIM_D28
EIM_D29
IOMUXC_SW_MUX_CTL_PAD_EIM_D29
IOMUXC_SW_PAD_CTL_PAD_EIM_D29
EIM_D30
IOMUXC_SW_MUX_CTL_PAD_EIM_D30
IOMUXC_SW_PAD_CTL_PAD_EIM_D30
NVCC_
EIM__0
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
EIM_D31
Mux Control
IOMUXC_SW_MUX_CTL_PAD_EIM_D31
NVCC_
EIM__1
Pad / Group Control
IOMUXC_SW_PAD_CTL_PAD_EIM_D31
IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__1
EIM_A24
IOMUXC_SW_MUX_CTL_PAD_EIM_A24
IOMUXC_SW_PAD_CTL_PAD_EIM_A24
EIM_A23
IOMUXC_SW_MUX_CTL_PAD_EIM_A23
IOMUXC_SW_PAD_CTL_PAD_EIM_A23
EIM_A22
IOMUXC_SW_MUX_CTL_PAD_EIM_A22
IOMUXC_SW_PAD_CTL_PAD_EIM_A22
EIM_A21
IOMUXC_SW_MUX_CTL_PAD_EIM_A21
IOMUXC_SW_PAD_CTL_PAD_EIM_A21
EIM_A20
IOMUXC_SW_MUX_CTL_PAD_EIM_A20
IOMUXC_SW_PAD_CTL_PAD_EIM_A20
EIM_A19
IOMUXC_SW_MUX_CTL_PAD_EIM_A19
IOMUXC_SW_PAD_CTL_PAD_EIM_A19
EIM_A18
IOMUXC_SW_MUX_CTL_PAD_EIM_A18
IOMUXC_SW_PAD_CTL_PAD_EIM_A18
EIM_A17
IOMUXC_SW_MUX_CTL_PAD_EIM_A17
IOMUXC_SW_PAD_CTL_PAD_EIM_A17
EIM_A16
IOMUXC_SW_MUX_CTL_PAD_EIM_A16
IOMUXC_SW_PAD_CTL_PAD_EIM_A16
EIM_CS0
IOMUXC_SW_MUX_CTL_PAD_EIM_CS0
IOMUXC_SW_PAD_CTL_PAD_EIM_CS0
EIM_CS1
IOMUXC_SW_MUX_CTL_PAD_EIM_CS1
IOMUXC_SW_PAD_CTL_PAD_EIM_CS1
EIM_OE
IOMUXC_SW_MUX_CTL_PAD_EIM_OE
IOMUXC_SW_PAD_CTL_PAD_EIM_OE
EIM_RW
IOMUXC_SW_MUX_CTL_PAD_EIM_RW
IOMUXC_SW_PAD_CTL_PAD_EIM_RW
EIM_LBA
IOMUXC_SW_MUX_CTL_PAD_EIM_LBA
IOMUXC_SW_PAD_CTL_PAD_EIM_LBA
NVCC_
EIM__4
IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__4
EIM_EB0
IOMUXC_SW_MUX_CTL_PAD_EIM_EB0
IOMUXC_SW_PAD_CTL_PAD_EIM_EB0
EIM_EB1
IOMUXC_SW_MUX_CTL_PAD_EIM_EB1
IOMUXC_SW_PAD_CTL_PAD_EIM_EB1
EIM_DA0
IOMUXC_SW_MUX_CTL_PAD_EIM_DA0
IOMUXC_SW_PAD_CTL_PAD_EIM_DA0
EIM_DA1
IOMUXC_SW_MUX_CTL_PAD_EIM_DA1
IOMUXC_SW_PAD_CTL_PAD_EIM_DA1
EIM_DA2
IOMUXC_SW_MUX_CTL_PAD_EIM_DA2
IOMUXC_SW_PAD_CTL_PAD_EIM_DA2
EIM_DA3
IOMUXC_SW_MUX_CTL_PAD_EIM_DA3
IOMUXC_SW_PAD_CTL_PAD_EIM_DA3
EIM_DA4
IOMUXC_SW_MUX_CTL_PAD_EIM_DA4
IOMUXC_SW_PAD_CTL_PAD_EIM_DA4
EIM_DA5
IOMUXC_SW_MUX_CTL_PAD_EIM_DA5
IOMUXC_SW_PAD_CTL_PAD_EIM_DA5
EIM_DA6
IOMUXC_SW_MUX_CTL_PAD_EIM_DA6
IOMUXC_SW_PAD_CTL_PAD_EIM_DA6
EIM_DA7
IOMUXC_SW_MUX_CTL_PAD_EIM_DA7
IOMUXC_SW_PAD_CTL_PAD_EIM_DA7
EIM_DA8
IOMUXC_SW_MUX_CTL_PAD_EIM_DA8
IOMUXC_SW_PAD_CTL_PAD_EIM_DA8
EIM_DA9
IOMUXC_SW_MUX_CTL_PAD_EIM_DA9
IOMUXC_SW_PAD_CTL_PAD_EIM_DA9
EIM_DA10
IOMUXC_SW_MUX_CTL_PAD_EIM_DA10
IOMUXC_SW_PAD_CTL_PAD_EIM_DA10
EIM_DA11
IOMUXC_SW_MUX_CTL_PAD_EIM_DA11
IOMUXC_SW_PAD_CTL_PAD_EIM_DA11
EIM_DA12
IOMUXC_SW_MUX_CTL_PAD_EIM_DA12
IOMUXC_SW_PAD_CTL_PAD_EIM_DA12
EIM_DA13
IOMUXC_SW_MUX_CTL_PAD_EIM_DA13
IOMUXC_SW_PAD_CTL_PAD_EIM_DA13
EIM_DA14
IOMUXC_SW_MUX_CTL_PAD_EIM_DA14
IOMUXC_SW_PAD_CTL_PAD_EIM_DA14
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
EIM_DA15
IOMUXC_SW_MUX_CTL_PAD_EIM_DA15
IOMUXC_SW_PAD_CTL_PAD_EIM_DA15
NANDF_
WE_B
IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B
IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B
NANDF_
RE_B
IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B
IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B
EIM_WAIT
IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT
IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT
EIM_BCLK
IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK
NVCC_
EIM__7
IOMUXC_SW_PAD_CTL_PAD_NVCC_EIM__7
LVDS1_
TX3_P
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX3_P
LVDS1_
TX3_N
LVDS1_
TX2_P
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX2_P
LVDS1_
TX2_N
LVDS1_
CLK_P
IOMUXC_SW_MUX_CTL_PAD_LVDS1_CLK_P
LVDS1_
CLK_N
LVDS1_
TX1_P
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX1_P
LVDS1_
TX1_N
LVDS1_
TX0_P
IOMUXC_SW_MUX_CTL_PAD_LVDS1_TX0_P
LVDS1_
TX0_N
LVDS0_
TX3_P
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX3_P
LVDS0_
TX3_N
LVDS0_
CLK_P
IOMUXC_SW_MUX_CTL_PAD_LVDS0_CLK_P
LVDS0_
CLK_N
LVDS0_
TX2_P
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX2_P
LVDS0_
TX2_N
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
LVDS0_
TX1_P
Mux Control
Pad / Group Control
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX1_P
LVDS0_
TX1_N
LVDS0_
TX0_P
IOMUXC_SW_MUX_CTL_PAD_LVDS0_TX0_P
LVDS0_
TX0_N
GPIO_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_10
GPIO_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_11
GPIO_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_12
GPIO_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_13
GPIO_14
IOMUXC_SW_PAD_CTL_PAD_GPIO_14
DRAM_D24
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_D30
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_D26
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_
DQM3
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
DRAM_D28
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_D25
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_
SDQS3_B
DRAM_
SDQS3
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
DRAM_D27
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_D31
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
DRAM_D16
Mux Control
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_D29
IOMUXC_SW_PAD_CTL_GRP_B3DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3
DRAM_D18
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_
SDCKE1
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1
DRAM_D22
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_
DQM2
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
DRAM_D20
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_
SDBA0
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_D17
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_
SDODT1
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_D19
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_
SDQS2_B
DRAM_
SDQS2
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
DRAM_D21
Mux Control
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_CS1
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_D23
IOMUXC_SW_PAD_CTL_GRP_B2DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2
DRAM_
RESET
IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DRAM_
SDBA1
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_
SDCLK_1_
B
DRAM_
SDCLK_1
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
DRAM_A8
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
DRAM_
SDBA2
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A14
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A3
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A5
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A7
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A6
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A9
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A2
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A0
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
DRAM_A15
Mux Control
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A13
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A11
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A1
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A12
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_
CAS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DRAM_
SDWE
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_CS0
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_A4
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
DRAM_
SDCLK_0_
B
DRAM_
SDCLK_0
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
DRAM_A10
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_D4
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_D6
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_D2
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_
SDQS0_B
DRAM_
SDQS0
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
DRAM_
SDODT0
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DRAM_
DQM0
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DRAM_
RAS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DRAM_D5
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_D0
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_D7
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_
SDCKE0
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
DRAM_D1
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_D14
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
DRAM_D3
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0
DRAM_D12
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
DRAM_D10
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
Table continues on the next page...
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237
Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
DRAM_D8
Mux Control
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
DRAM_D13
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
DRAM_
SDQS1_B
DRAM_
SDQS1
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
DRAM_
DQM1
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DRAM_D9
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
DRAM_D15
Pad / Group Control
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
DRAM_D11
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1
CKIH1
CKIH2
PMIC_ON_
REQ
IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ
PMIC_
STBY_REQ
IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ
NANDF_
CLE
IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE
IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE
NANDF_
ALE
IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE
IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE
NANDF_
WP_B
IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B
IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B
NANDF_
RB0
IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0
IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0
NANDF_
CS0
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0
NANDF_
CS1
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1
NANDF_
CS2
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2
NANDF_
CS3
IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3
NVCC_
NANDF
FEC_MDIO
IOMUXC_SW_PAD_CTL_PAD_NVCC_NANDF
IOMUXC_SW_MUX_CTL_PAD_FEC_MDIO
IOMUXC_SW_PAD_CTL_PAD_FEC_MDIO
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
FEC_REF_
CLK
IOMUXC_SW_MUX_CTL_PAD_FEC_REF_CLK
IOMUXC_SW_PAD_CTL_PAD_FEC_REF_CLK
FEC_RX_
ER
IOMUXC_SW_MUX_CTL_PAD_FEC_RX_ER
IOMUXC_SW_PAD_CTL_PAD_FEC_RX_ER
FEC_CRS_ IOMUXC_SW_MUX_CTL_PAD_FEC_CRS_DV
DV
IOMUXC_SW_PAD_CTL_PAD_FEC_CRS_DV
FEC_RXD1 IOMUXC_SW_MUX_CTL_PAD_FEC_RXD1
IOMUXC_SW_PAD_CTL_PAD_FEC_RXD1
FEC_RXD0 IOMUXC_SW_MUX_CTL_PAD_FEC_RXD0
IOMUXC_SW_PAD_CTL_PAD_FEC_RXD0
FEC_TX_
EN
IOMUXC_SW_MUX_CTL_PAD_FEC_TX_EN
IOMUXC_SW_PAD_CTL_PAD_FEC_TX_EN
FEC_TXD1
IOMUXC_SW_MUX_CTL_PAD_FEC_TXD1
IOMUXC_SW_PAD_CTL_PAD_FEC_TXD1
FEC_TXD0
IOMUXC_SW_MUX_CTL_PAD_FEC_TXD0
IOMUXC_SW_PAD_CTL_PAD_FEC_TXD0
FEC_MDC
IOMUXC_SW_MUX_CTL_PAD_FEC_MDC
IOMUXC_SW_PAD_CTL_PAD_FEC_MDC
NVCC_FEC
IOMUXC_SW_PAD_CTL_PAD_NVCC_FEC
PATA_
DIOW
IOMUXC_SW_MUX_CTL_PAD_PATA_DIOW
IOMUXC_SW_PAD_CTL_PAD_PATA_DIOW
PATA_
DMACK
IOMUXC_SW_MUX_CTL_PAD_PATA_DMACK
IOMUXC_SW_PAD_CTL_PAD_PATA_DMACK
PATA_
DMARQ
IOMUXC_SW_MUX_CTL_PAD_PATA_DMARQ
IOMUXC_SW_PAD_CTL_PAD_PATA_DMARQ
PATA_
BUFFER_
EN
IOMUXC_SW_MUX_CTL_PAD_PATA_BUFFER_EN
IOMUXC_SW_PAD_CTL_PAD_PATA_BUFFER_EN
PATA_
INTRQ
IOMUXC_SW_MUX_CTL_PAD_PATA_INTRQ
IOMUXC_SW_PAD_CTL_PAD_PATA_INTRQ
PATA_
DIOR
IOMUXC_SW_MUX_CTL_PAD_PATA_DIOR
IOMUXC_SW_PAD_CTL_PAD_PATA_DIOR
PATA_
RESET_B
IOMUXC_SW_MUX_CTL_PAD_PATA_RESET_B
IOMUXC_SW_PAD_CTL_PAD_PATA_RESET_B
PATA_
IORDY
IOMUXC_SW_MUX_CTL_PAD_PATA_IORDY
IOMUXC_SW_PAD_CTL_PAD_PATA_IORDY
PATA_DA_
0
IOMUXC_SW_MUX_CTL_PAD_PATA_DA_0
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_0
PATA_DA_
1
IOMUXC_SW_MUX_CTL_PAD_PATA_DA_1
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_1
PATA_DA_
2
IOMUXC_SW_MUX_CTL_PAD_PATA_DA_2
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_2
PATA_CS_
0
IOMUXC_SW_MUX_CTL_PAD_PATA_CS_0
IOMUXC_SW_PAD_CTL_PAD_PATA_CS_0
PATA_CS_
1
IOMUXC_SW_MUX_CTL_PAD_PATA_CS_1
IOMUXC_SW_PAD_CTL_PAD_PATA_CS_1
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
NVCC_
PATA__2
Pad / Group Control
IOMUXC_SW_PAD_CTL_PAD_NVCC_PATA__2
PATA_
DATA0
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA0
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA0
PATA_
DATA1
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA1
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA1
PATA_
DATA2
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA2
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA2
PATA_
DATA3
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA3
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA3
PATA_
DATA4
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA4
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA4
PATA_
DATA5
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA5
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA5
PATA_
DATA6
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA6
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA6
PATA_
DATA7
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA7
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA7
PATA_
DATA8
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA8
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA8
PATA_
DATA9
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA9
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA9
PATA_
DATA10
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA10
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA10
PATA_
DATA11
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA11
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA11
PATA_
DATA12
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA12
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA12
PATA_
DATA13
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA13
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA13
PATA_
DATA14
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA14
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA14
PATA_
DATA15
IOMUXC_SW_MUX_CTL_PAD_PATA_DATA15
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA15
NVCC_
PATA__0
IOMUXC_SW_PAD_CTL_PAD_NVCC_PATA__0
SD1_
DATA0
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0
SD1_
DATA1
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1
SD1_CMD
IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
IOMUXC_SW_PAD_CTL_PAD_SD1_CMD
SD1_
DATA2
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2
Table continues on the next page...
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Table 4-1. Pin Control Registers (continued)
Pin Name
Mux Control
Pad / Group Control
SD1_CLK
IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK
SD1_
DATA3
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3
NVCC_SD1
IOMUXC_SW_PAD_CTL_PAD_NVCC_SD1
SD2_CLK
IOMUXC_SW_MUX_CTL_PAD_SD2_CLK
IOMUXC_SW_PAD_CTL_PAD_SD2_CLK
SD2_CMD
IOMUXC_SW_MUX_CTL_PAD_SD2_CMD
IOMUXC_SW_PAD_CTL_PAD_SD2_CMD
SD2_
DATA3
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3
SD2_
DATA2
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2
SD2_
DATA1
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1
SD2_
DATA0
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0
NVCC_SD2
IOMUXC_SW_PAD_CTL_PAD_NVCC_SD2
GPIO_0
IOMUXC_SW_MUX_CTL_PAD_GPIO_0
IOMUXC_SW_PAD_CTL_PAD_GPIO_0
GPIO_1
IOMUXC_SW_MUX_CTL_PAD_GPIO_1
IOMUXC_SW_PAD_CTL_PAD_GPIO_1
GPIO_9
IOMUXC_SW_MUX_CTL_PAD_GPIO_9
IOMUXC_SW_PAD_CTL_PAD_GPIO_9
GPIO_3
IOMUXC_SW_MUX_CTL_PAD_GPIO_3
IOMUXC_SW_PAD_CTL_PAD_GPIO_3
GPIO_6
IOMUXC_SW_MUX_CTL_PAD_GPIO_6
IOMUXC_SW_PAD_CTL_PAD_GPIO_6
GPIO_2
IOMUXC_SW_MUX_CTL_PAD_GPIO_2
IOMUXC_SW_PAD_CTL_PAD_GPIO_2
GPIO_4
IOMUXC_SW_MUX_CTL_PAD_GPIO_4
IOMUXC_SW_PAD_CTL_PAD_GPIO_4
GPIO_5
IOMUXC_SW_MUX_CTL_PAD_GPIO_5
IOMUXC_SW_PAD_CTL_PAD_GPIO_5
GPIO_7
IOMUXC_SW_MUX_CTL_PAD_GPIO_7
IOMUXC_SW_PAD_CTL_PAD_GPIO_7
GPIO_8
IOMUXC_SW_MUX_CTL_PAD_GPIO_8
IOMUXC_SW_PAD_CTL_PAD_GPIO_8
GPIO_16
IOMUXC_SW_MUX_CTL_PAD_GPIO_16
IOMUXC_SW_PAD_CTL_PAD_GPIO_16
GPIO_17
IOMUXC_SW_MUX_CTL_PAD_GPIO_17
IOMUXC_SW_PAD_CTL_PAD_GPIO_17
GPIO_18
IOMUXC_SW_MUX_CTL_PAD_GPIO_18
IOMUXC_SW_PAD_CTL_PAD_GPIO_18
NVCC_
GPIO
IOMUXC_SW_PAD_CTL_PAD_NVCC_GPIO
POR_B
IOMUXC_SW_PAD_CTL_PAD_POR_B
BOOT_
MODE1
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1
RESET_IN_
B
IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B
BOOT_
MODE0
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0
TEST_
MODE
IOMUXC_SW_PAD_CTL_PAD_TEST_MODE
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2 lists package pin multiplexing options by package pin.
Table 4-2. Pin Alternate Modes
Package
Pin Name
GPIO_19
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
KPP
COL[5]
IOMUXC_SW_PAD_CTL_PAD_GPIO_19
ALT1
GPIO-4
GPIO[5]
Drive Strength (DSE) = High
ALT2
CCM
CLKO
Low/high output voltage (HVE) = N/A
ALT3
SPDIF
OUT1
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_EXT_TRIG2
Pull / Keep Select (PUE) = Pull
ALT5
ECSPI-1
RDY
ALT6
FEC
TDATA[3]
ALT7
SRC
INT_BOOT
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
KEY_
COL0
ALT0
KPP
COL[0]
IOMUXC_SW_PAD_CTL_PAD_KEY_COL0
ALT1
GPIO-4
GPIO[6]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD5_TXC
Low/high output voltage (HVE) = N/A
ALT3
ARM
Platform
CTI_TRIGIN7
Hysteresis Enable (HYS) = Enabled
ALT4
UART-4
TXD_MUX
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
ECSPI-1
SCLK
DSE_TEST = Regular
ALT6
FEC
RDATA[3]
Open Drain Enable (ODE) = Disabled
ALT7
SRC
ANY_PU_RST
Pull / Keep Enable (PKE) =Enabled
Pull / Keep Select (PUE) = Pull
TEST_TS = Disabled
KEY_
ROW0
ALT0
KPP
ROW[0]
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0
ALT1
GPIO-4
GPIO[7]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD5_TXD
Low/high output voltage (HVE) = N/A
ALT3
ARM
Platform
CTI_TRIGIN_ACK7
Hysteresis Enable (HYS) = Enabled
ALT4
UART-4
RXD_MUX
Pull Up / Down (PUS) = 360K Ohm Pull Down
ALT5
ESCPI-1
MOSI
DSE_TEST = Regular
ALT6
FEC
TX_ER
Open Drain Enable (ODE) = Disabled
Pull / Keep Select (PUE) = Pull
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
KEY_
COL1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
KPP
COL[1]
IOMUXC_SW_PAD_CTL_PAD_KEY_COL1
ALT1
GPIO-4
GPIO[8]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD5_TXFS
Low/high output voltage (HVE) = N/A
ALT3
ARM
Platform
CTI_TRIGOUT_ACK6
Hysteresis Enable (HYS) = Enabled
ALT4
UART-5
TXD_MUX
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
ECSPI-1
MISO
DSE_TEST = Regular
ALT6
FEC
RX_CLK
Open Drain Enable (ODE) = Disabled
ALT7
USBPHY-1
TXREADY
Pull / Keep Enable (PKE) =Enabled
Pull / Keep Select (PUE) = Pull
TEST_TS = Disabled
KEY_
ROW1
ALT0
KPP
ROW[1]
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1
ALT1
GPIO-4
GPIO[9]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD5_RXD
Low/high output voltage (HVE) = N/A
ALT3
ARM
Platform
CTI_TRIGOUT_ACK7
Hysteresis Enable (HYS) = Enabled
ALT4
UART-5
RXD_MUX
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
ECSPI-1
SS0
DSE_TEST = Regular
ALT6
FEC
COL
Open Drain Enable (ODE) = Disabled
ALT7
USBPHY-1
RXVALID
Pull / Keep Enable (PKE) =Enabled
Pull / Keep Select (PUE) = Pull
TEST_TS = Disabled
KEY_
COL2
ALT0
KPP
COL[2]
IOMUXC_SW_PAD_CTL_PAD_KEY_COL2
ALT1
GPIO-4
GPIO[10]
Drive Strength (DSE) = High
ALT2
FLEXCAN-1
TXCAN
Low/high output voltage (HVE) = N/A
ALT3
ARM
Platform
CTI_TRIGOUT6
Hysteresis Enable (HYS) = Enabled
ALT4
FEC
MDIO
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
ECSPI-1
SS1
DSE_TEST = Regular
ALT6
FEC
RDATA[2]
Open Drain Enable (ODE) = Disabled
ALT7
USBPHY-1
RXACTIVE
Pull / Keep Enable (PKE) =Enabled
Pull / Keep Select (PUE) = Pull
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
KEY_
ROW2
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
KPP
ROW[2]
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2
ALT1
GPIO-4
GPIO[11]
Drive Strength (DSE) = High
ALT2
FLEXCAN-1
RXCAN
Low/high output voltage (HVE) = N/A
ALT3
ARM
Platform
CTI_TRIGOUT7
Hysteresis Enable (HYS) = Enabled
ALT4
FEC
MDC
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
ECSPI-1
SS2
DSE_TEST = Regular
ALT6
FEC
TDATA[2]
Open Drain Enable (ODE) = Disabled
ALT7
USBPHY-1
RXERROR
Pull / Keep Enable (PKE) =Enabled
Pull / Keep Select (PUE) = Pull
TEST_TS = Disabled
KEY_
COL3
ALT0
KPP
COL[3]
IOMUXC_SW_PAD_CTL_PAD_KEY_COL3
ALT1
GPIO-4
GPIO[12]
Drive Strength (DSE) = High
ALT2
USB
H2_DP
Low/high output voltage (HVE) = N/A
ALT3
SPDIF
IN1
Hysteresis Enable (HYS) = Enabled
ALT4
I2C-2
SCL
Pull / Keep Select (PUE) = Pull
ALT5
ECSPI-1
SS3
ALT6
FEC
CRS
ALT7
USBPHY-1
SIECLOCK
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
KEY_
ROW3
ALT0
KPP
ROW[3]
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3
ALT1
GPIO-4
GPIO[13]
Drive Strength (DSE) = High
ALT2
USB
H2_DM
Low/high output voltage (HVE) = N/A
ALT3
CCM
ASRC_EXT_CLK
Hysteresis Enable (HYS) = Enabled
ALT4
I2C-2
SDA
Pull / Keep Select (PUE) = Pull
ALT5
XTALOSC32 32K_OUT
K
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
ALT6
CCM
PLL4_BYP
Open Drain Enable (ODE) = Disabled
ALT7
USBPHY-1
LINESTATE[0]
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
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Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
KEY_
COL4
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
KPP
COL[4]
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4
ALT1
GPIO-4
GPIO[14]
Drive Strength (DSE) = High
ALT2
FLEXCAN-2
TXCAN
Low/high output voltage (HVE) = N/A
ALT3
IPU
SISG[4]
Hysteresis Enable (HYS) = Enabled
ALT4
UART-5
RTS
Pull / Keep Select (PUE) = Pull
ALT5
USB
USBOTG_OC
ALT7
USBPHY-1
LINESTATE[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
KEY_
ROW4
ALT0
KPP
ROW[4]
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4
ALT1
GPIO-4
GPIO[15]
Drive Strength (DSE) = High
ALT2
FLEXCAN-2
RXCAN
Low/high output voltage (HVE) = N/A
ALT3
IPU
SISG[5]
Hysteresis Enable (HYS) = Enabled
ALT4
UART-5
CTS
Pull / Keep Select (PUE) = Pull
ALT5
USB
USBOTG_PWR
ALT7
USBPHY-1
VBUSVALID
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DI0_
ALT0
DISP_CLK
ALT1
IPU
DI0_DISP_CLK
IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK
GPIO-4
GPIO[16]
Drive Strength (DSE) = High
ALT2
USB
USBH2_DIR
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_CORE_STATE[0]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[0]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT7
USBPHY-1
AVALID
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
DI0_PIN15 ALT0
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
IPU
DI0_PIN15
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15
ALT1
GPIO-4
GPIO[17]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD6_TXC
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_CORE_STATE[1]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT7
USBPHY-1
BVALID
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DI0_PIN2
ALT0
IPU
DI0_PIN2
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN2
ALT1
GPIO-4
GPIO[18]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD6_TXD
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_CORE_STATE[2]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[2]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT7
USBPHY-1
ENDSESSION
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DI0_PIN3
ALT0
IPU
DI0_PIN3
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN3
ALT1
GPIO-4
GPIO[19]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD6_TXFS
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_CORE_STATE[3]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[3]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT7
USBPHY-1
IDDIG
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DI0_PIN4
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DI0_PIN4
IOMUXC_SW_PAD_CTL_PAD_DI0_PIN4
ALT1
GPIO-4
GPIO[20]
Drive Strength (DSE) = High
ALT2
AUDMUX
AUD6_RXD
Hysteresis Enable (HYS) = Enabled
ALT3
ESDHV2-1
WP
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_YIELD
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[4]
ALT7
USBPHY-1
HOSTDISCONNECT
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT0
ALT0
IPU
DISP0_DAT[0]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT0
ALT1
GPIO-4
GPIO[21]
Drive Strength (DSE) = High
ALT2
CSPI
SCLK
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[0]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_CORE_RUN
Pull Up / Down (PUS) = 100K Ohm Pull Down
ALT6
EXTMC
EMI_DEBUG[5]
ALT7
USBPHY-2
TXREADY
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT1
ALT0
IPU
DISP0_DAT[1]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT1
ALT1
GPIO-4
GPIO[22]
Drive Strength (DSE) = High
ALT2
CSPI
MOSI
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[1]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_EVENT_
CHANNEL_SEL
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[6]
DSE_TEST = Regular
ALT7
USBPHY-2
RXVALID
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT2
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[2]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT2
ALT1
GPIO-4
GPIO[23]
Drive Strength (DSE) = High
ALT2
CSPI
MISO
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[2]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_MODE
Pull Up / Down (PUS) = 100K Ohm Pull Down
ALT6
EXTMC
EMI_DEBUG[7]
ALT7
USBPHY-2
RXACTIVE
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT3
ALT0
IPU
DISP0_DAT[3]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT3
ALT1
GPIO-4
GPIO[24]
Drive Strength (DSE) = High
ALT2
CSPI
SS0
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[3]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_BUS_ERROR
Pull Up / Down (PUS) = 100K Ohm Pull Down
ALT6
EXTMC
EMI_DEBUG[8]
ALT7
USBPHY-2
RXERROR
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT4
ALT0
IPU
DISP0_DAT[4]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT4
ALT1
GPIO-4
GPIO[25]
Drive Strength (DSE) = High
ALT2
CSPI
SS1
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[4]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_BUS_RWB
Pull Up / Down (PUS) = 100K Ohm Pull Down
ALT6
EXTMC
EMI_DEBUG[9]
ALT7
USBPHY-2
SIECLOCK
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT5
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[5]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT5
ALT1
GPIO-4
GPIO[26]
Drive Strength (DSE) = High
ALT2
CSPI
SS2
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[5]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_MATCHED_
DMBUS
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[10]
DSE_TEST = Regular
ALT7
USBPHY-2
LINESTATE[0]
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT6
ALT0
IPU
DISP0_DAT[6]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT6
ALT1
GPIO-4
GPIO[27]
Drive Strength (DSE) = High
ALT2
CSPI
SS3
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[6]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_RTBUFFER_
WRITE
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[11]
DSE_TEST = Regular
ALT7
USBPHY-2
LINESTATE[1]
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT7
ALT0
IPU
DISP0_DAT[7]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT7
ALT1
GPIO-4
GPIO[28]
Drive Strength (DSE) = High
ALT2
CSPI
RDY
Hysteresis Enable (HYS) = Enabled
ALT3
USB
USBH2_DATA[7]
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_EVENT_
CHANNEL[0]
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[12]
DSE_TEST = Regular
ALT7
USBPHY-2
VBUSVALID
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT8
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[8]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT8
ALT1
GPIO-4
GPIO[29]
Drive Strength (DSE) = High
ALT2
PWM-1
PWMO
Hysteresis Enable (HYS) = Enabled
ALT3
WDOG-1
WDOG_B
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_EVENT_
CHANNEL[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[13]
DSE_TEST = Regular
ALT7
USBPHY-2
AVALID
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT9
ALT0
IPU
DISP0_DAT[9]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT9
ALT1
GPIO-4
GPIO[30]
Drive Strength (DSE) = High
ALT2
PWM-2
PWMO
Hysteresis Enable (HYS) = Enabled
ALT3
WDOG-2
WDOG_B
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_EVENT_
CHANNEL[2]
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[14]
DSE_TEST = Regular
ALT7
USBPHY-2
VSTATUS[0]
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT10
ALT0
IPU
DISP0_DAT[10]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT10
ALT1
GPIO-4
GPIO[31]
Drive Strength (DSE) = High
ALT2
USB
USBH2_STP
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_EVENT_
CHANNEL[3]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[15]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT7
USBPHY-2
VSTATUS[1]
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT11
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[11]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT11
ALT1
GPIO-5
GPIO[5]
Drive Strength (DSE) = High
ALT2
USB
USBH2_NXT
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_EVENT_
CHANNEL[4]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
ALT6
EXTMC
EMI_DEBUG[16]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT7
USBPHY-2
VSTATUS[2]
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT12
ALT0
IPU
DISP0_DAT[12]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT12
ALT1
GPIO-5
GPIO[6]
Drive Strength (DSE) = High
ALT2
USB
USBH2_CLK
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_EVENT_
CHANNEL[5]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[17]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT7
USBPHY-2
VSTATUS[3]
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT13
ALT0
IPU
DISP0_DAT[13]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT13
ALT1
GPIO-5
GPIO[7]
Drive Strength (DSE) = High
ALT3
AUDMUX
AUD5_RXFS
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[0]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[18]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT7
USBPHY-2
VSTATUS[4]
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT14
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[14]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT14
ALT1
GPIO-5
GPIO[8]
Drive Strength (DSE) = High
ALT3
AUDMUX
AUD5_RXC
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[1]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[19]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT7
USBPHY-2
VSTATUS[5]
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT15
ALT0
IPU
DISP0_DAT[15]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT15
ALT1
GPIO-5
GPIO[9]
Drive Strength (DSE) = High
ALT2
ECSPI-1
SS1
Hysteresis Enable (HYS) = Enabled
ALT3
ECSPI-2
SS1
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[2]
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[20]
DSE_TEST = Regular
ALT7
USBPHY-2
VSTATUS[6]
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT16
ALT0
IPU
DISP0_DAT[16]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT16
ALT1
GPIO-5
GPIO[10]
Drive Strength (DSE) = High
ALT2
ECSPI-2
MOSI
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD5_TXC
Pull / Keep Select (PUE) = Pull
ALT4
SDMA
SDMA_EXT_EVENT[0]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[3]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
ALT6
EXTMC
EMI_DEBUG[21]
Open Drain Enable (ODE) = Disabled
ALT7
USBPHY-2
VSTATUS[7]
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT17
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[17]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT17
ALT1
GPIO-5
GPIO[11]
Drive Strength (DSE) = High
ALT2
ECSPI-2
MISO
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD5_TXD
Pull / Keep Select (PUE) = Pull
ALT4
SDMA
SDMA_EXT_EVENT[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[4]
ALT6
EXTMC
EMI_DEBUG[22]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT18
ALT0
IPU
DISP0_DAT[18]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT18
ALT1
GPIO-5
GPIO[12]
Drive Strength (DSE) = High
ALT2
ECSPI-2
SS0
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD5_TXFS
Pull / Keep Select (PUE) = Pull
ALT4
AUDMUX
AUD4_RXFS
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[5]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
ALT6
EXTMC
EMI_DEBUG[23]
Open Drain Enable (ODE) = Disabled
ALT7
EXTMC
WEIM_CS[2]
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT19
ALT0
IPU
DISP0_DAT[19]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19
ALT1
GPIO-5
GPIO[13]
Drive Strength (DSE) = High
ALT2
ECSPI-2
SCLK
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD5_RXD
Pull / Keep Select (PUE) = Pull
ALT4
AUDMUX
AUD4_RXC
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[6]
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
ALT6
EXTMC
EMI_DEBUG[24]
Open Drain Enable (ODE) = Disabled
ALT7
EXTMC
WEIM_CS[3]
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT20
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[20]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT20
ALT1
GPIO-5
GPIO[14]
Drive Strength (DSE) = High
ALT2
ECSPI-1
SCLK
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD4_TXC
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_EVT_CHN_
LINES[7]
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
ALT6
EXTMC
EMI_DEBUG[25]
DSE_TEST = Regular
ALT7
SATA_PHY
TDI
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT21
ALT0
IPU
DISP0_DAT[21]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT21
ALT1
GPIO-5
GPIO[15]
Drive Strength (DSE) = High
ALT2
ECSPI-1
MOSI
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD4_TXD
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_BUS_DEVICE[0]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[26]
ALT7
SATA_PHY
TDO
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DISP0_
DAT22
ALT0
IPU
DISP0_DAT[22]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT22
ALT1
GPIO-5
GPIO[16]
Drive Strength (DSE) = High
ALT2
ECSPI-1
MISO
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD4_TXFS
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_BUS_DEVICE[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[27]
ALT7
SATA_PHY
TCK
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DISP0_
DAT23
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
DISP0_DAT[23]
IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT23
ALT1
GPIO-5
GPIO[17]
Drive Strength (DSE) = High
ALT2
ECSPI-1
SS0
Hysteresis Enable (HYS) = Enabled
ALT3
AUDMUX
AUD4_RXD
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_BUS_DEVICE[2]
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT6
EXTMC
EMI_DEBUG[28]
ALT7
SATA_PHY
TMS
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
CSI0_
PIXCLK
ALT0
IPU
CSI0_PIXCLK
IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK
ALT1
GPIO-5
GPIO[18]
Drive Strength (DSE) = High
ALT5
SDMA
DEBUG_PC[0]
Low/high output voltage = N/A
ALT6
EXTMC
EMI_DEBUG[29]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
MCLK
ALT0
IPU
CSI0_HSYNC
IOMUXC_SW_PAD_CTL_PAD_CSI0_MCLK
ALT1
GPIO-5
GPIO[19]
Drive Strength (DSE) = High
ALT2
CCM
CSI0_MCLK
Low/high output voltage = N/A
ALT5
SDMA
DEBUG_PC[1]
Hysteresis Enable (HYS) = Enabled
ALT6
EXTMC
EMI_DEBUG[30]
Pull / Keep Select (PUE) = Pull
ALT7
TPIU
TRCTL
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
CSI0_
DATA_EN
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
CSI0_DATA_EN
IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN
ALT1
GPIO-5
GPIO[20]
Drive Strength (DSE) = High
ALT5
SDMA
DEBUG_PC[2]
Low/high output voltage = N/A
ALT6
EXTMC
EMI_DEBUG[31]
Hysteresis Enable (HYS) = Enabled
ALT7
TPIU
TRCLK
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
VSYNC
ALT0
IPU
CSI0_VSYNC
IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC
ALT1
GPIO-5
GPIO[21]
Drive Strength (DSE) = High
ALT5
SDMA
DEBUG_PC[3]
Low/high output voltage = N/A
ALT6
EXTMC
EMI_DEBUG[32]
Hysteresis Enable (HYS) = Enabled
ALT7
TPIU
TRACE[0]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT4
ALT0
IPU
CSI0_D[4]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT4
ALT1
GPIO-5
GPIO[22]
Drive Strength (DSE) = High
ALT2
KPP
COL[5]
Low/high output voltage = N/A
ALT3
ECSPI-1
SCLK
Hysteresis Enable (HYS) = Enabled
ALT4
USB
USBH3_STP
Pull / Keep Select (PUE) = Pull
ALT5
AUDMUX
AUD3_TXC
ALT6
EXTMC
EMI_DEBUG[33]
ALT7
TPIU
TRACE[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
CSI0_
DAT5
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
CSI0_D[5]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT5
ALT1
GPIO-5
GPIO[23]
Drive Strength (DSE) = High
ALT2
KPP
ROW[5]
Low/high output voltage = N/A
ALT3
ECSPI-1
MOSI
Hysteresis Enable (HYS) = Enabled
ALT4
USB
USBH3_NXT
Pull / Keep Select (PUE) = Pull
ALT5
AUDMUX
AUD3_TXD
ALT6
EXTMC
EMI_DEBUG[34]
ALT7
TPIU
TRACE[2]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT6
ALT0
IPU
CSI0_D[6]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT6
ALT1
GPIO-5
GPIO[24]
Drive Strength (DSE) = High
ALT2
KPP
COL[6]
Low/high output voltage = N/A
ALT3
ECSPI-1
MISO
Hysteresis Enable (HYS) = Enabled
ALT4
USB
USBH3_CLK
Pull / Keep Select (PUE) = Pull
ALT5
AUDMUX
AUD3_TXFS
ALT6
EXTMC
EMI_DEBUG[35]
ALT7
TPIU
TRACE[3]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT7
ALT0
IPU
CSI0_D[7]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT7
ALT1
GPIO-5
GPIO[25]
Drive Strength (DSE) = High
ALT2
KPP
ROW[6]
Low/high output voltage = N/A
ALT3
ECSPI-1
SS0
Hysteresis Enable (HYS) = Enabled
ALT4
USB
USBH3_DIR
Pull / Keep Select (PUE) = Pull
ALT5
AUDMUX
AUD3_RXD
ALT6
EXTMC
EMI_DEBUG[36]
ALT7
TPIU
TRACE[4]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
CSI0_
DAT8
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
CSI0_D[8]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT8
ALT1
GPIO-5
GPIO[26]
Drive Strength (DSE) = High
ALT2
KPP
COL[7]
Low/high output voltage = N/A
ALT3
ECSPI-2
SCLK
Hysteresis Enable (HYS) = Enabled
ALT4
USB
USBH3_OC
Pull / Keep Select (PUE) = Pull
ALT5
I2C-1
SDA
ALT6
EXTMC
EMI_DEBUG[37]
ALT7
TPIU
TRACE[5]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT9
ALT0
IPU
CSI0_D[9]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT9
ALT1
GPIO-5
GPIO[27]
Drive Strength (DSE) = High
ALT2
KPP
ROW[7]
Low/high output voltage = N/A
ALT3
ECSPI-2
MOSI
Hysteresis Enable (HYS) = Enabled
ALT4
USB
USBH3_PWR
Pull / Keep Select (PUE) = Pull
ALT5
I2C-1
SCL
ALT6
EXTMC
EMI_DEBUG[38]
ALT7
TPIU
TRACE[6]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT10
ALT0
IPU
CSI0_D[10]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT10
ALT1
GPIO-5
GPIO[28]
Drive Strength (DSE) = High
ALT2
UART-1
TXD_MUX
Low/high output voltage = N/A
ALT3
ECSPI-2
MISO
Hysteresis Enable (HYS) = Enabled
ALT4
AUDMUX
AUD3_RXC
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_PC[4]
ALT6
EXTMC
EMI_DEBUG[39]
ALT7
TPIU
TRACE[7]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
CSI0_
DAT11
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
CSI0_D[11]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT11
ALT1
GPIO-5
GPIO[29]
Drive Strength (DSE) = High
ALT2
UART-1
RXD_MUX
Low/high output voltage = N/A
ALT3
ECSPI-2
SS0
Hysteresis Enable (HYS) = Enabled
ALT4
AUDMUX
AUD3_RXFS
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_PC[5]
ALT6
EXTMC
EMI_DEBUG[40]
ALT7
TPIU
TRACE[8]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT12
ALT0
IPU
CSI0_D[12]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT12
ALT1
GPIO-5
GPIO[30]
Drive Strength (DSE) = High
ALT2
UART-4
TXD_MUX
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[0]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[6]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[41]
ALT7
TPIU
TRACE[9]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT13
ALT0
IPU
CSI0_D[13]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT13
ALT1
GPIO-5
GPIO[31]
Drive Strength (DSE) = High
ALT2
UART-4
RXD_MUX
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[1]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[7]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[42]
ALT7
TPIU
TRACE[10]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
CSI0_
DAT14
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
CSI0_D[14]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT14
ALT1
GPIO-6
GPIO[0]
Drive Strength (DSE) = High
ALT2
UART-5
TXD_MUX
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[2]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[8]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[43]
ALT7
TPIU
TRACE[11]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT15
ALT0
IPU
CSI0_D[15]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT15
ALT1
GPIO-6
GPIO[1]
Drive Strength (DSE) = High
ALT2
UART-5
RXD_MUX
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[3]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[9]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[44]
ALT7
TPIU
TRACE[12]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT16
ALT0
IPU
CSI0_D[16]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT16
ALT1
GPIO-6
GPIO[2]
Drive Strength (DSE) = High
ALT2
UART-4
RTS
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[4]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[10]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[45]
ALT7
TPIU
TRACE[13]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
CSI0_
DAT17
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
IPU
CSI0_D[17]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT17
ALT1
GPIO-6
GPIO[3]
Drive Strength (DSE) = High
ALT2
UART-4
CTS
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[5]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[11]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[46]
ALT7
TPIU
TRACE[14]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT18
ALT0
IPU
CSI0_D[18]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT18
ALT1
GPIO-6
GPIO[4]
Drive Strength (DSE) = High
ALT2
UART-5
RTS
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[6]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[12]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[47]
ALT7
TPIU
TRACE[15]
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CSI0_
DAT19
ALT0
IPU
CSI0_D[19]
IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT19
ALT1
GPIO-6
GPIO[5]
Drive Strength (DSE) = High
ALT2
UART-5
CTS
Low/high output voltage = N/A
ALT4
USB
USBH3_DATA[7]
Hysteresis Enable (HYS) = Enabled
ALT5
SDMA
DEBUG_PC[13]
Pull / Keep Select (PUE) = Pull
ALT6
EXTMC
EMI_DEBUG[48]
ALT7
USBPHY-2
BISTOK
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
JTAG_
TMS
Mode
-
Instance
SJC
Block I/O
TMS
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 47K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
JTAG_
MOD
-
SJC
MOD
IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
JTAG_
TRSTB
-
SJC
TRSTB
IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 47K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
JTAG_TDI -
Instance
SJC
Block I/O
TDI
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 47K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
JTAG_
TCK
-
SJC
TCK
IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
JTAG_
TDO
-
SJC
TDO
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = N/A
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_A25
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_A[25]
IOMUXC_SW_PAD_CTL_PAD_EIM_A25
ALT1
GPIO-5
GPIO[2]
Drive Strength (DSE) = High
ALT2
ECSPI-2
RDY
Low/high output voltage = N/A
ALT3
IPU
DI1_PIN12
Hysteresis Enable (HYS) = Disabled
ALT4
CSPI
SS1
Pull / Keep Select (PUE) = Pull
ALT6
IPU
DI0_D1_CS
ALT7
USBPHY-1
BISTOK
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_EB2
ALT0
EXTMC
WEIM_EB[2]
IOMUXC_SW_PAD_CTL_PAD_EIM_EB2
ALT1
GPIO-2
GPIO[30]
Drive Strength (DSE) = High
ALT2
CCM
DI1_EXT_CLK
Low/high output voltage = N/A
ALT3
IPU
SER_DISP1_CS
Hysteresis Enable (HYS) = Enabled
ALT4
ECSPI-1
SS0
Pull / Keep Select (PUE) = Pull
ALT5
I2C-2
SCL
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D16
ALT0
EXTMC
WEIM_D[16]
IOMUXC_SW_PAD_CTL_PAD_EIM_D16
ALT1
GPIO-3
GPIO[16]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN5
Low/high output voltage = N/A
ALT3
IPU
DISPB1_SER_CLK
Hysteresis Enable (HYS) = Enabled
ALT4
ECSPI-1
SCLK
Pull / Keep Select (PUE) = Pull
ALT5
I2C-2
SDA
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_D17
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_D[17]
IOMUXC_SW_PAD_CTL_PAD_EIM_D17
ALT1
GPIO-3
GPIO[17]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN6
Low/high output voltage = N/A
ALT3
IPU
DISPB1_SER_DIN
Hysteresis Enable (HYS) = Enabled
ALT4
ECSPI-1
MISO
Pull / Keep Select (PUE) = Pull
ALT5
I2C-3
SCL
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D18
ALT0
EXTMC
WEIM_D[18]
IOMUXC_SW_PAD_CTL_PAD_EIM_D18
ALT1
GPIO-3
GPIO[18]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN7
Low/high output voltage = N/A
ALT3
IPU
DISPB1_SER_DIO
Hysteresis Enable (HYS) = Enabled
ALT4
ECSPI-1
MOSI
Pull / Keep Select (PUE) = Pull
ALT5
I2C-3
SDA
ALT6
IPU
DI1_D0_CS
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D19
ALT0
EXTMC
WEIM_D[19]
IOMUXC_SW_PAD_CTL_PAD_EIM_D19
ALT1
GPIO-3
GPIO[19]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN8
Low/high output voltage = N/A
ALT3
IPU
DISPB1_SER_RS
Hysteresis Enable (HYS) = Enabled
ALT4
ECSPI-1
SS1
Pull / Keep Select (PUE) = Pull
ALT5
EPIT-1
EPITO
ALT6
UART-1
CTS
ALT7
USB
USBH2_OC
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_D20
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_D[20]
IOMUXC_SW_PAD_CTL_PAD_EIM_D20
ALT1
GPIO-3
GPIO[20]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN16
Low/high output voltage = N/A
ALT3
IPU
SER_DISP0_CS
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
SS0
Pull / Keep Select (PUE) = Pull
ALT5
EPIT-2
EPITO
ALT6
UART-1
RTS
ALT7
USB
USBH2_PWR
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D21
ALT0
EXTMC
WEIM_D[21]
IOMUXC_SW_PAD_CTL_PAD_EIM_D21
ALT1
GPIO-3
GPIO[21]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN17
Low/high output voltage = N/A
ALT3
IPU
DISPB0_SER_CLK
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
SCLK
Pull / Keep Select (PUE) = Pull
ALT5
I2C-1
SCL
ALT6
USB
USBOTG_OC
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D22
ALT0
EXTMC
WEIM_D[22]
IOMUXC_SW_PAD_CTL_PAD_EIM_D22
ALT1
GPIO-3
GPIO[22]
Drive Strength (DSE) = High
ALT2
IPU
DI0_PIN1
Low/high output voltage = N/A
ALT3
IPU
DISPB0_SER_DIN
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
MISO
Pull / Keep Select (PUE) = Pull
ALT6
USB
USBOTG_PWR
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_D23
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_D[23]
IOMUXC_SW_PAD_CTL_PAD_EIM_D23
ALT1
GPIO-3
GPIO[23]
Drive Strength (DSE) = High
ALT2
UART-3
CTS
Low/high output voltage = N/A
ALT3
UART-1
DCD
Hysteresis Enable (HYS) = Enabled
ALT4
IPU
DI0_D0_CS
Pull / Keep Select (PUE) = Pull
ALT5
IPU
DI1_PIN2
ALT6
IPU
CSI1_DATA_EN
ALT7
IPU
DI1_PIN14
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_EB3
ALT0
EXTMC
WEIM_EB[3]
IOMUXC_SW_PAD_CTL_PAD_EIM_EB3
ALT1
GPIO-2
GPIO[31]
Drive Strength (DSE) = High
ALT2
UART-3
RTS
Low/high output voltage = N/A
ALT3
UART-1
RI
Hysteresis Enable (HYS) = Enabled
ALT5
IPU
DI1_PIN3
Pull / Keep Select (PUE) = Pull
ALT6
IPU
CSI1_HSYNC
ALT7
IPU
DI1_PIN16
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D24
ALT0
EXTMC
WEIM_D[24]
IOMUXC_SW_PAD_CTL_PAD_EIM_D24
ALT1
GPIO-3
GPIO[24]
Drive Strength (DSE) = High
ALT2
UART-3
TXD_MUX
Low/high output voltage = N/A
ALT3
ECSPI-1
SS2
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
SS2
Pull / Keep Select (PUE) = Pull
ALT5
AUDMUX
AUD5_RXFS
ALT6
ECSPI-2
SS2
ALT7
UART-1
DTR
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_D25
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_D[25]
IOMUXC_SW_PAD_CTL_PAD_EIM_D25
ALT1
GPIO-3
GPIO[25]
Drive Strength (DSE) = High
ALT2
UART-3
RXD_MUX
Low/high output voltage = N/A
ALT3
ECSPI-1
SS3
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
SS3
Pull / Keep Select (PUE) = Pull
ALT5
AUDMUX
AUD5_RXC
ALT6
ECSPI-2
SS3
ALT7
UART-1
DSR
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D26
ALT0
EXTMC
WEIM_D[26]
IOMUXC_SW_PAD_CTL_PAD_EIM_D26
ALT1
GPIO-3
GPIO[26]
Drive Strength (DSE) = High
ALT2
UART-2
TXD_MUX
Low/high output voltage = N/A
ALT3
FIRI
RXD
Hysteresis Enable (HYS) = Enabled
ALT4
IPU
CSI0_D[1]
Pull / Keep Select (PUE) = Pull
ALT5
IPU
DI1_PIN11
ALT6
IPU
SISG[2]
ALT7
IPU
DISP1_DAT[22]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D27
ALT0
EXTMC
WEIM_D[27]
IOMUXC_SW_PAD_CTL_PAD_EIM_D27
ALT1
GPIO-3
GPIO[27]
Drive Strength (DSE) = High
ALT2
UART-2
RXD_MUX
Low/high output voltage = N/A
ALT3
FIRI
TXD
Hysteresis Enable (HYS) = Enabled
ALT4
IPU
CSI0_D[0]
Pull / Keep Select (PUE) = Pull
ALT5
IPU
DI1_PIN13
ALT6
IPU
SISG[3]
ALT7
IPU
DISP1_DAT[23]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
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269
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_D28
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_D[28]
IOMUXC_SW_PAD_CTL_PAD_EIM_D28
ALT1
GPIO-3
GPIO[28]
Drive Strength (DSE) = High
ALT2
UART-2
CTS
Low/high output voltage = N/A
ALT3
IPU
DISPB0_SER_DIO
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
MOSI
Pull / Keep Select (PUE) = Pull
ALT5
I2C-1
SDA
ALT6
IPU
EXT_TRIG
ALT7
IPU
DI0_PIN13
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D29
ALT0
EXTMC
WEIM_D[29]
IOMUXC_SW_PAD_CTL_PAD_EIM_D29
ALT1
GPIO-3
GPIO[29]
Drive Strength (DSE) = High
ALT2
UART-2
RTS
Low/high output voltage = N/A
ALT3
IPU
DISPB0_SER_RS
Hysteresis Enable (HYS) = Enabled
ALT4
CSPI
SS0
Pull / Keep Select (PUE) = Pull
ALT5
IPU
DI1_PIN15
ALT6
IPU
CSI1_VSYNC
ALT7
IPU
DI0_PIN14
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_D30
ALT0
EXTMC
WEIM_D[30]
IOMUXC_SW_PAD_CTL_PAD_EIM_D30
ALT1
GPIO-3
GPIO[30]
Drive Strength (DSE) = High
ALT2
UART-3
CTS
Low/high output voltage = N/A
ALT3
IPU
CSI0_D[3]
Hysteresis Enable (HYS) = Enabled
ALT4
IPU
DI0_PIN11
Pull / Keep Select (PUE) = Pull
ALT5
IPU
DISP1_DAT[21]
ALT6
USB
USBH1_OC
ALT7
USB
USBH2_OC
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_D31
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_D[31]
IOMUXC_SW_PAD_CTL_PAD_EIM_D31
ALT1
GPIO-3
GPIO[31]
Drive Strength (DSE) = High
ALT2
UART-3
RTS
Low/high output voltage = N/A
ALT3
IPU
CSI0_D[2]
Hysteresis Enable (HYS) = Enabled
ALT4
IPU
DI0_PIN12
Pull / Keep Select (PUE) = Pull
ALT5
IPU
DISP1_DAT[20]
ALT6
USB
USBH1_PWR
ALT7
USB
USBH2_PWR
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_A24
ALT0
EXTMC
WEIM_A[24]
IOMUXC_SW_PAD_CTL_PAD_EIM_A24
ALT1
GPIO-5
GPIO[4]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[19]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[19]
Hysteresis Enable (HYS) = Enabled
ALT6
IPU
SISG[2]
Pull / Keep Select (PUE) = Pull
ALT7
USBPHY-2
BVALID
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_A23
ALT0
EXTMC
WEIM_A[23]
IOMUXC_SW_PAD_CTL_PAD_EIM_A23
ALT1
GPIO-6
GPIO[6]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[18]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[18]
Hysteresis Enable (HYS) = Enabled
ALT6
IPU
SISG[3]
Pull / Keep Select (PUE) = Pull
ALT7
USBPHY-2
ENDSESSION
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
271
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_A22
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_A[22]
IOMUXC_SW_PAD_CTL_PAD_EIM_A22
ALT1
GPIO-2
GPIO[16]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[17]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[17]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[7]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_A21
ALT0
EXTMC
WEIM_A[21]
IOMUXC_SW_PAD_CTL_PAD_EIM_A21
ALT1
GPIO-2
GPIO[17]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[16]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[16]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[6]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_A20
ALT0
EXTMC
WEIM_A[20]
IOMUXC_SW_PAD_CTL_PAD_EIM_A20
ALT1
GPIO-2
GPIO[18]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[15]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[15]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[5]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
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Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_A19
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_A[19]
IOMUXC_SW_PAD_CTL_PAD_EIM_A19
ALT1
GPIO-2
GPIO[19]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[14]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[14]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[4]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_A18
ALT0
EXTMC
WEIM_A[18]
IOMUXC_SW_PAD_CTL_PAD_EIM_A18
ALT1
GPIO-2
GPIO[20]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[13]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[13]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[3]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_A17
ALT0
EXTMC
WEIM_A[17]
IOMUXC_SW_PAD_CTL_PAD_EIM_A17
ALT1
GPIO-2
GPIO[21]
Drive Strength (DSE) = High
ALT2
IPU
DISP1_DAT[12]
Low/high output voltage = N/A
ALT3
IPU
CSI1_D[12]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[2]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
273
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_A16
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_A[16]
IOMUXC_SW_PAD_CTL_PAD_EIM_A16
ALT1
GPIO-2
GPIO[22]
Drive Strength (DSE) = High
ALT2
IPU
DI1_DISP_CLK
Low/high output voltage = N/A
ALT3
IPU
CSI1_PIXCLK
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[1]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_CS0
ALT0
EXTMC
WEIM_CS[0]
IOMUXC_SW_PAD_CTL_PAD_EIM_CS0
ALT1
GPIO-2
GPIO[23]
Drive Strength (DSE) = High
ALT2
ECSPI-2
SCLK
Low/high output voltage = N/A
ALT3
IPU
DI1_PIN5
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_CS1
ALT0
EXTMC
WEIM_CS[1]
IOMUXC_SW_PAD_CTL_PAD_EIM_CS1
ALT1
GPIO-2
GPIO[24]
Drive Strength (DSE) = High
ALT2
ECSPI-2
MOSI
Low/high output voltage = N/A
ALT3
IPU
DI1_PIN6
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
274
Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_OE
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_OE
IOMUXC_SW_PAD_CTL_PAD_EIM_OE
ALT1
GPIO-2
GPIO[25]
Drive Strength (DSE) = High
ALT2
ECSPI-2
MISO
Low/high output voltage = N/A
ALT3
IPU
DI1_PIN7
Hysteresis Enable (HYS) = Disabled
ALT7
USBPHY-2
IDDIG
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_RW
ALT0
EXTMC
WEIM_RW
IOMUXC_SW_PAD_CTL_PAD_EIM_RW
ALT1
GPIO-2
GPIO[26]
Drive Strength (DSE) = High
ALT2
ECSPI-2
SS0
Low/high output voltage = N/A
ALT3
IPU
DI1_PIN8
Hysteresis Enable (HYS) = Disabled
ALT7
USBPHY-2
HOSTDISCONNECT
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_LBA
ALT0
EXTMC
WEIM_LBA
IOMUXC_SW_PAD_CTL_PAD_EIM_LBA
ALT1
GPIO-2
GPIO[27]
Drive Strength (DSE) = High
ALT2
ECSPI-2
SS1
Low/high output voltage = N/A
ALT3
IPU
DI1_PIN17
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG1[0]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
275
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_EB0
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
WEIM_EB[0]
IOMUXC_SW_PAD_CTL_PAD_EIM_EB0
ALT1
GPIO-2
GPIO[28]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[11]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[11]
Hysteresis Enable (HYS) = Disabled
ALT5
GPC
PMIC_RDY
Pull / Keep Select (PUE) = Pull
ALT7
SRC
BT_CFG2[7]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_EB1
ALT0
EXTMC
WEIM_EB[1]
IOMUXC_SW_PAD_CTL_PAD_EIM_EB1
ALT1
GPIO-2
GPIO[29]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[10]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[10]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG2[6]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA0
ALT0
EXTMC
NAND_WEIM_DA[0]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA0
ALT1
GPIO-3
GPIO[0]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[9]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[9]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG2[5]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
276
Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_DA1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NAND_WEIM_DA[1]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA1
ALT1
GPIO-3
GPIO[1]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[8]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[8]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG2[4]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA2
ALT0
EXTMC
NAND_WEIM_DA[2]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA2
ALT1
GPIO-3
GPIO[2]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[7]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[7]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG2[3]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA3
ALT0
EXTMC
NAND_WEIM_DA[3]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA3
ALT1
GPIO-3
GPIO[3]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[6]
Low/high output voltage = NA
ALT4
IPU
CSI1_D[6]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG2[2]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
277
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_DA4
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NAND_WEIM_DA[4]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA4
ALT1
GPIO-3
GPIO[4]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[5]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[5]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[7]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA5
ALT0
EXTMC
NAND_WEIM_DA[5]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA5
ALT1
GPIO-3
GPIO[5]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[4]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[4]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[6]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA6
ALT0
EXTMC
NAND_WEIM_DA[6]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA6
ALT1
GPIO-3
GPIO[6]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[3]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[3]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[5]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
278
Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
EIM_DA7
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NAND_WEIM_DA[7]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA7
ALT1
GPIO-3
GPIO[7]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[2]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[2]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[4]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA8
ALT0
EXTMC
NAND_WEIM_DA[8]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA8
ALT1
GPIO-3
GPIO[8]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[1]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[1]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[3]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA9
ALT0
EXTMC
NAND_WEIM_DA[9]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA9
ALT1
GPIO-3
GPIO[9]
Drive Strength (DSE) = High
ALT3
IPU
DISP1_DAT[0]
Low/high output voltage = N/A
ALT4
IPU
CSI1_D[0]
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[2]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
279
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
EIM_DA10 ALT0
EXTMC
NAND_WEIM_DA[10]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA10
ALT1
GPIO-3
GPIO[10]
Drive Strength (DSE) = High
ALT3
IPU
DI1_PIN15
Low/high output voltage = N/A
ALT4
IPU
CSI1_DATA_EN
Hysteresis Enable (HYS) = Disabled
ALT7
SRC
BT_CFG3[1]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA11 ALT0
EXTMC
NAND_WEIM_DA[11]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA11
ALT1
GPIO-3
GPIO[11]
Drive Strength (DSE) = High
ALT3
IPU
DI1_PIN2
Low/high output voltage = N/A
ALT4
IPU
CSI1_HSYNC
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA12 ALT0
EXTMC
NAND_WEIM_DA[12]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA12
ALT1
GPIO-3
GPIO[12]
Drive Strength (DSE) = High
ALT3
IPU
DI1_PIN3
Low/high output voltage = N/A
ALT4
IPU
CSI1_VSYNC
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
EIM_DA13 ALT0
EXTMC
NAND_WEIM_DA[13]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA13
ALT1
GPIO-3
GPIO[13]
Drive Strength (DSE) = High
ALT3
IPU
DI1_D0_CS
Low/high output voltage = N/A
ALT4
CCM
DI1_EXT_CLK
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA14 ALT0
EXTMC
NAND_WEIM_DA[14]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA14
ALT1
GPIO-3
GPIO[14]
Drive Strength (DSE) = High
ALT3
IPU
DI1_D1_CS
Low/high output voltage = N/A
ALT4
CCM
DI0_EXT_CLK
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_DA15 ALT0
EXTMC
NAND_WEIM_DA[15]
IOMUXC_SW_PAD_CTL_PAD_EIM_DA15
ALT1
GPIO-3
GPIO[15]
Drive Strength (DSE) = High
ALT3
IPU
DI1_PIN1
Low/high output voltage = N/A
ALT4
IPU
DI1_PIN4
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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12/2011
6/2012
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281
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
NANDF_
WE_B
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NANDF_WE_B
IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B
ALT1
GPIO-6
GPIO[12]
Drive Strength (DSE) = High
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
NANDF_
RE_B
ALT0
EXTMC
NANDF_RE_B
IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B
ALT1
GPIO-6
GPIO[13]
Drive Strength (DSE) = High
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
EIM_WAIT ALT0
EXTMC
WEIM_WAIT
IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT
ALT1
GPIO-5
GPIO[0]
Drive Strength (DSE) = Low
ALT2
EXTMC
WEIM_DTACK_B
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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6/2012
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Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
EIM_BCLK -
Instance
EXTMC
Block I/O
WEIM_BCLK
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK
Drive Strength (DSE) = High
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = N/A
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
LVDS1_
TX3_P
ALT0
GPIO-6
GPI[22]
ALT1
LDB
LVDS1_TX3
LVDS1_
TX3_N
-
GPIO-6
GPI[23]
LVDS1_
TX2_P
ALT0
GPIO-6
GPI[24]
ALT1
LDB
LVDS1_TX2
LVDS1_
TX2_N
-
GPIO-6
GPI[25]
LVDS1_
CLK_P
ALT0
GPIO-6
GPI[26]
ALT1
LDB
LVDS1_CLK
LVDS1_
CLK_N
-
GPIO-6
GPI[27]
LVDS1_
TX1_P
ALT0
GPIO-6
GPI[28]
ALT1
LDB
LVDS1_TX1
LVDS1_
TX1_N
-
GPIO-6
GPI[29]
LVDS1_
TX0_P
ALT0
GPIO-6
GPI[30]
ALT1
LDB
LVDS1_TX0
LVDS1_
TX0_N
-
GPIO-6
GPI[31]
LVDS0_
TX3_P
ALT0
GPIO-7
GPI[22]
ALT1
LDB
LVDS0_TX3
LVDS0_
TX3_N
-
GPIO-7
GPI[23]
LVDS0_
CLK_P
ALT0
GPIO-7
GPI[24]
ALT1
LDB
LVDS0_CLK
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
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283
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
LVDS0_
CLK_N
-
GPIO-7
GPI[25]
LVDS0_
TX2_P
ALT0
GPIO-7
GPI[26]
ALT1
LDB
LVDS0_TX2
LVDS0_
TX2_N
-
GPIO-7
GPI[27]
LVDS0_
TX1_P
ALT0
GPIO-7
GPI[28]
ALT1
LDB
LVDS0_TX1
LVDS0_
TX1_N
-
GPIO-7
GPI[29]
LVDS0_
TX0_P
ALT0
GPIO-7
GPI[30]
ALT1
LDB
LVDS0_TX0
LVDS0_
TX0_N
-
GPIO-7
GPI[31]
GPIO_10
ALT0
GPIO-4
GPIO[0]
ALT1
XTALOSC32 32K_OUT
K
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_GPIO_10
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Enabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
GPIO_11
-
GPIO-4
GPIO[1]
IOMUXC_SW_PAD_CTL_PAD_GPIO_11
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Enabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
GPIO_12
-
GPIO-4
GPIO[2]
IOMUXC_SW_PAD_CTL_PAD_GPIO_12/13
GPIO_13
-
GPIO-4
GPIO[3]
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Enabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
GPIO_14
-
GPIO-4
GPIO[4]
IOMUXC_SW_PAD_CTL_PAD_GPIO_14
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Enabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
DRAM_
D24
-
EXTMC
DRAM_D[24]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
285
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
D30
Mode
-
Instance
EXTMC
Block I/O
DRAM_D[30]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
D26
-
EXTMC
DRAM_D[26]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
DQM3
-
EXTMC
DRAM_DQM[3]
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = HiZ
DRAM_
D28
-
EXTMC
DRAM_D[28]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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6/2012
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Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
D25
Mode
-
Instance
EXTMC
Block I/O
DRAM_D[25]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDQS3_B
-
EXTMC
DRAM_SDQS_B[3]
See DRAM_SDQS3 settings.
DRAM_
SDQS3
-
EXTMC
DRAM_SDQS[3]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = Dependent on reference resistor
DRAM_
D27
-
EXTMC
DRAM_D[27]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
D31
-
EXTMC
DRAM_D[31]
DRAM_
D16
-
EXTMC
DRAM_D[16]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
287
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
DRAM_
D29
-
EXTMC
DRAM_D[29]
DRAM_
D18
-
EXTMC
DRAM_D[18]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDCKE1
-
EXTMC
DRAM_SDCKE[1]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
On Die Termination = HiZ
DRAM_
D22
-
EXTMC
DRAM_D[22]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
DQM2
-
EXTMC
DRAM_DQM[2]
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = HiZ
Table continues on the next page...
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6/2012
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Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
D20
Mode
-
Instance
EXTMC
Block I/O
DRAM_D[20]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDBA0
-
EXTMC
DRAM_SDBA[0]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
D17
-
EXTMC
DRAM_D[17]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDODT1
-
EXTMC
DRAM_ODT[1]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
On Die Termination = HiZ
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
289
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
D19
Mode
-
Instance
EXTMC
Block I/O
DRAM_D[19]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDQS2_B
-
EXTMC
DRAM_SDQS_B[2]
See DRAM_SDQS2 settings.
DRAM_
SDQS2
-
EXTMC
DRAM_SDQS[2]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = Dependent on reference resistor
DRAM_
D21
-
EXTMC
DRAM_D[21]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
CS1
-
EXTMC
DRAM_CS[1]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
290
Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
D23
Mode
-
Instance
EXTMC
Block I/O
DRAM_D[23]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
RESET
-
EXTMC
DRAM_RESET
IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
On Die Termination = HiZ
DRAM_
SDBA1
-
EXTMC
DRAM_SDBA[1]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDCLK_
1_B
-
EXTMC
DRAM_SDCLK1_B
See DRAM_SDCL_K_1 settings.
DRAM_
SDCLK_1
-
EXTMC
DRAM_SDCLK1
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = DDR2 input type
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = HiZ
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
291
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
DRAM_A8 -
Instance
EXTMC
Block I/O
DRAM_A[8]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDBA2
-
EXTMC
DRAM_SDBA[2]
DRAM_
A14
-
EXTMC
DRAM_A[14]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_A3 -
EXTMC
DRAM_A[3]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_A5 -
EXTMC
DRAM_A[5]
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_A7 -
EXTMC
DRAM_A[7]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_A6 -
EXTMC
DRAM_A[6]
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
292
Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
DRAM_A9 -
EXTMC
DRAM_A[9]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_A2 -
EXTMC
DRAM_A[2]
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_A0 -
EXTMC
DRAM_A[0]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_
A15
EXTMC
DRAM_A[15]
Drive Strength (DSE) = DDR2/DDR3
-
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
A13
-
EXTMC
DRAM_A[13]
DRAM_
A11
-
EXTMC
DRAM_A[11]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_A1 -
EXTMC
DRAM_A[1]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_
A12
EXTMC
DRAM_A[12]
Drive Strength (DSE) = DDR2/DDR3
-
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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6/2012
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293
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
DRAM_
CAS
-
EXTMC
DRAM_CAS
DRAM_
SDWE
-
EXTMC
DRAM_SDWE
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
CS0
-
EXTMC
DRAM_CS[0]
DRAM_A4 -
EXTMC
DRAM_A[4]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDCLK_
0_B
-
EXTMC
DRAM_SDCLK0_B
See DRAM_SDCLK_0 settings
DRAM_
SDCLK_0
-
EXTMC
DRAM_SDCLK0
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keeper
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = DDR2 input type
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = HiZ
DRAM_
A10
-
EXTMC
DRAM_A[10]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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6/2012
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
DRAM_D4 -
Instance
EXTMC
Block I/O
DRAM_D[4]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_D6 -
EXTMC
DRAM_D[6]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_D2 -
EXTMC
DRAM_D[2]
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDQS0_B
-
EXTMC
DRAM_SDQS_B[0]
See DRAM_SDQS0 settings
DRAM_
SDQS0
-
EXTMC
DRAM_SDQS[0]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = Dependent on Reference Resistor
DRAM_
SDODT0
-
EXTMC
DRAM_ODT[0]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
On Die Termination = HiZ
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
295
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
DQM0
Mode
-
Instance
EXTMC
Block I/O
DRAM_DQM[0]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = 100k Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = HiZ
DRAM_
RAS
-
EXTMC
DRAM_RAS
IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination = HiZ
DRAM_D5 -
EXTMC
DRAM_D[5]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_D0 -
EXTMC
DRAM_D[0]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_D7 -
EXTMC
DRAM_D[7]
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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6/2012
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
DRAM_
SDCKE0
Mode
-
Instance
EXTMC
Block I/O
DRAM_SDCKE[0]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
On Die Termination =HiZ
DRAM_D1 -
EXTMC
DRAM_D[1]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
D14
-
EXTMC
DRAM_D[14]
DRAM_D3 -
EXTMC
DRAM_D[3]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
D12
-
EXTMC
DRAM_D[12]
DRAM_
D10
-
EXTMC
DRAM_D[10]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
297
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
DRAM_D8 -
EXTMC
DRAM_D[8]
IOMUXC_SW_PAD_CTL_GRP_*
DRAM_
D13
EXTMC
DRAM_D[13]
Drive Strength (DSE) = DDR2/DDR3
-
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
DRAM_
SDQS1_B
-
EXTMC
DRAM_SDQS_B[1]
See DRAM_SDQS1 settings
DRAM_
SDQS1
-
EXTMC
DRAM_SDQS[1]
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQ_S1
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
On Die Termination = Dependent on Reference Resistor
DRAM_
DQM1
-
EXTMC
DRAM_DQM[1]
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Keep
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Disabled
TEST_TS = Disabled
On Die Termination =HiZ
DRAM_D9 -
EXTMC
DRAM_D[9]
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
Instance
Block I/O
DRAM_
D15
-
EXTMC
DRAM_D[15]
DRAM_
D11
-
EXTMC
DRAM_D[11]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_GRP_*
Drive Strength (DSE) = DDR2/DDR3
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DDR/CMOS Input Mode = CMOS
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
CKIH1
-
CAMP-1
CKIH
CKIH2
-
CAMP-2
CKIH
PMIC_
ON_REQ
-
SRTC
SRTCALARM
IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = N/A
Pull Up / Down (PUS) = N/A
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
PMIC_
STBY_
REQ
-
CCM
PMIC_VSTBY_REQ
IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ
Drive Strength (DSE) = High
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = N/A
Pull Up / Down (PUS) = N/A
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
299
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
NANDF_
CLE
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NANDF_CLE
IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE
ALT1
GPIO-6
GPIO[7]
Drive Strength (DSE) = High
ALT7
USBPHY-1
VSTATUS[0]
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) =100 K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
NANDF_
ALE
ALT0
EXTMC
NANDF_ALE
IOMUXC_SW_PAD_CTL_PAD_NAND_ALE
ALT1
GPIO-6
GPIO[8]
Drive Strength (DSE) = High
ALT7
USBPHY-1
VSTATUS[1]
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
NANDF_
WP_B
ALT0
EXTMC
NANDF_WP_B
IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B
ALT1
GPIO-6
GPIO[9]
Drive Strength (DSE) = High
ALT7
USBPHY-1
VSTATUS[2]
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Freescale Semiconductor, Inc.
Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
NANDF_
RB0
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NANDF_RB[0]
IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0
ALT1
GPIO-6
GPIO[10]
Drive Strength (DSE) = High
ALT7
USBPHY-1
VSTATUS[3]
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
NANDF_
CS0
ALT0
EXTMC
NANDF_CS[0]
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0
ALT1
GPIO-6
GPIO[11]
Drive Strength (DSE) = High
ALT7
USBPHY-1
VSTATUS[4]
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
NANDF_
CS1
ALT0
EXTMC
NANDF_CS[1]
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1
ALT1
GPIO-6
GPIO[14]
Drive Strength (DSE) = High
ALT6
MLB
MLBCLK
Low/high output voltage = N/A
ALT7
USBPHY-1
VSTATUS[5]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
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301
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
NANDF_
CS2
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
EXTMC
NANDF_CS[2]
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2
ALT1
GPIO-6
GPIO[15]
Drive Strength (DSE) = High
ALT2
IPU
SISG[0]
Low/high output voltage = N/A
ALT3
ESAI-1
TX0
Hysteresis Enable (HYS) = Enabled
ALT4
EXTMC
WEIM_CRE
Pull / Keep Select (PUE) = Pull
ALT5
CCM
CSI0_MCLK
ALT6
MLB
MLBSIG
ALT7
USBPHY-1
VSTATUS[6]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
NANDF_
CS3
ALT0
EXTMC
NANDF_CS[3]
IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3
ALT1
GPIO-6
GPIO[16]
Drive Strength (DSE) = High
ALT2
IPU
SISG[1]
Low/high output voltage = N/A
ALT3
ESAI-1
TX1
Hysteresis Enable (HYS) = Enabled
ALT4
EXTMC
WEIM_A[26]
Pull / Keep Select (PUE) = Pull
ALT6
MLB
MLBDAT
ALT7
USBPHY-1
VSTATUS[7]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_
MDIO
ALT0
FEC
MDIO
IOMUXC_SW_PAD_CTL_PAD_FEC_MDIO
ALT1
GPIO-1
GPIO[22]
Drive Strength (DSE) = High
ALT2
ESAI-1
SCKR
Low/high output voltage = N/A
ALT3
FEC
COL
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_PS2
Pull / Keep Select (PUE) = Pull
ALT5
SDMA
DEBUG_BUS_DEVICE[3]
ALT6
EXTMC
EMI_DEBUG[49]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
FEC_
REF_CLK
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
FEC
TX_CLK
IOMUXC_SW_PAD_CTL_PAD_FEC_REF_CLK
ALT1
GPIO-1
GPIO[23]
Drive Strength (DSE) = High
ALT2
ESAI-1
FSR
Low/high output voltage = N/A
ALT5
SDMA
DEBUG_BUS_DEVICE[4]
Hysteresis Enable (HYS) = Enabled
ALT6
EXTMC
EMI_DEBUG[50]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_RX_
ER
ALT0
FEC
RX_ER
IOMUXC_SW_PAD_CTL_PAD_FEC_RX_ER
ALT1
GPIO-1
GPIO[24]
Drive Strength (DSE) = High
ALT2
ESAI-1
HCKR
Low/high output voltage = N/A
ALT3
FEC
RX_CLK
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_PS3
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_
CRS_DV
ALT0
FEC
RX_DV
IOMUXC_SW_PAD_CTL_PAD_FEC_CRS_DV
ALT1
GPIO-1
GPIO[25]
Drive Strength (DSE) = High
ALT2
ESAI-1
SCKT
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
12/2011
6/2012
Freescale Semiconductor, Inc.
303
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
FEC_
RXD1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
FEC
RDATA[1]
IOMUXC_SW_PAD_CTL_PAD_FEC_RXD1
ALT1
GPIO-1
GPIO[26]
Drive Strength (DSE) = High
ALT2
ESAI-1
FST
Low/high output voltage = N/A
ALT3
MLB
MLBSIG
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_PS1
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_
RXD0
ALT0
FEC
RDATA[0]
IOMUXC_SW_PAD_CTL_PAD_FEC_RXD0
ALT1
GPIO-1
GPIO[27]
Drive Strength (DSE) = High
ALT2
ESAI-1
HCKT
Low/high output voltage = N/A
ALT3
XTALOSC32 32K_OUT
K
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_TX_
EN
ALT0
FEC
TX_EN
IOMUXC_SW_PAD_CTL_PAD_FEC_TX_EN
ALT1
GPIO-1
GPIO[28]
Drive Strength (DSE) = High
ALT2
ESAI-1
TX3_RX2
Low/high output voltage = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
FEC_
TXD1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
FEC
TDATA[1]
IOMUXC_SW_PAD_CTL_PAD_FEC_TXD1
ALT1
GPIO-1
GPIO[29]
Drive Strength (DSE) = High
ALT2
ESAI-1
TX2_RX3
Low/high output voltage = N/A
ALT3
MLB
MLBCLK
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_PRSC_CLK
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_
TXD0
ALT0
FEC
TDATA[0]
IOMUXC_SW_PAD_CTL_PAD_FEC_TXD0
ALT1
GPIO-1
GPIO[30]
Drive Strength (DSE) = High
ALT2
ESAI-1
TX4_RX1
Low/high output voltage = N/A
ALT7
USBPHY-2
DATAOUT[0]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
FEC_MDC ALT0
FEC
MDC
IOMUXC_SW_PAD_CTL_PAD_FEC_MDC
ALT1
GPIO-1
GPIO[31]
Drive Strength (DSE) = High
ALT2
ESAI-1
TX5_RX0
Low/high output voltage = N/A
ALT3
MLB
MLBDAT
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_ALARM1_TRIG
Pull / Keep Select (PUE) = Pull
ALT7
USBPHY-2
DATAOUT[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DIOW
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
DIOW
IOMUXC_SW_PAD_CTL_PAD_PATA_DIOW
ALT1
GPIO-6
GPIO[17]
Drive Strength (DSE) = High
ALT3
UART-1
TXD_MUX
Low/high output voltage = N/A
ALT7
USBPHY-2
DATAOUT[2]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DMACK
ALT0
PATA
DMACK
IOMUXC_SW_PAD_CTL_PAD_PATA_DMACK
ALT1
GPIO-6
GPIO[18]
Drive Strength (DSE) = High
ALT3
UART-1
RXD_MUX
Low/high output voltage = N/A
ALT7
USBPHY-2
DATAOUT[3]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DMARQ
ALT0
PATA
DMARQ
IOMUXC_SW_PAD_CTL_PAD_PATA_DMARQ
ALT1
GPIO-7
GPIO[0]
Drive Strength (DSE) = High
ALT3
UART-2
TXD_MUX
Low/high output voltage = N/A
ALT5
CCM
CCM_OUT_0
Hysteresis Enable (HYS) = Enabled
ALT7
USBPHY-2
DATAOUT[4]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
BUFFER_
EN
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
BUFFER_EN
IOMUXC_SW_PAD_CTL_PAD_PATA_BUFFER_EN
ALT1
GPIO-7
GPIO[1]
Drive Strength (DSE) = High
ALT3
UART-2
RXD_MUX
Low/high output voltage = N/A
ALT5
CCM
CCM_OUT_1
Hysteresis Enable (HYS) = Enabled
ALT7
USBPHY-2
DATAOUT[5]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
INTRQ
ALT0
PATA
INTRQ
IOMUXC_SW_PAD_CTL_PAD_PATA_INTRQ
ALT1
GPIO-7
GPIO[2]
Drive Strength (DSE) = High
ALT3
UART-2
CTS
Low/high output voltage = N/A
ALT4
FLEXCAN-1
TXCAN
Hysteresis Enable (HYS) = Enabled
ALT5
CCM
CCM_OUT_2
Pull / Keep Select (PUE) = Pull
ALT7
USBPHY-2
DATAOUT[6]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DIOR
ALT0
PATA
DIOR
IOMUXC_SW_PAD_CTL_PAD_PATA_DIOR
ALT1
GPIO-7
GPIO[3]
Drive Strength (DSE) = High
ALT3
UART-2
RTS
Low/high output voltage = N/A
ALT4
FLEXCAN-1
RXCAN
Hysteresis Enable (HYS) = Enabled
ALT7
USBPHY-2
DATAOUT[7]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
RESET_B
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
PATA_RESET_B
IOMUXC_SW_PAD_CTL_PAD_PATA_RESET_B
ALT1
GPIO-7
GPIO[4]
Drive Strength (DSE) = High
ALT2
ESDHCV3-3
CMD
Low/high output voltage = N/A
ALT3
UART-1
CTS
Hysteresis Enable (HYS) = Enabled
ALT4
FLEXCAN-2
TXCAN
Pull / Keep Select (PUE) = Pull
ALT7
USBPHY-1
DATAOUT[0]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
IORDY
ALT0
PATA
IORDY
IOMUXC_SW_PAD_CTL_PAD_PATA_IORDY
ALT1
GPIO-7
GPIO[5]
Drive Strength (DSE) = High
ALT2
ESDHCV3-3
CLK
Low/high output voltage = N/A
ALT3
UART-1
RTS
Hysteresis Enable (HYS) = Enabled
ALT4
FLEXCAN-2
RXCAN
Pull / Keep Select (PUE) = Pull
ALT7
USBPHY-1
DATAOUT[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DA_0
ALT0
PATA
DA_0
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_0
ALT1
GPIO-7
GPIO[6]
Drive Strength (DSE) = High
ALT2
ESDHCV3-3
RST
Low/high output voltage = N/A
ALT4
OWIRE
LINE
Hysteresis Enable (HYS) = Enabled
ALT7
USBPHY-1
DATAOUT[2]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DA_1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
DA_1
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_1
ALT1
GPIO-7
GPIO[7]
Drive Strength (DSE) = High
ALT2
ESDHCV2-4
CMD
Low/high output voltage = N/A
ALT4
UARTV3-3
CTS
Hysteresis Enable (HYS) = Enabled
ALT7
USBPHY-1
DATAOUT[3]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DA_2
ALT0
PATA
DA_2
IOMUXC_SW_PAD_CTL_PAD_PATA_DA_2
ALT1
GPIO-7
GPIO[8]
Drive Strength (DSE) = High
ALT2
ESDHCV2-4
CLK
Low/high output voltage = N/A
ALT4
UART-3
RTS
Hysteresis Enable (HYS) = Enabled
ALT7
USBPHY-1
DATAOUT[4]
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
CS_0
ALT0
PATA
CS_0
IOMUXC_SW_PAD_CTL_PAD_PATA_CS_0
ALT1
GPIO-7
GPIO[9]
Drive Strength (DSE) = High
ALT4
UART-3
TXD_MUX
Low/high output voltage = N/A
ALT7
USBPHY-1
DATAOUT[5]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
CS_1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
CS_1
IOMUXC_SW_PAD_CTL_PAD_PATA_CS_1
ALT1
GPIO-7
GPIO[10]
Drive Strength (DSE) = High
ALT4
UART-3
RXD_MUX
Low/high output voltage = N/A
ALT7
USBPHY-1
DATAOUT[6]
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA0
ALT0
PATA
PATA_DATA[0]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA0
ALT1
GPIO-2
GPIO[0]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[0]
Low/high output voltage = N/A
ALT4
ESDHCV3-3
DAT4
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[0]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[0]
ALT7
USBPHY-1
DATAOUT[7]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA1
ALT0
PATA
PATA_DATA[1]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA1
ALT1
GPIO-2
GPIO[1]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[1]
Low/high output voltage = N/A
ALT4
ESDHCV3-3
DAT5
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[1]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DATA2
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
PATA_DATA[2]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA2
ALT1
GPIO-2
GPIO[2]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[2]
Low/high output voltage = N/A
ALT4
ESDHCV3-3
DAT6
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[2]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[2]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA3
ALT0
PATA
PATA_DATA[3]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA3
ALT1
GPIO-2
GPIO[3]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[3]
Low/high output voltage = N/A
ALT4
ESDHCV3-3
DAT7
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[3]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[3]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA4
ALT0
PATA
PATA_DATA[4]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA4
ALT1
GPIO-2
GPIO[4]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[4]
Low/high output voltage = N/A
ALT4
ESDHCV2-4
DAT4
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[4]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[4]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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311
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DATA5
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
PATA_DATA[5]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA5
ALT1
GPIO-2
GPIO[5]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[5]
Low/high output voltage = N/A
ALT4
ESDHCV2-4
DAT5
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[5]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[5]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA6
ALT0
PATA
PATA_DATA[6]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA6
ALT1
GPIO-2
GPIO[6]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[6]
Low/high output voltage = N/A
ALT4
ESDHCV2-4
DAT6
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[6]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[6]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA7
ALT0
PATA
PATA_DATA[7]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA7
ALT1
GPIO-2
GPIO[7]
Drive Strength (DSE) = High
ALT3
EXTMC
NANDF_D[7]
Low/high output voltage = N/A
ALT4
ESDHCV2-4
DAT7
Hysteresis Enable (HYS) = Enabled
ALT5
GPU3D
GPU_DEBUG_OUT[7]
Pull / Keep Select (PUE) = Pull
ALT6
IPU
IPU_DIAG_BUS[7]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DATA8
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
PATA_DATA[8]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA8
ALT1
GPIO-2
GPIO[8]
Drive Strength (DSE) = High
ALT2
ESDHCV2-1
DAT4
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[8]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV3-3
DAT0
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[8]
ALT6
IPU
IPU_DIAG_BUS[8]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA9
ALT0
PATA
PATA_DATA[9]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA9
ALT1
GPIO-2
GPIO[9]
Drive Strength (DSE) = High
ALT2
ESDHCV2-1
DAT5
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[9]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV3-3
DAT1
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[9]
ALT6
IPU
IPU_DIAG_BUS[9]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA10
ALT0
PATA
PATA_DATA[10]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA10
ALT1
GPIO-2
GPIO[10]
Drive Strength (DSE) = High
ALT2
ESDHCV2-1
DAT6
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[10]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV3-3
DAT2
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[10]
ALT6
IPU
IPU_DIAG_BUS[10]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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313
Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DATA11
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
PATA_DATA[11]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA11
ALT1
GPIO-2
GPIO[11]
Drive Strength (DSE) = High
ALT2
ESDHCV2-1
DAT7
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[11]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV3-3
DAT3
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[11]
ALT6
IPU
IPU_DIAG_BUS[11]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA12
ALT0
PATA
PATA_DATA[12]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA12
ALT1
GPIO-2
GPIO[12]
Drive Strength (DSE) = High
ALT2
ESDHCV2-2
DAT4
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[12]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV2-4
DAT0
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[12]
ALT6
IPU
IPU_DIAG_BUS[12]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA13
ALT0
PATA
PATA_DATA[13]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA13
ALT1
GPIO-2
GPIO[13]
Drive Strength (DSE) = High
ALT2
ESDHCV2-2
DAT5
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[13]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV2-4
DAT1
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[13]
ALT6
IPU
IPU_DIAG_BUS[13]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
PATA_
DATA14
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
PATA
PATA_DATA[14]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA14
ALT1
GPIO-2
GPIO[14]
Drive Strength (DSE) = High
ALT2
ESDHCV2-2
DAT6
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[14]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV2-4
DAT2
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[14]
ALT6
IPU
IPU_DIAG_BUS[14]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
PATA_
DATA15
ALT0
PATA
PATA_DATA[15]
IOMUXC_SW_PAD_CTL_PAD_PATA_DATA15
ALT1
GPIO-2
GPIO[15]
Drive Strength (DSE) = High
ALT2
ESDHCV2-2
DAT7
Low/high output voltage = N/A
ALT3
EXTMC
NANDF_D[15]
Hysteresis Enable (HYS) = Enabled
ALT4
ESDHCV2-4
DAT3
Pull / Keep Select (PUE) = Pull
ALT5
GPU3D
GPU_DEBUG_OUT[15]
ALT6
IPU
IPU_DIAG_BUS[15]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD1_
DATA0
ALT0
ESDHCV2-1
DAT0
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0
ALT1
GPIO-1
GPIO[16]
Drive Strength (DSE) = High
ALT3
GPT
IND_CAPIN1
Low/high output voltage = N/A
ALT5
CSPI
MISO
Hysteresis Enable (HYS) = Enabled
ALT7
CCM
PLL3_BYP
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
SD1_
DATA1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESDHCV2-1
DAT1
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1
ALT1
GPIO-1
GPIO[17]
Drive Strength (DSE) = High
ALT3
GPT
IND_CAPIN2
Low/high output voltage = N/A
ALT5
CSPI
SS0
Hysteresis Enable (HYS) = Enabled
ALT7
CCM
PLL4_BYP
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD1_CMD ALT0
ESDHCV2-1
CMD
IOMUXC_SW_PAD_CTL_PAD_SD1_CMD
ALT1
GPIO-1
GPIO[18]
Drive Strength (DSE) = High
ALT3
GPT
DO_CMPOUT1
Low/high output voltage = N/A
ALT5
CSPI
MOSI
Hysteresis Enable (HYS) = Enabled
ALT7
CCM
PLL1_BYP
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD1_
DATA2
ALT0
ESDHCV2-1
DAT2
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2
ALT1
GPIO-1
GPIO[19]
Drive Strength (DSE) = High
ALT2
GPT
DO_CMPOUT2
Low/high output voltage = N/A
ALT3
PWM-2
PWMO
Hysteresis Enable (HYS) = Enabled
ALT4
WDOG-1
WDOG_B
Pull / Keep Select (PUE) = Pull
ALT5
CSPI
SS1
ALT6
WDOG-1
WDOG_RST_B_DEB
ALT7
CCM
PLL2_BYP
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
SD1_CLK
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESDHCV2-1
CLK
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK
ALT1
GPIO-1
GPIO[20]
Drive Strength (DSE) = High
ALT2
XTALOSC32 32K_OUT
K
Low/high output voltage = N/A
ALT3
GPT
IND_CLKIN
Pull / Keep Select (PUE) = Pull
ALT5
CSPI
SCLK
Pull Up / Down (PUS) = 100K Ohm Pull Up
ALT7
SATA_PHY
DTB[0]
DSE_TEST = Regular
Hysteresis Enable (HYS) = Enabled
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD1_
DATA3
ALT0
ESDHCV2-1
DAT3
OMUXC_SW_PAD_CTL_PAD_SD1_DATA3
ALT1
GPIO-1
GPIO[21]
Drive Strength (DSE) = High
ALT2
GPT
IND_CMPOUT3
Low/high output voltage = N/A
ALT3
PWM-1
PWMO
Hysteresis Enable (HYS) = Enabled
ALT4
WDOG-2
WDOG_B
Pull / Keep Select (PUE) = Pull
ALT5
CSPI
SS2
ALT6
WDOG-2
WDOG_RST_B_DEB
ALT7
SATA_PHY
DTB[1]
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD2_CLK
ALT0
ESDHCV2-2
CLK
IOMUXC_SW_PAD_CTL_PAD_SD2_CLK
ALT1
GPIO-1
GPIO[10]
Drive Strength (DSE) = High
ALT2
KPP
COL[5]
Low/high output voltage = N/A
ALT3
AUDMUX
AUD4_RXFS
Hysteresis Enable (HYS) = Enabled
ALT5
CSPI
SCLK
Pull / Keep Select (PUE) = Pull
ALT7
SCC
RANDOM_V
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
Mode
SD2_CMD ALT0
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ESDHCV2-2
CMD
IOMUXC_SW_PAD_CTL_PAD_SD2_CMD
ALT1
GPIO-1
GPIO[11]
Drive Strength (DSE) = High
ALT2
KPP
ROW[5]
Low/high output voltage = N/A
ALT3
AUDMUX
AUD4_RXC
Hysteresis Enable (HYS) = Enabled
ALT5
CSPI
MOSI
Pull / Keep Select (PUE) = Pull
ALT7
SCC
RANDOM
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD2_
DATA3
ALT0
ESDHCV2-2
DAT3
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3
ALT1
GPIO-1
GPIO[12]
Drive Strength (DSE) = High
ALT2
KPP
COL[6]
Low/high output voltage = N/A
ALT3
AUDMUX
AUD4_TXC
Hysteresis Enable (HYS) = Enabled
ALT5
CSPI
SS2
Pull / Keep Select (PUE) = Pull
ALT7
SJC
DONE
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD2_
DATA2
ALT0
ESDHCV2-2
DAT2
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2
ALT1
GPIO-1
GPIO[13]
Drive Strength (DSE) = High
ALT2
KPP
ROW[6]
Low/high output voltage = N/A
ALT3
AUDMUX
AUD4_TXD
Hysteresis Enable (HYS) = Enabled
ALT5
CSPI
SS1
Pull / Keep Select (PUE) = Pull
ALT7
SJC
FAIL
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
SD2_
DATA1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESDHCV2-2
DAT1
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1
ALT1
GPIO-1
GPIO[14]
Drive Strength (DSE) = High
ALT2
KPP
COL[7]
Low/high output voltage = N/A
ALT3
AUDMUX
AUD4_TXFS
Hysteresis Enable (HYS) = Enabled
ALT5
CSPI
SS0
Pull / Keep Select (PUE) = Pull
ALT7
RTIC
RTIC_SEC_VIO
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
SD2_
DATA0
ALT0
ESDHCV2-2
DAT0
IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0
ALT1
GPIO-1
GPIO[15]
Drive Strength (DSE) = High
ALT2
KPP
ROW[7]
Low/high output voltage = N/A
ALT3
AUDMUX
AUD4_RXD
Hysteresis Enable (HYS) = Enabled
ALT5
CSPI
MISO
Pull / Keep Select (PUE) = Pull
ALT7
RTIC
RTIC_DONE_INT
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
GPIO_0
ALT0
CCM
CLKO
IOMUXC_SW_PAD_CTL_PAD_GPIO_0
ALT1
GPIO-1
GPIO[0]
Drive Strength (DSE) = High
ALT2
KPP
COL[5]
Low/high output voltage = N/A
ALT3
CCM
SSI_EXT1_CLK
Hysteresis Enable (HYS) = Enabled
ALT4
EPIT-1
EPITO
Pull / Keep Select (PUE) = Pull
ALT5
SRTC
SRTC_ALARM_DEB
ALT6
USB
USBH1_PWR
ALT7
CSU
TD
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
GPIO_1
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESAI-1
SCKR
IOMUXC_SW_PAD_CTL_PAD_GPIO_1
ALT1
GPIO-1
GPIO[1]
Drive Strength (DSE) = High
ALT2
KPP
ROW[5]
Low/high output voltage = N/A
ALT3
CCM
SSI_EXT2_CLK
Hysteresis Enable (HYS) = Enabled
ALT4
PWM-2
PWMO
Pull / Keep Select (PUE) = Pull
ALT5
WDOG-2
WDOG_B
ALT6
ESDHCV2-1
CD
ALT7
SRC
TESTER_ACK
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
GPIO_9
ALT0
ESAI-1
FSR
IOMUXC_SW_PAD_CTL_PAD_GPIO_9
ALT1
GPIO-1
GPIO[9]
Drive Strength (DSE) = High
ALT2
KPP
COL[6]
Low/high output voltage = N/A
ALT3
CCM
REF_EN_B
Hysteresis Enable (HYS) = Enabled
ALT4
PWM-1
PWMO
Pull / Keep Select (PUE) = Pull
ALT5
WDOG-1
WDOG_B
ALT6
ESDHCV2-1
WP
ALT7
SCC
FAIL_STATE
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
GPIO_3
ALT0
ESAI-1
HCKR
IOMUXC_SW_PAD_CTL_PAD_GPIO_3
ALT1
GPIO-1
GPIO[3]
Drive Strength (DSE) = High
ALT2
I2C-3
SCL
Low/high output voltage = N/A
ALT3
DPLLC-1
TOG_EN
Hysteresis Enable (HYS) = Enabled
ALT4
CCM
CLKO2
Pull / Keep Select (PUE) = Pull
ALT5
OBSERVE_
MUX
OBSRV_INT_OUT0
ALT6
USB
USBH1_OC
Open Drain Enable (ODE) = Disabled
ALT7
MLB
MLBCLK
Pull / Keep Enable (PKE) =Enabled
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
GPIO_6
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESAI-1
SCKT
IOMUXC_SW_PAD_CTL_PAD_GPIO_6
ALT1
GPIO-1
GPIO[6]
Drive Strength (DSE) = High
ALT2
I2C-3
SDA
Low/high output voltage = N/A
ALT3
CCM
CCM_OUT_0
Hysteresis Enable (HYS) = Enabled
ALT4
CSU
CSU_INT_DEB
Pull / Keep Select (PUE) = Pull
ALT5
OBSERVE_
MUX
OBSRV_INT_OUT1
ALT6
ESDHCV2-2
LCTL
Open Drain Enable (ODE) = Disabled
ALT7
MLB
MLBSIG
Pull / Keep Enable (PKE) =Enabled
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
TEST_TS = Disabled
GPIO_2
ALT0
ESAI-1
FST
IOMUXC_SW_PAD_CTL_PAD_GPIO_2
ALT1
GPIO-1
GPIO[2]
Drive Strength (DSE) = High
ALT2
KPP
ROW[6]
Low/high output voltage = N/A
ALT3
CCM
CCM_OUT_1
Hysteresis Enable (HYS) = Enabled
ALT4
CSU
CSU_ALARM_AUT[0]
Pull / Keep Select (PUE) = Pull
ALT5
OBSERVE_
MUX
OBSRV_INT_OUT2
ALT6
ESDHCV2-2
WP
Open Drain Enable (ODE) = Disabled
ALT7
MLB
MLBDAT
Pull / Keep Enable (PKE) =Enabled
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
TEST_TS = Disabled
GPIO_4
ALT0
ESAI-1
HCKT
IOMUXC_SW_PAD_CTL_PAD_GPIO_4
ALT1
GPIO-1
GPIO[4]
Drive Strength (DSE) = High
ALT2
KPP
COL[7]
Low/high output voltage = N/A
ALT3
CCM
CCM_OUT_2
Hysteresis Enable (HYS) = Enabled
ALT4
CSU
CSU_ALARM_AUT[1]
Pull / Keep Select (PUE) = Pull
ALT5
OBSERVE_
MUX
OBSRV_INT_OUT3
ALT6
ESDHCV2-2
CD
Open Drain Enable (ODE) = Disabled
ALT7
SCC
SEC_STATE
Pull / Keep Enable (PKE) =Enabled
Pull Up / Down (PUS) = 100K Ohm Pull Up
DSE_TEST = Regular
TEST_TS = Disabled
Table continues on the next page...
i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2,.1,
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
GPIO_5
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESAI-1
TX2_RX3
IOMUXC_SW_PAD_CTL_PAD_GPIO_5
ALT1
GPIO-1
GPIO[5]
Drive Strength (DSE) = High
ALT2
KPP
ROW[7]
Low/high output voltage = N/A
ALT3
CCM
CLKO
Hysteresis Enable (HYS) = Enabled
ALT4
CSU
CSU_ALARM_AUT[2]
Pull / Keep Select (PUE) = Pull
ALT5
OBSERVE_
MUX
OBSRV_INT_OUT4
ALT6
I2C-3
SCL
Open Drain Enable (ODE) = Disabled
ALT7
CCM
PLL1_BYP
Pull / Keep Enable (PKE) =Enabled
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
TEST_TS = Disabled
GPIO_7
ALT0
ESAI-1
TX4_RX1
IOMUXC_SW_PAD_CTL_PAD_GPIO_7
ALT1
GPIO-1
GPIO[7]
Drive Strength (DSE) = High
ALT2
EPIT-1
EPITO
Low/high output voltage = N/A
ALT3
FLEXCAN-1
TXCAN
Hysteresis Enable (HYS) = Enabled
ALT4
UART-2
TXD_MUX
Pull / Keep Select (PUE) = Pull
ALT5
FIRI
RXD
ALT6
SPDIF
PLOCK
ALT7
CCM
PLL2_BYP
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
GPIO_8
ALT0
ESAI-1
TX5_RX0
IOMUXC_SW_PAD_CTL_PAD_GPIO_8
ALT1
GPIO-1
GPIO[8]
Drive Strength (DSE) = High
ALT2
EPIT-2
EPITO
Low/high output voltage = N/A
ALT3
FLEXCAN-1
RXCAN
Hysteresis Enable (HYS) = Enabled
ALT4
UART-2
RXD_MUX
Pull / Keep Select (PUE) = Pull
ALT5
FIRI
TXD
ALT6
SPDIF
SRCLK
ALT7
CCM
PLL3_BYP
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
GPIO_16
Mode
Instance
Block I/O
Pad Control Register / Package Pin Drive Default
Settings
ALT0
ESAI-1
TX3_RX2
IOMUXC_SW_PAD_CTL_PAD_GPIO_16
ALT1
GPIO-7
GPIO[11]
Drive Strength (DSE) = High
ALT2
TZIC
PWRFAIL_INT
Low/high output voltage = N/A
ALT3
ARM
Platform
PMU_IRQ_B
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_EXT_TRIG1
Pull Up / Down (PUS) = 360K Ohm Pull Down
ALT5
SPDIF
IN1
DSE_TEST = Regular
ALT6
I2C-3
SDA
Open Drain Enable (ODE) = Disabled
ALT7
SJC
DE_B
Pull / Keep Enable (PKE) =Enabled
Pull / Keep Select (PUE) = Pull
TEST_TS = Disabled
GPIO_17
ALT0
ESAI-1
TX0
IOMUXC_SW_PAD_CTL_PAD_GPIO_17
ALT1
GPIO-7
GPIO[12]
Drive Strength (DSE) = High
ALT2
SDMA
SDMA_EXT_EVENT[0]
Low/high output voltage = N/A
ALT3
GPC
PMIC_RDY
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_FSV_TRIG
Pull / Keep Select (PUE) = Pull
ALT5
SPDIF
OUT1
ALT6
IPU
SNOOP2
ALT7
SJC
JTAG_ACT
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
GPIO_18
ALT0
ESAI-1
TX1
IOMUXC_SW_PAD_CTL_PAD_GPIO_18
ALT1
GPIO-7
GPIO[13]
Drive Strength (DSE) = High
ALT2
SDMA
SDMA_EXT_EVENT[1]
Low/high output voltage = N/A
ALT3
OWIRE
LINE
Hysteresis Enable (HYS) = Enabled
ALT4
RTC
CE_RTC_ALARM2_TRIG
Pull / Keep Select (PUE) = Pull
ALT5
CCM
ASRC_EXT_CLK
ALT6
ESDHCV2-1
LCTL
ALT7
SRC
SYSTEM_RST
Pull Up / Down (PUS) = 360K Ohm Pull Down
DSE_TEST = Regular
Open Drain Enable (ODE) = Disabled
Pull / Keep Enable (PKE) =Enabled
TEST_TS = Disabled
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
POR_B
Mode
-
Instance
SRC
Block I/O
POR_B
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_POR_B
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
BOOT_
MODE1
-
SRC
BOOT_MODE[1]
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = Fast
TEST_TS = Disabled
RESET_
IN_B
-
SRC
RESET_B
IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Up
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-2. Pin Alternate Modes (continued)
Package
Pin Name
BOOT_
MODE0
Mode
-
Instance
SRC
Block I/O
BOOT_MODE[0]
Pad Control Register / Package Pin Drive Default
Settings
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Enabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
TEST_
MODE
-
TCU
TEST_MODE
IOMUXC_SW_PAD_CTL_PAD_TEST_MODE
Drive Strength (DSE) = N/A
Hysteresis Enable (HYS) = Disabled
Pull / Keep Select (PUE) = Pull
Pull Up / Down (PUS) = 100K Ohm Pull Down
Strength Mode (STRENGTH_MODE) = 4-LEVEL
DSE_TEST = Regular
Open Drain Enable (ODE) = N/A
Pull / Keep Enable (PKE) =Enabled
Slew Rate () = N/A
TEST_TS = Disabled
Table 4-3 shows block I/O multiplexing options by block instance.
Table 4-3. Muxing Options sorted by IPs
Block Instance
Block I/O
Pin
Mode
TZIC
PWRFAIL_INT
GPIO_16
ALT2
RTIC
RTIC_DONE_INT
SD2_DATA0
ALT7
RTIC_SEC_VIO
SD2_DATA1
ALT7
SRTCALARM
PMIC_ON_REQ
No Muxing (ALT0)
SRTC_ALARM_DEB
GPIO_0
ALT5
TCU
TEST_MODE
TEST_MODE
No Muxing (ALT0)
GPC
PMIC_RDY
EIM_EB0
ALT5
GPIO_17
ALT3
SRTC
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
MLB
Block I/O
MLBCLK
ALT3
GPIO_3
ALT7
NANDF_CS1
ALT6
FEC_MDC
ALT3
GPIO_2
ALT7
NANDF_CS3
ALT6
FEC_RXD1
ALT3
GPIO_6
ALT7
NANDF_CS2
ALT6
CSI0_DAT6
ALT3
DISP0_DAT22
ALT2
EIM_D17
ALT4
KEY_COL1
ALT5
CSI0_DAT5
ALT3
DISP0_DAT21
ALT2
EIM_D18
ALT4
MOSI
KEY_ROW0
ALT5
RDY
GPIO_19
ALT5
SCLK
CSI0_DAT4
ALT3
DISP0_DAT20
ALT2
EIM_D16
ALT4
KEY_COL0
ALT5
CSI0_DAT7
ALT3
DISP0_DAT23
ALT2
EIM_EB2
ALT4
KEY_ROW1
ALT5
DISP0_DAT15
ALT2
EIM_D19
ALT4
KEY_COL2
ALT5
EIM_D24
ALT3
KEY_ROW2
ALT5
EIM_D25
ALT3
KEY_COL3
ALT5
MLBSIG
MISO
MOSI
ECSPI-1
Mode
FEC_TXD1
MLBDAT
ECSPI-1
Pin
SS0
SS1
SS2
SS3
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
ECSPI-2
Block I/O
MISO
ALT3
DISP0_DAT17
ALT2
EIM_OE
ALT2
CSI0_DAT9
ALT3
DISP0_DAT16
ALT2
EIM_CS1
ALT2
RDY
EIM_A25
ALT2
SCLK
CSI0_DAT8
ALT3
DISP0_DAT19
ALT2
EIM_CS0
ALT2
CSI0_DAT11
ALT3
DISP0_DAT18
ALT2
EIM_RW
ALT2
DISP0_DAT15
ALT3
EIM_LBA
ALT2
SS2
EIM_D24
ALT6
SS3
EIM_D25
ALT6
CTS
EIM_D19
ALT6
PATA_RESET_B
ALT3
DCD
EIM_D23
ALT3
DSR
EIM_D25
ALT7
DTR
EIM_D24
ALT7
RI
EIM_EB3
ALT3
RTS
EIM_D20
ALT6
PATA_IORDY
ALT3
CSI0_DAT11
ALT2
PATA_DMACK
ALT3
CSI0_DAT10
ALT2
PATA_DIOW
ALT3
EIM_D28
ALT2
PATA_INTRQ
ALT3
SS0
SS1
UART-1
RXD_MUX
TXD_MUX
UART-2
Mode
CSI0_DAT10
MOSI
ECSPI-2
Pin
CTS
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
UART-2
Block I/O
RTS
ALT2
PATA_DIOR
ALT3
EIM_D27
ALT2
GPIO_8
ALT4
PATA_BUFFER_EN
ALT3
EIM_D26
ALT2
GPIO_7
ALT4
PATA_DMARQ
ALT3
EIM_D23
ALT2
EIM_D30
ALT2
PATA_DA_1
ALT4
EIM_D31
ALT2
EIM_EB3
ALT2
PATA_DA_2
ALT4
EIM_D25
ALT2
PATA_CS_1
ALT4
EIM_D24
ALT2
PATA_CS_0
ALT4
CTS
CSI0_DAT17
ALT2
RTS
CSI0_DAT16
ALT2
RXD_MUX
CSI0_DAT13
ALT2
KEY_ROW0
ALT4
CSI0_DAT12
ALT2
KEY_COL0
ALT4
CSI0_DAT19
ALT2
KEY_ROW4
ALT4
CSI0_DAT18
ALT2
KEY_COL4
ALT4
CSI0_DAT15
ALT2
KEY_ROW1
ALT4
CSI0_DAT14
ALT2
KEY_COL1
ALT4
GPIO_3
ALT3
TXD_MUX
CTS
RTS
RXD_MUX
TXD_MUX
UART-4
TXD_MUX
UART-5
CTS
RTS
RXD_MUX
TXD_MUX
DPLLC-1
Mode
EIM_D29
RXD_MUX
UART-3
Pin
TOG_EN
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
ARM Platform
WDOG-1
Block I/O
Pin
CTI_TRIGIN7
KEY_COL0
ALT3
CTI_TRIGIN_ACK7
KEY_ROW0
ALT3
CTI_TRIGOUT6
KEY_COL2
ALT3
CTI_TRIGOUT7
KEY_ROW2
ALT3
CTI_TRIGOUT_ACK6
KEY_COL1
ALT3
CTI_TRIGOUT_ACK7
KEY_ROW1
ALT3
PMU_IRQ_B
GPIO_16
ALT3
WDOG_B
DISP0_DAT8
ALT3
GPIO_9
ALT5
SD1_DATA2
ALT4
WDOG_RST_B_DEB
WDOG-2
Mode
WDOG_B
ALT6
DISP0_DAT9
ALT3
GPIO_1
ALT5
SD1_DATA3
ALT4
WDOG_RST_B_DEB
ALT6
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
ESAI-1
Block I/O
FSR
FST
HCKR
HCKT
SCKR
SCKT
TX0
TX1
TX2_RX3
TX3_RX2
TX4_RX1
TX5_RX0
Pin
Mode
FEC_REF_CLK
ALT2
GPIO_9
ALT0
FEC_RXD1
ALT2
GPIO_2
ALT0
FEC_RX_ER
ALT2
GPIO_3
ALT0
FEC_RXD0
ALT2
GPIO_4
ALT0
FEC_MDIO
ALT2
GPIO_1
ALT0
FEC_CRS_DV
ALT2
GPIO_6
ALT0
GPIO_17
ALT0
NANDF_CS2
ALT3
GPIO_18
ALT0
NANDF_CS3
ALT3
FEC_TXD1
ALT2
GPIO_5
ALT0
FEC_TX_EN
ALT2
GPIO_16
ALT0
FEC_TXD0
ALT2
GPIO_7
ALT0
FEC_MDC
ALT2
GPIO_8
ALT0
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
DRAM_A[0]
DRAM_A0
No Muxing (ALT0)
DRAM_A[10]
DRAM_A10
No Muxing (ALT0)
DRAM_A[11]
DRAM_A11
No Muxing (ALT0)
DRAM_A[12]
DRAM_A12
No Muxing (ALT0)
DRAM_A[13]
DRAM_A13
No Muxing (ALT0)
DRAM_A[14]
DRAM_A14
No Muxing (ALT0)
DRAM_A[15]
DRAM_A15
No Muxing (ALT0)
DRAM_A[1]
DRAM_A1
No Muxing (ALT0)
DRAM_A[2]
DRAM_A2
No Muxing (ALT0)
DRAM_A[3]
DRAM_A3
No Muxing (ALT0)
DRAM_A[4]
DRAM_A4
No Muxing (ALT0)
DRAM_A[5]
DRAM_A5
No Muxing (ALT0)
DRAM_A[6]
DRAM_A6
No Muxing (ALT0)
DRAM_A[7]
DRAM_A7
No Muxing (ALT0)
DRAM_A[8]
DRAM_A8
No Muxing (ALT0)
DRAM_A[9]
DRAM_A9
No Muxing (ALT0)
DRAM_CAS
DRAM_CAS
No Muxing (ALT0)
DRAM_CS[0]
DRAM_CS0
No Muxing (ALT0)
DRAM_CS[1]
DRAM_CS1
No Muxing (ALT0)
DRAM_DQM[0]
DRAM_DQM0
No Muxing (ALT0)
DRAM_DQM[1]
DRAM_DQM1
No Muxing (ALT0)
DRAM_DQM[2]
DRAM_DQM2
No Muxing (ALT0)
DRAM_DQM[3]
DRAM_DQM3
No Muxing (ALT0)
DRAM_D[0]
DRAM_D0
No Muxing (ALT0)
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
DRAM_D[10]
DRAM_D10
No Muxing (ALT0)
DRAM_D[11]
DRAM_D11
No Muxing (ALT0)
DRAM_D[12]
DRAM_D12
No Muxing (ALT0)
DRAM_D[13]
DRAM_D13
No Muxing (ALT0)
DRAM_D[14]
DRAM_D14
No Muxing (ALT0)
DRAM_D[15]
DRAM_D15
No Muxing (ALT0)
DRAM_D[16]
DRAM_D16
No Muxing (ALT0)
DRAM_D[17]
DRAM_D17
No Muxing (ALT0)
DRAM_D[18]
DRAM_D18
No Muxing (ALT0)
DRAM_D[19]
DRAM_D19
No Muxing (ALT0)
DRAM_D[1]
DRAM_D1
No Muxing (ALT0)
DRAM_D[20]
DRAM_D20
No Muxing (ALT0)
DRAM_D[21]
DRAM_D21
No Muxing (ALT0)
DRAM_D[22]
DRAM_D22
No Muxing (ALT0)
DRAM_D[23]
DRAM_D23
No Muxing (ALT0)
DRAM_D[24]
DRAM_D24
No Muxing (ALT0)
DRAM_D[25]
DRAM_D25
No Muxing (ALT0)
DRAM_D[26]
DRAM_D26
No Muxing (ALT0)
DRAM_D[27]
DRAM_D27
No Muxing (ALT0)
DRAM_D[28]
DRAM_D28
No Muxing (ALT0)
DRAM_D[29]
DRAM_D29
No Muxing (ALT0)
DRAM_D[2]
DRAM_D2
No Muxing (ALT0)
DRAM_D[30]
DRAM_D30
No Muxing (ALT0)
DRAM_D[31]
DRAM_D31
No Muxing (ALT0)
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
DRAM_D[3]
DRAM_D3
No Muxing (ALT0)
DRAM_D[4]
DRAM_D4
No Muxing (ALT0)
DRAM_D[5]
DRAM_D5
No Muxing (ALT0)
DRAM_D[6]
DRAM_D6
No Muxing (ALT0)
DRAM_D[7]
DRAM_D7
No Muxing (ALT0)
DRAM_D[8]
DRAM_D8
No Muxing (ALT0)
DRAM_D[9]
DRAM_D9
No Muxing (ALT0)
DRAM_ODT[0]
DRAM_SDODT0
No Muxing (ALT0)
DRAM_ODT[1]
DRAM_SDODT1
No Muxing (ALT0)
DRAM_RAS
DRAM_RAS
No Muxing (ALT0)
DRAM_RESET
DRAM_RESET
No Muxing (ALT0)
DRAM_SDBA[0]
DRAM_SDBA0
No Muxing (ALT0)
DRAM_SDBA[1]
DRAM_SDBA1
No Muxing (ALT0)
DRAM_SDBA[2]
DRAM_SDBA2
No Muxing (ALT0)
DRAM_SDCKE[0]
DRAM_SDCKE0
No Muxing (ALT0)
DRAM_SDCKE[1]
DRAM_SDCKE1
No Muxing (ALT0)
DRAM_SDCLK0
DRAM_SDCLK_0
No Muxing (ALT0)
DRAM_SDCLK0_B
DRAM_SDCLK_0_B
No Muxing (ALT0)
DRAM_SDCLK1
DRAM_SDCLK_1
No Muxing (ALT0)
DRAM_SDCLK1_B
DRAM_SDCLK_1_B
No Muxing (ALT0)
DRAM_SDQS[0]
DRAM_SDQS0
No Muxing (ALT0)
DRAM_SDQS[1]
DRAM_SDQS1
No Muxing (ALT0)
DRAM_SDQS[2]
DRAM_SDQS2
No Muxing (ALT0)
DRAM_SDQS[3]
DRAM_SDQS3
No Muxing (ALT0)
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
DRAM_SDQS_B[0]
DRAM_SDQS0_B
No Muxing (ALT0)
DRAM_SDQS_B[1]
DRAM_SDQS1_B
No Muxing (ALT0)
DRAM_SDQS_B[2]
DRAM_SDQS2_B
No Muxing (ALT0)
DRAM_SDQS_B[3]
DRAM_SDQS3_B
No Muxing (ALT0)
DRAM_SDWE
DRAM_SDWE
No Muxing (ALT0)
EMI_DEBUG[0]
DI0_DISP_CLK
ALT6
EMI_DEBUG[10]
DISP0_DAT5
ALT6
EMI_DEBUG[11]
DISP0_DAT6
ALT6
EMI_DEBUG[12]
DISP0_DAT7
ALT6
EMI_DEBUG[13]
DISP0_DAT8
ALT6
EMI_DEBUG[14]
DISP0_DAT9
ALT6
EMI_DEBUG[15]
DISP0_DAT10
ALT6
EMI_DEBUG[16]
DISP0_DAT11
ALT6
EMI_DEBUG[17]
DISP0_DAT12
ALT6
EMI_DEBUG[18]
DISP0_DAT13
ALT6
EMI_DEBUG[19]
DISP0_DAT14
ALT6
EMI_DEBUG[1]
DI0_PIN15
ALT6
EMI_DEBUG[20]
DISP0_DAT15
ALT6
EMI_DEBUG[21]
DISP0_DAT16
ALT6
EMI_DEBUG[22]
DISP0_DAT17
ALT6
EMI_DEBUG[23]
DISP0_DAT18
ALT6
EMI_DEBUG[24]
DISP0_DAT19
ALT6
EMI_DEBUG[25]
DISP0_DAT20
ALT6
EMI_DEBUG[26]
DISP0_DAT21
ALT6
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
EMI_DEBUG[27]
DISP0_DAT22
ALT6
EMI_DEBUG[28]
DISP0_DAT23
ALT6
EMI_DEBUG[29]
CSI0_PIXCLK
ALT6
EMI_DEBUG[2]
DI0_PIN2
ALT6
EMI_DEBUG[30]
CSI0_MCLK
ALT6
EMI_DEBUG[31]
CSI0_DATA_EN
ALT6
EMI_DEBUG[32]
CSI0_VSYNC
ALT6
EMI_DEBUG[33]
CSI0_DAT4
ALT6
EMI_DEBUG[34]
CSI0_DAT5
ALT6
EMI_DEBUG[35]
CSI0_DAT6
ALT6
EMI_DEBUG[36]
CSI0_DAT7
ALT6
EMI_DEBUG[37]
CSI0_DAT8
ALT6
EMI_DEBUG[38]
CSI0_DAT9
ALT6
EMI_DEBUG[39]
CSI0_DAT10
ALT6
EMI_DEBUG[3]
DI0_PIN3
ALT6
EMI_DEBUG[40]
CSI0_DAT11
ALT6
EMI_DEBUG[41]
CSI0_DAT12
ALT6
EMI_DEBUG[42]
CSI0_DAT13
ALT6
EMI_DEBUG[43]
CSI0_DAT14
ALT6
EMI_DEBUG[44]
CSI0_DAT15
ALT6
EMI_DEBUG[45]
CSI0_DAT16
ALT6
EMI_DEBUG[46]
CSI0_DAT17
ALT6
EMI_DEBUG[47]
CSI0_DAT18
ALT6
EMI_DEBUG[48]
CSI0_DAT19
ALT6
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
EMI_DEBUG[49]
FEC_MDIO
ALT6
EMI_DEBUG[4]
DI0_PIN4
ALT6
EMI_DEBUG[50]
FEC_REF_CLK
ALT6
EMI_DEBUG[5]
DISP0_DAT0
ALT6
EMI_DEBUG[6]
DISP0_DAT1
ALT6
EMI_DEBUG[7]
DISP0_DAT2
ALT6
EMI_DEBUG[8]
DISP0_DAT3
ALT6
EMI_DEBUG[9]
DISP0_DAT4
ALT6
NANDF_ALE
NANDF_ALE
ALT0
NANDF_CLE
NANDF_CLE
ALT0
NANDF_CS[0]
NANDF_CS0
ALT0
NANDF_CS[1]
NANDF_CS1
ALT0
NANDF_CS[2]
NANDF_CS2
ALT0
NANDF_CS[3]
NANDF_CS3
ALT0
NANDF_D[0]
PATA_DATA0
ALT3
NANDF_D[10]
PATA_DATA10
ALT3
NANDF_D[11]
PATA_DATA11
ALT3
NANDF_D[12]
PATA_DATA12
ALT3
NANDF_D[13]
PATA_DATA13
ALT3
NANDF_D[14]
PATA_DATA14
ALT3
NANDF_D[15]
PATA_DATA15
ALT3
NANDF_D[1]
PATA_DATA1
ALT3
NANDF_D[2]
PATA_DATA2
ALT3
NANDF_D[3]
PATA_DATA3
ALT3
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
NANDF_D[4]
PATA_DATA4
ALT3
NANDF_D[5]
PATA_DATA5
ALT3
NANDF_D[6]
PATA_DATA6
ALT3
NANDF_D[7]
PATA_DATA7
ALT3
NANDF_D[8]
PATA_DATA8
ALT3
NANDF_D[9]
PATA_DATA9
ALT3
NANDF_RB[0]
NANDF_RB0
ALT0
NANDF_RE_B
NANDF_RE_B
ALT0
NANDF_WE_B
NANDF_WE_B
ALT0
NANDF_WP_B
NANDF_WP_B
ALT0
NAND_WEIM_DA[0]
EIM_DA0
ALT0
NAND_WEIM_DA[10]
EIM_DA10
ALT0
NAND_WEIM_DA[11]
EIM_DA11
ALT0
NAND_WEIM_DA[12]
EIM_DA12
ALT0
NAND_WEIM_DA[13]
EIM_DA13
ALT0
NAND_WEIM_DA[14]
EIM_DA14
ALT0
NAND_WEIM_DA[15]
EIM_DA15
ALT0
NAND_WEIM_DA[1]
EIM_DA1
ALT0
NAND_WEIM_DA[2]
EIM_DA2
ALT0
NAND_WEIM_DA[3]
EIM_DA3
ALT0
NAND_WEIM_DA[4]
EIM_DA4
ALT0
NAND_WEIM_DA[5]
EIM_DA5
ALT0
NAND_WEIM_DA[6]
EIM_DA6
ALT0
NAND_WEIM_DA[7]
EIM_DA7
ALT0
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
Block I/O
Pin
Mode
NAND_WEIM_DA[8]
EIM_DA8
ALT0
NAND_WEIM_DA[9]
EIM_DA9
ALT0
WEIM_A[16]
EIM_A16
ALT0
WEIM_A[17]
EIM_A17
ALT0
WEIM_A[18]
EIM_A18
ALT0
WEIM_A[19]
EIM_A19
ALT0
WEIM_A[20]
EIM_A20
ALT0
WEIM_A[21]
EIM_A21
ALT0
WEIM_A[22]
EIM_A22
ALT0
WEIM_A[23]
EIM_A23
ALT0
WEIM_A[24]
EIM_A24
ALT0
WEIM_A[25]
EIM_A25
ALT0
WEIM_A[26]
NANDF_CS3
ALT4
WEIM_BCLK
EIM_BCLK
No Muxing (ALT0)
WEIM_CRE
NANDF_CS2
ALT4
WEIM_CS[0]
EIM_CS0
ALT0
WEIM_CS[1]
EIM_CS1
ALT0
WEIM_CS[2]
DISP0_DAT18
ALT7
WEIM_CS[3]
DISP0_DAT19
ALT7
WEIM_DTACK_B
EIM_WAIT
ALT2
WEIM_D[16]
EIM_D16
ALT0
WEIM_D[17]
EIM_D17
ALT0
WEIM_D[18]
EIM_D18
ALT0
WEIM_D[19]
EIM_D19
ALT0
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
EXTMC
IPU
Block I/O
Pin
Mode
WEIM_D[20]
EIM_D20
ALT0
WEIM_D[21]
EIM_D21
ALT0
WEIM_D[22]
EIM_D22
ALT0
WEIM_D[23]
EIM_D23
ALT0
WEIM_D[24]
EIM_D24
ALT0
WEIM_D[25]
EIM_D25
ALT0
WEIM_D[26]
EIM_D26
ALT0
WEIM_D[27]
EIM_D27
ALT0
WEIM_D[28]
EIM_D28
ALT0
WEIM_D[29]
EIM_D29
ALT0
WEIM_D[30]
EIM_D30
ALT0
WEIM_D[31]
EIM_D31
ALT0
WEIM_EB[0]
EIM_EB0
ALT0
WEIM_EB[1]
EIM_EB1
ALT0
WEIM_EB[2]
EIM_EB2
ALT0
WEIM_EB[3]
EIM_EB3
ALT0
WEIM_LBA
EIM_LBA
ALT0
WEIM_OE
EIM_OE
ALT0
WEIM_RW
EIM_RW
ALT0
WEIM_WAIT
EIM_WAIT
ALT0
CSI0_DATA_EN
CSI0_DATA_EN
ALT0
CSI0_D[0]
EIM_D27
ALT4
CSI0_D[10]
CSI0_DAT10
ALT0
CSI0_D[11]
CSI0_DAT11
ALT0
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Pin
Mode
CSI0_D[12]
CSI0_DAT12
ALT0
CSI0_D[13]
CSI0_DAT13
ALT0
CSI0_D[14]
CSI0_DAT14
ALT0
CSI0_D[15]
CSI0_DAT15
ALT0
CSI0_D[16]
CSI0_DAT16
ALT0
CSI0_D[17]
CSI0_DAT17
ALT0
CSI0_D[18]
CSI0_DAT18
ALT0
CSI0_D[19]
CSI0_DAT19
ALT0
CSI0_D[1]
EIM_D26
ALT4
CSI0_D[2]
EIM_D31
ALT3
CSI0_D[3]
EIM_D30
ALT3
CSI0_D[4]
CSI0_DAT4
ALT0
CSI0_D[5]
CSI0_DAT5
ALT0
CSI0_D[6]
CSI0_DAT6
ALT0
CSI0_D[7]
CSI0_DAT7
ALT0
CSI0_D[8]
CSI0_DAT8
ALT0
CSI0_D[9]
CSI0_DAT9
ALT0
CSI0_HSYNC
CSI0_MCLK
ALT0
CSI0_PIXCLK
CSI0_PIXCLK
ALT0
CSI0_VSYNC
CSI0_VSYNC
ALT0
CSI1_DATA_EN
EIM_D23
ALT6
EIM_DA10
ALT4
CSI1_D[0]
EIM_DA9
ALT4
CSI1_D[10]
EIM_EB1
ALT4
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Pin
Mode
CSI1_D[11]
EIM_EB0
ALT4
CSI1_D[12]
EIM_A17
ALT3
CSI1_D[13]
EIM_A18
ALT3
CSI1_D[14]
EIM_A19
ALT3
CSI1_D[15]
EIM_A20
ALT3
CSI1_D[16]
EIM_A21
ALT3
CSI1_D[17]
EIM_A22
ALT3
CSI1_D[18]
EIM_A23
ALT3
CSI1_D[19]
EIM_A24
ALT3
CSI1_D[1]
EIM_DA8
ALT4
CSI1_D[2]
EIM_DA7
ALT4
CSI1_D[3]
EIM_DA6
ALT4
CSI1_D[4]
EIM_DA5
ALT4
CSI1_D[5]
EIM_DA4
ALT4
CSI1_D[6]
EIM_DA3
ALT4
CSI1_D[7]
EIM_DA2
ALT4
CSI1_D[8]
EIM_DA1
ALT4
CSI1_D[9]
EIM_DA0
ALT4
CSI1_HSYNC
EIM_DA11
ALT4
EIM_EB3
ALT6
CSI1_PIXCLK
EIM_A16
ALT3
CSI1_VSYNC
EIM_D29
ALT6
EIM_DA12
ALT4
EIM_D23
ALT4
DI0_D0_CS
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Pin
Mode
DI0_D1_CS
EIM_A25
ALT6
DI0_DISP_CLK
DI0_DISP_CLK
ALT0
DI0_PIN1
EIM_D22
ALT2
DI0_PIN11
EIM_D30
ALT4
DI0_PIN12
EIM_D31
ALT4
DI0_PIN13
EIM_D28
ALT7
DI0_PIN14
EIM_D29
ALT7
DI0_PIN15
DI0_PIN15
ALT0
DI0_PIN16
EIM_D20
ALT2
DI0_PIN17
EIM_D21
ALT2
DI0_PIN2
DI0_PIN2
ALT0
DI0_PIN3
DI0_PIN3
ALT0
DI0_PIN4
DI0_PIN4
ALT0
DI0_PIN5
EIM_D16
ALT2
DI0_PIN6
EIM_D17
ALT2
DI0_PIN7
EIM_D18
ALT2
DI0_PIN8
EIM_D19
ALT2
DI1_D0_CS
EIM_D18
ALT6
EIM_DA13
ALT3
DI1_D1_CS
EIM_DA14
ALT3
DI1_DISP_CLK
EIM_A16
ALT2
DI1_PIN1
EIM_DA15
ALT3
DI1_PIN11
EIM_D26
ALT5
DI1_PIN12
EIM_A25
ALT3
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Pin
Mode
DI1_PIN13
EIM_D27
ALT5
DI1_PIN14
EIM_D23
ALT7
DI1_PIN15
EIM_D29
ALT5
EIM_DA10
ALT3
DI1_PIN16
EIM_EB3
ALT7
DI1_PIN17
EIM_LBA
ALT3
DI1_PIN2
EIM_D23
ALT5
EIM_DA11
ALT3
EIM_DA12
ALT3
EIM_EB3
ALT5
DI1_PIN4
EIM_DA15
ALT4
DI1_PIN5
EIM_CS0
ALT3
DI1_PIN6
EIM_CS1
ALT3
DI1_PIN7
EIM_OE
ALT3
DI1_PIN8
EIM_RW
ALT3
DISP0_DAT[0]
DISP0_DAT0
ALT0
DISP0_DAT[10]
DISP0_DAT10
ALT0
DISP0_DAT[11]
DISP0_DAT11
ALT0
DISP0_DAT[12]
DISP0_DAT12
ALT0
DISP0_DAT[13]
DISP0_DAT13
ALT0
DISP0_DAT[14]
DISP0_DAT14
ALT0
DISP0_DAT[15]
DISP0_DAT15
ALT0
DISP0_DAT[16]
DISP0_DAT16
ALT0
DISP0_DAT[17]
DISP0_DAT17
ALT0
DI1_PIN3
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Pin
Mode
DISP0_DAT[18]
DISP0_DAT18
ALT0
DISP0_DAT[19]
DISP0_DAT19
ALT0
DISP0_DAT[1]
DISP0_DAT1
ALT0
DISP0_DAT[20]
DISP0_DAT20
ALT0
DISP0_DAT[21]
DISP0_DAT21
ALT0
DISP0_DAT[22]
DISP0_DAT22
ALT0
DISP0_DAT[23]
DISP0_DAT23
ALT0
DISP0_DAT[2]
DISP0_DAT2
ALT0
DISP0_DAT[3]
DISP0_DAT3
ALT0
DISP0_DAT[4]
DISP0_DAT4
ALT0
DISP0_DAT[5]
DISP0_DAT5
ALT0
DISP0_DAT[6]
DISP0_DAT6
ALT0
DISP0_DAT[7]
DISP0_DAT7
ALT0
DISP0_DAT[8]
DISP0_DAT8
ALT0
DISP0_DAT[9]
DISP0_DAT9
ALT0
DISP1_DAT[0]
EIM_DA9
ALT3
DISP1_DAT[10]
EIM_EB1
ALT3
DISP1_DAT[11]
EIM_EB0
ALT3
DISP1_DAT[12]
EIM_A17
ALT2
DISP1_DAT[13]
EIM_A18
ALT2
DISP1_DAT[14]
EIM_A19
ALT2
DISP1_DAT[15]
EIM_A20
ALT2
DISP1_DAT[16]
EIM_A21
ALT2
DISP1_DAT[17]
EIM_A22
ALT2
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Pin
Mode
DISP1_DAT[18]
EIM_A23
ALT2
DISP1_DAT[19]
EIM_A24
ALT2
DISP1_DAT[1]
EIM_DA8
ALT3
DISP1_DAT[20]
EIM_D31
ALT5
DISP1_DAT[21]
EIM_D30
ALT5
DISP1_DAT[22]
EIM_D26
ALT7
DISP1_DAT[23]
EIM_D27
ALT7
DISP1_DAT[2]
EIM_DA7
ALT3
DISP1_DAT[3]
EIM_DA6
ALT3
DISP1_DAT[4]
EIM_DA5
ALT3
DISP1_DAT[5]
EIM_DA4
ALT3
DISP1_DAT[6]
EIM_DA3
ALT3
DISP1_DAT[7]
EIM_DA2
ALT3
DISP1_DAT[8]
EIM_DA1
ALT3
DISP1_DAT[9]
EIM_DA0
ALT3
DISPB0_SER_CLK
EIM_D21
ALT3
DISPB0_SER_DIN
EIM_D22
ALT3
DISPB0_SER_DIO
EIM_D28
ALT3
DISPB0_SER_RS
EIM_D29
ALT3
DISPB1_SER_CLK
EIM_D16
ALT3
DISPB1_SER_DIN
EIM_D17
ALT3
DISPB1_SER_DIO
EIM_D18
ALT3
DISPB1_SER_RS
EIM_D19
ALT3
EXT_TRIG
EIM_D28
ALT6
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
IPU
Block I/O
Mode
IPU_DIAG_BUS[0]
PATA_DATA0
ALT6
IPU_DIAG_BUS[10]
PATA_DATA10
ALT6
IPU_DIAG_BUS[11]
PATA_DATA11
ALT6
IPU_DIAG_BUS[12]
PATA_DATA12
ALT6
IPU_DIAG_BUS[13]
PATA_DATA13
ALT6
IPU_DIAG_BUS[14]
PATA_DATA14
ALT6
IPU_DIAG_BUS[15]
PATA_DATA15
ALT6
IPU_DIAG_BUS[1]
PATA_DATA1
ALT6
IPU_DIAG_BUS[2]
PATA_DATA2
ALT6
IPU_DIAG_BUS[3]
PATA_DATA3
ALT6
IPU_DIAG_BUS[4]
PATA_DATA4
ALT6
IPU_DIAG_BUS[5]
PATA_DATA5
ALT6
IPU_DIAG_BUS[6]
PATA_DATA6
ALT6
IPU_DIAG_BUS[7]
PATA_DATA7
ALT6
IPU_DIAG_BUS[8]
PATA_DATA8
ALT6
IPU_DIAG_BUS[9]
PATA_DATA9
ALT6
SER_DISP0_CS
EIM_D20
ALT3
SER_DISP1_CS
EIM_EB2
ALT3
SISG[0]
NANDF_CS2
ALT2
SISG[1]
NANDF_CS3
ALT2
SISG[2]
EIM_A24
ALT6
EIM_D26
ALT6
EIM_A23
ALT6
EIM_D27
ALT6
SISG[4]
KEY_COL4
ALT3
SISG[5]
KEY_ROW4
ALT3
SNOOP2
GPIO_17
ALT6
32K_OUT
FEC_RXD0
ALT3
GPIO_10
ALT1
KEY_ROW3
ALT5
SD1_CLK
ALT2
SISG[3]
XTALOSC32K
Pin
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
SDMA
Block I/O
Pin
Mode
DEBUG_BUS_DEVICE[0]
DISP0_DAT21
ALT5
DEBUG_BUS_DEVICE[1]
DISP0_DAT22
ALT5
DEBUG_BUS_DEVICE[2]
DISP0_DAT23
ALT5
DEBUG_BUS_DEVICE[3]
FEC_MDIO
ALT5
DEBUG_BUS_DEVICE[4]
FEC_REF_CLK
ALT5
DEBUG_BUS_ERROR
DISP0_DAT3
ALT5
DEBUG_BUS_RWB
DISP0_DAT4
ALT5
DEBUG_CORE_RUN
DISP0_DAT0
ALT5
DEBUG_CORE_STATE[0]
DI0_DISP_CLK
ALT5
DEBUG_CORE_STATE[1]
DI0_PIN15
ALT5
DEBUG_CORE_STATE[2]
DI0_PIN2
ALT5
DEBUG_CORE_STATE[3]
DI0_PIN3
ALT5
DEBUG_EVENT_CHANNEL[0]
DISP0_DAT7
ALT5
DEBUG_EVENT_CHANNEL[1]
DISP0_DAT8
ALT5
DEBUG_EVENT_CHANNEL[2]
DISP0_DAT9
ALT5
DEBUG_EVENT_CHANNEL[3]
DISP0_DAT10
ALT5
DEBUG_EVENT_CHANNEL[4]
DISP0_DAT11
ALT5
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
SDMA
SDMA
Block I/O
Pin
DEBUG_EVENT_CHANNEL[5]
DISP0_DAT12
Mode
ALT5
DEBUG_EVENT_CHANNEL_SEL DISP0_DAT1
ALT5
DEBUG_EVT_CHN_LINES[0]
DISP0_DAT13
ALT5
DEBUG_EVT_CHN_LINES[1]
DISP0_DAT14
ALT5
DEBUG_EVT_CHN_LINES[2]
DISP0_DAT15
ALT5
DEBUG_EVT_CHN_LINES[3]
DISP0_DAT16
ALT5
DEBUG_EVT_CHN_LINES[4]
DISP0_DAT17
ALT5
DEBUG_EVT_CHN_LINES[5]
DISP0_DAT18
ALT5
DEBUG_EVT_CHN_LINES[6]
DISP0_DAT19
ALT5
DEBUG_EVT_CHN_LINES[7]
DISP0_DAT20
ALT5
DEBUG_MATCHED_DMBUS
DISP0_DAT5
ALT5
DEBUG_MODE
DISP0_DAT2
ALT5
DEBUG_PC[0]
CSI0_PIXCLK
ALT5
DEBUG_PC[10]
CSI0_DAT16
ALT5
DEBUG_PC[11]
CSI0_DAT17
ALT5
DEBUG_PC[12]
CSI0_DAT18
ALT5
DEBUG_PC[13]
CSI0_DAT19
ALT5
DEBUG_PC[1]
CSI0_MCLK
ALT5
DEBUG_PC[2]
CSI0_DATA_EN
ALT5
DEBUG_PC[3]
CSI0_VSYNC
ALT5
DEBUG_PC[4]
CSI0_DAT10
ALT5
DEBUG_PC[5]
CSI0_DAT11
ALT5
DEBUG_PC[6]
CSI0_DAT12
ALT5
DEBUG_PC[7]
CSI0_DAT13
ALT5
DEBUG_PC[8]
CSI0_DAT14
ALT5
DEBUG_PC[9]
CSI0_DAT15
ALT5
DEBUG_RTBUFFER_WRITE
DISP0_DAT6
ALT5
DEBUG_YIELD
DI0_PIN4
ALT5
SDMA_EXT_EVENT[0]
DISP0_DAT16
ALT4
GPIO_17
ALT2
DISP0_DAT17
ALT4
GPIO_18
ALT2
SDMA_EXT_EVENT[1]
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
FEC
Block I/O
COL
Pin
Mode
FEC_MDIO
ALT3
KEY_ROW1
ALT6
CRS
KEY_COL3
ALT6
MDC
FEC_MDC
ALT0
KEY_ROW2
ALT4
FEC_MDIO
ALT0
KEY_COL2
ALT4
RDATA[0]
FEC_RXD0
ALT0
RDATA[1]
FEC_RXD1
ALT0
RDATA[2]
KEY_COL2
ALT6
RDATA[3]
KEY_COL0
ALT6
RX_CLK
FEC_RX_ER
ALT3
KEY_COL1
ALT6
RX_DV
FEC_CRS_DV
ALT0
RX_ER
FEC_RX_ER
ALT0
TDATA[0]
FEC_TXD0
ALT0
TDATA[1]
FEC_TXD1
ALT0
TDATA[2]
KEY_ROW2
ALT6
TDATA[3]
GPIO_19
ALT6
TX_CLK
FEC_REF_CLK
ALT0
TX_EN
FEC_TX_EN
ALT0
TX_ER
KEY_ROW0
ALT6
MDIO
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
PATA
OBSERVE_
MUX
Block I/O
Pin
Mode
BUFFER_EN
PATA_BUFFER_EN
ALT0
CS_0
PATA_CS_0
ALT0
CS_1
PATA_CS_1
ALT0
DA_0
PATA_DA_0
ALT0
DA_1
PATA_DA_1
ALT0
DA_2
PATA_DA_2
ALT0
DIOR
PATA_DIOR
ALT0
DIOW
PATA_DIOW
ALT0
DMACK
PATA_DMACK
ALT0
DMARQ
PATA_DMARQ
ALT0
INTRQ
PATA_INTRQ
ALT0
IORDY
PATA_IORDY
ALT0
PATA_DATA[0]
PATA_DATA0
ALT0
PATA_DATA[10]
PATA_DATA10
ALT0
PATA_DATA[11]
PATA_DATA11
ALT0
PATA_DATA[12]
PATA_DATA12
ALT0
PATA_DATA[13]
PATA_DATA13
ALT0
PATA_DATA[14]
PATA_DATA14
ALT0
PATA_DATA[15]
PATA_DATA15
ALT0
PATA_DATA[1]
PATA_DATA1
ALT0
PATA_DATA[2]
PATA_DATA2
ALT0
PATA_DATA[3]
PATA_DATA3
ALT0
PATA_DATA[4]
PATA_DATA4
ALT0
PATA_DATA[5]
PATA_DATA5
ALT0
PATA_DATA[6]
PATA_DATA6
ALT0
PATA_DATA[7]
PATA_DATA7
ALT0
PATA_DATA[8]
PATA_DATA8
ALT0
PATA_DATA[9]
PATA_DATA9
ALT0
PATA_RESET_B
PATA_RESET_B
ALT0
OBSRV_INT_OUT0
GPIO_3
ALT5
OBSRV_INT_OUT1
GPIO_6
ALT5
OBSRV_INT_OUT2
GPIO_2
ALT5
OBSRV_INT_OUT3
GPIO_4
ALT5
OBSRV_INT_OUT4
GPIO_5
ALT5
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
FIRI
Block I/O
RXD
ALT3
GPIO_7
ALT5
EIM_D27
ALT3
GPIO_8
ALT5
GPIO_18
ALT5
KEY_ROW3
ALT3
GPIO_6
ALT3
PATA_DMARQ
ALT5
GPIO_2
ALT3
PATA_BUFFER_EN
ALT5
GPIO_4
ALT3
PATA_INTRQ
ALT5
GPIO_0
ALT0
GPIO_19
ALT2
GPIO_5
ALT3
CLKO2
GPIO_3
ALT4
CSI0_MCLK
CSI0_MCLK
ALT2
NANDF_CS2
ALT5
DI0_EXT_CLK
EIM_DA14
ALT4
DI1_EXT_CLK
EIM_DA13
ALT4
EIM_EB2
ALT2
GPIO_5
ALT7
SD1_CMD
ALT7
GPIO_7
ALT7
SD1_DATA2
ALT7
GPIO_8
ALT7
SD1_DATA0
ALT7
KEY_ROW3
ALT6
SD1_DATA1
ALT7
PMIC_VSTBY_REQ
PMIC_STBY_REQ
No Muxing (ALT0)
REF_EN_B
GPIO_9
ALT3
SSI_EXT1_CLK
GPIO_0
ALT3
SSI_EXT2_CLK
GPIO_1
ALT3
ASRC_EXT_CLK
CCM_OUT_0
CCM
Mode
EIM_D26
TXD
CCM
Pin
CCM_OUT_1
CCM_OUT_2
CLKO
PLL1_BYP
PLL2_BYP
PLL3_BYP
PLL4_BYP
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPT
KPP
Block I/O
Pin
Mode
IND_CAPIN1
SD1_DATA0
ALT3
IND_CAPIN2
SD1_DATA1
ALT3
IND_CLKIN
SD1_CLK
ALT3
DO_CMPOUT1
SD1_CMD
ALT3
DO_CMPOUT2
SD1_DATA2
ALT2
DO_CMPOUT3
SD1_DATA3
ALT2
COL[0]
KEY_COL0
ALT0
COL[1]
KEY_COL1
ALT0
COL[2]
KEY_COL2
ALT0
COL[3]
KEY_COL3
ALT0
COL[4]
KEY_COL4
ALT0
COL[5]
CSI0_DAT4
ALT2
GPIO_0
ALT2
GPIO_19
ALT0
SD2_CLK
ALT2
CSI0_DAT6
ALT2
GPIO_9
ALT2
SD2_DATA3
ALT2
CSI0_DAT8
ALT2
GPIO_4
ALT2
SD2_DATA1
ALT2
ROW[0]
KEY_ROW0
ALT0
ROW[1]
KEY_ROW1
ALT0
ROW[2]
KEY_ROW2
ALT0
ROW[3]
KEY_ROW3
ALT0
ROW[4]
KEY_ROW4
ALT0
ROW[5]
CSI0_DAT5
ALT2
GPIO_1
ALT2
SD2_CMD
ALT2
CSI0_DAT7
ALT2
GPIO_2
ALT2
SD2_DATA2
ALT2
CSI0_DAT9
ALT2
GPIO_5
ALT2
SD2_DATA0
ALT2
COL[6]
COL[7]
ROW[6]
ROW[7]
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
I2C-1
Block I/O
SCL
ALT5
EIM_D21
ALT5
CSI0_DAT8
ALT5
EIM_D28
ALT5
EIM_EB2
ALT5
KEY_COL3
ALT4
EIM_D16
ALT5
KEY_ROW3
ALT4
EIM_D17
ALT5
GPIO_3
ALT2
GPIO_5
ALT6
SDA
EIM_D18
ALT5
SDA
GPIO_16
ALT6
GPIO_6
ALT2
GPIO_16
ALT5
KEY_COL3
ALT3
GPIO_17
ALT5
GPIO_19
ALT3
PLOCK
GPIO_7
ALT6
SRCLK
GPIO_8
ALT6
SCL
SDA
I2C-3
SPDIF
Mode
CSI0_DAT9
SDA
I2C-2
Pin
SCL
IN1
OUT1
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-1
GPIO-1
Block I/O
Pin
Mode
GPIO[0]
GPIO_0
ALT1
GPIO[10]
SD2_CLK
ALT1
GPIO[11]
SD2_CMD
ALT1
GPIO[12]
SD2_DATA3
ALT1
GPIO[13]
SD2_DATA2
ALT1
GPIO[14]
SD2_DATA1
ALT1
GPIO[15]
SD2_DATA0
ALT1
GPIO[16]
SD1_DATA0
ALT1
GPIO[17]
SD1_DATA1
ALT1
GPIO[18]
SD1_CMD
ALT1
GPIO[19]
SD1_DATA2
ALT1
GPIO[1]
GPIO_1
ALT1
GPIO[20]
SD1_CLK
ALT1
GPIO[21]
SD1_DATA3
ALT1
GPIO[22]
FEC_MDIO
ALT1
GPIO[23]
FEC_REF_CLK
ALT1
GPIO[24]
FEC_RX_ER
ALT1
GPIO[25]
FEC_CRS_DV
ALT1
GPIO[26]
FEC_RXD1
ALT1
GPIO[27]
FEC_RXD0
ALT1
GPIO[28]
FEC_TX_EN
ALT1
GPIO[29]
FEC_TXD1
ALT1
GPIO[2]
GPIO_2
ALT1
GPIO[30]
FEC_TXD0
ALT1
GPIO[31]
FEC_MDC
ALT1
GPIO[3]
GPIO_3
ALT1
GPIO[4]
GPIO_4
ALT1
GPIO[5]
GPIO_5
ALT1
GPIO[6]
GPIO_6
ALT1
GPIO[7]
GPIO_7
ALT1
GPIO[8]
GPIO_8
ALT1
GPIO[9]
GPIO_9
ALT1
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-2
GPIO-2
Block I/O
Pin
Mode
GPIO[0]
PATA_DATA0
ALT1
GPIO[10]
PATA_DATA10
ALT1
GPIO[11]
PATA_DATA11
ALT1
GPIO[12]
PATA_DATA12
ALT1
GPIO[13]
PATA_DATA13
ALT1
GPIO[14]
PATA_DATA14
ALT1
GPIO[15]
PATA_DATA15
ALT1
GPIO[16]
EIM_A22
ALT1
GPIO[17]
EIM_A21
ALT1
GPIO[18]
EIM_A20
ALT1
GPIO[19]
EIM_A19
ALT1
GPIO[1]
PATA_DATA1
ALT1
GPIO[20]
EIM_A18
ALT1
GPIO[21]
EIM_A17
ALT1
GPIO[22]
EIM_A16
ALT1
GPIO[23]
EIM_CS0
ALT1
GPIO[24]
EIM_CS1
ALT1
GPIO[25]
EIM_OE
ALT1
GPIO[26]
EIM_RW
ALT1
GPIO[27]
EIM_LBA
ALT1
GPIO[28]
EIM_EB0
ALT1
GPIO[29]
EIM_EB1
ALT1
GPIO[2]
PATA_DATA2
ALT1
GPIO[30]
EIM_EB2
ALT1
GPIO[31]
EIM_EB3
ALT1
GPIO[3]
PATA_DATA3
ALT1
GPIO[4]
PATA_DATA4
ALT1
GPIO[5]
PATA_DATA5
ALT1
GPIO[6]
PATA_DATA6
ALT1
GPIO[7]
PATA_DATA7
ALT1
GPIO[8]
PATA_DATA8
ALT1
GPIO[9]
PATA_DATA9
ALT1
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-3
GPIO-3
Block I/O
Pin
Mode
GPIO[0]
EIM_DA0
ALT1
GPIO[10]
EIM_DA10
ALT1
GPIO[11]
EIM_DA11
ALT1
GPIO[12]
EIM_DA12
ALT1
GPIO[13]
EIM_DA13
ALT1
GPIO[14]
EIM_DA14
ALT1
GPIO[15]
EIM_DA15
ALT1
GPIO[16]
EIM_D16
ALT1
GPIO[17]
EIM_D17
ALT1
GPIO[18]
EIM_D18
ALT1
GPIO[19]
EIM_D19
ALT1
GPIO[1]
EIM_DA1
ALT1
GPIO[20]
EIM_D20
ALT1
GPIO[21]
EIM_D21
ALT1
GPIO[22]
EIM_D22
ALT1
GPIO[23]
EIM_D23
ALT1
GPIO[24]
EIM_D24
ALT1
GPIO[25]
EIM_D25
ALT1
GPIO[26]
EIM_D26
ALT1
GPIO[27]
EIM_D27
ALT1
GPIO[28]
EIM_D28
ALT1
GPIO[29]
EIM_D29
ALT1
GPIO[2]
EIM_DA2
ALT1
GPIO[30]
EIM_D30
ALT1
GPIO[31]
EIM_D31
ALT1
GPIO[3]
EIM_DA3
ALT1
GPIO[4]
EIM_DA4
ALT1
GPIO[5]
EIM_DA5
ALT1
GPIO[6]
EIM_DA6
ALT1
GPIO[7]
EIM_DA7
ALT1
GPIO[8]
EIM_DA8
ALT1
GPIO[9]
EIM_DA9
ALT1
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-4
GPIO-4
Block I/O
Pin
Mode
GPIO[0]
GPIO_10
ALT0
GPIO[10]
KEY_COL2
ALT1
GPIO[11]
KEY_ROW2
ALT1
GPIO[12]
KEY_COL3
ALT1
GPIO[13]
KEY_ROW3
ALT1
GPIO[14]
KEY_COL4
ALT1
GPIO[15]
KEY_ROW4
ALT1
GPIO[16]
DI0_DISP_CLK
ALT1
GPIO[17]
DI0_PIN15
ALT1
GPIO[18]
DI0_PIN2
ALT1
GPIO[19]
DI0_PIN3
ALT1
GPIO[1]
GPIO_11
No Muxing (ALT0)
GPIO[20]
DI0_PIN4
ALT1
GPIO[21]
DISP0_DAT0
ALT1
GPIO[22]
DISP0_DAT1
ALT1
GPIO[23]
DISP0_DAT2
ALT1
GPIO[24]
DISP0_DAT3
ALT1
GPIO[25]
DISP0_DAT4
ALT1
GPIO[26]
DISP0_DAT5
ALT1
GPIO[27]
DISP0_DAT6
ALT1
GPIO[28]
DISP0_DAT7
ALT1
GPIO[29]
DISP0_DAT8
ALT1
GPIO[2]
GPIO_12
No Muxing (ALT0)
GPIO[30]
DISP0_DAT9
ALT1
GPIO[31]
DISP0_DAT10
ALT1
GPIO[3]
GPIO_13
No Muxing (ALT0)
GPIO[4]
GPIO_14
No Muxing (ALT0)
GPIO[5]
GPIO_19
ALT1
GPIO[6]
KEY_COL0
ALT1
GPIO[7]
KEY_ROW0
ALT1
GPIO[8]
KEY_COL1
ALT1
GPIO[9]
KEY_ROW1
ALT1
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-5
GPIO-5
GPIO-6
Block I/O
Pin
Mode
GPIO[0]
EIM_WAIT
ALT1
GPIO[10]
DISP0_DAT16
ALT1
GPIO[11]
DISP0_DAT17
ALT1
GPIO[12]
DISP0_DAT18
ALT1
GPIO[13]
DISP0_DAT19
ALT1
GPIO[14]
DISP0_DAT20
ALT1
GPIO[15]
DISP0_DAT21
ALT1
GPIO[16]
DISP0_DAT22
ALT1
GPIO[17]
DISP0_DAT23
ALT1
GPIO[18]
CSI0_PIXCLK
ALT1
GPIO[19]
CSI0_MCLK
ALT1
GPIO[20]
CSI0_DATA_EN
ALT1
GPIO[21]
CSI0_VSYNC
ALT1
GPIO[22]
CSI0_DAT4
ALT1
GPIO[23]
CSI0_DAT5
ALT1
GPIO[24]
CSI0_DAT6
ALT1
GPIO[25]
CSI0_DAT7
ALT1
GPIO[26]
CSI0_DAT8
ALT1
GPIO[27]
CSI0_DAT9
ALT1
GPIO[28]
CSI0_DAT10
ALT1
GPIO[29]
CSI0_DAT11
ALT1
GPIO[2]
EIM_A25
ALT1
GPIO[30]
CSI0_DAT12
ALT1
GPIO[31]
CSI0_DAT13
ALT1
GPIO[4]
EIM_A24
ALT1
GPIO[5]
DISP0_DAT11
ALT1
GPIO[6]
DISP0_DAT12
ALT1
GPIO[7]
DISP0_DAT13
ALT1
GPIO[8]
DISP0_DAT14
ALT1
GPIO[9]
DISP0_DAT15
ALT1
GPIO[0]
CSI0_DAT14
ALT1
GPIO[10]
NANDF_RB0
ALT1
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-6
Block I/O
Pin
Mode
GPIO[11]
NANDF_CS0
ALT1
GPIO[12]
NANDF_WE_B
ALT1
GPIO[13]
NANDF_RE_B
ALT1
GPIO[14]
NANDF_CS1
ALT1
GPIO[15]
NANDF_CS2
ALT1
GPIO[16]
NANDF_CS3
ALT1
GPIO[17]
PATA_DIOW
ALT1
GPIO[18]
PATA_DMACK
ALT1
GPIO[1]
CSI0_DAT15
ALT1
GPIO[2]
CSI0_DAT16
ALT1
GPIO[3]
CSI0_DAT17
ALT1
GPIO[4]
CSI0_DAT18
ALT1
GPIO[5]
CSI0_DAT19
ALT1
GPIO[6]
EIM_A23
ALT1
GPIO[7]
NANDF_CLE
ALT1
GPIO[8]
NANDF_ALE
ALT1
GPIO[9]
NANDF_WP_B
ALT1
GPI[22]
LVDS1_TX3_P
ALT0
GPI[23]
LVDS1_TX3_N
No Muxing (ALT0)
GPI[24]
LVDS1_TX2_P
ALT0
GPI[25]
LVDS1_TX2_N
No Muxing (ALT0)
GPI[26]
LVDS1_CLK_P
ALT0
GPI[27]
LVDS1_CLK_N
No Muxing (ALT0)
GPI[28]
LVDS1_TX1_P
ALT0
GPI[29]
LVDS1_TX1_N
No Muxing (ALT0)
GPI[30]
LVDS1_TX0_P
ALT0
GPI[31]
LVDS1_TX0_N
No Muxing (ALT0)
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPIO-7
SJC
Block I/O
Pin
Mode
GPIO[0]
PATA_DMARQ
ALT1
GPIO[10]
PATA_CS_1
ALT1
GPIO[11]
GPIO_16
ALT1
GPIO[12]
GPIO_17
ALT1
GPIO[13]
GPIO_18
ALT1
GPIO[1]
PATA_BUFFER_EN
ALT1
GPIO[2]
PATA_INTRQ
ALT1
GPIO[3]
PATA_DIOR
ALT1
GPIO[4]
PATA_RESET_B
ALT1
GPIO[5]
PATA_IORDY
ALT1
GPIO[6]
PATA_DA_0
ALT1
GPIO[7]
PATA_DA_1
ALT1
GPIO[8]
PATA_DA_2
ALT1
GPIO[9]
PATA_CS_0
ALT1
GPI[22]
LVDS0_TX3_P
ALT0
GPI[23]
LVDS0_TX3_N
No Muxing (ALT0)
GPI[24]
LVDS0_CLK_P
ALT0
GPI[25]
LVDS0_CLK_N
No Muxing (ALT0)
GPI[26]
LVDS0_TX2_P
ALT0
GPI[27]
LVDS0_TX2_N
No Muxing (ALT0)
GPI[28]
LVDS0_TX1_P
ALT0
GPI[29]
LVDS0_TX1_N
No Muxing (ALT0)
GPI[30]
LVDS0_TX0_P
ALT0
GPI[31]
LVDS0_TX0_N
No Muxing (ALT0)
DE_B
GPIO_16
ALT7
DONE
SD2_DATA3
ALT7
FAIL
SD2_DATA2
ALT7
JTAG_ACT
GPIO_17
ALT7
MOD
JTAG_MOD
No Muxing (ALT0)
TCK
JTAG_TCK
No Muxing (ALT0)
TDI
JTAG_TDI
No Muxing (ALT0)
TDO
JTAG_TDO
No Muxing (ALT0)
TMS
JTAG_TMS
No Muxing (ALT0)
TRSTB
JTAG_TRSTB
No Muxing (ALT0)
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
CAMP-1
Block I/O
CKIH
CSPI
CSPI
No Muxing (ALT0)
CKIH2
No Muxing (ALT0)
FAIL_STATE
GPIO_9
ALT7
RANDOM
SD2_CMD
ALT7
RANDOM_V
SD2_CLK
ALT7
SEC_STATE
GPIO_4
ALT7
MISO
DISP0_DAT2
ALT2
EIM_D22
ALT4
SD1_DATA0
ALT5
SD2_DATA0
ALT5
MOSI
DISP0_DAT1
ALT2
MOSI
EIM_D28
ALT4
SD1_CMD
ALT5
SD2_CMD
ALT5
RDY
DISP0_DAT7
ALT2
SCLK
DISP0_DAT0
ALT2
EIM_D21
ALT4
SD1_CLK
ALT5
SD2_CLK
ALT5
DISP0_DAT3
ALT2
EIM_D20
ALT4
EIM_D29
ALT4
SD1_DATA1
ALT5
SD2_DATA1
ALT5
DISP0_DAT4
ALT2
EIM_A25
ALT4
SD1_DATA2
ALT5
SD2_DATA2
ALT5
DISP0_DAT5
ALT2
EIM_D24
ALT4
SD1_DATA3
ALT5
SD2_DATA3
ALT5
DISP0_DAT6
ALT2
EIM_D25
ALT4
KEY_COL0
ALT7
SS0
SS1
SS2
SS3
SRC
Mode
CKIH1
CAMP-2
SCC
Pin
ANY_PU_RST
Table continues on the next page...
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361
Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
SRC
Block I/O
Pin
Mode
BOOT_MODE[0]
BOOT_MODE0
No Muxing (ALT0)
BOOT_MODE[1]
BOOT_MODE1
No Muxing (ALT0)
BT_CFG1[0]
EIM_LBA
ALT7
BT_CFG1[1]
EIM_A16
ALT7
BT_CFG1[2]
EIM_A17
ALT7
BT_CFG1[3]
EIM_A18
ALT7
BT_CFG1[4]
EIM_A19
ALT7
BT_CFG1[5]
EIM_A20
ALT7
BT_CFG1[6]
EIM_A21
ALT7
BT_CFG1[7]
EIM_A22
ALT7
BT_CFG2[2]
EIM_DA3
ALT7
BT_CFG2[3]
EIM_DA2
ALT7
BT_CFG2[4]
EIM_DA1
ALT7
BT_CFG2[5]
EIM_DA0
ALT7
BT_CFG2[6]
EIM_EB1
ALT7
BT_CFG2[7]
EIM_EB0
ALT7
BT_CFG3[1]
EIM_DA10
ALT7
BT_CFG3[2]
EIM_DA9
ALT7
BT_CFG3[3]
EIM_DA8
ALT7
BT_CFG3[4]
EIM_DA7
ALT7
BT_CFG3[5]
EIM_DA6
ALT7
BT_CFG3[6]
EIM_DA5
ALT7
BT_CFG3[7]
EIM_DA4
ALT7
INT_BOOT
GPIO_19
ALT7
POR_B
POR_B
No Muxing (ALT0)
RESET_B
RESET_IN_B
No Muxing (ALT0)
SYSTEM_RST
GPIO_18
ALT7
TESTER_ACK
GPIO_1
ALT7
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
RTC
TPIU
Block I/O
Pin
Mode
CE_RTC_ALARM1_TRIG
FEC_MDC
ALT4
CE_RTC_ALARM2_TRIG
GPIO_18
ALT4
CE_RTC_EXT_TRIG1
GPIO_16
ALT4
CE_RTC_EXT_TRIG2
GPIO_19
ALT4
CE_RTC_FSV_TRIG
GPIO_17
ALT4
CE_RTC_PRSC_CLK
FEC_TXD1
ALT4
CE_RTC_PS1
FEC_RXD1
ALT4
CE_RTC_PS2
FEC_MDIO
ALT4
CE_RTC_PS3
FEC_RX_ER
ALT4
TRACE[0]
CSI0_VSYNC
ALT7
TRACE[10]
CSI0_DAT13
ALT7
TRACE[11]
CSI0_DAT14
ALT7
TRACE[12]
CSI0_DAT15
ALT7
TRACE[13]
CSI0_DAT16
ALT7
TRACE[14]
CSI0_DAT17
ALT7
TRACE[15]
CSI0_DAT18
ALT7
TRACE[1]
CSI0_DAT4
ALT7
TRACE[2]
CSI0_DAT5
ALT7
TRACE[3]
CSI0_DAT6
ALT7
TRACE[4]
CSI0_DAT7
ALT7
TRACE[5]
CSI0_DAT8
ALT7
TRACE[6]
CSI0_DAT9
ALT7
TRACE[7]
CSI0_DAT10
ALT7
TRACE[8]
CSI0_DAT11
ALT7
TRACE[9]
CSI0_DAT12
ALT7
TRCLK
CSI0_DATA_EN
ALT7
TRCTL
CSI0_MCLK
ALT7
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
GPU3D
FLEXCAN-1
Block I/O
PATA_DATA0
ALT5
GPU_DEBUG_OUT[10]
PATA_DATA10
ALT5
GPU_DEBUG_OUT[11]
PATA_DATA11
ALT5
GPU_DEBUG_OUT[12]
PATA_DATA12
ALT5
GPU_DEBUG_OUT[13]
PATA_DATA13
ALT5
GPU_DEBUG_OUT[14]
PATA_DATA14
ALT5
GPU_DEBUG_OUT[15]
PATA_DATA15
ALT5
GPU_DEBUG_OUT[1]
PATA_DATA1
ALT5
GPU_DEBUG_OUT[2]
PATA_DATA2
ALT5
GPU_DEBUG_OUT[3]
PATA_DATA3
ALT5
GPU_DEBUG_OUT[4]
PATA_DATA4
ALT5
GPU_DEBUG_OUT[5]
PATA_DATA5
ALT5
GPU_DEBUG_OUT[6]
PATA_DATA6
ALT5
GPU_DEBUG_OUT[7]
PATA_DATA7
ALT5
GPU_DEBUG_OUT[8]
PATA_DATA8
ALT5
GPU_DEBUG_OUT[9]
PATA_DATA9
ALT5
RXCAN
GPIO_8
ALT3
RXCAN
KEY_ROW2
ALT2
PATA_DIOR
ALT4
GPIO_7
ALT3
KEY_COL2
ALT2
PATA_INTRQ
ALT4
KEY_ROW4
ALT2
PATA_IORDY
ALT4
KEY_COL4
ALT2
PATA_RESET_B
ALT4
DISP0_DAT8
ALT2
GPIO_9
ALT4
SD1_DATA3
ALT3
DISP0_DAT9
ALT2
GPIO_1
ALT4
SD1_DATA2
ALT3
GPIO_18
ALT3
PATA_DA_0
ALT4
RXCAN
TXCAN
PWM-1
PWMO
PWM-2
OWIRE
Mode
GPU_DEBUG_OUT[0]
TXCAN
FLEXCAN-2
Pin
LINE
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
LDB1
EPIT-1
Block I/O
Mode
LVDS0_CLK
LVDS0_CLK_P
ALT1
LVDS0_TX0
LVDS0_TX0_P
ALT1
LVDS0_TX1
LVDS0_TX1_P
ALT1
LVDS0_TX2
LVDS0_TX2_P
ALT1
LVDS0_TX3
LVDS0_TX3_P
ALT1
LVDS1_CLK
LVDS1_CLK_P
ALT1
LVDS1_TX0
LVDS1_TX0_P
ALT1
LVDS1_TX1
LVDS1_TX1_P
ALT1
LVDS1_TX2
LVDS1_TX2_P
ALT1
LVDS1_TX3
LVDS1_TX3_P
ALT1
EPITO
EIM_D19
ALT5
GPIO_0
ALT4
GPIO_7
ALT2
EIM_D20
ALT5
GPIO_8
ALT2
CSU_ALARM_AUT[0]
GPIO_2
ALT4
CSU_ALARM_AUT[1]
GPIO_4
ALT4
CSU_ALARM_AUT[2]
GPIO_5
ALT4
CSU_INT_DEB
GPIO_6
ALT4
TD
GPIO_0
ALT7
EPIT-2
CSU
Pin
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
USBPHY-1
Block I/O
Pin
Mode
AVALID
DI0_DISP_CLK
ALT7
BISTOK
EIM_A25
ALT7
BVALID
DI0_PIN15
ALT7
DATAOUT[0]
PATA_RESET_B
ALT7
DATAOUT[1]
PATA_IORDY
ALT7
DATAOUT[2]
PATA_DA_0
ALT7
DATAOUT[3]
PATA_DA_1
ALT7
DATAOUT[4]
PATA_DA_2
ALT7
DATAOUT[5]
PATA_CS_0
ALT7
DATAOUT[6]
PATA_CS_1
ALT7
DATAOUT[7]
PATA_DATA0
ALT7
ENDSESSION
DI0_PIN2
ALT7
HOSTDISCONNECT
DI0_PIN4
ALT7
IDDIG
DI0_PIN3
ALT7
LINESTATE[0]
KEY_ROW3
ALT7
LINESTATE[1]
KEY_COL4
ALT7
RXACTIVE
KEY_COL2
ALT7
RXERROR
KEY_ROW2
ALT7
RXVALID
KEY_ROW1
ALT7
SIECLOCK
KEY_COL3
ALT7
TXREADY
KEY_COL1
ALT7
VBUSVALID
KEY_ROW4
ALT7
VSTATUS[0]
NANDF_CLE
ALT7
VSTATUS[1]
NANDF_ALE
ALT7
VSTATUS[2]
NANDF_WP_B
ALT7
VSTATUS[3]
NANDF_RB0
ALT7
VSTATUS[4]
NANDF_CS0
ALT7
VSTATUS[5]
NANDF_CS1
ALT7
VSTATUS[6]
NANDF_CS2
ALT7
VSTATUS[7]
NANDF_CS3
ALT7
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
USBPHY-2
Block I/O
Pin
Mode
AVALID
DISP0_DAT8
ALT7
BISTOK
CSI0_DAT19
ALT7
BVALID
EIM_A24
ALT7
DATAOUT[0]
FEC_TXD0
ALT7
DATAOUT[1]
FEC_MDC
ALT7
DATAOUT[2]
PATA_DIOW
ALT7
DATAOUT[3]
PATA_DMACK
ALT7
DATAOUT[4]
PATA_DMARQ
ALT7
DATAOUT[5]
PATA_BUFFER_EN
ALT7
DATAOUT[6]
PATA_INTRQ
ALT7
DATAOUT[7]
PATA_DIOR
ALT7
ENDSESSION
EIM_A23
ALT7
HOSTDISCONNECT
EIM_RW
ALT7
IDDIG
EIM_OE
ALT7
LINESTATE[0]
DISP0_DAT5
ALT7
LINESTATE[1]
DISP0_DAT6
ALT7
RXACTIVE
DISP0_DAT2
ALT7
RXERROR
DISP0_DAT3
ALT7
RXVALID
DISP0_DAT1
ALT7
SIECLOCK
DISP0_DAT4
ALT7
TXREADY
DISP0_DAT0
ALT7
VBUSVALID
DISP0_DAT7
ALT7
VSTATUS[0]
DISP0_DAT9
ALT7
VSTATUS[1]
DISP0_DAT10
ALT7
VSTATUS[2]
DISP0_DAT11
ALT7
VSTATUS[3]
DISP0_DAT12
ALT7
VSTATUS[4]
DISP0_DAT13
ALT7
VSTATUS[5]
DISP0_DAT14
ALT7
VSTATUS[6]
DISP0_DAT15
ALT7
VSTATUS[7]
DISP0_DAT16
ALT7
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
AUDMUX
Block I/O
Mode
AUD3_RXC
CSI0_DAT10
ALT4
AUD3_RXD
CSI0_DAT7
ALT5
AUD3_RXFS
CSI0_DAT11
ALT4
AUD3_TXC
CSI0_DAT4
ALT5
AUD3_TXD
CSI0_DAT5
ALT5
AUD3_TXFS
CSI0_DAT6
ALT5
AUD4_RXC
DISP0_DAT19
ALT4
SD2_CMD
ALT3
DISP0_DAT23
ALT3
SD2_DATA0
ALT3
DISP0_DAT18
ALT4
SD2_CLK
ALT3
DISP0_DAT20
ALT3
SD2_DATA3
ALT3
DISP0_DAT21
ALT3
SD2_DATA2
ALT3
DISP0_DAT22
ALT3
SD2_DATA1
ALT3
DISP0_DAT14
ALT3
EIM_D25
ALT5
DISP0_DAT19
ALT3
KEY_ROW1
ALT2
AUD5_RXFS
DISP0_DAT13
ALT3
AUD5_RXFS
EIM_D24
ALT5
AUD5_TXC
DISP0_DAT16
ALT3
KEY_COL0
ALT2
DISP0_DAT17
ALT3
KEY_ROW0
ALT2
DISP0_DAT18
ALT3
KEY_COL1
ALT2
AUD6_RXD
DI0_PIN4
ALT2
AUD6_TXC
DI0_PIN15
ALT2
AUD6_TXD
DI0_PIN2
ALT2
AUD6_TXFS
DI0_PIN3
ALT2
AUD4_RXD
AUD4_RXFS
AUD4_TXC
AUD4_TXD
AUD4_TXFS
AUD5_RXC
AUD5_RXD
AUDMUX
Pin
AUD5_TXD
AUD5_TXFS
Table continues on the next page...
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
ESDHCV2-1
ESDHCV2-2
Block I/O
Pin
Mode
CD
GPIO_1
ALT6
CLK
SD1_CLK
ALT0
CMD
SD1_CMD
ALT0
DAT0
SD1_DATA0
ALT0
DAT1
SD1_DATA1
ALT0
DAT2
SD1_DATA2
ALT0
DAT3
SD1_DATA3
ALT0
DAT4
PATA_DATA8
ALT2
DAT5
PATA_DATA9
ALT2
DAT6
PATA_DATA10
ALT2
DAT7
PATA_DATA11
ALT2
LCTL
GPIO_18
ALT6
WP
DI0_PIN4
ALT3
WP
GPIO_9
ALT6
CD
GPIO_4
ALT6
CLK
SD2_CLK
ALT0
CMD
SD2_CMD
ALT0
DAT0
SD2_DATA0
ALT0
DAT1
SD2_DATA1
ALT0
DAT2
SD2_DATA2
ALT0
DAT3
SD2_DATA3
ALT0
DAT4
PATA_DATA12
ALT2
DAT5
PATA_DATA13
ALT2
DAT6
PATA_DATA14
ALT2
DAT7
PATA_DATA15
ALT2
LCTL
GPIO_6
ALT6
WP
GPIO_2
ALT6
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
ESDHCV3-3
ESDHCV2-4
SATA_PHY
USB
Block I/O
Pin
Mode
CLK
PATA_IORDY
ALT2
CMD
PATA_RESET_B
ALT2
DAT0
PATA_DATA8
ALT4
DAT1
PATA_DATA9
ALT4
DAT2
PATA_DATA10
ALT4
DAT3
PATA_DATA11
ALT4
DAT4
PATA_DATA0
ALT4
DAT5
PATA_DATA1
ALT4
DAT6
PATA_DATA2
ALT4
DAT7
PATA_DATA3
ALT4
RST
PATA_DA_0
ALT2
CLK
PATA_DA_2
ALT2
CMD
PATA_DA_1
ALT2
DAT0
PATA_DATA12
ALT4
DAT1
PATA_DATA13
ALT4
DAT2
PATA_DATA14
ALT4
DAT3
PATA_DATA15
ALT4
DAT4
PATA_DATA4
ALT4
DAT5
PATA_DATA5
ALT4
DAT6
PATA_DATA6
ALT4
DAT7
PATA_DATA7
ALT4
DTB[0]
SD1_CLK
ALT7
DTB[1]
SD1_DATA3
ALT7
TCK
DISP0_DAT22
ALT7
TDI
DISP0_DAT20
ALT7
TDO
DISP0_DAT21
ALT7
TMS
DISP0_DAT23
ALT7
H2_DM
KEY_ROW3
ALT2
H2_DP
KEY_COL3
ALT2
USBH1_OC
EIM_D30
ALT6
GPIO_3
ALT6
EIM_D31
ALT6
GPIO_0
ALT6
DISP0_DAT12
ALT2
USBH1_PWR
USBH2_CLK
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Table 4-3. Muxing Options sorted by IPs (continued)
Block Instance
USB
Block I/O
Mode
USBH2_DATA[0]
DISP0_DAT0
ALT3
USBH2_DATA[1]
DISP0_DAT1
ALT3
USBH2_DATA[2]
DISP0_DAT2
ALT3
USBH2_DATA[3]
DISP0_DAT3
ALT3
USBH2_DATA[4]
DISP0_DAT4
ALT3
USBH2_DATA[5]
DISP0_DAT5
ALT3
USBH2_DATA[6]
DISP0_DAT6
ALT3
USBH2_DATA[7]
DISP0_DAT7
ALT3
USBH2_DIR
DI0_DISP_CLK
ALT2
USBH2_NXT
DISP0_DAT11
ALT2
USBH2_OC
EIM_D19
ALT7
EIM_D30
ALT7
EIM_D20
ALT7
EIM_D31
ALT7
USBH2_STP
DISP0_DAT10
ALT2
USBH3_CLK
CSI0_DAT6
ALT4
USBH3_DATA[0]
CSI0_DAT12
ALT4
USBH3_DATA[1]
CSI0_DAT13
ALT4
USBH3_DATA[2]
CSI0_DAT14
ALT4
USBH3_DATA[3]
CSI0_DAT15
ALT4
USBH3_DATA[4]
CSI0_DAT16
ALT4
USBH3_DATA[5]
CSI0_DAT17
ALT4
USBH3_DATA[6]
CSI0_DAT18
ALT4
USBH3_DATA[7]
CSI0_DAT19
ALT4
USBH3_DIR
CSI0_DAT7
ALT4
USBH3_NXT
CSI0_DAT5
ALT4
USBH3_OC
CSI0_DAT8
ALT4
USBH3_PWR
CSI0_DAT9
ALT4
USBH3_STP
CSI0_DAT4
ALT4
USBOTG_OC
EIM_D21
ALT6
KEY_COL4
ALT5
EIM_D22
ALT6
KEY_ROW4
ALT5
USBH2_PWR
USB
Pin
USBOTG_PWR
1. If the LVDS Display Bridge (LDB) block is disabled, then each LVDS output pin pair is available to be used as a pair of
general purpose CMOS inputs (controlled by the GPIO blocks).
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4.2.2 Daisy Chain Control
To increase the flexibility of routing signals from package pins to certain block I/Os, the
IOMUXC provides multiplexers that can be programmed to receive inputs from a number
of different package pins. This is called daisy chaining. This selection is controlled by
daisy chain control registers. These are described below.
Table 4-4 shows the daisy chain control registers sorted by package pin.
Table 4-4. Daisy Chain Multiplexer Control Registers (by pin)
Pin Name
Daisy Chain Control Registers
GPIO_19
IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
KEY_COL0
IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT
IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
KEY_ROW0
IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
KEY_COL1
IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT
IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT
IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
KEY_ROW1
IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT
IOMUXC_FEC_FEC_COL_SELECT_INPUT
IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
KEY_COL2
IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT
IOMUXC_FEC_FEC_MDI_SELECT_INPUT
KEY_ROW2
IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT
KEY_COL3
IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT
IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT
KEY_ROW3
IOMUXC_CCM_IPP_ASRC_EXT_SELECT_INPUT
IOMUXC_CCM_PLL4_BYPASS_CLK_SELECT_INPUT
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
KEY_COL4
IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
KEY_ROW4
IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT
IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
NVCC_KEYPAD
DI0_DISP_CLK
DI0_PIN15
DI0_PIN2
DI0_PIN3
DI0_PIN4
IOMUXC_ESDHC1_IPP_WP_ON_SELECT_INPUT
DISP0_DAT0
IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
DISP0_DAT1
IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
DISP0_DAT2
IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
DISP0_DAT3
IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT
DISP0_DAT4
IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
DISP0_DAT5
IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
DISP0_DAT6
IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT
DISP0_DAT7
DISP0_DAT8
DISP0_DAT9
DISP0_DAT10
DISP0_DAT11
DISP0_DAT12
DISP0_DAT13
IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT
DISP0_DAT14
IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT
DISP0_DAT15
IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT
DISP0_DAT16
IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_SDMA_EVENTS_14_SELECT_INPUT
DISP0_DAT17
IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT
IOMUXC_SDMA_EVENTS_15_SELECT_INPUT
DISP0_DAT18
IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT
IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
DISP0_DAT19
IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT
IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT
IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT
DISP0_DAT20
IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT
DISP0_DAT21
IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT
DISP0_DAT22
IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT
DISP0_DAT23
IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT
CSI0_PIXCLK
CSI0_MCLK
CSI0_DATA_EN
CSI0_VSYNC
CSI0_DAT4
IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
CSI0_DAT5
IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
CSI0_DAT6
IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
CSI0_DAT7
IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
CSI0_DAT8
IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT
IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
CSI0_DAT9
IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
CSI0_DAT10
IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT
IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
CSI0_DAT11
IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT
IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
CSI0_DAT12
IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
CSI0_DAT13
IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT
CSI0_DAT14
IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
CSI0_DAT15
IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT
CSI0_DAT16
IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT
CSI0_DAT17
IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT
CSI0_DAT18
IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
CSI0_DAT19
IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT
NVCC_CSI__0
JTAG_TMS
JTAG_MOD
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TDO
EIM_A25
IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
EIM_EB2
IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT
EIM_D16
IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
EIM_D17
IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT
IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT
IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT
NVCC_EIM__0
EIM_D18
IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT
IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT
EIM_D19
IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT
IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT
EIM_D20
IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT
IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
EIM_D21
IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT
EIM_D22
IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
EIM_D23
Daisy Chain Control Registers
IOMUXC_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
EIM_EB3
IOMUXC_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
EIM_D24
IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT
IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
EIM_D25
IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT
IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
EIM_D26
IOMUXC_FIRI_IPP_IND_RXD_SELECT_INPUT
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
EIM_D27
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
EIM_D28
IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT
IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT
IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
EIM_D29
IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT
IOMUXC_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT
IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
EIM_D30
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT
EIM_D31
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
NVCC_EIM__1
EIM_A24
EIM_A23
EIM_A22
EIM_A21
EIM_A20
EIM_A19
EIM_A18
EIM_A17
EIM_A16
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
EIM_CS0
IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT
EIM_CS1
IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT
EIM_OE
IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT
EIM_RW
IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT
EIM_LBA
IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT
NVCC_EIM__4
EIM_EB0
IOMUXC_GPC_PMIC_RDY_SELECT_INPUT
EIM_EB1
EIM_DA0
EIM_DA1
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA5
EIM_DA6
EIM_DA7
EIM_DA8
EIM_DA9
EIM_DA10
IOMUXC_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT
EIM_DA11
IOMUXC_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT
EIM_DA12
IOMUXC_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT
EIM_DA13
IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT
EIM_DA14
EIM_DA15
NANDF_WE_B
NANDF_RE_B
EIM_WAIT
EIM_BCLK
NVCC_EIM__7
LVDS1_TX3_P
LVDS1_TX3_N
LVDS1_TX2_P
LVDS1_TX2_N
LVDS1_CLK_P
LVDS1_CLK_N
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
LVDS1_TX1_P
LVDS1_TX1_N
LVDS1_TX0_P
LVDS1_TX0_N
LVDS0_TX3_P
LVDS0_TX3_N
LVDS0_CLK_P
LVDS0_CLK_N
LVDS0_TX2_P
LVDS0_TX2_N
LVDS0_TX1_P
LVDS0_TX1_N
LVDS0_TX0_P
LVDS0_TX0_N
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
DRAM_D24
DRAM_D30
DRAM_D26
DRAM_DQM3
DRAM_D28
DRAM_D25
DRAM_SDQS3_B
DRAM_SDQS3
DRAM_D27
DRAM_D31
DRAM_D16
DRAM_D29
DRAM_D18
DRAM_SDCKE1
DRAM_D22
DRAM_DQM2
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
DRAM_D20
DRAM_SDBA0
DRAM_D17
DRAM_SDODT1
DRAM_D19
DRAM_SDQS2_B
DRAM_SDQS2
DRAM_D21
DRAM_CS1
DRAM_D23
DRAM_RESET
DRAM_SDBA1
DRAM_SDCLK_1_
B
DRAM_SDCLK_1
DRAM_A8
DRAM_SDBA2
DRAM_A14
DRAM_A3
DRAM_A5
DRAM_A7
DRAM_A6
DRAM_A9
DRAM_A2
DRAM_A0
DRAM_A15
DRAM_A13
DRAM_A11
DRAM_A1
DRAM_A12
DRAM_CAS
DRAM_SDWE
DRAM_CS0
DRAM_A4
DRAM_SDCLK_0_
B
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
DRAM_SDCLK_0
DRAM_A10
DRAM_D4
DRAM_D6
DRAM_D2
DRAM_SDQS0_B
DRAM_SDQS0
DRAM_SDODT0
DRAM_DQM0
DRAM_RAS
DRAM_D5
DRAM_D0
DRAM_D7
DRAM_SDCKE0
DRAM_D1
DRAM_D14
DRAM_D3
DRAM_D12
DRAM_D10
DRAM_D8
DRAM_D13
DRAM_SDQS1_B
DRAM_SDQS1
DRAM_DQM1
DRAM_D9
DRAM_D15
DRAM_D11
CKIH1
CKIH2
PMIC_ON_REQ
PMIC_STBY_REQ
NANDF_CLE
NANDF_ALE
NANDF_WP_B
NANDF_RB0
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
NANDF_CS0
NANDF_CS1
IOMUXC_MLB_MLBCLK_IN_SELECT_INPUT
NANDF_CS2
IOMUXC_ESAI1_IPP_IND_SDO0_SELECT_INPUT
IOMUXC_MLB_MLBSIG_IN_SELECT_INPUT
NANDF_CS3
IOMUXC_ESAI1_IPP_IND_SDO1_SELECT_INPUT
IOMUXC_MLB_MLBDAT_IN_SELECT_INPUT
NVCC_NANDF
FEC_MDIO
IOMUXC_ESAI1_IPP_IND_SCKR_SELECT_INPUT
IOMUXC_FEC_FEC_COL_SELECT_INPUT
IOMUXC_FEC_FEC_MDI_SELECT_INPUT
FEC_REF_CLK
IOMUXC_ESAI1_IPP_IND_FSR_SELECT_INPUT
FEC_RX_ER
IOMUXC_ESAI1_IPP_IND_HCKR_SELECT_INPUT
IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT
FEC_CRS_DV
IOMUXC_ESAI1_IPP_IND_SCKT_SELECT_INPUT
FEC_RXD1
IOMUXC_ESAI1_IPP_IND_FST_SELECT_INPUT
IOMUXC_MLB_MLBSIG_IN_SELECT_INPUT
FEC_RXD0
IOMUXC_ESAI1_IPP_IND_HCKT_SELECT_INPUT
FEC_TX_EN
IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT
FEC_TXD1
IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT
IOMUXC_MLB_MLBCLK_IN_SELECT_INPUT
FEC_TXD0
IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT
FEC_MDC
IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT
IOMUXC_MLB_MLBDAT_IN_SELECT_INPUT
NVCC_FEC
PATA_DIOW
IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
PATA_DMACK
IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
PATA_DMARQ
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
PATA_BUFFER_
EN
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
PATA_INTRQ
IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
PATA_DIOR
IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT
IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
PATA_RESET_B
IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
PATA_IORDY
IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT
IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
PATA_DA_0
IOMUXC_OWIRE_BATTERY_LINE_IN_SELECT_INPUT
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
Daisy Chain Control Registers
PATA_DA_1
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
PATA_DA_2
IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
PATA_CS_0
IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
PATA_CS_1
IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
NVCC_PATA__2
PATA_DATA0
PATA_DATA1
PATA_DATA2
PATA_DATA3
PATA_DATA4
PATA_DATA5
PATA_DATA6
PATA_DATA7
PATA_DATA8
PATA_DATA9
PATA_DATA10
PATA_DATA11
PATA_DATA12
PATA_DATA13
PATA_DATA14
PATA_DATA15
NVCC_PATA__0
SD1_DATA0
IOMUXC_CCM_PLL3_BYPASS_CLK_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
SD1_DATA1
IOMUXC_CCM_PLL4_BYPASS_CLK_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT
SD1_CMD
IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
SD1_DATA2
IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
SD1_CLK
IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
SD1_DATA3
IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
NVCC_SD1
Table continues on the next page...
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Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
SD2_CLK
Daisy Chain Control Registers
IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
SD2_CMD
IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
SD2_DATA3
IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
SD2_DATA2
IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
SD2_DATA1
IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_SS0_B_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
SD2_DATA0
IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
NVCC_SD2
GPIO_0
IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT
GPIO_1
IOMUXC_ESAI1_IPP_IND_SCKR_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
GPIO_9
IOMUXC_ESAI1_IPP_IND_FSR_SELECT_INPUT
IOMUXC_ESDHC1_IPP_WP_ON_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
GPIO_3
IOMUXC_ESAI1_IPP_IND_HCKR_SELECT_INPUT
IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT
IOMUXC_MLB_MLBCLK_IN_SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT
GPIO_6
IOMUXC_ESAI1_IPP_IND_SCKT_SELECT_INPUT
IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT
IOMUXC_MLB_MLBSIG_IN_SELECT_INPUT
GPIO_2
IOMUXC_ESAI1_IPP_IND_FST_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
IOMUXC_MLB_MLBDAT_IN_SELECT_INPUT
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-4. Daisy Chain Multiplexer Control Registers (by pin) (continued)
Pin Name
GPIO_4
Daisy Chain Control Registers
IOMUXC_ESAI1_IPP_IND_HCKT_SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
GPIO_5
IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT
IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
GPIO_7
IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT
IOMUXC_FIRI_IPP_IND_RXD_SELECT_INPUT
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
GPIO_8
IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT
IOMUXC_CCM_PLL3_BYPASS_CLK_SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT
IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
GPIO_16
IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT
IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT
IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT
GPIO_17
IOMUXC_ESAI1_IPP_IND_SDO0_SELECT_INPUT
IOMUXC_GPC_PMIC_RDY_SELECT_INPUT
IOMUXC_SDMA_EVENTS_14_SELECT_INPUT
GPIO_18
IOMUXC_CCM_IPP_ASRC_EXT_SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO1_SELECT_INPUT
IOMUXC_OWIRE_BATTERY_LINE_IN_SELECT_INPUT
IOMUXC_SDMA_EVENTS_15_SELECT_INPUT
NVCC_GPIO
POR_B
BOOT_MODE1
RESET_IN_B
BOOT_MODE0
TEST_MODE
Table 4-5 shows the daisy chain control registers sorted by block instance and block I/O.
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
Block
Instance
Block I/O
AUDMUX AUD4_RXD
AUD4_TXD
AUD4_RXC
AUD4_RXFS
AUDMUX AUD4_TXC
AUD4_TXFS
AUD5_RXD
Select Register
DAISY
Mode
IOMUXC_AUDMUX_P4_INPUT_DA_AMX_ 0
SELECT_INPUT
DISP0_
DAT23
ALT3
1
SD2_
DATA0
ALT3
IOMUXC_AUDMUX_P4_INPUT_DB_AMX_ 0
SELECT_INPUT
DISP0_
DAT21
ALT3
1
SD2_
DATA2
ALT3
0
DISP0_
DAT19
ALT4
1
SD2_
CMD
ALT3
0
DISP0_
DAT18
ALT4
1
SD2_
CLK
ALT3
0
DISP0_
DAT20
ALT3
1
SD2_
DATA3
ALT3
0
DISP0_
DAT22
ALT3
1
SD2_
DATA1
ALT3
IOMUXC_AUDMUX_P5_INPUT_DA_AMX_ 0
SELECT_INPUT
KEY_
ROW1
ALT2
DISP0_
DAT19
ALT3
KEY_
ROW0
ALT2
DISP0_
DAT17
ALT3
IOMUXC_AUDMUX_P4_INPUT_RXCLK_
AMX_SELECT_INPUT
IOMUXC_AUDMUX_P4_INPUT_RXFS_
AMX_SELECT_INPUT
IOMUXC_AUDMUX_P4_INPUT_TXCLK_
AMX_SELECT_INPUT
IOMUXC_AUDMUX_P4_INPUT_TXFS_
AMX_SELECT_INPUT
1
AUD5_TXD
Package
Pin
IOMUXC_AUDMUX_P5_INPUT_DB_AMX_ 0
SELECT_INPUT
1
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
Block I/O
AUDMUX AUD5_RXC
AUD5_RXFS
AUD5_TXC
AUD5_TXFS
CAN-1
CAN-2
RXCAN
RXCAN
Select Register
IOMUXC_AUDMUX_P5_INPUT_RXCLK_
AMX_SELECT_INPUT
IOMUXC_AUDMUX_P5_INPUT_RXFS_
AMX_SELECT_INPUT
IOMUXC_AUDMUX_P5_INPUT_TXCLK_
AMX_SELECT_INPUT
IOMUXC_AUDMUX_P5_INPUT_TXFS_
AMX_SELECT_INPUT
IOMUXC_CAN1_IPP_IND_CANRX_
SELECT_INPUT
IOMUXC_CAN2_IPP_IND_CANRX_
SELECT_INPUT
DAISY
Package
Pin
Mode
0
DISP0_
DAT14
ALT3
1
EIM_D25 ALT5
0
DISP0_
DAT13
1
EIM_D24 ALT5
0
KEY_
COL0
ALT2
1
DISP0_
DAT16
ALT3
0
KEY_
COL1
ALT2
1
DISP0_
DAT18
ALT3
0b00
KEY_
ROW2
ALT2
0b01
PATA_
DIOR
ALT4
0b10
GPIO_8
ALT3
0
KEY_
ROW4
ALT2
1
PATA_
IORDY
ALT4
ALT3
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
CCM
Block I/O
ASRC_EXT_CLK
DI1_EXT_CLK
PLL1_BYP
PLL2_BYP
PLL3_BYP
PLL4_BYP
Select Register
IOMUXC_CCM_IPP_ASRC_EXT_
SELECT_INPUT
DAISY
Package
Pin
Mode
0
KEY_
ROW3
1
GPIO_18 ALT5
IOMUXC_CCM_IPP_DI1_CLK_SELECT_
INPUT
0
EIM_EB2 ALT2
1
EIM_
DA13
ALT4
IOMUXC_CCM_PLL1_BYPASS_CLK_
SELECT_INPUT
0
SD1_
CMD
ALT7
1
GPIO_5
ALT7
0
SD1_
DATA2
ALT7
1
GPIO_7
ALT7
0
SD1_
DATA0
ALT7
1
GPIO_8
ALT7
0
KEY_
ROW3
ALT6
1
SD1_
DATA1
ALT7
IOMUXC_CCM_PLL2_BYPASS_CLK_
SELECT_INPUT
IOMUXC_CCM_PLL3_BYPASS_CLK_
SELECT_INPUT
IOMUXC_CCM_PLL4_BYPASS_CLK_
SELECT_INPUT
ALT3
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
CSPI
Block I/O
SCLK
MISO
MOSI
CSPI
SS0
Select Register
IOMUXC_CSPI_IPP_CSPI_CLK_IN_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b00
DISP0_
DAT0
0b01
EIM_D21 ALT4
0b10
SD1_
CLK
ALT5
0b11
SD2_
CLK
ALT5
DISP0_
DAT2
ALT2
IOMUXC_CSPI_IPP_IND_MISO_SELECT_ 0b00
INPUT
ALT2
0b01
EIM_D22 ALT4
0b10
SD1_
DATA0
ALT5
0b11
SD2_
DATA0
ALT5
IOMUXC_CSPI_IPP_IND_MOSI_SELECT_ 0b00
INPUT
DISP0_
DAT1
ALT2
IOMUXC_CSPI_IPP_IND_SS0_B_
SELECT_INPUT
0b01
EIM_D28 ALT4
0b10
SD1_
CMD
ALT5
0b11
SD2_
CMD
ALT5
0b000
DISP0_
DAT3
ALT2
0b001
EIM_D20 ALT4
0b010
EIM_D29 ALT4
0b011
SD1_
DATA1
ALT5
0b100
SD2_
DATA1
ALT5
Table continues on the next page...
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
CSPI
Block I/O
SS1
IOMUXC_CSPI_IPP_IND_SS1_B_
SELECT_INPUT
SS2
IOMUXC_CSPI_IPP_IND_SS2_B_
SELECT_INPUT
SS3
ECSPI-1
Select Register
IOMUXC_CSPI_IPP_IND_SS3_B_
SELECT_INPUT
SCLK
MISO
MOSI
IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_
SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_MISO_
SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_MOSI_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b00
DISP0_
DAT4
ALT2
0b01
EIM_A25 ALT4
0b10
SD1_
DATA2
ALT5
0b11
SD2_
DATA2
ALT5
0b00
DISP0_
DAT5
ALT2
0b01
EIM_D24 ALT4
0b10
SD1_
DATA3
ALT5
0b11
SD2_
DATA3
ALT5
0
DISP0_
DAT6
ALT2
1
EIM_D25 ALT4
0b00
KEY_
COL0
ALT5
0b01
DISP0_
DAT20
ALT2
0b10
CSI0_
DAT4
ALT3
0b11
EIM_D16 ALT4
0b00
KEY_
COL1
ALT5
0b01
DISP0_
DAT22
ALT2
0b10
CSI0_
DAT6
ALT3
0b11
EIM_D17 ALT4
0b00
KEY_
ROW0
ALT5
0b01
DISP0_
DAT21
ALT2
0b10
CSI0_
DAT5
ALT3
0b11
EIM_D18 ALT4
Table continues on the next page...
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Controlling Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
ECSPI-1
Block I/O
SS0
SS1
ECSPI-1
SS2
SS3
Select Register
IOMUXC_ECSPI1_IPP_IND_SS_B_0_
SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_1_
SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_2_
SELECT_INPUT
IOMUXC_ECSPI1_IPP_IND_SS_B_3_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b00
KEY_
ROW1
ALT5
0b01
DISP0_
DAT23
ALT2
0b10
CSI0_
DAT7
ALT3
0b11
EIM_EB2 ALT4
0b00
KEY_
COL2
ALT5
0b01
DISP0_
DAT15
ALT2
0b10
EIM_D19 ALT4
0
KEY_
ROW2
1
EIM_D24 ALT3
0
KEY_
COL3
1
EIM_D25 ALT3
ALT5
ALT5
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Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
ECSPI-2
Block I/O
SCLK
MISO
MOSI
SS0
Select Register
IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_
SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_MISO_
SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_MOSI_
SELECT_INPUT
IOMUXC_ECSPI2_IPP_IND_SS_B_0_
SELECT_INPUT
SS1
IOMUXC_ECSPI2_IPP_IND_SS_B_1_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b00
DISP0_
DAT19
ALT2
0b01
CSI0_
DAT8
ALT3
0b10
EIM_CS0 ALT2
0b00
DISP0_
DAT17
ALT2
0b01
CSI0_
DAT10
ALT3
0b10
EIM_OE
ALT2
0b00
DISP0_
DAT16
ALT2
0b01
CSI0_
DAT9
ALT3
0b10
EIM_CS1 ALT2
0b00
DISP0_
DAT18
ALT2
0b01
CSI0_
DAT11
ALT3
0b10
EIM_RW
ALT2
0
DISP0_
DAT15
ALT3
1
EIM_LBA ALT2
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Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
ESAI-1
Block I/O
FSR
Select Register
DAISY
IOMUXC_ESAI1_IPP_IND_FSR_SELECT_ 0
INPUT
FST
IOMUXC_ESAI1_IPP_IND_FST_SELECT_
INPUT
HCKR
HCKT
SCKR
SCKT
TX0
IOMUXC_ESAI1_IPP_IND_HCKR_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_HCKT_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SCKR_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SCKT_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO0_
SELECT_INPUT
TX1
IOMUXC_ESAI1_IPP_IND_SDO1_
SELECT_INPUT
TX2_RX3
TX3_RX2
TX4_RX1
TX5_RX0
IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_
SELECT_INPUT
IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_
SELECT_INPUT
Package
Pin
Mode
FEC_
REF_
CLK
ALT2
1
GPIO_9
ALT0
0
FEC_
RXD1
ALT2
1
GPIO_2
ALT0
0
FEC_
RX_ER
ALT2
1
GPIO_3
ALT0
0
FEC_
RXD0
ALT2
1
GPIO_4
ALT0
0
FEC_
MDIO
ALT2
1
GPIO_1
ALT0
0
FEC_
CRS_DV
ALT2
1
GPIO_6
ALT0
0
NANDF_
CS2
ALT3
1
GPIO_17 ALT0
0
NANDF_
CS3
1
GPIO_18 ALT0
0
FEC_
TXD1
ALT2
1
GPIO_5
ALT0
0
FEC_
TX_EN
ALT2
1
GPIO_16 ALT0
0
FEC_
TXD0
ALT2
1
GPIO_7
ALT0
0
FEC_
MDC
ALT2
1
GPIO_8
ALT0
ALT3
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
Block I/O
Select Register
DAISY
Package
Pin
Mode
ESDHCV WP
2-1
IOMUXC_ESDHC1_IPP_WP_ON_
SELECT_INPUT
0
DI0_PIN4 ALT3
1
GPIO_9
ALT6
FEC
IOMUXC_FEC_FEC_COL_SELECT_
INPUT
0
KEY_
ROW1
ALT6
1
FEC_
MDIO
ALT3
IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0
KEY_
COL2
ALT4
1
FEC_
MDIO
ALT0
0
KEY_
COL1
ALT6
1
FEC_
RX_ER
ALT3
IOMUXC_FIRI_IPP_IND_RXD_SELECT_
INPUT
0
EIM_D26 ALT3
1
GPIO_7
IOMUXC_GPC_PMIC_RDY_SELECT_
INPUT
0
EIM_EB0 ALT5
1
GPIO_17 ALT3
IOMUXC_I2C1_IPP_SCL_IN_SELECT_
INPUT
0
CSI0_
DAT9
1
EIM_D21 ALT5
0
CSI0_
DAT8
1
EIM_D28 ALT5
0
KEY_
COL3
1
EIM_EB2 ALT5
0
KEY_
ROW3
1
EIM_D16 ALT5
0b00
EIM_D17 ALT5
0b01
GPIO_3
ALT2
0b10
GPIO_5
ALT6
0b00
EIM_D18 ALT5
0b01
GPIO_6
0b10
GPIO_16 ALT6
COL
MDIO
RX_CLK
FIRI
GPC
I2C-1
RXD
PMIC_RDY
SCL
SDA
I2C-2
IOMUXC_I2C1_IPP_SDA_IN_SELECT_
INPUT
SCL
IOMUXC_I2C2_IPP_SCL_IN_SELECT_
INPUT
SDA
I2C-3
IOMUXC_FEC_FEC_RX_CLK_SELECT_
INPUT
IOMUXC_I2C2_IPP_SDA_IN_SELECT_
INPUT
SCL
IOMUXC_I2C3_IPP_SCL_IN_SELECT_
INPUT
SDA
IOMUXC_I2C3_IPP_SDA_IN_SELECT_
INPUT
ALT5
ALT5
ALT5
ALT4
ALT4
ALT2
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Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
IPU
Block I/O
DISPB0_SER_DIN
DISPB1_SER_DIN
CSI1_DATA_EN
CSI1_HSYNC
CSI1_VSYNC
Select Register
DAISY
Package
Pin
Mode
IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_ 0
D_SELECT_INPUT
1
EIM_D22 ALT3
IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_ 0
D_SELECT_INPUT
1
EIM_D17 ALT3
IOMUXC_IPU_IPP_IND_SENS1_DATA_
EN_SELECT_INPUT
0
EIM_D23 ALT6
1
EIM_
DA10
IOMUXC_IPU_IPP_IND_SENS1_HSYNC_
SELECT_INPUT
0
EIM_EB3 ALT6
1
EIM_
DA11
IOMUXC_IPU_IPP_IND_SENS1_VSYNC_
SELECT_INPUT
0
EIM_D29 ALT6
1
EIM_
DA12
EIM_D28 ALT3
EIM_D18 ALT3
ALT4
ALT4
ALT4
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
KPP
Block I/O
COL[5]
COL[6]
COL[7]
ROW[5]
ROW[6]
ROW[7]
Select Register
IOMUXC_KPP_IPP_IND_COL_5_
SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_6_
SELECT_INPUT
IOMUXC_KPP_IPP_IND_COL_7_
SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_5_
SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_6_
SELECT_INPUT
IOMUXC_KPP_IPP_IND_ROW_7_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b00
GPIO_19 ALT0
0b01
CSI0_
DAT4
ALT2
0b10
SD2_
CLK
ALT2
0b11
GPIO_0
ALT2
0b00
CSI0_
DAT6
ALT2
0b01
SD2_
DATA3
ALT2
0b10
GPIO_9
ALT2
0b00
CSI0_
DAT8
ALT2
0b01
SD2_
DATA1
ALT2
0b10
GPIO_4
ALT2
0b00
CSI0_
DAT5
ALT2
0b01
SD2_
CMD
ALT2
0b10
GPIO_1
ALT2
0b00
CSI0_
DAT7
ALT2
0b01
SD2_
DATA2
ALT2
0b10
GPIO_2
ALT2
0b00
CSI0_
DAT9
ALT2
0b01
SD2_
DATA0
ALT2
0b10
GPIO_5
ALT2
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Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
MLB
Block I/O
MLBCLK
MLBDAT
MLBSIG
OWIRE
SDMA
LINE
SDMA_EXT_
EVENT[0]
SDMA_EXT_
EVENT[1]
SPDIF
IN1
Select Register
IOMUXC_MLB_MLBCLK_IN_SELECT_
INPUT
IOMUXC_MLB_MLBDAT_IN_SELECT_
INPUT
IOMUXC_MLB_MLBSIG_IN_SELECT_
INPUT
IOMUXC_OWIRE_BATTERY_LINE_IN_
SELECT_INPUT
IOMUXC_SDMA_EVENTS_14_SELECT_
INPUT
IOMUXC_SDMA_EVENTS_15_SELECT_
INPUT
IOMUXC_SPDIF_SPDIF_IN1_SELECT_
INPUT
DAISY
Package
Pin
Mode
0b00
NANDF_
CS1
ALT6
0b01
FEC_
TXD1
ALT3
0b10
GPIO_3
ALT7
0b00
NANDF_
CS3
ALT6
0b01
FEC_
MDC
ALT3
0b10
GPIO_2
ALT7
0b00
NANDF_
CS2
ALT6
0b01
FEC_
RXD1
ALT3
0b10
GPIO_6
ALT7
0
PATA_
DA_0
ALT4
1
GPIO_18 ALT3
0
DISP0_
DAT16
1
GPIO_17 ALT2
0
DISP0_
DAT17
1
GPIO_18 ALT2
0
KEY_
COL3
1
GPIO_16 ALT5
ALT4
ALT4
ALT3
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
UART-1
Block I/O
RTS
IOMUXC_UART1_IPP_UART_RTS_B_
SELECT_INPUT
RXD_MUX
UART-2
Select Register
RTS
IOMUXC_UART1_IPP_UART_RXD_MUX_
SELECT_INPUT
IOMUXC_UART2_IPP_UART_RTS_B_
SELECT_INPUT
RXD_MUX
IOMUXC_UART2_IPP_UART_RXD_MUX_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b00
EIM_D19 ALT6
0b01
EIM_D20 ALT6
0b10
PATA_
RESET_
B
ALT3
0b11
PATA_
IORDY
ALT3
0b00
CSI0_
DAT10
ALT2
0b01
CSI0_
DAT11
ALT2
0b10
PATA_
DIOW
ALT3
0b11
PATA_
DMACK
ALT3
0b00
EIM_D28 ALT2
0b01
EIM_D29 ALT2
0b10
PATA_
INTRQ
ALT3
0b11
PATA_
DIOR
ALT3
0b000
EIM_D26 ALT2
0b001
EIM_D27 ALT2
0b010
PATA_
DMARQ
ALT3
0b011
PATA_
BUFFER
_EN
ALT3
0b100
GPIO_7
ALT4
0b101
GPIO_8
ALT4
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Controlling Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
UART-3
Block I/O
RTS
IOMUXC_UART3_IPP_UART_RTS_B_
SELECT_INPUT
RXD_MUX
UART-4
Select Register
RTS
IOMUXC_UART3_IPP_UART_RXD_MUX_
SELECT_INPUT
IOMUXC_UART4_IPP_UART_RTS_B_
SELECT_INPUT
RXD_MUX
IOMUXC_UART4_IPP_UART_RXD_MUX_
SELECT_INPUT
DAISY
Package
Pin
Mode
0b000
EIM_D23 ALT2
0b001
EIM_EB3 ALT2
0b010
EIM_D30 ALT2
0b011
EIM_D31 ALT2
0b100
PATA_
DA_1
ALT4
0b101
PATA_
DA_2
ALT4
0b00
EIM_D24 ALT2
0b01
EIM_D25 ALT2
0b10
PATA_
CS_0
ALT4
0b11
PATA_
CS_1
ALT4
0
CSI0_
DAT16
ALT2
1
CSI0_
DAT17
ALT2
0b00
KEY_
COL0
ALT4
0b01
KEY_
ROW0
ALT4
0b10
CSI0_
DAT12
ALT2
0b11
CSI0_
DAT13
ALT2
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Chapter 4 External Signals and Pin Multiplexing
Table 4-5. Daisy Chain Multiplexer Control Registers (by block instance / block I/O)
(continued)
Block
Instance
UART-5
Block I/O
RTS
IOMUXC_UART5_IPP_UART_RTS_B_
SELECT_INPUT
RXD_MUX
USB
Select Register
USBOTG_OC
USBH1_OC
USBH2_OC
USBH2_OC
DAISY
Package
Pin
Mode
0b00
KEY_
COL4
ALT4
0b01
KEY_
ROW4
ALT4
0b10
CSI0_
DAT18
ALT2
0b11
CSI0_
DAT19
ALT2
0b00
KEY_
COL1
ALT4
0b01
KEY_
ROW1
ALT4
0b10
CSI0_
DAT14
ALT2
0b11
CSI0_
DAT15
ALT2
0
KEY_
COL4
ALT5
1
EIM_D21 ALT6
IOMUXC_USBOH3_IPP_IND_UH1_OC_
SELECT_INPUT
0
EIM_D30 ALT6
1
GPIO_3
IOMUXC_USBOH3_IPP_IND_UH2_OC_
SELECT_INPUT
0
EIM_D19 ALT7
1
EIM_D30 ALT7
IOMUXC_UART5_IPP_UART_RXD_MUX_
SELECT_INPUT
IOMUXC_USBOH3_IPP_IND_OTG_OC_
SELECT_INPUT
ALT6
4.3 Special Package Pins
In addition to the package pins discussed above, i.MX53 has other dedicated pins that
serve special purposes. These are generally pins that convey signals with special voltage
or drive characteristics or are used for test purposes.
Table 4-6 lists package analog and power pins and their characteristics.
Table 4-6. Special Package Pins
Pin Name
Internal Signal Name
Buffer Type
Signal Use
CKIL
CKIL
Analog
Pervasive
ECKIL
ECKIL
Analog
Pervasive
EXTAL
EXTAL
Analog
Pervasive
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Special Package Pins
Table 4-6. Special Package Pins (continued)
Pin Name
Internal Signal Name
Buffer Type
Signal Use
FASTR_ANA
FASTR_ANA
Analog
Freescale use only
FASTR_DIG
FASTR_DIG
Analog
Freescale use only
DRAM_CALIBRATION
DRAM_CALIBRATION
Calibration
External Memory
Controller
LVDS_BG_RES
LVDS_BG_RES
Analog
Pervasive
SATA_REFCLKM
SATA_REFCLKM
Analog
SATA PHY
SATA_REFCLKP
SATA_REFCLKP
Analog
SATA PHY
SATA_REXT
SATA_REXT
Analog
SATA PHY
SATA_RXM
SATA_RXM
Analog
SATA PHY
SATA_RXP
SATA_RXP
Analog
SATA PHY
SATA_TXM
SATA_TXM
Analog
SATA PHY
SATA_TXP
SATA_TXP
Analog
SATA PHY
TVCDC_IOB_BACK
TVCDC_IOB_BACK
Analog
TV Encoder
TVCDC_IOG_BACK
TVCDC_IOG_BACK
Analog
TV Encoder
TVCDC_IOR_BACK
TVCDC_IOR_BACK
Analog
TV Encoder
TVDAC_COMP
TVDAC_COMP
Analog
TV Encoder
TVDAC_IOB
TVDAC_IOB
Analog
TV Encoder
TVDAC_IOG
TVDAC_IOG
Analog
TV Encoder
TVDAC_IOR
TVDAC_IOR
Analog
TV Encoder
TVDAC_VREF
TVDAC_VREF
Analog
TV Encoder
USB_H1_DN
USB_H1_DN
Analog50
USB H1 PHY
USB_H1_DP
USB_H1_DP
Analog50
USB H1 PHY
USB_H1_GPANAIO
USB_H1_GPANAIO
Analog25
USB H1 PHY
USB_H1_RREFEXT
USB_H1_RREFEXT
Analog25
USB H1 PHY
USB_H1_VBUS
USB_H1_VBUS
Analog50
USB H1 PHY
USB_OTG_DN
USB_OTG_DN
Analog50
USB OTG PHY
USB_OTG_DP
USB_OTG_DP
Analog50
USB OTG PHY
USB_OTG_GPANAIO
USB_OTG_GPANAIO
Analog25
USB OTG PHY
USB_OTG_ID
USB_OTG_ID
Analog25
USB OTG PHY
USB_OTG_RREFEXT
USB_OTG_RREFEXT
Analog25
USB OTG PHY
USB_OTG_VBUS
USB_OTG_VBUS
Analog50
USB OTG PHY
XTAL
XTAL
Analog
Pervasive
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Chapter 5
External Memory
5.1 Overview
The External Memory Controller (EXTMC) is the block that services all i.MX53 external
memory accesses requests (read/write/erase/program) from all the AXI bus masters in the
system. All accesses are arbitrated by the Multi Master Multi Memory Interface (M4IF)
block and controlled by the respective memory controller. The high level block diagram
is presented in Figure 5-1.
Each AXI bus master interface port is an AXI interface with separated input bus for read
and write access, so masters that handle separated buses for read and write access can
access the EXTMC. The data width can be 32 or 64 bits. All ports support 32 or 64-bit
IF.
NOTE
The following is a summary of the EXTMC used in i.MX53.
This summary takes precedence if any discrepancy between the
information here and the information in the EXTMC (and
related sub-blocks) block guide arises. Please note that in case
of conflict, the information related to frequencies of operation
supersedes that of the block chapters and is superseded by that
of the data sheet.
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Overview
Figure 5-1. EXTMC High Level Block Diagram
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Chapter 5 External Memory
5.2 External Memory Interface - i.MX53 Specific
Configuration
The EXTMC provides the ability to connect to a wide variety of memory devices. This
chapter contains the technical information about the operation and configuration of the
EXTMC in the chip to allow the designer to quickly integrate external memory devices
into new and existing designs. Pin sharing is done between the data bus of the external
interface module (EIM) and the NAND Flash Controller (NFC) in order to reduce the
total number of pins needed for the EXTMC.
The EXTMC is an External Memory Interface and arbitration between multi AXI masters
to multi memory controllers, divided into three major channels: fast memories (DDR2,
DDR3, LPDDR2) channel, slow memories (NOR-FLASH/PSRAM/NAND-FLASH etc.)
channel, Internal Memory (RAM, ROM) channel, and Internal GMEM memory.
In order to increase the bandwidth performance, the EXTMC separates the buffering and
the arbitration between accesses to fast channel slow channel and Internal Memory
channels, so parallel accesses can occur. By separating the three channels slow accesses
don't interfere with fast accesses.
The EXTMC contains the arbitration interface and different external memory controllers
in order to support several memory devices:
•
•
•
•
M4IF - Multi Master Multi Memory Interface.
ESDRAMC - Enhanced DDR2/DDR3/LPDDR2 memory controller.
NFC - NANDFlash memory controller.
EIM - SRAM/PSRAM/NOR FLASH memory controller
5.2.1 EXTMC - AXI Bus Masters
The table below provides details on AXI bus masters and the AXI bus master interface
port associated with each master. Please refer to the M4IF chapter for buffer sizes for
each master.
Table 5-1. AXI Bus Masters
Block
Direct Bus
Master
Port
Buffered
Boundary
Crossing
Max frequency
Mhz
IPU
AXI
0
y
4K
200MHz
VPU
AXI
1
y
4K
200MHz
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External Memory Interface - i.MX53 Specific Configuration
Table 5-1. AXI Bus Masters (continued)
Block
Direct Bus
Master
Port
Buffered
Boundary
Crossing
Max frequency
Mhz
DAP
AHB via AHBMAX
2
n
1K
133MHz
SAHARA
AHB via AHBMAX
2
n
1K
133MHz
SCC
AHB via AHBMAX
2
n
1K
133MHz
RTIC
AHB via AHBMAX
2
n
1K
133MHz
SDMA (non-burst)
AHB via AHBMAX
2
n
1K
133MHz
ESDHCV2-2
AHB via AHBMAX
2
n
1K
133MHz
ESDHCV2-1
AHB via AHBMAX
2
n
1K
133MHz
ECSPI-1
AHB via AHBMAX
2
n
1K
133MHz
ESDHCV2-3
AHB via AHBMAX
2
n
1K
133MHz
PATA
AHB via AHBMAX
2
n
1K
133MHz
EXTMC ARB3
AHB via AHBMAX
2
n
1K
133MHz
ARM Cortex-A8
AXI
3
y
4K
200MHz
SDMA (burst)
AHB via PLARB1
4
n
1K
133MHz
FEC
AHB via PLARB1
4
n
1K
66MHz
SATA
AHB via PLARB1
4
n
1K
133MHz
GPU3D
AXI
5
y
4K
200MHz
GPU2D (OpenVG)
AXI
6
y
4K
200MHz
USB
AXI
7
n
4K
133MHz
5.2.2 Features
Each of the EXTMC memory controller block guide specify detailed information on the
supported features, programming model. However, in i.MX53 some of those feature are
disabled or not supported.
The EXTMC in the i.MX53 includes these distinctive features:
• Multi Master Multi Memory Interface (M4IF)
• Supports multiple accesses from 8 masters through different input ports
interfaces. Each port can support either of the following two data width options:
• x32 AXI port.
• x64 AXI port.
• Supports different clock domain for each AXI port master.
• Configurable memory watermark protection per DDR2/DDR3/LPDDR2 CS.
• Enhanced arbitration scheme for fast channel, consider page hit/miss, last access
details (read/write) and fixed priority configuration.
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Chapter 5 External Memory
• Enhanced DDR Controller (ESDRAMC)
• Up to 2 chip selects support up to 1GByte each.
• x64 AXI port.
• Supports x16/x32 DDR2 memories up to 400MHz (800 MHz data rate)
• Supports x16/x32 DDR3 memories up to 400MHz (800 MHz data rate)
• Supports x32 LPDDR2 memory (Please refer to the i.MX53 Data Sheet for
target frequencies)
• Supports latency hiding logic.
• NANDFlash Controller - (NFC)
• x8/x16 NAND interface.
• Up to 8 chip selects support up to 8Gbit in 1/2K page mode, 64Gbit in 2K page
mode and 256Gbit in 4K page mode each.
• 4.5K RAM Internal Buffer
• MLC and SLC memory support.
• Configurable operation mode - symmetric and asymmetric.
• Configurable page mode, 1/2K, 2K or 4K.
• ECC support up to 16 bit.
• Supports up to 8 mutually exclusive, yet interleaved nand devices.
• Automatic Common NAND Operations
• External Interface Memory Controller - (EIM)
• Up to 4 chip selects, programmable using the General Purpose Register in
IOMUXC.
• Supports x32/x16/x8 PSRAM/NOR (at slow frequency).
• Supports DVFS, voltage and frequency change.
• Supports automatic shut-down (power saving features)
• Enhanced debug capabilities (trace mode).
Table 5-2. EIM multiplexing
Setup
Non Multiplexed Address/Data Mode
8 Bit
MUM = 0,
DSZ = 100
16 Bit
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 111
MUM = 0,
DSZ = 001
MUM = 0,
DSZ = 010
Multiplexed Address/
Data mode
32 Bit
16 Bit
32 Bit
MUM = 0,
DSZ = 011
MUM = 1,
DSZ = 001
MUM = 1,
DSZ = 011
A[15:0]
EIM_DA[15: EIM_DA[15: EIM_DA[15: EIM_DA[15: EIM_DA[15: EIM_DA[15: EIM_DA[15: EIM_DA[15:
0]
0]
0]
0]
0]
0]
0]
0]
A[25:16]
EIM_A[25:1 EIM_A[25:1 EIM_A[25:1 EIM_A[25:1 EIM_A[25:1 EIM_A[24:1 EIM_A[25:1 EIM_A[8:0]
6]
6]
6]
6]
6]
6]1
6]
D[7:0],
EIM_EB0
NANDF_D[
7:0]
-
-
NANDF_D[
7:0]2
-
NANDF_D[
7:0]
EIM_DA[7:0 EIM_DA[7:0
]
]
D[15:8],
EIM_EB1
-
NANDF_D[
15:8]
-
NANDF_D[
15:8]3
-
NANDF_D[
15:8]
EIM_DA[15: EIM_DA[15:
8]
8]
Table continues on the next page...
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EXTMC Setup
Table 5-2. EIM multiplexing (continued)
Setup
Non Multiplexed Address/Data Mode
8 Bit
MUM = 0,
DSZ = 100
16 Bit
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 111
MUM = 0,
DSZ = 001
MUM = 0,
DSZ = 010
Multiplexed Address/
Data mode
32 Bit
16 Bit
32 Bit
MUM = 0,
DSZ = 011
MUM = 1,
DSZ = 001
MUM = 1,
DSZ = 011
D[23:16],
EIM_EB2
-
-
-
-
EIM_D[23:1 EIM_D[23:1 6]
6]
NANDF_D[
7:0]
D[31:24],
EIM_EB3
-
-
EIM_D[31:2 4]
EIM_D[31:2 EIM_D[31:2 4]
4]
NANDF_D[
15:8]
1. For 32-bit, the address range is A[24:0], due to address space allocation in memory map.
2. NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0]
3. NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8]
5.3 EXTMC Setup
The following section describes i.MX53 specific requirements in order to use the
EXTMC.
5.3.1 Clock Domains
EXTMC contains the following clock domains:
•
•
•
•
•
EXTMC IP Bus clock.
ESDCTLV2 main clock (up to 400MHz)
Slow arbitration clock. (up to 133MHz)
Internal memory arbitration 1 & 2 clocks. (up to 133MHz)
8 x master clocks, can be asynchronous to EXTMC arbitration clocks (up to
200MHz) see Table 5-3.
• NFC main clock - should be integer divided from slow arbitration clock. (up to
50MHz)
• SDCLK - SDR/DDR clock to SDR/DDR SDRAM device.
• BCLK - NOR Flash/PSRAM clock WEIMv2 in synchronous mode.
5.3.2 Boot Scenarios
The EXTMC memory controllers allow booting from the following memories: NOR
Flash devices (through the EIM) and NAND Flash devices (through the NFC) special
signals coming from the SoC define the different booting options to those memories like
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Chapter 5 External Memory
the memory data width, memory page size and other specific parameters for the initial
access of the boot. For more details refer to the memory controllers detailed chapters and
boot chapter.
5.3.3 Watermark Ports
Watermark regions are supported in the EXTMC while the configuration is handled by
the CSU. The external memory spaces will have trust zone area's that only trust zone
accesses will be able to reach. Non trust zone accesses will be blocked. The central
security unit (CSU) has the registers that define those regions and send the indication of
the region and if specific access is trust zone or not to the EXTMC.
The watermark indication is dynamic and can change for each access.
For details on the watermark configuration refer to the CSU chapter.
5.3.4 EXTMC I/O Multiplexing
The EXTMC gives the system the ability to multiplex some of its signals in the SoC to
allow pin sharing between the different memory controllers. Multiplexing is possible on
the "slow" channel only because of timing limitations.
Only shared i.MX53 pins signals/busses are routed through the IOMUXC toward the
external devices. Signals (mainly controls) that have dedicated pins are directly routed
from the memory controllers to the external devices.
Table 5-3. EXTMC I/O Multiplexing in i.MX53
EXTMC port
i.MX53 pin
Mode
DRAM_A[0]
DRAM_A0
No Muxing (ALT0)
DRAM_A[10]
DRAM_A10
No Muxing (ALT0)
DRAM_A[11]
DRAM_A11
No Muxing (ALT0)
DRAM_A[12]
DRAM_A12
No Muxing (ALT0)
DRAM_A[13]
DRAM_A13
No Muxing (ALT0)
DRAM_A[14]
DRAM_A14
No Muxing (ALT0)
DRAM_A[15]
DRAM_A15
No Muxing (ALT0)
DRAM_A[1]
DRAM_A1
No Muxing (ALT0)
DRAM_A[2]
DRAM_A2
No Muxing (ALT0)
DRAM_A[3]
DRAM_A3
No Muxing (ALT0)
DRAM_A[4]
DRAM_A4
No Muxing (ALT0)
Table continues on the next page...
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EXTMC Setup
Table 5-3. EXTMC I/O Multiplexing in i.MX53 (continued)
EXTMC port
i.MX53 pin
Mode
DRAM_A[5]
DRAM_A5
No Muxing (ALT0)
DRAM_A[6]
DRAM_A6
No Muxing (ALT0)
DRAM_A[7]
DRAM_A7
No Muxing (ALT0)
DRAM_A[8]
DRAM_A8
No Muxing (ALT0)
DRAM_A[9]
DRAM_A9
No Muxing (ALT0)
DRAM_CAS
DRAM_CAS
No Muxing (ALT0)
DRAM_CS[0]
DRAM_CS0
No Muxing (ALT0)
DRAM_CS[1]
DRAM_CS1
No Muxing (ALT0)
DRAM_DQM[0]
DRAM_DQM0
No Muxing (ALT0)
DRAM_DQM[1]
DRAM_DQM1
No Muxing (ALT0)
DRAM_DQM[2]
DRAM_DQM2
No Muxing (ALT0)
DRAM_DQM[3]
DRAM_DQM3
No Muxing (ALT0)
DRAM_D[0]
DRAM_D0
No Muxing (ALT0)
DRAM_D[10]
DRAM_D10
No Muxing (ALT0)
DRAM_D[11]
DRAM_D11
No Muxing (ALT0)
DRAM_D[12]
DRAM_D12
No Muxing (ALT0)
DRAM_D[13]
DRAM_D13
No Muxing (ALT0)
DRAM_D[14]
DRAM_D14
No Muxing (ALT0)
DRAM_D[15]
DRAM_D15
No Muxing (ALT0)
DRAM_D[16]
DRAM_D16
No Muxing (ALT0)
DRAM_D[17]
DRAM_D17
No Muxing (ALT0)
DRAM_D[18]
DRAM_D18
No Muxing (ALT0)
DRAM_D[19]
DRAM_D19
No Muxing (ALT0)
DRAM_D[1]
DRAM_D1
No Muxing (ALT0)
DRAM_D[20]
DRAM_D20
No Muxing (ALT0)
DRAM_D[21]
DRAM_D21
No Muxing (ALT0)
DRAM_D[22]
DRAM_D22
No Muxing (ALT0)
DRAM_D[23]
DRAM_D23
No Muxing (ALT0)
DRAM_D[24]
DRAM_D24
No Muxing (ALT0)
DRAM_D[25]
DRAM_D25
No Muxing (ALT0)
DRAM_D[26]
DRAM_D26
No Muxing (ALT0)
DRAM_D[27]
DRAM_D27
No Muxing (ALT0)
DRAM_D[28]
DRAM_D28
No Muxing (ALT0)
DRAM_D[29]
DRAM_D29
No Muxing (ALT0)
DRAM_D[2]
DRAM_D2
No Muxing (ALT0)
Table continues on the next page...
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Chapter 5 External Memory
Table 5-3. EXTMC I/O Multiplexing in i.MX53 (continued)
EXTMC port
i.MX53 pin
Mode
DRAM_D[30]
DRAM_D30
No Muxing (ALT0)
DRAM_D[31]
DRAM_D31
No Muxing (ALT0)
DRAM_D[3]
DRAM_D3
No Muxing (ALT0)
DRAM_D[4]
DRAM_D4
No Muxing (ALT0)
DRAM_D[5]
DRAM_D5
No Muxing (ALT0)
DRAM_D[6]
DRAM_D6
No Muxing (ALT0)
DRAM_D[7]
DRAM_D7
No Muxing (ALT0)
DRAM_D[8]
DRAM_D8
No Muxing (ALT0)
DRAM_D[9]
DRAM_D9
No Muxing (ALT0)
DRAM_ODT[0]
DRAM_SDODT0
No Muxing (ALT0)
DRAM_ODT[1]
DRAM_SDODT1
No Muxing (ALT0)
DRAM_RAS
DRAM_RAS
No Muxing (ALT0)
DRAM_RESET
DRAM_RESET
No Muxing (ALT0)
DRAM_SDBA[0]
DRAM_SDBA0
No Muxing (ALT0)
DRAM_SDBA[1]
DRAM_SDBA1
No Muxing (ALT0)
DRAM_SDBA[2]
DR
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