NXP MPC5553 32-bit MCU Reference Manual

NXP MPC5553 32-bit MCU Reference Manual
Freescale Semiconductor
Addendum
Document Number: e200z6RMAD
Rev. 0.2, 10/2006
Errata to the
e200z6 PowerPC™ Core
Reference Manual, Rev. 0
This errata describes corrections to the e200z6 PowerPC™ Core Reference Manual, Revision 0. For
convenience, the section number and page number of the errata item in the reference manual are provided.
Items in bold are new since the last revision of this document.
To locate any published updates for this document, visit our website listed on the back cover of this
document.
Section, Page No.
2.3.1, 2-8
Changes
Add the following to the description of MSR[EE]:
“If MSR[EE] = 0 and a transfer error occurs, a DSI or ISI is taken rather than a
machine check or checkstop, as defined by the PowerPC architecture. For more
information see the note in Section 5.6.2, “Machine Check Interrupt (IVOR1),”.1
This does not affect the e200z6 with VLE.”
1. Which is provided in an erratum below.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
2.7.2.3, 2-26
32
Field
Machine Check Syndrome Register (MCSR) bits 59 and 60 are incorrectly shown
to be reserved. Replace Figure 2-21 and Table 2-14 with the following:
33
MCP —
34
35
36
37
58
CP_
EXCP_
CPERR
PERR
ERR
Reset
—
59
BUS_
IRERR
60
61
62 63
BUS_
BUS_
DRERR WRERR
—
All zeros
R/W
R/W
SPR
SPR 572
Figure 2-21. Machine Check Syndrome Register (MCSR)
Table 2-14. MCSR Field Descriptions
Bits
Name
32
MCP
33
—
34
CP_PERR
35
CPERR
36
EXCP_ERR
37–58
—
59
BUS_IRERR
Read bus error on Instruction fetch
Unlikely
60
BUS_DRERR
Read bus error on data load
Unlikely
61
BUS_WRERR Write bus error on buffered store or cache line push
62–63
—
Description
Machine check input signal
Reserved, should be cleared.
Recoverable
Maybe
—
Cache push parity error
Unlikely
Cache parity error
Precise
ISI, ITLB, or bus error on first instruction fetch for an exception handler
Precise
Reserved, should be cleared.
Reserved, should be cleared.
—
Unlikely
—
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
2
Freescale Semiconductor
2.13.1, 2-55
Add WAM bit 42 to the L1 Cache Control and Status Register 0 (L1CSR0).
Replace Figure 2-40 and Table 2-26 with the following:
Way Partitioning APU Bits
32
Field
35
36
39
WID
WDD
40
41
42
43
44
45
46
47
AWID
AWDD
WAM
CWM
DPB
DSB
DSTRM
CPE
60
61
62
63
CABT
CFI
CE
Reset
All zeros
R/W
R/W
Line Locking APU Bits
48
Field
52
—
Reset
53
54
55
CUL
CLO
CLFR
56
—
All zeros
R/W
R/W
SPR
SPR 1010
Figure 2-40. L1 Cache Control and Status Register 0 (L1CSR0)
Table 2-26. L1CSR0 Field Descriptions
Bits
Name
Description
32–35
WID
Way instruction disable. WID and WDD are used for locking ways of the cache and determining the cache
replacement policy.
0 The corresponding way is available for replacement by instruction miss line fills.
1 The corresponding way is not available for replacement by instruction miss line fills.
Bit 0 corresponds to way 0, bit 1 corresponds to way 1, bit 2 corresponds to way 2, and
bit 3 corresponds to way 3.
36–39
WDD
Way data disable. WID and WDD are used for locking ways of the cache and determining the cache
replacement policy.
0 The corresponding way is available for replacement by data miss line fills.
1 The corresponding way is not available for replacement by data miss line fills.
Bit 4 corresponds to way 0, bit 5 corresponds to way 1, bit 6 corresponds to way 2, bit 7 corresponds to
way 3.
40
AWID
Additional ways instruction disable
0 Additional ways beyond 0–3 are available for replacement by instruction miss line fills.
1 Additional ways beyond 0–3 are not available for replacement by instruction miss line fills.
For the 32-Kbyte 8-way cache, ways 4–7 are considered additional ways.
41
AWDD
Additional ways data disable
0 Additional ways beyond 0–3 are available for replacement by data miss line fills.
1 Additional ways beyond 0–3 are not available for replacement by data miss line fills.
For the 32-Kbyte 8-way cache, ways 4–7 are considered additional ways.
42
WAM
Cache way partitioning APU. Way access mode.
0 All ways are available for access.
1 Only ways partitioned for the specific type of access are used for a fetch or read operation.
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
3
Table 2-26. L1CSR0 Field Descriptions (continued)
Bits
Name
Description
43
CWM
Cache write mode. When set to write-through mode, the W page attribute from an optional MMU is ignored
and all writes are treated as write through required. When set, write accesses are performed in copy-back
mode unless the W page attribute from an optional MMU is set.
0 Cache operates in write-through mode.
1 Cache operates in copy-back mode.
44
DPB
Disable push buffer
0 Push buffer enabled
1 Push buffer disabled
45
DSB
Disable store buffer
0 Store buffer enabled
1 Store buffer disabled
46
DSTRM Disable streaming
0 Streaming is enabled.
1 Streaming is disabled.
47
CPE
Cache parity enable
0 Parity checking is disabled.
1 Parity checking is enabled.
48–52
—
Reserved, should be cleared.
53
CUL
Cache unable to lock. Indicates a lock set instruction was not effective in locking a cache line. This bit is set
by hardware on an “unable to lock” condition (other than lock overflows), and remain set until cleared by
software writing 0 to this bit location.
54
CLO
Cache lock overflow. Indicates a lock overflow (overlocking) condition occurred. Set by hardware on an
overlocking condition, and remains set until cleared by software writing 0 to this bit location.
55
CLFC
Cache lock bits flash clear. When written to a 1, a cache lock bits flash clear operation is initiated by
hardware. Once complete, this bit is reset to 0. Writing a 1 while a flash clear operation is in progress results
in an undefined operation. Writing a 0 to this bit while a flash clear operation is in progress has no effect.
Cache lock bits flash clear operations require approximately 134 cycles to complete. Clearing occurs
regardless of the enable (CE) value.
56–60
—
61
CABT
Cache operation aborted. Indicates a cache invalidate or a cache lock bits flash clear operation was aborted
prior to completion. Set by hardware on an aborted condition, and remains set until cleared by software
writing 0 to this bit location.
62
CINV
Cache invalidate
0 No cache invalidate
1 Cache invalidation operation
When written to a 1, a cache invalidation operation is initiated by hardware. Then invalidation is complete,
CINV is reset to 0. Writing a 1 while invalidation is in progress causes an undefined operation. Writing a 0
to this bit while an invalidation operation is in progress is ignored. Cache invalidation operations require
approximately 134 cycles to complete. Invalidation occurs regardless of the enable (CE) value.
63
CE
Cache enable. When disabled, cache lookups are not performed for normal load or store accesses.
Other L1CSR0 cache control operations are still available. Also, store buffer operation is not affected by CE.
0 Cache is disabled
1 Cache is enabled
Reserved, should be cleared.
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
4
Freescale Semiconductor
Add the following at the end of Section 3.9.2:1
Table 3-11 lists all supported instructions, including VLE instructions. Note that
only the e200z6 with VLE supports the instructions defined by the VLE, which
are designated with the prefixes, e_ and se_.
3.9.2, 3-33
Table 3-11. Full Instruction Listing
Mnemonic
Instruction Name
Source
add
Add
Book E
add.
Add & record CR
Book E
addc
Add Carrying
Book E
addc.
Add Carrying & record CR
Book E
addco
Add Carrying & record OV
Book E
addco.
Add Carrying & record OV & CR
Book E
adde
Add Extended with CA
Book E
adde.
Add Extended with CA & record CR
Book E
addeo
Add Extended with CA & record OV
Book E
addeo.
Add Extended with CA & record OV & CR
Book E
addi
Add Immediate
Book E
addic
Add Immediate Carrying
Book E
addic.
Add Immediate Carrying & record CR
Book E
addis
Add Immediate Shifted
Book E
addme
Add to Minus One Extended with CA
Book E
addme.
Add to Minus One Extended with CA & record CR
Book E
addmeo
Add to Minus One Extended with CA & record OV
Book E
addmeo.
Add to Minus One Extended with CA & record OV & CR
Book E
addo
Add & record OV
Book E
addo.
Add & record OV & CR
Book E
addze
Add to Zero Extended with CA
Book E
addze.
Add to Zero Extended with CA & record CR
Book E
addzeo
Add to Zero Extended with CA & record OV
Book E
addzeo.
Add to Zero Extended with CA & record OV & CR
Book E
and
AND
Book E
and.
AND & record CR
Book E
andc
AND with Complement
Book E
andc.
AND with Complement & record CR
Book E
andi.
AND Immediate and record CR
Book E
1. Note that this change appeared in Revision 0.1 of the addendum but the source for instructions designated with the prefixes
e_ and se_ in Table 3-11 has been updated since then.
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
5
Table 3-11. Full Instruction Listing (continued)
Mnemonic
andis.
Instruction Name
Source
AND Immediate Shifted and record CR
Book E
b
Branch
Book E
ba
Branch Absolute
Book E
bc
Branch Conditional
Book E
bca
Branch Conditional Absolute
Book E
bcctr
Branch Conditional to Count Register
Book E
bcctrl
Branch Conditional to Count Register and Link
Book E
bcl
Branch Conditional and Link
Book E
bcla
Branch Conditional and Link Absolute
Book E
bclr
Branch Conditional to Link Register
Book E
bclrl
Branch Conditional to Link Register and Link
Book E
bl
Branch and Link
Book E
bla
Branch and Link Absolute
Book E
Increment1
brinc
Bit Reversed
cmp
Compare
Book E
cmpi
Compare Immediate
Book E
cmpl
Compare Logical
Book E
cmpli
Compare Logical Immediate
Book E
cntlzw
Count Leading Zeros Word
Book E
cntlzw.
Count Leading Zeros Word and record CR
Book E
crand
Condition Register AND
Book E
crandc
Condition Register AND with Complement
Book E
Condition Register Equivalent
Book E
Condition Register NAND
Book E
Condition Register NOR
Book E
cror
Condition Register OR
Book E
crorc
Condition Register OR with Complement
Book E
crxor
Condition Register XOR
Book E
dcba
Data Cache Block Allocate
Book E
dcbf
Data Cache Block Flush
Book E
dcbi
Data Cache Block Invalidate
Book E
dcblc
Data Cache Block Lock Clear
Cache locking
dcbst
Data Cache Block Store
Book E
dcbt
Data Cache Block Touch
Book E
creqv
crnand
crnor
dcbtls
Data Cache Block Touch and Lock Set
SPE
Cache locking
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
6
Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
dcbtst
dcbtstls
Instruction Name
Data Cache Block Touch for Store
Data Cache Block Touch for Store and Lock Set
Source
Book E
Cache locking
dcbz
Data Cache Block set to Zero
Book E
divw
Divide Word
Book E
divw.
Divide Word and record CR
Book E
divwo
Divide Word and record OV
Book E
divwo.
Divide Word and record OV and CR
Book E
divwu
Divide Word Unsigned
Book E
divwu.
Divide Word Unsigned and record CR
Book E
divwuo
Divide Word Unsigned and record OV
Book E
divwuo.
Divide Word Unsigned and record OV and CR
Book E
efsabs
Floating-Point Absolute Value
Scalar SPFP
efsadd
Floating-Point Add
Scalar SPFP
efscfsf
Convert Floating-Point from Signed Fraction
Scalar SPFP
efscfsi
Convert Floating-Point from Signed Integer
Scalar SPFP
efscfuf
Convert Floating-Point from Unsigned Fraction
Scalar SPFP
efscfui
Convert Floating-Point from Unsigned Integer
Scalar SPFP
efscmpeq
Floating-Point Compare Equal
Scalar SPFP
efscmpgt
Floating-Point Compare Greater Than
Scalar SPFP
efscmplt
Floating-Point Compare Less Than
Scalar SPFP
efsctsf
Convert Floating-Point to Signed Fraction
Scalar SPFP
efsctsi
Convert Floating-Point to Signed Integer
Scalar SPFP
efsctsiz
Convert Floating-Point to Signed Integer with Round toward Zero
Scalar SPFP
efsctuf
Convert Floating-Point to Unsigned Fraction
Scalar SPFP
efsctui
Convert Floating-Point to Unsigned Integer
Scalar SPFP
efsctuiz
Convert Floating-Point to Unsigned Integer with Round toward Zero
Scalar SPFP
efsdiv
Floating-Point Divide
Scalar SPFP
efsmul
Floating-Point Multiply
Scalar SPFP
efsnabs
Floating-Point Negative Absolute Value
Scalar SPFP
efsneg
Floating-Point Negate
Scalar SPFP
efssub
Floating-Point Subtract
Scalar SPFP
efststeq
Floating-Point Test Equal
Scalar SPFP
efststgt
Floating-Point Test Greater Than
Scalar SPFP
efststlt
Floating-Point Test Less Than
Scalar SPFP
eqv
Equivalent
Book E
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
7
Table 3-11. Full Instruction Listing (continued)
Mnemonic
eqv.
evabs
evaddiw
Instruction Name
Equivalent and record CR
Source
Book E
Vector Absolute Value
SPE
Vector Add Immediate Word
SPE
evaddsmiaaw Vector Add Signed, Modulo, Integer to Accumulator Word
SPE
evaddssiaaw
SPE
Vector Add Signed, Saturate, Integer to Accumulator Word
evaddumiaaw Vector Add Unsigned, Modulo, Integer to Accumulator Word
SPE
evaddusiaaw
Vector Add Unsigned, Saturate, Integer to Accumulator Word
SPE
Vector Add Word
SPE
evand
Vector AND
SPE
evandc
Vector AND with Complement
SPE
evcmpeq
Vector Compare Equal
SPE
evcmpgts
Vector Compare Greater Than Signed
SPE
evcmpgtu
Vector Compare Greater Than Unsigned
SPE
evcmplts
Vector Compare Less Than Signed
SPE
evcmpltu
Vector Compare Less Than Unsigned
SPE
evcntlsw
Vector Count Leading Sign Bits Word
SPE
evcntlzw
Vector Count Leading Zeros Word
SPE
evdivws
Vector Divide Word Signed
SPE
evdivwu
Vector Divide Word Unsigned
SPE
Vector Equivalent
SPE
evextsb
Vector Extend Sign Byte
SPE
evextsh
Vector Extend Sign Half Word
SPE
evfsabs
Vector Floating-Point Absolute Value
SPE
evfsabs
Floating-Point Absolute Value
evfsadd
Vector Floating-Point Add
evfsadd
Floating-Point Add
evfscfsf
Vector Convert Floating-Point from Signed Fraction
evfscfsf
Convert Floating-Point from Signed Fraction
evfscfsi
Vector Convert Floating-Point from Signed Integer
evfscfsi
Convert Floating-Point from Signed Integer
evfscfuf
Vector Convert Floating-Point from Unsigned Fraction
evfscfuf
Convert Floating-Point from Unsigned Fraction
evfscfui
Vector Convert Floating-Point from Unsigned Integer
evfscfui
Convert Floating-Point from Unsigned Integer
evaddw
eveqv
evfscmpeq
Vector Floating-Point Compare Equal
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
8
Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
evfscmpeq
Floating-Point Compare Equal
evfscmpgt
Vector Floating-Point Compare Greater Than
evfscmpgt
Floating-Point Compare Greater Than
evfscmplt
Vector Floating-Point Compare Less Than
evfscmplt
Floating-Point Compare Less Than
evfsctsf
Vector Convert Floating-Point to Signed Fraction
evfsctsf
Convert Floating-Point to Signed Fraction
evfsctsi
Vector Convert Floating-Point to Signed Integer
evfsctsi
Convert Floating-Point to Signed Integer
evfsctsiz
Vector Convert Floating-Point to Signed Integer with Round toward Zero
evfsctsiz
Convert Floating-Point to Signed Integer with Round toward Zero
evfsctuf
Vector Convert Floating-Point to Unsigned Fraction
evfsctuf
Convert Floating-Point to Unsigned Fraction
evfsctui
Vector Convert Floating-Point to Unsigned Integer
evfsctui
Convert Floating-Point to Unsigned Integer
evfsctuiz
Vector Convert Floating-Point to Unsigned Integer with Round toward Zero
evfsctuiz
Convert Floating-Point to Unsigned Integer with Round toward Zero
evfsdiv
Vector Floating-Point Divide
evfsdiv
Floating-Point Divide
evfsmul
Vector Floating-Point Multiply
evfsmul
Floating-Point Multiply
evfsnabs
Vector Floating-Point Negative Absolute Value
evfsnabs
Floating-Point Negative Absolute Value
evfsneg
Vector Floating-Point Negate
evfsneg
Floating-Point Negate
evfssub
Vector Floating-Point Subtract
evfssub
Floating-Point Subtract
evfststeq
Vector Floating-Point Test Equal
evfststeq
Floating-Point Test Equal
evfststgt
Vector Floating-Point Test Greater Than
evfststgt
Floating-Point Test Greater Than
evfststlt
Vector Floating-Point Test Less Than
evfststlt
Floating-Point Test Less Than
Source
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
SPE
Vector SPFP
evldd
Vector Load Double Word into Double Word
SPE
evlddx
Vector Load Double Word into Double Word Indexed
SPE
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
9
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
evldh
Vector Load Double into Half Words
SPE
evldhx
Vector Load Double into Half Words Indexed
SPE
evldw
Vector Load Double into Two Words
SPE
evldwx
Vector Load Double into Two Words Indexed
SPE
evlhhesplat
Vector Load Half Word into Half Words Even and Splat
SPE
evlhhesplatx
Vector Load Half Word into Half Words Even and Splat Indexed
SPE
evlhhossplat
Vector Load Half Word into Half Word Odd Signed and Splat
SPE
evlhhossplatx Vector Load Half Word into Half Word Odd Signed and Splat Indexed
SPE
evlhhousplat
SPE
Vector Load Half Word into Half Word Odd Unsigned and Splat
evlhhousplatx Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed
SPE
evlwhe
Vector Load Word into Two Half Words Even
SPE
evlwhex
Vector Load Word into Two Half Words Even Indexed
SPE
evlwhos
Vector Load Word into Half Words Odd Signed (with sign extension)
SPE
evlwhosx
Vector Load Word into Half Words Odd Signed Indexed (with sign extension)
SPE
evlwhou
Vector Load Word into Two Half Words Odd Unsigned (zero-extended)
SPE
evlwhoux
Vector Load Word into Two Half Words Odd Unsigned Indexed (zero-extended)
SPE
evlwhsplat
Vector Load Word into Half Words and Splat
SPE
evlwhsplatx
Vector Load Word into Half Words and Splat Indexed
SPE
evlwwsplat
Vector Load Word into Word and Splat
SPE
evlwwsplatx
Vector Load Word into Word and Splat Indexed
SPE
Vector Merge High
SPE
Vector Merge High/Low
SPE
Vector Merge Low
SPE
Vector Merge Low/High
SPE
evmergehi
evmergehilo
evmergelo
evmergelohi
evmhegsmfaa Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate
SPE
evmhegsmfan Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate
Negative
SPE
evmhegsmiaa Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate
SPE
evmhegsmian Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate
Negative
SPE
evmhegumiaa Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate
SPE
evmhegumian Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate
Negative
SPE
evmhesmf
Vector Multiply Half Words, Even, Signed, Modulo, Fractional
SPE
evmhesmfa
Vector Multiply Half Words, Even, Signed, Modulo, Fractional, Accumulate
SPE
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
10
Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
evmhesmfaaw Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate into
Words
SPE
evmhesmfanw Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate
Negative into Words
SPE
evmhesmi
Vector Multiply Half Words, Even, Signed, Modulo, Integer
SPE
evmhesmia
Vector Multiply Half Words, Even, Signed, Modulo, Integer, Accumulate
SPE
evmhesmiaaw Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate into Words
SPE
evmhesmianw Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate Negative
into Words
SPE
evmhessf
Vector Multiply Half Words, Even, Signed, Saturate, Fractional
SPE
evmhessfa
Vector Multiply Half Words, Even, Signed, Saturate, Fractional, Accumulate
SPE
evmhessfaaw Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate into
Words
SPE
evmhessfanw Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate
Negative into Words
SPE
evmhessiaaw Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate into
Words
SPE
evmhessianw Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate Negative
into Words
SPE
evmheumi
Vector Multiply Half Words, Even, Unsigned, Modulo, Integer
SPE
evmheumia
Vector Multiply Half Words, Even, Unsigned, Modulo, Integer, Accumulate
SPE
evmheumiaaw Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate into
Words
SPE
evmheumianw Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate
Negative into Words
SPE
evmheusiaaw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate into
Words
SPE
evmheusianw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate
Negative into Words
SPE
evmhogsmfaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate
SPE
evmhogsmfan Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate
Negative
SPE
evmhogsmiaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate
SPE
evmhogsmian Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate
Negative
SPE
evmhogumiaa Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate
SPE
evmhogumian Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate
Negative
SPE
evmhosmf
Vector Multiply Half Words, Odd, Signed, Modulo, Fractional
SPE
evmhosmfa
Vector Multiply Half Words, Odd, Signed, Modulo, Fractional, Accumulate
SPE
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
11
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
evmhosmfaaw Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and Accumulate into
Words
SPE
evmhosmfanw Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and Accumulate
Negative into Words
SPE
evmhosmi
Vector Multiply Half Words, Odd, Signed, Modulo, Integer
SPE
evmhosmia
Vector Multiply Half Words, Odd, Signed, Modulo, Integer, Accumulate
SPE
evmhosmiaaw Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate into Words
SPE
evmhosmianw Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate Negative
into Words
SPE
evmhossf
Vector Multiply Half Words, Odd, Signed, Saturate, Fractional
SPE
evmhossfa
Vector Multiply Half Words, Odd, Signed, Saturate, Fractional, Accumulate
SPE
evmhossfaaw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate into
Words
SPE
evmhossfanw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate
Negative into Words
SPE
evmhossiaaw Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate into Words
SPE
evmhossianw Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate Negative
into Words
SPE
evmhoumi
Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer
SPE
evmhoumia
Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer, Accumulate
SPE
evmhoumiaaw Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate into
Words
SPE
evmhoumianw Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate Negative
into Words
SPE
evmhousiaaw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate into
Words
SPE
evmhousianw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate
Negative into Words
SPE
evmra
Initialize Accumulator
SPE
evmwhsmf
Vector Multiply Word High Signed, Modulo, Fractional
SPE
evmwhsmfa
Vector Multiply Word High Signed, Modulo, Fractional and Accumulate
SPE
evmwhsmi
Vector Multiply Word High Signed, Modulo, Integer
SPE
evmwhsmia
Vector Multiply Word High Signed, Modulo, Integer and Accumulate
SPE
evmwhssf
Vector Multiply Word High Signed, Saturate, Fractional
SPE
evmwhssfa
Vector Multiply Word High Signed, Saturate, Fractional and Accumulate
SPE
evmwhumi
Vector Multiply Word High Unsigned, Modulo, Integer
SPE
evmwhumia
Vector Multiply Word High Unsigned, Modulo, Integer and Accumulate
SPE
Vector Multiply Word Low Unsigned, Modulo, Integer
SPE
evmwlsmi
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
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Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
evmwlsmiaaw Vector Multiply Word Low Signed, Modulo, Integer and Accumulate in Words
SPE
evmwlsmianw Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words
SPE
evmwlssiaaw
Vector Multiply Word Low Signed, Saturate, Integer and Accumulate in Words
SPE
evmwlssianw
Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in
Words
SPE
Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate
SPE
evmwlumia
evmwlumiaaw Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate in Words
SPE
evmwlumianw Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in
Words
SPE
evmwlusiaaw Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate in Words
SPE
evmwlusianw Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in
Words
SPE
evmwsmf
Vector Multiply Word Signed, Modulo, Fractional
SPE
evmwsmfa
Vector Multiply Word Signed, Modulo, Fractional and Accumulate
SPE
evmwsmfaa
Vector Multiply Word Signed, Modulo, Fractional and Accumulate
SPE
evmwsmfan
Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative
SPE
evmwsmi
Vector Multiply Word Signed, Modulo, Integer
SPE
evmwsmia
Vector Multiply Word Signed, Modulo, Integer and Accumulate
SPE
evmwsmiaa
Vector Multiply Word Signed, Modulo, Integer and Accumulate
SPE
evmwsmian
Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative
SPE
evmwssf
Vector Multiply Word Signed, Saturate, Fractional
SPE
evmwssfa
Vector Multiply Word Signed, Saturate, Fractional and Accumulate
SPE
evmwssfaa
Vector Multiply Word Signed, Saturate, Fractional and Accumulate
SPE
evmwssfan
Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative
SPE
evmwumi
Vector Multiply Word Unsigned, Modulo, Integer
SPE
evmwumia
Vector Multiply Word Unsigned, Modulo, Integer and Accumulate
SPE
evmwumiaa
Vector Multiply Word Unsigned, Modulo, Integer and Accumulate
SPE
evmwumian
Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative
SPE
evnand
Vector NAND
SPE
evneg
Vector Negate
SPE
evnor
Vector NOR
SPE
evor
Vector OR
SPE
evorc
Vector OR with Complement
SPE
evrlw
Vector Rotate Left Word
SPE
evrlwi
Vector Rotate Left Word Immediate
SPE
Vector Round Word
SPE
evrndw
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
13
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
evsel
Vector Select
SPE
evslw
Vector Shift Left Word
SPE
evslwi
Vector Shift Left Word Immediate
SPE
evsplatfi
Vector Splat Fractional Immediate
SPE
evsplati
Vector Splat Immediate
SPE
evsrwis
Vector Shift Right Word Immediate Signed
SPE
evsrwiu
Vector Shift Right Word Immediate Unsigned
SPE
evsrws
Vector Shift Right Word Signed
SPE
evsrwu
Vector Shift Right Word Unsigned
SPE
evstdd
Vector Store Double of Double
SPE
evstddx
Vector Store Double of Double Indexed
SPE
evstdh
Vector Store Double of Four Half Words
SPE
evstdhx
Vector Store Double of Four Half Words Indexed
SPE
evstdw
Vector Store Double of Two Words
SPE
evstdwx
Vector Store Double of Two Words Indexed
SPE
evstwhe
Vector Store Word of Two Half Words from Even
SPE
evstwhex
Vector Store Word of Two Half Words from Even Indexed
SPE
evstwho
Vector Store Word of Two Half Words from Odd
SPE
evstwhox
Vector Store Word of Two Half Words from Odd Indexed
SPE
evstwwe
Vector Store Word of Word from Even
SPE
evstwwex
Vector Store Word of Word from Even Indexed
SPE
evstwwo
Vector Store Word of Word from Odd
SPE
evstwwox
Vector Store Word of Word from Odd Indexed
SPE
evsubfsmiaaw Vector Subtract Signed, Modulo, Integer to Accumulator Word
SPE
evsubfssiaaw Vector Subtract Signed, Saturate, Integer to Accumulator Word
SPE
evsubfumiaaw Vector Subtract Unsigned, Modulo, Integer to Accumulator Word
SPE
evsubfusiaaw Vector Subtract Unsigned, Saturate, Integer to Accumulator Word
SPE
evsubfw
Vector Subtract from Word
SPE
evsubifw
Vector Subtract Immediate from Word
SPE
evxor
Vector XOR
SPE
extsb
Extend Sign Byte
Book E
extsb.
Extend Sign Byte and record CR
Book E
extsh
Extend Sign Half Word
Book E
extsh.
Extend Sign Half Word and record CR
Book E
e_add16i
Add Immediate
VLE (32-bit opcodes)
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
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Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
e_add2i.
Add (2 operand) Immediate and Record CR
VLE (32-bit opcodes)
e_add2is
Add (2 operand) Immediate Shifted
VLE (32-bit opcodes)
e_addi
Add Immediate
VLE (32-bit opcodes)
e_addi.
Add Immediate and Record
VLE (32-bit opcodes)
e_addic
Add Immediate Carrying
VLE (32-bit opcodes)
e_addic.
Add Immediate Carrying and Record
VLE (32-bit opcodes)
e_and2i.
AND (2 operand) Immediate & record CR
VLE (32-bit opcodes)
e_and2is.
AND (2 operand) Immediate Shifted & record CR
VLE (32-bit opcodes)
e_andi
AND Immediate
VLE (32-bit opcodes)
e_andi.
AND Immediate and Record
VLE (32-bit opcodes)
e_b
Branch
VLE (32-bit opcodes)
e_bc
Branch Conditional
VLE (32-bit opcodes)
e_bcl
Branch Conditional & Link
VLE (32-bit opcodes)
e_bl
Branch & Link
VLE (32-bit opcodes)
Compare Immediate
VLE (32-bit opcodes)
Compare Halfword
VLE (32-bit opcodes)
Compare Halfword Immediate
VLE (32-bit opcodes)
Compare Halfword Logical
VLE (32-bit opcodes)
Compare Halfword Logical Immediate
VLE (32-bit opcodes)
Compare Immediate
VLE (32-bit opcodes)
e_cmpl16i
Compare Logical Immediate
VLE (32-bit opcodes)
e_cmpli
Compare Logical Immediate
VLE (32-bit opcodes)
e_crand
Condition Register AND
VLE (32-bit opcodes)
e_crandc
Condition Register AND with Complement
VLE (32-bit opcodes)
e_creqv
Condition Register Equivalent
VLE (32-bit opcodes)
Condition Register NAND
VLE (32-bit opcodes)
Condition Register NOR
VLE (32-bit opcodes)
e_cror
Condition Register OR
VLE (32-bit opcodes)
e_crorc
Condition Register OR with Complement
VLE (32-bit opcodes)
e_crxor
Condition Register XOR
VLE (32-bit opcodes)
Load Byte & Zero
VLE (32-bit opcodes)
e_lbzu
Load Byte & Zero with Update
VLE (32-bit opcodes)
e_lha
Load Halfword Algebraic
VLE (32-bit opcodes)
Load Halfword Algebraic With Update
VLE (32-bit opcodes)
Load Halfword & Zero
VLE (32-bit opcodes)
e_cmp16i
e_cmph
e_cmph16i
e_cmphl
e_cmphl16i
e_cmpi
e_crnand
e_crnor
e_lbz
e_lhau
e_lhz
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
15
Table 3-11. Full Instruction Listing (continued)
Mnemonic
e_lhzu
Instruction Name
Source
Load Halfword & Zero with Update
VLE (32-bit opcodes)
e_li
Load Immediate
VLE (32-bit opcodes)
e_lis
Load Immediate Shifted
VLE (32-bit opcodes)
e_lmw
Load Multiple Word
VLE (32-bit opcodes)
e_lwz
Load Word & Zero
VLE (32-bit opcodes)
e_lwzu
Load Word & Zero with Update
VLE (32-bit opcodes)
e_mcrf
Move Condition Register Field
VLE (32-bit opcodes)
e_mull2i
Multiply Low Word (2 operand) Immediate
VLE (32-bit opcodes)
e_mulli
Multiply Low Immediate
VLE (32-bit opcodes)
e_or2i
OR (2 operand) Immediate
VLE (32-bit opcodes)
e_or2is
OR (2 operand) Immediate Shifted
VLE (32-bit opcodes)
e_ori
OR Immediate
VLE (32-bit opcodes)
e_ori.
OR Immediate and Record
VLE (32-bit opcodes)
e_rlw
Rotate Left Word
VLE (32-bit opcodes)
e_rlw.
Rotate Left Word & record CR
VLE (32-bit opcodes)
e_rlwi
Rotate Left Word Immediate
VLE (32-bit opcodes)
e_rlwi.
Rotate Left Word Immediate & record CR
VLE (32-bit opcodes)
e_rlwimi
Rotate Left Word Immed then Mask Insert
VLE (32-bit opcodes)
e_rlwinm
Rotate Left Word Immed then AND with Mask
VLE (32-bit opcodes)
e_slwi
Shift Left Word Immediate
VLE (32-bit opcodes)
e_slwi.
Shift Left Word Immediate & record CR
VLE (32-bit opcodes)
e_srwi
Shift Right Word Immediate
VLE (32-bit opcodes)
e_srwi.
Shift Right Word Immediate & record CR
VLE (32-bit opcodes)
e_stb
Store Byte
VLE (32-bit opcodes)
e_stbu
Store Byte with Update
VLE (32-bit opcodes)
e_sth
Store Halfword
VLE (32-bit opcodes)
e_sthu
Store Halfword with Update
VLE (32-bit opcodes)
e_stmw
Store Multiple Word
VLE (32-bit opcodes)
Store Word
VLE (32-bit opcodes)
Store Word with Update
VLE (32-bit opcodes)
e_subfic
Subtract from Immediate Carrying
VLE (32-bit opcodes)
e_subfic.
Subtract from Immediate and Record
VLE (32-bit opcodes)
e_xori
XOR Immediate
VLE (32-bit opcodes)
e_xori.
XOR Immediate and Record
VLE (32-bit opcodes)
e_stw
e_stwu
icbi
Instruction Cache Block Invalidate
Book E
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
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Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
icblc
Instruction Cache Block Lock Clear
icbt
Instruction Cache Block Touch
icbtls
Instruction Cache Block Touch and Lock Set
isel
Integer Select
isync
Source
Cache locking
Book E
Cache locking
EIS
Instruction Synchronize
Book E
Load Byte and Zero
Book E
lbzu
Load Byte and Zero with Update
Book E
lbzux
Load Byte and Zero with Update Indexed
Book E
lbzx
Load Byte and Zero Indexed
Book E
lha
Load Half Word Algebraic
Book E
lhau
Load Half Word Algebraic with Update
Book E
lhaux
Load Half Word Algebraic with Update Indexed
Book E
lhax
Load Half Word Algebraic Indexed
Book E
lhbrx
Load Half Word Byte-Reverse Indexed
Book E
Load Half Word and Zero
Book E
lhzu
Load Half Word and Zero with Update
Book E
lhzux
Load Half Word and Zero with Update Indexed
Book E
lhzx
Load Half Word and Zero Indexed
Book E
lmw
Load Multiple Word
Book E
lwarx
Load Word and Reserve Indexed
Book E
lwbrx
Load Word Byte-Reverse Indexed
Book E
Load Word and Zero
Book E
lwzu
Load Word and Zero with Update
Book E
lwzux
Load Word and Zero with Update Indexed
Book E
lwzx
Load Word and Zero Indexed
Book E
Memory Barrier
Book E
mcrf
Move Condition Register Field
Book E
mcrxr
Move to Condition Register from XER
Book E
mfcr
Move From Condition Register
Book E
Move From Device Control Register
Book E
Move From Device Control Register Indexed
Book E
mfmsr
Move From Machine State Register
Book E
mfspr
Move From Special Purpose Register
Book E
Memory Synchronize
Book E
Move To Condition Register Fields
Book E
lbz
lhz
lwz
mbar 2
mfdcr3
mfdcrx
3
msync 2
mtcrf
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
17
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
mtdcr3
Move To Device Control Register
Book E
mtdcrx3
Move To Device Control Register Indexed
Book E
mtmsr
Move To Machine State Register
Book E
mtspr
Move To Special Purpose Register
Book E
mulhw
Multiply High Word
Book E
mulhw.
Multiply High Word and record CR
Book E
mulhwu
Multiply High Word Unsigned
Book E
mulhwu.
Multiply High Word Unsigned and record CR
Book E
mulli
Multiply Low Immediate
Book E
mullw
Multiply Low Word
Book E
mullw.
Multiply Low Word and record CR
Book E
mullwo
Multiply Low Word and record OV
Book E
mullwo.
Multiply Low Word and record OV and CR
Book E
nand
NAND
Book E
nand.
NAND and record CR
Book E
neg
Negate
Book E
neg.
Negate and record CR
Book E
nego
Negate and record OV
Book E
nego.
Negate and record OV and record CR
Book E
nor
NOR
Book E
nor.
NOR and record CR
Book E
or
OR
Book E
or.
OR and record CR
Book E
orc
OR with Complement
Book E
orc.
OR with Complement and record CR
Book E
ori
OR Immediate
Book E
oris
OR Immediate Shifted
Book E
rfci
Return From Critical Interrupt
Book E
rfdi
Return From Debug Interrupt
Debug
rfi
Return From Interrupt
Book E
rlwimi
Rotate Left Word Immed then Mask Insert
Book E
rlwimi.
Rotate Left Word Immed then Mask Insert and record CR
Book E
rlwinm
Rotate Left Word Immed then AND with Mask
Book E
rlwinm.
Rotate Left Word Immed then AND with Mask and record CR
Book E
rlwnm
Rotate Left Word then AND with Mask
Book E
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
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Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
rlwnm.
sc
Instruction Name
Source
Rotate Left Word then AND with Mask and record CR
Book E
System Call
Book E
se_add
Add
VLE (16-bit opcodes)
se_addi
Add Immediate
VLE (16-bit opcodes)
se_and
AND
VLE (16-bit opcodes)
se_and.
AND and Record
VLE (16-bit opcodes)
se_andc
AND with Complement
VLE (16-bit opcodes)
se_andi
And Immediate
VLE (16-bit opcodes)
se_b
Branch
VLE (16-bit opcodes)
se_bc
Branch Conditional
VLE (16-bit opcodes)
se_bclri
Bit Clear Immediate
VLE (16-bit opcodes)
se_bctr
Branch to Count Register
VLE (16-bit opcodes)
se_bctrl
Branch to Count Register & Link
VLE (16-bit opcodes)
se_bgeni
Bit Generate Immediate
VLE (16-bit opcodes)
se_bl
Branch and Link
VLE (16-bit opcodes)
se_blr
Branch to Link Register
VLE (16-bit opcodes)
se_blrl
Branch to Link Register & Link
VLE (16-bit opcodes)
se_bmaski
Bit Mask Generate Immediate
VLE (16-bit opcodes)
se_bseti
Bit Set Immediate
VLE (16-bit opcodes)
se_btsti
Bit Test Immediate
VLE (16-bit opcodes)
se_cmp
Compare
VLE (16-bit opcodes)
se_cmph
Compare Halfword
VLE (16-bit opcodes)
se_cmphl
Compare Halfword Logical
VLE (16-bit opcodes)
se_cmpi
Compare Immediate
VLE (16-bit opcodes)
se_cmpl
Compare Logical
VLE (16-bit opcodes)
se_cmpli
Compare Logical Immediate
VLE (16-bit opcodes)
se_extsb
Extend Sign Byte
VLE (16-bit opcodes)
se_extsh
Extend Sign Halfword
VLE (16-bit opcodes)
se_extzb
Extend with Zeros Byte
VLE (16-bit opcodes)
se_extzh
Extend with Zeros Halfword
VLE (16-bit opcodes)
se_illegal
Illegal
VLE (16-bit opcodes)
se_isync
Instruction Synchronize
VLE (16-bit opcodes)
se_lbz
Load Byte and Zero
VLE (16-bit opcodes)
se_lhz
Load Halfword and Zero
VLE (16-bit opcodes)
Load Immediate
VLE (16-bit opcodes)
se_li
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
19
Table 3-11. Full Instruction Listing (continued)
Mnemonic
se_lwz
Instruction Name
Source
Load Word and Zero
VLE (16-bit opcodes)
se_mfar
Move from Alternate Register
VLE (16-bit opcodes)
se_mfctr
Move From Count Register
VLE (16-bit opcodes)
se_mflr
Move From Link Register
VLE (16-bit opcodes)
Move Register
VLE (16-bit opcodes)
se_mtar
Move to Alternate Register
VLE (16-bit opcodes)
se_mtctr
Move To Count Register
VLE (16-bit opcodes)
se_mtlr
Move To Link Register
VLE (16-bit opcodes)
Multiply Low Word
VLE (16-bit opcodes)
se_neg
Negate
VLE (16-bit opcodes)
se_not
NOT
VLE (16-bit opcodes)
se_or
OR
VLE (16-bit opcodes)
se_rfci
Return From Critical Interrupt
VLE (16-bit opcodes)
se_rfdi
Return From Debug Interrupt
VLE (16-bit opcodes)
se_rfi
Return From Interrupt
VLE (16-bit opcodes)
se_sc
System Call
VLE (16-bit opcodes)
se_slw
Shift Left Word
VLE (16-bit opcodes)
se_slwi
Shift Left Word Immediate
VLE (16-bit opcodes)
se_sraw
Shift Right Algebraic Word
VLE (16-bit opcodes)
se_srawi
Shift Right Algebraic Word Immediate
VLE (16-bit opcodes)
se_srw
Shift Right Word
VLE (16-bit opcodes)
se_srwi
Shift Right Word Immediate
VLE (16-bit opcodes)
se_stb
Store Byte
VLE (16-bit opcodes)
se_sth
Store Halfword
VLE (16-bit opcodes)
se_stw
Store Word
VLE (16-bit opcodes)
se_sub
Subtract
VLE (16-bit opcodes)
se_subf
Subtract From
VLE (16-bit opcodes)
se_subi
Subtract Immediate
VLE (16-bit opcodes)
se_subi.
Subtract Immediate and Record
VLE (16-bit opcodes)
se_mr
se_mullw
slw
Shift Left Word
Book E
slw.
Shift Left Word and record CR
Book E
sraw
Shift Right Algebraic Word
Book E
sraw.
Shift Right Algebraic Word and record CR
Book E
srawi
Shift Right Algebraic Word Immediate
Book E
srawi.
Shift Right Algebraic Word Immediate and record CR
Book E
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
20
Freescale Semiconductor
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
srw
Shift Right Word
Book E
srw.
Shift Right Word and record CR
Book E
stb
Store Byte
Book E
stbu
Store Byte with Update
Book E
stbux
Store Byte with Update Indexed
Book E
stbx
Store Byte Indexed
Book E
sth
Store Half Word
Book E
Store Half Word Byte-Reverse Indexed
Book E
sthu
Store Half Word with Update
Book E
sthux
Store Half Word with Update Indexed
Book E
sthx
Store Half Word Indexed
Book E
stmw
Store Multiple Word
Book E
Store Word
Book E
stwbrx
Store Word Byte-Reverse Indexed
Book E
stwcx.
Store Word Conditional Indexed and record CR
Book E
stwu
Store Word with Update
Book E
stwux
Store Word with Update Indexed
Book E
stwx
Store Word Indexed
Book E
subf
Subtract From
Book E
subf.
Subtract From and record CR
Book E
subfc
Subtract From Carrying
Book E
subfc.
Subtract From Carrying and record CR
Book E
subfco
Subtract From Carrying and record OV
Book E
subfco.
Subtract From Carrying and record OV and CR
Book E
subfe
Subtract From Extended with CA
Book E
subfe.
Subtract From Extended with CA and record CR
Book E
subfeo
Subtract From Extended with CA and record OV
Book E
subfeo.
Subtract From Extended with CA and record OV and CR
Book E
Subtract From Immediate Carrying
Book E
subfme
Subtract From Minus One Extended with CA
Book E
subfme.
Subtract From Minus One Extended with CA and record CR
Book E
subfmeo
Subtract From Minus One Extended with CA and record OV
Book E
subfmeo.
Subtract From Minus One Extended with CA and record OV and CR
Book E
subfo
Subtract From and record OV
Book E
subfo.
Subtract From and record OV and CR
Book E
sthbrx
stw
subfic
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
21
Table 3-11. Full Instruction Listing (continued)
Mnemonic
Instruction Name
Source
subfze
Subtract From Zero Extended with CA
Book E
subfze.
Subtract From Zero Extended with CA and record CR
Book E
subfzeo
Subtract From Zero Extended with CA and record OV
Book E
subfzeo.
Subtract From Zero Extended with CA and record OV and CR
Book E
TLB Invalidate Virtual Address Indexed
Book E
tlbre
TLB Read Entry
Book E
tlbsx
TLB Search Indexed
Book E
tlbsync
TLB Synchronize
Book E
tlbwe
TLB Write Entry
Book E
tw
Trap Word
Book E
twi
Trap Word Immediate
Book E
wrtee
Write External Enable
Book E
wrteei
Write External Enable Immediate
Book E
xor
XOR
Book E
xor.
XOR and record CR
Book E
xori
XOR Immediate
Book E
xoris
XOR Immediate Shifted
Book E
tlbivax
1
An implementation can restrict the number of bits specified in a mask. Devices that implements 16-bit instructions are limited
to 16 bits, which allows the user to perform bit-reversed address computations for 65536-byte samples.
2 See Section 3.7, “Memory Synchronization and Reservation Instructions.”
3 The core CPU will take an illegal instruction exception for unsupported DCR values.
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
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Freescale Semiconductor
5.6.2, 5-10; 5.6.3, 5-13; and 5.6.4, 5-13
Add the following note to the ends of Sections 5.6.2, 5.6.3, and 5.6.4:
NOTE
If MSR[EE] = 0 and a transfer error occurs, a DSI or ISI is
taken rather than a machine check or checkstop, as defined by
the PowerPC architecture. Such transfer error conditions that
would cause either a DSI or ISI should only apply when
MSR[EE] = 1. This does not affect the e200z6 with VLE.
In case of such errors, one of the following is recommended:
•
•
11.3, 11-8
Treat the DSI/ISI as an unrecoverable exception and do not
return from interrupt handler, perform a reset instead.
If HID0[DCLREE]=1, check SRR1 in the DSI and ISI
handlers; if SRR1[EE] is set, the interrupt is recoverable
and code can return from the interrupt without an issue. If
SRR1[EE] is clear, treat the interrupt as non-recoverable
and code should not return from interrupt.
Added the following row to Table 11-5, “Event Code Encodings (TCODE = 33)”:
0100
Disabling Program Trace
Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
Freescale Semiconductor
23
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Document Number: e200z6RMAD
Rev. 0.2
10/2006
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