NXP MPC8275, MPC8280, MPC8270 Reference manual

NXP MPC8275, MPC8280, MPC8270 Reference manual

MPC8280 PowerQUICC™ II Family Reference Manual Supports

MPC8270 MPC8275 MPC8280 MPC8280RM Rev. 1, 12/2005

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Document Number: MPC8280RM Rev. 1, 12/2005

Part I—Overview

Overview G2_LE Core Memory Map

Part II—Configuration and Reset

System Interface Unit (SIU) Reset

Part III—The Hardware Interface

External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port

Part IV—Communications Processor Module

Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode Universal Serial Bus Controller Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) ATM Controller and AAL0, AAL1, and AAL5 ATM AAL1 Circuit Emulation Service ATM AAL2 Inverse Multiplexing for ATM (IMA)

I 1 2 3 II 4 5 27 28 29 30 31 32 33 34 14 15 16 17 18 19 20 21 22 23 24 25 26 III 6 7 8 9 10 11 12 13 IV

I 1 2 3 II 4 5 III IV 6 7 8 9 10 11 12 13 27 28 29 30 31 32 33 34 14 15 16 17 18 19 20 21 22 23 24 25 26 Part I—Overview

Overview G2_LE Core Memory Map

Part II—Configuration and Reset

System Interface Unit (SIU) Reset

Part III—The Hardware Interface

External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port

Part IV—Communications Processor Module

Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode Universal Serial Bus Controller Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) ATM Controller and AAL0, AAL1, and AAL5 ATM AAL1 Circuit Emulation Service ATM AAL2 Inverse Multiplexing for ATM (IMA)

ATM Transmission Convergence Layer Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I 2 C Controller Parallel I/O Ports Register Quick Reference Guide Revision History Glossary Index

35 36 37 38 39 40 41 A B GLO IND

35 36 37 38 39 40 41 A B GLO IND

ATM Transmission Convergence Layer Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I 2 C Controller Parallel I/O Ports Register Quick Reference Guide Revision History Glossary Index

1.1

1.2

1.2.1

1.2.2

1.2.3

1.3

1.3.1

1.4

1.5

1.6

1.6.1

1.6.2

1.7

1.7.1

1.7.1.1

1.7.1.2

1.7.1.3

1.7.1.4

1.7.1.5

1.7.1.6

1.7.2

1.7.2.1

Paragraph Number

Contents

Title

Contents About This Book

Page Number

Before Using this Manual—Important Note ................................................................ lxxxi Audience ....................................................................................................................... lxxxi

Organization................................................................................................................. lxxxii

Suggested Reading...................................................................................................... lxxxiv

Conventions ................................................................................................................. lxxxv

Acronyms and Abbreviations ..................................................................................... lxxxvi

PowerPC Architecture Terminology Conventions...................................................... lxxxix

Part I Overview

Chapter 1 Overview

Features ............................................................................................................................ 1-1

Architecture Overview..................................................................................................... 1-5

G2_LE Core ................................................................................................................. 1-6

System Interface Unit (SIU) ........................................................................................ 1-7 Communications Processor Module (CPM) ................................................................ 1-7

Software Compatibility Issues ......................................................................................... 1-8 Signals.......................................................................................................................... 1-8

Differences Between MPC860 and MPC8280 .............................................................. 1-10 Serial Protocol Table...................................................................................................... 1-10

MPC8280 Configurations .............................................................................................. 1-11 Pin Configurations ..................................................................................................... 1-11 Serial Performance..................................................................................................... 1-11

Application Examples.................................................................................................... 1-12 Communication Systems ........................................................................................... 1-12

Remote Access Server ........................................................................................... 1-13

Regional Office Router.......................................................................................... 1-14 LAN-to-WAN Bridge Router ................................................................................ 1-14

Cellular Base Station ............................................................................................. 1-15

Telecommunications Switch Controller ................................................................ 1-16

SONET Transmission Controller........................................................................... 1-17 Bus Configurations .................................................................................................... 1-17 Basic System.......................................................................................................... 1-17

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2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.4.1

2.2.4.2

2.2.4.3

2.2.4.4

2.2.5

2.2.6

2.2.6.1

2.2.6.2

2.3

2.3.1

2.3.1.1

2.3.1.2

2.3.1.2.1

2.3.1.2.2

2.3.1.2.3

2.3.1.2.4

2.3.2

2.3.2.1

2.3.2.2

2.3.2.3

2.4

2.4.1

2.4.2

2.4.2.1

2.4.2.2

2.4.2.3

Paragraph Number

1.7.2.2

1.7.2.3

1.7.2.4

1.7.2.5

1.7.2.6

Contents

Title Page Number

High-Performance Communication....................................................................... 1-18

High-Performance System Microprocessor........................................................... 1-19

PCI ......................................................................................................................... 1-20 PCI with 155-Mbps ATM ...................................................................................... 1-20

The MPC8280 as PCI Agent ................................................................................. 1-21

Chapter 2 G2_LE Core

Overview.......................................................................................................................... 2-1

G2_LE Core Features ..................................................................................................... 2-3

Instruction Unit ............................................................................................................ 2-5 Instruction Queue and Dispatch Unit........................................................................... 2-5

Branch Processing Unit (BPU) .................................................................................... 2-6 Independent Execution Units....................................................................................... 2-6 Integer Unit (IU) ...................................................................................................... 2-6 Floating-Point Unit (FPU) ....................................................................................... 2-6

Load/Store Unit (LSU) ............................................................................................ 2-7 System Register Unit (SRU).................................................................................... 2-7 Completion Unit .......................................................................................................... 2-7 Memory Subsystem Support........................................................................................ 2-7

Memory Management Units (MMUs)..................................................................... 2-8 Cache Units.............................................................................................................. 2-8 Programming Model ........................................................................................................ 2-8 Register Set .................................................................................................................. 2-8

PowerPC Register Set.............................................................................................. 2-9

MPC8280-Specific Registers................................................................................. 2-11 Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11

Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14 Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14

Processor Version Register (PVR)..................................................................... 2-15 PowerPC Instruction Set and Addressing Modes ...................................................... 2-15 Calculating Effective Addresses ............................................................................ 2-15

PowerPC Instruction Set........................................................................................ 2-16

MPC8280 Implementation-Specific Instruction Set.............................................. 2-17

Cache Implementation ................................................................................................... 2-18 PowerPC Cache Model.............................................................................................. 2-18 MPC8280 Implementation-Specific Cache Implementation ..................................... 2-18

Data Cache............................................................................................................. 2-19

Instruction Cache ................................................................................................... 2-20 Cache Locking ....................................................................................................... 2-20

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2.5.1

2.5.2

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2.6.2

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2.8

Contents

Title Page Number

Entire Cache Locking ........................................................................................ 2-20 Way Locking...................................................................................................... 2-20

Exception Model............................................................................................................ 2-21 PowerPC Exception Model........................................................................................ 2-21

Implementation-Specific Exception Model ............................................................... 2-22

Memory Management.................................................................................................... 2-25 PowerPC Memory Management................................................................................ 2-25 Implementation-Specific MMU Features .................................................................. 2-25

Instruction Timing.......................................................................................................... 2-26

Differences Between the MPC8280 G2_LE Embedded Core and the MPC603e............................................................................ 2-27

4.1

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.2

4.2.1

4.2.1.1

4.2.1.2

4.2.2

4.2.2.1

4.2.2.2

4.2.2.3

4.2.3

4.2.4

4.2.4.1

4.3

3.1

Chapter 3 Memory Map

Internal Memory Map ...................................................................................................... 3-2

Part II Configuration and Reset

Chapter 4 System Interface Unit (SIU)

System Configuration and Protection .............................................................................. 4-2

Bus Monitor ................................................................................................................. 4-3 Timers Clock................................................................................................................ 4-3

Time Counter (TMCNT).............................................................................................. 4-4

Periodic Interrupt Timer (PIT)..................................................................................... 4-5

Software Watchdog Timer ........................................................................................... 4-6

Interrupt Controller .......................................................................................................... 4-7

Interrupt Configuration ................................................................................................ 4-8

Machine Check Interrupt ......................................................................................... 4-9 INT Interrupt............................................................................................................ 4-9 Interrupt Source Priorities............................................................................................ 4-9

SCC, FCC, and MCC Relative Priority ................................................................. 4-12

PIT, TMCNT, PCI, and IRQ Relative Priority ...................................................... 4-13 Highest Priority Interrupt....................................................................................... 4-13 Masking Interrupt Sources......................................................................................... 4-13

Interrupt Vector Generation and Calculation ............................................................. 4-14

Port C External Interrupts ...................................................................................... 4-16

Programming Model ...................................................................................................... 4-17

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4.3.1

4.3.1.1

4.3.1.2

4.3.1.3

4.3.1.4

4.3.1.5

4.3.1.6

4.3.1.7

4.3.2

4.3.2.1

4.3.2.2

4.3.2.3

4.3.2.4

4.3.2.5

4.3.2.6

4.3.2.7

4.3.2.8

4.3.2.9

4.3.2.10

4.3.2.11

4.3.2.12

4.3.2.13

4.3.2.14

4.3.2.15

4.3.2.16

4.3.3

4.3.3.1

4.3.3.2

4.3.3.3

4.3.4

4.3.4.1

4.3.4.2

4.4

Contents

Title Page Number

Interrupt Controller Registers .................................................................................... 4-17 SIU Interrupt Configuration Register (SICR)........................................................ 4-17

SIU Interrupt Priority Register (SIPRR)................................................................ 4-18

CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) ............................. 4-19

SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ................................ 4-21

SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........................................ 4-22

SIU Interrupt Vector Register (SIVEC) ................................................................. 4-24

SIU External Interrupt Control Register (SIEXR)................................................. 4-25

System Configuration and Protection Registers ........................................................ 4-26 Bus Configuration Register (BCR)........................................................................ 4-26

60x Bus Arbiter Configuration Register (PPC_ACR)........................................... 4-29

60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)......................... 4-30

Local Bus Arbiter Configuration Register (LCL_ACR) ....................................... 4-31

Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL) .............. 4-32

SIU Module Configuration Register (SIUMCR)................................................... 4-33

Internal Memory Map Register (IMMR)............................................................... 4-36

System Protection Control Register (SYPCR) ...................................................... 4-37

Software Service Register (SWSR) ....................................................................... 4-38

60x Bus Transfer Error Status and Control Register 1 (TESCR1) ........................ 4-39

60x Bus Transfer Error Status and Control Register 2 (TESCR2) ........................ 4-41

Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)................. 4-42

Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)................. 4-43 Time Counter Status and Control Register (TMCNTSC)...................................... 4-43

Time Counter Register (TMCNT) ......................................................................... 4-44

Time Counter Alarm Register (TMCNTAL) ......................................................... 4-45

Periodic Interrupt Registers ....................................................................................... 4-46 Periodic Interrupt Status and Control Register (PISCR) ....................................... 4-46

Periodic Interrupt Timer Count Register (PITC) ................................................... 4-47

Periodic Interrupt Timer Register (PITR).............................................................. 4-48 PCI Control Registers ................................................................................................ 4-48

PCI Base Register (PCIBRx)................................................................................. 4-49

PCI Mask Register (PCIMSKx) ............................................................................ 4-50 SIU Pin Multiplexing..................................................................................................... 4-50

5.1

5.1.1

5.1.2

5.1.3

Chapter 5 Reset

Reset Causes .................................................................................................................... 5-1

Reset Actions ............................................................................................................... 5-2 Power-On Reset Flow .................................................................................................. 5-2

HRESET Flow ............................................................................................................. 5-3

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5.2

5.3

5.4

5.4.1

5.4.2

5.4.2.1

5.4.2.2

5.4.2.3

5.4.2.4

Contents

Title Page Number

SRESET Flow.............................................................................................................. 5-3

Reset Status Register (RSR) ............................................................................................ 5-4

Reset Mode Register (RMR) ........................................................................................... 5-5

Reset Configuration ......................................................................................................... 5-6

Hard Reset Configuration Word .................................................................................. 5-8

Hard Reset Configuration Examples ......................................................................... 5-10 Single MPC8280 with Default Configuration ....................................................... 5-10 Single MPC8280 Configured from Boot EPROM ................................................ 5-10

Multiple MPC8280s Configured from Boot EPROM ........................................... 5-11

Multiple MPC8280s in a System with No EPROM .............................................. 5-13

6.1

6.2

Part III The Hardware Interface

Chapter 6 External Signals

Functional Pinout ............................................................................................................. 6-1

Signal Descriptions .......................................................................................................... 6-2

7.1

7.2

7.2.1

7.2.1.1

7.2.1.1.1

7.2.1.1.2

7.2.1.2

7.2.1.2.1

7.2.1.2.2

7.2.1.3

7.2.1.3.1

7.2.1.3.2

7.2.2

7.2.2.1

7.2.2.1.1

7.2.2.2

7.2.3

7.2.3.1

Chapter 7 60x Signals

Signal Configuration........................................................................................................ 7-2 Signal Descriptions .......................................................................................................... 7-2

Address Bus Arbitration Signals.................................................................................. 7-3 Bus Request (BR)—Output ..................................................................................... 7-3 Address Bus Request (BR)—Output ................................................................... 7-3 Address Bus Request (BR)—Input...................................................................... 7-3

Bus Grant (BG)........................................................................................................ 7-4 Bus Grant (BG)—Input ....................................................................................... 7-4 Bus Grant (BG)—Output..................................................................................... 7-4

Address Bus Busy (ABB)........................................................................................ 7-5 Address Bus Busy (ABB)—Output..................................................................... 7-5 Address Bus Busy (ABB)—Input ....................................................................... 7-5 Address Transfer Start Signal ...................................................................................... 7-5 Transfer Start (TS) ................................................................................................... 7-5 Transfer Start (TS)—Output ................................................................................ 7-5

Transfer Start (TS)—Input....................................................................................... 7-6 Address Transfer Signals ............................................................................................. 7-6 Address Bus (A[0–31])............................................................................................ 7-6

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7.2.4.1

7.2.4.1.1

7.2.4.1.2

7.2.4.2

7.2.4.3

7.2.4.4

7.2.4.4.1

7.2.4.4.2

7.2.4.5

7.2.4.6

7.2.5

7.2.5.1

7.2.5.1.1

7.2.5.1.2

7.2.5.2

7.2.5.2.1

7.2.5.2.2

7.2.6

7.2.6.1

7.2.6.1.1

7.2.6.1.2

7.2.6.2

7.2.6.2.1

7.2.6.2.2

7.2.7

7.2.7.1

7.2.7.1.1

7.2.7.1.2

7.2.7.2

7.2.7.2.1

7.2.7.2.2

7.2.8

7.2.8.1

7.2.8.1.1

7.2.8.1.2

7.2.8.2

7.2.8.2.1

7.2.8.2.2

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Contents

Title Page Number

Address Bus (A[0–31])—Output......................................................................... 7-6

Address Bus (A[0–31])—Input ........................................................................... 7-7 Address Transfer Attribute Signals.............................................................................. 7-7 Transfer Type (TT[0–4]).......................................................................................... 7-7 Transfer Type (TT[0–4])—Output....................................................................... 7-7 Transfer Type (TT[0–4])—Input ......................................................................... 7-7 Transfer Size (TSIZ[0–3]) ....................................................................................... 7-7

Transfer Burst (TBST)............................................................................................. 7-8 Global (GBL)........................................................................................................... 7-8 Global (GBL)—Output........................................................................................ 7-8 Global (GBL)—Input .......................................................................................... 7-8

Caching-Inhibited (CI)—Output ............................................................................. 7-9 Write-Through (WT)—Output ................................................................................ 7-9 Address Transfer Termination Signals......................................................................... 7-9 Address Acknowledge (AACK) .............................................................................. 7-9 Address Acknowledge (AACK)—Output........................................................... 7-9

Address Acknowledge (AACK)—Input ........................................................... 7-10 Address Retry (ARTRY)........................................................................................ 7-10 Address Retry (ARTRY)—Output .................................................................... 7-10 Address Retry (ARTRY)—Input ....................................................................... 7-10

Data Bus Arbitration Signals ..................................................................................... 7-11 Data Bus Grant (DBG) .......................................................................................... 7-11 Data Bus Grant (DBG)—Input.......................................................................... 7-11 Data Bus Grant (DBG)—Output ....................................................................... 7-11

Data Bus Busy (DBB) ........................................................................................... 7-12 Data Bus Busy (DBB)—Output ........................................................................ 7-12 Data Bus Busy (DBB)—Input ........................................................................... 7-12 Data Transfer Signals................................................................................................. 7-12

Data Bus (D[0–63]) ............................................................................................... 7-13 Data Bus (D[0–63])—Output ............................................................................ 7-13 Data Bus (D[0–63])—Input............................................................................... 7-13 Data Bus Parity (DP[0–7])..................................................................................... 7-13

Data Bus Parity (DP[0–7])—Output ................................................................. 7-14 Data Bus Parity (DP[0–7])—Input .................................................................... 7-14 Data Transfer Termination Signals ............................................................................ 7-14 Transfer Acknowledge (TA) .................................................................................. 7-14

Transfer Acknowledge (TA)—Input ................................................................. 7-15 Transfer Acknowledge (TA)—Output............................................................... 7-15

Transfer Error Acknowledge (TEA)...................................................................... 7-16 Transfer Error Acknowledge (TEA)—Input ..................................................... 7-16 Transfer Error Acknowledge (TEA)—Output................................................... 7-16

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8.1

8.2

8.2.1

8.2.2

8.3

8.3.1

8.3.2

8.4

8.4.1

8.4.2

8.4.3

8.4.3.1

8.4.3.2

8.4.3.3

8.4.3.4

8.4.3.5

8.4.3.6

8.4.3.7

8.4.3.8

8.4.4

8.4.4.1

8.4.4.2

8.4.5

8.5

8.5.1

8.5.2

8.5.3

8.5.4

8.5.5

8.5.6

8.6

8.7

8.7.1

Paragraph Number

7.2.8.3

7.2.8.3.1

7.2.8.3.2

Contents

Title Page Number

Partial Data Valid Indication (PSDVAL) ............................................................... 7-16

Partial Data Valid (PSDVAL)—Input................................................................ 7-17 Partial Data Valid (PSDVAL)—Output ............................................................. 7-17

Chapter 8 The 60x Bus

Terminology ..................................................................................................................... 8-1

Bus Configuration............................................................................................................ 8-2 Single-MPC8280 Bus Mode........................................................................................ 8-2

60x-Compatible Bus Mode.......................................................................................... 8-3

60x Bus Protocol Overview ............................................................................................. 8-4

Arbitration Phase ......................................................................................................... 8-5

Address Pipelining and Split-Bus Transactions........................................................... 8-6

Address Tenure Operations.............................................................................................. 8-7 Address Arbitration...................................................................................................... 8-7

Address Pipelining....................................................................................................... 8-8

Address Transfer Attribute Signals.............................................................................. 8-9 Transfer Type Signal (TT[0–4]) Encoding .............................................................. 8-9

Transfer Code Signals TC[0–2] ............................................................................. 8-12 TBST and TSIZ[0–3] Signals and Size of Transfer .............................................. 8-12

Burst Ordering During Data Transfers .................................................................. 8-13

Effect of Alignment on Data Transfers.................................................................. 8-14

Effect of Port Size on Data Transfers .................................................................... 8-15

60x-Compatible Bus Mode—Size Calculation ..................................................... 8-17

Extended Transfer Mode ....................................................................................... 8-18

Address Transfer Termination ................................................................................... 8-21 Address Retried with ARTRY ............................................................................... 8-21

Address Tenure Timing Configuration .................................................................. 8-23 Pipeline Control ......................................................................................................... 8-23

Data Tenure Operations ................................................................................................. 8-24 Data Bus Arbitration.................................................................................................. 8-24

Data Streaming Mode ................................................................................................ 8-25 Data Bus Transfers and Normal Termination ............................................................ 8-25

Effect of ARTRY Assertion on Data Transfer and Arbitration ................................. 8-26 Port Size Data Bus Transfers and PSDVAL Termination.......................................... 8-26

Data Bus Termination by Assertion of TEA.............................................................. 8-28

Memory Coherency—MEI Protocol ............................................................................. 8-29

Processor State Signals .................................................................................................. 8-30

Support for the lwarx/stwcx. Instruction Pair ........................................................... 8-31

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9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.9.1

9.9.1.1

9.9.1.2

9.9.1.2.1

9.9.1.2.2

9.9.1.2.3

9.9.1.2.4

9.9.1.3

9.9.1.3.1

9.9.1.3.2

9.9.1.4

9.9.1.4.1

9.9.1.4.2

9.9.1.4.3

9.9.1.4.4

9.9.1.4.5

9.9.1.4.6

9.9.1.4.7

9.9.1.5

9.9.1.5.1

9.9.1.5.2

9.9.2

9.9.2.1

9.9.2.2

9.9.2.3

9.10

Paragraph Number

8.7.2

8.8

Contents

Title Page Number

TLBISYNC Input ...................................................................................................... 8-31 Little-Endian Mode........................................................................................................ 8-31

Chapter 9 PCI Bridge

Signals.............................................................................................................................. 9-3 Clocking........................................................................................................................... 9-3 PCI Bridge Initialization .................................................................................................. 9-3 SDMA Interface............................................................................................................... 9-3

Interrupts from PCI Bridge .............................................................................................. 9-4 60x Bus Arbitration Priority ............................................................................................ 9-4 60x Bus Masters............................................................................................................... 9-4

CompactPCI Hot Swap Specification Support ................................................................ 9-5 PCI Interface .................................................................................................................... 9-5

PCI Interface Operation ............................................................................................... 9-6 Bus Commands ........................................................................................................ 9-6

PCI Protocol Fundamentals ..................................................................................... 9-7

Basic Transfer Control......................................................................................... 9-8 Addressing ........................................................................................................... 9-8

Byte Enable Signals............................................................................................. 9-9 Bus Driving and Turnaround ............................................................................... 9-9 Bus Transactions...................................................................................................... 9-9 Read and Write Transactions ............................................................................... 9-9

Transaction Termination .................................................................................... 9-11

Other Bus Operations ............................................................................................ 9-13 Device Selection ................................................................................................ 9-13

Fast Back-to-Back Transactions ........................................................................ 9-14 Data Streaming .................................................................................................. 9-14

Host Mode Configuration Access...................................................................... 9-15

Agent Mode Configuration Access ................................................................... 9-16 Special Cycle Command ................................................................................... 9-16

Interrupt Acknowledge ...................................................................................... 9-17 Error Functions ...................................................................................................... 9-17 Parity.................................................................................................................. 9-17

Error Reporting.................................................................................................. 9-18

PCI Bus Arbitration ................................................................................................... 9-19 Bus Parking............................................................................................................ 9-19 Arbitration Algorithm............................................................................................ 9-19

Master Latency Timer............................................................................................ 9-20

Address Map .................................................................................................................. 9-21

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Address Map Programming ....................................................................................... 9-24 Address Translation ................................................................................................... 9-24

PCI Inbound Translation........................................................................................ 9-25

PCI Outbound Translation ..................................................................................... 9-26 SIU Registers ............................................................................................................. 9-26

Configuration Registers ................................................................................................. 9-27 Memory-Mapped Configuration Registers ................................................................ 9-27

Message Unit (I 2

O) Registers................................................................................ 9-30

DMA Controller Registers..................................................................................... 9-30 PCI Outbound Translation Address Registers (POTARx) .................................... 9-30

PCI Outbound Base Address Registers (POBARx) .............................................. 9-31

PCI Outbound Comparison Mask Registers (POCMRx) ..................................... 9-32

Discard Timer Control Register (PTCR) .............................................................. 9-33 General Purpose Control Register (GPCR) .......................................................... 9-33

PCI General Control Register (PCI_GCR) ........................................................... 9-35 Error Status Register (ESR) .................................................................................. 9-35

Error Mask Register (EMR) ................................................................................. 9-37

Error Control Register (ECR) ............................................................................... 9-38

PCI Error Address Capture Register (PCI_EACR) .............................................. 9-39

PCI Error Data Capture Register (PCI_EDCR) .................................................... 9-40 PCI Error Control Capture Register (PCI_ECCR) ............................................... 9-40

PCI Inbound Translation Address Registers (PITARx) ........................................ 9-42 PCI Inbound Base Address Registers (PIBARx) .................................................. 9-42

PCI Inbound Comparison Mask Registers (PICMRx) .......................................... 9-43

PCI Bridge Configuration Registers ........................................................................ 9-45

Vendor ID Register ............................................................................................... 9-47 Device ID Register ............................................................................................... 9-47 PCI Bus Command Register ................................................................................. 9-47

PCI Bus Status Register ........................................................................................ 9-48

Revision ID Register ............................................................................................. 9-50 PCI Bus Programming Interface Register ............................................................ 9-50

Subclass Code Register ......................................................................................... 9-51 PCI Bus Base Class Code Register ....................................................................... 9-51

PCI Bus Cache Line Size Register ....................................................................... 9-52 PCI Bus Latency Timer Register .......................................................................... 9-52

Header Type Register ........................................................................................... 9-53 BIST Control Register .......................................................................................... 9-53 PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR) .................................................................................................. 9-53

General Purpose Local Access Base Address Registers (GPLABARx) .............. 9-54

Subsystem Vendor ID Register ............................................................................. 9-55

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Title Page Number

Subsystem Device ID Register ............................................................................. 9-56 PCI Bus Capabilities Pointer Register .................................................................. 9-56

PCI Bus Interrupt Line Register ........................................................................... 9-57 PCI Bus Interrupt Pin Register ............................................................................. 9-57

PCI Bus MIN GNT ............................................................................................... 9-58 PCI Bus MAX LAT .............................................................................................. 9-58

PCI Bus Function Register ................................................................................... 9-59

PCI Bus Arbiter Configuration Register ............................................................... 9-60

PCI Hot Swap Register Block .............................................................................. 9-61 PCI Hot Swap Control Status Register ................................................................. 9-61

PCI Configuration Register Access from the Core ............................................... 9-62 PCI Configuration Register Access in Big-Endian Mode .................................... 9-62

Additional Information on Endianess ............................................................... 9-63 Notes on GPCR[LE_MODE] ........................................................................... 9-63

Initializing the PCI Configuration Registers ........................................................ 9-64

Message Unit (I 2

O) ....................................................................................................... 9-66

Message Registers...................................................................................................... 9-66

Inbound Message Registers (IMRx) ..................................................................... 9-67 Outbound Message Registers (OMRx) ................................................................. 9-67

Door Bell Registers ................................................................................................... 9-68 Outbound Doorbell Register (ODR) ..................................................................... 9-68

Inbound Doorbell Register (IDR) ......................................................................... 9-69

I

2 O Unit .................................................................................................................... 9-70

PCI Configuration Identification .......................................................................... 9-71 Inbound FIFOs ...................................................................................................... 9-71

Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound Free_FIFO Tail Pointer Register (IFTPR) .................................................... 9-72

Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound Post_FIFO Tail Pointer Register (IPTPR) .................................................... 9-73

Outbound FIFOs ................................................................................................... 9-75 Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound Free_FIFO Tail Pointer Register (OFTPR) .................................................. 9-75

Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound Post_FIFO Tail Pointer Register (OPTPR) ................................................... 9-76

I 2

O Registers.......................................................................................................... 9-78

Inbound FIFO Queue Port Register (IFQPR) ................................................... 9-78

Outbound FIFO Queue Port Register (OFQPR) ............................................... 9-79

Outbound Message Interrupt Status Register (OMISR) ................................... 9-80

Outbound Message Interrupt Mask Register (OMIMR) .................................. 9-81

Inbound Message Interrupt Status Register (IMISR) ....................................... 9-82

Inbound Message Interrupt Mask Register (IMIMR) ....................................... 9-83

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Title Page Number

Messaging Unit Control Register (MUCR) ...................................................... 9-84

Queue Base Address Register (QBAR) ............................................................ 9-85

DMA Controller............................................................................................................. 9-86 DMA Operation ......................................................................................................... 9-86

DMA Direct Mode................................................................................................. 9-87 DMA Chaining Mode ............................................................................................ 9-87

DMA Coherency.................................................................................................... 9-88 Halt and Error Conditions...................................................................................... 9-88 DMA Transfer Types ............................................................................................. 9-88

DMA Registers ...................................................................................................... 9-89 DMA Mode Registers 0–3 (DMAMRx) .......................................................... 9-89

DMA Status Registers 0–3 (DMASRx) ............................................................ 9-91

DMA Current Descriptor Address Registers 0–3 (DMACDARx) ................... 9-92

DMA Source Address Registers 0–3 (DMASARx) ......................................... 9-93

DMA Destination Address Registers 0–3 (DMADARx) ................................. 9-94 DMA Byte Count Registers 0–3 (DMABCRx) ................................................ 9-94

DMA Next Descriptor Address Registers 0–3 (DMANDARx) ....................... 9-95

DMA Segment Descriptors........................................................................................ 9-96

Descriptor in Big-Endian Mode............................................................................. 9-97

Descriptor in Little-Endian Mode.......................................................................... 9-98 Error Handling ............................................................................................................... 9-98

Interrupt and Error Signals ........................................................................................ 9-99 PCI Bus Error Signals............................................................................................ 9-99 System Error (SERR) ........................................................................................ 9-99 Parity Error (PERR)........................................................................................... 9-99 Error Reporting.................................................................................................. 9-99 Illegal Register Access Error ................................................................................. 9-99

PCI Interface ........................................................................................................ 9-100 Address Parity Error ........................................................................................ 9-100 Data Parity Error.............................................................................................. 9-100 Master-Abort Transaction Termination ........................................................... 9-100

Target-Abort Error ........................................................................................... 9-101 NMI ................................................................................................................. 9-101 Embedded Utilities .............................................................................................. 9-101 Outbound Free Queue Overflow ..................................................................... 9-101 Inbound Post Queue Overflow ........................................................................ 9-101 Inbound DoorBell Machine Check.................................................................. 9-101

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10.1.1

10.1.2

10.1.3

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10.1.5

10.1.6

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10.3

10.4

10.5

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Title

Chapter 10 Clocks and Power Control

Page Number

MPC8280 Clock Block Diagram ................................................................................... 10-1 Main PLL................................................................................................................... 10-1

Core PLL.................................................................................................................... 10-2 Skew Elimination....................................................................................................... 10-2 Dividers...................................................................................................................... 10-2 Internal Clock Signals................................................................................................ 10-2

PCI Bridge as an Agent Operating from the PCI System Clock ............................... 10-4 PCI Bridge as a Host Generating the PCI System Clock .......................................... 10-4

External Clock Inputs .................................................................................................... 10-5 PLL Pins ....................................................................................................................... 10-5

System Clock Control Register (SCCR)........................................................................ 10-6

System Clock Mode Register (SCMR).......................................................................... 10-7

Core PLL Configurations........................................................................................... 10-8

Clock Configuration Modes........................................................................................... 10-9

Chapter 11 Memory Controller

Features .......................................................................................................................... 11-3

Basic Architecture.......................................................................................................... 11-4

Address and Address Space Checking....................................................................... 11-7

Page Hit Checking ..................................................................................................... 11-8 Error Checking and Correction (ECC) ...................................................................... 11-8 Parity Generation and Checking ................................................................................ 11-8 Transfer Error Acknowledge (TEA) Generation ....................................................... 11-8

Machine Check Interrupt (MCP) Generation ............................................................ 11-9 Data Buffer Controls (BCTLx and LWR) ................................................................. 11-9 Atomic Bus Operation ............................................................................................... 11-9 Data Pipelining ......................................................................................................... 11-9

External Memory Controller Support ...................................................................... 11-10 External Address Latch Enable Signal (ALE) ......................................................... 11-10 ECC/Parity Byte Select (PBSE) .............................................................................. 11-10

Partial Data Valid Indication (PSDVAL) ..................................................................11-11

BADDR[27:31] Signal Connections ....................................................................... 11-12 Register Descriptions ................................................................................................... 11-12

Base Registers (BRx) ............................................................................................... 11-13

Option Registers (ORx) ........................................................................................... 11-15

60x SDRAM Mode Register (PSDMR) .................................................................. 11-20

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Local Bus SDRAM Mode Register (LSDMR)........................................................ 11-24

Machine A/B/C Mode Registers (MxMR)............................................................... 11-26

Memory Data Register (MDR) ................................................................................ 11-28

Memory Address Register (MAR) .......................................................................... 11-29

60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-30 Local Bus-Assigned UPM Refresh Timer (LURT) ................................................. 11-30

60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-31

Local Bus-Assigned SDRAM Refresh Timer (LSRT) ............................................ 11-32 Memory Refresh Timer Prescaler Register (MPTPR) ............................................. 11-32

60x Bus Error Status and Control Registers (TESCRx) .......................................... 11-33 Local Bus Error Status and Control Registers (L_TESCRx) .................................. 11-33 SDRAM Machine ........................................................................................................ 11-33

Supported SDRAM Configurations......................................................................... 11-35 SDRAM Power-On Initialization ............................................................................ 11-35 JEDEC-Standard SDRAM Interface Commands .................................................... 11-35

Page-Mode Support and Pipeline Accesses............................................................. 11-36 Bank Interleaving .................................................................................................... 11-36

Using BNKSEL Signals in Single-MPC8280 Bus Mode.................................... 11-37 SDRAM Address Multiplexing (SDAM and BSMA)......................................... 11-37

SDRAM Device-Specific Parameters...................................................................... 11-38

Precharge-to-Activate Interval............................................................................. 11-39 Activate to Read/Write Interval ........................................................................... 11-39

Column Address to First Data Out—CAS Latency............................................. 11-40

Last Data Out to Precharge.................................................................................. 11-41 Last Data In to Precharge—Write Recovery ....................................................... 11-41

Refresh Recovery Interval (RFRC) ..................................................................... 11-42 External Address Multiplexing Signal................................................................. 11-42 External Address and Command Buffers (BUFCMD)........................................ 11-42

SDRAM Interface Timing ....................................................................................... 11-43

SDRAM Read/Write Transactions........................................................................... 11-46

SDRAM Mode-Set Command Timing .................................................................... 11-47 SDRAM Refresh...................................................................................................... 11-47

SDRAM Refresh Timing ......................................................................................... 11-48 SDRAM Configuration Examples ........................................................................... 11-48

SDRAM Configuration Example (Page-Based Interleaving).............................. 11-49

SDRAM Configuration Example (Bank-Based Interleaving) ................................. 11-50

General-Purpose Chip-Select Machine (GPCM)......................................................... 11-52

Timing Configuration .............................................................................................. 11-53

Chip-Select Assertion Timing ............................................................................. 11-54

Chip-Select and Write Enable Deassertion Timing ............................................. 11-55

Relaxed Timing.................................................................................................... 11-56

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Output Enable (OE) Timing ................................................................................ 11-58

Programmable Wait State Configuration ............................................................. 11-59 Extended Hold Time on Read Accesses .............................................................. 11-59

External Access Termination ................................................................................... 11-61

Boot Chip-Select Operation..................................................................................... 11-62

Differences Between the MPC8xx GPCM and MPC82xx GPCM .......................... 11-63 User-Programmable Machines (UPMs)....................................................................... 11-63

Requests ................................................................................................................... 11-65

Memory Access Requests.................................................................................... 11-66 UPM Refresh Timer Requests ............................................................................. 11-66

Software Requests—run Command .................................................................... 11-67 Exception Requests.............................................................................................. 11-67 Programming the UPMs .......................................................................................... 11-67

Clock Timing ........................................................................................................... 11-68

The RAM Array....................................................................................................... 11-70

RAM Words ......................................................................................................... 11-71

Chip-Select Signals (CxTx) ............................................................................. 11-75

Byte-Select Signals (BxTx) ............................................................................. 11-76

General-Purpose Signals (GxTx, GOx) ........................................................... 11-77 Loop Control.................................................................................................... 11-77 Repeat Execution of Current RAM Word (REDO) ........................................ 11-77

Address Multiplexing .......................................................................................... 11-78 Data Valid and Data Sample Control................................................................... 11-78

Signals Negation.................................................................................................. 11-79 The Wait Mechanism ........................................................................................... 11-79

Extended Hold Time on Read Accesses ............................................................. 11-80 UPM DRAM Configuration Example ..................................................................... 11-80

Differences Between the MPC8xx UPM and MPC82xx UPM ............................... 11-81

Memory System Interface Example Using UPM ........................................................ 11-82

EDO Interface Example....................................................................................... 11-93

Handling Devices with Slow or Variable Access Times............................................ 11-101 Hierarchical Bus Interface Example ...................................................................... 11-101 Slow Devices Example .......................................................................................... 11-101 External Master Support (60x-Compatible Mode) .................................................... 11-101

60x-Compatible External Masters (non-MPC8280).............................................. 11-102 MPC8280 External Masters................................................................................... 11-102 Extended Controls in 60x-Compatible Mode ........................................................ 11-102 Address Incrementing for External Bursting Masters ........................................... 11-102

External Masters Timing........................................................................................ 11-103

Example of External Master Using the SDRAM Machine ............................... 11-105

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Title

Chapter 12 Secondary (L2) Cache Support

Page Number

L2 Cache Configurations ............................................................................................... 12-1 Copy-Back Mode ....................................................................................................... 12-1

Write-Through Mode ................................................................................................. 12-2

ECC/Parity Mode....................................................................................................... 12-4

L2 Cache Interface Parameters ...................................................................................... 12-6

System Requirements When Using the L2 Cache Interface.......................................... 12-7 L2 Cache Operation ....................................................................................................... 12-7 Timing Example............................................................................................................. 12-7

13.1

13.2

13.3

13.4

13.5

13.6

14.1

14.2

14.3

14.3.1

14.3.2

14.3.3

14.3.4

14.3.5

14.3.6

14.3.7

14.3.8

14.3.9

14.3.10

Chapter 13 IEEE 1149.1 Test Access Port

Overview........................................................................................................................ 13-1

TAP Controller............................................................................................................... 13-2

Boundary Scan Register................................................................................................. 13-3

Instruction Register........................................................................................................ 13-5

MPC8280 Restrictions ................................................................................................... 13-7 Nonscan Chain Operation .............................................................................................. 13-7

Part IV Communications Processor Module

Chapter 14 Communications Processor Module Overview

Features .......................................................................................................................... 14-1

Serial Configurations ..................................................................................................... 14-3

Communications Processor (CP) ................................................................................... 14-4 CPM Performance Evaluation ................................................................................... 14-4 Features ...................................................................................................................... 14-4

CP Block Diagram ..................................................................................................... 14-5

G2_LE Core Interface................................................................................................ 14-7 Peripheral Interface.................................................................................................... 14-7

Execution from RAM ................................................................................................ 14-8

RISC Controller Configuration Register (RCCR) ..................................................... 14-9

RISC Time-Stamp Control Register (RTSCR) ........................................................ 14-10

RISC Time-Stamp Register (RTSR) ........................................................................ 14-11 RISC Microcode Revision Number......................................................................... 14-11

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14.6.2

14.6.3

14.6.4

14.6.5

14.6.6

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Title Page Number

Command Set............................................................................................................... 14-12 CP Command Register (CPCR)............................................................................... 14-12

CP Commands ..................................................................................................... 14-14

Command Register Example ................................................................................... 14-17 Command Execution Latency.................................................................................. 14-17 Dual-Port RAM............................................................................................................ 14-17

Buffer Descriptors (BDs)......................................................................................... 14-21 Parameter RAM ....................................................................................................... 14-21

RISC Timer Tables....................................................................................................... 14-23 RISC Timer Table Parameter RAM......................................................................... 14-23

RISC Timer Command Register (TM_CMD) ......................................................... 14-25 RISC Timer Table Entries........................................................................................ 14-25 RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 14-25

set timer Command.................................................................................................. 14-26 RISC Timer Initialization Sequence ........................................................................ 14-26

RISC Timer Initialization Example ......................................................................... 14-27 RISC Timer Interrupt Handling ............................................................................... 14-27 RISC Timer Table Scan Algorithm.......................................................................... 14-27

Using the RISC Timers to Track CP Loading ......................................................... 14-28

Chapter 15 Serial Interface with Time-Slot Assigner

Features .......................................................................................................................... 15-3

Overview........................................................................................................................ 15-4

Enabling Connections to TSA ....................................................................................... 15-7

Serial Interface RAM ..................................................................................................... 15-8

One Multiplexed Channel with Static Frames ........................................................... 15-9 One Multiplexed Channel with Dynamic Frames ..................................................... 15-9

Programming SIx RAM Entries .............................................................................. 15-10

SIx RAM Programming Example............................................................................ 15-14

Static and Dynamic Routing .................................................................................... 15-15

Serial Interface Registers ............................................................................................. 15-17 SI Global Mode Registers (SIxGMR) ..................................................................... 15-17 SI Mode Registers (SIxMR) .................................................................................... 15-17

SIx RAM Shadow Address Registers (SIxRSR) ..................................................... 15-24 SI Command Register (SIxCMDR)......................................................................... 15-24

SI Status Registers (SIxSTR)................................................................................... 15-25 Serial Interface IDL Interface Support ........................................................................ 15-25

IDL Interface Example ............................................................................................ 15-26

IDL Interface Programming..................................................................................... 15-29

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Title Page Number

Serial Interface GCI Support ....................................................................................... 15-30

SI GCI Activation/Deactivation Procedure ............................................................. 15-32 Serial Interface GCI Programming .......................................................................... 15-32 Normal Mode GCI Programming ........................................................................ 15-32

SCIT Programming.............................................................................................. 15-33

16.1

16.2

16.3

16.4

16.4.1

16.4.2

16.4.3

16.4.4

16.4.5

16.4.6

17.1

17.2

17.3

18.1

18.2

18.2.1

18.2.2

18.2.3

18.2.4

18.2.5

18.2.6

18.2.7

Chapter 16 CPM Multiplexing

Features .......................................................................................................................... 16-2

Enabling Connections to TSA or NMSI ........................................................................ 16-3

NMSI Configuration ...................................................................................................... 16-4

CMX Registers .............................................................................................................. 16-7 CMX UTOPIA Address Register (CMXUAR) ......................................................... 16-7

CMX SI1 Clock Route Register (CMXSI1CR)....................................................... 16-12

CMX SI2 Clock Route Register (CMXSI2CR)....................................................... 16-13 CMX FCC Clock Route Register (CMXFCR) ........................................................ 16-13

CMX SCC Clock Route Register (CMXSCR) ........................................................ 16-16

CMX SMC Clock Route Register (CMXSMR) ...................................................... 16-19

Chapter 17 Baud-Rate Generators (BRGs)

BRG Configuration Registers 1–8 (BRGCx) ................................................................ 17-2

Autobaud Operation on a UART ................................................................................... 17-4

UART Baud Rate Examples .......................................................................................... 17-5

Chapter 18 Timers

Features .......................................................................................................................... 18-1

General-Purpose Timer Units ........................................................................................ 18-2

Cascaded Mode.......................................................................................................... 18-3 Timer Global Configuration Registers (TGCR1 and TGCR2).................................. 18-3

Timer Mode Registers (TMR1–TMR4)..................................................................... 18-5

Timer Reference Registers (TRR1–TRR4) ............................................................... 18-6

Timer Capture Registers (TCR1–TCR4) ................................................................... 18-7 Timer Counters (TCN1–TCN4)................................................................................. 18-7 Timer Event Registers (TER1–TER4)....................................................................... 18-7

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19.1

19.2

19.2.1

19.2.2

19.2.3

19.2.4

19.3

19.4

19.5

19.5.1

19.5.1.1

19.5.1.2

19.5.1.3

19.5.2

19.5.2.1

19.5.2.1.1

19.5.2.1.2

19.5.2.2

19.5.2.2.1

19.5.2.2.2

19.5.3

19.5.4

19.6

19.7

19.7.1

19.7.1.1

19.7.1.2

19.7.2

19.8

19.8.1

19.8.2

19.8.2.1

19.8.2.2

19.8.2.3

19.8.3

19.8.4

19.8.5

19.9

Paragraph Number

Contents

Title

Chapter 19 SDMA Channels and IDMA Emulation

Page Number

SDMA Bus Arbitration and Bus Transfers .................................................................... 19-2

SDMA Registers ............................................................................................................ 19-3 SDMA Status Register (SDSR) ................................................................................. 19-3

SDMA Mask Register (SDMR)................................................................................. 19-4 SDMA Transfer Error Address Registers (PDTEA and LDTEA)............................. 19-4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM) ......................... 19-4

IDMA Emulation ........................................................................................................... 19-5 IDMA Features .............................................................................................................. 19-5

IDMA Transfers ............................................................................................................. 19-6 Memory-to-Memory Transfers .................................................................................. 19-6

External Request Mode.......................................................................................... 19-8

Normal Mode......................................................................................................... 19-9 Working with a PCI Bus ........................................................................................ 19-9 Memory to/from Peripheral Transfers ....................................................................... 19-9

Dual-Address Transfers ....................................................................................... 19-10 Peripheral to Memory ...................................................................................... 19-10 Memory to Peripheral ...................................................................................... 19-10 Single Address (Fly-By) Transfers ...................................................................... 19-10

Peripheral-to-Memory Fly-By Transfers ......................................................... 19-11 Memory-to-Peripheral Fly-By Transfers ......................................................... 19-11 Controlling 60x Bus Bandwidth .............................................................................. 19-11

PCI Burst Length and Latency Control ................................................................... 19-12 IDMA Priorities ........................................................................................................... 19-12

IDMA Interface Signals ............................................................................................... 19-13 DREQx and DACKx ............................................................................................... 19-13

Level-Sensitive Mode .......................................................................................... 19-14 Edge-Sensitive Mode........................................................................................... 19-14 DONEx .................................................................................................................... 19-14 IDMA Operation .......................................................................................................... 19-14

Auto Buffer and Buffer Chaining ............................................................................ 19-15

IDMAx Parameter RAM ......................................................................................... 19-16

DMA Channel Mode (DCM)............................................................................... 19-18

Data Transfer Types as Programmed in DCM..................................................... 19-20 Programming DTS and STS ................................................................................ 19-20

IDMA Performance ................................................................................................. 19-22 IDMA Event Register (IDSR) and Mask Register (IDMR) .................................... 19-22

IDMA BDs............................................................................................................... 19-23

IDMA Commands........................................................................................................ 19-26

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20.1

20.1.1

20.1.2

20.1.3

20.1.4

20.2

20.3

20.3.1

20.3.2

20.3.3

20.3.4

20.3.5

20.3.5.1

20.3.5.2

20.3.6

20.3.6.1

20.3.7

20.3.7.1

20.3.7.2

20.3.7.3

20.3.7.4

20.3.7.5

20.3.8

Paragraph Number

19.9.1

19.9.2

19.10

19.10.1

19.11

19.12

19.12.1

19.12.2

19.12.3

Contents

Title Page Number

start_idma Command............................................................................................... 19-26 stop_idma Command ............................................................................................... 19-26

IDMA Bus Exceptions ................................................................................................. 19-27 Externally Recognizing IDMA Operand Transfers ................................................. 19-27

Programming the Parallel I/O Registers ...................................................................... 19-28

IDMA Programming Examples ................................................................................... 19-29 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA2 ............................ 19-29

Memory-to-Peripheral Fly-By Mode—IDMA3 ...................................................... 19-30

Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1 ............................................ 19-32

Chapter 20 Serial Communications Controllers (SCCs)

Features .......................................................................................................................... 20-2

The General SCC Mode Registers (GSMR1–GSMR4) ............................................ 20-3

Protocol-Specific Mode Register (PSMR) ................................................................ 20-9 Data Synchronization Register (DSR)....................................................................... 20-9

Transmit-on-Demand Register (TODR) .................................................................. 20-10 SCC Buffer Descriptors (BDs) .................................................................................... 20-10

SCC Parameter RAM................................................................................................... 20-13

SCC Base Addresses................................................................................................ 20-14

Function Code Registers (RFCR and TFCR) .......................................................... 20-15

Handling SCC Interrupts ......................................................................................... 20-16 Initializing the SCCs................................................................................................ 20-16

Controlling SCC Timing with RTS, CTS, and CD .................................................. 20-17 Synchronous Protocols ........................................................................................ 20-17

Asynchronous Protocols ...................................................................................... 20-20

Digital Phase-Locked Loop (DPLL) Operation....................................................... 20-21

Encoding Data with a DPLL................................................................................ 20-23

Reconfiguring the SCCs .......................................................................................... 20-24 General Reconfiguration Sequence for an SCC Transmitter............................... 20-24

Reset Sequence for an SCC Transmitter.............................................................. 20-25 General Reconfiguration Sequence for an SCC Receiver ................................... 20-25 Reset Sequence for an SCC Receiver.................................................................. 20-25 Switching Protocols ............................................................................................. 20-25 Saving Power ........................................................................................................... 20-25

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22.1

22.2

22.3

22.4

22.5

22.6

22.7

22.8

22.9

22.10

22.11

22.12

21.1

21.2

21.3

21.4

21.5

21.6

21.7

21.8

21.9

21.10

21.11

21.12

21.13

21.14

21.15

21.16

21.17

21.18

21.19

21.20

21.21

21.22

Paragraph Number

Contents

Title

Chapter 21 SCC UART Mode

Page Number

Features .......................................................................................................................... 21-2 Normal Asynchronous Mode......................................................................................... 21-2

Synchronous Mode ........................................................................................................ 21-3 SCC UART Parameter RAM ......................................................................................... 21-3

Data-Handling Methods: Character- or Message-Based ............................................... 21-5 Error and Status Reporting............................................................................................. 21-5

SCC UART Commands ................................................................................................. 21-6

Multidrop Systems and Address Recognition ............................................................... 21-7 Receiving Control Characters ........................................................................................ 21-7

Hunt Mode (Receiver) ................................................................................................... 21-9 Inserting Control Characters into the Transmit Data Stream......................................... 21-9

Sending a Break (Transmitter)..................................................................................... 21-10 Sending a Preamble (Transmitter) ............................................................................... 21-10

Fractional Stop Bits (Transmitter) ............................................................................... 21-11

Handling Errors in the SCC UART Controller ............................................................ 21-12

UART Mode Register (PSMR).................................................................................... 21-13

SCC UART Receive Buffer Descriptor (RxBD) ......................................................... 21-15

SCC UART Transmit Buffer Descriptor (TxBD) ........................................................ 21-18

SCC UART Event Register (SCCE) and Mask Register (SCCM) .............................. 21-19

SCC UART Status Register (SCCS)............................................................................ 21-21

SCC UART Programming Example ............................................................................ 21-22

S-Records Loader Application..................................................................................... 21-23

Chapter 22 SCC HDLC Mode

SCC HDLC Features ..................................................................................................... 22-1

SCC HDLC Channel Frame Transmission .................................................................... 22-2 SCC HDLC Channel Frame Reception ......................................................................... 22-2

SCC HDLC Parameter RAM......................................................................................... 22-3

Programming the SCC in HDLC Mode......................................................................... 22-5 SCC HDLC Commands ................................................................................................. 22-5

Handling Errors in the SCC HDLC Controller.............................................................. 22-6

HDLC Mode Register (PSMR)...................................................................................... 22-7

SCC HDLC Receive Buffer Descriptor (RxBD) ........................................................... 22-8

SCC HDLC Transmit Buffer Descriptor (TxBD)........................................................ 22-12

HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ................................. 22-13

SCC HDLC Status Register (SCCS)............................................................................ 22-15

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23.1

23.2

23.3

23.4

23.5

23.6

23.7

23.8

23.9

23.10

23.11

23.12

23.13

23.14

23.15

23.16

23.17

Paragraph Number

22.13

22.13.1

22.13.2

22.14

22.14.1

22.14.2

22.14.3

22.14.4

22.14.5

22.14.6

22.14.6.1

22.14.6.2

Contents

Title Page Number

SCC HDLC Programming Examples .......................................................................... 22-16 SCC HDLC Programming Example #1................................................................... 22-16

SCC HDLC Programming Example #2................................................................... 22-18 HDLC Bus Mode with Collision Detection................................................................. 22-18

HDLC Bus Features................................................................................................. 22-20 Accessing the HDLC Bus ........................................................................................ 22-20

Increasing Performance ........................................................................................... 22-21

Delayed RTS Mode.................................................................................................. 22-22

Using the Time-Slot Assigner (TSA) ...................................................................... 22-23 HDLC Bus Protocol Programming.......................................................................... 22-23 Programming GSMR and PSMR for the HDLC Bus Protocol ........................... 22-23

HDLC Bus Controller Programming Example.................................................... 22-24

24.1

24.2

24.3

24.4

Chapter 23 SCC BISYNC Mode

Features .......................................................................................................................... 23-2 SCC BISYNC Channel Frame Transmission ................................................................ 23-2

SCC BISYNC Channel Frame Reception ..................................................................... 23-3 SCC BISYNC Parameter RAM ..................................................................................... 23-3

SCC BISYNC Commands ............................................................................................. 23-4

SCC BISYNC Control Character Recognition .............................................................. 23-5

BISYNC SYNC Register (BSYNC).............................................................................. 23-7

SCC BISYNC DLE Register (BDLE) ........................................................................... 23-8

Sending and Receiving the Synchronization Sequence ................................................. 23-9 Handling Errors in the SCC BISYNC ........................................................................... 23-9

BISYNC Mode Register (PSMR)................................................................................ 23-10

SCC BISYNC Receive BD (RxBD) ............................................................................ 23-12

SCC BISYNC Transmit BD (TxBD)........................................................................... 23-14

BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).......................... 23-15

SCC Status Registers (SCCS)...................................................................................... 23-16

Programming the SCC BISYNC Controller ................................................................ 23-17

SCC BISYNC Programming Example ........................................................................ 23-18

Chapter 24 SCC Transparent Mode

Features .......................................................................................................................... 24-1

SCC Transparent Channel Frame Transmission Process............................................... 24-2 SCC Transparent Channel Frame Reception Process .................................................... 24-2

Achieving Synchronization in Transparent Mode ......................................................... 24-3

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25.1

25.2

25.3

25.4

25.5

25.6

25.7

25.8

25.9

25.10

25.11

25.12

25.13

25.14

25.15

25.16

25.17

25.18

Paragraph Number

24.4.1

24.4.1.1

24.4.1.2

24.4.1.2.1

24.4.1.3

24.4.2

24.4.2.1

24.4.2.2

24.4.3

24.5

24.6

24.7

24.8

24.9

24.10

24.11

24.12

24.13

24.14

Contents

Title Page Number

Synchronization in NMSI Mode................................................................................ 24-3 In-Line Synchronization Pattern............................................................................ 24-3 External Synchronization Signals.......................................................................... 24-3

External Synchronization Example ................................................................... 24-4

Transparent Mode without Explicit Synchronization ............................................ 24-5 Synchronization and the TSA .................................................................................... 24-5 Inline Synchronization Pattern .............................................................................. 24-5 Inherent Synchronization....................................................................................... 24-5 End of Frame Detection ............................................................................................. 24-5

CRC Calculation in Transparent Mode.......................................................................... 24-6 SCC Transparent Parameter RAM................................................................................. 24-6 SCC Transparent Commands......................................................................................... 24-6

Handling Errors in the Transparent Controller .............................................................. 24-7

Transparent Mode and the PSMR .................................................................................. 24-8 SCC Transparent Receive Buffer Descriptor (RxBD) ................................................... 24-8

SCC Transparent Transmit Buffer Descriptor (TxBD)................................................ 24-10

SCC Transparent Event Register (SCCE)/Mask Register (SCCM)............................. 24-11

SCC Status Register in Transparent Mode (SCCS) ..................................................... 24-12

SCC2 Transparent Programming Example.................................................................. 24-13

Chapter 25 SCC Ethernet Mode

Ethernet on the MPC8280.............................................................................................. 25-1

Features .......................................................................................................................... 25-2

Connecting the MPC8280 to Ethernet ........................................................................... 25-4

SCC Ethernet Channel Frame Transmission ................................................................. 25-5

SCC Ethernet Channel Frame Reception....................................................................... 25-6 The Content-Addressable Memory (CAM) Interface.................................................... 25-6

SCC Ethernet Parameter RAM ...................................................................................... 25-7

Programming the Ethernet Controller............................................................................ 25-9 SCC Ethernet Commands .............................................................................................. 25-9

SCC Ethernet Address Recognition............................................................................. 25-11

Hash Table Algorithm.................................................................................................. 25-12 Interpacket Gap Time................................................................................................... 25-12 Handling Collisions ..................................................................................................... 25-12

Internal and External Loopback................................................................................... 25-13 Full-Duplex Ethernet Support...................................................................................... 25-13 Handling Errors in the Ethernet Controller.................................................................. 25-13

Ethernet Mode Register (PSMR) ................................................................................. 25-14

SCC Ethernet Receive BD ........................................................................................... 25-16

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28.1

28.2

28.2.1

28.2.2

28.2.3

28.2.3.1

28.2.4

28.2.4.1

28.2.4.2

28.2.4.3

28.2.4.4

28.2.4.5

28.2.5

28.2.6

28.3

28.3.1

28.3.2

28.3.3

28.3.4

28.3.5

Paragraph Number

27.5.7.6

27.5.7.7

27.5.7.8

27.6

27.6.1

27.6.2

27.6.3

27.6.4

27.7

27.7.1

27.7.2

27.8

27.9

27.10

27.10.1

27.11

27.11.1

Contents

Title Page Number

USB Mask Register (USBMR)............................................................................ 27-21 USB Status Register (USBS)............................................................................... 27-21

USB Start of Frame Timer (USSFT) ................................................................... 27-22 USB Buffer Descriptor Ring........................................................................................ 27-22

USB Receive Buffer Descriptor (Rx BD) for Host and Function ........................... 27-24

USB Transmit Buffer Descriptor (Tx BD) for Function.......................................... 27-26

USB Transmit Buffer Descriptor (Tx BD) for Host ................................................ 27-27

USB Transaction Buffer Descriptor (TrBD) for Host.............................................. 27-29

USB CP Commands..................................................................................................... 27-32 STOP Tx Command................................................................................................. 27-32

RESTART Tx Command ......................................................................................... 27-33 USB Controller Errors ................................................................................................. 27-33

USB Function Controller Initialization Example ........................................................ 27-34

Programming the USB Host Controller (Packet-Level) .............................................. 27-35 USB Host Controller Initialization Example ........................................................... 27-35

Programming the USB Host Controller (Transaction-Level) ...................................... 27-37 USB Host Controller Initialization Example ........................................................... 27-37

Chapter 28 Serial Management Controllers (SMCs)

Features .......................................................................................................................... 28-2 Common SMC Settings and Configurations ................................................................. 28-2 SMC Mode Registers (SMCMR1/SMCMR2)........................................................... 28-2

SMC Buffer Descriptor Operation............................................................................. 28-4

SMC Parameter RAM................................................................................................ 28-5

SMC Function Code Registers (RFCR/TFCR) ..................................................... 28-8 Disabling SMCs On-the-Fly ...................................................................................... 28-8

SMC Transmitter Full Sequence............................................................................ 28-9 SMC Transmitter Shortcut Sequence .................................................................... 28-9 SMC Receiver Full Sequence ................................................................................ 28-9 SMC Receiver Shortcut Sequence......................................................................... 28-9 Switching Protocols ............................................................................................... 28-9

Saving Power ........................................................................................................... 28-10 Handling Interrupts in the SMC............................................................................... 28-10 SMC in UART Mode ................................................................................................... 28-10

Features .................................................................................................................... 28-11 SMC UART Channel Transmission Process ........................................................... 28-11 SMC UART Channel Reception Process................................................................. 28-11 Programming the SMC UART Controller ............................................................... 28-11

SMC UART Transmit and Receive Commands ...................................................... 28-12

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Paragraph Number

28.3.6

28.3.7

28.3.8

28.3.9

28.3.10

28.3.11

28.3.12

28.4

28.4.1

28.4.2

28.4.3

28.4.4

28.4.5

28.4.6

28.4.7

28.4.8

28.4.9

28.4.10

28.4.11

28.5

28.5.1

28.5.2

28.5.2.1

28.5.2.2

28.5.3

28.5.3.1

28.5.3.2

28.5.4

28.5.5

28.5.6

28.5.7

28.5.8

28.5.9

Contents

Title Page Number

Sending a Break ....................................................................................................... 28-12

Sending a Preamble ................................................................................................. 28-13 Handling Errors in the SMC UART Controller ....................................................... 28-13

SMC UART RxBD .................................................................................................. 28-14

SMC UART TxBD .................................................................................................. 28-17

SMC UART Event Register (SMCE)/Mask Register (SMCM) .............................. 28-18

SMC UART Controller Programming Example...................................................... 28-19

SMC in Transparent Mode........................................................................................... 28-20 Features .................................................................................................................... 28-20

SMC Transparent Channel Transmission Process ................................................... 28-21 SMC Transparent Channel Reception Process ........................................................ 28-21

Using SMSYN for Synchronization ........................................................................ 28-22

Using the Time-Slot Assigner (TSA) for Synchronization...................................... 28-23

SMC Transparent Commands.................................................................................. 28-25 Handling Errors in the SMC Transparent Controller............................................... 28-25

SMC Transparent RxBD.......................................................................................... 28-26

SMC Transparent TxBD .......................................................................................... 28-27

SMC Transparent Event Register (SMCE)/Mask Register (SMCM)...................... 28-28

SMC Transparent NMSI Programming Example.................................................... 28-29

The SMC in GCI Mode ............................................................................................... 28-30 SMC GCI Parameter RAM...................................................................................... 28-30

Handling the GCI Monitor Channel ........................................................................ 28-31 SMC GCI Monitor Channel Transmission Process ............................................. 28-31 SMC GCI Monitor Channel Reception Process .................................................. 28-31 Handling the GCI C/I Channel ................................................................................ 28-31 SMC GCI C/I Channel Transmission Process ..................................................... 28-31

SMC GCI C/I Channel Reception Process .......................................................... 28-32 SMC GCI Commands.............................................................................................. 28-32 SMC GCI Monitor Channel RxBD ......................................................................... 28-32

SMC GCI Monitor Channel TxBD.......................................................................... 28-33 SMC GCI C/I Channel RxBD ................................................................................. 28-33

SMC GCI C/I Channel TxBD.................................................................................. 28-34 SMC GCI Event Register (SMCE)/Mask Register (SMCM).................................. 28-34

29.1

29.1.1

29.2

29.3

Chapter 29 Multi-Channel Controllers (MCCs)

MCC Operation Overview............................................................................................. 29-2 MCC Data Structure Organization............................................................................. 29-2

Global MCC Parameters ................................................................................................ 29-4

Channel-Specific Parameters ......................................................................................... 29-5

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29.3.3.2

29.3.4

29.3.4.1

29.3.4.2

29.3.4.2.1

29.3.4.3

29.3.4.3.1

29.3.4.3.2

29.3.4.3.3

29.3.4.4

29.3.4.4.1

29.3.4.4.2

29.3.4.4.3

29.3.4.4.4

29.3.4.5

29.4

29.5

29.5.1

29.5.2

29.5.3

29.5.4

29.6

29.7

29.8

29.8.1

29.8.1.1

29.8.1.2

Paragraph Number

29.3.1

29.3.1.1

29.3.1.2

29.3.1.3

29.3.1.4

29.3.2

29.3.2.1

29.3.2.2

29.3.2.3

29.3.2.4

29.3.3

29.3.3.1

29.3.3.1.1

Contents

Title Page Number

Channel-Specific HDLC Parameters ......................................................................... 29-5

Internal Transmitter State (TSTATE)—HDLC Mode ........................................... 29-7

Interrupt Mask (INTMSK)—HDLC Mode ........................................................... 29-8 Channel Mode Register (CHAMR)—HDLC Mode.............................................. 29-8

Internal Receiver State (RSTATE)—HDLC Mode ............................................. 29-10

Channel-Specific Transparent Parameters ............................................................... 29-11

Internal Transmitter State (TSTATE)—Transparent Mode ................................. 29-12 Interrupt Mask (INTMSK)—Transparent Mode ................................................. 29-12 Channel Mode Register (CHAMR)—Transparent Mode.................................... 29-12

Internal Receiver State (RSTATE)—Transparent Mode ..................................... 29-14 MCC Parameters for AAL1 CES Usage.................................................................. 29-14 Channel-Specific Parameters—AAL1 CES ........................................................ 29-14

Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES............................................................................ 29-15 Channel Mode Register (CHAMR)—AAL1 CES .............................................. 29-15

Channel-Specific SS7 Parameters ........................................................................... 29-17

Extended Channel Mode Register (ECHAMR)—SS7 Mode.............................. 29-20

Signal Unit Error Monitor (SUERM)—SS7 Mode ............................................. 29-22

SUERM in Japanese SS7................................................................................. 29-23 SS7 Configuration Register—SS7 Mode ............................................................ 29-23

AERM Implementation ................................................................................... 29-24 AERM in Japanese SS7 ................................................................................... 29-24

Disabling SUERM ........................................................................................... 29-25 SU Filtering—SS7 Mode..................................................................................... 29-25 Comparison Mask............................................................................................ 29-25 Comparison State Machine.............................................................................. 29-25

Filtering Limitations ........................................................................................ 29-26 Resetting the SU Filtering Mechanism............................................................ 29-26

Octet Counting Mode—SS7 Mode...................................................................... 29-27 Channel Extra Parameters............................................................................................ 29-27

Superchannels .............................................................................................................. 29-28 Superchannel Table.................................................................................................. 29-28

Superchannels and Receiving .................................................................................. 29-29 Transparent Slot Synchronization............................................................................ 29-29 Superchannelling Programming Examples.............................................................. 29-29

MCC Configuration Registers (MCCFx) .................................................................... 29-32

MCC Commands ......................................................................................................... 29-33

MCC Exceptions .......................................................................................................... 29-34

MCC Event Register (MCCE)/Mask Register (MCCM) ........................................ 29-36

Interrupt Circular Table Entry ............................................................................. 29-37

Global Transmitter Underrun (GUN) .................................................................. 29-38

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30.1

30.2

30.2.1

30.3

30.4

30.5

30.6

30.7

30.7.1

30.8

30.8.1

30.8.2

30.8.3

30.9

30.10

30.10.1

30.10.1.1

30.10.1.2

30.10.1.3

30.11

30.12

Paragraph Number

29.8.1.2.1

29.8.1.2.2

29.8.1.2.3

29.8.1.2.4

29.8.1.2.5

29.8.1.2.6

29.8.1.2.7

29.8.1.3

29.8.1.4

29.9

29.9.1

29.9.2

29.10

29.10.1

29.10.2

29.11

Contents

Title Page Number

TDM Clock...................................................................................................... 29-39 Synchronization Pulse ..................................................................................... 29-39 SIRAM Programming...................................................................................... 29-39

MCC Initialization ........................................................................................... 29-40 CPM Bandwidth .............................................................................................. 29-40 CPM Priority.................................................................................................... 29-40

Bus Latency ..................................................................................................... 29-41 Recovery from GUN Errors................................................................................. 29-41 Global Overrun (GOV)........................................................................................ 29-41 MCC Buffer Descriptors.............................................................................................. 29-41

Receive Buffer Descriptor (RxBD) ......................................................................... 29-42

Transmit Buffer Descriptor (TxBD) ........................................................................ 29-44

MCC Initialization and Start/Stop Sequence ............................................................... 29-46

Stopping and Restarting a Single-Channel .............................................................. 29-47 Stopping and Restarting a Superchannel ................................................................. 29-47

MCC Latency and Performance .................................................................................. 29-48

Chapter 30 Fast Communications Controllers (FCCs)

Overview........................................................................................................................ 30-1

General FCC Mode Registers (GFMRx) ....................................................................... 30-3

General FCC Expansion Mode Register (GFEMR) .................................................. 30-7

FCC Protocol-Specific Mode Registers (FPSMRx) ...................................................... 30-8 FCC Data Synchronization Registers (FDSRx)............................................................. 30-8

FCC Transmit-on-Demand Registers (FTODRx).......................................................... 30-9

FCC Buffer Descriptors ............................................................................................... 30-10

FCC Parameter RAM................................................................................................... 30-12

FCC Function Code Registers (FCRx) .................................................................... 30-14 Interrupts from the FCCs ............................................................................................. 30-14

FCC Event Registers (FCCEx) ................................................................................ 30-15 FCC Mask Registers (FCCMx) ............................................................................... 30-15 FCC Status Registers (FCCSx)................................................................................ 30-15 FCC Initialization ........................................................................................................ 30-15

FCC Interrupt Handling ............................................................................................... 30-16 FCC Transmit Errors................................................................................................ 30-16

Re-Initialization Procedure .................................................................................. 30-17 Recovery Sequence.............................................................................................. 30-17 Adjusting Transmitter BD Handling.................................................................... 30-17 FCC Timing Control .................................................................................................... 30-17

Disabling the FCCs On-the-Fly ................................................................................... 30-20

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31.2

31.2.1

31.2.1.1

31.2.1.2

31.2.1.2.1

31.2.1.3

31.2.1.4

31.2.1.5

31.2.2

31.2.2.1

31.2.2.2

31.2.2.2.1

31.2.2.3

31.2.2.4

31.2.3

31.2.4

31.3

31.3.1

31.3.2

31.3.3

31.3.3.1

31.3.3.2

31.3.4

31.3.5

31.3.5.1

31.3.5.2

31.3.5.3

31.3.5.3.1

31.3.5.3.2

Paragraph Number

30.12.1

30.12.2

30.12.3

30.12.4

30.12.5

30.13

Contents

Title Page Number

FCC Transmitter Full Sequence............................................................................... 30-21 FCC Transmitter Shortcut Sequence ....................................................................... 30-21 FCC Receiver Full Sequence ................................................................................... 30-21 FCC Receiver Shortcut Sequence............................................................................ 30-21

Switching Protocols ................................................................................................. 30-22 Saving Power ............................................................................................................... 30-22

Chapter 31 ATM Controller and AAL0, AAL1, and AAL5

Features .......................................................................................................................... 31-1

ATM Controller Overview............................................................................................. 31-5 Transmitter Overview ................................................................................................ 31-5 AAL5 Transmitter Overview................................................................................. 31-5 AAL1 Transmitter Overview................................................................................. 31-5

AAL1 CES Transmitter Overview .................................................................... 31-6 AAL0 Transmitter Overview................................................................................. 31-6 AAL2 Transmitter Overview................................................................................. 31-6 Transmit External Rate and Internal Rate Modes.................................................. 31-6 Receiver Overview .................................................................................................... 31-6

AAL5 Receiver Overview ..................................................................................... 31-7 AAL1 Receiver Overview ..................................................................................... 31-7

AAL1 CES Receiver Overview......................................................................... 31-8 AAL0 Receiver Overview ..................................................................................... 31-8 AAL2 Receiver Overview ..................................................................................... 31-8 Performance Monitoring............................................................................................ 31-8 ABR Flow Control..................................................................................................... 31-8 ATM Pace Control (APC) Unit...................................................................................... 31-8 APC Modes and ATM Service Types ........................................................................ 31-8

APC Unit Scheduling Mechanism ............................................................................. 31-9

Determining the Scheduling Table Size................................................................... 31-10 Determining the Cells Per Slot (CPS) in a Scheduling Table.............................. 31-10 Determining the Number of Slots in a Scheduling Table .................................... 31-10

Determining the Time-Slot Scheduling Rate of a Channel ..................................... 31-11 ATM Traffic Type .................................................................................................... 31-11 Peak Cell Rate Traffic Type................................................................................. 31-11 Determining the PCR Traffic Type Parameters ................................................... 31-11

Peak and Sustain Traffic Type (VBR) ................................................................. 31-12 Example for Using VBR Traffic Parameters ................................................... 31-12

Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2 .......................... 31-13

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31.3.6

31.4

31.4.1

31.4.2

31.4.2.1

31.4.2.2

31.4.3

31.4.4

31.5

31.5.1

31.5.1.1

31.5.1.2

31.5.1.3

31.5.2

31.5.2.1

31.5.3

31.6

31.6.1

31.6.2

31.6.3

31.6.4

31.6.5

31.6.6

31.6.6.1

31.6.6.2

31.6.6.3

31.6.6.4

31.7

31.7.1

31.8

31.9

31.9.1

31.9.2

31.9.3

31.9.4

31.9.5

31.9.6

31.9.7

31.9.8

31.10

Contents

Title Page Number

Peak and Minimum Cell Rate Traffic Type (UBR+)........................................... 31-13 Determining the Priority of an ATM Channel ......................................................... 31-13 VCI/VPI Address Lookup Mechanism........................................................................ 31-13

External CAM Lookup ............................................................................................ 31-14

Address Compression .............................................................................................. 31-15

VP-Level Address Compression Table (VPLT) .................................................. 31-16

VC-Level Address Compression Tables (VCLTs)............................................... 31-17

Misinserted Cells ..................................................................................................... 31-18 Receive Raw Cell Queue ......................................................................................... 31-18

Available Bit Rate (ABR) Flow Control...................................................................... 31-19

The ABR Model....................................................................................................... 31-20 ABR Flow Control Source End-System Behavior .............................................. 31-20

ABR Flow Control Destination End-System Behavior ....................................... 31-21 ABR Flowcharts .................................................................................................. 31-21

RM Cell Structure .................................................................................................... 31-26 RM Cell Rate Representation .............................................................................. 31-26

ABR Flow Control Setup......................................................................................... 31-27 OAM Support .............................................................................................................. 31-27 ATM-Layer OAM Definitions ................................................................................. 31-27

Virtual Path (F4) Flow Mechanism ......................................................................... 31-28 Virtual Channel (F5) Flow Mechanism ................................................................... 31-28 Receiving OAM F4 or F5 Cells ............................................................................... 31-28 Transmitting OAM F4 or F5 Cells........................................................................... 31-28

Performance Monitoring.......................................................................................... 31-29

Running a Performance Block Test ..................................................................... 31-30 PM Block Monitoring.......................................................................................... 31-30

PM Block Generation .......................................................................................... 31-31

BRC Performance Calculations ........................................................................... 31-32 User-Defined Cells (UDC) .......................................................................................... 31-32 UDC Extended Address Mode (UEAD).................................................................. 31-32

ATM Layer Statistics ................................................................................................... 31-33 ATM-to-TDM Interworking ........................................................................................ 31-33 Automatic Data Forwarding .................................................................................... 31-33

Using Interrupts in Automatic Data Forwarding ..................................................... 31-34

Timing Issues ........................................................................................................... 31-35 Clock Synchronization (SRTS and Adaptive FIFOs) .............................................. 31-35 Mapping TDM Time Slots to VCs........................................................................... 31-35 CAS Support ............................................................................................................ 31-35

Trunk Condition....................................................................................................... 31-36 ATM-to-ATM Data Forwarding............................................................................... 31-36 ATM Memory Structure............................................................................................... 31-36

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31.10.1.1

31.10.1.2

31.10.1.3

31.10.2

31.10.2.1

31.10.2.2

31.10.2.2.1

31.10.2.2.2

31.10.2.2.3

31.10.2.2.4

31.10.2.2.5

31.10.2.2.6

31.10.2.3

31.10.2.3.1

31.10.2.3.2

31.10.2.3.3

31.10.2.3.4

31.10.2.3.5

31.10.2.3.6

31.10.2.3.7

31.10.2.3.8

31.10.3

31.10.4

31.10.4.1

31.10.4.2

31.10.4.3

31.10.5

31.10.5.1

31.10.5.2

31.10.5.2.1

31.10.5.2.2

31.10.5.2.3

31.10.5.2.4

31.10.5.3

31.10.5.4

31.10.5.5

31.10.5.6

31.10.5.7

31.10.5.8

31.10.5.9

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Title Page Number

Parameter RAM ....................................................................................................... 31-36

Determining UEAD_OFFSET (UEAD Mode Only) .......................................... 31-39 VCI Filtering (VCIF) ........................................................................................... 31-39

Global Mode Entry (GMODE)............................................................................ 31-40

Connection Tables (RCT, TCT, and TCTE) ............................................................ 31-41 ATM Channel Code ............................................................................................. 31-41

Receive Connection Table (RCT)........................................................................ 31-43

AAL5 Protocol-Specific RCT ......................................................................... 31-46

AAL5-ABR Protocol-Specific RCT................................................................ 31-47 AAL1 Protocol-Specific RCT ......................................................................... 31-47

AAL0 Protocol-Specific RCT ......................................................................... 31-49

AAL1 CES Protocol-Specific RCT ................................................................. 31-50 AAL2 Protocol-Specific RCT ......................................................................... 31-50 Transmit Connection Table (TCT)....................................................................... 31-50

AAL5 Protocol-Specific TCT ......................................................................... 31-53

AAL1 Protocol-Specific TCT ......................................................................... 31-54

AAL0 Protocol-Specific TCT ......................................................................... 31-55 AAL1 CES Protocol-Specific TCT ................................................................. 31-55 AAL2 Protocol-Specific TCT ......................................................................... 31-55

VBR Protocol-Specific TCTE ......................................................................... 31-56

UBR+ Protocol-Specific TCTE....................................................................... 31-57 ABR Protocol-Specific TCTE ......................................................................... 31-57

OAM Performance Monitoring Tables .................................................................... 31-60

APC Data Structure ................................................................................................. 31-61

APC Parameter Tables ......................................................................................... 31-62

APC Priority Table .............................................................................................. 31-63 APC Scheduling Tables ....................................................................................... 31-63

ATM Controller Buffer Descriptors (BDs) .............................................................. 31-64 Transmit Buffer Operation................................................................................... 31-64

Receive Buffer Operation .................................................................................... 31-65 Static Buffer Allocation ................................................................................... 31-65

Global Buffer Allocation ................................................................................. 31-66

Free Buffer Pools ............................................................................................. 31-67

Free Buffer Pool Parameter Tables.................................................................. 31-68

ATM Controller Buffers....................................................................................... 31-69 AAL5 RxBD........................................................................................................ 31-69

AAL1 RxBD........................................................................................................ 31-71

AAL0 RxBD........................................................................................................ 31-72

AAL1 CES RxBD................................................................................................ 31-73 AAL2 RxBD........................................................................................................ 31-73 AAL5, AAL1 CES User-Defined Cell—RxBD Extension ................................. 31-73

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31.10.7

31.11

31.11.1

31.11.2

31.11.3

31.12

31.12.1

31.12.1.1

31.12.2

31.12.2.1

31.12.2.2

31.12.2.3

31.12.3

31.13

31.13.1

31.13.2

31.13.3

31.14

31.15

31.15.1

31.15.1.1

31.15.1.2

31.15.1.3

31.15.1.4

31.15.1.5

31.15.1.6

31.16

31.17

31.17.1

31.17.2

31.17.3

Contents

Title Page Number

AAL5 TxBDs....................................................................................................... 31-74

AAL1 TxBDs....................................................................................................... 31-75

AAL0 TxBDs....................................................................................................... 31-76

AAL1 CES TxBDs .............................................................................................. 31-77 AAL2 TxBDs....................................................................................................... 31-77 AAL5, AAL1 User-Defined Cell—TxBD Extension.......................................... 31-77 AAL1 Sequence Number (SN) Protection Table..................................................... 31-77

UNI Statistics Table ................................................................................................. 31-78

ATM Exceptions .......................................................................................................... 31-79 Interrupt Queues ...................................................................................................... 31-79

Interrupt Queue Entry .............................................................................................. 31-80 Interrupt Queue Parameter Tables ........................................................................... 31-80

The UTOPIA Interface ................................................................................................ 31-81 UTOPIA Interface Master Mode ............................................................................. 31-81

UTOPIA Master Multiple PHY Operation.......................................................... 31-82

UTOPIA Interface Slave Mode ............................................................................... 31-83

UTOPIA Slave Multiple PHY Operation ............................................................ 31-84 UTOPIA Clocking Modes ................................................................................... 31-84 UTOPIA Loop-Back Modes ................................................................................ 31-84

Extended Number of PHYs ..................................................................................... 31-85 ATM Registers ............................................................................................................. 31-85 General FCC Mode Register (GFMR)..................................................................... 31-85 FCC Protocol-Specific Mode Register (FPSMR).................................................... 31-85

ATM Event Register (FCCE)/Mask Register (FCCM)............................................ 31-88

ATM Transmit Command ............................................................................................ 31-89

Transmission Rate Modes—External, Internal, and Expanded Internal...................... 31-90

FCC Transmit Internal Rate Mode .......................................................................... 31-91 FCC Transmit Internal Rate Register (FTIRRx) ................................................. 31-91

Example ............................................................................................................... 31-92

Internal Rate Programming Model ...................................................................... 31-93 FCC Transmit Internal Rate Port Enable Registers (FIRPERx).......................... 31-93

FCC Internal Rate Event Registers (FIRERx) ..................................................... 31-94

FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO) ................... 31-95

SRTS Generation and Clock Recovery Using External Logic .................................... 31-97

Configuring the ATM Controller for Maximum CPM Performance ........................... 31-98 Using Transmit Internal Rate Mode ........................................................................ 31-98

APC Configuration .................................................................................................. 31-99 Buffer Configuration................................................................................................ 31-99

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32.1

32.2

32.2.1

32.2.2

32.3

32.4

32.4.1

32.4.1.1

32.4.1.2

32.4.2

32.4.3

32.4.4

32.4.5

32.4.6

32.4.7

32.4.7.1

32.4.7.2

32.4.7.2.1

32.4.7.3

32.4.7.3.1

32.5

32.5.1

32.6

32.6.1

32.7

32.8

32.8.1

32.9

32.9.1

32.9.1.1

32.9.2

32.9.2.1

32.10

32.11

32.11.1

32.11.2

32.12

32.12.1

Paragraph Number

Contents

Title

Chapter 32 ATM AAL1 Circuit Emulation Service

Page Number

Features .......................................................................................................................... 32-1

AAL1 CES Transmitter Overview................................................................................. 32-3 Data Path.................................................................................................................... 32-3 Signaling Path ............................................................................................................ 32-3

AAL1 CES Receiver Overview ..................................................................................... 32-4

Interworking Functions.................................................................................................. 32-6 Automatic Data Forwarding ...................................................................................... 32-6

ATM-to-TDM ........................................................................................................ 32-7 TDM-to-ATM ........................................................................................................ 32-7

Timing Issues ............................................................................................................. 32-8

Clock Synchronization (SRTS, Adaptive FIFO) ....................................................... 32-9 Mapping TDM Time Slots to VCs............................................................................. 32-9

Trunk Condition....................................................................................................... 32-10 Channel Associated Signaling (CAS) Support ........................................................ 32-10

Mapping VC Signaling to CAS Blocks ................................................................... 32-11

CAS Routing Table.............................................................................................. 32-12

TDM-to-ATM CAS Support................................................................................ 32-13

CAS Mapping Using the Core (Optional) ....................................................... 32-14 ATM-to-TDM CAS Support................................................................................ 32-14

CAS Updates Using the Core (Optional) ........................................................ 32-15 ATM-to-TDM Adaptive Slip Control .......................................................................... 32-15

CES Adaptive Threshold Tables.............................................................................. 32-16

3-Step-SN Algorithm ................................................................................................... 32-20 The Three States of the Algorithm .......................................................................... 32-20

Pointer Verification Mechanism .................................................................................. 32-21

AAL-1 Memory Structure............................................................................................ 32-22 AAL1 CES Parameter RAM.................................................................................... 32-22

Receive and Transmit Connection Tables (RCT, TCT) ............................................... 32-25

Receive Connection Table (RCT)............................................................................ 32-26

AAL1 CES Protocol-Specific RCT ..................................................................... 32-29

Transmit Connection Table (TCT)........................................................................... 32-32

AAL1 CES Protocol-Specific TCT ..................................................................... 32-34

Outgoing CAS Status Register (OCASSR) ................................................................ 32-36 Buffer Descriptors........................................................................................................ 32-36 Transmit Buffer Operation....................................................................................... 32-36

Receive Buffer Operation ........................................................................................ 32-37

ATM Controller Buffers............................................................................................... 32-38

AAL1 CES RxBD.................................................................................................... 32-39

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33.1

33.2

33.3

33.3.1

33.3.2

33.3.2.1

33.3.2.2

33.3.3

33.3.4

33.3.5

33.3.5.1

33.3.5.2

33.3.5.3

33.3.5.4

33.3.5.5

33.4

33.4.1

33.4.2

33.4.3

33.4.4

33.4.4.1

33.4.4.2

33.4.4.3

33.4.4.4

33.4.4.5

33.4.4.6

33.4.4.7

33.4.4.8

33.5

Paragraph Number

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32.13

32.13.1

32.14

32.15

32.16

32.17

32.18

Contents

Title Page Number

AAL1 CES TxBDs .................................................................................................. 32-40

AAL1 CES Exceptions ................................................................................................ 32-41 AAL1 CES Interrupt Queue Entry........................................................................... 32-41

AAL1 Sequence Number (SN) Protection Table ........................................................ 32-42

Internal AAL1 CES Statistics Tables........................................................................... 32-43

External AAL1 CES Statistics Tables.......................................................................... 32-44 CES-Specific Additions to the MCC ........................................................................... 32-44 Application Considerations.......................................................................................... 32-44

Chapter 33 ATM AAL2

Introduction.................................................................................................................... 33-1

Features .......................................................................................................................... 33-3

AAL2 Transmitter.......................................................................................................... 33-5 Transmitter Overview ................................................................................................ 33-5

Transmit Priority Mechanism .................................................................................... 33-6 Round Robin Priority............................................................................................. 33-6

Fixed Priority ......................................................................................................... 33-7 Partial Fill Mode (PFM) ............................................................................................ 33-7

No STF Mode ............................................................................................................ 33-8

AAL2 Tx Data Structures .......................................................................................... 33-9 AAL2 Protocol-Specific TCT................................................................................ 33-9

CPS Tx Queue Descriptor ................................................................................... 33-12

CPS Buffer Structure ........................................................................................... 33-14

SSSAR Tx Queue Descriptor .............................................................................. 33-16

SSSAR Transmit Buffer Descriptor..................................................................... 33-18

AAL2 Receiver ............................................................................................................ 33-19 Receiver Overview .................................................................................................. 33-19

Mapping of PHY | VP | VC | CID............................................................................ 33-20

AAL2 Switching ...................................................................................................... 33-21

AAL2 RX Data Structures ....................................................................................... 33-22

AAL2 Protocol-Specific RCT ............................................................................. 33-23

CID Mapping Tables and RxQDs........................................................................ 33-26 CPS Rx Queue Descriptors.................................................................................. 33-26

CPS Receive Buffer Descriptor (RxBD) ............................................................. 33-27

CPS Switch Rx Queue Descriptor ....................................................................... 33-28

SWITCH Receive/Transmit Buffer Descriptor (RxBD)...................................... 33-29

SSSAR Rx Queue Descriptor .............................................................................. 33-30

SSSAR Receive Buffer Descriptor ...................................................................... 33-32

AAL2 Parameter RAM ................................................................................................ 33-34

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34.1

34.1.1

34.1.2

34.1.3

34.1.4

34.1.5

34.1.6

34.2

34.2.1

34.2.2

34.2.3

34.2.3.1

34.2.3.2

34.3

34.3.1

34.3.1.1

34.3.1.2

34.3.2

34.3.2.1

34.3.2.1.1

34.3.2.2

34.3.2.3

34.3.2.4

34.3.3

34.3.3.1

34.3.3.2

34.3.3.2.1

34.3.3.2.2

34.3.3.3

34.4

34.4.1

34.4.2

34.4.2.1

34.4.2.1.1

34.4.2.1.2

Paragraph Number

33.6

33.7

Contents

Title Page Number

User-Defined Cells in AAL2 ....................................................................................... 33-37

AAL2 Exceptions ........................................................................................................ 33-38

Chapter 34 Inverse Multiplexing for ATM (IMA)

Features .......................................................................................................................... 34-1

References.................................................................................................................. 34-3 IMA Versions Supported ........................................................................................... 34-3 MPC8280 Versions Supported................................................................................... 34-3

PHY-Layer Devices Supported.................................................................................. 34-4 ATM Features Not Supported .................................................................................... 34-4 Additional Impact on MPC8280 Features ................................................................. 34-4 IMA Protocol Overview ............................................................................................... 34-4 Introduction................................................................................................................ 34-4

IMA Frame Overview................................................................................................ 34-5

Overview of IMA Cells ............................................................................................. 34-7 IMA Control Cells ................................................................................................. 34-7

IMA Filler Cells..................................................................................................... 34-8 IMA Microcode Architecture ........................................................................................ 34-8 IMA Function Partitioning......................................................................................... 34-8

User Plane Functions Performed by Microcode .................................................... 34-9 Plane Management Functions Performed by Microcode....................................... 34-9 Transmit Architecture ................................................................................................ 34-9

TRL Operation..................................................................................................... 34-10

TRL Service Latency....................................................................................... 34-11 Non-TRL Operation............................................................................................. 34-11

Transmit Queue Operation Examples (ITC mode).............................................. 34-12

Differences in CTC Operation ............................................................................. 34-14

Receive Architecture................................................................................................ 34-15 Cell Reception Task ............................................................................................. 34-15

Cell Processing Activation Function ................................................................... 34-18 On-Demand Cell Processing ........................................................................... 34-18

IDCR-Regulated Cell Processing .................................................................... 34-19

Cell Processing Task............................................................................................ 34-20 IMA Programming Model ........................................................................................... 34-20 Data Structure Organization .................................................................................... 34-20

IMA FCC Programming .......................................................................................... 34-22 FCC Registers ..................................................................................................... 34-22 FPSMRx .......................................................................................................... 34-22 FTIRRx ............................................................................................................ 34-22

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34.4.4.1.4

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34.4.4.2.4

34.4.5

34.4.5.1

34.4.5.1.1

34.4.5.1.2

34.4.5.1.3

34.4.5.2

34.4.5.2.1

34.4.5.2.2

34.4.5.3

34.4.6

34.4.6.1

34.4.6.2

34.4.7

34.4.7.1

34.4.7.2

34.4.8

34.4.8.1

34.4.8.2

34.4.8.2.1

34.4.8.2.2

34.4.8.2.3

34.4.8.3

34.4.8.4

34.4.8.5

Contents

Title Page Number

FCC Parameters ................................................................................................... 34-22 TCELL_TMP_BASE and RCELL_TMP_BASE ........................................... 34-22 GMODE........................................................................................................... 34-22 IMA-Specific FCC Parameters............................................................................ 34-22

IMA Root Table ....................................................................................................... 34-23

IMA Control (IMACNTL) .................................................................................. 34-25 IMA Group Tables ................................................................................................... 34-25 IMA Group Transmit Table Entry ....................................................................... 34-25

IMA Group Transmit Control (IGTCNTL) .................................................... 34-27 IMA Group Transmit State (IGTSTATE) ....................................................... 34-27

Transmit Group Order Table............................................................................ 34-28

ICP Cell Templates .......................................................................................... 34-29

IMA Group Receive Table Entry......................................................................... 34-31

IMA Group Receive Control (IGRCNTL) ..................................................... 34-34 IMA Group Receive State (IGRSTATE) ........................................................ 34-34

IMA Receive Group Frame Size .................................................................... 34-35 Receive Group Order Tables ........................................................................... 34-35

IMA Link Tables...................................................................................................... 34-36 IMA Link Transmit Table Entry .......................................................................... 34-36

IMA Link Transmit Control (ILTCNTL) ....................................................... 34-37

IMA Link Transmit State (ILTSTATE) .......................................................... 34-38

IMA Transmit Interrupt Status (ITINTSTAT) ................................................ 34-39

IMA Link Receive Table Entry ........................................................................... 34-40

IMA Link Receive Control (ILRCNTL) ........................................................ 34-41

IMA Link Receive State (ILRSTATE) ........................................................... 34-42

IMA Link Receive Statistics Table ...................................................................... 34-43 Structures in External Memory................................................................................ 34-43

Transmit Queues .................................................................................................. 34-44 Delay Compensation Buffers (DCB)................................................................... 34-44

IMA Exceptions ....................................................................................................... 34-45 IMA Interrupt Queue Entry ................................................................................. 34-45

ICP Cell Reception Exceptions ........................................................................... 34-46

IDCR Timer Programming ...................................................................................... 34-47 IDCR Master Clock ............................................................................................. 34-47 IDCR FCC Parameter Shadow ............................................................................ 34-47 MPC8280 Features Unavailable if IDCR is Used ........................................... 34-47

Programming the FCC Parameter Shadow...................................................... 34-48 On-the-Fly Changes of FCC Parameters ......................................................... 34-48

IDCR_Init Command........................................................................................... 34-49 IDCR Root Parameters ........................................................................................ 34-49 IDCR Table Entry ................................................................................................ 34-49

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34.5.1

34.5.2

34.5.3

34.5.3.1

34.5.3.2

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34.5.3.6

34.5.3.7

34.5.3.8

34.5.3.9

34.5.3.10

34.5.3.11

34.5.3.12

34.5.3.13

34.5.4

34.5.4.1

34.5.4.2

34.5.4.3

34.5.4.3.1

34.5.4.3.2

34.5.4.4

34.5.4.4.1

34.5.4.4.2

34.5.4.5

34.5.4.5.1

34.5.4.5.2

34.5.4.6

34.5.4.7

34.5.4.8

34.5.4.9

34.5.4.10

34.5.4.11

Contents

Title Page Number

IDCR Counter Algorithm .................................................................................... 34-50 IDCR Events ........................................................................................................ 34-50

APC Programming for IMA .................................................................................... 34-51

Programming for CBR, UBR, VBR, and UBR+ ................................................. 34-52 Programming for ABR ........................................................................................ 34-52

Changing IMA Version............................................................................................ 34-53 IMA Software Interface and Requirements ................................................................. 34-53 Software Model........................................................................................................ 34-53

Initialization Procedure............................................................................................ 34-54 Software Responsibilities ........................................................................................ 34-54 System Definition ................................................................................................ 34-54

General Operation................................................................................................ 34-55 Receive Link State Machine Control................................................................... 34-55 Receive Group State Machine Control ................................................................ 34-55 Transmit Link State Machine Control ................................................................. 34-55

Transmit Group State Machine Control............................................................... 34-56 Group Symmetry Control .................................................................................... 34-56 ICP End-to-End Channel Transmission............................................................... 34-56 Link Addition and Slow Recovery (LASR) Procedure ....................................... 34-56 Failure Alarms ..................................................................................................... 34-56

Test Pattern Control ............................................................................................. 34-57 Performance Parameter Measurement and Reporting ......................................... 34-57 SNMP MIBs ........................................................................................................ 34-57 IMA Software Procedures ....................................................................................... 34-57 Transmit ICP Cell Signalling............................................................................... 34-57 Receive Link Start-up Procedure ......................................................................... 34-57

Group Start-up Procedure ................................................................................... 34-58

As Initiator (TX).............................................................................................. 34-59

As Responder (RX) ......................................................................................... 34-60 Link Addition Procedure ..................................................................................... 34-60

Rx Steps ........................................................................................................... 34-61 TX Parameters ................................................................................................. 34-61

Link Removal Procedure ..................................................................................... 34-62 Rx Steps ........................................................................................................... 34-62

TX Parameters ................................................................................................. 34-63 Link Receive Deactivation Procedure ................................................................. 34-63

Link Receive Reactivation Procedure ................................................................. 34-64 TRL On-the-Fly Change Procedure..................................................................... 34-64

Transmit Event Response Procedures.................................................................. 34-65 Receive Event Response Procedures ................................................................... 34-65

Test Pattern Procedure ......................................................................................... 34-67

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35.1

35.2

35.2.1

35.2.1.1

35.2.2

35.2.2.1

35.2.3

35.2.4

35.3

35.4

35.4.1

35.4.1.1

35.4.1.2

35.4.1.3

35.4.1.4

35.4.2

35.4.2.1

35.4.2.2

35.4.3

35.4.3.1

35.4.3.2

35.4.3.3

35.4.3.4

35.4.3.5

35.4.3.6

35.4.4

35.4.5

35.4.5.1

35.4.5.2

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34.5.4.11.2

34.5.4.12

34.5.4.12.1

34.5.4.12.2

34.5.4.13

34.5.4.13.1

34.5.4.13.2

Contents

Title Page Number

As Initiator (NE).............................................................................................. 34-67 As Responder (FE) .......................................................................................... 34-67

IDCR Operation................................................................................................... 34-68 IDCR Start-up.................................................................................................. 34-68

Activating a Group in IDCR Mode ................................................................. 34-69 End-to-End Channel Signalling Procedure.......................................................... 34-69 Transmit ........................................................................................................... 34-69

Receive ............................................................................................................ 34-70

Chapter 35 ATM Transmission Convergence Layer

Features .......................................................................................................................... 35-2

Functionality .................................................................................................................. 35-3 Receive ATM Cell Functions..................................................................................... 35-3

Receive ATM 2-Cell FIFO .................................................................................... 35-5 Transmit ATM Cell Functions ................................................................................... 35-5

Transmit ATM 2-Cell FIFO ................................................................................... 35-6 Receive UTOPIA Interface........................................................................................ 35-6 Transmit UTOPIA Interface ...................................................................................... 35-6 Signals............................................................................................................................ 35-6 TC Layer Programming Mode ...................................................................................... 35-6 TC Layer Registers .................................................................................................... 35-6

TC Layer Mode Registers 1–8 (TCMODEx) ........................................................ 35-7

Cell Delineation State Machine Registers 1–8 (CDSMRx)................................... 35-8

TC Layer Event Registers 1–8 (TCERx) ............................................................... 35-9

TC Layer Mask Register (TCMRx)..................................................................... 35-10 TC Layer General Registers .................................................................................... 35-10 TC Layer General Event Register (TCGER)....................................................... 35-10

TC Layer General Status Register (TCGSR)....................................................... 35-11 TC Layer Cell Counters ........................................................................................... 35-11 Received Cell Counters 1–8 (TC_RCCx)............................................................ 35-11 Transmitted Cell Counters 1–8 (TC_TCCx)........................................................ 35-11

Errored Cell Counters 1–8 (TC_ECCx)............................................................... 35-12 Corrected Cell Counters 1–8 (TC_CCCx) ........................................................... 35-12 Transmitted IDLE Cell Counters 1–8 (TC_ICCx)............................................... 35-12 Filtered Cell Counters 1–8 (TC_FCCx)............................................................... 35-12 Programming FCC2................................................................................................. 35-12 Programming and Operating the TC Layer ............................................................. 35-12 Receive ................................................................................................................ 35-12

Transmit ............................................................................................................... 35-13

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36.1

36.2

36.3

36.3.1

36.4

36.5

36.6

36.7

36.8

36.9

36.10

36.11

36.12

36.13

36.14

36.15

36.16

36.17

36.18

36.18.1

36.18.2

36.19

36.20

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35.5.1

35.5.2

35.5.3

35.5.4

35.5.5

35.5.6

35.5.7

35.5.8

35.5.9

Contents

Title Page Number

Implementation Example ............................................................................................. 35-15 Operating the TC Layer at Higher Frequencies....................................................... 35-15 Programming a T1 Application ............................................................................... 35-15

Step 1 ....................................................................................................................... 35-16 Step 2 ....................................................................................................................... 35-16 Step 3 ....................................................................................................................... 35-16 Step 4 ....................................................................................................................... 35-16

Step 5 ....................................................................................................................... 35-17 Step 6 ....................................................................................................................... 35-17 Step 7 ....................................................................................................................... 35-17

Chapter 36 Fast Ethernet Controller

Fast Ethernet on the MPC8280 ...................................................................................... 36-2 Features .......................................................................................................................... 36-2

Connecting the MPC8280 to Fast Ethernet ................................................................... 36-4

Connecting the MPC8280 to Ethernet (RMII) .......................................................... 36-5 Ethernet Channel Frame Transmission .......................................................................... 36-5

Ethernet Channel Frame Reception ............................................................................... 36-6

Flow Control .................................................................................................................. 36-7

CAM Interface ............................................................................................................... 36-8 Ethernet Parameter RAM............................................................................................... 36-8

Programming Model .................................................................................................... 36-12 Ethernet Command Set ................................................................................................ 36-12

RMON Support............................................................................................................ 36-14

Ethernet Address Recognition ..................................................................................... 36-15

Hash Table Algorithm.................................................................................................. 36-17

Interpacket Gap Time................................................................................................... 36-18 Handling Collisions ..................................................................................................... 36-18 Internal and External Loopback................................................................................... 36-18 Ethernet Error-Handling Procedure ............................................................................. 36-18

Fast Ethernet Registers ................................................................................................ 36-19 FCC Ethernet Mode Registers (FPSMRx)............................................................... 36-19

Ethernet Event Register (FCCE)/Mask Register (FCCM) ...................................... 36-21

Ethernet RxBDs ........................................................................................................... 36-23

Ethernet TxBDs ........................................................................................................... 36-26

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37.2

37.3

37.4

37.5

37.5.1

37.5.2

37.6

37.7

37.8

37.9

37.10

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Contents

Title

Chapter 37 FCC HDLC Controller

Page Number

Key Features .................................................................................................................. 37-1

HDLC Channel Frame Transmission Processing .......................................................... 37-2

HDLC Channel Frame Reception Processing ............................................................... 37-3 HDLC Parameter RAM ................................................................................................. 37-3

Programming Model ...................................................................................................... 37-5 HDLC Command Set................................................................................................. 37-5

HDLC Error Handling ............................................................................................... 37-6

HDLC Mode Register (FPSMR) ................................................................................... 37-8

HDLC Receive Buffer Descriptor (RxBD).................................................................... 37-9

HDLC Transmit Buffer Descriptor (TxBD) ................................................................ 37-12

HDLC Event Register (FCCE)/Mask Register (FCCM) ............................................. 37-14

FCC Status Register (FCCS) ....................................................................................... 37-16

38.1

38.2

38.3

38.3.1

38.3.2

38.3.3

39.1

39.2

39.3

39.3.1

39.3.2

39.3.3

39.4

39.4.1

39.4.1.1

39.4.2

39.4.3

39.5

Chapter 38 FCC Transparent Controller

Features .......................................................................................................................... 38-1

Transparent Channel Operation ..................................................................................... 38-2 Achieving Synchronization in Transparent Mode ......................................................... 38-2 In-Line Synchronization Pattern................................................................................ 38-2

External Synchronization Signals .............................................................................. 38-3

Transparent Synchronization Example ...................................................................... 38-4

Chapter 39 Serial Peripheral Interface (SPI)

Features .......................................................................................................................... 39-1

SPI Clocking and Signal Functions ............................................................................... 39-2 Configuring the SPI Controller...................................................................................... 39-2

The SPI as a Master Device ....................................................................................... 39-3

The SPI as a Slave Device ......................................................................................... 39-4 The SPI in Multimaster Operation............................................................................. 39-4

Programming the SPI Registers ..................................................................................... 39-6 SPI Mode Register (SPMODE) ................................................................................. 39-6

SPI Examples with Different SPMODE[LEN] Values.......................................... 39-8

SPI Event/Mask Registers (SPIE/SPIM) ................................................................... 39-9

SPI Command Register (SPCOM) .......................................................................... 39-10 SPI Parameter RAM .................................................................................................... 39-10

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40.1

40.2

40.3

40.3.1

40.3.2

40.3.3

40.3.4

40.4

40.4.1

40.4.2

40.4.3

40.4.4

40.4.5

40.5

40.6

40.7

40.7.1

40.7.1.1

40.7.1.2

Paragraph Number

39.5.1

39.6

39.7

39.7.1

39.7.1.1

39.7.1.2

39.8

39.9

39.10

Contents

Title Page Number

Receive/Transmit Function Code Registers (RFCR/TFCR).................................... 39-12 SPI Commands ............................................................................................................ 39-12

The SPI Buffer Descriptor (BD) Table ........................................................................ 39-13 SPI Buffer Descriptors (BDs) .................................................................................. 39-13

SPI Receive BD (RxBD) ..................................................................................... 39-14

SPI Transmit BD (TxBD) .................................................................................... 39-15

SPI Master Programming Example ............................................................................. 39-16

SPI Slave Programming Example................................................................................ 39-17 Handling Interrupts in the SPI ..................................................................................... 39-17

41.1

41.2

41.2.1

41.2.2

41.2.3

Chapter 40

I 2

C Controller

Features .......................................................................................................................... 40-2 I

2 C Controller Clocking and Signal Functions .............................................................. 40-2

I

2 C Controller Transfers ................................................................................................ 40-2

I

2 C Master Write (Slave Read).................................................................................. 40-3

I2C Loopback Testing................................................................................................ 40-4 I2C Master Read (Slave Write).................................................................................. 40-4

I2C Multi-Master Considerations .............................................................................. 40-5 I

2 C Registers .................................................................................................................. 40-5

I2C Mode Register (I2MOD) .................................................................................... 40-6

I2C Address Register (I2ADD) ................................................................................. 40-7 I2C Baud Rate Generator Register (I2BRG) ............................................................. 40-7 I

2 C Event/Mask Registers (I2CER/I2CMR) ............................................................. 40-7

I2C Command Register (I2COM) ............................................................................. 40-8

I

2 C Parameter RAM....................................................................................................... 40-9

I

2 C Commands............................................................................................................. 40-11

The I 2

C Buffer Descriptor (BD) Table ........................................................................ 40-11

I2C Buffer Descriptors (BDs).................................................................................. 40-12 I2C Receive Buffer Descriptor (RxBD) .............................................................. 40-12

I2C Transmit Buffer Descriptor (TxBD) ............................................................. 40-13

Chapter 41 Parallel I/O Ports

Features .......................................................................................................................... 41-1 Port Registers ................................................................................................................. 41-1

Port Open-Drain Registers (PODRA–PODRD) ........................................................ 41-2 Port Data Registers (PDATA–PDATD) ..................................................................... 41-2

Port Data Direction Registers (PDIRA–PDIRD)....................................................... 41-3

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41.2.5

41.3

41.4

41.4.1

41.4.2

41.5

41.6

Contents

Title Page Number

Port Pin Assignment Register (PPAR)....................................................................... 41-4 Port Special Options Registers A–D (PSORA–PSORD) .......................................... 41-4

Port Block Diagram ....................................................................................................... 41-6 Port Pins Functions ........................................................................................................ 41-6

General Purpose I/O Pins........................................................................................... 41-7 Dedicated Pins ........................................................................................................... 41-7 Ports Tables .................................................................................................................... 41-7

Interrupts from Port C.................................................................................................. 41-20

A.1

A.2

A.3

Appendix A Register Quick Reference Guide

PowerPC Registers—User Registers .............................................................................. A-1 PowerPC Registers—Supervisor Registers .................................................................... A-1

MPC8280-Specific SPRs ................................................................................................ A-3

Appendix B Revision History

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Figures

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4-12

4-13

4-14

4-15

4-16 4-17

Figure Number Title Page Number

Figures

MPC8280 Block Diagram....................................................................................................... 1-6

MPC8280 External Signals ..................................................................................................... 1-9

Remote Access Server Configuration ................................................................................... 1-13

Regional Office Router Configuration.................................................................................. 1-14

LAN-to-WAN Bridge Router Configuration ........................................................................ 1-15 Cellular Base Station Configuration ..................................................................................... 1-15

Telecommunications Switch Controller Configuration ........................................................ 1-16

SONET Transmission Controller Configuration .................................................................. 1-17

Basic System Configuration.................................................................................................. 1-18 High-Performance Communication ...................................................................................... 1-18

High-Performance System Microprocessor Configuration................................................... 1-19

PCI Configuration ................................................................................................................. 1-20 PCI with 155-Mbps ATM Configuration .............................................................................. 1-20

MPC8280 as PCI Agent ........................................................................................................ 1-21

MPC8280 Integrated Processor Core Block Diagram ............................................................ 2-2

MPC8280 Programming Model—Registers ......................................................................... 2-10

Hardware Implementation Register 0 (HID0) ...................................................................... 2-11

Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-14 Hardware Implementation-Dependent Register 2 (HID2).................................................... 2-14

Data Cache Organization ...................................................................................................... 2-19

Internal Memory ..................................................................................................................... 3-1

SIU Block Diagram................................................................................................................. 4-1

System Configuration and Protection Logic ........................................................................... 4-3

Timers Clock Generation ........................................................................................................ 4-4

TMCNT Block Diagram ......................................................................................................... 4-5 PIT Block Diagram ................................................................................................................. 4-5

Software Watchdog Timer Service State Diagram.................................................................. 4-6

Software Watchdog Timer Block Diagram ............................................................................. 4-7

MPC8280 Interrupt Structure.................................................................................................. 4-8

Interrupt Request Masking.................................................................................................... 4-14

SIU Interrupt Configuration Register (SICR) ....................................................................... 4-17

SIU Interrupt Priority Register (SIPRR) ............................................................................... 4-18

CPM High Interrupt Priority Register (SCPRR_H).............................................................. 4-19

CPM Low Interrupt Priority Register (SCPRR_L)............................................................... 4-20

SIPNR_H .............................................................................................................................. 4-21

SIPNR_L ............................................................................................................................... 4-22

SIMR_H ................................................................................................................................ 4-23 SIMR_L ................................................................................................................................ 4-23

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Figures

Figure Number

4-18

4-19

4-20

4-21

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4-23

4-24 4-25

4-26

4-27 4-28

4-29

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4-31

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7-1

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4-40

4-41

4-42

5-1

5-2

5-3

5-4

5-5

5-6

5-7

Title Page Number

SIU Interrupt Vector Register (SIVEC) ................................................................................ 4-24

Interrupt Table Handling Example........................................................................................ 4-25

SIU External Interrupt Control Register (SIEXR) ................................................................ 4-26

Bus Configuration Register (BCR) ....................................................................................... 4-27

PPC_ACR ............................................................................................................................. 4-29

PPC_ALRH........................................................................................................................... 4-30

PPC_ALRL ........................................................................................................................... 4-31 LCL_ACR ............................................................................................................................. 4-31

LCL_ALRH .......................................................................................................................... 4-32

LCL_ALRL........................................................................................................................... 4-33 SIU Model Configuration Register (SIUMCR) .................................................................... 4-33

Internal Memory Map Register (IMMR) .............................................................................. 4-36

System Protection Control Register (SYPCR)...................................................................... 4-37

60x Bus Transfer Error Status and Control Register 1 (TESCR1) ....................................... 4-39

60x Bus Transfer Error Status and Control Register 2 (TESCR2) ....................................... 4-41

Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) ................................ 4-42

Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) ................................ 4-43

Time Counter Status and Control Register (TMCNTSC) ..................................................... 4-44

Time Counter Register (TCMCNT)...................................................................................... 4-45 Time Counter Alarm Register (TMCNTAL) ........................................................................ 4-45

Periodic Interrupt Status and Control Register (PISCR)....................................................... 4-46

Periodic interrupt Timer Count Register (PITC) .................................................................. 4-47

Periodic Interrupt Timer Register (PITR) ............................................................................. 4-48

PCI Base Registers (PCIBRx)............................................................................................... 4-49

PCI Mask Register (PCIMSKx)............................................................................................ 4-50

Power-on Reset Flow .............................................................................................................. 5-3

Reset Status Register (RSR).................................................................................................... 5-4

Reset Mode Register (RMR)................................................................................................... 5-5

Hard Reset Configuration Word.............................................................................................. 5-8

Single Chip with Default Configuration ............................................................................... 5-10

Configuring a Single Chip from EPROM............................................................................. 5-11

Configuring Multiple Chips .................................................................................................. 5-12

MPC8280 External Signals ..................................................................................................... 6-2

Signal Groupings..................................................................................................................... 7-2

Single-MPC8280 Bus Mode ................................................................................................... 8-3

60x-Compatible Bus Mode ..................................................................................................... 8-4

Basic Transfer Protocol........................................................................................................... 8-5

Address Bus Arbitration with External Bus Master................................................................ 8-8

Address Pipelining .................................................................................................................. 8-9

Interface to Different Port Size Devices ............................................................................... 8-16

Retry Cycle ........................................................................................................................... 8-22

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Figures

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9-15

9-16

9-17

9-18

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9-22

9-23

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9-25

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9-28

9-29

9-30

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9-32

9-33 9-34

Figure Number

8-8

8-9

8-10

8-11

8-12

9-1 9-2

9-3 9-4

9-5 9-6

9-7

9-8

9-9

9-10

9-11

9-12

9-13

Title Page Number

Single-Beat and Burst Data Transfers ................................................................................... 8-26

28-Bit Extended Transfer to 32-Bit Port Size ....................................................................... 8-27

Burst Transfer to 32-Bit Port Size......................................................................................... 8-28

Data Tenure Terminated by Assertion of TEA ..................................................................... 8-29

MEI Cache Coherency Protocol—State Diagram (WIM = 001) .......................................... 8-30

PCI Bridge in the MPC8280 ................................................................................................... 9-2 PCI Bridge Structure ............................................................................................................... 9-2

Single Beat Read Example.................................................................................................... 9-10 Burst Read Example.............................................................................................................. 9-10

Single Beat Write Example ................................................................................................... 9-11 Burst Write Example ............................................................................................................. 9-11

Target-Initiated Terminations ................................................................................................ 9-12

PCI Configuration Type 0 Translation (Top = CONFIG_ADDR) (Bottom = PCI Address Lines) .............................................. 9-15

PCI Parity Operation ............................................................................................................. 9-18

PCI Arbitration Example ...................................................................................................... 9-20

Address Decode Flow Chart for 60x Bus Mastered Transactions ........................................ 9-21

Address Decode Flow Chart for PCI Mastered Transactions ............................................... 9-22

Address Decode Flow Chart for Embedded Utilities (DMA, Message Unit) Mastered Transactions................................................................. 9-23

Address Map Example .......................................................................................................... 9-24

Inbound PCI Memory Address Translation .......................................................................... 9-25

Outbound PCI Memory Address Translation ....................................................................... 9-26

PCI Outbound Translation Address Registers (POTARx) .................................................... 9-30

PCI Outbound Base Address Registers (POBARx).............................................................. 9-31

PCI Outbound Comparison Mask Registers (POCMRx) ..................................................... 9-32

Discard Timer Control register (PTCR) ................................................................................ 9-33

General Purpose Control Register (GPCR) .......................................................................... 9-34

PCI General Control Register (PCI_GCR) ........................................................................... 9-35

Error Status Register (ESR) .................................................................................................. 9-36

Error Mask Register (EMR).................................................................................................. 9-37

Error Control Register (ECR) ............................................................................................... 9-38

PCI Error Address Capture Register (PCI_EACR) .............................................................. 9-39

PCI Error Data Capture Register (PCI_EDCR) .................................................................... 9-40

PCI Error Control Capture Register (PCI_ECCR) ............................................................... 9-41

PCI Inbound Translation Address Registers (PITARx) ........................................................ 9-42

PCI Inbound Base Address Registers (PIBARx) .................................................................. 9-43

PCI Inbound Comparison Mask Registers (PICMRx).......................................................... 9-44

PCI Bridge PCI Configuration Registers .............................................................................. 9-46

Vendor ID Register................................................................................................................ 9-47 Device ID Register................................................................................................................ 9-47

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9-46 9-47

9-48 9-49

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Figure Number

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9-37 9-38

9-39 9-40

9-41 9-42

9-43 9-44

9-45

Title Page Number

PCI Bus Command Register ................................................................................................. 9-48

PCI Bus Status Register ........................................................................................................ 9-49

Revision ID Register ............................................................................................................. 9-50 PCI Bus Programming Interface Register............................................................................. 9-50

Subclass Code Register ......................................................................................................... 9-51 PCI Bus Base Class Code Register ....................................................................................... 9-51

PCI Bus Cache Line Size Register........................................................................................ 9-52 PCI Bus Latency Timer Register .......................................................................................... 9-52

Header Type Register ............................................................................................................ 9-53 BIST Control Register .......................................................................................................... 9-53

PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR).................................................................................................................. 9-54

General Purpose Local Access Base Address Registers (GPLABARx)............................... 9-55 Subsystem Vendor ID Register ............................................................................................. 9-55

Subsystem Device ID Register ............................................................................................. 9-56 PCI Bus Capabilities Pointer Register .................................................................................. 9-56

PCI Bus Interrupt Line Register............................................................................................ 9-57 PCI Bus Interrupt Pin Register.............................................................................................. 9-57

PCI Bus MIN GNT ............................................................................................................... 9-58 PCI Bus MAX LAT............................................................................................................... 9-58

PCI Bus Function Register.................................................................................................... 9-59

PCI Bus Arbiter Configuration Register ............................................................................... 9-60

Hot Swap Register Block ...................................................................................................... 9-61 Hot Swap Control Status Register......................................................................................... 9-61

Data Structure for Register Initialization .............................................................................. 9-64

PCI Configuration Data Structure for the EEPROM ............................................................ 9-66

Inbound Message Registers (IMRx) ..................................................................................... 9-67

Outbound Message Registers (OMRx) ................................................................................. 9-68

Outbound Doorbell Register (ODR) ..................................................................................... 9-69 Inbound Doorbell Register (IDR) ......................................................................................... 9-69

I 2

O Message Queue .............................................................................................................. 9-71

Inbound Free_FIFO Head Pointer Register (IFHPR) ........................................................... 9-72

Inbound Free_FIFO Tail Pointer Register (IFTPR) .............................................................. 9-73

Inbound Post_FIFO Head Pointer Register (IPHPR) ........................................................... 9-74 Inbound Post_FIFO Tail Pointer Register (IPTPR) .............................................................. 9-74

Outbound Free_FIFO Head Pointer Register (OFHPR) ....................................................... 9-75

Outbound Free_FIFO Tail Pointer Register (OFTPR).......................................................... 9-76

Outbound Post_FIFO Head Pointer Register (OPHPR) ....................................................... 9-77

Outbound Post_FIFO Tail Pointer Register (OPTPR) .......................................................... 9-78

Inbound FIFO Queue Port Register (IFQPR) ....................................................................... 9-79 Outbound FIFO Queue Port Register (OFQPR) ................................................................... 9-79

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Figure Number

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9-76

9-77

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Outbound Message Interrupt Status Register (OMISR) ....................................................... 9-80

Outbound Message Interrupt Mask Register (OMIMR)....................................................... 9-81

Inbound Message Interrupt Status Register (IMISR)............................................................ 9-82

Inbound Message Interrupt Mask Register (IMIMR) ........................................................... 9-83

Messaging Unit Control Register (MUCR) .......................................................................... 9-84

Queue Base Address Register (QBAR) ................................................................................ 9-85

DMA Controller Block Diagram .......................................................................................... 9-86

DMA Mode Registers 0–3 (DMAMRx) ............................................................................... 9-89

DMA Status Registers 0–3 (DMASRx) ................................................................................ 9-91

DMA Current Descriptor Address Registers 0–3 (DMACDARx) ....................................... 9-92

DMA Source Address Registers 0–3 (DMASARx).............................................................. 9-93

DMA Destination Address Registers 0–3 (DMADARx)...................................................... 9-94

DMA Byte Count Registers 0–3 (DMABCRx) .................................................................... 9-95 DMA Next Descriptor Address Registers 0–3 (DMANDARx)............................................ 9-95

DMA Chain of Segment Descriptors .................................................................................... 9-97

MPC8280 System Clock Architecture .................................................................................. 10-3

PCI Bridge as an Agent, Operating from the PCI System Clock ......................................... 10-4

PCI Bridge as a Host, Generating the PCI System Clock..................................................... 10-5 PLL Filtering Circuit............................................................................................................. 10-5

System Clock Control Register (SCCR) ............................................................................... 10-6

System Clock Mode Register (SCMR) ................................................................................. 10-7

Dual-Bus Architecture .......................................................................................................... 11-2

Memory Controller Machine Selection................................................................................. 11-5

Simple System Configuration ............................................................................................... 11-6

Basic Memory Controller Operation..................................................................................... 11-7

Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer ............................11-11

Base Registers (BRx) .......................................................................................................... 11-13

Option Registers (ORx)—SDRAM Mode .......................................................................... 11-15

ORx —GPCM Mode........................................................................................................... 11-17

ORx—UPM Mode .............................................................................................................. 11-19

60x/Local SDRAM Mode Register (PSDMR/LSDMR) .................................................... 11-20

Machine x Mode Registers (MxMR) .................................................................................. 11-26

Memory Data Register (MDR) ........................................................................................... 11-29 Memory Address Register (MAR)...................................................................................... 11-29

60x Bus-Assigned UPM Refresh Timer (PURT)................................................................ 11-30 Local Bus-Assigned UPM Refresh Timer (LURT)............................................................. 11-30

60x Bus-Assigned SDRAM Refresh Timer (PSRT) ........................................................... 11-31

Local Bus-Assigned SDRAM Refresh Timer (LSRT)........................................................ 11-32 Memory Refresh Timer Prescaler Register (MPTPR) ........................................................ 11-32

128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) ......................... 11-34

PRETOACT = 2 (2 Clock Cycles)...................................................................................... 11-39

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Figures

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ACTTORW = 2 (2 Clock Cycles)....................................................................................... 11-40 CL = 2 (2 Clock Cycles) ..................................................................................................... 11-40

LDOTOPRE = 2 (–2 Clock Cycles).................................................................................... 11-41 WRC = 2 (2 Clock Cycles) ................................................................................................. 11-41

RFRC = 4 (6 Clock Cycles) ................................................................................................ 11-42 EAMUX = 1........................................................................................................................ 11-42

BUFCMD = 1...................................................................................................................... 11-43 SDRAM Single-Beat Read, Page Closed, CL = 3 .............................................................. 11-43

SDRAM Single-Beat Read, Page Hit, CL = 3 .................................................................... 11-44 SDRAM Two-Beat Burst Read, Page Closed, CL = 3........................................................ 11-44 SDRAM Four-Beat Burst Read, Page Miss, CL = 3........................................................... 11-44

SDRAM Single-Beat Write, Page Hit................................................................................. 11-45 SDRAM Three-Beat Burst Write, Page Closed .................................................................. 11-45 SDRAM Read-after-Read Pipeline, Page Hit, CL = 3........................................................ 11-45

SDRAM Write-after-Write Pipelined, Page Hit.................................................................. 11-46 SDRAM Read-after-Write Pipelined, Page Hit .................................................................. 11-46

SDRAM Mode-Set Command Timing ............................................................................... 11-47 Mode Data Bit Settings ....................................................................................................... 11-47

SDRAM Bank-Staggered CBR Refresh Timing................................................................. 11-48

GPCM-to-SRAM Configuration......................................................................................... 11-52

GPCM Peripheral Device Interface .................................................................................... 11-54

GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................................. 11-55 GPCM Memory Device Interface ....................................................................................... 11-55

GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)....................... 11-56 GPCM Memory Device Basic Timing (ACS ≠

00, CSNT = 1, TRLX = 0)....................... 11-56

GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) .................... 11-57 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1) .................... 11-57

GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) ................... 11-58 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) ................... 11-58

GPCM Read Followed by Read (ORx[29–30] = 00, Fastest Timing) ................................ 11-59

GPCM Read Followed by Read (ORx[29–30] = 01).......................................................... 11-60 GPCM Read Followed by Write (ORx[29–30] = 01) ......................................................... 11-60

GPCM Read Followed by Write (ORx[29–30] = 10) ......................................................... 11-61

External Termination of GPCM Access.............................................................................. 11-62

User-Programmable Machine Block Diagram.................................................................... 11-64

RAM Array Indexing .......................................................................................................... 11-65

Memory Refresh Timer Request Block Diagram ............................................................... 11-66

Memory Controller UPM Clock Scheme for Integer Clock Ratios.................................... 11-68

Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios ................................................................................................................... 11-69

UPM Signals Timing Example ........................................................................................... 11-70

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

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RAM Array and Signal Generation .................................................................................... 11-71 The RAM Word................................................................................................................... 11-71

CS Signal Selection............................................................................................................. 11-76 BS Signal Selection............................................................................................................. 11-76

UPM Read Access Data Sampling...................................................................................... 11-79

Wait Mechanism Timing for Internal and External Synchronous Masters ......................... 11-80

DRAM Interface Connection to the 60x Bus (64-Bit Port Size) ........................................ 11-82

Single-Beat Read Access to FPM DRAM .......................................................................... 11-84

Single-Beat Write Access to FPM DRAM ......................................................................... 11-85

Burst Read Access to FPM DRAM (No LOOP) ................................................................ 11-86

Burst Read Access to FPM DRAM (LOOP) ...................................................................... 11-87

Burst Write Access to FPM DRAM (No LOOP)................................................................ 11-88

Refresh Cycle (CBR) to FPM DRAM ................................................................................ 11-89

Exception Cycle .................................................................................................................. 11-90

FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)................. 11-92

MPC8280/EDO Interface Connection to the 60x Bus ........................................................ 11-93

Single-Beat Read Access to EDO DRAM .......................................................................... 11-94

Single-Beat Write Access to EDO DRAM ......................................................................... 11-95

Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States ...................................................................................................................... 11-96

Burst Read Access to EDO DRAM .................................................................................... 11-97

Burst Write Access to EDO DRAM ................................................................................... 11-98

Refresh Cycle (CBR) to EDO DRAM ................................................................................ 11-99

Exception Cycle For EDO DRAM ................................................................................... 11-100

Pipelined Bus Operation and Memory Access in 60x-Compatible Mode ........................ 11-104

External Master Access (GPCM)...................................................................................... 11-105

External Master Configuration with SDRAM Device ...................................................... 11-106

L2 Cache in Copy-Back Mode.............................................................................................. 12-2

External L2 Cache in Write-Through Mode ......................................................................... 12-4

External L2 Cache in ECC/Parity Mode............................................................................... 12-6

Read Access with L2 Cache.................................................................................................. 12-8

Test Logic Block Diagram .................................................................................................... 13-2

TAP Controller State Machine .............................................................................................. 13-3

Output Pin Cell (O.Pin)......................................................................................................... 13-4 Observe-Only Input Pin Cell (I.Obs) .................................................................................... 13-4

Output Control Cell (IO.CTL) .............................................................................................. 13-5 General Arrangement of Bidirectional Pin Cells .................................................................. 13-5

CPM Block Diagram............................................................................................................. 14-3

Communications Processor (CP) Block Diagram................................................................. 14-6

RISC Controller Configuration Register (RCCR.................................................................. 14-9

RISC Time-Stamp Control Register (RTSCR) ................................................................... 14-11

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

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Figures

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RISC Time-Stamp Register (RTSR) ................................................................................... 14-11

CP Command Register (CPCR).......................................................................................... 14-12

Internal RAM Block Diagram............................................................................................. 14-18

Internal Data RAM Memory Map ...................................................................................... 14-19

Instruction RAM Partitioning ............................................................................................. 14-20

RISC Timer Table RAM Usage .......................................................................................... 14-24

RISC Timer Command Register (TM_CMD) .................................................................... 14-25

RISC Timer Event Register (RTER)/Mask Register (RTMR)............................................ 14-26

SI Block Diagram.................................................................................................................. 15-2

Various Configurations of a Single TDM Channel ............................................................... 15-5

Dual TDM Channel Example ............................................................................................... 15-6

Enabling Connections to the TSA......................................................................................... 15-8

One TDM Channel with Static Frames and Independent Rx and Tx Routes ....................... 15-9

One TDM Channel with Shadow RAM for Dynamic Route Change................................. 15-10 SIx RAM Entry Fields ........................................................................................................ 15-10

Using the SWTR Feature .................................................................................................... 15-12

Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size .................... 15-16

SI Global Mode Registers (SIxGMR)................................................................................. 15-17

SI Mode Registers (SIxMR) ............................................................................................... 15-18

One-Clock Delay from Sync to Data (xFSD = 01)............................................................. 15-20 No Delay from Sync to Data (xFSD = 00).......................................................................... 15-20

Falling Edge (FE) Effect When CE = 1 and xFSD = 01..................................................... 15-21 Falling Edge (FE) Effect When CE = 0 and xFSD = 01..................................................... 15-21

Falling Edge (FE) Effect When CE = 1 and xFSD = 00..................................................... 15-22

Falling Edge (FE) Effect When CE = 0 and xFSD = 00..................................................... 15-23

SIx RAM Shadow Address Registers (SIxRSR) ................................................................ 15-24 SI Command Register (SIxCMDR) .................................................................................... 15-24

SI Status Registers (SIxSTR) .............................................................................................. 15-25

Dual IDL Bus Application Example ................................................................................... 15-26

IDL Terminal Adaptor......................................................................................................... 15-27

IDL Bus Signals .................................................................................................................. 15-28

GCI Bus Signals .................................................................................................................. 15-31

CPM Multiplexing Logic (CMX) Block Diagram................................................................ 16-2

Enabling Connections to the TSA......................................................................................... 16-4

Bank of Clocks ...................................................................................................................... 16-5

CMX UTOPIA Address Register (CMXUAR) .................................................................... 16-7

Connection of the Master Address........................................................................................ 16-9 Connection of the Slave Address .......................................................................................... 16-9

Multi-PHY Receive Address Multiplexing......................................................................... 16-11

CMX SI1 Clock Route Register (CMXSI1CR) .................................................................. 16-12

CMX SI2 Clock Route Register (CMXSI2CR) .................................................................. 16-13

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CMX FCC Clock Route Register (CMXFCR) ................................................................... 16-14

CMX SCC Clock Route Register (CMXSCR) ................................................................... 16-16

CMX SMC Clock Route Register (CMXSMR) ................................................................. 16-19

Baud-Rate Generator (BRG) Block Diagram ....................................................................... 17-1

Baud-Rate Generator Configuration Registers (BRGCx)..................................................... 17-2

Timer Block Diagram ........................................................................................................... 18-1

Timer Cascaded Mode Block Diagram................................................................................. 18-3

Timer Global Configuration Register 1 (TGCR1) ................................................................ 18-4

Timer Global Configuration Register 2 (TGCR2) ................................................................ 18-5

Timer Mode Registers (TMR1–TMR4)................................................................................ 18-6

Timer Reference Registers (TRR1–TRR4)........................................................................... 18-7 Timer Capture Registers (TCR1–TCR4) .............................................................................. 18-7 Timer Counter Registers (TCN1–TCN4).............................................................................. 18-7

Timer Event Registers (TER1–TER4) .................................................................................. 18-8

SDMA Data Paths ................................................................................................................. 19-1

SDMA Bus Arbitration (Transaction Steal).......................................................................... 19-3 SDMA Status Register (SDSR) ............................................................................................ 19-3

SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM) ........................................... 19-4

IDMA Transfer Buffer in the Dual-Port RAM ..................................................................... 19-7

Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer (Size = 128 Bytes) ............................................................................................................ 19-8

IDMAx Channel BD Table.................................................................................................. 19-15

DCM Parameters................................................................................................................. 19-18

IDMA Event/Mask Registers (IDSR/IDMR) ..................................................................... 19-23 IDMA BD Structure ............................................................................................................ 19-23

SCC Block Diagram.............................................................................................................. 20-2

GSMR_H—General SCC Mode Register (High Order)....................................................... 20-3

GSMR_L—General SCC Mode Register (Low Order)........................................................ 20-5

Data Synchronization Register (DSR) .................................................................................. 20-9

Transmit-on-Demand Register (TODR) ............................................................................. 20-10

SCC Buffer Descriptors (BDs)............................................................................................ 20-11

SCC BD and Buffer Memory Structure .............................................................................. 20-12

Function Code Registers (RFCR and TFCR) ..................................................................... 20-15

Output Delay from RTS Asserted for Synchronous Protocols ........................................... 20-18 Output Delay from CTS Asserted for Synchronous Protocols ........................................... 20-18

CTS Lost in Synchronous Protocols ................................................................................... 20-19

Using CD to Control Synchronous Protocol Reception...................................................... 20-20

DPLL Receiver Block Diagram .......................................................................................... 20-21

DPLL Transmitter Block Diagram...................................................................................... 20-22

DPLL Encoding Examples.................................................................................................. 20-23

UART Character Format ....................................................................................................... 21-1

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lvii

Figures

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Two UART Multidrop Configurations.................................................................................. 21-7

Control Character Table ........................................................................................................ 21-8

Transmit Out-of-Sequence Register (TOSEQ) ................................................................... 21-10

Asynchronous UART Transmitter ...................................................................................... 21-11

Protocol-Specific Mode Register for UART (PSMR) ........................................................ 21-13

SCC UART Receiving using RxBDs.................................................................................. 21-16

SCC UART Receive Buffer Descriptor (RxBD) ................................................................ 21-17

SCC UART Transmit Buffer Descriptor (TxBD) ............................................................... 21-18

SCC UART Interrupt Event Example ................................................................................. 21-20 SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................................... 21-20

SCC Status Register for UART Mode (SCCS) ................................................................... 21-21

HDLC Framing Structure...................................................................................................... 22-2

HDLC Address Recognition ................................................................................................. 22-4

HDLC Mode Register (PSMR)............................................................................................. 22-7

SCC HDLC Receive Buffer Descriptor (RxBD) .................................................................. 22-8

SCC HDLC Receiving Using RxBDs................................................................................. 22-11

SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 22-12

HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................................ 22-13

SCC HDLC Interrupt Event Example................................................................................. 22-15 CC HDLC Status Register (SCCS) ..................................................................................... 22-15

Typical HDLC Bus Multi-Master Configuration................................................................ 22-19

Typical HDLC Bus Single-Master Configuration............................................................... 22-20

Detecting an HDLC Bus Collision...................................................................................... 22-21 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ................................... 22-21

HDLC Bus Transmission Line Configuration .................................................................... 22-22 Delayed RTS Mode ............................................................................................................. 22-22

HDLC Bus TDM Transmission Line Configuration .......................................................... 22-23

Classes of BISYNC Frames .................................................................................................. 23-1

Control Character Table and RCCM..................................................................................... 23-6

BISYNC SYNC (BSYNC) ................................................................................................... 23-7

BISYNC DLE (BDLE) ......................................................................................................... 23-8

Protocol-Specific Mode Register for BISYNC (PSMR) .................................................... 23-10

SCC BISYNC RxBD .......................................................................................................... 23-12

SCC BISYNC Transmit BD (TxBD) .................................................................................. 23-14

BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ................................. 23-16 SCC Status Registers (SCCS) ............................................................................................. 23-16

Sending Transparent Frames between MPC8280s ............................................................... 24-4

SCC Transparent Receive Buffer Descriptor (RxBD) .......................................................... 24-8

SCC Transparent Transmit Buffer Descriptor (TxBD) ....................................................... 24-10

SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................................... 24-11

SCC Status Register in Transparent Mode (SCCS) ............................................................ 24-12

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lviii Freescale Semiconductor

Figures

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Ethernet Frame Structure ...................................................................................................... 25-1

Ethernet Block Diagram........................................................................................................ 25-2

Connecting the MPC8280 to Ethernet .................................................................................. 25-4

Ethernet Address Recognition Flowchart ........................................................................... 25-11

Ethernet Mode Register (PSMR) ........................................................................................ 25-14

SCC Ethernet RxBD ........................................................................................................... 25-16

Ethernet Receiving using RxBDs ....................................................................................... 25-18

SCC Ethernet TxBD............................................................................................................ 25-19

SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ......................................... 25-20

Ethernet Interrupt Events Example ..................................................................................... 25-21

LocalTalk Frame Format....................................................................................................... 26-1

Connecting the MPC8280 to LocalTalk................................................................................ 26-3

USB Interface........................................................................................................................ 27-3

USB Function Block Diagram ............................................................................................. 27-5

USB Controller Operating Modes......................................................................................... 27-6

USB Controller Block Diagram ........................................................................................... 27-8

USB Controller Operating Modes......................................................................................... 27-9

Endpoint Pointer Registers (EPxPTR) ................................................................................ 27-13

Frame Number (FRAME_N) in Function Mode—Updated by USB Controller................ 27-15 Frame Number (FRAME_N) in Host Mode—Updated by Application Software ............. 27-15

USB Function Code Registers (RFCR and TFCR)............................................................. 27-16

USB Mode Register (USMOD) .......................................................................................... 27-17

USB Slave Address Register (USADR) ............................................................................. 27-18 USB Endpoint Registers (USEP1–USEP4) ........................................................................ 27-18

USB Command Register (USCOM) ................................................................................... 27-20 USB Event Register (USBER)............................................................................................ 27-20

USB Status Register (USBS) .............................................................................................. 27-21

USB Start of Frame Timer (USSFT)................................................................................... 27-22

USB Memory Structure....................................................................................................... 27-23

USB Receive Buffer Descriptor (Rx BD),.......................................................................... 27-24

USB Transmit Buffer Descriptor (Tx BD),......................................................................... 27-26

USB Transmit Buffer Descriptor (Tx BD),......................................................................... 27-28

USB Transaction Buffer Descriptor (TrBD), ...................................................................... 27-30

SMC Block Diagram............................................................................................................. 28-1

SMC Mode Registers (SMCMR1/SMCMR2)...................................................................... 28-3

SMC Memory Structure........................................................................................................ 28-5

SMC Function Code Registers (RFCR/TFCR)..................................................................... 28-8

SMC UART Frame Format................................................................................................. 28-10

SMC UART RxBD ............................................................................................................. 28-14

RxBD Example ................................................................................................................... 28-16

SMC UART TxBD.............................................................................................................. 28-17

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SMC UART Event Register (SMCE)/Mask Register (SMCM) ......................................... 28-18

SMC UART Interrupts Example......................................................................................... 28-19

Synchronization with SMSYNx.......................................................................................... 28-23

Synchronization with the TSA ............................................................................................ 28-24

SMC Transparent RxBD ..................................................................................................... 28-26

SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ................................. 28-28

SMC Monitor Channel RxBD............................................................................................. 28-32

SMC Monitor Channel TxBD............................................................................................. 28-33 SMC C/I Channel RxBD..................................................................................................... 28-33

SMC C/I Channel TxBD..................................................................................................... 28-34

SMC GCI Event Register (SMCE)/Mask Register (SMCM) ............................................. 28-35

BD Structure for One MCC .................................................................................................. 29-3

TSTATE High Byte ............................................................................................................... 29-7

INTMSK Mask Bits .............................................................................................................. 29-8 Channel Mode Register (CHAMR) ...................................................................................... 29-8

Rx Internal State (RSTATE) High Byte .............................................................................. 29-10

Channel Mode Register (CHAMR)—Transparent Mode ................................................... 29-12

INTMSK Mask Bits ............................................................................................................ 29-15 Channel Mode Register (CHAMR)—CES Mode............................................................... 29-15

Extended Channel Mode Register (ECHAMR).................................................................. 29-21

SS7 Configuration Register (SS7_OPT) ............................................................................. 29-23

Mask1 Format ..................................................................................................................... 29-25 Mask2 Format ..................................................................................................................... 29-25

Super Channel Table Entry ................................................................................................. 29-28

Transmitter Super Channel Example .................................................................................. 29-30

Receiver Super Channel with Slot Synchronization Example............................................ 29-31

Receiver Super Channel without Slot Synchronization Example....................................... 29-32 SI MCC Configuration Register (MCCF)........................................................................... 29-32

Interrupt Circular Table....................................................................................................... 29-35

MCC Event Register (MCCE)/Mask Register (MCCM).................................................... 29-36

Interrupt Circular Table Entry ............................................................................................. 29-37

MCC Receive Buffer Descriptor (RxBD)........................................................................... 29-42

MCC Transmit Buffer Descriptor (TxBD).......................................................................... 29-44

FCC Block Diagram.............................................................................................................. 30-3

General FCC Mode Register (GFMR).................................................................................. 30-4

General FCC Expansion Mode Register (GFEMR) ............................................................. 30-8

FCC Data Synchronization Register (FDSR) ....................................................................... 30-9 FCC Transmit-on-Demand Register (FTODR)..................................................................... 30-9

FCC Memory Structure....................................................................................................... 30-10

Buffer Descriptor Format.................................................................................................... 30-11

Function Code Register (FCRx) ......................................................................................... 30-14

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31-11

31-12

31-13

31-14

31-15 31-16

31-17

31-18

31-19

31-20

31-21

31-22

31-23

31-24

31-25

31-26

31-27 31-28

31-29

31-30

31-31

31-32

31-33

31-34

31-35

31-36

31-37

Title Page Number

Output Delay from RTS Asserted ....................................................................................... 30-18 Output Delay from CTS Asserted ....................................................................................... 30-18

CTS Lost ............................................................................................................................. 30-19

Using CD to Control Reception .......................................................................................... 30-20

APC Scheduling Table Mechanism ...................................................................................... 31-9

VBR Pacing Using the GCRA (Leaky Bucket Algorithm) ................................................ 31-12

External CAM Data Input Fields ........................................................................................ 31-14 External CAM Output Fields .............................................................................................. 31-14

Address Compression Mechanism...................................................................................... 31-15

General VCOFFSET Formula for Contiguous VCLTs ....................................................... 31-16

VP Pointer Address Compression....................................................................................... 31-17

VC Pointer Address Compression ...................................................................................... 31-18

ATM Address Recognition Flowchart ................................................................................ 31-19

MPC8280’s ABR Basic Model ........................................................................................... 31-20

ABR Transmit Flow ............................................................................................................ 31-22

ABR Transmit Flow (continued) ........................................................................................ 31-23

ABR Transmit Flow (continued) ........................................................................................ 31-24

ABR Receive Flow ............................................................................................................. 31-25

Rate Format for RM Cells................................................................................................... 31-26 Rate Formula for RM Cells................................................................................................. 31-26

Performance Monitoring Cell Structure (FMCs and BRCs)............................................... 31-29

FMC, BRC Insertion ........................................................................................................... 31-31

Format of User-Defined Cells ............................................................................................. 31-32

External CAM Address in UDC Extended Address Mode ................................................. 31-33

ATM-to-TDM Interworking................................................................................................ 31-34

VCI Filtering Enable Bits ................................................................................................... 31-39

Global Mode Entry (GMODE) ........................................................................................... 31-40

Example of a 1024-Entry Receive Connection Table ......................................................... 31-42

Receive Connection Table (RCT) Entry ............................................................................. 31-43

AAL5 Protocol-Specific RCT............................................................................................. 31-46

AAL5-ABR Protocol-Specific RCT ................................................................................... 31-47 AAL1 Protocol-Specific RCT............................................................................................. 31-47

AAL0 Protocol-Specific RCT............................................................................................. 31-49

Transmit Connection Table (TCT) Entry ............................................................................ 31-50

AAL5 Protocol-Specific TCT ............................................................................................. 31-53

AAL1 Protocol-Specific TCT ............................................................................................. 31-54

AAL0 Protocol-Specific TCT ............................................................................................. 31-55

Transmit Connection Table Extension (TCTE)—VBR Protocol-Specific ......................... 31-56

UBR+ Protocol-Specific TCTE .......................................................................................... 31-57

ABR Protocol-Specific TCTE ............................................................................................ 31-58

OAM Performance Monitoring Table ................................................................................. 31-60

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxi

Figures

Figure Number

32-1 32-2

32-3

32-4

32-5

32-6

32-7

32-8

32-9

31-38

31-39

31-40

31-41

31-42

31-43 31-44

31-45

31-46

31-47

31-48

31-49

31-50

31-51

31-52

31-53

31-54

31-55

31-56

31-57

31-58

31-59

31-60

31-61

31-62 31-63

31-64

31-65

31-66 31-67

31-68

31-69

Title Page Number

ATM Pace Control Data Structure ...................................................................................... 31-62

The APC Scheduling Table Structure ................................................................................. 31-63

Control Slot ......................................................................................................................... 31-64

Transmit Buffers and BD Table Example ........................................................................... 31-65

Receive Static Buffer Allocation Example ......................................................................... 31-66

Receive Global Buffer Allocation Example ....................................................................... 31-67 Free Buffer Pool Structure .................................................................................................. 31-67

Free Buffer Pool Entry ........................................................................................................ 31-68

AAL5 RxBD ....................................................................................................................... 31-69

AAL1 RxBD ....................................................................................................................... 31-71

AAL0 RxBD ....................................................................................................................... 31-72

User-Defined Cell—RxBD Extension ................................................................................ 31-73

AAL5 TxBD ....................................................................................................................... 31-74

AAL1 TxBD ....................................................................................................................... 31-75

AAL0 TxBDs ...................................................................................................................... 31-76

User-Defined Cell—TxBD Extension ................................................................................ 31-77

AAL1 Sequence Number (SN) Protection Table ................................................................ 31-78

Interrupt Queue Structure.................................................................................................... 31-79

Interrupt Queue Entry ......................................................................................................... 31-80

UTOPIA Master Mode Signals ........................................................................................... 31-81

UTOPIA Slave Mode Signals ............................................................................................. 31-83

FCC ATM Mode Register (FPSMR) .................................................................................. 31-86

ATM Event Register (FCCE)/FCC Mask Register (FCCM) .............................................. 31-88

COMM_INFO Field ........................................................................................................... 31-89

FCC Transmit Internal Rate Register (FTIRR)................................................................... 31-92 FCC Transmit Internal Rate Clocking ................................................................................ 31-92

FCC Transmit Internal Rate Port Enable Register (FIRPERx)........................................... 31-94

FCC Internal Rate Event Register (FIRERx)...................................................................... 31-95

FCC Internal Rate Selection Register HI (FIRSRx_HI) ..................................................... 31-96 FCC Internal Rate Selection Register LO (FIRSRx_LO)................................................... 31-96

AAL1 CES SRTS Generation Using External Logic.......................................................... 31-97

AAL1 CES SRTS Clock Recovery Using External Logic ................................................. 31-98

AAL1 Transmit Cell Format ................................................................................................. 32-3 AAL1 SDT Cell Types.......................................................................................................... 32-3

AAL1 Framing Formats........................................................................................................ 32-4

AAL1 CES Receiver Data flow ............................................................................................ 32-6

ATM-to-TDM Interworking.................................................................................................. 32-7

TDM-to-ATM Interworking.................................................................................................. 32-8

Mapping CAS Data on a Serial Interface............................................................................ 32-10

Internal CAS Block Formats............................................................................................... 32-11

Mapping CAS Entry............................................................................................................ 32-12

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxii Freescale Semiconductor

Figures

Figure Number

32-10 32-11

32-12

32-13

32-14

32-15

32-16

32-17

32-18

32-19

32-20

32-21

32-22

32-23

32-24

32-25

32-26

32-27

32-28

32-29

32-30

32-31

32-32

33-1

33-2

33-3

33-4

33-5

33-6

33-7

33-8

33-9

33-10 33-11

33-12

33-13

33-14

33-15

33-16

33-17

33-18

Title Page Number

AAL1 CES CAS Routing Table (CRT) .............................................................................. 32-12 AAL1 CES CAS Routing Table Entry................................................................................ 32-12

CAS Flow TDM-to-ATM.................................................................................................... 32-13

CAS Flow ATM-to-TDM.................................................................................................... 32-14

Data Structure for ATM-to-TDM Adaptive Slip Control ................................................... 32-16

CES Adaptive Threshold Table........................................................................................... 32-17

Pre-Underrun Sequence ...................................................................................................... 32-18

Pre-Overrun Sequence ........................................................................................................ 32-19

Recoverable Sync Fail Sequence Options .......................................................................... 32-20

3-Step-SN-Algorithm .......................................................................................................... 32-21

Pointer Verification Mechanism.......................................................................................... 32-22

Receive Connection Table (RCT) Entry ............................................................................. 32-26

AAL1 CES Protocol-Specific RCT .................................................................................... 32-29

Transmit Connection Table (TCT) Entry ........................................................................... 32-32

AAL1 CES Protocol-Specific TCT..................................................................................... 32-34

Outgoing CAS Status Register (OCASSR)......................................................................... 32-36

Transmit Buffers and BD Table Example ........................................................................... 32-37

Receive Buffers and BD Table Example ............................................................................ 32-38

AAL1 CES RxBD ............................................................................................................... 32-39

AAL1 CES TxBD ............................................................................................................... 32-40

AAL1 CES Interrupt Queue Entry...................................................................................... 32-41

AAL1 Sequence Number (SN) Protection Table ................................................................ 32-43

TDM-to-ATM Timing Issue................................................................................................ 32-45

AAL2 Data Units .................................................................................................................. 33-1

AAL2 Sublayer Structure...................................................................................................... 33-2

AAL2 Switching Example .................................................................................................... 33-3

Round Robin Priority ............................................................................................................ 33-6

Fixed Priority Mode .............................................................................................................. 33-7

AAL2 Protocol-Specific Transmit Connection Table (TCT)................................................ 33-9

CPS Tx Queue Descriptor (TxQD) ..................................................................................... 33-13

Buffer Structure Example for CPS Packets......................................................................... 33-14

CPS TxBD........................................................................................................................... 33-15

CPS Packet Header Format................................................................................................. 33-16 SSSAR Tx Queue Descriptor.............................................................................................. 33-16

SSSAR TxBD ..................................................................................................................... 33-18

CID Mapping Process ......................................................................................................... 33-21

AAL2 Switching ................................................................................................................. 33-22

AAL2 Protocol-Specific Receive Connection Table (RCT) ............................................... 33-23

CPS Rx Queue Descriptor................................................................................................... 33-26

CPS Receive Buffer Descriptor .......................................................................................... 33-27

CPS Switch Rx Queue Descriptor ...................................................................................... 33-29

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxiii

Figures

34-10

34-11

34-12

34-13

34-14 34-15

34-16

34-17 34-18

34-19

34-20

34-21 34-22

34-23

34-24

34-25

34-26 34-27

34-28 34-29

34-30

34-31

34-32

34-33

35-1

Figure Number

33-19

33-20

33-21

33-22

33-23

33-24

34-1

34-2

34-3

34-4

34-5

34-6 34-7

34-8

34-9

Title Page Number

Switch Receive/Transmit Buffer Descriptor ....................................................................... 33-29

SSSAR Rx Queue Descriptor ............................................................................................. 33-31

SSSAR Receive Buffer Descriptor ..................................................................................... 33-32

UDC Header Table .............................................................................................................. 33-37

AAL2 Interrupt Queue Entry CID

≠ 0 ................................................................................ 33-38

AAL2 Interrupt Queue Entry CID = 0 ................................................................................ 33-39

Basic Concept of IMA .......................................................................................................... 34-5

Illustration of IMA Frames ................................................................................................... 34-6

IMA Microcode Overview.................................................................................................... 34-7

IMA Frame and ICP Cell Formats ........................................................................................ 34-8

IMA Transmit Task Interaction........................................................................................... 34-10

Transmit Queue Normal Operating State............................................................................ 34-12 Transmit Queue Behavior: Link Clock Rate Same as TRL ................................................ 34-12

Transmit Queue Behavior: Link Clock Rate Slower than TRL .......................................... 34-13

Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence ......

34-14

IMA Receive Task Interaction ............................................................................................ 34-15

IMA Microcode: Receive Process ...................................................................................... 34-17

IMA Root Table Data Structures......................................................................................... 34-21

IMA Control (IMACNTL).................................................................................................. 34-25

IMA Group Transmit Control (IGTCNTL)......................................................................... 34-27 IMA Group Transmit State (IGTSTATE)............................................................................ 34-27

Transmit Group Order Table Entry ..................................................................................... 34-28

IMA Group Receive Control (IGRCNTL).......................................................................... 34-34 IMA Group Receive State (IGRSTATE)............................................................................. 34-34

IMA Receive Group Frame Size (IGRSTATE) .................................................................. 34-35

Receive Group Order Table Entry....................................................................................... 34-36

IMA Link Transmit Control (ILTCNTL)............................................................................ 34-38 IMA Link Transmit State (ILTSTATE) ............................................................................... 34-38

IMA Transmit Interrupt Status (ITINTSTAT)..................................................................... 34-39

IMA Link Receive Control (ILRCNTL)............................................................................. 34-41

IMA Link Receive State (ILRSTATE)................................................................................ 34-42

IMA Transmit Queue .......................................................................................................... 34-44 Cell Buffer in Delay Compensation Buffer......................................................................... 34-44

IMA Delay Compensation Buffer ....................................................................................... 34-45 IMA Interrupt Queue Entry................................................................................................. 34-45

IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR) ............................................ 34-50

COMM_INFO Field ........................................................................................................... 34-53

IMA Microcode/Software Interaction................................................................................. 34-54

Near-End versus Far-End .................................................................................................... 34-60

Serial ATM Using FCC2 and TC Blocks (Single Channel).................................................. 35-1

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxiv Freescale Semiconductor

Figures

Figure Number

38-2

39-1

39-2

39-3

39-4

39-5

39-6

39-7

39-8

35-2

35-3

35-4

35-5

35-6

35-7

35-8

35-9

35-10 35-11

35-12

36-1

36-2

36-3

36-4

36-5

36-6

36-7

36-8

36-9

36-10

36-11

37-1

37-2

37-3

37-4

37-5

37-6

37-7

37-8 37-9

38-1

Title Page Number

TC Layer Block Diagram...................................................................................................... 35-3

TC Cell Delineation State Machine ...................................................................................... 35-4

HEC: Receiver Modes of Operation ..................................................................................... 35-5

TC Layer Mode Registers (TCMODEx)............................................................................... 35-7

Cell Delineation State Machine Registers (CDSMRx) ......................................................... 35-8

TC Layer Event Registers (TCERx) ..................................................................................... 35-9

TC Layer General Event Register (TCGER) ...................................................................... 35-10

TC Layer General Status Register (TCGSR) ...................................................................... 35-11

TC Operation in FCC External Rate Mode......................................................................... 35-14 TC Operation in FCC Internal Rate Mode (Sub Rate Mode) ............................................. 35-14

Example of Serial ATM Application .................................................................................. 35-15

Ethernet Frame Structure ...................................................................................................... 36-1

Ethernet Block Diagram ....................................................................................................... 36-2

Connecting the MPC8280 to Ethernet .................................................................................. 36-4

Connecting the MPC8280 to Ethernet (RMII)...................................................................... 36-5

Ethernet Address Recognition Flowchart ........................................................................... 36-16

FCC Ethernet Mode Registers (FPSMRx) .......................................................................... 36-20

Ethernet Event Register (FCCE)/Mask Register (FCCM).................................................. 36-22

Ethernet Interrupt Events Example ..................................................................................... 36-23

Fast Ethernet Receive Buffer (RxBD) ................................................................................ 36-24

Ethernet Receiving Using RxBDs....................................................................................... 36-26

Fast Ethernet Transmit Buffer (TxBD) ............................................................................... 36-27

HDLC Framing Structure...................................................................................................... 37-2

HDLC Address Recognition Example .................................................................................. 37-5

HDLC Mode Register (FPSMR)........................................................................................... 37-8

FCC HDLC Receiving Using RxBDs................................................................................. 37-10

FCC HDLC Receive Buffer Descriptor (RxBD) ................................................................ 37-11

FCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 37-12

HDLC Event Register (FCCE)/Mask Register (FCCM) .................................................... 37-14

HDLC Interrupt Event Example ......................................................................................... 37-16 FCC Status Register (FCCS)............................................................................................... 37-16

In-Line Synchronization Pattern ........................................................................................... 38-2

Sending Transparent Frames between MPC8280s ............................................................... 38-4

SPI Block Diagram ............................................................................................................... 39-1

Single-Master/Multi-Slave Configuration ............................................................................ 39-3

Multi-Master Configuration .................................................................................................. 39-5

SPMODE—SPI Mode Register ............................................................................................ 39-6

SPI Transfer Format with SPMODE[CP] = 0....................................................................... 39-7

SPI Transfer Format with SPMODE[CP] = 1....................................................................... 39-8

SPIE/SPIM—SPI Event/Mask Registers .............................................................................. 39-9

SPCOM—SPI Command Register ..................................................................................... 39-10

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxv

Figures

39-9

39-10

39-11

39-12

40-1

40-2

40-3 40-4

40-5

40-6

40-7 40-8

40-9 40-10

40-11

40-12

40-13

40-14

41-1

41-2 41-3

41-4

41-5

41-6

41-7

Figure Number Title Page Number

RFCR/TFCR—Function Code Registers............................................................................ 39-12

SPI Memory Structure......................................................................................................... 39-13

SPI RxBD............................................................................................................................ 39-14

SPI TxBD ............................................................................................................................ 39-15

I 2

C Controller Block Diagram .............................................................................................. 40-1

I 2

C Master/Slave General Configuration.............................................................................. 40-2

I 2

C Transfer Timing .............................................................................................................. 40-3

I 2

C Master Write Timing ...................................................................................................... 40-3

I 2

C Master Read Timing ....................................................................................................... 40-4

I 2

C Mode Register (I2MOD) ................................................................................................ 40-6

I 2

C Address Register (I2ADD) ............................................................................................. 40-7

I 2

C Baud Rate Generator Register (I2BRG)......................................................................... 40-7

I 2

C Event/Mask Registers (I2CER/I2CMR)......................................................................... 40-8

I 2

C Command Register (I2COM) ......................................................................................... 40-8

I 2

C Function Code Registers (RFCR/TFCR)...................................................................... 40-10

I 2

C Memory Structure......................................................................................................... 40-12

I 2

C RxBD............................................................................................................................ 40-13

I 2

C TxBD ............................................................................................................................ 40-14

Port Open-Drain Registers (PODRA–PODRD) ................................................................... 41-2

Port Data Registers (PDATA–PDATD) ................................................................................ 41-3 Port Data Direction Register (PDIR) .................................................................................... 41-3

Port Pin Assignment Register (PPARA–PPARD)................................................................. 41-4

Special Options Registers (PSORA–POSRD) ...................................................................... 41-5

Port Functional Operation ..................................................................................................... 41-6

Primary and Secondary Option Programming ...................................................................... 41-8

lxvi

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Tables

1-1

1-2

1-3

2-1

2-2

2-3

2-4

2-5

2-6

3-1

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

4-18

4-19

4-20

4-21

4-22

4-23

4-24

4-25

4-26

5-1

5-2

Table Number Title Page Number

Tables

MPC8280 Serial Protocols.................................................................................................... 1-10

Serial Performance ................................................................................................................ 1-11

MPC8270 Serial Performance .............................................................................................. 1-12

HID0 Field Descriptions ....................................................................................................... 2-11

HID1 Field Descriptions ....................................................................................................... 2-14

HID2 Field Descriptions ....................................................................................................... 2-15

Exception Classifications for the Processor Core ................................................................. 2-22

Exceptions and Conditions.................................................................................................... 2-23

Differences Between G2_LE Core and MPC603e................................................................ 2-27

Internal Memory Map ............................................................................................................. 3-2

System Configuration and Protection Functions .................................................................... 4-2

Interrupt Source Priority Levels............................................................................................ 4-10

Encoding the Interrupt Vector ............................................................................................... 4-14

SICR Field Descriptions ....................................................................................................... 4-18

SIPRR Field Descriptions ..................................................................................................... 4-19

SCPRR_H Field Descriptions ............................................................................................... 4-20

SCPRR_L Field Descriptions ............................................................................................... 4-21

SIEXR Field Descriptions..................................................................................................... 4-26

BCR Field Descriptions ........................................................................................................ 4-27

PPC_ACR Field Descriptions ............................................................................................... 4-30

LCL_ACR Field Descriptions .............................................................................................. 4-31

SIUMCR Register Field Descriptions................................................................................... 4-34

IMMR Field Descriptions ..................................................................................................... 4-37

SYPCR Field Descriptions.................................................................................................... 4-38

TESCR1 Field Descriptions.................................................................................................. 4-39

TESCR2 Field Descriptions.................................................................................................. 4-41

L_TESCR1 Field Descriptions ............................................................................................. 4-42

L_TESCR2 Field Descriptions ............................................................................................. 4-43

TMCNTSC Field Descriptions ............................................................................................. 4-44

TMCNTAL Field Descriptions ............................................................................................. 4-45

PISCR Field Descriptions ..................................................................................................... 4-46

PITC Field Descriptions........................................................................................................ 4-47

PITR Field Descriptions........................................................................................................ 4-48

PCIBRx Field Descriptions................................................................................................... 4-49

PCIMSKx Field Descriptions ............................................................................................... 4-50

SIU Pins Multiplexing Control ............................................................................................. 4-51

Reset Causes ........................................................................................................................... 5-1

Reset Actions for Each Reset Source...................................................................................... 5-2

Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxvii

Tables

Table Number

5-3

5-4

5-5 5-6

5-7

6-1

7-1

7-2

8-1

8-2

8-3 8-4

8-5

8-6

8-7

8-8

9-13 9-14

9-15

9-16

9-17

9-18

9-19

9-20 9-21

8-9

8-10 8-11

8-12

9-1

9-2

9-3

9-4 9-5

9-6

9-7

9-8

9-9

9-10

9-11

9-12

Title Page Number

RSR Field Descriptions........................................................................................................... 5-4

RMR Field Descriptions ......................................................................................................... 5-6

RSTCONF Connections in Multiple-MPC8280 Systems....................................................... 5-7 Configuration EPROM Addresses .......................................................................................... 5-7

Hard Reset Configuration Word Field Descriptions ............................................................... 5-8

External Signals ...................................................................................................................... 6-3

Data Bus Lane Assignments ................................................................................................. 7-13

DP[0–7] Signal Assignments ................................................................................................ 7-14

Terminology ............................................................................................................................ 8-1

Transfer Type Encoding ........................................................................................................ 8-10

Transfer Code Encoding for 60x Bus.................................................................................... 8-12 Transfer Size Signal Encoding.............................................................................................. 8-12

Burst Ordering....................................................................................................................... 8-13

Aligned Data Transfers ......................................................................................................... 8-14

Unaligned Data Transfer Example (4-Byte Example) .......................................................... 8-15

Data Bus: Read Cycle Requirements and Write Cycle Content ........................................... 8-17

Address and Size State Calculations ..................................................................................... 8-18

Data Bus Contents for Extended Write Cycles ..................................................................... 8-19 Data Bus Requirements for Extended Read Cycles.............................................................. 8-19

Address and Size State for Extended Transfers .................................................................... 8-20

PCI Terminology..................................................................................................................... 9-6

PCI Command Definitions...................................................................................................... 9-7

Internal Memory Map ........................................................................................................... 9-27

POTARx Field Descriptions ................................................................................................. 9-31 POBARx Field Descriptions ................................................................................................. 9-31

POCMRx Field Descriptions ................................................................................................ 9-32

PTCR Field Descriptions ...................................................................................................... 9-33

GPCR Field Descriptions...................................................................................................... 9-34

PCI_GCR Field Descriptions................................................................................................ 9-35

ESR Field Descriptions ......................................................................................................... 9-36

EMR Field Descriptions........................................................................................................ 9-37

ECR Field Descriptions ........................................................................................................ 9-39

PCI_EACR Field Descriptions ............................................................................................. 9-40 PCI_EDCR Field Description ............................................................................................... 9-40

PCI_ECCR Field Descriptions.............................................................................................. 9-41

PITARx Field Descriptions ................................................................................................... 9-42

PIBARx Field Descriptions .................................................................................................. 9-43

PICMRx Field Descriptions.................................................................................................. 9-44

PCI Bridge PCI Configuration Registers .............................................................................. 9-45

Vendor ID Register Description ............................................................................................ 9-47 Device ID Register Description ............................................................................................ 9-47

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxviii Freescale Semiconductor

Tables

Table Number

9-22

9-23

9-24 9-25

9-26 9-27

9-28 9-29

9-30 9-31

9-32

9-33

9-34 9-35 9-36

9-37

9-54 9-55

9-56

9-57

9-58

9-59 9-60

9-61

9-62

9-38

9-39 9-40

9-41

9-42

9-43

9-44

9-45

9-46

9-47

9-48

9-49

9-50

9-51

9-52

9-53

Title Page Number

PCI Bus Command Register Description.............................................................................. 9-48

PCI Bus Status Register Description..................................................................................... 9-49

Revision ID Register Description ......................................................................................... 9-50 PCI Bus Programming Interface Register Description ......................................................... 9-50

Subclass Code Register Description ..................................................................................... 9-51 PCI Bus Base Class Code Register Description ................................................................... 9-51

PCI Bus Cache Line Size Register Description .................................................................... 9-52 PCI Bus Latency Timer Register Description....................................................................... 9-52

Header Type Register Description ........................................................................................ 9-53 BIST Control Register Description....................................................................................... 9-53

PIMMRBAR Field Descriptions........................................................................................... 9-54

GPLABARx Field Descriptions............................................................................................ 9-55

Subsystem Vendor ID Register Description.......................................................................... 9-56 Subsystem Device ID Description Register.......................................................................... 9-56 PCI Bus Capabilities Pointer Register Description............................................................... 9-56

PCI Bus Interrupt Line Register Description ........................................................................ 9-57 PCI Bus Interrupt Pin Register Description .......................................................................... 9-57

PCI Bus MIN GNT Description............................................................................................ 9-58 PCI Bus MAX LAT Description ........................................................................................... 9-58

PCI Bus Function Register Field Descriptions ..................................................................... 9-59

PCI Bus Arbiter Configuration Register Field Description .................................................. 9-60

Hot Swap Register Block Field Descriptions ....................................................................... 9-61

Hot Swap Control Status Register Field Descriptions .......................................................... 9-62

Bit Settings for Register Initialization Data Structure .......................................................... 9-65

IMRx Field Descriptions....................................................................................................... 9-67

OMRx Field Descriptions ..................................................................................................... 9-68

ODR Field Descriptions........................................................................................................ 9-69

IDR Field Descriptions ......................................................................................................... 9-70

IFHPR Field Descriptions ..................................................................................................... 9-72

IFTPR Field Descriptions ..................................................................................................... 9-73

IPHPR Field Descriptions ..................................................................................................... 9-74

IPTPR Field Descriptions...................................................................................................... 9-75

OFHPR Field Descriptions ................................................................................................... 9-76 OFTPR Field Descriptions.................................................................................................... 9-76

OPHPR Field Descriptions ................................................................................................... 9-77

OPTPR Field Descriptions .................................................................................................... 9-78

IFQPR Field Descriptions ..................................................................................................... 9-79

OFQPR Field Descriptions ................................................................................................... 9-80 OMISR Field Descriptions.................................................................................................... 9-80

OMIMR Field Descriptions .................................................................................................. 9-81

IMISR Field Descriptions ..................................................................................................... 9-82

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxix

Tables

Table Number

9-63

9-64 9-65

9-66

9-67

9-68 9-69

9-70

9-71

9-72 9-73

10-1

10-2

10-3

10-4

11-1

11-2 11-3

11-4

11-5

11-6

11-7

11-8

11-9

11-10

11-11

11-12 11-13

11-14 11-15

11-16 11-17

11-18

11-19

11-20 11-21

11-22 11-23 11-24

11-25 11-26

Title Page Number

IMIMR Field Descriptions.................................................................................................... 9-83

MUCR Field Descriptions .................................................................................................... 9-85 QBAR Field Descriptions ..................................................................................................... 9-85

DMAMRx Field Descriptions............................................................................................... 9-90

DMASRx Field Descriptions ................................................................................................ 9-92

DMACDARx Field Descriptions .......................................................................................... 9-93 DMASARx Field Descriptions ............................................................................................. 9-93

DMADARx Field Descriptions............................................................................................. 9-94

DMABCRx Field Descriptions ............................................................................................. 9-95

DMANDARx Field Descriptions.......................................................................................... 9-96 DMA Segment Descriptor Fields.......................................................................................... 9-96

Dedicated PLL Pins .............................................................................................................. 10-5

SCCR Field Descriptions ...................................................................................................... 10-6

SCMR Field Descriptions ..................................................................................................... 10-7

60x Bus-to-Core Frequency .................................................................................................. 10-8

Number of PSDVAL Assertions Needed for TA Assertion .................................................11-11

BADDR Connections.......................................................................................................... 11-12 60x Bus Memory Controller Registers ............................................................................... 11-12

BRx Field Descriptions ....................................................................................................... 11-13

ORx Field Descriptions (SDRAM Mode) .......................................................................... 11-16

ORx—GPCM Mode Field Descriptions ............................................................................. 11-17

Option Register (ORx)—UPM Mode ................................................................................. 11-19

PSDMR Field Descriptions................................................................................................. 11-21

LSDMR Field Descriptions ................................................................................................ 11-24

Machine x Mode Registers (MxMR) .................................................................................. 11-27

MDR Field Descriptions ..................................................................................................... 11-29

MAR Field Description....................................................................................................... 11-30 60x Bus-Assigned UPM Refresh Timer (PURT)................................................................ 11-30

Local Bus-Assigned UPM Refresh Timer (LURT)............................................................. 11-31 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ........................................................... 11-31

LSRT Field Descriptions..................................................................................................... 11-32 MPTPR Field Descriptions ................................................................................................. 11-32

SDRAM Interface Signals .................................................................................................. 11-33

SDRAM Interface Commands ............................................................................................ 11-35

SDRAM Address Multiplexing (A0–A15) ......................................................................... 11-38 SDRAM Address Multiplexing (A16–A31) ....................................................................... 11-38

60x Address Bus Partition................................................................................................... 11-49 SDRAM Device Address Port during activate Command.................................................. 11-49 SDRAM Device Address Port during read/write Command .............................................. 11-49

Register Settings (Page-Based Interleaving)....................................................................... 11-50 60x Address Bus Partition................................................................................................... 11-50

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxx Freescale Semiconductor

Tables

Table Number

15-1

15-2

15-3

15-4

15-5

15-6

15-7 15-8

15-9

11-27 11-28 11-29

11-30

11-31

11-32

11-33

11-34

11-35

11-36

11-37

11-38

11-39 11-40 11-41

11-42

11-43

11-44

13-1

13-2

14-1

14-2

14-3

14-4

14-5

14-6

14-7

14-8

14-9

14-10

14-11

14-12

Title Page Number

SDRAM Device Address Port During activate Command ................................................. 11-51 SDRAM Device Address Port During read/write Command ............................................. 11-51 Register Settings (Bank-Based Interleaving) ...................................................................... 11-51

GPCM Interfaces Signals.................................................................................................... 11-52

GPCM Strobe Signal Behavior ........................................................................................... 11-53

TRLX and EHTR Combinations......................................................................................... 11-59

Boot Bank Field Values after Reset .................................................................................... 11-62

UPM Interfaces Signals ...................................................................................................... 11-63

UPM Routines Start Addresses ........................................................................................... 11-66

RAM Word Bit Settings ...................................................................................................... 11-72

MxMR Loop Field Usage ................................................................................................... 11-77

UPM Address Multiplexing ................................................................................................ 11-78

60x Address Bus Partition................................................................................................... 11-81 DRAM Device Address Port during an activate command ................................................ 11-81 Register Settings ................................................................................................................. 11-81

UPMs Attributes Example .................................................................................................. 11-83

UPMs Attributes Example .................................................................................................. 11-91

EDO Connection Field Value Example .............................................................................. 11-93

TAP Signals........................................................................................................................... 13-2

Instruction Decoding............................................................................................................. 13-6

Possible MPC8280 Applications .......................................................................................... 14-3

Peripheral Prioritization ........................................................................................................ 14-7

RISC Controller Configuration Register Field Descriptions ................................................ 14-9

RTSCR Field Descriptions.................................................................................................. 14-11

RISC Microcode Revision Number .................................................................................... 14-12

CP Command Register Field Descriptions ......................................................................... 14-13

CP Command Opcodes ....................................................................................................... 14-14

Command Descriptions....................................................................................................... 14-15

Buffer Descriptor Format.................................................................................................... 14-21

Parameter RAM .................................................................................................................. 14-22

RISC Timer Table Parameter RAM .................................................................................... 14-24

TM_CMD Field Descriptions ............................................................................................. 14-25

SIx RAM Entry (MCC = 0) ................................................................................................ 15-11

SIx RAM Entry (MCC = 1) ................................................................................................ 15-13

SIx RAM Entry Descriptions .............................................................................................. 15-14

SIxGMR Field Descriptions................................................................................................ 15-17

SIxMR Field Descriptions .................................................................................................. 15-18

SIxRSR Field Descriptions ................................................................................................. 15-24

SIxCMDR Field Description .............................................................................................. 15-25 SIxSTR Field Descriptions ................................................................................................. 15-25

IDL Signal Descriptions...................................................................................................... 15-27

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxxi

Tables

Table Number

15-10

15-11

15-12

16-1

16-2

16-3

16-4

16-5

16-6

16-7

17-1

17-2

17-3

18-1

18-2

18-3

18-4

19-1

19-2

19-3

19-4

19-5

19-6

19-7 19-8

19-9

19-10

19-11

19-12 19-13

19-14 19-15

19-16

19-17

20-1

20-2

20-3

20-4

20-5 20-6

20-7

Title Page Number

SIx RAM Entries for an IDL Interface ............................................................................... 15-29

GCI Signals ......................................................................................................................... 15-31

SIx RAM Entries for a GCI Interface (SCIT Mode) .......................................................... 15-33

Clock Source Options ........................................................................................................... 16-6

CMXUAR Field Descriptions............................................................................................... 16-7

CMXSI1CR Field Descriptions .......................................................................................... 16-12

CMXSI2CR Field Descriptions .......................................................................................... 16-13

CMXFCR Field Descriptions.............................................................................................. 16-14

CMXSCR Field Descriptions.............................................................................................. 16-16

CMXSMR Field Descriptions............................................................................................. 16-19

BRGCx Field Descriptions ................................................................................................... 17-3

BRG External Clock Source Options.................................................................................... 17-4

Typical Baud Rates for Asynchronous Communication ....................................................... 17-5

TGCR1 Field Descriptions.................................................................................................... 18-4

TGCR2 Field Descriptions.................................................................................................... 18-5

TMR1–TMR4 Field Descriptions ......................................................................................... 18-6

TER Field Descriptions......................................................................................................... 18-8

SDSR Field Descriptions ...................................................................................................... 19-3

PDTEM and LDTEM Field Descriptions ............................................................................. 19-5

IDMA Transfer Parameters ................................................................................................... 19-7

IDMAx Parameter RAM..................................................................................................... 19-16

DCM Field Descriptions ..................................................................................................... 19-18

IDMA Channel Data Transfer Operation............................................................................ 19-20

Valid Memory-to-Memory STS/DTS Values...................................................................... 19-21 Valid STS/DTS Values for Peripherals ............................................................................... 19-21

IDSR/IDMR Field Descriptions.......................................................................................... 19-23

IDMA BD Field Descriptions ............................................................................................. 19-24

IDMA Bus Exceptions ........................................................................................................ 19-27

Parallel I/O Register Programming—Port C ...................................................................... 19-28 Parallel I/O Register Programming—Port A ...................................................................... 19-28

Parallel I/O Register Programming—Port D ...................................................................... 19-29 Example: Peripheral-to-Memory Mode—IDMA2 ............................................................. 19-29

Example: Memory-to-Peripheral Fly-By Mode (on 60x)–IDMA3 .................................... 19-30

Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1.............................. 19-32

GSMR_H Field Descriptions ................................................................................................ 20-3

GSMR_L Field Descriptions ................................................................................................ 20-5

TODR Field Descriptions ................................................................................................... 20-10

SCC Parameter RAM Map for All Protocols...................................................................... 20-13

Parameter RAM—SCC Base Addresses............................................................................. 20-15 RFCRx /TFCRx Field Descriptions.................................................................................... 20-15

SCCx Event, Mask, and Status Registers ........................................................................... 20-16

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxxii Freescale Semiconductor

Tables

Table Number

20-8

20-9

21-1

21-2 21-3

21-4

21-5

21-6

21-7 21-8

21-9

21-10

21-11

21-12

21-13

21-14

22-1

22-2 22-3

22-4 22-5

22-6

22-7

22-8

22-9

22-10

23-1

23-2 23-3

23-4

23-5

23-6 23-7

23-8 23-9

23-10

23-11

23-12

23-13

23-14

23-15

Title Page Number

Preamble Requirements ...................................................................................................... 20-22

DPLL Codings .................................................................................................................... 20-24

UART-Specific SCC Parameter RAM Memory Map ........................................................... 21-4

Transmit Commands ............................................................................................................. 21-6 Receive Commands............................................................................................................... 21-6

Control Character Table, RCCM, and RCCR Descriptions .................................................. 21-8

TOSEQ Field Descriptions ................................................................................................. 21-10

DSR Fields Descriptions ..................................................................................................... 21-11

Transmission Errors ............................................................................................................ 21-12 Reception Errors ................................................................................................................. 21-12

PSMR UART Field Descriptions ........................................................................................ 21-13

SCC UART RxBD Status and Control Field Descriptions ................................................. 21-17

SCC UART TxBD Status and Control Field Descriptions ................................................. 21-18

SCCE/SCCM Field Descriptions for UART Mode ........................................................... 21-21

UART SCCS Field Descriptions ......................................................................................... 21-22

UART Control Characters for S-Records Example ............................................................ 21-24

HDLC-Specific SCC Parameter RAM Memory Map .......................................................... 22-3

Transmit Commands ............................................................................................................. 22-5 Receive Commands .............................................................................................................. 22-5

Transmit Errors ................................................................................................................... 22-6 Receive Errors....................................................................................................................... 22-6

PSMR HDLC Field Descriptions.......................................................................................... 22-7

SCC HDLC RxBD Status and Control Field Descriptions ................................................... 22-9

SCC HDLC TxBD Status and Control Field Descriptions ................................................. 22-12

SCCE/SCCM Field Descriptions ....................................................................................... 22-13

HDLC SCCS Field Descriptions......................................................................................... 22-16

SCC BISYNC Parameter RAM Memory Map ..................................................................... 23-3

Transmit Commands ............................................................................................................. 23-5 Receive Commands............................................................................................................... 23-5

Control Character Table and RCCM Field Descriptions ...................................................... 23-7

BSYNC Field Descriptions ................................................................................................... 23-8

BDLE Field Descriptions...................................................................................................... 23-9 Receiver SYNC Pattern Lengths of the DSR........................................................................ 23-9

Transmit Errors ................................................................................................................... 23-10 Receive Errors..................................................................................................................... 23-10

PSMR Field Descriptions.................................................................................................... 23-11

SCC BISYNC RxBD Status and Control Field Descriptions ............................................. 23-12

SCC BISYNC TxBD Status and Control Field Descriptions ............................................. 23-14

SCCE/SCCM Field Descriptions ........................................................................................ 23-16

SCCS Field Descriptions .................................................................................................... 23-17

Control Characters .............................................................................................................. 23-18

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxxiii

Tables

Table Number

24-1

24-2 24-3

24-4 24-5

24-6

24-7

24-8

24-9

24-10

25-1

25-2 25-3

25-4

25-5

25-6

25-7

25-8

25-9

27-1

27-2

27-3

27-4

27-5

27-6

27-7 27-8

27-9

27-10 27-11

27-12

27-13

27-14 27-15

27-16

27-17

27-18

27-19

27-20 27-21

28-1

Title Page Number

Receiver SYNC Pattern Lengths of the DSR........................................................................ 24-3

SCC Transparent Parameter RAM Memory Map................................................................. 24-6 Transmit Commands ............................................................................................................. 24-6

Receive Commands............................................................................................................... 24-7 Transmit Errors ..................................................................................................................... 24-7

Receive Errors....................................................................................................................... 24-8

SCC Transparent RxBD Status and Control Field Descriptions ........................................... 24-9

SCC Transparent TxBD Status and Control Field Descriptions ......................................... 24-10

SCCE/SCCM Field Descriptions ....................................................................................... 24-11

SCCS Field Descriptions .................................................................................................... 24-12

SCC Ethernet Parameter RAM Memory Map ...................................................................... 25-7

Transmit Commands ........................................................................................................... 25-10 Receive Commands............................................................................................................. 25-10

Transmission Errors ............................................................................................................ 25-13

Reception Errors ................................................................................................................. 25-14

PSMR Field Descriptions.................................................................................................... 25-15

SCC Ethernet RxBD Status and Control Field Descriptions .............................................. 25-16

SCC Ethernet TxBD Status and Control Field Descriptions .............................................. 25-19

SCCE/SCCM Field Descriptions ........................................................................................ 25-20

USB Pins Functions .............................................................................................................. 27-3

USB Tokens .......................................................................................................................... 27-6

USB Tokens ........................................................................................................................ 27-10

USB Parameter RAM Memory Map .................................................................................. 27-12

Endpoint Parameter Block .................................................................................................. 27-13

FRAME_N Field Descriptions............................................................................................ 27-15

FRAME_N Field Descriptions............................................................................................ 27-16 RFCR and TFCR Fields ...................................................................................................... 27-16

USMOD Fields ................................................................................................................... 27-17

USADR Fields .................................................................................................................... 27-18 USEPx Field Descriptions .................................................................................................. 27-18

USCOM Fields.................................................................................................................... 27-20

USBER Fields ..................................................................................................................... 27-21

USBS Fields ........................................................................................................................ 27-22 USSFT Fields ...................................................................................................................... 27-22

USB Rx BD Fields .............................................................................................................. 27-24

USB Function Tx BD Fields ............................................................................................... 27-26

USB Host Tx BD Fields...................................................................................................... 27-28

USB Host TrBD Fields ....................................................................................................... 27-30

USB Controller Transmission Errors .................................................................................. 27-33 USB Controller Reception Errors ....................................................................................... 27-33

SMCMR1/SMCMR2 Field Descriptions.............................................................................. 28-3

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxxiv Freescale Semiconductor

Tables

Table Number

28-2

28-3

28-4 28-5

28-6

28-7

28-8

28-9

28-10 28-11 28-12

28-13

28-14 28-15

28-16

28-17

28-18 28-19

28-20

28-21 28-22

28-23

29-1

29-2

29-3

29-4

29-5

29-6

29-7

29-8

29-9

29-10

29-11

29-12 29-13

29-14

29-15

29-16

29-17

29-18

29-19

Title Page Number

SMC UART and Transparent Parameter RAM Memory Map ............................................. 28-6

RFCR/TFCR Field Descriptions ........................................................................................... 28-8

Transmit Commands ........................................................................................................... 28-12 Receive Commands............................................................................................................. 28-12

SMC UART Errors.............................................................................................................. 28-13

SMC UART RxBD Field Descriptions ............................................................................... 28-14

SMC UART TxBD Field Descriptions ............................................................................... 28-17

SMCE/SMCM Field Descriptions ...................................................................................... 28-18

SMC Transparent Transmit Commands.............................................................................. 28-25 SMC Transparent Receive Commands ............................................................................... 28-25 SMC Transparent Error Conditions .................................................................................... 28-25

SMC Transparent RxBD Field Descriptions....................................................................... 28-26

SMC Transparent TxBD ..................................................................................................... 28-27 SMC Transparent TxBD Field Descriptions ....................................................................... 28-27

SMCE/SMCM Field Descriptions ...................................................................................... 28-28

SMC GCI Parameter RAM Memory Map .......................................................................... 28-30

SMC GCI Commands ......................................................................................................... 28-32 SMC Monitor Channel RxBD Field Descriptions .............................................................. 28-32

SMC Monitor Channel TxBD Field Descriptions .............................................................. 28-33

SMC C/I Channel RxBD Field Descriptions ...................................................................... 28-34 SMC C/I Channel TxBD Field Descriptions ...................................................................... 28-34

SMCE/SMCM Field Descriptions ...................................................................................... 28-35

Global MCC Parameters ....................................................................................................... 29-4

Channel-Specific Parameters for HDLC............................................................................... 29-6

TSTATE High-Byte Field Descriptions ................................................................................ 29-7

CHAMR Field Descriptions.................................................................................................. 29-9

RSTATE High-Byte Field Descriptions .............................................................................. 29-10

Channel-Specific Parameters for Transparent Operation.................................................... 29-11

CHAMR Field Descriptions—Transparent Mode .............................................................. 29-13

CES-Specific Global MCC Parameters .............................................................................. 29-14

CHAMR Field Descriptions—CES Mode .......................................................................... 29-15

Channel-Specific Parameters for SS7 ................................................................................. 29-18

ECHAMR Fields Description ............................................................................................. 29-21

Parameter Values for SUERM in Japanese SS7.................................................................. 29-23 SS7 Configuration Register Fields Description .................................................................. 29-23

Channel Extra Parameters ................................................................................................... 29-27

MCCF Field Descriptions ................................................................................................... 29-32

Group Channel Assignments .............................................................................................. 29-33

MCC Commands................................................................................................................. 29-34

MCCE/MCCM Register Field Descriptions ....................................................................... 29-36

Interrupt Circular Table Entry Field Descriptions .............................................................. 29-37

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxxv

Tables

Table Number

29-20

29-21

29-22

30-1

30-2

30-3

30-4

30-5

30-6

31-1

31-2

31-3 31-4

31-5 31-6

31-7

31-8

31-9

31-10

31-11

31-12 31-13

31-14

31-15

31-16

31-17

31-18

31-19

31-20

31-21

31-22

31-23

31-24

31-25

31-26

31-27

31-28

31-29

31-30

31-31

31-32

Title Page Number

GUN Error Recovery .......................................................................................................... 29-41

RxBD Field Descriptions .................................................................................................... 29-42

TxBD Field Descriptions .................................................................................................... 29-44

Internal Clocks to CPM Clock Frequency Ratio .................................................................. 30-3

GFMR Register Field Descriptions....................................................................................... 30-4

GFEMRx Field Descriptions ................................................................................................ 30-8

FTODR Field Descriptions ................................................................................................. 30-10

FCC Parameter RAM Common to All Protocols Except ATM .......................................... 30-12

FCRx Field Descriptions..................................................................................................... 30-14

ATM Service Types............................................................................................................... 31-9

External CAM Input and Output Field Descriptions .......................................................... 31-14

Field Descriptions for Address Compression ..................................................................... 31-16 VCOFFSET Calculation Examples for Contiguous VCLTs ............................................... 31-16

VP-Level Table Entry Address Calculation Example......................................................... 31-17 VC-Level Table Entry Address Calculation Example ........................................................ 31-17

Fields and their Positions in RM Cells................................................................................ 31-26

Pre-Assigned Header Values at the UNI ............................................................................. 31-27

Pre-Assigned Header Values at the NNI ............................................................................. 31-28

Performance Monitoring Cell Fields................................................................................... 31-30

ATM Parameter RAM Map................................................................................................. 31-36

UEAD_OFFSETs for Extended Addresses in the UDC Extra Header ............................... 31-39 VCI Filtering Enable Field Descriptions ............................................................................ 31-39

GMODE Field Descriptions................................................................................................ 31-40

Receive and Transmit Connection Table Sizes ................................................................... 31-41

RCT Field Descriptions ...................................................................................................... 31-44

RCT Settings (AAL5 Protocol-Specific) ............................................................................ 31-46

ABR Protocol-Specific RCT Field Descriptions ................................................................ 31-47

AAL1 Protocol-Specific RCT Field Descriptions .............................................................. 31-48

AAL0-Specific RCT Field Descriptions ............................................................................. 31-49

TCT Field Descriptions....................................................................................................... 31-51

AAL5-Specific TCT Field Descriptions ............................................................................. 31-53

AAL1 Protocol-Specific TCT Field Descriptions .............................................................. 31-54

AAL0-Specific TCT Field Descriptions ............................................................................. 31-55

VBR-Specific TCTE Field Descriptions............................................................................. 31-56

UBR+ Protocol-Specific TCTE Field Descriptions............................................................ 31-57

ABR-Specific TCTE Field Descriptions............................................................................. 31-58

OAM—Performance Monitoring Table Field Descriptions ............................................... 31-61

APC Parameter Table .......................................................................................................... 31-62

APC Priority Table Entry .................................................................................................... 31-63

Control Slot Field Description ............................................................................................ 31-64

Free Buffer Pool Entry Field Descriptions.......................................................................... 31-68

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxxvi Freescale Semiconductor

Tables

Table Number

31-33

31-34

31-35

31-36

31-37

31-38

31-39

31-40

31-41

31-42

31-43

31-44

31-45

31-46

31-47

31-48

31-49

31-50

31-51

31-52

31-53

31-54

32-1

32-2

32-3

32-4

32-5

32-6

32-7

32-8

32-9

32-10

32-11

32-12

32-13

32-14

32-15

33-1

33-2

33-3

33-4

Title Page Number

Free Buffer Pool Parameter Table ....................................................................................... 31-68

Receive and Transmit Buffers............................................................................................. 31-69

AAL5 RxBD Field Descriptions......................................................................................... 31-70

AAL1 RxBD Field Descriptions......................................................................................... 31-71

AAL0 RxBD Field Descriptions......................................................................................... 31-72

AAL5 TxBD Field Descriptions ......................................................................................... 31-74

AAL1 TxBD Field Descriptions ......................................................................................... 31-75

AAL0 TxBD Field Descriptions ......................................................................................... 31-76

UNI Statistics Table ............................................................................................................ 31-78

Interrupt Queue Entry Field Description ............................................................................ 31-80

Interrupt Queue Parameter Table ........................................................................................ 31-81

UTOPIA Master Mode Signal Descriptions ....................................................................... 31-82

UTOPIA Slave Mode Signals ............................................................................................. 31-83

UTOPIA Loop-Back Modes ............................................................................................... 31-85

FCC ATM Mode Register (FPSMR) .................................................................................. 31-86

FCCE/FCCM Field Descriptions ........................................................................................ 31-89

COMM_INFO Field Descriptions ...................................................................................... 31-90

FTIRRx Field Descriptions ................................................................................................. 31-92

FIRPERx Field Descriptions (TIREM=1) .......................................................................... 31-94

FIRERx Field Descriptions (TIREM=1)............................................................................. 31-95

IRSRx_HI Field Descriptions (TIREM=1)......................................................................... 31-96

FIRSRx_LO Field Descriptions (TIREM=1) ..................................................................... 31-97

CAS Routing Table Entry Field Descriptions ..................................................................... 32-13

CES Adaptive Threshold Table Field Descriptions ............................................................ 32-17

AAL1 CES Field Descriptions............................................................................................ 32-22

AAL1 CES Parameters ....................................................................................................... 32-25

RCT Field Descriptions ...................................................................................................... 32-27

AAL1 CES Protocol-Specific RCT Field Descriptions ...................................................... 32-29

TCT Field Descriptions....................................................................................................... 32-32

AAL1 CES Protocol-Specific TCT Field Descriptions ...................................................... 32-35

OCASSR Field Descriptions............................................................................................... 32-36

Receive and Transmit Buffers............................................................................................. 32-38

AAL1 CES RxBD Field Descriptions ................................................................................ 32-39

AAL1 CES TxBD Field Descriptions................................................................................. 32-40

AAL1 CES Interrupt Queue Entry Field Descriptions ....................................................... 32-41

AAL1 CES DPR Statistics Table ........................................................................................ 32-43

AAL1 CES External Statistics Table .................................................................................. 32-44

AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions ................. 33-9

CPS TxQD Field Descriptions ............................................................................................ 33-13

CPS TxBD Field Descriptions ............................................................................................ 33-15

SSSAR TxQD Field Descriptions....................................................................................... 33-17

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor lxxvii

Tables

Table Number

33-5

33-6

33-7

33-8

33-9

33-10

33-11

33-12

33-13

33-14

33-15

34-1

34-2

34-3

34-4 34-5

34-6

34-7 34-8

34-9

34-10

34-11

34-12 34-13

34-14 34-15

34-16 34-17

34-18

34-19

34-20

34-21

34-22

34-23

34-24

34-25 34-26

34-27

34-28

34-29

35-1

Title Page Number

SSSAR TxBD Field Descriptions ....................................................................................... 33-18

AAL2 Protocol-Specific RCT Field Descriptions .............................................................. 33-23

CPS RxQD Field Descriptions............................................................................................ 33-27

CPS RxBD Field Descriptions ............................................................................................ 33-28

CPS Switch RxQD Field Descriptions................................................................................ 33-29

Switch RxBD Field Descriptions ........................................................................................ 33-30

SSSAR RxQD Field Descriptions....................................................................................... 33-31

SSSAR RxBD Field Descriptions....................................................................................... 33-33

AAL2 Parameter RAM ....................................................................................................... 33-34

AAL2 Interrupt Queue Entry CID

≠ 0 Field Descriptions.................................................. 33-38

AAL2 Interrupt Queue Entry CID = 0 Field Descriptions.................................................. 33-39

IMA Sublayer in Layer Reference Model............................................................................. 34-2

FCC Parameter RAM Additions ......................................................................................... 34-22

IMA Root Table .................................................................................................................. 34-23

IMACNTL Field Descriptions ............................................................................................ 34-25 IMA Group Transmit Table Entry ...................................................................................... 34-25

IGTCNTL Field Descriptions ............................................................................................. 34-27

IGTSTATE Field Descriptions ............................................................................................ 34-28 Transmit Group Order Table Entry Field Descriptions....................................................... 34-28

ICP Cell Template .............................................................................................................. 34-29

IMA Group Receive Table Entry ....................................................................................... 34-31

IGRCNTL Field Descriptions ............................................................................................. 34-34

IGRSTATE Field Descriptions............................................................................................ 34-35 IRGFS Field Descriptions ................................................................................................... 34-35

Receive Group Order Table Entry Field Descriptions ........................................................ 34-36 IMA Link Transmit Table Entry ........................................................................................ 34-36

ILTCNTL Field Descriptions .............................................................................................. 34-38 ILTSTATE Field Descriptions............................................................................................. 34-38

ITINTSTAT Field Descriptions........................................................................................... 34-39

IMA Link Receive Table Entry........................................................................................... 34-40

ILRCNTL Field Descriptions ............................................................................................. 34-41

ILRSTATE Field Descriptions ............................................................................................ 34-42

IMA Link Receive Statistics Table Entry ........................................................................... 34-43

IMA Interrupt Queue Entry Field Descriptions .................................................................. 34-46

Unavailable Features when DREQx used as IDCR Master Clock ..................................... 34-48

IDCR IMA Root Parameters............................................................................................... 34-49 IDCR Table Entry ............................................................................................................... 34-49

IDSR/IDMR Field Descriptions.......................................................................................... 34-50

Examples of APC Programming for IMA .......................................................................... 34-51

COMM_INFO Field Descriptions ...................................................................................... 34-53

TC Layer Signals .................................................................................................................. 35-6

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Tables

Table Number

39-1

39-2

39-3

39-4

39-5

39-6 39-7

39-8

39-9

35-2

35-3 35-4

35-5

35-6

35-7 35-8 35-9

35-10 35-11 35-12

36-1

36-2

36-3 36-4

36-5

36-6 36-7

36-8

36-9

36-10

36-11

37-1

37-2

37-3 37-4

37-5

37-6

37-7

37-8

37-9

37-10

Title Page Number

TCMODEx Field Descriptions.............................................................................................. 35-7

CDSMRx Field Descriptions ................................................................................................ 35-9 TCERx Field Descriptions .................................................................................................... 35-9

TCGER Field Descriptions ................................................................................................. 35-10

TCGSR Field Descriptions ................................................................................................. 35-11

Programming GFMR and FPSMR to Setup the FCC2 ....................................................... 35-16 Enable FCC2 ....................................................................................................................... 35-16 Programming the CPM MUX for a TI Application ............................................................ 35-16

Programming the TC Layer Block...................................................................................... 35-17 Programming the SI RAM (Rx or Tx) for a T1 Application .............................................. 35-17 Programming SI Registers to Enable TDM ........................................................................ 35-17

Flow Control Frame Structure .............................................................................................. 36-7

Ethernet-Specific Parameter RAM ....................................................................................... 36-9

Transmit Commands ........................................................................................................... 36-13 Receive Commands............................................................................................................. 36-13

RMON Statistics and Counters ........................................................................................... 36-14

Transmission Errors ............................................................................................................ 36-19 Reception Errors ................................................................................................................. 36-19

FPSMR Ethernet Field Descriptions................................................................................... 36-20

FCCE/FCCM Field Descriptions ........................................................................................ 36-22

RxBD Field Descriptions .................................................................................................... 36-24

Ethernet TxBD Field Definitions ........................................................................................ 36-27

FCC HDLC-Specific Parameter RAM Memory Map .......................................................... 37-3

Transmit Commands ............................................................................................................. 37-5

Receive Commands............................................................................................................... 37-6 HDLC Transmission Errors .................................................................................................. 37-6

HDLC Reception Errors ....................................................................................................... 37-7

FPSMR Field Descriptions .................................................................................................. 37-8

RxBD field Descriptions ..................................................................................................... 37-11

HDLC TxBD Field Descriptions ....................................................................................... 37-13

FCCE/FCCM Field Descriptions ........................................................................................ 37-15

FCCS Register Field Descriptions ...................................................................................... 37-17

SPMODE Field Descriptions ................................................................................................ 39-6

Example Conventions ........................................................................................................... 39-8

SPIE/SPIM Field Descriptions.............................................................................................. 39-9

SPCOM Field Descriptions................................................................................................. 39-10

SPI Parameter RAM Memory Map .................................................................................... 39-11

RFCR/TFCR Field Descriptions ......................................................................................... 39-12 SPI Commands.................................................................................................................... 39-12

SPI RxBD Status and Control Field Descriptions............................................................... 39-14

SPI TxBD Status and Control Field Descriptions............................................................... 39-15

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Tables

Table Number

40-1

40-2 40-3

40-4

40-5 40-6

40-7 40-8

40-9

40-10

41-1

41-2

41-3

41-4

41-5

41-6

41-7

41-8

Title Page Number

II2MOD Field Descriptions .................................................................................................. 40-6

I2ADD Field Descriptions .................................................................................................... 40-7 I2BRG Field Descriptions..................................................................................................... 40-7

I2CER/I2CMR Field Descriptions........................................................................................ 40-8

I2COM Field Descriptions.................................................................................................... 40-9 I 2

C Parameter RAM Memory Map....................................................................................... 40-9

RFCR/TFCR Field Descriptions ......................................................................................... 40-11 I 2

C Transmit/Receive Commands....................................................................................... 40-11

I 2

C RxBD Status and Control Bits...................................................................................... 40-13

I 2

C TxBD Status and Control Bits ...................................................................................... 40-14

PODRx Field Descriptions ................................................................................................... 41-2

PDIR Field Descriptions ....................................................................................................... 41-3

PPAR Field Descriptions....................................................................................................... 41-4

PSORx Field Descriptions .................................................................................................... 41-5

Port A—Dedicated Pin Assignment (PPARA = 1) ............................................................... 41-8

Port B Dedicated Pin Assignment (PPARB = 1) ................................................................ 41-12

Port C Dedicated Pin Assignment (PPARC = 1) ................................................................ 41-15

Port D Dedicated Pin Assignment (PPARD = 1) .............................................................. 41-17

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About This Book

The MPC8280 is a versatile communications processor that integrates on one chip a high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The primary objective of this manual is to help communications system designers build systems using any member of the MPC8280 PowerQUICC II™ family of communications processors and to help software designers provide operating systems and user-level applications to take complete advantage of the MPC8280.

NOTE: Devices Supported by This Manual

This manual supports the MPC8280, the MPC8275, and the MPC8270, which are collectively called either the MPC8280 or the PowerQUICC II throughout this manual. Device numbers are cited only if information does not pertain to all devices.

Although this book describes aspects of the PowerPC architecture that are critical for understanding the MPC8280 core, it does not contain a complete description of the architecture. Where additional information might help the reader, references are made to Programming Environments Manual for 32-Bit

Implementation of the PowerPC Architecture, Rev. 2. Refer to “Architecture Documentation” for ordering

information.

The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to use the most recent version of the documentation. For more information, contact your sales representative.

Before Using this Manual—Important Note

Before using this manual, determine whether it is the latest revision and if there are errata or addenda. To locate any published errata or updates for this document, refer to the worldwide web at www.freescale.com.

Audience

This manual is intended for software and hardware developers and application programmers who want to develop products for the MPC8280. It is assumed that the reader has a basic understanding of computer networking, OSI layers, RISC architecture, and communications protocols described herein. Where useful, additional sources provide in-depth discussions of such topics.

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Organization

Following is a summary and a brief description of the chapters of this manual: • • • •

Part I, “Overview,”

operation and listing basic features. — provides a high-level description of the MPC8280, describing general

Chapter 1, “Overview,”

provides a high-level description of MPC8280 functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.

Chapter 2, “G2_LE Core,”

provides an overview of the MPC8280 core, summarizing topics described in further detail in subsequent chapters.

Chapter 3, “Memory Map,”

presents a table showing where MPC8280 registers are mapped in memory. It includes cross references that indicate where the registers are described in detail.

Part II, “Configuration and Reset,”

describes start-up behavior of the MPC8280.

Chapter 4, “System Interface Unit (SIU),”

describes the system configuration and protection functions that provide various monitors and timers, and the 60x bus configuration.

Chapter 5, “Reset,”

describes the behavior of the MPC8280 at reset and start-up.

Part III, “The Hardware Interface,”

describes external signals, clocking, memory control, and power management of the MPC8280.

Chapter 6, “External Signals,”

shows a functional pinout of the MPC8280 and describes the MPC8280 signals. —

Chapter 7, “60x Signals,”

describes signals on the 60x bus. —

Chapter 8, “The 60x Bus,”

describes the operation of the bus used by processors that implement the PowerPC architecture.

Chapter 9, “PCI Bridge,”

describes how the PCI bridge enables the MPC8280 to gluelessly bridge PCI agents to a host processor that implements the PowerPC architecture and how it is compliant with PCI Specification Revision 2.2.

Chapter 10, “Clocks and Power Control,”

describes the clocking architecture of the MPC8280.

Chapter 11, “Memory Controller,”

describes the memory controller, which controls a maximum of eight memory banks shared among a general-purpose chip-select machine (GPCM) and three user-programmable machines (UPMs). —

Chapter 12, “Secondary (L2) Cache Support,”

provides information about implementation and configuration of a level-2 cache. —

Chapter 13, “IEEE 1149.1 Test Access Port,”

describes the dedicated user-accessible test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

Part IV, “Communications Processor Module,”

describes the configuration, clocking, and operation of the various communications protocols that the MPC8280 supports.

Chapter 14, “Communications Processor Module Overview,”

CPM.

provides a brief overview of the —

Chapter 15, “Serial Interface with Time-Slot Assigner,”

describes the SIU, which controls system start-up, initialization and operation, protection, as well as the external system bus.

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Chapter 16, “CPM Multiplexing,”

describes the CPM multiplexing logic (CMX) that connects the physical layer—UTOPIA, MII, modem lines. —

Chapter 17, “Baud-Rate Generators (BRGs),”

describes the eight independent, identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and SMCs. —

Chapter 18, “Timers,”

describes the timer implementation, which can be configured as four identical 16-bit or two 32-bit general-purpose timers. —

Chapter 19, “SDMA Channels and IDMA Emulation,”

describes the two physical serial DMA (SDMA) channels on the MPC8280.

Chapter 20, “Serial Communications Controllers (SCCs),”

describes the four serial communications controllers (SCC), which can be configured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks. —

Chapter 21, “SCC UART Mode,”

describes the MPC8280 implementation of universal asynchronous receiver transmitter (UART) protocol that sends low-speed data between devices. —

Chapter 22, “SCC HDLC Mode,”

describes the MPC8280 implementation of HDLC protocol. —

Chapter 23, “SCC BISYNC Mode,”

describes the MPC8280 implementation of byte-oriented BISYNC protocol developed by IBM for use in networking products. —

Chapter 24, “SCC Transparent Mode,”

describes the MPC8280 implementation of transparent mode (also called totally transparent mode), which provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation. —

Chapter 25, “SCC Ethernet Mode,”

describes the MPC8280 implementation of Ethernet protocol.

Chapter 26, “SCC AppleTalk Mode,”

describes the MPC8280 implementation of AppleTalk.

Chapter 27, “Universal Serial Bus Controller,”

describes the MPC8280’s USB controller, including basic operation, the parameter RAM, and registers.

Chapter 28, “Serial Management Controllers (SMCs),”

describes two serial management controllers, full-duplex ports that can be configured independently to support one of three protocols—UART, transparent, or general-circuit interface (GCI). —

Chapter 29, “Multi-Channel Controllers (MCCs),”

describes the MPC8280’s multi-channel controller (MCC), which handles up to 128 serial, full-duplex data channels. —

Chapter 30, “Fast Communications Controllers (FCCs),”

describes the MPC8280’s fast communications controllers (FCCs), which are SCCs optimized for synchronous high-rate protocols.

Chapter 31, “ATM Controller and AAL0, AAL1, and AAL5,”

describes the MPC8280 ATM controller, which provides the ATM and AAL layers of the ATM protocol. The ATM controller performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and AAL0, and most of the common parts convergence sublayer (CP-CS) of these protocols. —

Chapter 32, “ATM AAL1 Circuit Emulation Service,”

describes the implementation of circuit emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the MPC8280.

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• • • —

Chapter 33, “ATM AAL2,”

describes the functionality and data structures of ATM adaptation layer type 2 (AAL2) CPS, CPS switching, and SSSAR.

Chapter 34, “Inverse Multiplexing for ATM (IMA),”

describes specifications for the inverse multiplexing for ATM (IMA) microcode.

Chapter 35, “ATM Transmission Convergence Layer,”

describes how the MPC8280 can support applications that receive ATM traffic over the standard serial protocols like E1, T1, and xDSL via its serial interface (SIx TDMx and NMSI) ports because of its internally implemented TC-layer functionality.

Chapter 36, “Fast Ethernet Controller,”

describes the MPC8280’s implementation of the Ethernet IEEE 802.3 protocol.

Chapter 37, “FCC HDLC Controller,”

describes the FCC implementation of the HDLC protocol. —

Chapter 38, “FCC Transparent Controller,”

describes the FCC implementation of the transparent protocol.

— —

Chapter 39, “Serial Peripheral Interface (SPI),”

describes the serial peripheral interface, which allows the MPC8280 to exchange data between other PowerQUICC II chips, the MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.

Chapter 40, “I 2 C Controller,”

describes the MPC8280 implementation of the inter-integrated circuit (I 2 C®) controller, which allows data to be exchanged with other I 2 C devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters. —

Chapter 41, “Parallel I/O Ports,”

describes the four general-purpose I/O ports A–D. Each signal in the I/O ports can be configured as a general-purpose I/O signal or as a signal dedicated to supporting communications devices, such as SMCs, SCCs. MCCs, and FCCs.

Appendix A, “Register Quick Reference Guide,”

provides a quick reference to the registers incorporated in the G2_LE core.

Appendix B, “Revision History,”

provides a list of the major differences between revisions of the MPC8280 PowerQUICC II Family Reference Manual. This book also includes an index and a glossary.

Suggested Reading

This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture.

MPC82xx Documentation

Supporting documentation for the MPC8280 can be accessed through the world-wide web at www.freescale.com. This documentation includes technical specifications, reference materials, and detailed applications notes.

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Architecture Documentation

Architecture documentation is organized in the following types of documents: • • • • Manuals—These books provide details about individual implementations of the PowerPC architecture and are intended to be used with the Programming Environments Manual. These include the G2 Core Reference Manual (Freescale order #: G2CORERM).

Programming environments manuals—These books provide information about resources defined by the PowerPC architecture that are common to processors that implement the PowerPC architecture. The two versions include one that describes the functionality of the combined 32- and 64-bit architecture models and one that describes only the 32-bit model. The MPC8280 adheres to the 32-bit architecture definition. — Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture (Freescale order #: MPCFPE32B) The Programmer’s Pocket Reference Guide for the PowerPC Architecture: MPCPRGREF/D—This guide provides an overview of registers, instructions, and exceptions for 32-bit implementations.

Application notes—These short documents contain useful information about specific design issues useful to programmers and engineers working with Freescale’s processors. For a current list of documentation, refer to www.freescale.com.

Conventions

This document uses the following notational conventions:

Table 1:

Bold entries in figures and tables showing registers and parameter RAM should be initialized by the user.

B ld mnemonics

Instruction mnemonics are shown in lowercase bold.

italics

Italics indicate variable command parameters, for example, bcctrx.

Book titles in text are set in italics.

0x0 0b0 rA, rB rD REG[FIELD] Prefix to denote hexadecimal number Prefix to denote binary number Instruction syntax used to identify a source GPR Instruction syntax used to identify a destination GPR x

n

¬ Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.

In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Used to express an undefined numerical value NOT logical operator Freescale Semiconductor

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| & AND logical operator OR logical operator CMX CPM CR CRC CTR DABR DAR DEC DMA DPLL DRAM DSISR DTLB EA EEST

Acronyms and Abbreviations

Table i

contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.

Table i. Acronyms and Abbreviated Terms Term

A/D ALU ATM BD BIST BPU BRI BUID CAM CEPT

Meaning

Analog-to-digital Arithmetic logic unit Asynchronous transfer mode Buffer descriptor Built-in self test Branch processing unit Basic rate interface.

Bus unit ID Content-addressable memory Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations).

CPM multiplexing logic Communication processor module Condition register Cyclic redundancy check Count register Data address breakpoint register Data address register Decrementer register Direct memory access Digital phase-locked loop Dynamic random access memory Register used for determining the source of a DSI exception Data translation lookaside buffer Effective address Enhanced Ethernet serial transceiver lxxxvi

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Term

IDL IEEE IrDA ISDN ITLB IU JTAG LIFO EPROM FPR FPSCR FPU GCI GPCM GPR GUI HDLC I 2 C LR LRU LSB lsb LSU MAC MESI MMU MSB msb MSR NaN NIA NMSI No-op

Table i. Acronyms and Abbreviated Terms (continued) Meaning

Erasable programmable read-only memory Floating-point register Floating-point status and control register Floating-point unit General circuit interface General-purpose chip-select machine General-purpose register Graphical user interface High-level data link control Inter-integrated circuit Inter-chip digital link Institute of Electrical and Electronics Engineers Infrared Data Association Integrated services digital network Instruction translation lookaside buffer Integer unit Joint Test Action Group Last-in-first-out Link register Least recently used Least-significant byte Least-significant bit Load/store unit Multiply accumulate Modified/exclusive/shared/invalid—cache coherency protocol Memory management unit Most-significant byte Most-significant bit Machine state register Not a number Next instruction address Nonmultiplexed serial interface No operation Freescale Semiconductor

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Term

OEA OSI PCI PCMCIA PIR PRI PVR RISC RTOS RWITM Rx SCC SCP SDLC SDMA SI SRR0 SRR1 TAP TB TDM TLB TSA Tx UART SIMM SIU SMC SNA SPI SPR SPRG n SRAM

Table i. Acronyms and Abbreviated Terms (continued) Meaning

Operating environment architecture Open systems interconnection Peripheral component interconnect Personal Computer Memory Card International Association Processor identification register Primary rate interface Processor version register Reduced instruction set computing Real-time operating system Read with intent to modify Receive Serial communication controller Serial control port Synchronous data link control Serial DMA Serial interface Signed immediate value System interface unit Serial management controller Systems network architecture Serial peripheral interface Special-purpose register Registers available for general purposes Static random access memory Machine status save/restore register 0 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit Universal asynchronous receiver/transmitter lxxxviii

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Term

UIMM UISA UPM USART USB VA VEA XER

Table i. Acronyms and Abbreviated Terms (continued) Meaning

Unsigned immediate value User instruction set architecture User-programmable machine Universal synchronous/asynchronous receiver/transmitter Universal serial bus Virtual address Virtual environment architecture Register used primarily for indicating conditions such as carries and overflows for integer operations

PowerPC Architecture Terminology Conventions

Table ii

lists certain terms used in this manual that differ from the architecture terminology conventions.

Table ii. Terminology Conventions The Architecture Specification

Data storage interrupt (DSI) Extended mnemonics Instruction storage interrupt (ISI) Interrupt Privileged mode (or privileged state) Problem mode (or problem state) Real address Relocation Storage (locations) Storage (the act of)

This Manual

DSI exception Simplified mnemonics ISI exception Exception Supervisor-level privilege User-level privilege Physical address Translation Memory Access Freescale Semiconductor

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Table iii

describes instruction field notation conventions used in this manual.

Table iii. Instruction Field Conventions The Architecture Specification

BA, BB, BT BF, BFA D DS FLM FXM RA, RB, RT, RS SI U UI /, //, ///

Equivalent to: crb

A,

crb

B,

crb

D (respectively)

crf

D,

crf

S (respectively) d ds FM CRM

r

A,

r

B,

r

D,

r

S (respectively) SIMM IMM UIMM 0...0 (shaded) xc

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Part I Overview

Intended Audience

Part I is intended for readers who need a high-level understanding of the MPC8280.

Contents

Part I provides a high-level description of the MPC8280, describing general operation and listing basic

features. • • •

Chapter 1, “Overview,”

provides a high-level description of MPC8280 functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.

Chapter 2, “G2_LE Core,”

provides an overview of the MPC8280 core.

Chapter 3, “Memory Map,”

presents a table showing where MPC8280 registers are mapped in memory. It includes cross references that indicate where the registers are described in detail.

Conventions

Part I uses the following notational conventions:

mnemonics

Instruction mnemonics are shown in lowercase bold.

italics

Italics indicate variable command parameters, for example, bcctrx.

Book titles in text are set in italics.

0x0 0b0 rA, rB rD REG[FIELD] Prefix to denote hexadecimal number Prefix to denote binary number Instruction syntax used to identify a source GPR Instruction syntax used to identify a destination GPR Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.

x

n

In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value Freescale Semiconductor

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I-1

Acronyms and Abbreviations

Table I-1

contains acronyms and abbreviations that are used in this document.

Table I-1. Acronyms and Abbreviated Terms Term

ATM BD BPU COP CP CPM CRC CTR DABR DAR DEC DMA DPLL DRAM DTLB EA FCC‘ FPR GPCM GPR HDLC I 2 C IEEE ISDN ITLB IU JTAG LRU LSU MCC

Meaning

Asynchronous Mode Buffer descriptor Branch processing unit Common on-chip processor Communications processor Communications processor module Cyclic redundancy check Count register Data address breakpoint register Data address register Decrementer register Direct memory access Digital phase-locked loop Dynamic random access memory Data translation lookaside buffer Effective address Fast communications controller Floating-point register General-purpose chip-select machine General-purpose register High-level data link control Inter-integrated circuit Institute of Electrical and Electronics Engineers Integrated services digital network Instruction translation lookaside buffer Integer unit Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Multi-channel controller I-2

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Term

MII MMU MSR NMSI OEA OSI PCI RISC RTC RTOS Rx SCC SDLC SDMA SI SIU SMC SPI SPR SRAM TAP TB TDM TLB TSA Tx UART UISA UPM VEA

Table I-1. Acronyms and Abbreviated Terms (continued) Meaning

Media-independent interface Memory management unit Machine state register Nonmultiplexed serial interface Operating environment architecture Open systems interconnection Peripheral component interconnect Reduced instruction set computing Real-time clock Real-time operating system Receive Serial communications controller Synchronous data link control Serial DMA Serial interface System interface unit Serial management controller Serial peripheral interface Special-purpose register Static random access memory Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit Universal asynchronous receiver/transmitter User instruction set architecture User-programmable machine Virtual environment architecture Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

I-3

I-4

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Chapter 1 Overview

The MPC8280 is a versatile communications processor that integrates on one chip a high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The MPC8280 core—a G2_LE—is an embedded variant of the MPC603e microprocessor with 16 Kbytes of instruction cache and 16 Kbytes of data cache. The system interface unit (SIU) consists of a flexible memory controller that interfaces to almost any user-defined memory system, a 60x-to-PCI bus bridge, and many other peripherals making this device a complete system on a chip. The MPC8280 communications processor module (CPM) includes all the peripherals found in the MPC8260 PowerQUICC II family. In addition, the MPC8280 offers USB functionality.

This manual describes the functional operation of MPC8280, with an emphasis on peripheral functions.

Chapter 2, “G2_LE Core,”

is an overview of the microprocessor core; detailed information about the core can be found in the G2 Core Reference Manual (order number: G2CORERM).

1.1

Features

The following is an overview of the MPC8280 feature set: • Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 166–450 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm • • — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — Supports bus snooping for data cache coherency — Floating-point unit (FPU) Separate power supply for internal logic and for I/O Separate PLLs for G2_LE core and for the CPM — G2_LE core and CPM can run at different frequencies for power/performance optimization Freescale Semiconductor

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Overview

• • • • — Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios 64-bit data and 32-bit address 60x bus — Bus supports multiple master designs — Supports single- and four-beat burst transfers — 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller — Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus — Single-master bus, supports external slaves — Eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge — Programmable host bridge and agent — 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V — Synchronous and asynchronous 60x and PCI clock modes — All internal address space available to external PCI host — DMA for memory block transfers — PCI-to-60x address remapping PCI bridge — PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz — On-chip arbitration — Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming — PCI host bridge or peripheral capabilities — Includes 4 DMA channels for the following transfers: – PCI-to-60x to 60x-to-PCI – 60x-to-PCI to PCI-to-60x – PCI-to-60x to PCI-to-60x – 60x-to-PCI to 60x-to-PCI — Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers — Supports the I 2 O standard — Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August 3, 1998) — Support for 66.67/83.33/100 MHz, 3.3 V specification 1-2

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Freescale Semiconductor

Overview

• • • • — 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port — Uses the local bus signals, removing need for additional pins System interface unit (SIU) — Clock synthesizer — Reset controller — Real-time clock (RTC) register — Periodic interrupt timer — Hardware bus monitor and software watchdog timer — IEEE 1149.1 JTAG test access port 12-bank memory controller — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable peripherals — Byte write enables and selectable parity generation — 32-bit address decodes with programmable bank size — Three user-programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine — Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local) — Dedicated interface logic for SDRAM CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols — Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte dual-port instruction RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers supporting the following protocols: – 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII) – ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM support for the MPC8270) – Transparent – HDLC—Up to T3 rates (clear channel) – FCC2 can also be connected to the TC layer (MPC8280 only) Freescale Semiconductor

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Overview

— Two multichannel controllers (MCCs) (one MCC on the MPC8270) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Universal serial bus (USB) controller – USB 2.0 full/low rate compatible – USB host mode –Supports control, bulk, interrupt, and isochronous data transfers –CRC16 generation and checking –NRZI encoding/decoding with bit stuffing –Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub.

–Flexible data buffers with multiple buffers per frame –Supports local loopback mode for diagnostics (12 Mbps only) – Supports USB slave mode –Four independent endpoints support control, bulk, interrupt, and isochronous data transfers –CRC16 generation and checking –CRC5 checking –NRZI encoding/decoding with bit stuffing –12- or 1.5-Mbps data rate –Flexible data buffers with multiple buffers per frame –Automatic retransmission upon transmit error — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels 1-4

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Overview

– Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One inter-integrated circuit (I 2 C) controller (identical to the MPC860 I 2 C controller) – Microwire compatible – Multiple-master, single-master, and slave modes — Up to eight TDM interfaces (four on the MPC8270) – Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270 and the MPC8275) – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces — Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels — Four independent 16-bit timers that can be interconnected as two 32-bit timers — Transmission convergence (TC) layer (MPC8280 only) — Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only). Supported by eight TC layers between the TDMs and FCC2.

1.2

Architecture Overview

The MPC8280 has two external buses to accommodate bandwidth requirements from the high-speed

system core and the very fast communications channels. Figure 1-1 shows the block diagram of the

superset MPC8280 device. Features that are device- or package-specific are noted. For package information, refer to the MPC8280 PowerQUICC II Family Hardware Specifications (order number: MPC8280EC).

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Overview G2_LE Core

16 Kbytes I-Cache I-MMU 16 Kbytes D-Cache D-MMU Timers Parallel I/O Baud Rate Generators

Communication Processor Module (CPM)

Interrupt Controller 32 KB Instruction RAM 32 KB Data RAM 32-bit RISC Microcontroller and Program ROM IMA

1

Microcode Serial DMAs 4 Virtual IDMAs

System Interface Unit (SIU)

Bus Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Clock Counter System Functions

60x Bus

PCI Bus 32 bits, up to 66 MHz or Local Bus 32 bits, up to 100 MHz MCC1

1

MCC2 FCC1 FCC2 FCC3 TC Layer Hardware

1

SCC1 SCC2 SCC3 SCC4/

USB

SMC1 Time Slot Assigner SMC2 Serial Interface 2 SPI I 2 C 8 TDM Ports

2

3 MII or RMII Ports 2 UTOPIA Ports

3

Non-Multiplexed I/O Notes: 1 MPC8280 only (not on MPC8270, the VR package, nor the ZQ package) 2 MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have only 1 SI block and 4 TDM ports (TDM2[A–D]).

3 MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)

Figure 1-1. MPC8280 Block Diagram

Both the system core and the CPM have an internal PLL, which allows independent optimization of the frequencies at which they run. The system core and CPM are both connected to the 60x bus.

1.2.1

G2_LE Core

The G2_LE core is derived from the MPC603e microprocessor with power management modifications. The core is a high-performance low-power implementation of the family of reduced instruction set computer (RISC) microprocessors. The G2_LE core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits. The G2_LE cache provides snooping to ensure data coherency with other masters. This helps ensure coherency between the CPM and system core.

The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit split-transaction external data bus, which is connected directly to the external MPC8280 pins.

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Overview

The G2_LE core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator support. The G2_LE core can be disabled. In this mode, the MPC8280 functions as a slave peripheral to an external core or to another PowerQUICC II device with its core enabled.

1.2.2

System Interface Unit (SIU)

The SIU consists of the following: • • • • • • • • A 60x-compatible parallel system bus configurable to 64-bit data width. The MPC8280 supports 64-, 32-, 16-, and 8-bit port sizes. The MPC8280 internal arbiter arbitrates between internal components that can access the bus (system core, PCI bridge, CPM, and one external master). This arbiter can be disabled, and an external arbiter can be used if necessary.

A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used to enhance the operation of the very high-speed communication controllers. Without requiring extensive manipulation by the core, the bus can be used to store connection tables for ATM or buffer descriptors (BDs) for the communication channels or raw data that is transmitted between channels. The local bus is synchronous to the 60x bus and runs at the same frequency.

The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1) bus. In PCI mode the bus can be programmed as a host or as an agent. The PCI bus can be configured to run synchronously or asynchronously to the 60x bus. The MPC8280 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory block transfers. Applications that require both the local bus and PCI bus need to connect an external PCI bridge.

Memory controller supporting 12 memory banks that can be allocated for either the system or the local bus. The memory controller is an enhanced version of the MPC860 memory controller. It supports three user-programmable machines. Besides all MPC860 features, the memory controller also supports SDRAM with page mode and address data pipeline.

Supports JTAG controller IEEE 1149.1 test access port (TAP).

A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer, and other system functions useful in embedded applications.

Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM (MCM69C232/MCM69C432).

1.2.3

Communications Processor Module (CPM)

The CPM contains features that allow the MPC8280 to excel in a variety of applications targeted mainly for networking and telecommunication markets.

The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP performance and additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps full-duplex). Freescale Semiconductor

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Overview

The following list summarizes the major features of the CPM: • • • • • • • • The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus) from the 60x bus (used by the system core). With this separate bus, the CP does not affect the performance of the G2_LE core. The CP handles the lower layer tasks and DMA control activities, leaving the G2_LE core free to handle higher layer activities. The CP has an instruction set optimized for communications, but can also be used for general-purpose applications, relieving the system core of small often repeated tasks.

Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst transfers to the 60x bus and to the local bus.

Three full-duplex, serial fast communications controllers (FCCs) supporting ATM (155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces on the MPC8280), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and totally transparent operation. Each FCC can be configured to transmit fully transparent and receive HDLC or vice-versa. (Note that the MPC8270 does not support ATM (155 Mbps) protocol.) Two multichannel controllers (MCCs) that can handle an aggregate of 256 X 64 Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling of the 64-Kbps channels.

Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/Ethernet, high- level synchronous data link control, HDLC, local talk, UART, synchronous UART, BISYNC, and transparent.

Two full-duplex serial management controllers (SMC) supporting GCI, UART, and transparent operations Serial peripheral interface (SPI) and I 2 C bus controllers Time-slot assigner (TSA) that supports multiplexing of data from any of the four SCCs, three FCCs, and two SMCs.

1.3

Software Compatibility Issues

As much as possible, the MPC8280 CPM features were made similar to those of the previous MPC860 PowerQUICC family devices and the MPC8260 PowerQUICC II family devices. The code flow ports easily from previous devices to the MPC8280, except for new protocols supported by the MPC8280. Although many registers are new, most registers retain the old status and event bits, so an understanding of the programming models of the MC68360, MPC860, or MPC85015 is helpful. Note that the MPC8280 initialization code requires changes from the MPC860 initialization code (Freescale provides reference code).

1.3.1

Signals

Figure 1-2 shows MPC8280 signals grouped by function. Note that many of these signals are multiplexed

and this figure does not indicate how these signals are multiplexed.

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NOTE

A bar over a signal name indicates that the signal is active low—for example, BB (bus busy). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0–3] (transfer size signals) are referred to as asserted when they are high and negated when they are low.

VCCSYN/GNDSYN/VCCSYN1//VDDH/ VDD/VSS PCI_PAR/

L_A14

SMI/PCI_FRAME/

L_A15

PCI_TRDY/

L_A16

CKSTOP_OUT/PCI_IRDY/

L_A17

PCI_STOP/

L_A18

PCI_DEVSEL/

L_A19

PCI_IDSEL/

L_A20

PCI_PERR/

L_A21

PCI_SERR/

L_A22

PCI_REQ0/

L_A23

CPCI_HS_ES/PCI_REQ1/

L_A24

PCI_GNT0/

L_A25

CPCI_HS_LED/PCI_GNT1/

L_A26

CPCI_HS_ENUM/PCI_CLK/

L_A27

CORE_SRESET/PCI_RST/

L_A28

PCI_INTA/

L_A29

PCI_REQ2/

L_A30

DLLOUT/

L_A31

PCI_AD[0–31]/

LCL_D[0–31]

PCI_C/BE[0–3]/

LCL_DP[0–3]

⎯⎯⎯> 100 <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯⎯ <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 4 PCI_CFG[3–0]/LBS[0–3]/ LSDDQM[0–3]/

LWE[0–3]

<⎯⎯⎯ PCI_MODCK_H0/LGPL0/

LSDA10

PCI_MODCK_H1/LGPL1/

LSDWE

PCI_MODCK_H2/LGPL2/LSDRAS/

LOE

PCI_MODCK_H3/LGPL3/

LSDCAS

LPBS/LGPL4/LUPMWAIT/

LGTA

PCI_MODCK/

LGPL5 LWR

<⎯⎯⎯ <⎯⎯⎯ <⎯⎯⎯ <⎯⎯⎯ <⎯⎯> <⎯⎯> <⎯⎯>

PA[0–31] PB[4–31] PC[0–31] PD[4–31]

4 <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> 32 28 32 28 PCI_RST/

PORESET

⎯⎯⎯>

RSTCONF

⎯⎯⎯>

HRESET

<⎯⎯>

SRESET

<⎯⎯>

QREQ

<⎯⎯⎯

XFC

⎯⎯⎯>

CLKIN1

⎯⎯⎯>

TRIS

⎯⎯⎯> BNKSEL[0]/TC[0]/AP[1]/

MODCK1

<⎯⎯> BNKSEL[1]/TC[1]/AP[2]/

MODCK2

<⎯⎯> BNKSEL[2]/TC[2]/AP[3]/

MODCK3

<⎯⎯>

PCI_MODE

⎯⎯⎯>

CLKIN2

NC ⎯⎯⎯> ⎯⎯⎯> 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1

L O C A L B U S M E M C P I O R S T C L K 6 0 x B U S M E M C J T A G

5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 2 1 1 8 32 <⎯⎯>

A[0–31]

<⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯⎯ <⎯⎯> ⎯⎯⎯> ⎯⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> ⎯⎯⎯> <⎯⎯> <⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯>

TT[0–4] TSIZ[0–3] TBST GBL CI

/BADDR29/IRQ2

WT

/IRQ1 /BADDR30/IRQ3

L2_HIT CPU_BG CPU_DBG CPU_BR BR BG ABB TS

/IRQ2

AACK ARTRY DBG DBB NC IRQ1 IRQ2 TA TEA IRQ0 IRQ7 ALE

/IRQ4 /BADDR31/IRQ5/CINT /IRQ3

D[0–63]

/DP0/RSRV/EXT_BR2

IRQ3/ IRQ4/ IRQ5/ IRQ6/ IRQ7/

/DP1/EXT_BG2 /DP2/TLBISYNC/EXT_DBG2 DP3/CKSTP_OUT/EXT_BR3 DP4/CORE_SRESET/EXT_BG3 DP5/TBEN/EXT_DBG3/CINT DP6/CSE0 DP7/CSE1

PSDVAL

/NMI_OUT /INT_OUT/APE

CS[0–9] CS[10] CS[11] BCTL0

/BCTL1 /AP[0]

BADDR[27–28] PWE[0–7]

/PSDDQM[0–7]/PBS[0–7] ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> <⎯⎯>

PSDA10

/PGPL0

PSDWE POE

/PSDRAS/PGPL2

PSDCAS PGTA

<⎯⎯⎯

TRST

⎯⎯⎯>

TDO

/PGPL1 /PGPL3 /PUPMWAIT/PGPL4/PPBS ⎯⎯⎯>

PSDAMUX

/PGPL5 <⎯⎯⎯

TMS

<⎯⎯⎯

TDI

<⎯⎯⎯

TCK Figure 1-2. MPC8280 External Signals Overview

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Overview

1.4

Differences Between MPC860 and MPC8280

The following MPC860 features are not included in the MPC8280.

• • • • • • • • • • • • • • On-chip crystal oscillators (must use external oscillator) 4-MHz oscillator (input clock must be at the bus speed) Low power (stand-by) modes Battery-backup real-time clock (must use external battery-backup clock) BDM (COP offers most of the same functionality) True little-endian mode PCMCIA interface Infrared (IR) port QMC protocol in SCC (256 HDLC channels are supported by the MCCs) Multiply and accumulate (MAC) block in the CPM Centronics port (PIP) Pulse-width modulated outputs SCC Ethernet controller option to sample 1 byte from the parallel port when a receive frame is complete Parallel CAM interface for SCC (Ethernet)

1.5

Serial Protocol Table

Table 1-1

summarizes available protocols for each serial port.

Table 1-1. MPC8280 Serial Protocols Port Port

ATM (Utopia) 1 100BaseT 10BaseT HDLC HDLC_BUS Transparent UART DPLL Multichannel Universal serial bus 1 Not on the MPC8270

FCC

√ √ √ √ √

SCC

√ √ √ √ √ √

MCC

√ √ √

SMC

√ √

USB

√ 1-10

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Overview

1.6

MPC8280 Configurations

The MPC8280 offers flexibility in configuring the device for specific applications. The functions mentioned in the above sections are all available in the device, but not all of them can be used at the same time. This does not imply that the device is not fully activated in any given implementation: The CPM architecture has the advantage of using common hardware resources for many different protocols, and applications. Two physical factors limit the functionality in any given system—pinout and performance.

1.6.1

Pin Configurations

Some pins have multiple functions. Choosing one function may preclude the use of another. Information

about multiplexing constraints can be found in Chapter 16, “CPM Multiplexing,”

and

Chapter 41, “Parallel I/O Ports .”

1.6.2

Serial Performance

Serial performance depends on a number of factors: • • • • Serial rate versus CPM clock frequency for adequate sampling on serial channels Serial rate and protocol versus CPM clock frequency for CP protocol handling Serial rate and protocol versus bus bandwidth Serial rate and protocol versus system core clock for adequate protocol handling The second item above is addressed in this section—the CP’s ability to handle high bit-rate protocols in parallel. Slow bit-rate protocols do not significantly affect those numbers.

Table 1-2

describes a few options to configure the fast communications channels on the MPC8280. The frequency specified is the minimum CPM frequency necessary to run the mentioned protocols concurrently at full-duplex.

Table 1-2. Serial Performance 1 FCC1 FCC2

155-Mbps ATM 100 BaseT 155-Mbps ATM 100 BaseT 100 BaseT 100 BaseT 100 BaseT 155-Mbps ATM 100 BaseT 45-Mbps HDLC 45-Mbps HDLC 100 BaseT 100 BaseT 1

For the MPC8270 see Table 1-3 .

FCC3

100 BaseT 100 BaseT

MCC

128 * 64 Kbps channels 128 * 64 Kbps channels 256 * 64 Kbps channels 256 * 64 Kbps channels 256 * 64 Kbps 256 * 64 Kbps 16 * 576 Kbps

CPM Clock (MHz)

133 133 133 133 166 133 133 166 166

60x Bus Clock (MHz)

66 66 66 66 66 66 66 66 66 Freescale Semiconductor

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Overview

Table 1-3

shows serial performance for the MPC8270, which does not support ATM (155-Mbps).

Table 1-3. MPC8270 Serial Performance FCC 1 FCC 2 FCC 3 MCC CPM Clock (MHz) 60x Bus Clock (MHz)

100 BaseT 100 BaseT 100 BaseT 45-Mbps HDLC 45-Mbps HDLC 100 BaseT 100 BaseT 100 BaseT 100 BaseT 45-Mbps 45-Mbps 45-Mbps 45-Mbps 100 BaseT 100 BaseT 100 BaseT 100 BaseT 100 BaseT 128 * 64 Kbps channels 128 * 64 Kbps channels 128 * 64 Kbps channels 128 * 64 Kbps channels 8 * 576 Kbps channels 128 * 64 Kbps channels 133 133 133 133 133 133 133 66 66 66 66 66 66 66 FCCs can also be used to run slower HDLC or 10 BaseT, for example. The CP’s RISC architecture has the advantage of using common hardware resources for all FCCs.

1.7

Application Examples

The MPC8280 can be configured to meet many system application needs, as described in the following

sections and shown in Figure 1-3

through Figure 1-11 .

NOTE: Differences among MPC8280 PowerQUICC II Family Devices

Refer to

Figure 1-1

and

Section 1.1, “Features,”

to determine possible differences in features between a given device and the following descriptions.

1.7.1

Communication Systems

The following sections describe the following examples of communication systems: • • • • • •

Section 1.7.1.1, “Remote Access Server”

Section 1.7.1.2, “Regional Office Router” Section 1.7.1.3, “LAN-to-WAN Bridge Router”

Section 1.7.1.4, “Cellular Base Station”

Section 1.7.1.5, “Telecommunications Switch Controller”

Section 1.7.1.6, “SONET Transmission Controller”

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Overview 1.7.1.1

Remote Access Server

Figure 1-3 shows remote access server configuration.

MPC8280 Quad T1 Framer TDM0 TDM7 60x Bus SDRAM/DRAM/SRAM Channelized Data (up to 256 channels) 155 Mbps ATM PHY MII Transceiver Framer or UTOPIA Multi PHY Local Bus SDRAM/DRAM/SRAM ATM Connection Tables (optional) 10/100BaseT or E3 clear channel (takes one TDM) DSP Bank SMC/I 2 C/SPI/SCC Slaves on Local Bus Slow Comm PHY

Figure 1-3. Remote Access Server Configuration

In this application, eight TDM ports are connected to external framers. In the MPC8280, each group of four ports support up to 128 channels. One TDM interface can support 32–128 channels. The MPC8280 receives and transmits data in transparent or HDLC mode, and stores or retrieves the channelized data from memory. The data can be stored either in memory residing on the 60x bus or in memory residing on the local bus.

The main trunk can be configured as 155 Mbps full-duplex ATM, using the UTOPIA interface, or as 10/100 BaseT Fast Ethernet with MII interface, or as a high-speed serial channel (up to 45 Mbps). In ATM mode, there may be a need to store connection tables in external memory on the local bus; for example, 128 active internal connections require 8 Kbytes of dual-port RAM. The need for local bus depends on the total throughput of the system. The MPC8280 supports automatic (without software intervention) cross- connect between ATM and MCC, routing ATM AAL1 frames to MCC slots.

The local bus can be used as an interface to a bank of DSPs that can run code that performs analog modem signal modulation. Data to and from the DSPs can be transferred through the parallel bus with the internal virtual IDMA.

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Overview

The MPC8280 memory controller supports many types of memories, including EDO DRAM and page-mode, pipeline SDRAM for efficient burst transfers.

1.7.1.2

Regional Office Router

Figure 1-4 shows a regional office router configuration.

MPC8280 TDM0 Quad T1 Framer TDM3 MII Transceiver 10/100BaseT 10/100BaseT 60x Bus SDRAM/DRAM/SRAM Channelized Data (up to 128 channels) Slow Comm PHY SMC/I 2 C/SPI/SCC

Figure 1-4. Regional Office Router Configuration

In this application, the MPC8280 is connected to four TDM interfaces channelizing up to 128 channels. Each TDM port supports 32–128 channels. If 128 channels are needed, each TDM port can be configured to support 32 channels. This example has two MII ports for 10/100 BaseT LAN connections. In all the examples, the SCC ports can be used for management.

1.7.1.3

LAN-to-WAN Bridge Router

Figure 1-5 shows a LAN-to-WAN router configuration, which is similar to the previous example.

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Overview

MII Transceiver MPC8280 10/100BaseT UTOPIA Multi PHY 60x Bus SDRAM/DRAM/SRAM Data 155 Mbps ATM PHY 155 Mbps ATM PHY MII Transceiver or UTOPIA Multi PHY Local Bus SDRAM/DRAM/SRAM ATM Connection Tables (optional) 10/100BaseT Slow Comm PHY SMC/I 2 C/SPI/SCC

Figure 1-5. LAN-to-WAN Bridge Router Configuration 1.7.1.4

Cellular Base Station

Figure 1-6 shows a cellular base station configuration.

MPC8280 TDM0 SDRAM/DRAM/SRAM Framer 60x Bus Channelized Data (up to 256 channels) TDM1 DSP Bank Local Bus Slow Comm PHY SMC/I2C/SPI/SCC Slaves on Local Bus

Figure 1-6. Cellular Base Station Configuration

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Overview

Here the MPC8280 channelizes two E1s (up to 256, 16-Kbps channels).

The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred through the parallel bus to the host port of the DSPs with the internal virtual IDMA.

The slow communication ports (SCCs, SMCs, I 2 C, SPI) can be used for management and debug functions.

1.7.1.5

Telecommunications Switch Controller

Figure 1-7 shows a telecommunications switch controller configuration.

MPC8280 155 Mbps ATM PHY UTOPIA Multi PHY SDRAM/DRAM/SRAM 60x Bus 10/100BaseT MII Transceiver Slow Comm PHY 10/100BaseT SMC/I 2 C/SPI/SCC (10BaseT) Local Bus SDRAM/DRAM/SRAM ATM Connection Tables

Figure 1-7. Telecommunications Switch Controller Configuration

The CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This includes two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The G2_LE core can operate at a different (higher) speed, if the application requires it.

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Overview 1.7.1.6

SONET Transmission Controller

Figure 1-8 shows a SONET transmission controller configuration

.

576 Kbps SONET Transceivers MPC8280 TDM0 TDM3 60x Bus SDRAM/DRAM/SRAM Channelized Data (up to 16 channels) MII Transceiver Slow Comm PHY 10/100BaseT SMC/I2C/SPI/SCC (10BaseT) Local Bus SDRAM/DRAM/SRAM ATM Connection Tables

Figure 1-8. SONET Transmission Controller Configuration

In this application, the MPC8280 implements super channeling with the MCC. Nine 64-Kbps channels are combined to form a 576-Kbps channel. The MPC8280 at 133 MHz can support up to sixteen 576-Kbps superchannels. The MPC8280 also supports subchanneling (under 64 Kbps) with its MCC.

1.7.2

Bus Configurations

The following sections describe the following possible bus configurations: • • • • • •

Section 1.7.2.1, “Basic System”

Section 1.7.2.2, “High-Performance Communication”

Section 1.7.2.3, “High-Performance System Microprocessor”

Section 1.7.2.4, “PCI” Section 1.7.2.5, “PCI with 155-Mbps ATM”

Section 1.7.2.6, “The MPC8280 as PCI Agent”

1.7.2.1

Basic System

In the basic system configuration, shown in Figure 1-9 , the G2_LE core is enabled and uses the 64-bit 60x

data bus. The 32-bit local bus data is needed to store connection tables for many active ATM connections. The local bus may also be used to store data that does not need to be heavily processed by the core. The Freescale Semiconductor

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Overview

CP can store large data frames in the local memory without interfering with the operation of the system core. MPC8280 SDRAM/SRAM/DRAM/Flash 60x Bus PHY Communication Channels 155 Mbps ATM PHY UTOPIA Local Bus SDRAM/SRAM/DRAM ATM Connection Tables

Figure 1-9. Basic System Configuration 1.7.2.2

High-Performance Communication

Figure 1-10 shows a high-performance communication configuration.

MPC8280-A SDRAM/SRAM/DRAM PHY Communication Channels Local Bus ATM Connection Tables 155 Mbps ATM PHY UTOPIA 60x Bus SDRAM/SRAM/DRAM/Flash 1-18 PHY MPC8280-B (master/slave) Communication Channels 155 Mbps ATM PHY SDRAM/SRAM/DRAM UTOPIA Local Bus or PCI Bus ATM Connection Tables

Figure 1-10. High-Performance Communication MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Overview

Serial throughput is enhanced by connecting one MPC8280 in master or slave mode (with system core enabled or disabled) to another MPC8280 in master mode with the core enabled. The core in MPC8280-A can access the memory on the local bus of MPC8280-B.

1.7.2.3

High-Performance System Microprocessor

Figure 1-11 shows a configuration with a high-performance system microprocessor (MPC750).

MPC750 32-Kbyte I cache 32-Kbyte D cache Backside Cache PHY MPC8280 (slave) Communication Channels 60x Bus SDRAM/SRAM/DRAM 155 Mbps ATM PHY UTOPIA Local Bus SDRAM/SRAM/DRAM ATM Connection Tables

Figure 1-11. High-Performance System Microprocessor Configuration

In this system, the G2_LE core internal is disabled and an external high-performance microprocessor is connected to the 60x bus.

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Overview 1.7.2.4

PCI

See

Figure 1-12 for PCI configuration.

PHY MPC8280 Communication Channels Host or Agent 60x Bus SDRAM/SRAM/DRAM/Flash PCI Bus

Figure 1-12. PCI Configuration

In this system the local bus is configured as PCI (33-MHz 32-bit data bus version 2.1). The MPC8280 can be configured as a host or as an agent on the PCI bus. The 60x bus and PCI bus are asynchronous; there is no frequency dependency between the two. The PCI bus is a 3.3-V bus.

1.7.2.5

PCI with 155-Mbps ATM

Figure 1-13 shows the PCI with 155-Mbps ATM configuration.

PCI Bus PCI Bridge 1-20 PHY ATM PHY MPC8280 Communication Channels 60x Bus SDRAM/SRAM/DRAM UTOPIA Local Bus SDRAM/SRAM/DRAM ATM Connection Tables

Figure 1-13. PCI with 155-Mbps ATM Configuration MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Overview

This system supports PCI and implements a 155-Mbps, full-duplex ATM with more than 128 active connections. The MPC8280 cannot support both functions simultaneously. The local bus is needed to store ATM connection tables. Therefore, an external PCI bridge is necessary. In systems with fewer than 128 active connections or where the ATM average bit rate is lower that 155 Mbps, the local bus may not be necessary to store connection tables, and it may be possible to use it as PCI bus.

1.7.2.6

The MPC8280 as PCI Agent

Figure 1-14 shows the configuration when the MPC8280 acts as the PCI agent.

MPC8280 PHY Communication Channels 60x Bus SDRAM/SRAM/DRAM ATM Connection Tables and/or Communication Data ATM PHY UTOPIA Agent PCI Bus Host PCI Bridge System Bus Host Processor Memory

Figure 1-14. MPC8280 as PCI Agent

In this system, the MPC8280 is a PCI agent on an I/O card and the PCI host resides on the PCI bus. An external PCI bridge is used to connect the host to the PCI bus. The internal PCI bridge in the MPC8280 is used to bridge between the PCI bus and the 60x bus on the MPC8280.

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Chapter 2 G2_LE Core

The MPC8280 contains an embedded G2_LE processor core, which is a derivative of the G2 core and the original MPC603e PowerPC microprocessor design. This chapter provides an overview of the basic functionality of the G2_LE processor core. For detailed information regarding the processor, refer to the following:

• • G2 PowerPC Core Reference Manual The Programming Environments for 32-Bit Implementations of the PowerPC Architecture

This section describes the details of the processor core, provides a block diagram showing the major functional units, and briefly describes how those units interact.

MPC8280-specific implementation includes most of the G2_LE features. The unimplemented features are

described in the Section 2.2, “G2_LE Core Features.”

The signals associated with the processor core are described individually in

Chapter 7, “60x Signals.”

Chapter 8, “The 60x Bus,”

describes how those signals interact.

2.1

Overview

The processor core is a low-power implementation of the family reduced instruction set computing (RISC) microprocessors that implement the PowerPC architecture. The processor core implements the 32-bit portion of the PowerPC architecture, which supports 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.

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G2_LE Core

Figure 2-1 is a block diagram of the processor core.

64-Bit (Two Instructions)

Sequential Fetcher

64-Bi t

Instruction Queue

64-Bit

Branch Processing Unit

CTR CR LR

System Register

/

Unit

+

Integer Unit

* XER + Dispatch Unit 64-Bit 64-Bit (Two Instructions)

Instruction Unit

GPR File GP Rename Registers 32-Bit

Load/Store Unit

+ 64-Bit FPR File FP Rename Registers

Floating Point Unit

/ * + FPSCR

Completion Unit

32-Bit

D MMU

SRs DBAT Array DTLB Power Dissipation Control JTAG/COP Interface Time Base Counter/ Decrementer Clock Multiplier Touch Load Buffer Copy-Back Buffer Tags 16-Kbyte D Cache 64-Bit

I MMU

SRs ITLB IBAT Array Tags 16-Kbyte I Cache

Core Interface

2-2 32-Bit Address Bus 32-/64-Bit Data Bus

Figure 2-1. MPC8280 Integrated Processor Core Block Diagram MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

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G2_LE Core

The processor core is a superscalar processor that can issue and retire as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the processor core makes completion appear sequential.

The processor core integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput. Most integer instructions execute in one clock cycle. On the processor core, the FPU is pipelined so a single-precision multiply-add instruction can be issued and completed every clock cycle. The processor core provides hardware support for all single- and double-precision floating-point operations for most value representations and all rounding modes.

The processor core supports integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. The 32 architecturally-defined floating point registers (FPRs) can be used to hold 32, 64-bit operands that can in turn be transferred to and from the 32 general-purpose registers (GPRs), which can hold 32, 32-bit operands.

The processor core provides separate on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The processor core also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of eight entries each. Effective addresses are compared simultaneously with all eight entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.

As an added feature to the MPC603e core, the MPC8280 can lock the contents of 1–3 ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It allows data to be locked into the data cache, which may be important to code that must have deterministic execution.

The processor core has a 60x bus that incorporates a 64-bit data bus and a 32-bit address bus. The processor core supports single-beat and burst data transfers for memory accesses and supports memory-mapped I/O operations.

2.2

G2_LE Core Features

This section describes the major features of the processor core: • High-performance, superscalar microprocessor — As many as three instructions issued and retired per clock cycle — As many as four instructions in execution per clock cycle — Single-cycle execution for most instructions — Pipelined FPU for all single-precision and most double-precision operations Freescale Semiconductor

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G2_LE Core

• • • • Five independent execution units and two register files — BPU featuring static branch prediction — A 32-bit IU — Fully IEEE 754–compliant FPU for both single- and double-precision operations — LSU for data transfer between data cache and GPRs and FPRs — SRU that executes condition register (CR), special-purpose register (SPR), and integer add/compare instructions — Thirty-two GPRs for integer operands — Thirty-two FPRs for floating-point operands. They also can be used for general operands using floating-point load and store operations. High instruction and data throughput — Zero-cycle branch capability (branch folding) — Programmable static branch prediction on unresolved conditional branches — BPU that performs CR lookahead operations — Instruction fetch unit capable of fetching two instructions per clock from the instruction cache — A six-entry instruction queue that provides lookahead capability — Independent pipelines with feed-forwarding that reduces data dependencies in hardware — 16-Kbyte data cache—Four-way set-associative, physically addressed; LRU replacement algorithm — 16-Kbyte instruction cache—Four-way set-associative, physically addressed; LRU replacement algorithm — Cache write-back or write-through operation programmable on a per page or per block basis — Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size — A 64-entry, two-way set-associative ITLB — A 64-entry, two-way set-associative DTLB — Eight-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks — Software table search operations and updates supported through fast trap mechanism — 52-bit virtual address; 32-bit physical address Facilities for enhanced system performance — A 32- or 64-bit, split-transaction external data bus with burst transfers — Support for one-level address pipelining and out-of-order bus transactions — Critical interrupt exception support — Hardware support for misaligned little-endian accesses Integrated power management — One power-saving mode: doze — Automatic dynamic power reduction when internal functional units are idle 2-4

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• Deterministic behavior and debug features — On-chip cache locking options for the instruction and data caches (1–3 ways or the entire cache contents can be locked) — In-system testability and debugging features through JTAG and boundary-scan capability Features supported by the G2_LE core not present on the MPC8280: • • True little-endian mode for compatibility with other true little-endian devices Nap and sleep power-saving modes

Figure 2-1 shows how the execution units—IU, BPU, LSU, and SRU—operate independently and in

parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip. The processor core provides address translation and protection facilities, including an ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit. The MMUs translate addresses for cache or external memory accesses.

2.2.1

Instruction Unit

As shown in Figure 2-1 , the instruction unit, which contains a fetch unit, instruction queue, dispatch unit,

and the BPU, provides centralized control of instruction flow to the execution units. The instruction unit determines the address of the next instruction to be fetched based on information from the sequential fetcher and from the BPU. The instruction unit fetches the instructions from the instruction cache into the instruction queue. The BPU extracts branch instructions from the fetcher and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in progress in the execution pipeline.

Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If any of these instructions are to be executed in the BPU, they are decoded but not issued. Instructions to be executed by the IU, LSU, and SRU are issued and allowed to complete up to the register write-back stage. Write-back is allowed when a correctly predicted branch is resolved, and instruction execution continues without interruption on the predicted path. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.

2.2.2

Instruction Queue and Dispatch Unit

The instruction queue (IQ), shown in Figure 2-1 , holds as many as six instructions and loads up to two

instructions from the instruction unit during a single cycle. The instruction fetch unit continuously loads as many instructions as space in the IQ allows. Instructions are dispatched to their respective execution units from the dispatch unit at a maximum rate of two instructions per cycle. Reservation stations at the IU, LSU, and SRU facilitate instruction dispatch to those units. The dispatch unit checks for source and destination register dependencies, determines dispatch serializations, and inhibits subsequent instruction dispatching as required.

Section 2.7, “Instruction Timing,”

describes instruction dispatch in detail.

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2.2.3

Branch Processing Unit (BPU)

The BPU receives branch instructions from the fetch unit and performs CR lookahead operations on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.

The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore, when an unresolved conditional branch instruction is encountered, instructions are fetched from the predicted target stream until the conditional branch is resolved.

The BPU contains an adder to compute branch target addresses and three user-control registers—the link register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch target address for the Branch Conditional to Link Register (bclrx) instruction. The CTR contains the branch target address for the Branch Conditional to Count Register (bcctrx) instruction. The contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather than GPRs or FPRs, execution of branch instructions is largely independent from execution of other instructions.

2.2.4

Independent Execution Units

The PowerPC architecture’s support for independent execution units allows implementation of processors with out-of-order instruction execution. For example, because branch instructions do not depend on GPRs or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches. In addition to the BPU, the processor core provides three other execution units and a completion unit, which are described in the following sections.

2.2.4.1

Integer Unit (IU)

The IU executes all integer instructions. The IU executes one integer instruction at a time, performing computations with its arithmetic logic unit (ALU), multiplier, divider, and XER register. Most integer instructions are single-cycle instructions. Thirty-two general-purpose registers are provided to support integer operations. Stalls due to contention for GPRs are minimized by the automatic allocation of rename registers. The processor core writes the contents of the rename registers to the appropriate GPR when integer instructions are retired by the completion unit.

2.2.4.2

Floating-Point Unit (FPU)

The FPU contains a single-precision multiply-add array and the floating-point status and control register (FPSCR). The multiply-add array allows the processor core to efficiently implement multiply and multiply-add operations. The FPU is pipelined so that single-precision instructions and double-precision instructions can be issued back-to-back. Thirty-two floating-point registers are provided to support floating-point operations. Stalls due to contention for FPRs are minimized by the automatic allocation of rename registers. The core writes the contents of the rename registers to the appropriate FPR when floating-point instructions are retired by the completion unit.

The processor core supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero, and infinity) in hardware, eliminating the latency incurred by software exception routines.

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G2_LE Core 2.2.4.3

Load/Store Unit (LSU)

The LSU executes all load and store instructions and provides the data transfer interface between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment, and provides sequencing for load/store string and multiple instructions.

Load and store instructions are issued and translated in program order; however, the actual memory accesses can occur out of order. Synchronizing instructions are provided to enforce strict ordering where needed.

Cacheable loads, when free of data dependencies, execute in an out-of-order manner with a maximum throughput of one per cycle and a two-cycle total latency. Data returned from the cache is held in a rename register until the completion logic commits the value to a GPR or FPR. Store operations do not occur until a predicted branch is resolved. They remain in the store queue until the completion logic signals that the store operation will be completed to memory. The processor core executes store instructions with a maximum throughput of one per cycle and a three-cycle total latency. The time required to perform the actual load or store operation varies depending on whether the operation involves the cache, system memory, or an I/O device.

2.2.4.4

System Register Unit (SRU)

The SRU executes various system-level instructions, including condition register logical operations and move to/from special-purpose register instructions, and also executes integer add/compare instructions. Because SRU instructions affect modes of processor operation, most SRU instructions are completion-serialized. That is, the instruction is held for execution in the SRU until all prior instructions issued have completed. Results from completion-serialized instructions executed by the SRU are not available or forwarded for subsequent instructions until the instruction completes.

2.2.5

Completion Unit

The completion unit tracks instructions from dispatch through execution, and then retires, or completes them in program order. Completing an instruction commits the processor core to any architectural register changes caused by that instruction. In-order completion ensures the correct architectural state when the processor core must recover from a mispredicted branch or any exception.

Instruction state and other information required for completion is kept in a first-in-first-out (FIFO) queue of five completion buffers. A single completion buffer is allocated for each instruction once it enters the dispatch unit. An available completion buffer is a required resource for instruction dispatch; if no completion buffers are available, instruction dispatch stalls. A maximum of two instructions per cycle are completed in order from the queue.

2.2.6

Memory Subsystem Support

The processor core supports cache and memory management through separate instruction and data MMUs (IMMU and DMMU). The processor core also provides dual 16-Kbyte instruction and data caches, and an efficient processor bus interface to facilitate access to main memory and other bus subsystems. The memory subsystem support functions are described in the following subsections.

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G2_LE Core 2.2.6.1

Memory Management Units (MMUs)

The processor core’s MMUs support up to 4 Petabytes (2 52 ) of virtual memory and 4 Gbytes (2 32 ) of physical memory (referred to as real memory in the PowerPC architecture specification) for instructions and data. The MMUs also control access privileges for these spaces on block and page granularities. Referenced and changed status is maintained by the processor for each page to assist implementation of a demand-paged virtual memory system. A key bit is implemented to provide information about memory protection violations prior to page table search operations.

The LSU calculates effective addresses for data loads and stores, performs data alignment to and from cache memory, and provides the sequencing for load and store string and multiple word instructions. The instruction unit calculates the effective addresses for instruction fetching.

The MMUs translate effective addresses and enforce the protection hierarchy programmed by the operating system in relation to the supervisor/user privilege level of the access and in relation to whether the access is a load or store.

2.2.6.2

Cache Units

The processor core provides independent 16-Kbyte, four-way set-associative instruction and data caches. The cache block size is 32 bytes. The caches are designed to adhere to a write-back policy, but the processor core allows control of cacheability, write policy, and memory coherency at the page and block levels. The caches use a least recently used (LRU) replacement algorithm. The load/store and instruction fetch units provide the caches with the address of the data or instruction to be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.

2.3

Programming Model

The following subsections describe the PowerPC instruction set and addressing modes.

2.3.1

Register Set

This section describes the register organization in the processor core as defined by the three programming environments of the PowerPC architecture—the user instruction set architecture (UISA), the virtual environment architecture (VEA), and the operating environment architecture (OEA), as well as the G2_LE core implementation-specific registers. Full descriptions of the basic register set defined by the PowerPC architecture are provided in Chapter 2 in The Programming Environments Manual. The PowerPC architecture defines register-to-register operations for all arithmetic instructions. Source data for these instructions is accessed from the on-chip registers or is provided as an immediate value embedded in the opcode. The three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions and reducing the number of instructions required for certain operations. Data is transferred between memory and registers with explicit load and store instructions only.

Figure 2-2 shows the complete MPC8280 register set and the programming environment to which each

register belongs. This figure includes both the PowerPC register set and the MPC8280-specific registers.

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G2_LE Core

Note that some registers common to other processors that implement the PowerPC architecture may not be implemented in the MPC8280’s processor core. Unsupported SPR values are treated as follows: • • Any mtspr with an invalid SPR executes as a no-op.

Any mfspr with an invalid SPR causes boundedly undefined results in the target register.

Conversely, some SPRs in the processor core may not be implemented or may not be implemented in the same way as in other processors that implement the PowerPC architecture.

2.3.1.1

PowerPC Register Set

The PowerPC UISA registers, shown in Figure 2-2 , can be accessed by either user- or supervisor-level

instructions. The general-purpose registers (GPRs) and floating-point registers (FPRs) are accessed through instruction operands. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as the mtspr and mfspr instructions) or implicit as part of the execution (or side effect) of an instruction. Some registers are accessed both explicitly and implicitly. The number to the right of the register name indicates the number that is used in the syntax of the instruction operands to access the register (for example, the number used to access the XER is 1). For more information on the PowerPC register set, refer to Chapter 2 in The Programming Environments Manual.

Note that the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core Reference Manual, is determined by the CIP bit in the hard reset configuration word in the MPC8280. This is

described in Section 5.4.1, “Hard Reset Configuration Word.”

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G2_LE Core USER MODEL General-Purpose Registers (32-Bit)

GPR0 GPR1 GPR31

Floating-Point Registers (64-Bit)

FPR0 FPR1 FPR31

Condition Register

CR

Floating-Point Status and Control Register

FPSCR

XER

XER SPR 1

Link Register

LR SPR 8

Count Register

CTR SPR 9

Time Base Facility (For Reading)

TBL TBU SPR268 SPR269

SUPERVISOR MODEL Configuration Registers Hardware Implementation Registers Machine State Register

MSR HID0 1 SPR 1008 HID1 1 HID2 1 SPR 1009 SPR 1011

Memory Base Address Register

MBAR 2 SPR 311

System/Processor Version Register

SVR 1 PVR SPR 286 SPR 287

Instruction BAT Registers

IBAT0U

Memory Management Registers Data BAT Registers Software Table Search Registers 1

SPR 528 DBAT0U SPR 536 DMISS SPR 976 IBAT0L SPR 529 DBAT0L SPR 537 DCMP SPR 977 IBAT1U SPR 530 DBAT1U SPR 538 HASH1 SPR 978 IBAT1L SPR 531 DBAT1L SPR 539 HASH2 SPR 979 IBAT2U SPR 532 DBAT2U SPR 540 IMISS SPR 980 IBAT2L SPR 533 DBAT2L SPR 541 ICMP SPR 981 IBAT3U SPR 534 DBAT3U SPR 542 RPA SPR 982 IBAT3L SPR 535 DBAT3L SPR 543

SDR1

IBAT4U 1 IBAT4L 1 IBAT5U 1 SPR 560 SPR 561 SPR 562 DBAT4U 1 DBAT4L 1 DBAT5U 1 SPR 568 SPR 569 SPR 570 SDR1 SPR 25

Segment Registers

IBAT5L 1 SPR 563 DBAT5L 1 SPR 571 SR0 IBAT6U 1 SPR 564 DBAT6U 1 SPR 572 SR1 IBAT6L 1 SPR 565 DBAT6L 1 SPR 573 IBAT7U 1 IBAT7L 1 SPR 566 SPR 567 DBAT7U 1 DBAT7L 1 SPR 574 SPR 575 SR15

Exception Handling Registers Miscellaneous Registers Decrementer SPRGs DSISR

DEC SPR 22 SPRG0 SPR 272 DSISR SPR 18 SPRG1 SPRG2 SPRG3 SPRG4 1 SPRG5 1 SPRG6 1 SPRG7 1 SPR 273 SPR 274 SPR 275 SPR 276 SPR 277 SPR 278 SPR 279

Save and Restore Registers

SRR0 SRR1 SPR 26 SPR 27

External Address Register (Optional)

EAR TBL TBU SPR 282

Time Base Facility (For Writing)

SPR 284 SPR 285

Critical Interrupt Registers 1

CSRR0 CSRR1 SPR 58 SPR 59

Breakpoint Registers Instruction/Data Address Breakpoint Register 1 Instruction/Data Address Breakpoint Control 1

IABR 1 SPR 1010 IBCR SPR 309 IABR2 1 SPR 1018 DBCR SPR 310 DABR 1 SPR 1013 DABR2 1 SPR 317 1 These implementation-specific registers may not be supported by other PowerPC processors or processor cores.

Figure 2-2. MPC8280 Programming Model—Registers MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

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G2_LE Core 2.3.1.2

MPC8280-Specific Registers

The set of registers specific to the MPC603e are also shown in Figure 2-2 . Most of these are described in

the G2 Core Reference Manual and are implemented in the MPC8280 as follows: • • • • MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, and RPA. These registers facilitate the software required to search the page tables in memory.

IABR and IABR2. These registers facilitate the setting of instruction address breakpoints.

DABR and DABR2. These registers facilitate the setting of data address breakpoints.

IBCR and DBCR. These registers give further control to the instruction and data address breakpoints.

The hardware implementation-dependent registers (HIDx) are implemented differently in the MPC8280, and they are described in the following subsections.

2.3.1.2.1

Hardware Implementation-Dependent Register 0 (HID0)

Figure 2-3 shows the MPC8280 implementation of HID0.

0 EMCP 1 — 2 EBA 3 EBD 4 — 6 7 8 PAR DOZE 9 — 10 STOP 11 DPM 12 — 14 15 NHR 16 ICE 17 DCE 18 19 20 21 ILOCK DLOCK ICFI DCFI 22 — 23 24 IFEM 25 — 26 27 FBIOB 28 ABE

Figure 2-3. Hardware Implementation Register 0 (HID0)

29 — 30 31 NOOPTI

Table 2-1

shows the bit definitions for HID0.

Table 2-1. HID0 Field Descriptions Bits

0 1 2 3

Name

EMCP — EBA EBD

Description

Enable machine check input pin 0 The assertion of the MCP does not cause a machine check exception. 1 Enables the entry into a machine check exception based on assertion of the MCP input, detection of a cache parity error, detection of an address parity error, or detection of a data parity error.

Note that the machine check exception is further affected by MSR[ME], which specifies whether the processor checkstops or continues processing.

Reserved Enable/disable 60x bus address parity checking 0 Prevents address parity checking.

1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception if MSR[ME] = 1.

EBA and EBD let the processor operate with memory subsystems that do not generate parity. Enable 60x bus data parity checking 0 Parity checking is disabled.

1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception if MSR[ME] = 1.

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4–6 7 8 9 10 11 12–14 15 16 17

Name

— PAR DOZE — STOP DPM — NHR ICE DCE

Table 2-1. HID0 Field Descriptions (continued) Description

Reserved Disable precharge of ARTRY.

0 Precharge of ARTRY enabled 1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high (negated) state, allowing multiple ARTRY signals to be tied together. If this is done, the system must restore the signals to the high state. Doze mode enable. Operates in conjunction with MSR[POW]. 1 0 Doze mode disabled.

1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] after this bit is set. In doze mode, the PLL, time base, and snooping remain active.

Reserved, should be cleared.

Stop mode enable. Operates in conjunction with MSR[POW]. 1 0 Stop mode disabled.

1 Stop mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. When this occurs, the processor asserts QREQ to indicate that it is ready to enter sleep mode. The main MPC8280’s PLL remains active and all the internal clocks—including the core’s clock—stop. Dynamic power management enable. 1 0 Dynamic power management is disabled.

1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect operational performance and is transparent to software or any external hardware. Reserved Not hard reset (software-use only)—Helps software distinguish a hard reset from a soft reset. 0 A hard reset occurred if software had previously set this bit.

1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs and this bit remains set, software can tell it was a soft reset. Instruction cache enable 2 0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored and all accesses are propagated to the bus as single-beat transactions. For those transactions, however, CI reflects the original state determined by address translation regardless of cache disabled status. ICE is zero at power-up.

1 The instruction cache is enabled Data cache enable 2 0 The data cache is neither accessed nor updated. All pages are accessed as if they were marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored and all accesses are propagated to the bus as single-beat transactions. For those transactions, however, CI reflects the original state determined by address translation regardless of cache disabled status. DCE is zero at power-up.

1 The data cache is enabled.

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18 19 20 21 22–23 24 25–26 27 28

Table 2-1. HID0 Field Descriptions (continued) Name

ILOCK DLOCK ICFI DCFI — IFEM — FBIOB ABE

Description

Instruction cache lock 0 Normal operation 1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-beat, however, CI still reflects the original state as determined by address translation independent of cache locked or disabled status.

To prevent locking during a cache access, an

isync

must precede the setting of ILOCK.

Data cache lock 0 Normal operation 1 Data cache is locked. A locked cache supplies data normally on a hit but an access is treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-beat, however, CI still reflects the original state as determined by address translation independent of cache locked or disabled status. A snoop hit to a locked L1 data cache performs as if the cache were not locked. A cache block invalidated by a snoop remains invalid until the cache is unlocked. To prevent locking during a cache access, a

sync

must precede the setting of DLOCK.

Instruction cache flash invalidate 2 0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation begins (usually the next cycle after the write operation to the register). The instruction cache must be enabled for the invalidation to occur. 1 An invalidate operation is issued that marks the state of each instruction cache block as invalid without writing back modified cache blocks to memory. Cache access is blocked during this time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. Setting ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set. Once the L1 flash invalidate bits are set through an

mtspr

instruction, hardware automatically resets these bits in the next cycle (provided that the corresponding cache enable bits are set in HID0).

Data cache flash invalidate 2 0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins (usually the next cycle after the write operation to the register). The data cache must be enabled for the invalidation to occur. 1 An invalidate operation is issued that marks the state of each data cache block as invalid without writing back modified cache blocks to memory. Cache access is blocked during this time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. Setting DCFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set. Once the L1 flash invalidate bits are set through an

mtspr

instruction, hardware automatically resets these bits in the next cycle (provided that the corresponding cache enable bits are set in HID0).

Reserved Enable M bit on 60x bus for instruction fetches 0 M bit not reflected on 60x bus. Instruction fetches are treated as nonglobal on the bus.

1 Instruction fetches reflect the M bit from the WIM settings on the 60x bus. Reserved Force branch indirect on bus. 0 Register indirect branch targets are fetched normally 1 Forces register indirect branch targets to be fetched externally.

Address broadcast enable 0

dcbf

,

dcbi

, and

dcbst

instructions are not broadcast on the 60x bus. 1

dcbf

,

dcbi

, and

dcbst

generate address-only broadcast operations on the 60x bus.

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G2_LE Core Table 2-1. HID0 Field Descriptions (continued) Bits Name Description

29–30 — Reserved 31 NOOPTI No-op the data cache touch instructions.

0 The

dcbt

and

dcbtst

instructions are enabled. 1 The

dcbt

and

dcbtst

instructions are no-oped globally. 1 2 See Chapter 10, “Power Management , ” of the G2 Core Reference Manual for more information.

See Chapter 4, “Instruction and Data Cache Operation , ” of the G2 Core Reference Manual for more information.

2.3.1.2.2

Hardware Implementation-Dependent Register 1 (HID1)

The MPC8280 implementation of HID1 is shown in

Figure 2-4

.

0 PLLCFG 4 5 —

Figure 2-4. Hardware Implementation-Dependent Register 1 (HID1)

Table 2-2

shows the bit definitions for HID1.

Table 2-2. HID1 Field Descriptions Bits Name Function

0–4 5–31 PLLCFG PLL configuration setting. These bits reflect the state of the PLL_CFG[0:4] signals.

— Reserved 31

2.3.1.2.3

Hardware Implementation-Dependent Register 2 (HID2)

The processor core implements an additional hardware implementation-dependent register, shown in

Figure 2-5 .

0 — 12 13 14 HBE — 15 SFP 16 18 19 IWLCK — 23 24 26 27 DWLCK

Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)

— 31 2-14

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Table 2-3

describes the HID2 fields.

Table 2-3. HID2 Field Descriptions Bits Name Function

0–12 13 14 15 — HBE — SFP Reserved High BAT enable. Enables the four additional pairs of BAT registers (IBAT4–IBAT7 and DBAT4–DBAT7). These BATs are accessible by the

mfspr

and

mtspr

instructions regardless of the setting of HID2[HBE].

Reserved Speed for low power. Setting SFP reduces power consumption at the cost of reducing the maximum frequency, which benefits power-sensitive applications that are not frequency-critical.

16–18 19–23 27–31 IWLCK Instruction cache way lock. Useful for locking blocks of instructions into the instruction cache for time-critical applications that require deterministic behavior. See

Section 2.4.2.3, “Cache Locking .”

— 24–26 DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical applications where deterministic behavior is required. See

Section 2.4.2.3, “Cache Locking .”

— Reserved Reserved

2.3.1.2.4

Processor Version Register (PVR)

Software can identify the MPC8280’s processor core by reading the processor version register (PVR). The processor version number is 0x80822013.

2.3.2

PowerPC Instruction Set and Addressing Modes

All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction pipelining.

2.3.2.1

Calculating Effective Addresses

The effective address (EA) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. The PowerPC architecture supports two simple memory addressing modes: • • EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index) EA = (rA|0) + rB (register indirect with index) These simple addressing modes allow efficient address generation for memory accesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle.

For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the memory operand is considered to wrap around from the maximum effective address to effective address 0.

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Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.

In addition to the functionality of the MPC603e, the MPC8280 has additional hardware support for misaligned little-endian accesses. Except for string/multiple load and store instructions, little-endian load/store accesses not on a word boundary generate exceptions under the same circumstances as big-endian requests.

2.3.2.2

PowerPC Instruction Set

The PowerPC instructions are divided into the following categories: • • • • • Integer instructions—These include arithmetic and logical instructions. — Integer arithmetic — Integer compare — Integer logical — Integer rotate and shift Floating-point instructions—These include floating-point computational instructions, as well as instructions that affect the FPSCR.

— Floating-point arithmetic — Floating-point multiply/add — Floating-point rounding and conversion — Floating-point compare — Floating-point status and control Load/store instructions—These include integer and floating-point load and store instructions.

— Integer load and store — Integer load and store with byte reverse — Integer load and store string/multiple — Floating-point load and store Flow control instructions—These include branching instructions, condition register logical instructions, trap instructions, and other synchronizing instructions that affect the instruction flow.

— Branch and trap — Condition register logical — Primitives used to construct atomic memory operations (lwarx and stwcx.) — Synchronize Processor control instructions—These instructions are used for synchronizing memory accesses and management of caches, TLBs, and the segment registers. — Move to/from SPR — Move to/from MSR — Instruction synchronize 2-16

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• • Memory control instructions—These provide control of caches, TLBs, and segment registers.

— Supervisor-level cache management — User-level cache management — Segment register manipulation — TLB management The G2_LE core implements the following instructions, which are defined as optional by the PowerPC architecture: — External Control In Word Indexed (eciwx) — External Control Out Word Indexed (ecowx) — Floating Select (fsel) — Floating Reciprocal Estimate Single-Precision (fres) — Floating Reciprocal Square Root Estimate (frsqrte) — Store Floating-Point as Integer Word (stfiwx) Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. Integer instructions operate on byte, half-word, and word operands. The PowerPC architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs. Floating-point instructions operate on single-precision (one word) and double-precision (one double word) floating-point operands. It also provides for word and double-word operand loads and stores between memory and a set of 32 floating-point registers (FPRs).

Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and written back to the target location with separate instructions. Decoupling arithmetic instructions from memory accesses increases throughput by facilitating pipelining. Processors that implement the PowerPC architecture follow the program flow when they are in the normal execution state. However, the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. Either kind of exception may cause one of several components of the system software to be invoked.

2.3.2.3

MPC8280 Implementation-Specific Instruction Set

The G2_LE core instruction set is defined as follows: • • The core provides hardware support for all 32-bit PowerPC instructions.

The core provides the following two implementation-specific instructions used for software tablesearch operations following TLB misses: — Load Data TLB Entry (tlbld) — Load Instruction TLB Entry (tlbli) Freescale Semiconductor

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• The G2_LE implements the following instruction, which supports critical interrupts. This is a supervisor-level, context synchronizing instruction.

— Return from Critical Interrupt (rfci)

2.4

Cache Implementation

The MPC8280 processor core has separate data and instruction caches. The cache implementation is described in the following sections.

2.4.1

PowerPC Cache Model

The PowerPC architecture does not define hardware aspects of cache implementations. For example, some processors, including the MPC8280’s processor core, have separate instruction and data caches (Harvard architecture), while others implement a unified cache. Microprocessors that implement the PowerPC architecture control the following memory access modes on a page or block basis: • • • Write-back/write-through mode Caching-inhibited mode Memory coherency The PowerPC cache management instructions provide a means by which the application programmer can affect the cache contents.

2.4.2

MPC8280 Implementation-Specific Cache Implementation

As shown in Figure 2-1 , the caches provide a 64-bit interface to the instruction fetch unit and load/store

unit. The surrounding logic selects, organizes, and forwards the requested information to the requesting unit. Write operations to the cache can be performed on a byte basis, and a complete read-modify-write operation to the cache can occur in each cycle.

Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits A27–A31 of the effective addresses are zero); thus, a cache block never crosses a page boundary. Misaligned accesses across a page boundary can incur a performance penalty.

The cache blocks are loaded in to the processor core in four beats of 64 bits each. The burst load is performed as critical double word first. To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the processor core implements the MEI protocol. These three states, modified, exclusive, and invalid, indicate the state of the cache block as follows: • • • Modified—The cache block is modified with respect to system memory; that is, data for this address is valid only in the cache and not in system memory.

Exclusive—This cache block holds valid data that is identical to the data at this address in system memory. No other cache has this data.

Invalid—This cache block does not hold valid data.

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Data Cache

As shown in

Figure 2-6

, the data cache is configured as 128 sets of four blocks each. Each block consists of 32 bytes, two state bits, and an address tag. The two state bits implement the three-state MEI (modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC architecture defines the term ‘block’ as a cacheable unit. For the MPC8280’s processor core, the block size is equivalent to a cache line.

128 Sets Block 0 Block 1 Block 2 Block 3 Address Tag 0 Address Tag 1 Address Tag 2 Address Tag 3 State State State State Words 0–7 Words 0–7 Words 0–7 Words 0–7 8 Words/Block

Figure 2-6. Data Cache Organization

Because the processor core data cache tags are single-ported, simultaneous load or store and snoop accesses cause resource contention. Snoop accesses have the highest priority and are given first access to the tags, unless the snoop access coincides with a tag write, in which case the snoop is retried and must rearbitrate for access to the cache. Loads or stores that are deferred due to snoop accesses are executed on the clock cycle following the snoop.

Because the caches on the processor core are write-back caches, the predominant type of transaction for most applications is burst-read memory operations, followed by burst-write memory operations, and single-beat (noncacheable or write-through) memory read and write operations. When a cache block is filled with a burst read, the critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays.

Additionally, there can be address-only operations, variants of the burst and single-beat operations, (for example, global memory operations that are snooped and atomic memory operations), and address retry activity (for example, when a snooped read access hits a modified line in the cache).

Setting HID0[ABE] causes execution of the dcbf, dcbi, and dcbst instructions to be broadcast onto the 60x bus. The value of ABE does not affect dcbz instructions, which are always broadcast and snooped. The cache operations are intended primarily for managing on-chip caches. However, the optional broadcast feature is necessary to allow proper management of a system using an external copyback L2 cache.

The address and data buses operate independently to support pipelining and split transactions during memory accesses. The processor core pipelines its own transactions to a depth of one level.

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Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of the internal bus without sacrificing coherency of the data. The processor core allows pending read operations to precede previous store operations (except when a dependency exists, or in cases where a non-cacheable access is performed), and provides support for a write operation to precede a previously queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data tenures of a read operation). Because the processor can dynamically optimize run-time ordering of load/store traffic, overall performance is improved.

2.4.2.2

Instruction Cache

The instruction cache also consists of 128 sets of four blocks, and each block consists of 32 bytes, an address tag, and a valid bit. The instruction cache may not be written to except through a block fill operation caused by a cache miss. In the processor core, internal access to the instruction cache is blocked only until the critical load completes. The processor core supports instruction fetching from other instruction cache lines following the forwarding of the critical first double word of a cache line load operation. The processor core’s instruction cache is blocked only until the critical load completes (hits under reloads are allowed). Successive instruction fetches from the cache line being loaded are forwarded, and accesses to other instruction cache lines can proceed during the cache line load operation. The instruction cache is not snooped, and cache coherency must be maintained by software. A fast hardware invalidation capability is provided to support cache maintenance. The organization of the

instruction cache is very similar to the data cache shown in Figure 2-6 .

2.4.2.3

Cache Locking

The processor core supports cache locking, which is the ability to prevent some or all of a microprocessor’s instruction or data cache from being overwritten. Cache entries can be locked for either an entire cache or for individual ways within the cache. Entire data cache locking is enabled by setting HID0[DLOCK], and entire instruction cache locking is enabled by setting HID0[ILOCK]. For more information, refer to the application note Cache Locking on the G2 Core (order number: AN1767). Cache way locking is controlled by the IWLCK and DWLCK bits of HID2.

2.4.2.3.1

Entire Cache Locking

When an entire cache is locked, hits within the cache are supplied in the same manner as hits to an unlocked cache. Any access that misses in the cache is treated as a cache-inhibited access. Cache entries that are invalid at the time of locking will remain invalid and inaccessible until the cache is unlocked. Once the cache has been unlocked, all entries (including invalid entries) are available. Entire cache locking is inefficient if the number of instructions or the size of data to be locked is small compared to the cache size.

2.4.2.3.2

Way Locking

Locking only a portion of the cache is accomplished by locking ways within the cache. Locking always begins with the first way (way0) and is sequential, that is, it is valid to lock ways 0, 1, and 2 but it is not 2-20

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possible to lock just way0 and way2. When using way locking at least one way must be left unlocked. The maximum number of lockable ways is three.

Unlike entire cache locking, invalid entries in a locked way are accessible and available for data placement. As hits to the cache fill invalid entries within a locked way, the entries become valid and locked. This behavior differs from entire cache locking, where nothing is placed in the cache, even if invalid entries exist in the cache. Unlocked ways of the cache behave normally.

2.5

Exception Model

This section describes the PowerPC exception model and implementation-specific details of the MPC8280 core.

2.5.1

PowerPC Exception Model

The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor mode. Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception—for example, the DSISR identifies instructions that cause a DSI exception. Additionally, some exception conditions can be explicitly enabled or disabled by software.

The PowerPC architecture requires that exceptions be handled in program order; therefore, although a particular implementation may recognize exception conditions out of order, exceptions are taken in strict order. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute stage, are required to complete before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in the completion stage successfully completes execution or generates an exception, and the completed store queue is emptied. Unless a catastrophic condition causes a system reset or machine check exception, only one exception is handled at a time. If, for example, a single instruction encounters multiple exception conditions, those conditions are handled sequentially. After the exception handler handles an exception, the instruction execution continues until the next exception condition is encountered. However, in many cases there is no attempt to re-execute the instruction. This method of recognizing and handling exception conditions sequentially guarantees that exceptions are recoverable.

Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state from being lost due to a system reset or machine check exception or to an instruction-caused exception in the exception handler. SRR0 and SRR1 should also be saved before enabling external interrupts.

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The PowerPC architecture supports four types of exceptions: • • • • Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are handled precisely; that is, the machine state at the time the exception occurs is known and can be completely restored. This means that (excluding the trap and system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the faulting instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. Once the exception is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception handler). When an exception is taken due to a trap or system call instruction, execution resumes at an address provided by the handler.

Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point exception modes: recoverable and nonrecoverable. Even though the G2_LE core provides a means to enable the imprecise modes, it implements these modes identically to the precise mode (that is, all enabled floating-point enabled exceptions are always precise on the core).

Asynchronous, maskable—The external, system management interrupt (SMI), and decrementer interrupts are maskable asynchronous exceptions. When these exceptions occur, their handling is postponed until the next instruction and any exceptions associated with that instruction complete execution. If no instructions are in the execution units, the exception is taken immediately upon determination of the correct restart address (for loading SRR0).

Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions: system reset and the machine check exception. These exceptions may not be recoverable, or may provide a limited degree of recoverability. All exceptions report recoverability through MSR[RI].

2.5.2

Implementation-Specific Exception Model

As specified by the PowerPC architecture, all processor core exceptions can be described as either precise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of which are maskable) are caused by events external to the processor’s execution. Synchronous exceptions, which are all handled precisely by the processor core, are caused by instructions. The processor core exception classes are shown in

Table 2-4 .

Table 2-4. Exception Classifications for the Processor Core Synchronous/Asynchronous

Asynchronous, nonmaskable Asynchronous, maskable Synchronous

Precise/Imprecise

Imprecise Precise Precise

Exception Type

Machine check System reset External interrupt Decrementer System management interrupt Critical interrupt Instruction-caused exceptions Although exceptions have other characteristics as well, such as whether they are maskable or nonmaskable, the distinctions shown in

Table 2-4

define categories of exceptions that the processor core

handles uniquely. Note that Table 2-4

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The processor core’s exceptions, and conditions that cause them, are listed in

Table 2-5 .

Table 2-5. Exceptions and Conditions Exception Type Vector Offset (hex)

Reserved 00000 System reset 00100 Machine check 00200 DSI ISI External interrupt Alignment 00300 00400 00500 00600

Causing Conditions

— A system reset is caused by the assertion of either SRESET or HRESET. Note that the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core Reference Manual, is determined by the CIP bit in the hard reset configuration word.

This is described in Section 5.4.1, “Hard Reset Configuration Word

.” A machine check is caused by the assertion of the TEA signal during a data bus transaction, assertion of MCP, or an address or data parity error. The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as follows: 1 Set if the translation of an attempted access is not found in the primary hash table 4 entry group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT register; otherwise cleared. Set if a memory access is not permitted by the page or DBAT protection mechanism; otherwise cleared. 5 Set by an

eciwx

or

ecowx

instruction if the access is to an address that is marked as write-through, or execution of a load/store instruction that accesses a 6 direct-store segment.

Set for a store operation and cleared for a load operation. 11 Set if

eciwx

or

ecowx

is used and EAR[E] is cleared.

An ISI exception is caused when an instruction fetch cannot be performed for any of the following reasons: • The effective (logical) address cannot be translated. That is, there is a page fault for this portion of the translation, so an ISI exception must be taken to load the PTE (and possibly the page) into memory.

• The fetch access is to a direct-store segment (indicated by SRR1[3] set).

• The fetch access violates memory protection (indicated by SRR1[4] set). If the key bits (Ks and Kp) in the segment register and the PP bits in the PTE are set to prohibit read access, instructions cannot be fetched from this location.

An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.

An alignment exception is caused when the processor core cannot perform a memory access for any of the reasons described below: • The operand of a floating-point load or store is to a direct-store segment.

• The operand of a floating-point load or store is not word-aligned.

• The operand of a

lmw

,

stmw

,

lwarx

, or

stwcx.

is not word-aligned.

• The operand of an elementary, multiple or string load or store crosses a segment boundary with a change to the direct store T bit.

• The operand of

dcbz

instruction is in memory that is write-through required or caching inhibited, or

dcbz

is executed in an implementation that has either no data cache or a write-through data cache.

• A misaligned

eciwx

or

ecowx

instruction • A multiple or string access with MSR[LE] set The processor core differs from MPC603e User’s Manual in that it initiates an alignment exception when it detects a misaligned

eciwx

or

ecowx

instruction and does not initiate an alignment exception when a little-endian access is misaligned.

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G2_LE Core Table 2-5. Exceptions and Conditions (continued) Exception Type Vector Offset (hex) Causing Conditions

Program Floating-point unavailable Decrementer 00700 00800 00900 A program exception is caused by one of the following exception conditions, which correspond to bit settings in SRR1 and arise during execution of an instruction: • Illegal instruction—An illegal instruction program exception is generated when execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode fields (including PowerPC instructions not implemented in the processor core), or when execution of an optional instruction not provided in the processor core is attempted (these do not include those optional instructions that are treated as no-ops). • Privileged instruction—A privileged instruction type program exception is generated when the execution of a privileged instruction is attempted and the MSR register user privilege bit, MSR[PR], is set. In the processor core, this exception is generated for

mtspr

or

mfspr

with an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all processors that implement the PowerPC architecture.

• Trap—A trap type program exception is generated when any of the conditions specified in a trap instruction is met. A floating-point unavailable exception is caused by an attempt to execute a floating-point instruction (including floating-point load, store, and move instructions) when the floating-point available bit is cleared (MSR[FP] = 0).

The decrementer exception occurs when the most significant bit of the decrementer (DEC) register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.

A critical interrupt is caused when MSR[CE] = 1 and the CINT signal is asserted.

Critical interrupt Reserved System call Trace Floating-point assist Reserved Instruction translation miss Data load translation miss Data store translation miss Instruction address breakpoint 00A00 00B00–00BFF — 00C00 A system call exception occurs when a System Call (

sc

) instruction is executed. 00D00 00E00 A trace exception is taken when MSR[SE] = 1 or when the currently completing instruction is a branch and MSR[BE] = 1.

Not implemented.

00E10–00FFF — 01000 An instruction translation miss exception is caused when the effective address for an instruction fetch cannot be translated by the ITLB.

01100 01200 01300 A data load translation miss exception is caused when the effective address for a data load operation cannot be translated by the DTLB.

A data store translation miss exception is caused when the effective address for a data store operation cannot be translated by the DTLB, or when a DTLB hit occurs, and the changed bit in the PTE must be set due to a data store operation.

An instruction address breakpoint exception occurs when the address (bits 0–29) in the IABR matches the next instruction to complete in the completion unit, and the IABR enable bit (bit 30) is set. 2-24

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G2_LE Core Table 2-5. Exceptions and Conditions (continued) Exception Type

System management interrupt Reserved

Vector Offset (hex)

01400 signal is asserted.

01500–02FFF —

Causing Conditions

A system management interrupt is caused when MSR[EE] = 1 and the SMI input

2.6

Memory Management

The following subsections describe the memory management unit (MMU) features of the PowerPC architecture and the G2_LE implementation.

2.6.1

PowerPC Memory Management

The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for memory accesses and to provide access protection on blocks and pages of memory.

The core generates two types of accesses that require address translation: instruction accesses and data accesses to memory generated by load and store instructions.

The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory management permits execution of programs larger than the size of physical memory; demand-paged memory implies that individual pages are loaded into physical memory from system memory only when they are first accessed by an executing program.

The hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page numbers. The page table size is a power of two, and its starting address is a multiple of its size.

The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of 8 bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search operations.

Address translations are enabled by setting bits in the MSR. MSR[IR] enables instruction address translations, and MSR[DR] enables data address translations.

2.6.2

Implementation-Specific MMU Features

The instruction and data memory management units in the G2_LE core provide 4 Gbytes of logical address space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size. Block sizes range from 128 Kbytes to 256 Mbytes and are software selectable. In addition, the core uses an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses. The MMUs in the G2_LE core rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas.

Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most recently used page table Freescale Semiconductor

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G2_LE Core

entries. Software is responsible for maintaining the consistency of the TLB with memory. The core TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The core provides hardware assist for software table search operations through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.

For instructions and data that maintain address translations for blocks of memory, the G2_LE core provides independent eight-entry BAT arrays. These entries define blocks that can vary from 128 Kbytes to 256 Mbytes. The BAT arrays are maintained by system software. Adding the HID2[HBE] to the G2_LE enables or disables the four additional pairs of BAT registers. However, regardless of the setting of HID2[HBE], these BATs are accessible by mfspr and mtspr.

As specified by the PowerPC architecture, the hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page numbers. The page table size is a power of two, and its starting address is a multiple of its size.

As specified by the PowerPC architecture, the page table contains a number of PTEGs. A PTEG contains eight PTEs of 8 bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search operations.

2.7

Instruction Timing

The G_LE2 core is a pipelined superscalar processor core. Because instruction processing is reduced into a series of stages, an instruction does not require all of the resources of an execution unit at the same time. For example, after an instruction completes the decode stage, it can pass on to the next stage, while the subsequent instruction can advance into the decode stage. This improves the throughput of the instruction flow. For example, it may take three cycles for a single floating-point instruction to execute, but if there are no stalls in the floating-point pipeline, a series of floating-point instructions can have a throughput of one instruction per cycle.

The core instruction pipeline has four major pipeline stages, described as follows: • • • The fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction fetch. Additionally, if possible, the BPU decodes branches during the fetch stage and folds out branch instructions before the dispatch stage.

The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determining which of the instructions are eligible to be dispatched in the current cycle. In addition, the source operands of the instructions are read from the appropriate register file and dispatched with the instruction to the execute pipeline stage. At the end of the dispatch pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit.

In the execute pipeline stage, each execution unit with an executable instruction executes the selected instruction (perhaps over multiple cycles), writes the instruction's result into the appropriate rename register, and notifies the completion stage when the execution has finished. In the case of an internal exception, the execution unit reports the exception to the completion/write-back pipeline stage and discontinues instruction execution until the exception is handled. The exception is not signaled until that instruction is the next to be completed. Execution of most floating-point instructions is pipelined within the FPU allowing up to three instructions to be executing in the FPU concurrently. The FPU pipeline stages are multiply, add, and 2-26

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G2_LE Core

• round-convert. The LSU has two pipeline stages. The first stage is for effective address calculation and MMU translation, and the second is for accessing data in the cache.

The complete/write-back pipeline stage maintains the correct architectural machine state and transfers the contents of the rename registers to the GPRs and FPRs as instructions are retired. If the completion logic detects an instruction causing an exception, all following instructions are canceled, their execution results in rename registers are discarded, and instructions are fetched from the correct instruction stream.

A superscalar processor core issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel. The G2_LE core has five independent execution units, one each for integer instructions, floating-point instructions, branch instructions, load/store instructions, and system register instructions. The IU and the FPU each have dedicated register files for maintaining operands (GPRs and FPRs, respectively), allowing integer and floating-point calculations to occur simultaneously without interference. Integer division performance of the G2_LE core has been improved, with the divwux and divwx instructions executing in 20 clock cycles instead of the 37 cycles required in the MPC603e.

The core provides support for single-cycle store and an adder/comparator in the system register unit that allows the dispatch and execution of multiple integer add and compare instructions on each cycle. Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction timing among processor cores varies accordingly.

2.8

Differences Between the MPC8280 G2_LE Embedded Core and the MPC603e

The G2_LE processor core is a derivative of the MPC603e microprocessor design. Some changes have been made and are visible either to a programmer or a system designer. Any software designed around an MPC603e is functional when replaced with the G2_LE except for the specific customer-visible changes listed in

Table 2-6

.

Software can distinguish between the MPC603e and the G2_LE by reading the processor version register (PVR). The G2_LE processor version number is 0x0081; the processor revision level starts at 0x0100 and is incremented for each revision of the chip.

Table 2-6. Differences Between G2_LE Core and MPC603e Description Impact

An additional input interrupt signal, CINT, implements a critical interrupt function. MSR[CE] is allocated for enabling the critical interrupt A new instruction is implemented for critical interrupt Vector offset for critical interrupt Two new registers are implemented for saving processor state for critical interrupts Return from Critical Interrupt ( handlers respectively.

rfci

) is implemented to return from these exception An exception vector offset of 0x00A00 is defined for critical interrupt CSRR0 and CSRR1 have the same bit assignments as SRR0 and SRR1, Freescale Semiconductor

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G2_LE Core Table 2-6. Differences Between G2_LE Core and MPC603e (continued) Description Impact

Supports instruction and data cache way-locking in addition to entire instruction and data cache locking Implements a cache way locking mechanism for both the instruction and data caches. One to three of the four ways in the cache can be locked with control bits in the HID2 register. See

Section 2.3.1.2.3, “Hardware Implementation-Dependent Register 2 (HID2).”

Four additional SPRG registers One new address breakpoint register IABR2 Two new data address breakpoint registers are implemented in the G2_LE One instruction register and one data breakpoint control register are implemented The additional SPRGs reduce latencies that may be incurred from saving registers to memory while in an exception handler Instruction address breakpoint exceptions in both the MPC603e and the G2_LE cores use the 0x01300 vector offset The two new data address breakpoint registers (DABR and DABR2) expand the debug functionality of the breakpoints. The new breakpoint registers are accessible as SPRs with

mtspr

and

mfspr

.

IBCR and DBCR are implemented to support the additional debug features. These registers are accessible as SPRs with

mtspr

and

mfspr

.

Vector offset for data address breakpoint exception is 0x00300 Data address breakpoint exception is a DSI exception. The cause of a DSI exception can be determined by the bit settings of DSISR[9]. DAR contains the address of the breakpoint match condition.

One new register is implemented for supporting system level memory map The G2_LE has eight pairs of data and eight pairs of instruction BAT registers System memory base address register (MBAR) can be accessed with address for the system memory map.

mtspr

or

mfspr

using SPR311 in supervisor mode. It can store the present memory base IBAT4–IBAT7 are the four additional pairs of instruction BATs and DBAT4–DBAT7 are the four additional data BATs. HID2[HBE] is added for enabling or disabling the four additional pairs of BAT registers. These BATs are accessible by the

mfspr

and

mtspr

instructions regardless of the setting of HID2[HBE].

Added hardware support for misaligned little endian accesses Except for strings/multiples, little-endian load/store accesses not on a word boundary generate exceptions under the same circumstances as big-endian accesses.

Removed misalignment support for

eciwx

and

ecowx

instructions These instructions take an alignment exception if not on a word boundary.

Added ability to broadcast

dcbf

,

dcbi

, and

dcbst

onto the 60x bus Setting HID0[ABE] enables the new broadcast feature (new in the PID7v-603e). The default is to not broadcast these operations.

Added ability to reflect the value of the M bit onto the 60x bus during instruction translations Setting HID0[IFEM] enables this feature. The default is to not present the M bit on the bus.

Removed HID0[EICE] Added pin-configurable reset vector Addition of speed-for-power functionality There is no support for ICE pipeline tracking.

The value of MSR[IP], interrupt prefix, is determined at hard reset by the hardware configuration word. The processor core implements an additional dynamic power management mechanism. HID2[SFP] controls this function. See

Section 2.3.1.2.3, “Hardware Implementation-Dependent Register 2 (HID2).”

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Chapter 3 Memory Map

The MPC8280’s internal memory resources are mapped within a contiguous block of memory. The size of the internal space is 256 Kbytes. The location of this block within the global 4-Gbyte real memory space can be mapped on 256-Kbytes resolution through an implementation-specific special register called the

internal memory map register (IMMR). For more information, see Section 4.3.2.7, “Internal Memory Map Register (IMMR).”

Figure 3-1 shows the internal memory resources.

DPRAM1 16 Kbytes Global memory1 0 1 Gbyte 2 Gbyte 3 Gbyte 4 Gbyte 0x0_0000 Dual-Port RAM 0x1_0000 0x2_0000 (see note 2) IRAM 32 Kbytes 0x3_0000 0x4_0000 The location of the 256-Kbyte block of internal memory within global memory is selected according to the internal memory map register (IMMR). Internal memory must be mapped on 256-Kbyte resolution. 1 Location of internal memory resources in this figure is for illustration only.

2 The right vertical column is for illustration only. For a complete list of modules and registers, refer to

Table 3-1 .

Figure 3-1. Internal Memory

DPRAM2 16 Kbytes SIU Memory controller PCI Interrupt controller Clocks/Reset I/O ports CPM CPM interface Serial interface Freescale Semiconductor

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3-1

Memory Map

3.1

Internal Memory Map

Table 3-1

defines the internal memory map of the MPC8280.

Table 3-1. Internal Memory Map Address (offset) Register R/W Size Reset Section/Page CPM Dual-Port RAM (Data)

0x00000– 0x03FFF Dual-port RAM (DPRAM1) 0x04000– 0x07FFF Reserved 0x08000– 0x0BFFF Dual-port RAM (DPRAM2) 0x0C000– 0x0FFFF Reserved 0x10000 SIU module configuration register (SIUMCR)

General SIU

R/W — R/W — 0x10004 0x10008 0x1000E 0x10010– 0x10023 System protection control register (SYPCR) Reserved Software service register (SWSR) Reserved 0x10024 Bus configuration register (BCR) R/W 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes R/W 32 bits R/W — W — 32 bits 6 bytes 16 bits 20 bytes see

Figure 4-28

0xFFFF_FF07 — undefined — 32 bits — — — — 0x10028 60x bus arbiter configuration register (PPC_ACR) R/W — R/W 8 bits 24 bits 32 bits reset configuration see

Figure 4-22

— 0x0126_3457 0x10029 Reserved 0x1002C 60x bus arbitration-level register high (first 8 clients) (PPC_ALRH) 0x10030 60x bus arbitration-level register low (next 8 clients) (PPC_ALRL) 0x10034 Local arbiter configuration register (LCL_ACR) 0x10035 Reserved 0x10038 Local arbitration-level register (first 8 clients) (LCL_ALRH) 0x1003C Local arbitration-level register (next 8 clients) (LCL_ALRL) 0x10040 0x10044 60x bus transfer error status control register 1 (TESCR1) 60x bus transfer error status control register 2 (TESCR2) R/W R/W — R/W R/W R/W R/W 32 bits 8 bits 24 bits 32 bits 32 bits 32 bits 32 bits 0x89AB_CDEF 0x02 — 0x0126_3457 0x89AB_ CDEF 0x0000_0000 0x0000_0000

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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register Memory Controller R/W

0x10048 Local bus transfer error status control register 1 (L_TESCR1) R/W 0x1004C Local bus transfer error status control register 2 (L_TESCR2) R/W 0x10050 60x bus DMA transfer error address (PDTEA) 0x10054 60x bus DMA transfer error MSNUM (PDTEM) 0x10055 0x10058 Reserved Local bus DMA transfer error address (LDTEA) R R — R 0x1005C Local bus DMA transfer error MSNUM (LDTEM) 0x1005D– 0x100FF Reserved R — 0x10100 Base register bank 0 (BR0) R/W

Size

32 bits 32 bits 32 bits 8 bits 24 bits 32 bits 8 bits 163 bytes 32 bits 0x10104 Option register bank 0 (OR0) 0x10108 Base register bank 1 (BR1) 0x1010C Option register bank 1 (OR1) 0x10110 Base register bank 2 (BR2) 0x10114 Option register bank 2 (OR2) 0x10118 Base register bank 3 (BR3) 0x1011C Option register bank 3 (OR3) 0x10120 Base register bank 4 (BR4) 0x10124 Option register bank 4 (OR4) 0x10128 Base register bank 5 (BR5) 0x1012C Option register bank 5 (OR5) 0x10130 Base register bank 6 (BR6) 0x10134 Option register bank 6 (OR6) 0x10138 Base register bank 7 (BR7) 0x1013C Option register bank 7 (OR7) 0x10140 Base register bank 8 (BR8) 0x10144 Option register bank 8 (OR8) 0x10148 Base register bank 9 (BR9) 0x1014C Option register bank 9 (OR9) 0x10150 Base register bank 10 (BR10) 0x10154 Option register bank 10 (OR10)

Reset Section/Page

0x0000_0000 0x0000_0000 undefined undefined — undefined undefined —

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— R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits see

Figure 11-6

0xFE00_0EF4 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined 0x0000_0000 undefined

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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x10158 Base register bank 11 (BR11) 0x1015C Option register bank 11 (OR11) 0x10160 Reserved 0x10168 Memory address register (MAR) 0x1016C Reserved 0x10170 Machine A mode register (MAMR) 0x10174 Machine B mode register (MBMR) 0x10178 Machine C mode register (MCMR) 0x1017C Reserved 0x10184 Memory periodic timer prescaler (MPTPR) 0x10188 Memory data register (MDR) 0x1018C Reserved 0x10190 60x bus SDRAM mode register (PSDMR) 0x10194 Local bus SDRAM mode register (LSDMR) 0x10198 60x bus-assigned UPM refresh timer (PURT) 0x10199 Reserved 0x1019C 60x bus-assigned SDRAM refresh timer (PSRT) 0x1019D Reserved 0x101A0 Local bus-assigned UPM refresh timer (LURT) 0x101A1 Reserved 0x101A4 Local bus-assigned SDRAM refresh timer (LSRT) 0x101A5 Reserved 0x101A8 Internal memory map register (IMMR)

R/W Size

0x101AC PCI base register 0 (PCIBR0) 0x101B0 PCI base register 1 (PCIBR1) 0x101B4– 0x101C3 Reserved 0x101C4 PCI mask register 0 (PCIMSK0) 0x101C8 PCI mask register 1 (PCIMSK1) 0x101CC – 0x101FF Reserved

Reset

— R/W — R/W — R/W R/W R/W — R/W — R/W R/W R/W — R/W R/W — R/W R/W R/W — R/W 32 bits 32 bits 32 bits 32 bits 32 bits 48 bits 16 bits 32 bits 32 bits 32 bits 32 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 32 bits 32 bits 32 bits R/W R/W — 32 bits 32 bits 16 bytes 0x0000_0000 undefined — undefined — 0x0004_0000 0x0004_0000 0x0004_0000 — undefined undefined — 0x0000_0000 0x0000_0000 0x00 — 0x00 — 0x00 — 0x00 — reset configuration 0x0000_0000 0x0000_0000 —

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— R/W R/W — 32 bits 32 bits 52 bytes 0x0000_0000 0x0000_0000 —

Section/Page

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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page

0x10200– 0x10 21F Reserved 0x10224 Time counter register (TMCNT) 0x10228 Reserved

System Integration Timers

— 0x10220 Time counter status and control register (TMCNTSC) 0x1022C Time counter alarm register (TMCNTAL) 0x10230– 0x1023F Reserved 0x10240 Periodic interrupt status and control register (PISCR) 0x10244 Periodic interrupt count register (PITC) 0x10248 Periodic interrupt timer register (PITR) 0x1024C– 0x102A8 Reserved 0x102AA– 0x1042F Reserved R/W R/W — R/W — 16 bits 32 bits 32 bits 32 bits 16 bytes R/W R/W R — — 32 bytes 16 bits 32 bits 32 bits 92 bytes 372 bytes — 0x0000 0x0000_0000 — 0x0000_0000 — 0x0000 0x0000_0000 0x0000_0000 — —

PCI

0x10430 Outbound interrupt status register (OMISR) 0x10434 Outbound interrupt mask register (OMIMR) 0x10440 Inbound FIFO queue port register (IFQPR) 0x10444 Outbound FIFO queue port register (OFQPR) 0x10450 Inbound message register 0 (IMR0) 0x10454 Inbound message register 1 (IMR1) 0x10458 Outbound message register 0 (OMR0) 0x1045C Outbound message register 1 (OMR1) 0x10460 Outbound doorbell register (ODR) 0x10468 Inbound doorbell register (IDR) 0x10480 Inbound message interrupt status register (IMISR) 0x10484 Inbound message interrupt mask register (IMIMR) 0x104A0 Inbound free_FIFO head pointer register (IFHPR) 0x104A8 Inbound free_FIFO tail pointer register (IFTPR) 0x104B0 Inbound post_FIFO head pointer register (IPHPR) 0x104B8 Inbound post_FIFO tail pointer register (IPTPR) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits —

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— — 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 undefined undefined undefined undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000

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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x104C0 Outbound free_FIFO head pointer register (OFHPR) 0x104C8 Outbound free_FIFO tail pointer register (OFTPR) 0x104D0 Outbound post_FIFO head pointer register (OPHPR) 0x104D8 Outbound post_FIFO tail pointer register (OPTPR) 0x104E4 Message unit control register (MUCR) 0x104F0 Queue base address register (QBAR) 0x10500 DMA 0 mode register (DMAMR0) 0x10504 DMA 0 status register (DMASR0) 0x10508 DMA 0 current descriptor address register (DMACDAR0) 0x10510 DMA 0 source address register (DMASAR0) 0x10518 DMA 0 destination address register (DMADAR0) 0x10520 DMA 0 byte count register (DMABCR0) 0x10524 DMA 0 next descriptor address register (DMANDAR0) 0x10580 DMA 1 mode register (DMAMR1) 0x10584 DMA 1 status register (DMASR1) 0x10588 DMA 1 current descriptor address register (DMACDAR1) 0x10590 DMA 1 source address register (DMASAR1) 0x10598 DMA 1 destination address register (DMADAR1) 0x105A0 DMA 1 byte count register (DMABCR1) 0x105A4 DMA 1 next descriptor address register (DMANDAR1) 0x10600 DMA 2 mode register (DMAMR2) 0x10604 DMA 2 status register (DMASR2) 0x10608 DMA 2 current descriptor address register (DMACDAR2) 0x10610 DMA 2 source address register (DMASAR2) 0x10618 DMA 2 destination address register (DAR2) 0x10620 DMA 2 byte count register (DMABCR2) 0x10624 DMA 2 next descriptor address register (DMANDAR2) 0x10680 DMA 3 mode register (DMAMR3) 0x10684 DMA 3 status register (DMASR3) 0x10688 DMA 3 current descriptor address register (DMACDAR3) 0x10690 DMA 3 source address register (DMASAR3) 0x10698 DMA 3 destination address register (DMADAR3)

R/W Size

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits

Reset Section/Page

0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0002 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000

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0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000

9.13.1.6.5/9-94 9.13.1.6.6/9-94

9.13.1.6.7/9-95

9.13.1.6.1/9-89

9.13.1.6.2/9-91

9.13.1.6.3/9-92

9.13.1.6.4/9-93

9.13.1.6.5/9-94 9.13.1.6.6/9-94

9.13.1.6.7/9-95

9.13.1.6.1/9-89

9.13.1.6.2/9-91

9.13.1.6.3/9-92

9.13.1.6.4/9-93

9.13.1.6.5/9-94

3-6

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W

0x106A0 0x106A4 0x10800 0x10808 0x10810 0x10818 0x10820 0x10828 0x10830 0x10838 0x10840 0x10878 0x1087C 0x10880 0x10884 0x10888 0x1088C DMA 3 byte count register (DMABCR3) DMA 3 next descriptor address register (DMANDAR3) PCI outbound translation address register 0 (POTAR0) PCI outbound base address register 0 (POBAR0) PCI outbound comparison mask register 0 (POCMR0) PCI outbound translation address register 1 (POTAR1) PCI outbound base address register 1 (POBAR1) PCI outbound comparison mask register 1 (POCMR1) PCI outbound translation address register 2 (POTAR2) PCI outbound base address register 2 (POBAR2) PCI outbound comparison mask register 2 (POCMR2) Discard timer control register (PTCR) General purpose control register (GPCR) PCI general control register (PCI_GCR) Error status register (ESR) Error mask register (EMR) Error control register (ECR) 0x10890 0x10898 0x108A0 0x108D0 0x108D8 0x108E0 PCI error address capture register (PCI_EACR) PCI error data capture register (PCI_EDCR) PCI error control capture register (PCI_ECCR) PCI inbound translation address register 1 (PITAR1) PCI inbound base address register 1 (PIBAR1) PCI inbound comparison mask register 1 (PICMR1) 0x108E8 PCI inbound translation address register 0 (PITAR0) 0x108F0 PCI inbound base address register 0 (PIBAR0) 0x108F8 0x10900 PCI inbound comparison mask register 0 (PICMR0) PCI CFG_ADDR 0x10904 PCI CFG_DATA 0x10908 PCI INT_AC R/W R/W R/W R/W

Interrupt Controller

0x10C00 SIU interrupt configuration register (SICR) 0x10C02 Reserved R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Size

32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 16 bits 16 bits

Reset

0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0FFF 0x0000_00FF

9.13.1.6.6/9-94

9.13.1.6.7/9-95

9.11.1.3/9-30

9.11.1.4/9-31

9.11.1.5/9-32

9.11.1.3/9-30

9.11.1.4/9-31

9.11.1.5/9-32

9.11.1.3/9-30

9.11.1.4/9-31

9.11.1.5/9-32

9.11.1.6/9-33 9.11.1.7/9-33

9.11.1.8/9-35 9.11.1.9/9-35

9.11.1.10/9-37

9.11.1.11/9-38

0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 undefined 0x0000_0000 undefined

9.11.1.12/9-39

9.11.1.13/9-40 9.11.1.14/9-40

9.11.1.15/9-42 9.11.1.16/9-42

9.11.1.17/9-43

9.11.1.15/9-42 9.11.1.16/9-42

9.11.1.17/9-43

9.9.1.4.4/9-15 9.9.1.4.4/9-15

9.9.1.4.7/9-17

0x0000 —

Section/Page

4.3.1.1/4-17

— Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-7

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x10C04 SIU interrupt vector register (SIVEC) 0x10C08 SIU interrupt pending register (high) (SIPNR_H) 0x10C0C SIU interrupt pending register (low) (SIPNR_L) 0x10C10 SIU interrupt priority register (SIPRR) 0x10C14 CPM interrupt priority register (high) (SCPRR_H) 0x10C18 CPM interrupt priority register (low) (SCPRR_L) 0x10C1C SIU interrupt mask register (high) (SIMR_H) 0x10C20 SIU interrupt mask register (low) (SIMR_L) 0x10C24 SIU external interrupt control register (SIEXR) 0x10C28– 0x10C7F Reserved

Clocks and Reset R/W Size Reset

R/W R/W R/W R/W R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits R/W — 32 bits 88 bytes 0x0000_0000 undefined 0x0000_0000 0x0530_9770 0x0530_9770 0x0530_9770 0x0000_0000 0x0000_0000 0x0000_0000 — 0x10C80 System clock control register (SCCR) 0x10C88 0x10C90 0x10C94 0x10C98– 0x10CFF System clock mode register (SCMR) Reset status register (RSR) Reset mode register (RMR) Reserved R/W R R/W R/W — 32 bits see

Table 10-2

32 bits 32 bits 32 bits 104 bytes see

Table 10-3

0x0000_0003 0x0000_0000 —

Input/Output Port Section/Page

4.3.1.6/4-24

4.3.1.4/4-21 4.3.1.4/4-21

4.3.1.2/4-18

4.3.1.3/4-19 4.3.1.3/4-19

4.3.1.5/4-22 4.3.1.5/4-22

4.3.1.7/4-25

10.4/10-6

10.5/10-7

5.2/5-4

5.3/5-5

— 0x10D00 Port A data direction register (PDIRA) 0x10D04 Port A pin assignment register (PPARA) 0x10D08 Port A special options register (PSORA) 0x10D0C Port A open drain register (PODRA) 0x10D10 Port A data register (PDATA) 0x10D14– 0x10D1F Reserved 0x10D20 Port B data direction register (PDIRB) 0x10D24 Port B pin assignment register (PPARB) 0x10D28 Port B special option register (PSORB) 0x10D2C Port B open drain register (PODRB) 0x10D30 Port B data register (PDATB) 0x10D34– 0x10D3F Reserved R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits R/W — 32 bits 12 bytes 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 — R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits R/W — 32 bits 12 bytes 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 —

41.2.3/41-3

41.2.4/41-4 41.2.5/41-4

41.2.1/41-2 41.2.2/41-2

41.2.3/41-3

41.2.4/41-4 41.2.5/41-4

41.2.1/41-2 41.2.2/41-2

— 3-8

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x10D40 Port C data direction register (PDIRC) 0x10D44 Port C pin assignment register (PPARC) 0x10D48 Port C special option register (PSORC) 0x10D4C Port C open drain register (PODRC) 0x10D50 Port C data register (PDATC) 0x10D54– 0x10D5F Reserved 0x10D60 Port D data direction register (PDIRD) 0x10D64 Port D pin assignment register (PPARD) 0x10D68 Port D special option register (PSORD) 0x10D6C Port D open drain register (PODRD) 0x10D70 Port D data register (PDATD)

CPM Timers

0x10D80 Timer 1 and timer 2 global configuration register (TGCR1) 0x10D81 Reserved 0x10D84 Timer 3 and timer 4 global configuration register (TGCR2) 0x10D85– 0x10D8F Reserved 0x10D90 Timer 1 mode register (TMR1) 0x10D92 Timer 2 mode register (TMR2) 0x10D94 Timer 1 reference register (TRR1) 0x10D96 Timer 2 reference register (TRR2) 0x10D98 Timer 1 capture register (TCR1) 0x10D9A Timer 2 capture register (TCR2) 0x10D9C Timer 1 counter (TCN1) 0x10D9E Timer 2 counter (TCN2) 0x10DA0 Timer 3 mode register (TMR3) 0x10DA2 Timer 4 mode register (TMR4) 0x10DA4 Timer 3 reference register (TRR3) 0x10DA6 Timer 4 reference register (TRR4) 0x10DA8 Timer 3 capture register (TCR3) 0x10DAA Timer 4 capture register (TCR4) 0x10DAC Timer 3 counter (TCN3)

R/W Size

R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits R/W — 32 bits 12 bytes 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 — R/W R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits 32 bits R/W — 8 bits 24 bits R/W — 8 bits 11 bytes R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits

Reset

0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00 — 0x00 — 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000

Section/Page

41.2.3/41-3

41.2.4/41-4 41.2.5/41-4

41.2.1/41-2 41.2.2/41-2

41.2.3/41-3

41.2.4/41-4 41.2.5/41-4

41.2.1/41-2 41.2.2/41-2

18.2.2/18-3

18.2.2/18-3

18.2.3/18-5 18.2.3/18-5

18.2.4/18-6 18.2.4/18-6

18.2.5/18-7 18.2.5/18-7 18.2.6/18-7 18.2.6/18-7

18.2.3/18-5 18.2.3/18-5

18.2.4/18-6 18.2.4/18-6

18.2.5/18-7 18.2.5/18-7 18.2.6/18-7

Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-9

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x10DAE Timer 4 counter (TCN4) 0x10DB0 Timer 1 event register (TER1) 0x10DB2 Timer 2 event register (TER2) 0x10DB4 Timer 3 event register (TER3) 0x10DB6 Timer 4 event register (TER4) 0x10DB8– 0x11017 Reserved

R/W Size

R/W R/W R/W R/W R/W — 16 bits 16 bits 16 bits 16 bits 16 bits 608 bytes

SDMA–General

0x11018 SDMA status register (SDSR) 0x11019 Reserved 0x1101C SDMA mask register (SDMR) 0x1101D Reserved R/W — R/W — 8 bits 24 bits 8 bits 24 bits

IDMA

0x11020 IDMA 1 event register (IDSR1) 0x11021 Reserved 0x11024 IDMA 1 mask register (IDMR1) 0x11025 Reserved 0x11028 IDMA 2 event register (IDSR2) 0x11029 Reserved 0x1102C IDMA 2 mask register (IDMR2) 0x1102D Reserved 0x11030 IDMA 3 event register (IDSR3) 0x11031 Reserved 0x11034 IDMA 3 mask register (IDMR3) 0x11035 Reserved 0x11038 IDMA 4 event register (IDSR4) 0x11039 Reserved 0x1103C IDMA 4 mask register (IDMR4) 0x1103D– 0x112FF Reserved R/W — R/W — R/W — R/W — R/W — R/W — R/W — R/W — 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 707 bytes 0x00 — 0x00 — 0x00 — 0x00 — 0x00 — 0x00 — 0x00 — 0x00 — 0x00 — 0x00 —

Reset

0x0000 0x0000 0x0000 0x0000 0x0000 —

Section/Page

18.2.6/18-7 18.2.7/18-7 18.2.7/18-7 18.2.7/18-7 18.2.7/18-7

19.2.1/19-3

19.2.2/19-4

19.8.4/19-22

19.8.4/19-22

19.8.4/19-22

19.8.4/19-22

19.8.4/19-22

19.8.4/19-22

19.8.4/19-22

19.8.4/19-22

— 3-10

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register FCC1

0x11300 FCC1 general mode register (GFMR1) 0x11304 FCC1 protocol-specific mode register (FPSMR1) 0x11308 FCC1 transmit on demand register (FTODR1) 0x1130A Reserved 0x1130C FCC1 data synchronization register (FDSR1) 0x1130E Reserved 0x11310 FCC1 event register (FCCE1) 0x11312 Reserved 0x11314 FCC1 mask register (FCCM1) 0x11316 Reserved 0x11318 FCC1 status register (FCCS1) 0x11319 Reserved 0x1131C FCC1 transmit internal rate registers for PHY0 (FTIRR1_PHY0) 0x1131D FCC1 transmit internal rate registers for PHY1 (FTIRR1_PHY1) 0x1131E FCC1 transmit internal rate registers for PHY2 (FTIRR1_PHY2) 0x1131F FCC1 transmit internal rate registers for PHY3 (FTIRR1_PHY3)

R/W

R/W — R/W — R/W — R/W — R — R/W R/W R/W

Size

R/W R/W 32 bits 32 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 24 bits 8 bits 8 bits 8 bits R/W 8 bits

Reset

0x00

Section/Page

0x0000_0000 0x0000_0000

30.2/30-3

31.13.2/31-85

(ATM)

34.4.2.1.1/34-2 2

(IMA)

36.18.1/36-19

(Ethernet)

37.6/37-8

(HDLC) 0x0000 — 0x7E7E — 0x0000_0000

30.5/30-9

30.4/30-8

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC) — — 0x0000_0000 — 0x00 — 0x00 0x00

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC) —

37.10/37-16

(HDLC) —

31.15.1.4/31-93

(ATM)

34.4.2.1.2/34-2 2

(IMA) 0x00 Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-11

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register FCC2

0x11320 FCC2 general mode register (GFMR2) 0x11324 FCC2 protocol-specific mode register (FPSMR2) 0x11328 FCC2 transmit on-demand register (FTODR2) 0x1132A Reserved 0x1132C FCC2 data synchronization register (FDSR2) 0x1132E Reserved 0x11330 FCC2 event register (FCCE2) 0x11332 Reserved 0x11334 FCC2 mask register (FCCM2) 0x11336 Reserved 0x11338 FCC2 status register (FCCS2) 0x11339 Reserved 0x1133C FCC2 transmit internal rate registers for PHY0 (FTIRR2_PHY0) 0x1133D FCC2 transmit internal rate registers for PHY1 (FTIRR2_PHY1) 0x11133E FCC2 transmit internal rate registers for PHY2 (FTIRR2_PHY2) 0x1133F FCC2 transmit internal rate registers for PHY3 (FTIRR2_PHY3)

R/W

R/W R/W R/W — R/W — R/W — R/W — R — R/W R/W R/W

Size

32 bits 32 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 24 bits 8 bits 8 bits 8 bits R/W 8 bits

Reset

0x00

Section/Page

0x0000_0000 0x0000_0000

30.2/30-3

31.13.2/31-85

(ATM)

34.4.2.1.1/34-2 2

(IMA)

36.18.1/36-19

(Ethernet)

37.6/37-8

(HDLC) 0x0000 — 0x7E7E — 0x0000_0000

30.5/30-9

30.4/30-8

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC) — — 0x0000_0000 — 0x00 — 0x00 0x00

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC) —

37.10/37-16

(HDLC) —

31.15.1.4/31-93

(ATM)

34.4.2.1.2/34-2 2

(IMA) 0x00 3-12

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register FCC3

0x11340 FCC3 general mode register (GFMR3) 0x11344 FCC3 protocol-specific mode register (FPSMR3) 0x11348 FCC3 transmit on-demand register (FTODR3) 0x1134A Reserved 0x1134C FCC3 data synchronization register (FDSR3) 0x1134E Reserved 0x11350 FCC3 event register (FCCE3) 0x11352 Reserved 0x11354 FCC3 mask register (FCCM3) 0x11356 Reserved 0x11358 FCC3 status register (FCCS3)

R/W

R/W R/W 32 bits 32 bits R/W — R/W — R/W — R/W — R

Size

16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits

Reset Section/Page

0x0000_0000 0x0000_0000 0x0000 — 0x7E7E — 0x0000 — 0x0000 — 0x0000

30.2/30-3

31.13.2/31-85

(ATM)

34.4.2.1.1/34-2 2

(IMA)

36.18.1/36-19

(Ethernet)

37.6/37-8

(HDLC)

30.5/30-9

30.4/30-8

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC) —

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC) —

37.10/37-16

(HDLC) 0x11359– 0x11379 Reserved —

FCC1 Extended Registers

0x11380 FCC1 internal rate port enable register (FIRPER1) 0x11384 FCC1 internal rate event register (FIRER1) 0x11388 FCC1 internal rate select register high (FIRSR1_HI) 0x1138C FCC1 internal rate select register low (FIRSR1_LO) 0x11390 FCC1 general extended mode register (GFEMR1) — — — — — 32 bit 32 bit 32 bit 32 bit 8 bit 0x0000_0000

31.15.1.4/31-93

0x0000_0000

31.15.1.5/31-94

0x0000_0000

31.15.1.6/31-95

0x0000_0000

31.15.1.6/31-95

0x00

30.2.1/30-7

Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-13

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset)

0x11391– 0x1139F Reserved

Register R/W

Size

15 bytes 0x113D0 General FCC3 expansion mode register (GFEMR3) 0x113D1 Reserved

FCC3 Extended Registers TC Layer 1 1

0x11400 0x11402 0x11404 0x11406 0x11408 0x1140A 0x1140C 0x1140E 0x11410 0x11412 TC1 mode register (TCMODE1) 1 TC1 cell delineation state machine register (CDSMR1) 1 TC1 event register (TCER1) 1 TC1 received cells counter (TC_RCC1) 1 TC1 mask register (TCMR1) 1 TC1 filtered cells counter (TC_FCC1) 1 TC1 corrected cells counter (TC_CCC1) 1 TC1 idle cells counter (TC_ICC1) 1 TC1 transmitted cells counter (TC_TCC1) 1 TC1 error cells counter (TC_ECC1) 1 0x11414 Reserved 0x11420 0x11422 0x11424 0x11426 0x11428 0x1142A

TC Layer 2 1

TC2 mode register (TCMODE2) 1 TC2 cell delineation state machine register (CDSMR2) 1 TC2 event register (TCER2) 1 TC2 received cells counter (TC_RCC2) 1 TC2 mask register (TCMR2) 1 TC2 filtered cells counter (TC_FCC2) 1 R/W — 8 bits 47 bytes R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits R/W R/W — 16 bits 16 bits 12 bytes 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits

Reset

— 0x113A0 0x113B0 FCC2 internal rate port enable register (FIRPER2) 0x113A4 FCC2 internal rate event register (FIRER2) 0x113A8 FCC2 internal rate select register high (FIRSR2_HI) 0x113AC FCC2 internal rate select register low (FIRSR2_LO) FCC2 general expansion mode register (GFEMR2) 0x113B1– 0x113CF Reserved

FCC2 Extended Registers

R/W R/W R/W R/W 32 bits 32 bits 32 bits 32 bits R/W — 8 bits 31 bytes 0x0000_0000

31.15.1.4/31-93

0x0000_0000

31.15.1.5/31-94

0x0000_0000

31.15.1.6/31-95

0x0000_0000

31.15.1.6/31-95

0x00 —

30.2.1/30-7

— 0x00 — 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 — 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000

Section/Page

30.2.1/30-7

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12

3-14

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x1142C 0x1142E 0x11430 0x11432 TC2 corrected cells counter (TC_CCC2) 1 TC2 idle cells counter (TC_ICC2) 1 TC2 transmitted cells counter (TC_TCC2) 1 TC2 error cells counter (TC_ECC2) 1 0x11434 Reserved

TC Layer 3 1

0x11440 0x11442 0x11444 0x11446 0x11448 0x1144A 0x1144C 0x1144E 0x11450 0x11452 TC3 mode register (TCMODE3) 1 TC3 cell delineation state machine register (CDSMR3) 1 TC3 event register (TCER3) 1 TC3 received cells counter (TC_RCC3) 1 TC3 mask register (TCMR3) 1 TC3 filtered cells counter (TC_FCC3) 1 TC3 corrected cells counter (TC_CCC3) 1 TC3 idle cells counter (TC_ICC3) 1 TC3 transmitted cells counter (TC_TCC3) 1 TC3 error cells counter (TC_ECC3) 1 0x11454 Reserved 0x11460 0x11462 0x11464 0x11466 0x11468 0x1146A 0x1146C 0x1146E 0x11470 0x11472 0x11474

TC Layer 4 1

TC4 mode register (TCMODE4) 1 TC4 cell delineation state machine register (CDSMR4) 1 TC4 event register (TCER4) 1 TC4 received cells counter (TC_RCC4) 1 TC4 mask register (TCMR4) 1 TC4 filtered cells counter (TC_FCC4) 1 TC4 corrected cells counter (TC_CCC4) 1 TC4 idle cells counter (TC_ICC4) 1 TC4 transmitted cells counter (TC_TCC4) 1 TC4 error cells counter (TC_ECC4) 1 Reserved 1

TC Layer 5 1

0x11480 TC5 mode register (TCMODE5) 1

R/W Size

R/W R/W R/W R/W — 16 bits 16 bits 16 bits 16 bits 12 bytes R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits R/W R/W — 16 bits 16 bits 12 bytes R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits R/W R/W — 16 bits 16 bits 12 bytes R/W 16 bits

Reset

0x0000 0x0000 0x0000 0x0000 —

Section/Page

35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

— 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 —

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

— 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 —

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

— 0x0000

35.4.1.1/35-7

Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-15

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11482 0x11484 0x11486 0x11488 0x1148A 0x1148C 0x1148E 0x11490 0x11492 TC5 cell delineation state machine register (CDSMR5) 1 TC5 event register (TCER5) 1 TC5 received cells counter (TC_RCC5) 1 TC5 mask register (TCMR5) 1 TC5 filtered cells counter (TC_FCC5) 1 TC5 corrected cells counter (TC_CCC5) 1 TC5 idle cells counter (TC_ICC5) 1 TC5 transmitted cells counter (TC_TCC5) 1 TC5 error cells counter (TC_ECC5) 1 0x11494 Reserved

TC Layer 6 1

0x114A0 0x114A2 0x114A4 0x114A6 0x114A8 0x114AA 0x114AC 0x114AE 0x114B0 0x114B2 TC6 mode register (TCMODE6) 1 TC6 cell delineation state machine register (CDSMR6) 1 TC6 event register (TCER6) 1 TC6 received cells counter (TC_RCC6) 1 TC6 mask register (TCMR6) 1 TC6 filtered cells counter (TC_FCC6) 1 TC6 corrected cells counter (TC_CCC6) 1 TC6 idle cells counter (TC_ICC6) 1 TC6 transmitted cells counter (TC_TCC6) 1 TC6 error cells counter (TC_ECC6) 1 0x114B4 Reserved

TC Layer 7 1

0x114C0 0x114C2 0x114C4 0x114C6 0x114C8 0x114CA 0x114CC 0x114CE 0x114D0 TC7 mode register (TCMODE7) 1 TC7 cell delineation state machine register (CDSMR7) 1 TC7 event register (TCER7) 1 TC7 received cells counter (TC_RCC7) 1 TC7 mask register (TCMR7) 1 TC7 filtered cells counter (TC_FCC7) 1 TC7 corrected cells counter (TC_CCC7) 1 TC7 idle cells counter (TC_ICC7) 1 TC7 transmitted cells counter (TC_TCC7) 1

R/W Size

R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits R/W — 16 bits 12 bytes R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits R/W R/W — 16 bits 16 bits 12 bytes R/W R/W R/W R/W R/W R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits

Reset

0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 —

Section/Page

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

— 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 —

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

— 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

3-16

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x114D2 TC7 error cells counter (TC_ECC7) 1 0x114D4 Reserved

TC Layer 8 1

0x114E0 0x114E2 0x114E4 0x114E6 0x114E8 0x114EA 0x114EC 0x114EE 0x114F0 0x114F2 TC8 mode register (TCMODE8) 1 TC8 cell delineation state machine register (CDSMR8) 1 TC8 event register (TCER8) 1 TC8 received cells counter (TC_RCC8) 1 TC8 mask register (TCMR8) 1 TC8 filtered cells counter (TC_FCC8) 1 TC8 corrected cells counter (TC_CCC8) 1 TC8 idle cells counter (TC_ICC8) 1 TC8 transmitted cells counter (TC_TCC8) 1 TC8 error cells counter (TC_ECC8) 1 0x114F4 Reserved

TC Layer—General 1 R/W

R/W — 16 bits 12 bytes R/W R/W R/W R/W R/W R/W R/W R/W

Size

16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits R/W R/W — 16 bits 16 bits 12 bytes 0x11500 0x11502 TC general status register (TCGSR) 1 TC general event register (TCGER) 1 R R/W 16 bits 16 bits

BRGs 5–8

0x115F0 BRG5 configuration register (BRGC5) 0x115F4 BRG6 configuration register (BRGC6) 0x1115F8 BRG7 configuration register (BRGC7) 0x115FC BRG8 configuration register (BRGC8) 0x11600– 0x1185F Reserved R/W R/W R/W R/W — 32 bits 32 bits 32 bits 32 bits 608 bytes

I 2 C

0x11860 I 2 C mode register (I2MOD) 0x11861 0x11864 0x11865 0x11868 I Reserved 2 C address register (I2ADD) Reserved I 2 C BRG register (I2BRG) 0x11869 0x1186C Reserved I 2 C command register (I2COM) R/W — R/W — R/W — R/W 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits

Reset

0x0000 — 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 — 0x0000 0x0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 — 0x00 — 0x00 — 0x00 — 0x00

Section/Page

35.4.3.3/35-12

35.4.1.1/35-7

35.4.1.2/35-8

35.4.1.3/35-9

35.4.1.4/35-10 35.4.1.4/35-10

35.4.3.6/35-12 35.4.3.4/35-12 35.4.3.5/35-12

35.4.3.2/35-11

35.4.3.3/35-12

35.4.2.2/35-11

35.4.2.1/35-10

17.1/17-2

40.4.1/40-6

40.4.2/40-7

40.4.3/40-7

40.4.5/40-8

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-17

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset)

0x1186D 0x11870 Reserved I 2 C event register (I2CER) 0x11871

Register

C mask register (I2CMR)

BRGs 1–4 R/W

— R/W — R/W —

Size

24 bits 8 bits 24 bits 8 bits 315 bytes 0x119C0 Communications processor command register (CPCR) 0x119C4 CP configuration register (RCCR) 0x119C8– 0x119D5 Reserved 0x119DE Reserved 0x119E0 CP time-stamp register (RTSR)

Communications Processor

0x119D6 CP timers event register (RTER) 0x119DA CP timers mask register (RTMR) 0x119DC CP time-stamp timer control register (RTSCR) R/W R/W — 32 bits 32 bits 14 bytes R/W R/W — R/W R/W 16 bits 16 bits 16 bits 16 bits 32 bits

Reset

— 0x00 — 0x00 — 0x0000_0000 0x0000_0000 — 0x0000_0000 0x0000_0000 0x0000 — 0x0000 0x119F0 0x119F4 0x119F8 0x119FC 0x11A0A BRG1 configuration register (BRGC1) BRG2 configuration register (BRGC2) BRG3 configuration register (BRGC3) BRG4 configuration register (BRGC4) 0x11A00 SCC1 general mode register (GSMR_L1) 0x11A04 SCC1 general mode register (GSMR_H1) 0x11A08 SCC1 protocol-specific mode register (PSMR1)

SCC1

Reserved R/W R/W R/W R/W R/W R/W R/W — 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 16 bits 16 bits 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000 —

Section/Page

40.4.4/40-7

40.4.4/40-7

14.4.1/14-12

14.3.7/14-9

14.6.4/14-25

14.3.8/14-10

14.3.9/14-11

17.1/17-2

20.1.1/20-3

20.1.2/20-9

21.16/21-13

(UART)

22.8/22-7

(HDLC)

23.11/23-10

(BISYNC)

24.9/24-8

(Transparent)

25.17/25-14

(Ethernet) — 3-18

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11A0C SCC1 transmit-on-demand register (TODR1) 0x11A0E SCC1 data synchronization register (DSR1) 0x11A10 SCC1 event register (SCCE1) 0x11A14 SCC1 mask register (SCCM1) 0x11A16 Reserved 0x11A17 SCC1 status register (SCCS1)

R/W

R/W R/W R/W R/W 16 bits 16 bits 16 bits 16 bits — R/W

Size

8 bits 8 bits — 8 bytes

Reset

0x0000 0x7E7E 0x0000 0x0000 — 0x00 —

Section/Page

20.1.4/20-10

20.1.3/20-9

21.19/21-19

(UART)

22.11/22-13

(HDLC)

23.14/23-15

(BISYNC)

24.12/24-11

(Transparent)

25.20/25-20

(Ethernet) —

21.20/21-21

(UART)

22.12/22-15

(HDLC)

23.15/23-16

(BISYNC)

24.13/24-12

(Transparent) — 0x11A18– 0x11A1F Reserved 0x11A20 SCC2 general mode register (low) (GSMR_L2) 0x11A24 SCC2 general mode register (high) (GSMR_H2) 0x11A28 SCC2 protocol-specific mode register (PSMR2)

SCC2

0x11A2A Reserved 0x11A2C SCC2 transmit-on-demand register (TODR2) 0x11A2E SCC2 data synchronization register (DSR2) R/W R/W R/W 32 bits 32 bits 16 bits — R/W R/W 16 bits 16 bits 16 bits 0x0000_0000 0x0000_0000 0x0000 — 0x0000 0x7E7E

20.1.1/20-3

20.1.2/20-9

21.16/21-13

(UART)

22.8/22-7

(HDLC)

23.11/23-10

(BISYNC)

24.9/24-8

(Transparent)

25.17/25-14

(Ethernet) —

20.1.4/20-10

20.1.3/20-9

Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-19

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11A30 SCC2 event register (SCCE2) 0x11A34 SCC2 mask register (SCCM2) 0x11A36 Reserved 0x11A37 SCC2 status register (SCCS2)

R/W

R/W R/W — R/W

Size

16 bits 16 bits 8 bits 8 bits — 8 bytes

Reset

0x0000 0x0000 — 0x00 —

Section/Page

21.19/21-19

(UART)

22.11/22-13

(HDLC)

23.14/23-15

(BISYNC)

24.12/24-11

(Transparent)

25.20/25-20

(Ethernet) —

21.20/21-21

(UART)

22.12/22-15

(HDLC)

23.15/23-16

(BISYNC)

24.13/24-12

(Transparent) — 0x11A38– 0x11A3F Reserved 0x11A40 SCC3 general mode register (GSMR_L3) 0x11A44 SCC3 general mode register (GSMR_H3) 0x11A48 SCC3 protocol-specific mode register (PSMR3)

SCC3

0x11A4A Reserved 0x11A4C SCC3 transmit on demand register (TODR3) 0x11A4E SCC3 data synchronization register (DSR3) R/W R/W R/W 32 bits 32 bits 16 bits — R/W R/W 16 bits 16 bits 16 bits 0x0000_0000 0x0000_0000 0x0000 — 0x0000 0x7E7E

20.1.1/20-3

20.1.2/20-9

21.16/21-13

(UART)

22.8/22-7

(HDLC)

23.11/23-10

(BISYNC)

24.9/24-8

(Transparent)

25.17/25-14

(Ethernet) —

20.1.4/20-10

20.1.3/20-9

3-20

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11A50 SCC3 event register (SCCE3) 0x11A54 SCC3 mask register (SCCM3) 0x11A56 Reserved 0x11A57 SCC3 status register (SCCS3)

R/W

R/W R/W 16 bits 16 bits — R/W

Size

8 bits 8 bits — 8 bytes

Reset

0x0000 0x0000 — 0x00 —

Section/Page

21.19/21-19

(UART)

22.11/22-13

(HDLC)

23.14/23-15

(BISYNC)

24.12/24-11

(Transparent)

25.20/25-20

(Ethernet) —

21.20/21-21

(UART)

22.12/22-15

(HDLC)

23.15/23-16

(BISYNC)

24.13/24-12

(Transparent) — 0x11A58– 0x11A5F Reserved 0x11A60 SCC4 general mode register (GSMR_L4) 0x11A64 SCC4 general mode register (GSMR_H4) 0x11A68 SCC4 protocol-specific mode register (PSMR4)

SCC4

0x11A6A Reserved 0x11A6C SCC4 transmit on-demand register (TODR4) 0x11A6E SCC4 data synchronization register (DSR4) R/W R/W R/W 32 bits 32 bits 16 bits — R/W R/W 16 bits 16 bits 16 bits 0x0000_0000 0x0000_0000 0x0000 — 0x0000 0x7E7E

20.1.1/20-3

20.1.2/20-9

21.16/21-13

(UART)

22.8/22-7

(HDLC)

23.11/23-10

(BISYNC)

24.9/24-8

(Transparent)

25.17/25-14

(Ethernet) —

20.1.4/20-10

20.1.3/20-9

Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-21

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11A70 SCC4 event register (SCCE4) 0x11A74 SCC4 mask register (SCCM4) 0x11A77 SCC4 status register (SCCS4) 0x11A78– 0x11A7F Reserved

R/W

R/W R/W —

Size

16 bits 16 bits 8 bits — 8 bytes

Reset

0x0000 0x0000 0x00 —

Section/Page

21.19/21-19

(UART)

22.11/22-13

(HDLC)

23.14/23-15

(BISYNC)

24.12/24-11

(Transparent)

25.20/25-20

(Ethernet)

21.20/21-21

(UART)

22.12/22-15

(HDLC)

23.15/23-16

(BISYNC)

24.13/24-12

(Transparent) —

SMC1

0x11A82 SMC1 mode register (SMCMR1) 0x11A84 Reserved 0x11A86 SMC1 event register (SMCE1) 0x11A87 Reserved 0x11A8A SMC1 mask register (SMCM1) 0x11A8B– 0x11A91 Reserved R/W — R/W — R/W 16 bits 8 bits 24 bits 8 bits — 7 bytes 0x0000 — 0x00 — 0x00 —

28.2.1/28-2

28.3.11/28-18

(UART)

28.4.10/28-28

(Transparent)

28.5.9/28-34

(GCI) —

SMC2

0x11A92 SMC2 mode register (SMCMR2) 0x11A94 Reserved 0x11A96 SMC2 event register (SMCE2) 0x11A97 Reserved 0x11A9A SMC2 mask register (SMCM2) 0x11A9B– 0x11A9F Reserved R/W — R/W — R/W 16 bits 8 bits 24 bits 8 bits — 5 bytes 0x0000 — 0x00 — 0x00 —

28.2.1/28-2

28.3.11/28-18

(UART)

28.4.10/28-28

(Transparent)

28.5.9/28-34

(GCI) — 3-22

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register SPI

0x11AA0 SPI mode register (SPMODE) 0x11AA2 Reserved 0x11AA6 SPI event register (SPIE) 0x11AA7 Reserved 0x11AAA SPI mask register (SPIM) 0x11AAB Reserved 0x11AAD SPI command register (SPCOM) 0x11AAE – 0x11AFF Reserved

CPM Mux

0x11B00 CPM mux SI1 clock route register (CMXSI1CR) 0x11B02 CPM mux SI2 clock route register (CMXSI2CR) 0x11B03 Reserved 0x11B04 CPM mux FCC clock route register (CMXFCR) 0x11B08 CPM mux SCC clock route register (CMXSCR) 0x11B0C CPM mux SMC clock route register (CMXSMR) 0x11B0D 0x11B0E Reserved CPM mux UTOPIA address register (CMXUAR) 2 0x11B10– 0x11B1F Reserved

SI1 Registers

0x11B20 SI1 TDMA1 mode register (SI1AMR) 0x11B22 SI1 TDMB1 mode register (SI1BMR) 0x11B24 SI1 TDMC1 mode register (SI1CMR) 0x11B26 SI1 TDMD1 mode register (SI1DMR) 0x11B28 SI1 global mode register (SI1GMR) 0x11B29 Reserved 0x11B2A SI1 command register (SI1CMDR) 0x11B2B Reserved 0x11B2C SI1 status register (SI1STR) 0x11B2D Reserved

R/W Size

R/W — R/W — 16 bits 4 bytes 8 bits 24 bits R/W — W — 8 bits 24 bits 8 bits 82 bytes R/W R/W — R/W R/W 8 bits 8 bits 8 bits 32 bits 32 bits R/W — 8 bits 8 bits R/W — 16 bits 16 bytes 0x00 0x00 — 0x0000_0000 0x0000_0000 0x00 — 0x0000 — R/W R/W R/W R/W R/W — R/W — R/W — 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits

Reset

0x0000 — 0x00 — 0x00 — 0x00 — 0x0000 0x0000 0x0000 0x0000 0x00 — 0x00 — 0x00 —

Section/Page

39.4.1/39-6

39.4.2/39-9

39.4.2/39-9

39.4.3/39-10

16.4.2/16-12

16.4.3/16-13

16.4.4/16-13

16.4.5/16-16

16.4.6/16-19

16.4.1/16-7

15.5.2/15-17 15.5.1/15-17

15.5.4/15-24

15.5.5/15-25

— Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-23

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11B2E SI1 RAM shadow address register (SI1RSR)

MCC1 Registers 1

0x11B30 MCC1 event register (MCCE1) 1 0x11B32 0x11B34 Reserved MCC1 mask register (MCCM1) 1 0x11B36 0x11B38 Reserved MCC1 configuration register (MCCF1) 1 0x11B39– 0x11B3F Reserved

SI2 Registers R/W

R/W

Size

16 bits R/W — R/W — R/W — 16 bits 16 bits 16 bits 16 bits 8 bits 7 bytes 0x11B40 0x11B42 0x11B44 0x11B46 0x11B48 0x11B49 0x11B4A 0x11B4B 0x11B4C 0x11B4D 0x11B4E SI2 TDMA2 mode register (SI2AMR) SI2 TDMB2 mode register (SI2BMR) SI2 TDMC2 mode register (SI2CMR) SI2 TDMD2 mode register (SI2DMR) SI2 global mode register (SI2GMR) Reserved SI2 command register (SI2CMDR) Reserved SI2 status register (SI2STR) Reserved SI2 RAM shadow address register (SI2RSR)

MCC2 Registers

R/W R/W R/W R/W R/W — R/W — R/W — R/W 16 bits 16 bits 16 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 16 bits 16 bits 0x11B50 MCC2 event register (MCCE2) 0x11B52 Reserved 0x11B54 MCC2 mask register (MCCM2) 0x11B56 Reserved 0x11B58 MCC2 configuration register (MCCF2) 0x11B59 Reserved R/W — R/W — R/W — 16 bits 16 bits 16 bits 16 bits 8 bits 7 bytes

USB

0x11B60 0x11B61 0x11B62 USB mode register (USMOD) USB address register (USADR) USB command register (USCOM) R/W R/W R/W 8 bits 8 bits 8 bits 3-24

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Reset

0x0000 0x0000 — 0x0000 — 0x00 — 0x0000 0x0000 0x0000 0x0000 0x00 — 0x00 — 0x00 — 0x0000 0x0000 — 0x0000 — 0x00 — 0x00 0x00 0x00

Section/Page

15.5.3/15-24

29.8.1/29-36 29.8.1/29-36

29.6/29-32

15.5.2/15-17 15.5.1/15-17

15.5.4/15-24

15.5.5/15-25

15.5.3/15-24

29.8.1/29-36

29.8.1/29-36

29.6/29-32

27.5.7.1/27-17

27.5.7.2/27-18

27.5.7.4/27-20

Freescale Semiconductor

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register

0x11B64 0x11B66 0x11B68 0x11B6A USB end point 1 register (USEP1) USB end point 2 register (USEP2) USB end point 3 register (USEP3) USB end point 4 register (USEP4) 0x11B6C– 0x11B6F Reserved 0x11B70 0x11B72 0x11B74 0x11B77 USB event register (USBER) Reserved USB mask register (USBMR) USB status register (USBS) 0x11B79– 0x11FFF Reserved

R/W

R/W R/W R/W R/W — R/W — R/W R/W —

SI1 RAM

0x12000– 0x121FF SI 1 transmit routing RAM (SI1TxRAM) 0x12200– 0x123FF Reserved 0x12400– 0x125FF SI 1 receive routing RAM (SI1RxRAM) 0x12600– 0x127FF Reserved R/W — R/W —

SI2 RAM

0x12800– 0x129FF SI 2 transmit routing RAM (SI2TxRAM) 0x12A00– 0x12BFF Reserved 0x12C00– 0x12DFF SI 2 receive routing RAM (SI2RxRAM) 0x12E00– 0x12FFF Reserved R/W — R/W — 0x13000– 0x137FF Reserved — 0x13800– 0x13FFF Reserved —

Size

16 bits 16 bits 16 bits 16 bits 32 bits 16 bits 16 bits 16 bits 8 bits 1158 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes bytes bytes

Reset

0x0000 0x0000 0x0000 0x0000 — 0x0000 0x0000 0x0000 0x00 — undefined — undefined — undefined — undefined —

Section/Page

27.5.7.3/27-18 27.5.7.3/27-18 27.5.7.3/27-18 27.5.7.3/27-18

27.5.7.5/27-20

27.5.7.6/27-21 27.5.7.7/27-21

15.4.3/15-10

15.4.3/15-10

15.4.3/15-10

15.4.3/15-10

— Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-25

Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size

0x20000– 0x27FFF CPM Instruction RAM (IRAM) 1 2 MPC8280 only. Reserved on other devices.

Reserved on the MPC8270.

CPM Dual-Port RAM (Instruction)

R/W 32 Kbytes

Reset

Undefined

Section/Page

3-26

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Part II Configuration and Reset

Intended Audience

Part II is intended for system designers and programmers who need to understand the operation of the

MPC8280 at start up. It assumes understanding of the PowerPC programming model described in the previous chapters and a high level understanding of the MPC8280.

Contents

Part II describes start-up behavior of the MPC8280.

It contains the following chapters: • •

Chapter 4, “System Interface Unit (SIU),”

describes the system configuration and protection functions which provide various monitors and timers, and the 60x bus configuration.

Chapter 5, “Reset,”

describes the behavior of the MPC8280 at reset and start-up.

Suggested Reading

Supporting documentation for the MPC8280 can be accessed through the world-wide web at www.freescale.com. This documentation includes technical specifications, reference materials, and detailed applications notes.

Conventions

This chapter uses the following notational conventions:

Bold

Bold entries in figures and tables showing registers and parameter RAM should be initialized by the user.

mnemonics

italics

Instruction mnemonics are shown in lowercase bold. Italics indicate variable command parameters, for example, bcctrx.

Book titles in text are set in italics.

Prefix to denote hexadecimal number 0x0 0b0 rA, rB rD REG[FIELD] Prefix to denote binary number Instruction syntax used to identify a source GPR Instruction syntax used to identify a destination GPR Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For Freescale Semiconductor

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

II-1

x

n

example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.

In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value

Acronyms and Abbreviations

Table II-1

contains acronyms and abbreviations that are used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.

Term

lsb LSU MSB msb MSR PCI RTOS Rx BIST DMA DRAM EA GPR IEEE LSB SPR SWT Tx

Table II-1. Acronyms and Abbreviated Terms Meaning

Built-in self test Direct memory access Dynamic random access memory Effective address General-purpose register Institute of Electrical and Electronics Engineers Least-significant byte Least-significant bit Load/store unit Most-significant byte Most-significant bit Machine state register Peripheral component interconnect Real-time operating system Receive Special-purpose register Software watchdog timer Transmit II-2

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Chapter 4 System Interface Unit (SIU)

The system interface unit (SIU) consists of several functions that control system start-up and initialization, as well as operation, protection, and the external system bus. Key features of the SIU include the following: • • • • • • • • • System configuration and protection System reset monitoring and generation Clock synthesizer Power management 60x bus interface Flexible, high-performance memory controller Level-two cache controller interface PCI interface IEEE 1149.1 test-access port (TAP)

Figure 4-1 is a block diagram of the SIU.

60x Bus (32-Bit Address/64-Bit Data) G2_LE Core Configuration Registers Memory Controller Core Control Counters Bridge Interrupt Controller Memory Controller Local Control Communications Processor Local Bus (18-Bit Address/32-Bit Data)

Figure 4-1. SIU Block Diagram

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The system configuration and protection functions provide various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, and time counter. The clock synthesizer generates the clock signals used by the SIU and other MPC8280 modules. The SIU clocking scheme supports stop and normal modes.

The 60x bus interface is a standard pipelined bus. The MPC8280 allows external bus masters to request and obtain system bus mastership.

Chapter 8, “The 60x Bus,”

describes bus operation, but 60x bus configuration is explained in this section.

The memory controller module, described in Chapter 11, “Memory Controller,”

provides a seamless interface to many types of memory devices and peripherals. It supports up to twelve memory banks, each with its own device and timing attributes. The PCI interface enables the use of standard peripherals. The MPC8280’s implementation supports circuit board test strategies through a user- accessible test logic that is fully compliant with the IEEE 1149.1 test access port.

4.1

System Configuration and Protection

The MPC8280 incorporates many system functions that normally must be provided in external circuits. In addition, it is designed to provide maximum system safeguards against hardware and/or software faults.

Table 4-1

describes functions provided in the system configuration and protection submodule.

Table 4-1. System Configuration and Protection Functions Function Description

System configuration The SIU allows the user to configure the system according to the particular requirements. The functions include control of parity checking and part and mask number constants.

60x bus monitor Local bus monitor Software watchdog timer Monitors the transfer acknowledge (TA) and address acknowledge (AACK) response time for all bus accesses initiated by internal or external masters. TEA is asserted if the TA/AACK response limit is exceeded. This function can be disabled if needed.

Monitors transfers between local bus internal masters and local bus slaves. An internal TEA assertion occurs if the transfer time limit is exceeded. This function can be disabled.

Asserts a reset or NMI interrupt, selected by the system protection control register (SYPCR) if the software fails to service the software watchdog timer for a certain period of time (for example, because software is lost or trapped in a loop). After a system reset, this function is enabled, selects a maximum time-out period, and asserts a system reset if the time-out is reached. The software watchdog timer can be disabled or its time-out period may be changed in the SYPCR. Once the SYPCR is written, it cannot

be written again until a system reset. For more information, see Section 4.1.5, “Software Watchdog Timer .”

Periodic interrupt timer (PIT) Time counter Generates periodic interrupts for use with a real-time operating system or the application software. The periodic interrupt timer (PIT) is clocked by the timersclk clock, providing a period from 122 µs to 8 seconds. The PIT function can be disabled if needed. See

Section 4.1.4, “Periodic Interrupt Timer (PIT) .”

Provides a time-of-day information to the operating system/application software. It is composed of a 45-bit counter and an alarm register. A maskable interrupt is generated when the counter reaches the value programmed in the alarm register. The time counter (TMCNT) is clocked by the timersclk clock. See

Section 4.1.3, “Time Counter (TMCNT) .”

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Figure 4-2 is a block diagram of the system configuration and protection logic.

Module Configuration Bus clock/8 timersclk Bus Monitors Periodic Interrupt Timer System Reset Core’s MCP TEA Interrupt Bus Clock Software Watchdog Timer System Reset Core’s MCP timersclk Time Counter Interrupt

Figure 4-2. System Configuration and Protection Logic

Many aspects of system configuration are controlled by several SIU module configuration registers,

described in Section 4.3.2, “System Configuration and Protection Registers.”

4.1.1

Bus Monitor

The MPC8280 has two bus monitors, one for the 60x bus and one for the local bus. The bus monitor ensures that each bus cycle is terminated within a reasonable period. The bus monitor does not count when the bus is idle. When a transaction starts (TS asserted), the bus monitor starts counting down from the time-out value. For standard bus transactions with an address tenure and a data tenure, the bus monitor counts until a data beat is acknowledged on the bus. It then reloads the time-out value and resumes the count down. This process continues until the whole data tenure is completed. Following the data tenure the bus monitor will idle in case there is no pending transaction; otherwise it will reload the time-out value and resume counting. For address-only transactions, the bus monitor counts until AACK is asserted. If the monitor times out for a standard bus transaction, transfer error acknowledge (TEA) is asserted. If the monitor times out for an address-only transaction, the bus monitor asserts AACK and a core machine check or reset interrupt is generated, depending on SYPCR[SWRI]. To allow variation in system peripheral response times, SYPCR[BMT] defines the time-out period, whose maximum value can be 2,040 system bus clocks. The timing mechanism is clocked by the system bus clock divided by eight.

4.1.2

Timers Clock

The two SIU timers (the time counter and the periodic interrupt timer) use the same clock source,

timersclk, which can be derived from several sources, as described in Figure 4-3 .

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The user should select external clock and/or BRG1 programming to yield either 4 MHz or 32 KHz at this point.

PC[26] Divide by 4 Divide by 512 Ports Programming CPM clock PISCR[PTF] timersclk for PIT timersclk for TMCNT PC[27] PC[29] BRG1 TMCNTSC[TCF] Ports Programming PC[25]

Figure 4-3. Timers Clock Generation

For details, see Section 41.2.4, “Port Pin Assignment Register (PPAR).”

For proper time counter operation, the user must ensure that the frequency of timersclk for TMCNT is 8,192 Hz by properly selecting the external clock and programming BRG1 and the prescaler control bits in the time counter status and control register (TMCNTSC[TCF]) and periodic interrupt status and control register (PISCR[PTF]).

4.1.3

Time Counter (TMCNT)

The time counter (TMCNT) is a 32-bit counter that is clocked by timersclk. It provides a time-of-day indication to the operating system and application software. The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset. It is initialized by the software; the user should set the timersclk frequency to 8,192 Hz, as explained in

Section 4.1.2, “Timers Clock.”

TMCNT can be programmed to generate a maskable interrupt when the time value matches the value in its associated alarm register. It can also be programmed to generate an interrupt every second. The time counter control and status register (TMCNTSC) is used to enable or disable the various timer functions and report the interrupt source.

Figure 4-4

shows a block diagram of TMCNT.

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timersclk for TMCNT (8,192 Hz) Divide by 8,192 32-Bit Counter

System Interface Unit (SIU)

SEC Interrupt = Alarm Interrupt 32-Bit Register

Figure 4-4. TMCNT Block Diagram

Section 4.3.2.15, “Time Counter Register (TMCNT),”

describes the time counter register.

4.1.4

Periodic Interrupt Timer (PIT)

The periodic interrupt timer consists of a 16-bit counter clocked by timersclk. The 16-bit counter decrements to zero when loaded with a value from the periodic interrupt timer count register (PITC); after the timer reaches zero, PISCR[PS] is set and an interrupt is generated if PISCR[PIE] = 1. At the next input clock edge, the value in the PITC is loaded into the counter and the process repeats. When a new value is loaded into the PITC, the PIT is updated, the divider is reset, and the counter begins counting. Setting PS creates a pending interrupt that remains pending until PS is cleared. If PS is set again before being cleared, the interrupt remains pending until PS is cleared. Any write to the PITC stops the current countdown and the count resumes with the new value in PITC. If PTE = 0, the PIT cannot count and retains the old count value. The PIT is not affected by reads.

Figure 4-5 is a block diagram of the PIT.

PISCR[PTE] PITC timersclk for PIT Clock Disable 16-Bit Modulus Counter PISCR[PS] PISCR[PIE]

Figure 4-5. PIT Block Diagram

The time-out period is calculated as follows: PITperiod = F timersclk = ------------------------ 8192 This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).

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System Interface Unit (SIU)

4.1.5

Software Watchdog Timer

The SIU provides the software watchdog timer option to prevent system lock in case the software becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the SYPCR,

described in Section 4.3.2.8, “System Protection Control Register (SYPCR).”

The software watchdog timer is enabled after reset to cause a hard reset if it times out. If the software watchdog timer is not needed, the user must clear SYPCR[SWE] to disable it. If used, the software watchdog timer requires a special service sequence to be executed periodically. Without this periodic servicing, the software watchdog timer times out and issues a reset or a nonmaskable interrupt, programmed in SYPCR[SWRI]. Once software writes SWRI, the state of SWE cannot be changed. The software watchdog timer service sequence consists of the following two steps: 1. Write 0x556C to the software service register (SWSR) 2. Write 0xAA39 to SWSR The service sequence clears the watchdog timer and the timing process begins again. If a value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over. Although the writes must occur in the correct order before a time-out, any number of instructions can be executed between the

writes. This allows interrupts and exceptions to occur between the two writes when necessary. Figure 4-6

shows a state diagram for the watchdog timer. Reset 0x556C/Don’t reload State 0 Waiting for 0x556C State 1 Waiting for 0xAA39 0xAA39/Reload Not 0x556C/Don’t reload Not 0xAA39/Don’t reload

Figure 4-6. Software Watchdog Timer Service State Diagram

Although most software disciplines permit or even encourage the watchdog concept, some systems require a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable range for the time-out period.

Figure 4-7

shows how to handle this need. 4-6

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SWSR Service Logic SYPCR[SWTC] SWE Bus Clock Clock Disable Divide By 2,048 MUX Reload 16-Bit SWR/Decrementer Rollover = 0 SWP Time-out Reset or MCP

Figure 4-7. Software Watchdog Timer Block Diagram

In Figure 4-7 , the range is determined by SYPCR[SWTC]. The value in SWTC is then loaded into a 16-bit

decrementer clocked by the system clock. An additional divide-by-2,048 prescaler is used when needed.

The decrementer begins counting when loaded with a value from SWTC. After the timer reaches 0x0, a software watchdog expiration request is issued to the reset or MCP control logic. Upon reset, SWTC is set to the maximum value and is again loaded into the software watchdog register (SWR), starting the process over. When a new value is loaded into SWTC, the software watchdog timer is not updated until the servicing sequence is written to the SWSR. If SYPCR[SWE] is loaded with 0, the modulus counter does not count.

4.2

Interrupt Controller

• • • • • • • Key features of the interrupt controller include the following: • Communications processor module (CPM) interrupt sources (FCCs, SCCs, MCCs, timers, SMCs, TC layers, I 2 C, IDMA, SDMA, and SPI) SIU interrupt sources (PIT, TMCNT, and PCI) 24 external sources (16 port C and 8 IRQ) Programmable priority between PIT, TMCNT, and PCI Programmable priority between SCCs, FCCs, and MCCs Two priority schemes for the SCCs: grouped, spread Programmable highest priority request Unique vector number for each interrupt source Freescale Semiconductor

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4.2.1

Interrupt Configuration

Figure 4-8 shows the MPC8280 interrupt structure. The interrupt controller receives interrupts from

internal sources, such as the PIT or TMCNT, from the CPM, the PCI bridge (with its own interrupt controller), and from external pins (port C parallel I/O pins).

Software watchdog timer Memory controller data errors PCI IRQ[0–7] 8 Bus monitor address only Fall/ Level IRQ[1–7] IRQ0 OR IRQ5 MCP CINT Port C[0–15]

Note

1 MPC8280 only 16 PCI TMCNT PIT Edge/ Fall Timer1 Timer2 Timer3 Timer4 FCC1 FCC2 FCC3 MCC1 1 MCC2 SCC1 SCC2 SCC3 USB/SCC4 SMC1 SMC2 SPI I2C IDMA1 IDMA2 IDMA3 IDMA4 SDMA RISC Timers TC layers 1

Figure 4-8. MPC8280 Interrupt Structure

G2_LE Core INT 4-8

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If the software watchdog timer is programmed to generate an interrupt, it always generates a machine check interrupt to the core. The external IRQ0 can generate MCP as well. Note that the core takes the machine check interrupt when MCP is asserted; it takes an external interrupt for any other interrupt asserted by the interrupt controller. The core will take the critical interrupt when CINT is asserted.

The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block event are also maskable.

All interrupt sources are prioritized and bits are set in the interrupt pending register (SIPNR). On the MPC8280, the prioritization of the interrupt sources is flexible in the following two aspects: • • The relative priority of the FCCs, SCCs, and MCCs can be modified One interrupt source can be assigned the highest priority When an unmasked interrupt source is pending in the SIPNR, the interrupt controller sends an interrupt request to the core. When an exception is taken, the interrupt mask bit in the machine state register (MSR[EE]) is cleared to disable further interrupt requests until software can handle them. The SIU interrupt vector register (SIVEC) is updated with a 6-bit vector corresponding to the sub-block with the highest current priority.

4.2.1.1

Machine Check Interrupt

There are several sources for a machine check interrupt (MCP): • • • • •

Software watchdog timer (when programmed to generate an interrupt—See “Software Watchdog Timer.”

)

Section 4.1.5,

IRQ0 signal (when the internal core is enabled) Memory controller for parity/ECC errors (see Section 10.2.6, “Machine Check Interrupt (MCP) Generation”) PCI bridge Bus monitor time out (on an address only transaction—see Section 4.1.1, “Bus Monitor”) When the internal core is enabled, these sources cause the interrupt controller to send a MCP to the core. When the core is disabled the MCP assertion is reflected on IRQ0/NMI_OUT so that an external core can serve it.

4.2.1.2

INT Interrupt

Besides the MCP sources listed above, other interrupts are taken by the core through the INT interrupt. If the internal core is disabled, INT is reflected on IRQ7/INT_OUT so that an external core can serve it. The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block event are also maskable.

4.2.2

Interrupt Source Priorities

The interrupt controller has 37 interrupt sources that assert one interrupt request to the core.

Table 4-2

shows prioritization of all interrupt sources. As described in following sections, flexibility exists in the Freescale Semiconductor

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relative ordering of the interrupts, but, in general, relative priorities are as shown. A single interrupt priority number is associated with each table entry.

Note that the group and spread options, shown with YCC entries in

Table 4-2 , are described in

Section 4.2.2.1, “SCC, FCC, and MCC Relative Priority.”

Table 4-2. Interrupt Source Priority Levels Priority Level

17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Interrupt Source Description Multiple Events

Highest XSIU1 — No (TMCNT,PIT,PCI = Yes) XSIU2 (Grouped) XSIU3 (Grouped) XSIU4 (Grouped) No (TMCNT,PIT,PCI = Yes) No (TMCNT,PIT,PCI = Yes) No (TMCNT,PIT,PCI XCC1 Yes = Yes) XCC2 XCC3 XCC4 XSIU2 (Spread) Yes Yes Yes No (TMCNT,PIT,PCI = Yes) XCC5 XCC6 XCC7 XCC8 XSIU5 (Grouped) XSIU6 (Grouped) XSIU7 (Grouped) XSIU8 (Grouped) Yes Yes Yes Yes No (TMCNT,PIT,PCI = Yes) No (TMCNT,PIT,PCI = Yes) No (TMCNT,PIT,PCI = Yes) No (TMCNT,PIT,PCI = Yes) XSIU3 (Spread) YCC1 (Grouped) YCC2 (Grouped) YCC3 (Grouped) YCC4 (Grouped) YCC5 (Grouped) YCC6 (Grouped) YCC7 (Grouped) No (TMCNT,PIT,PCI = Yes) Yes Yes Yes Yes Yes Yes Yes 4-10

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System Interface Unit (SIU) Table 4-2. Interrupt Source Priority Levels (continued) Priority Level

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Interrupt Source Description

YCC8 (Grouped) XSIU4 (Spread) Parallel I/O–PC15 Timer 1 Parallel I/O–PC14 YCC1 (Spread) Parallel I/O–PC13 SDMA Bus Error USB IDMA1 YCC2 (Spread) Parallel I/O–PC12 Parallel I/O–PC11 IDMA2 Timer 2 Parallel I/O–PC10 XSIU5 (GSIU = 1) YCC3 (Spread) RISC Timer Table I2C YCC4 (Spread) Parallel I/O–PC9 Parallel I/O–PC8 IRQ6 IDMA3 IRQ7 Timer 3 XSIU6 (GSIU = 1) YCC5 (Spread) Parallel I/O–PC7 Parallel I/O–PC6 Parallel I/O–PC5 Timer 4

Multiple Events

Yes No (TMCNT,PIT,PCI = Yes) Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No No (TMCNT,PIT,PCI = Yes) Yes Yes Yes Yes No No No Yes No Yes No (TMCNT,PIT,PCI = Yes) Yes No No No Yes Freescale Semiconductor

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System Interface Unit (SIU) Table 4-2. Interrupt Source Priority Levels (continued) Priority Level

60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Interrupt Source Description

YCC6 (Spread) Parallel I/O–PC4 XSIU7 (GSIU = 1) IDMA4 SPI Parallel I/O–PC3 Parallel I/O–PC2 SMC1 YCC7 (spread) SMC2 Parallel I/O–PC1 Parallel I/O–PC0 XSIU8 (GSIU = 1) YCC8(spread) Reserved

Multiple Events

Yes No No (TMCNT,PIT,PCI = Yes) Yes Yes No No Yes Yes Yes No No No (TMCNT,PIT,PCI = Yes) Yes — Notice the lack of SDMA interrupt sources, which are reported through each individual FCC, SCC, SMC, SPI, or I 2 C channel. The only true SDMA interrupt source is the SDMA channel bus error entry that is reported when a bus error occurs during an SDMA access. There are two ways to add flexibility to the table of CPM interrupt priorities—the FCC, MCC, and SCC relative priority option, described in

Section 4.2.2.1, “SCC, FCC, and MCC Relative Priority,”

and the highest priority option, described in

Section 4.2.2.3, “Highest Priority Interrupt.”

4.2.2.1

SCC, FCC, and MCC Relative Priority

The relative priority between the four SCCs, three FCCs, and MCC is programmable and can be changed dynamically. In

Table 4-2 there is no entry for SCC1–SCC4, MCC1–MCC2, FCC1–FCC3, but rather there

are entries for XCC1–XCC8 and YCC1–YCC8. Each SCC can be mapped to any YCC location and each FCC and MCC can be mapped to any XCC location. The SCC, FCC, and MCC priorities are programmed in the CPM interrupt priority registers (SCPRR_H and SCPRR_L) and can be changed dynamically to implement a rotating priority.

In addition, the grouping of the locations of the YCC entries has the following two options • Group. In the group scheme, all SCCs are grouped together at the top of the priority table, ahead of most other CPM interrupt sources. This scheme is ideal for applications where all SCCs, FCCs, and MCCs function at a very high data rate and interrupt latency is very important. 4-12

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• Spread. In the spread scheme, priorities are spread over the table so other sources can have lower interrupt latencies. This scheme is also programmed in the SICR but cannot be changed dynamically.

4.2.2.2

PIT, TMCNT, PCI, and IRQ Relative Priority

The MPC8280 has seven general-purpose interrupt requests (IRQs), five of which, with the PIT, the PCI interrupt controller, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have fixed priority.

4.2.2.3

Highest Priority Interrupt

In addition to the FCC/MCC/SCC relative priority option, SICR[HP] can be used to specify one interrupt source as having highest priority. This interrupt remains within the same interrupt level as the other interrupt controller interrupts, but is serviced before any other interrupt in the table. If the highest priority feature is not used, select the interrupt request in XSIU1 to be the highest priority interrupt; the standard interrupt priority order is used. SICR[HP] can be updated dynamically to allow the user to change a normally low priority source into a high priority-source for a certain period.

4.2.3

Masking Interrupt Sources

By programming the SIU mask registers, SIMR_H and SIMR_L, the user can mask interrupt requests to the core. Each SIMR bit corresponds to an interrupt source. To enable an interrupt, set the corresponding SIMR bit. When a masked interrupt source has a pending interrupt request, the corresponding SIPNR bit is set, even though the interrupt is not generated to the core. The user can mask all interrupt sources to implement a polling interrupt servicing scheme. When an interrupt source has multiple interrupting events, the user can individually mask these events by programming a mask register within that block.

Table 4-2

shows which interrupt sources have multiple interrupting events.

Figure 4-9 shows an example of how the masking occurs, using an SCC as an example.

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SCCE Event Bit Mask Bit SCCM SIPNR 13 Input (or 13 Event Bits) Mask Bit SIMR (Other Unmasked Requests) Request to the core

Figure 4-9. Interrupt Request Masking

4.2.4

Interrupt Vector Generation and Calculation

Pending unmasked interrupts are presented to the core in order of priority. The interrupt vector that allows the core to locate the interrupt service routine is made available to the core by reading SIVEC. The interrupt controller passes an interrupt vector corresponding to the highest-priority, unmasked, pending interrupt.

Table 4-3 lists encodings for the six low-order bits of the interrupt vector.

Table 4-3. Encoding the Interrupt Vector Interrupt Number

4 5 0 1 2 3

Interrupt Source Description

Error (No interrupt) I 2 C SPI RISC Timers SMC1 SMC2

Interrupt Vector

0b00_0000 0b00_0001 0b00_0010 0b00_0011 0b00_0100 0b00_0101 4-14

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System Interface Unit (SIU) Table 4-3. Encoding the Interrupt Vector (continued) Interrupt Number

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26–31 32 33 34 35 36 37 38 39 40 41 42 43

Interrupt Source Description

IDMA1 IDMA2 IDMA3 IDMA4 SDMA USB Timer1 Timer2 Timer3 Timer4 TMCNT PIT PCI IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Reserved FCC1 FCC2 FCC3 Reserved MCC1 1 MCC2 Reserved Reserved SCC1 SCC2 SCC3 SCC4

Interrupt Vector

0b00_0110 0b00_0111 0b00_1000 0b00_1001 0b00_1010 0b00_1011 0b00_1100 0b00_1101 0b00_1110 0b00_1111 0b01_0000 0b01_0001 0b01_0010 0b01_0011 0b01_0100 0b01_0101 0b01_0110 0b01_0111 0b01_1000 0b01_1001 0b01_1010–01_1111 0b10_0000 0b10_0001 0b10_0010 0b10_0011 0b10_0100 0b10_0101 0b10_0110 0b10_0111 0b10_1000 0b10_1001 0b10_1010 0b10_1011 Freescale Semiconductor

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System Interface Unit (SIU) Interrupt Number

44 45–47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 MPC8280 only.

Table 4-3. Encoding the Interrupt Vector (continued) Interrupt Source Description

TC Layer 1 Reserved PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Interrupt Vector

0b10_1100 0b10_11xx 0b11_0000 0b11_0001 0b11_0010 0b11_0011 0b11_0100 0b11_0101 0b11_0110 0b11_0111 0b11_1000 0b11_1001 0b11_1010 0b11_1011 0b11_1100 0b11_1101 0b11_1110 0b11_1111 Note that the interrupt vector table differs from the interrupt priority table in only two ways: • • FCC, SCC, and MCC vectors are fixed; they are not affected by the SCC group mode, spread mode, or the relative priority order of the FCCs, SCCs, and MCC. An error vector exists as the last entry in

Table 4-3 . The error vector is issued when no interrupt is

requesting service.

4.2.4.1

Port C External Interrupts

There are 16 external interrupts, coming from the parallel I/O port C pins, PC[0–15]. When ones of these pins is configured as an input, a change according to the SIU external interrupt control register (SIEXR) causes an interrupt request signal to be sent to the interrupt controller. PC[0–15] lines can be programmed to assert an interrupt request upon any change. Each port C line asserts a unique interrupt request to the interrupt pending register and has a different internal interrupt priority level within the interrupt controller. Requests can be masked independently in the interrupt mask register (SIMR). Notice that the global SIMR is cleared on system reset so pins left floating do not cause false interrupts.

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4.3

Programming Model

The SIU registers are grouped into the following three categories: • • • Interrupt controller registers. These registers control configuration, prioritization, and masking of interrupts. They also include registers for determining the interrupt sources. These registers are

described in Section 4.3.1, “Interrupt Controller Registers.”

System configuration and protection registers. These include registers for configuring the SIU, defining the base address for the internal memory map, configuring the watchdog timer, specifying bus characteristics, as well as general functionality of the 60x, and local buses such as arbitration,

error status, and control. These registers are described in Section 4.3.2, “System Configuration and Protection Registers.”

Periodic interrupt registers. These include registers for configuring and providing status for periodic interrupts. See

Section 4.3.3, “Periodic Interrupt Registers.”

4.3.1

Interrupt Controller Registers

There are seven interrupt controller registers, described in the following sections: • • • • • • •

Section 4.3.1.1, “SIU Interrupt Configuration Register (SICR)”

Section 4.3.1.2, “SIU Interrupt Priority Register (SIPRR)”

Section 4.3.1.3, “CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)”

Section 4.3.1.4, “SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)”

Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L)”

Section 4.3.1.6, “SIU Interrupt Vector Register (SIVEC)”

Section 4.3.1.7, “SIU External Interrupt Control Register (SIEXR)”

4.3.1.1

SIU Interrupt Configuration Register (SICR)

The SIU interrupt configuration register (SICR), shown in Figure 4-10 , defines the highest priority

interrupt and whether interrupts are grouped or spread in the priority table,

Table 4-2

. Field Reset R/W Addr 0 — 1 2 7 8 HP — 0000_0000_0000_0000 R/W 0x10C00

Figure 4-10. SIU Interrupt Configuration Register (SICR)

13 14 GSIU 15 SPS Freescale Semiconductor

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System Interface Unit (SIU)

The SICR register bits are described in Table 4-4

.

Table 4-4. SICR Field Descriptions Bits

0–1 2–7 8–13 14 15

Name Description

— HP Reserved, should be cleared.

Highest priority. Specifies the 6-bit interrupt number of the single interrupt controller interrupt source that is advanced to the highest priority in the table. HP can be modified dynamically. To retain the original priority, program HP to the interrupt number assigned to XSIU1. Port C interrupts have a fixed priority level and cannot be advanced to the highest priority level.

Reserved, should be cleared.

— GSIU Group SIU. Selects the relative XSIU priority scheme. It cannot be changed dynamically.

0 Grouped. The XSIUs are grouped by priority at the top of the table.

1 Spread. The XSIUs are spread by priority in the table.

SPS Spread priority scheme. Selects the relative YCC priority scheme. It cannot be changed dynamically.

0 Grouped. The YCCs are grouped by priority at the top of the table.

1 Spread. The YCCs are spread by priority in the table.

4.3.1.2

SIU Interrupt Priority Register (SIPRR)

The SIU interrupt priority register (SIPRR), shown in Figure 4-11

, defines the priority between IRQ1–IRQ5, PIT, PCI, and TMCNT.

Field Reset R/W Addr 0 XS1P 000 2 3 XS2P 001 5 6 8 XS3P 010 R/W 0x10C10 9 XS4P 011 11 Field Reset R/W Addr 16 XS5P 100 18 19 XS6P 101 21 22 24 XS7P 110 R/W 0x10C12 25 XS8P 111 27

Figure 4-11. SIU Interrupt Priority Register (SIPRR)

12 28 — 0000 — 0000 15 31 4-18

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System Interface Unit (SIU)

The SIPRR register bits are described in Table 4-5 .

Table 4-5. SIPRR Field Descriptions Bits

0–2 3–11, 16–27 12–15, 28–31

Name Description

XS1P–XSIU1 Priority order. Defines which PIT/TMCNT/PCI/IRQs asserts its request in the XSIU1 priority position. The user should not program the same PIT/TMCNT/PCI/IRQs to more than one priority position (1–8). These bits can be changed dynamically.

000 TMCNT asserts its request in the XSIU1 position.

001 PIT asserts its request in the XSIU1 position.

010 PCI asserts its request in the XSIU1 position.

011 IRQ1 asserts its request in the XSIU1 position.

100 IRQ2 asserts its request in the XSIU1 position.

101 IRQ3 asserts its request in the XSIU1 position.

110 IRQ4 asserts its request in the XSIU1 position.

111 IRQ5 asserts its request in the XSIU1 position.

XS2P– XS8P Same as XS1P, but for XSIU2–XSIU8.

— Reserved, should be cleared.

4.3.1.3

CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)

The CPM high interrupt priority register (SCPRR_H), shown in

Figure 4-12

, define priorities between the FCCs and MCCs. 15 Field Reset R/W Addr 0 XC1P 000 2 3 XC2P 001 5 6 8 XC3P 010 R/W 0x10C14 9 XC4P 011 11 12 Field Reset R/W Addr 16 XC5P 100 18 19 XC6P 101 21 22 24 XC7P 110 R/W 0x10C16 25 XC8P 111 27 28

Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)

— 0000 — 0000 31 Freescale Semiconductor

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System Interface Unit (SIU)

Table 4-6

describes SCPRR_H fields.

Table 4-6. SCPRR_H Field Descriptions Bits Name Description

0–2 3–11 12–15 XC1P–XCC1 Priority order. Defines which FCC/MCC asserts its request in the XCC1 priority position. The user should not program the same FCC/MCC to more than one priority position (1–8). These bits can be changed dynamically.

000 FCC1 asserts its request in the XCC1 position.

001 FCC2 asserts its request in the XCC1 position.

010 FCC3 asserts its request in the XCC1 position.

011 XCC1 position not active.

100 MCC1 asserts its request in the XCC1 position.

1 101 MCC2 asserts its request in the XCC1 position.

110 XCC1 position not active.

111 XCC1 position not active.

XC2P–XC4P — Same as XC1P, but for XCC2–XCC4 Reserved, should be cleared.

16–27 XC5P–XC8P 28–31 — 1 MPC8280 only.

Same as XC1P, but for XCC5–XCC8 Reserved, should be cleared.

The CPM low interrupt priority register (SCPRR_L), shown in

Figure 4-13

, defines prioritization of SCCs and TC layer.

Field Reset R/W Addr 0 YC1P 000 2 3 YC2P 001 5 6 8 YC3P 010 R/W 0x10C18 9 YC4P 011 11 12 Field Reset R/W Addr 16 YC5P 100 18 19 YC6P 101 21 22 YC7P 110 R/W 24 25 YC8P 111 27 28 0x10C20

Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L)

— 0000 — 0000 15 31 4-20

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System Interface Unit (SIU)

Table 4-7

describes SCPRR_L fields.

Table 4-7. SCPRR_L Field Descriptions Bits Name Description

0–2 YC1P–YCC1 Priority order. Defines which SCC asserts its request in the YCC1 priority position. Do not program the same SCC to multiple priority positions. This field can be changed dynamically.

000 SCC1 asserts its request in the YCC1 position.

001 SCC2 asserts its request in the YCC1 position.

010 SCC3 asserts its request in the YCC1 position.

011 SCC4 asserts its request in the YCC1 position.

100 TC layer asserts its request in the YCC1 position (MPC8280 only. Reserved on other devices.) 1XX YCC1 position is not active.

3–11 YC2P–YC8P Same as YC1P, but for YCC2–YCC8 12–15 — Reserved, should be cleared.

16–27 YC5P–YC8P Same as YC1P, but for YCC5–YCC8 28–31 — Reserved, should be cleared.

4.3.1.4

SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)

Each bit in the interrupt pending registers (SIPNR_H and SIPNR_L), shown in

Figure 4-14 and

Figure 4-15 , corresponds to an interrupt source. When an interrupt is received, the interrupt controller sets

the corresponding SIPNR bit.

0 Field PC0 1 PC1 2 PC2 3 PC3 4 PC4 5 PC5 6 PC6 7 PC7 8 PC8 9 10 11 12 PC9 PC10 PC11 PC12 13 PC13 14 15 PC14 PC15 Reset R/W Addr Undefined (the user should write 1s to clear these bits before using) R/W 0x10C08 Field Reset 16 — 17 18 19 20 21 22 23 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 24 — Undefined (the user should write 1s to clear these bits before using) 28 29 TMCNT 0 1 30 PIT 0 1 R/W R/W Addr 0x10C10 1 These fields are zero after reset because their corresponding mask register bits are cleared (disabled).

Figure 4-14. SIPNR_H

31 PCI 0 1 Freescale Semiconductor

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System Interface Unit (SIU)

Figure 4-15 shows SIPNR_L fields.

0 1 2 Field FCC1 FCC2 FCC3 Reset R/W Addr 3 — 4 5 MCC1 2 MCC2 6 — 7 8 9 0000_0000_0000_0000 1 10 11 SCC1 SCC2 SCC3 SCC4 R/W 0x10C0C 12 TC 2 13 — 15 16 Field I2C 17 SPI 18 19 20 21 22 23 24 25 RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA 0000_0000_0000_000 1 26 — 27 28 29 30 31 TIMER1 TIMER2 TIMER3 TIMER4 — 0 1 Reset R/W R/W Addr 0x10C0E 1 These fields are zero after reset because their corresponding mask register bits are cleared (disabled).

2 MPC8280 only. Reserved on all other devices.

Figure 4-15. SIPNR_L

When a pending interrupt is handled, the user clears the corresponding SIPNR bit. However, if an event register exists, the unmasked event register bits should be cleared instead, causing the SIPNR bit to be cleared. SIPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing zeros to this register has no effect. Note that the SCC/FCC/MCC SIPNR bit positions are not changed according to their relative priority.

4.3.1.5

SIU Interrupt Mask Registers (SIMR_H and SIMR_L)

Each bit in the SIU interrupt mask register (SIMR) corresponds to a interrupt source. The user masks an interrupt by clearing and enables an interrupt by setting the corresponding SIMR bit. When a masked interrupt occurs, the corresponding SIPNR bit is set, regardless of the SIMR bit although no interrupt request is passed to the core. If an interrupt source requests interrupt service when the user clears its SIMR bit, the request stops. If the user sets the SIMR bit later, a previously pending interrupt request is processed by the core, according to its assigned priority. The SIMR can be read by the user at any time.

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System Interface Unit (SIU)

Figure 4-16 shows the SIMR_H register.

0 Field PC0 1 PC1 2 PC2 3 PC3 4 PC4 5 PC5 6 PC6 7 PC7 8 PC8 9 10 11 12 PC9 PC10 PC11 PC12 Reset R/W Addr 0000_0000_0000_0000 R/W 0x10C1C 13 PC13 14 15 PC14 PC15 28 29 TMCNT 30 PIT 31 PCI Field 16 — Reset R/W Addr 17 18 19 20 21 22 23 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 24 0000_0000_0000_0000 R/W 0x10C1E —

Figure 4-16. SIMR_H

Figure 4-17 shows SIMR_L.

0 1 2 Field FCC1 FCC2 FCC3 Reset R/W Addr 3 — 4 5 MCC1 1 MCC2 6 — 7 8 9 SCC1 SCC2 SCC3 0000_0000_0000_0000 10 11 SCC4 R/W 0x10C20 12 TC 1 13 — 15 16 Field I2C Reset R/W 17 SPI 18 19 20 21 Addr 2 MPC8280 only. Reserved on the other devices.

22 23 24 25 RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA 0000_0000_0000_0000 R/W 0x10C22

Figure 4-17. SIMR_L

26 — 27 28 29 30 31 TIMER1 TIMER2 TIMER3 TIMER4 — Note the following: • • • SCC/TC/MCC/FCC SIMR bit positions are not affected by their relative priority. The user can clear pending register bits that were set by multiple interrupt events only by clearing all unmasked events in the corresponding event register. If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to the core, the error vector is issued (if no other interrupts pending). Thus, the user should always include an error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.

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System Interface Unit (SIU) 4.3.1.6

SIU Interrupt Vector Register (SIVEC)

The SIU interrupt vector register (SIVEC), shown in Figure 4-18 , contains an 8-bit code representing the

unmasked interrupt source of the highest priority level. Field Reset R/W Addr 0 Interrupt Code 5 6 0 7 0 8 0 9 0 0000_0000_0000_0000 R 0x10C04 10 0 11 0 12 0 13 0 14 0 15 0 Field Reset R/W Addr 16 0 17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 0000_0000_0000_0000 R 0x10C06 26 0 27 0

Figure 4-18. SIU Interrupt Vector Register (SIVEC)

28 0 29 0 30 0 31 0 The SIVEC can be read as either a byte, half word, or a word. When read as a byte, a branch table can be used in which each entry contains one instruction (branch). When read as a half word, each entry can contain a full routine of up to 256 instructions. The interrupt code is defined such that its two lsbs are zeroes, allowing indexing into the table, as shown in

Figure 4-19 .

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INTR: • • • Save state R3 <- @ SIVEC R4 <-- BASE OF BRANCH TABLE • • • lbz add mtspr bctr RX, R3 (0) RX, RX, R4 CTR, RX # load as byte INTR: • • • Save state R3 <- @ SIVEC R4 <-- BASE OF BRANCH TABLE • • • lhz add mtspr bctr RX, R3 (0) RX, RX, R4 CTR, RX # load as half BASE BASE + 4 BASE + 8 BASE + C BASE +10 BASE + n b Routine1 b Routine2 b Routine3 b Routine4 • • BASE BASE + 400 BASE + 800 BASE + C00 BASE +1000 BASE + n 1st Instruction of Routine1 • 1st Instruction of Routine2 • 1st Instruction of Routine3 • 1st Instruction of Routine4 • • • • •

Figure 4-19. Interrupt Table Handling Example NOTE

The MPC8280 differs from previous MPC8xx implementations in that when an interrupt request occurs, SIVEC can be read. If there are multiple interrupt sources, SIVEC latches the highest priority interrupt. Note that the value of SIVEC cannot change while it is being read.

4.3.1.7

SIU External Interrupt Control Register (SIEXR)

Each defined bit in the SIU external interrupt control register (SIEXR), shown in

Figure 4-20 , determines

whether the corresponding port C line asserts an interrupt request upon either a high-to-low change or any change on the pin. External interrupts can come from port C (PC[0-15]). Freescale Semiconductor

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System Interface Unit (SIU)

0 1 2 3 4 5 6 7 8 9 10 Field EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC 10 11 EDPC 11 12 EDPC 12 13 EDPC 13 14 EDPC 14 15 EDPC 15 Reset 0000_0000_0000_0000 R/W Addr R/W 0x10C24 31 16 Field EDI0 17 EDI1 18 EDI2 19 EDI3 20 EDI4 21 EDI5 22 EDI6 23 EDI7 Reset R/W R/W 24 0000_0000_0000_0000 Addr 0x10C26 — R

Figure 4-20. SIU External Interrupt Control Register (SIEXR)

Table 4-8

describes SIEXR fields.

Table 4-8. SIEXR Field Descriptions Bits Name Description

0–15 16–23 EDPCx EDIx Edge detect mode for port Cx. The corresponding port C line (PCx) asserts an interrupt request according to the following: 0 Any change on PCx generates an interrupt request.

1 High-to-low change on PCx generates an interrupt request.

Edge detect mode for IRQ x. The corresponding IRQ line (IRQx) asserts an interrupt request according to the following: 0 Low assertion on IRQ x generates an interrupt request.

1 High-to-low change on IRQ x generates an interrupt request.

4.3.2

System Configuration and Protection Registers

The system configuration and protection registers are described in the following sections.

4.3.2.1

Bus Configuration Register (BCR)

The bus configuration register (BCR), shown in

Figure 4-21

, contains configuration bits for various features and wait states on the 60x bus.

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System Interface Unit (SIU)

Field 0 EBM Reset note 1 R/W 1 APD 3 4 L2C 5 L2D 7 8 9 PLDP DREF 10 DAM 11 12 13 14 15 EAV ETM LETM EPAR LEPAR 000_0000_0000_0000 R/W Field Reset 16 NPQM 18 19 — 20 21 22 EXDD LPLDP 0000_0000_000 — 25 26 27 SPAR ISPS note 1 28 R/W R/W Addr 0x10024 1

Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word

.”

Figure 4-21. Bus Configuration Register (BCR)

Figure 4-9 describes BCR fields.

Table 4-9. BCR Field Descriptions Bits

0 1–3 4 5–7 8 9 10 — 0000 31

Name Description

EBM APD External bus mode. 0 Single MPC8280 bus mode is assumed 1 60x-compatible bus mode. For more information refer to

Section 8.2, “Bus Configuration

.” Address phase delay. Specifies the number of address tenure wait states for address operations initiated by a 60x bus master. BCR[APD] specifies the number of address tenure wait states for address operations initiated by 60x-bus devices. APD indicates how many cycles the MPC8280 should wait for ARTRY, but because it is assumed that ARTRY can be asserted (by other masters) only on cachable address spaces, APD is considered only on transactions that hit one of the 60x-assigned memory controller banks and have the GBL signal asserted during address phase.

L2C Secondary cache controller. See

Chapter 12, “Secondary (L2) Cache Support .”

0 No secondary cache controller is assumed. 1 An external secondary cache controller is assumed.

L2 cache hit delay. Controls the number of clock cycles from the assertion of TS until HIT is valid.

L2D PLDP Pipeline maximum depth. See

Section 8.4.5, “Pipeline Control .”

0 The pipeline maximum depth is one.

1 The pipeline maximum depth is zero.

DREF Disable reflection. Disables reflection of system bus reflection on external pins of internal transfers on 60x bus.

0 Enable reflection 1 Disable reflection DAM Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM). This bit is similar to BCR[EXDD] but with opposite polarity.

0 The memory controller inserts one wait state between the assertion of TS and the assertion of CS when external master accesses an address space controlled by the memory controller.

1 The memory controller asserts CS on the cycle following the assertion of TS by external master accessing an address space controlled by the memory controller.

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System Interface Unit (SIU) Table 4-9. BCR Field Descriptions (continued) Bits Name Description

11 12 13 14 EAV ETM Enable address visibility. Normally, when the MPC8280 is in single-MPC8280 bus mode, the bank select signals for SDRAM accesses are multiplexed on the 60x bus address lines. So, for SDRAM accesses, the internal address is not visible for debug purposes. However the bank select signals can also be driven on dedicated pins (see SIUMCR[APPC]). In this case EAV can be used to force address visibility.

0 Bank select signals are driven on 60x bus address lines. There is no full address visibility.

1 Bank select signals are not driven on address bus. During READ and WRITE commands to SDRAM devices, the full address is driven on 60x bus address lines.

Compatibility mode enable. See

Section 8.4.3.8, “Extended Transfer Mode .”

0 Strict 60x bus mode. Extended transfer mode is disabled. 1 Extended transfer mode is enabled.

LETM Local bus compatibility mode enable. See

Section 8.4.3.8, “Extended Transfer Mode

.” 0 Extended transfer mode is disabled on the local bus. 1 Extended transfer mode is enable on the local bus. Note that if the local bus memory controller is configured to work with read-modify-write parity, LETM must be cleared.

EPAR Even parity. Determines odd or even parity on the 60x bus. 0 Odd parity 1 Even parity Writing the memory with EPAR = 1 and reading the memory with EPAR = 0 generates parity errors for testing.

15 LEPAR Local bus even parity. Determines odd or even parity on the local bus. 0 Odd parity 1 Even parity Writing the memory with LEPAR = 1 and reading the memory with LEPAR = 0 generates parity errors for testing.

16–18 NPQM Non MPC8280 master. Identifies the type of bus masters which are connected to the arbitration lines when the MPC8280 is in internal arbiter mode. Possible types are MPC8280 master and non-MPC8280 master. This field is related to the data pipelining bits (BRx[DR]) in the memory controller. Because an external bus master that is not a MPC8280 cannot use the data pipelining feature, the MPC8280, which controls the memory, needs to know when a non-MPC8280 master is accessing the memory and handle the transaction differently.

NPQM[0] designates the type of master connected to the set of pins BR, BG, and DBG. NPQM[1] designates the type of master connected to the set of pins EXT_BR2, EXT_BG2, and EXT_DBG2. NPQM[2] designates the type of master which is connected to the set of pins EXT_BR3, EXT_BG3 and EXT_DBG3 0 The bus master connected to the arbitration lines is a MPC8280.

1 The bus master connected to the arbitration lines is not a MPC8280.

19–20 — Reserved, should be cleared. 4-28

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System Interface Unit (SIU) Table 4-9. BCR Field Descriptions (continued) Bits Name Description

21 EXDD External master delay disable. Generally, the MPC8280 adds one clock cycle delay for each external master access to a region controlled by the memory controller. This occurs because the external master drives the address on the external pins (compared to internal master, like the MPC8280’s DMA, which drives the address on an internal bus in the chip). Thus, it is assumed that an additional cycle is needed for the memory controllers banks to complete the address match. However in some cases (when the bus is operated in low frequency), this extra cycle is not needed. The user can disable the extra cycle by setting EXDD.

0 The memory controller inserts one wait state between the assertion of TS and the assertion of CS when external master accesses an address space controlled by the memory controller.

1 The memory controller asserts CS on the cycle following the assertion of TS by external master accessing an address space controlled by the memory controller.

22 23–25 26 LPLDP Local bus pipeline maximum depth. See

Section 8.4.5, “Pipeline Control

.” 0 The local bus pipeline maximum depth is one.

1 The local bus pipeline maximum depth is zero.

— Reserved, should be cleared.

SPAR Slave parity check. If set enables parity check on 60x bus transactions to the MPC8280's internal memory space. In case of a parity error a core machine check is asserted and the error is reported in TESCR1[ISBE,PAR] and TESCR2[REGS,DPR,PCI0,PCI1,LCL].

27 ISPS 28–31 — Internal space port size. Defines the port size of MPC8280’s internal space region as seen to external masters. Setting ISPS enables a 32-bit master to access MPC8280 internal space.

0 MPC8280 acts as a 64-bit slave to external masters accesses to its internal space.

1 MPC8280 acts as a 32-bit slave to external masters accesses to its internal space.

Reserved, should be cleared.

4.3.2.2

60x Bus Arbiter Configuration Register (PPC_ACR)

The 60x bus arbiter configuration register (PPC_ACR), shown in

Figure 4-22 , defines the arbiter modes

and parked master on the 60x bus.

Field Reset R/W 0 — 1 000 2 DBGD 3 EARB 1 See note R/W 4 PRKM 0010 Addr 0x10028 1 Depends on reset configuration sequence. See

Section 5.4.1, “Hard Reset Configuration Word .”

Figure 4-22. PPC_ACR

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System Interface Unit (SIU)

Table 4-10

describes PPC_ACR fields.

Table 4-10. PPC_ACR Field Descriptions Bits

0–1 2 3 4–7

Name Description

— DBGD EARB PRKM Reserved, should be cleared.

Data bus grant delay. Specifies the minimum number of data tenure wait states for 60x bus master-initiated data operations. This is the minimum delay between TS and DBG. 0 DBG is asserted with TS if the data bus is free. 1 DBG is asserted one cycle after TS if the data bus is not busy. See

Section 8.5.1, “Data Bus Arbitration .”

External arbitration.

0 Internal arbitration is performed. See Section 8.3.1, “Arbitration Phase .”

1 External arbitration is assumed. Parking master. 0000 CPM high request level refers to the IDMA which involves peripherals and the following serial channels (SCC, SPI, SMC, and I 2 C) 0001 CPM middle request level refers to all other serial channels (FCCs and MCCs) 0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See

Section 30.7.1, “FCC Function Code Registers (FCRx)

.”) 0011 PCI request level. Reserved on all other devices.

0100 Reserved 0101 Reserved 0110 Internal core 0111 External master 1 1000 External master 2 1001 External master 3 Values 1010–1111 are reserved.

4.3.2.3

60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)

The 60x bus arbitration-level registers, shown in

Figure 4-23

and Figure 4-24 , define arbitration priority

of MPC8280 bus masters. Priority field 0 has highest-priority. For information about MPC8280 bus master indexes, see the description of PPC_ACR[PRKM] in

Table 4-10 .

0 3 Field Reset R/W Addr Priority Field 0 0000 Field Reset R/W Addr 16 Priority Field 4 0011 19 4 7 8 11 Priority Field 1 0001 Priority Field 2 0010 R/W 0x1002C 20 23 24 Priority Field 5 0100 Priority Field 6 0101 R/W 0x1002E

Figure 4-23. PPC_ALRH

27 12 Priority Field 3 0110 15 28 Priority Field 7 0111 31 4-30

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PPC_ALRL, shown in

Figure 4-24

, defines arbitration priority of 60x bus masters 8–15. Priority field 0 is the highest-priority arbitration level. For information about the MPC8280 bus master indexes, see the description of PPC_ACR[PRKM] in

Table 4-10 .

0 3 Field Reset R/W Addr Priority Field 8 1000 Field Reset R/W Addr 16 Priority Field 12 1100 19 4 Priority Field 9 1001 7 8 Priority Field 10 1010 11 R/W 0x10030 20 23 24 Priority Field 13 1101 Priority Field 14 1110 R/W 0x10032

Figure 4-24. PPC_ALRL

27 12 Priority Field 11 1011 15 28 Priority Field 15 1111 31

4.3.2.4

Local Bus Arbiter Configuration Register (LCL_ACR)

The local bus arbiter configuration register (LCL_ACR), shown in Figure 4-25 , defines the arbiter modes

and the parked master on the local bus. Field Reset R/W Addr 0 — 1 2 DBGD 3 — 0000_0010 R/W 0x10034 4

Figure 4-25. LCL_ACR

Table 4-11

describes LCL_ACR register bits.

Table 4-11. LCL_ACR Field Descriptions

PRKM

Bits

0–1 2 3

Name Description

— — Reserved, should be cleared.

DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for PowerPC master-initiated data operations. This is the minimum delay between TS and DBG. 0 DBG is asserted with TS if the data bus is free. 1 DBG is asserted one cycle after TS if the data bus is not busy. See

Section 8.5.1, “Data Bus Arbitration

.” Reserved, should be cleared.

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System Interface Unit (SIU) Table 4-11. LCL_ACR Field Descriptions (continued) Bits

4–7

Name Description

PRKM Parking master. Defines the parked master. 0000 CPM high request level refers to the IDMA which involves peripherals and the following serial channels (SCC, SPI, SMC, and I 2 C) 0001 CPM middle request level refers to all other serial channels (FCCs and MCCs) 0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See Section 28.7.1, “FCC Function Code Registers (FCRx).” 0011 Host bridge Values 0100–1111 are reserved.

4.3.2.5

Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)

The local bus arbitration level registers (LCL_ALRH and LCL_ALRL), shown in

Figure 4-26 and

Figure 4-27 , define arbitration priority for local bus masters 0–7. Priority field 0 has highest-priority. For

information about the MPC8280 local bus master indexes see LCL_ACR[PRKM] in Table 4-11 .

0 3 Field Reset R/W Addr Priority Field 0 0000 Field Reset R/W Addr 16 Priority Field 4 0011 19 4 7 8 11 Priority Field 1 0001 Priority Field 2 0010 R/W 0x10038 20 23 24 Priority Field 5 0100 Priority Field 6 0101 R/W 0x10040

Figure 4-26. LCL_ALRH

27 12 Priority Field 3 0110 15 28 Priority Field 7 0111 31 4-32

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LCL_ALRL, shown in

Figure 4-27

, defines arbitration priority of MPC8280 local bus masters 8–15. 0 3 Field Reset R/W Addr Priority Field 8 1000 Field Reset R/W Addr 16 Priority Field 12 1100 19 4 Priority Field 9 1001 7 8 Priority Field 10 1010 11 R/W 0x1003C 20 23 24 Priority Field 13 1101 Priority Field 14 1110 R/W 0x1003E

Figure 4-27. LCL_ALRL

27 12 Priority Field 11 1011 15 28 Priority Field 15 1111 31

4.3.2.6

SIU Module Configuration Register (SIUMCR)

The SIU module configuration register (SIUMCR), shown in

Figure 4-28 , contains bits that configure

various features in the SIU module.

Field Reset 0 BBD see note R/W Addr 1 ESE 2 PBSE 00 3 CDIS 4 DPPC 5 6 7 L2CPC 8 LBPC see note 9 R/W 0x10000 10 11 APPC 12 13 CS10PC Field Reset 16 MMR 17 see note 18 LPBSE 0 19 — see note 20 21 DBA ABA 0 0 22 — see note R/W R/W Addr 0x10002 1

Depends on rest configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word .”

Figure 4-28. SIU Model Configuration Register (SIUMCR)

14 15 BCTLC 00 31 Freescale Semiconductor

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System Interface Unit (SIU)

Table 4-12

describes SIUMCR fields.

Table 4-12. SIUMCR Register Field Descriptions Bits

0 1 2 3 4–5 6–7

Name Description

BBD ESE PBSE CDIS DPPC L2CPC Bus busy disable. 0 ABB/IRQ2 pin is ABB, DBB/IRQ3 pin is DBB 1 ABB/IRQ2 pin is IRQ2, DBB/IRQ3 pin is IRQ3 External snoop enable. Configures GBL/IRQ1 0 External snooping disabled. (GBL/IRQ1 pin is IRQ1) 1 External snooping enabled. (GBL/IRQ1 pin is GBL) Parity byte select enable. 0 Parity byte select is disabled. GPL4 output of UPM is available for memory control.

1 Parity byte select is enabled. GPL4 pin is used as parity byte select output from the MPC8280.

Note:

Should not be set if BRx[DECC] = 00. Refer to Section 11.3.1, “Base Registers (BRx)

.” Core disable.

0 The MPC8280 core is enabled.

1 The MPC8280 core is disabled. MPC8280 functions as a slave device.

Data parity pins configuration. Note that the additional arbitration lines (EXT_BR2, EXT_BG2, EXT_DBG2, EXT_BR3, EXT_BG3, and EXT_DBG3) are operational only when ACR[EARB] = 0. Setting EARB (to choose external arbiter) combined with programming DPPC to 11 deactivates these lines.

DPPC Pin

DP(0)/RSRV DP(1)/IRQ1 DP(2)/TLBISYNC/IRQ2 DP(3)/IRQ3 DP(4)/IRQ4 DP(5)/TBEN/IRQ5/CINT DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 L2 cache pins configuration.

00

— IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

01

DP(0) DP(1) DP(2) DP(3) DP(4) DP(5) DP(6) DP(7)

10 11

RSRV IRQ1 EXT_BR2 EXT_BG2 TLBISYNC EXT_DBG2 CKSTP_OUT EXT_BR3 CORE_SRE SET TBEN EXT_BG3 EXT_DBG3 CSE(0) CSE(1) IRQ6 IRQ7

Pin

CI/BADDR(29)/IRQ2 WT/BADDR(30)/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR(31)/IRQ5/CINT

L2CPC = 00

CI WT L2_HIT CPU_BG

Multiplexing L2CPC = 01

IRQ2 IRQ3 IRQ4 IRQ5

L2CPC = 10

BADDR(29) BADDR(30) — BADDR(31) 4-34

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System Interface Unit (SIU) Table 4-12. SIUMCR Register Field Descriptions (continued) Bits

8–9 10–11 12–13 14–15 16-17

Name

LBPC

Description

Local bus pins configuration.

Note:

LBPC should be programmed only during the hard reset configuration sequence (using the hard reset configuration word).

00 Local bus pins function as local bus 01 Local bus pins function as PCI bus. Reserved on all other devices.

10 Local bus pins function as core pins 11 Reserved APPC Address parity pins configuration. Note that during power on reset the MODCK pins are used for PLL configuration. The pin multiplexing indicated in the table applies only to normal operation. Selection between IRQ7 and INT_OUT is according to CPU state. If the core is disabled, the pin is INT_OUT; otherwise it is IRQ7.

APPC Pin 00

TC(0)

01

AP(1)

10

BNKSEL(0)

11

— MODCK1/AP(1)/TC(0)/ BNKSEL(0) MODCK2/AP(2)/TC(1)/ BNKSEL(1) MODCK3/AP(3)/TC(2)/ BNKSEL(2) IRQ7/INT_OUT/APE CS11/AP(0) CS10PC Chip select 10-pin configuration. TC(1) TC(2) IRQ7/ INT_OUT CS11 AP(2) AP(3) APE AP(0) BNKSEL(1) BNKSEL(2) IRQ7/ INT_OUT CS11 IRQ7/ INT_OUT — BCTLC MMR

Pin

CS10/BCTL1

00

CS10

CS10PC 01

BCTL1

10

— Configuration for the control lines for external buffers.

00 BCTL0 is used as W/R control for external buffers. BCTL1 is used as OE control for external buffers.

01 BCTL0 is used as W/R control for external buffers. BCTL1 is used as OE control for external buffers.

10 BCTL0 is used as WE control for external buffers. BCTL1 is used as RE control for external buffers.

11 Reserved Mask masters requests. In some systems, several bus masters are active during normal operation; only one should be active during boot sequence. The active master, which is the boot device, initializes system memories and devices and enables all other masters. MMR facilitates such a boot scheme by masking the selected master’s bus requests. MMR can be configured through the hard reset configuration sequence (see

Section 5.4.2, “Hard Reset Configuration Examples ”). Typically system

configuration identifies only one master is the boot device, which initializes the system and then enables all other devices by writing 00 to MMR.

Note:

It is not recommended to mask the request of a master which is defined as the parked master in the arbiter, since this cannot prevent this master from getting a bus grant.

00 No masking on bus request lines.

01 Reserved 10 The MPC8280’s internal core bus request masked and external bus requests two and three masked (boot master connected to external bus request 1).

11 All external bus requests masked (boot master is the MPC8280’s internal core).

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System Interface Unit (SIU) Bits

18 19 20 21 22–31

Table 4-12. SIUMCR Register Field Descriptions (continued) Name Description

LPBSE — DBA Local bus parity byte select enable.

0 Parity byte select is disabled. LGPL4 output of UPM is available for memory control.

1 Parity byte select is enabled. LGPL4 pin is used as local bus parity byte select output from the MPC8280.

Reserved, should be cleared.

ABA — Data output buffer impedance configuration. The pins in this group include D[0-63] and PWE[0-7]/PSDDQM[0-7]/PBS[0-7]. 0 The output buffer typical impedance is 45 Ω.

1 The output buffer typical impedance is 25 Ω . Address output buffer impedance configuration. The pins in this group include A[0-31], PSDA10/PGPL0, PSDWE/PGPL1, POE/PSDRAS/PGPL2, PSDCAS/PGPL3, PGTA/PUPM, WAIT/PGPl4, PSDAMUX/PGPL5 and BNKSEL[0:2]. 0 The output buffer typical impedance is 45 Ω . 1 The output buffer typical impedance is 25 Ω . Reserved, should be cleared.

4.3.2.7

Internal Memory Map Register (IMMR)

The internal memory map register (IMMR), shown in

Figure 4-29 , contains identification of a specific

device as well as the base address for the internal memory map. Software can deduce availability and location of any on-chip system resources from the values in IMMR. PARTNUM and MASKNUM are mask programmed and cannot be changed for any particular device.

Field Reset R/W Addr 0 13 14 ISB — Depends on reset configuration sequence. See

Section 5.4.1, “Hard Reset Configuration Word .”

15 R/W 0x101A8 16 31 Field Reset R/W Addr 23 24 PARTNUM 0000_1010 MASKNUM 0000_0000 R 0x101AA

Figure 4-29. Internal Memory Map Register (IMMR)

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System Interface Unit (SIU)

Table 4-13

describes IMMR fields.

Table 4-13. IMMR Field Descriptions Bits Name Description

0–13 14–15 16–23 ISB — PARTNUM Internal space base. Defines the base address of the internal memory space. The value of ISB be configured at reset to one of 8 addresses; it can then be changed to any value by the software. The default is 0, which maps to address 0x0000_0000. ISB defines the 14 msbs of the memory map register base address. IMMR itself is mapped in the internal memory space region. As soon as the ISB is written with a new base address, the IMMR base address is relocated according to the ISB. ISB can be configured to one of 8 possible addresses at reset to enable the configuration of multiple-MPC8280 systems.

The number of programmable bits in this field, and hence the resolution of the location of internal space, depends on the internal memory space of a specific implementation. In the MPC8280, all 14 bits can be programmed. See Chapter 3, “Memory Map ,” for details on the device’s internal memory map and Chapter 5, “Reset ,” for the available default initial values.

Reserved, should be cleared. Part number. This read-only field is mask-programmed with a code corresponding to the part number of the part on which the SIU is located. It is intended to help factory test and user code which is sensitive to part changes. This changes when the part number changes. For example, it would change if any new module is added or if the size of any memory module is changed. It would not change if the part is changed to fix a bug in an existing module. The part number for the MPC8280 is 0x0A.

24–31 MASKNUM Mask number. This read-only field is mask-programmed with a code corresponding to the mask number of the part on which the SIU is located. It is intended to help factory test and user code which is sensitive to part changes. It is programmed in a commonly changed layer and should be changed for all mask set changes. The first revision of the MPC8280 has 0x00 in this field. The value of this field is changed every revision of the device.

4.3.2.8

System Protection Control Register (SYPCR)

The system protection control register, shown in

Figure 4-30

, controls the system monitors, software watchdog period, and bus monitor timing. SYPCR can be read at any time but can be written only once after system reset.

0 Field Reset R/W Addr Field Reset R/W Addr 16 15 SWTC 1111_1111_1111_1111 R/W 0x10004 BMT 1111_1111 23 24 25 PBME LBME R/W 0 0 0x10006 26 — 00_0

Figure 4-30. System Protection Control Register (SYPCR)

28 29 30 31 SWE SWRI SWP 1 1 1 Freescale Semiconductor

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System Interface Unit (SIU)

Table 4-14

describes SYPCR fields.

Table 4-14. SYPCR Field Descriptions Bits Name Description

0–15 16–23 24 25 26–28 29 30 31 SWTC Software watchdog timer count. Contains the count value for the software watchdog timer.

BMT Bus monitor timing. Defines the time-out period for the bus monitor, the granularity of this field is 8 bus clocks. (BMT = 0xFF is translated to 0x7f8 clock cycles). BMT is used both in the 60x and local bus monitors.

Note that the value 0 in invalid; an error is generated for each bus transaction.

PBME 60x bus monitor enable. 0 60x bus monitor is disabled.

1 The 60x bus monitor is enabled. LBME Local bus monitor enable. 0 Local bus monitor is disabled.

1 The local bus monitor is enabled.

— SWE Reserved, should be cleared. Software watchdog enable. Enables the operation of the software watchdog timer. It should be cleared by software after a system reset to disable the software watchdog timer. SWRI Software watchdog reset/interrupt select. 0 Software watchdog timer and bus monitor time-out cause a machine check interrupt to the core. 1 Software watchdog timer and bus monitor time-out cause a hard reset (this is the default value after soft reset).

SWP Software watchdog prescale. Controls the divide-by-2,048 software watchdog timer prescaler. 0 The software watchdog timer is not prescaled. 1 The software watchdog timer clock is prescaled.

4.3.2.9

Software Service Register (SWSR)

The software service register (SWSR) is the location to which the software watchdog timer servicing sequence is written. To prevent software watchdog timer time-out, the user should write 0x556C followed by 0xAA39 to this register, which resides at 0x1000E. SWSR can be written at any time, but returns all zeros when read.

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System Interface Unit (SIU) 4.3.2.10

60x Bus Transfer Error Status and Control Register 1 (TESCR1)

The 60x bus transfer error status and control register 1 (TESCR1) is shown in

Figure 4-31 .

2 3 4 5 6 7–9 Field Reset R/W Addr 0 BM 1 2 ISBE PAR 3 ECC2 4 ECC1 5 WP 6 EXT 7 TC 0000_0000_0000_0000 R/W 0x10040 9 10 — 11 TT 15 Field Reset R/W Addr 16 — 17 DMD 18 — 19 PCIMCP 20 DER 21 IRQ0 22 SWD 23 ADO 0000_0000_0000_0000 R/W 0x10042

Note:

Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.

24 ECNT

Figure 4-31. 60x Bus Transfer Error Status and Control Register 1 (TESCR1)

Table 4-15

describes TESCR1 fields.

Table 4-15. TESCR1 Field Descriptions Bits

0 1 31

Name

BM ISBE

Description

60x bus monitor time-out. Set when TEA is asserted due to the 60x bus monitor time-out.

Internal space bus error. Indicates that one of the following occurred: • TEA was asserted due to an error on a transaction to MPC8280’s internal memory space • An MCP was caused by a parity error on a transaction to MPC8280’s internal memory space. Possible only if BCR[SPAR] = 1.

PAR ECC2 ECC1 WP EXT TC TESCR2[REGS,DPR, LCL, PCI0, PCI1] indicate which of MPC8280’s internal slaves caused the error. 60x bus parity error. Indicates that an MCP was caused due to one of the following: • Parity error on 60x bus access controlled by the memory controller. TESCR2[PB] indicates which byte lane caused the error; TESCR2[BNK] indicates which memory controller bank was accessed.

• Parity error on a transaction to MPC8280’s internal memory space. Possible only if BCR[SPAR] = 1.

Double ECC error. Indicates that MCP was asserted due to double ECC error on the 60x bus. TESCR2[BNK] indicates which memory controller bank was accessed.

Single ECC error. Indicates that MCP was asserted due to single bit ECC error on the 60x bus. TESCR2[BNK] indicates which memory controller bank was accessed. Single-bit errors are fixed by the ECC logic. However, if the ECC counter (ECNT) has reached its maximum value, all single-bit errors cause the assertion of MCP.

Write protect error. Indicates that a write was attempted to a 60x bus memory region that was defined as read-only in the memory controller. Note that this alone does not cause TEA assertion. Usually, in this case, the bus monitor will time-out.

External error. Indicates that TEA was asserted by an external bus slave.

Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA or MCP. See

Section 8.4.3.2, “Transfer Code Signals TC[0–2],”

for a description of the various transfer codes.

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System Interface Unit (SIU) Table 4-15. TESCR1 Field Descriptions (continued) Bits Name Description

10 11–15 16 17 18 19 — TT Reserved, should be cleared.

Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA or MCP. See

Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,”

for a description of the various transfer types.

Reserved, should be cleared.

— DMD Data errors disable.

0 Errors are enabled.

1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.

— Reserved, should be cleared.

PCIMCP PCI machine check. Set when a core machine check is asserted from the PCI bridge.

20 21 DER IRQ0 22 23 24–31 SWD ADO ECNT .Data error. Set when a core machine check is asserted due to ECC or parity errors.

External machine check. Set when a machine check is asserted due to the external machine check pin (IRQ0).

Software watchdog time-out. Indicates that a core machine check was asserted due to a time-out in the software watchdog. See Section 4.1.5, “Software Watchdog Timer.” 60x bus monitor address-only time-out. Set when a core machine check is asserted due to time-out of the bus monitor in an address only transaction. See Section 4.1.1, “Bus Monitor.” Single ECC error counter. Indicates the number of single ECC errors that occurred in the system. When the counter reaches its maximum value (255), MCP is asserted for all single ECC errors. This feature gives the system the ability to withstand a few random errors yet react to a catastrophic failure. The user can set a lower threshold to the number of tolerated single ECC errors by writing some value to ECNT. The counter starts from this value instead of zero.

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System Interface Unit (SIU) 4.3.2.11

60x Bus Transfer Error Status and Control Register 2 (TESCR2)

The 60x bus transfer error status and control register 2 (TESCR2) is shown in

Figure 4-32 .

Field Reset R/W Addr 0 — 1 2 REGS DPR 3 — 4 PCI0 5 PCI1 6 — 7 LCL 8 0000_0000_0000_0000 R/W 0x10044 PB 15 16 Field Reset R/W Addr BNK 0000_0000_0000_0000 Note: all bits are status bits and are cleared by writing 1s.

R/W 0x10046 27 28 —

Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)

The TESCR2 register is described in

Table 4-16 .

Table 4-16. TESCR2 Field Descriptions

31

Bits

0 1 2 3 4 5 6 7 8–15 16–27 28–31

Name Description

— Reserved, should be cleared.

REGS Internal registers error. An error occurred in a transaction to the MPC8280’s internal registers.

DPR — PCI0 PCI1 — LCL PB BNK — Dual port ram error. An error occurred in a transaction to the MPC8280’s dual-port RAM.

Reserved, should be cleared.

PCI memory space 0 error. An error occurred in a transaction to the PCI memory space configured by PCIBR0 and PCIMSK0.

PCI memory space 1 error. An error occurred in a transaction to the PCI memory space configured by PCIBR1 and PCIMSK1.

Reserved, should be cleared.

Local bus bridge error. An error occurred in a transaction to the MPC8280’s 60x bus to local bus bridge.

Parity error on byte. There are eight parity error status bits, one per 8-bit lane. A bit is set for the byte that had a parity error.

Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is set for the 60x bus memory controller bank that had an error. Note that this field is invalid if the error was not caused by ECC or parity checks.

Reserved, should be cleared.

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System Interface Unit (SIU) 4.3.2.12

Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)

The local bus transfer error status and control register 1 (L_TESCR1) is shown in Figure 4-33

.

Field 0 BM Reset R/W Addr 1 — 2 PAR 3 — 4 5 WP 6 — 7 TC 9 0000_0000_0000_0000 R/W 0x10048 10 — 11 TT 15 Field Reset R/W Addr 16 — 17 DMD 18 — 19 20 DER 21 0000_0000_0000_0000 R/W 0x1004A Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.

Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)

The L_TESCR1 register bits are described in Table 4-17

.

Table 4-17. L_TESCR1 Field Descriptions

31

Bits

0 1 2 3–4 5 6 7–9 10 11–15 16 17

Name Description

BM — PAR — WP — TC — TT — DMD Bus monitor time-out. Indicates that TEA was asserted due to the local bus monitor time-out.

Reserved, should be cleared.

Parity error. Indicates that MCP was asserted due to parity error on the local bus. L_TESCR2[PB] indicates the byte lane that caused the error and L_TESCR2[BNK] indicates which memory controller bank was accessed.

Reserved, should be cleared.

Write protect error. Indicates that a write was attempted to a local bus memory region that was defined as read-only in the memory controller. Note that this alone does not cause TEA assertion. Usually, in this case, the bus monitor will time-out.

Reserved, should be cleared.

Transfer code. Indicates the transfer code of the local bus transaction that caused the TEA. 000 60x-local bridge 001 Reserved 010 Local DMA function code 0 011 Local DMA function code 1 1xx Reserved Reserved, should be cleared.

Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA.

Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,”

describes the various transfer types.

Reserved, should be cleared.

Data errors disable. Setting this bit disables parity errors on the local bus.

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System Interface Unit (SIU) Table 4-17. L_TESCR1 Field Descriptions (continued) Bits

18–19 20 21–31

Name

— DER —

Description

Reserved, should be cleared.

Data error. Set when a core machine check is asserted due to parity errors in the local bus.

Reserved, should be cleared.

4.3.2.13

Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)

The local bus transfer error status and control register 2 (L_TESCR2) is shown in Figure 4-34

.

0 11 12 15 Field Reset R/W Addr — 0000_0000_0000_0000 R/W 0x1004C PB 16 Field Reset R/W Addr BNK 0000_0000_0000_0000 Note: all bits are status bits and are cleared by writing 1s.

R/W 0x1004E 27 28 —

Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)

Table 4-18

describes L_TESCR2 fields.

Table 4-18. L_TESCR2 Field Descriptions

31

Bits

0–11 12–15 16–27 28–31

Name

— PB BNK —

Description

Reserved, should be cleared.

Parity error on byte. There are four parity error status bits, one per 8-bit lane. A bit is set for the byte that had a parity error.

Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is set for the local bus memory controller bank that had an error. Note that BNK is invalid if the error was not caused by ECC or PARITY checks.

Reserved, should be cleared.

4.3.2.14

Time Counter Status and Control Register (TMCNTSC)

The time counter status and control register (TMCNTSC), shown in

Figure 4-35 , is used to enable the

different TMCNT functions and for reporting the source of the interrupts. The register can be read at any time. Status bits are cleared by writing ones; writing zeros does not affect the value of a status bit.

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System Interface Unit (SIU)

.

Field Reset R/W Addr 0 — 7 8 SEC 9 ALR 0000_0000_0000_0000 R/W 0x10220 10 — 11 12 SIE

Figure 4-35. Time Counter Status and Control Register (TMCNTSC)

13 ALE 14 TCF 15 TCE

Table 4-19

describes TMCNTSC fields.

Table 4-19. TMCNTSC Field Descriptions Bits

0–7 8 9 10–11 12 13 14 15

Name Description

— SEC ALR — SIE ALE TCF TCE Reserved, should be cleared.

Once per second interrupt. This status bit is set every second and should be cleared by software.

Alarm interrupt. This status bit is set when the value of the TMCNT is equal to the value programmed in the alarm register.

Reserved, should be cleared.

Second interrupt enable. 0 The time counter does not generate an interrupt when SEC is set.

1 The time counter generates an interrupt when SEC is set.

Alarm interrupt enable. If ALE = 1, the time counter generates an interrupt when ALR is set.

Time counter frequency. The input clock to the time counter may be either 4 MHz or 32 KHz. The user should set the TCF bit according to the frequency of this clock. 0 The input clock to the time counter is 4 MHz. 1 The input clock to the time counter is 32 KHz.

See Section 4.1.2, “Timers Clock

” for further details.

Time counter enable. Is not affected by soft or hard reset.

0 The time counter is disabled. 1 The time counter is enabled.

4.3.2.15

Time Counter Register (TMCNT)

The time counter register (TMCNT), shown in

Figure 4-36

, contains the current value of the time counter. The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset.

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System Interface Unit (SIU)

0 15 Field Reset R/W Addr TMCNT 0000_0000_0000_0000 R/W 0x10224 16 31 Field Reset R/W Addr TMCNT 0000_0000_0000_0000 R/W 0x10226

Figure 4-36. Time Counter Register (TCMCNT) 4.3.2.16

Time Counter Alarm Register (TMCNTAL)

The time counter alarm register (TMCNTAL), shown in Figure 4-37 , holds a value (ALARM). When the

value of TMCNT equals ALARM, a maskable interrupt is generated.

15 0 Field Reset R/W Addr Field Reset R/W Addr 16 ALARM 0000_0000_0000_0000 R/W 0x1022C ALARM 0000_0000_0000_0000 R/W 0x1222E

Figure 4-37. Time Counter Alarm Register (TMCNTAL)

31

Table 4-20

describes TMCNTAL fields.

Table 4-20. TMCNTAL Field Descriptions Bits Name Description

0–31 ALARM The alarm interrupt is generated when ALARM field matches the corresponding TMCNT bits. The resolution of the alarm is 1 second.

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System Interface Unit (SIU)

4.3.3

Periodic Interrupt Registers

The periodic interrupt registers are described in the following sections.

4.3.3.1

Periodic Interrupt Status and Control Register (PISCR)

The periodic interrupt status and control register (PISCR), shown in

Figure 4-38 , contains the interrupt

request level and the interrupt status bit. It also contains the controls for the 16 bits to be loaded in a modulus counter. Field Reset R/W Addr 0 — 7 8 PS 0x10240 9 0000_0000_0000_0000 R/W — 12

Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)

13 PIE 14 PTF 15 PTE

Table 4-21

describes PISCR fields.

Table 4-21. PISCR Field Descriptions Bits

0–7 8 9–12 13 14 15

Name Description

— PS — PIE Reserved, should be cleared. Periodic interrupt status. Asserted if the PIT issues an interrupt. The PIT issues an interrupt after the modulus counter counts to zero. The PS bit can be negated by writing a one to PS. A write of zero has no effect on this bit.

Reserved, should be cleared. Periodic interrupt enable. If PIE = 1, the periodic interrupt timer generates an interrupt when PS = 1.

PTF Periodic interrupt frequency. The input clock to the periodic interrupt timer may be either 4 MHz or 32 KHz. The user should set the PTF bit according to the frequency of this clock. 0 The input clock to the periodic interrupt timer is 4 MHz. 1 The input clock to the periodic interrupt timer is 32 KHz.

See

Section 4.1.2, “Timers Clock,”

for further details PTE Periodic timer enable. This bit controls the counting of the periodic interrupt timer. When the timer is disabled, it maintains its old value. When the counter is enabled, it continues counting using the previous value.

0 Disable counter.

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System Interface Unit (SIU) 4.3.3.2

Periodic Interrupt Timer Count Register (PITC)

The periodic interrupt timer count register (PITC), shown in

Figure 4-39

, contains the 16 bits to be loaded in a modulus counter. 0 15 Field Reset R/W Addr PITC 0000_0000_0000_0000 R/W 0x10244 16 Field Reset R/W Addr — 0000_0000_0000_0000 R/W 0x10246

Figure 4-39. Periodic interrupt Timer Count Register (PITC)

Table 4-22

describes PITC fields.

Table 4-22. PITC Field Descriptions

31

Bits Name Description

0–15 16–31 PITC Periodic interrupt timing count. Bits 0–15 are defined as the PITC, which contains the count for the periodic timer. Setting PITC to 0xFFFF selects the maximum count period.

— Reserved, should be cleared.

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System Interface Unit (SIU) 4.3.3.3

Periodic Interrupt Timer Register (PITR)

The periodic interrupt timer register (PITR), shown in Figure 4-40 , is a read-only register that shows the

current value in the periodic interrupt down counter. The PITR counter is not affected by reads or writes to it. 0 Field Reset R/W Addr PIT 0000_0000_0000_0000 Read Only 0x10248 16 Field Reset R/W Addr — 0000_0000_0000_0000 Read Only 0x1024A

Figure 4-40. Periodic Interrupt Timer Register (PITR)

Table 4-23

describes PITR fields.

Table 4-23. PITR Field Descriptions Bits

0–15 16–31

Name Description

PITC Periodic interrupt timing count. Bits 0–15 are defined as the PIT. It contains the current count remaining for the periodic timer. Writes have no effect on this field.

— Reserved, should be cleared.

15 31

4.3.4

PCI Control Registers

Two pairs of registers detect accesses from the 60x bus side to the PCI bridge (other than PCI internal registers accesses). Each pair consists of a PCI base register (PCIBRx) for comparing addresses and a corresponding PCI mask register (PCIMSKx). 4-48

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System Interface Unit (SIU) 4.3.4.1

PCI Base Register (PCIBRx)

Figure 4-41 shows the PCI base register.

0 Field Reset R/W Addr Field 16 BA Reset R/W Addr 17 BA 0000_0000_0000_0000 R/W 0x101AC (PCIBR0); 0x101B0 (PCIBR1) — 0000_0000_0000_0000 R/W 0x101AE (PCIBR0); 0x101B2 (PCIBR1) 30 15 31 V

Figure 4-41. PCI Base Registers (PCIBRx)

Table 4-24

describes PCIBRx fields.

Table 4-24. PCIBRx Field Descriptions Bits

0–16 17–30 31

Name

BA — V

Description

Base Address. The upper 17 bits of each base address register are compared to the address on the 60x bus address bus to determine if the access should be claimed by the PCI bridge. Used with PCIMSKx[AM] Reserved. Should be cleared.

Valid bit. Indicates that the contents of the PCIBRx and PCIMSKx pairs are valid.

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System Interface Unit (SIU) 4.3.4.2

PCI Mask Register (PCIMSKx)

Figure 4-42 shows the PCI mask register.

0 Field Reset R/W Addr Field 16 AM Reset R/W Addr 17 AM 0000_0000_0000_0000 R/W 0x101C4 (PCIBR0); 0x101C8 (PCIBR1) — 0000_0000_0000_0000 R/W 0x101C6 (PCIBR0); 0x101CA (PCIBR1)

Figure 4-42. PCI Mask Register (PCIMSKx)

Table 4-25

describes PCIMSKx fields.

Table 4-25. PCIMSKx Field Descriptions Bits

31–17 16–0

Name

— AM

Description

Reserved. Should be cleared.

Address Mask. Masks corresponding PCIBRx bits. 0 Corresponding address bits are masked.

1 Corresponding address bits are compared.

15 31

4.4

SIU Pin Multiplexing

Some functions share pins. The actual pinout of the MPC8280 is shown in the hardware specifications. The control of the actual functionality used on a specific pin is shown in

Table 4-26 .

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System Interface Unit (SIU) Table 4-26. SIU Pins Multiplexing Control Pin Name

GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5/CINT ABB/IRQ2 DBB/IRQ3 NC/DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3/CINT IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 CS[10]/BCTL1 CS[11]/AP[0] PCI_PAR/ L_A14 SMI/PCI_FRAME/ L_A15 PCI_TRDY/ L_A16 CKSTOP_OUT/PCI_IRDY/ L_A17 PCI_STOP/ L_A18 PCI_DEVSEL/ L_A19 PCI_IDSEL/ L_A20 PCI_PERR/ L_A21 PCI_SERR/ L_A22 PCI_REQ0/ L_A23 PCI_REQ1/ L_A24 PCI_GNT0/ L_A25 PCI_GNT1/ L_A26 PCI_CLK/ L_A27 CORE_SRESET/PCI_RST/ L_A28 PCI_INTA/ L_A29 PCI_REQ2/ L_A30 AD[0–31]/ LCL_D[0–31] C/BE[0–3]/ LCL_DP[0–3] BNKSEL[0]/TC[0]/AP[1]/MODCK1 BNKSEL[1]/TC[1]/AP[2]/MODCK2 BNKSEL[2]/TC[2]/AP[3]/MODCK3 PWE[0–7]/PSDDQM[0–7]/PBS[0–7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LBS[0–3]/LSDDQM[0–3]/LWE[0–3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS/LOE LGPL3/LSDCAS LPBS/LGPL4/LUPMWAIT/LGTA LGPL5/LSDAMUX

Pin Configuration Control

Controlled by SIUMCR programming see Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR),”

for more details.

Controlled dynamically according to the specific memory controller machine that handles the current bus transaction.

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Chapter 5 Reset

The MPC8280 has several inputs to the reset logic: • • Power-on reset (PORESET) External hard reset (HRESET) • • • • • External soft reset (SRESET) Software watchdog reset Bus monitor reset Checkstop reset JTAG reset All of these reset sources are fed into the reset controller and, depending on the source of the reset, different

actions are taken. The reset status register, described in Section 5.2, “Reset Status Register (RSR),”

indicates the last sources to cause a reset.

5.1

Reset Causes

Table 5-1

describes reset causes.

Table 5-1. Reset Causes Name Description

Power-on reset (PORESET) Hard reset (HRESET) Input pin. Asserting this pin initiates the power-on reset flow that resets all the chip and configures various attributes of the chip including its clock mode.

This is a bidirectional I/O pin. The MPC8280 can detect an external assertion of HRESET only if it occurs while the MPC8280 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-collector pin.

Soft reset (SRESET) Software watchdog reset Bus monitor reset Bidirectional I/O pin. The MPC8280 can only detect an external assertion of SRESET if it occurs while the MPC8280 is not asserting reset. SRESET is an open-drain pin.

After the MPC8280’s watchdog counts to zero, a software watchdog reset is signaled. The enabled software watchdog event then generates an internal hard reset sequence.

After the MPC8280’s bus monitor counts to zero, a bus monitor reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence.

Checkstop reset JTAG reset If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), checkstop reset is asserted. The enabled checkstop event then generates an internal hard reset sequence.

When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated.

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5.1.1

Reset Actions

The reset block has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. Because there is no soft nor hard reset in the 603e core, asserting external SRESET generates a reset to the 603e core and a soft reset to the remainder of the device, The impact on the given application is the reset to the core resets the MSR[IP] to the value in the HRCW[CIP],

see Table 5-7 .

Table 5-2

identifies reset actions for each reset source.

Table 5-2. Reset Actions for Each Reset Source Reset Source

Power-on reset External hard reset Software watchdog Bus monitor Checkstop

Reset Logic and PLL States Reset System Configuration Sampled Clock Module Reset HRESET Driven Other Internal Logic Reset 1 SRESET Driven Core Reset

Yes No Yes Yes Yes Yes Yes Yes JTAG reset External soft reset No No No No 1 Includes all other CPM and core logic not explicitly noted elsewhere in the table.

Yes Yes Yes Yes Yes Yes Yes Yes Yes

5.1.2

Power-On Reset Flow

Assertion of the PORESET external pin initiates the power-on reset flow. PORESET should be asserted externally for at least 16 input clock cycles after external power to the chip reaches at least 2/3 Vcc. The value driven on RSTCONF while PORESET changes from assertion to negation determines the chip configuration. If RSTCONF is negated (driven high) while PORESET changes, the chip acts as a configuration slave. If RSTCONF is asserted while PORESET changes, the chip acts as a configuration master.

Section 5.4, “Reset Configuration,”

explains the configuration sequence and the terms ‘configuration master’ and ‘configuration slave.’ Directly after the negation of PORESET and choice of the reset operation mode as configuration master or configuration slave, the MPC8280 starts the configuration process. The MPC8280 asserts HRESET and SRESET throughout the power-on reset process, including configuration. Configuration takes 1,024 CLOCKIN cycles, after which MODCK[1–3] are sampled to determine the chips working mode. Next the MPC8280 halts until the main PLL locks. As described in

Section 10.6, “Clock Configuration Modes,”

the main PLL locks according to MODCK[1–3], which are sampled, and to MODCK_HI (MODCK[4–7]) taken from the reset configuration word. The main PLL lock can take up to 200 µs depending on the specific chip. During this time HRESET and SRESET are asserted. When the main PLL is locked, the clock block starts distributing clock signals in the chip. HRESET remains asserted for another 512 clocks and is then released. The SRESET is released three clocks later.

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Reset

Figure 5-4 shows the power-on reset flow.

PORESET Input External pin is asserted for min 16 RSTCONF is sampled for master determination PORESET Internal MODCK[1–3] are sampled. MODCK_HI bits are ready for PLL HRESET Output PLL is locked (no external indication) SRESET Output PLL locking period HRESET /SRESET are extended for 512/515 CLKIN (respectively), from PLL lock time.

PORESET to internal logic is extended for 1024 CLKIN.

In reset configuration mode: reset configuration sequence occurs in this period.

Interval depends on PLL locking time.

Figure 5-1. Power-on Reset Flow

5.1.3

HRESET Flow

The HRESET flow may be initiated externally by asserting HRESET or internally when the chip detects a reason to assert HRESET. In both cases the chip continues asserting HRESET and SRESET throughout the HRESET flow. The HRESET flow begins with the hard reset configuration sequence, which

configures the chip as explained in Section 5.4, “Reset Configuration.”

After the chip asserts HRESET and SRESET for 1,024 input clock cycles, it releases both signals and exits the HRESET flow. An external pull-up resistor should negate the signals. After negation is detected, a 16-cycle period is taken before testing the presence of an external (hard/soft) reset.

5.1.4

SRESET Flow

The SRESET flow may be initiated externally by asserting SRESET or internally when the chip detects a cause to assert SRESET. In both cases the chip asserts SRESET for 512 input clock cycles, after which the chip releases SRESET and exits the SRESET flow. An external pull-up resistor should negate SRESET; after negation is detected, a 16-cycle period is taken before testing the presence of an external (hard/soft) reset. While SRESET is asserted, internal hardware is reset but hard reset configuration does not change.

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5.2

Reset Status Register (RSR)

The reset status register (RSR), shown in Figure 5-2 , is memory-mapped into the MPC8280’s SIU register

map.

0 15 Field R/W Reset Addr — R/W 0000_0000_0000_0000

0x10C90

Field R/W Reset Addr 16 — 25 0x10C92 26 27 JTRS CSRS R/W 0000_0000_0000_0011

Figure 5-2. Reset Status Register (RSR)

28 SWRS 29 30 31 BMRS ESRS EHRS

Table 5-3

describes RSR fields.

Table 5-3. RSR Field Descriptions Bits

0–25 26 27 28 29

Name Function

— Reserved, should be cleared.

JTRS JTAG reset status. When the JTAG reset request is set, JTRS is set and remains set until software clears it. JTRS is cleared by writing a 1 to it (writing zero has no effect).

0 No JTAG reset event occurred 1 A JTAG reset event occurred CSRS Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled by the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by writing a 1 to it (writing zero has no effect).

0 No enabled checkstop reset event occurred 1 An enabled checkstop reset event occurred SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is detected, the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by writing a 1 to it (writing zero has no effect).

0 No software watchdog reset event occurred 1 A software watchdog reset event has occurred BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected, BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero has no effect).

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Bits

30 31

Table 5-3. RSR Field Descriptions (continued) Name Function

ESRS External soft reset status. When an external soft reset event is detected, ESRS is set and it remains that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect).

0 No external soft reset event has occurred 1 An external soft reset event has occurred EHRS External hard reset status. When an external hard reset event is detected, EHRS is set and it remains set until software clears it. EHRS is cleared by writing a 1 (writing zero has no effect).

0 No external hard reset event has occurred 1 An external hard reset event has occurred

Reset NOTE

The reset status register accumulates reset events. For example, because software watchdog expiration results in a hard reset, which in turn results in a soft reset, RSR[SWRS], RSR[ESRS] and RSR[EHRS] are all set after a software watchdog reset.

5.3

Reset Mode Register (RMR)

The reset mode register (RMR), shown in

Figure 5-3

, is memory-mapped into the SIU register map.

0 15 Field — R/W Reset Addr R/W 0000_0000_0000_0000

0x10C94

16 30 31 CSRE Field R/W Reset Addr — R/W 0000_0000_0000_0000 0x10C96

Figure 5-3. Reset Mode Register (RMR)

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Table 5-4

describes RMR fields.

Table 5-4. RMR Field Descriptions Bits Name Function

0–30 31 — Reserved, should be cleared. CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception conditions. Setting CSRE configures the chip to perform a hard reset sequence whenever the core enters checkstop state.

0 Reset not generated when core enters checkstop state.

1 Reset generated when core enters checkstop state.

Note:

When the core is disabled, CSRE must be cleared.

5.4

Reset Configuration

Various features may be configured during hard reset or power-on reset. For example, one configurable features is core disable, which can be used to configure a system that uses two MPC8280s, one a slave device and the other a the host with an active core. Most configurable features are reconfigured whenever HRESET is asserted. However, the clock mode is configured only when PORESET is asserted. The 32-bit hard reset configuration word is described in

Section 5.4.1, “Hard Reset Configuration Word.”

The reset configuration sequence is designed to support a system that uses up to eight MPC8280 chips, each configured differently. It needs no additional glue logic for reset configuration. The description below explains the operation of this sequence with regard to a multiple-MPC8280 system.

This and other simpler systems are described in Section 5.4.2, “Hard Reset Configuration Examples.”

In a typical multi-MPC8280 system, one MPC8280 should act as the configuration master while all other MPC8280s should act as configuration slaves. The configuration master in the system typically reads the various configuration words from EPROM in the system and uses them to configure itself as well as the configuration slaves. How the MPC8280 acts during reset configuration is determined by the value of the RSTCONF input while PORESET changes from assertion to negation. If RSTCONF is asserted while PORESET changes, MPC8280 is a configuration master; otherwise, it is a slave. In a typical multiple-MPC8280 system, RSTCONF input of the configuration master should be hard wired to ground, while RSTCONF inputs of other chips should be connected to the high-order address bits of the

configuration master, as described in Table 5-5

.

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Reset Table 5-5. RSTCONF Connections in Multiple-MPC8280 Systems Configured Device

Configuration master First configuration slave Second configuration slave Third configuration slave Fourth configuration slave Fifth configuration slave Sixth configuration slave Seventh configuration slave

RSTCONF Connection

GND A0 A1 A2 A3 A4 A5 A6 The configuration words for all MPC8280s are assumed to reside in an EPROM connected to CS0 of the configuration master. Because the port size of this EPROM is not known to the configuration master, before reading the configuration words, the configuration master reads all configuration words byte-by-byte only from locations that are independent of port size.

Table 5-6. shows addresses that should be used to configure the various MPC8280s. Byte addresses that

do not appear in this table have no effect on the configuration of the MPC8280 chips. The values of the

bytes in Table 5-6

are always read on byte lane D[0–7] regardless of the port size .

Table 5-6. Configuration EPROM Addresses Configured Device

Configuration master First configuration slave Second configuration slave Third configuration slave Fourth configuration slave Fifth configuration slave Sixth configuration slave Seventh configuration slave

Byte 0 Address

0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0

Byte 1 Address

0x08 0x28 0x48 0x68 0x88 0xA8 0xC8 0xE8

Byte 2 Address

0x10 0x30 0x50 0x70 0x90 0xB0 0xD0 0xF0

Byte 3 Address

0x18 0x38 0x58 0x78 0x98 0xB8 0xD8 0xF8 The configuration master first reads a value from address 0x00 then reads a value from addresses 0x08, 0x10, and 0x18. These four bytes are used to form the configuration word of the configuration master, which then proceeds reading the bytes that form the configuration word of the first slave device. The configuration master drives the whole configuration word on D[0–31] and toggles its A0 address line. Each configuration slave uses its RSTCONF input as a strobe for latching the configuration word during HRESET assertion time. Thus, the first configuration slave whose RSTCONF input is connected to configuration master’s A0 output latches the word driven on D[0–31] as its configuration word. In this way the configuration master continues to configure all MPC8280 chips in the system. The configuration master always reads eight configuration words regardless of the number of MPC8280 parts in the system. Freescale Semiconductor

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In a simple system that uses one stand-alone MPC8280, it is possible to use the default hard reset configuration word (all zeros). This is done by tying RSTCONF input to VCC. Another scenario may be a system which has no boot EPROM. In this case the user can configure the MPC8280 as a configuration slave by driving RSTCONF to 1 during PORESET assertion and then applying a negative pulse on RSTCONF and an appropriate configuration word on D[0–31]. In such a system, asserting HRESET in the middle of operation causes the MPC8280 to return to the configuration programmed after PORESET assertion (not the default configuration represented by configuration word of all zeros).

5.4.1

Hard Reset Configuration Word

The contents of the hard reset configuration word are shown in Figure 5-4

.

0 1 2 3 Field EARB EXMC CDIS EBM Reset 4 BPS 5 Field 16 BMS Reset 17 BBD 18 MMR 19 20 21 LBPC 22 23 APPC 24 25 CS10PC 0000_0000_0000_0000 26 ALD_EN

Figure 5-4. Hard Reset Configuration Word

27 —

Table 5-7

describes hard reset configuration word fields.

Table 5-7. Hard Reset Configuration Word Field Descriptions

28 MODCK_H 31

Bits

0 1 2 3 4–5 6

Name

EARB 1 EXMC CDIS 1 EBM 1 BPS CIP 1 6 CIP 7 ISPS 8 9 L2CPC 0000_0000_0000_0000 10 DPPC 11 12 PLLBP 13 ISB 15

Description

External arbitration. Defines the initial value for ACR[EARB]. If EARB = 1, external arbitration is

assumed. See Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR)

.” External MEMC. Defines the initial value of BR0[EMEMC]. If EXMC = 1, an external memory controller is assumed. See

Section 11.3.1, “Base Registers (BRx) .”

Core disable. Defines the initial value for the SIUMCR[CDIS]. 0 The core is active. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR)

.” 1 The core is disabled. In this mode the MPC8280 functions as a slave. External bus mode. Defines the initial value of BCR[EBM]. See

Section 4.3.2.1, “Bus Configuration Register (BCR) .”

Boot port size. Defines the initial value of BR0[PS], the port size for memory controller bank 0. 00 64-bit port size 01 8-bit port size 10 16-bit port size 11 32-bit port size

See Section 11.3.1, “Base Registers (BRx) .”

Core initial prefix. Defines the initial value of MSR[IP]. Exception prefix. The setting of this bit specifies whether an exception vector offset is prepended with Fs or 0s. In the following description, nnnnn is the offset of the exception vector. 0 MSR[IP] = 1 (default). Exceptions are vectored to the physical address 0xFFF n_nnnn 1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000 n_nnnn. 5-8

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Table 5-7. Hard Reset Configuration Word Field Descriptions (continued) Bits

7 8–9 10–11 12 13–15 16 17 18–19 20–21 22–23 24–25

Name

ISPS L2CPC DPPC PLLBP ISB BMS BBD MMR LBPC APPC 1 1 1 1 1 1 CS10PC 1

Description

Internal space port size. Defines the initial value of BCR[ISPS]. Setting ISPS configures the MPC8280 to respond to accesses from a 32-bit external master to its internal space. See

Section 4.3.2.1, “Bus Configuration Register (BCR) .”

L2 cache pins configuration. Defines the initial value of SIUMCR[L2CPC]. See Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR) .”

Data parity pin configuration. Defines the initial value of SIUMCR[DPPC]. For more details refer

to Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR)

.” PLL bypass 0 Normal operation 1 Bypass CPM PLL Initial internal space base select. Defines the initial value of IMMR[0–14] and determines the base address of the internal memory space. 000 0x0000_0000 001 0x00F0_0000 010 0x0F00_0000 011 0x0FF0_0000 100 0xF000_0000 101 0xF0F0_0000 110 0xFF00_0000 111 0xFFF0_0000

See Section 4.3.2.7, “Internal Memory Map Register (IMMR) .”

Boot memory space. Defines the initial value for BR0[BA]. There are two possible boot memory regions: HIMEM and LOMEM. 0 0xFE00_0000—0xFFFF_FFFF 1 0x0000_0000—0x01FF_FFFF

See Section 11.3.1, “Base Registers (BRx) .”

Bus busy disable. Defines the initial value of SIUMCR[BBD]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR) .”

Mask masters requests. Defines the initial value of SIUMCR[MMR]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR)

.” Local bus pin configuration. Defines the value of SIUMCR[LBPC]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR)

.” 00 Local bus pins function as local bus 01 Local bus pins function as PCI bus 10 Local bus pins function as core pins 11 Reserved Address parity pin configuration. Defines the initial value of SIUMCR[APPC]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR) .”

CS10 pin configuration. Defines the initial value of SIUMCR[CS10PC]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR) .”

Note:

During the reset configuration sequence, the BCTL1/CS10 pin toggles like POE of the 60x bus GPCM, regardless of the configuration of the reset configuration word. After the reset configuration sequence, the BCTL1/CS10 pin behaves according to the configuration of SIUMCR[CS10PC].

Reset

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Reset Table 5-7. Hard Reset Configuration Word Field Descriptions (continued) Bits Name Description

26 ALD_EN CP auto load enable. Allows the CP to automatically load the essential PCI configuration registers from the EEPROM during reset.

0 CP auto load is disabled. 1 CP auto load is enabled.

Reserved, should be cleared. 27 — 28–31 MODCK_H High-order bits of the MODCK bus, which determine the clock reset configuration. See

Chapter 10, “Clocks and Power Control,”

for details.

Note:

If the device is configured to PCI mode (PCI_MODE is driven low), this field has no effect and the value for MODCK_H is loaded directly from the MODCK_H pins. Note that the value of the MODCK_H bits are derived from the dedicated PCI_MODCK_H[0:3] pins when operating in PCI mode. 1 The user should exercise caution when changing this bit. This bit has an immediate effect on the external bus and may result in unstable system operation.

5.4.2

Hard Reset Configuration Examples

This section presents some examples of hard reset configurations in different systems.

5.4.2.1

Single MPC8280 with Default Configuration

This is the simplest configuration scenario. It can be used if the default values achieved by clearing the hard reset configuration word are desired. This is applicable only for systems using single-MPC8280 bus mode (as opposed to 60x bus mode). To enter this mode, tie RSTCONF to V CC as shown in

Figure 5-5

. The MPC8280 does not access the boot EPROM; it is assumed that the default configuration is used upon exiting hard reset.

PORESET Vcc Configuration Slave Chip HRESET PORESET A[0–31] D[0–31] RSTCONF

Figure 5-5. Single Chip with Default Configuration

Vcc

5.4.2.2

Single MPC8280 Configured from Boot EPROM

For a configuration that differs from the default, the MPC8280 can be used as a configuration master by

tying RSTCONF to GND as shown in Figure 5-6 . The MPC8280 can access the boot EPROM. It is

assumed the configuration is as defined there upon exiting hard reset.

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PORESET VCC EPROM Control Signals HRESET PORESET Configuration Master Chip A[0–31] D[0–31] RSTCONF Boot EPROM A[..] D[0–7]

Figure 5-6. Configuring a Single Chip from EPROM 5.4.2.3

Multiple MPC8280s Configured from Boot EPROM

For a complex system with multiple MPC8280 devices that may each be configured differently, configuration is done by assigning one configuration master and multiple configuration slaves. The MPC8280 that controls the boot EPROM should be the configuration master—RSTCONF tied to GND. The RSTCONF inputs of the other MPC8280 devices are tied to the address bus lines, thus assigning them

as configuration slaves. See Figure 5-7 .

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PORESET VCC EPROM Control Signals HRESET PORESET Configuration Master Chip A[0–31] D[0–31] RSTCONF HRESET PORESET Configuration Slave Chip 1 D[0–31] RSTCONF A0 HRESET PORESET Configuration Slave Chip 2 D[0–31] RSTCONF A1 Boot EPROM A[..] D[0–7] 5-12 HRESET PORESET Configuration Slave Chip 7 D[0–31] RSTCONF A6

Figure 5-7. Configuring Multiple Chips MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

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Reset

In this system, the configuration master initially reads its own configuration word. It then reads other

configuration words and drives them to the configuration slaves by asserting RSTCONF. As Figure 5-7

shows, this complex configuration is done without additional glue logic. The configuration master controls the whole process by asserting the EPROM control signals and the system’s address signals as needed.

5.4.2.4

Multiple MPC8280s in a System with No EPROM

In some cases, the configuration master capabilities of the MPC8280 cannot be used. This can happen for example if there is no boot EPROM in the system or the boot EPROM is not controlled by an MPC8280.

If this occurs, the user must do one of the following: • • • Accept the default configuration, Emulate the configuration master actions in external logic (where the MPC8280 is a configuration slave).

The external hardware should be connected to all RSTCONF pins of the different devices and to the upper 32 bits of the data bus. During PORESET, the rising edge the external hardware should negate all RSTCONF inputs to put all of the devices in their configuration slave mode. For 1,024 clocks after PORESET negation, the external hardware can configure the different devices by driving appropriate configuration words on the data bus and asserting RSTCONF for each device to strobe the data being received.

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Part III The Hardware Interface

Intended Audience

Part III is intended for system designers who need to understand how each MPC8280 signal works and how those signals interact.

Contents

Part III describes external signals, clocking, memory control, and power management of the MPC8280.

It contains the following chapters: • • • • • • • •

Chapter 6, “External Signals,”

MPC8280 signals. shows a functional pinout of the MPC8280 and describes the

Chapter 7, “60x Signals,”

describes signals on the 60x bus.

Chapter 8, “The 60x Bus,”

describes the operation of the bus used by PowerPC processors.

Chapter 10, “Clocks and Power Control,”

describes the clocking architecture of the MPC8280.

Chapter 9, “PCI Bridge,”

describes how the PCI bridge enables the MPC8280 to bridge PCI agents gluelessly to a host processor that implements the PowerPC architecture and how it is compliant with PCI Specification Revision 2.2.

Chapter 11, “Memory Controller,”

describes the memory controller, which controlling a maximum of eight memory banks shared between a general-purpose chip-select machine (GPCM) and three user-programmable machines (UPMs).

Chapter 12, “Secondary (L2) Cache Support,”

provides information about implementation and configuration of a level-2 cache.

Chapter 13, “IEEE 1149.1 Test Access Port,”

describes the dedicated user-accessible test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

Suggested Reading

This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. Freescale Semiconductor

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MPC82xx Documentation

Supporting documentation for the MPC8280 can be accessed through the world-wide web at www.freescale.com. This documentation includes technical specifications, reference materials, and detailed applications notes.

Conventions

n

¬ | & This document uses the following notational conventions:

Bold

Bold entries in figures and tables showing registers and parameter RAM should be initialized by the user.

mnemonics

italics

Instruction mnemonics are shown in lowercase bold. Italics indicate variable command parameters, for example, bcctrx.

0x0 0b0 REG[FIELD] x Book titles in text are set in italics.

Prefix to denote hexadecimal number Prefix to denote binary number Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.

In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value NOT logical operator AND logical operator OR logical operator

Acronyms and Abbreviations

Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.

Term

BD BIST BRI CAM

Table I-i. Acronyms and Abbreviated Terms Meaning

Buffer descriptor Built-in self test Basic rate interface Content-addressable memory III-2

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Term

CPM CRC DMA DPLL DRAM DSISR EA EEST GCI GPCM HDLC I 2 C IDL IEEE IrDA ISDN JTAG LIFO LRU LSB lsb LSU MAC MMU MSB msb MSR NMSI OSI PCI PCMCIA

Table I-i. Acronyms and Abbreviated Terms (continued) Meaning

Communications processor module Cyclic redundancy check Direct memory access Digital phase-locked loop Dynamic random access memory Register used for determining the source of a DSI exception Effective address Enhanced Ethernet serial transceiver General circuit interface General-purpose chip-select machine High-level data link control Inter-integrated circuit Inter-chip digital link Institute of Electrical and Electronics Engineers Infrared Data Association Integrated services digital network Joint Test Action Group Last-in-first-out Least recently used Least-significant byte Least-significant bit Load/store unit Multiply accumulate Memory management unit Most-significant byte Most-significant bit Machine state register Nonmultiplexed serial interface Open systems interconnection Peripheral component interconnect Personal Computer Memory Card International Association Freescale Semiconductor

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Term

PRI Rx SCC SCP SDLC SDMA SI SIU SMC SNA SPI SPR SRAM TDM TLB TSA Tx UART UISA UPM USART

Table I-i. Acronyms and Abbreviated Terms (continued) Meaning

Primary rate interface Receive Serial communications controller Serial control port Synchronous data link control Serial DMA Serial interface System interface unit Serial management controller Systems network architecture.

Serial peripheral interface Special-purpose register Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit Universal asynchronous receiver/transmitter User instruction set architecture User-programmable machine Universal synchronous/asynchronous receiver/transmitter III-4

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Chapter 6 External Signals

This chapter describes the external signals. A more detailed description of 60x bus signals is provided in

Chapter 8, “The 60x Bus.”

6.1

Functional Pinout

Figure 6-1 shows MPC8280 signals grouped by function. Note that many signals are multiplexed and this

figure does not indicate how these signals are multiplexed.

NOTE

A bar over a signal name indicates that the signal is active low—for example, BB (bus busy). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0–1] (transfer size signals) are referred to as asserted when they are high and negated when they are low.

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External Signals

VCCSYN/GNDSYN/VCCSYN1//VDDH/ VDD/VSS PCI_PAR/

L_A14

SMI/PCI_FRAME/

L_A15

PCI_TRDY/

L_A16

CKSTOP_OUT/PCI_IRDY/

L_A17

PCI_STOP/

L_A18

PCI_DEVSEL/

L_A19

PCI_IDSEL/

L_A20

PCI_PERR/

L_A21

PCI_SERR/

L_A22

PCI_REQ0/

L_A23

CPCI_HS_ES/PCI_REQ1/

L_A24

PCI_GNT0/

L_A25

CPCI_HS_LED/PCI_GNT1/

L_A26

CPCI_HS_ENUM/GNT2/

L_A27

CORE_SRESET/PCI_RST/

L_A28

PCI_INTA/

L_A29

PCI_REQ2/

L_A30

DLLOUT/

L_A31

PCI_AD[31-0]/

LCL_D[0–31]

PCI_C/BE[3-0]/

LCL_DP[0–3]

⎯⎯⎯> 100 <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯⎯ <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 4 PCI_CFG[3–0]/LBS[0–3]/ <⎯⎯⎯ LSDDQM[0–3]/

LWE[0–3]

PCI_MODCK_H0/LGPL0/

LSDA10

PCI_MODCK_H1/LGPL1/

LSDWE

PCI_MODCK_H2/LGPL2/LSDRAS/

LOE

PCI_MODCK_H3/LGPL3/

LSDCAS

LPBS/LGPL4/LUPMWAIT/

LGTA

PCI_MODCK/

LGPL5 LWR

<⎯⎯⎯ <⎯⎯⎯ <⎯⎯⎯ <⎯⎯⎯ <⎯⎯> <⎯⎯> <⎯⎯>

PA[0–31] PB[4–31] PC[0–31] PD[4–31]

4 <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> 32 28 32 28 PCI_RST/

PORESET

⎯⎯⎯>

RSTCONF

⎯⎯⎯>

HRESET

<⎯⎯>

SRESET

<⎯⎯>

QREQ

<⎯⎯⎯

XFC

⎯⎯⎯>

CLKIN1

⎯⎯⎯>

TRIS

⎯⎯⎯> BNKSEL[0]/TC[0]/AP[1]/

MODCK1

<⎯⎯> BNKSEL[1]/TC[1]/AP[2]/

MODCK2

<⎯⎯> BNKSEL[2]/TC[2]/AP[3]/

MODCK3

<⎯⎯>

PCI_MODE

⎯⎯⎯>

CLKIN2

NC ⎯⎯⎯> ⎯⎯⎯> 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1

L O C A L B U S M E M C P I O R S T C L K 6 0 x B U S M E M C J T A G

5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 64 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 2 1 1 8 1 1 1 1 1 32 <⎯⎯>

A[0–31]

<⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯⎯ <⎯⎯> ⎯⎯⎯> ⎯⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯>

TT[0–4] TSIZ[0–3] TBST GBL CI

/BADDR29/IRQ2

WT

/BADDR30/IRQ3

L2_HIT CPU_BG CPU_DBG CPU_BR BR BG ABB TS AACK ARTRY DBG DBB

/IRQ1 /IRQ2 /IRQ3

D[0–63] NC

/IRQ4 /BADDR31/IRQ5/CINT /DP0/RSRV/EXT_BR2

IRQ1 IRQ2 IRQ3/

/DP1/EXT_BG2 /DP2/TLBISYNC/EXT_DBG2 DP3/CKSTP_OUT/EXT_BR3 <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> <⎯⎯> ⎯⎯⎯> <⎯⎯> <⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> ⎯⎯⎯> <⎯⎯> ⎯⎯⎯>

IRQ4/ IRQ5/ IRQ6/ IRQ7/ PSDVAL TA TEA IRQ0 IRQ7

DP4/CORE_SRESET/EXT_BG3 DP5/TBEN/EXT_DBG3/CINT DP6/CSE0 DP7/CSE1 /NMI_OUT /INT_OUT/APE

CS[0–9] CS[10] CS[11] BADDR[27–28] ALE BCTL0 PWE[0–7] PSDA10 PSDWE POE

/PSDRAS/PGPL2

PSDCAS PGTA

/BCTL1 /AP[0] /PSDDQM[0–7]/PBS[0–7] /PGPL0 /PGPL1 /PGPL3 /PUPMWAIT/PGPL4/PPBS <⎯⎯−

PSDAMUX

/PGPL5

TMS

<⎯⎯⎯

TDI

<⎯⎯− <⎯⎯− −⎯⎯>

TCK TRST TDO Figure 6-1. MPC8280 External Signals

6.2

Signal Descriptions

The MPC8280 system bus, shown in Table 6-1 , consists of all the signals that interface with the external

bus. Many of these pins perform different functions, depending on how the user assigns them. 6-2

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External Signals Table 6-1. External Signals

BR BG ABB

Signal Description

60x bus request—This is an output when an external arbiter is used and an input when an internal arbiter is used. As an output the MPC8280 asserts this pin to request ownership of the 60x bus. As an input an external master should assert this pin to request 60x bus ownership from the internal arbiter.

60x bus grant—This is an output when an internal arbiter is used and an input when an external arbiter is used. As an output the MPC8280 asserts this pin to grant 60x bus ownership to an external bus master. As an input the external arbiter should assert this pin to grant 60x bus ownership to the MPC8280.

60x address bus busy—(Input/output) As an output the MPC8280 asserts this pin for the duration of the address bus tenure. Following an AACK, which terminates the address bus tenure, the MPC8280 negates ABB for a fraction of a bus cycle and than stops driving this pin. As an input the MPC8280 will not assume 60x bus ownership as long as it senses this pin is asserted by an external 60x bus master.

IRQ2 TS A[0–31] TT[0–4] TBST TSIZ[0–3] AACK ARTRY DBG Interrupt Request 2—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

60x bus transfer start—(Input/output) Assertion of this pin signals the beginning of a new address bus tenure. The MPC8280 asserts this signal when one of its internal 60x bus masters (core, DMA, PCI bridge) begins an address tenure. When the MPC8280 senses this pin being asserted by an external 60x bus master, it will respond to the address bus tenure as required (snoop if enabled, access internal MPC8280 resources, memory controller support).

60x address bus—These are input/output pins. When the MPC8280 is in external master bus mode, these pins function as the 60x address bus. The MPC8280 drives the address of its internal 60x bus masters and respond to addresses generated by external 60x bus masters. When the MPC8280 is in internal master bus mode, these pins are used as address lines connected to memory devices and controlled by the MPC8280’s memory controller.

60x bus transfer type—These are input/output pins. The 60x bus master drives these pins during the address tenure to specify the type of the transaction.

60x bus transfer burst—(Input/output) The 60x bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers 4 double words).

60x transfer size—These are input/output pins. The 60x bus master drives these pins with a value indicating the amount of bytes transferred in the current transaction.

60x address acknowledge—This is an input/output signal. A 60x bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal terminates the address tenure.

60x address retry—(Input/output) Assertion of this signal indicates that the bus transaction should be retried by the 60x bus master. The MPC8280 asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations.

60x data bus grant—This is an output when an internal arbiter is used and an input when an external arbiter is used. As an output the MPC8280 asserts this pin to grant 60x data bus ownership to an external bus master. As an input the external arbiter should assert this pin to grant 60x data bus ownership to the MPC8280.

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External Signals Table 6-1. External Signals (continued)

DBB

Signal Description

60x data bus busy—(Input/output) As an output the MPC8280 asserts this pin for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MPC8280 negates DBB for a fraction of a bus cycle and than stops driving this pin. As an input, the MPC8280 does not assume 60x data bus ownership as long as it senses DBB asserted by an external 60x bus master.

IRQ3 D[0–63] DP[0] RSRV EXT_BR2 IRQ1 DP[1] EXT_BG2 IRQ2 DP[2] TLBISYNC EXT_DBG2 Interrupt request 3—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

60x data bus—These are input/output pins. In write transactions the 60x bus master drives the valid data on this bus. In read transactions the 60x slave drives the valid data on this bus.

60x data parity 0—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 0 pin should give odd parity (odd number of 1’s) on the group of signals that includes data parity 0 and D[0–7].

Reservation—The value driven on this output pin represents the state of the coherency bit in the reservation address register that is used by the

lwarx

and

stwcx.

instructions.

External bus request 2—(Input). An external master should assert this pin to request 60x bus ownership from the internal arbiter.

Interrupt request 1—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

60x data parity 1—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 1 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes data parity 1 and D[8–15].

External bus grant 2—(Output) The MPC8280 asserts this pin to grant 60x bus ownership to an external bus master.

Interrupt request 2—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

60x data parity 2—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 2 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes data parity 2 and S[16–23].

TLB sync—This input pin can be used to synchronize 60x core instruction execution to hardware indications. Asserting this pin will force the core to stop instruction execution following a

tlbsync

instruction execution. The core resumes instructions execution once this pin is negated.

External data bus grant 2—(Output) The MPC8280 asserts this pin to grant 60x data bus ownership to an external bus master.

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External Signals Table 6-1. External Signals (continued)

IRQ3

Signal Description

Interrupt request 3—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

DP[3] 60x data parity 3—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 3 pin should give odd parity (odd number of 1’s) on the group of signals that includes data parity 3 and D[24–31].

CKSTP_OUT EXT_BR3 Checkstop output—(Output) Assertion indicates that the core is in its checkstop mode.

IRQ4 External bus request 3—(Input) An external master should assert this pin to request 60x bus ownership from the internal arbiter.

Interrupt request 4—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

DP[4] 60x data parity 4—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 4 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes data parity 4 and D[32–39].

CORE_SRESET EXT_BG3 IRQ5 DP[5] Core system reset—(Input) Asserting this pin will force the core to branch to its reset vector.

External bus grant 3—(Output) The MPC8280 asserts this pin to grant 60x bus ownership to an external bus master.

Interrupt request 5—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

60x data parity 5—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 5 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes data parity 5 and D[40–47].

TBEN EXT_DBG3 CINT IRQ6 Time base enable—This is a count enable input to the Time Base counter in the core.

External data bus grant 3—(Output) The MPC8280 asserts this pin to grant 60x data bus ownership to an external bus master.

Critical interrupt—Critical interrupt input to the core Interrupt request 6—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

DP[6] CSE[0] IRQ7 DP[7] 60x data parity 6—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 6 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes data parity 6 and D[48–55].

Cache set entry 0—The cache set entry outputs from the core represent the cache replacement set element for the current core transaction reloading into or writing out of the cache.

Interrupt request 7—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

60x data parity 7—(Input/output) The 60x master or slave that drives the data bus drives also the data parity signals. The value driven on data parity 7 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes data parity 7 and D[56–63].

CSE[1] Freescale Semiconductor Cache set entry 1—The cache set entry outputs from the core represent the cache replacement set element for the current core transaction reloading into or writing out of the cache.

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External Signals Table 6-1. External Signals (continued)

PSDVAL TA TEA GBL

Signal Description

60x data valid—(Input/output) Assertion of the PSDVAL pin indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to indicate 60x data transfer terminations while the PSDVAL signal is asserted with each data beat movement. Thus always when TA is asserted, PSDVAL will be asserted but when PSDVAL is asserted, TA is not necessarily asserted. For example when a double word (2x64 bits) transfer is initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted 3 times without TA and finally both pins will be asserted to terminate the transfer.

Transfer acknowledge—(Input/output) Indicates that a 60x data beat is valid on the data bus. For 60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x burst transfers TA is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer.

Transfer error acknowledge—(Input/output) Assertion of this pin indicates a bus error. 60x masters within the MPC8280 monitor the state of this pin. MPC8280’s internal bus monitor may assert this pin in case it identified a 60x bus transfer that is hung.

Global—(Input/output) When a 60x master within the chip initiates a bus transaction it drives this pin. When an external 60x master initiates a bus transaction it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the system. The MPC8280’s data cache monitors the state of this pin.

IRQ1 CI BADDR29 IRQ2 WT BADDR30 IRQ3 Interrupt request 1—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

Cache inhibit—Output pin. Used for L2 cache control. For each MPC8280 60x transaction initiated in the core, the state of this pin indicates if this transaction should be cached or not. Assertion of the CI pin indicates that the transaction should not be cached. Burst address 29—There are five burst address output pins. These pins are outputs of the 60x memory controller. These pins are used in external master configuration and are connected directly to memory devices controlled by MPC8280’s memory controller. For information on the

use of this signal, see Section 11.2.14, “BADDR[27:31] Signal Connections

.” Interrupt request 2—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

Write through—Output used for L2 cache control. For each core-initiated MPC8280 60x transaction, the state of this pin indicates if the transaction should be cached using write-through or copy-back mode. Assertion of WT indicates that the transaction should be cached using the write-through mode. Burst address 30—There are five burst address output pins. These pins are outputs of the 60x memory controller. These pins are used in external master configuration and are connected directly to memory devices controlled by MPC8280’s memory controller. For information on the

use of this signal, see Section 11.2.14, “BADDR[27:31] Signal Connections

.” Interrupt request 3—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

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External Signals Table 6-1. External Signals (continued) Signal Description

L2_HIT L2 cache hit—(Input) It is used for L2 cache control. Assertion of this pin indicates that the 60x transaction will be handled by the L2 cache. In this case, the memory controller will not start an access to the memory it controls.

IRQ4 CPU_BG BADDR31 IRQ5 CINT CPU_DBG CPU_BR CS[0–9] CS[10] BCTL1 CS[11] AP[0] BADDR[27–28] ALE Interrupt request 4—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

CPU bus grant—(Output) The value of the 60x core bus grant is driven on this pin to be used by an external MPC2605GA L2 cache. The driven bus grant is not qualified; that is, when using an external arbiter, the user should qualify this signal with the bus grant input to the MPC8280 before connecting it to the L2 cache.

Burst address 31—There are five burst address output of the 60x memory controller used in an external master configuration and are connected directly to the memory devices controlled by

MPC8280’s memory controller. For information on the use of this signal, see Section 11.2.14, “BADDR[27:31] Signal Connections .”

Interrupt Request 5—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

Critical interrupt—Critical interrupt input to the core CPU data bus grant—(Output) Valid only when using the internal arbiter (PPC_ACR[EARB] = 0). The OR of all data bus grant signals for internal masters from the internal arbiter is driven on CPU_DBG. CPU_DBG should be connected to the CPU DBG input of an external MPC2605GA L2 cache. (If an external arbiter is used, the CPU DBG input of the external MPC2605GA L2 cache should be connected to the DBG driven from the external arbiter to this MPC8280.) CPU bus request—(Output) The value of the 60x core bus request is driven on this pin for the use of an external L2 cache.

Chip select—These are output pins that enable specific memory devices or peripherals connected to MPC8280 buses. Chip select—These are output pins that enable specific memory devices or peripherals connected to MPC8280 buses.

Buffer control 1—Output signal whose function is controlling buffers on the 60x data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR),”

for details.

Chip select—Output that enable specific memory devices or peripherals connected to MPC8280 buses.

Address parity 0—(Input/output) The 60x master that drives the address bus, drives also the address parity signals. The value driven on address parity 0 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes address parity 0 and A[0–7].

Burst address 27–28—There are five burst address output pins. These pins are outputs of the 60x memory controller. Used in external master configuration and connected directly to the memory devices controlled by MPC8280’s memory controller. For information on the use of these signals, see

Section 11.2.14, “BADDR[27:31] Signal Connections .”

Address latch enable—This output pin controls the external address latch that should be used in external master 60x bus configuration.

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External Signals Table 6-1. External Signals (continued) Signal Description

BCTL0 PWE[0–7] Buffer control 0—Output whose function is controlling buffers on the 60x data bus. Usually used with BCTL1 that is multiplexed on CS10. The exact function of this pin is defined by the value of

SIUMCR[BCTLC]. See Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR),”

for details.

60x bus write enable—Outputs of the 60x bus GPCM. These pins select byte lanes for write operations.

PSDDQM[0–7] PBS[0–7] PSDA10 PGPL0 PSDWE PGPL1 POE PSDRAS PGPL2 PSDCAS PGPL3 PGTA PUPMWAIT PGPL4 PPBS 60x bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

60x bus UPM byte select—The byte select pins are outputs of the UPM in the memory controller. They are used to select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device.

60x bus SDRAM A10—(Output) from the 60x bus SDRAM controller. Part of the address when a row address is driven and is part of the command when a column address is driven.

60x bus UPM general purpose line 0—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

60x bus SDRAM write enable—(Output) from the 60x bus SDRAM controller. Should be connected to SDRAMs’ WE input.

60x bus UPM general purpose line 1—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

60x bus output enable—The output enable pin is an output of the 60x bus GPCM. Controls the output buffer of memory devices during read operations.

60x bus SDRAM ras—Output from the 60x bus SDRAM controller. Should be connected to SDRAMs’ RAS input.

60x bus UPM general purpose line 2—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

60x bus SDRAM CAS—Output from the 60x bus SDRAM controller. Should be connected to SDRAMs’ CAS input.

60x bus UPM general purpose line 3—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

60x GPCM TA—This input pin is used for transaction termination during GPCM operation. Requires external pull up resistor for proper operation.

60x bus UPM wait—This is an input to the UPM. An external device may hold this pin high to force the UPM to wait until the device is ready for the continuation of the operation.

60x bus UPM general purpose line 4—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

60x bus parity byte select—In systems in which data parity is stored in a separate chip, this output is used as the byte-select for that chip.

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External Signals Table 6-1. External Signals (continued) Signal Description

PSDAMUX 60x bus SDRAM address multiplexer—This output pin controls the 60x SDRAM address multiplexer when the MPC8280 is in external master mode.

PGPL5 LWE[0–3] 60x bus UPM general purpose line 5—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

Local bus write enable—The write enable pins are outputs of the Local bus GPCM. These pins select specific byte lanes for write operations.

LSDDQM[0–3] LBS[0–3] PCI_CFG[0-3] LSDA10 LGPL0 Local bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

Local bus UPM byte select—The byte select pins are outputs of the UPM in the memory controller. They are used to select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device.

PCI Configuration—In PCI mode, PCI_CFG[0-3] configure the PCI bridge to Host or agent and control the PCI arbiter operation: • PCI_CFG[0] is PCI_HOST, when High enables the PCI bridge for Agent operation, when Low enables the PCI as Host. • PCI_CFG[1] is PCI_ARB_EN, when Low enables the PCI internal arbiter logic, when High disables the internal arbiter logic (and an external arbiter should be used).

• PCI_CFG[2] is the DLL_Enable. In PCI mode, this pin should be pulled high externally in order to use the DLL. • PCI_CFG[3] is reserved and should be pulled high externally.

Local bus SDRAM A10—Output from the 60x bus SDRAM controller. Is part of the address when a row address is driven and is part of the command when a column address is driven.

Local bus UPM general purpose line 0—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

PCI_MODCK_H0 PCI MODCK_H0—In PCI mode, defines the operating mode of internal clock circuits.

LSDWE Local bus SDRAM write enable—Output from the local bus SDRAM controller. Should be connected to the WE inputs of the SDRAMs.

LGPL1 Local bus UPM general purpose line 1—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

PCI_MODCK_H1 LOE PCI MODCK_H1—In PCI mode, defines the operating mode of internal clock circuits.

Local bus output enable—The output enable pin is an output of the Local bus GPCM. Controls the output buffer of memory devices during read operations.

LSDRAS LGPL2 Local bus SDRAM RAS—Output from the Local bus SDRAM controller. Should be connected to the SDRAM RAS input.

Local bus UPM general purpose line 2—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

PCI_MODCK_H2 PCI MODCK_H2—In PCI mode, defines the operating mode of internal clock circuits.

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External Signals Table 6-1. External Signals (continued) Signal Description

LSDCAS Local bus SDRAM CAS—Output from the Local bus SDRAM controller. Should be connected to the CAS inputs of the SDRAMs.

LGPL3 LUPMWAIT Local bus UPM general purpose line 3—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

PCI_MODCK_H3 LGTA PCI MODCK_H3—In PCI mode, defines the operating mode of internal clock circuits.

Local bus GPCM TA—This input pin is used for transaction termination during GPCM operation. Requires external pull up resistor for proper operation.

LGPL4 Local bus UPM wait—This is an input to the UPM. An external device may hold this pin high to force the UPM to wait until the device is ready for the continuation of the operation.

Local bus UPM general purpose line 4—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

LPBS LGPL5 PCI_MODCK LWR L_A14 Local bus parity byte select—In systems in which the data parity is stored in a separate chip, this output is used as the byte select for that chip.

Local bus UPM general purpose line 5—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.

PCI MODCK—In PCI mode, defines additional operating modes of internal clock circuits.

Local write—The local write pin is an output from the local bus memory controller. It is used to distinguish between read and write transactions.

Local bus address 14—Local bus address bit 14 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI_PAR L_A15 SMI PCI_FRAME L_A16 PCI_TRDY PCI parity—PCI parity input/output pin. Assertion of this pin indicates that odd parity is driven across PCI_AD[31-0] and PCI_C/BE[3–0] during address and data phases. Negation of PCI_PAR indicates that even parity is driven across the PCI_AD[31-0] and PCI_C / BE[3–0] during address and data phases.

Local bus address 15—Local bus address bit 15 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

System management interrupt—System management interrupt input to the core.

PCI frame—PCI cycle frame input / output pin. Used by the current PCI master to indicate the beginning and duration of an access. Driven by the MPC8280 when its PCI interface is the master of the access. Otherwise, it is an input.

Local bus address 16—Local bus address bit 16 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI target ready—PCI target ready input/output pin. This pin is driven by the MPC8280 when its PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is ready to send or accept a data beat.

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External Signals Table 6-1. External Signals (continued)

L_A17

Signal Description

Local bus address 17—Local bus address bit 17 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI_IRDY CKSTOP_OUT L_A18 PCI_STOP L_A19 PCI_DEVSEL L_A20 PCI_IDSEL L_A21 PCI_PERR L_A22 PCI_SERR L_A23 PCI_REQ0 PCI initiator ready—PCI initiator ready input/output pin. This pin is driven by the MPC8280 when its PCI interface is the initiator of a PCI transfer. Assertion of this pin indicates that the PCI initiator is ready to send or accept a data beat.

Checkstop output—(Output) Assertion of CKSTOP_OUT indicates the core is in checkstop mode. Local bus address 18—Local bus address bit 18 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI stop—PCI stop input/output pin. This pin is driven by the MPC8280 when its PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is requesting the master to stop the current PCI transfer.

Local bus address 19—Local bus address bit 19 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI device select—PCI device select input/output pin. This pin is driven by the MPC8280 when its PCI interface has decoded its own address as the target of the current PCI transfer. As an input, PCI_DEVSEL indicates whether any device on the PCI bus has been selected.

Local bus address 20—Local bus address bit 20 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI initialization device select—(Input) Used to select the MPC8280’s PCI interface during a PCI configuration cycle.

Local bus address 21—Local bus address bit 21 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI parity error—PCI data parity error input/output pin. Assertion of this pin indicates that a data parity error was detected during a PCI transfer (except for a special cycle).

Local bus address 22—Local bus address bit 22 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI system error—PCI system error input/output pin. Assertion of this pin indicates that a PCI system error was detected during a PCI transfer. The PCI system error is for reporting address parity errors, data parity errors on a special cycle command, or other catastrophic system errors.

Local bus address 23—Local bus address bit 23 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI arbiter request 0—PCI request 0 input/output pin. When the MPC8280’s internal PCI arbiter is used, this is an input pin. In this mode assertion of this pin indicates that an external PCI device is requesting the PCI bus. When an external PCI arbiter is used, this is an output pin. In this mode assertion of this pin indicates that the MPC8280’s PCI interface is requesting the PCI bus.

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External Signals Table 6-1. External Signals (continued)

L_A24

Signal Description

Local bus address 24—Local bus address bit 24 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI_REQ1 CPCI_HS_ES L_A25 PCI_GNT0 L_A26 PCI_GNT1 PCI arbiter request 1—PCI request 1 input pin. When the MPC8280’s internal PCI arbiter is used, assertion of this pin indicates that an external PCI device is requesting the PCI bus.

CompactPCI Hot Swap Ejector Switch—Hot Swap Ejector Switch input pin. In a CompactPCI system, when the MPC8280’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface to connect to the ejector switch logic. 0 Switch is closed 1 Switch is open Important note: When functioning as the CPCI_HS_ES input, this signal must be filtered (debounced) by an external circuit. Do not connect this input directly to the ejector switch. The input must be a monotonically rising/falling signal.

Local bus address 25—Local bus address bit 25 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI arbiter grant 0—PCI grant 0 input/output pin. When the MPC8280’s internal PCI arbiter is used, this is an output pin. In this mode, assertion of PCI_GNT0 indicates that an the external PCI device that requested the PCI bus with PCI_REQ0 is granted the bus. When an external PCI arbiter is used, this is an input pin. In this mode, assertion of PCI_GNT0 indicates that the MPC8280’s PCI interface is granted the PCI bus.

Local bus address 26—Local bus address bit 26 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI arbiter grant 1—PCI grant 1 output pin. When the MPC8280’s internal PCI arbiter is used, assertion of PCI_GNT1 indicates that the external PCI device that requested the PCI bus with PCI_REQ1 pin is granted the bus.

CPCI_HS_LED L_A27 CompactPCI Hot Swap LED—Hot Swap LED output pin. In CompactPCI system, when the MPC8280’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface to connect to the Hot Swap LED. The Hot Swap pins are not available when the internal arbiter is used.

0 LED is off 1 LED is on Local bus address 27—Local bus address bit 27 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI_GNT2 CPCI_HS_ENUM PCI arbiter grant 2—PCI grant 2 output pin. When the MPC8280’s internal PCI arbiter is used, assertion of PCI_GNT2 indicates that the external PCI device that requested the PCI bus with PCI_REQ2 pin is granted the bus. CompactPCI Hot Swap Enumerator—Hot Swap ENUM output pin. In CompactPCI system, when the MPC8280’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface to connect to the host as the enumeration request. 6-12

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External Signals Table 6-1. External Signals (continued)

L_A28

Signal Description

Local bus address 28—Local bus address bit 28 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI_RST CORE_SRESET L_A29 PCI_INTA L_A30 PCI_REQ2 L_A31 DLLOUT LCL_D[0–31] PCI_AD[31-0] LCL_DP[0–3] PCI_C / BE[3-0] IRQ0 NMI_OUT PCI reset—PCI reset output pin. When the MPC8280 is the host in the PCI system, PCI_RST is an output. Core system reset—This is an input to the core. When this input pin is asserted the core branches to its reset vector.

Local bus address 29—Local bus address bit 29 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI INTA—(output) When the MPC8280 is an agent of the PCI system, this pin is an output used by the MPC8280 to signal an interrupt to the PCI host. (When the MPC8280 is the host in the PCI system, the general IRQ pins are used for delivering PCI interrupts to the host.) Local bus address 30—Local bus address bit 30 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

PCI arbiter request 2—PCI request 2 input pin. When the MPC8280’s internal PCI arbiter is used, assertion of this pin indicates that an external PCI device is requesting the PCI bus.

Local bus address 31—Local bus address bit 31 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant.

DLL Clock Out—DLL output pin. This is the DLL output reference clock. See

Figure 10-2 and

Figure 10-3 .

Local bus data—Local bus data input/output pins. In the local data bus bit 0 is most significant and bit 31 is least significant.

PCI address/data—PCI bus address/data input/output pins. During an address phase PCI_AD[31-0] contains a physical address, during a data phase PCI_AD[31-0] contains the data bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb.

Local bus data parity—Local bus data parity input/output pins. In local bus write operations the MPC8280 drives these pins. In local bus read operations the accessed device drives these pins. LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0–7]. LCL_DP[1] is driven with a value that gives odd parity with LCL_D[8–15]. LCL_DP[2] is driven with a value that gives odd parity with LCL_D[16–23]. LCL_DP[3] is driven with a value that gives odd parity with LCL_D[24–31]. PCI command/byte enable—PCI command/byte enable input/output pins. The MPC8280 drives these pins when it is the initiator of a PCI transfer. During an address phase the PCI_C/BE[3-0] defines the command, during the data phase PCI_C/BE[3-0] defines the byte enables. PCI_C/BE[3] is the msb and PCI_C/BE[0] is the lsb.

Interrupt request 0—This input is an external line that causes an MCP interrupt to the core. Non-maskable interrupt output—This is an output driven from MPC8280’s internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt is pending in MPC8280’s internal interrupt controller.

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External Signals Table 6-1. External Signals (continued)

IRQ7

Signal Description

Interrupt request 7—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.

INT_OUT APE TRST TCK TMS TDI TDO TRIS PORESET PCI_RST HRESET SRESET QREQ RSTCONF MODCK1 AP[1] TC[0] BNKSEL[0] Interrupt output—This is an output driven from MPC8280’s internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in MPC8280’s internal interrupt controller.

Address parity error—This output pin is asserted when the MPC8280 detects wrong parity driven on its address parity pins by an external master.

Test reset (JTAG)— Input only. This is the reset input to the MPC8280’s JTAG/COP controller. See

Section 13.1, “Overview,”

and

Section 13.6, “Nonscan Chain Operation .”

Test clock (JTAG)—Input only. Provides the clock input for MPC8280’s JTAG/COP controller.

Test mode select (JTAG)—Input only. Controls the state of MPC8280’s JTAG/COP controller.

Test data in (JTAG)—Input only. Data input to MPC8280’s JTAG/COP controller.

Test data out (JTAG)—Output only. Data output from MPC8280’s JTAG/COP controller.

Three-state—Asserting TRIS forces all other MPC8280’s pins to high impedance state.

Power-on reset—When asserted, this input line causes the MPC8280 to enter power-on reset state. PCI reset—PCI reset input pin. When the MPC8280 is an agent in the PCI system, PCI_RST is an input. Hard reset—This open drain line, when asserted causes the MPC8280 to enter hard reset state. Soft reset—This open drain line, when asserted causes the MPC8280 to enter the soft reset state. Quiescent request— Output only. Indicates that MPC8280’s internal core is about to enter its low power mode. In the MPC8280 this pin will be typically used for debug purposes.

RSTCONF —Input used during reset configuration sequence of the chip. Find detailed explanation of its function in

Section 5.1.2, “Power-On Reset Flow,”

and

Section 5.4, “Reset Configuration .”

MODCK1—Clock mode input. Defines the operating mode of internal clock circuits.

Address parity 1—(Input/output) The 60x master that drives the address bus, drives also the address parity signals. The value driven on address parity 1 pin should give odd parity (odd number of 1s) on the group of signals that includes address parity 1 and A[8–15].

Transfer Code 0—The transfer code output pins supply information that can be useful for debug purposes for each of the MPC8280’s initiated bus transactions.

Bank Select 0—The bank select outputs are used for selecting SDRAM bank when the MPC8280 is in 60x compatible bus mode. BNKSEL0 is msb of the three BNKSEL signals.

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External Signals Table 6-1. External Signals (continued) Signal Description

MODCK2 MODCK2—Clock mode input. Defines the operating mode of internal clock circuits.

AP[2] TC[1] BNKSEL[1] MODCK3 AP[3] TC[2] BNKSEL[2] XFC CLKIN1 CLKIN2 PCI_MODE PA[0–31] PB[4–31] PC[0–31] PD[4–31] Power Supply Address parity 2—(Input/output) The 60x master that drives the address bus, drives also the address parity signals. The value driven on address parity 2 pin should give odd parity (odd number of 1s) on the group of signals that includes address parity 2 and A[16–23].

Transfer code 1—The transfer code output pins supply information that can be useful for debug purposes for each of the MPC8280’s initiated bus transactions.

Bank select 1—The bank select outputs are used for selecting SDRAM bank when the MPC8280 is in 60x-compatible bus mode.

MODCK3—Clock mode input. Defines the operating mode of internal clock circuits.

Address parity 3—(Input/output) The 60x master that drives the address bus, drives also the address parity signals. The value driven on address parity 3 pin should give odd parity (odd number of 1s) on the group of signals that includes address parity 3 and A[24—31].

Transfer code 2—The transfer code output pins supply information that can be useful for debug purposes for each of the MPC8280’s initiated bus transactions.

Bank select 2—The bank select outputs are used for selecting SDRAM bank when the MPC8280 is in 60x-compatible bus mode. BNKSEL2 is lsb of the three BNKSEL signals.

External filter capacitance—Input connection for an external capacitor filter for PLL circuitry. Clock In—Primary clock input to MPC8280’s PLL. In a PCI system, where the MPC8280 PCI interface is operated from the PCI bus clock, CLKIN should be connected to the PCI bus clock. In that case, the 60x bus clock is driven on CLKOUT. See

Figure 10-2

and Figure 10-3

.

Clock In2—This is the clock input to the MPC8280’s DLL, which is used for deskewing the output

reference clock. See Figure 10-2 and

Figure 10-3 .

PCI mode pin—This pin enables the PCI bridge of the MPC8280.

• When Low, the PCI bridge is enabled, PCI interface replaces the Local bus.

• When High, the PCI bridge is disabled, the MPC8280 operates with the Local bus.

This pin has an internal pull up resistor so it defaults to Local bus operation.

General-purpose I/O port A bits 0–31—CPM port multiplexing is described in Chapter 41, “Parallel I/O Ports .” General-purpose I/O port B bits 4–31—CPM port multiplexing is described in Chapter 41, “Parallel I/O Ports .” General-purpose I/O port C bits 0–31—CPM port multiplexing is described in Chapter 41, “Parallel I/O Ports .” General-purpose I/O port D bits 4–31—CPM port multiplexing is described in Chapter 41, “Parallel I/O Ports .”

VDD—This is the power supply of the internal logic.

VDDH—This is the power supply of the I/O Buffers. VCCSYN—This is the power supply of the PLL circuitry. GNDSYN—This is a special ground of the PLL circuitry. VCCSYN1—This is the power supply of the core’s PLL circuitry.

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External Signals

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Chapter 7 60x Signals

This chapter describes the MPC8280 processor’s external signals. It contains a concise description of individual signals, showing behavior when a signal is asserted and negated, when the signal is an input and an output, and the differences in how signals work in external-master or internal-only configurations.

NOTE

A bar over a signal name indicates that the signal is active low– for example, ARTRY (address retry) and TS (transfer start). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active-low, such as TSIZ[0–3] (transfer size signals) and TT[0–4] (transfer type signals) are referred to as asserted when they are high and negated when they are low.

The 60x bus signals used with MPC8280 are grouped as follows: • • • • • • • • Address arbitration signals—In external arbiter mode, MPC8280 uses these signals to arbitrate for address bus mastership. The MPC8280 arbiter uses these signals to enable an external device to arbitrate for address bus mastership.

Address transfer start signals—These signals indicate that a bus master has begun a transaction on the address bus.

Address transfer signals (address bus)—These signals are used to transfer the address.

Transfer attribute signals—These signals provide information about the type of transfer, such as the transfer size and whether the transaction is single, single extended, bursted, write-through or cache-inhibited.

Address transfer termination signals—These signals are used to acknowledge the end of the address phase of the transaction. They also indicate whether a condition exists that requires the address phase to be repeated.

Data arbitration signals—The MPC8280, in external arbiter mode, uses these signals to arbitrate for data bus mastership. The MPC8280 arbiter uses these signals to enable an external device to arbitrate for data bus mastership.

Data transfer signals—These signals, which consist of the data bus, data parity, and data parity error signals, transfer the data and ensure its integrity.

Data transfer termination signals—Data termination signals are required after each data beat in a data transfer. In a single-beat transaction, the data termination signals also indicate the end of the tenure. For burst accesses or extended port-size accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat.

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60x Signals

7.1

Signal Configuration

Figure 7-1 shows the 60x bus signal configuration grouping of the MPC8280.

NOTE

The MPC8280 hardware specifications provide a pinout showing numbers

of pins. These are shown in Figure 7-1 .

Address Arbitration Address Start Address Bus Transfer Attributes Bus Request (BR) Bus Grant (BG) Address Bus Busy (ABB) Transfer Start (TS) Address (A[0–31]) Address Parity (AP[0–3]) Address Parity Error (APE) Transfer Type (TT[0–4]) Transfer Code (TC[0–2]) Transfer Burst (TBST) Transfer Size (TSIZ[0–3]) Global (GBL) Cache Inhibit (CI) Write-Through (WT) 1 1 1 1 1 1 1 4 1 1 32 64 8 4 1 5 1 1 3 1 1 Data Bus Grant (DBG) Data Bus Busy (DBB) Data (D[0–63]) Data Parity (DP[0–7]) Partial Data Valid Indication (PSDVAL) Transfer Acknowledge (TA) Transfer Error Acknowledge (TEA) Data Arbitration Data Transfer Data Termination Address Termination Address Acknowledge (AACK) Address Retry (ARTRY) 1 1 1 1 Reservation TLBISYNC Processor State

Figure 7-1. Signal Groupings

7.2

Signal Descriptions

This section describes individual MPC8280 60x signals, grouped according to Figure 7-1 . Note that the

following sections briefly summarize signal functions.

Chapter 8, “The 60x Bus,”

describes many of these signals in greater detail, both in terms of their function and how groups of signals interact.

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60x Signals

7.2.1

Address Bus Arbitration Signals

The address arbitration signals are a collection of input and output signals devices use to request address bus mastership, recognize when the request is granted, and indicate to other devices when mastership is

granted. For a detailed description of how these signals interact, see Section 8.4.1, “Address Arbitration.”

Bus arbitration signals have no meaning in internal-only mode.

7.2.1.1

Bus Request (BR)—Output

The bus request (BR) signal is both an input and an output signal on the MPC8280.

7.2.1.1.1

Address Bus Request (BR)—Output

Following are the state meaning and timing comments for the BR signal output.

State Meaning

Asserted—Indicates that MPC8280 is requesting mastership of the address bus. Note that BR may be asserted for one or more cycles and then deasserted due to an internal cancellation of the bus request (for example, due to a load hit in the touch load buffer). See

Section 8.4.1, “Address Arbitration.”

Timing Comments

Negated—Indicates that the MPC8280 is not requesting the address bus. The MPC8280 may have no bus operation pending, it may be parked, or the ARTRY input was asserted on the previous bus clock cycle.

Assertion—May occur on any cycle; does not occur if the MPC8280 is parked and the address bus is idle (BG asserted and ABB input negated).

Negation—Occurs for at least one cycle following a qualified BG even if another transaction is pending; also negated for at least one cycle following any qualified ARTRY on the bus unless MPC8280 asserted ARTRY and requires a snoop copyback; may also be negated if MPC8280 cancels the bus request internally before receiving a qualified BG.

High Impedance—Occurs during a hard reset or checkstop condition

7.2.1.1.2

Address Bus Request (BR)—Input

Following are the state meaning and timing comments for the BR signal input.

State Meaning

Asserted—Indicates that the external master has a bus transaction to perform and is waiting for a qualified BG to begin the address tenure. BR may be asserted even if the two possible pipelined address tenures have already been granted.

Timing Comments

Negated—Indicates that the external master has no bus transaction to perform, or if the device is parked, that it is potentially ready to start a bus transaction on the next clock cycle (with proper qualification, see BG).

Assertion—May occur on any cycle; does not occur if the external master is parked and the address bus is idle (BG asserted and ABB input negated).

Negation—Occurs for at least one cycle after a qualified BG even if another transaction is pending; also negated for at least one cycle following any qualified ARTRY on the bus unless this chip asserted the ARTRY and requires to perform

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60x Signals

a snoop copyback; may also be negated if the external master cancels a bus request internally before receiving a qualified BG.

High Impedance—Occurs during a hard reset or checkstop condition.

7.2.1.2

Bus Grant (BG)

The address bus grant (BG) signal is both an input and an output signal.

7.2.1.2.1

Bus Grant (BG)—Input

The following are the state meaning and timing comments for the BG signal input.

State Meaning

Asserted—Indicates that the MPC8280 may, with the proper qualification, begin a bus transaction and assume ownership of the address bus. A qualified bus grant is generally determined from the bus state as follows: QBG = BG • ¬ABB • ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that the assertion of BR is not required for a qualified bus grant (for bus parking).

Timing Comments

Negated—Indicates that the MPC8280 is not granted next address ownership.

Assertion—May occur on any cycle. Once the MPC8280 has assumed address bus ownership, it does not begin checking for BG again until the cycle after AACK.

Negation—May occur whenever the MPC8280 must be prevented from using the address bus. The MPC8280 may still assume address bus ownership on the cycle BG is negated if it was asserted the previous cycle with other bus grant qualifications.

7.2.1.2.2

Bus Grant (BG)—Output

Following are the state meaning and timing comments for the BG signal output.

State Meaning

Asserted—Indicates that the external device may, with the proper qualification, begin a bus transaction and assume ownership of the address bus. A qualified bus grant is generally determined from the bus state as follows: QBG = BG • ¬ABB • ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that the assertion of BR is not required for a qualified bus grant (for bus parking).

Timing Comments

Negated—Indicates that the external device is not granted next address ownership.

Assertion—May occur on any cycle. Once the external device has assumed address bus ownership, it does not begin checking for BG again until the cycle after AACK.

Negation—May occur when an external device must be kept from using the address bus. The external device may still assume address bus ownership on the cycle that BG is negated if it was asserted the previous cycle with other bus grant qualifications.

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Address Bus Busy (ABB)

The address bus busy (ABB) signal is both an input and an output signal.

7.2.1.3.1

Address Bus Busy (ABB)—Output

Following are the state meaning and timing comments for the ABB output signal.

State Meaning

Asserted—Indicates that the MPC8280 is the current address bus master. The MPC8280 may not assume address bus ownership in case a bus request is internally cancelled by the cycle a qualified BG would have been recognized.

Timing Comments

Negated—Indicates that MPC8280 is not the current address bus master.

Assertion—Occurs the cycle after a qualified BG is accepted by MPC8280 and remains asserted for the duration of the address tenure.

Turn-Off Sequencing—Negates for a fraction of a bus cycle (1/2 minimum, depends on clock mode) starting the cycle following the assertion of AACK. It then goes to the high impedance state.

7.2.1.3.2

Address Bus Busy (ABB)—Input

Following are the state meaning and timing comments for the ABB input signal.

State Meaning

Asserted—Indicates that external device is the address bus master.

Negated—Indicates that the address bus may be available for use by the MPC8280 (see BG). The MPC8280 also tracks the state of ABB on the bus from the TS and AACK inputs. (See section on address arbitration phase.)

Timing Comments

Assertion—May occur whenever the MPC8280 must be prevented from using the address bus.

Negation—May occur whenever the MPC8280 may use the address bus.

7.2.2

Address Transfer Start Signal

In the internal only mode the address transfer start signal has no meaning. Address transfer start signal are input and output signals that indicate that an address bus transfer has begun.

7.2.2.1

Transfer Start (TS)

The TS signal is both an input and an output signal on the MPC8280.

7.2.2.1.1

Transfer Start (TS)—Output

Following are the state meaning and timing comments for the TS output signal.

State Meaning

Asserted—Indicates that the MPC8280 has started a bus transaction and that the address bus and transfer attribute signals are valid. It is also an implied data bus Freescale Semiconductor

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request if the transfer attributes TT[0–4] indicate that a data tenure is required for the transaction.

Negated—Has no special meaning during a normal transaction.

Assertion/Negation—Driven and asserted on the cycle after a qualified BG is accepted by MPC8280; remains asserted for one clock only. Negated for the remainder of the address tenure. Assertion is coincident with the first clock that ABB is asserted.

High Impedance—Occurs the cycle following the assertion of AACK (same cycle as ABB negation).

7.2.2.2

Transfer Start (TS)—Input

Following are the state meaning and timing comments for the TS input signal.

State Meaning

Asserted—Indicates that another device has begun a bus transaction and that the address bus and transfer attribute signals are valid for snooping.

Timing Comments

Negated—Has no special meaning.

Assertion/Negation—Must be asserted for one cycle only and then immediately negated. Assertion may occur at any time during the assertion of ABB.

7.2.3

Address Transfer Signals

In internal only mode the memory controller uses these signals for glueless address transfers to memory and I/O devices.

The address transfer signals are used to transmit the address.

7.2.3.1

Address Bus (A[0–31])

The address bus (A[0–31]) consists of 32 signals that are both input and output signals.

7.2.3.1.1

Address Bus (A[0–31])—Output

Following are the state meaning and timing comments for the A[0–31] output signals.

State Meaning

Content—Specifies the physical address of the bus transaction. For burst or extended operations, the address is a double-word.

Timing Comments

Assertion/Negation—Driven valid on the same cycle that TS is driven/asserted; remains driven/valid for the duration of the address tenure.

High Impedance— Occurs the cycle following the assertion of AACK; no precharge action performed on release.

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Address Bus (A[0–31])—Input

Following are the state meaning and timing comments for the A[0–31] input signals.

State Meaning

Asserted—Indicates that another device has begun a bus transaction and that the address bus and transfer attribute signals are valid for snooping and in slave mode.

Timing Comments

Negated—Has no special meaning.

Assertion/Negation—Must be valid on the same cycle that TS is asserted; sampled by the processor only on this cycle.

7.2.4

Address Transfer Attribute Signals

In internal only mode the address transfer attribute signals have no meaning. The transfer attribute signals are a set of signals that further characterize the transfer—such as the size of the transfer, whether it is a read or write operation, and whether it is a burst or single-beat transfer. For a detailed description of how these signals interact, see

Section 7.2.4, “Address Transfer Attribute Signals.”

7.2.4.1

Transfer Type (TT[0–4])

The transfer type signals (TT[0–4]) consist of five input/output signals on the MPC8280. For a complete description of TT[0–4] signals and transfer type encoding, see

Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding.”

7.2.4.1.1

Transfer Type (TT[0–4])—Output

Following are the state meaning and timing comments for the TT[0–4] output signals on the MPC8280.

State Meaning

Asserted/Negated—Specifies the type of transfer in progress.

Timing Comments

Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.4.1.2

Transfer Type (TT[0–4])—Input

Following are the state meaning and timing comments for the TT[0–4] input signals on the MPC8280.

State Meaning

Asserted/Negated—Specifies the type of transfer in progress for snooping by the MPC8280.

Timing Comments

Assertion/Negation—Same as A[0–31].

7.2.4.2

Transfer Size (TSIZ[0–3])

The transfer size (TSIZ[0–3]) signals consist of four input/output signals on the MPC8280, following are the state meaning and timing comments for the TSIZ[0–3] signals on the MPC8280.

State Meaning

Asserted/Negated—Specifies the data transfer size for the transaction (see

Section 8.4.3.3, “TBST and TSIZ[0–3] Signals and Size of Transfer”

). During graphics transfer operations, these signals form part of the Resource ID (see TBST).

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Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.4.3

Transfer Burst (TBST)

The transfer burst (TBST) signal is an input/output signal on the MPC8280. Following are the state meaning and timing comments for the TBST output/input signal.

State Meaning

Asserted—Indicates that a burst transfer is in progress (see

Section 8.4.3.3, “TBST and TSIZ[0–3] Signals and Size of Transfer”

). During graphics transfer operations, this signal forms part of the Resource ID field from the EAR as follows:

Timing Comments

TBST || TSIZ[0–3] = EAR[28–31]. (See TBST.) Negated—Indicates that a burst transfer is not in progress.

Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.4.4

Global (GBL)

The global (GBL) signal is an input/output signal on the MPC8280.

7.2.4.4.1

Global (GBL)—Output

Following are the state meaning and timing comments for the GBL output signal.

State Meaning

Asserted—Indicates that the transaction is global and should be snooped by other devices. GBL reflects the M bit (WIM bits) from the MMU except during certain transactions.

Negated—Indicates that the transaction is not global and should not be snooped by other devices.

Timing Comments

Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.4.4.2

Global (GBL)—Input

Following are the state meaning and timing comments for the GBL input signal.

State Meaning

Asserted—Indicates that a transaction must be snooped by MPC8280.

Timing Comments

Negated—Indicates that a transaction should not be snooped by MPC8280. (In addition, certain non-global transactions are snooped for reservation coherency.) Assertion/Negation—Same as A[0–31].

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Caching-Inhibited (CI)—Output

The cache inhibit (CI) signal is an output signal on the MPC8280. Following are the state meaning and timing comments for CI.

State Meaning

Asserted—Indicates that the transaction in progress should not be cached. CI reflects the I bit (WIM bits) from the MMU except during certain transactions.

Timing Comments

Negated—Indicates that the transaction should be cached.

Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.4.6

Write-Through (WT)—Output

The write-through (WT) signal is an output signal on the MPC8280. Following are the state meaning and timing comments for WT.

State Meaning

Asserted—Indicates that the transaction should operate in write-through mode. WT reflects the W bit (WIM bits) from the MMU except during certain transactions. WT may be asserted during read transactions.

Timing Comments

Negated—Indicates that the transaction should not operate in write-through mode.

Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.5

Address Transfer Termination Signals

The address transfer termination signals are used to indicate either that the address phase of the transaction has completed successfully or must be repeated, and when it should be terminated. For detailed

information about how these signals interact, see Section 7.2.5, “Address Transfer Termination Signals.”

The address transfer termination signals have no meaning in internal only mode.

7.2.5.1

Address Acknowledge (AACK)

The address acknowledge (AACK) signal is an input/output on the MPC8280.

7.2.5.1.1

Address Acknowledge (AACK)—Output

.Following are the state meaning and timing comments for AACK as an output signal.

State Meaning

Asserted—Indicates that the address tenure of a transaction is terminated. On the cycle following the assertion of AACK, the bus master releases the address-tenure-related signals to the high-impedance state and samples ARTRY.

Timing Comments

Negated—Indicates that the address bus and the transfer attributes must remain driven, if negated during ABB.

Assertion—Occurs a programmable number of clocks after TS or whenever ARTRY conditions are resolved.

Negation—Occurs one clock after assertion.

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Address Acknowledge (AACK)—Input

Following are the state meaning and timing comments for AACK as an input signal.

State Meaning

Asserted—Indicates that a 60x bus slave is terminating the address tenure. On the cycle following the assertion of AACK, the bus master releases the address tenure related signals to the high-impedance state and samples ARTRY.

Negated—Indicates that the address tenure must remain active and the address tenure related signals driven.

Timing Comments

Assertion—Occurs during the 60x bus slave access, at least two clocks after TS.

Negation—Occurs one clock after assertion.

7.2.5.2

Address Retry (ARTRY)

The address retry (ARTRY) signal is both an input and output signal on the MPC8280.

7.2.5.2.1

Address Retry (ARTRY)—Output

Following are the state meaning and timing comments for ARTRY as an output signal.

State Meaning

Asserted—Indicates that the MPC8280 detects a condition in which an address tenure must be retried. If the MPC8280 processor needs to update memory as a result of snoop that caused the retry, the MPC8280 asserts BR the second cycle after AACK if ARTRY is asserted.

Timing Comments

High Impedance—Indicates that the MPC8280 does not need the address tenure to be retried. Assertion—Asserted the third bus cycle following the assertion of TS if a retry is required.

Negation—Occurs the second bus cycle after the assertion of AACK. Since this signal may be simultaneously driven by multiple devices, it negates in a unique fashion. First the buffer goes to high impedance for a minimum of one-half processor cycle (dependent on the clock mode), then it is driven negated for one bus cycle before returning to high impedance.

7.2.5.2.2

Address Retry (ARTRY)—Input

Following are the state meaning and timing comments for the ARTRY input.

State Meaning

Asserted—If the MPC8280 is the address bus master, ARTRY indicates that the MPC8280 must retry the preceding address tenure and immediately negate BR (if asserted). If the associated data tenure has started, the MPC8280 also aborts the data tenure immediately even if the burst data has been received. If the MPC8280 is not the address bus master, this input indicates that the MPC8280 should negate BR for one bus clock cycle immediately after external device asserts ARTRY to permit a copy-back operation to main memory. Note that the subsequent address presented on the address bus may not be the one that generated the assertion of ARTRY.

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Timing Comments 60x Signals

Negated/High Impedance—Indicates that the MPC8280 does not need to retry the last address tenure. Assertion—May occur as early as the second cycle following the assertion of TS and must occur by the bus clock cycle immediately following the assertion of AACK if an address retry is required. Negation—Must occur during the second cycle after the assertion of AACK.

7.2.6

Data Bus Arbitration Signals

The data bus arbitration signals have no meaning in internal-only mode. Like the address bus arbitration signals, data bus arbitration signals maintain an orderly process for determining data bus mastership. Note that there is no data bus arbitration signal equivalent to the address bus arbitration signal BR (bus request), because, except for address-only transactions, TS implies data bus

requests. For a detailed description on how these signals interact, see Section 8.5.1, “Data Bus Arbitration.”

7.2.6.1

Data Bus Grant (DBG)

The data bus grant signal (DBG) is an output/input on the MPC8280.

7.2.6.1.1

Data Bus Grant (DBG)—Input

DBG an input when MPC8280 is configured to an external arbiter. The following are the state meaning and timing comments for DBG.

State Meaning

Asserted—Indicates that the MPC8280 may, with the proper qualification, assume mastership of the data bus. The MPC8280 derives a qualified data bus grant when DBG is asserted and DBB and ARTRY are negated; that is, the data bus is not busy (DBB is negated), and there is no outstanding attempt to perform an ARTRY of the associated address tenure.

Timing Comments

Negated—Indicates that the MPC8280 must hold off its data tenures.

Assertion—May occur any time to indicate the MPC8280 is free to take data bus mastership. It is not sampled until TS is asserted. Negation—May occur at any time to indicate the MPC8280 cannot assume data bus mastership.

7.2.6.1.2

Data Bus Grant (DBG)—Output

DBG signal is output when the MPC8280 configured to use the internal arbiter. Following are the state meaning and timing comments for the DBG signal.

State Meaning

Asserted—Indicates that the external device may, with the proper qualification, assume mastership of the data bus. A qualified data bus grant is defined as the assertion of DBG, negation of DBB, and negation of ARTRY. The requirement for the ARTRY signal is only for the address bus tenure associated with the data bus Freescale Semiconductor

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tenure about to be granted (that is, not for another address tenure available because of address pipelining).

Negated—Indicates that an external device is not granted mastership of the data bus.

Assertion—Occurs on the first clock in which the data bus is not busy and the processor has the highest priority outstanding data transaction.

Negation—Occurs one clock after assertion.

7.2.6.2

Data Bus Busy (DBB)

The data bus busy (DBB) signal is both an input and output signal on the MPC8280.

7.2.6.2.1

Data Bus Busy (DBB)—Output

Following are the state meaning and timing comments for the DBB output signal.

State Meaning

Asserted—Indicates that the MPC8280 is the data bus master. The MPC8280 always assumes data bus mastership if it needs the data bus and determines a qualified data bus grant (see DBG).

Timing Comments

Negated—Indicates that the MPC8280 is not using the data bus.

Assertion—Occurs during the bus clock cycle following a qualified DBG. Negation—Occurs for a minimum of one-half bus clock cycle following the assertion of the final TA following TEA or certain ARTRY cases. High Impedance—Occurs after DBB is negated.

7.2.6.2.2

Data Bus Busy (DBB)—Input

Following are the state meaning and timing comments for the DBB input signal.

State Meaning

Asserted—Indicates that another device is bus master.

Timing Comments

Negated—Indicates that the data bus is free (with proper qualification, see DBG) for use by the MPC8280.

Assertion—Must occur when the MPC8280 must be prevented from using the data bus.

Negation—May occur whenever the data bus is available.

7.2.7

Data Transfer Signals

Data transfer signals are used in the same way in both internal only and external master modes. Like the address transfer signals, the data transfer signals are used to transmit data and to generate and monitor parity for the data transfer. For a detailed description of how data transfer signals interact, see

Section 7.2.7, “Data Transfer Signals.”

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Data Bus (D[0–63])

The data bus (D[0–63]) states have the same meanings in both internal only mode external master mode. The data bus consists of 64 signals that are both inputs and outputs on the MPC8280. Following are the state meaning and timing comments for the data bus.

State Meaning Timing Comments

The data bus holds 8 byte lanes assigned as shown in

Table 7-2

and whether the transfer is a single-beat or burst operation.

.

The number of times the data bus is driven depends on the transfer size, port size,

7.2.7.1.1

Data Bus (D[0–63])—Output

Following are the state meaning and timing comments for the D[0–63] output signals.

State Meaning

Asserted/Negated—Represents the state of data during a data write. Byte lanes not selected for data transfer do not supply valid data. MPC8280 duplicates data to enable valid data to be sent to different port sizes.

Timing Comments

Assertion/Negation—Initial beat coincides with DBB, for bursts, transitions on the bus clock cycle following each assertion of TA and, for port size, transitions on the bus clock cycle following each assertion of PSDVAL.

High Impedance—Occurs on the bus clock cycle after the final assertion of TA, TEA, or certain ARTRY cases.

Table 7-1. Data Bus Lane Assignments Data Bus Signals

D0–D7 D8–D15 D16–D23 D24–D31 D32–D39 D40–D47 D48–D55 D56–D63

Byte Lane

0 1 6 7 2 3 4 5

7.2.7.1.2

Data Bus (D[0–63])—Input

Following are the state meaning and timing comments for the D[0–63] input signals.

State Meaning

Asserted/Negated—Represents the state of data during a data read transaction.

Timing Comments

Assertion/Negation—Data must be valid on the same bus clock cycle that TA and/or PSDVAL is asserted.

7.2.7.2

Data Bus Parity (DP[0–7])

The eight data bus parity (DP[0–7]) signals both output and input signals.

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Data Bus Parity (DP[0–7])—Output

Following are the state meaning and timing comments for the DP[0–7] output signals.

State Meaning

Asserted/Negated—Represents odd parity for each of 8 bytes of data write transactions. Odd parity means that an odd number of bits, including the parity bit, are driven high. The signal assignments are listed in

Table 7-2 .

Table 7-2. DP[0–7] Signal Assignments Signal Name

DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7

Data Bus Signal Assignments

D[0–7] D[8–15 D[16–23] D[24–31] D[32–39] D[40–47] D[48–55] D[56–63]

Timing Comments

Assertion/Negation—The same as the data bus. High Impedance—The same as the data bus.

7.2.7.2.2

Data Bus Parity (DP[0–7])—Input

Following are the state meaning and timing comments for the DP input signals.

State Meaning

Asserted/Negated—Represents odd parity for each byte of read data. Parity is checked on all data byte lanes, regardless of the size of the transfer. Detected even parity causes a checkstop if data parity errors are enabled in the BCS[PAR_EN].

Timing Comments

Assertion/Negation—The same as D[0–63].

7.2.8

Data Transfer Termination Signals

Data termination signals are required after each data beat in a data transfer. Note that in a single-beat transaction that is not a port-size transfer, the data termination signals also indicate the end of the tenure. In burst or port size accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat. For a detailed description of how these signals interact, see

Section 8.5, “Data Tenure Operations.”

7.2.8.1

Transfer Acknowledge (TA)

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Transfer Acknowledge (TA)—Input

Following are the state meaning and timing comments for the TA input signal.

State Meaning

Asserted—Indicates that a single-beat data transfer completed successfully or that a data beat in a burst transfer completed successfully. Note that TA must be asserted for each data beat in a burst transaction. For more information, see

Section 8.5.3, “Data Bus Transfers and Normal Termination

.”

Timing Comments

Negated—(During assertion of DBB) indicates that, until TA is asserted, the MPC8280 must continue to drive the data for the current write or must wait to sample the data for reads.

Assertion—Depends on whether or not the PCI controller can initiate 60x bus global transactions when the address retry mechanism is in use: PCI controller is not used or cannot initiate global transactions— Assertion must occur at least one cycle following AACK for the current transaction; otherwise, assertion may occur at any time during the assertion of DBB. The system can withhold assertion of TA to indicate that the MPC8280 should insert wait states to extend the duration of the data beat. PCI controller can initiate global transactions—Assertion must occur at least one clock cycle following AACK for the current transaction and at least one clock cycle after ARTRY can be asserted. Negation—Must occur after the bus clock cycle of the final (or only) data beat of the transfer. For a burst transfer, the system can assert TA for one bus clock cycle and then negate it to advance the burst transfer to the next beat and insert wait states during the next beat. (Note: when configured for 1:1 clock mode and is performing a burst read into the data cache, the MPC8280 requires two wait states between the assertion of TS and the first assertion of TA for that transaction, or one wait state for 1.5:1 clock mode.)

7.2.8.1.2

Transfer Acknowledge (TA)—Output

Following are the state meaning and timing comments for TA as an output signal.

State Meaning

Asserted—Indicates that the data has been latched for a write operation, or that the data is valid for a read operation, thus terminating the current data beat. If it is the last or only data beat, this also terminates the data tenure.

Timing Comments

Negated—Indicates that master must extend the current data beat (insert wait states) until data can be provided or accepted by the MPC8280. Assertion—Depends on whether or not the PCI controller can initiate 60x bus global transactions when the address retry mechanism is in use: PCI controller is not used or cannot initiate global transactions—Assertion must occur at least one cycle following AACK for the current transaction; occurs on the clock in which the current data transfer can be completed. Freescale Semiconductor

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PCI controller can initiate global transactions—Assertion must occur at least one clock cycle following AACK for the current transaction and at least one clock cycle after ARTRY can be asserted. Negation—Occurs after the clock cycle of the final (or only) data beat of the transfer. For a burst transfer, TA may be negated between beats to insert one or more wait states before the completion of the next beat.

7.2.8.2

Transfer Error Acknowledge (TEA)

The transfer error acknowledge (TEA) signal is both input and output on the MPC8280.

7.2.8.2.1

Transfer Error Acknowledge (TEA)—Input

Following are the state meaning and timing comments for the TEA input signal.

State Meaning

Asserted—Indicates that a bus error occurred. The assertion of TEA causes the negation/high impedance of DBB in the next clock cycle. However, data entering the MPC8280 internal memory resources such as GPRs or caches are not invalidated.

Timing Comments

Negated—Indicates that no bus error was detected. Assertion—May be asserted while DBB is asserted and for the cycle after is TA is asserted during a read operation. TEA should be asserted for one cycle only. Negation—TEA must be negated no later than the negation of DBB.

7.2.8.2.2

Transfer Error Acknowledge (TEA)—Output

Following are the state meaning and timing comments for the TEA output.

State Meaning

Asserted—Indicates that a bus error has occurred. Assertion of TEA terminates the transaction in progress; that is, asserting TA is unnecessary because it is ignored by the target device. An unsupported memory transaction, such as a direct-store access or a graphics read or write, causes the assertion of TEA (provided TEA is enabled and the address transfer matches the MPC8280 memory map).

Timing Comments

Negated—Indicates that no bus error was detected.

Assertion—Occurs on the first clock after the bus error is detected.

Negation—Occurs one clock after assertion.

7.2.8.3

Partial Data Valid Indication (PSDVAL)

The partial data valid indication (PSDVAL) is both an input and output on the MPC8280.

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Partial Data Valid (PSDVAL)—Input

Following are the state meaning and timing comments for the PSDVAL input signal. Note that TA asserts with PSDVAL to indicate the termination of the current transfer and for each complete data beat in burst transactions.

State Meaning

Asserted—Indicates that a beat data transfer completed successfully. Note that PSDVAL must be asserted for each data beat in a single beat, port size and burst transaction,. For more information, see

Section 8.5.5, “Port Size Data Bus Transfers and PSDVAL Termination.”

Timing Comments

Negated—(During DBB) indicates that, until PSDVAL is asserted, the MPC8280 must continue to drive the data for the current write or must wait to sample the data for reads.

Assertion—Must not occur before AACK for the current transaction (if the address retry mechanism is to be used to prevent invalid data from being used by the MPC8280); otherwise, assertion may occur at any time during the assertion of DBB. The system can withhold assertion of PSDVAL to indicate that the MPC8280 should insert wait states to extend the duration of the data beat. Negation—Must occur after the bus clock cycle of the final (or only) data beat of the transfer. For a burst and/or port size transfer, the system can assert PSDVAL for one bus clock cycle and then negate it to insert wait states during the next beat. (Note: when the MPC8280 processor is configured for 1:1 clock mode and is performing a burst read into the data cache, the MPC8280 requires two wait state between the assertion of TS and the first assertion of PSDVAL for that transaction, or 1 wait state for 1.5:1 clock mode.)

7.2.8.3.2

Partial Data Valid (PSDVAL)—Output

Following are the state meaning and timing comments for PSDVAL as an output signal.

State Meaning

Asserted—Indicates that the data has been latched for a write operation, or that the data is valid for a read operation, thus terminating the current data beat. If it is the last or only data beat, this also terminates the data tenure.

Timing Comments

Negated—Indicates that the master must extend the current data beat (insert wait states) until data can be provided or accepted by the MPC8280. Assertion—Occurs on the clock in which the current data transfer can be completed. Negation—Occurs after the clock cycle of the final (or only) data beat of the transfer. For a burst transfer, PSDVAL may be negated between beats to insert one or more wait states before the completion of the next beat.

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Chapter 8 The 60x Bus

The 60x bus, which is used by processors that implement the PowerPC architecture, provides flexible support for the on-chip MPC603 processor as well as other internal and external bus devices. The 60x bus supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as many as 256 bits of data in a four-beat burst. The 60x data bus can be accessed in 8-, 16-, 32-, and 64-bit data ports. The 60x bus supports accesses of 1, 2, 3, and 4 bytes, aligned or unaligned, on 4-byte (word) boundaries; it also supports 64-, 128-, 192-, and 256-bit accesses. The address and data buses support synchronous, one-level pipeline transactions. The 60x bus interface can be configured to support both external and internal masters or internal masters only.

8.1

Terminology

Table 8-1

defines terms used in this chapter.

Table 8-1. Terminology Term

Atomic Beat Burst Cache block Clean Flush Kill Lane Master Modified

Definition

A bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other access to that address. The MPC8280 initiates the read and write separately, but signals the memory system that it is attempting an atomic operation. If the operation fails, status is kept so that MPC8280 can try again.

A single state on the MPC8280 interface that may extend across multiple bus cycles. (An MPC8280 transaction can be composed of multiple address or data beats.) A multiple-beat data transfer whose total size is typically equal to a cache block size (in MPC8280: 32 bytes, or 4 data beats at 8 bytes per beat).

The PowerPC architecture defines the basic unit of coherency as a cache block, which can be considered the same thing as a cache line. An operation that causes a cache block to be written to memory if modified, and then left in a valid, unmodified state in the cache.

An operation that causes a cache block to be invalidated in the cache, and its data, if modified, to be written back to main memory.

An operation that causes a cache block to be invalidated in the cache without writing any modified data to memory.

A sub-grouping of signals within a bus. An 8-bit section of the address or data bus may be referred to as a byte lane for that bus.

The device that owns the address or data bus, the device that initiates or requests the transaction.

Identifies a cache block The M state in a MESI or MEI protocol.

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The 60x Bus Table 8-1. Terminology (continued) Term Definition

Parking Pipelining Slave Granting potential bus mastership without requiring a bus request from that device. This eliminates the arbitration delay associated with the bus request.

Initiating a bus transaction before the current one finishes. This involves running an address tenure for a new bus transaction before the data tenure for a current bus transaction completes.

The device addressed by the master. The slave is identified in the address tenure and is responsible for sourcing or sinking the requested data for the master during the data tenure.

Snooping Monitoring addresses driven by a bus master to detect the need for coherency actions.

Split-transaction A transaction with separate request and response tenures.

Tenure Transaction The period of bus mastership. For MPC8280, there can be separate address bus tenures and data bus tenures.

A complete exchange between two bus devices. A typical transaction is composed of an address tenure and a data tenure, which may overlap or occur separately from the address tenure. A transaction can minimally consist of an address tenure alone.

8.2

Bus Configuration

The 60x bus supports separate bus configurations for internal masters and external bus masters. • • Single-MPC8280 bus mode connects external devices by using only the memory controller. This

is described in Section 8.2.1, “Single-MPC8280 Bus Mode.”

The 60x-compatible bus mode, described in

Section 8.2.2, “60x-Compatible Bus Mode,”

enables connections to other masters and 60x-bus slaves, such as an external L2 cache controller.

The figures in the following sections show how the MPC8280 can be connected in these two configurations.

8.2.1

Single-MPC8280 Bus Mode

In single-MPC8280 bus mode, the MPC8280 is the only bus device in the system. The internal memory

controller controls all devices on the external pins. Figure 8-1 shows the signal connections for

single-MPC8280 bus mode.

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The 60x Bus

MPC8280 A[0–31] APE TS Latch & DRAM MUX I/O TT[0–4] TSIZ[0–3] TBST CI WT GBL AACK ARTRY DBG D[0–63] DP[0–7] TA TEA Memory Control Signals MEM

Figure 8-1. Single-MPC8280 Bus Mode NOTE

In single-MPC8280 bus mode, the MPC8280 uses the address bus as a memory address bus. Slaves cannot use the 60x bus signals because the addresses have memory timing, not address tenure timing.

8.2.2

60x-Compatible Bus Mode

The 60x-compatible bus mode can include one or more potential external masters (for example, an L2 cache, an ASIC DMA, a high-end processor that implements the PowerPC architecture, or a second MPC8280). When operating in a multiprocessor configuration, the MPC8280 snoops bus operations and

maintains coherency between the primary caches and main memory. Figure 8-2

shows how an external processor is attached to the MPC8280.

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The 60x Bus

MPC8280 APE TS BR BG TS A[0–31] AP[0–3] TT[0–4] TSIZ[0–3] TBST CI WT GBL AACK ARTRY DBG Memory Control Signals D[0–63] DP[0–7] Latch Latch & DRAM MUX I/O MEM BR External Device BG DBG TA TEA

Figure 8-2. 60x-Compatible Bus Mode

8.3

60x Bus Protocol Overview

Typically, 60x bus accesses consist of address and data tenures, which in turn each consist of three

phases—arbitration, transfer, and termination, as shown in Figure 8-3.. The independence of the tenures is

indicated by showing the data tenure overlap the next address tenure, which allows split-bus transactions to be implemented at the system level in multiprocessor systems.

Figure 8-3 shows a data transfer that

consists of a single-beat transfer of as many as 256 bits. Four-beat burst transfers of 32-byte cache blocks require data transfer termination signals for each beat of data. Note that the MPC8280 supports port sizes of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not defined by the 60x 8-4

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The 60x Bus

bus specification. For more information, see

Section 8.5.5, “Port Size Data Bus Transfers and PSDVAL Termination.”

Data Tenure Arbitration 1- or 4-Beat Transfer Termination Independent Address and Data Tenures Next Address Tenure Arbitration Transfer Termination

Figure 8-3. Basic Transfer Protocol

The basic functions of the address and data tenures are as follows: • • Address tenure — Arbitration: Address bus arbitration signals are used to request and grant address bus mastership.

— Transfer: After a device is granted address bus mastership, it transfers the address. The address signals and the transfer attribute signals control the address transfer.

— Termination: After the address transfer, the system acknowledges that the address tenure is complete or that it must be repeated, signalled by the assertion of the address retry signal (ARTRY).

Data tenure — Arbitration: After the address tenure begins, the bus device arbitrates for data bus mastership.

— Transfer: After the device is granted data bus mastership, it samples the data bus for read operations or drives the data bus for write operations.

— Termination: Acknowledgment of a successful data transfer is required after each beat in a data transfer. In single-beat transactions, the data termination signals also indicate the end of the tenure. In burst or port-size accesses, data termination signals indicate the completion of individual beats and, after the final data beat, the end of the tenure.

8.3.1

Arbitration Phase

The external bus design permits one device (either the MPC8280 or a bus-attached external device) to be granted bus mastership at a time. Bus arbitration can be handled either by an external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for three external bus masters besides the MPC8280. The arbitration configuration (external or internal) is determined at system reset by sampling configuration pins. See

Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR),”

for more information.

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The 60x Bus

The MPC8280 controls bus access through the bus request (BR) and bus grant (BG) signals. It determines the state of the address and data bus busy signals by monitoring DBG, TS, AACK, and TA, and it qualifies them with ABB and DBB.

The following signals are used for address bus arbitration: • • • BR (bus request)—A device asserts BR to request address bus mastership.

BG (bus grant)—Assertion indicates that a bus device may, with proper qualification, assume mastership of the address bus. A qualified bus grant occurs when BG is asserted while ABB and ARTRY are negated.

ABB (address bus busy)—A device asserts ABB to indicate it is the current address bus master. Note that if all devices assert ABB with TS and would normally negate ABB after AACK is asserted, the devices can ignore ABB because the MPC8280 can internally generate ABB. The MPC8280’s ABB, if enabled, must be tied to a pull-up resistor.

The following signals are used for data bus arbitration: • • DBG (data bus grant)—Indicates that a bus device can, with the proper qualification, assume data bus mastership. A qualified data bus grant occurs when DBG is asserted while DBB and ARTRY are negated.

DBB (data bus busy)—Assertion by the device indicates that the device is the current data bus master. The device master always assumes data bus mastership if it needs the data bus and is given a qualified data bus grant (see DBG). Note that if all devices assert DBB in conjunction with qualified data bus grant and would normally negate DBB after the last TA is asserted, the devices can ignore DBB because the MPC8280 can generate DBB internally. The MPC8280’s DBB signal, if enabled, must be tied to a pull-up resistor. The following is a summary of rules for arbitration: • • Preference among devices is determined at the request level. The MPC8280 supports eight levels of bus requests. When no bus device is requesting the address bus, the MPC8280 parks the device selected in the arbiter configuration register on the bus.

For more information, see Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR).”

8.3.2

Address Pipelining and Split-Bus Transactions

The 60x bus protocol provides independent address and data bus capability to support pipelined and split-bus transaction system organizations. Address pipelining allows the next address tenure to begin before the current data tenure has finished. Although this ability does not inherently reduce memory latency, support for address pipelining and split-bus transactions can greatly improve effective bus/memory throughput. These benefits are most fully realized in shared-memory, multiple-master implementations where bus bandwidth is critical to system performance.

External arbitration (as provided by the MPC8280) is required in systems in which multiple devices share the system bus. The MPC8280 uses the address acknowledge (AACK) signal to control pipelining. The MPC8280 supports both one- and zero-level bus pipelining. One-level pipelining is achieved by asserting AACK to the current address bus master and granting mastership of the address bus to the next requesting 8-6

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The 60x Bus

master before the current data bus tenure has completed. Two address tenures can occur before the current data bus tenure completes. The MPC8280 also supports non-pipelined accesses.

8.4

Address Tenure Operations

This section describes the three phases of the address tenure—address bus arbitration, address transfer, and address termination.

8.4.1

Address Arbitration

Bus arbitration can be handled either by an external arbiter or by the internal on-chip arbiter. The arbitration configuration (external or internal) is chosen at system reset. For internal arbitration, the MPC8280 provides arbitration for the 60x address bus and the system is optimized for three external bus masters besides the MPC8280. The bus request (BR) for the external device is an external input to the arbiter. The bus grant signal for the external device (BG) is output to the external device.The BG signal asserted by MPC8280’s on-chip arbiter is asserted one clock after the current master on the bus has asserted AACK; therefore, it can be called a qualified BG. Assuming that all potential masters negate ABB one clock after receiving AACK, the device receiving BG can start the address tenure (by asserting TS) one clock after receiving BG. In addition to the external signals, there are internal request and grant signals for the MPC8280 processor, communications processor, refresh controller, and the PCI internal bridge. Bus accesses are prioritized, with programmable priority. When a MPC8280’s internal master needs the 60x bus, it asserts the internal bus request along with the request level. The arbiter asserts the internal bus grant for the highest priority request. The MPC8280 supports address bus parking through the use of the parked master bits in the arbiter configuration register. The MPC8280 parks the address bus (asserts the address bus grant signal in anticipation of an address bus request) to the external master or internal masters. When a device is parked, the arbiter can hold BG asserted for a device even if that device has not requested the bus. Therefore, when the parked device needs to perform a bus transaction, it skips the bus request delay and assumes address bus mastership on the next cycle. For this case, BR is not asserted and the access latency seen by the device is shortened by one cycle.

The MPC8280 and external device bus devices qualify BG by sampling ARTRY in the negated state prior to taking address bus mastership. The negation of ARTRY during the address retry window (one cycle after the assertion of AACK) indicates that no address retry is requested. If a device detects ARTRY asserted, it cannot accept a address bus grant during the ARTRY cycle or the cycle following. A device that asserts ARTRY due to a modified cache block hit, for example, asserts its bus request during the cycle after the assertion of ARTRY and assumes bus mastership for the cache block push when it is given a bus grant.

The series of address transfers in Figure 8-4 shows the transfer protocol when the MPC8280 is configured

in 60x-compatible bus mode. In this example, MPC8280 is initially parked on the bus with BG INT-asserted (note that BG INT is an internal signal not seen by the user at the pins), which lets it start an address bus tenure by asserting TS. During the same clock cycle, the external master’s bus request is asserted to request access to the 60x bus, thereby causing the negation of BG INT internally and the assertion of BG at the pin. Following MPC8280’s address tenure, the external master takes the bus and initiates its address transaction. The on-chip arbiter samples BR during the clock cycle in which AACK is Freescale Semiconductor

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asserted; if BR is not asserted (no pending request), it negates BG and asserts the parked bus grant (BG_INT in this example).

The master can assert BR and receive a qualified bus grant without subsequently using the bus. It can negate (cancel) BR before accepting a qualified bus grant. This can occur when a replacement copyback transaction waiting to be run on the bus is killed by a snoop of another bus master. This can also occur when the reservation set by a pending stwcx. transaction is cancelled by a snoop of another master. In both cases, the pending transaction by the processor is cancelled and BR is negated.

CLKOUT BR INT BG INT BR BG ABB ADDR+ TS AACK ARTRY MPC8280 External External MPC8280

Figure 8-4. Address Bus Arbitration with External Bus Master

8.4.2

Address Pipelining

The MPC8280 supports one-level address pipelining by asserting AACK to the current bus master when its data tenure starts and by granting the address bus to the next requesting device before the current data bus tenure completes. Address pipelining improves data throughput by allowing the memory-control hardware to decode a new set of address and control signals while the current data transaction finishes. The MPC8280 pipelines data bus operations in strict order with the associated address operations.

Figure 8-5 shows how address pipelining allows address tenures to overlap the associated data tenures.

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CLKOUT ADDR + ATTR TS AACK DBG TA Address Tenure Data Tenure Address 1 Address 2 Data 1

Figure 8-5. Address Pipelining

Data 2

8.4.3

Address Transfer Attribute Signals

During the address transfer, the address is placed on the address signals, A[0–31]. The bus master provides other signals that characterize the address transfer—transfer type (TT[0–4]), transfer code (TC[0–2]), transfer size (TSIZ[0–3]), and transfer burst (TBST) signals. These signals are discussed in the following sections.

8.4.3.1

Transfer Type Signal (TT[0–4]) Encoding

The transfer type signals define the nature of the transfer requested. They indicate whether the operation

is an address-only transaction or whether both address and data are to be transferred. Table 8-2

describes the MPC8280’s action as master, slave, and snooper.

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The 60x Bus Table 8-2. Transfer Type Encoding TT[0–4] 1 60x Bus Specification 2 MPC8280 as Bus Master MPC8280 as Snooper MPC8280 as Slave

00000 00100 01000 01100 10000 101 00 11000

Command

Clean block

Transaction

Address only

Bus Trans.

Address only (if enabled)

Transaction Source dcbst

(if enabled)

Action on Hit

Not applicable Flush block

sync

Kill block

eieio

Graphics write TLB invalidate Address only Address only Address only Address only (if enabled)

dcbf

(if enabled) Address only (if enabled) Address only

sync

(if enabled)

dcbz

or

dcbi

(if enabled) Address only Address only (if enabled)

eieio

(if enabled) Single-beat write Single-beat write (non-GBL)

ecowx

Address only Not applicable Not applicable Not applicable Not applicable Flush, cancel reservation Not applicable Not applicable Not applicable

Action on Slave Hit

AACK asserted; MPC8280 takes no further action. AACK is asserted; MPC8280 takes no further action.

Assert AACK. BG is negated until MPC8280 buffers are flushed.

AACK is asserted.

Assert AACK. BG is negated until MPC8280 buffers are flushed.

No action.

11100 00001 00101 01001 01101 Graphics read

lwarx

reservation set Reserved

tlbsync icbi

Single-beat read — Address only Single-beat read (non-GBL) Address only Not applicable Not applicable Address only Not applicable Not applicable

eciwx

Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable AACK is asserted; MPC8280 takes no further action.

MPC8280 takes no action.

Address-only operation. AACK is asserted; MPC8280 takes no further action. Illegal Address-only operation. AACK is asserted; MPC8280 takes no further action.

Address-only operation. AACK is asserted; MPC8280 takes no further action.

Illegal 1XX01 00010 Reserved for customer — WR w/flush Single-beat write or Burst Not applicable Single-beat write Not applicable CI, WT store, or non-processor master under Not applicable Flush, cancel reservation Write, assert AACK and TA.

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The 60x Bus Table 8-2. Transfer Type Encoding (continued) TT[0–4] 1 60x Bus Specification 2 MPC8280 as Bus Master MPC8280 as Snooper MPC8280 as Slave Command Transaction Bus Trans.

Transaction Source Action on Hit Action on Slave Hit

00110 01010 01110 10010 10110 11010 11110 WR w/Kill Read Burst Burst (non-GBL) Single-beat read or burst Single-beat read Burst Read with intent to modify Reserved Burst WR w/flush atomic Single-beat write Not applicable Single-beat write Not applicable Castout, ca-op push, or snoop copyback CI load, CI I-fetch or nonprocessor master Load miss, store miss, or I-fetch

stwcx.

Not applicable Kill, cancel reservation Clean or flush Flush Flush, cancel reservation Not applicable Read atomic Read with intent to modify atomic Single-beat read or burst Burst Single-beat read Burst

lwarx

(CI load)

lwarx

(load miss) Clean or flush Flush Write, assert AACK and TA.

Read, assert AACK and TA.

Read, assert AACK and TA.

Write, assert AACK and TA Illegal Read, assert AACK and TA Read, assert AACK and TA 00011 00111 01011 Reserved Reserved — — Not applicable Not applicable Not applicable Not applicable Read with no intent to cache Single-beat read or burst Not applicable Not applicable Not applicable Not applicable Clean Illegal Illegal Read, assert AACK and TA 01111 Reserved — Not applicable Not applicable Not applicable Illegal 1XX11 Reserved for customer — Not applicable Not applicable Not applicable Illegal 1 2 TT1 can be interpreted as a read-versus-write indicator for the bus.

This column specifies the TT encoding for the general 60x protocol. The processor generates or snoops only a subset of those encodings.

NOTE

• • Regarding

Table 8-2 :

For reads, the processor cleans or flushes during a snoop based on the TBST input. The processor cleans for single-beat reads (TBST negated) to emulate read-with-no-intent-to-cache operations.

Castouts and snoop copybacks are generally marked as non-global and are not snooped (except for reservation monitoring). However, other masters performing DMA write operations with the same TT encoding and marked as a global WR operation (whether global or non-global) Freescale Semiconductor

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• will cancel an active reservation during a snoop hit in the reservation register (independent of a snoop hit in the cache).

A non-processor read can cause the internal processor to invalidate the corresponding cache line if it exists.

8.4.3.2

Transfer Code Signals TC[0–2]

The transfer code signals, TC[0–2], provide supplemental information about the corresponding address (mainly regarding the source of the transaction). Note that TCx signals can be used with the TT[0–4] and TBST to further define the current transaction.

Table 8-3. Transfer Code Encoding for 60x Bus 60x Bus TC[0–2]

000 001 010 011 100 101 110 111

Read Write

Core data transaction Core touch load Core instruction fetch Reserved Any write — — — Reserved DMA function code 0 DMA function code 1

8.4.3.3

TBST and TSIZ[0–3] Signals and Size of Transfer

As shown in

Table 8-4 , the transfer size signals (TSIZ[0–3]) and the transfer burst signal (TBST) together

indicate the size of the requested data transfer. These signals can be used with address bits A[27–31] and the device port size to determine which portion of the data bus contains valid data for a write transaction or which portion of the bus should contain valid data for a read transaction.

The MPC8280 uses four double word burst transactions for transferring cache blocks. For these transactions, TSIZ[0–3] are encoded as 0b0010, and address bits A[27–28] determine which double-word is sent first.

The MPC8280 supports critical-word-first burst transactions (double-word-aligned) from the processor. The MPC8280 transfers the critical double word of data first, followed by the double words from increasing addresses, wrapping back to the beginning of the eight-word block as required.

Table 8-4. Transfer Size Signal Encoding Comments TBST

Negated Negated

TSIZ[0–3]

0 0 0 1 0 0 1 0

Transfer Size

1 Byte 2 Bytes Byte Half word

Source

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TBST

Negated Negated Negated Negated Negated Negated Negated Negated Asserted

The 60x Bus TSIZ[0–3]

0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 0

Table 8-4. Transfer Size Signal Encoding (continued) Transfer Size

3 Bytes 4 Bytes 5 Bytes 6 Bytes 7 Bytes 8 Bytes 16 Bytes 24 Bytes 32 bytes

Comments

— Word Extended 5 bytes Extended 6 bytes Extended 7 bytes Double-word (maximum data bus size) Extended double double word Extended triple double word Quad double-word (4 maximum data beats)

Source

Core and DMA Core and DMA SDMA (MPC8280 only) SDMA (MPC8280 only) SDMA (MPC8280 only) Core and DMA SDMA (MPC8280 only) SDMA (MPC8280 only) Core and DMA

NOTE

The basic coherency size of the bus is 32 bytes for the processor (cache-block size). Data transfers that cross an aligned 32-byte boundary must present a new address onto the bus at that boundary for proper snoop operation, or must operate as non-coherent with respect to the MPC8280.

8.4.3.4

Burst Ordering During Data Transfers

During burst transfers, 32 bytes of data (one cache block) are transferred to or from the cache. Burst write transfers are performed zero double-word-first. However, because burst reads are performed critical-double-word-first, a burst-read transfer may not start with the first double word of the cache block and the cache-block-fill operation may wrap around the end of the cache block.

Table 8-5 describes

MPC8280 burst ordering.

Table 8-5. Burst Ordering Double Word Starting Address: Data Transfer

1st data beat 2nd data beat 3rd data beat

A[27–28] = 00 1

DW0 DW1 DW2 2

A[27–28] = 01

DW1 DW2 DW3

A[27–28] = 10

DW2 DW3 DW0

A[27–28] = 11

DW3 DW0 DW1 4th data beat DW3 DW0 DW1 DW2 1 2 A[27–28] specifies the first double word of the 32-byte block being transferred; any subsequent double words must wrap-around the block. A[29–31] are always 0b000 for burst transfers by the MPC8280.

DW x represents the double word that would be addressed by A[27–28] = x if a nonburst transfer were performed.

Each data beat is terminated with an assertion of TA.

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Effect of Alignment on Data Transfers

Table 8-6

lists the aligned transfers that can occur to and from the MPC8280. These are transfers in which

the data is aligned to an address that is an integer multiple of the size of the data. For example, Table 8-6

shows that 1-byte data is always aligned; however, a 4-byte word must reside at an address that is a multiple of 4 to be aligned.

In Figure 8-6 ,

Table 8-6

, and Table 8-7

, OP0 is the most-significant byte of a word operand and OP7 is the least-significant byte.

Table 8-6. Aligned Data Transfers Data Bus Byte Lanes Program Transfer Size TSIZ[0–3] A[29–31] D0...

...D31

D32...

...D63

Byte Half-Word Word 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0

B0

OP0 — — — — — — — OP0 — — — OP0 — 1

B1

— OP1 — — — — — — OP1 — — — — 2 OP1

B2

— — OP2 — — — — — — OP2 — — OP2 —

B3

— — — OP3 — — — — — OP3 — — OP3 —

B4

— — — — OP4 — — — — — OP4 — — OP4

B5

— — — — — OP5 — — — — OP5 — — OP5

B6

— — — — — — OP6 — — — — OP6 — OP6

B7

— — — — — — — OP7 — — — OP7 — OP7 Double-Word 0 0 0 0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 1 2 OP n: These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand and OP7 is the least-significant byte.

—: These lanes are ignored during reads and driven with undefined data during writes.

The MPC8280 supports misaligned memory operations, although they may degrade performance substantially. A misaligned memory address is one that is not aligned to the size of the data being transferred (such as, a word read from an odd byte address). The MPC8280’s processor bus interface supports misaligned transfers within a word (32-bit aligned) boundary, as shown in

Table 8-7 . Note that

the 4-byte transfer in

Table 8-7

is only one example of misalignment. As long as the attempted transfer does not cross a word boundary, the MPC8280 can transfer the data to the misaligned address within a single bus transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus transfers to access data that crosses a word boundary.

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Due to the performance degradation, misaligned memory operations should be avoided. In addition to the double-word straddle boundary condition, the processor’s address translation logic can generate substantial exception overhead when the load/store multiple and load/store string instructions access misaligned data. It is strongly recommended that software attempt to align code and data where possible.

Table 8-7. Unaligned Data Transfer Example (4-Byte Example) Data Bus Byte Lanes Program Size of Word (4 bytes) TSIZ[1–3] A[29–31] D0...

...D31

D32...

...D63

Aligned Misaligned—1st access 2nd access Misaligned—1st access 2nd access Misaligned—1st access 2nd access Aligned Misaligned—1st access 2nd access Misaligned—1st access 2nd access Misaligned—1st access 2nd access 1 2 A: Byte lane used —: Byte lane not used 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0

B1

A A — — — — — — — — — A — A

B0

A 1 — — — — — — — — A — A — A

B3

A A — A — A — — — — — — — —

B2

A A — A — — — — — — — — — A

B5

— — — — A — A A A — — — — —

B4

— 2 — A — A — A A — — — — — —

B7

— — — — — — — A A — A — A —

B6

— — — — — — A A A — A — — —

8.4.3.6

Effect of Port Size on Data Transfers

The MPC8280 can transfer operands through its 64-bit data port. If the transfer is controlled by the internal memory controller, the MPC8280 can support 8-, 16-, 32-, and 64-bit data port sizes as demonstrated in

Figure 8-6 . The bus requires that the portion of the data bus used for a transfer to or from a particular port

size be fixed. A 64-bit port must reside on data bus bits D[0–63], a 32-bit port must reside on bits D[0–31], a 16-bit port must reside on bits D[0–15], and an 8-bit port must reside on bits D[0–7]. The MPC8280 always tries to transfer the maximum amount of data on all bus cycles: for a word operation, it always assumes the port is 64 bits wide when beginning the bus cycle; for burst and extended byte cycles, a 64-bit bus is assumed.

Figure 8-6. shows the device connections on the data bus. Table 8-8 lists the bytes required on the data bus

for read cycles.

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0 OP0 OP1 OP2 OP3 31 OP4 Interface Output Register OP5 OP6 OP7 63 D[0–7] OP0 D[8–15] OP1 D[15–23] OP2 D[24–31] OP3 D[32–39] D[40–47] OP4 OP5 D[48–55] D[56–63] OP6 OP7 64-Bit Port Size OP0 OP4 OP1 OP5 OP2 OP6 OP3 OP7 32-Bit Port Size OP0 OP2 OP4 OP6 OP1 OP3 OP5 OP7 16-Bit Port Size OP0 OP7 8-Bit Port Size

Figure 8-6. Interface to Different Port Size Devices

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The 60x Bus Table 8-8. Data Bus: Read Cycle Requirements and Write Cycle Content Port Size/Data Bus Assignments Transfer Size TSIZ[0–3] Address State 1 A[29–31]

Byte (0001) Half Word (0010) Triple Byte (0011) Word (0100) 000 001 010 011 100 101 110 111 000 001 010 100 101 110 000 001 100 101 000 100 0–7 OP0 2 8–15 16–23 24–31 32–39 40–47 48–55 56–63 — 3 — — — — — — 0–7 OP0 8–15 16–23 24–31 — — — — — — — — — — OP1 — — — — — — OP0 OP1 — — — — — — OP2 — — — — — — OP1 OP2 — — — — OP2 OP3 — — — OP0 OP1 OP2 — — — OP0 OP1 OP2 OP3 — — — — — — — — — OP3 — — — — — — — — — — OP1 OP2 OP3 — — — — — — OP4 — — — — — — — — — — — — — — — — OP5 — — — — — OP4 OP5 — — — — — — — — OP6 — — — — — OP5 OP6 — — — — — — OP7 — — — — — OP6 OP7 — — OP4 OP5 OP6 — — — OP5 OP6 OP7 — — — — — — OP4 — — — OP0 OP1 — — OP1 — — — OP5 — — OP1 OP2 — OP4 OP5 — — OP0 OP1 OP2 — — — OP2 — — — OP6 — — OP2 — OP5 OP6 OP6 OP1 OP2 OP4 OP5 OP6 — OP5 OP6 OP4 OP5 OP6 OP7 OP4 OP5 OP6 — — OP3 — — — OP7 — — OP3 OP2 OP3 OP2 — — OP7 OP6 OP7 OP6 — OP3 — OP7 0–7 OP0 — OP2 — OP4 — OP6 — — — — — 8–15 — — — — 0–7 OP0 OP1 OP1 OP2 OP3 OP3 OP4 OP5 OP5 OP6 OP7 OP7 OP0 OP1 OP0 OP1 OP1 OP4 OP5 OP4 OP5 OP5 OP0 OP1 OP0 OP1 OP1 OP4 OP5 OP4 OP5 OP5 OP0 OP1 OP2 OP3 OP0 OP1 OP0 OP7 OP4 OP5 OP4 Double Word (0000) 000 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP0 OP1 OP0 1 2 3 Address state is the calculated address for port size.

OP n: These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand and OP7 is the least-significant byte.

— These lanes are ignored during read cycles and driven with undefined data during write cycles.

8.4.3.7

60x-Compatible Bus Mode—Size Calculation

To comply with the requirements listed in Table 8-6

and

Table 8-7 , the transfer size and a new address must

be calculated at the termination of each beat of a port-size transaction. In single-MPC8280 bus mode, these calculations are internal and do not constrain the system. In 60x-compatible bus mode, the external slave or master must determine the new address and size.

Table 8-9 describes the address and size calculation

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state machine. Note that the address and size states are for internal use and are not transferred on the address or TSIZ pins. Extended transactions (16- and 24-byte) are not described here but can be determined by extending this table for 9-, 10-, 16-, 23-, and 24-byte transactions.

Table 8-9. Address and Size State Calculations Next Size State Size State

Byte 2-Byte 3-Byte 4-Byte 5-Byte 6-Byte 7-Byte 8-Byte x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x 1 0 0 0 0 1 0 0 x 0 1 1 1 0 0 1 0 1 0 1 0 1 x 0 0 0 1 1 0 x 1 0 0 0 0 0 x x 0 0 0 x 0 0 0 0 0 0 x 0 0 0 0 0 x x 0 0 0 0 0 1 x x 0 0 x x 1 1 0 0 1 1 x x

Address State [0–4]

x x x x x x x x x x x x x x x x x x x x x x x x x x

Port Size

x Byte Half Byte Half Word Byte Half Word Byte Byte Half Byte Byte Half Word Double Byte Byte Byte Byte 2-Byte 2-Byte 2-Byte 2-Byte Byte 2-Byte Byte 2-Byte 3-Byte 2-Byte 4-Byte 5-Byte 4-Byte 6-Byte 7-Byte 6-Byte 4-Byte

Next Address State [0–4]

x Stop x x x x x x x Stop Stop x x x x Stop x x x x Stop x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 x 0 0 1 1 0 0 1 1 x x 1 0 1 0 0 0 1 x 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0

8.4.3.8

Extended Transfer Mode

The MPC8280 supports an extended transfer mode that improves bus performance. This should not be confused with the extended bus protocol used to support direct-store operations supported in some earlier processors that implement the PowerPC architecture. The MPC8280 can generate 5-, 6-, 7-, 16-, or 24-byte 8-18

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extended transfers. These transactions are compatible with the 60x bus, but some slaves or masters do not support these features. Clear BCR[ETM] to disable this type of transaction. This places the MPC8280 in

strict 60x bus mode. The following tables are extensions to Table 8-7 ,

Table 8-8

, and Table 8-9

.

Table 8-10

lists the patterns of the extended data transfer for write cycles when MPC8280 initiates an access. Note that 16- and 24-byte transfers are always eight-byte aligned and use a 64-bit or less port size.

Table 8-10. Data Bus Contents for Extended Write Cycles Transfer Size TSIZ[0–3])

5 Bytes (0101) 6 Bytes (0110) 7 Bytes (0111)

Address State A[29–31]

000 011 000 010 000 001

External Data Bus Pattern D[0–7] D[8–15] D[16–23] D[24–31] D[32–39] D[40–47] D[48–55] D[56–63]

OP0 OP3 OP0 OP2 OP0 OP1 OP1 OP3 OP1 OP3 OP1 OP1 OP2 — OP2 OP2 OP2 OP2 OP3 OP3 OP3 OP3 OP3 OP3 OP4 OP4 OP4 OP4 OP4 OP4 — OP5 OP5 OP5 OP5 OP5 — OP6 — OP6 OP6 OP6 — OP7 — OP7 — OP7

Table 8-11

lists the bytes required on the data bus for extended read cycles. Note that 16- and 24-byte transfers are always 8-byte aligned and use a maximum 64-bit port size.

Table 8-11. Data Bus Requirements for Extended Read Cycles Transfer Size TSIZ[0–3] Addres s State A[29-31 ]

5 Byte (0101) 000 0–7 8–15 16–2 3 OP 0 OP 1 24–3 1 32–3 9 OP2 OP3 OP4

Port Size/Data Bus Assignments

40–4 7 — 48–5 5 — 56–6 3 — 0–7 OP 0 8–15 OP1 16–2 3 24–3 1 0–7 8–15 0–7 OP2 OP3 OP0 OP1 OP0 6 Byte (0110) 011 000 — OP 0 — OP 1 — OP3 OP4 OP5 OP6 OP7 OP2 OP3 OP4 OP5 — — — OP 0 — OP1 — OP3 — OP2 OP3 OP0 OP3 OP3 OP1 OP0 7 Byte (0111) 010 000 001 — OP 0 — — OP 1 OP2 OP3 OP4 OP5 OP6 OP7 OP2 OP3 OP4 OP5 OP6 — OP 1 OP2 OP3 OP4 OP5 OP6 OP7 — OP 0 — — OP1 OP1 OP2 OP3 OP2 OP3 OP2 OP2 OP3 OP0 OP1 OP0 OP2 OP3 — OP1 OP1 Freescale Semiconductor

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Table 8-12

includes added states to the transfer size calculation state machine. Only extended transfers use these states.

Table 8-12. Address and Size State for Extended Transfers Size State [0–3]

Half 3-Byte Word 5-Byte 6-Byte x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 1 x 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 x 0 1 x 0 1 0 0 0 1 0 x 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 x 0 1 x 0 0 1 0 1 x 1 x 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 x 0 0 x 0 0 0 0 0

Address State[0–4]

x x x x x x x x x x x x x x x x x x x x x x x x x x x

Port Size

Byte Half Byte Half Byte Byte Half Word Double Byte Half Word Double

Next Size State [0–3]

Byte Half Byte 3-Byte Word 3-Byte Word Byte Word 5-Byte Word Half Word

Next Address State[0–4]

x x Stop x x x x x x x x x x x x x x x Stop x x x x x x x Stop x x x x x x x x x x x x x x x x x x x x x x x x 1 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 8-20

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7-Byte x x x x x x x

Address State[0–4]

x x x x x x x 0 0 0 0 0 0 x 0 0 0 0 0 0 x 0 1 0 1 0 1 x

Port Size

Byte Half Word Double

Next Size State [0–3]

6-Byte 5-Byte 6-Byte 3-Byte 4-Byte

Next Address State[0–4]

x x Stop x x x x x x x x x x 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 0 0 0 Extended transfer mode is enabled by setting the BCR[ETM].

8.4.4

Address Transfer Termination

Address transfer termination occurs with the assertion of the address acknowledge (AACK) signal, or retried with the assertion of ARTRY. ARTRY must remain asserted until one clock after AACK; the bus clock cycle after AACK is called the ARTRY window. The MPC8280 controls assertion of AACK unless the cycle is claimed by an external slave, such as an external L2 cache controller. Following the assertion of L2_HIT, the L2 cache controller is responsible for asserting AACK. When AACK is asserted by the external slave, it should be asserted for one clock cycle and then negated for one clock cycle before entering a high-impedance state. The MPC8280 holds AACK in a high-impedance state until it is required to assert AACK to terminate the address cycle. The MPC8280 uses AACK to enforce a pipeline depth of one to its internal slaves.

8.4.4.1

Address Retried with ARTRY

The address transfer can be terminated with the requirement to retry if ARTRY is asserted during the address tenure and through the cycle following AACK. The assertion causes the entire transaction (address and data tenure) to be rerun. As a snooping device, the MPC8280 processor asserts ARTRY for a snooped transaction that hits modified data in the data cache that must be written back to memory, or if the snooped transaction could not be serviced. As a bus master, the MPC8280 responds to an assertion of ARTRY by aborting the bus transaction and requesting the bus again, as shown in

Figure 8-7

. Note that after recognizing an assertion of ARTRY and aborting the current transaction, the MPC8280 may not run the same transaction the next time it is granted the bus.

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CLKOUT BR INT BG INT BR BG ABB ADDR + ATTR MPC8280 TS AACK External External MPC8280 ARTRY

Figure 8-7. Retry Cycle

As a bus master, the MPC8280 recognizes either an early or qualified ARTRY and prevents the data tenure associated with the retried address tenure. If the data tenure has begun, the MPC8280 terminates the data tenure immediately even if the burst data has been received. If the assertion of ARTRY is received up to or on the bus cycle as the first (or only) assertion of TA for the data tenure, the MPC8280 ignores the first data beat. If it is a read operation, the MPC8280 does not forward data internally to the cache, execution unit, or any other MPC8280 internal storage. This address retry case succeeds because the data tenure is aborted in time, and the entire transaction is rerun. This retry mechanism allows the memory system to begin operating in parallel with the bus snoopers, provided external devices do not present data sooner than the bus cycle before all snoop responses can be determined and asserted on the bus. Note that the system must ensure that ARTRY is never asserted later than the cycle of the first or only assertion of TA (if the PCI controller can initiate global transactions, the system must ensure that ARTRY is never asserted on the same cycle or later then the first or only assertion of TA). This guarantees the relationship between TA and ARTRY such that, in case of an address retry, the data may be cancelled in the chip before it can be forwarded internally to the internal memory resources (registers or cache). Generally, the memory system must also detect this event and abort any transfer in progress. If this 8-22

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TA/ARTRY relationship is not met, the master may enter an undefined state. Users may use PPC_ACR[DBGD] to ensure correct operation of the system.

During the clock of a qualified ARTRY, each device master determines whether it should negate BR and ignore BG on the following cycle. The following cycle is referred to as the window-of-opportunity for the snooping master. During this window, only the snooping master that asserted ARTRY and requires a snoop copyback operation is allowed to assert BR. This guarantees the snooping master a window of opportunity to request and be granted the bus before the just-retried master can restart its transaction. BG is also blocked in the window-of-opportunity, so the arbiter has a chance to negate BG to an already granted potential bus master to perform a new arbitration.

Note that in some systems, an external processor may be unable to perform a pending snoop copyback when a new snoop operation is performed. In this case, the MPC8280 requests the window of opportunity if it hits on the new snooped address. To clear its internal snoop queue, it performs the snoop copyback operation for the earlier snooped address instead of the current snooped address.

8.4.4.2

Address Tenure Timing Configuration

During address tenures initiated by 60x-bus devices, the timing of the assertion of AACK by the MPC8280 is determined by the BCR[APD] and the pipeline status of the 60x bus. Because the MPC8280 can support one level of pipelining, it uses AACK to control the 60x-bus pipeline condition. To maintain the one-level pipeline, AACK is not asserted for a pipelined address tenure until the current data tenure ends. The MPC8280 also delays asserting AACK until no more address retry conditions can occur. Note that the earliest the MPC8280 can assert AACK is the clock cycle when the wait-state values set by BCR[APD] have expired.

BCR[APD] specifies the minimum number of address tenure wait states for address operations initiated by 60x-bus devices. APD indicates how many cycles the MPC8280 should wait for ARTRY, but because it is assumed that ARTRY can be asserted (by other masters) only on cacheable address spaces, APD is considered only on transactions that hit a 60x-assigned memory controller bank and that have GBL asserted during the address phase.

Extra wait states may occur because of other MPC8280 configuration parameters. Note that in a system with an L2 cache, the number of wait states configured by BCR[APD] should be at least as large as the value needed by the L2 controller to assert hit response. In systems with multiple potential masters, the number of wait states configured by BCR[APD] should be at least as large as the value the slowest master would need by to assert a snoop response. For example, additional wait states are required when the internal processor is in 1:1 clock mode; this case requires at least one wait state to generate the ARTRY response.

8.4.5

Pipeline Control

The MPC8280 supports the two following modes: • One-level pipeline mode—To maintain the one-level pipeline, AACK is not asserted for a pipelined address tenure until the current data tenure ends. In 60x-compatible bus mode, a two-level pipeline depth can occur (for example, when an external 60x-bus slave does not support Freescale Semiconductor

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The 60x Bus

• one-level pipelining). When the internal arbiter counts a pipeline depth of two (two assertions of AACK before the assertion of the current data tenure) it negates all address bus grant (BG) signals.

No-pipeline mode—The MPC8280 does not assert AACK until the corresponding data tenure ends.

8.5

Data Tenure Operations

This section describes the operation of the MPC8280 during the data bus arbitration, transfer, and termination phases of the data tenure.

NOTE: External Master Writes to DPRAM

DPRAM is clocked by the CPM clock and not by the 60x bus clock. Therefore, data is not latched at the TA assertion cycle during writes to DPRAM from the external master. Instead, the data is latched earlier. It is necessary, then, that the external master drive the data bus immediately after DBG and hold the data bus until after TA.

8.5.1

Data Bus Arbitration

The beginning of an address transfer, marked by the assertion of transfer start (TS), is also an implicit data bus request provided that the transfer type signals (TT[0–4]) indicate that the transaction is not address-only.

The MPC8280 arbiter supports one external master and uses DBG to grant the external master data bus.The DBG signals are not asserted if the data bus, which is shared with memory, is busy with a transaction.

A qualified data bus grant (QDBG) can be expressed as the assertion of DBG while DBB and ARTRY (associated with the data bus operation) are negated.

Note that the MPC8280 arbiter should assert DBG only when it is certain that the first TA will be asserted with or after the associated ARTRY. The MPC8280 DBG is asserted with TS if the data bus is free and if the PPC_ACR[DBGD] = 0. If PPC_ACR[DBGD] = 1, DBG is asserted one cycle after TS if the data bus is not busy. The DBG delay should be used to ensure that ARTRY is not asserted after the first or only TA assertion. For the programming model, see

Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR).”

Note that DBB should not be asserted after the data tenure is finished. Assertion of DBB after the last TA causes improper operation of the bus. (MPC8280 internal masters do not assert DBB after the last TA.) Note the following: • External bus arbiters must comply with the following restriction on assertion of DBG which is connected to the MPC8280. In case the data bus is not busy with the data of a previous transaction on the bus, external arbiter must assert DBG in the same cycle in which TS is asserted (by a master which was granted the bus) or in the following cycle. In case the external arbiter asserts DBG on the cycle in which TS was asserted, PPC_ACR[DBGD] should be zero. Otherwise, PPC_ACR[DBGD] should be set.

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• External masters connected to the 60x bus must assert DBB only for the duration of its data tenure. External masters should not use DBB to prevent other masters from using the data bus after their data tenure has ended.

8.5.2

Data Streaming Mode

The MPC8280 supports a special data streaming mode that can improve bus performance in some conditions. Generally, the bus protocol requires one idle cycle between any two data tenures. This idle cycle is essential to prevent contention on the data bus when the driver of the data is changing. However, when the driver on the data bus is the same for both data tenures, this idle cycle may be omitted. In data streaming mode, the MPC8280 omits the idle cycle where possible. MPC8280 applications often require data stream transfers of more than 4 x 64 bits. For example, the ATM cell’s payload is 6 x 64 bits. All this data is driven from a single device on the bus, so data-streaming saves a cycle for such a transfer. When data-streaming mode is enabled, transactions initiated by the core are not affected, while transactions initiated by other bus masters within the chip omit the idle cycle if the data driver is the same. Note that data streaming mode cannot be enabled when the MPC8280 is in 60x-compatible bus mode and a device that uses DBB is connected to the bus. This restriction is due to the fact that a MPC8280 for which data streaming mode is enabled may leave DBB asserted after the last TA of a transaction and this is a violation of the strict bus protocol. The data streaming mode is enabled by setting BCR[ETM].

8.5.3

Data Bus Transfers and Normal Termination

The data transfer signals include D[0–63] and DP[0–7]. For memory accesses, the data signals form a 64-bit data path, D[0–63], for read and write operations.

The MPC8280 handles data transfers in either single-beat or burst operations. Single-beat operations can transfer from 1 to 24 bytes of data at a time. Burst operations always transfer eight words in four double-word beats. A burst transaction is indicated by the assertion of TBST by the bus master. A transaction is terminated normally by asserting TA.

The three following signals are used to terminate the individual data beats of the data tenure and the data tenure itself: • • • TA indicates normal termination of data transactions. It must always be asserted on the bus cycle coincident with the data that it is qualifying. It may be withheld by the slave for any number of clocks until valid data is ready to be supplied or accepted.

Asserting TEA indicates a nonrecoverable bus error event. Upon receiving a final (or only) termination condition, the MPC8280 always negates DBB for one cycle, except when fast data bus grant is performed.

Asserting ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the address tenure associated with the data tenure in operation (the data tenure may not be terminated due to address pipelining). The earliest allowable assertion of TA depends directly on the latest possible assertion of ARTRY.

Figure 8-8 shows both a single-beat and burst data transfer. The MPC8280 asserts TA to mark the cycle in

which data is accepted. In a normal burst transfer, the fourth assertion of TA signals the end of a transfer. Freescale Semiconductor

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The 60x Bus

CLKOUT ADDR + ATTR TS AACK DBG TA PSDVAL D[0–63] D0 D1 D2

Figure 8-8. Single-Beat and Burst Data Transfers

D3

8.5.4

Effect of ARTRY Assertion on Data Transfer and Arbitration

The MPC8280 allows an address tenure to overlap its associated data tenure. The MPC8280 internally guarantees that the first TA of the data tenure is delayed to be at the same time or after the ARTRY window (the clock after the assertion of AACK).

8.5.5

Port Size Data Bus Transfers and PSDVAL Termination

The MPC8280 can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in

Section 8.4.3, “Address Transfer Attribute Signals.”

Single-beat transaction sizes can be 8, 16, 32, 64, 128, and 192 bits; burst transactions are 256 bits. Single-beat and burst transactions are divided into to a number of intermediate beats depending on the port size. The MPC8280 asserts PSDVAL to mark the cycle in which data is accepted. Assertion of PSDVAL in conjunction with TA marks the end of the transfer in single-beat mode.

The fourth assertion of PSDVAL in conjunction with TA signals the end of a burst transfer. Figure 8-9

shows an extended transaction of 4 words to a port size of 32 bits. The single-beat transaction is translated to four port-sized beats.

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CLKOUT ADDR + ATTR TS AACK DBG PSDVAL TA D[0–31] D0 D1 D2 D3

Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size The 60x Bus

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The 60x Bus

Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided into two

port-sized beats such that the four double words are transferred in eight beats.

CLKOUT ADDR + ATTR TS AACK DBG PSDVAL TA D[0–31] D0 D1 D2 D3 D4 D5

Figure 8-10. Burst Transfer to 32-Bit Port Size

D6 D7

8.5.6

Data Bus Termination by Assertion of TEA

If a device initiates a transaction that is not supported by the MPC8280, the MPC8280 signals an error by asserting TEA. Because the assertion of TEA is sampled by the device only during the data tenure of the bus transaction, the MPC8280 ensures that the device master receives a qualified data bus grant by asserting DBG before asserting TEA. The data tenure is terminated by a single assertion of TEA regardless of the port size or whether the data tenure is a single-beat or burst transaction. This sequence is shown in

Figure 8-11.. In Figure 8-11. the data bus is busy at the beginning of the transaction, thus delaying the

assertion of DBG. Note that data errors (parity and ECC) are reported not by assertion of TEA but by assertion of MCP.

Because the assertion of TEA is sampled by the device only during the data tenure of the bus transaction, the MPC8280 ensures that the device receives a qualified data bus grant by asserting DBG before asserting TEA. The data tenure is terminated by a single assertion of TEA regardless of the port size or whether the data tenure is a single-beat or burst transaction. 8-28

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This sequence is shown in Figure 8-11

. In

Figure 8-11 the data bus is busy at the beginning of the

transaction, thus delaying the assertion of DBG.

CLKOUT For Burst ADDR + ATTR For Single TS AACK DBG TA TEA Data

Figure 8-11. Data Tenure Terminated by Assertion of TEA

The MPC8280 interprets the following bus transactions as bus errors: • • Direct-store transactions, as indicated by the assertion of XATS.

Bus errors asserted by slaves (internal or external).

8.6

Memory Coherency—MEI Protocol

The MPC8280 provides dedicated hardware to ensure memory coherency by snooping bus transactions, by maintaining information about the status of data in a cache block, and by the address retry capability. Each data cache block includes status bits that support the modified/exclusive/invalid, or MEI, cache-coherency protocol.

Asserting the global (GBL) output signal indicates whether the current transaction must be snooped by other snooping devices on the bus. Address bus masters assert GBL to indicate that the current transaction is a global access (that is, an access to memory shared by more than one device). If GBL is not asserted for the transaction, that transaction is not snooped. When other devices detect the GBL input asserted, they must respond by snooping any addresses broadcast. Normally, GBL reflects the M bit value specified for the memory reference in the corresponding translation descriptor. Care must be taken to minimize the number of pages marked as global, because the retry protocol discussed in the previous section used to enforce coherency can require significant bus bandwidth.

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When the MPC8280 processor is not the address bus master, GBL is an input. The MPC8280 processor snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualified snooping condition). No snoop update to the MPC8280 processor cache occurs if the transaction is not marked global. This includes invalidation cycles.

When the MPC8280 processor detects a qualified snoop condition, the address associated with the TS is compared against the data cache tags. Snooping completes if no hit is detected. However, if the address

hits in the cache, the MPC8280 processor reacts according to the MEI protocol shown in Figure 8-12

. This figure assumes that WIM = 0b001 (memory space is marked for write-back, caching-allowed, and coherency-enforced modes).

Invalid SH/CRW SH/CRW WM RM WH Modified Exclusive SH RH RH WH SH/CIR SH = Snoop hit RH = Read hit WH = Write hit WM = Write miss RM = Read miss SH/CRW = Snoop hit, cacheable read/write SH/CIR = Snoop hit, cache-inhibited read = Snoop push = Cache line fill

Figure 8-12. MEI Cache Coherency Protocol—State Diagram (WIM = 001)

8.7

Processor State Signals

This section describes the MPC8280’s support for atomic update and memory through the use of the lwarx/stwcx. instruction pair. It also describes the TLBISYNC input.

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8.7.1

Support for the lwarx/stwcx. Instruction Pair

The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.) instructions provide a way to update memory atomically by setting a reservation on the load and checking that the reservation is still valid before the store is performed. In the MPC8280, reservations are made on behalf of aligned, 32-byte sections of the memory address space.

The reservation (RSRV) output signal is driven synchronously with the bus clock and reflects the status of the reservation coherency bit in the reservation address register. Note that each external master must do its own snooping; the MPC8280 does not provide external reservation snooping.

8.7.2

TLBISYNC Input

The TLBISYNC input permits hardware synchronization of changes to MMU tables when the MPC8280 and another DMA master share the MMU translation tables in system memory. A DMA master asserts TLBISYNC when it uses shared addresses that the MPC8280 could change in the MMU tables during the DMA master’s tenure.

When the TLBISYNC input is asserted, the MPC8280 cannot complete any instructions past a tlbsync instruction. Generally, during the execution of an eciwx or ecowx instruction, the selected DMA device should assert the MPC8280’s TLBISYNC signal and hold it asserted during its DMA tenure if it is using a shared translation address. Subsequent instructions by the MPC8280 processor should include a sync and tlbsync instruction before any MMU table changes are performed. This prevents the MPC8280 from making disruptive table changes during the DMA tenure.

8.8

Little-Endian Mode

The MPC8280 supports a little-endian mode in which low-order address bits are operated on (munged) based on the size of the requested data transfer. This mode allows a little-endian program running on the processor with a big-endian memory system to offset into a data structure and receive the same results as it would if it were operating on a true little-endian processor and memory system. For example, writing a word to memory as a word operation on the bus and then reading in the second byte of that word as a byte operation on the bus.

NOTE

When the processor is selected for little-endian operation, the bus interface is still operating in big-endian mode. That is, byte address 0 of a double word (as selected by A[29–31] on the bus—after the internal address munge) still selects the most significant (left most) byte of the double word on D[0–7]. If the processor interfaces with a true little-endian environment, the system may need to perform byte-lane swapping or other operations external to the processor.

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The 60x Bus

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Chapter 9 PCI Bridge

The PCI bridge enables the MPC8280 to bridge PCI devices gluelessly to a processor that implements the PowerPC architecture, to serve as a PCI interface for CompactPCI™ (CPCI) systems or as a basis for passive PCI NIC implementations. In addition, multiple MPC8280 processors can interface with each other over the PCI bus.

The key features of the PCI bridge are as follows: • • • • • • • • • • • PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz On-chip arbitration Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming PCI host bridge or peripheral capabilities Includes 4 DMA channels for the following transfers: — PCI-to-60x to 60x-to-PCI — 60x-to-PCI to PCI-to-60x — PCI-to-60x to PCI-to-60x — 60x-to-PCI to 60x-to-PCI Includes all of the configuration registers required by the PCI standard as well as message and doorbell registers Supports the I 2 O standard Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) Support for 66 MHz, 3.3 V specification Uses a buffer pool for the 60x-PCI bus interface Makes use of the local bus signals to avoid the need for additional pins Freescale Semiconductor

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PCI Bridge

MPC8280 G2_LE Core 60x Bus SDMA Communications Processor Module DPRAM PCI Bridge 60x-to-Local Bridge 0 Mux 1 PCI_MODE

Figure 9-1. PCI Bridge in the MPC8280

MPC8280 60x Bus/Local SDMA MPC8280 Internal PCI Bridge I/O Sequencer 60x Interface Buffer Pool PCI Bus 9-2 Embedded Utilities DMA I 2 O Regs PCI Interface PCI Bus

Figure 9-2. PCI Bridge Structure MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

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PCI Bridge

9.1

Signals

To avoid the need for additional pins, the PCI bridge is designed to make use of the local bus signals. Therefore, many of these pins perform different functions, depending on how the user configures them. PCI bridge signals are described in

Chapter 6, “External Signals.”

9.2

Clocking

PCI bridge clocking is described in Chapter 10, “Clocks and Power Control.”

9.3

PCI Bridge Initialization

The PCI bridge uses fields from the hard reset configuration word (refer to Section 5.4.1, “Hard Reset Configuration Word”

) which are loaded during a hard reset (that is, assertion of the HRESET signal). This section discusses PCI bridge initialization issues after reset.

The local bus pin configuration (LBPC) field of the hard reset configuration word should be programmed to 0b01 so that the local bus operates as the PCI bus. For PCI agent applications, the PCI_RST signal should be connected to the power-on reset (PORESET) pin of the MPC8280. If the core is disabled, in PCI agent mode, an EEPROM must be provided for loading the PCI configuration data.

For core-disabled, PCI agent applications, the communications processor (CP) can perform the minimal initialization of the internal PCI bridge configuration registers required before responding to configuration cycles. When the auto-load enable (ALD_EN) bit is set in the hard reset configuration word, the CP automatically loads the PCI configuration data from the EPROM immediately following hard reset. (In addition to the hard reset configuration word, the PCI configuration register data should be programmed

within the EPROM according to the port size. Refer to configuration register loading in Section 9.11.2.28, “Initializing the PCI Configuration Registers,”

for further details.) To prevent premature accesses, CFG_LOCK (see

Section 9.11.2.22, “PCI Bus Function Register”

) is automatically set during hard reset so that all attempted PCI accesses are retried. The user must re-enable PCI accesses by clearing CFG_LOCK at the end of the PCI bridge initialization procedure.

In addition to the configuration register programming, several configuration pins are available in PCI mode only. See

Table 6-1 for a description of the external signals.

9.4

SDMA Interface

As shown in Figure 9-1 , the PCI bridge has an interface to the SDMA controller. The CP can direct the

SDMA controller to bring data from the PCI bus memory/IO space into the dual-port RAM, or vice versa. The user can choose if the data buffers, buffer descriptors, or any other needed data will reside on the 60x bus or on the PCI bus. Because the PCI is replacing the local bus interface when PCI_MODE is active, the PCI path is automatically chosen whenever the choice between 60x and local bus was programmed to local. When the PCI bridge is disabled (PCI_MODE is negated), the SDMA transfers data to local memory through the local bus interface whenever the choice is programmed to local. No change occurs when the programmed option is the 60x bus. Refer to the descriptions of DTB and BIB in

Table 31-16 .

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PCI Bridge NOTE

Although the user can direct the SDMA to the 60x bus, transactions can be redirected to the PCI bridge if they fall in one of the PCI windows of the 60x bus memory map (PCIBR0 or PCIBR1; refer to

Section 4.3.4.1, “PCI Base Register (PCIBRx)”

). Data flow of this kind is not recommended because it is not optimal. However, if it is implemented, the user must set strict 60x bus mode (BCR[ETM] = 0).

9.5

Interrupts from PCI Bridge

Each of the PCI bridge interrupt sources—the PCI error condition detector, the DMA unit, and the message unit—can generate an interrupt to the SIU interrupt controller. PCI bridge interrupts are reflected in

SIPNR_H[PCI] (refer to Section 4.3.1.4, “SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)”

). PCI bridge interrupts can be masked in general with SIMR_H[PCI] (refer to

Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L)”

). Specific interrupt sources can be masked independently by masking the relevant bits in the following registers—error mask register, DMA mode register, inbound message interrupt mask register, and the outbound message interrupt mask register. Each

of these registers is described in Section 9.11.1, “Memory-Mapped Configuration Registers.”

The interrupt service routine can determine the source of the interrupt by reading the status bits of the following registers—the error status register, the DMA general status register, the inbound message interrupt status register, and the outbound message interrupt status register.

For PCI interrupt vector calculation, refer to

Section 4.2.4, “Interrupt Vector Generation and Calculation.”

For the priority of PCI interrupts, refer to Section 4.3.1.2, “SIU Interrupt Priority Register (SIPRR).”

9.6

60x Bus Arbitration Priority

To prevent 60x bus arbitration deadlock, the PCI bridge should be programmed to have a high arbitration priority level within the 60x bus. The 60x bus arbitration-level register (PPC_ALRH) should be programmed so that the PCI request level index (0b0011) has a priority higher than all other 60x bus masters which address the PCI space through the 60x-PCI bridge (that is, the internal core or any external masters). Masters which do not perform transactions in the PCI space (through the 60x-PCI bridge) can have higher priority. Note that the default value of ALRH (0x0126_7893l) does not meet this requirement.

The same guidelines to prevent 60x bus arbitration deadlock apply to the programming of the parked master. That is, program the parked master in the 60x bus arbiter configuration register

(PPC_ACR[PRKM]) to be the PCI bridge (0b0011); refer to Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR).”

9.7

60x Bus Masters

The number of external 60x bus masters allowed access to the PCI bridge is limited by the number of pending requests that the PCI bridge is able to service. This number depends on the processor type of the master. For example, up to two second generation (G2) processors that implement the PowerPC architecture or three third generation (G3) processors can be accommodated.

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9.8

CompactPCI Hot Swap Specification Support

CompactPCI is an open specification supported by the PCI Industrial Computer Manufacturers Group (PICMG) and is intended for embedded applications using PCI. CompactPCI Hot Swap is an extension of the CompactPCI specification and allows the insertion and extraction (or “hot swapping”) of boards without adversely affecting system operation.

The Hot Swap specification defines three levels of support: • • • Hot Swap capable Hot Swap friendly Hot Swap ready The MPC8280 is a Hot Swap friendly device, meaning that it supports the hardware and software connection processes as defined in the Hot Swap specification. This level of support allows the board and system designers to build full Hot Swap and high availability systems based on the MPC8280 device as a PCI target device. The only compliance exception is that the device pins are not 5-volt tolerant. Application boards should be used in 3.3V signaling back planes, or add 5-to-3.3 volt signaling voltage converters, if needed, to be used in 5V back planes.

For more information regarding the Hot Swap process, refer to the Hot Swap Specification PICMG 2.1, R1.0, August 3, 1998.

9.9

PCI Interface

The PCI bridge connects the processor and memory system to the I/O components via the PCI system bus. This interface acts as both initiator (master) and target (slave) device. The PCI bridge uses a 32-bit multiplexed, address/data bus that can run at frequencies up to 66 MHz. The interface provides address and data parity with error checking and reporting. The interface provides for three physical address spaces—32-bit address memory, 32-bit address I/O, and PCI configuration space.

The PCI bridge can function as either a host bridge or an agent device. Note that the PCI bridge can be configured from the PCI bus while in agent mode. An address translation mechanism is provided to map PCI memory windows between the host and agent.

The following are the major features supported by the PCI interface: • • • • • • • • • PCI Specification Revision 2.2 compliant On-chip arbitration supports 3 external PCI bus masters (in addition to the PCI bridge itself) Arbiter supports high-priority request and grant signal pairs Supports accesses to all PCI address spaces Supports PCI-to-60x-memory and 60x-memory-to-PCI streaming Memory prefetching of PCI read accesses and support for delayed read transactions Supports posting of processor to PCI and PCI to memory writes Supports selectable snoop PCI host bridge capabilities Freescale Semiconductor

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• • PCI agent mode capabilities which include the ability to configure from a remote host Address translation units for address mapping between host and agent.

Efforts were made to keep the terminology in this chapter consistent with the PCI Specification, revision 2.2, and other PCI documentation; therefore, the terms found in

Table 9-1

may differ from most documentation for processors that implement the PowerPC architecture (for example, architecture specification or reference manuals).

Table 9-1. PCI Terminology Term

LSB/Lower order MSB/High order Byte Word Double word Quad word Beat Burst Edge/Clock edge Cycle/Clock cycle Asserted/negated Address phase Data phase(s)

Definition

Represents bit 0 or the bits closest to the LSB Represents bit 31 or the bits closest to the MSB Represents 8 bits of information Represents 16 bits or 2 bytes Represents 32 bits or 2 words or 4 bytes Represents 64 bits or 2 double-words or 4 words or 8 bytes Represents any valid data during a data transfer Represents any 1 or more beat transfers Represents the rising edge of the PCI clock Represents the time period between clock edges Represents the globally visible

state

of the signal on the clock edge Represents the first clock cycle where FRAME is asserted Represents the clock cycle(s) where IRDY and TRDY are asserted

NOTE: PCI Bridge Signal Naming

PCI bridge signals are defined in most cases with the prefix “PCI_” (for

example, PCI_IRDY—see Figure 6-1

). In this chapter, however, the prefix

is not used. For descriptions of PCI bridge signals, refer to Chapter 6, “External Signals.”

9.9.1

PCI Interface Operation

The following sections discuss the operation of the PCI bus.

9.9.1.1

Bus Commands

PCI bus commands indicate the type of transaction occurring on the bus. These commands are encoded on

PCI_C/BE[3-0] during the address phase of the transaction. PCI bus commands are described in Table 9-2 .

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PCI Bridge Table 9-2. PCI Command Definitions PCI_C/BE[3-0]

0b0000 0b0001 0b0010 0b0011 0b010x 0b0110 0b0111 0b100x 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111

Supported as: Command Type Definition

Interrupt acknowledge Special cycle I/O read I/O write — Memory read Memory write — Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write and invalidate

Initiator Target

YES NO YES YES YES — YES YES — YES YES YES NO YES NO NO NO NO — YES YES — YES YES YES NO YES YES A read implicitly addressed to the system interrupt controller. The size of the vector to be returned is indicated on the byte enables after the address phase.

Provides a simple message broadcast mechanism. See

Section 9.9.1.4.6, “Special Cycle Command .”

Accesses agents mapped in I/O address space.

Accesses agents mapped in I/O address space. Reserved. No response occurs.

Accesses agents mapped in memory address space. A read from prefetchable space, when seen as a target, fetches a cache line of data (32 bytes) from the starting address, even though all 32 bytes may not actually be sent to the initiator.

Accesses agents mapped in memory address space.

Reserved. No response occurs.

Accesses the configuration space of each agent. An agent is selected when its IDSEL signal is asserted. See

Section 9.9.1.4.4, “Host Mode Configuration Access ” for

more detail of configuration accesses. As a target, a configuration read is only accepted if the PCI bridge is configured to be in agent mode.

Accesses the configuration space of each agent. An agent is selected when its IDSEL signal is asserted. See

Section 9.9.1.4.4, “Host Mode Configuration Access ”. As

a target, a configuration write is only accepted if the PCI bridge is configured to be in agent mode.

Causes a prefetch of the next cache line.

Transfers an 8 byte address to devices.

Indicates that the initiator intends to transfer an entire cache line of data.

Indicates that the initiator will transfer an entire cache line of data, and if PCI has any cacheable memory, this line needs to be invalidated.

9.9.1.2

PCI Protocol Fundamentals

The bus transfer mechanism on the PCI bus is called a burst. A burst is comprised of an address phase and one or more data phases. All signals are sampled on the rising edge of the PCI clock. Each signal has a setup and hold window with respect to the rising clock edge, in which transitions are not allowed. Outside this aperture, signal values or transitions have no significance.

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PCI Bridge 9.9.1.2.1

Basic Transfer Control

PCI data transfers are controlled with three fundamental signals: • • • FRAME is driven by an initiator to indicate the beginning and end of a transaction.

IRDY (initiator ready) is driven by an initiator, allowing it to force wait cycles.

TRDY (target ready) is driven by a target, allowing it to force wait cycles.

The bus is idle when both FRAME and IRDY are negated. The first clock cycle in which FRAME is asserted indicates the beginning of the address phase. The address and the bus command code are transferred in that cycle. The next cycle ends the address phase and begins the data phase. During the data phase, data is transferred in each cycle that both IRDY and TRDY are asserted. Once the PCI bridge, as an initiator, has asserted IRDY it does not change IRDY or FRAME until the current data phase completes, regardless of the state of TRDY. Once the PCI bridge, as a target, has asserted TRDY or STOP it does not change DEVSEL, TRDY, or STOP until the current data phase completes.

When the PCI bridge (as a master) intends to complete only one more data transfer, FRAME is negated and IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target indicates it is ready (TRDY asserted) the bus returns to the idle state.

9.9.1.2.2

Addressing

The PCI specification defines three physical address spaces—memory, I/O, and configuration. The memory and I/O address spaces are standard for all systems. The configuration address space has been defined specifically to support PCI hardware configuration. Each PCI device decodes the address for each PCI transaction with each agent responsible for its own address decode.

The information contained in the two lower address bits (AD1 and AD0) depends on the address space. In the I/O address space, all 32 address/data lines provide the full byte address. AD[1-0] are used for the generation of DEVSEL and indicate the least significant valid byte involved in the transfer. Once a target has claimed an I/O access, it first determines if it can complete the entire access as indicated by the byte enable signals. If all the selected bytes are not in the address range, the entire access should not be completed; that is, the target should not transfer any data and should terminate the transaction with a target-abort” (refer to

Section 9.9.1.3, “Bus Transactions”

).

In the configuration address space, accesses are decoded to a double-word address using AD[7-2]. An agent determines if it is the target of the access when a configuration command is decoded, IDSEL is asserted, and AD[1-0] are 0b00; otherwise, the agent ignores the current transaction. The PCI bridge determines a configuration access is for a device on the PCI bus by decoding a configuration command. When in agent mode, the PCI bridge responds to host-generated PCI configuration cycles when its IDSEL is asserted during a configuration cycle. For memory accesses, the double-word address is decoded using AD[31–2]; thereafter, the address is incremented internally by one double-word (4 bytes) until the end of the burst transfer. Another initiator in a memory access should drive 0b00 on AD[1-0] during the address phase to indicate a linear incrementing burst order. The PCI bridge checks AD[1-0] during a memory command access and provides the linear incrementing burst order. On reads, if AD[1-0] is 0b10, which represents a cache line wrap, the PCI bridge linearly increments the burst order starting at the critical word, wraps at the end of the cache 9-8

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PCI Bridge

line, and disconnects after reading one cache line. If AD[1-0] is 0bx1 (a reserved encoding) and the PCI_C/BE[3-0] signals indicate a memory transaction, it executes a target disconnect after the first data phase is completed. Note that AD[1-0] are included in parity calculations.

9.9.1.2.3

Byte Enable Signals

The byte enable signals (BE[3-0]) indicate which byte lanes carry valid data. The byte enable signals may enable different bytes for each of the data phases. The byte enable signals are valid on the edge of the clock that starts each data phase and remain valid for the entire data phase.

If the PCI bridge, as a target, sees no byte enable signals asserted, it completes the current data phase with no permanent change. This implies that on a read transaction, the PCI bridge expects the data not to be changed, and on a write transaction, the data is not stored.

9.9.1.2.4

Bus Driving and Turnaround

The turnaround-cycle is one clock cycle and is required to avoid contention. This cycle occurs at different times for different signals. IRDY, TRDY, and DEVSEL use the address phase as their turnaround-cycle. FRAME, PCI_C/BE[3-0], and AD[31-0] use the idle cycle between transactions as their turnaround-cycle. (An idle cycle in PCI is when both FRAME and IRDY are negated.) Byte lanes not involved in the current data transfer are driven to a stable condition even though the data is not valid.

9.9.1.3

Bus Transactions

The timing diagrams in this section show the relationship of significant signals involved in bus transactions. Note the following conventions: • • • • • • When a signal is drawn as a solid line, it is actively being driven by the current initiator or target. When a signal is drawn as a dashed line, no agent is actively driving it. Three-stated signals with slashes between the two rails have indeterminate values. The terms ‘edge’ and ‘clock edge’ refer to the rising edge of the clock. The terms ‘asserted’ and ‘negated’ refer to the globally visible state of the signal on the clock edge, and not to signal transitions. The symbol represents a turnaround-cycle.

9.9.1.3.1

Read and Write Transactions

Both read and write transactions begin with an address phase followed by a data phase. The address phase occurs when FRAME is asserted for the first time, and the AD[31-0] signals contain a byte address and the PCI_C/BE[3-0] signals contain a bus command. The data phase consists of the actual data transfer and possible wait cycles; the byte enable signals remain actively driven from the first clock of the data phase through the end of the transaction.

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PCI Bridge

A read transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals

indicate a read command. Figure 9-3 shows an example of a single beat read transaction.

PCI_CLK AD[31:0] PCI_C/BE[3:0] FRAME ADDR CMD BYTE ENABLES DATA IRDY DEVSEL TRDY

Figure 9-3. Single Beat Read Example

Figure 9-4 shows an example of a burst read transaction.

PCI_CLK AD[31:0] PCI_C/BE[3:0] FRAME ADDR CMD DATA1 BYTE ENABLES 1 DATA2 BYTE ENABLES 2 IRDY DEVSEL TRDY

Figure 9-4. Burst Read Example

During the turnaround-cycle following the address phase, the PCI_C/BE[3-0] signals indicate which byte lanes are involved in the data phase. The turnaround-cycle must be enforced by the target with the TRDY signal if using fast DEVSEL assertion. The earliest the target can provide valid data is one cycle after the turnaround-cycle. The target must drive the AD[31-0] signals when DEVSEL is asserted.

The data phase completes when data is transferred, which occurs when both IRDY and TRDY are asserted on the same clock edge. When either is negated a wait cycle is inserted and no data is transferred. To indicate the last data phase IRDY must be asserted when FRAME is negated.

A write transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals

indicate a write command. Figure 9-5 shows an example of a single beat write transaction.

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PCI Bridge

PCI_CLK AD[31:0] PCI_C/BE[3:0] FRAME ADDR CMD DATA BYTE ENABLES IRDY DEVSEL TRDY

Figure 9-5. Single Beat Write Example

Figure 9-6 shows an example of a burst write transaction.

PCI_CLK AD[31:0] PCI_C/BE[3:0] FRAME ADDR DATA1 CMD BEs 1 DATA2 BEs 2 DATA3 DATA4 BEs 3 BEs 4 IRDY DEVSEL TRDY

Figure 9-6. Burst Write Example

A write transaction is similar to a read transaction except no turnaround cycle is needed following the address phase because the initiator provides both address and data. Data phases are the same for both read and write transactions.

9.9.1.3.2

Transaction Termination

The termination of a PCI transaction is orderly and systematic, regardless of the cause of the termination. All transactions end when FRAME and IRDY are both negated, indicating the idle cycle.

The PCI bridge as an initiator terminates a transaction when FRAME is negated and IRDY is asserted. This indicates that the final data phase is in progress. The final data transfer occurs when both TRDY and IRDY are asserted. A master-abort is an abnormal case of an initiated termination. If the PCI bridge detects that DEVSEL has remained negated for more than four clocks after the assertion of FRAME, it negates FRAME and then, on the next clock, negates IRDY. On aborted reads, the PCI bridge returns 0xFFFF_FFFF. The data is lost on aborted writes.

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PCI Bridge

When the PCI bridge as a target needs to suspend a transaction, it asserts STOP. Once asserted, STOP remains asserted until FRAME is negated. Depending on the circumstances, data may or may not be transferred during the request for termination. If TRDY and IRDY are asserted during the assertion of STOP, data is transferred. This type of target-initiated termination is called a ‘disconnect B,’ shown in

Figure 9-7 . If TRDY is asserted when STOP is asserted but IRDY is not, TRDY must remain asserted until

IRDY is asserted and the data is transferred. This is called a “disconnect A” target-initiated termination,

also shown in Figure 9-7 . However, if TRDY is negated when STOP is asserted, no more data is

transferred, and the initiator therefore does not have to wait for a final data transfer (see the ‘retry’ diagram

in Figure 9-7 ).

PCI_CLK FRAME IRDY DEVSEL TRDY STOP PCI_CLK FRAME IRDY DEVSEL Disconnect A Disconnect B PCI_CLK FRAME IRDY DEVSEL Retry TRDY TRDY STOP STOP Latency disconnect

Figure 9-7. Target-Initiated Terminations

Target abort Note that when an initiator is terminated by STOP, it must negate its REQx signal for a minimum of two PCI clocks (of which one clock is needed for the bus to return to the idle state). If the initiator intends to complete the transaction, it should reassert its REQx immediately following the two clocks or potential starvation may occur. If the initiator does not intend to complete the transaction, it can assert REQx whenever it needs to use the PCI bus again.

The PCI bridge terminates a transaction in the following cases: • Eight PCI clock cycles have elapsed between data phases. This is a ‘latency disconnect’ (see

Figure 9-7 ).

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• • • • AD[1-0] is 0bx1 (a reserved burst ordering encoding) during the address phase and one data phase has completed.

The PCI command is a configuration command and one data phase has completed when a streaming transaction crosses a 4K page boundary.

A streaming transaction runs out of I/O sequencer buffer entries.

A cache line wrap transaction has completed a cache line transfer.

Another target-initiated termination is the retry termination. Retry refers to termination requested because the target is currently in a state where it is unable to process the transaction. This can occur because no buffer entries are available in the I/O sequencer, or the sixteen clock latency timer has expired without transfer of the first data. The target latency timer of the PCI bridge can be optionally disabled see

Section 9.11.2.22, “PCI Bus Function Register.”

When the PCI bridge is in host mode it does not respond to any PCI configuration transactions. When the PCI bridge is in agent mode and AGENT_CFG_LOCK is set (refer to

Section 9.11.2.22, “PCI Bus Function Register”

) the PCI bridge will retry all configuration transactions. Note that all retried accesses

need to be completed. An example of a retry is shown in Figure 9-7 .

Note that because a target can determine whether or not data is transferred (when both IRDY and TRDY are asserted), if it wants to do only one more data transfer and then stop, it may assert TRDY and STOP at the same time.

Target-abort refers to the abnormal termination that is used when a fatal error has occurred, or when a target will never be able to respond. Target-abort is indicated by the fact that STOP is asserted and DEVSEL is negated. This indicates that the target requires the transaction to be terminated and does not want the transaction tried again. Note that any transferred data may have been corrupted. The PCI bridge terminates a transaction with target-abort in the case in which it is the intended target of a read transaction from system memory and the data from memory is corrupt. If the PCI bridge is the intended target of a transaction and an address parity error occurs, or a data parity error occurs on a write transaction to system memory, it continues the transaction on the PCI bus but aborts internally. The PCI bridge does not target-abort in this case.

If the PCI bridge is mastering a transaction and the transaction terminates with a target-abort, undefined data will be returned on a read and write data will be lost. An example of a target-abort is shown in

Figure 9-7 .

An initiator may retry any target disconnect accesses, except target-abort, at a later time starting with the address of the next non-transferred data. Retry is actually a special case of disconnect where no data transfer occurs at all and the initiator must start the entire transaction over again.

9.9.1.4

Other Bus Operations

The following sections provide information on additional PCI bus operations.

9.9.1.4.1

Device Selection

As a target, the PCI bridge drives DEVSEL one clock following the address phase as indicated in the configuration space status register; see

Section 9.11.2.4, “PCI Bus Status Register.”

The PCI bridge as a Freescale Semiconductor

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target qualifies the address/data lines with FRAME before asserting DEVSEL. DEVSEL is asserted at or before the clock edge at which the PCI bridge enables its TRDY, STOP, or data (for a read). DEVSEL is not negated until FRAME is negated, with IRDY asserted and either STOP or TRDY asserted. The

exception to this is a target-abort; see Section 9.9.1.3.2, “Transaction Termination.”

As an initiator, if the PCI bridge does not see the assertion of DEVSEL within 4 clocks of FRAME, it terminates the transaction with a master-abort as described in

Section 9.9.1.3.2, “Transaction Termination.”

9.9.1.4.2

Fast Back-to-Back Transactions

In the two types of fast back-to-back transactions, the first type places the burden of avoiding contention on the initiator while the second places the burden on all potential targets. The PCI bridge as a target supports both types of fast back-to-back transactions but does not support them as an initiator. The PCI bridge as a target has the fast back-to-back enable bit hardwired to one, or enabled; see

Table 9-18 .

For the first type (governed by the initiator), the initiator may only run a fast back-to-back transaction to the same target. For the second type, when the PCI bridge detects a fast-back-to-back operation and did not drive DEVSEL in the previous cycle, it delays the assertion of DEVSEL and TRDY for one cycle to allow the other target to get off the bus.

9.9.1.4.3

Data Streaming

The PCI bridge provides data streaming for PCI transactions to and from prefetchable memory. In other words, when the PCI bridge is a target for a PCI initiated transaction, it supplies or accepts multiple cache lines of data without disconnecting. For PCI transactions to non-prefetchable space, the PCI bridge disconnects after the first data phase so that no streaming can occur.

For PCI memory reads, streaming is achieved by performing speculative reads from memory in prefetchable space. A block of memory can be marked as prefetchable by setting the prefetch bit in the corresponding inbound ATU (see

Table 9-18

) in the following cases: • • • When reads do not alter the contents of memory (reads have no side effects) When reads return all bytes regardless of the byte enable signals When writes can be merged without causing errors For a memory read command or a memory read line command, the PCI bridge reads one cache line from memory. If the PCI read or read line transaction crosses a cache line boundary, the PCI bridge starts the read of a new cache line. For a memory read multiple command, the PCI bridge reads two cache lines from memory. When the PCI transaction finishes the read for the first cache line, the PCI bridge performs a speculative read of a third cache line. The PCI bridge continues this prefetching until the end of the transaction.

For PCI writes to memory, streaming is achieved by buffering the transaction in the space available within the I/O sequencer. This allows PCI memory writes to execute with no wait states.

A disconnect occurs if the PCI bridge runs out of buffer space on writes, or the PCI bridge cannot supply consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also occurs if the transaction crosses a 4K page boundary. 9-14

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

PCI Bridge

For core- or DMA-initiated transfers, the PCI bridge streams over cache line boundaries if the prefetch bit in the corresponding outbound ATU is enabled and the address space identified by the outbound ATU is marked as PCI memory space.

9.9.1.4.4

Host Mode Configuration Access

The PCI bridge provides two types of configuration accesses to support hierarchical bridges. To access configuration space, a value is written to the CONFIG_ADDR register specifying which PCI bus, which device, and which configuration register to be accessed.

When the PCI bridge sees an access t