NXP MPC8545E PowerQUICC® III Processor Reference Manual

NXP MPC8545E PowerQUICC®  III Processor Reference Manual
This manual has been updated in several places.
Please consult "Errata to MPC8548E PowerQUICC III Integrated
Host Processor Family Reference Manual, Rev. 2," Rev 2.4,
available from freescale.com (order ID MPC8548ERMAD), to see
these changes.
MPC8548E PowerQUICC™ III
Integrated Processor
Family Reference Manual
Supports
MPC8548E
MPC8548
MPC8547E
MPC8545E
MPC8545
MPC8543E
MPC8543
MPC8548ERM
Rev. 2
02/2007
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Part I—Overview
I
Overview
1
Memory Map
2
Signal Descriptions
3
Reset, Clocking, and Initialization
4
Part II—e500 Core Complex and L2 Cache
II
Core Complex Overview
5
Core Register Summary
6
L2 Look-Aside Cache/SRAM
7
Part III—Memory, Security, and I/O Interfaces
III
e500 Coherency Module
8
DDR Memory Controller
9
Programmable Interrupt Controller
10
I2C Interfaces
11
DUART
12
Local Bus Controller
13
Enhanced Three-Speed Ethernet Controllers
14
DMA Controller
15
PCI/PCI-X Bus Interface
16
Serial RapidIO Interface
17
PCI Express Interface Controller
18
Security Engine (SEC) 2.1
19
Part IV—Global Functions and Debug
IV
Global Utilities
20
Device Performance Monitor
21
Debug Features and Watchpoint Facility
22
MPC8547E
A
MPC8545E
B
MPC8543E
C
Revision History
D
Glossary
GLO
Index 1 Register Index (Memory-Mapped Registers)
REG
Index 2 General Index
IND
I
Part I—Overview
1
Overview
2
Memory Map
3
Signal Descriptions
4
Reset, Clocking, and Initialization
II
Part II—e500 Core Complex and L2 Cache
5
Core Complex Overview
6
Core Register Summary
7
L2 Look-Aside Cache/SRAM
III
Part III—Memory, Security, and I/O Interfaces
8
e500 Coherency Module
9
DDR Memory Controller
10
Programmable Interrupt Controller
11
I2C Interfaces
12
DUART
13
Local Bus Controller
14
Enhanced Three-Speed Ethernet Controllers
15
DMA Controller
16
PCI/PCI-X Bus Interface
17
Serial RapidIO Interface
18
PCI Express Interface Controller
19
Security Engine (SEC) 2.1
IV
Part IV—Global Functions and Debug
20
Global Utilities
21
Device Performance Monitor
22
Debug Features and Watchpoint Facility
A
MPC8547E
B
MPC8545E
C
MPC8543E
D
Revision History
GLO
Glossary
REG
Index 1 Register Index (Memory-Mapped Registers)
IND
Index 2 General Index
Contents
Paragraph
Number
Title
Page
Number
Contents
About This Book
Audience ............................................................................................................................cv
Organization.......................................................................................................................cv
Suggested Reading......................................................................................................... cviii
General Information................................................................................................... cviii
Related Documentation.............................................................................................. cviii
Conventions ......................................................................................................................cix
Signal Conventions ............................................................................................................cx
Acronyms and Abbreviations ............................................................................................cx
Part I
Overview
Chapter 1
Overview
1.1
1.2
1.2.1
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
1.3.10
1.3.11
1.3.12
1.3.13
1.3.14
1.3.15
1.3.16
Introduction...................................................................................................................... 1-1
MPC8548E Overview...................................................................................................... 1-2
Key Features ................................................................................................................ 1-2
MPC8548E Architecture Overview............................................................................... 1-10
e500 Core Overview .................................................................................................. 1-10
On-Chip Memory Unit............................................................................................... 1-14
On-Chip Memory as Memory-Mapped SRAM......................................................... 1-15
On-Chip Memory as L2 Cache.................................................................................. 1-15
e500 Coherency Module (ECM)................................................................................ 1-16
DDR SDRAM Controller .......................................................................................... 1-16
Programmable Interrupt Controller (PIC).................................................................. 1-17
Integrated Security Engine (SEC) for the MPC8548E .............................................. 1-18
I2C Controllers........................................................................................................... 1-19
Boot Sequencer .......................................................................................................... 1-19
Dual Universal Asynchronous Receiver/Transmitter (DUART) ............................... 1-19
Local Bus Controller.................................................................................................. 1-19
Enhanced Three-Speed Ethernet Controllers (eTSECs)............................................ 1-20
OceaN Switch Fabric ................................................................................................. 1-22
Integrated DMA......................................................................................................... 1-22
PCI/PCI-X Controllers............................................................................................... 1-22
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v
Contents
Paragraph
Number
1.3.17
1.3.18
1.3.18.1
1.3.19
1.3.20
1.3.21
1.3.22
1.3.23
1.3.24
1.4
1.4.1
Page
Number
Title
High Speed I/O Interfaces.......................................................................................... 1-23
Serial RapidIO Interface ............................................................................................ 1-23
RapidIO Message Unit .......................................................................................... 1-23
PCI Express Interface ................................................................................................ 1-24
Power Management ................................................................................................... 1-24
Clocking..................................................................................................................... 1-25
Address Map .............................................................................................................. 1-25
Processing Across the On-Chip Fabric...................................................................... 1-25
Data Processing with the e500 Coherency Module ................................................... 1-26
MPC8548E Application Examples ................................................................................ 1-26
MPC8548E Applications ........................................................................................... 1-26
Chapter 2
Memory Map
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.3.7
2.2.3.8
2.2.3.9
2.2.4
2.2.5
2.2.5.1
2.2.5.2
2.2.5.3
2.2.5.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
Local Memory Map Overview and Example .................................................................. 2-1
Address Translation and Mapping ................................................................................... 2-3
SRAM Windows.......................................................................................................... 2-4
Window into Configuration Space............................................................................... 2-4
Local Access Windows................................................................................................ 2-4
Local Access Register Memory Map ...................................................................... 2-5
Local Access IP Block Revision Register 1 (LAIPBRR1)...................................... 2-6
Local Access IP Block Revision Register 2 (LAIPBRR2)...................................... 2-6
Local Access Window n Base Address Registers (LAWBAR0–LAWBAR9)........ 2-7
Local Access Window n Attributes Registers (LAWAR0–LAWAR9) .................... 2-7
Precedence of Local Access Windows .................................................................... 2-8
Configuring Local Access Windows ....................................................................... 2-8
Distinguishing Local Access Windows from Other Mapping Functions ................ 2-9
Illegal Interaction Between Local Access Windows and DDR
SDRAM Chip Selects.......................................................................................... 2-9
Outbound Address Translation and Mapping Windows.............................................. 2-9
Inbound Address Translation and Mapping Windows .............................................. 2-10
Serial RapidIO Inbound ATMU............................................................................. 2-10
PCI/PCI-X Inbound ATMU................................................................................... 2-10
PCI Express Inbound ATMU................................................................................. 2-10
Illegal Interaction Between Inbound ATMUs and Local Access Windows .......... 2-10
Configuration, Control, and Status Register Map.......................................................... 2-10
Accessing CCSR Memory from the Local Processor................................................ 2-11
Accessing CCSR Memory from External Masters .................................................... 2-12
Organization of CCSR Memory ................................................................................ 2-12
General Utilities Registers ......................................................................................... 2-13
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number
2.3.5
2.3.6
2.3.7
2.3.8
2.4
Title
Page
Number
Interrupt Controller and CCSR .................................................................................. 2-14
Serial RapidIO and CCSR ......................................................................................... 2-14
Device-Specific Utilities............................................................................................ 2-15
Accessing Reserved Registers and Bits ..................................................................... 2-16
Complete CCSR Map .................................................................................................... 2-16
Chapter 3
Signal Descriptions
3.1
3.2
3.3
Signals Overview ............................................................................................................. 3-1
Configuration Signals Sampled at Reset ....................................................................... 3-18
Output Signal States During Reset ................................................................................ 3-20
Chapter 4
Reset, Clocking, and Initialization
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.1.1
4.3.1.1.1
4.3.1.1.2
4.3.1.2
4.3.1.2.1
4.3.1.2.2
4.3.1.3
4.3.1.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
4.4.3.4
Overview.......................................................................................................................... 4-1
External Signal Descriptions ........................................................................................... 4-1
System Control Signals................................................................................................ 4-2
Clock Signals ............................................................................................................... 4-3
Memory Map/Register Definition ................................................................................... 4-3
Local Configuration Control........................................................................................ 4-3
Accessing Configuration, Control, and Status Registers......................................... 4-4
Updating CCSRBAR ........................................................................................... 4-4
Configuration, Control, and Status Base Address Register (CCSRBAR)........... 4-5
Accessing Alternate Configuration Space ............................................................... 4-5
Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6
Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6
Boot Page Translation.............................................................................................. 4-7
Boot Page Translation Register (BPTR).............................................................. 4-7
Boot Sequencer ............................................................................................................ 4-7
Functional Description..................................................................................................... 4-8
Reset Operations .......................................................................................................... 4-8
Soft Reset................................................................................................................. 4-8
Hard Reset ............................................................................................................... 4-8
Power-On Reset Sequence........................................................................................... 4-9
Power-On Reset Configuration.................................................................................. 4-10
System PLL Ratio.................................................................................................. 4-11
e500 Core PLL Ratio ............................................................................................. 4-12
Boot ROM Location .............................................................................................. 4-12
Host/Agent Configuration ..................................................................................... 4-13
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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vii
Contents
Paragraph
Number
4.4.3.5
4.4.3.6
4.4.3.7
4.4.3.8
4.4.3.9
4.4.3.10
4.4.3.11
4.4.3.12
4.4.3.13
4.4.3.14
4.4.3.15
4.4.3.16
4.4.3.17
4.4.3.18
4.4.3.19
4.4.3.20
4.4.3.21
4.4.3.22
4.4.3.23
4.4.3.24
4.4.3.25
4.4.3.26
4.4.3.27
4.4.4
4.4.4.1
4.4.4.2
4.4.4.2.1
4.4.4.3
4.4.4.4
Page
Number
Title
I/O Port Selection .................................................................................................. 4-14
CPU Boot Configuration ....................................................................................... 4-15
Boot Sequencer Configuration .............................................................................. 4-15
DDR SDRAM Type............................................................................................... 4-16
eTSEC1 and eTSEC2 Width.................................................................................. 4-16
eTSEC3 and eTSEC4 Width.................................................................................. 4-17
eTSEC1 Protocol ................................................................................................... 4-17
eTSEC2 Protocol ................................................................................................... 4-18
eTSEC3 Protocol ................................................................................................... 4-18
eTSEC4 Protocol ................................................................................................... 4-19
RapidIO Device ID ................................................................................................ 4-19
RapidIO System Size............................................................................................. 4-20
PCI Clock Selection............................................................................................... 4-20
PCI Speed Configuration ....................................................................................... 4-21
PCI Bus Width ....................................................................................................... 4-21
PCI I/O Impedance ................................................................................................ 4-22
PCI Arbiter Configuration ..................................................................................... 4-22
PCI Debug Configuration ...................................................................................... 4-23
PCI-X Configuration ............................................................................................. 4-23
Memory Debug Configuration .............................................................................. 4-23
DDR Debug Configuration.................................................................................... 4-24
General-Purpose POR Configuration .................................................................... 4-24
SerDes Enable........................................................................................................ 4-24
Clocking..................................................................................................................... 4-25
System Clock/PCI Clock ....................................................................................... 4-25
RapidIO and PCI Express Clocks.......................................................................... 4-26
Minimum Frequency Requirements .................................................................. 4-27
Ethernet Clocks...................................................................................................... 4-27
Real Time Clock .................................................................................................... 4-27
Part II
e500 Core Complex and L2 Cache
Chapter 5
Core Complex Overview
5.1
5.1.1
5.1.2
5.2
5.3
Overview.......................................................................................................................... 5-1
Upward Compatibility ................................................................................................. 5-3
Core Complex Summary ............................................................................................. 5-3
e500 Processor and System Version Numbers................................................................. 5-4
Features ............................................................................................................................ 5-5
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number
5.3.1
5.4
5.5
5.5.1
5.5.2
5.5.3
5.6
5.7
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.9
5.9.1
5.9.2
5.9.3
5.9.4
5.10
5.10.1
5.10.2
5.10.3
5.10.4
5.11
5.12
5.12.1
5.12.2
5.12.3
5.13
5.13.1
5.13.1.1
5.13.1.2
5.13.2
5.13.3
5.13.4
5.13.5
5.13.6
5.14
Title
Page
Number
e500v2 Differences .................................................................................................... 5-11
Instruction Set ................................................................................................................ 5-12
Instruction Flow ............................................................................................................. 5-14
Initial Instruction Fetch.............................................................................................. 5-14
Branch Detection and Prediction ............................................................................... 5-14
e500 Execution Pipeline ............................................................................................ 5-15
Programming Model ...................................................................................................... 5-17
On-Chip Cache Implementation .................................................................................... 5-19
Interrupts and Exception Handling ................................................................................ 5-19
Exception Handling ................................................................................................... 5-19
Interrupt Classes ........................................................................................................ 5-20
Interrupt Types ........................................................................................................... 5-20
Upper Bound on Interrupt Latencies ......................................................................... 5-21
Interrupt Registers...................................................................................................... 5-21
Memory Management.................................................................................................... 5-23
Address Translation ................................................................................................... 5-25
MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)..................................... 5-26
Process ID Registers (PID0–PID2)............................................................................ 5-27
TLB Coherency.......................................................................................................... 5-27
Memory Coherency ....................................................................................................... 5-27
Atomic Update Memory References ......................................................................... 5-28
Memory Access Ordering.......................................................................................... 5-28
Cache Control Instructions ........................................................................................ 5-28
Programmable Page Characteristics .......................................................................... 5-28
Core Complex Bus (CCB) ............................................................................................. 5-28
Performance Monitoring................................................................................................ 5-29
Global Control Register ............................................................................................. 5-29
Performance Monitor Counter Registers ................................................................... 5-29
Local Control Registers ............................................................................................. 5-30
Legacy Support of Power Architecture Technology...................................................... 5-30
Instruction Set Compatibility..................................................................................... 5-30
User Instruction Set ............................................................................................... 5-30
Supervisor Instruction Set...................................................................................... 5-31
Memory Subsystem ................................................................................................... 5-31
Exception Handling ................................................................................................... 5-31
Memory Management................................................................................................ 5-31
Reset........................................................................................................................... 5-31
Little-Endian Mode.................................................................................................... 5-32
PowerQUICC III Implementation Details ..................................................................... 5-32
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number
Page
Number
Title
Chapter 6
Core Register Summary
6.1
6.1.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.7
6.7.1
6.7.1.1
6.7.1.2
6.7.1.3
6.7.1.4
6.7.1.5
6.7.1.6
6.7.1.7
6.7.1.8
6.7.2
6.7.2.1
6.7.2.2
6.7.2.3
6.7.2.4
6.8
Overview.......................................................................................................................... 6-1
Register Set .................................................................................................................. 6-1
Register Model for 32-Bit Implementations .................................................................... 6-3
Special-Purpose Registers (SPRs) ............................................................................... 6-4
Registers for Computational Operations.......................................................................... 6-8
General-Purpose Registers (GPRs).............................................................................. 6-8
Integer Exception Register (XER)............................................................................... 6-8
Registers for Branch Operations...................................................................................... 6-9
Condition Register (CR) .............................................................................................. 6-9
Link Register (LR)..................................................................................................... 6-11
Count Register (CTR)................................................................................................ 6-11
Processor Control Registers........................................................................................... 6-11
Machine State Register (MSR) .................................................................................. 6-11
Processor ID Register (PIR) ...................................................................................... 6-13
Processor Version Register (PVR)............................................................................. 6-13
System Version Register (SVR)................................................................................. 6-14
Timer Registers .............................................................................................................. 6-14
Timer Control Register (TCR)................................................................................... 6-14
Timer Status Register (TSR)...................................................................................... 6-15
Time Base Registers .................................................................................................. 6-16
Decrementer Register ................................................................................................ 6-16
Decrementer Auto-Reload Register (DECAR).......................................................... 6-17
Interrupt Registers.......................................................................................................... 6-17
Interrupt Registers Defined by the Embedded and Base Categories ......................... 6-17
Save/Restore Register 0 (SRR0)............................................................................ 6-17
Save/Restore Register 1 (SRR1)............................................................................ 6-17
Critical Save/Restore Register 0 (CSRR0) ............................................................ 6-17
Critical Save/Restore Register 1 (CSRR1) ............................................................ 6-18
Data Exception Address Register (DEAR)............................................................ 6-18
Interrupt Vector Prefix Register (IVPR) ................................................................ 6-18
Interrupt Vector Offset Registers (IVORn)............................................................ 6-18
Exception Syndrome Register (ESR) .................................................................... 6-19
Additional Interrupt Registers ................................................................................... 6-20
Machine Check Save/Restore Register 0 (MCSRR0) ........................................... 6-20
Machine Check Save/Restore Register 1 (MCSRR1) ........................................... 6-20
Machine Check Address Register (MCAR/MCARU) .......................................... 6-21
Machine Check Syndrome Register (MCSR)........................................................ 6-21
Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 6-22
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Paragraph
Number
6.9
6.9.1
6.9.2
6.9.3
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.12
6.12.1
6.12.2
6.12.3
6.12.4
6.12.4.1
6.12.4.2
6.12.5
6.12.5.1
6.12.5.2
6.12.5.3
6.12.5.4
6.12.5.5
6.12.5.6
6.12.5.7
6.13
6.13.1
6.13.1.1
6.13.1.2
6.13.1.3
6.13.2
6.13.3
6.13.4
6.14
6.14.1
6.15
6.15.1
6.15.2
Title
Page
Number
Branch Target Buffer (BTB) Registers .......................................................................... 6-23
Branch Buffer Entry Address Register (BBEAR) ..................................................... 6-23
Branch Buffer Target Address Register (BBTAR) .................................................... 6-23
Branch Unit Control and Status Register (BUCSR) .................................................. 6-24
Hardware Implementation-Dependent Registers........................................................... 6-25
Hardware Implementation-Dependent Register 0 (HID0)......................................... 6-25
Hardware Implementation-Dependent Register 1 (HID1)......................................... 6-26
L1 Cache Configuration Registers................................................................................. 6-28
L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 6-28
L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 6-29
L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 6-30
L1 Cache Configuration Register 1 (L1CFG1) ......................................................... 6-31
MMU Registers.............................................................................................................. 6-32
Process ID Registers (PID0–PID2)............................................................................ 6-32
MMU Control and Status Register 0 (MMUCSR0) .................................................. 6-32
MMU Configuration Register (MMUCFG) .............................................................. 6-32
TLB Configuration Registers (TLBnCFG)................................................................ 6-33
TLB0 Configuration Register 0 (TLB0CFG) ........................................................ 6-33
TLB1 Configuration Register 1 (TLB1CFG) ........................................................ 6-34
MMU Assist Registers............................................................................................... 6-35
MAS Register 0 (MAS0) ....................................................................................... 6-35
MAS Register 1 (MAS1) ....................................................................................... 6-35
MAS Register 2 (MAS2) ....................................................................................... 6-36
MAS Register 3 (MAS3) ....................................................................................... 6-37
MAS Register 4 (MAS4) ....................................................................................... 6-38
MAS Register 6 (MAS6) ....................................................................................... 6-38
MAS Register 7 (MAS7) ....................................................................................... 6-39
Debug Registers ............................................................................................................. 6-39
Debug Control Registers (DBCR0–DBCR2) ............................................................ 6-39
Debug Control Register 0 (DBCR0)...................................................................... 6-39
Debug Control Register 1 (DBCR1)...................................................................... 6-41
Debug Control Register 2 (DBCR2)...................................................................... 6-42
Debug Status Register (DBSR).................................................................................. 6-43
Instruction Address Compare Registers (IAC1–IAC2) ............................................. 6-45
Data Address Compare Registers (DAC1–DAC2).................................................... 6-45
Signal Processing and Embedded Floating-Point Status
and Control Register (SPEFSCR).............................................................................. 6-45
Accumulator (ACC)................................................................................................... 6-47
Performance Monitor Registers (PMRs) ....................................................................... 6-48
Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-49
Local Control A Registers (PMLCa0–PMLCa3, UPMLCa0–UPMLCa3) ............... 6-50
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6.15.3
6.15.4
Page
Number
Title
Local Control B Registers (PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) .............. 6-51
Performance Monitor Counter Registers (PMC0–PMC3, UPMC0–UPMC3).......... 6-52
Chapter 7
L2 Look-Aside Cache/SRAM
7.1
7.1.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.2.1
7.3.1.2.2
7.3.1.2.3
7.3.1.3
7.3.1.3.1
7.3.1.3.2
7.3.1.4
7.3.1.4.1
7.3.1.4.2
7.4
7.4.1
7.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.8
L2 Cache Overview ......................................................................................................... 7-1
L2 Cache and SRAM Features .................................................................................... 7-2
L2 Cache and SRAM Organization ................................................................................. 7-4
Accessing the On-Chip Array as an L2 Cache ............................................................ 7-5
Accessing the On-Chip Array as an SRAM ................................................................ 7-5
Connection of the On-Chip Memory to the System .................................................... 7-7
Memory Map/Register Definition ................................................................................... 7-8
L2/SRAM Register Descriptions ............................................................................... 7-10
L2 Control Register (L2CTL)................................................................................ 7-10
L2 Cache External Write Registers ....................................................................... 7-13
L2 Cache External Write Address Registers 0–3 (L2CEWARn) ...................... 7-13
L2 Cache External Write Address Registers Extended Address 0–3
(L2CEWAREAn)........................................................................................... 7-14
L2 Cache External Write Control Registers 0–3 (L2CEWCRn)....................... 7-15
L2 Memory-Mapped SRAM Registers ................................................................. 7-16
L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn) ........ 7-16
L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
(L2SRBAREAn)............................................................................................ 7-17
L2 Error Registers.................................................................................................. 7-17
Error Injection Registers.................................................................................... 7-18
Error Control and Capture Registers ................................................................. 7-20
External Writes to the L2 Cache (Cache Stashing)........................................................ 7-25
Stash-Only Cache Regions ........................................................................................ 7-26
L2 Cache Timing ........................................................................................................... 7-27
L2 Cache and SRAM Coherency................................................................................... 7-27
L2 Cache Coherency Rules........................................................................................ 7-28
Memory-Mapped SRAM Coherency Rules .............................................................. 7-29
L2 Cache Locking.......................................................................................................... 7-29
Locking the Entire L2 Cache ..................................................................................... 7-29
Locking Programmed Memory Ranges..................................................................... 7-30
Locking Selected Lines.............................................................................................. 7-30
Clearing Locks on Selected Lines ............................................................................. 7-30
Flash Clearing of Instruction and Data Locks ........................................................... 7-31
Locks with Stale Data ................................................................................................ 7-31
PLRU L2 Replacement Policy....................................................................................... 7-31
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Paragraph
Number
7.8.1
7.8.2
7.9
7.9.1
7.9.1.1
7.9.1.2
7.9.2
7.9.3
7.9.3.1
7.9.3.2
7.9.4
7.9.5
7.9.6
Title
Page
Number
PLRU Bit Update Considerations.............................................................................. 7-32
Allocation of Lines .................................................................................................... 7-32
L2 Cache Operation ....................................................................................................... 7-33
Initialization ............................................................................................................... 7-33
L2 Cache Initialization .......................................................................................... 7-33
Memory-Mapped SRAM Initialization ................................................................. 7-33
Flash Invalidation of the L2 Cache............................................................................ 7-34
Managing Errors ........................................................................................................ 7-34
ECC Errors............................................................................................................. 7-34
Tag Parity Errors.................................................................................................... 7-34
L2 Cache States ......................................................................................................... 7-34
L2 State Transitions ................................................................................................... 7-35
Error Checking and Correcting (ECC) ...................................................................... 7-39
Part III
Memory, Security, and I/O Interfaces
Chapter 8
e500 Coherency Module
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.1.5
8.2.1.6
8.2.1.7
8.2.1.8
8.2.1.9
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
Introduction...................................................................................................................... 8-1
Overview...................................................................................................................... 8-2
Features........................................................................................................................ 8-2
Memory Map/Register Definition ................................................................................... 8-3
Register Descriptions................................................................................................... 8-3
ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3
ECM CCB Port Configuration Register (EEBPCR) ............................................... 8-4
ECM IP Block Revision Register 1 (EIPBRR1) ..................................................... 8-5
ECM IP Block Revision Register 2 (EIPBRR2) ..................................................... 8-5
ECM Error Detect Register (EEDR) ....................................................................... 8-6
ECM Error Enable Register (EEER) ....................................................................... 8-7
ECM Error Attributes Capture Register (EEATR) .................................................. 8-7
ECM Error Low Address Capture Register (EELADR) ......................................... 8-8
ECM Error High Address Capture Register (EEHADR) ........................................ 8-9
Functional Description..................................................................................................... 8-9
I/O Arbiter.................................................................................................................... 8-9
CCB Arbiter................................................................................................................. 8-9
Transaction Queue ..................................................................................................... 8-10
Global Data Multiplexor............................................................................................ 8-10
CCB Interface ............................................................................................................ 8-10
Initialization/Application Information ........................................................................... 8-10
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Page
Number
Title
Chapter 9
DDR Memory Controller
9.1
9.2
9.2.1
9.3
9.3.1
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.1.5
9.4.1.6
9.4.1.7
9.4.1.8
9.4.1.9
9.4.1.10
9.4.1.11
9.4.1.12
9.4.1.13
9.4.1.14
9.4.1.15
9.4.1.16
9.4.1.17
9.4.1.18
9.4.1.19
9.4.1.20
9.4.1.21
9.4.1.22
9.4.1.23
9.4.1.24
9.4.1.25
9.4.1.26
9.4.1.27
Introduction...................................................................................................................... 9-1
Features ............................................................................................................................ 9-2
Modes of Operation ..................................................................................................... 9-3
External Signal Descriptions ........................................................................................... 9-3
Signals Overview......................................................................................................... 9-3
Detailed Signal Descriptions ....................................................................................... 9-6
Memory Interface Signals........................................................................................ 9-6
Clock Interface Signals............................................................................................ 9-9
Debug Signals........................................................................................................ 9-10
Memory Map/Register Definition ................................................................................. 9-10
Register Descriptions................................................................................................. 9-11
Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-11
Chip Select Configuration (CSn_CONFIG).......................................................... 9-12
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 9-14
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 9-14
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-16
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-18
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-20
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-23
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-25
DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-26
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-26
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-29
DDR SDRAM Data Initialization (DDR_DATA_INIT) ....................................... 9-30
DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 9-30
DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-31
DDR Initialization Extended Address (DDR_INIT_EXT_ADDR) ...................... 9-31
DDR IP Block Revision 1 (DDR_IP_REV1)........................................................ 9-32
DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 9-32
Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI) ........ 9-33
Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 9-33
Memory Data Path Error Injection Mask ECC (ERR_INJECT)........................... 9-34
Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-34
Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 9-35
Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 9-35
Memory Error Detect (ERR_DETECT)................................................................ 9-35
Memory Error Disable (ERR_DISABLE)............................................................. 9-36
Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-37
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Paragraph
Number
9.4.1.28
9.4.1.29
9.4.1.30
9.4.1.31
9.5
9.5.1
9.5.1.1
9.5.2
9.5.3
9.5.4
9.5.4.1
9.5.5
9.5.6
9.5.7
9.5.8
9.5.8.1
9.5.8.2
9.5.8.2.1
9.5.9
9.5.10
9.5.11
9.5.12
9.6
9.6.1
9.6.2
9.6.3
9.6.3.1
9.6.3.2
9.6.3.3
Title
Page
Number
Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-38
Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-39
Memory Error Extended Address Capture (CAPTURE_EXT_ADDRESS)......... 9-40
Single-Bit ECC Memory Error Management (ERR_SBE) ................................... 9-40
Functional Description................................................................................................... 9-41
DDR SDRAM Interface Operation............................................................................ 9-45
Supported DDR SDRAM Organizations............................................................... 9-45
DDR SDRAM Address Multiplexing........................................................................ 9-47
JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-52
DDR SDRAM Interface Timing................................................................................ 9-54
Clock Distribution ................................................................................................. 9-57
DDR SDRAM Mode-Set Command Timing............................................................. 9-58
DDR SDRAM Registered DIMM Mode ................................................................... 9-59
DDR SDRAM Write Timing Adjustments ................................................................ 9-59
DDR SDRAM Refresh .............................................................................................. 9-60
DDR SDRAM Refresh Timing.............................................................................. 9-61
DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-61
Self-Refresh in Sleep Mode............................................................................... 9-63
DDR Data Beat Ordering........................................................................................... 9-64
Page Mode and Logical Bank Retention ................................................................... 9-64
Error Checking and Correcting (ECC) ...................................................................... 9-65
Error Management ..................................................................................................... 9-67
Initialization/Application Information........................................................................... 9-68
Programming Differences Between Memory Types.................................................. 9-69
DDR SDRAM Initialization Sequence ...................................................................... 9-72
Using Forced Self-Refresh Mode to Implement a Battery-Backed
RAM System ......................................................................................................... 9-72
Hardware Based Self-Refresh................................................................................ 9-72
Software Based Self-Refresh................................................................................. 9-73
Bypassing Re-initialization During Battery-Backed Operation ............................ 9-73
Chapter 10
Programmable Interrupt Controller
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.4.1
10.1.4.2
Introduction.................................................................................................................... 10-1
Overview.................................................................................................................... 10-1
Features...................................................................................................................... 10-1
Interrupts to the Processor Core................................................................................. 10-2
Modes of Operation ................................................................................................... 10-3
Mixed Mode (GCR[M] = 1) .................................................................................. 10-3
Pass-Through Mode (GCR[M] = 0) ...................................................................... 10-3
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Number
10.1.5
10.1.5.1
10.1.5.2
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
10.3.1.6
10.3.1.7
10.3.1.8
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.3.2.5
10.3.2.6
10.3.3
10.3.3.1
10.3.3.2
10.3.3.3
10.3.3.4
10.3.3.5
10.3.3.6
10.3.3.7
10.3.4
10.3.4.1
10.3.4.2
10.3.4.3
10.3.5
10.3.5.1
10.3.5.2
10.3.5.3
10.3.6
10.3.6.1
Page
Number
Title
Interrupt Sources........................................................................................................ 10-4
Interrupt Routing—Mixed Mode........................................................................... 10-4
Internal Interrupt Sources ...................................................................................... 10-5
External Signal Descriptions ......................................................................................... 10-6
Signal Overview ........................................................................................................ 10-6
Detailed Signal Descriptions ..................................................................................... 10-6
Memory Map/Register Definition ................................................................................. 10-7
Global Registers....................................................................................................... 10-16
Block Revision Register 1 (BRR1)...................................................................... 10-16
Block Revision Register 2 (BRR2)...................................................................... 10-17
Feature Reporting Register (FRR)....................................................................... 10-17
Global Configuration Register (GCR)................................................................. 10-18
Vendor Identification Register (VIR) .................................................................. 10-19
Processor Initialization Register (PIR) ................................................................ 10-19
IPI Vector/Priority Registers (IPIVPRn) ............................................................. 10-20
Spurious Vector Register (SVR).......................................................................... 10-21
Global Timer Registers ............................................................................................ 10-21
Timer Frequency Reporting Register (TFRR)..................................................... 10-21
Global Timer Current Count Registers (GTCCRn) ............................................. 10-22
Global Timer Base Count Registers (GTBCRn).................................................. 10-22
Global Timer Vector/Priority Registers (GTVPRn)............................................. 10-23
Global Timer Destination Registers (GTDRn) .................................................... 10-24
Timer Control Register (TCR)............................................................................. 10-24
External, IRQ_OUT, and Critical Interrupt Summary Registers............................. 10-26
External Interrupt Summary Register (ERQSR) ................................................. 10-26
IRQ_OUT Summary Register 0 (IRQSR0) ......................................................... 10-27
IRQ_OUT Summary Register 1 (IRQSR1) ......................................................... 10-28
IRQ_OUT Summary Register 2 (IRQSR2) ......................................................... 10-28
Critical Interrupt Summary Register 0 (CISR0).................................................. 10-29
Critical Interrupt Summary Register 1 (CISR1).................................................. 10-29
Critical Interrupt Summary Register 2 (CISR2).................................................. 10-30
Performance Monitor Mask Registers (PMMRs).................................................... 10-30
Performance Monitor n Mask Registers 0 (PMnMR0) ....................................... 10-30
Performance Monitor n Mask Registers 1 (PMnMR1) ....................................... 10-31
Performance Monitor n Mask Registers 2 (PMnMR2) ....................................... 10-31
Message Registers.................................................................................................... 10-32
Message Registers (MSGR0–MSGR3) ............................................................... 10-32
Message Enable Register (MER)......................................................................... 10-32
Message Status Register (MSR) .......................................................................... 10-33
Shared Message Signaled Registers ........................................................................ 10-34
Shared Message Signaled Interrupt Registers (MSIRs) ...................................... 10-34
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Paragraph
Number
10.3.6.2
10.3.6.3
10.3.6.4
10.3.6.5
10.3.7
10.3.7.1
10.3.7.2
10.3.7.3
10.3.7.4
10.3.7.5
10.3.7.6
10.3.8
10.3.8.1
10.3.8.2
10.3.8.3
10.3.8.4
10.3.8.5
10.4
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.5
10.5.1
10.5.1.1
10.5.1.2
Title
Page
Number
Shared Message Signaled Interrupt Status Register (MSISR)............................. 10-34
Shared Message Signaled Interrupt Index Register (MSIIR) .............................. 10-35
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRn).......... 10-35
Shared Message Signaled Interrupt Destination Register (MSIDRn) ................. 10-36
Interrupt Source Configuration Registers ................................................................ 10-37
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................... 10-37
External Interrupt Destination Registers (EIDR0–EIDR11) ............................... 10-38
Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR47)......................... 10-38
Internal Interrupt Destination Registers (IIDR0–IIDR47) .................................. 10-39
Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3) ................. 10-40
Messaging Interrupt Destination Registers (MIDR0–MIDR3) ........................... 10-41
Per-CPU Registers ................................................................................................... 10-41
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3).......................... 10-43
Processor Current Task Priority Register (CTPR)............................................... 10-44
Who Am I Register (WHOAMI) ......................................................................... 10-45
Processor Interrupt Acknowledge Register (IACK)............................................ 10-45
Processor End of Interrupt Register (EOI) .......................................................... 10-46
Functional Description................................................................................................. 10-46
Flow of Interrupt Control......................................................................................... 10-46
Interrupt Source Priority ...................................................................................... 10-48
Processor Current Task Priority........................................................................... 10-48
Interrupt Acknowledge ........................................................................................ 10-48
Nesting of Interrupts ................................................................................................ 10-49
Spurious Vector Generation ..................................................................................... 10-49
Messaging Interrupts................................................................................................ 10-49
Shared Message Signaled Interrupts........................................................................ 10-49
PCI Express INTx.................................................................................................... 10-50
Global Timers .......................................................................................................... 10-50
Reset of the PIC ....................................................................................................... 10-51
Initialization/Application Information ......................................................................... 10-51
Programming Guidelines ......................................................................................... 10-51
PIC Registers ....................................................................................................... 10-51
Changing Interrupt Source Configuration ........................................................... 10-53
Chapter 11
Interfaces
I2C
11.1
11.1.1
11.1.2
11.1.3
Introduction.................................................................................................................... 11-1
Overview.................................................................................................................... 11-2
Features...................................................................................................................... 11-2
Modes of Operation ................................................................................................... 11-2
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Number
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.1.1
11.3.1.2
11.3.1.3
11.3.1.4
11.3.1.5
11.3.1.6
11.4
11.4.1
11.4.1.1
11.4.1.2
11.4.1.3
11.4.1.4
11.4.1.5
11.4.1.5.1
11.4.1.5.2
11.4.1.6
11.4.2
11.4.2.1
11.4.3
11.4.4
11.4.4.1
11.4.4.2
11.4.4.2.1
11.4.4.2.2
11.4.4.3
11.4.5
11.4.5.1
11.4.5.2
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
Page
Number
Title
External Signal Descriptions ......................................................................................... 11-3
Signal Overview ........................................................................................................ 11-3
Detailed Signal Descriptions ..................................................................................... 11-3
Memory Map/Register Definition ................................................................................. 11-4
Register Descriptions................................................................................................. 11-5
I2C Address Register (I2CADR) ........................................................................... 11-6
I2C Frequency Divider Register (I2CFDR)........................................................... 11-6
I2C Control Register (I2CCR) ............................................................................... 11-7
I2C Status Register (I2CSR) .................................................................................. 11-9
I2C Data Register (I2CDR).................................................................................. 11-10
Digital Filter Sampling Rate Register (I2CDFSRR) ............................................11-11
Functional Description..................................................................................................11-11
Transaction Protocol .................................................................................................11-11
START Condition ................................................................................................ 11-12
Slave Address Transmission................................................................................ 11-12
Repeated START Condition ................................................................................ 11-13
STOP Condition................................................................................................... 11-13
Protocol Implementation Details ......................................................................... 11-13
Transaction Monitoring—Implementation Details.......................................... 11-13
Control Transfer—Implementation Details ..................................................... 11-14
Address Compare—Implementation Details ....................................................... 11-15
Arbitration Procedure .............................................................................................. 11-15
Arbitration Control .............................................................................................. 11-15
Handshaking ............................................................................................................ 11-16
Clock Control........................................................................................................... 11-16
Clock Synchronization......................................................................................... 11-16
Input Synchronization and Digital Filter ............................................................. 11-16
Input Signal Synchronization .......................................................................... 11-16
Filtering of SCL and SDA Lines ..................................................................... 11-17
Clock Stretching .................................................................................................. 11-17
Boot Sequencer Mode.............................................................................................. 11-17
EEPROM Calling Address .................................................................................. 11-18
EEPROM Data Format ........................................................................................ 11-19
Initialization/Application Information ......................................................................... 11-21
Initialization Sequence............................................................................................. 11-21
Generation of START .............................................................................................. 11-21
Post-Transfer Software Response ............................................................................ 11-22
Generation of STOP................................................................................................. 11-22
Generation of Repeated START .............................................................................. 11-23
Generation of SCL When SDA Low ....................................................................... 11-23
Slave Mode Interrupt Service Routine..................................................................... 11-23
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Number
11.5.7.1
11.5.7.2
11.5.8
Title
Page
Number
Slave Transmitter and Received Acknowledge ................................................... 11-23
Loss of Arbitration and Forcing of Slave Mode.................................................. 11-23
Interrupt Service Routine Flowchart........................................................................ 11-24
Chapter 12
DUART
12.1
12.1.1
12.1.2
12.2
12.2.1
12.2.2
12.3
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3
12.3.1.4
12.3.1.5
12.3.1.6
12.3.1.7
12.3.1.8
12.3.1.9
12.3.1.10
12.3.1.11
12.3.1.12
12.3.1.13
12.4
12.4.1
12.4.1.1
12.4.1.2
12.4.1.3
12.4.1.4
12.4.2
12.4.3
12.4.4
12.4.4.1
12.4.4.2
12.4.4.3
Overview........................................................................................................................ 12-1
Features...................................................................................................................... 12-1
Modes of Operation ................................................................................................... 12-2
External Signal Descriptions ......................................................................................... 12-3
Signal Overview ........................................................................................................ 12-3
Detailed Signal Descriptions ..................................................................................... 12-3
Memory Map/Register Definition ................................................................................. 12-4
Register Descriptions................................................................................................. 12-6
Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB] = 0) .................... 12-6
Transmitter Holding Registers (UTHR0, UTHR1) (ULCR[DLAB] = 0) ............. 12-6
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
(ULCR[DLAB] = 1) .......................................................................................... 12-7
Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 12-9
Interrupt ID Registers (UIIR0, UIIR1) (ULCR[DLAB] = 0) .............................. 12-10
FIFO Control Registers (UFCR0, UFCR1) (ULCR[DLAB] = 0)....................... 12-11
Line Control Registers (ULCR0, ULCR1).......................................................... 12-12
Modem Control Registers (UMCR0, UMCR1)................................................... 12-14
Line Status Registers (ULSR0, ULSR1) ............................................................. 12-15
Modem Status Registers (UMSR0, UMSR1) ...................................................... 12-16
Scratch Registers (USCR0, USCR1) ................................................................... 12-17
Alternate Function Registers (UAFR0, UAFR1) (ULCR[DLAB] = 1) .............. 12-17
DMA Status Registers (UDSR0, UDSR1) .......................................................... 12-18
Functional Description................................................................................................. 12-19
Serial Interface......................................................................................................... 12-20
START Bit ........................................................................................................... 12-20
Data Transfer ....................................................................................................... 12-21
Parity Bit .............................................................................................................. 12-21
STOP Bit.............................................................................................................. 12-21
Baud-Rate Generator Logic ..................................................................................... 12-21
Local Loopback Mode ............................................................................................. 12-22
Errors ....................................................................................................................... 12-22
Framing Error ...................................................................................................... 12-22
Parity Error .......................................................................................................... 12-22
Overrun Error....................................................................................................... 12-22
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Contents
Paragraph
Number
12.4.5
12.4.5.1
12.4.5.2
12.4.5.3
12.5
Page
Number
Title
FIFO Mode .............................................................................................................. 12-22
FIFO Interrupts .................................................................................................... 12-23
DMA Mode Select ............................................................................................... 12-23
Interrupt Control Logic........................................................................................ 12-23
DUART Initialization/Application Information .......................................................... 12-24
Chapter 13
Local Bus Controller
13.1
13.1.1
13.1.2
13.1.3
13.1.3.1
13.1.3.2
13.1.4
13.2
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.2.1
13.3.1.2.2
13.3.1.2.3
13.3.1.2.4
13.3.1.3
13.3.1.4
13.3.1.5
13.3.1.6
13.3.1.7
13.3.1.8
13.3.1.9
13.3.1.10
13.3.1.11
13.3.1.12
13.3.1.13
13.3.1.14
13.3.1.15
13.3.1.16
13.4
13.4.1
Introduction.................................................................................................................... 13-1
Overview.................................................................................................................... 13-2
Features...................................................................................................................... 13-2
Modes of Operation ................................................................................................... 13-3
LBC Bus Clock and Clock Ratios ......................................................................... 13-3
Source ID Debug Mode ......................................................................................... 13-4
Power-Down Mode.................................................................................................... 13-4
External Signal Descriptions ......................................................................................... 13-4
Memory Map/Register Definition ................................................................................. 13-8
Register Descriptions............................................................................................... 13-10
Base Registers (BR0–BR7) ................................................................................. 13-10
Option Registers (OR0–OR7).............................................................................. 13-12
Address Mask .................................................................................................. 13-12
Option Registers (ORn)—GPCM Mode ......................................................... 13-13
Option Registers (ORn)—UPM Mode ............................................................ 13-15
Option Registers (ORn)—SDRAM Mode ...................................................... 13-16
UPM Memory Address Register (MAR)............................................................. 13-17
UPM Mode Registers (MxMR) ........................................................................... 13-17
Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 13-20
UPM Data Register (MDR) ................................................................................. 13-20
SDRAM Machine Mode Register (LSDMR) ...................................................... 13-21
UPM Refresh Timer (LURT)............................................................................... 13-23
SDRAM Refresh Timer (LSRT).......................................................................... 13-23
Transfer Error Status Register (LTESR) .............................................................. 13-24
Transfer Error Check Disable Register (LTEDR)................................................ 13-25
Transfer Error Interrupt Enable Register (LTEIR) .............................................. 13-26
Transfer Error Attributes Register (LTEATR) ..................................................... 13-27
Transfer Error Address Register (LTEAR).......................................................... 13-28
Local Bus Configuration Register (LBCR) ......................................................... 13-29
Clock Ratio Register (LCRR).............................................................................. 13-30
Functional Description................................................................................................. 13-31
Basic Architecture.................................................................................................... 13-32
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Paragraph
Number
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.1.5
13.4.1.6
13.4.1.7
13.4.2
13.4.2.1
13.4.2.2
13.4.2.2.1
13.4.2.2.2
13.4.2.2.3
13.4.2.2.4
13.4.2.2.5
13.4.2.3
13.4.2.4
13.4.3
13.4.3.1
13.4.3.2
13.4.3.3
13.4.3.4
13.4.3.5
13.4.3.6
13.4.3.7
13.4.3.7.1
13.4.3.7.2
13.4.3.7.3
13.4.3.7.4
13.4.3.7.5
13.4.3.7.6
13.4.3.8
13.4.3.9
13.4.3.10
13.4.3.11
13.4.3.11.1
13.4.4
13.4.4.1
13.4.4.1.1
13.4.4.1.2
13.4.4.1.3
Title
Page
Number
Address and Address Space Checking ................................................................ 13-32
External Address Latch Enable Signal (LALE) .................................................. 13-32
Data Transfer Acknowledge (TA) ....................................................................... 13-34
Data Buffer Control (LBCTL)............................................................................. 13-35
Atomic Operation ................................................................................................ 13-35
Parity Generation and Checking (LDP)............................................................... 13-35
Bus Monitor ......................................................................................................... 13-36
General-Purpose Chip-Select Machine (GPCM)..................................................... 13-36
Timing Configuration .......................................................................................... 13-37
Chip-Select Assertion Timing ............................................................................. 13-39
Programmable Wait State Configuration......................................................... 13-39
Chip-Select and Write Enable Negation Timing ............................................. 13-40
Relaxed Timing ............................................................................................... 13-40
Output Enable (LOE) Timing.......................................................................... 13-42
Extended Hold Time on Read Accesses .......................................................... 13-43
External Access Termination (LGTA) ................................................................. 13-45
Boot Chip-Select Operation................................................................................. 13-45
SDRAM Machine .................................................................................................... 13-46
Supported SDRAM Configurations..................................................................... 13-46
SDRAM Power-On Initialization ........................................................................ 13-47
Intel PC133 and JEDEC-Standard SDRAM Interface Commands ..................... 13-48
Page Hit Checking ............................................................................................... 13-49
Page Management................................................................................................ 13-49
SDRAM Address Multiplexing ........................................................................... 13-49
SDRAM Device-Specific Parameters.................................................................. 13-50
Precharge-to-Activate Interval......................................................................... 13-51
Activate-to-Read/Write Interval ...................................................................... 13-51
Column Address to First Data Out—CAS Latency......................................... 13-52
Last Data In to Precharge—Write Recovery ................................................... 13-52
Refresh Recovery Interval (RFRC) ................................................................. 13-53
External Address and Command Buffers (BUFCMD).................................... 13-53
SDRAM Interface Timing ................................................................................... 13-54
SDRAM Read/Write Transactions....................................................................... 13-56
SDRAM MODE-SET Command Timing............................................................ 13-56
SDRAM Refresh.................................................................................................. 13-56
SDRAM Refresh Timing ................................................................................. 13-57
User-Programmable Machines (UPMs)................................................................... 13-57
UPM Requests ..................................................................................................... 13-58
Memory Access Requests................................................................................ 13-59
UPM Refresh Timer Requests ......................................................................... 13-60
Software Requests—RUN Command ............................................................. 13-60
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Contents
Paragraph
Number
13.4.4.1.4
13.4.4.2
13.4.4.2.1
13.4.4.2.2
13.4.4.3
13.4.4.4
13.4.4.4.1
13.4.4.4.2
13.4.4.4.3
13.4.4.4.4
13.4.4.4.5
13.4.4.4.6
13.4.4.4.7
13.4.4.4.8
13.4.4.4.9
13.4.4.4.10
13.4.4.5
13.4.4.6
13.4.4.7
13.5
13.5.1
13.5.1.1
13.5.1.2
13.5.1.3
13.5.1.4
13.5.2
13.5.2.1
13.5.2.2
13.5.2.3
13.5.2.4
13.5.3
13.5.4
13.5.4.1
13.5.4.2
13.5.4.3
13.5.4.3.1
13.5.4.3.2
13.5.4.3.3
13.5.4.3.4
13.5.4.3.5
13.5.4.3.6
Page
Number
Title
Exception Requests.......................................................................................... 13-61
Programming the UPMs ...................................................................................... 13-61
UPM Programming Example (Two Sequential Writes to the RAM Array).... 13-62
UPM Programming Example (Two Sequential Reads from the RAM Array) 13-62
UPM Signal Timing............................................................................................. 13-63
RAM Array .......................................................................................................... 13-63
RAM Words..................................................................................................... 13-64
Chip-Select Signal Timing (CSTn) ................................................................. 13-66
Byte Select Signal Timing (BSTn) .................................................................. 13-67
General-Purpose Signals (GnTn, GOn)........................................................... 13-68
Loop Control (LOOP) ..................................................................................... 13-68
Repeat Execution of Current RAM Word (REDO) ......................................... 13-68
Address Multiplexing (AMX) ......................................................................... 13-69
Data Valid and Data Sample Control (UTA) ................................................... 13-70
LGPL[0:5] Signal Negation (LAST) ............................................................... 13-70
Wait Mechanism (WAEN) ............................................................................... 13-70
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 13-71
Extended Hold Time on Read Accesses .............................................................. 13-72
Memory System Interface Example Using UPM ................................................ 13-72
Initialization/Application Information ......................................................................... 13-78
Interfacing to Peripherals......................................................................................... 13-78
Multiplexed Address/Data Bus and Non-Multiplexed Address Signals ............. 13-78
Peripheral Hierarchy on the Local Bus................................................................ 13-79
Peripheral Hierarchy on the Local Bus for Very High Bus Speeds..................... 13-79
GPCM Timings.................................................................................................... 13-80
Bus Turnaround ....................................................................................................... 13-81
Address Phase After Previous Read .................................................................... 13-81
Read Data Phase After Address Phase ................................................................ 13-81
Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 13-82
UPM Cycles with Additional Address Phases..................................................... 13-82
Interface to Different Port-Size Devices.................................................................. 13-82
Interfacing to SDRAM............................................................................................. 13-84
Basic SDRAM Capabilities of the Local Bus...................................................... 13-84
Maximum Amount of SDRAM Supported.......................................................... 13-85
SDRAM Machine Limitations............................................................................. 13-86
Analysis of Maximum Row Number Due to Bank Select Multiplexing......... 13-86
Bank Select Signals ......................................................................................... 13-86
128-Mbyte SDRAM ........................................................................................ 13-87
256-Mbyte SDRAM ........................................................................................ 13-89
512-Mbyte SDRAM ........................................................................................ 13-89
Power-Down Mode.......................................................................................... 13-90
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Contents
Paragraph
Number
13.5.4.3.7
13.5.4.3.8
13.5.4.4
13.5.5
13.5.6
13.5.6.1
13.5.6.1.1
13.5.6.1.2
13.5.6.1.3
13.5.6.1.4
13.5.6.2
13.5.6.2.1
13.5.6.2.2
13.5.6.2.3
Title
Page
Number
Self-Refresh ..................................................................................................... 13-91
SDRAM Timing .............................................................................................. 13-92
Parity Support for SDRAM ................................................................................. 13-94
Interfacing to ZBT SRAM....................................................................................... 13-95
Interfacing to DSP Host Ports.................................................................................. 13-97
Interfacing to MSC8101 HDI16 .......................................................................... 13-97
HDI16 Peripherals ........................................................................................... 13-97
Physical Interconnections ................................................................................ 13-98
Supporting Burst Transfers............................................................................ 13-100
Host 60x Bus: HDI16 Peripheral Interface Hardware Timings..................... 13-100
Interfacing to MSC8102 DSI............................................................................. 13-101
DSI in Asynchronous SRAM-Like Mode ..................................................... 13-101
DSI in Synchronous Mode ............................................................................ 13-104
Broadcast Accesses........................................................................................ 13-110
Chapter 14
Enhanced Three-Speed Ethernet Controllers
14.1
14.2
14.3
14.4
14.4.1
14.5
14.5.1
14.5.2
14.5.3
14.5.3.1
14.5.3.1.1
14.5.3.1.2
14.5.3.1.3
14.5.3.1.4
14.5.3.1.5
14.5.3.1.6
14.5.3.1.7
14.5.3.1.8
14.5.3.1.9
14.5.3.2
14.5.3.2.1
14.5.3.2.2
Overview........................................................................................................................ 14-1
Features .......................................................................................................................... 14-1
Modes of Operation ....................................................................................................... 14-4
External Signals Description ......................................................................................... 14-6
Detailed Signal Descriptions ..................................................................................... 14-8
Memory Map/Register Definition ............................................................................... 14-11
Top-Level Module Memory Map ............................................................................ 14-12
Detailed Memory Map............................................................................................. 14-12
Memory-Mapped Register Descriptions.................................................................. 14-21
eTSEC General Control and Status Registers...................................................... 14-21
Controller ID Register (TSEC_ID).................................................................. 14-21
Controller ID Register (TSEC_ID2)................................................................ 14-22
Interrupt Event Register (IEVENT) ................................................................ 14-23
Interrupt Mask Register (IMASK) .................................................................. 14-27
Error Disabled Register (EDIS)....................................................................... 14-29
Ethernet Control Register (ECNTRL) ............................................................. 14-31
Pause Time Value Register (PTV) ................................................................... 14-33
DMA Control Register (DMACTRL) ............................................................. 14-34
TBI Physical Address Register (TBIPA) ......................................................... 14-35
Receive and Transmit FIFO Control and Status Registers .................................. 14-36
FIFO Receive Alarm Start Threshold Register (FIFO_RX_ALARM) ........... 14-37
FIFO Receive Alarm Shut-off Threshold Register
(FIFO_RX_ALARM_SHUTOFF) .............................................................. 14-37
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Paragraph
Number
14.5.3.2.3
14.5.3.2.4
14.5.3.2.5
14.5.3.3
14.5.3.3.1
14.5.3.3.2
14.5.3.3.3
14.5.3.3.4
14.5.3.3.5
14.5.3.3.6
14.5.3.3.7
14.5.3.3.8
14.5.3.3.9
14.5.3.3.10
14.5.3.3.11
14.5.3.4
14.5.3.4.1
14.5.3.4.2
14.5.3.4.3
14.5.3.4.4
14.5.3.4.5
14.5.3.4.6
14.5.3.4.7
14.5.3.4.8
14.5.3.4.9
14.5.3.4.10
14.5.3.4.11
14.5.3.4.12
14.5.3.4.13
14.5.3.5
14.5.3.5.1
14.5.3.5.2
14.5.3.5.3
14.5.3.5.4
14.5.3.5.5
14.5.3.6
14.5.3.6.1
14.5.3.6.2
14.5.3.6.3
14.5.3.6.4
14.5.3.6.5
Page
Number
Title
FIFO Transmit Threshold Register (FIFO_TX_THR) .................................... 14-38
FIFO Transmit Starve Register (FIFO_TX_STARVE) ................................... 14-38
FIFO Transmit Starve Shutoff Register (FIFO_TX_STARVE_SHUTOFF)... 14-39
eTSEC Transmit Control and Status Registers.................................................... 14-40
Transmit Control Register (TCTRL) ............................................................... 14-40
Transmit Status Register (TSTAT)................................................................... 14-41
Default VLAN Control Word Register (DFVLAN) ........................................ 14-43
Transmit Interrupt Coalescing Register (TXIC).............................................. 14-44
Transmit Queue Control Register (TQUEUE) ................................................ 14-45
TxBD Ring 0–3 Weighting Register (TR03WT)............................................. 14-46
TxBD Ring 4–7 Weighting Register (TR47WT)............................................. 14-47
Transmit Data Buffer Pointer High Register (TBDBPH)................................ 14-47
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...................... 14-48
Transmit Descriptor Base Address High Register (TBASEH)........................ 14-48
Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ............... 14-49
eTSEC Receive Control and Status Registers ..................................................... 14-50
Receive Control Register (RCTRL) ................................................................ 14-50
Receive Status Register (RSTAT).................................................................... 14-52
Receive Interrupt Coalescing Register (RXIC) ............................................... 14-54
Receive Queue Control Register (RQUEUE) ................................................. 14-55
Receive Bit Field Extract Control Register (RBIFX)...................................... 14-56
Receive Queue Filer Table Address Register (RQFAR) ................................. 14-58
Receive Queue Filer Table Control Register (RQFCR) .................................. 14-58
Receive Queue Filer Table Property Register (RQFPR) ................................. 14-60
Maximum Receive Buffer Length Register (MRBLR) ................................... 14-63
Receive Data Buffer Pointer High Register (RBDBPH) ................................. 14-63
Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7) ....................... 14-64
Receive Descriptor Base Address High Register (RBASEH)......................... 14-64
Receive Descriptor Base Address Registers (RBASE0–RBASE7) ................ 14-65
MAC Functionality.............................................................................................. 14-66
Configuring the MAC ..................................................................................... 14-66
Controlling CSMA/CD.................................................................................... 14-66
Handling Packet Collisions ............................................................................ 14-66
Controlling Packet Flow.................................................................................. 14-67
Controlling PHY Links.................................................................................... 14-68
MAC Registers .................................................................................................... 14-68
MAC Configuration 1 Register (MACCFG1)................................................. 14-68
MAC Configuration 2 Register (MACCFG2)................................................. 14-70
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 14-72
Half-Duplex Register (HAFDUP) ................................................................... 14-73
Maximum Frame Length Register (MAXFRM) ............................................. 14-74
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Paragraph
Number
14.5.3.6.6
14.5.3.6.7
14.5.3.6.8
14.5.3.6.9
14.5.3.6.10
14.5.3.6.11
14.5.3.6.12
14.5.3.6.13
14.5.3.6.14
14.5.3.6.15
14.5.3.6.16
14.5.3.7
14.5.3.7.1
14.5.3.7.2
14.5.3.7.3
14.5.3.7.4
14.5.3.7.5
14.5.3.7.6
14.5.3.7.7
14.5.3.7.8
14.5.3.7.9
14.5.3.7.10
14.5.3.7.11
14.5.3.7.12
14.5.3.7.13
14.5.3.7.14
14.5.3.7.15
14.5.3.7.16
14.5.3.7.17
14.5.3.7.18
14.5.3.7.19
14.5.3.7.20
14.5.3.7.21
14.5.3.7.22
14.5.3.7.23
14.5.3.7.24
14.5.3.7.25
14.5.3.7.26
Title
Page
Number
MII Management Configuration Register (MIIMCFG) .................................. 14-74
MII Management Command Register (MIIMCOM)....................................... 14-75
MII Management Address Register (MIIMADD)........................................... 14-76
MII Management Control Register (MIIMCON)............................................ 14-76
MII Management Status Register (MIIMSTAT) ............................................. 14-77
MII Management Indicator Register (MIIMIND)........................................... 14-77
Interface Status Register (IFSTAT).................................................................. 14-78
MAC Station Address Part 1 Register (MACSTNADDR1) ........................... 14-78
MAC Station Address Part 2 Register (MACSTNADDR2) ........................... 14-79
MAC Exact Match Address 1–15 Part 1 Registers
(MAC01ADDR1–MAC15ADDR1)............................................................ 14-80
MAC Exact Match Address 1–15 Part 2 Registers
(MAC01ADDR2–MAC15ADDR2)............................................................ 14-80
MIB Registers...................................................................................................... 14-81
Transmit and Receive 64-Byte Frame Counter (TR64) .................................. 14-81
Transmit and Receive 65- to 127-Byte Frame Counter (TR127) .................... 14-82
Transmit and Receive 128- to 255-Byte Frame Counter (TR255) .................. 14-82
Transmit and Receive 256- to 511-Byte Frame Counter (TR511) .................. 14-83
Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) ................. 14-83
Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)........... 14-84
Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter
(TRMGV) .................................................................................................... 14-84
Receive Byte Counter (RBYT)........................................................................ 14-85
Receive Packet Counter (RPKT) ..................................................................... 14-85
Receive FCS Error Counter (RFCS) ............................................................... 14-86
Receive Multicast Packet Counter (RMCA) ................................................... 14-86
Receive Broadcast Packet Counter (RBCA) ................................................... 14-87
Receive Control Frame Packet Counter (RXCF) ............................................ 14-87
Receive Pause Frame Packet Counter (RXPF)................................................ 14-88
Receive Unknown Opcode Packet Counter (RXUO)...................................... 14-88
Receive Alignment Error Counter (RALN) .................................................... 14-89
Receive Frame Length Error Counter (RFLR)................................................ 14-89
Receive Code Error Counter (RCDE) ............................................................. 14-90
Receive Carrier Sense Error Counter (RCSE)................................................. 14-90
Receive Undersize Packet Counter (RUND)................................................... 14-91
Receive Oversize Packet Counter (ROVR)..................................................... 14-91
Receive Fragments Counter (RFRG) .............................................................. 14-92
Receive Jabber Counter (RJBR)...................................................................... 14-92
Receive Dropped Packet Counter (RDRP)...................................................... 14-93
Transmit Byte Counter (TBYT) ...................................................................... 14-93
Transmit Packet Counter (TPKT).................................................................... 14-94
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Paragraph
Number
14.5.3.7.27
14.5.3.7.28
14.5.3.7.29
14.5.3.7.30
14.5.3.7.31
14.5.3.7.32
14.5.3.7.33
14.5.3.7.34
14.5.3.7.35
14.5.3.7.36
14.5.3.7.37
14.5.3.7.38
14.5.3.7.39
14.5.3.7.40
14.5.3.7.41
14.5.3.7.42
14.5.3.7.43
14.5.3.7.44
14.5.3.7.45
14.5.3.7.46
14.5.3.7.47
14.5.3.7.48
14.5.3.8
14.5.3.8.1
14.5.3.8.2
14.5.3.9
14.5.3.9.1
14.5.3.10
14.5.3.10.1
14.5.3.10.2
14.5.4
14.5.4.1
14.5.4.1.1
14.5.4.1.2
14.5.4.1.3
14.5.4.2
14.5.4.2.1
14.5.4.2.2
14.5.4.3
14.5.4.3.1
14.5.4.3.2
Page
Number
Title
Transmit Multicast Packet Counter (TMCA) .................................................. 14-94
Transmit Broadcast Packet Counter (TBCA) .................................................. 14-95
Transmit Pause Control Frame Counter (TXPF)............................................. 14-95
Transmit Deferral Packet Counter (TDFR) ..................................................... 14-96
Transmit Excessive Deferral Packet Counter (TEDF) .................................... 14-96
Transmit Single Collision Packet Counter (TSCL) ......................................... 14-97
Transmit Multiple Collision Packet Counter (TMCL) .................................... 14-97
Transmit Late Collision Packet Counter (TLCL) ............................................ 14-98
Transmit Excessive Collision Packet Counter (TXCL)................................... 14-98
Transmit Total Collision Counter (TNCL) ...................................................... 14-99
Transmit Drop Frame Counter (TDRP)........................................................... 14-99
Transmit Jabber Frame Counter (TJBR) ....................................................... 14-100
Transmit FCS Error Counter (TFCS) ............................................................ 14-100
Transmit Control Frame Counter (TXCF)..................................................... 14-101
Transmit Oversize Frame Counter (TOVR) .................................................. 14-101
Transmit Undersize Frame Counter (TUND)................................................ 14-102
Transmit Fragment Counter (TFRG)............................................................. 14-102
Carry Register 1 (CAR1) ............................................................................... 14-103
Carry Register 2 (CAR2) ............................................................................... 14-104
Carry Mask Register 1 (CAM1) .................................................................... 14-105
Carry Mask Register 2 (CAM2) .................................................................... 14-106
Receive Filer Rejected Packet Counter (RREJ) ............................................ 14-108
Hash Function Registers .................................................................................... 14-108
Individual/Group Address Registers 0–7 (IGADDRn) ................................. 14-108
Group Address Registers 0–7 (GADDRn) .................................................... 14-109
FIFO Registers................................................................................................... 14-110
FIFO Configuration Register (FIFOCFG)..................................................... 14-110
DMA Attribute Registers....................................................................................14-111
Attribute Register (ATTR)..............................................................................14-111
Attribute Extract Length and Extract Index Register (ATTRELI) ............... 14-112
Ten-Bit Interface (TBI) .......................................................................................... 14-113
TBI Transmit Process ........................................................................................ 14-113
Packet Encapsulation..................................................................................... 14-113
8B10B Encoding............................................................................................ 14-114
Preamble Shortening...................................................................................... 14-114
TBI Receive Process.......................................................................................... 14-114
Synchronization ............................................................................................. 14-114
Auto-Negotiation for 1000BASE-X.............................................................. 14-114
TBI MII Set Register Descriptions .................................................................... 14-114
Control Register (CR).................................................................................... 14-115
Status Register (SR)....................................................................................... 14-117
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Paragraph
Number
14.5.4.3.3
14.5.4.3.4
14.5.4.3.5
14.5.4.3.6
14.5.4.3.7
14.5.4.3.8
14.5.4.3.9
14.5.4.3.10
14.6
14.6.1
14.6.1.1
14.6.1.2
14.6.1.3
14.6.1.4
14.6.1.5
14.6.1.6
14.6.1.7
14.6.2
14.6.2.1
14.6.2.2
14.6.2.3
14.6.2.4
14.6.2.5
14.6.2.6
14.6.2.7
14.6.3
14.6.3.1
14.6.3.1.1
14.6.3.1.2
14.6.3.2
14.6.3.3
14.6.3.4
14.6.3.5
14.6.3.5.1
14.6.3.5.2
14.6.3.6
14.6.3.7
14.6.3.7.1
14.6.3.7.2
14.6.3.8
14.6.3.9
Title
Page
Number
AN Advertisement Register (ANA) .............................................................. 14-118
AN Link Partner Base Page Ability Register (ANLPBPA)........................... 14-120
AN Expansion Register (ANEX) .................................................................. 14-121
AN Next Page Transmit Register (ANNPT).................................................. 14-121
AN Link Partner Ability Next Page Register (ANLPANP) .......................... 14-122
Extended Status Register (EXST) ................................................................. 14-123
Jitter Diagnostics Register (JD) ..................................................................... 14-124
TBI Control Register (TBICON)................................................................... 14-125
Functional Description............................................................................................... 14-126
Connecting to Physical Interfaces on Ethernet ...................................................... 14-126
Media-Independent Interface (MII) ................................................................... 14-127
Reduced Media-Independent Interface (RMII) ................................................. 14-127
Gigabit Media-Independent Interface (GMII) ................................................... 14-129
Reduced Gigabit Media-Independent Interface (RGMII) ................................. 14-129
Ten-Bit Interface (TBI)...................................................................................... 14-130
Reduced Ten-Bit Interface (RTBI) .................................................................... 14-131
Ethernet Physical Interfaces Signal Summary................................................... 14-133
Connecting to FIFO Interfaces .............................................................................. 14-135
Flow Control...................................................................................................... 14-137
CRC Appending and Checking ......................................................................... 14-137
8-Bit GMII-Style Packet FIFO Mode................................................................ 14-138
8-Bit Encoded Packet FIFO Mode .................................................................... 14-139
16-Bit GMII-Style Packet FIFO Mode ............................................................. 14-140
16-Bit Encoded Packet FIFO Mode ................................................................. 14-141
FIFO Interface Signal Summary........................................................................ 14-142
Gigabit Ethernet Controller Channel Operation .................................................... 14-143
Initialization Sequence....................................................................................... 14-143
Hardware Controlled Initialization ................................................................ 14-143
User Initialization .......................................................................................... 14-143
Soft Reset and Reconfiguring Procedure........................................................... 14-144
Gigabit Ethernet Frame Transmission ............................................................... 14-145
Gigabit Ethernet Frame Reception .................................................................... 14-146
Ethernet Preamble Customization ..................................................................... 14-147
User-Defined Preamble Transmission ........................................................... 14-148
User-Visible Preamble Reception.................................................................. 14-148
RMON Support.................................................................................................. 14-149
Frame Recognition............................................................................................. 14-149
Destination Address Recognition and Frame Filtering ................................. 14-149
Hash Table Algorithm.................................................................................... 14-151
Magic Packet Mode ........................................................................................... 14-153
Flow Control...................................................................................................... 14-153
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Paragraph
Number
14.6.3.10
14.6.3.10.1
14.6.3.10.2
14.6.3.10.3
14.6.3.11
14.6.3.12
14.6.3.13
14.6.4
14.6.4.1
14.6.4.2
14.6.4.3
14.6.5
14.6.5.1
14.6.5.1.1
14.6.5.1.2
14.6.5.1.3
14.6.5.1.4
14.6.5.1.5
14.6.5.1.6
14.6.5.1.7
14.6.5.1.8
14.6.5.2
14.6.5.2.1
14.6.5.2.2
14.6.6
14.6.6.1
14.6.6.2
14.6.6.3
14.7
14.7.1
14.7.1.1
14.7.1.2
14.7.1.3
14.7.1.4
14.7.1.5
14.7.1.6
14.7.1.7
14.7.1.8
Page
Number
Title
Interrupt Handling ............................................................................................. 14-154
Interrupt Coalescing ...................................................................................... 14-155
Interrupt Coalescing By Frame Count Threshold.......................................... 14-156
Interrupt Coalescing By Timer Threshold ..................................................... 14-156
Inter-Frame Gap Time ....................................................................................... 14-157
Internal and External Loop Back....................................................................... 14-157
Error-Handling Procedure.................................................................................. 14-157
TCP/IP Off-Load ................................................................................................... 14-159
Frame Control Blocks........................................................................................ 14-159
Transmit Path Off-Load ..................................................................................... 14-160
Receive Path Off-Load ...................................................................................... 14-162
Quality of Service (QoS) Provision ....................................................................... 14-163
Receive Queue Filer .......................................................................................... 14-163
Filing Rules ................................................................................................... 14-164
Comparing Properties with Bit Masks........................................................... 14-165
Special-Case Rules ........................................................................................ 14-166
Filer Interrupt Events..................................................................................... 14-166
Setting Up the Receive Queue Filer Table .................................................... 14-166
Filer Example—802.1p Priority Filing.......................................................... 14-167
Filer Example—IP Diff-Serv Code Points Filing.......................................... 14-167
Filer Example—TCP and UDP Port Filing .................................................. 14-168
Transmission Scheduling................................................................................... 14-169
Priority-Based Queuing (PBQ)...................................................................... 14-169
Modified Weighted Round-Robin Queuing (MWRR) .................................. 14-170
Buffer Descriptors.................................................................................................. 14-171
Data Buffer Descriptors ..................................................................................... 14-171
Transmit Data Buffer Descriptors (TxBD) ........................................................ 14-172
Receive Buffer Descriptors (RxBD).................................................................. 14-176
Initialization/Application Information ....................................................................... 14-178
Interface Mode Configuration ............................................................................... 14-178
MII Interface Mode............................................................................................ 14-179
GMII Interface Mode......................................................................................... 14-183
TBI Interface Mode .......................................................................................... 14-187
RGMII Interface Mode ...................................................................................... 14-191
RMII Interface Mode ........................................................................................ 14-195
RTBI Interface Mode ........................................................................................ 14-199
8-Bit FIFO Mode ............................................................................................... 14-203
16-Bit FIFO Mode ............................................................................................ 14-206
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Title
Page
Number
Chapter 15
DMA Controller
15.1
15.1.1
15.1.2
15.1.3
15.1.4
15.2
15.2.1
15.2.2
15.3
15.3.1
15.3.1.1
15.3.1.2
15.3.1.3
15.3.1.4
15.3.1.5
15.3.1.5.1
15.3.1.6
15.3.1.7
15.3.1.7.1
15.3.1.8
15.3.1.9
15.3.1.10
15.3.1.11
15.3.1.12
15.3.1.13
15.3.1.14
15.4
15.4.1
15.4.1.1
15.4.1.1.1
15.4.1.1.2
15.4.1.1.3
15.4.1.1.4
15.4.1.2
15.4.1.2.1
15.4.1.2.2
15.4.1.2.3
15.4.1.2.4
Introduction.................................................................................................................... 15-1
Block Diagram........................................................................................................... 15-1
Overview.................................................................................................................... 15-2
Features...................................................................................................................... 15-2
Modes of Operation ................................................................................................... 15-2
External Signal Description ........................................................................................... 15-5
Signal Overview ........................................................................................................ 15-5
Detailed Signal Descriptions ..................................................................................... 15-6
Memory Map/Register Definition ................................................................................. 15-6
DMA Register Descriptions....................................................................................... 15-9
Mode Registers (MRn) ........................................................................................ 15-10
Status Registers (SRn) ......................................................................................... 15-12
Current Link Descriptor Address Registers (CLNDARn and ECLNDARn) ...... 15-13
Source Attributes Registers (SATRn).................................................................. 15-15
Source Address Registers (SARn)....................................................................... 15-17
Source Address Registers for RapidIO Maintenance Reads (SARn).............. 15-18
Destination Attributes Registers (DATRn).......................................................... 15-18
Destination Address Registers (DARn)............................................................... 15-20
Destination Address Registers for RapidIO Maintenance Writes (DARn) ..... 15-21
Byte Count Registers (BCRn) ............................................................................. 15-22
Next Link Descriptor Address Registers (NLNDARn and ENLNDARn) .......... 15-22
Current List Descriptor Address Registers (CLSDARn and ECLSDARn)......... 15-23
Next List Descriptor Address Registers (NLSDARn and ENLSDARn)............. 15-24
Source Stride Registers (SSRn) ........................................................................... 15-25
Destination Stride Registers (DSRn) ................................................................... 15-26
DMA General Status Register (DGSR) ............................................................... 15-27
Functional Description................................................................................................. 15-28
DMA Channel Operation......................................................................................... 15-28
Basic DMA Mode Transfer ................................................................................. 15-29
Basic Direct Mode ........................................................................................... 15-29
Basic Direct Single-Write Start Mode ............................................................. 15-30
Basic Chaining Mode ...................................................................................... 15-30
Basic Chaining Single-Write Start Mode ........................................................ 15-31
Extended DMA Mode Transfer ........................................................................... 15-31
Extended Direct Mode..................................................................................... 15-31
Extended Direct Single-Write Start Mode....................................................... 15-32
Extended Chaining Mode ................................................................................ 15-32
Extended Chaining Single-Write Start Mode .................................................. 15-32
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Paragraph
Number
15.4.1.3
15.4.1.4
15.4.1.4.1
15.4.1.4.2
15.4.1.5
15.4.1.6
15.4.1.7
15.4.1.8
15.4.2
15.4.3
15.4.4
15.4.5
15.5
15.5.1
15.5.1.1
15.5.1.2
15.5.1.3
15.5.1.4
15.5.1.5
Page
Number
Title
External Control Mode Transfer.......................................................................... 15-33
Channel Continue Mode for Cascading Transfer Chains .................................... 15-34
Basic Mode ...................................................................................................... 15-34
Extended Mode................................................................................................ 15-35
Channel Abort...................................................................................................... 15-35
Bandwidth Control............................................................................................... 15-35
Channel State ....................................................................................................... 15-35
Illustration of Stride Size and Stride Distance..................................................... 15-36
DMA Transfer Interfaces ......................................................................................... 15-36
DMA Errors ............................................................................................................. 15-36
DMA Descriptors..................................................................................................... 15-37
Limitations and Restrictions .................................................................................... 15-40
DMA System Considerations ...................................................................................... 15-41
Unusual DMA Scenarios ......................................................................................... 15-43
DMA to e500 Core .............................................................................................. 15-43
DMA to Ethernet ................................................................................................. 15-44
DMA to Configuration, Control, and Status Registers........................................ 15-44
DMA to I2C ......................................................................................................... 15-44
DMA to DUART ................................................................................................. 15-44
Chapter 16
PCI/PCI-X Bus Interface
16.1
16.1.1
16.1.1.1
16.1.1.2
16.1.2
16.1.3
16.1.3.1
16.1.3.1.1
16.1.3.1.2
16.1.3.1.3
16.1.3.2
16.1.3.3
16.1.3.4
16.1.3.5
16.1.3.6
16.2
16.3
16.3.1
Introduction.................................................................................................................... 16-1
Overview.................................................................................................................... 16-2
Outbound Transactions .......................................................................................... 16-3
Inbound Transactions............................................................................................. 16-4
Features...................................................................................................................... 16-4
Modes of Operation ................................................................................................... 16-5
Host/Agent Mode Configuration ........................................................................... 16-5
Host Mode ......................................................................................................... 16-5
Agent Mode ....................................................................................................... 16-5
Agent Configuration Lock Mode ...................................................................... 16-5
PCI/X-64 or Dual PCI-32 Interface Configuration ............................................... 16-6
PCI/X Clocking Configuration .............................................................................. 16-6
PCI/X Arbiter (Internal/External Arbiter) Configuration...................................... 16-6
PCI/X Impedance Configuration ........................................................................... 16-6
PCI/X Debug Configuration .................................................................................. 16-6
External Signal Descriptions ......................................................................................... 16-6
Memory Map/Register Definitions .............................................................................. 16-14
PCI/X Memory-Mapped Registers .......................................................................... 16-14
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Paragraph
Number
16.3.1.1
16.3.1.1.1
16.3.1.1.2
16.3.1.1.3
16.3.1.2
16.3.1.2.1
16.3.1.2.2
16.3.1.2.3
16.3.1.2.4
16.3.1.3
16.3.1.3.1
16.3.1.3.2
16.3.1.3.3
16.3.1.3.4
16.3.1.4
16.3.1.4.1
16.3.1.4.2
16.3.1.4.3
16.3.1.4.4
16.3.1.4.5
16.3.1.4.6
16.3.1.4.7
16.3.1.4.8
16.3.1.4.9
16.3.1.4.10
16.3.2
16.3.2.1
16.3.2.2
16.3.2.3
16.3.2.4
16.3.2.5
16.3.2.6
16.3.2.7
16.3.2.8
16.3.2.9
16.3.2.10
16.3.2.11
16.3.2.12
16.3.2.13
16.3.2.14
Title
Page
Number
PCI/X Configuration Access Registers ............................................................... 16-17
PCI/X Configuration Address Register (CFG_ADDR) .................................. 16-17
PCI Configuration Data Register (CFG_DATA) ............................................. 16-18
PCI/X Interrupt Acknowledge Register (INT_ACK)...................................... 16-19
PCI/X ATMU Outbound Registers...................................................................... 16-19
PCI/X Outbound Translation Address Registers (POTARn) .......................... 16-19
PCI/X Outbound Translation Extended Address Registers (POTEARn)........ 16-20
PCI/X Outbound Window Base Address Registers (POWBARn).................. 16-20
PCI/X Outbound Window Attributes Registers (POWARn)........................... 16-21
PCI/X ATMU Inbound Registers......................................................................... 16-22
PCI/X Inbound Translation Address Registers (PITARn)............................... 16-23
PCI/X Inbound Window Base Address Registers (PIWBARn) ...................... 16-24
PCI/X Inbound Window Base Extended Address Registers
(PIWBEARn) .............................................................................................. 16-24
PCI/X Inbound Window Attributes Registers (PIWARn) ............................... 16-25
PCI/X Error Management Registers.................................................................... 16-26
PCI/X Error Detect Register (ERR_DR)......................................................... 16-27
PCI/X Error Capture Disable Register (ERR_CAP_DR)................................ 16-28
PCI/X Error Enable Register (ERR_EN) ........................................................ 16-29
PCI/X Error Attributes Capture Register (ERR_ATTRIB) ............................. 16-30
PCI/X Error Address Capture Register (ERR_ADDR)................................... 16-31
PCI/X Error Extended Address Capture Register (ERR_EXT_ADDR)......... 16-31
PCI/X Error Data Low Capture Register (ERR_DL) ...................................... 16-32
PCI/X Error Data High Capture Register (ERR_DH)..................................... 16-32
PCI/X Gasket Timer Register (GAS_TIMR) .................................................. 16-32
PCI-X Split Completion Timer Register (PCIX_TIMR)................................. 16-33
PCI/X Configuration Header ................................................................................... 16-33
PCI Vendor ID Register—Offset 0x00 ................................................................ 16-34
PCI Device ID Register—Offset 0x02 ................................................................ 16-35
PCI Bus Command Register—Offset 0x04 ......................................................... 16-35
PCI Bus Status Register—Offset 0x06................................................................ 16-36
PCI Revision ID Register—Offset 0x08 ............................................................. 16-38
PCI Bus Programming Interface Register—Offset 0x09 .................................... 16-38
PCI Subclass Code Register—Offset 0x0A......................................................... 16-39
PCI Bus Base Class Code Register—Offset 0x0B .............................................. 16-39
PCI Bus Cache Line Size Register—Offset 0x0C............................................... 16-39
PCI Bus Latency Timer Register—0x0D ............................................................ 16-40
PCI Base Address Registers ................................................................................ 16-40
PCI Subsystem Vendor ID Register..................................................................... 16-42
PCI Subsystem ID Register ................................................................................. 16-43
PCI Bus Capabilities Pointer Register ................................................................. 16-43
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Paragraph
Number
16.3.2.15
16.3.2.16
16.3.2.17
16.3.2.18
16.3.2.19
16.3.2.20
16.3.2.21
16.3.2.22
16.3.2.23
16.3.2.24
16.4
16.4.1
16.4.1.1
16.4.1.2
16.4.1.3
16.4.1.4
16.4.2
16.4.2.1
16.4.2.2
16.4.2.3
16.4.2.3.1
16.4.2.3.2
16.4.2.3.3
16.4.2.4
16.4.2.5
16.4.2.6
16.4.2.7
16.4.2.7.1
16.4.2.7.2
16.4.2.8
16.4.2.8.1
16.4.2.8.2
16.4.2.9
16.4.2.10
16.4.2.11
16.4.2.11.1
16.4.2.11.2
16.4.2.11.3
16.4.2.11.4
16.4.2.11.5
16.4.2.12
Page
Number
Title
PCI Bus Interrupt Line Register .......................................................................... 16-43
PCI Bus Interrupt Pin Register ............................................................................ 16-44
PCI Bus Minimum Grant Register (MIN_GNT)................................................. 16-44
PCI Bus Maximum Latency Register (MAX_LAT)............................................ 16-45
PCI Bus Function Register (PBFR) ..................................................................... 16-45
PCI Bus Arbiter Configuration Register (PBACR)............................................. 16-46
PCI-X Next Capabilities ID Register—0x60 ...................................................... 16-47
PCI-X Capability Pointer Register—0x61 .......................................................... 16-47
PCI-X Command Register—0x62....................................................................... 16-47
PCI-X Status Register—0x64.............................................................................. 16-48
Functional Description................................................................................................. 16-49
PCI/X Bus Arbitration ............................................................................................. 16-49
PCI Bus Arbiter Operation .................................................................................. 16-50
PCI Bus Parking .................................................................................................. 16-51
Broken Master Lock-Out ..................................................................................... 16-51
Power-Saving Modes and the PCI Arbiter .......................................................... 16-51
PCI Bus Protocol ..................................................................................................... 16-52
Basic Transfer Control......................................................................................... 16-52
PCI Bus Commands............................................................................................. 16-53
Addressing ........................................................................................................... 16-54
Memory Space Addressing.............................................................................. 16-54
I/O Space Addressing ...................................................................................... 16-55
Configuration Space Addressing ..................................................................... 16-55
Device Selection .................................................................................................. 16-55
Byte Alignment.................................................................................................... 16-56
Bus Driving and Turnaround ............................................................................... 16-56
PCI Bus Transactions........................................................................................... 16-56
PCI Read Transactions .................................................................................... 16-56
PCI Write Transactions.................................................................................... 16-58
Transaction Termination ...................................................................................... 16-59
Master-Initiated Termination ........................................................................... 16-59
Target-Initiated Termination ............................................................................ 16-60
Fast Back-to-Back Transactions .......................................................................... 16-62
Dual Address Cycles............................................................................................ 16-62
Configuration Cycles ........................................................................................... 16-64
PCI Configuration Space Header .................................................................... 16-64
Host Accessing the PCI Configuration Space ................................................. 16-66
Agent Accessing the PCI Configuration Space ............................................... 16-67
PCI Type 0 Configuration Translation............................................................. 16-68
Type 1 Configuration Translation.................................................................... 16-69
Other Bus Transactions........................................................................................ 16-69
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Paragraph
Number
16.4.2.12.1
16.4.2.12.2
16.4.2.13
16.4.2.13.1
16.4.2.13.2
16.4.3
16.4.3.1
16.4.3.2
16.4.3.3
16.4.3.4
16.4.3.5
16.4.3.6
16.4.3.6.1
16.4.3.6.2
16.4.3.6.3
16.4.3.7
16.4.3.8
16.4.3.9
16.5
16.5.1
16.5.1.1
16.5.1.2
16.5.1.3
16.5.2
16.5.3
16.5.4
16.5.5
16.5.5.1
Title
Page
Number
Interrupt-Acknowledge Transactions .............................................................. 16-69
Special-Cycle Transactions ............................................................................. 16-70
PCI Error Functions............................................................................................. 16-71
PCI Parity ........................................................................................................ 16-71
Error Reporting................................................................................................ 16-72
PCI-X Bus Protocol ................................................................................................. 16-73
PCI-X Terminology ............................................................................................. 16-74
PCI-X Command Encodings ............................................................................... 16-74
PCI-X Attribute Phase ......................................................................................... 16-75
PCI-X Transactions.............................................................................................. 16-77
PCI-X Wait State and Termination Rules ............................................................ 16-80
PCI-X Split Transactions ..................................................................................... 16-81
Split Response ................................................................................................. 16-82
Completion Address ........................................................................................ 16-83
Completer Attributes ....................................................................................... 16-84
PCI-X Configuration Transactions ...................................................................... 16-85
PCI-X Error Functions......................................................................................... 16-86
Error Reporting.................................................................................................... 16-86
Initialization/Application Information ......................................................................... 16-89
Power-On Reset Configuration Modes.................................................................... 16-89
Host Mode ........................................................................................................... 16-89
Agent Mode ......................................................................................................... 16-90
Agent Configuration Lock Mode......................................................................... 16-90
Extended 64-bit PCI1/X Signal Connections .......................................................... 16-90
Nonposted Writes in PCI-X ..................................................................................... 16-90
PCI-X Outbound Read Transaction Alignment ....................................................... 16-91
Byte Ordering .......................................................................................................... 16-91
Byte Order for Configuration Transactions ......................................................... 16-92
Chapter 17
Serial RapidIO Interface
17.1
17.2
17.3
17.3.1
17.3.2
17.4
17.4.1
17.4.2
17.4.2.1
Overview........................................................................................................................ 17-1
Features .......................................................................................................................... 17-1
Modes of Operation ....................................................................................................... 17-3
RapidIO Port .............................................................................................................. 17-3
Message Unit ............................................................................................................. 17-3
1x/4x LP-Serial Signal Descriptions.............................................................................. 17-3
Serial Rapid I/O Interface Overview ......................................................................... 17-4
Serial Rapid I/O Interface Detailed Signal Descriptions ........................................... 17-4
SD_TX[4:7]/SD_TX[4:7]—Outputs ..................................................................... 17-4
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Number
17.4.2.2
17.5
17.6
17.6.1
17.6.1.1
17.6.1.2
17.6.1.3
17.6.1.4
17.6.1.5
17.6.1.6
17.6.1.7
17.6.1.8
17.6.1.9
17.6.1.10
17.6.1.11
17.6.1.12
17.6.1.13
17.6.1.14
17.6.2
17.6.2.1
17.6.2.2
17.6.2.3
17.6.2.4
17.6.2.5
17.6.2.6
17.6.2.7
17.6.2.8
17.6.2.9
17.6.3
17.6.3.1
17.6.3.2
17.6.3.3
17.6.3.4
17.6.3.5
Page
Number
Title
SD_RX[4:7]/SD_RX[4:7]—Inputs ....................................................................... 17-4
Memory Map/Register Definition ................................................................................. 17-4
RapidIO Endpoint Configuration Register Definitions ............................................... 17-11
RapidIO Architectural Registers.............................................................................. 17-11
Device Identity Capability Register (DIDCAR).................................................. 17-11
Device Information Capability Register (DICAR).............................................. 17-11
Assembly Identity Capability Register (AIDCAR) ............................................. 17-12
Assembly Information Capability Register (AICAR) ......................................... 17-13
Processing Element Features Capability Register (PEFCAR) ............................ 17-13
Source Operations Capability Register (SOCAR)............................................... 17-14
Destination Operations Capability Register (DOCAR)....................................... 17-15
Mailbox Command and Status Register (MCSR) ............................................... 17-17
Port-Write and Doorbell Command and Status Register (PWDCSR)................. 17-18
Processing Element Logical Layer Control Command and Status Register
(PELLCCSR)................................................................................................... 17-19
Local Configuration Space Base Address 1 Command and Status Register
(LCSBA1CSR) ................................................................................................ 17-20
Base Device ID Command and Status Register (BDIDCSR).............................. 17-21
Host Base Device ID Lock Command and Status Register (HBDIDLCSR) ...... 17-21
Component Tag Command and Status Register (CTCSR) .................................. 17-22
RapidIO Extended Features Space, 1x/4x LP-Serial Registers ............................... 17-22
Port Maintenance Block Header 0 Register (PMBH0)........................................ 17-22
Port Link Time-Out Control Command and Status Register (PLTOCCSR) ....... 17-23
Port Response Time-Out Control Command and Status Register
(PRTOCCSR) .................................................................................................. 17-23
General Control Command and Status Register (GCCSR) ................................. 17-24
Link Maintenance Request Command and Status Register (LMREQCSR)........ 17-25
Link Maintenance Response Command and Status Register (LMRESPCSR) ... 17-25
Local ackID Status Command and Status Register (LASCSR) .......................... 17-26
Error and Status Command and Status Register (ESCSR) .................................. 17-27
Control Command and Status Register (CCSR).................................................. 17-28
RapidIO Extended Features Space—Error Reporting Logical Registers................ 17-30
Error Reporting Block Header Register (ERBH) ................................................ 17-30
Logical/Transport Layer Error Detect Command and Status Register
(LTLEDCSR)................................................................................................... 17-31
Logical/Transport Layer Error Enable Command and Status Register
(LTLEECSR) ................................................................................................... 17-33
Logical/Transport Layer Address Capture Command and Status Register
(LTLACCSR) .................................................................................................. 17-34
Logical/Transport Layer Device ID Capture Command and Status Register
(LTLDIDCCSR) .............................................................................................. 17-35
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Contents
Paragraph
Number
17.6.3.6
17.6.4
17.6.4.1
17.6.4.2
17.6.4.3
17.6.4.4
17.6.4.5
17.6.4.6
17.6.4.7
17.6.4.8
17.6.4.9
17.6.5
17.6.5.1
17.6.5.2
17.6.5.3
17.6.5.4
17.6.5.5
17.6.5.6
17.6.5.7
17.6.5.8
17.6.5.9
17.6.5.10
17.6.5.11
17.6.6
17.6.6.1
17.6.6.2
17.6.7
17.6.7.1
17.6.7.2
17.6.7.3
17.6.7.4
17.6.7.5
17.6.7.6
17.6.7.7
17.6.7.8
17.6.7.9
17.7
Title
Page
Number
Logical/Transport Layer Control Capture Command and Status Register
(LTLCCCSR)................................................................................................... 17-36
RapidIO Extended Features Space—Error Reporting Physical Registers............... 17-36
Error Detect Command and Status Register (EDCSR) ....................................... 17-36
Error Rate Enable Command and Status Register (ERECSR) ............................ 17-37
Error Capture Attributes Command and Status Register (ECACSR).................. 17-38
Packet/Control Symbol Error Capture Command and Status Register 0
(PCSECCSR0)................................................................................................. 17-39
Packet Error Capture Command and Status Register 1 (PECCSR1)................... 17-40
Packet Error Capture Command and Status Register 2 (PECCSR2)................... 17-40
Packet Error Capture Command and Status Register 3 (PECCSR3)................... 17-41
Error Rate Command and Status Register (ERCSR)........................................... 17-41
Error Rate Threshold Command and Status Register (ERTCSR) ....................... 17-42
RapidIO Implementation Space Registers............................................................... 17-43
Logical Layer Configuration Register (LLCR) ................................................... 17-43
Error/Port-Write Interrupt Status Register (EPWISR) ........................................ 17-44
Logical Retry Error Threshold Configuration Register (LRETCR).................... 17-44
Physical Retry Error Threshold Configuration Register (PRETCR)................... 17-45
Alternate Device ID Command and Status Register (ADIDCSR) ...................... 17-45
Accept-All Configuration Register (AACR) ....................................................... 17-46
Logical Outbound Packet Time-to-Live Configuration Register (LOPTTLCR) 17-46
Implementation Error Command and Status Register (IECSR) ......................... 17-47
Physical Configuration Register (PCR)............................................................... 17-48
Serial Link Command and Status Register (SLCSR) ......................................... 17-48
Serial Link Error Injection Configuration Register (SLEICR)............................ 17-49
Revision Control Registers ...................................................................................... 17-50
IP Block Revision Register 1 (IPBRR1) ............................................................. 17-50
IP Block Revision Register 2 (IPBRR2) ............................................................. 17-50
RapidIO Implementation Space—ATMU Registers................................................ 17-51
Segmented Outbound Window Description ........................................................ 17-51
RapidIO Outbound Window Translation Address Registers 0–8
(ROWTARn).................................................................................................... 17-53
RapidIO Outbound Window Translation Extended Address Registers 0–8
(ROWTEARn)................................................................................................. 17-54
RapidIO Outbound Window Base Address Registers 1–8 (ROWBARn) ........... 17-55
RapidIO Outbound Window Attributes Registers 0–8 (ROWARn) .................... 17-55
RapidIO Outbound Window Segment 1–3 Registers 1–8 (ROWSnRn) ............. 17-57
RapidIO Inbound Window Translation Address Registers 0–4 (RIWTARn) ..... 17-58
RapidIO Inbound Window Base Address Registers 1–4 (RIWBARn) ............... 17-59
RapidIO Inbound Window Attributes Registers 0–4 (RIWARn) ........................ 17-60
RapidIO Message Unit Registers................................................................................. 17-62
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number
17.7.1
17.7.1.1
17.7.1.2
17.7.1.3
17.7.1.4
17.7.1.5
17.7.1.6
17.7.1.7
17.7.1.8
17.7.1.9
17.7.1.10
17.7.1.11
17.7.2
17.7.2.1
17.7.2.2
17.7.2.3
17.7.2.4
17.7.2.5
17.7.3
17.7.3.1
17.7.3.2
17.7.3.3
17.7.3.4
17.7.3.5
17.7.4
17.7.4.1
17.7.4.2
Page
Number
Title
RapidIO Outbound Message 0 Registers................................................................. 17-62
Outbound Message n Mode Registers (OMnMR)............................................... 17-62
Outbound Message n Status Registers (OMnSR)................................................ 17-64
Extended Outbound Message n Descriptor Queue Dequeue Pointer
Address Registers (EOMnDQDPAR) and Outbound Descriptor Queue
Dequeue Pointer Address Registers (OMnDQDPAR) .................................... 17-65
Extended Outbound Message n Descriptor Queue Enqueue Pointer
Address Registers (EOMnDQEPAR) and Outbound Message n
Descriptor Queue Enqueue Pointer Address Registers (OMnDQEPAR)........ 17-67
Extended Outbound Message n Source Address Registers (EOMnSAR)
and Outbound Message n Source Address Registers (OMnSAR) .................. 17-68
Outbound Message n Destination Port Registers (OMnDPR) ............................ 17-69
Outbound Message n Destination Attributes Registers (OMnDATR) ................ 17-70
Outbound Message n Double-word Count Registers (OMnDCR) ...................... 17-70
Outbound Message n Retry Error Threshold Configuration
Registers (OMnRETCR) ................................................................................. 17-71
Outbound Message n Multicast Group Registers (OMnMGR)........................... 17-72
Outbound Message n Multicast List Registers (OMnMLR) ............................... 17-72
RapidIO Inbound Message Registers ...................................................................... 17-73
Inbound Message n Mode Registers (IMnMR) ................................................... 17-73
Inbound Message n Status Registers (IMnSR) .................................................... 17-75
Extended Inbound Message Frame Queue Dequeue Pointer
Address Registers (EIMnFQDPAR) and Inbound Message Frame
Queue Dequeue Pointer Address Registers (IMnFQDPAR) ........................... 17-76
Extended Inbound Message Frame Queue Enqueue Pointer
Address Registers (EIMnFQEPAR) and Inbound Message Frame
Queue Enqueue Pointer Address Registers (IMnFQEPAR)............................ 17-77
Inbound Message n Maximum Interrupt Report Interval Registers
(IMnMIRIR) .................................................................................................... 17-78
Outbound RapidIO Doorbell Controller Registers .................................................. 17-79
Outbound Doorbell Mode Register (ODMR)...................................................... 17-79
Outbound Doorbell Status Register (ODSR)....................................................... 17-80
Outbound Doorbell Destination Port Register (ODDPR) ................................... 17-80
Outbound Doorbell Destination Attributes Register (ODDATR) ....................... 17-81
Outbound Doorbell Retry Error Threshold Configuration Register
(ODRETCR).................................................................................................... 17-82
Inbound RapidIO Doorbell Controller..................................................................... 17-82
Inbound Doorbell Mode Register (IDMR) .......................................................... 17-82
Inbound Doorbell Status Register (IDSR) ........................................................... 17-84
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Contents
Paragraph
Number
17.7.4.3
17.7.4.4
17.7.4.5
17.7.5
17.7.5.1
17.7.5.2
17.7.5.3
17.8
17.8.1
17.8.2
17.8.3
17.8.4
17.8.4.1
17.8.4.1.1
17.8.4.2
17.8.5
17.8.5.1
17.8.5.2
17.8.6
17.8.6.1
17.8.6.2
17.8.7
17.8.8
17.8.9
17.8.10
17.8.11
17.8.11.1
17.8.11.1.1
17.8.11.1.2
17.8.11.2
17.8.11.2.1
17.8.11.2.2
17.8.12
17.8.12.1
17.8.12.2
Title
Page
Number
Extended Inbound Doorbell Queue Dequeue Pointer Address Register
(EIDQDPAR) and Inbound Doorbell Queue Dequeue Pointer Address
Register (IDQDPAR)....................................................................................... 17-85
Extended Inbound Doorbell Queue Enqueue Pointer Address Register
(EIDQEPAR) and Inbound Doorbell Queue Enqueue Pointer Address
Register (IDQEPAR) ....................................................................................... 17-86
Inbound Doorbell Maximum Interrupt Report Interval Register (IDMIRIR) ..... 17-87
RapidIO Port-Write Registers.................................................................................. 17-88
Inbound Port-Write Mode Register (IPWMR) .................................................... 17-88
Inbound Port-Write Status Register (IPWSR) ..................................................... 17-89
Extended Inbound Port-Write Queue Base Address Register
(EIPWQBAR) and Inbound Port-Write Queue Base Address
Register (IPWQBAR)...................................................................................... 17-89
Functional Description................................................................................................. 17-90
RapidIO Transaction Summary ............................................................................... 17-90
RapidIO Packet Format Summary ........................................................................... 17-92
RapidIO Control Symbol Summary ........................................................................ 17-93
Accessing Configuration Registers via RapidIO Packets........................................ 17-95
Inbound Maintenance Accesses........................................................................... 17-95
Guidelines........................................................................................................ 17-95
Outbound Maintenance Accesses ........................................................................ 17-95
RapidIO Outbound ATMU ...................................................................................... 17-96
Valid Hits to Multiple ATMU Windows.............................................................. 17-96
Window Boundary Crossing Errors..................................................................... 17-97
RapidIO Inbound ATMU ......................................................................................... 17-98
Hits to Multiple ATMU Windows ....................................................................... 17-98
Window Boundary Crossing Errors..................................................................... 17-98
Generating Link-Request/Reset-Device .................................................................. 17-99
Outbound Drain Mode ............................................................................................. 17-99
Input Port Disable Mode........................................................................................ 17-100
Software Assisted Error Recovery Register Support............................................. 17-100
Hot-Swap Support.................................................................................................. 17-101
Method 1............................................................................................................ 17-101
Extraction....................................................................................................... 17-101
Insertion ......................................................................................................... 17-102
Method 2 with RapidIO Port Hot-Swapped ...................................................... 17-102
Extraction....................................................................................................... 17-102
Insertion ......................................................................................................... 17-103
Errors and Error Handling ..................................................................................... 17-103
RapidIO Error Description ................................................................................ 17-103
Physical Layer RapidIO Errors Detected .......................................................... 17-104
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number
17.8.12.3
17.8.12.3.1
17.9
17.9.1
17.9.2
17.9.3
17.9.4
17.9.4.1
17.9.4.1.1
17.9.4.1.2
17.9.4.1.3
17.9.4.1.4
17.9.4.1.5
17.9.4.1.6
17.9.4.1.7
17.9.4.1.8
17.9.4.1.9
17.9.4.2
17.9.4.2.1
17.9.4.2.2
17.9.4.2.3
17.9.4.2.4
17.9.4.2.5
17.9.4.2.6
17.9.4.2.7
17.9.4.2.8
17.9.4.2.9
17.9.4.2.10
17.9.4.2.11
17.9.4.2.12
17.9.4.2.13
17.9.4.2.14
17.9.4.3
17.9.5
17.9.5.1
17.9.5.2
17.9.5.3
17.9.5.4
17.9.5.5
17.9.5.5.1
17.9.5.5.2
Page
Number
Title
Logical Layer Errors and Error Handling.......................................................... 17-106
Logical Layer RapidIO Errors Detected........................................................ 17-107
RapidIO Message Unit............................................................................................... 17-139
Overview................................................................................................................ 17-139
Features.................................................................................................................. 17-140
Outbound Modes of Operation .............................................................................. 17-141
Outbound Message Controller Operation .............................................................. 17-141
Direct Mode Operation ...................................................................................... 17-141
Interrupts........................................................................................................ 17-142
Message Error Response Errors .................................................................... 17-143
Packet Response Time-out Errors ................................................................. 17-143
Retry Error Threshold Exceeded Errors ........................................................ 17-143
Transaction Errors ......................................................................................... 17-143
Error Handling ............................................................................................... 17-144
Disabling and Enabling the Message Controller ........................................... 17-144
Hardware Error Handling .............................................................................. 17-144
Programming Errors ...................................................................................... 17-148
Chaining Mode .................................................................................................. 17-149
Message Controller Initialization .................................................................. 17-150
Chaining Mode Operation ............................................................................. 17-150
Changing Descriptor Queues in Chaining Mode........................................... 17-152
Preventing Queue Overflow in Chaining Mode ............................................ 17-152
Switching Between Direct and Chaining Modes........................................... 17-152
Chaining Mode Descriptor Format................................................................ 17-152
Chaining Mode Controller Interrupts ............................................................ 17-153
Message Error Response Errors .................................................................... 17-154
Packet Response Time-out Errors ................................................................. 17-154
Retry Error Threshold Exceeded Errors ........................................................ 17-154
Transaction Errors ......................................................................................... 17-154
Error Handling ............................................................................................... 17-155
Hardware Error Handling .............................................................................. 17-155
Programming Errors ...................................................................................... 17-156
Message Controller Arbitration ......................................................................... 17-156
Inbound Message Controller Operation................................................................. 17-157
Inbound Message Controller Initialization ........................................................ 17-158
Inbound Controller Operation............................................................................ 17-158
Message Steering ............................................................................................... 17-159
Retry Response Conditions................................................................................ 17-159
Inbound Message Controller Interrupts ............................................................. 17-160
Message Request Time-out Errors................................................................. 17-160
Transaction Errors ......................................................................................... 17-160
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Contents
Paragraph
Number
17.9.5.5.3
17.9.5.5.4
17.9.5.5.5
17.9.5.5.6
17.9.6
17.10
17.10.1
17.10.2
17.10.2.1
17.10.2.1.1
17.10.2.1.2
17.10.2.1.3
17.10.2.1.4
17.10.2.1.5
17.10.2.1.6
17.10.2.1.7
17.10.2.1.8
17.10.2.2
17.10.2.2.1
17.10.2.2.2
17.10.2.2.3
17.10.2.2.4
17.10.2.2.5
17.10.2.2.6
17.10.2.2.7
17.10.2.2.8
17.10.2.2.9
17.10.2.2.10
17.10.2.3
17.10.3
17.10.3.1
17.10.3.2
17.10.3.3
17.10.3.4
17.10.3.5
17.10.3.5.1
17.10.3.6
17.10.3.6.1
17.10.3.7
17.10.3.8
Title
Page
Number
Error Handling ............................................................................................... 17-161
Hardware Error Handling .............................................................................. 17-161
Programming Errors ...................................................................................... 17-166
Disabling and Enabling the Inbound Message Controller............................. 17-167
RapidIO Message Passing Logical Specification Registers .................................. 17-168
RapidIO Doorbell and Port-Write Unit...................................................................... 17-168
Features.................................................................................................................. 17-168
Doorbell Controller................................................................................................ 17-169
Outbound Doorbell Controller........................................................................... 17-169
Interrupts........................................................................................................ 17-170
Error Response Errors ................................................................................... 17-170
Packet Response Time-Out Errors................................................................. 17-171
Retry Error Threshold Exceeded Errors ........................................................ 17-171
Error Handling ............................................................................................... 17-171
Disabling and Enabling the Doorbell Controller ........................................... 17-171
Hardware Error Handling .............................................................................. 17-171
Programming Errors ...................................................................................... 17-174
Inbound Doorbell Controller ............................................................................. 17-175
Inbound Doorbell Controller Initialization.................................................... 17-175
Inbound Doorbell Controller Operation ........................................................ 17-175
Inbound Doorbell Queue Entry Format......................................................... 17-176
Retry Response Conditions ........................................................................... 17-177
Doorbell Controller Interrupts ....................................................................... 17-177
Transaction Errors ......................................................................................... 17-177
Error Handling ............................................................................................... 17-178
Hardware Error Handling .............................................................................. 17-178
Programming Errors ...................................................................................... 17-181
Disabling and Enabling the Doorbell Controller ........................................... 17-181
RapidIO Message Passing Logical Specification Registers .............................. 17-181
Port-Write Controller ............................................................................................. 17-182
Port-Write Controller Initialization ................................................................... 17-182
Port-Write Controller Operation........................................................................ 17-183
Port-Write Controller Interrupt .......................................................................... 17-183
Discarding Port-Writes ...................................................................................... 17-184
Transaction Errors.............................................................................................. 17-184
Error Handling ............................................................................................... 17-184
Hardware Error Handling .................................................................................. 17-184
Programming Errors ...................................................................................... 17-188
Disabling and Enabling the Port-Write Controller ............................................ 17-188
RapidIO Message Passing Logical Specification Registers .............................. 17-188
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Paragraph
Number
Page
Number
Title
Chapter 18
PCI Express Interface Controller
18.1
18.1.1
18.1.1.1
18.1.1.2
18.1.2
18.1.3
18.1.3.1
18.1.3.2
18.2
18.3
18.3.1
18.3.2
18.3.2.1
18.3.2.2
18.3.2.3
18.3.2.4
18.3.2.5
18.3.3
18.3.3.1
18.3.3.2
18.3.3.3
18.3.3.4
18.3.4
18.3.4.1
18.3.4.2
18.3.5
18.3.5.1
18.3.5.1.1
18.3.5.1.2
18.3.5.1.3
18.3.5.1.4
18.3.5.2
18.3.5.2.1
18.3.5.2.2
18.3.5.2.3
18.3.5.2.4
Introduction.................................................................................................................... 18-1
Overview.................................................................................................................... 18-1
Outbound Transactions .......................................................................................... 18-2
Inbound Transactions............................................................................................. 18-3
Features...................................................................................................................... 18-3
Modes of Operation ................................................................................................... 18-4
Root Complex/Endpoint Modes ............................................................................ 18-4
Link Width............................................................................................................. 18-4
External Signal Descriptions ......................................................................................... 18-4
Memory Map/Register Definitions ................................................................................ 18-5
PCI Express Memory Mapped Registers................................................................... 18-5
PCI Express Configuration Access Registers............................................................ 18-9
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) .............. 18-9
PCI Express Configuration Data Register (PEX_CONFIG_DATA)................... 18-10
PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR) 18-11
PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR) 18-11
PCI Express Configuration Register (PEX_CONFIG)........................................ 18-12
PCI Express Power Management Event and Message Registers ............................ 18-13
PCI Express PME and Message Detect Register (PEX_PME_MES_DR) ......... 18-13
PCI Express PME and Message Disable Register (PEX_PME_MES_DISR) .... 18-14
PCI Express PME and Message Interrupt Enable Register
(PEX_PME_MES_IER) .................................................................................. 18-16
PCI Express Power Management Command Register (PEX_PMCR) ................ 18-17
PCI Express IP Block Revision Registers ............................................................... 18-18
IP Block Revision Register 1 (PEX_IP_BLK_REV1)........................................ 18-18
IP Block Revision Register 2 (PEX_IP_BLK_REV2)........................................ 18-19
PCI Express ATMU Registers ................................................................................. 18-19
PCI Express Outbound ATMU Registers ............................................................ 18-19
PCI Express Outbound Translation Address Registers (PEXOTARn) ........... 18-20
PCI Express Outbound Translation Extended Address Registers
(PEXOTEARn)............................................................................................ 18-21
PCI Express Outbound Window Base Address Registers (PEXOWBARn)... 18-21
PCI Express Outbound Window Attributes Registers (PEXOWARn)............ 18-22
PCI Express Inbound ATMU Registers ............................................................... 18-24
EP Inbound ATMU Implementation................................................................ 18-24
RC Inbound ATMU Implementation............................................................... 18-25
PCI Express Inbound Translation Address Registers (PEXITARn)................ 18-25
PCI Express Inbound Window Base Address Registers (PEXIWBARn) ....... 18-26
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Contents
Paragraph
Number
18.3.5.2.5
18.3.5.2.6
18.3.6
18.3.6.1
18.3.6.2
18.3.6.3
18.3.6.4
18.3.6.5
18.3.6.6
18.3.6.7
18.3.6.8
18.3.7
18.3.7.1
18.3.7.1.1
18.3.7.1.2
18.3.7.2
18.3.8
18.3.8.1
18.3.8.1.1
18.3.8.1.2
18.3.8.1.3
18.3.8.1.4
18.3.8.1.5
18.3.8.1.6
18.3.8.1.7
18.3.8.1.8
18.3.8.1.9
18.3.8.1.10
18.3.8.2
18.3.8.2.1
18.3.8.2.2
18.3.8.2.3
18.3.8.2.4
18.3.8.2.5
18.3.8.2.6
18.3.8.2.7
18.3.8.2.8
18.3.8.3
18.3.8.3.1
18.3.8.3.2
Title
Page
Number
PCI Express Inbound Window Base Extended Address Registers
(PEXIWBEARn) ......................................................................................... 18-27
PCI Express Inbound Window Attributes Registers (PEXIWARn) ................ 18-27
PCI Express Error Management Registers .............................................................. 18-29
PCI Express Error Detect Register (PEX_ERR_DR).......................................... 18-29
PCI Express Error Interrupt Enable Register (PEX_ERR_EN) .......................... 18-32
PCI Express Error Disable Register (PEX_ERR_DISR) .................................... 18-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT) ............... 18-35
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)............................ 18-36
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)............................ 18-38
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)............................ 18-39
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)............................ 18-40
PCI Express Configuration Space Access ............................................................... 18-42
RC Configuration Register Access...................................................................... 18-42
PCI Express Configuration Access Register Mechanism................................ 18-42
Outbound ATMU Configuration Mechanism (RC-Only) ............................... 18-42
EP Configuration Register Access....................................................................... 18-43
PCI Compatible Configuration Headers .................................................................. 18-43
Common PCI Compatible Configuration Header Registers................................ 18-44
PCI Express Vendor ID Register—Offset 0x00 .............................................. 18-44
PCI Express Device ID Register—Offset 0x02............................................... 18-44
PCI Express Command Register—Offset 0x04 .............................................. 18-44
PCI Express Status Register—Offset 0x06 ..................................................... 18-46
PCI Express Revision ID Register—Offset 0x08............................................ 18-47
PCI Express Class Code Register—Offset 0x09 ............................................. 18-47
PCI Express Cache Line Size Register—Offset 0x0C .................................... 18-48
PCI Express Latency Timer Register—0x0D.................................................. 18-49
PCI Express Header Type Register—0x0E ..................................................... 18-49
PCI Express BIST Register—0x0F ................................................................. 18-50
Type 0 Configuration Header .............................................................................. 18-50
PCI Express Base Address Registers—0x10–0x27......................................... 18-50
PCI Express Subsystem Vendor ID Register (EP-Mode Only)—0x2C .......... 18-53
PCI Express Subsystem ID Register (EP-Mode Only)—0x2E ....................... 18-53
Capabilities Pointer Register—0x34 ............................................................... 18-54
PCI Express Interrupt Line Register (EP-Mode Only)—0x3C ....................... 18-54
PCI Express Interrupt Pin Register—0x3D..................................................... 18-55
PCI Express Minimum Grant Register (EP-Mode Only)—0x3E ................... 18-55
PCI Express Maximum Latency Register (EP-Mode Only)—0x3F ............... 18-56
Type 1 Configuration Header .............................................................................. 18-56
PCI Express Base Address Register 0—0x10 ................................................. 18-57
PCI Express Primary Bus Number Register—Offset 0x18............................. 18-57
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Paragraph
Number
18.3.8.3.3
18.3.8.3.4
18.3.8.3.5
18.3.8.3.6
18.3.8.3.7
18.3.8.3.8
18.3.8.3.9
18.3.8.3.10
18.3.8.3.11
18.3.8.3.12
18.3.8.3.13
18.3.8.3.14
18.3.8.3.15
18.3.8.3.16
18.3.8.3.17
18.3.8.3.18
18.3.8.3.19
18.3.8.3.20
18.3.9
18.3.9.1
18.3.9.2
18.3.9.3
18.3.9.4
18.3.9.5
18.3.9.6
18.3.9.7
18.3.9.8
18.3.9.9
18.3.9.10
18.3.9.11
18.3.9.12
18.3.9.13
18.3.9.14
18.3.9.15
18.3.9.16
18.3.9.17
18.3.9.18
18.3.9.19
18.3.9.20
18.3.9.21
18.3.9.22
Page
Number
Title
PCI Express Secondary Bus Number Register—Offset 0x19......................... 18-58
PCI Express Subordinate Bus Number Register—Offset 0x1A...................... 18-58
PCI Express Secondary Latency Timer Register—0x1B ................................ 18-59
PCI Express I/O Base Register—0x1C ........................................................... 18-59
PCI Express I/O Limit Register—0x1D.......................................................... 18-59
PCI Express Secondary Status Register—0x1E .............................................. 18-60
PCI Express Memory Base Register—0x20 ................................................... 18-61
PCI Express Memory Limit Register—0x22 .................................................. 18-61
PCI Express Prefetchable Memory Base Register—0x24 .............................. 18-62
PCI Express Prefetchable Memory Limit Register—0x26 ............................. 18-62
PCI Express Prefetchable Base Upper 32 Bits Register—0x28...................... 18-63
PCI Express Prefetchable Limit Upper 32 Bits Register—0x2C .................... 18-63
PCI Express I/O Base Upper 16 Bits Register—0x30 .................................... 18-63
PCI Express I/O Limit Upper 16 Bits Register—0x32 ................................... 18-64
Capabilities Pointer Register—0x34 ............................................................... 18-64
PCI Express Interrupt Line Register—0x3C ................................................... 18-65
PCI Express Interrupt Pin Register—0x3D..................................................... 18-65
PCI Express Bridge Control Register—0x3E ................................................. 18-66
PCI Compatible Device-Specific Configuration Space........................................... 18-67
PCI Express Power Management Capability ID Register—0x44 ....................... 18-68
PCI Express Power Management Capabilities Register—0x46.......................... 18-68
PCI Express Power Management Status and Control Register—0x48 ............... 18-69
PCI Express Power Management Data Register—0x4B..................................... 18-69
PCI Express Capability ID Register—0x4C........................................................ 18-70
PCI Express Capabilities Register—0x4E........................................................... 18-70
PCI Express Device Capabilities Register—0x50............................................... 18-71
PCI Express Device Control Register—0x54...................................................... 18-71
PCI Express Device Status Register—0x56 ........................................................ 18-72
PCI Express Link Capabilities Register—0x58 .................................................. 18-73
PCI Express Link Control Register—0x5C......................................................... 18-73
PCI Express Link Status Register—0x5E ........................................................... 18-74
PCI Express Slot Capabilities Register—0x60.................................................... 18-75
PCI Express Slot Control Register—0x64 .......................................................... 18-75
PCI Express Slot Status Register—0x66 ............................................................. 18-76
PCI Express Root Control Register (RC Mode Only)—0x68............................. 18-77
PCI Express Root Status Register (RC Mode Only)—0x6C............................... 18-77
PCI Express MSI Message Capability ID Register (EP Mode Only)—0x70 ..... 18-78
PCI Express MSI Message Control Register (EP Mode Only)—0x72 ............... 18-78
PCI Express MSI Message Address Register (EP Mode Only)—0x74 .............. 18-79
PCI Express MSI Message Upper Address Register (EP Mode Only)—0x78 ... 18-79
PCI Express MSI Message Data Register (EP Mode Only)—0x7C ................... 18-79
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Contents
Paragraph
Number
18.3.10
18.3.10.1
18.3.10.2
18.3.10.3
18.3.10.4
18.3.10.5
18.3.10.6
18.3.10.7
18.3.10.8
18.3.10.9
18.3.10.10
18.3.10.11
18.3.10.12
18.3.10.13
18.3.10.14
18.3.10.15
18.3.10.16
18.3.10.17
18.3.10.18
18.3.10.19
18.3.10.20
18.4
18.4.1
18.4.1.1
18.4.1.2
18.4.1.2.1
18.4.1.3
18.4.1.4
18.4.1.5
18.4.1.6
18.4.1.7
18.4.1.8
18.4.1.9
18.4.1.9.1
18.4.1.9.2
18.4.2
18.4.2.1
18.4.2.1.1
18.4.2.1.2
18.4.2.1.3
18.4.2.1.4
Title
Page
Number
PCI Express Extended Configuration Space ........................................................... 18-80
PCI Express Advanced Error Reporting Capability ID Register—0x100........... 18-81
PCI Express Uncorrectable Error Status Register—0x104 ................................. 18-81
PCI Express Uncorrectable Error Mask Register—0x108 .................................. 18-82
PCI Express Uncorrectable Error Severity Register—0x10C ............................. 18-83
PCI Express Correctable Error Status Register—0x110 ..................................... 18-84
PCI Express Correctable Error Mask Register—0x114 ...................................... 18-84
PCI Express Advanced Error Capabilities and Control Register—0x118 .......... 18-85
PCI Express Header Log Register—0x11C–0x12B ............................................ 18-86
PCI Express Root Error Command Register—0x12C......................................... 18-87
PCI Express Root Error Status Register—0x130 ................................................ 18-87
PCI Express Correctable Error Source ID Register—0x134............................... 18-88
PCI Express Error Source ID Register—0x136 .................................................. 18-88
LTSSM State Status Register—0x404................................................................. 18-89
PCI Express Controller Core Clock Ratio Register—0x440............................... 18-90
PCI Express Power Management Timer Register—0x450 ................................. 18-91
PCI Express PME Time-Out Register (EP-Mode Only)—0x454 ....................... 18-92
PCI Express Subsystem Vendor ID Update Register (EP Mode Only)—0x478. 18-93
Configuration Ready Register—0x4B0............................................................... 18-93
PME_To_Ack Timeout Register (RC-Mode Only)—0x590 ............................... 18-94
Secondary Status Interrupt Mask Register (RC-Mode Only)—0x5A0 ............... 18-94
Functional Description................................................................................................. 18-96
Architecture ............................................................................................................. 18-97
PCI Express Transactions .................................................................................... 18-97
Byte Ordering ...................................................................................................... 18-98
Byte Order for Configuration Transactions ..................................................... 18-99
Lane Reversal ...................................................................................................... 18-99
Transaction Ordering Rules ............................................................................... 18-100
Memory Space Addressing................................................................................ 18-100
I/O Space Addressing ........................................................................................ 18-101
Configuration Space Addressing ....................................................................... 18-101
Serialization of Configuration and I/O Writes................................................... 18-101
Messages............................................................................................................ 18-101
Outbound ATMU Message Generation ......................................................... 18-101
Inbound Messages ......................................................................................... 18-103
Interrupts............................................................................................................... 18-105
EP Interrupt Generation..................................................................................... 18-105
Hardware INTx Message Generation ............................................................ 18-105
Hardware MSI Generation............................................................................. 18-105
Software INTx Message Generation ............................................................. 18-106
Software MSI Generation.............................................................................. 18-106
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Paragraph
Number
18.4.2.2
18.4.2.2.1
18.4.2.2.2
18.4.3
18.4.4
18.4.4.1
18.4.5
18.5
18.5.1
Page
Number
Title
RC Handling of INTx Message and MSI Interrupt ........................................... 18-106
INTx Message Handling................................................................................ 18-106
MSI Handling ................................................................................................ 18-106
Initial Credit Advertisement .................................................................................. 18-106
Power Management ............................................................................................... 18-107
L2/L3 Ready Link State..................................................................................... 18-108
Hot Reset................................................................................................................ 18-108
Initialization/Application Information ....................................................................... 18-108
Boot Mode and Inbound Configuration Transactions ........................................... 18-108
Chapter 19
Security Engine (SEC) 2.1
19.1
19.1.1
19.1.2
19.1.2.1
19.1.2.1.1
19.1.2.1.2
19.1.2.2
19.1.2.3
19.1.2.4
19.1.2.5
19.1.2.6
19.1.2.7
19.1.3
19.1.4
19.1.4.1
19.1.4.2
19.2
19.3
19.3.1
19.3.2
19.3.2.1
19.3.2.2
19.3.3
19.3.4
19.3.5
19.4
19.4.1
19.4.1.1
SEC 2.1 Architecture Overview .................................................................................... 19-2
Descriptors ................................................................................................................. 19-4
Execution Units (EUs) ............................................................................................... 19-5
Public Key Execution Unit (PKEU) ...................................................................... 19-5
Elliptic Curve Operations .................................................................................. 19-5
Modular Exponentiation Operations ................................................................. 19-6
Data Encryption Standard Execution Unit (DEU)................................................. 19-6
ARC Four Execution Unit (AFEU) ....................................................................... 19-6
Message Digest Execution Unit (MDEU) ............................................................. 19-7
Random Number Generator (RNG)....................................................................... 19-7
Advanced Encryption Standard Execution Unit (AESU)...................................... 19-7
Kasumi Execution Unit (KEU).............................................................................. 19-8
Crypto-Channels ........................................................................................................ 19-8
Controller ................................................................................................................... 19-9
Channel-Controlled Access ................................................................................. 19-10
Host-Controlled Access ....................................................................................... 19-10
Configuration of Internal Memory Space .................................................................... 19-10
Descriptor Overview.................................................................................................... 19-16
Descriptor Structure ................................................................................................. 19-16
Descriptor Format: Header Dword .......................................................................... 19-17
Selecting Execution Units—EU_SEL0 and EU_SEL1 ....................................... 19-18
Selecting Descriptor Type—DESC_TYPE ......................................................... 19-19
Descriptor Format: Pointer Dwords......................................................................... 19-20
Link Table Format ................................................................................................... 19-21
Descriptor Types ...................................................................................................... 19-24
Execution Units............................................................................................................ 19-25
Public Key Execution Unit (PKEU) ........................................................................ 19-26
PKEU Mode Register (PKEUMR)...................................................................... 19-26
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Paragraph
Number
19.4.1.2
19.4.1.3
19.4.1.4
19.4.1.5
19.4.1.6
19.4.1.7
19.4.1.8
19.4.1.9
19.4.1.10
19.4.1.10.1
19.4.1.10.2
19.4.1.10.3
19.4.1.10.4
19.4.2
19.4.2.1
19.4.2.2
19.4.2.3
19.4.2.4
19.4.2.5
19.4.2.6
19.4.2.7
19.4.2.8
19.4.2.9
19.4.2.10
19.4.2.11
19.4.3
19.4.3.1
19.4.3.2
19.4.3.2.1
19.4.3.3
19.4.3.4
19.4.3.5
19.4.3.6
19.4.3.7
19.4.3.8
19.4.3.9
19.4.3.10
19.4.3.10.1
19.4.3.10.2
19.4.3.11
19.4.3.12
Title
Page
Number
PKEU Key Size Register (PKEUKSR) ............................................................... 19-27
PKEU AB Size Register (PKEUABS) ................................................................ 19-28
PKEU Data Size Register (PKEUDSR) .............................................................. 19-28
PKEU Reset Control Register (PKEURCR) ....................................................... 19-29
PKEU Status Register (PKEUSR)....................................................................... 19-29
PKEU Interrupt Status Register (PKEUISR)....................................................... 19-31
PKEU Interrupt Control Register (PKEUICR).................................................... 19-32
PKEU EU Go Register (PKEUEUG) .................................................................. 19-33
PKEU Parameter Memories ................................................................................ 19-33
PKEU Parameter Memory A ........................................................................... 19-33
PKEU Parameter Memory B ........................................................................... 19-33
PKEU Parameter Memory E ........................................................................... 19-33
PKEU Parameter Memory N ........................................................................... 19-33
Data Encryption Standard Execution Unit (DEU)................................................... 19-34
DEU Mode Register (DEUMR) .......................................................................... 19-34
DEU Key Size Register (DEUKSR).................................................................... 19-35
DEU Data Size Register (DEUDSR)................................................................... 19-35
DEU Reset Control Register (DEURCR)............................................................ 19-36
DEU Status Register (DEUSR) ........................................................................... 19-36
DEU Interrupt Status Register (DEUISR) ........................................................... 19-37
DEU Interrupt Control Register (DEUICR) ........................................................ 19-39
DEU EU Go Register (DEUEUG) ...................................................................... 19-41
DEU IV Register (DEUIV) ................................................................................. 19-41
DEU Key Registers 1–3 (DEUKn)...................................................................... 19-41
DEU FIFOs .......................................................................................................... 19-41
ARC Four Execution Unit (AFEU) ......................................................................... 19-41
AFEU Mode Register (AFEUMR)...................................................................... 19-42
Host-Provided Context via Prevent Permute....................................................... 19-42
Dump Context.................................................................................................. 19-42
AFEU Key Size Register (AFEUKSR) ............................................................... 19-43
AFEU Context/Data Size Register (AFEUDSR) ................................................ 19-44
AFEU Reset Control Register (AFEURCR) ....................................................... 19-44
AFEU Status Register (AFEUSR)....................................................................... 19-45
AFEU Interrupt Status Register (AFEUISR)....................................................... 19-46
AFEU Interrupt Control Register (AFEUICR).................................................... 19-48
AFEU EU Go Register (AFEUEUG) .................................................................. 19-49
AFEU Context ..................................................................................................... 19-49
AFEU Context Memory .................................................................................. 19-49
AFEU Context Memory Pointer Register ....................................................... 19-50
AFEU Key Registers 0–1 (AFEUKn) ................................................................. 19-50
AFEU FIFOs........................................................................................................ 19-50
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Paragraph
Number
19.4.4
19.4.4.1
19.4.4.2
19.4.4.3
19.4.4.4
19.4.4.5
19.4.4.6
19.4.4.7
19.4.4.8
19.4.4.9
19.4.4.10
19.4.4.11
19.4.4.12
19.4.4.13
19.4.5
19.4.5.1
19.4.5.2
19.4.5.3
19.4.5.4
19.4.5.5
19.4.5.6
19.4.5.7
19.4.5.8
19.4.6
19.4.6.1
19.4.6.2
19.4.6.3
19.4.6.4
19.4.6.5
19.4.6.6
19.4.6.7
19.4.6.8
19.4.6.9
19.4.6.9.1
19.4.6.9.2
19.4.6.9.3
19.4.6.9.4
19.4.6.9.5
19.4.6.9.6
19.4.7
19.4.7.1
Page
Number
Title
Message Digest Execution Unit (MDEU) ............................................................... 19-50
MDEU Mode Register (MDEUMR) ................................................................... 19-50
Recommended Settings for MDEU Mode Register ............................................ 19-53
MDEU Key Size Register (MDEUKSR) ............................................................ 19-54
MDEU Data Size Register (MDEUDSR)............................................................ 19-54
MDEU Reset Control Register (MDEURCR)..................................................... 19-55
MDEU Status Register (MDEUSR) .................................................................... 19-55
MDEU Interrupt Status Register (MDEUISR).................................................... 19-57
MDEU Interrupt Control Register (MDEUICR) ................................................. 19-58
MDEU ICV Size Register (MDEUICVSR) ........................................................ 19-59
MDEU EU Go Register (MDEUEUG) ............................................................... 19-59
MDEU Context Registers .................................................................................... 19-60
MDEU Key Registers .......................................................................................... 19-61
MDEU FIFOs ...................................................................................................... 19-62
Random Number Generator (RNG)......................................................................... 19-62
RNG Mode Register (RNGMR).......................................................................... 19-63
RNG Data Size Register (RNGDSR) .................................................................. 19-63
RNG Reset Control Register (RNGRCR) ........................................................... 19-63
RNG Status Register (RNGSR)........................................................................... 19-64
RNG Interrupt Status Register (RNGISR)........................................................... 19-65
RNG Interrupt Control Register (RNGICR)........................................................ 19-66
RNG EU Go Register (RNGEUG) ...................................................................... 19-67
RNG FIFO ........................................................................................................... 19-67
Advanced Encryption Standard Execution Unit (AESU)........................................ 19-67
AESU Mode Register (AESUMR)...................................................................... 19-67
AESU Key Size Register (AESUKSR) ............................................................... 19-69
AESU Data Size Register (AESUDSR) .............................................................. 19-69
AESU Reset Control Register (AESURCR) ....................................................... 19-70
AESU Status Register (AESUSR)....................................................................... 19-71
AESU Interrupt Status Register (AESUISR)....................................................... 19-72
AESU Interrupt Control Register (AESUICR).................................................... 19-73
AESU EU Go Register (AESUEUG) .................................................................. 19-74
AESU Context Registers ..................................................................................... 19-75
Context for CBC Mode.................................................................................... 19-76
Context for Counter Mode............................................................................... 19-76
Context for SRT Mode .................................................................................... 19-76
Context for CCM Mode................................................................................... 19-77
AESU Key Registers ....................................................................................... 19-79
AESU FIFOs.................................................................................................... 19-79
Kasumi Execution Unit (KEU)................................................................................ 19-79
KEU Mode Register (KEUMR) .......................................................................... 19-80
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Paragraph
Number
19.4.7.2
19.4.7.3
19.4.7.4
19.4.7.5
19.4.7.6
19.4.7.7
19.4.7.8
19.4.7.9
19.4.7.10
19.4.7.11
19.4.7.12
19.4.7.13
19.4.7.14
19.4.7.15
19.4.7.16
19.5
19.5.1
19.5.1.1
19.5.1.2
19.5.1.3
19.5.1.4
19.5.1.5
19.5.1.6
19.5.2
19.5.2.1
19.5.2.2
19.5.2.3
19.6
19.6.1
19.6.1.1
19.6.1.2
19.6.2
19.6.2.1
19.6.2.2
19.6.2.3
19.6.2.4
19.6.3
19.6.4
19.6.5
19.6.5.1
19.6.5.2
Title
Page
Number
KEU Key Size Register (KEUKSR).................................................................... 19-81
KEU Data Size Register (KEUDSR)................................................................... 19-81
KEU Reset Control Register (KEURCR)............................................................ 19-82
KEU Status Register (KEUSR) ........................................................................... 19-83
KEU Interrupt Status Register (KEUISR) ........................................................... 19-84
KEU Interrupt Control Register (KEUICR) ........................................................ 19-85
KEU Data Out Register (F9 MAC) (KEUDOR) ................................................. 19-87
KEU EU Go Register (KEUEUG) ...................................................................... 19-87
KEU IV 1 Register (KEUIV1) ............................................................................ 19-88
KEU ICV_In Register (KEUICV)....................................................................... 19-88
KEU IV_2 Register (Fresh) (KEUIV2) ............................................................... 19-89
KEU Context Data Registers (KEUCn) .............................................................. 19-89
KEU Key Data Registers_1 and _2 (Confidentiality Key) (KEUKDn) .............. 19-89
KEU Key Data Registers _3 and _4 (Integrity Key) (KEUKDn) ....................... 19-90
KEU FIFOs .......................................................................................................... 19-90
Crypto-Channels .......................................................................................................... 19-91
Channel Registers .................................................................................................... 19-92
Crypto-Channel Configuration Registers 1–4 (CCCRn) ..................................... 19-92
Crypto-Channel Pointer Status Registers 1–4 (CCPSRn) ................................... 19-95
Crypto-Channel Current Descriptor Pointer Registers 1–4 (CCDPRn) ............ 19-100
Fetch FIFO Address Registers 1–4 (FFn).......................................................... 19-101
Crypto-Channel 1–4 Descriptor Buffers [0–7] (DBn[0–7]) .............................. 19-102
Link Table Buffer Registers (Scatter or Gather)—LTB0–3 .............................. 19-102
Channel Interrupts.................................................................................................. 19-103
Channel Done Interrupt ..................................................................................... 19-103
Channel Error Interrupt...................................................................................... 19-103
Channel Reset .................................................................................................... 19-103
Security Controller..................................................................................................... 19-104
Assignment of EUs to Channels ............................................................................ 19-104
Channel Priority Arbitration .............................................................................. 19-105
Channel Round-Robin Arbitration .................................................................... 19-105
Bus Transfers ......................................................................................................... 19-105
Arbitration for Use of the Controller and Buses................................................ 19-106
System Bus Master Reads ................................................................................. 19-107
System Bus Master Writes................................................................................. 19-107
System Bus Slave Transactions (Reads and Writes) ......................................... 19-107
Snooping by Caches............................................................................................... 19-108
Controller Interrupts .............................................................................................. 19-108
Controller Registers ............................................................................................... 19-109
EU Assignment Status Register (EUASR) ........................................................ 19-109
Interrupt Mask Register (IMR).......................................................................... 19-110
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Contents
Paragraph
Number
19.6.5.3
19.6.5.4
19.6.5.5
19.6.5.6
19.6.5.7
19.7
Page
Number
Title
Interrupt Status Register (ISR) ...........................................................................19-111
Interrupt Clear Register (ICR) ........................................................................... 19-112
ID Register......................................................................................................... 19-113
IP Block Revision Register................................................................................ 19-113
Master Control Register (MCR) ........................................................................ 19-114
Power-Saving Mode................................................................................................... 19-115
Part IV
Global Functions and Debug
Chapter 20
Global Utilities
20.1
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.3
20.3.1
20.3.2
20.4
20.4.1
20.4.1.1
20.4.1.2
20.4.1.3
20.4.1.4
20.4.1.5
20.4.1.6
20.4.1.7
20.4.1.8
20.4.1.9
20.4.1.10
20.4.1.11
20.4.1.12
20.4.1.13
20.4.1.14
20.4.1.15
20.4.1.16
Overview........................................................................................................................ 20-1
Global Utilities Features ................................................................................................ 20-1
Power Management and Block Disables ................................................................... 20-1
Accessing Current POR Configuration Settings........................................................ 20-1
General-Purpose I/O .................................................................................................. 20-1
Interrupt and Local Bus Signal Multiplexing ............................................................ 20-1
Clock Control............................................................................................................. 20-2
External Signal Description ........................................................................................... 20-2
Signals Overview....................................................................................................... 20-2
Detailed Signal Descriptions ..................................................................................... 20-2
Memory Map/Register Definition ................................................................................. 20-3
Register Descriptions................................................................................................. 20-5
POR PLL Status Register (PORPLLSR) ............................................................... 20-5
POR Boot Mode Status Register (PORBMSR)..................................................... 20-6
POR I/O Impedance Status and Control Register (PORIMPSCR) ....................... 20-7
POR Device Status Register (PORDEVSR).......................................................... 20-8
POR Debug Mode Status Register (PORDBGMSR) .......................................... 20-10
POR Device Status Register 2 (PORDEVSR2)................................................... 20-11
General-Purpose POR Configuration Register (GPPORCR) .............................. 20-11
General-Purpose I/O Control Register (GPIOCR) .............................................. 20-12
General-Purpose Output Data Register (GPOUTDR) ......................................... 20-12
General-Purpose Input Data Register (GPINDR)................................................ 20-14
Alternate Function Signal Multiplex Control Register (PMUXCR) ................... 20-14
Device Disable Register (DEVDISR) ................................................................. 20-15
Power Management Control and Status Register (POWMGTCSR).................... 20-17
Machine Check Summary Register (MCPSUMR).............................................. 20-19
Reset Request Status and Control Register (RSTRSCR) .................................... 20-20
Processor Version Register (PVR)....................................................................... 20-20
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Paragraph
Number
20.4.1.17
20.4.1.18
20.4.1.19
20.4.1.20
20.4.1.21
20.4.1.22
20.4.1.23
20.4.1.24
20.4.1.25
20.4.1.26
20.4.1.27
20.5
20.5.1
20.5.1.1
20.5.1.2
20.5.1.3
20.5.1.4
20.5.1.5
20.5.1.5.1
20.5.1.5.2
20.5.1.5.3
20.5.1.6
20.5.1.7
20.5.1.8
20.5.1.8.1
20.5.1.8.2
20.5.1.9
20.5.1.10
20.5.1.11
20.5.2
20.5.3
Title
Page
Number
System Version Register (SVR)........................................................................... 20-21
Reset Control Register (RSTCR)......................................................................... 20-22
LBC Voltage Select Control Register (LBCVSELCR) ....................................... 20-22
DDR Calibration Status Register (DDRCSR) ..................................................... 20-23
DDR Control Driver Register (DDRCDR).......................................................... 20-23
DDR Clock Disable Register (DDRCLKDR) ..................................................... 20-25
Clock Out Control Register (CLKOCR) ............................................................. 20-25
SerDes Control Register 0 (SRDSCR0) .............................................................. 20-26
SerDes Control Register 1 (SRDSCR1) .............................................................. 20-27
eTSEC1 and eTSEC2 I/O Overdrive Control Register (TSEC12IOOVCR)....... 20-28
eTSEC3 and eTSEC4 I/O Overdrive Control Register (TSEC34IOOVCR)....... 20-29
Functional Description................................................................................................. 20-30
Power Management ................................................................................................. 20-30
Relationship Between Core and Device Power Management States................... 20-30
CKSTP_IN is Not Power Management ............................................................... 20-31
Dynamic Power Management.............................................................................. 20-31
Shutting Down Unused Blocks............................................................................ 20-31
Software-Controlled Power-Down States............................................................ 20-32
Doze Mode ...................................................................................................... 20-32
Nap Mode ........................................................................................................ 20-32
Sleep Mode ...................................................................................................... 20-32
Power Management Control Fields ..................................................................... 20-33
Power-Down Sequence Coordination.................................................................. 20-33
Interrupts and Power Management ...................................................................... 20-35
Interrupts and Power Management Controlled by MSR[WE] ........................ 20-35
Interrupts and Power Management Controlled by POWMGTCSR................. 20-35
Snooping in Power-Down Modes........................................................................ 20-36
Software Considerations for Power Management ............................................... 20-36
Requirements for Reaching and Recovering from Sleep State............................ 20-36
General-Purpose I/O Signals ................................................................................... 20-37
Interrupt and Local Bus Signal Multiplexing .......................................................... 20-37
Chapter 21
Device Performance Monitor
21.1
21.1.1
21.1.2
21.2
21.3
21.3.1
Introduction.................................................................................................................... 21-1
Overview.................................................................................................................... 21-2
Features...................................................................................................................... 21-3
Signal Descriptions ........................................................................................................ 21-3
Memory Map and Register Definition........................................................................... 21-3
Register Summary...................................................................................................... 21-3
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
xlix
Contents
Paragraph
Number
21.3.2
21.3.2.1
21.3.2.2
21.3.3
21.3.3.1
21.4
21.4.1
21.4.2
21.4.3
21.4.4
21.4.5
21.4.6
21.4.7
21.4.8
Page
Number
Title
Control Registers ....................................................................................................... 21-5
Performance Monitor Global Control Register (PMGC0) .................................... 21-5
Performance Monitor Local Control Registers (PMLCAn, PMLCBn)................. 21-5
Counter Registers....................................................................................................... 21-9
Performance Monitor Counters (PMC0–PMC9)................................................... 21-9
Functional Description................................................................................................. 21-11
Performance Monitor Interrupt................................................................................ 21-11
Event Counting ........................................................................................................ 21-11
Threshold Events ..................................................................................................... 21-11
Chaining................................................................................................................... 21-12
Triggering ................................................................................................................ 21-13
Burstiness Counting................................................................................................. 21-13
Performance Monitor Events ................................................................................... 21-15
Performance Monitor Examples .............................................................................. 21-28
Chapter 22
Debug Features and Watchpoint Facility
22.1
22.1.1
22.1.2
22.1.3
22.1.3.1
22.1.3.2
22.1.3.3
22.1.3.4
22.1.3.5
22.2
22.2.1
22.2.2
22.2.2.1
22.2.2.2
22.2.2.3
22.3
22.3.1
22.3.1.1
22.3.1.2
22.3.1.3
22.3.1.4
22.3.1.5
22.3.2
Introduction.................................................................................................................... 22-1
Overview.................................................................................................................... 22-1
Features...................................................................................................................... 22-3
Modes of Operation ................................................................................................... 22-3
Local Bus (LBC) Debug Mode.............................................................................. 22-4
DDR SDRAM Interface Debug Modes ................................................................. 22-4
PCI Interface Debug Modes .................................................................................. 22-4
Watchpoint Monitor Modes ................................................................................... 22-4
Trace Buffer Modes ............................................................................................... 22-5
External Signal Description ........................................................................................... 22-5
Overview.................................................................................................................... 22-5
Detailed Signal Descriptions ..................................................................................... 22-7
Debug Signals—Details......................................................................................... 22-7
Watchpoint Monitor Trigger Signals—Details...................................................... 22-8
Test Signals—Details............................................................................................. 22-8
Memory Map/Register Definition ............................................................................... 22-10
Watchpoint Monitor Register Descriptions ............................................................. 22-11
Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)...................... 22-11
Watchpoint Monitor Address Register (WMAR)................................................ 22-13
Watchpoint Monitor Address Mask Register (WMAMR) ................................. 22-13
Watchpoint Monitor Transaction Mask Register (WMTMR) ............................. 22-13
Watchpoint Monitor Status Register (WMSR) .................................................... 22-15
Trace Buffer Register Descriptions.......................................................................... 22-16
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number
22.3.2.1
22.3.2.2
22.3.2.3
22.3.2.4
22.3.2.5
22.3.2.6
22.3.2.7
22.3.2.8
22.3.3
22.3.3.1
22.3.3.2
22.3.4
22.3.4.1
22.4
22.4.1
22.4.2
22.4.3
22.4.3.1
22.4.3.2
22.4.4
22.4.5
22.4.5.1
22.4.6
22.4.6.1
22.5
Title
Page
Number
Trace Buffer Control Registers (TBCR0, TBCR1) ............................................. 22-16
Trace Buffer Address Register (TBAR) .............................................................. 22-18
Trace Buffer Address Mask Register (TBAMR)................................................. 22-19
Trace Buffer Transaction Mask Register (TBTMR)............................................ 22-19
Trace Buffer Status Register (TBSR) .................................................................. 22-20
Trace Buffer Access Control Register (TBACR) ................................................ 22-21
Trace Buffer Access Data High Register (TBADHR)......................................... 22-21
Trace Buffer Access Data Register (TBADR)..................................................... 22-22
Context ID Registers................................................................................................ 22-22
Programmed Context ID Register (PCIDR) ........................................................ 22-22
Current Context ID Register (CCIDR) ................................................................ 22-23
Trigger Out Function ............................................................................................... 22-23
Trigger Out Source Register (TOSR) .................................................................. 22-24
Functional Description................................................................................................. 22-24
Source and Target ID ............................................................................................... 22-24
PCI Interface Debug ................................................................................................ 22-25
DDR SDRAM Interface Debug............................................................................... 22-26
Debug Information on Debug Pins ...................................................................... 22-26
Debug Information on ECC Pins......................................................................... 22-26
Local Bus Interface Debug ...................................................................................... 22-26
Watchpoint Monitor ................................................................................................. 22-26
Watchpoint Monitor Performance Monitor Events ............................................. 22-27
Trace Buffer ............................................................................................................. 22-27
Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 22-28
Initialization ................................................................................................................. 22-30
Appendix A
MPC8547E
A.1
A.2
A.3
A.3.1
A.3.2
A.3.3
A.4
Overview of Differences................................................................................................. A-1
Differences in Signals ..................................................................................................... A-2
Differences in Peripheral Blocks .................................................................................... A-3
PCI/PCI-X Bus Interface ............................................................................................ A-3
Serial RapidIO Interface ............................................................................................. A-3
PCI Express Interface ................................................................................................. A-3
I/O Port Selection............................................................................................................ A-3
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Contents
Paragraph
Number
Page
Number
Title
Appendix B
MPC8545E
B.1
B.2
B.3
B.3.1
B.3.2
B.3.3
B.3.4
B.3.5
B.3.6
B.4
Overview of Differences..................................................................................................B-1
Differences in Signals ......................................................................................................B-2
Differences in Peripheral Blocks .....................................................................................B-3
DDR Memory Controller.............................................................................................B-3
Enhanced Three-Speed Ethernet Controllers...............................................................B-3
PCI/PCI-X Bus Interface .............................................................................................B-3
Serial RapidIO Interface ..............................................................................................B-3
PCI Express Interface ..................................................................................................B-3
Security Engine............................................................................................................B-3
I/O Port Selection.............................................................................................................B-3
Appendix C
MPC8543E
C.1
C.2
C.3
C.3.1
C.3.2
C.3.3
C.3.4
C.3.5
C.3.6
C.4
Overview of Differences..................................................................................................C-1
Differences in Signals ......................................................................................................C-2
Differences in Peripheral Blocks .....................................................................................C-3
L2 Look-Aside Cache/SRAM .....................................................................................C-3
DDR Memory Controller.............................................................................................C-3
Enhanced Three-Speed Ethernet Controllers...............................................................C-4
PCI/PCI-X Bus Interface .............................................................................................C-4
PCI Express Interface ..................................................................................................C-4
Security Engine............................................................................................................C-4
I/O Port Selection.............................................................................................................C-4
Appendix D
Revision History
D.1
D.2
Changes From Revision 1 to Revision 2 ........................................................................ D-1
Changes From Revision 0 to Revision 1 ...................................................................... D-12
Index 1
Register Index (Memory-Mapped Registers)
Index 2
General Index
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Figures
Figure
Number
Title
Page
Number
Figures
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
5-7
MPC8548E Block Diagram .................................................................................................... 1-2
Integrated Security Engine Functional Blocks...................................................................... 1-18
Processing Transactions Across the On-Chip Fabric............................................................ 1-25
VPN Access Router Enabled by PCI Express and Ethernet ................................................. 1-26
High-Performance Communication System Using Distributed Processing ......................... 1-27
High-Performance Communication System Using MPC8548E ........................................... 1-27
RAID Controller Application Using MPC8548E ................................................................. 1-28
MPC8548E with SerDes ....................................................................................................... 1-28
MPC8548E as a Control Plane Processor for a DSP Farm Interconnected with RapidIO ... 1-28
Local Memory Map Example ................................................................................................. 2-2
Local Access IP Block Revision Register 1 (LAIPBRR1) ..................................................... 2-6
Local Access IP Block Revision Register 2 (LAIPBRR2) ..................................................... 2-6
Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7) ....................... 2-7
Local Access Window n Attributes Registers (LAWAR0–LAWAR7) ................................... 2-7
Top-Level Register Map Example ........................................................................................ 2-11
General Utilities Registers Mapping to Configuration, Control,
and Status Memory Block ................................................................................................ 2-13
PIC Mapping to Configuration, Control, and Status Memory Block ................................... 2-14
RapidIO Mapping to Configuration, Control, and Status Memory Block............................ 2-15
Device-Specific Register Mapping to Configuration, Control,
and Status Memory Block ................................................................................................ 2-16
MPC8548E Signal Groupings (1/3)........................................................................................ 3-2
MPC8548E Signal Groupings (2/3) (Continued).................................................................... 3-3
MPC8548E Signal Groupings (3/3) (Continued).................................................................... 3-4
Configuration, Control, and Status Register Base Address Register (CCSRBAR)................ 4-5
Alternate Configuration Base Address Register (ALTCBAR) ............................................... 4-6
Alternate Configuration Attribute Register (ALTCAR) ......................................................... 4-6
Boot Page Translation Register (BPTR) ................................................................................. 4-7
Power-On Reset Sequence .................................................................................................... 4-10
Clock Subsystem Block Diagram ......................................................................................... 4-26
RTC and Core Timer Facilities Clocking Options ................................................................ 4-28
e500 Core Complex Block Diagram ....................................................................................... 5-2
Vector and Floating-Point APUs............................................................................................. 5-6
Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 5-8
Three-Stage Load/Store Unit .................................................................................................. 5-9
Instruction Pipeline Flow ...................................................................................................... 5-15
GPR Issue Queue (GIQ) ....................................................................................................... 5-16
e500 Core Programming Model............................................................................................ 5-18
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Figures
Figure
Number
5-8
5-9
5-10
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
Page
Number
Title
MMU Structure ..................................................................................................................... 5-24
Effective-to-Real Address Translation Flow......................................................................... 5-25
Effective-to-Real Address Translation Flow (e500v2) ......................................................... 5-26
Core Register Model ............................................................................................................... 6-2
Integer Exception Register (XER) .......................................................................................... 6-8
Condition Register (CR) ......................................................................................................... 6-9
Link Register (LR) ................................................................................................................ 6-11
Count Register (CTR) ........................................................................................................... 6-11
Machine State Register (MSR) ............................................................................................. 6-11
Processor ID Register (PIR).................................................................................................. 6-13
Processor Version Register (PVR) ........................................................................................ 6-13
System Version Register (SVR)............................................................................................ 6-14
Timer Control Register (TCR) .............................................................................................. 6-14
Timer Status Register (TSR) ................................................................................................. 6-15
Time Base Upper/Lower Registers (TBU/TBL)................................................................... 6-16
Decrementer Register (DEC) ................................................................................................ 6-16
Decrementer Auto-Reload Register (DECAR)..................................................................... 6-17
Save/Restore Register 0 (SRR0) ........................................................................................... 6-17
Save/Restore Register 1 (SRR1) ........................................................................................... 6-17
Critical Save/Restore Register 0 (CSRR0) ........................................................................... 6-17
Critical Save/Restore Register 1 (CSRR1) ........................................................................... 6-18
Data Exception Address Register (DEAR) ........................................................................... 6-18
Interrupt Vector Prefix Register (IVPR) ............................................................................... 6-18
Interrupt Vector Offset Registers (IVORn) ........................................................................... 6-18
Exception Syndrome Register (ESR).................................................................................... 6-19
Machine Check Save/Restore Register 0 (MCSRR0)........................................................... 6-20
Machine Check Save/Restore Register 1 (MCSRR1)........................................................... 6-20
Machine Check Address Register (MCAR).......................................................................... 6-21
Machine Check Address Register Upper (MCARU)............................................................ 6-21
Machine Check Syndrome Register (MCSR) ....................................................................... 6-21
Software-Use SPRs (SPRG0–SPRG7 and USPRG0)........................................................... 6-22
Branch Buffer Entry Address Register (BBEAR) ................................................................ 6-23
Branch Buffer Target Address Register (BBTAR)................................................................ 6-23
Branch Unit Control and Status Register (BUCSR) ............................................................. 6-24
Hardware Implementation-Dependent Register 0 (HID0).................................................... 6-25
Hardware Implementation-Dependent Register 1 (HID1).................................................... 6-26
L1 Cache Control and Status Register 0 (L1CSR0).............................................................. 6-28
L1 Cache Control and Status Register 1 (L1CSR1).............................................................. 6-29
L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 6-30
L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 6-31
Process ID Registers (PID0–PID2)....................................................................................... 6-32
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Figures
Figure
Number
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59
6-60
6-61
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
Title
Page
Number
MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-32
MMU Configuration Register (MMUCFG) ......................................................................... 6-32
TLB Configuration Register 0 (TLB0CFG) ......................................................................... 6-33
TLB Configuration Register 1 (TLB1CFG) ......................................................................... 6-34
MAS Register 0 (MAS0) ...................................................................................................... 6-35
MAS Register 1 (MAS1) ...................................................................................................... 6-35
MAS Register 2 (MAS2) ...................................................................................................... 6-36
MAS Register 3 (MAS3) ...................................................................................................... 6-37
MAS Register 4 (MAS4) ...................................................................................................... 6-38
MAS Register 6 (MAS6) ...................................................................................................... 6-38
MAS Register 7 (MAS7) ...................................................................................................... 6-39
Debug Control Register 0 (DBCR0) ..................................................................................... 6-39
Debug Control Register 1 (DBCR1) ..................................................................................... 6-41
Debug Control Register 2 (DBCR2) ..................................................................................... 6-42
Debug Status Register (DBSR)............................................................................................. 6-43
Instruction Address Compare Registers (IAC1–IAC2) ........................................................ 6-45
Data Address Compare Registers (DAC1–DAC2) ............................................................... 6-45
Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR) 6-45
Accumulator (ACC) .............................................................................................................. 6-47
Performance Monitor Global Control Register 0 (PMGC0),
User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 6-49
Local Control A Registers (PMLCa0–PMLCa3), User Local Control A Registers
(UPMLCa0–UPMLCa3) .................................................................................................. 6-50
Local Control B Registers (PMLCb0–PMLCb3)/User Local Control B Registers
(UPMLCb0–UPMLCb3).................................................................................................. 6-51
Performance Monitor Counter Registers (PMC0–PMC3)/User Performance Monitor
Counter Registers (UPMC0–UPMC3)............................................................................. 6-52
L2 Cache/SRAM Configuration ............................................................................................. 7-1
Cache Organization ................................................................................................................. 7-4
Physical Address Usage for L2 Cache Accesses .................................................................... 7-5
Physical Address Usage for SRAM Accesses ........................................................................ 7-6
Data Bus Connection of CCB ................................................................................................. 7-8
Address Bus Connection of CCB............................................................................................ 7-8
L2 Control Register (L2CTL) ............................................................................................... 7-10
Cache External Write Address Registers (L2CEWARn) ...................................................... 7-14
Cache External Write Address Registers Extended Address (L2CEWAREAn)................... 7-14
Cache External Write Control Registers (L2CEWCR0–L2CEWCR3) ................................ 7-15
L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)................................... 7-16
L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
(L2SRBAREAn) .............................................................................................................. 7-17
L2 Error Injection Mask High Register (L2ERRINJHI) ...................................................... 7-18
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Figures
Figure
Number
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
Page
Number
Title
L2 Error Injection Mask Low Register (L2ERRINJLO) ...................................................... 7-19
L2 Error Injection Mask Control Register (L2ERRINJCTL) ............................................... 7-19
L2 Error Capture Data High Register (L2CAPTDATAHI)................................................... 7-20
L2 Error Capture Data Low Register (L2CAPTDATALO) .................................................. 7-20
L2 Error Syndrome Register (L2CAPTECC) ....................................................................... 7-20
L2 Error Detect Register (L2ERRDET) ............................................................................... 7-21
L2 Error Disable Register (L2ERRDIS) ............................................................................... 7-22
L2 Error Interrupt Enable Register (L2ERRINTEN) ........................................................... 7-22
L2 Error Attributes Capture Register (L2ERRATTR) .......................................................... 7-23
L2 Error Address Capture Register (L2ERRADDRH)......................................................... 7-24
L2 Error Address Capture Register (L2ERRADDRL) ......................................................... 7-24
L2 Error Control Register (L2ERRCTL).............................................................................. 7-25
L2 Cache Line Replacement Algorithm ............................................................................... 7-31
e500 Coherency Module Block Diagram................................................................................ 8-1
ECM CCB Address Configuration Register (EEBACR)........................................................ 8-3
ECM CCB Port Configuration Register (EEBPCR)............................................................... 8-4
ECM IP Block Revision Register 1 (EIPBRR1)..................................................................... 8-5
ECM IP Block Revision Register 2 (EIPBRR2)..................................................................... 8-5
ECM Error Detect Register (EEDR)....................................................................................... 8-6
ECM Error Enable Register (EEER) ...................................................................................... 8-7
ECM Error Attributes Capture Register (EEATR) ................................................................. 8-7
ECM Error Low Address Capture Register (EELADR)......................................................... 8-8
ECM Error High Address Capture Register (EEHADR)........................................................ 8-9
DDR Memory Controller Simplified Block Diagram............................................................. 9-2
Chip Select Bounds Registers (CSn_BNDS)........................................................................ 9-12
Chip Select Configuration Register (CSn_CONFIG) ........................................................... 9-12
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) ................................................ 9-14
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) ................................................ 9-14
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 9-16
DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 9-18
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 9-20
DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 9-23
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-25
DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 9-26
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) ................................ 9-26
DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-29
DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-30
DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)....... 9-30
DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-31
DDR Initialization Extended Address Configuration Register (DDR_INIT_EXT_ADDR) 9-31
DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-32
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Figures
Figure
Number
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44
9-45
9-46
9-47
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
Title
Page
Number
DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-32
Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI) ......... 9-33
Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 9-33
Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)............................ 9-34
Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 9-34
Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 9-35
Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 9-35
Memory Error Detect Register (ERR_DETECT) ................................................................. 9-36
Memory Error Disable Register (ERR_DISABLE).............................................................. 9-36
Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 9-37
Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 9-38
Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 9-39
Memory Error Extended Address Capture Register (CAPTURE_EXT_ADDRESS).......... 9-40
Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 9-40
DDR Memory Controller Block Diagram ............................................................................ 9-42
Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-43
Typical DDR SDRAM Interface Signals .............................................................................. 9-43
Example 256-Mbyte DDR SDRAM Configuration With ECC ............................................ 9-44
DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-56
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-56
DDR SDRAM 4-Beat Burst Write Timing—ACTTORW = 4 ............................................. 9-57
DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs .................................... 9-58
DDR SDRAM Mode-Set Command Timing........................................................................ 9-58
Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-59
Write Timing Adjustments Example for Write Latency = 1 ................................................. 9-60
DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-61
DDR SDRAM Power-Down Mode ...................................................................................... 9-62
DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-63
DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-63
Pass-Through Mode Example ............................................................................................... 10-3
Block Revision Register 1 (BRR1) ..................................................................................... 10-16
Block Revision Register 2 (BRR2) ..................................................................................... 10-17
Feature Reporting Register (FRR) ...................................................................................... 10-17
Global Configuration Register (GCR) ................................................................................ 10-18
Vendor Identification Register (VIR).................................................................................. 10-19
Processor Initialization Register (PIR) ............................................................................... 10-19
IPI Vector/Priority Register (IPIVPRn) .............................................................................. 10-20
Spurious Vector Register (SVR) ......................................................................................... 10-21
Timer Frequency Reporting Register (TFRR) .................................................................... 10-21
Global Timer Current Count Registers (GTCCRn)............................................................. 10-22
Global Timer Base Count Register (GTBCRn)................................................................... 10-22
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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11-1
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11-6
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Title
Global Timer Vector/Priority Register (GTVPRn).............................................................. 10-23
Global Timer Destination Registers (GTDRn).................................................................... 10-24
Example Calculation for Cascaded Timers......................................................................... 10-25
Timer Control Register (TCR) ............................................................................................ 10-25
External Interrupt Summary Register (ERQSR)................................................................. 10-27
IRQ_OUT Summary Register 0 (IRQSR0) ........................................................................ 10-27
IRQ_OUT Summary Register 1 (IRQSR1) ........................................................................ 10-28
IRQ_OUT Summary Register 2 (IRQSR2) ........................................................................ 10-28
Critical Interrupt Summary Register 0 (CISR0) ................................................................. 10-29
Critical Interrupt Summary Register 1 (CISR1) ................................................................. 10-29
Critical Interrupt Summary Register 2 (CISR2) ................................................................. 10-30
Performance Monitor n Mask Registers 0 (PMnMR0)....................................................... 10-30
Performance Monitor n Mask Registers 1 (PMnMR1)....................................................... 10-31
Performance Monitor n Mask Registers 2 (PMnMR2)....................................................... 10-31
Message Registers (MSGRs) .............................................................................................. 10-32
Message Enable Register (MER) ........................................................................................ 10-33
Message Status Register (MSR).......................................................................................... 10-33
Shared Message Signaled Interrupt Register (MSIRs) ....................................................... 10-34
Shared Message Signaled Interrupt Status Register (MSISR)............................................ 10-34
Shared Message Signaled Interrupt Index Register (MSIIR) ............................................. 10-35
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRn)......................... 10-35
Shared Message Signaled Interrupt Destination Registers (MSIDRn) ............................... 10-36
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................................... 10-37
External Interrupt Destination Registers (EIDRs) .............................................................. 10-38
Internal Interrupt Vector/Priority Registers (IIVPRs) ......................................................... 10-39
Internal Interrupt Destination Registers (IIDRs) ................................................................ 10-40
Messaging Interrupt Vector/Priority Registers (MIVPRs).................................................. 10-40
Messaging Interrupt Destination Registers (MIDRs) ......................................................... 10-41
Per-CPU Register Address Decoding in a Four-Core Device............................................. 10-43
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3) ......................................... 10-43
Processor Current Task Priority Register (CTPR) .............................................................. 10-44
Processor Who Am I Register (WHOAMI)........................................................................ 10-45
Processor Interrupt Acknowledge Register (IACK) ........................................................... 10-45
End of Interrupt Register (EOI) .......................................................................................... 10-46
PIC Interrupt Processing Flow Diagram ............................................................................. 10-47
I2C Block Diagram................................................................................................................ 11-1
I2C Address Register (I2CADR)........................................................................................... 11-6
I2C Frequency Divider Register (I2CFDR) .......................................................................... 11-6
I2C Control Register (I2CCR)............................................................................................... 11-7
I2C Status Register (I2CSR) ................................................................................................. 11-9
I2C Data Register (I2CDR) ................................................................................................. 11-10
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I2C Digital Filter Sampling Rate Register (I2CDFSRR).....................................................11-11
I2C Interface Transaction Protocol...................................................................................... 11-12
EEPROM Data Format for One Register Preload Command............................................. 11-19
EEPROM Contents ............................................................................................................. 11-20
Example I2C Interrupt Service Routine Flowchart ............................................................. 11-25
UART Block Diagram .......................................................................................................... 12-2
Receiver Buffer Registers (URBR0, URBR1)...................................................................... 12-6
Transmitter Holding Registers (UTHR0, UTHR1)............................................................... 12-7
Divisor Most Significant Byte Registers (UDMB0, UDMB1)............................................. 12-7
Divisor Least Significant Byte Registers (UDLB0, UDLB1)............................................... 12-8
Interrupt Enable Register (UIER) ......................................................................................... 12-9
Interrupt ID Registers (UIIR).............................................................................................. 12-10
FIFO Control Registers (UFCR0, UFCR1) ........................................................................ 12-11
Line Control Register (ULCR) ........................................................................................... 12-13
Modem Control Register (UMCR) ..................................................................................... 12-14
Line Status Register (ULSR) .............................................................................................. 12-15
Modem Status Register (UMSR) ........................................................................................ 12-16
Scratch Register (USCR) .................................................................................................... 12-17
Alternate Function Register (UAFR) .................................................................................. 12-17
DMA Status Register (UDSR) ............................................................................................ 12-18
UART Bus Interface Transaction Protocol Example .......................................................... 12-20
Local Bus Controller Block Diagram ................................................................................... 13-1
Base Registers (BRn) .......................................................................................................... 13-10
Option Registers (ORn) in GPCM Mode............................................................................ 13-13
Option Registers (ORn) in UPM Mode .............................................................................. 13-15
Option Registers (ORn) in SDRAM Mode......................................................................... 13-16
UPM Memory Address Register (MAR) ............................................................................ 13-17
UPM Mode Registers (MxMR)........................................................................................... 13-17
Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 13-20
UPM Data Register (MDR) ................................................................................................ 13-20
SDRAM Machine Mode Register (LSDMR) ..................................................................... 13-21
UPM Refresh Timer (LURT) .............................................................................................. 13-23
LSRT SDRAM Refresh Timer (LSRT)............................................................................... 13-23
Transfer Error Status Register (LTESR) ............................................................................. 13-24
Transfer Error Check Disable Register (LTEDR) ............................................................... 13-25
Transfer Error Interrupt Enable Register (LTEIR).............................................................. 13-26
Transfer Error Attributes Register (LTEATR) .................................................................... 13-27
Transfer Error Address Register (LTEAR) ......................................................................... 13-28
Local Bus Configuration Register....................................................................................... 13-29
Clock Ratio Register (LCRR) ............................................................................................. 13-30
Basic Operation of Memory Controllers in the LBC.......................................................... 13-32
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 ......................................... 13-34
Basic LBC Bus Cycle with LALE, TA, and LCSn ............................................................. 13-34
Local Bus to GPCM Device Interface ................................................................................ 13-36
GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0) ........................................ 13-37
GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0) ..... 13-40
GPCM Relaxed Timing Read (XACS = 0, ACS = 1x, SCY = 1, EHTR = 0, TRLX = 1) . 13-41
GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0,
CSNT = 0, TRLX = 1) ................................................................................................... 13-41
GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1). 13-42
GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1). 13-42
GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 13-43
GPCM Read Followed by Write (TRLX = 0, EHTR = 1,
1-Cycle Extended Hold Time on Reads)........................................................................ 13-44
GPCM Read Followed by Write
(TRLX = 1, EHTR = 0, 4-Cycle Extended Hold Time on Reads) ................................. 13-44
External Termination of GPCM Access.............................................................................. 13-45
Connection to a 32-Bit SDRAM with 12 Address Lines.................................................... 13-47
SDRAM Address Multiplexing .......................................................................................... 13-50
PRETOACT = 2 (2 Clock Cycles)...................................................................................... 13-51
ACTTORW = 2 (2 Clock Cycles)....................................................................................... 13-51
CL = 2 (2 Clock Cycles) ..................................................................................................... 13-52
WRC = 2 (2 Clock Cycles) ................................................................................................. 13-52
RFRC = 4 (6 Clock Cycles) ................................................................................................ 13-53
BUFCMD = 1, LCRR[BUFCMDC] = 2............................................................................. 13-53
SDRAM Single-Beat Read, Page Closed, CL = 3 .............................................................. 13-54
SDRAM Single-Beat Read, Page Hit, CL = 3 .................................................................... 13-54
SDRAM Two-Beat Burst Read, Page Closed, CL = 3........................................................ 13-54
SDRAM Four-Beat Burst Read, Page Miss, CL = 3........................................................... 13-54
SDRAM Single-Beat Write, Page Hit................................................................................. 13-55
SDRAM Three-Beat Write, Page Closed............................................................................ 13-55
SDRAM Read-After-Read Pipelined, Page Hit, CL = 3..................................................... 13-55
SDRAM Write-After-Write Pipelined, Page Hit................................................................. 13-55
SDRAM Read-After-Write Pipelined, Page Hit ................................................................. 13-56
SDRAM MODE-SET Command........................................................................................ 13-56
SDRAM Bank-Staggered Auto-Refresh Timing ................................................................ 13-57
User-Programmable Machine Functional Block Diagram.................................................. 13-58
RAM Array Indexing .......................................................................................................... 13-59
Memory Refresh Timer Request Block Diagram ............................................................... 13-60
UPM Clock Scheme............................................................................................................ 13-63
RAM Array and Signal Generation .................................................................................... 13-63
RAM Word Field Descriptions ........................................................................................... 13-64
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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LCSn Signal Selection ........................................................................................................ 13-67
LBS Signal Selection .......................................................................................................... 13-67
UPM Read Access Data Sampling...................................................................................... 13-70
Effect of LUPWAIT Signal ................................................................................................. 13-71
Single-Beat Read Access to FPM DRAM .......................................................................... 13-73
Single-Beat Write Access to FPM DRAM ......................................................................... 13-74
Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown).............................. 13-75
Refresh Cycle (CBR) to FPM DRAM ................................................................................ 13-76
Exception Cycle .................................................................................................................. 13-77
Multiplexed Address/Data Bus ........................................................................................... 13-78
Local Bus Peripheral Hierarchy.......................................................................................... 13-79
Local Bus Peripheral Hierarchy for Very High Bus Speeds ............................................... 13-80
GPCM Address Timings ..................................................................................................... 13-80
GPCM Data Timings........................................................................................................... 13-81
Interface to Different Port-Size Devices ............................................................................. 13-83
128-Mbyte SDRAM Diagram............................................................................................. 13-87
SDRAM Power-Down Timing............................................................................................ 13-91
SDRAM Self-Refresh Mode Timing .................................................................................. 13-92
Local Bus PLL Operation ................................................................................................... 13-94
Parity Support for SDRAM................................................................................................. 13-95
Interface to ZBT SRAM ..................................................................................................... 13-96
MSC8101 HDI16 Peripheral Registers............................................................................... 13-98
Interface to MSC8101 HDI16............................................................................................. 13-99
Interface to MSC8102 DSI in Asynchronous Mode ......................................................... 13-102
Asynchronous Write to MSC8102 DSI............................................................................. 13-103
Asynchronous Read from MSC8102 DSI......................................................................... 13-104
Interface to MSC8102 DSI in Synchronous Mode ........................................................... 13-105
UPM Synchronization Cycle ............................................................................................ 13-106
Synchronous Single Write to MSC8102 DSI.................................................................... 13-107
Synchronous Single Read from MSC8102 DSI................................................................ 13-108
Synchronous Burst Write to MSC8102 DSI ..................................................................... 13-109
Synchronous Burst Read from MSC8102 DSI ................................................................. 13-110
eTSEC Block Diagram.......................................................................................................... 14-2
TSEC_ID Register .............................................................................................................. 14-21
TSEC_ID2 Register ............................................................................................................ 14-22
IEVENT Register Definition .............................................................................................. 14-24
IMASK Register Definition ................................................................................................ 14-28
EDIS Register Definition .................................................................................................... 14-29
ECNTRL Register Definition ............................................................................................. 14-31
PTV Register Definition...................................................................................................... 14-33
DMACTRL Register........................................................................................................... 14-34
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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TBIPA Register Definition.................................................................................................. 14-36
FIFO_RX_ALARM Register Definition ............................................................................ 14-37
FIFO_RX_ALARM_SHUTOFF Register Definition......................................................... 14-37
FIFO_TX_THR Register Definition ................................................................................... 14-38
FIFO_TX_STARVE Register Definition ............................................................................ 14-38
FIFO_TX_STARVE_SHUTOFF Register Definition ........................................................ 14-39
TCTRL Register Definition ................................................................................................ 14-40
TSTAT Register Definition ................................................................................................. 14-42
DFVLAN Register Definition............................................................................................. 14-43
TXIC Register Definition.................................................................................................... 14-44
TQUEUE Register Definition ............................................................................................. 14-45
TR03WT Register Definition.............................................................................................. 14-46
TR47WT Register Definition.............................................................................................. 14-47
TBDBPH Register Definition ............................................................................................. 14-47
TBPTR0–TBPTR7 Register Definition .............................................................................. 14-48
TBASEH Register Definition ............................................................................................. 14-49
TBASE Register Definition ................................................................................................ 14-49
RCTRL Register Definition ................................................................................................ 14-50
RSTAT Register Definition ................................................................................................. 14-52
RXIC Register Definition ................................................................................................... 14-54
RQUEUE Register Definition............................................................................................. 14-55
RBIFX Register Definition ................................................................................................. 14-56
Receive Queue Filer Table Address Register Definition .................................................... 14-58
Receive Queue Filer Table Control Register Definition ..................................................... 14-58
Receive Queue Filer Table Property IDs 0, 2–15 Register Definition................................ 14-60
Receive Queue Filer Table Property ID1 Register Definition ............................................ 14-60
MRBLR Register Definition ............................................................................................... 14-63
RBDBPH Register Definition............................................................................................. 14-63
RBPTR0–RBPTR7 Register Definition .............................................................................. 14-64
RBASEH Register Definition ............................................................................................. 14-65
RBASE Register Definition ................................................................................................ 14-65
MACCFG1 Register Definition .......................................................................................... 14-68
MACCFG2 Register Definition .......................................................................................... 14-70
IPGIFG Register Definition ................................................................................................ 14-72
Half-Duplex Register Definition......................................................................................... 14-73
Maximum Frame Length Register Definition..................................................................... 14-74
MII Management Configuration Register Definition ......................................................... 14-74
MIIMCOM Register Definition .......................................................................................... 14-75
MIIMADD Register Definition .......................................................................................... 14-76
MII Mgmt Control Register Definition............................................................................... 14-76
MIIMSTAT Register Definition.......................................................................................... 14-77
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Title
Page
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MII Mgmt Indicator Register Definition ............................................................................ 14-77
Interface Status Register Definition .................................................................................... 14-78
MAC Station Address Part 1 Register Definition ............................................................... 14-79
MAC Station Address Part 2 Register Definition ............................................................... 14-79
MAC Exact Match Address n Part 1 Register Definition ................................................... 14-80
MAC Exact Match Address x Part 2 Register Definition ................................................... 14-80
Transmit and Receive 64-Byte Frame Register Definition ................................................. 14-81
Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 14-82
Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 14-82
Transmit and Received 256- to 511-Byte Frame Register Definition................................. 14-83
Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 14-83
Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 14-84
Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 14-84
Receive Byte Counter Register Definition.......................................................................... 14-85
Receive Packet Counter Register Definition ...................................................................... 14-85
Receive FCS Error Counter Register Definition................................................................. 14-86
Receive Multicast Packet Counter Register Definition ...................................................... 14-86
Receive Broadcast Packet Counter Register Definition ..................................................... 14-87
Receive Control Frame Packet Counter Register Definition .............................................. 14-87
Receive Pause Frame Packet Counter Register Definition ................................................. 14-88
Receive Unknown OPCode Packet Counter Register Definition ....................................... 14-88
Receive Alignment Error Counter Register Definition....................................................... 14-89
Receive Frame Length Error Counter Register Definition ................................................. 14-89
Receive Code Error Counter Register Definition ............................................................... 14-90
Receive Carrier Sense Error Counter Register Definition .................................................. 14-90
Receive Undersize Packet Counter Register Definition ..................................................... 14-91
Receive Oversize Packet Counter Register Definition ....................................................... 14-91
Receive Fragments Counter Register Definition ................................................................ 14-92
Receive Jabber Counter Register Definition....................................................................... 14-92
Receive Dropped Packet Counter Register Definition ....................................................... 14-93
Transmit Byte Counter Register Definition ........................................................................ 14-93
Transmit Packet Counter Register Definition ..................................................................... 14-94
Transmit Multicast Packet Counter Register Definition ..................................................... 14-94
Transmit Broadcast Packet Counter Register Definition .................................................... 14-95
Transmit Pause Control Frame Counter Register Definition .............................................. 14-95
Transmit Deferral Packet Counter Register Definition....................................................... 14-96
Transmit Excessive Deferral Packet Counter Register Definition...................................... 14-96
Transmit Single Collision Packet Counter Register Definition .......................................... 14-97
Transmit Multiple Collision Packet Counter Register Definition....................................... 14-97
Transmit Late Collision Packet Counter Register Definition ............................................. 14-98
Transmit Excessive Collision Packet Counter Register Definition .................................... 14-98
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Transmit Total Collision Counter Register Definition........................................................ 14-99
Transmit Drop Frame Counter Register Definition ............................................................ 14-99
Transmit Jabber Frame Counter Register Definition ........................................................ 14-100
Transmit FCS Error Counter Register Definition ............................................................. 14-100
Transmit Control Frame Counter Register Definition ...................................................... 14-101
Transmit Oversized Frame Counter Register Definition .................................................. 14-101
Transmit Undersize Frame Counter Register Definition .................................................. 14-102
Transmit Fragment Counter Register Definition .............................................................. 14-102
Carry Register 1 (CAR1) Register Definition................................................................... 14-103
Carry Register 2 (CAR2) Register Definition................................................................... 14-104
Carry Mask Register 1 (CAM1) Register Definition........................................................ 14-105
Carry Mask Register 2 (CAM2) Register Definition........................................................ 14-107
Receive Filer Rejected Packet Counter Register Definition ............................................. 14-108
IGADDRn Register Definition ......................................................................................... 14-109
GADDRn Register Definition........................................................................................... 14-109
FIFOCFG Register Definition .......................................................................................... 14-110
ATTR Register Definition ................................................................................................. 14-112
ATTRELI Register Definition........................................................................................... 14-113
Control Register Definition............................................................................................... 14-115
Status Register Definition ................................................................................................. 14-117
AN Advertisement Register Definition............................................................................. 14-118
AN Link Partner Base Page Ability Register Definition .................................................. 14-120
AN Expansion Register Definition ................................................................................... 14-121
AN Next Page Transmit Register Definition .................................................................... 14-121
AN Link Partner Ability Next Page Register Definition .................................................. 14-122
Extended Status Register Definition ................................................................................. 14-123
Jitter Diagnostics Register Definition ............................................................................... 14-124
TBI Control Register Definition ....................................................................................... 14-125
eTSEC-MII Connection .................................................................................................... 14-127
eTSEC-RMII Connection ................................................................................................. 14-128
eTSEC-GMII Connection ................................................................................................. 14-129
eTSEC-RGMII Connection............................................................................................... 14-130
eTSEC-TBI Connection.................................................................................................... 14-131
eTSEC-RTBI Connection ................................................................................................. 14-132
eTSEC-FIFO (8-Bit) Connection...................................................................................... 14-138
8-Bit GMII-Style Packet FIFO Timing ............................................................................. 14-138
8-Bit Encoded Packet FIFO Timing ................................................................................. 14-139
eTSEC-FIFO (16-Bit) Connection.................................................................................... 14-140
16-Bit GMII-Style Packet FIFO Timing ........................................................................... 14-141
16-Bit Encoded Packet FIFO Timing ............................................................................... 14-142
Definition of Custom Preamble Sequence ........................................................................ 14-148
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Definition of Received Preamble Sequence...................................................................... 14-149
Ethernet Address Recognition Flowchart ......................................................................... 14-150
Sample C Code for Computing eTSEC Hash Table Indices............................................. 14-152
Location of Frame Control Blocks for TOE Parameters .................................................. 14-160
Transmit Frame Control Block ......................................................................................... 14-160
Receive Frame Control Block........................................................................................... 14-162
Structure of the Receive Queue Filer Table ...................................................................... 14-164
Example of eTSEC Memory Structure for BDs ............................................................... 14-172
Buffer Descriptor Ring...................................................................................................... 14-172
Transmit Buffer Descriptor ............................................................................................... 14-173
Mapping of TxBDs to a C Data Structure......................................................................... 14-173
Receive Buffer Descriptor................................................................................................. 14-176
Mapping of RxBDs to a C Data Structure ........................................................................ 14-177
DMA Block Diagram............................................................................................................ 15-1
DMA Operational Flow Chart .............................................................................................. 15-4
DMA Signal Summary.......................................................................................................... 15-5
DMA Mode Registers (MRn) ............................................................................................. 15-10
Status Registers (SRn)......................................................................................................... 15-12
Basic Chaining Mode Flow Chart....................................................................................... 15-14
Extended Current Link Descriptor Address Registers (ECLNDARn) ............................... 15-14
Current Link Descriptor Address Registers (CLNDARn) .................................................. 15-15
Source Attributes Registers (SATRn) ................................................................................. 15-16
Source Address Registers (SARn) ...................................................................................... 15-17
Source Address Registers for RapidIO Maintenance Reads (SARn) ................................. 15-18
Destination Attributes Registers (DATRn) ......................................................................... 15-19
Destination Address Registers (DARn) .............................................................................. 15-20
Destination Address Registers for RapidIO Maintenance Writes (DARn)......................... 15-21
Byte Count Registers (BCRn)............................................................................................. 15-22
Next Link Descriptor Address Registers (NLNDARn) ...................................................... 15-22
Extended Next Link Descriptor Address Registers (ENLNDARn).................................... 15-23
Extended Current List Descriptor Address Registers (ECLSDARn) ................................. 15-24
Current List Descriptor Address Registers (CLSDARn) .................................................... 15-24
Extended Next List Descriptor Address Registers (ENLSDARn)...................................... 15-25
Next List Descriptor Address Registers (NLSDARn) ........................................................ 15-25
Source Stride Registers (SSRn) .......................................................................................... 15-26
Destination Stride Registers (DSRn) .................................................................................. 15-26
DMA General Status Register (DGSR) .............................................................................. 15-27
External Control Interface Timing ...................................................................................... 15-34
Stride Size and Stride Distance ........................................................................................... 15-36
DMA Transaction Flow with DMA Descriptors ................................................................ 15-39
List Descriptor Format ........................................................................................................ 15-40
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Link Descriptor Format....................................................................................................... 15-40
DMA Data Paths ................................................................................................................. 15-42
PCI/X Controller Block Diagram ......................................................................................... 16-2
PCI/X Interface External Signals.......................................................................................... 16-7
PCI/X CFG_ADDR Register .............................................................................................. 16-17
PCI/X CFG_DATA Register ............................................................................................... 16-18
PCI/X INT_ACK Register .................................................................................................. 16-19
PCI/X Outbound Translation Address Registers (POTARn) .............................................. 16-19
PCI/X Outbound Translation Extended Address Registers (POTEARn) ........................... 16-20
PCI/X Outbound Window Base Address Registers (POWBARn) ..................................... 16-20
PCI/X Outbound Window 0 (Default) Attributes Register (POWAR0) ............................. 16-21
PCI/X Outbound Window 1–4 Attributes Registers (POWAR1–POWAR4) ..................... 16-21
PCI/X Inbound Translation Address Registers (PITARn) .................................................. 16-23
PCI/X Inbound Window Base Address Registers............................................................... 16-24
PCI/X Inbound Window Base Extended Address Registers (PIWBEARn) ....................... 16-24
PCI/X Inbound Window Attributes Registers..................................................................... 16-25
PCI/X Error Detect Register (ERR_DR) ............................................................................ 16-27
PCI/X Error Capture Disable Register (ERR_CAP_DR) ................................................... 16-28
PCI/X Error Enable Register (ERR_EN)............................................................................ 16-29
PCI/X Error Attributes Capture Register (ERR_ATTRIB)................................................. 16-30
PCI/X Error Address Capture Register (ERR_ADDR) ...................................................... 16-31
PCI/X Error Extended Address Capture Register (ERR_EXT_ADDR) ............................ 16-31
PCI/X Error Data Low Capture Register (ERR_DL) ......................................................... 16-32
PCI/X Error Data High Capture Register (ERR_DH) ........................................................ 16-32
PCI/X Gasket Timer Register (GAS_TIMR)...................................................................... 16-32
PCI-X Split Completion Timer Register (PCIX_TIMR) .................................................... 16-33
Common PCI and PCI-X Configuration Header ................................................................ 16-34
PCI-X Additional Configuration Registers......................................................................... 16-34
PCI Vendor ID Register ...................................................................................................... 16-34
PCI Device ID Register....................................................................................................... 16-35
PCI Bus Command Register ............................................................................................... 16-35
PCI Bus Status Register ...................................................................................................... 16-37
PCI Revision ID Register.................................................................................................... 16-38
PCI Bus Programming Interface Register........................................................................... 16-38
PCI Subclass Code Register................................................................................................ 16-39
PCI Bus Base Class Code Register ..................................................................................... 16-39
PCI Bus Cache Line Size Register...................................................................................... 16-39
PCI Bus Latency Timer Register ........................................................................................ 16-40
PCI Configuration and Status Register Base Address Register (PCSRBAR) .................... 16-41
32-Bit Memory Base Address Register .............................................................................. 16-41
64-Bit Low Memory Base Address Register ...................................................................... 16-41
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64-Bit High Memory Base Address Register ..................................................................... 16-42
PCI Subsystem Vendor ID Register .................................................................................... 16-42
PCI Subsystem ID Register................................................................................................. 16-43
PCI Bus Capabilities Pointer Register ................................................................................ 16-43
PCI Bus Interrupt Line Register.......................................................................................... 16-43
PCI Bus Interrupt Pin Register............................................................................................ 16-44
PCI Bus Minimum Grant Register (MIN_GNT) ................................................................ 16-44
PCI Bus Maximum Latency Register (MAX_LAT) ........................................................... 16-45
PCI Bus Function Register.................................................................................................. 16-45
PCI Bus Arbiter Configuration Register ............................................................................. 16-46
PCI-X Next Capabilities ID Register.................................................................................. 16-47
PCI-X Capability Pointer Register...................................................................................... 16-47
PCI-X Command Register .................................................................................................. 16-48
PCI-X Status Register ......................................................................................................... 16-48
PCI Arbitration Example .................................................................................................... 16-51
PCI Single-Beat Read Transaction...................................................................................... 16-57
PCI Burst Read Transaction................................................................................................ 16-58
PCI Single-Beat Write Transaction..................................................................................... 16-58
PCI Burst Write Transaction ............................................................................................... 16-59
PCI Target-Initiated Terminations....................................................................................... 16-61
DAC Single-Beat Read Example........................................................................................ 16-63
DAC Burst Read Example .................................................................................................. 16-63
DAC Single-Beat Write Example ....................................................................................... 16-64
DAC Burst Write Example ................................................................................................. 16-64
Standard PCI Configuration Header ................................................................................... 16-65
PCI Type 0 Configuration Translation ................................................................................ 16-68
PCI Parity Operation........................................................................................................... 16-71
PCI_AD[31:0] During PCI-X Burst/DWORD Attribute Phase ......................................... 16-76
Typical PCI-X Write Transaction........................................................................................ 16-77
Burst Memory Write Transaction........................................................................................ 16-78
Memory Read Block Transaction ....................................................................................... 16-79
DWORD (4-Byte) Write Transaction ................................................................................. 16-80
DWORD (4-Byte) Read Transaction .................................................................................. 16-80
Split Response to a Read Transaction ................................................................................. 16-82
Split Response to a DWORD (4-Byte) Write Transaction.................................................. 16-82
Split Completion Transaction Address AD[31:0]............................................................... 16-83
AD[31:0] During PCI-X Split Completion Attribute Phase ............................................... 16-84
PCI-X Type 0 Configuration Translation............................................................................ 16-85
AD[31:0] During PCI-X Configuration Attribute Phase .................................................... 16-86
Address Invariant Byte Ordering—4 bytes Outbound........................................................ 16-91
Address Invariant Byte Ordering—4 bytes Inbound .......................................................... 16-92
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Address Invariant Byte Ordering—8 bytes Outbound........................................................ 16-92
Address Invariant Byte Ordering—2 bytes Inbound .......................................................... 16-92
CFG_DATA Byte Ordering................................................................................................. 16-93
RapidIO Endpoint and RMU ................................................................................................ 17-1
Device Identity Capability Register (DIDCAR) ................................................................. 17-11
Device Information Capability Register (DICAR) ............................................................. 17-12
Assembly Identity Capability Register (AIDCAR) ............................................................ 17-12
Assembly Information Capability Register (AICAR) ........................................................ 17-13
Processing Element Features Capability Register (PEFCAR)............................................ 17-13
Source Operations Capability Register (SOCAR) .............................................................. 17-14
Destination Operations Capability Register (DOCAR) ...................................................... 17-15
Mailbox Command and Status Register (MCSR) ............................................................... 17-17
Port-Write and Doorbell Command and Status Register (PWDCSR) ................................ 17-18
Processing Element Logic Layer Control Command and Status Register (PELLCCSR) .. 17-19
Local Configuration Space Base Address 1 Command and Status
Register (LCSBA1CSR) ................................................................................................ 17-20
Base Device ID Command and Status Register (BDIDCSR) ............................................. 17-21
Host Base Device ID Lock Command and Status Register (HBDIDLCSR)...................... 17-21
Component Tag Command and Status Register (CTCSR) ................................................. 17-22
Port Maintenance Block Header 0 (PMBH0) ..................................................................... 17-22
Port Link Time-Out Control Command and Status Register (PLTOCCSR)....................... 17-23
Port Response Time-Out Control Command and Status Register (PRTOCCSR)............... 17-23
General Control Command and Status Register (GCCSR)................................................. 17-24
Link Maintenance Request Command and Status Register (LMREQCSR)....................... 17-25
Link Maintenance Response Command and Status Register (LMRESPCSR)................... 17-25
Local ackID Status Command and Status Register (LASCSR).......................................... 17-26
Error and Status Command and Status Register (ESCSR) ................................................. 17-27
Control Command and Status Register (CCSR) ................................................................. 17-28
Error Reporting Block Header (ERBH).............................................................................. 17-30
Logical/Transport Layer Error Detect Command and Status Register (LTLEDCSR)........ 17-31
Logical/Transport Layer Error Enable Command and Status Register (LTLEECSR)........ 17-33
Logical/Transport Layer Address Capture Command and Status Register (LTLACCSR). 17-34
Logical/Transport Layer Device ID Capture Command and Status Register
(LTLDIDCCSR) ............................................................................................................. 17-35
Logical/Transport Layer Control Capture Command and Status Register (LTLCCCSR).. 17-36
Error Detect Command and Status Register (EDCSR)....................................................... 17-37
Error Rate Enable Command and Status Register (ERECSR)............................................ 17-37
Error Capture Attributes Command and Status Register (ECACSR) ................................. 17-38
Packet/Control Symbol Error Capture Command and Status Register 0 (PCSECCSR0) .. 17-39
Packet Error Capture Command and Status Register 1 (PECCSR1).................................. 17-40
Packet Error Capture Command and Status Register 2 (PECCSR2).................................. 17-40
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Packet Error Capture Command and Status Register 3 (PECCSR3).................................. 17-41
Error Rate Command and Status Register (ERCSR) .......................................................... 17-41
Error Rate Threshold Command and Status Register (ERTCSR)....................................... 17-42
Logical Layer Configuration Register (LLCR) .................................................................. 17-43
Error/Port-Write Interrupt Status Register (EPWISR)........................................................ 17-44
Logical Retry Error Threshold Configuration Register (LRETCR) ................................... 17-44
Physical Retry Error Threshold Configuration Register (PRETCR) .................................. 17-45
Alternate Device ID Command and Status Register (ADIDCSR)...................................... 17-46
Accept-All Configuration Register (AACR) ...................................................................... 17-46
Logical Outbound Packet Time-to-Live Configuration Register (LOPTTLCR) ................ 17-47
Implementation Error Command and Status Register (IECSR) ......................................... 17-47
Physical Configuration Register (PCR) .............................................................................. 17-48
Serial Link Command and Status Register (SLCSR) ......................................................... 17-48
Serial Link Error Injection Configuration Register (SLEICR) ........................................... 17-49
IP Block Revision Register 1 (IPBRR1)............................................................................. 17-50
IP Block Revision Register 2 (IPBRR2)............................................................................. 17-50
Example of Attribute Aliasing ............................................................................................ 17-52
Example of Multi-Targeting................................................................................................ 17-53
RapidIO Outbound Window Translation Address Registers 0–8 (ROWTARn)................. 17-53
RapidIO Outbound Window Translation Extended Address Registers 0–8 ....................... 17-54
RapidIO Outbound Window Base Address Registers 1–8.................................................. 17-55
RapidIO Outbound Window Attributes Registers 0–8 ....................................................... 17-55
RapidIO Outbound Window Segment 1–3 Registers 1–8 (ROWSnRn)............................. 17-57
RapidIO Inbound Window Translation Address Registers 0–4 (RIWTARn)..................... 17-59
RapidIO Inbound Window Base Address Registers1–4 ..................................................... 17-59
Outbound Message n Mode Registers (OMnMR) .............................................................. 17-62
Outbound Message n Status Registers (OMnSR) ............................................................... 17-64
Extended Outbound Message n Descriptor Queue Dequeue Pointer Address
Registers (EOMnDQDPAR) .......................................................................................... 17-66
Outbound Message n Descriptor Queue Dequeue Pointer Address
Registers (OMnDQDPAR)............................................................................................. 17-66
Extended Outbound Message n Descriptor Queue Enqueue Pointer
Registers (EOMnDQEPAR)........................................................................................... 17-67
Outbound Message n Descriptor Queue Enqueue Pointer Registers (OMnDQEPAR) ...... 17-68
Extended Outbound Message n Source Address Registers (EOMnSAR) .......................... 17-68
Outbound Message n Source Address Registers (OMnSAR)............................................. 17-68
Outbound Message n Destination Port Registers (OMnDPR)............................................ 17-69
Outbound Message n Destination Attributes Registers (OMnDATR)................................ 17-70
Outbound Message n Double Word Count Registers (OMnDCR) ..................................... 17-70
Outbound Message n Retry Error Threshold Configuration Registers (OMnRETCR)...... 17-71
Outbound Message n Multicast Group Registers (OMnMGR) .......................................... 17-72
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Outbound Message n Multicast List Registers (OMnMLR)............................................... 17-72
Inbound Message n Mode Registers (IMnMR) .................................................................. 17-73
Inbound Message n Status Registers (IMnSR) ................................................................... 17-75
Extended Inbound Message n Frame Queue Dequeue Pointer Address
Registers (EIMnFQDPAR)............................................................................................. 17-76
Inbound Message n Frame Queue Dequeue Pointer Address Registers (IMnFQDPAR) ... 17-77
Extended Inbound Message n Frame Queue Enqueue Pointer Address
Registers (EIMnFQEPAR) ............................................................................................. 17-78
Inbound Message n Frame Queue Enqueue Pointer Address Registers (IMnFQEPAR).... 17-78
Inbound Message n Maximum Interrupt Report Interval Registers (IMnMIRIR) ............. 17-79
Outbound Mode Register (ODMR) .................................................................................... 17-79
Outbound Doorbell Status Register (ODSR) ...................................................................... 17-80
Outbound Doorbell Destination Port Registers (ODDPR) ................................................. 17-80
Outbound Doorbell Destination Attributes Register (ODDATR)....................................... 17-81
Outbound Doorbell Retry Error Threshold Configuration Register (ODRETCR)............. 17-82
Inbound Doorbell Mode Register (IDMR) ......................................................................... 17-82
Inbound Doorbell Status Register (IDSR) .......................................................................... 17-84
Extended Inbound Doorbell Queue Dequeue Pointer Address Registers (EIDQDPAR) ... 17-85
Inbound Doorbell Queue Dequeue Pointer Address Registers (IDQDPAR)...................... 17-86
Extended Inbound Doorbell Queue Enqueue Pointer Address Register (EIDQEPAR)...... 17-86
Inbound Doorbell Queue Enqueue Pointer Address Register (IDQEPAR) ........................ 17-87
Inbound Doorbell Maximum Interrupt Report Interval Register (IDMIRIR) .................... 17-87
Inbound Port-Write Mode Register (IPWMR).................................................................... 17-88
Inbound Port-Write Status Register (IPWSR) .................................................................... 17-89
Extended Port-Write Queue Base Address Register (EIPWQBAR) .................................. 17-89
Inbound Port-Write Queue Base Address Register (IPWQBAR)....................................... 17-90
Outbound Frame Queue Structure .................................................................................... 17-149
Descriptor Dequeue Pointer and Descriptor ..................................................................... 17-153
Inbound Message Structure............................................................................................... 17-157
Inbound Doorbell Queue and Pointer Structure................................................................ 17-169
Doorbell Entry Format ...................................................................................................... 17-176
Inbound Port-Write Structure............................................................................................ 17-182
PCI Express Controller Block Diagram................................................................................ 18-2
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) ............................. 18-9
PCI Express Configuration Data Register (PEX_CONFIG_DATA) .................................. 18-10
PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR)............... 18-11
PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR) ............... 18-11
PCI Express Configuration Register (PEX_CONFIG) ....................................................... 18-12
PCI Express PME and Message Detect Register (PEX_PME_MES_DR)......................... 18-13
PCI Express PME and Message Disable Register (PEX_PME_MES_DISR) ................... 18-14
PCI Express PME and Message Interrupt Enable Register (PEX_PME_MES_IER) ........ 18-16
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PCI Express Power Management Command Register (PEX_PMCR) ............................... 18-17
IP Block Revision Register 1 .............................................................................................. 18-18
IP Block Revision Register 2 .............................................................................................. 18-19
RC Outbound Transaction Flow ......................................................................................... 18-20
PCI Express Outbound Translation Address Registers (PEXOTARn) ............................... 18-20
PCI Express Outbound Translation Extended Address Registers (PEXOTEARn) ............ 18-21
PCI Express Outbound Window Base Address Registers (PEXOWBARn) ...................... 18-21
PCI Express Outbound Window Attributes Register 0 (PEXOWAR0).............................. 18-22
PCI Express Outbound Window Attributes Registers 1–4 (PEXOWARn) ........................ 18-22
RC Inbound Transaction Flow ............................................................................................ 18-25
PCI Express Inbound Translation Address Registers (PEXITARn) ................................... 18-25
PCI Express Inbound Window Base Address Registers (PEXIWBARn)........................... 18-26
PCI Express Inbound Window Base Extended Address Registers (PEXIWBEARn) ........ 18-27
PCI Express Inbound Window Attributes Registers (PEXIWARn).................................... 18-27
PCI Express Error Detect Register (PEX_ERR_DR) ......................................................... 18-30
PCI Express Error Interrupt Enable Register (PEX_ERR_EN).......................................... 18-32
PCI Express Error Disable Register (PEX_ERR_DISR).................................................... 18-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)............................... 18-35
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
Internal Source, Outbound Transaction.......................................................................... 18-36
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
External Source, Inbound Transaction ........................................................................... 18-37
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
Internal Source, Outbound Transaction.......................................................................... 18-38
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
External Source, Inbound Transaction ........................................................................... 18-38
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
Internal Source, Outbound Transaction.......................................................................... 18-39
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
External Source, Inbound Transaction ........................................................................... 18-40
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
Internal Source, Outbound Transaction.......................................................................... 18-41
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
External Source, Inbound Transaction ........................................................................... 18-41
PCI Express PCI-Compatible Configuration Header Common Registers.......................... 18-43
PCI Express Vendor ID Register......................................................................................... 18-44
PCI Express Device ID Register ......................................................................................... 18-44
PCI Express Command Register......................................................................................... 18-45
PCI Express Status Register................................................................................................ 18-46
PCI Express Revision ID Register ...................................................................................... 18-47
PCI Express Class Code Register ....................................................................................... 18-48
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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PCI Express Bus Cache Line Size Register ........................................................................ 18-48
PCI Express Bus Latency Timer Register........................................................................... 18-49
PCI Express Bus Latency Timer Register........................................................................... 18-49
PCI Express PCI-Compatible Configuration Header—Type 0........................................... 18-50
PCI Express Base Address Register 0 (PEXCSRBAR)...................................................... 18-51
32-Bit Memory Base Address Register (BAR1)................................................................. 18-51
64-Bit Low Memory Base Address Register ...................................................................... 18-52
64-Bit High Memory Base Address Register ..................................................................... 18-52
PCI Express Subsystem Vendor ID Register ...................................................................... 18-53
PCI Express Subsystem ID Register ................................................................................... 18-53
Capabilities Pointer Register............................................................................................... 18-54
PCI Express Interrupt Line Register ................................................................................... 18-54
PCI Express Interrupt Pin Register ..................................................................................... 18-55
PCI Express Maximum Grant Register (MAX_GNT) ....................................................... 18-55
PCI Express Maximum Latency Register (MAX_LAT)..................................................... 18-56
PCI Express PCI-Compatible Configuration Header—Type 1........................................... 18-56
PCI Express Base Address Register 0 (PEXCSRBAR)...................................................... 18-57
PCI Express Primary Bus Number Register ....................................................................... 18-57
PCI Express Secondary Bus Number Register ................................................................... 18-58
PCI Express Subordinate Bus Number Register................................................................. 18-58
PCI Express I/O Base Register ........................................................................................... 18-59
PCI Express I/O Limit Register .......................................................................................... 18-59
PCI Express Secondary Status Register.............................................................................. 18-60
PCI Express Memory Base Register ................................................................................... 18-61
PCI Express Memory Limit Register.................................................................................. 18-61
PCI Express Prefetchable Memory Base Register .............................................................. 18-62
PCI Express Prefetchable Memory Limit Register............................................................. 18-62
PCI Express Prefetchable Base Upper 32 Bits Register ..................................................... 18-63
PCI Express Prefetchable Limit Upper 32 Bits Register .................................................... 18-63
PCI Express I/O Base Upper 16 Bits Register .................................................................... 18-63
PCI Express I/O Limit Upper 16 Bits Register................................................................... 18-64
Capabilities Pointer Register............................................................................................... 18-64
PCI Express Interrupt Line Register ................................................................................... 18-65
PCI Express Interrupt Pin Register ..................................................................................... 18-65
PCI Express Bridge Control Register ................................................................................. 18-66
PCI Compatible Device-Specific Configuration Space ...................................................... 18-67
PCI Express Power Management Capability ID Register .................................................. 18-68
PCI Express Power Management Capabilities Register ..................................................... 18-68
PCI Express Power Management Status and Control Register........................................... 18-69
PCI Express Power Management Data Register................................................................. 18-69
PCI Express Capability ID Register.................................................................................... 18-70
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PCI Express Capabilities Register ...................................................................................... 18-70
PCI Express Device Capabilities Register .......................................................................... 18-71
PCI Express Device Control Register ................................................................................. 18-71
PCI Express Device Status Register ................................................................................... 18-72
PCI Express Link Capabilities Register.............................................................................. 18-73
PCI Express Link Control Register..................................................................................... 18-73
PCI Express Link Status Register ....................................................................................... 18-74
PCI Express Slot Capabilities Register ............................................................................... 18-75
PCI Express Slot Control Register...................................................................................... 18-75
PCI Express Slot Status Register ........................................................................................ 18-76
PCI Express Root Control Register .................................................................................... 18-77
PCI Express Root Status Register ....................................................................................... 18-77
PCI Express Capability ID Register.................................................................................... 18-78
PCI Express MSI Message Control Register ...................................................................... 18-78
PCI Express MSI Message Address Register ..................................................................... 18-79
PCI Express MSI Message Upper Address Register .......................................................... 18-79
PCI Express MSI Message Data Register........................................................................... 18-79
PCI Express Extended Configuration Space....................................................................... 18-80
PCI Express Advanced Error Reporting Capability ID Register ........................................ 18-81
PCI Express Uncorrectable Error Status Register............................................................... 18-81
PCI Express Uncorrectable Error Mask Register ............................................................... 18-82
PCI Express Uncorrectable Error Severity Register ........................................................... 18-83
PCI Express Correctable Error Status Register................................................................... 18-84
PCI Express Correctable Error Mask Register ................................................................... 18-84
PCI Express Advanced Error Capabilities and Control Register........................................ 18-85
PCI Express Header Log Register ...................................................................................... 18-86
PCI Express Root Error Command Register....................................................................... 18-87
PCI Express Root Error Command Register....................................................................... 18-87
PCI Express Correctable Error Source ID Register ............................................................ 18-88
PCI Express Correctable Error Source ID Register ............................................................ 18-88
PCI Express LTSSM State Status Register (PEX_LTSSM_STAT) .................................... 18-89
PCI Express IP Block Core Clock Ratio Register (PEX_GCLK_RATIO) ........................ 18-91
PCI Express Power Management Timer Register (PEX_PM_TIMER) ............................. 18-91
PCI Express PME Time-Out Register (PEX_PME_TIMEOUT) ....................................... 18-92
PCI Express Subsystem Vendor ID Update Register (PEX_SSVID_UPDATE)................ 18-93
PCI Express Configuration Ready Register (PEX_CFG_READY) ................................... 18-93
PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR) ................... 18-94
PCI Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK)................................ 18-95
Requestor/Completer Relationship ..................................................................................... 18-96
PCI Express High-Level Layering...................................................................................... 18-96
PCI Express Packet Flow.................................................................................................... 18-97
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Figures
Figure
Number
18-125
18-126
18-127
18-128
18-129
18-130
19-1
19-2
19-3
19-4
19-5
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19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
19-34
19-35
Page
Number
Title
Address Invariant Byte Ordering—4 bytes Outbound........................................................ 18-98
Address Invariant Byte Ordering—4 bytes Inbound .......................................................... 18-98
Address Invariant Byte Ordering—8 bytes Outbound........................................................ 18-99
Address Invariant Byte Ordering—2 bytes Inbound .......................................................... 18-99
PEX_CONFIG_DATA Byte Ordering................................................................................ 18-99
WAKE Generation Example ............................................................................................. 18-108
SEC Connected to System Bus ............................................................................................. 19-3
SEC Functional Modules ...................................................................................................... 19-3
Descriptor Format ............................................................................................................... 19-16
Header Dword ..................................................................................................................... 19-17
Pointer Dword ..................................................................................................................... 19-20
Link Table Entry ................................................................................................................. 19-21
Descriptors, Link Tables, and Data Parcels ........................................................................ 19-23
PKEU Mode Register.......................................................................................................... 19-26
PKEU Key Size Register .................................................................................................... 19-28
PKEU AB Size Register ..................................................................................................... 19-28
PKEU Data Size Register ................................................................................................... 19-29
PKEU Reset Control Register............................................................................................. 19-29
PKEU Status Register ......................................................................................................... 19-30
PKEU Interrupt Status Register .......................................................................................... 19-31
PKEU Interrupt Control Register........................................................................................ 19-32
PKEU EU Go Register........................................................................................................ 19-33
DEU Mode Register............................................................................................................ 19-34
DEU Key Size Register....................................................................................................... 19-35
DEU Data Size Register...................................................................................................... 19-35
DEU Reset Control Register ............................................................................................... 19-36
DEU Status Register ........................................................................................................... 19-36
DEU Interrupt Status Register ............................................................................................ 19-38
DEU Interrupt Control Register .......................................................................................... 19-39
DEU EU Go Register .......................................................................................................... 19-41
AFEU Mode Register.......................................................................................................... 19-42
AFEU Key Size Register .................................................................................................... 19-43
AFEU Context/Data Size Register...................................................................................... 19-44
AFEU Reset Control Register............................................................................................. 19-45
AFEU Status Register ......................................................................................................... 19-45
AFEU Interrupt Status Register .......................................................................................... 19-46
AFEU Interrupt Control Register........................................................................................ 19-48
AFEU EU Go Register........................................................................................................ 19-49
MDEU Mode Register in Old Configuration (NEW = 0)................................................... 19-51
MDEU Mode Register in New Configuration (NEW = 1) ................................................. 19-52
MDEU Key Size Register ................................................................................................... 19-54
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Figures
Figure
Number
19-36
19-37
19-38
19-39
19-40
19-41
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19-68
19-69
19-70
19-71
19-72
19-73
19-74
19-75
19-76
Title
Page
Number
MDEU Data Size Register .................................................................................................. 19-55
MDEU Reset Control Register ........................................................................................... 19-55
MDEU Status Register........................................................................................................ 19-56
MDEU Interrupt Status Register ......................................................................................... 19-57
MDEU Interrupt Control Register ...................................................................................... 19-58
MDEU ICV Size Register................................................................................................... 19-59
MDEU EU Go Register ...................................................................................................... 19-60
MDEU Context Register ..................................................................................................... 19-61
RNG Mode Register............................................................................................................ 19-63
RNG Data Size Register ..................................................................................................... 19-63
RNG Reset Control Register............................................................................................... 19-63
RNG Status Register ........................................................................................................... 19-64
RNG Interrupt Status Register ............................................................................................ 19-65
RNG Interrupt Control Register.......................................................................................... 19-66
RNG EU Go Register.......................................................................................................... 19-67
AESU Mode Register.......................................................................................................... 19-67
AESU Key Size Register .................................................................................................... 19-69
AESU Data Size Register ................................................................................................... 19-70
AESU Reset Control Register............................................................................................. 19-70
AESU Status Register ......................................................................................................... 19-71
AESU Interrupt Status Register .......................................................................................... 19-72
AESU Interrupt Control Register........................................................................................ 19-73
AESU EU Go Register........................................................................................................ 19-75
AESU Context Register ...................................................................................................... 19-75
AESU CCM Context Registers........................................................................................... 19-77
KEU Mode Register............................................................................................................ 19-80
KEU Key Size Register....................................................................................................... 19-81
KEU Data Size Register...................................................................................................... 19-82
KEU Reset Control Register ............................................................................................... 19-82
KEU Status Register ........................................................................................................... 19-83
KEU Interrupt Status Register ............................................................................................ 19-84
KEU Interrupt Control Register .......................................................................................... 19-86
KEU Data Out Register (F9 MAC)..................................................................................... 19-87
KEU EU Go Register .......................................................................................................... 19-88
KEU IV_1 Register ............................................................................................................. 19-88
KEU IV_2 Register (Fresh) ................................................................................................ 19-89
KEU Key Data Register_1 (CK-high) ................................................................................ 19-90
KEU Key Data Register_2 (CK-Low) ................................................................................ 19-90
KEU Key Data Register_3 (IK-high).................................................................................. 19-90
KEU Key Data Register_4 (IK-low)................................................................................... 19-90
Crypto-Channel Configuration Register (CCCR)............................................................... 19-92
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxv
Figures
Figure
Number
19-77
19-78
19-79
19-80
19-81
19-82
19-83
19-84
19-85
19-86
19-87
19-88
19-89
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
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20-14
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20-21
20-22
20-23
20-24
20-25
20-26
20-27
20-28
Page
Number
Title
Header Dword Writeback Format ....................................................................................... 19-94
Crypto-Channel Pointer Status Register ............................................................................. 19-95
Crypto-Channel Current Descriptor Pointer Register ....................................................... 19-100
Fetch FIFO ........................................................................................................................ 19-101
Descriptor Buffer Format.................................................................................................. 19-102
Link Table Buffer .............................................................................................................. 19-103
EU Assignment Status Register (EUASR) ....................................................................... 19-109
Interrupt Mask Register (IMR) ........................................................................................ 19-110
Interrupt Status Register (ISR)...........................................................................................19-111
Interrupt Clear Register (ICR) .......................................................................................... 19-112
ID Register (ID) ................................................................................................................ 19-113
IP Block Revision Register ............................................................................................... 19-113
Master Control Register (MCR) ....................................................................................... 19-114
POR PLL Status Register (PORPLLSR) .............................................................................. 20-5
POR Boot Mode Status Register (PORBMSR) .................................................................... 20-6
POR I/O Impedance Status and Control Register (PORIMPSCR) ....................................... 20-7
POR Device Status Register (PORDEVSR) ......................................................................... 20-8
POR Debug Mode Status Register (PORDBGMSR).......................................................... 20-10
POR Device Status Register 2 (PORDEVSR2) .................................................................. 20-11
POR Configuration Register (GPPORCR) ......................................................................... 20-11
General-Purpose I/O Control Register (GPIOCR).............................................................. 20-12
General-Purpose Output Data Register (GPOUTDR) ........................................................ 20-13
General-Purpose Output Data Register (GPINDR) ............................................................ 20-14
Alternate Function Pin Multiplex Control Register (PMUXCR) ....................................... 20-14
Device Disable Register (DEVDISR)................................................................................. 20-15
Power Management Control and Status Register (POWMGTCSR) ................................... 20-17
Machine Check Summary Register (MCPSUMR) ............................................................. 20-19
Reset Request Status and Control Register (RSTRSCR).................................................... 20-20
Processor Version Register (PVR) ...................................................................................... 20-20
System Version Register (SVR).......................................................................................... 20-21
Reset Control Register (RSTCR)........................................................................................ 20-22
LBC Voltage Select Control Register (LBCVSELCR)....................................................... 20-22
DDR Calibration Status Register (DDRCSR)..................................................................... 20-23
DDR Control Driver Register (DDRCDR) ......................................................................... 20-24
DDR Clock Disable Register (DDRCLKDR) .................................................................... 20-25
Clock Out Control Register (CLKOCR)............................................................................. 20-25
SerDes Control Register 0 (SRDSCR0).............................................................................. 20-26
SerDes Control Register 1 (SRDSCR1).............................................................................. 20-27
TSEC12 I/O Overdrive Control Register (TSEC12IOOVCR) ........................................... 20-28
TSEC34 Overdrive Control Register (TSEC34IOOVCR) ................................................. 20-29
e500 Core Power Management State Diagram ................................................................... 20-30
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Figures
Figure
Number
20-29
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
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22-22
22-23
A-1
B-1
C-1
Title
Page
Number
MPC8548E Power Management Handshaking Signals...................................................... 20-34
Performance Monitor Block Diagram................................................................................... 21-2
Performance Monitor Global Control Register (PMGC0).................................................... 21-5
Performance Monitor Local Control Register A0 (PMLCA0) ............................................. 21-6
Performance Monitor Local Control A Registers (PMLCA1–PMLCA9)............................ 21-6
Performance Monitor Local Control Register B0 (PMLCB0).............................................. 21-7
Performance Monitor Local Control Register B (PMLCB1–PMLCB9) .............................. 21-8
Performance Monitor Counter Register 0 (PMC0)............................................................. 21-10
Performance Monitor Counter Register (PMC1–PMC9) ................................................... 21-10
Duration Threshold Event Sequence Timing Diagram ....................................................... 21-12
Burst Size, Distance, Granularity, and Burstiness Counting............................................... 21-13
Burstiness Counting Timing Diagram ................................................................................ 21-15
Debug and Watchpoint Monitor Block Diagram .................................................................. 22-2
Watchpoint Monitor Control Register 0 (WMCR0) ........................................................... 22-11
Watchpoint Monitor Control Register 1 (WMCR1) ........................................................... 22-12
Watchpoint Monitor Address Register (WMAR) ............................................................... 22-13
Watchpoint Monitor Address Mask Register (WMAMR).................................................. 22-13
Watchpoint Monitor Transaction Mask Register (WMTMR)............................................. 22-14
Watchpoint Monitor Status Register (WMSR) ................................................................... 22-15
Trace Buffer Control Register 0 (TBCR0).......................................................................... 22-16
Trace Buffer Control Register 1 (TBCR1).......................................................................... 22-17
Trace Buffer Address Register (TBAR).............................................................................. 22-18
Trace Buffer Address Mask Register (TBAMR) ................................................................ 22-19
Trace Buffer Transaction Mask Register (TBTMR) ........................................................... 22-19
Trace Buffer Status Register (TBSR).................................................................................. 22-20
Trace Buffer Access Control Register (TBACR)) .............................................................. 22-21
Trace Buffer Read High Register (TBADHR).................................................................... 22-21
Trace Buffer Access Data Register (TBADR) .................................................................... 22-22
Programmed Context ID Register (PCIDR) ....................................................................... 22-23
Current Context ID Register (CCIDR) ............................................................................... 22-23
Trigger Out Source Register (TOSR).................................................................................. 22-24
e500 Coherency Module Dispatch (CMD) Trace Buffer Entry.......................................... 22-28
DDR Trace Buffer Entry ..................................................................................................... 22-29
PCI Trace Buffer Entry ....................................................................................................... 22-29
PCI Express Trace Buffer Entry.......................................................................................... 22-30
MPC8547E Block Diagram ................................................................................................... A-2
MPC8545E Block Diagram ....................................................................................................B-2
MPC8543E Block Diagram ....................................................................................................C-2
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Figures
Figure
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Title
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Tables
Table
Number
Title
Page
Number
Tables
i
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
Acronyms and Abbreviated Terms............................................................................................cx
Available L2 Cache/SRAM Configurations ......................................................................... 1-15
Supported eTSEC1 and eTSEC2 Configurations ................................................................. 1-21
Supported eTSEC3 and eTSEC4 Configurations ................................................................. 1-22
Target Interface Codes ............................................................................................................ 2-1
Local Access Windows Example............................................................................................ 2-2
Format of ATMU Window Definitions................................................................................... 2-3
Local Access Register Memory Map...................................................................................... 2-5
LAIPBRR1 Field Descriptions ............................................................................................... 2-6
LAIPBRR2 Field Descriptions ............................................................................................... 2-6
LAWBARn Field Descriptions ............................................................................................... 2-7
LAWARn Field Descriptions .................................................................................................. 2-7
Overlapping Local Access Windows ...................................................................................... 2-8
Local Memory Configuration, Control, and Status Register Summary................................ 2-12
Memory Map......................................................................................................................... 2-17
MPC8548E Signal Reference by Functional Block................................................................ 3-5
MPC8548E Alphabetical Signal Reference.......................................................................... 3-12
MPC8548E Reset Configuration Signals.............................................................................. 3-19
Output Signal States During System Reset ........................................................................... 3-20
Signal Summary ...................................................................................................................... 4-1
System Control Signals—Detailed Signal Descriptions ......................................................... 4-2
Clock Signals—Detailed Signal Descriptions ........................................................................ 4-3
Local Configuration Control Register Map ............................................................................ 4-4
CCSRBAR Bit Settings .......................................................................................................... 4-5
ALTCBAR Bit Settings........................................................................................................... 4-6
ALTCAR Bit Settings ............................................................................................................. 4-6
BPTR Bit Settings ................................................................................................................... 4-7
CCB Clock PLL Ratio .......................................................................................................... 4-11
e500 Core Clock PLL Ratios ................................................................................................ 4-12
Boot ROM Location.............................................................................................................. 4-12
Host/Agent Configuration..................................................................................................... 4-13
I/O Port Selection.................................................................................................................. 4-14
CPU Boot Configuration....................................................................................................... 4-15
Boot Sequencer Configuration.............................................................................................. 4-15
DDR DRAM Type ................................................................................................................ 4-16
eTSEC1/eTSEC2 Width Configuration ................................................................................ 4-16
eTSEC3/eTSEC4 Width Configuration ................................................................................ 4-17
eTSEC1 Protocol Configuration ........................................................................................... 4-18
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Tables
Table
Number
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
Page
Number
Title
eTSEC2 Protocol Configuration ........................................................................................... 4-18
eTSEC3 Protocol Configuration ........................................................................................... 4-19
eTSEC4 Protocol Configuration ........................................................................................... 4-19
RapidIO Device ID ............................................................................................................... 4-19
RapidIO System Size ............................................................................................................ 4-20
PCI1/PCI-X Clock Select...................................................................................................... 4-20
PCI2 Clock Select ................................................................................................................. 4-21
PCI1 Speed Configuration .................................................................................................... 4-21
PCI2 Speed Configuration .................................................................................................... 4-21
PCI-32 Configuration............................................................................................................ 4-21
PCI1/PCI-X I/O Impedance .................................................................................................. 4-22
PCI2 I/O Impedance.............................................................................................................. 4-22
PCI1/PCI-X Arbiter Configuration....................................................................................... 4-22
PCI2 Arbiter Configuration .................................................................................................. 4-22
PCI Debug Configuration ..................................................................................................... 4-23
PCI1/PCI-X Configuration ................................................................................................... 4-23
Memory Debug Configuration.............................................................................................. 4-23
DDR Debug Configuration ................................................................................................... 4-24
General-Purpose POR Configuration.................................................................................... 4-24
SerDes Enable POR Configuration....................................................................................... 4-25
High Speed Interface Clocking ............................................................................................. 4-27
Device Revision Level Cross-Reference ................................................................................ 5-4
Performance Monitor Instructions ........................................................................................ 5-12
Cache Locking Instructions .................................................................................................. 5-12
Scalar and Vector Embedded Floating-Point APU Instructions ........................................... 5-12
BTB Locking Instructions..................................................................................................... 5-13
Interrupt Registers................................................................................................................. 5-21
Interrupt Vector Registers and Exception Conditions........................................................... 5-22
Differences Between the e500 Core and the PowerQUICC III Core Implementation ........ 5-32
Base and Embedded Category Special-Purpose Registers (by SPR Abbreviation)................ 6-4
Additional SPRs (by SPR Abbreviation) ................................................................................ 6-7
XER Field Description............................................................................................................ 6-9
BI Operand Settings for CR Fields ......................................................................................... 6-9
CR0 Bit Descriptions ............................................................................................................ 6-11
MSR Field Descriptions........................................................................................................ 6-12
PVR Field Descriptions ........................................................................................................ 6-14
SVR Field Descriptions ........................................................................................................ 6-14
TCR Field Descriptions ........................................................................................................ 6-15
TSR Field Descriptions ......................................................................................................... 6-16
IVOR Assignments ............................................................................................................... 6-18
ESR Field Descriptions ......................................................................................................... 6-19
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Tables
Table
Number
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
1
7-2
7-3
7-4
7-5
7-6
7-7
Title
Page
Number
MCSR Field Descriptions ..................................................................................................... 6-21
SPR Assignments ................................................................................................................. 6-22
BBEAR Field Descriptions ................................................................................................... 6-23
BBTAR Field Descriptions ................................................................................................... 6-23
BUCSR Field Descriptions ................................................................................................... 6-24
HID0 Field Descriptions ....................................................................................................... 6-25
HID1 Field Descriptions ....................................................................................................... 6-26
L1CSR0 Field Descriptions .................................................................................................. 6-28
L1CSR1 Field Descriptions .................................................................................................. 6-29
L1CFG0 Field Descriptions .................................................................................................. 6-30
L1CFG1 Field Descriptions .................................................................................................. 6-31
MMUCSR0 Field Descriptions............................................................................................. 6-32
MMUCFG Field Descriptions .............................................................................................. 6-33
TLB0CFG Field Descriptions ............................................................................................... 6-33
TLB1CFG Field Descriptions ............................................................................................... 6-34
MAS0 Field Descriptions—MMU Read/Write and Replacement Control .......................... 6-35
MAS1 Field Descriptions—Descriptor Context and Configuration Control........................ 6-36
MAS2 Field Descriptions—EPN and Page Attributes ......................................................... 6-36
MAS3 Field Descriptions–RPN and Access Control ........................................................... 6-37
MAS4 Field Descriptions—Hardware Replacement Assist Configuration.......................... 6-38
MAS6—TLB Search Context Register 0.............................................................................. 6-39
MAS 7 Field Descriptions—High Order RPN ..................................................................... 6-39
DBCR0 Field Descriptions ................................................................................................... 6-40
DBCR1 Field Descriptions ................................................................................................... 6-41
DBCR2 Field Descriptions ................................................................................................... 6-42
DBSR Field Descriptions...................................................................................................... 6-44
SPEFSCR Field Descriptions................................................................................................ 6-45
ACC FIeld Descriptions........................................................................................................ 6-47
Supervisor-Level PMRs (PMR[5] = 1) ................................................................................. 6-48
User-Level PMRs (PMR[5] = 0) (Read Only)...................................................................... 6-48
PMGC0 Field Descriptions ................................................................................................... 6-49
PMLCa0–PMLCa3 Field Descriptions ................................................................................. 6-50
PMLCb0–PMLCb3 Field Descriptions ................................................................................ 6-51
PMC0–PMC3 Field Descriptions ......................................................................................... 6-52
Available L2 Cache/SRAM Configurations ........................................................................... 7-3
Way Selection for SRAM Accesses........................................................................................ 7-6
L2/SRAM Memory-Mapped Registers................................................................................... 7-9
L2CTL Field Descriptions .................................................................................................... 7-10
L2CEWARn Field Descriptions............................................................................................ 7-14
L2CEWAREAn Field Descriptions ...................................................................................... 7-14
L2CEWCRn Field Descriptions............................................................................................ 7-15
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Tables
Table
Number
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
Page
Number
Title
L2SRBARn Field Descriptions............................................................................................. 7-16
L2SRBAREAn Field Descriptions ....................................................................................... 7-17
L2ERRINJHI Field Description............................................................................................ 7-18
L2ERRINJLO Field Description .......................................................................................... 7-19
L2ERRINJCTL Field Descriptions....................................................................................... 7-19
L2CAPTDATAHI Field Description..................................................................................... 7-20
L2CAPTDATALO Field Description.................................................................................... 7-20
L2CAPTECC Field Descriptions .......................................................................................... 7-21
L2ERRDET Field Descriptions ............................................................................................ 7-21
L2ERRDIS Field Descriptions.............................................................................................. 7-22
L2ERRINTEN Field Descriptions ........................................................................................ 7-23
L2ERRATTR Field Descriptions .......................................................................................... 7-23
L2ERRADDRH Field Description ....................................................................................... 7-24
L2ERRADDRL Field Description........................................................................................ 7-25
L2ERRCTL Field Descriptions ............................................................................................ 7-25
Fastest Read Timing—Hit in L2 ........................................................................................... 7-27
PLRU Bit Update Algorithm ................................................................................................ 7-32
PLRU-Based Victim Selection Mechanism .......................................................................... 7-33
L2 Cache States..................................................................................................................... 7-35
State Transitions Due to Core-Initiated Transactions ........................................................... 7-35
State Transitions Due to System-Initiated Transactions ....................................................... 7-38
L2 Cache ECC Syndrome Encoding..................................................................................... 7-39
L2 Cache ECC Syndrome Encoding (Check Bits) ............................................................... 7-40
ECM Memory Map................................................................................................................. 8-3
EEBACR Field Descriptions .................................................................................................. 8-4
EEBPCR Field Descriptions ................................................................................................... 8-4
EIPBRR1 Field Descriptions .................................................................................................. 8-5
EIPBRR2 Field Descriptions .................................................................................................. 8-6
EEDR Field Descriptions........................................................................................................ 8-6
EEER Field Descriptions ........................................................................................................ 8-7
EEATR Field Descriptions...................................................................................................... 8-7
EELADR Field Descriptions .................................................................................................. 8-8
EEHADR Field Descriptions .................................................................................................. 8-9
DDR Memory Interface Signal Summary .............................................................................. 9-3
Memory Address Signal Mappings......................................................................................... 9-5
Memory Interface Signals—Detailed Signal Descriptions ..................................................... 9-6
Clock Signals—Detailed Signal Descriptions ........................................................................ 9-9
DDR Memory Controller Memory Map............................................................................... 9-10
CSn_BNDS Field Descriptions............................................................................................. 9-12
CSn_CONFIG Field Descriptions ........................................................................................ 9-13
TIMING_CFG_3 Field Descriptions .................................................................................... 9-14
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
lxxxii
Freescale Semiconductor
Tables
Table
Number
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44
9-45
9-46
9-47
9-48
Title
Page
Number
TIMING_CFG_0 Field Descriptions .................................................................................... 9-15
TIMING_CFG_1 Field Descriptions .................................................................................... 9-16
TIMING_CFG_2 Field Descriptions .................................................................................... 9-19
DDR_SDRAM_CFG Field Descriptions.............................................................................. 9-21
DDR_SDRAM_CFG_2 Field Descriptions.......................................................................... 9-24
DDR_SDRAM_MODE Field Descriptions.......................................................................... 9-25
DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 9-26
DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 9-27
Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 9-29
DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 9-29
DDR_DATA_INIT Field Descriptions ................................................................................. 9-30
DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 9-30
DDR_INIT_ADDR Field Descriptions ................................................................................ 9-31
DDR_INIT_EXT_ADDR Field Descriptions....................................................................... 9-32
DDR_IP_REV1 Field Descriptions ...................................................................................... 9-32
DDR_IP_REV2 Field Descriptions ...................................................................................... 9-33
DATA_ERR_INJECT_HI Field Descriptions....................................................................... 9-33
DATA_ERR_INJECT_LO Field Descriptions ..................................................................... 9-33
ERR_INJECT Field Descriptions ......................................................................................... 9-34
CAPTURE_DATA_HI Field Descriptions............................................................................ 9-34
CAPTURE_DATA_LO Field Descriptions........................................................................... 9-35
CAPTURE_ECC Field Descriptions .................................................................................... 9-35
ERR_DETECT Field Descriptions ....................................................................................... 9-36
ERR_DISABLE Field Descriptions...................................................................................... 9-37
ERR_INT_EN Field Descriptions ........................................................................................ 9-37
CAPTURE_ATTRIBUTES Field Descriptions .................................................................... 9-38
CAPTURE_ADDRESS Field Descriptions .......................................................................... 9-39
CAPTURE_EXT_ADDRESS Field Descriptions ................................................................ 9-40
ERR_SBE Field Descriptions ............................................................................................... 9-40
Byte Lane to Data Relationship ............................................................................................ 9-45
Supported DDR2 SDRAM Device Configurations .............................................................. 9-46
DDR1 Address Multiplexing for 64-Bit Data Bus with Interleaving Disabled.................... 9-47
DDR1 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled.................... 9-48
DDR2 Address Multiplexing for 64-Bit Data Bus with Interleaving Disabled.................... 9-49
DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled.................... 9-50
Example of Address Multiplexing for 64-Bit Data Bus Interleaving Between
Two Banks ....................................................................................................................... 9-51
Example of Address Multiplexing for 64-Bit Data Bus Interleaving Between Four Banks 9-52
DDR SDRAM Command Table............................................................................................ 9-53
DDR SDRAM Interface Timing Intervals ............................................................................ 9-54
DDR SDRAM Power-Saving Modes Refresh Configuration............................................... 9-62
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxxiii
Tables
Table
Number
9-49
9-50
9-51
9-52
9-53
9-54
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-26
10-27
10-28
10-29
10-30
10-31
10-32
10-33
10-34
10-35
Page
Number
Title
Memory Controller–Data Beat Ordering .............................................................................. 9-64
DDR SDRAM ECC Syndrome Encoding ............................................................................ 9-66
DDR SDRAM ECC Syndrome Encoding (Check Bits) ....................................................... 9-67
Memory Controller Errors .................................................................................................... 9-68
Memory Interface Configuration Register Initialization Parameters.................................... 9-68
Programming Differences Between Memory Types............................................................. 9-69
Processor Interrupts Generated Outside the Core—Types and Sources ............................... 10-2
e500 Core-Generated Interrupts that Cause a Wake-Up ....................................................... 10-3
Internal Interrupt Sources...................................................................................................... 10-5
PIC Interface Signals ............................................................................................................ 10-6
Interrupt Signals—Detailed Signal Descriptions .................................................................. 10-6
PIC Register Address Map.................................................................................................... 10-8
BRR1 Field Descriptions .................................................................................................... 10-17
BRR2 Field Descriptions .................................................................................................... 10-17
FRR Field Descriptions....................................................................................................... 10-18
GCR Field Descriptions ...................................................................................................... 10-18
VIR Field Descriptions ....................................................................................................... 10-19
PIR Field Descriptions ........................................................................................................ 10-20
IPIVPRn Field Descriptions................................................................................................ 10-20
SVR Field Descriptions ...................................................................................................... 10-21
TFRR Field Descriptions .................................................................................................... 10-22
GTCCRn Field Descriptions ............................................................................................... 10-22
GTBCRn Field Descriptions ............................................................................................... 10-23
GTVPRn Field Descriptions ............................................................................................... 10-23
GTDRn Field Descriptions.................................................................................................. 10-24
Parameters for Hourly Interrupt Timer Cascade Example.................................................. 10-25
TCR Field Descriptions ...................................................................................................... 10-25
ERQSR Field Descriptions ................................................................................................. 10-27
IRQSR0 Field Descriptions ................................................................................................ 10-27
IRQSR1 Field Descriptions ................................................................................................ 10-28
IRQSR2 Field Descriptions ................................................................................................ 10-28
CISR0 Field Descriptions ................................................................................................... 10-29
CISR1 Field Descriptions ................................................................................................... 10-29
CISR2 Field Descriptions ................................................................................................... 10-30
PMnMR0 Field Descriptions .............................................................................................. 10-31
PMnMR1 Field Descriptions .............................................................................................. 10-31
PMnMR2 Field Descriptions .............................................................................................. 10-32
MSGRn Field Descriptions................................................................................................. 10-32
MER Field Descriptions...................................................................................................... 10-33
MSR Field Descriptions...................................................................................................... 10-33
MSIRs Field Descriptions ................................................................................................... 10-34
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
lxxxiv
Freescale Semiconductor
Tables
Table
Number
10-36
10-37
10-38
10-39
10-40
10-41
10-42
10-43
10-44
10-45
10-46
10-47
10-48
10-49
10-50
10-51
10-52
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
Title
Page
Number
MSISR Field Descriptions .................................................................................................. 10-35
MSIIR Field Descriptions ................................................................................................... 10-35
MSIVPRn Field Descriptions ............................................................................................. 10-36
MSIDRn Field Descriptions................................................................................................ 10-36
EIVPRn Field Descriptions................................................................................................. 10-37
EIDRn Field Descriptions................................................................................................... 10-38
IIVPRn Field Descriptions.................................................................................................. 10-39
IIDRn Field Descriptions .................................................................................................... 10-40
MIVPRn Field Descriptions................................................................................................ 10-41
MIDRn Field Descriptions.................................................................................................. 10-41
Per-CPU Registers—Private Access Address Offsets ........................................................ 10-42
IPIDRn Field Descriptions.................................................................................................. 10-44
CTPR Field Descriptions .................................................................................................... 10-44
WHOAMI Field Descriptions ............................................................................................. 10-45
IACK Field Descriptions .................................................................................................... 10-46
EOI Field Descriptions........................................................................................................ 10-46
PCI Express INTx/IRQn Sharing........................................................................................ 10-50
I2C Interface Signal Descriptions ......................................................................................... 11-3
I2C Interface Signal—Detailed Signal Descriptions............................................................. 11-4
I2C Memory Map .................................................................................................................. 11-5
I2CADR Field Descriptions.................................................................................................. 11-6
I2CFDR Field Descriptions .................................................................................................. 11-7
I2CCR Field Descriptions ..................................................................................................... 11-8
I2CSR Field Descriptions ..................................................................................................... 11-9
I2CDR Field Descriptions................................................................................................... 11-10
I2CDFSRR Field Descriptions.............................................................................................11-11
DUART Signal Overview ..................................................................................................... 12-3
DUART Signals—Detailed Signal Descriptions .................................................................. 12-3
DUART Register Summary .................................................................................................. 12-5
URBR Field Descriptions ..................................................................................................... 12-6
UTHR Field Descriptions ..................................................................................................... 12-7
UDMB Field Descriptions .................................................................................................... 12-7
UDLB Field Descriptions ..................................................................................................... 12-8
Baud Rate Examples ............................................................................................................. 12-8
UIER Field Descriptions ....................................................................................................... 12-9
UIIR Field Descriptions ...................................................................................................... 12-10
UIIR IID Bits Summary...................................................................................................... 12-11
UFCR Field Descriptions.................................................................................................... 12-12
ULCR Field Descriptions.................................................................................................... 12-13
Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] .................................. 12-14
UMCR Field Descriptions .................................................................................................. 12-14
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxxv
Tables
Table
Number
12-16
12-17
12-18
12-19
12-20
12-21
12-22
12-23
12-24
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
13-26
13-27
13-28
13-29
13-30
13-31
13-32
Page
Number
Title
ULSR Field Descriptions .................................................................................................... 12-15
UMSR Field Descriptions................................................................................................... 12-16
USCR Field Descriptions.................................................................................................... 12-17
UAFR Field Descriptions.................................................................................................... 12-18
UDSR Field Descriptions.................................................................................................... 12-18
UDSR[TXRDY] Set Conditions ......................................................................................... 12-19
UDSR[TXRDY] Cleared Conditions.................................................................................. 12-19
UDSR[RXRDY] Set Conditions......................................................................................... 12-19
UDSR[RXRDY] Cleared .................................................................................................... 12-19
Signal Properties—Summary................................................................................................ 13-4
Local Bus Controller Detailed Signal Descriptions .............................................................. 13-5
Local Bus Controller Memory Map...................................................................................... 13-9
BRn Field Descriptions....................................................................................................... 13-11
Memory Bank Sizes in Relation to Address Mask ............................................................ 13-12
ORn—GPCM Field Descriptions ....................................................................................... 13-13
ORn—UPM Field Descriptions .......................................................................................... 13-15
ORn—SDRAM Field Descriptions .................................................................................... 13-16
MAR Field Descriptions ..................................................................................................... 13-17
MxMR Field Descriptions................................................................................................... 13-17
MRTPR Field Descriptions ................................................................................................. 13-20
MDR Field Descriptions ..................................................................................................... 13-20
LSDMR Field Descriptions ................................................................................................ 13-21
LURT Field Descriptions .................................................................................................... 13-23
LSRT Field Descriptions..................................................................................................... 13-24
LTESR Field Descriptions .................................................................................................. 13-25
LTEDR Field Descriptions.................................................................................................. 13-26
LTEIR Field Descriptions ................................................................................................... 13-27
LTEATR Field Descriptions................................................................................................ 13-28
LTEAR Field Descriptions.................................................................................................. 13-29
LBCR Field Descriptions.................................................................................................... 13-29
LCRR Field Descriptions.................................................................................................... 13-30
GPCM Write Control Signal Timing .................................................................................. 13-37
GPCM Read Control Signal Timing ................................................................................... 13-38
Boot Bank Field Values After Reset ................................................................................... 13-46
SDRAM Interface Commands ............................................................................................ 13-48
UPM Routines Start Addresses........................................................................................... 13-59
RAM Word Field Descriptions ........................................................................................... 13-64
MxMR Loop Field Use ....................................................................................................... 13-68
UPM Address Multiplexing ................................................................................................ 13-69
Data Bus Requirements For Read Cycle............................................................................. 13-83
Typical SDRAM Devices.................................................................................................... 13-85
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
lxxxvi
Freescale Semiconductor
Tables
Table
Number
13-33
13-34
13-35
13-36
13-37
13-38
13-39
13-40
13-41
13-42
13-43
13-44
13-45
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
14-23
14-24
14-25
14-26
14-27
14-28
Title
Page
Number
LADn Signal Connections to 128-Mbyte SDRAM ............................................................ 13-87
Logical Address Bus Partitioning ....................................................................................... 13-88
SDRAM Device Address Port During Address Phase........................................................ 13-88
SDRAM Device Address Port During READ/WRITE Command..................................... 13-88
Register Settings for 128-Mbyte SDRAMs ........................................................................ 13-89
Logical Address Partitioning .............................................................................................. 13-89
SDRAM Device Address Port During Address Phase........................................................ 13-90
SDRAM Device Address Port During READ/WRITE Command..................................... 13-90
Register Settings for 512-Mbyte SDRAMs ........................................................................ 13-90
SDRAM Capacitance .......................................................................................................... 13-92
SDRAM AC Characteristics ............................................................................................... 13-93
Local Bus to MSC8101 HDI16 Connections...................................................................... 13-98
UPM Synchronization Cycles ........................................................................................... 13-106
eTSECn Network Interface Signal Properties ...................................................................... 14-6
eTSEC Signals—Detailed Signal Descriptions .................................................................... 14-8
Module Memory Map Summary......................................................................................... 14-12
Module Memory Map ......................................................................................................... 14-13
TSEC_ID Field Descriptions .............................................................................................. 14-22
TSEC_ID2 Field Descriptions ............................................................................................ 14-23
IEVENT Field Descriptions................................................................................................ 14-24
IMASK Field Descriptions ................................................................................................. 14-28
EDIS Field Descriptions ..................................................................................................... 14-30
ECNTRL Field Descriptions............................................................................................... 14-31
eTSEC Interface Configurations ......................................................................................... 14-33
PTV Field Descriptions ....................................................................................................... 14-34
DMACTRL Field Descriptions........................................................................................... 14-34
TBIPA Field Descriptions ................................................................................................... 14-36
FIFO_RX_ALARM Field Descriptions.............................................................................. 14-37
FIFO_RX_ALARM_SHUTOFF Field Descriptions.......................................................... 14-37
FIFO_TX_THR Field Descriptions .................................................................................... 14-38
FIFO_TX_STARVE Field Descriptions ............................................................................. 14-39
FIFO_TX_STARVE_SHUTOFF Field Descriptions.......................................................... 14-39
TCTRL Field Descriptions.................................................................................................. 14-40
TSTAT Field Descriptions................................................................................................... 14-42
DFVLAN Field Descriptions .............................................................................................. 14-44
TXIC Field Descriptions ..................................................................................................... 14-44
TQUEUE Field Descriptions .............................................................................................. 14-45
TR03WT Field Descriptions ............................................................................................... 14-46
TR47WT Field Descriptions ............................................................................................... 14-47
TBDBPH Field Descriptions .............................................................................................. 14-48
TBPTRn Field Descriptions ................................................................................................ 14-48
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxxvii
Tables
Table
Number
14-29
14-30
14-31
14-32
14-33
14-34
14-35
14-36
14-37
14-38
14-39
14-40
14-41
14-42
14-43
14-44
14-45
14-46
14-47
14-48
14-49
14-50
14-51
14-52
14-53
14-54
14-55
14-56
14-57
14-58
14-59
14-60
14-61
14-62
14-63
14-64
14-65
14-66
14-67
14-68
14-69
Page
Number
Title
TBASEH Field Descriptions............................................................................................... 14-49
TBASE0–TBASE7 Field Descriptions ............................................................................... 14-49
RCTRL Field Descriptions ................................................................................................. 14-50
RSTAT Field Descriptions .................................................................................................. 14-52
RXIC Field Descriptions..................................................................................................... 14-54
RQUEUE Field Descriptions .............................................................................................. 14-55
RBIFX Field Descriptions .................................................................................................. 14-57
RQFAR Field Descriptions ................................................................................................. 14-58
RQFCR Field Descriptions ................................................................................................. 14-59
RQFPR Field Descriptions.................................................................................................. 14-61
MRBLR Field Descriptions ................................................................................................ 14-63
RBDBPH Field Descriptions .............................................................................................. 14-64
RBPTRn Field Descriptions................................................................................................ 14-64
RBASEH Field Descriptions .............................................................................................. 14-65
RBASE0–RBASE7 Field Descriptions .............................................................................. 14-65
MACCFG1 Field Descriptions ........................................................................................... 14-69
MACCFG2 Field Descriptions ........................................................................................... 14-70
IPGIFG Field Descriptions ................................................................................................. 14-72
HAFDUP Field Descriptions .............................................................................................. 14-73
MAXFRM Descriptions...................................................................................................... 14-74
MIIMCFG Field Descriptions............................................................................................. 14-75
MIIMCOM Descriptions..................................................................................................... 14-75
MIIMADD Field Descriptions............................................................................................ 14-76
MIIMCON Field Descriptions ............................................................................................ 14-77
MIIMSTAT Field Descriptions ........................................................................................... 14-77
MIIMIND Field Descriptions ............................................................................................. 14-78
IFSTAT Field Descriptions ................................................................................................. 14-78
MACSTNADDR1 Field Descriptions ................................................................................ 14-79
MACSTNADDR2 Field Descriptions ................................................................................ 14-79
MACnADDR1 Field Descriptions...................................................................................... 14-80
MAC01ADDR2–MAC15ADDR2 Field Descriptions ....................................................... 14-81
TR64 Field Descriptions ..................................................................................................... 14-82
TR127 Field Descriptions ................................................................................................... 14-82
TR255 Field Descriptions ................................................................................................... 14-82
TR511 Field Descriptions ................................................................................................... 14-83
TR1K Field Descriptions .................................................................................................... 14-83
TRMAX Field Descriptions................................................................................................ 14-84
TRMGV Field Descriptions................................................................................................ 14-84
RBYT Field Descriptions.................................................................................................... 14-85
RPKT Field Descriptions .................................................................................................... 14-85
RFCS Field Descriptions .................................................................................................... 14-86
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
lxxxviii
Freescale Semiconductor
Tables
Table
Number
14-70
14-71
14-72
14-73
14-74
14-75
14-76
14-77
14-78
14-79
14-80
14-81
14-82
14-83
14-84
14-85
14-86
14-87
14-88
14-89
14-90
14-91
14-92
14-93
14-94
14-95
14-96
14-97
14-98
14-99
14-100
14-101
14-102
14-103
14-104
14-105
14-106
14-107
14-108
14-109
14-110
Title
Page
Number
RMCA Field Descriptions .................................................................................................. 14-86
RBCA Field Descriptions ................................................................................................... 14-87
RXCF Field Descriptions.................................................................................................... 14-87
RXPF Field Descriptions .................................................................................................... 14-88
RXUO Field Descriptions ................................................................................................... 14-88
RALN Field Descriptions ................................................................................................... 14-89
RFLR Field Descriptions .................................................................................................... 14-89
RCDE Field Descriptions.................................................................................................... 14-90
RCSE Field Descriptions .................................................................................................... 14-90
RUND Field Descriptions ................................................................................................... 14-91
ROVR Field Descriptions ................................................................................................... 14-91
RFRG Field Descriptions.................................................................................................... 14-92
RJBR Field Descriptions..................................................................................................... 14-92
RDRP Field Descriptions.................................................................................................... 14-93
TBYT Field Descriptions.................................................................................................... 14-93
TPKT Field Descriptions .................................................................................................... 14-94
TMCA Field Descriptions................................................................................................... 14-94
TBCA Field Descriptions.................................................................................................... 14-95
TXPF Field Descriptions .................................................................................................... 14-95
TDFR Field Descriptions .................................................................................................... 14-96
TEDF Field Descriptions .................................................................................................... 14-96
TSCL Field Descriptions .................................................................................................... 14-97
TMCL Field Descriptions ................................................................................................... 14-97
TLCL Field Descriptions .................................................................................................... 14-98
TXCL Field Descriptions.................................................................................................... 14-98
TNCL Field Descriptions.................................................................................................... 14-99
TDRP Field Descriptions .................................................................................................... 14-99
TJBR Field Descriptions ................................................................................................... 14-100
TFCS Field Descriptions................................................................................................... 14-100
TXCF Field Descriptions .................................................................................................. 14-101
TOVR Field Descriptions ................................................................................................. 14-101
TUND Field Descriptions ................................................................................................. 14-102
TFRG Field Descriptions .................................................................................................. 14-102
CAR1 Field Descriptions .................................................................................................. 14-103
CAR2 Field Descriptions .................................................................................................. 14-104
CAM1 Field Descriptions ................................................................................................. 14-105
CAM2 Field Descriptions ................................................................................................. 14-107
RREJ Field Descriptions ................................................................................................... 14-108
IGADDRn Field Descriptions........................................................................................... 14-109
GADDRn Field Descriptions ............................................................................................ 14-109
FIFOCFG Field Descriptions............................................................................................ 14-110
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxxix
Tables
Table
Number
14-111
14-112
14-113
14-114
14-115
14-116
14-117
14-118
14-119
14-120
14-121
14-122
14-123
14-124
14-125
14-126
14-127
14-128
14-129
14-130
14-131
14-132
14-133
14-134
14-135
14-136
14-137
14-138
14-139
14-140
14-141
14-142
14-143
14-144
14-145
14-146
14-147
14-148
14-149
14-150
14-151
Page
Number
Title
ATTR Field Descriptions .................................................................................................. 14-112
ATTRELI Field Descriptions ............................................................................................ 14-113
TBI MII Register Set......................................................................................................... 14-115
CR Field Descriptions ....................................................................................................... 14-116
SR Descriptions................................................................................................................. 14-117
ANA Field Descriptions.................................................................................................... 14-118
PAUSE Priority Resolution............................................................................................... 14-119
ANLPBPA Field Descriptions .......................................................................................... 14-120
ANEX Field Descriptions ................................................................................................. 14-121
ANNPT Field Descriptions ............................................................................................... 14-122
ANLPANP Field Descriptions .......................................................................................... 14-122
EXST Field Descriptions .................................................................................................. 14-123
JD Field Descriptions........................................................................................................ 14-124
TBICON Field Descriptions ............................................................................................. 14-125
Ethernet Modes versus eTSEC (V = Available) ............................................................... 14-126
GMII, MII, and RMII Signals Multiplexing ..................................................................... 14-133
RGMII, TBI, and RTBI Signals Multiplexing .................................................................. 14-134
Shared Signals................................................................................................................... 14-135
Valid Combinations of eTSEC Signals and Interface Modes ........................................... 14-136
Signal Encoding for GMII-Style 8-Bit FIFO .................................................................... 14-139
Signal Encoding for Encoded 8-Bit FIFO......................................................................... 14-139
Signal Encoding for GMII-Style 16-Bit FIFO .................................................................. 14-141
Signal Encoding for Encoded 16-Bit FIFO....................................................................... 14-142
Steps for Minimum Register Initialization........................................................................ 14-143
Custom Preamble Field Descriptions................................................................................ 14-148
Received Preamble Field Descriptions ............................................................................. 14-149
Flow Control Frame Structure .......................................................................................... 14-153
Non-Error Transmit Interrupts .......................................................................................... 14-155
Non-Error Receive Interrupts............................................................................................ 14-155
Interrupt Coalescing Timing Threshold Ranges ............................................................... 14-156
Transmission Errors .......................................................................................................... 14-157
Reception Errors ............................................................................................................... 14-158
Tx Frame Control Block Descriptions .............................................................................. 14-161
Rx Frame Control Block Descriptions.............................................................................. 14-162
Special Filer Rules ............................................................................................................ 14-166
Receive Queue Filer Interrupt Events ............................................................................... 14-166
Filer Table Example—802.1p Priority Filing ................................................................... 14-167
Filer Table Example—IP Diff-Serv Code Points Filing ................................................... 14-168
Filer Table Example—TCP and UDP Port Filing............................................................. 14-168
Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 14-174
Receive Buffer Descriptor Field Descriptions .................................................................. 14-177
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
xc
Freescale Semiconductor
Tables
Table
Number
14-152
14-153
14-154
14-155
14-156
14-157
14-158
14-159
14-160
14-161
14-162
14-163
14-164
14-165
14-166
14-167
14-168
14-169
14-170
14-171
14-172
14-173
14-174
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
Title
Page
Number
MII Interface Mode Signal Configuration ........................................................................ 14-179
Shared MII Signals............................................................................................................ 14-180
MII Mode Register Initialization Steps............................................................................. 14-180
GMII Interface Mode Signal Configuration ..................................................................... 14-183
Shared GMII Signals......................................................................................................... 14-184
GMII Mode Register Initialization Steps.......................................................................... 14-184
TBI Interface Mode Signal Configuration ........................................................................ 14-187
Shared TBI Signals ........................................................................................................... 14-188
TBI Mode Register Initialization Steps............................................................................. 14-188
RGMII Interface Mode Signal Configuration................................................................... 14-191
Shared RGMII Signals ...................................................................................................... 14-192
RGMII Mode Register Initialization Steps ....................................................................... 14-192
RMII Interface Mode Signal Configuration...................................................................... 14-195
Shared RMII Signals ......................................................................................................... 14-196
RMII Mode Register Initialization Steps .......................................................................... 14-196
RTBI Interface Mode Signal Configuration...................................................................... 14-199
Shared RTBI Signals ......................................................................................................... 14-200
RTBI Mode Register Initialization Steps .......................................................................... 14-200
8-Bit FIFO Interface Mode Signal Configurations, eTSEC1/2 ........................................ 14-203
8-Bit FIFO Interface Mode Signal Configurations, eTSEC3/4 ........................................ 14-204
8-Bit FIFO Mode Register Initialization Steps ................................................................. 14-205
16-Bit FIFO Interface Mode Signal Configuration (eTSECs1 & 2)................................. 14-206
16-Bit FIFO Mode Register Initialization Steps ............................................................... 14-208
Relationship of Modes and Features ..................................................................................... 15-3
DMA Mode Bit Settings ....................................................................................................... 15-3
DMA Signals—Detailed Signal Descriptions....................................................................... 15-6
DMA Register Summary ...................................................................................................... 15-7
MRn Field Descriptions ...................................................................................................... 15-10
SRn Field Descriptions ....................................................................................................... 15-13
ECLNDARn Field Descriptions ......................................................................................... 15-15
CLNDARn Field Descriptions............................................................................................ 15-15
SATRn Field Descriptions .................................................................................................. 15-16
SARn Field Descriptions .................................................................................................... 15-18
SARn Field Descriptions .................................................................................................... 15-18
DATRn Field Descriptions.................................................................................................. 15-19
DARn Field Descriptions.................................................................................................... 15-21
DARn Field Descriptions.................................................................................................... 15-21
BCRn Field Descriptions .................................................................................................... 15-22
NLNDARn Field Descriptions............................................................................................ 15-22
ENLNDARn Field Descriptions ......................................................................................... 15-23
ECLSDARn Field Descriptions .......................................................................................... 15-24
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
xci
Tables
Table
Number
15-19
15-20
15-21
15-22
15-23
15-24
15-25
15-26
15-27
15-28
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
16-20
16-21
16-22
16-23
16-24
16-25
16-26
16-27
16-28
16-29
16-30
16-31
Page
Number
Title
CLSDARn Field Descriptions ............................................................................................ 15-24
ENLSDARn Field Descriptions.......................................................................................... 15-25
NLSDARn Field Descriptions ............................................................................................ 15-25
SSRn Field Descriptions ..................................................................................................... 15-26
DSRn Field Descriptions .................................................................................................... 15-26
DGSR Field Descriptions.................................................................................................... 15-27
Channel State Table............................................................................................................. 15-35
List DMA Descriptor Summary.......................................................................................... 15-37
Link DMA Descriptor Summary ........................................................................................ 15-38
MPC8548E DMA Paths...................................................................................................... 15-43
POR Parameters for PCI/X Controller.................................................................................. 16-5
PCI1/X and PCI2 Interface Signals—Detailed Signal Descriptions .................................... 16-8
PCI/X Memory-Mapped Register Map............................................................................... 16-14
PCI CFG_ADDR Field Descriptions.................................................................................. 16-17
PCI/X CFG_DATA Field Descriptions ............................................................................... 16-18
PCI/X INT_ACK Field Descriptions.................................................................................. 16-19
POTARn Field Descriptions ............................................................................................... 16-20
POTEARn Field Descriptions............................................................................................. 16-20
POWBARn Field Descriptions ........................................................................................... 16-21
POWARn Field Descriptions .............................................................................................. 16-21
PITARn Field Descriptions ................................................................................................. 16-24
PIWBAR Field Descriptions............................................................................................... 16-24
PIWBEAR Field Descriptions ............................................................................................ 16-25
PIWARn Field Descriptions................................................................................................ 16-25
ERR_DR Field Descriptions ............................................................................................... 16-28
ERR_CAP_DR Field Descriptions ..................................................................................... 16-29
ERR_EN Field Descriptions ............................................................................................... 16-30
ERR_ATTRIB Field Descriptions ...................................................................................... 16-30
ERR_ADDR Field Descriptions ......................................................................................... 16-31
ERR_EXT_ADDR Field Descriptions ............................................................................... 16-32
ERR_DL Field Description................................................................................................. 16-32
ERR_DH Field Description ................................................................................................ 16-32
GAS_TIMR Field Descriptions .......................................................................................... 16-33
PCIX_TIMR Field Descriptions ......................................................................................... 16-33
PCI Vendor ID Register Field Description ......................................................................... 16-35
PCI Device ID Register Field Description.......................................................................... 16-35
PCI Bus Command Register Field Descriptions................................................................. 16-35
PCI Bus Status Register Field Descriptions........................................................................ 16-37
PCI Revision ID Register Field Descriptions ..................................................................... 16-38
PCI Bus Programming Interface Register Field Description.............................................. 16-38
PCI Subclass Code Register Field Description................................................................... 16-39
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor
Tables
Table
Number
16-32
16-33
16-34
16-35
16-36
16-37
16-38
16-39
16-40
16-41
16-42
16-43
16-44
16-45
16-46
16-47
16-48
16-49
16-50
16-51
16-52
16-53
16-54
16-55
16-56
16-57
16-58
16-59
16-60
16-61
16-62
16-63
16-64
16-65
16-66
16-67
17-1
17-2
17-3
17-4
17-5
Title
Page
Number
PCI Bus Base Class Code Register Field Description ........................................................ 16-39
PCI Bus Cache Line Size Register Field Descriptions ....................................................... 16-40
PCI Bus Latency Timer Register Field Descriptions .......................................................... 16-40
PCSRBAR Field Descriptions ............................................................................................ 16-41
32-Bit Memory Base Address Register Field Descriptions ................................................ 16-41
64-Bit Low Memory Base Address Register Field Descriptions........................................ 16-42
Bit Setting for 64-Bit High Memory Base Address Register.............................................. 16-42
PCI Subsystem Vendor ID Register Field Description ....................................................... 16-42
PCI Subsystem ID Register Field Description.................................................................... 16-43
PCI Bus Capabilities Pointer Register Field Description ................................................... 16-43
PCI Bus Interrupt Line Register Field Description............................................................. 16-44
PCI Bus Interrupt Pin Register Field Description............................................................... 16-44
PCI Bus Minimum Grant Register Field Description ......................................................... 16-44
PCI Bus Maximum Latency Register Field Description .................................................... 16-45
PCI Bus Function Register Field Descriptions ................................................................... 16-45
PCI Bus Arbiter Configuration Register Field Descriptions .............................................. 16-46
PCI-X Next Capabilities ID Register Field Descriptions ................................................... 16-47
PCI-X Capability Pointer Register Field Description......................................................... 16-47
PCI-X Command Register Field Descriptions.................................................................... 16-48
PCI-X Status Register Field Descriptions........................................................................... 16-48
PCI Bus Commands ............................................................................................................ 16-53
Supported Combinations of PCI_AD[1:0].......................................................................... 16-54
PCI Configuration Space Header Summary ....................................................................... 16-65
PCI Type 0 Configuration—Device Number to ADn Translation...................................... 16-68
Special-Cycle Message Encodings ..................................................................................... 16-70
PCI Mode Error Actions ..................................................................................................... 16-72
PCI-X Command Encodings............................................................................................... 16-74
Burst/DWORD Transaction Attribute Summary ................................................................ 16-76
Split Completion Transaction Address ............................................................................... 16-83
PCI-X Split Completion Transaction Attribute Summary .................................................. 16-84
PCI-X Type 0 Configuration—Device Number to ADn Translation ................................. 16-85
PCI-X Configuration Transaction Attribute Summary ....................................................... 16-86
PCI-X Mode Error Actions ................................................................................................. 16-87
Affected Configuration Register Bits for POR ................................................................... 16-89
Power-On Reset Values for Affected Configuration Bits ................................................... 16-89
Extended 64-bit PCI1/X Signal Connections...................................................................... 16-90
RapidIO Memory Map ......................................................................................................... 17-5
DIDCAR Field Descriptions ............................................................................................... 17-11
DICAR Field Descriptions.................................................................................................. 17-12
AIDCAR Field Descriptions ............................................................................................... 17-12
AICAR Field Descriptions.................................................................................................. 17-13
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
xciii
Tables
Table
Number
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
17-21
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
17-31
17-32
17-33
17-34
17-35
17-36
17-37
17-38
17-39
17-40
17-41
17-42
17-43
17-44
17-45
17-46
Page
Number
Title
PEFCAR Field Descriptions ............................................................................................... 17-13
SOCAR Field Descriptions ................................................................................................. 17-14
DOCAR Field Descriptions ................................................................................................ 17-16
MCSR Field Definitions ..................................................................................................... 17-17
PWDCSR Field Descriptions.............................................................................................. 17-18
PELLCCSR Field Descriptions .......................................................................................... 17-20
LCSBA1CSR Field Descriptions........................................................................................ 17-20
BDIDCSR Field Descriptions ............................................................................................. 17-21
HBDIDLCSR Field Descriptions........................................................................................ 17-22
CTCSR Field Descriptions.................................................................................................. 17-22
PMBH0 Field Descriptions ................................................................................................. 17-23
PLTOCCSR Field Descriptions .......................................................................................... 17-23
PRTOCCSR Field Descriptions .......................................................................................... 17-24
GCCSR Field Descriptions ................................................................................................. 17-24
LMREQCSR Field Descriptions......................................................................................... 17-25
LMRESPCSR Field Descriptions ....................................................................................... 17-26
LASCSR Field Descriptions ............................................................................................... 17-26
ESCSR Field Descriptions .................................................................................................. 17-27
CCSR Field Descriptions .................................................................................................... 17-29
ERBH Field Descriptions.................................................................................................... 17-30
LTLEDCSR Field Descriptions .......................................................................................... 17-31
LTLEECSR Field Descriptions........................................................................................... 17-33
LTLACCSR Field Descriptions .......................................................................................... 17-35
LTLDIDCCSR Field Descriptions ...................................................................................... 17-35
LTLCCCSR Field Descriptions .......................................................................................... 17-36
EDCSR Field Descriptions ................................................................................................. 17-37
ERECSR Field Descriptions ............................................................................................... 17-38
ECACSR Field Descriptions............................................................................................... 17-39
PCSECCSR0 Field Descriptions ........................................................................................ 17-40
PECCSR1 Field Descriptions ............................................................................................. 17-40
PECCSR2 Field Descriptions ............................................................................................. 17-40
PECCSR3 Field Descriptions ............................................................................................. 17-41
ERCSR Field Descriptions.................................................................................................. 17-41
ERTCSR Field Descriptions ............................................................................................... 17-43
LLCR Field Descriptions .................................................................................................... 17-43
EPWISR Field Descriptions................................................................................................ 17-44
LRETCR Field Descriptions ............................................................................................... 17-45
PRETCR Field Descriptions ............................................................................................... 17-45
ADIDCSR Field Descriptions............................................................................................. 17-46
AACR Field Descriptions ................................................................................................... 17-46
LOPTTLCR Field Descriptions .......................................................................................... 17-47
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor
Tables
Table
Number
17-47
17-48
17-49
17-50
17-51
17-52
17-53
17-54
17-55
17-56
17-57
17-58
17-59
17-60
17-61
17-62
17-63
17-64
17-65
17-66
17-67
17-68
17-69
17-70
17-71
17-72
17-73
17-74
17-75
17-76
17-77
17-78
17-79
17-80
17-81
17-82
17-83
17-84
17-85
17-86
17-87
Title
Page
Number
IECSR Field Descriptions ................................................................................................... 17-47
PCR Field Descriptions ...................................................................................................... 17-48
SLCSR Field Descriptions .................................................................................................. 17-49
SLEICR Field Descriptions ................................................................................................ 17-49
IPBRR1 Field Descriptions................................................................................................. 17-50
IPBRR2 Field Descriptions................................................................................................. 17-51
ROWTARn Field Descriptions ........................................................................................... 17-54
ROWTEARn Field Descriptions ........................................................................................ 17-54
ROWBARn Descriptions.................................................................................................... 17-55
ROWARn Field Descriptions.............................................................................................. 17-56
ROWSnRn Field Descriptions ............................................................................................ 17-58
RIWTARn Field Descriptions............................................................................................. 17-59
RIWBARn Field Descriptions ............................................................................................ 17-60
RapidIO Inbound Window Attributes Register 1–4............................................................ 17-60
RapidIO Inbound Window Attributes Register 0................................................................ 17-60
RIWARn Field Descriptions ............................................................................................... 17-60
OMnMR Field Descriptions................................................................................................ 17-63
OMnSR Field Descriptions ................................................................................................. 17-64
EOMnDQDPAR Field Descriptions ................................................................................... 17-66
OMnDQDPAR Field Descriptions...................................................................................... 17-66
EOMnDQEPAR Field Descriptions.................................................................................... 17-67
OMnDQEPAR Field Descriptions ...................................................................................... 17-68
EOMnSAR Field Descriptions............................................................................................ 17-68
OMnSAR Field Descriptions .............................................................................................. 17-69
OMnDPR Field Descriptions .............................................................................................. 17-69
OMnDATR Field Descriptions ........................................................................................... 17-70
OMnDCR Field Descriptions.............................................................................................. 17-71
OMnRETCR Field Descriptions ......................................................................................... 17-71
OMnMGR Field Descriptions............................................................................................. 17-72
OMnMLR Field Descriptions ............................................................................................. 17-73
IMnMR Field Descriptions ................................................................................................. 17-73
IMnSR Field Descriptions .................................................................................................. 17-75
EIMnFQDPAR Field Descriptions ..................................................................................... 17-76
IMnFQDPAR Field Descriptions ........................................................................................ 17-77
EIMnFQEPAR Field Descriptions...................................................................................... 17-78
IMnFQEPAR Field Descriptions ........................................................................................ 17-78
IMnMIRIR Field Descriptions............................................................................................ 17-79
ODMR Field Descriptions .................................................................................................. 17-79
ODSR Field Descriptions.................................................................................................... 17-80
ODDPR Field Descriptions................................................................................................. 17-81
ODDATR Field Descriptions .............................................................................................. 17-81
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
xcv
Tables
Table
Number
17-88
17-89
17-90
17-91
17-92
17-93
17-94
17-95
17-96
17-97
17-98
17-99
17-100
17-101
17-102
17-103
17-104
17-105
17-106
17-107
17-108
17-109
17-110
17-111
17-112
17-113
17-114
17-115
17-116
17-117
17-118
17-119
17-120
17-121
17-122
17-123
17-124
17-125
17-126
17-127
Page
Number
Title
ODRETCR Field Descriptions............................................................................................ 17-82
IDMR Field Descriptions.................................................................................................... 17-83
IDSR Field Descriptions ..................................................................................................... 17-84
EIDQDPAR Field Descriptions .......................................................................................... 17-85
IDQDPAR Field Descriptions............................................................................................. 17-86
EIDQEPAR Field Descriptions........................................................................................... 17-87
IDQEPAR Field Descriptions ............................................................................................. 17-87
IDMIRIR Field Descriptions .............................................................................................. 17-87
IPWMR Field Descriptions................................................................................................. 17-88
IPWSR Field Descriptions .................................................................................................. 17-89
EIPWQBAR Field Descriptions ......................................................................................... 17-90
IPWQBAR Field Descriptions............................................................................................ 17-90
RapidIO I/O Transactions ................................................................................................... 17-91
RapidIO Message Passing Transactions ............................................................................. 17-91
RapidIO GSM Transactions ................................................................................................ 17-92
RapidIO Small Transport Field Packet Format................................................................... 17-92
1x/4x LP-Serial Control Symbol Format ............................................................................ 17-93
Physical RapidIO Errors Detected .................................................................................... 17-105
Physical RapidIO Threshold Response............................................................................. 17-106
Hardware Errors For NRead Transaction.......................................................................... 17-107
Hardware Errors For Maintenance Read/Write Req Transaction ..................................... 17-109
Hardware Errors For Atomic (inc, dec, set, or clr) Read Transaction ...............................17-111
Hardware Errors For NWrite, NWrite_r, and Unsupported Atomic Test-and-Swap
Transactions.................................................................................................................. 17-113
Hardware Errors For SWrite Transactions........................................................................ 17-116
Hardware Errors For Maintenance Response Transactions .............................................. 17-117
Hardware Errors For IO/GSM Response Transactions (Not Maintenance) ..................... 17-120
Hardware Errors For DMA Message Response Transactions .......................................... 17-125
Hardware Errors For Message Request Transactions ....................................................... 17-127
Hardware Errors For Message Response Transactions..................................................... 17-129
Hardware Errors For Doorbell Request Transaction......................................................... 17-130
Hardware Errors For Doorbell Response Transactions..................................................... 17-132
Hardware Errors for PortWrite Transaction...................................................................... 17-134
Hardware Errors for Reserved Ftype ................................................................................ 17-136
Hardware Errors for Outbound Transaction Crossed ATMU Boundary........................... 17-138
Hardware Errors for Outbound Packet Time-to-live Errors ............................................ 17-139
Outbound Message Direct Mode Hardware Errors........................................................... 17-145
Outbound Message Direct Mode Programming Errors .................................................... 17-148
Outbound Message Unit Descriptor Summary ................................................................. 17-152
Outbound Message Chaining Mode Hardware Errors ...................................................... 17-156
Outbound Message Chaining Mode Programming Errors................................................ 17-156
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor
Tables
Table
Number
17-128
17-129
17-130
17-131
17-132
17-133
17-134
17-135
17-136
17-137
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
18-17
18-18
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
Title
Page
Number
Inbound Message Hardware Errors................................................................................... 17-162
Inbound Message Programming Errors ............................................................................ 17-166
Outbound Doorbell Hardware Errors................................................................................ 17-172
Outbound Doorbell Programming Errors ......................................................................... 17-174
Inbound Doorbell Target Info Definition.......................................................................... 17-176
Source Info Definition ...................................................................................................... 17-176
Inbound Doorbell Hardware Errors .................................................................................. 17-178
Inbound Doorbell Programming Errors ............................................................................ 17-181
Inbound Port-Write Hardware Errors................................................................................ 17-185
Inbound Port-Write Programming Errors ......................................................................... 17-188
POR Parameters for PCI Express Controller ........................................................................ 18-4
PCI Express Interface Signals—Detailed Signal Descriptions............................................. 18-5
PCI Express Memory-Mapped Register Map ....................................................................... 18-6
PEX_CONFIG_ADDR Field Descriptions .......................................................................... 18-9
PEX_CONFIG_DATA Field Descriptions ......................................................................... 18-10
PEX_OTB_CPL_TOR Field Descriptions ......................................................................... 18-11
PEX_CONF_RTY_TOR Field Descriptions ...................................................................... 18-12
PEX_CONFIG Field Descriptions...................................................................................... 18-12
PEX_PME_MES_DR Field Descriptions........................................................................... 18-13
PEX_PME_MES_DISR Field Descriptions ....................................................................... 18-15
PEX_PME_MES_IER Field Descriptions.......................................................................... 18-16
PEX_PMCR Field Descriptions.......................................................................................... 18-18
PCI Express IP Block Revision Register 1 Field Descriptions........................................... 18-18
PCI Express IP Block Revision Register 2 Field Descriptions........................................... 18-19
PEXOTARn Field Descriptions .......................................................................................... 18-20
PCI Express Outbound Extended Address Translation Register n Field Descriptions....... 18-21
PCI Express Outbound Window Base Address Register n Field Descriptions................... 18-22
PEXOWARn Field Descriptions ......................................................................................... 18-22
PCI Express Inbound Translation Address Registers Field Descriptions ........................... 18-26
PCI Express Inbound Window Base Address Register Field Descriptions ........................ 18-26
PCI Express Inbound Window Base Extended Address Register Field Descriptions ........ 18-27
PCI Express Inbound Window Attributes Registers Field Descriptions............................. 18-27
PCI Express Error Detect Register Field Descriptions ....................................................... 18-30
PCI Express Error Interrupt Enable Register Field Descriptions ....................................... 18-32
PCI Express Error Disable Register Field Descriptions ..................................................... 18-34
PCI Express Error Capture Status Register Field Descriptions .......................................... 18-36
PCI Express Error Capture Register 0 Field Descriptions
Internal Source, Outbound Transaction.......................................................................... 18-37
PCI Express Error Capture Register 0 Field Descriptions
External Source, Inbound Transaction ........................................................................... 18-37
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
xcvii
Tables
Table
Number
18-29
18-30
18-31
18-32
18-33
18-34
18-35
18-36
18-37
18-38
18-39
18-40
18-41
18-42
18-43
18-44
18-45
18-46
18-47
18-48
18-49
18-50
18-51
18-52
18-53
18-54
18-55
18-56
18-57
18-58
18-59
18-60
18-61
18-62
18-63
18-64
Page
Number
Title
PCI Express Error Capture Register 1 Field Descriptions
Internal Source, Outbound Transaction.......................................................................... 18-38
PCI Express Error Capture Register 1 Field Descriptions
External Source, Inbound Transaction ........................................................................... 18-39
PCI Express Error Capture Register 2 Field Descriptions
Internal Source, Outbound Transaction.......................................................................... 18-40
PCI Express Error Capture Register 2 Field Descriptions
External Source, Inbound Transaction ........................................................................... 18-40
PCI Express Error Capture Register 3 Field Descriptions
Internal Source, Outbound Transaction.......................................................................... 18-41
PEX Error Capture Register 3 Field Descriptions External Source, Inbound Transaction. 18-41
PCI Express Vendor ID Register Field Description............................................................ 18-44
PCI Express Device ID Register Field Description ............................................................ 18-44
PCI Express Command Register Field Descriptions .......................................................... 18-45
PCI Express Status Register Field Descriptions ................................................................. 18-46
PCI Express Revision ID Register Field Descriptions........................................................ 18-47
PCI Express Class Code Register Field Descriptions ......................................................... 18-48
PCI Express Bus Cache Line Size Register Field Descriptions.......................................... 18-48
PCI Express Bus Latency Timer Register Field Descriptions ............................................ 18-49
PCI Express Bus Latency Timer Register Field Descriptions ............................................ 18-49
PEXCSRBAR Field Descriptions ....................................................................................... 18-51
32-Bit Memory Base Address Register (BAR1) Field Descriptions .................................. 18-51
64-Bit Low Memory Base Address Register Field Descriptions........................................ 18-52
Bit Setting for 64-Bit High Memory Base Address Register.............................................. 18-52
PCI Express Subsystem Vendor ID Register Field Description ......................................... 18-53
PCI Express Subsystem ID Register Field Description ...................................................... 18-53
Capabilities Pointer Register Field Description.................................................................. 18-54
PCI Express Interrupt Line Register Field Description ...................................................... 18-54
PCI Express Interrupt Pin Register Field Description ........................................................ 18-55
PCI Express Maximum Grant Register Field Description.................................................. 18-55
PCI Express Maximum Latency Register Field Description .............................................. 18-56
PEXCSRBAR Field Descriptions ....................................................................................... 18-57
PCI Express Primary Bus Number Register Field Description .......................................... 18-57
PCI Express Secondary Bus Number Register Field Description ...................................... 18-58
PCI Express Subordinate Bus Number Register Field Description.................................... 18-58
PCI Express I/O Base Register Field Description .............................................................. 18-59
PCI Express I/O Limit Register Field Description ............................................................. 18-60
PCI Express Secondary Status Register Field Description ................................................. 18-60
PCI Express Memory Base Register Field Description ...................................................... 18-61
PCI Express Memory Limit Register Field Description ..................................................... 18-61
PCI Express Prefetchable Memory Base Register Field Description ................................. 18-62
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor
Tables
Table
Number
18-65
18-66
18-67
18-68
18-69
18-70
18-71
18-72
18-73
18-74
18-75
18-76
18-77
18-78
18-79
18-80
18-81
18-82
18-83
18-84
18-85
18-86
18-87
18-88
18-89
18-90
18-91
18-92
18-93
18-94
18-95
18-96
18-97
18-98
18-99
18-100
18-101
18-102
18-103
18-104
18-105
Title
Page
Number
PCI Express Prefetchable Memory Limit Register Field Description................................ 18-62
PCI Express Prefetchable Base Upper 32 Bits Register ..................................................... 18-63
PCI Express Prefetchable Limit Upper 32 Bits Register .................................................... 18-63
PCI Express I/O Base Upper 16 Bits Register Field Description ....................................... 18-64
PCI Express I/O Limit Upper 16 Bits Register Field Description...................................... 18-64
Capabilities Pointer Register Field Description.................................................................. 18-64
PCI Express Interrupt Line Register Field Description ...................................................... 18-65
PCI Express Interrupt Pin Register Field Description ........................................................ 18-65
PCI Express Bridge Control Register Field Description .................................................... 18-66
PCI Express Power Management Capability ID Register Field Description...................... 18-68
PCI Express Power Management Capabilities Register Field Description ........................ 18-68
PCI Express Status and Control Register Field Description............................................... 18-69
PCI Express Power Management Data Register Field Description.................................... 18-69
PCI Express Capability ID Register Field Description....................................................... 18-70
PCI Express Capabilities Register Field Description ......................................................... 18-70
PCI Express Device Capabilities Register Field Description ............................................. 18-71
PCI Express Device Control Register Field Description .................................................... 18-72
PCI Express Device Status Register Field Description....................................................... 18-72
PCI Express Link Capabilities Register Field Description ................................................. 18-73
PCI Express Link Control Register Field Description........................................................ 18-73
PCI Express Link Status Register Field Description .......................................................... 18-74
PCI Express Slot Capabilities Register Field Description .................................................. 18-75
PCI Express Slot Control Register Field Description ......................................................... 18-76
PCI Express Slot Status Register Field Descriptions.......................................................... 18-76
PCI Express Root Control Register Field Description........................................................ 18-77
PCI Express Root Status Register Field Description .......................................................... 18-77
PCI Express Capability ID Register Field Description....................................................... 18-78
PCI Express MSI Message Control Register Field Description ......................................... 18-78
PCI Express MSI Message Address Register Field Description ........................................ 18-79
PCI Express MSI Message Upper Address Register Field Description ............................. 18-79
PCI Express MSI Message Data Register Field Description.............................................. 18-80
PCI Express Advanced Error Reporting Capability ID Register Field Description ........... 18-81
PCI Express Uncorrectable Error Status Register Field Description.................................. 18-81
PCI Express Uncorrectable Error Mask Register Field Description................................... 18-82
PCI Express Uncorrectable Error Severity Register Field Description .............................. 18-83
PCI Express Correctable Error Status Register Field Description...................................... 18-84
PCI Express Correctable Error Mask Register Field Description....................................... 18-85
PCI Express Advanced Error Capabilities and Control Register Field Description........... 18-85
PCI Express Header Log Register Field Description.......................................................... 18-86
PCI Express Root Error Command Register Field Description.......................................... 18-87
PCI Express Root Error Command Register Field Description.......................................... 18-87
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Tables
Table
Number
18-106
18-107
18-108
18-109
18-110
18-111
18-112
18-113
18-114
18-115
18-116
18-117
18-118
18-119
18-120
18-121
18-122
18-123
18-124
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
Page
Number
Title
PCI Express Correctable Error Source ID Register Field Description ............................... 18-88
PCI Express Correctable Error Source ID Register Field Description ............................... 18-88
PEX_LTSSM_STAT Field Descriptions ............................................................................. 18-89
PEX_LTSSM_STAT Status Codes...................................................................................... 18-89
PEX_GCLK_RATIO Field Descriptions ............................................................................ 18-91
PEX_PM_TIMER Field Descriptions ................................................................................ 18-92
PEX_PME_TIMEOUT Field Descriptions ........................................................................ 18-92
PEX_SSVID_UPDATE Field Descriptions........................................................................ 18-93
PEX_CFG_READY Field Descriptions ............................................................................. 18-94
PEX_PME_TO_ACK_TOR Field Descriptions................................................................. 18-94
PEX_SS_INTR_MASK Field Descriptions ....................................................................... 18-95
PCI Express Transactions ................................................................................................... 18-97
Lane Assignment With and Without Lane Reversal ......................................................... 18-100
Internal Platform (OCeaN) Message Data Format ........................................................... 18-102
PCI Express ATMU Outbound Messages ......................................................................... 18-102
PCI Express RC Inbound Message Handling ................................................................... 18-103
PCI Express EP Inbound Message Handling.................................................................... 18-104
Initial credit advertisement................................................................................................ 18-107
Power Management State Supported ................................................................................ 18-107
Example Descriptor............................................................................................................... 19-4
SEC Base Address Map ...................................................................................................... 19-10
SEC Address Map............................................................................................................... 19-11
Header Dword Bit Definitions ............................................................................................ 19-17
EU_SEL0 and EU_SEL1 Values ........................................................................................ 19-18
Descriptor Types ................................................................................................................. 19-19
Pointer Dword Field Definitions......................................................................................... 19-20
Link Table Field Definitions ............................................................................................... 19-22
Descriptor Format by Type ................................................................................................. 19-24
PKEU[ROUTINE] Field Values ......................................................................................... 19-27
PKEU Reset Control Register Field Descriptions .............................................................. 19-29
PKEU Status Register Field Descriptions........................................................................... 19-30
PKEU interrupt Status Register Field Descriptions ............................................................ 19-31
PKEU Interrupt Control Register Field Descriptions ......................................................... 19-32
DEU Mode Register Field Descriptions ............................................................................. 19-34
DEU Key Size Register Field Descriptions ........................................................................ 19-35
DEU Reset Control Register Field Descriptions................................................................. 19-36
DEU Status Register Field Descriptions ............................................................................. 19-37
DEU Interrupt Status Register Field Descriptions .............................................................. 19-38
DEU Interrupt Control Register Field Descriptions ........................................................... 19-39
AFEU Mode Register Field Descriptions ........................................................................... 19-43
AFEU Reset Control Register Field Descriptions .............................................................. 19-45
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Table
Number
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
19-34
19-35
19-36
19-37
19-38
19-39
19-40
19-41
19-42
19-43
19-44
19-45
19-46
19-47
19-48
19-49
19-50
19-51
19-52
19-53
19-54
19-55
19-56
19-57
19-58
19-59
19-60
19-61
19-62
20-1
Title
Page
Number
AFEU Status Register Field Descriptions........................................................................... 19-46
AFEU Interrupt Status Register Field Descriptions............................................................ 19-47
AFEU Interrupt Control Register Field Descriptions ......................................................... 19-48
MDEU Mode Register in Old Configuration (NEW = 0)................................................... 19-51
MDEU Mode Register in New Configuration (NEW = 1) ................................................. 19-52
Mode Register —HMAC or SSL-MAC Generated by Single Descriptor.......................... 19-53
Mode Register —HMAC Generated Across a Sequence of Descriptors............................ 19-54
MDEU Reset Control Register Field Descriptions ............................................................. 19-55
MDEU Status Register Field Descriptions ......................................................................... 19-56
MDEU Interrupt Status Register Field Descriptions .......................................................... 19-57
MDEU Interrupt Control Register Field Descriptions ........................................................ 19-58
RNG Reset Control Register Field Descriptions ................................................................ 19-64
RNG Status Register Field Descriptions............................................................................. 19-64
RNG Interrupt Status Register Field Descriptions.............................................................. 19-65
RNG Interrupt Control Register Field Descriptions ........................................................... 19-66
AESU Mode Register.......................................................................................................... 19-68
AES Cipher Modes ............................................................................................................. 19-68
AESU Reset Control Register Field Descriptions .............................................................. 19-70
AESU Status Register Field Descriptions........................................................................... 19-71
AESU Interrupt Status Register Field Descriptions............................................................ 19-72
AESU Interrupt Control Register Field Descriptions ......................................................... 19-73
KEU Mode Register Field Descriptions ............................................................................. 19-80
KEU Reset Control Register Field Descriptions................................................................. 19-82
KEU Status Register Field Descriptions ............................................................................. 19-83
KEU Interrupt Status Register Field Descriptions .............................................................. 19-84
KEU Interrupt Control Register Field Descriptions ........................................................... 19-86
KEU IV_1 Register Field Descriptions .............................................................................. 19-88
Crypto-Channel Configuration Register (CCCR) Field Descriptions ................................ 19-93
Header Dword Writeback Field Descriptions ..................................................................... 19-94
Crypto-Channel Pointer Status Register Field Descriptions ............................................... 19-95
G_STATE and S_STATE Field Values................................................................................ 19-97
CHN_STATE Field Values.................................................................................................. 19-98
Crypto-Channel Pointer Status Register Error Field Descriptions ..................................... 19-98
Channel Pointer Status Register PTR_DW Field Values .................................................... 19-99
Channel Current Descriptor Pointer Register Field Descriptions ..................................... 19-100
Fetch FIFO Field Descriptions......................................................................................... 19-101
Channel Assignment Value ............................................................................................... 19-109
Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers .............. 19-110
Channel Current Descriptor Pointer Register Signals....................................................... 19-113
Master Control Register (MCR) Field Descriptions ......................................................... 19-114
External Signal Summary ..................................................................................................... 20-2
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Table
Number
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
20-22
20-23
20-24
20-25
20-26
20-27
20-28
20-29
20-30
20-31
20-32
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
Page
Number
Title
Detailed Signal Descriptions................................................................................................. 20-2
Global Utilities Block Register Summary ............................................................................ 20-3
PORPLLSR Field Descriptions ............................................................................................ 20-5
PORBMSR Field Descriptions ............................................................................................. 20-6
PORIMPSCR Field Descriptions.......................................................................................... 20-7
PORDEVSR Field Descriptions ........................................................................................... 20-8
PORDBGMSR Field Descriptions...................................................................................... 20-10
PORDEVSR2 Field Descriptions ....................................................................................... 20-11
GPPORCR Field Descriptions ............................................................................................ 20-11
GPIOCR Field Descriptions................................................................................................ 20-12
GPOUTDR Field Descriptions ........................................................................................... 20-13
GPINDR Field Descriptions ............................................................................................... 20-14
PMUXCR Field Descriptions ............................................................................................. 20-15
DEVDISR Field Descriptions ............................................................................................. 20-16
POWMGTCSR Field Descriptions ..................................................................................... 20-18
MCPSUMR Field Descriptions .......................................................................................... 20-19
RSTRSCR Field Descriptions............................................................................................. 20-20
PVR Field Descriptions ...................................................................................................... 20-21
SVR Field Descriptions ...................................................................................................... 20-21
RSTCR Field Descriptions.................................................................................................. 20-22
LBCVSELCR Field Descriptions ....................................................................................... 20-22
DDRCSR Field Descriptions .............................................................................................. 20-23
DDRCDR Field Descriptions.............................................................................................. 20-24
DDRCLKDR Field Descriptions ........................................................................................ 20-25
CLKOCR Field Descriptions .............................................................................................. 20-26
SRDSCR0 Field Descriptions ............................................................................................. 20-27
SRDSCR1 Field Descriptions ............................................................................................. 20-28
TSEC12IOOVCR Field Descriptions ................................................................................. 20-29
TSEC34IOOVCR Field Descriptions ................................................................................. 20-29
MPC8548E Power Management Modes—Basic Description ............................................ 20-31
Power Management Entry Protocol and Initiating Functional Units .................................. 20-33
Control Register Memory Map ............................................................................................. 21-4
PMGC0 Field Descriptions ................................................................................................... 21-5
PMLCA0 Field Descriptions ................................................................................................ 21-6
PMLCA1–PMLCA9 Field Descriptions............................................................................... 21-6
PMLCB0 Field Descriptions................................................................................................. 21-7
PMLCBn Field Descriptions................................................................................................. 21-8
PMC0 Field Descriptions.................................................................................................... 21-10
PMC[1–9] Field Descriptions ............................................................................................. 21-10
Burst Definition................................................................................................................... 21-13
Performance Monitor Events .............................................................................................. 21-15
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Table
Number
21-11
21-12
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
22-12
22-13
22-14
22-15
22-16
22-17
22-18
22-19
22-20
22-21
22-22
22-23
22-24
22-25
22-26
22-27
22-28
22-29
22-30
A-1
B-1
C-1
C-2
Title
Page
Number
PMGC0 and PMLCAn Settings.......................................................................................... 21-28
Register Settings for Counting Examples ........................................................................... 21-29
POR Configuration Settings and Debug Modes ................................................................... 22-3
Debug, Watchpoint and Test Signal Summary...................................................................... 22-6
Debug Signals—Detailed Signal Descriptions ..................................................................... 22-7
Watchpoint and Trigger Signals—Detailed Signal Descriptions .......................................... 22-8
JTAG Test and Other Signals—Detailed Signal Descriptions .............................................. 22-8
Debug and Watchpoint Monitor Memory Map................................................................... 22-10
WMCR0 Field Descriptions................................................................................................ 22-11
WMCR1 Field Descriptions................................................................................................ 22-12
WMAR Field Descriptions ................................................................................................. 22-13
WMAMR Field Descriptions.............................................................................................. 22-13
WMTMR Field Descriptions .............................................................................................. 22-14
Transaction Types By Interface........................................................................................... 22-14
WMSR Field Descriptions .................................................................................................. 22-15
TBCR0 Field Descriptions.................................................................................................. 22-16
TBCR1 Field Descriptions.................................................................................................. 22-18
TBAR Field Descriptions.................................................................................................... 22-18
TBAMR Field Descriptions ................................................................................................ 22-19
TBTMR Field Descriptions ................................................................................................ 22-20
TBSR Field Descriptions .................................................................................................... 22-20
TBACR Field Descriptions ................................................................................................. 22-21
TBADHR Field Descriptions.............................................................................................. 22-22
TBADR Field Descriptions................................................................................................. 22-22
PCIDR Field Descriptions .................................................................................................. 22-23
CCIDR Field Descriptions .................................................................................................. 22-23
TOSR Field Descriptions .................................................................................................... 22-24
Source and Target ID Values............................................................................................... 22-25
CMD Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 000) .............................. 22-28
DDR Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 001) ............................... 22-29
PCI Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 010 or 101)...................... 22-29
PCI Express Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 100) ................... 22-30
Comparison of Features Among MPC8548E PowerQUICC III Processor
Family Members ............................................................................................................... A-1
Comparison of Features Among MPC8548E PowerQUICC III Processor
Family Members ................................................................................................................B-1
Comparison of Features Among MPC8548E PowerQUICC III Processor
Family Members ................................................................................................................C-1
Available L2 Cache/SRAM Configurations ...........................................................................C-3
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Title
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About This Book
This reference manual defines the functionality of the MPC8548E. This device integrates an e500v2
processor core, based on Power Architecture™ technology, with system logic required for networking,
telecommunications, and wireless infrastructure applications. The processor core is a low-power
implementation of the family of reduced instruction set computing (RISC) embedded processors that
implement the embedded category of the Power Architecture technology. This book is intended as a
companion to the PowerPC™ e500 Core Family Reference Manual.
Audience
It is assumed that the reader understands operating systems, microprocessor system design, and the basic
principles of RISC processing.
Organization
Following is a summary and a brief description of the major parts of this reference manual:
Part I, “Overview,” describes the many features of the MPC8548E integrated host processor at an
overview level. The following chapters are included:
• Chapter 1, “Overview,” provides a high-level description of features and functionality of the
MPC8548E integrated host processor. It describes the MPC8548E, its interfaces, and its
programming model. The functional operation of the MPC8548E with emphasis on peripheral
functions is also described.
• Chapter 2, “Memory Map,” describes the memory map of the MPC8548E. An overview of the
local address map is followed by a description of how local access windows are used to define the
local address map. The inbound and outbound address translation mechanisms used to map to and
from external memory spaces are described next. Finally, the configuration, control, and status
registers are described, including a complete listing of all memory-mapped registers with cross
references to the sections detailing descriptions of each.
• Chapter 3, “Signal Descriptions,” provides a listing of all the external signals, cross-references for
signals that serve multiple functions, output signal states at reset, and reset configuration signals
(and the modes they define).
• Chapter 4, “Reset, Clocking, and Initialization,” describes the hard and soft resets, the power-on
reset (POR) sequence, power-on reset configuration, clocking, and initialization of the
MPC8548E.
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Part II, “e500 Core Complex and L2 Cache,” describes the many features of the MPC8548E core processor
at an overview level and the interaction between the core complex and the L2 cache. The following
chapters are included:
• Chapter 5, “Core Complex Overview,” provides an overview of the e500v2 core processor and the
L1 caches and MMU that, together with the core, comprise the core complex.
• Chapter 6, “Core Register Summary,” provides a listing of the e500v2 registers in reference form.
• Chapter 7, “L2 Look-Aside Cache/SRAM,” describes the L2 cache of the MPC8548E. Note that
the L2 cache can also be addressed directly as memory-mapped SRAM.
Part III, “Memory, Security, and I/O Interfaces,” defines the memory, security, and I/O interfaces of the
MPC8548E and how these blocks interact with one another and with other blocks on the device. The
following chapters are included:
• Chapter 8, “e500 Coherency Module,” defines the e500v2 coherency module and how it facilitates
communication between the e500v2 core complex, the L2 cache, and the other blocks that
comprise the coherent memory domain of the MPC8548E.
The ECM provides a mechanism for I/O-initiated transactions to snoop the core complex bus
(CCB) of the e500v2 core in order to maintain coherency across cacheable local memory. It also
provides a flexible, easily expandable switch-type structure for e500v2- and I/O-initiated
transactions to be routed (dispatched) to target modules on the MPC8548E.
• Chapter 9, “DDR Memory Controller,” describes the DDR/DDR2 SDRAM memory controller of
the MPC8548E. This fully programmable controller supports most DDR memories available
today, including both buffered and unbuffered devices. The built-in error checking and correction
(ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic power
management and auto-precharge modes simplify memory system design. Special features like
ECC error injection support rapid system debug.
• Chapter 10, “Programmable Interrupt Controller,” describes the embedded programmable
interrupt controller (PIC) of the MPC8548E. The PIC is an OpenPIC-compliant interrupt controller
that provides interrupt management and is responsible for receiving hardware-generated interrupts
from different sources (both internal and external), prioritizing them and delivering them to the
CPU for servicing.
• Chapter 11, “I2C Interfaces,” describes the inter-IC (IIC or I2C) bus controllers of the MPC8548E.
This synchronous, serial, bidirectional, multi-master bus allows two-wire connection of devices,
such as microcontrollers, EEPROMs, real-time clock devices, A/D converters and LCDs. The
MPC8548E powers up in boot sequencer mode which allows the I2C1 controller to initialize
configuration registers.
• Chapter 12, “DUART,” describes the (dual) universal asynchronous receiver/transmitters
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
• Chapter 13, “Local Bus Controller,” describes the local bus controller of the MPC8548E. The main
component of the local bus controller (LBC) is its memory controller which provides a seamless
interface to many types of memory devices and peripherals. The memory controller is responsible
for controlling eight memory banks shared by a high performance SDRAM machine, a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines
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•
•
•
•
•
•
(UPMs). As such, it supports a minimal glue logic interface to synchronous DRAM (SDRAM),
SRAM, EPROM, Flash EPROM, burstable RAM, regular DRAM devices, extended data output
DRAM devices, and other peripherals.
Chapter 14, “Enhanced Three-Speed Ethernet Controllers,” describes the four enhanced
three-speed Ethernet controllers on the MPC8548E. These controllers provide 10/100/1Gb
Ethernet support with a complete set of media-independent interface options including MII, RMII,
GMII, RGMII, TBI, and RTBI. Each controller provides very high throughput using a captive
DMA channel and direct connection to the MPC8548E memory coherency module. The
controllers provide four full-duplex FIFO interface modes and quality of service support. They are
backward compatible with PowerQUICC III TSEC controllers.
Chapter 15, “DMA Controller,” describes the four-channel general-purpose DMA controller of the
MPC8548E. The DMA controller transfers blocks of data independent of the e500v2 core or
external hosts. Data movement occurs among the local address space. The DMA controller has four
high-speed channels. Both the e500 core and external masters can initiate a DMA transfer. All
channels are capable of complex data movement and advanced transaction chaining.
Chapter 16, “PCI/PCI-X Bus Interface,” describes the PCI controller of the MPC8548E.
Chapter 17, “Serial RapidIO Interface,” describes the serial RapidIO interface of the MPC8548E.
Chapter 18, “PCI Express Interface Controller,” describes the PCI-Express implementation of the
MPC8548E.
Chapter 19, “Security Engine (SEC) 2.1,” describes the security controller of the MPC8548E.
Part IV, “Global Functions and Debug,” defines other global blocks of the MPC8548E. The following
chapters are included:
• Chapter 20, “Global Utilities,” defines the global utilities of the MPC8548E. These include power
management, I/O device enabling, power-on-reset (POR) configuration monitoring,
general-purpose I/O signal use, and multiplexing for the interrupt and local bus chip select signals.
• Chapter 21, “Device Performance Monitor,” describes the performance monitor of the
MPC8548E. Note that the MPC8548E performance monitor is similar to but separate from the
performance monitor implemented on the e500v2 core.
• Chapter 22, “Debug Features and Watchpoint Facility,” describes the debug features and
watchpoint monitor of the MPC8548E.
This manual contains appendixes describing the other members of the MPC8548E family and an appendix
containing the manual’s revision history. These appendixes are as follows:
• Appendix A, “MPC8547E,” contains the text of the product brief of this derivative of the
MPC8548E.
• Appendix B, “MPC8545E,” contains the text of the product brief of this derivative of the
MPC8548E.
• Appendix C, “MPC8543E,” contains the text of the product brief of this derivative of the
MPC8548E.
• Appendix D, “Revision History,” lists the major differences between revisions of the MPC8548E
PowerQUICC III Integrated Processor Family Reference Manual.
This reference manual also includes a glossary, a register index and a general index.
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Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor,
San Francisco, CA, provides useful information about the Power Architecture technology and computer
architecture in general:
• The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
• Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and David
A. Patterson
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, by David
A. Patterson and John L. Hennessy
Related Documentation
Freescale documentation is available from the sources listed on the back cover of this manual; the
document order numbers are included in parentheses for ease in ordering:
• EREF: A Reference for Freescale Book E and the e500 Core (Freescale order no. EREF)—This
book, sometimes refered to simply as EREF, provides a higher-level view of the programming
model as it is defined by Book E, the Freescale Book E implementation standards, and the e500
microprocessor.
• PowerPC™ e500 Core Family Reference Manual (Freescale order no. E500CORERM)—This
book provides in-depth coverage of the e500 embedded microprocessor core for hardware and
software developers.
• Reference manuals (formerly called user’s manuals)—These books provide details about
individual implementations.
• Addenda/errata to reference or user’s manuals—Because some processors have follow-on parts an
addendum is provided that describes the additional features and functionality changes. These
addenda are intended for use with the corresponding reference or user’s manuals.
• Hardware specifications—Hardware specifications provide specific data regarding bus timing,
signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
• Product Briefs—Each device has a technical summary that provides an overview of its features.
This document is roughly equivalent to the overview (Chapter 1) of an implementation’s reference
or user’s manual.
• Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale processors.
Additional literature is published as new processors become available. For a current list of documentation,
refer to http://www.freescale.com.
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Conventions
This document uses the following notational conventions:
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics
Internal signals are set in lowercase italics, for example, core_int
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
Instruction syntax used to identify a source GPR
rD
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations for registers are shown in uppercase text. Specific bits, fields, or
ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode
enable bit in the machine state register.
x
In some contexts, such as signal encodings, an unitalicized x indicates a don’t
care.
x
An italicized x indicates an alphanumeric variable.
n
An italicized n indicates a numeric variable.
¬
NOT logical operator
&
AND logical operator
|
OR logical operator
||
Concatenation, for example TCR[WP]||TCR[WPEXT]
Indicates a reserved bit field in a memory-mapped or an e500 register.
R
—
W
Indicates a read-only bit field in a memory-mapped register.
R FIELDNAME
W
Indicates a write-only bit field in a memory-mapped register. Although these bits
can be written to as ones or zeros, they are always read as zeros.
R
W FIELDNAME
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Signal Conventions
OVERBAR
lowercase_italics
lowercase_plaintext
An overbar indicates that a signal is active-low.
Lowercase italics is used to indicate internal signals.
Lowercase plain text is used to indicate signals that are used for configuration. For
more information, see Section 3.2, “Configuration Signals Sampled at Reset.”
Acronyms and Abbreviations
Table i contains acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term
ADB
ATMU
Meaning
Allowable disconnect boundary
Address translation and mapping unit
BD
Buffer descriptor
BIST
Built-in self test
BTB
Branch target buffer
BUID
Bus unit ID
CAM
Content-addressable memory
CCB
Core complex bus
CCSR
Configuration control and status register
CEPT
Conférence des administrations européenes des postes et télécommunications (European Conference
of Postal and Telecommunications Administrations)
COL
Collision
CRC
Cyclic redundancy check
CRS
Carrier sense
DDR
Double data rate
DMA
Direct memory access
DPLL
Digital phase-locked loop
DRAM
Dynamic random access memory
DUART
Dual universal asynchronous receiver/transmitter
EA
Effective address
ECC
Error checking and correction
ECM
e500 coherency module
EHPI
Enhanced host port interface
EPROM
Erasable programmable read-only memory
FCS
Frame-check sequence
FEC
10/100 fast Ethernet controller
GCI
General circuit interface
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Table i. Acronyms and Abbreviated Terms (continued)
Term
GMII
Meaning
Gigabit media independent interface
GPCM
General-purpose chip-select machine
GPIO
General-purpose I/O
GPR
General-purpose register
GUI
Graphical user interface
I2C
Inter-integrated circuit
IDL
Inter-chip digital link
IEEE
Institute of Electrical and Electronics Engineers
IPG
Interpacket gap
IrDA
Infrared Data Association
ITLB
Instruction translation lookaside buffer
IU
Integer unit
JTAG
Joint Test Action Group
LAE
Local access error
LAW
Local access window
LBC
Local bus controller
LIFO
Last-in-first-out
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
LSU
Load/store unit
MAC
Multiply accumulate, media access control
MDI
Medium-dependent interface
MESI
Modified/exclusive/shared/invalid—cache coherency protocol
MII
Media independent interface
MMU
Memory management unit
MSB
Most-significant byte
msb
Most-significant bit
NMSI
Nonmultiplexed serial interface
No-op
No operation
OCeaN
On-chip network
OSI
Open systems interconnection
PCI
Peripheral component interconnect bus
PCMCIA
Personal Computer Memory Card International Association
PCS
Physical coding sublayer
PIC
Programmable interrupt controller
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Table i. Acronyms and Abbreviated Terms (continued)
Term
Meaning
PMA
Physical medium attachment
PMD
Physical medium dependent
POR
Power-on reset
RGMII
Reduced gigabit media independent interface
RISC
Reduced instruction set computing
RTOS
Real-time operating system
RWITM
RWM
Rx
Read with intent to modify
Read modify write
Receive
RxBD
Receive buffer descriptor
SCC
Serial communication controller
SCP
Serial control port
SDLC
Synchronous data link control
SDMA
Serial DMA
SFD
SI
Start frame delimiter
Serial interface
SIU
System interface unit
SPR
Special-purpose register
SRAM
Static random access memory
TAP
Test access port
TBI
Ten-bit interface
TDM
Time-division multiplexed
TLB
Translation lookaside buffer
TSA
Time-slot assigner
TSEC
Tx
Three-speed Ethernet controller
Transmit
TxBD
Transmit buffer descriptor
UART
Universal asynchronous receiver/transmitter
UPM
User-programmable machine
USB
Universal serial bus
UTP
Unshielded twisted pair
VA
ZBT
Virtual address
Zero bus turnaround
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Part I
Overview
Part I describes the many features of the MPC8548E integrated host processor at an overview level. The
following chapters are included:
Chapter 1, “Overview,” provides a high-level description of features and functionality of the MPC8548E
integrated host processor. It describes the MPC8548E, its interfaces, and programming model. The
functional operation of the MPC8548E, with emphasis on peripheral functions, is also described.
Chapter 2, “Memory Map,” describes the MPC8548E memory map. An overview of the local address map
is followed by a description of how local access windows are used to define the local address map. The
inbound and outbound address translation mechanisms used to map to and from external memory spaces
are described next. Finally, the configuration, control, and status registers are described, including a
complete listing of all memory mapped registers with cross references to the sections detailing descriptions
of each.
Chapter 3, “Signal Descriptions,” provides a listing of all the external signals, cross-references for signals
that serve multiple functions, output signal states at reset, and reset configuration signals (and the modes
they define).
Chapter 4, “Reset, Clocking, and Initialization,” describes the hard and soft resets, power-on reset
sequence, power-on reset (POR) configuration, clocking, and initialization of the MPC8548E.
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Chapter 1
Overview
The MPC8548E integrates an e500v2 processor core built on Power Architecture™ technology with
system logic required for networking, telecommunications, and wireless infrastructure applications. The
MPC8548E is a member of the PowerQUICC™ III family of devices that combine system-level support
for industry-standard interfaces with processors that implement the embedded category of the Power
Architecture technology. This chapter provides a high-level description of features and functionality of the
MPC8548E integrated processor.
Although this chapter is written from the perspective of the MPC8548E, most of the material applies to
the MPC8547E, MPC8545E, and MPC8543E as well. For information on differences between these parts
and the MPC8548E, see Appendix A, “MPC8547E,” Appendix B, “MPC8545E,” and Appendix C,
“MPC8543E.”
1.1
Introduction
The MPC8548E uses the e500 core and high-speed interconnect technology to balance processor
performance with I/O system throughput. The e500 core implements the Power Architecture™ definition
of the embedded category instruction set architecture and provides unprecedented levels of hardware and
software debugging support.
In addition, the MPC8548E offers a double-precision floating-point auxiliary processing unit (APU),
512 Kbytes of level-2 cache, four integrated 10/100/1Gb enhanced three-speed Ethernet controllers
(eTSECs) with TCP/IP acceleration and classification capabilities, a DDR/DDR2 SDRAM memory
controller, two PCI/PCI-X controllers that can serve as a single 64-bit PCI/PCI-X controller or two 32-bit
controllers, a programmable interrupt controller, two I2C controllers, a four-channel DMA controller, an
integrated security engine with XOR acceleration, a general-purpose I/O port, and dual universal
asynchronous receiver/transmitters (DUART). For high speed interconnect, the MPC8548E provides a set
of multiplexed pins that support two high-speed interface standards: 1x/4x serial RapidIO (with message
unit) and up to x8 PCI Express. The high level of integration in the MPC8548E helps simplify board design
and offers significant bandwidth and performance.
The MPC8548E is also available without a security engine, in a configuration known as the MPC8548. All
specifications other than those relating to security apply to the MPC8548 exactly as described in this
document.
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Overview
1.2
MPC8548E Overview
This section provides a high-level overview of MPC8548E features. Figure 1-1 shows the major functional
units within the MPC8548E.
DDR
SDRAM
DDR/DDR2/
Memory Controller
Security
Engine
Flash
SDRAM
GPIO
Local Bus Controller
XOR
Engine
Programmable Interrupt
Controller (PIC)
IRQs
Serial
DUART
I2C
I2C
Controller
I2C
I2C
Controller
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
RTBI, RGMII,
RMII
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
e500
Coherency
Module
512-Kbyte
L2 Cache/
SRAM
Core Complex
Bus
e500 Core
32-Kbyte L1
Instruction
Cache
Serial RapidIO
or
PCI Express
OceaN
Switch
Fabric
32-bit PCI Bus Interface
(If 64-bit not used)
32-bit PCI/
64-bit PCI/PCI-X
Bus Interface
32-Kbyte
L1 Data
Cache
4x RapidIO
x8 PCI Express
PCI 32-bit
66 MHz
PCI/PCI-X
133 MHz
4-Channel DMA
Controller
Figure 1-1. MPC8548E Block Diagram
1.2.1
Key Features
The following list provides an overview of the MPC8548E feature set:
• High-performance 32-bit enhanced e500 core that implements the embedded category of the Power
Architecture technology
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis, with separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64-bit) integer and fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
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Overview
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•
•
— 36-bit real addressing (up to 64 Gbytes of memory)
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte–4-Gbyte page sizes.
— Enhanced hardware and software debug support
— Performance monitor facility that is similar to, but separate from, the MPC8548E performance
monitor
The e500 defines features that are not implemented on the MPC8548E. It also generally defines
some features that the MPC8548E implements more specifically. An understanding of these
differences can be critical to ensure proper operations.
Section 1.3.1, “e500 Core Overview,” includes a comprehensive list of e500 core features.
512-Kbyte L2 cache/SRAM
— Flexible configuration. See Section 1.3.2, “On-Chip Memory Unit,” for more information.
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
– One, two, or four ways can be configured for stashing only
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions.
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately.
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
Address translation and mapping unit (ATMU)
— Ten local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express
– Four inbound windows plus a default window on RapidIO
– Four outbound windows plus default translation for PCI/PCI-X and PCI Express
– Eight outbound windows plus default translation for RapidIO with segmentation and
sub-segmentation support
DDR/DDR2 memory controller
— Programmable timing supporting DDR and DDR2 SDRAM
— 64-bit data interface
— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes
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•
— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16/x32 data ports
— Full ECC support
— Page mode support
– Up to 16 simultaneous open pages for DDR
– Up to 32 simultaneous open pages for DDR2
— Contiguous or discontiguous memory mapping
— Chip select interleaving support
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
— Sleep mode support for self-refresh SDRAM
— On-die termination support when using DDR2
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)
— Support for battery-backed main memory
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports shared message signaled interrupts
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports a variety of other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, WTLS/WAP, SSL/TLS, and 3GPP
— Four crypto-channels, each supporting multi-command descriptor chains
– Dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
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Overview
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•
•
— PKEU—public key execution unit
– RSA and Diffie-Hellman; programmable field size up to 2048 bits
– Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to
511 bits
— DEU—Data Encryption Standard (DES) execution unit
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— AESU—Advanced Encryption Standard (AES) unit
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, and CCM modes
– 128-, 192-, and 256-bit key lengths
— AFEU—ARC four execution unit
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— MDEU—message digest execution unit
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— KEU—Kasumi execution unit
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA-3 algorithms
— RNG—random number generator
— XOR engine accelerates parity checking in RAID storage applications.
Dual I2C controllers
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I2C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I2C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
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Overview
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•
Local bus controller (LBC)
— Multiplexed 32-bit address and data bus operating at up to 166 MHz
— Eight chip selects support eight external slaves.
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Four enhanced three-speed Ethernet controllers (eTSECs)
— Backward compatible with MPC8540/MPC8560 (PowerQUICC III) TSEC
— Three-speed support (10/100/1000 Mbps)
— Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
— Support for four full-duplex FIFO interface modes
— Support for various Ethernet physical interfaces:
– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII
– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMI
— Flexible configuration for multiple PHY interface configurations. See Section 1.3.13,
“Enhanced Three-Speed Ethernet Controllers (eTSECs),” for more information.
— TCP/IP acceleration and QoS features available
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
– Supported in all FIFO modes
— Quality of service support:
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE
802.1 virtual local area network (VLAN) tags and priority
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Overview
•
•
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound frames
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
— MAC address recognition:
– Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
– Up to 16 exact-match MAC addresses supported
– Broadcast address (accept/reject)
– Hash table match on up to 512 multicast addresses
– Promiscuous mode
— Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
— RMON statistics support
— 10-Kbyte internal transmit and 2-Kbyte receive FIFOs
— MII management interface for control and status
— Ability to force allocation of header information and buffer descriptors into L2 cache
OCeaN switch fabric
— Full crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
Integrated DMA controller
— Four-channel controller
— All channels accessible by both the local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
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Overview
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•
Two PCI/PCI-X controllers
— PCI 2.2 and PCI-X 1.0 compatible
— One 32-/64-bit PCI/PCI-X port with support for speeds of up to 133 MHz (maximum PCI-X
speed is 110 MHz when operated in synchronous mode)
— Second 32-bit PCI port with support for speeds from 16 to 66 MHz (available when the first
port is in 32-bit mode)
— Host and agent mode support
— 64-bit dual address cycle (DAC) support
— PCI-X supports multiple split transactions
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
Serial RapidIO interface unit
— Supports RapidIO Interconnect Specification, Revision 1.2
— Both 1x and 4x LP-serial link interfaces
— Long- and short-haul electricals with selectable pre-compensation
— Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane
— Auto detection of 1x- and 4x-mode operation during port initialization
— Link initialization and synchronization
— Large and small size transport information field support selectable at initialization time
— 34-bit addressing
— Up to 256 bytes data payload
— All transaction flows and priorities
— Atomic set/clr/inc/dec for read-modify-write operations
— Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at
a remote memory system
— Receiver-controlled flow control
— Error detection, recovery, and time-out for packets and control symbols as required by the
RapidIO specification
— Register and register bit extensions as described in part VIII (Error Management) of the
specification
— Hardware recovery only
— Register support is not required for software-mediated error recovery.
— Accept-all mode of operation for fail-over support
— Support for RapidIO error injection
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Overview
•
•
•
•
•
— Internal LP-serial and application interface-level loopback modes
— Memory and PHY BIST for at-speed production test
RapidIO–compliant message unit
— 4 Kbytes of payload per message
— Up to sixteen 256-byte segments per message
— Two inbound data message structures within the inbox
— Capable of receiving three letters at any mailbox
— Two outbound data message structures within the outbox
— Capable of sending three letters simultaneously
— Single segment multicast to up to 32 devIDs
— Chaining and direct modes in the outbox
— Single inbound doorbell message structure
— Facility to accept port-write messages
PCI Express interface
— PCI Express 1.0a compatible
— Supports x8, x4, x2, and x1 link widths
— Auto-detection of number of connected lanes
— Selectable operation as root complex or endpoint
— Both 32- and 64-bit addressing
— 256-byte maximum payload size
— Virtual channel 0 only
— Full 64-bit decode with 36-bit wide windows
Pin multiplexing for the high speed I/O interfaces supports one of the following configurations:
— x8 PCI Express
— x4 PCI Express and 4x serial RapidIO
Power management
— Supports power saving modes: doze, nap, and sleep
— Employs dynamic power management, which automatically minimizes power consumption of
blocks when they are idle
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter-specific events
— Supports 64 reference events that can be counted on any of the eight counters
— Supports duration and quantity threshold counting
— Burstiness feature permits counting of burst events with a programmable time between bursts.
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
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Overview
•
•
•
1.3
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE 1149.1 compliant, JTAG boundary scan
783 FC-PBGA package
MPC8548E Architecture Overview
The following sections describe the major functional units of the MPC8548E.
1.3.1
e500 Core Overview
This device uses the e500 microprocessor core complex. The e500 core has an internal PLL that allows
independent optimization of the operating frequencies. The core frequencies are derived from either the
primary PCI clock input or an external oscillator. For background information regarding the e500 core
refer to the following documents:
• EREF: A Reference for Freescale Book E and the e500 Core (Freescale order no. EREF)
• PowerPC™ e500 Core Family Reference Manual (Freescale order no. E500CORERM)
• PowerPC™ e500 Application Binary Interface User's Guide (Freescale order no. E500ABIUG)
NOTE
The e500 defines features that are not implemented on this device. It also
generally defines some features that this device implements more
specifically. An understanding of these differences can be critical to ensure
proper operations.
The following is a brief list of some of the key features of the e500 core complex:
• Implements full Book E 32-bit architecture
• Implements additional instructions, registers, and interrupts defined by auxiliary processing units
(APUs). The SPE APU provides an extensive instruction set for 64-bit vector integer and fractional
operations. The embedded floating-point APUs provide vector single-precision instructions that
operate on operands comprised of two 32-bit elements; the single-precision scalar instructions use
only the bottom word. The double-precision floating-point APU provides scalar (64-bit)
double-precision floating-point instructions that use the 64-bit GPRs.
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Overview
NOTE
The SPE APU and double-precision floating-point APU functionality is
implemented in all PowerQUICC III devices. However, these instructions
will not be supported in devices subsequent to PowerQUICC III. Freescale
strongly recommends that use of these instructions be confined to libraries
and device drivers. Customer software that uses SPE, double-precision
floating-point, or embedded floating-point APU instructions at the
assembly level or that uses SPE intrinsics will require rewriting for upward
compatibility with next-generation PowerQUICC devices.
Freescale offers a libcfsl_e500 library that uses SPE APU instructions.
Freescale will also provide libraries to support next-generation
PowerQUICC devices.
•
•
•
•
•
•
•
L1 cache structure
— 32-Kbyte, 32-byte line, eight-way set-associative instruction cache
— 32-Kbyte, 32-byte line, eight-way set-associative data cache
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU replacement algorithm
— Copy-back data cache
Dual-dispatch superscalar
Precise exception handling
Seven-stage pipeline control
Instruction unit
— Twelve-entry instruction queue
— Full hardware detection of interlocks
— Dispatch of up to two instructions per cycle
— Dispatch serialization control
— Register dependency resolution and renaming
Branch unit (BU)
— Dynamic branch prediction
— Two-entry branch instruction queue (BIQ)
— Executes all branch and CR logical instruction
Completion unit
— As many as 14 instructions allowed in 14-entry completion queue
— In-order retirement of up to two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts and mispredicted branches
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•
•
•
•
•
•
•
•
Two simple execution units that perform:
— Single-cycle add and subtract
— Single-cycle shift and rotate
— Single-cycle logical operations
— Supports integer signal processing operations
Multiple-cycle execution unit (MU)
— 4-cycle latency for integer and floating-point multiplication (including integer, fractional, and
both vector and scalar floating-point multiply instructions)
— Variable-latency divide: 4, 11, 19, and 35 cycles for all Book E, SPE, and embedded
floating-point divide instructions. Note that the MU allows divide instructions to bypass the
second two MU pipeline stages, freeing those stages for other MU instructions to execute in
parallel.
— 4-cycle floating-point multiply
— 4-cycle floating-point add and subtract
Double-precision floating-point APU
Signal processing engine APU (SPE APU). The single instruction multiple data (SIMD) capability
provided by the 64-bit execution units (MIU, LSU, SIU1) is not a separate execution unit. The
hardware that executes 32-bit Book E instructions also executes the lower half of 64-bit SPE APU
instructions.
— Single-cycle integer add and subtract
— Single-cycle logical operations
— Single-cycle shift and rotate
— 4-cycle integer pipelined multiplies
— 4-, 11-, 19-, and 35-cycle integer divides
— 4-cycle SIMD pipelined multiply-accumulate (MAC)
— 64-bit accumulator for MAC operations
Single-precision vector and scalar floating-point APUs
Load/store unit (LSU)
— 3-cycle load latency
— Fully pipelined
— Nine-entry load queue allows up to nine load misses before stalling
— Can continue servicing load hits when load queue is full
— Six-entry store queue allows full pipelining of stores
Cache coherency
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)
— High-speed, on-chip local bus with data tagging
— 36-bit address bus
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— 60x-like address protocol with address pipelining and retry/copyback
— Two general-purpose read data, one write data bus
— 128-bit data plus parity/tags (each data bus)
— Supports out-of-order reads, in-order writes
— Little to no data bus arbitration logic required for native systems
— Supports one-level pipelining of addresses with address-retry responses
Extended exception handling
— Supports Book E interrupt model
– Interrupt vector prefix register (IVPR)
– Interrupt vector offset registers (IVORs) 0–15 as defined in Book E plus e500-defined
IVORs 32–35
– Exception syndrome register (ESR)
– Book E–defined preempting critical interrupt, including critical interrupt status registers
(CSRR0 and CSRR1) and an rfci instruction
— e500-specific interrupts not defined in Book E architecture
– SPE APU unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
Memory management unit (MMU)
— Data L1 MMU
– Four-entry, fully-associative TLB array for variable-sized pages
– 64-entry, four-way set-associative TLB for 4-Kbyte pages
— Instruction L1 MMU
– Four-entry, four-way set-associative TLB for 4-Kbyte pages
— Unified L2 MMU
– 16-entry, fully-associative TLB array for variable-sized pages
– 512-entry, four-way set-associative TLB for 4-Kbyte pages
— Software reload for TLBs
— Support for as much as 4 Gbytes (232) of virtual memory
— Support for as much as 64 Gbytes (236) of physical memory
— Support for big-endian and true little-endian memory on a per-page basis
Power management
— Dynamic power management on the core minimizes power consumption of functional units,
such as execution units, caches, and MMUs, when they are idle.
— Core power-saving modes: core-halted and core-stopped
— NAP, DOZE, and SLEEP bits in HID0 that can be used to assert nap, doze, and sleep core
output signals to initiate power-saving modes at the integrated device level.
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•
1.3.2
Testability
— LSSD scan design
— JTAG interface
— ESP support
On-Chip Memory Unit
The MPC8548E contains an internal 512-Kbyte memory array that can be configured as memory-mapped
SRAM or as a look-aside L2 cache. The array can also be divided into two arrays, one of which may be
used as cache and the other as SRAM.
The memory controller for this array connects to the core complex bus (CCB) and communicates via
128-bit read and write buses to the e500 core and the MPC8548E system logic.
The on-chip memory unit contains:
• 512 Kbytes of on-chip memory
— L2 cache partitioning is configurable; see Table 1-1 for detailed information.
– Can act as a 512-Kbyte L2 cache
– 512-Kbyte array organized as 2048 eight-way sets of 32-byte cache lines
– Array can be partitioned into either L2 cache or memory mapped SRAM on a 1-, 2-, 4-, or
8-way basis
– Stashing of I/O data into the L2 array is supported, but can be limited to a 1-, 2-, or 4-way
basis
— SRAM operation is byte-accessible.
— Data ECC on 64-bit boundaries (single-error correction, double-error detection)
— Tag parity (1 bit covering all tag bits)
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types.
— Separate locking for instructions and data so that locks can be set and cleared separately
— Supports locking the entire cache or selected lines
– Individual line locks are set and cleared through core-initiated instructions, by external
reads or writes, or by accesses to programmed memory ranges.
— Flash clearing done through writes to L2 configuration registers
— Locks for the entire cache may be set and cleared by accesses to memory-mapped control
registers.
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Table 1-1 lists the possible L2 cache/SRAM configurations.
Table 1-1. Available L2 Cache/SRAM Configurations
Cache
Stash-only Region
SRAM Region 1
SRAM Region 2
512 Kbytes
—
—
—
448 Kbytes
384 Kbytes
—
64 Kbytes
—
64 Kbytes
—
—
—
128 Kbytes
—
64 Kbytes
64 Kbytes
64 Kbytes
—
128 Kbytes
—
—
64 Kbytes
128 Kbytes
—
64 Kbytes
64 Kbytes
64 Kbytes
320 Kbytes
256 Kbytes
128 Kbytes
64 Kbytes
—
—
256 Kbytes
—
128 Kbytes
128 Kbytes
128 Kbytes
192 Kbytes
128 Kbytes
128 Kbytes
—
64 Kbytes
64 Kbytes
256 Kbytes
—
—
64 Kbytes
256 Kbytes
—
128 Kbytes
128 Kbytes
256 Kbytes
64 Kbytes
—
128 Kbytes
256 Kbytes
—
128 Kbytes
128 Kbytes
256 Kbytes
—
—
256 Kbytes
1.3.3
128 Kbytes
—
64 Kbytes
64 Kbytes
512 Kbytes
—
256 Kbytes
256 Kbytes
256 Kbytes
—
128 Kbytes
128 Kbytes
On-Chip Memory as Memory-Mapped SRAM
When the on-chip memory is configured as an SRAM, the memory can be configured to reside at any
aligned location in the memory map. It is byte-accessible, and fully ECC protected using
read-modify-write transactions for sub-cache-line transactions. I/O devices can access the SRAM by
marking transactions global so that they are directed to the CCB.
1.3.4
On-Chip Memory as L2 Cache
The on-chip memory arrays include a 512-Kbyte data array, an address tag array, and a status array.
The data array is organized as 2048 sets of eight cache lines. Each cache line size is 32 bytes. The
replacement policy within each eight-way set is governed by a pseudo-LRU algorithm. The data is
protected with ECC and the tag array is protected by parity.
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The L2 cache tags are non-blocking for efficient load/store and snooping operations. The L2 cache can be
accessed internally while a load miss is pending (allowing hits under misses). Subsequent to a load miss
updating the memory, loads or stores can occur to that line on the very next cycle.
The L2 status array maintains status bits for each line that are used to determine the status of the line.
Different combinations of these bits result in different L2 states. Note that because the cache is always
write-through, there is no modified state. The status bits include:
• V—Valid
• IL—Instruction locked
• DL—Data locked
All accesses to the L2 memory are fully pipelined so back-to-back loads and stores can have single-cycle
throughput.
The cache can be configured to allocate instructions only, data only, or both. It can also be configured to
allocate global I/O writes that correspond to a programmable address window or that use a special
transaction type (stashing). In this way, DMA engines or I/O devices can force data into the cache.
Line locks can be set in a variety of ways. The Book E architecture defines instructions that explicitly set
and clear locks in the L2. These instructions are supported by the core complex and the L2 controller. In
addition, the L2 controller can be configured to lock all lines that fall into either of two specified address
ranges when the line is allocated. Finally, the entire cache can be locked by writing to a configuration
register in the L2 cache controller.
The status array tracks line locks as either instruction locks or data locks for each line, and the status array
supports flash clearing of all instruction locks or data locks separately by writes to configuration registers
in the L2 controller.
1.3.5
e500 Coherency Module (ECM)
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be
routed or dispatched to target modules on the device.
1.3.6
DDR SDRAM Controller
The MPC8548E supports DDR and DDR2 SDRAM. The memory interface controls main memory
accesses and provides for a maximum of 16 Gbytes of main memory. The memory controller can be
configured to support the various memory sizes through software initialization of on-chip configuration
registers.
The MPC8548E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs
or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of
64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support
up to four banks of memory. The MPC8548E supports bank sizes from 64 Mbytes to 4 Gbytes. Nine
column address strobes (MDM[0:8]) are used to provide byte selection for memory bank writes.
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The MPC8548E can be configured to retain the currently active SDRAM page for pipelined burst accesses.
Page mode support of up to 16 simultaneously open pages (32 for DDR2) can dramatically reduce access
latencies for page hits. Depending on the memory system design and timing parameters, using page mode
can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page.
The MPC8548E supports error checking and correction (ECC) for system memory. Using ECC, the
MPC8548E detects and corrects all single-bit errors and detects all double-bit errors and all errors within
a nibble.
The MPC8548E can invoke a level of system power management by asserting the MCKE SDRAM signal
on-the-fly to put the memory into a low-power sleep mode.
The MPC8548E offers the following options to support battery-backed main memory:
• Hardware based
An external voltage sense device is connected to the MPC8548E via an interrupt line. The external
interrupt from this device is steered through the MPC8548E interrupt controller to the IRQ_OUT
signal. The IRQ_OUT signal from the interrupt controller is steered to an enable bit in the DDR
controller which immediately causes main memory to enter self-refresh mode.
This proposal precludes any other simultaneous use of IRQ_OUT.
• Software based
The DDR controller also has a software-programmable bit that immediately puts main memory
into self-refresh mode.
It is expected that a critical interrupt routine triggered by an external voltage sense device will have
time to set this bit.
The DDR controller offers an initialization bypass feature which system designers may use to prevent
re-initialization of main memory during system power-on following abnormal shutdown.
1.3.7
Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for a general-purpose interrupt control. The interrupt controller unit implements the logic and
programming structures of the OpenPIC architecture. The MPC8548E interrupt controller unit supports its
processor core and provides for 12 external interrupts (with fully nested interrupt delivery), four message
interrupts, internal-logic driven interrupts, and four global high resolution timers. Up to 16 programmable
interrupt priority levels are supported.
The MPC8548E supports reception of interrupt messages from the PCI Express interface. The PIC
supports INTx and message signaled interrupts (MSI) from the PCI Express interface. Four INTx
interrupts are presented as independent PIC interrupt sources. There are 256 individual MSI interrupt
sources supported as eight groups of 32 sources. Each of the eight groups constitutes an independent PIC
interrupt source. Individual interrupt sources have associated with them a vector, priority, and destination
value.
The interrupt controller unit can be bypassed to allow use of an external interrupt controller.
Inter-processor interrupt (IPI) communication is supported through the external interrupt and core reset
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signals of different processor cores on the same device. The four IPIs are only used for self-interrupt in a
single-core device such as the MPC8548E.
1.3.8
Integrated Security Engine (SEC) for the MPC8548E
NOTE
The features described in this section are only available on the MPC8548E.
The MPC8548 does not include an integrated security engine.
The SEC is a modular and scalable security core optimized to process all the algorithms associated with
IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is
designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of
the data, and every effort has been made to provide the SEC with the flexibility to perform single-pass
operations for current and emerging security protocols. The version of the SEC used in the MPC8548E is
specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL
3.1/TLS 1.0, IPSec, SRTP, and 802.11i.
A block diagram of the integrated security engine’s internal architecture is shown in Figure 1-2. The bus
interface module is designed to transfer 64-bit words between the internal bus and any register inside the
SEC.
Cryptochannel
Cryptochannel
Master/
Slave
Interface
Cryptochannel
Cryptochannel
Control
PKEU
FIFO
FIFO
FIFO
FIFO
FIFO
DEU
MDEU
AFEU
KEU
RNG
FIFO
FIFO
AESU
XOR
FIFO
FIFO
FIFO
FIFO
Figure 1-2. Integrated Security Engine Functional Blocks
An operation begins with a write of a pointer to a crypto-channel fetch register that points to a data packet
descriptor. The channel requests the descriptor and decodes the operation to be performed. The channel
then requests the controller to assign crypto-execution units and fetch the keys, IVs, and data needed to
perform the given operation. The controller satisfies the requests by assigning execution units to the
channel and by making requests to the master interface. As data is processed, it is written to the individual
execution unit’s output buffer and then back to system memory via the bus interface module.
The SEC functionality is compatible with code written for the integrated security engine present in the
Freescale MPC8541E and MPC8555E devices.
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The SEC also offers acceleration of the exclusive OR (XOR) operation used to generate parity data in
RAID applications. XOR operations use SEC descriptors and offload both parity generation and data
movement from the e500 core.
1.3.9
I2C Controllers
The MPC8548E provides two inter-IC (IIC or I2C) interfaces. The I2C bus is a two-wire, bidirectional
serial bus that provides a simple, efficient method of data exchange between devices. The synchronous,
multi-master bus of the I2C allows the MPC8548E to exchange data with other I2C devices such as
microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire bus
(serial data SDA and serial clock SCL) minimizes the interconnections between devices. I2C allows the
connection of additional devices to the bus for expansion and system development.
The I2C controller is a true multimaster bus which includes collision detection and arbitration that prevents
data corruption if two or more masters attempt to control the bus simultaneously. This feature allows for
complex applications with multiprocessor control. The I2C controller consists of a transmitter/receiver
unit, a clocking unit, and a control unit. The dual I2C units support general broadcast mode, and on-chip
filtering rejects spikes on the bus.
1.3.10
Boot Sequencer
The MPC8548E provides a boot sequencer that uses the I2C interface to access an external serial ROM
and loads the data into the MPC8548E configuration registers. The boot sequencer is enabled by a
configuration pin sampled at the negation of the MPC8548E hardware reset signal. If enabled, the boot
sequencer holds the MPC8548E processor core in reset until the boot sequence is complete. If the boot
sequencer is not enabled, the processor core exits reset and fetches boot code in default configurations.
1.3.11
Dual Universal Asynchronous Receiver/Transmitter (DUART)
The MPC8548E includes a DUART intended for use in maintenance, bringing-up, and debugging of
systems. The MPC8548E provides a standard four-wire handshake (SIN, SOUT, RTS, CTS) for each port.
The DUART is a slave interface. An interrupt is provided to the interrupt controller or optionally steered
externally to allow device handshakes. Interrupts are generated for transmit, receive, line status, and
MODEM status.
The MPC8548E DUART supports full-duplex operation. It is compatible with the PC16450 and PC16550
programming models. Also, 16-byte FIFOs are supported for both the transmitter and the receiver.
Software programmable baud generators divide the system clock to generate a 16x clock. Serial interface
data formats (data length, parity, 1/1.5/2 stop bits, baud rate) are also software selectable.
1.3.12
Local Bus Controller
The MPC8548E local bus controller (LBC) port allows connections with a wide variety of external
memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be
programmed separately to access different types of devices. The general-purpose chip select machine
(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user
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programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC
interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be
configured so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM
controller. All may exist in the same system.
The GPCM provides a flexible asynchronous interface to SRAM, EPROM, FEPROM, ROM, and other
devices such as asynchronous DSP host interfaces and CAMs. Minimal glue logic is required. Handshake
signals can be configured to transition on fractions of the system clock. The GPCM does not support
bursting.
The UPM allows an extremely flexible interface in which the programmer configures each of a set of
general-purpose protocol signals by writing the transition pattern into a memory array. The UPM supports
synchronous and bursting interfaces. It also supports multiplexed addressing so that a simple DRAM
interface can be implemented. The UPM is entirely flexible in order to provide a very high degree of
customization with respect to both asynchronous and burst-synchronous interfaces, which permits glueless
or almost glueless connection to burst SRAM, custom ASIC, and synchronous DSP interfaces.
The LBC provides a synchronous DRAM (SDRAM) machine that provides the control functions and
signals for glueless connection to JEDEC–compliant SDRAM devices. An internal PLL (phase-locked
loop) for bus clock generation ensures improved data setup margins for board designs. The SDRAM
machine can optimize burst transfers and exploits interleaving to maximize data transfer bandwidth and
minimize access latency. Programmable row and column address multiplexing allows a variety of
SDRAM configurations and sizes to be supported without hardware changes.
1.3.13
Enhanced Three-Speed Ethernet Controllers (eTSECs)
The MPC8548E has four on-chip enhanced three-speed Ethernet controllers. The eTSECs incorporate a
media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps Ethernet/802.3
networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs include
2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.
Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with
minimal change.
The MPC8548E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache
to speed classification or other frame processing.
Each eTSEC provides hardware support for accelerating TCP/IP packet transmission and reception. By
default, TCP/IP acceleration is not enabled, and the eTSEC processes frames as pure Ethernet frames.
TCP/IP acceleration can be performed at a number of levels. The eTSEC can parse frames at layer 2 of the
stack only (Ethernet headers and switching headers), layers 2 to 3 (including IP v4 or IP v6), or layers 2
to 4 (including TCP and UDP).
On receive, the eTSEC provides protocol header recognition, header verification (IP v4 header checksum
verification), and TCP/UDP payload checksum verification including verification of associated
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pseudo-header checksums. On transmit, the eTSEC provides IP v4 and TCP/UDP header checksum
generation. The eTSEC does not checksum transmitted packets with IP header options or IP fragments.
To provide for quality of service, transmission from up to eight queues is supported with priority-based
queue selection. Arbitration is a modified weighted round-robin queue selection with fair bandwidth
allocation.
On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical
receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame
rejection is supported for filtering applications.
Filing can be based on Ethernet, IP, and TCP/UDP properties, including VLAN fields, Ether-type, IP
protocol type, IP TOS or differentiated services, IP source and destination addresses, TCP/UDP port
numbers, or user-defined bit fields.
Each eTSEC provides a full-duplex packet FIFO interface port that bypasses the Ethernet MAC, but
re-uses the PHY interface pins. As a result, the FIFO interface normally does not impose the overheads of
Ethernet framing. The FIFO interface operates synchronously, at up to 200 MHz, providing up to 3.2-Gbps
full-duplex transfer rates. Bare IP packets, with an optional 32-bit CRC check sequence, can be transferred
to the eTSEC directly. The eTSEC Tx and Rx FIFOs, TCP/IP acceleration functions, and DMA continue
to be used in packet FIFO mode.
The FIFO interface supports 8- and 16-bit modes subject to pin-multiplexing limitations. It shares the same
pins used for supporting the selectable MII, GMII, RMII (on eTSEC 1–3), RGMII, RTBI, and TBI
interface protocols. As a result, use of some FIFO modes can limit the number of eTSECs that can be
operating.
NOTE
While some of the Ethernet interfaces support either 2.5- or 3.3-V operation,
the voltages of eTSEC1 and eTSEC2 must be the same. Likewise, the
voltages of eTSEC3 and eTSEC4 must match.
Table 1-2 lists available configurations for eTSECs 1 and 2.
Table 1-2. Supported eTSEC1 and eTSEC2 Configurations1
Mode Option
eTSEC1
eTSEC2
Ethernet standard interfaces
TBI, GMII, or MII
TBI, GMII, or MII
Ethernet reduced interfaces
RTBI, RGMII, or RMII
RTBI, RGMII, or RMII
FIFO and mixed interfaces
8-bit FIFO
RTBI, RGMII, RMII, or
8-bit FIFO
TBI, GMII, MII, RTBI, RGMII,
RMII, or 8-bit FIFO
8-bit FIFO
16-bit FIFO
Not used/not available
1
Both interfaces must use the same voltage.
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Table 1-3 lists the available configurations for eTSECs 3 and 4.
Table 1-3. Supported eTSEC3 and eTSEC4 Configurations1
Mode Option
eTSEC3
eTSEC4
Ethernet standard interfaces
TBI, GMII, or MII
Not used/not available
Ethernet reduced interfaces
RTBI, RGMII, or RMII
RTBI, RGMII, or RMII
8-bit FIFO
Not used/not available
FIFO interface
1
1.3.14
Both interfaces must use the same voltage.
OceaN Switch Fabric
In order to reduce the strain on core interconnects with the addition of new functional blocks in this
generation of the PowerQUICC family, a multi-port, on-chip, non-blocking crossbar switch fabric called
OCeaN (on-chip network) has been provided. The switch fabric serves to decrease contention and increase
bandwidth. This non-blocking crossbar fabric allows full-duplex port communication with independent
per-port transaction queuing and flow control.
1.3.15
Integrated DMA
The MPC8548E DMA engine is capable of transferring blocks of data from any legal address range to any
other legal address range. Therefore, it can perform a DMA transfer between any of its I/O or memory
ports or even between two devices or locations on the same port.
The four-channel DMA controller allows chaining (both extended and direct) through local
memory-mapped chain descriptors. Scattering, gathering, and misaligned transfers are supported. In
addition, advanced capabilities such as stride transfers and complex transaction chaining are supported.
DMA transfers can be initiated by a single write to a configuration register. There is also support for
external control of transfers using DMA_DREQ, DMA_DACK, and DMA_DDONE handshake signals.
DMA descriptors encompass a rich set of attributes that allow DMA transfers to bypass outbound address
translation and supply external addresses and attributes directly to the RapidIO port. Local attributes such
as snoop and L2 write stashing can be specified by descriptors.
Interrupts are provided on a completed segment, link, list, chain, or on an error condition. Coherency is
selectable and hardware enforced (snoop/no snoop).
1.3.16
PCI/PCI-X Controllers
The MPC8548E has a 64-bit PCI/PCI-X controller and a second 32-bit PCI controller. Both are compatible
with the PCI Local Bus Specification, Revision 2.2. The PCI-X interface is compatible with the PCI-X
Addendum, Revision 1.0. Each controller can function as host or agent bridge interface in either PCI mode.
Due to pin multiplexing limitations, the PCI/PCI-X controller can operate in 64-bit mode or both interfaces
can operate simultaneously in 32-bit mode. Both interfaces support 32- and 64-bit addressing.
As a master, the MPC8548E supports read and write operations to PCI memory space, PCI I/O space, and
PCI configuration space. The MPC8548E can also generate PCI special-cycle and interrupt-acknowledge
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commands. As a target, the MPC8548E supports read and write operations to system memory as well as
configuration accesses.
The PCI-X functionality includes split transaction support for four outstanding split transactions. Split
response data is returned in order without interleaving. As a target, the MPC8548E supports all PCI-X
sizes. As a master it will internally combine transactions up to 256 bytes.
An internal arbiter can be used to support up to five external masters per interface. A round robin
arbitration algorithm with two priority levels is used.
Each interface can be clocked asynchronously from the other. The second PCI interface is available when
serial RapidIO is not used.
1.3.17
High Speed I/O Interfaces
The MPC8548E supports two high-speed I/O interface standards: serial RapidIO and PCI Express. Due to
pin multiplexing, one of the following configurations must be selected at power-on reset:
•
•
Single x8 PCI Express
Single x4/x2/x1 PCI Express and single 4x/1x serial RapidIO
1.3.18
Serial RapidIO Interface
The serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.2. RapidIO is
a high-performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can be
used in a variety of applications as an open standard. The RapidIO architecture provides a rich variety of
features including high data bandwidth, low-latency capability, and support for high-performance I/O
devices, as well as providing message-passing and software-managed programming models.
The RapidIO unit supports the I/O and message-passing logical specifications, both 8- and 16-bit common
transport specifications, and the 1x/4x LP-Serial physical layer specification of the RapidIO Interconnect
Specification, Revision 1.2. It does not support the globally shared memory logical specification.
Highlights of the implementation include: four priority levels and ordering within a priority level, CRC
error management, and 32- to 256-byte transactions.
The physical layer of the RapidIO unit can operate at 1.25-, 2.5-, and 3.125-Gbaud data rates over four
lanes. The theoretical unidirectional peak bandwidth is 10 Gbps. Receive and transmit ports operate
independently, resulting in an aggregate theoretical bandwidth of 20 Gbps.
The serial RapidIO interface is available when the second PCI interface is not used.
1.3.19 RapidIO Message Unit
The RapidIO messaging unit supports two inbox/outbox mailboxes (queues) for data and one doorbell
message structure. Both chaining and direct modes are provided for the outbox, and messages can hold up
to 16 packets of 256 bytes, or a total of 4 Kbytes.
The message unit supports up to three outstanding letters from one or more of the four mailboxes. The
message unit will pipeline letters to improve messaging performance.
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The message unit also supports the ability to multicast a single-segment 256-byte message to up to 32
different destination DevIDs.
1.3.20
PCI Express Interface
The MPC8548E supports a PCI Express interface compliant with the PCI Express Base Specification
Revision 1.0a. It is configurable at boot time to act as either root complex or endpoint.
The interface is selectable at boot time to support either 32 or 64-bit addressing. The maximum supported
packet payload size is 256 bytes.
The physical layer supports x8, x4, x2, and x1 lane widths with each lane running at the specified data rate
of 2.5 Gbaud.
The interface supports virtual channel 0 (VC0) and traffic class 0 (TC0) only.
Inbound INTx transactions are supported and change the state of one of four level-sensitive interrupts
presented to the PIC. Outbound INTx transactions are not supported.
Message signaled interrupt (MSI) transactions are supported and control up to 256 interrupt sources within
the PIC. Inbound transactions cause specific interrupt sources to be controlled within the PIC. Outbound
MSI transactions are created by software using the MSI Capability Register Sets.
The physical layer of the PCI Express interface operates at a 2.5-Gbaud data rate per lane. The theoretical
unidirectional peak bandwidth is 16 Gbps. Receive and transmit ports operate independently, resulting in
an aggregate theoretical bandwidth of 32 Gbps.
1.3.21
Power Management
In addition to low-voltage operation and dynamic power management in its execution units, the
MPC8548E supports four power consumption modes: full on, doze, nap, and sleep. The three low-power
modes, doze, nap, and sleep, can be entered under software control in the e500 core or by external masters
accessing a configuration register.
Doze mode suspends execution of instructions in the e500 core. The core is left in a standby mode in which
cache snooping and time base interrupts are still enabled. Device logic external to the processor core is
fully functional in this mode.
Nap mode shuts down clocks to all the e500 functional units except the time base, which can be disabled
separately. No snooping is performed in nap mode, but the device logic external to the processor core is
fully functional.
Sleep mode shuts down not only the e500 core, but also all of the MPC8548E I/O interfaces as well. Only
the interrupt controller and power management logic remain enabled so that the device can be awakened.
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Overview
1.3.22
Clocking
The MPC8548E takes in the SYSCLK signal as an input to the platform PLL and multiplies it to generate
the platform clock, which operates at the same frequency as the SDRAM data rate (for example,
666 MHz). The L2 cache also operates at this frequency. The e500 core uses the platform clock as an input
to its PLL, which multiplies it again to generate the core clock.
Although the DDR2 controller clocking is source synchronous, a PLL is used in the local bus memory
controller (LBC) to generate memory clocks. Six differential clock pairs are generated for DDR SDRAMs.
Two clock outputs are generated for the local bus controller (LBC).
1.3.23
Address Map
The MPC8548E supports a flexible 36-bit physical address map. Conceptually, the address map consists
of local space and external address space. The local address map is 64 Gbytes. The MPC8548E can be
made part of a larger system address space through the mapping of translation windows. This functionality
is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation
windows are provided. The ATMUs allows the MPC8548E to be part of larger address maps such as the
PCI or PCI Express 64-bit address environment and the RapidIO environment.
1.3.24
Processing Across the On-Chip Fabric
When processing across the on-chip fabric, the ATMUs at each fabric port are used to determine the flow
of data across the MPC8548E. The ATMUs at each fabric port are responsible for generating a fabric port
destination ID as well as a new local device address. The port ID and local address are based on the
programmed destination of the transaction. The following is a general overview of how the ATMUs
process transactions over the on-chip fabric (refer to Figure 1-3).
1. When a transaction on one of the fabric ports begins, the ATMU on the origination port translates
the programmed destination address into both a destination fabric port ID and a local device
address.
2. The data is then processed across the on-chip fabric from the origination port to the destination
port.
3. If the destination port connects off chip (for example, to a PCI or RapidIO device), the local device
address is translated by the destination port ATMU to an outbound address with respect to the
destination port’s memory map, and the data is processed accordingly.
2
1
3
ATMU
ATMU
Figure 1-3. Processing Transactions Across the On-Chip Fabric
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Overview
1.3.25
Data Processing with the e500 Coherency Module
Processing via the ECM is similar to processing across the on-chip fabric (in the sense of how data is
received and transmitted) with the exception that the transaction passes through the ECM. The purpose of
the ECM is to provide a means for any I/O transaction to maintain coherency with the cacheable DDR
SDRAM and the local bus memory. However, simply because the ECM is used does not make transactions
across it coherent. The e500 core and L2 cache are snooped to maintain coherency only if the transaction
across the ECM is designated as global (GBL bit set). Otherwise, the transaction passes through the ECM
using the ECM as a simple conduit to get to its destination. In essence, only global transactions across the
ECM are coherent transactions; all others (across the on-chip fabric) are non-coherent.
1.4
MPC8548E Application Examples
The following section provides block diagrams of different MPC8548E applications. The MPC8548E is a
very flexible device and can be configured to meet many system application needs. In order to build a
system, many factors should be considered.
1.4.1
MPC8548E Applications
The MPC8548E can be used for control processing in applications such as routers, switches, internet
access devices, firewall and other packet filtering processors, network attached storage, storage area
networks, imaging, and general-purpose embedded computing.
Figure 1-4 illustrates the MPC8548E in a virtual private network (VPN) access router that is enabled
through PCI Express and Ethernet.
MPC8548E
PCI Express
HighBandwidth
Aggregators
Data In
Data Out
Processor
Core
Complex
512-K L2
Memory
Block
RapidIO
4x eTSEC
Memory
Control
PCI
Data In
Data Out
10/100/1G
Ethernet
Security
DDR
Memory
Figure 1-4. VPN Access Router Enabled by PCI Express and Ethernet
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Overview
Figure 1-5 shows an MPC8548E as a control plane processor in a high-performance communication
system using distributed computing.
ASIC
Accelerator
Hardware
RapidIO Switch
MPC8548E
ASIC
Task Processor
MPC8548E
Processor 512-K L2
Core
Memory
Complex Block
Processor 512-K L2
Memory
Core
Complex
Block
RapidIO Interface
RapidIO 4x eTSEC
PCI/PCI Memory
Express
Control
66-MHz PCI
To Network
Forwarding
Plane
DDR
Memory
Four Gigabit
Ethernet Controllers
To
Control
Plane
PCI Express
Figure 1-5. High-Performance Communication System Using Distributed Processing
Figure 1-6 shows the MPC8548E as part of a high-end network card used in a system area network that is
enabled by PCI Express.
Server
Data
Control
Four 10/100/1Gb Ethernet Controllers
MPC8548E
DDR
Memory
Processor
Core
Complex
512-K L2
Memory
Block
RapidIO
4x eTSEC
PCI/PCI
Express
FPGA
ROM
GPCM/UPM/
SDRAM
Memory
Control
RTC/NVRAM
PCI Express Backplane
RAID Controller
Figure 1-6. High-Performance Communication System Using MPC8548E
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Overview
Figure 1-7 shows the MPC8548E in a redundant array of independent disks (RAID) controller application.
MPC8548E
Processor 512K L2
Core
Memory
Complex
Block
Disk Cache
DDR
Memory
Descriptor
Memory
Flash
4x eTSEC
Memory
PCI Express Control
XOR
PCI-X to System
SCSI
Control
PCI Express
Switch
Figure 1-7. RAID Controller Application Using MPC8548E
Figure 1-8 shows the MPC8548E in a serializer/deserializer (SerDes) data transfer mode application
enabled by Ethernet.
MPC8548E
Processor
Core
Complex
RapidIO
PCI
512-K L2
Memory
Block
4x eTSEC
Memory
Control
SerDes Interface
10/100/1Gb Ethernet
Data In Using 10-Bit Interface
Data Out Using 10-Bit Interface
SerDes
DDR
Memory
Figure 1-8. MPC8548E with SerDes
Figure 1-9 shows a DSP farm enabled by the MPC8548E.
Core Complex Unit
DSP
EPROM
DSP
RapidIO Switch
DSP
Local Bus
512-K
L2
Controller Port Memory Block
RapidIO
PCI
DSP
4x eTSEC
Memory
Control
Data In
Data Out
10/100/1Gb
Ethernet
DDR
Memory
DSP Farm
Backplane
Figure 1-9. MPC8548E as a Control Plane Processor for a DSP Farm Interconnected with RapidIO
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Chapter 2
Memory Map
This chapter describes the MPC8548E memory map. An overview of the local address map is followed by
a description of how local access windows are used to define the local address map. The inbound and
outbound address translation mechanisms used to map to and from external memory spaces are described
next. Finally, the configuration, control, and status registers are described, including a complete listing of
all memory-mapped registers with cross references to the sections detailing descriptions of each.
2.1
Local Memory Map Overview and Example
The MPC8548E provides an extremely flexible local memory map. The local memory map refers to the
36-bit address space seen by the processor as it accesses memory and I/O space. DMA engines also see
this same local memory map. All memory accessed by the device DDR SDRAM and local bus memory
controllers exists in this memory map, as do all memory-mapped configuration, control, and status
registers.
The local memory map is defined by a set of ten local access windows. Each of these windows maps a
region of memory to a particular target interface, such as the DDR SDRAM controller or the PCI/PCI-X
controller. Note that the local access windows do not perform any address translation. The size of each
window can be configured from 4 Kbytes to 32 Gbytes. The target interface is specified using the codes
shown in Table 2-1.
.
Table 2-1. Target Interface Codes
Target Interface
Target Code
PCI1/PCI-X
0000
PCI2
0001
PCI Express
0010
Local bus
0100
Serial RapidIO
1100
DDR SDRAM
1111
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Memory Map
Figure 2-1 shows an example memory map.
Example Local
Memory Map
0
0x0_A000_0000
DDR SDRAM
Memory
PCI
0x0_8000_0000
0x0_B000_0000
Local Bus SRAM
Serial
RapidIO
0x0_A000_000
I/O
Configuration Registers
0x0_C000_0000
CCSR
Local Bus Flash
Local Bus
DSP
Boot ROM
0x0_FFFF_FFFF
0x8_0000_0000
PCI-Express
0xF_FFFF_FFFF
Figure 2-1. Local Memory Map Example
Table 2-2 shows one corresponding set of local access window settings.
Table 2-2. Local Access Windows Example
Window
Base Address
Size
Target Interface
0
0x0_0000_0000
2 Gbytes
0b1111 (DDR SDRAM)
1
0x0_8000_0000
1 Mbyte
0b0100 (local bus)
2
0x0_A000_0000
256 Mbytes
0b0000 (PCI)
3
0x0_B000_0000
256 Mbytes
0b1100 (serial RapidIO)
4
0x0_C000_0000
256 Mbytes
0b0100 (local bus)
5
0x8_0000_0000
32 Gbytes
0b0100 (PCI Express)
6–9
Unused
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Memory Map
In this example, it is not necessary to use a local access window to specify the range of memory used for
memory-mapped registers because this is a fixed 1-Mbyte space pointed to by CCSRBAR. See
Section 4.3.1.1.2, “Configuration, Control, and Status Base Address Register (CCSRBAR).” Neither is it
required to define a local access window to describe the location of the boot ROM because it is in the
default location (see Section 4.4.3.3, “Boot ROM Location”). However, note that the e500 core only
provides one default TLB entry to access boot code and it allows for accesses within the highest 4 Kbytes
of the low 4 Gbytes of memory. In order for the e500 to access the full 8 Mbytes of default boot space (and
the 1 Mbyte of CCSR space), additional TLB entries must be set up within the e500 MMU for mapping
these regions.
2.2
Address Translation and Mapping
Four distinct types of translation and mapping operations are performed on transactions in the device.
These are as follows:
• Mapping a local address to a target interface
• Assigning attributes to transactions
• Translating the local 36-bit address to an external address space
• Translating external addresses to the local 36-bit address space
The local access windows perform target mapping for transactions within the local address space. No
address translation is performed by the local a
ccess windows.
Outbound ATMU windows perform the mapping from the local 36-bit address space to the address spaces
of RapidIO or PCI/PCI-X, which may be much larger than the local space. Outbound ATMU windows also
map attributes such as transaction type or priority level.
Inbound ATMU windows perform the address translation from the external address space to the local
address space, attach attributes and transaction types to the transaction, and also map the transaction to its
target interface. Note that in mapping the transaction to the target interface, an inbound ATMU window
performs a similar function as the local access windows. The target mappings created by an inbound
ATMU must be consistent with those of the local access windows. That is, if an inbound ATMU maps a
transaction to a given local address and a given target, a local access window must also map that same local
address to the same target.
All of the configuration registers that define translation and mapping functions use the concept of
translation or mapping windows, and all follow the same register format. Table 2-3 summarizes the general
format of these window definitions.
Table 2-3. Format of ATMU Window Definitions
Register
Function
Translation address
High-order address bits defining location of the window in the target address space
Base address
High-order address bits defining location of the window in the initial address space
Window size/attributes
Window enable, window size, target interface, and transaction attributes
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Memory Map
Windows must be a power-of-two size. To perform a translation or mapping function, the address of the
transaction is compared with the base address register of each window. The number of bits used in the
comparison is dictated by each window’s size attribute. When an address hits a window, if address
translation is being performed, the new translated address is created by concatenating the window offset
to the translation address. Again, the window’s size attribute dictates how many bits are translated.
2.2.1
SRAM Windows
The on-chip memory array of the MPC8548E can be configured as a memory-mapped SRAM ranging
from 64 Kbytes to 512 Kbytes. Configuration registers in the L2 cache controller set the base addresses
and sizes for these windows. When enabled, these windows supersede all other mappings of these
addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must never
overlap configuration space as defined by CCSRBAR. It is possible to have SRAM windows overlap local
access windows, but this is discouraged because processor and snoopable I/O transactions would map to
the SRAM while non-snooped I/O transactions would be mapped by the local access windows. Only if all
accesses to the SRAM address range are snoopable can results be consistent if the SRAM window overlaps
a local access window.
See Section 7.3.1.3.1, “L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn),” for
information about configuring SRAM windows.
2.2.2
Window into Configuration Space
CCSRBAR defines a window used to access all memory-mapped configuration, control, and status
registers. No address translation is done, so there are no associated translation address registers. The
window is always enabled with a fixed size of 1 Mbyte; no other attributes are attached, so there is no
associated size/attribute register. This window always takes precedence over all local access windows. See
Section 4.3.1.1.2, “Configuration, Control, and Status Base Address Register (CCSRBAR),” and
Section 2.3, “Configuration, Control, and Status Register Map.”
2.2.3
Local Access Windows
As demonstrated in the address map overview in Section 2.1, “Local Memory Map Overview and
Example,” local access windows associate a range of the local 36-bit address space with a particular target
interface. This allows the internal interconnections of the device to route a transaction from its source to
the proper target. No address translation is performed. The base address defines the high order address bits
that give the location of the window in the local address space. The window attributes enable the window,
define its size, and specify the target interface.
With the exception of configuration space (mapped by CCSRBAR), on-chip SRAM regions (mapped by
L2SRBAR registers), and default boot ROM, all addresses used by the system must be mapped by a local
access window. This includes addresses that are mapped by inbound ATMU windows; target mappings of
inbound ATMU windows and local access windows must be consistent.
The local access window registers exist as part of the local access block in the general utilities registers.
See Section 2.3.4, “General Utilities Registers.” A detailed description of the local access window
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Memory Map
registers is given in the following sections. Note that the minimum size of a window is 4 Kbytes, so the
low order 12 bits of the base address cannot be specified.
2.2.3.1
Local Access Register Memory Map
Table 2-4 shows the memory map for the local access registers. In this table and in the register figures and
field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
• Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Table 2-4. Local Access Register Memory Map
Local Memory
Offset (Hex)
Register
Access
Reset
Section/Page
0x0_0BF8
LAIPBRR1—Local access IP block revision register 1
R
0x0000_0000
2.2.3.2/2-6
0x0_0BFC
LAIPBRR2—Local access IP block revision register 2
R
0x0000_0000
2.2.3.3/2-6
0x0_0C08
LAWBAR0—Local access window 0 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C10
LAWAR0—Local access window 0 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C28
LAWBAR1—Local access window 1 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C30
LAWAR1—Local access window 1 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C48
LAWBAR2—Local access window 2 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C50
LAWAR2—Local access window 2 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C68
LAWBAR3—Local access window 3 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C70
LAWAR3—Local access window 3 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C88
LAWBAR4—Local access window 4 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C90
LAWAR4—Local access window 4 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0CA8
LAWBAR5—Local access window 5 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0CB0
LAWAR5—Local access window 5 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0CC8
LAWBAR6—Local access window 6 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0CD0
LAWAR6—Local access window 6 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0CE8
LAWBAR7—Local access window 7 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0CF0
LAWAR7—Local access window 7 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0D08
LAWBAR8—Local access window 8 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0D10
LAWAR8—Local access window 8 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0D28
LAWBAR9—Local access window 9 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0D30
LAWAR9—Local access window 9 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
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Memory Map
2.2.3.2
Local Access IP Block Revision Register 1 (LAIPBRR1)
The local access IP block revision register 1 is shown in Figure 2-2.
Offset 0x0_0BF8
Access: Read only
0
15 16
R
IP_ID
23 24
31
IP_MJ
IP_MN
W
Reset
All zeros
Figure 2-2. Local Access IP Block Revision Register 1 (LAIPBRR1)
Table 2-5 describes LAIPBRR1 fields.
Table 2-5. LAIPBRR1 Field Descriptions
Bits
Name
0–15
IP_ID
IP block ID
16–23
IP_MJ
Major revision
24–31
IP_MN
Minor revision
2.2.3.3
Description
Local Access IP Block Revision Register 2 (LAIPBRR2)
The local access IP block revision register 2 is shown in Figure 2-3.
Offset 0x0_0BFC
Access: Read only
0
7
8
15 16
R
23 24
31
IP_INT
IP_CFG
W
Reset
All zeros
Figure 2-3. Local Access IP Block Revision Register 2 (LAIPBRR2)
Table 2-6 describes LAIPBRR2 fields.
Table 2-6. LAIPBRR2 Field Descriptions
Bits
Name
0–7
—
8–15
IP_INT
16–23
—
24–31
IP_CFG
Description
Reserved
IP block integration options
Reserved
IP block configuration options
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Memory Map
Local Access Window n Base Address Registers
(LAWBAR0–LAWBAR9)
2.2.3.4
Figure 2-4 shows the bit fields of the LAWBARn registers.
Offset LAWBAR0: 0x0_0C08
LAWBAR1: 0x0_0C28
LAWBAR2: 0x0_0C48
LAWBAR3: 0x0_0C68
LAWBAR4: 0x0_0C88
0
7
R
Access: Read/Write
LAWBAR5: 0x0_0CA8
LAWBAR6: 0x0_0CC8
LAWBAR7: 0x0_0CE8
LAWBAR8: 0x0_0D08
LAWBAR9: 0x0_0D28
8
31
—
W
BASE_ADDR
Reset
All zeros
Figure 2-4. Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7)
Table 2-7 describes LAWBARn fields.
Table 2-7. LAWBAR n Field Descriptions
Bits
Name
0–7
—
8–31
Description
Write reserved, read = 0
BASE_ADDR Identifies the 24 most-significant address bits of the base of local access window n. The
specified base address should be aligned to the window size, as defined by LAWARn[SIZE].
Local Access Window n Attributes Registers (LAWAR0–LAWAR9)
2.2.3.5
Figure 2-5 shows the bit fields of the LAWARn registers.
Offset LAWSR0: 0xC10
LAWSR1: 0xC30
LAWSR2: 0xC50
LAWSR3: 0xC70
LAWSR4: 0xC90
0
R
W
1
7
EN
—
Access: Read/Write
LAWSR5: 0xCB0
LAWSR6: 0xCD0
LAWSR7: 0xCF0
LAWSR8: 0xD10
LAWSR9: 0xD30
8
11 12
25 26
TRGT_ID
Reset
—
31
SIZE
All zeros
Figure 2-5. Local Access Window n Attributes Registers (LAWAR0–LAWAR7)
Table 2-8 describes LAWARn fields.
Table 2-8. LAWARn Field Descriptions
Bits
Name
Description
0
EN
0 The local access window n (and all other LAWAR n and LAWBARn fields) are disabled.
1 The local access window n is enabled and other LAWAR n and LAWBARn fields combine to
identify an address range for this window.
1–7
—
Write reserved, read = 0
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Memory Map
Table 2-8. LAWARn Field Descriptions (continued)
Bits
8–11
Name
TRGT_IF Identifies the target interface ID when a transaction hits in the address range defined by this
window. Note that configuration registers and SRAM regions are mapped by the windows defined
by CCSRBAR and L2SRBAR. These mappings supersede local access window mappings, so
configuration registers and SRAM do not appear as a target for local access windows.
0000 PCI1/PCI-X
0001 PCI2
0010 PCI Express
0011 Reserved
0100 Local bus memory controller
0101–1011Reserved
1100 RapidIO
1101–1110Reserved
1111 DDR SDRAM
12–25
—
26–31
SIZE
2.2.3.6
Description
Write reserved, read = 0
Identifies the size of the window from the starting address. Window size is 2(SIZE+1) bytes.
000000–001010Reserved
001011 4 Kbytes
001100 8 Kbytes
00110116 Kbytes
. . . . . . . 2(SIZE+1) bytes
100010 32 Gbytes
100011–111111Reserved
Precedence of Local Access Windows
If two local access windows overlap, the lower numbered window takes precedence. For instance, if two
windows are set up as shown in Table 2-9, local access window 1 governs the mapping of the 1-Mbyte
region from 0x0_7FF0_0000 to 0x0_7FFF_FFF, even though the window described in local access
window 2 also encompasses that memory region.
Table 2-9. Overlapping Local Access Windows
2.2.3.7
Window
Base Address
Size
Target Interface
1
0x0_7FF0_0000
1 Mbyte
0b0100 (Local bus controller —LBC)
2
0x0_0000_0000
2 Gbytes
0b1111 (DDR SDRAM)
Configuring Local Access Windows
Once a local access window is enabled, it should not be modified while any device in the system may be
using the window. Neither should a new window be used until the effect of the write to the window is
visible to all blocks that use the window. This can be guaranteed by completing a read of the last local
access window configuration register before enabling any other devices to use the window. For instance,
if local access windows 0–3 are being configured in order during the initialization process, the last write
(to LAWAR3) should be followed by a read of LAWAR3 before any devices try to use any of these
windows. If the configuration is being done by the local e500 processor, the read of LAWAR3 should be
followed by an isync instruction.
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2.2.3.8
Distinguishing Local Access Windows from Other Mapping Functions
It is important to distinguish between the mapping function performed by the local access windows and
the additional mapping functions that happen at the target interface. The local access windows define how
a transaction is routed through the device internal interconnects from the transactions source to its target.
After the transaction has arrived at its target interface, that interface controller may perform additional
mapping. For instance, the DDR SDRAM controller has chip select registers that map a memory request
to a particular external device. Similarly, the local bus controller has base registers that perform a similar
function. The RapidIO and PCI/PCI-X interfaces have outbound address translation and mapping units
that map the local address into an external address space.
These other mapping functions are configured by programming the configuration, control, and status
registers of the individual interfaces. Note that there is no need to have a one-to-one correspondence
between local access windows and chip select regions or outbound ATMU windows. A single local access
window can be further decoded to any number of chip selects or to any number or outbound ATMU
windows at the target interface.
2.2.3.9
Illegal Interaction Between Local Access Windows and DDR
SDRAM Chip Selects
If a local access window maps an address to an interface other than the DDR SDRAM controller, then there
should not be a valid chip select configured for the same address in the DDR SDRAM controller. Because
DDR SDRAM chip selects boundaries are defined by a beginning and ending address, it is easy to define
them so that they do not overlap with local access windows that map to other interfaces.
2.2.4
Outbound Address Translation and Mapping Windows
Outbound address translation and mapping refers to the translation of addresses from the local 36-bit
address space to the external address space and attributes of a particular I/O interface. On the MPC8548E,
the following blocks have outbound address translation and mapping units (ATMUs):
• PCI/PCI-X
• Serial RapidIO
• PCI Express
The PCI1/PCI-X and PCI2 controllers each have four outbound ATMU windows plus a default window.
The PCI/PCI-X outbound ATMU registers include extended translation address registers so that up to 64
bits of external address space can be supported. See Section 16.3.1.2, “PCI/X ATMU Outbound
Registers,” for a detailed description of the PCI/PCI-X outbound ATMU windows.
The serial RapidIO controller has eight outbound ATMU windows plus a default window. If a transaction’s
address does not hit any of the eight outbound ATMU windows, the translation actions defined by the
default window are used. The default window is always enabled. See Section 17.6.7, “RapidIO
Implementation Space—ATMU Registers,” for a detailed description of the serial RapidIO outbound
ATMU windows.
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The PCI Express interface has four outbound ATMU windows plus a default window. The PCI Express
outbound ATMU registers include an extended translation address register so that up to 64 bits of external
address space can be supported.
2.2.5
Inbound Address Translation and Mapping Windows
Inbound address translation and mapping refers to the translation of an address from the external address
space of an I/O interface (such as PCI/PCI-X or RapidIO address space) to the local 36-bit address space
understood by the internal interfaces of the device. It also refers to the mapping of transactions to a
particular target interface and the assignment of transaction attributes. Both the RapidIO controller and the
PCI/PCI-X controller have inbound address translation and mapping units (ATMUs).
2.2.5.1
Serial RapidIO Inbound ATMU
The serial RapidIO controller has four inbound ATMU windows plus a default. If the inbound transaction’s
address does not hit any of the four inbound ATMU windows, the translation actions defined by the default
window are used. The default window is always enabled. See Section 17.6.7, “RapidIO Implementation
Space—ATMU Registers,” for a detailed description of the serial RapidIO inbound ATMU windows.
2.2.5.2
PCI/PCI-X Inbound ATMU
The PCI1/PCI-X and PCI2 controllers each have three general inbound ATMU windows plus a dedicated
window for memory mapped configuration accesses (PCSRBAR). These windows have a one-to-one
correspondence with the base address registers in the PCI/PCI-X programming model. Updating one
automatically updates the other. There is no default inbound window; if a PCI/PCI-X address does not
match one of the inbound ATMU windows, the device does not respond with an assertion of
PCI_DEVSEL. See Section 16.3.1.3, “PCI/X ATMU Inbound Registers,” for a detailed description of the
PCI/PCI-X inbound ATMU windows.
2.2.5.3
PCI Express Inbound ATMU
The PCI Express controller has three inbound ATMU windows plus a default.
2.2.5.4
Illegal Interaction Between Inbound ATMUs and Local Access
Windows
Since both local access windows and inbound ATMUs map transactions to a target interface, it is essential
that they not contradict one another. For instance, it is a programming error to have an inbound ATMU map
a transaction to the DDR SDRAM memory controller (target interface 0b1111) if the resulting translated local
address is mapped to PCI/PCI-X (target interface 0b0000) by a local access window. Such a programming
error may result in unpredictable system deadlocks.
2.3
Configuration, Control, and Status Register Map
All of the memory mapped configuration, control, and status registers in the MPC8548E are contained
within a 1-Mbyte address region. To allow for flexibility, the configuration, control, and status block is
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relocatable in the local address space. The local address map location of this register block is controlled
by the configuration, control, and status registers base address register (CCSRBAR), see Section 4.3.1.1.2,
“Configuration, Control, and Status Base Address Register (CCSRBAR).” The default value for
CCSRBAR is 4 Gbytes–9 Mbytes, or 0x0_FF70_0000.
NOTE
The configuration, control, and status window must not overlap a local
access window that maps to the DDR controller. Otherwise, undefined
behavior occurs.
An example of a top-level memory map with the default location of the configuration, control, and status
registers is shown in Figure 2-6.
CCSR Register
Memory Block
Example Local
Memory Map
0
0x0_0000
General
Utilities
Memory
0x4_0000
PIC
0x8_0000
I/O
Reserved
0xC_0000
CCSRBAR (4G-9M)
RapidIO
CCSR
4G-8M
4G
Only reserved if
Local Boot ROM
0xE_0000
Device-Specific
Utilities
0xF_FFFF
Shaded area indicates locations not
allowed for CCSRBAR.
Figure 2-6. Top-Level Register Map Example
2.3.1
Accessing CCSR Memory from the Local Processor
When the local e500 processor is used to configure CCSR space, the CCSR memory space should typically
be marked as cache-inhibited and guarded.
In addition, many configuration registers affect accesses to other memory regions; therefore writes to these
registers must be guaranteed to have taken effect before accesses are made to the associated memory
regions.
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To guarantee that the results of any sequence of writes to configuration registers are in effect, the final
configuration register write should be chased by a read of the same register, and that should be followed
by a SYNC instruction. Then accesses can safely be made to memory regions affected by the configuration
register write.
2.3.2
Accessing CCSR Memory from External Masters
In addition to being accessible by the e500 processor, the configuration, control, and status registers are
accessible from external interfaces. This allows external masters on the I/O ports to configure the device.
External masters do not need to know the location of the CCSR memory in the local address map. Rather, they
access this region of the local memory map through a window defined by a register in the interface
programming model that is accessible to the external master from its external memory map.
The PCI/PCI-X base address for accessing the local CCSR memory is selectable through the PCI/PCI-X
configuration and status register base address register (PCSRBAR), at offset 0x10, described in
Section 16.3.2.11, “PCI Base Address Registers.” An external PCI/PCI-X master sets this register by
running a PCI configuration cycle to the MPC8548E. Subsequent memory accesses by a PCI master to the
PCI address range indicated by PCSRBAR are translated to the local address indicated by the current
setting of CCSRBAR.
The serial RapidIO base address for accessing the local CCSR memory is selectable through the serial
RapidIO LCSBA1CSR, defined in the RapidIO programming model, see Section 17.6.1.11, “Local
Configuration Space Base Address 1 Command and Status Register (LCSBA1CSR).” An external serial
RapidIO master can set the value of LCSBA1CSR with a maintenance packet. Then subsequent read and
write packets whose RapidIO addresses match the window defined by LCSBA1CSR are translated to the
local address range indicated by CCSRBAR.
2.3.3
Organization of CCSR Memory
The configuration, control, and status registers are grouped according to functional units. Most functional
blocks are allocated a 4-Kbyte address space for registers. Registers that fall into this category are referred
to as general utilities registers. These registers occupy the first 256 Kbytes of CCSR memory.
Registers controlling functions that are not particular to a functional unit but to the device as a whole occupy
the highest 256 Kbytes of CCSR memory and are referred to as device-specific registers.
Some functional units, such as RapidIO and the OpenPIC-based interrupt controller have larger address
spaces as defined by their programming models. The registers for these blocks are given their own large
regions of CCSR memory.
Table 2-10. Local Memory Configuration, Control, and Status Register Summary
Offset from CCSRBAR
Register Grouping
0x0_0000–0x3_FFFF
General utilities
0x4_0000–0x7_FFFF
Programmable interrupt controller (PIC)
0x8_0000–0xB_FFFF
Reserved
0xC_0000–0xD_FFFF
RapidIO
0xE_0000–0xF_FFFF
Device-specific utilities
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2.3.4
General Utilities Registers
Figure 2-7 provides an overview of the general utilities registers.
General Utilities Registers Memory Block
0x0 0000
CCSR Memory Block
0x0 0000
General
Utilities
0x0 1000
Local Access
ECM
0x0 2000
DRAM
0x0 3000
I2C
0x0 4000
0x0 5000
DUART
Local Bus
0x0 6000
0x0 7000
OCeaN
0x0 8000
0x0 9000
PCI1/PCI-X
PCI2
0x0 A000
PCI Express
0x4 0000
General Utility Block
0xn n000
PIC
General
Registers
0x2 0000
0x8 0000
0x2 1000
L2 Cache
DMA
Reserved
0xC 0000
SRIO
0xn nC00
0x2 4000
eTSEC 1
0x2 5000
eTSEC 2
0x2 6000
eTSEC 3
0x2 7000
eTSEC 4
0xn nE00
0xn nF00
ATMU
Error Mgmt
Debug
0xE 0000
Device-Specific
Utilities
0xF FFFF
0x3 0000
SEC
0x3 FFFF
Figure 2-7. General Utilities Registers Mapping to Configuration, Control,
and Status Memory Block
Figure 2-7 also shows the organization of registers inside the 4-Kbyte register space allocated to an
individual functional block. The first 3 Kbytes are available for general registers. The next 512 bytes are
dedicated to address translation and mapping registers, if applicable to that particular functional unit (for
example, PCI1/PCI-X). If a unit has error management registers, they are typically placed starting at offset
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0xE00 from the beginning of the block’s 4-Kbyte space, and any debug registers are typically placed in
the final 256 bytes of the unit’s register space starting at offset 0xF00.
General utilities registers are accessed as 32-bit quantities except for the DUART and I2C registers, which
are accessed as bytes.
NOTE
Refer to detailed register descriptions for each functional unit for exact
locations, sizes, and access requirements. Some blocks may have exceptions
to the above guidelines.
2.3.5
Interrupt Controller and CCSR
The programmable interrupt controller (PIC) registers are at offset 0x4_0000 from CCSRBAR, see
Figure 2-8. Its programming model follows the OpenPIC architecture. The interrupt controller registers
should only be accessed with 32-bit accesses.
CCSR Register Memory Block
0x0 0000
General
Utilities
PIC Registers
0x4 0000
0x4 1000
0x4 1100
0x4 1200
0x4 0000
0x5 0000
0x5 1020
Global Cfg
Timers
External IRQs
Internal IRQs
PIC
0x6 0000
Processor
0x8 0000
0x7 FFFF
Reserved
0xC 0000
RIO
0xE 0000
Device-Specific
Utilities
0xF FFFF
Figure 2-8. PIC Mapping to Configuration, Control, and Status Memory Block
2.3.6
Serial RapidIO and CCSR
The serial RapidIO module uses 128 Kbytes of CCSR memory; refer to Figure 2-9. All registers are 32-bits
wide and should only be accessed with 32-bit accesses. The 4-Kbyte RapidIO implementation block has
the same internal organization as those defined for the general utilities described above.
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CCSR Register
Memory Block
RapidIO Configuration
0xC 0000
0x0 0000
General
Utilities
RapidIO Arch.
0xC 4100
RapidIO
Extended
Features
0x4 0000
PIC
0x8 0000
0xD 0000
0xD 1000
Reserved
RapidIO Impl.
RapidIO Messaging
0xC 0000
RIO
0xE 0000
Device-Specific
Utilities
0xF FFFF
Figure 2-9. RapidIO Mapping to Configuration, Control, and Status Memory Block
2.3.7
Device-Specific Utilities
The device-specific registers consist of power management, performance monitors, and device-wide
debug utilities (refer to Figure 2-10). These registers are accessible with 32-bit accesses only. Transactions
of other than 32-bit are considered a programming error and operation is undefined.
Reserved bits in the following register descriptions are not guaranteed to have predictable values. Software
must preserve the values of reserved bits when writing to a register. Also, when reading from a register,
software should not rely on the value of any reserved bit remaining consistent.
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Memory Map
Device-Specific
Registers
0xE 0000
0x0 0000
General
Utilities
0xE 1000
0xE 2000
Global Utilities
Perf. Monitor
Watchpoint/Debug
0x4 0000
PIC
0x8 0000
Reserved
0xC 0000
RIO
0xE 0000
0xF FFFF
Device-Specific
Utilities
0xF FFFC
Figure 2-10. Device-Specific Register Mapping to Configuration, Control,
and Status Memory Block
2.3.8
Accessing Reserved Registers and Bits
Reserved registers and bits in the CCSR memory space are not guaranteed to have predictable values. In
general, reads of reserved bits will return zeros, but software should not rely on the value of any reserved
bit being a zero or remaining consistent. Unless otherwise specified, when writing registers in CCSR
memory space, reserved bits should be written with zeros. Writing ones to a reserved bit may result in
undefined operation.
2.4
Complete CCSR Map
Table 2-11 lists the MPC8548E memory-mapped registers.
In this table and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
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•
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
NOTE
In the eTSEC (three-speed Ethernet controller) section of the following
table, registers denoted with an asterisk (*) are new to the enhanced TSEC
(eTSEC) and are not supported by PowerQUICC III TSECs.
Table 2-11. Memory Map
Offset
Register
Access
Reset
Section/Page
Local-Access Registers—Configuration, Control, and Status Registers
0x0_0000
CCSRBAR—Configuration, control, and status registers base
address register
R/W
0x000F_F700
4.3.1.1.2/4-5
0x0_0008
ALTCBAR—Alternate configuration base address register
R/W
0x0000_0000
4.3.1.2.1/4-6
0x0_0010
ALTCAR—Alternate configuration attribute register
R/W
0x0000_0000
4.3.1.2.1/4-6
0x0_0020
BPTR—Boot page translation register
R/W
0x0000_0000
4.3.1.3.1/4-7
Local-Access Registers—Local-Access Window Base and Size Registers
0x0_0BF8
LAIPBRR1—Local access IP block revision register 1
R
0x0000_0000
2.2.3.2/2-6
0x0_0BFC
LAIPBRR2—Local access IP block revision register 2
R
0x0000_0000
2.2.3.3/2-6
0x0_0C08
LAWBAR0—Local access window 0 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C10
LAWAR0—Local access window 0 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C28
LAWBAR1—Local access window 1 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C30
LAWAR1—Local access window 1 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C48
LAWBAR2—Local access window 2 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C50
LAWAR2—Local access window 2 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C68
LAWBAR3—Local access window 3 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C70
LAWAR3—Local access window 3 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0C88
LAWBAR4—Local access window 4 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0C90
LAWAR4—Local access window 4 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0CA8
LAWBAR5—Local access window 5 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0CB0
LAWAR5—Local access window 5 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0CC8
LAWBAR6—Local access window 6 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0CD0
LAWAR6—Local access window 6 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0CE8
LAWBAR7—Local access window 7 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0CF0
LAWAR7—Local access window 7 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0D08
LAWBAR8—Local access window 8 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0D10
LAWAR8—Local access window 8 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
0x0_0D28
LAWBAR9—Local access window 9 base address register
R/W
0x0000_0000
2.2.3.4/2-7
0x0_0D30
LAWAR9—Local access window 9 attribute register
R/W
0x0000_0000
2.2.3.5/2-7
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Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
e500 Coherency Module
0x0_1000
EEBACR—ECM CCB address configuration register
R/W
0x0000_0003
8.2.1.1/8-3
0x0_1010
EEBPCR—ECM CCB port configuration register
R/W
0x0n00_0000
8.2.1.2/8-4
0x0_1BF8
ECM IP Block Revision Register 1
R
0x0001_0000
8.2.1.3/8-5
0x0_1BFC
ECM IP Block Revision Register 2
R
0x0000_0000
8.2.1.4/8-5
0x0_1E00
EEDR—ECM error detect register
w1c
0x0000_0000
8.2.1.5/8-6
0x0_1E08
EEER—ECM error enable register
R/W
0x0000_0000
8.2.1.6/8-7
0x0_1E0C
EEATR—ECM error attributes capture register
R
0x0000_0000
8.2.1.7/8-7
0x0_1E10
EELADR—ECM error low address capture register
R
0x0000_0000
8.2.1.8/8-8
0x0_1E14
EEHADR—ECM error high address capture register
R
0x0000_0000
8.2.1.9/8-9
R/W
0x0000_0000
9.4.1.1/9-11
R/W
0x0000_0000
9.4.1.2/9-12
DDR Memory Controller
0x0_2000
CS0_BNDS—Chip select 0 memory bounds
0x0_2008
CS1_BNDS—Chip select 1 memory bounds
0x0_2010
CS2_BNDS—Chip select 2 memory bounds
0x0_2018
CS3_BNDS—Chip select 3 memory bounds
0x0_2080
CS0_CONFIG—Chip select 0 configuration
0x0_2084
CS1_CONFIG—Chip select 1 configuration
0x0_2088
CS2_CONFIG—Chip select 2 configuration
0x0_208C
CS3_CONFIG—Chip select 3 configuration
0x0_2100
TIMING_CFG_3—DDR SDRAM timing configuration 3
R/W
0x0000_0000
9.4.1.3/9-14
0x0_2104
TIMING_CFG_0—DDR SDRAM timing configuration 0
R/W
0x0011_0105
9.4.1.5/9-16
0x0_2108
TIMING_CFG_1—DDR SDRAM timing configuration 1
R/W
0x0000_0000
9.4.1.5/9-16
0x0_210C
TIMING_CFG_2—DDR SDRAM timing configuration 2
R/W
0x0000_0000
9.4.1.6/9-18
0x0_2110
DDR_SDRAM_CFG—DDR SDRAM control configuration
R/W
0x0200_0000
9.4.1.7/9-20
0x0_2114
DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
R/W
0x0000_0000
9.4.1.8/9-23
0x0_2118
DDR_SDRAM_MODE—DDR SDRAM mode configuration
R/W
0x0000_0000
9.4.1.9/9-25
0x0_211C
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
R/W
0x0000_0000
9.4.1.10/9-26
0x0_2120
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
R/W
0x0000_0000
9.4.1.11/9-26
0x0_2124
DDR_SDRAM_INTERVAL—DDR SDRAM interval
configuration
R/W
0x0000_0000
9.4.1.12/9-29
0x0_2128
DDR_DATA_INIT—DDR SDRAM data initialization
R/W
0x0000_0000
9.4.1.13/9-30
0x0_2130
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
R/W
0x0200_0000
9.4.1.14/9-30
0x0_2148
DDR_INIT_ADDRESS—DDR training initialization address
R/W
0x0000_0000
9.4.1.15/9-31
0x0_214C
DDR_INIT_EXT_ADDRESS—DDR training initialization
extended address
R/W
0x0000_0000
9.4.1.16/9-31
0x0_2BF8
DDR_IP_REV1—DDR IP Block Revision 1
R/W
0xnnnn_nnnn1
9.4.1.17/9-32
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Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x0_2BFC
DDR_IP_REV2—DDR IP Block Revision 2
R/W
0x00nn_00nn1
9.4.1.18/9-32
0x0_2E00
DATA_ERR_INJECT_HI—Memory data path error injection
mask high
R/W
0x0000_0000
9.4.1.19/9-33
0x0_2E04
DATA_ERR_INJECT_LO—Memory data path error injection
mask low
R/W
0x0000_0000
9.4.1.20/9-33
0x0_2E08
ECC_ERR_INJECT—Memory data path error injection mask
ECC
R/W
0x0000_0000
9.4.1.21/9-34
0x0_2E20
CAPTURE_DATA_HI—Memory data path read capture high
R/W
0x0000_0000
9.4.1.22/9-34
0x0_2E24
CAPTURE_DATA_LO—Memory data path read capture low
R/W
0x0000_0000
9.4.1.23/9-35
0x0_2E28
CAPTURE_ECC—Memory data path read capture ECC
R/W
0x0000_0000
9.4.1.24/9-35
0x0_2E40
ERR_DETECT—Memory error detect
w1c
0x0000_0000
9.4.1.25/9-35
0x0_2E44
ERR_DISABLE—Memory error disable
R/W
0x0000_0000
9.4.1.26/9-36
0x0_2E48
ERR_INT_EN—Memory error interrupt enable
R/W
0x0000_0000
9.4.1.27/9-37
0x0_2E4C
CAPTURE_ATTRIBUTES—Memory error attributes capture
R/W
0x0000_0000
9.4.1.28/9-38
0x0_2E50
CAPTURE_ADDRESS—Memory error address capture
R/W
0x0000_0000
9.4.1.29/9-39
0x0_2E54
CAPTURE_EXT_ADDRESS—Memory error extended
address capture
R/W
0x0000_0000
9.4.1.30/9-40
0x0_2E58
ERR_SBE—Single-Bit ECC memory error management
R/W
0x0000_0000
9.4.1.31/9-40
R/W
0x00
11.3.1.1/11-6
R/W
0x00
11.3.1.2/11-6
2C
I
I2C1 Registers
0x0_3000
0x0_3004
I2CADR—I2C address register
2C
I2CFDR—I
2C
frequency divider register
0x0_3008
I2CCR—I
control register
Mixed
0x00
11.3.1.3/11-7
0x0_300C
I2CSR—I2C
status register
Mixed
0x81
11.3.1.4/11-9
0x0_3010
I2CDR—I2C data register
R/W
0x00
11.3.1.5/11-10
0x0_3014
I2CDFSRR—I2C digital filter sampling rate register
R/W
0x10
11.3.1.6/11-11
I
0x0_3100–
0x0_3114
2C2
Registers
I2C2 Registers2
DUART Registers
0x0_4500
URBR—ULCR[DLAB] = 0 UART0 receiver buffer register
R
0x00
12.3.1.1/12-6
0x0_4500
UTHR—ULCR[DLAB] = 0 UART0 transmitter holding register
W
0x00
12.3.1.2/12-6
0x0_4500
UDLB—ULCR[DLAB] = 1 UART0 divisor least significant byte
register
R/W
0x00
12.3.1.3/12-7
0x0_4501
UIER—ULCR[DLAB] = 0 UART0 interrupt enable register
R/W
0x00
12.3.1.4/12-9
0x0_4501
UDMB—ULCR[DLAB] = 1 UART0 divisor most significant byte
register
R/W
0x00
12.3.1.3/12-7
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-19
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x0_4502
UIIR—ULCR[DLAB] = 0 UART0 interrupt ID register
R
0x01
12.3.1.5/12-10
0x0_4502
UFCR—ULCR[DLAB] = 0 UART0 FIFO control register
W
0x00
12.3.1.6/12-11
0x0_4502
UAFR—ULCR[DLAB] = 1 UART0 alternate function register
R/W
0x00
12.3.1.12/12-17
0x0_4503
ULCR—ULCR[DLAB] = x UART0 line control register
R/W
0x00
12.3.1.7/12-12
0x0_4504
UMCR—ULCR[DLAB] = x UART0 modem control register
R/W
0x00
12.3.1.8/12-14
0x0_4505
ULSR—ULCR[DLAB] = x UART0 line status register
R
0x60
12.3.1.9/12-15
0x0_4506
UMSR—ULCR[DLAB] = x UART0 modem status register
R
0x00
12.3.1.10/12-16
0x0_4507
USCR—ULCR[DLAB] = x UART0 scratch register
R/W
0x00
12.3.1.11/12-17
0x0_4510
UDSR—ULCR[DLAB] = x UART0 DMA status register
R
0x01
12.3.1.13/12-18
0x0_4600
URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
R
0x00
12.3.1.1/12-6
0x0_4600
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register
W
0x00
12.3.1.2/12-6
0x0_4600
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte
register
R/W
0x00
12.3.1.3/12-7
0x0_4601
UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
R/W
0x00
12.3.1.4/12-9
0x0_4601
UDMB_ULCR[DLAB] = 1 UART1 divisor most significant byte
register
R/W
0x00
12.3.1.3/12-7
0x0_4602
UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
R
0x01
12.3.1.5/12-10
0x0_4602
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
W
0x00
12.3.1.6/12-11
0x0_4602
UAFR—ULCR[DLAB] = 1 UART1 alternate function register
R/W
0x00
12.3.1.12/12-17
0x0_4603
ULCR—ULCR[DLAB] = x UART1 line control register
R/W
0x00
12.3.1.7/12-12
0x0_4604
UMCR—ULCR[DLAB] = x UART1 modem control register
R/W
0x00
12.3.1.8/12-14
0x0_4605
ULSR—ULCR[DLAB] = x UART1 line status register
R
0x60
12.3.1.9/12-15
0x0_4606
UMSR—ULCR[DLAB] = x UART1 modem status register
R
0x00
12.3.1.10/12-16
0x0_4607
USCR—ULCR[DLAB] = x UART1 scratch register
R/W
0x00
12.3.1.11/12-17
0x0_4610
UDSR—ULCR[DLAB] = x UART1 DMA status register
R
0x01
12.3.1.13/12-18
R/W
0x0000_nn013
13.3.1.1/13-10
Local Bus Controller Registers
0x0_5000
BR0—Base register 0
0x0_5008
BR1—Base register 1
0x0_5010
BR2—Base register 2
0x0_5018
BR3—Base register 3
0x0_5020
BR4—Base register 4
0x0_5028
BR5—Base register 5
0x0_5030
BR6—Base register 6
0x0_5038
BR7—Base register 7
0x0000_0000
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-20
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
R/W
0x0000_0FF7
13.3.1.2/13-12
0x0_5004
OR0—Options register 0
0x0_500C
OR1—Options register 1
0x0_5014
OR2—Options register 2
0x0_501C
OR3—Options register 3
0x0_5024
OR4—Options register 4
0x0_502C
OR5—Options register 5
0x0_5034
OR6—Options register 6
0x0_503C
OR7—Options register 7
0x0_5068
MAR—UPM address register
R/W
0x0000_0000
13.3.1.3/13-17
0x0_5070
MAMR—UPMA mode register
R/W
0x0000_0000
13.3.1.4/13-17
0x0_5074
MBMR—UPMB mode register
R/W
0x0000_0000
13.3.1.4/13-17
0x0_5078
MCMR—UPMC mode register
R/W
0x0000_0000
13.3.1.4/13-17
0x0_5084
MRTPR—Memory refresh timer prescaler register
R/W
0x0000_0000
13.3.1.5/13-20
0x0_5088
MDR—UPM data register
R/W
0x0000_0000
13.3.1.6/13-20
0x0_5094
LSDMR—SDRAM mode register
R/W
0x0000_0000
13.3.1.7/13-21
0x0_50A0
LURT—UPM refresh timer
R/W
0x0000_0000
13.3.1.8/13-23
0x0_50A4
LSRT—SDRAM refresh timer
R/W
0x0000_0000
13.3.1.9/13-23
0x0_50B0
LTESR—Transfer error status register
w1c
0x0000_0000
13.3.1.10/13-24
0x0_50B4
LTEDR—Transfer error disable register
R/W
0x0000_0000
13.3.1.11/13-25
0x0_50B8
LTEIR—Transfer error interrupt register
R/W
0x0000_0000
13.3.1.12/13-26
0x0_50BC
LTEATR—Transfer error attributes register
R/W
0x0000_0000
13.3.1.13/13-27
0x0_50C0
LTEAR—Transfer error address register
R/W
0x0000_0000
13.3.1.14/13-28
0x0_50D0
LBCR—Configuration register
R/W
0x0000_0000
13.3.1.15/13-29
0x0_50D4
LCRR—Clock ratio register
R/W
0x8000_0008
13.3.1.16/13-30
0x0000_0000
PCI/X Registers
PCI1/PCI-X Interface (PCI1/X)
PCI Configuration Access Registers
0x0_8000
CFG_ADDR—PCI configuration address
R/W
0x0000_0000
16.3.1.1.1/16-17
0x0_8004
CFG_DATA—PCI configuration data
R/W
0x0000_0000
16.3.1.1.2/16-18
0x0_8008
INT_ACK—PCI interrupt acknowledge
R
0x0000_0000
16.3.1.1.3/16-19
Reserved
—
—
—
0x0000_0000
16.3.1.2.1/16-19
0x0_800C–
0x0_8BFC
PCI ATMU Registers—Outbound and Inbound
0x0_8C00–0x0_8C3C–Outbound Window 0 (default)
0x0_8C00
POTAR0—PCI outbound window 0 (default) translation
address register
R/W
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-21
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
R/W
0x0000_0000
16.3.1.2.2/16-20
0x0_8C04
POTEAR0—PCI outbound window 0 (default) translation
extended address register
0x0_8C08
Reserved
—
—
0x0_8C0C
Reserved
—
—
0x0_8C10
POWAR0—PCI outbound window 0 (default) attributes register
R/W
0x8004_401F
0x0_8C14–
0x0_8C1C
Reserved
—
—
16.3.1.2.4/16-21
0x0_8C20–0x0_8C3C—Outbound Window 1
0x0_8C20
POTAR1—PCI outbound window 1 translation address register
R/W
0x0000_0000
16.3.1.2.1/16-19
0x0_8C24
POTEAR1—PCI outbound window 1 translation extended
address register
R/W
0x0000_0000
16.3.1.2.2/16-20
0x0_8C28
POWBAR1—PCI outbound window 1 base address register
R/W
0x0000_0000
16.3.1.2.3/16-20
0x0_8C2C
Reserved
—
—
0x0_8C30
POWAR1—PCI outbound window 1 attributes register
R/W
0x0000_0000
0x0_8C34–
0x0_8C3C
Reserved
—
—
16.3.1.2.4/16-21
0x0_8C40–0x0_8C5C—Outbound Window 2
0x0_8C40
POTAR2—PCI outbound window 2 translation address register
R/W
0x0000_0000
16.3.1.2.1/16-19
0x0_8C44
POTEAR2—PCI outbound window 2 translation extended
address register
R/W
0x0000_0000
16.3.1.2.2/16-20
0x0_8C48
POWBAR2—PCI outbound window 2 base address register
R/W
0x0000_0000
16.3.1.2.3/16-20
0x0_8C4C
Reserved
—
—
0x0_8C50
POWAR2—PCI outbound window 2 attributes register
R/W
0x0000_0000
0x0_8C54–
0x0_8C5C
Reserved
—
—
16.3.1.2.4/16-21
0x0_8C60–0x0_8C7C—Outbound Window 3
0x0_8C60
POTAR3—PCI outbound window 3 translation address register
R/W
0x0000_0000
16.3.1.2.1/16-19
0x0_8C64
POTEAR3—PCI outbound window 3 translation extended
address register
R/W
0x0000_0000
16.3.1.2.2/16-20
0x0_8C68
POWBAR3—PCI outbound window 3 base address register
R/W
0x0000_0000
16.3.1.2.3/16-20
0x0_8C6C
Reserved
—
—
0x0_8C70
POWAR3—PCI outbound window 3 attributes register
R/W
0x0000_0000
0x0_8C74–
0x0_8C7C
Reserved
—
—
16.3.1.2.4/16-21
0x0_8C80–0x0_8C9C—Outbound Window 4
0x0_8C80
POTAR4—PCI outbound window 4 translation address register
R/W
0x0000_0000
16.3.1.2.1/16-19
0x0_8C84
POTEAR4—PCI outbound window 4 translation extended
address register
R/W
0x0000_0000
16.3.1.2.2/16-20
0x0_8C88
POWBAR4—PCI outbound window 4 base address register
R/W
0x0000_0000
16.3.1.2.3/16-20
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-22
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
0x0_8C8C
Reserved
0x0_8C90
POWAR4—PCI outbound window 4 attributes register
0x0_8C94–
0x0_8D9C
Reserved
Access
Reset
—
—
R/W
0x0000_0000
—
—
Section/Page
16.3.1.2.4/16-21
0x0_8DA0–0x0_8DBC–Inbound Window 3
0x0_8DA0
PITAR3—PCI inbound window 3 translation address register
R/W
0x0000_0000
0x0_8DA4
Reserved
0x0_8DA8
16.3.1.3.1/16-23
—
—
PIWBAR3—PCI inbound window 3 base address register
R/W
0x0000_0000
16.3.1.3.2/16-24
0x0_8DAC
PIWBEAR3—PCI inbound window 3 base extended address
register
R/W
0x0000_0000
16.3.1.3.3/16-24
0x0_8DB0
PIWAR3—PCI inbound window 3 attributes register
R/W
0x0000_0000
16.3.1.3.4/16-25
0x0_8DB4–
0x0_8DBC
Reserved
—
—
0x0_8DC0–0x0_8DDC–Inbound Window 2
0x0_8DC0
PITAR2—PCI inbound window 2 translation address register
R/W
0x0000_0000
0x0_8DC4
Reserved
0x0_8DC8
16.3.1.3.1/16-23
—
—
PIWBAR2—PCI inbound window 2 base address register
R/W
0x0000_0000
16.3.1.3.2/16-24
0x0_8DCC
PIWBEAR2—PCI inbound window 2 base extended address
register
R/W
0x0000_0000
16.3.1.3.3/16-24
0x0_8DD0
PIWAR2—PCI inbound window 2 attributes register
R/W
0x0000_0000
16.3.1.3.4/16-25
0x0_8DD4–
0x0_8DDC
Reserved
—
—
0x0_8DE0–0x0_8DFC–Inbound Window 1
0x0_8DE0
PITAR1—PCI inbound window 1 translation address register
0x0_8DE4
Reserved
0x0_8DE8
PIWBAR1—PCI inbound window 1 base address register
0x0_8DEC
Reserved
0x0_8DF0
PIWAR1—PCI inbound window 1 attributes register
0x0_8DF4–
0x0_8DFC
Reserved
R/W
0x0000_0000
16.3.1.3.1/16-23
—
—
R/W
0x0000_0000
16.3.1.3.2/16-24
—
—
—
R/W
0x0000_0000
16.3.1.3.4/16-25
—
—
PCI Error Management Registers
0x0_8E00
ERR_DR—PCI error detect register
w1c
0x0000_0000
16.3.1.4.1/16-27
0x0_8E04
ERR_CAP_DR—PCI error capture disabled register
R/W
0x0000_0000
16.3.1.4.2/16-28
0x0_8E08
ERR_EN—PCI error enable register
R/W
0x0000_0000
16.3.1.4.3/16-29
0x0_8E0C
ERR_ATTRIB—PCI error attributes capture register
R/W
0x0000_0000
16.3.1.4.4/16-30
0x0_8E10
ERR_ADDR—PCI error address capture register
R/W
0x0000_0000
16.3.1.4.5/16-31
0x0_8E14
ERR_EXT_ADDR—PCI error extended address capture
register
R/W
0x0000_0000
16.3.1.4.6/16-31
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-23
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x0_8E18
ERR_DL—PCI error data low capture register
R/W
0x0000_0000
16.3.1.4.7/16-32
0x0_8E1C
ERR_DH—PCI error data high capture register
R/W
0x0000_0000
16.3.1.4.8/16-32
0x0_8E20
GAS_TIMR—PCI gasket timer register
R/W
0x0100_3FFF
16.3.1.4.9/16-32
0x0_8E24
PCIX_TIMR—PCI-X split completion timer register
R/W
0x0100_3FFF
16.3.1.4.10/16-33
0x0_8E28–
0x0_8EFC
Reserved
—
—
—
0x0_8F00–
0x0_8FFC
Reserved for debug
—
—
—
PCI2 Registers
0x0_9000–
0x0_9FFC
PCI2 registers
Note: All registers defined for PCI1/PCI-X are also defined for PCI2 (with the exception of PCIX_TIMR, which
applies only to the PCI-X interface); the offsets of PCI2 registers begin with 0x0_9nnn.
PCI Express Registers
PCI Express Configuration Access Registers
0x0_A000
PEX_CONFIG_ADDR—PCI Express configuration address
register
R/W
0x0000_0000
18.3.2.1/18-9
0x0_A004
PEX _CONFIG_DATA—PCI Express configuration data
register
R/W
0x0000_0000
18.3.2.2/18-10
0x0_A008
Reserved
—
—
0x0_A00C
PEX_OTB_CPL_TOR—PCI Express outbound completion
timeout register
R/W
0x0010_FFFF
18.3.2.3/18-11
0x0_A010
PEX_CONF_RTY_TOR—PCI Express configuration retry
timeout register
R/W
0x0400_FFFF
18.3.2.4/18-11
0x0_A014
PEX_CONFIG—PCI Express configuration register
R/W
0x0000_0000
18.3.2.5/18-12
0x0_A018–
0x0_A01C
Reserved
—
—
PCI Express Power Management Event & Message Registers
0x0_A020
PEX_PME_MES_DR—PCI Express PME & message detect
register
w1c
0x0000_0000
18.3.3.1/18-13
0x0_A024
PEX_PME_MES_DISR—PCI Express PME & message
disable register
R/W
0x0000_0000
18.3.3.2/18-14
0x0_A028
PEX_PME_MES_IER—PCI Express PME & message
interrupt enable register
R/W
0x0000_0000
18.3.3.3/18-16
0x0_A02C
PEX_PMCR—PCI Express power management command
register
R/W
0x0000_0000
18.3.3.4/18-17
0x0_A030–
0x0_ABF7
Reserved
—
—
R
0x0208_0100
PCI Express Block ID Registers
0x0_ABF8
PEX_IP_BLK_REV1—Block revision register 1
18.3.4.1/18-18
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-24
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
0x0_ABFC
Register
PEX_IP_BLK_REV2—Block revision register 2
Access
Reset
Section/Page
R
0x0000_0000
18.3.4.2/18-19
PCI Express ATMU Registers
0x0_AC00–0x0_AC1C–Outbound Window 0 (default)
0x0_AC00
PEXOTAR0—PCI Express outbound translation address
register 0 (default)
R/W
0x0000_0000
18.3.5.1.1/18-20
0x0_AC04
PEXOTEAR0—PCI Express outbound translation extended
address register 0 (default)
R/W
0x0000_0000
18.3.5.1.2/18-21
0x0_AC08–
0x0_AC0C
Reserved
—
—
0x0_AC10
PEXOWAR0—PCI Express outbound window attributes
register 0 (default)
Mixed
0x8004_4023
0x0_AC14–
0x0_AC1C
Reserved
—
—
18.3.5.1.4/18-22
0x0_AC20–0x0_AC3C—Outbound Window 1
0x0_AC20
PEXOTAR1—PCI Express outbound translation address
register 1
R/W
0x0000_0000
18.3.5.1.1/18-20
0x0_AC24
PEXOTEAR1—PCI Express outbound translation extended
address register 1
R/W
0x0000_0000
18.3.5.1.2/18-21
0x0_AC28
PEXOWBAR1—PCI Express outbound window base address
register 1
R/W
0x0000_0000
18.3.5.1.3/18-21
0x0_AC2C
Reserved
—
—
0x0_AC30
PEXOWAR1—PCI Express outbound window attributes
register 1
R/W
0x0004_4023
0x0_AC34–
0x0_AC3C
Reserved
—
—
18.3.5.1.4/18-22
0x0_AC40–0x0_AC5C—Outbound Window 2
0x0_AC40
PEXOTAR2—PCI Express outbound translation address
register 2
R/W
0x0000_0000
18.3.5.1.1/18-20
0x0_AC44
PEXOTEAR2—PCI Express outbound translation extended
address register 2
R/W
0x0000_0000
18.3.5.1.2/18-21
0x0_AC48
PEXOWBAR2—PCI Express outbound window base address
register 2
R/W
0x0000_0000
18.3.5.1.3/18-21
0x0_AC4C
Reserved
—
—
0x0_AC50
PEXOWAR2—PCI Express outbound window attributes
register 2
R/W
0x0004_4023
0x0_AC54–
0x0_AC5C
Reserved
—
—
18.3.5.1.4/18-22
0x0_AC60–0x0_AC7C—Outbound Window 3
0x0_AC60
PEXOTAR3—PCI Express outbound translation address
register 3
R/W
0x0000_0000
18.3.5.1.1/18-20
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-25
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x0_AC64
PEXOTEAR3—PCI Express outbound translation extended
address register 3
R/W
0x0000_0000
18.3.5.1.2/18-21
0x0_AC68
PEXOWBAR3—PCI Express outbound window base address
register 3
R/W
0x0000_0000
18.3.5.1.3/18-21
0x0_AC6C
Reserved
—
—
0x0_AC70
PEXOWAR3—PCI Express outbound window attributes
register 3
R/W
0x0004_4023
0x0_AC74–
0x0_AC7C
Reserved
—
—
18.3.5.1.4/18-22
0x0_AC80–0x0_AC9C—Outbound Window 4
0x0_AC80
PEXOTAR4—PCI Express outbound translation address
register 4
R/W
0x0000_0000
18.3.5.1.1/18-20
0x0_AC84
PEXOTEAR4—PCI Express outbound translation extended
address register 4
R/W
0x0000_0000
18.3.5.1.2/18-21
0x0_AC88
PEXOWBAR4—PCI Express outbound window base address
register 4
R/W
0x0000_0000
18.3.5.1.3/18-21
0x0_AC8C
Reserved
—
—
0x0_AC90
PEXOWAR4—PCI Express outbound window attributes
register 4
R/W
0x0004_4023
0x0_AC94–
0x0_AC9C
Reserved
—
—
0x0_ACA0–
0x0_AD9C
Reserved
—
—
18.3.5.1.4/18-22
0x0_ADA0–0x0_ADBC–Inbound Window 3
0x0_ADA0
PEXITAR3—PCI Express inbound translation address register
3
R/W
0x0000_0000
0x0_ADA4
Reserved
0x0_ADA8
18.3.5.2.3/18-25
—
—
PEXIWBAR3—PCI Express inbound window base address
register 3
R/W
0x0000_0000
18.3.5.2.4/18-26
0x0_ADAC
PEXIWBEAR3—PCI Express inbound window base extended
address register 3
R/W
0x0000_0000
18.3.5.2.5/18-27
0x0_ADB0
PEXIWAR3—PCI Express inbound window attributes register 3
R/W
0x20F4_4023
18.3.5.2.6/18-27
0x0_ADB4–
0x0_ADBC
Reserved
—
—
0x0_ADC0–0x0_ADDC–Inbound Window 2
0x0_ADC0
PEXITAR2—PCI Express inbound translation address register
2
0x0_ADC4
Reserved
0x0_ADC8
PEXIWBAR2—PCI Express inbound window base address
register 2
R/W
0x0000_0000
—
—
R/W
0x0000_0000
18.3.5.2.3/18-25
18.3.5.2.4/18-26
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-26
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x0_ADCC
PEXIWBEAR2—PCI Express inbound window base extended
address register 2
R/W
0x0000_0000
18.3.5.2.5/18-27
0x0_ADD0
PEXIWAR2—PCI Express inbound window attributes register 2
R/W
0x20F4_4023
18.3.5.2.6/18-27
0x0_ADD4–
0x0_ADDC
Reserved
—
—
0x0_ADE0–0x0_ADFC–Inbound Window 1
0x0_ADE0
PEXITAR1—PCI Express inbound translation address register
1
0x0_ADE4
Reserved
0x0_ADE8
PEXIWBAR1—PCI Express inbound window base address
register 1
0x0_ADEC
Reserved
0x0_ADF0
PEXIWAR1—PCI Express inbound window attributes register 1
0x0_ADF4–
0x0_ADFC
Reserved
R/W
0x0000_0000
—
—
R/W
0x0000_0000
—
—
R/W
0x20F4_4023
—
—
18.3.5.2.3/18-25
18.3.5.2.4/18-26
18.3.5.2.6/18-27
PCI Express Error Management Registers
0x0_AE00
PEX_ERR_DR—PCI Express error detect register
w1c
0x0000_0000
0x0_AE04
Reserved
0x0_AE08
PEX_ERR_EN—PCI Express error interrupt enable register
0x0_AE0C
Reserved
0x0_AE10
PEX_ERR_DISR—PCI Express error disable register
0x0_AE14–
0x0_AE1C
Reserved
0x0_AE20
PEX_ERR_CAP_STAT—PCI Express error capture status
register
0x0_AE24
Reserved
0x0_AE28
18.3.6.1/18-29
—
—
R/W
0x0000_0000
—
—
R/W
0x0000_0000
—
—
Mixed
0x0000_0000
—
—
PEX_ERR_CAP_R0—PCI Express error capture register 0
R/W
0x0000_0000
18.3.6.5/18-36
0x0_AE2C
PEX_ERR_CAP_R1—PCI Express error capture register 1
R/W
0x0000_0000
18.3.6.6/18-38
0x0_AE30
PEX_ERR_CAP_R2—PCI Express error capture register 2
R/W
0x0000_0000
‘
0x0_AE34
PEX_ERR_CAP_R3—PCI Express error capture register 3
R/W
0x0000_0000
‘
0x0_AE38–
0x0_AFFC
Reserved
—
—
18.3.6.2/18-32
18.3.6.3/18-34
18.3.6.4/18-35
L2/SRAM Memory-Mapped Configuration Registers
0x2_0000
L2CTL—L2 control register
R/W
0x2000_0000
7.3.1.1/7-10
0x2_0010
L2CEWAR0—L2 cache external write address register 0
R/W
0x0000_0000
7.3.1.2.1/7-13
0x2_0014
L2CEWAREA0—L2 cache external write address register
extended address 0
R/W
0x0000_0000
7.3.1.2.2/7-14
0x2_0018
L2CEWCR0—L2 cache external write control register 0
R/W
0x0000_0000
7.3.1.2.3/7-15
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-27
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x2_0020
L2CEWAR1—L2 cache external write address register 1
R/W
0x0000_0000
7.3.1.2.1/7-13
0x2_0024
L2CEWAREA1—L2 cache external write address register
extended address 1
R/W
0x0000_0000
7.3.1.2.2/7-14
0x2_0028
L2CEWCR1—L2 cache external write control register 1
R/W
0x0000_0000
7.3.1.2.3/7-15
0x2_0030
L2CEWAR2—L2 cache external write address register 2
R/W
0x0000_0000
7.3.1.2.1/7-13
0x2_0034
L2CEWAREA2—L2 cache external write address register
extended address 2
R/W
0x0000_0000
7.3.1.2.2/7-14
0x2_0038
L2CEWCR2—L2 cache external write control register 2
R/W
0x0000_0000
7.3.1.2.3/7-15
0x2_0040
L2CEWAR3—L2 cache external write address register 3
R/W
0x0000_0000
7.3.1.2.1/7-13
0x2_0044
L2CEWAREA3—L2 cache external write address register
extended address 3
R/W
0x0000_0000
7.3.1.2.2/7-14
0x2_0048
L2CEWCR3—L2 cache external write control register 3
R/W
0x0000_0000
7.3.1.2.3/7-15
0x2_0100
L2SRBAR0—L2 memory-mapped SRAM base address
register 0
R/W
0x0000_0000
7.3.1.3.1/7-16
0x2_0104
L2SRBAREA0—L2 memory-mapped SRAM base address
register extended address 0
R/W
0x0000_0000
7.3.1.3.2/7-17
0x2_0108
L2SRBAR1—L2 memory-mapped SRAM base address
register 1
R/W
0x0000_0000
7.3.1.3.1/7-16
0x2_010C
L2SRBAREA1—L2 memory-mapped SRAM base address
register extended address 1
R/W
0x0000_0000
7.3.1.3.2/7-17
0x2_0E00
L2ERRINJHI—L2 error injection mask high register
R/W
0x0000_0000
7.3.1.4.1/7-18
0x2_0E04
L2ERRINJLO—L2 error injection mask low register
R/W
0x0000_0000
7.3.1.4.1/7-18
0x2_0E08
L2ERRINJCTL—L2 error injection tag/ECC control register
R/W
0x0000_0000
7.3.1.4.1/7-18
0x2_0E20
L2CAPTDATAHI—L2 error data high capture register
R
0x0000_0000
7.3.1.4.2/7-20
0x2_0E24
L2CAPTDATALO—L2 error data low capture register
R
0x0000_0000
7.3.1.4.2/7-20
0x2_0E28
L2CAPTECC—L2 error syndrome register
R
0x0000_0000
7.3.1.4.2/7-20
0x2_0E40
L2ERRDET—L2 error detect register
w1c
0x0000_0000
7.3.1.4.2/7-20
0x2_0E44
L2ERRDIS—L2 error disable register
R/W
0x0000_0000
7.3.1.4.2/7-20
0x2_0E48
L2ERRINTEN—L2 error interrupt enable register
R/W
0x0000_0000
7.3.1.4.2/7-20
0x2_0E4C
L2ERRATTR—L2 error attributes capture register
R/W
0x0000_0000
7.3.1.4.2/7-20
0x2_0E50
L2ERRADDRH—L2 error address capture register high
R
0x0000_0000
7.3.1.4.2/7-20
0x2_0E54
L2ERRADDRL—L2 error address capture register low
R
0x0000_0000
7.3.1.4.2/7-20
0x2_0E58
L2ERRCTL—L2 error control register
R/W
0x0000_0000
7.3.1.4.2/7-20
DMA Registers
0x2_1100
MR0—DMA 0 mode register
R/W
0x0000_0000
15.3.1.1/15-10
0x2_1104
SR0—DMA 0 status register
Mixed
0x0000_0000
15.3.1.2/15-12
0x2_1108
ECLNDAR0—DMA 0 current link descriptor extended address
register
R/W
0x0000_0000
15.3.1.3/15-13
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-28
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x2_110C
CLNDAR0—DMA 0 current link descriptor address register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_1110
SATR0—DMA 0 source attributes register
R/W
0x0000_0000
15.3.1.4/15-15
0x2_1114
SAR0—DMA 0 source address register
R/W
0x0000_0000
15.3.1.5/15-17
0x2_1118
DATR0—DMA 0 destination attributes register
R/W
0x0000_0000
15.3.1.6/15-18
0x2_111C
DAR0—DMA 0 destination address register
R/W
0x0000_0000
15.3.1.7/15-20
0x2_1120
BCR0—DMA 0 byte count register
R/W
0x0000_0000
15.3.1.8/15-22
0x2_1124
ENLNDAR0—DMA 0 next link descriptor extended address
register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_1128
NLNDAR0—DMA 0 next link descriptor address register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_112C
Reserved
—
—
0x2_1130
ECLSDAR0—DMA 0 current list descriptor extended address
register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_1134
CLSDAR0—DMA 0 current list alternate base descriptor
address register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_1138
ENLSDAR0—DMA 0 next list descriptor extended address
register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_113C
NLSDAR0—DMA 0 next list descriptor address register
Mixed
0x0000_0000
15.3.1.11/15-24
0x2_1140
SSR0—DMA 0 source stride register
R/W
0x0000_0000
15.3.1.12/15-25
0x2_1144
DSR0—DMA 0 destination stride register
R/W
0x0000_0000
15.3.1.13/15-26
—
—
—
0x2_1148–
0x2_117C
Reserved
0x2_1180
MR1—DMA 1 mode register
R/W
0x0000_0000
15.3.1.1/15-10
0x2_1184
SR1—DMA 1 status register
Mixed
0x0000_0000
15.3.1.2/15-12
0x2_1188
ECLNDAR1—DMA 1 current link descriptor extended address
register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_118C
CLNDAR1—DMA 1 current link descriptor address register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_1190
SATR1—DMA 1 source attributes register
R/W
0x0000_0000
15.3.1.4/15-15
0x2_1194
SAR1—DMA 1 source address register
R/W
0x0000_0000
15.3.1.5/15-17
0x2_1198
DATR1—DMA 1 destination attributes register
R/W
0x0000_0000
15.3.1.6/15-18
0x2_119C
DAR1—DMA 1 destination address register
R/W
0x0000_0000
15.3.1.7/15-20
0x2_11A0
BCR1—DMA 1 byte count register
R/W
0x0000_0000
15.3.1.8/15-22
0x2_11A4
ENLNDAR1—DMA 1 next link descriptor extended address
register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_11A8
NLNDAR1—DMA 1 next link descriptor address register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_11AC
Reserved
—
—
—
0x2_11B0
ECLSDAR1—DMA 1 current list descriptor extended address
register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_11B4
CLSDAR1—DMA 1 current list alternate base descriptor
address register
R/W
0x0000_0000
15.3.1.10/15-23
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-29
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x2_11B8
ENLSDAR1—DMA 1 next list descriptor extended address
register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_11BC
NLSDAR1—DMA 1 next list descriptor address register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_11C0
SSR1—DMA 1 source stride register
R/W
0x0000_0000
15.3.1.12/15-25
0x2_11C4
DSR1—DMA 1 destination stride register
R/W
0x0000_0000
15.3.1.13/15-26
—
—
—
0x2_11C8–
0x2_11FC
Reserved
0x2_1200
MR2—DMA 2 mode register
R/W
0x0000_0000
15.3.1.1/15-10
0x2_1204
SR2—DMA 2 status register
Mixed
0x0000_0000
15.3.1.2/15-12
0x2_1208
ECLNDAR2—DMA 2 current link descriptor extended address
register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_120C
CLNDAR2—DMA 2 current link descriptor address register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_1210
SATR2—DMA 2 source attributes register
R/W
0x0000_0000
15.3.1.4/15-15
0x2_1214
SAR2—DMA 2 source address register
R/W
0x0000_0000
15.3.1.5/15-17
0x2_1218
DATR2—DMA 2 destination attributes register
R/W
0x0000_0000
15.3.1.6/15-18
0x2_121C
DAR2—DMA 2 destination address register
R/W
0x0000_0000
15.3.1.7/15-20
0x2_1220
BCR2—DMA 2 byte count register
R/W
0x0000_0000
15.3.1.8/15-22
0x2_1224
ENLNDAR2—DMA 2 next link descriptor extended address
register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_1228
NLNDAR2—DMA 2 next link descriptor address register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_122C
Reserved
—
—
—
0x2_1230
ECLSDAR2—DMA 2 current list descriptor extended address
register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_1234
CLSDAR2—DMA 2 current list alternate base descriptor
address register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_1238
ENLSDAR2—DMA 2 next list descriptor extended address
register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_123C
NLSDAR2—DMA 2 next list descriptor address register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_1240
SSR2—DMA 2 source stride register
R/W
0x0000_0000
15.3.1.12/15-25
0x2_1244
DSR2—DMA 2 destination stride register
R/W
0x0000_0000
15.3.1.13/15-26
—
—
—
0x2_1248–
0x2_127C
Reserved
0x2_1280
MR3—DMA 3 mode register
R/W
0x0000_0000
15.3.1.1/15-10
0x2_1284
SR3—DMA 3 status register
Mixed
0x0000_0000
15.3.1.2/15-12
0x2_1288
ECLNDAR3—DMA 3 current link descriptor extended address
register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_128C
CLNDAR3—DMA 3 current link descriptor address register
R/W
0x0000_0000
15.3.1.3/15-13
0x2_1290
SATR3—DMA 3 source attributes register
R/W
0x0000_0000
15.3.1.4/15-15
0x2_1294
SAR3—DMA 3 source address register
R/W
0x0000_0000
15.3.1.5/15-17
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-30
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x2_1298
DATR3—DMA 3 destination attributes register
R/W
0x0000_0000
15.3.1.6/15-18
0x2_129C
DAR3—DMA 3 destination address register
R/W
0x0000_0000
15.3.1.7/15-20
0x2_12A0
BCR3—DMA 3 byte count register
R/W
0x0000_0000
15.3.1.8/15-22
0x2_12A4
ENLNDAR3—DMA 3 next link descriptor extended address
register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_12A8
NLNDAR3—DMA 3 next link descriptor address register
R/W
0x0000_0000
15.3.1.9/15-22
0x2_12AC
Reserved
—
—
0x2_12B0
ECLSDAR3—DMA 3 current list descriptor extended address
register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_12B4
CLSDAR 3—DMA 3 current list alternate base descriptor
address register
R/W
0x0000_0000
15.3.1.10/15-23
0x2_12B8
ENLSDAR3—DMA 3 next list descriptor extended address
register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_12BC
NLSDAR3—DMA 3 next list descriptor address register
R/W
0x0000_0000
15.3.1.11/15-24
0x2_12C0
SSR3—DMA 3 source stride register
R/W
0x0000_0000
15.3.1.12/15-25
0x2_12C4
DSR3—DMA 3 destination stride register
R/W
0x0000_0000
15.3.1.13/15-26
Reserved
—
—
—
DGSR—DMA general status register
R
0x0000_0000
15.3.1.14/15-27
0x2_12C8–
0x2_12FC
0x2_1300
eTSEC Registers
eTSECn General Control and Status Registers
0x2_4000
TSEC_ID*—Controller ID register
R
0x0124_0000
14.5.3.1.1/14-21
0x2_4004
TSEC_ID2*—Controller ID register
R
0x0030_00F0
14.5.3.1.2/14-22
0x2_4008–
0x2_400C
Reserved
—
—
—
0x2_4010
IEVENT—Interrupt event register
w1c
0x0000_0000
14.5.3.1.3/14-23
0x2_4014
IMASK—Interrupt mask register
R/W
0x0000_0000
14.5.3.1.4/14-27
0x2_4018
EDIS—Error disabled register
R/W
0x0000_0000
14.5.3.1.5/14-29
0x2_401C
Reserved
—
—
—
0x2_4020
ECNTRL—Ethernet control register
R/W
0x0000_0000
14.5.3.1.6/14-31
0x2_4024
Reserved
—
—
—
0x2_4028
PTV—Pause time value register
R/W
0x0000_0000
14.5.3.1.7/14-33
0x2_402C
DMACTRL—DMA control register
R/W
0x0000_0000
14.5.3.1.8/14-34
0x2_4030
TBIPA—TBI PHY address register
R/W
0x0000_0000
14.5.3.1.9/14-35
0x2_4034–
0x2_4054
Reserved
—
—
—
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-31
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
eTSECn FIFO Control and Status Registers
0x2_4058
FIFO_RX_ALARM—FIFO receive alarm start threshold
register
R/W
0x0000_0040
14.5.3.2.1/14-37
0x2_405C
FIFO_RX_ALARM_SHUTOFF—FIFO receive alarm shut-off
threshold register
R/W
0x0000_0080
14.5.3.2.2/14-37
0x2_4060–
0x2_4088
Reserved
—
—
—
0x2_408C
FIFO_TX_THR—FIFO transmit threshold register
R/W
0x0000_0080
14.5.3.2.3/14-38
0x2_4090–
0x2_4094
Reserved
—
—
—
0x2_4098
FIFO_TX_STARVE—FIFO transmit starve register
R/W
0x0000_0040
14.5.3.2.4/14-38
0x2_409C
FIFO_TX_STARVE_SHUTOFF—FIFO transmit starve shut-off
register
R/W
0x0000_0080
14.5.3.2.5/14-39
0x2_40A0–
0x2_40FC
Reserved
—
—
—
eTSEC n Transmit Control and Status Registers
0x2_4100
TCTRL—Transmit control register
R/W
0x0000_0000
14.5.3.3.1/14-40
0x2_4104
TSTAT—Transmit status register
w1c
0x0000_0000
14.5.3.3.2/14-41
0x2_4108
DFVLAN*—Default VLAN control word
R/W
0x8100_0000
14.5.3.3.3/14-43
0x2_410C
Reserved
—
—
—
0x2_4110
TXIC—Transmit interrupt coalescing register
R/W
0x0000_0000
14.5.3.3.4/14-44
0x2_4114
TQUEUE*—Transmit queue control register
R/W
0x0000_8000
14.5.3.3.5/14-45
0x2_4118–
0x2_413C
Reserved
—
—
—
0x2_4140
TR03WT*—TxBD Rings 0–3 round-robin weightings
R/W
0x0000_0000
14.5.3.3.6/14-46
0x2_4144
TR47WT*—TxBD Rings 4–7 round-robin weightings
R/W
0x0000_0000
14.5.3.3.7/14-47
0x2_4148–
0x2_417C
Reserved
—
—
—
0x2_4180
TBDBPH*—Tx data buffer pointer high bits
R/W
0x0000_0000
14.5.3.3.8/14-47
0x2_4184
TBPTR0—TxBD pointer for ring 0
R/W
0x0000_0000
14.5.3.3.9/14-48
0x2_4188
Reserved
—
—
—
0x2_418C
TBPTR1*—TxBD pointer for ring 1
R/W
0x0000_0000
14.5.3.3.9/14-48
0x2_4190
Reserved
—
—
—
0x2_4194
TBPTR2*—TxBD pointer for ring 2
R/W
0x0000_0000
14.5.3.3.9/14-48
0x2_4198
Reserved
—
—
—
0x2_419C
TBPTR3*—TxBD pointer for ring 3
R/W
0x0000_0000
14.5.3.3.9/14-48
0x2_41A0
Reserved
—
—
—
0x2_41A4
TBPTR4*—TxBD pointer for ring 4
R/W
0x0000_0000
14.5.3.3.9/14-48
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-32
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
0x2_41A8
Reserved
0x2_41AC
TBPTR5*—TxBD pointer for ring 5
0x2_41B0
Reserved
0x2_41B4
TBPTR6*—TxBD pointer for ring 6
0x2_41B8
Reserved
0x2_41BC
TBPTR7*—TxBD pointer for ring 7
0x2_41C0–
0x2_41FC
Reserved
Access
Reset
Section/Page
—
—
—
R/W
0x0000_0000
14.5.3.3.9/14-48
—
—
—
R/W
0x0000_0000
14.5.3.3.9/14-48
—
—
—
R/W
0x0000_0000
14.5.3.3.9/14-48
—
—
—
0x2_4200
TBASEH—TxBD base address high bits
R/W
0x0000_0000
14.5.3.3.10/14-48
0x2_4204
TBASE0—TxBD base address of ring 0
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4208
Reserved
—
—
—
0x2_420C
TBASE1*—TxBD base address of ring 1
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4210
Reserved
—
—
—
0x2_4214
TBASE2*—TxBD base address of ring 2
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4218
Reserved
—
—
—
0x2_421C
TBASE3*—TxBD base address of ring 3
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4220
Reserved
—
—
—
0x2_4224
TBASE4*—TxBD base address of ring 4
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4228
Reserved
—
—
—
0x2_422C
TBASE5*—TxBD base address of ring 5
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4230
Reserved
—
—
—
0x2_4234
TBASE6*—TxBD base address of ring 6
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4238
Reserved
—
—
—
0x2_423C
TBASE7*—TxBD base address of ring 7
R/W
0x0000_0000
14.5.3.3.11/14-49
0x2_4240–
0x2_42FC
Reserved
—
—
—
eTSECn Receive Control and Status Registers
0x2_4300
RCTRL—Receive control register
R/W
0x0000_0000
14.5.3.4.1/14-50
0x2_4304
RSTAT—Receive status register
w1c
0x0000_0000
14.5.3.4.2/14-52
0x2_4308
Reserved
—
—
0x2_4310
RXIC—Receive interrupt coalescing register
R/W
0x0000_0000
14.5.3.4.3/14-54
0x2_4314
RQUEUE*—Receive queue control register.
R/W
0x0080_0080
14.5.3.4.4/14-55
0x2_4318–
0x2_432C
Reserved
—
—
—
0x2_4330
RBIFX*—Receive bit field extract control register
R/W
0x0000_0000
14.5.3.4.5/14-56
0x2_4334
RQFAR*—Receive queue filing table address register
R/W
0x0000_0000
14.5.3.4.6/14-58
0x2_4338
RQFCR*—Receive queue filing table control register
R/W
0x0000_0000
14.5.3.4.7/14-58
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-33
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x2_433C
RQFPR*—Receive queue filing table property register
R/W
0x0000_0000
14.5.3.4.8/14-60
0x2_4340
MRBLR—Maximum receive buffer length register
R/W
0x0000_0000
14.5.3.4.9/14-63
0x2_4344–
0x2_437C
Reserved
—
—
—
0x2_4380
RBDBPH*—Rx data buffer pointer high bits
R/W
0x0000_0000
14.5.3.4.10/14-63
0x2_4384
RBPTR0—RxBD pointer for ring 0
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_4388
Reserved
—
—
—
0x2_438C
RBPTR1*—RxBD pointer for ring 1
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_4390
Reserved
—
—
—
0x2_4394
RBPTR2*—RxBD pointer for ring 2
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_4398
Reserved
—
—
—
0x2_439C
RBPTR3*—RxBD pointer for ring 3
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_43A0
Reserved
—
—
—
0x2_43A4
RBPTR4*—RxBD pointer for ring 4
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_43A8
Reserved
—
—
—
0x2_43AC
RBPTR5*—RxBD pointer for ring 5
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_43B0
Reserved
—
—
—
0x2_43B4
RBPTR6*—RxBD pointer for ring 6
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_43B8
Reserved
—
—
—
0x2_43BC
RBPTR7*—RxBD pointer for ring 7
R/W
0x0000_0000
14.5.3.4.11/14-64
0x2_43C0–
0x2_43FC
Reserved
—
—
—
0x2_4400
RBASEH—RxBD base address high bits
R/W
0x0000_0000
14.5.3.4.12/14-64
0x2_4404
RBASE0—RxBD base address of ring 0
R/W
0x0000_0000
14.5.3.4.13/14-65
0x2_4408
Reserved
—
—
—
0x2_440C
RBASE1*—RxBD base address of ring 1
R/W
0x0000_0000
14.5.3.4.13/14-65
0x2_4410
Reserved
—
—
—
0x2_4414
RBASE2*—RxBD base address of ring 2
R/W
0x0000_0000
14.5.3.4.13/14-65
0x2_4418
Reserved
—
—
—
0x2_441C
RBASE3*—RxBD base address of ring 3
R/W
0x0000_0000
14.5.3.4.13/14-65
0x2_4420
Reserved
—
—
—
0x2_4424
RBASE4*—RxBD base address of ring 4
R/W
0x0000_0000
14.5.3.4.13/14-65
0x2_4428
Reserved
—
—
—
0x2_442C
RBASE5*—RxBD base address of ring 5
R/W
0x0000_0000
14.5.3.4.13/14-65
0x2_4430
Reserved
—
—
—
0x2_4434
RBASE6*—RxBD base address of ring 6
R/W
0x0000_0000
14.5.3.4.13/14-65
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-34
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
0x2_4438
Reserved
0x2_443C
RBASE7*—RxBD base address of ring 7
0x2_4440–
0x2_44FC
Reserved
Access
Reset
Section/Page
—
—
—
R/W
0x0000_0000
14.5.3.4.13/14-65
—
—
—
eTSEC n MAC Registers
0x2_4500
MACCFG1—MAC configuration register 1
R/W
0x0000_0000
14.5.3.6.1/14-68
0x2_4504
MACCFG2—MAC configuration register 2
R/W
0x0000_7000
14.5.3.6.2/14-70
0x2_4508
IPGIFG—Inter-packet/inter-frame gap register
R/W
0x4060_5060
14.5.3.6.3/14-72
0x2_450C
HAFDUP—Half-duplex control
R/W
0x00A1_F037
14.5.3.6.4/14-73
0x2_4510
MAXFRM—Maximum frame size
R/W
0x0000_0600
14.5.3.6.5/14-74
0x2_4514–
0x2_451C
Reserved
—
—
—
0x2_4520
MIIMCFG—MII management configuration
R/W
0x0000_0007
14.5.3.6.6/14-74
0x2_4524
MIIMCOM—MII management command
R/W
0x0000_0000
14.5.3.6.7/14-75
0x2_4528
MIIMADD—MII management address
R/W
0x0000_0000
14.5.3.6.8/14-76
0x2_452C
MIIMCON—MII management control
W
0x0000_0000
14.5.3.6.9/14-76
0x2_4530
MIIMSTAT—MII management status
R
0x0000_0000
14.5.3.6.10/14-77
0x2_4534
MIIMIND—MII management indicator
R
0x0000_0000
14.5.3.6.11/14-77
0x2_4538
Reserved
—
—
—
0x2_453C
IFSTAT—Interface status
R
0x0000_0000
14.5.3.6.12/14-78
0x2_4540
MACSTNADDR1—MAC station address register 1
R/W
0x0000_0000
14.5.3.6.13/14-78
0x2_4544
MACSTNADDR2—MAC station address register 2
R/W
0x0000_0000
14.5.3.6.14/14-79
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-35
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
14.5.3.6.15/14-80
14.5.3.6.16/14-80
0x2_4548
MAC01ADDR1*—MAC exact match address 1, part 1
R/W
0x0000_0000
0x2_454C
MAC01ADDR2*—MAC exact match address 1, part 2
R/W
0x0000_0000
0x2_4550
MAC02ADDR1*—MAC exact match address 2, part 1
R/W
0x0000_0000
0x2_4554
MAC02ADDR2*—MAC exact match address 2, part 2
R/W
0x0000_0000
0x2_4558
MAC03ADDR1*—MAC exact match address 3, part 1
R/W
0x0000_0000
0x2_455C
MAC03ADDR2*—MAC exact match address 3, part 2
R/W
0x0000_0000
0x2_4560
MAC04ADDR1*—MAC exact match address 4, part 1
R/W
0x0000_0000
0x2_4564
MAC04ADDR2*—MAC exact match address 4, part 2
R/W
0x0000_0000
0x2_4568
MAC05ADDR1*—MAC exact match address 5, part 1
R/W
0x0000_0000
0x2_456C
MAC05ADDR2*—MAC exact match address 5, part 2
R/W
0x0000_0000
0x2_4570
MAC06ADDR1*—MAC exact match address 6, part 1
R/W
0x0000_0000
0x2_4574
MAC06ADDR2*—MAC exact match address 6, part 2
R/W
0x0000_0000
0x2_4578
MAC07ADDR1*—MAC exact match address 7, part 1
R/W
0x0000_0000
0x2_457C
MAC07ADDR2*—MAC exact match address 7, part 2
R/W
0x0000_0000
0x2_4580
MAC08ADDR1*—MAC exact match address 8, part 1
R/W
0x0000_0000
0x2_4584
MAC08ADDR2*—MAC exact match address 8, part 2
R/W
0x0000_0000
0x2_4588
MAC09ADDR1*—MAC exact match address 9, part 1
R/W
0x0000_0000
0x2_458C
MAC09ADDR2*—MAC exact match address 9, part 2
R/W
0x0000_0000
0x2_4590
MAC10ADDR1*—MAC exact match address 10, part 1
R/W
0x0000_0000
0x2_4594
MAC10ADDR2*—MAC exact match address 10, part 2
R/W
0x0000_0000
0x2_4598
MAC11ADDR1*—MAC exact match address 11, part 1
R/W
0x0000_0000
0x2_459C
MAC11ADDR2*—MAC exact match address 11, part 2
R/W
0x0000_0000
0x2_45A0
MAC12ADDR1*—MAC exact match address 12, part 1
R/W
0x0000_0000
0x2_45A4
MAC12ADDR2*—MAC exact match address 12, part 2
R/W
0x0000_0000
0x2_45A8
MAC13ADDR1*—MAC exact match address 13, part 1
R/W
0x0000_0000
0x2_45AC
MAC13ADDR2*—MAC exact match address 13, part 2
R/W
0x0000_0000
0x2_45B0
MAC14ADDR1*—MAC exact match address 14, part 1
R/W
0x0000_0000
0x2_45B4
MAC14ADDR2*—MAC exact match address 14, part 2
R/W
0x0000_0000
0x2_45B8
MAC15ADDR1*—MAC exact match address 15, part 1
R/W
0x0000_0000
0x2_45BC
MAC15ADDR2*—MAC exact match address 15, part 2
R/W
0x0000_0000
0x2_45C0–
0x2_467C
Reserved
—
—
—
14.5.3.6.15/14-80
14.5.3.6.16/14-80
eTSEC n Transmit and Receive Counters
0x2_4680
TR64—Transmit and receive 64-byte frame counter
R/W
0x0000_0000
14.5.3.7.1/14-81
0x2_4684
TR127—Transmit and receive 65- to 127-byte frame counter
R/W
0x0000_0000
14.5.3.7.2/14-82
0x2_4688
TR255—Transmit and receive 128- to 255-byte frame counter
R/W
0x0000_0000
14.5.3.7.3/14-82
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-36
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x2_468C
TR511—Transmit and receive 256- to 511-byte frame counter
R/W
0x0000_0000
14.5.3.7.4/14-83
0x2_4690
TR1K—Transmit and receive 512- to 1023-byte frame counter
R/W
0x0000_0000
14.5.3.7.5/14-83
0x2_4694
TRMAX—Transmit and receive 1024- to 1518-byte frame
counter
R/W
0x0000_0000
14.5.3.7.6/14-84
0x2_4698
TRMGV—Transmit and receive 1519- to 1522-byte good VLAN
frame count
R/W
0x0000_0000
14.5.3.7.7/14-84
eTSECn Receive Counters
0x2_469C
RBYT—Receive byte counter
R/W
0x0000_0000
14.5.3.7.8/14-85
0x2_46A0
RPKT—Receive packet counter
R/W
0x0000_0000
14.5.3.7.9/14-85
0x2_46A4
RFCS—Receive FCS error counter
R/W
0x0000_0000
14.5.3.7.10/14-86
0x2_46A8
RMCA—Receive multicast packet counter
R/W
0x0000_0000
14.5.3.7.11/14-86
0x2_46AC
RBCA—Receive broadcast packet counter
R/W
0x0000_0000
14.5.3.7.12/14-87
0x2_46B0
RXCF—Receive control frame packet counter
R/W
0x0000_0000
14.5.3.7.13/14-87
0x2_46B4
RXPF—Receive PAUSE frame packet counter
R/W
0x0000_0000
14.5.3.7.14/14-88
0x2_46B8
RXUO—Receive unknown OP code counter
R/W
0x0000_0000
14.5.3.7.15/14-88
0x2_46BC
RALN—Receive alignment error counter
R/W
0x0000_0000
14.5.3.7.16/14-89
0x2_46C0
RFLR—Receive frame length error counter
R/W
0x0000_0000
14.5.3.7.17/14-89
0x2_46C4
RCDE—Receive code error counter
R/W
0x0000_0000
14.5.3.7.18/14-90
0x2_46C8
RCSE—Receive carrier sense error counter
R/W
0x0000_0000
14.5.3.7.19/14-90
0x2_46CC
RUND—Receive undersize packet counter
R/W
0x0000_0000
14.5.3.7.20/14-91
0x2_46D0
ROVR—Receive oversize packet counter
R/W
0x0000_0000
14.5.3.7.21/14-91
0x2_46D4
RFRG—Receive fragments counter
R/W
0x0000_0000
14.5.3.7.22/14-92
0x2_46D8
RJBR—Receive jabber counter
R/W
0x0000_0000
14.5.3.7.23/14-92
0x2_46DC
RDRP—Receive drop counter
R/W
0x0000_0000
14.5.3.7.24/14-93
eTSECn Transmit Counters
0x2_46E0
TBYT—Transmit byte counter
R/W
0x0000_0000
14.5.3.7.25/14-93
0x2_46E4
TPKT—Transmit packet counter
R/W
0x0000_0000
14.5.3.7.26/14-94
0x2_46E8
TMCA—Transmit multicast packet counter
R/W
0x0000_0000
14.5.3.7.27/14-94
0x2_46EC
TBCA—Transmit broadcast packet counter
R/W
0x0000_0000
14.5.3.7.28/14-95
0x2_46F0
TXPF—Transmit PAUSE control frame counter
R/W
0x0000_0000
14.5.3.7.29/14-95
0x2_46F4
TDFR—Transmit deferral packet counter
R/W
0x0000_0000
14.5.3.7.30/14-96
0x2_46F8
TEDF—Transmit excessive deferral packet counter
R/W
0x0000_0000
14.5.3.7.31/14-96
0x2_46FC
TSCL—Transmit single collision packet counter
R/W
0x0000_0000
14.5.3.7.32/14-97
0x2_4700
TMCL—Transmit multiple collision packet counter
R/W
0x0000_0000
14.5.3.7.33/14-97
0x2_4704
TLCL—Transmit late collision packet counter
R/W
0x0000_0000
14.5.3.7.34/14-98
0x2_4708
TXCL—Transmit excessive collision packet counter
R/W
0x0000_0000
14.5.3.7.35/14-98
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-37
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
R/W
0x0000_0000
14.5.3.7.36/14-99
—
—
—
0x2_470C
TNCL—Transmit total collision counter
0x2_4710
Reserved
0x2_4714
TDRP—Transmit drop frame counter
R/W
0x0000_0000
14.5.3.7.37/14-99
0x2_4718
TJBR—Transmit jabber frame counter
R/W
0x0000_0000
14.5.3.7.38/14-100
0x2_471C
TFCS—Transmit FCS error counter
R/W
0x0000_0000
14.5.3.7.39/14-100
0x2_4720
TXCF—Transmit control frame counter
R/W
0x0000_0000
14.5.3.7.40/14-101
0x2_4724
TOVR—Transmit oversize frame counter
R/W
0x0000_0000
14.5.3.7.41/14-101
0x2_4728
TUND—Transmit undersize frame counter
R/W
0x0000_0000
14.5.3.7.42/14-102
0x2_472C
TFRG—Transmit fragments frame counter
R/W
0x0000_0000
14.5.3.7.43/14-102
eTSECn Counter Control and TOE Statistics Registers
0x2_4730
CAR1—Carry register one register4
R
0x0000_0000
14.5.3.7.44/14-103
0x2_4734
CAR2—Carry register two register
4
R
0x0000_0000
14.5.3.7.45/14-104
0x2_4738
CAM1—Carry register one mask register
R/W
0xFE03_FFFF
14.5.3.7.46/14-105
0x2_473C
CAM2—Carry register two mask register
R/W
0x000F_FFFD
14.5.3.7.47/14-106
0x2_4740
RREJ*—Receive filer rejected packet counter
R/W
0x0000_0000
14.5.3.7.48/14-108
0x2_4744–
0x2_47FC
Reserved
—
—
—
14.5.3.8.1/14-108
Hash Function Registers
0x2_4800
IGADDR0—Individual/group address register 0
R/W
0x0000_0000
0x2_4804
IGADDR1—Individual/group address register 1
R/W
0x0000_0000
0x2_4808
IGADDR2—Individual/group address register 2
R/W
0x0000_0000
0x2_480C
IGADDR3—Individual/group address register 3
R/W
0x0000_0000
0x2_4810
IGADDR4—Individual/group address register 4
R/W
0x0000_0000
0x2_4814
IGADDR5—Individual/group address register 5
R/W
0x0000_0000
0x2_4818
IGADDR6—Individual/group address register 6
R/W
0x0000_0000
0x2_481C
IGADDR7—Individual/group address register 7
R/W
0x0000_0000
0x2_4820–
0x2_487C
Reserved
—
—
0x2_4880
GADDR0—Group address register 0
R/W
0x0000_0000
0x2_4884
GADDR1—Group address register 1
R/W
0x0000_0000
0x2_4888
GADDR2—Group address register 2
R/W
0x0000_0000
0x2_488C
GADDR3—Group address register 3
R/W
0x0000_0000
0x2_4890
GADDR4—Group address register 4
R/W
0x0000_0000
0x2_4894
GADDR5—Group address register 5
R/W
0x0000_0000
0x2_4898
GADDR6—Group address register 6
R/W
0x0000_0000
0x2_489C
GADDR7—Group address register 7
R/W
0x0000_0000
—
14.5.3.8.2/14-109
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-38
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
0x2_48A0–
0x2_49FC
Register
Access
Reset
—
—
R/W
0x0000_00C0
14.5.3.9.1/14-110
—
—
—
—
—
—
Reserved
Section/Page
—
eTSECn FIFO Control Registers
0x2_4A00
FIFOCFG*—FIFO interface configuration register
0x2_4A04–
0x2_4AFC
Reserved
eTSECn DMA Attribute Registers
0x2_4B00–
0x2_4BF4
Reserved
0x2_4BF8
ATTR—Attribute register
R/W
0x0000_0000
14.5.3.10.1/14-111
0x2_4BFC
ATTRELI—Attribute extract length and extract index register
R/W
0x0000_0000
14.5.3.10.2/14-112
—
—
—
eTSECn Future Expansion Space
0x2_4C00–
0x2_4FFF
Reserved
Other eTSECs
5
0x2_5000–
0x2_5FFF
eTSEC2 REGISTERS
0x2_6000–
0x2_6FFF
eTSEC3 REGISTERS 6
0x2_7000–
0x2_7FFF
eTSEC4 REGISTERS 7
Integrated Security Engine
Controller
0x3_1008
IMR—Interrupt mask register
R/W
0x0000_0000_
0000_0000
19.6.5.2/19-110
0x3_1010
ISR—Interrupt status register
R
0x0000_0000_
0000_0000
19.6.5.3/19-111
0x3_1018
ICR—Interrupt clear register
W
0x0000_0000_
0000_0000
19.6.5.4/19-112
0x3_1020
ID—Identification register
R
0x0030_0000_
0010_0000
19.6.5.5/19-113
0x3_1BF8
IP block revision
R
0x0030_0000_
0010_0000
19.6.5.6/19-113
0x3_1028
EUASR—EU assignment status register
R
0xF0F0_F0F0_
00FF_F0F0
19.6.5.1/19-109
0x3_1030
MCR—Master control register
R/W
0x0000_0000_
0000_0000
19.6.5.7/19-114
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-39
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
R/W
0x0000_0000_
0000_0000
19.5.1.1/19-92
Channel 1
0x3_1108
CCCR1—Crypto-channel 1 configuration register
0x3_1110
CCPSR1—Crypto-channel 1 pointer status register
R
0x0000_0000_
0000_0007
19.5.1.2/19-95
0x3_1140
CDPR1—Crypto-channel 1 current descriptor pointer register
R
0x0000_0000_
0000_0000
19.5.1.3/19-100
0x3_1148
FF1—Crypto-channel 1 fetch FIFO address register
W
0x0000_0000_
0000_0000
19.5.1.4/19-101
0x3_1180–
0x3_11BF
DB1—Crypto-channel 1 descriptor buffers [0–7]
R
0x0000_0000_
0000_0000
19.5.1.5/19-102
0x3_11C0–
0x3_11DF
Gather link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
0x3_11E0–
0x3_11FF
Scatter link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
R/W
0x0000_0000_
0000_0000
19.5.1.1/19-92
Channel 2
0x3_1208
CCCR2—Crypto-channel 2 configuration register
0x3_1210
CCPSR2—Crypto-channel 2 pointer status register
R
0x0000_0000_
0000_0007
19.5.1.2/19-95
0x3_1240
CDPR2—Crypto-channel 2 current descriptor pointer register
R
0x0000_0000_
0000_0000
19.5.1.3/19-100
0x3_1248
FF2—Crypto-channel 2 fetch FIFO address register
W
0x0000_0000_
0000_0000
19.5.1.4/19-101
0x3_1280–
0x3_12BF
DB2—Crypto-channel 2 descriptor buffers [0–7]
R
0x0000_0000_
0000_0000
19.5.1.5/19-102
0x3_12C0–
0x3_12DF
Gather link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
0x3_12E0–
0x3_12FF
Scatter link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
R/W
0x0000_0000_
0000_0000
19.5.1.1/19-92
Channel 3
0x3_1308
CCCR3—Crypto-channel3 configuration register
0x3_1310
CCPSR3—Crypto-channel3 pointer status register
R
0x0000_0000_
0000_0007
19.5.1.2/19-95
0x3_1340
CDPR3—Crypto-channel 3 current descriptor pointer register
R
0x0000_0000_
0000_0000
19.5.1.3/19-100
0x3_1348
FF3—Crypto-channel 3 fetch FIFO address register
W
0x0000_0000_
0000_0000
19.5.1.4/19-101
0x3_1380–
0x3_13BF
DB3—Crypto-channel 3 descriptor buffers [0–7]
R
0x0000_0000_
0000_0000
19.5.1.5/19-102
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x3_13C0–
0x3_13DF
Gather link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
0x3_13E0–
0x3_13FF
Scatter link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
R/W
0x0000_0000_
0000_0000
19.5.1.1/19-92
Channel 4
0x3_1408
CCCR4—Crypto-channel 4 configuration register
0x3_1410
CCPSR4—Crypto-channel 4 pointer status register
R
0x0000_0000_
0000_0007
19.5.1.2/19-95
0x3_1440
CDPR4—Crypto-channel 4 current descriptor pointer register
R
0x0000_0000_
0000_0000
19.5.1.3/19-100
0x3_1448
FF4—Crypto-channel 4 fetch FIFO address register
W
0x0000_0000_
0000_0000
19.5.1.4/19-101
0x3_1480–
0x3_14BF
DB4—Crypto-channel 4 descriptor buffers [0–7]
R
0x0000_0000_
0000_0000
19.5.1.5/19-102
0x3_14C0–
0x3_14DF
Gather link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
0x3_14E0–
0x3_14FF
Scatter link tables
W
0x0000_0000_
0000_0000
19.5.1.6/19-102
Data Encryption Standard Execution Unit (DEU)
0x3_2000
DEUMR—DEU mode register
R/W
0x0000_0000_
0000_0000
19.4.2.1/19-34
0x3_2008
DEUKSR—DEU key size register
R/W
0x0000_0000_
0000_0000
19.4.2.2/19-35
0x3_2010
DEUDSR—DEU data size register
R/W
0x0000_0000_
0000_0000
19.4.2.3/19-35
0x3_2018
DEURCR—DEU reset control register
R/W
0x0000_0000_
0000_0000
19.4.2.4/19-36
0x3_2028
DEUSR—DEU status register
R
0x0000_0000_
0000_0000
19.4.2.5/19-36
0x3_2030
DEUISR—DEU interrupt status register
R
0x0000_0000_
0000_0000
19.4.2.6/19-37
0x3_2038
DEUICR—DEU interrupt control register
R/W
0x0000_0000_
0000_3000
19.4.2.7/19-39
0x3_2050
DEUEUG—DEU EU go register
W
0x0000_0000_
0000_0000
19.4.2.8/19-41
0x3_2100
DEUIV—DEU initialization vector register
R/W
0x0000_0000_
0000_0000
19.4.2.9/19-41
0x3_2400
DEUK1—DEU key register 1
W
—
19.4.2.10/19-41
0x3_2408
DEUK2—DEU key register 2
W
—
19.4.2.10/19-41
0x3_2410
DEUK3—DEU key register 3
W
—
19.4.2.10/19-41
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-41
Memory Map
Table 2-11. Memory Map (continued)
Offset
0x3_2800–
0x3_2FFF
Register
DEU FIFO
Access
Reset
Section/Page
R/W
0x0000_0000_
0000_0000
19.4.2.11/19-41
Advanced Encryption Standard Execution Unit (AESU)
0x3_4000
AESUMR—AESU mode register
R/W
0x0000_0000_
0000_0000
19.4.6.1/19-67
0x3_4008
AESUKSR—AESU key size register
R/W
0x0000_0000_
0000_0000
19.4.6.2/19-69
0x3_4010
AESUDSR—AESU data size register
R/W
0x0000_0000_
0000_0000
19.4.6.3/19-69
0x3_4018
AESURCR—AESU reset control register
R/W
0x0000_0000_
0000_0000
19.4.6.4/19-70
0x3_4028
AESUSR—AESU status register
R
0x0000_0000_
0000_0000
19.4.6.5/19-71
0x3_4030
AESUISR—AESU interrupt status register
R
0x0000_0000_
0000_0000
19.4.6.6/19-72
0x3_4038
AESUICR—AESU interrupt control register
R/W
0x0000_0000_
0000_1000
19.4.6.7/19-73
0x3_4050
AESUEUG—AESU EU go register
W
0x0000_0000_
0000_0000
19.4.6.8/19-74
0x3_4100–
0x3_4108
AESU context memory registers
R/W
0x0000_0000_
0000_0000
19.4.6.9/19-75
0x3_4400–
0x3_4408
AESU key memory
R/W
0x0000_0000_
0000_0000
19.4.6.9.5/19-79
0x3_4800–
0x3_4FFF
AESU FIFO
R/W
0x0000_0000_
0000_0000
19.4.6.9.6/19-79
Message Digest Execution Unit (MDEU)
0x3_6000
MDEUMR—MDEU mode register
R/W
0x0000_0000_
0000_0000
19.4.4.1/19-50
0x3_6008
MDEUKSR—MDEU key size register
R/W
0x0000_0000_
0000_0000
19.4.4.3/19-54
0x3_6010
MDEUDSR—MDEU data size register
R/W
0x0000_0000_
0000_0000
19.4.4.4/19-54
0x3_6018
MDEURCR—MDEU reset control register
R/W
0x0000_0000_
0000_0000
19.4.4.5/19-55
0x3_6028
MDEUSR—MDEU status register
R
0x0000_0000_
0000_0000
19.4.4.6/19-55
0x3_6030
MDEUISR—MDEU interrupt status register
R
0x0000_0000_
0000_0000
19.4.4.7/19-57
0x3_6038
MDEUICR—MDEU interrupt control register
R/W
0x0000_0000_
0000_1000
19.4.4.8/19-58
0x3_6040
MDEUICVSR—MDEU ICV size register
W
0x0000_0000_
0000_0000
19.4.4.9/19-59
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-42
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
W
0x0000_0000_
0000_0000
19.4.4.10/19-59
R/W
0x0000_0000_
0000_0000
19.4.4.11/19-60
0x3_6050
MDEUEUG—MDEU EU go register
0x3_6100–
0x3_6120
MDEU context memory registers
0x3_6400–
0x3_647F
MDEU key memory
W
0x0000_0000_
0000_0000
19.4.4.12/19-61
0x3_6800–
0x3_6FFF
MDEU FIFO
W
0x0000_0000_
0000_0000
19.4.4.13/19-62
ARC Four Execution Unit (AFEU)
0x3_8000
AFEUMR—AFEU mode register
R/W
0x0000_0000_
0000_0000
19.4.3.1/19-42
0x3_8008
AFEUKSR—AFEU key size register
R/W
0x0000_0000_
0000_0000
19.4.3.3/19-43
0x3_8010
AFEUDSR—AFEU data size register
R/W
0x0000_0000_
0000_0000
19.4.3.4/19-44
0x3_8018
AFEURCR—AFEU reset control register
R/W
0x0000_0000_
0000_0000
19.4.3.5/19-44
0x3_8028
AFEUSR—AFEU status register
R
0x0000_0000_
0000_0000
19.4.3.6/19-45
0x3_8030
AFEUISR—AFEU interrupt status register
R
0x0000_0000_
0000_0000
19.4.3.7/19-46
0x3_8038
AFEUICR—AFEU interrupt control register
R/W
0x0000_0000_
0000_1000
19.4.3.8/19-48
0x3_8050
AFEUEUG—AFEU EU go register
W
0x0000_0000_
0000_0000
19.4.3.9/19-49
0x3_8100–
0x3_81FF
AFEU context memory registers
R/W
0x0000_0000_
0000_0000
19.4.3.10.1/19-49
0x3_8200
AFEU context memory pointers
R/W
0x0000_0000_
0000_0000
19.4.3.10.2/19-50
0x3_8400
AFEUK1—AFEU key register 0
W
—
19.4.3.11/19-50
0x3_8480
AFEUK2—AFEU key register 1
W
—
19.4.3.11/19-50
0x3_8800–
0x3_8FFF
(3_8E00)
AFEU FIFO
R/W
0x0000_0000_
0000_0000
19.4.3.12/19-50
Random Number Generator (RNG)
0x3_A000
RNGMR—RNG mode register
R/W
0x0000_0000_
0000_0000
19.4.5.1/19-63
0x3_A010
RNGDSR—RNG data size register
R/W
0x0000_0000_
0000_0000
19.4.5.2/19-63
0x3_A018
RNGRCR—RNG reset control register
R/W
0x0000_0000_
0000_0000
19.4.5.3/19-63
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-43
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x3_A028
RNGSR—RNG status register
R
0x0000_0000_
0000_0000
19.4.5.4/19-64
0x3_A030
RNGISR—RNG interrupt status register
R
0x0000_0000_
0000_0000
19.4.5.5/19-65
0x3_A038
RNGICR—RNG interrupt control register
R/W
0x0000_0000_
0000_1000
19.4.5.6/19-66
0x3_A050
RNGEUG—RNG EU go register
W
0x0000_0000_
0000_0000
19.4.5.7/19-67
0x3_A800–
0x3_AFFF
RNG FIFO
R
0x0000_0000_
0000_0000
19.4.5.8/19-67
Public Key Execution Units (PKEU)
0x3_C000
PKEUMR—PKEU mode register
R/W
0x0000_0000_
0000_0000
19.4.1.1/19-26
0x3_C008
PKEUKSR—PKEU key size register
R/W
0x0000_0000_
0000_0000
19.4.1.2/19-27
0x3_C010
PKEUDSR—PKEU data size register
R/W
0x0000_0000_
0000_0000
19.4.1.4/19-28
0x3_C018
PKEURCR—PKEU reset control register
R/W
0x0000_0000_
0000_0000
19.4.1.5/19-29
0x3_C028
PKEUSR—PKEU status register
R
0x0000_0000_
0000_0000
19.4.1.6/19-29
0x3_C030
PKEUISR—PKEU interrupt status register
R
0x0000_0000_
0000_0000
19.4.1.7/19-31
0x3_C038
PKEUICR—PKEU interrupt control register
R/W
0x0000_0000_
0000_1000
19.4.1.8/19-32
0x3_C040
PKEUABS—PKEU AB size register
R/W
0x0000_0000_
0000_0000
19.4.1.3/19-28
0x3_C050
PKEUEUG—PKEU EU go register
W
0x0000_0000_
0000_0000
19.4.1.9/19-33
0x3_C200–
0x3_C23F
PKEU parameter memory A0
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C240–
0x3_C27F
PKEU parameter memory A1
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C280–
0x3_C2BF
PKEU parameter memory A2
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C2C0–
0x3_C2FF
PKEU parameter memory A3
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C300–
0x3_C33F
PKEU parameter memory B0
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C340–
0x3_C37F
PKEU parameter memory B1
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C380–
0x3_C3BF
PKEU parameter memory B2
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-44
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x3_C3C0–
0x3_C3FF
PKEU parameter memory B3
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C400–
0x3_C4FF
PKEU parameter memory E
W
0x0000_0000_
0000_0000
19.4.1.10/19-33
0x3_C800–
0x3_C8FF
PKEU parameter memory N
R/W
0x0000_0000_
0000_0000
19.4.1.10/19-33
Kasumi Execution Unit (KEU)
0x3_E000
KEUMR—KEU mode register
R/W
0x0000_0000_
0000_0000
19.4.7.1/19-80
0x3_E008
KEUKSR—KEU key size register
R/W
0x0000_0000_
0000_0000
19.4.7.2/19-81
0x3_E010
KEUDSR—KEU data size register
R/W
0x0000_0000_
0000_0000
19.4.7.3/19-81
0x3_E018
KEURCR—KEU reset control register
R/W
0x0000_0000_
0000_0000
19.4.7.4/19-82
0x3_E028
KEUSR—KEU status register
R
0x0000_0000_
0000_0000
19.4.7.5/19-83
0x3_E030
KEUISR—KEU interrupt status register
R/W
0x0000_0000_
0000_0000
19.4.7.6/19-84
0x3_E038
KEUICR—KEU interrupt control register
R/W
0x0000_0000_
0000_1000
19.4.7.7/19-85
0x3_E048
KEUDOR—KEU data out register (F9 MAC)
R
0x0000_0000_
0000_0000
19.4.7.8/19-87
0x3_E050
KEUEUG—KEU EU go register
W
0x0000_0000_
0000_0000
19.4.7.9/19-87
0x3_E100
KEUIV1—KEU initialization vector 1 register
R/W
0x0000_0000_
0000_0000
19.4.7.10/19-88
0x3_E108
KEUICV—KEU ICV_In register
R/W
0x0000_0000_
0000_0000
19.4.7.11/19-88
0x3_E110
KEUIV2—KEU initialization vector 2 register (Fresh)
R/W
0x0000_0000_
0000_0000
19.4.7.12/19-89
0x3_E118
KEUC1—KEU context_1 register
R/W
0x0000_0000_
0000_0000
19.4.7.13/19-89
0x3_E120
KEUC2—KEU context_2 register
R/W
0x0000_0000_
0000_0000
19.4.7.13/19-89
0x3_E128
KEUC3—KEU context_3 register
R/W
0x0000_0000_
0000_0000
19.4.7.13/19-89
0x3_E130
KEUC4—KEU context_4 register
R/W
0x0000_0000_
0000_0000
19.4.7.13/19-89
0x3_E138
KEUC5—KEU context_5 register
R/W
0x0000_0000_
0000_0000
19.4.7.13/19-89
0x3_E140
KEUC6—KEU context_6 register
R/W
0x0000_0000_
0000_0000
19.4.7.13/19-89
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-45
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x3_E400
KEUKD1—KEU key data register_1 (CK-high)
R/W
0x0000_0000_
0000_0000
19.4.7.14/19-89
0x3_E408
KEUKD2—KEU key data register_2 (CK-low)
R/W
0x0000_0000_
0000_0000
19.4.7.14/19-89
0x3_E410
KEUKD3—KEU key data register_3 (IK-high)
R/W
0x0000_0000_
0000_0000
19.4.7.15/19-90
0x3_E418
KEUKD4—KEU key data register_4 (IK-low)
R/W
0x0000_0000_
0000_0000
19.4.7.15/19-90
0x3_E800–
0x3_EFFF
KEUFIFO
R/W
0x0000_0000_
0000_0000
19.4.7.16/19-90
Programmable Interrupt Controller Registers
Global Registers
0x4_0000
BRR1—Block Revision register 1
R
0x0040_0200
10.3.1.1/10-16
0x4_0010
BRR2—Block Revision register 2
R
0x0000_0001
10.3.1.2/10-17
0x4_0020–
0x4_0030
Reserved
—
—
—
0x4_0040
IPIDR0—Interprocessor interrupt 0 (IPI 0) dispatch register
W
0x0000_0000
10.3.8.1/10-43
0x4_0050
IPIDR1—Interprocessor interrupt 1 (IPI 1) dispatch register
0x4_0060
IPIDR2—Interprocessor interrupt 2 (IPI 2) dispatch register
0x4_0070
IPIDR3—Interprocessor interrupt 3 (IPI 3) dispatch register
0x4_0080
CTPR—Current task priority register
R/W
0x0000_000F
10.3.8.2/10-44
0x4_0090
WHOAMI—Who am I register
R
0x0000_0000
10.3.8.3/10-45
0x4_00A0
IACK—Interrupt acknowledge register
R
0x0000_0000
10.3.8.4/10-45
0x4_00B0
EOI—End of interrupt register
W
0x0000_0000
10.3.8.5/10-46
Reserved
—
—
—
0x4_1000
FRR—Feature reporting register
R
0x004F_0002
10.3.1.3/10-17
0x4_1010
Reserved
—
—
—
0x4_1020
GCR—Global configuration register
R/W
0x0000_0000
10.3.1.4/10-18
0x4_1030
Reserved
—
—
—
0x4_1040–
0x4_1070
Vendor reserved
—
—
—
0x4_1080
VIR—Vendor identification register
R
0x0000_0000
10.3.1.5/10-19
0x4_1090
PIR—Processor initialization register
R/W
0x0000_0000
10.3.1.6/10-19
0x4_10A0
IPIVPR0—IPI 0 vector/priority register
R/W
0x8000_0000
10.3.1.7/10-20
0x4_10B0
IPIVPR1—IPI 1 vector/priority register
0x4_10C0
IPIVPR2—IPI 2 vector/priority register
0x4_10D0
IPIVPR3—IPI 3 vector/priority register
0x4_00C0–
0x4_0FF0
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-46
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
0x4_10E0
Register
SVR—Spurious vector register
Access
Reset
Section/Page
R/W
0x0000_FFFF
10.3.1.8/10-21
R/W
0x0000_0000
10.3.2.1/10-21
R
0x0000_0000
10.3.2.2/10-22
Global Timer Registers
0x4_10F0
TFRR—Timer frequency reporting register
0x4_1100
GTCCR0—Global timer 0 current count register
0x4_1110
GTBCR0—Global timer 0 base count register
R/W
0x8000_0000
10.3.2.3/10-22
0x4_1120
GTVPR0—Global timer 0 vector/priority register
R/W
0x8000_0000
10.3.2.4/10-23
0x4_1130
GTDR0—Global timer 0 destination register
R/W
0x0000_0001
10.3.2.5/10-24
0x4_1140
GTCCR1—Global timer 1 current count register
R
0x0000_0000
10.3.2.2/10-22
0x4_1150
GTBCR1—Global timer 1 base count register
R/W
0x8000_0000
10.3.2.3/10-22
0x4_1160
GTVPR1—Global timer 1 vector/priority register
R/W
0x8000_0000
10.3.2.4/10-23
0x4_1170
GTDR1—Global timer 1 destination register
R/W
0x0000_0001
10.3.2.5/10-24
0x4_1180
GTCCR2—Global timer 2 current count register
R
0x0000_0000
10.3.2.2/10-22
0x4_1190
GTBCR2—Global timer 2 base count register
R/W
0x8000_0000
10.3.2.3/10-22
0x4_11A0
GTVPR2—Global timer 2 vector/priority register
R/W
0x8000_0000
10.3.2.4/10-23
0x4_11B0
GTDR2—Global timer 2 destination register
R/W
0x0000_0001
10.3.2.5/10-24
0x4_11C0
GTCCR3—Global timer 3 current count register
R
0x0000_0000
10.3.2.2/10-22
0x4_11D0
GTBCR3—Global timer 3 base count register
R/W
0x8000_0000
10.3.2.3/10-22
0x4_11E0
GTVPR3—Global timer 3 vector/priority register
R/W
0x8000_0000
10.3.2.4/10-23
0x4_11F0
GTDR3—Global timer 3 destination register
R/W
0x0000_0001
10.3.2.5/10-24
0x4_1200–
0x4_12F0
Reserved
—
—
—
0x4_1300
TCR—Timer control register
R/W
0x0000_0000
10.3.2.6/10-24
External, IRQ_OUT, and Critical Interrupt Summary Registers
0x4_1308
ERQSR—External interrupt summary register
R
0x0000_0000
10.3.3.1/10-26
0x4_1310
IRQSR0—IRQ_OUT summary register 0
R
0x0000_0000
10.3.3.2/10-27
0x4_1320
IRQSR1—IRQ_OUT summary register 1
R
0x0000_0000
10.3.3.3/10-28
0x4_1324
IRQSR2—IRQ_OUT summary register 2
R
0x0000_0000
10.3.3.4/10-28
0x4_1330
CISR0—Critical Interrupt summary register 0
R
0x0000_0000
10.3.3.5/10-29
0x4_1340
CISR1—Critical Interrupt summary register 1
R
0x0000_0000
10.3.3.6/10-29
0x4_1344
CISR2—Critical Interrupt summary register 2
R
0x0000_0000
10.3.3.7/10-30
Performance Monitor Mask Registers
0x4_1350
PM0MR0—Performance monitor 0 mask register 0
R/W
0x00FF_FFFF
10.3.4.1/10-30
0x4_1360
PM0MR1—Performance monitor 0 mask register 1
R/W
0xFFFF_FFFF
10.3.4.2/10-31
0x4_1364
PM0MR2—Performance monitor 0 mask register 2
R/W
0xFFFF_FFFF
10.3.4.3/10-31
0x4_1370
PM1MR0—Performance monitor 1 mask register 0
R/W
0x00FF_FFFF
10.3.4.1/10-30
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-47
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x4_1380
PM1MR1—Performance monitor 1 mask register 1
R/W
0xFFFF_FFFF
10.3.4.2/10-31
0x4_1384
PM1MR2—Performance monitor 1 mask register 2
R/W
0xFFFF_FFFF
10.3.4.3/10-31
0x4_1390
PM2MR0—Performance monitor 2 mask register 0
R/W
0x00FF_FFFF
10.3.4.1/10-30
0x4_13A0
PM2MR1—Performance monitor 2 mask register 1
R/W
0xFFFF_FFFF
10.3.4.2/10-31
0x4_13A4
PM2MR2—Performance monitor 2 mask register 2
R/W
0xFFFF_FFFF
10.3.4.3/10-31
0x4_13B0
PM3MR0—Performance monitor 3 mask register 0
R/W
0x00FF_FFFF
10.3.4.1/10-30
0x4_13C0
PM3MR1—Performance monitor 3 mask register 1
R/W
0xFFFF_FFFF
10.3.4.2/10-31
0x4_13C4
PM3MR2—Performance monitor 3 mask register 2
R/W
0xFFFF_FFFF
10.3.4.3/10-31
0x4_13D0–
0x4_13F0
Reserved
—
—
—
R/W
0x0000_0000
10.3.5.1/10-32
—
—
—
Message Registers
0x4_1400
MSGR0—Message register 0
0x4_1410
MSGR1—Message register 1
0x4_1420
MSGR2—Message register 2
0x4_1430
MSGR3—Message register 3
0x4_1440–
0x4_14F0
Reserved
0x4_1500
MER—Message enable register
R/W
0x0000_0000
10.3.5.2/10-32
0x4_1510
MSR—Message status register
R/W
0x0000_0000
10.3.5.3/10-33
0x4_1520–
0x4_15F0
Reserved
—
—
—
0x4_1600
MSIR0—Shared interrupt register 0
Special
0x0000_0000
10.3.6.1/10-34
0x4_1610
MSIR1—Shared interrupt register 1
Special
0x0000_0000
10.3.6.1/10-34
0x4_1620
MSIR2—Shared interrupt register 2
Special
0x0000_0000
10.3.6.1/10-34
0x4_1630
MSIR3—Shared interrupt register 3
Special
0x0000_0000
10.3.6.1/10-34
0x4_1640
MSIR4—Shared interrupt register 4
Special
0x0000_0000
10.3.6.1/10-34
0x4_1650
MSIR5—Shared interrupt register 5
Special
0x0000_0000
10.3.6.1/10-34
0x4_1660
MSIR6—Shared interrupt register 6
Special
0x0000_0000
10.3.6.1/10-34
0x4_1670
MSIR7—Shared interrupt register 7
Special
0x0000_0000
10.3.6.1/10-34
0x4_1680–
0x4_1700
Reserved
—
—
—
0x4_1720
MSISR—Shared message signaled interrupt status register
R
0x0000_0000
10.3.6.2/10-34
0x4_1740
MSIIR—Shared message signaled interrupt index register
W
0x0000_0000
10.3.6.3/10-35
0x4_1750–
0x4_FFFF
Reserved
—
—
—
PIC Register Address Map—Interrupt Source Configuration Registers
0x5_0000
EIVPR0—External interrupt 0 (IRQ0) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-48
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x5_0010
EIDR0—External interrupt 0 (IRQ0) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0020
EIVPR1—External interrupt 1 (IRQ1) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0030
EIDR1—External interrupt 1 (IRQ1) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0040
EIVPR2—External interrupt 2 (IRQ2) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0050
EIDR2—External interrupt 2 (IRQ2) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0060
EIVPR3—External interrupt 3 (IRQ3) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0070
EIDR3—External interrupt 3 (IRQ3) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0080
EIVPR4—External interrupt 4 (IRQ4) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0090
EIDR4—External interrupt 4 (IRQ4) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_00A0
EIVPR5—External interrupt 5 (IRQ5) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_00B0
EIDR5—External interrupt 5 (IRQ5) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_00C0
EIVPR6—External interrupt 6 (IRQ6) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_00D0
EIDR6—External interrupt 6 (IRQ6) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_00E0
EIVPR7—External interrupt 7 (IRQ7) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_00F0
EIDR7—External interrupt 7 (IRQ7) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0100
EIVPR8—External interrupt 8 (IRQ8) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0110
EIDR8—External interrupt 8 (IRQ8) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0120
EIVPR9—External interrupt 9 (IRQ9) vector/priority register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0130
EIDR9—External interrupt 9 (IRQ9) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0140
EIVPR10—External interrupt 10 (IRQ10) vector/priority
register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0150
EIDR10—External interrupt 10 (IRQ10) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0160
EIVPR11—External interrupt 11 (IRQ11) vector/priority
register
Mixed
0x8000_0000
10.3.7.1/10-37
0x5_0170
EIDR11—External interrupt 11 (IRQ11) destination register
Mixed
0x0000_0001
10.3.7.2/10-38
0x5_0180–
0x5_01F0
Reserved
—
—
—
0x5_0200
IIVPR0—Internal interrupt 0 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0210
IIDR0—Internal interrupt 0 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0220
IIVPR1—Internal interrupt 1 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0230
IIDR1—Internal interrupt 1 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0240
IIVPR2—Internal interrupt 2 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0250
IIDR2—Internal interrupt 2 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0260
IIVPR3—Internal interrupt 3 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0270
IIDR3—Internal interrupt 3 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0280
IIVPR4—Internal interrupt 4 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0290
IIDR4—Internal interrupt 4 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-49
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x5_02A0
IIVPR5—Internal interrupt 5 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_02B0
IIDR5—Internal interrupt 5 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_02C0
IIVPR6—Internal interrupt 6 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_02D0
IIDR6—Internal interrupt 6 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_02E0
IIVPR7—Internal interrupt 7 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_02F0
IIDR7—Internal interrupt 7 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0300
IIVPR8—Internal interrupt 8 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0310
IIDR8—Internal interrupt 8 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0320
IIVPR9—Internal interrupt 9 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0330
IIDR9—Internal interrupt 9 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0340
IIVPR10—Internal interrupt 10 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0350
IIDR10—Internal interrupt 10 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0360
IIVPR11—Internal interrupt 11 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0370
IIDR11—Internal interrupt 11 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0380
IIVPR12—Internal interrupt 12 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0390
IIDR12—Internal interrupt 12 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_03A0
IIVPR13—Internal interrupt 13 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_03B0
IIDR13—Internal interrupt 13 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_03C0
IIVPR14—Internal interrupt 14 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_03D0
IIDR14—Internal interrupt 14 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_03E0
IIVPR15—Internal interrupt 15 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_03F0
IIDR15—Internal interrupt 15 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0400
IIVPR16—Internal interrupt 16 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0410
IIDR16—Internal interrupt 16 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0420
IIVPR17—Internal interrupt 17 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0430
IIDR17—Internal interrupt 17 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0440
IIVPR18—Internal interrupt 18 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0450
IIDR18—Internal interrupt 18 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0460
IIVPR19—Internal interrupt 19 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0470
IIDR19—Internal interrupt 19 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0480
IIVPR20—Internal interrupt 20 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0490
IIDR20—Internal interrupt 20 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_04A0
IIVPR21—Internal interrupt 21 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_04B0
IIDR21—Internal interrupt 21 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_04C0
IIVPR22—Internal interrupt 22 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_04D0
IIDR22—Internal interrupt 22 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-50
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x5_04E0
IIVPR23—Internal interrupt 23 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_04F0
IIDR23—Internal interrupt 23 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0500
IIVPR24—Internal interrupt 24 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0510
IIDR24—Internal interrupt 24 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0520
IIVPR25—Internal interrupt 25 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0530
IIDR25—Internal interrupt 25 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0540
IIVPR26—Internal interrupt 26 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0550
IIDR26—Internal interrupt 26 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0560
IIVPR27—Internal interrupt 27 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0570
IIDR27—Internal interrupt 27 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0580
IIVPR28—Internal interrupt 28 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0590
IIDR28—Internal interrupt 28 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_05A0
IIVPR29—Internal interrupt 29 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_05B0
IIDR29—Internal interrupt 29 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_05C0
IIVPR30—Internal interrupt 30 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_05D0
IIDR30—Internal interrupt 30 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_05E0
IIVPR31—Internal interrupt 31 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_05F0
IIDR31—Internal interrupt 31 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0600
IIVPR32—Internal interrupt 32 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0610
IIDR32—Internal interrupt 32 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0620
IIVPR33—Internal interrupt 33 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0630
IIDR33—Internal interrupt 33 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0640
IIVPR34—Internal interrupt 34 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0650
IIDR34—Internal interrupt 34 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0660
IIVPR35—Internal interrupt 35 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0670
IIDR35—Internal interrupt 35 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0680
IIVPR36—Internal interrupt 36 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0690
IIDR36—Internal interrupt 36 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_06A0
IIVPR37—Internal interrupt 37 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_06B0
IIDR37—Internal interrupt 37 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_06C0
IIVPR38—Internal interrupt 38 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_06D0
IIDR38—Internal interrupt 38 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_06E0
IIVPR39—Internal interrupt 39 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_06F0
IIDR39—Internal interrupt 39 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0700
IIVPR40—Internal interrupt 40 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0710
IIDR40—Internal interrupt 40 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-51
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x5_0720
IIVPR41—Internal interrupt 41 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0730
IIDR41—Internal interrupt 41 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0740
IIVPR42—Internal interrupt 42 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0750
IIDR42—Internal interrupt 42 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0760
IIVPR43—Internal interrupt 43 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0770
IIDR43—Internal interrupt 43 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0780
IIVPR44—Internal interrupt 44 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_0790
IIDR44—Internal interrupt 44 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_07A0
IIVPR45—Internal interrupt 45 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_07B0
IIDR45—Internal interrupt 45 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_07C0
IIVPR46—Internal interrupt 46 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_07D0
IIDR46—Internal interrupt 46 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_07E0
IIVPR47—Internal interrupt 47 vector/priority register
Mixed
0x8080_0000
10.3.7.3/10-38
0x5_07F0
IIDR47—Internal interrupt 47 destination register
Mixed
0x0000_0001
10.3.7.4/10-39
0x5_0800–
0x5_15F0
Reserved
—
—
—
0x5_1600
MIVPR0—Messaging interrupt 0 (MSG 0) vector/priority
register
Mixed
0x8000_0000
10.3.7.5/10-40
0x5_1610
MIDR0—Messaging interrupt 0 (MSG 0) destination register
Mixed
0x0000_0001
10.3.7.6/10-41
0x5_1620
MIVPR1—Messaging interrupt 1 (MSG 1) vector/priority
register
Mixed
0x8000_0000
10.3.7.5/10-40
0x5_1630
MIDR1—Messaging interrupt 1 (MSG 1) destination register
Mixed
0x0000_0001
10.3.7.6/10-41
0x5_1640
MIVPR2—Messaging interrupt 2 (MSG 2) vector/priority
register
Mixed
0x8000_0000
10.3.7.5/10-40
0x5_1650
MIDR2—Messaging interrupt 2 (MSG 2) destination register
Mixed
0x0000_0001
10.3.7.6/10-41
0x5_1660
MIVPR3—Messaging interrupt 3 (MSG 3) vector/priority
register
Mixed
0x8000_0000
10.3.7.5/10-40
0x5_1670
MIDR3—Messaging interrupt 3 (MSG 3) destination register
Mixed
0x0000_0001
10.3.7.6/10-41
0x5_1680–
0x5_1BF0
Reserved
—
—
—
0x5_1C00
Shared message signaled interrupt vector/priority register 0
(MSIVPR0)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1C10
Shared message signaled interrupt destination register 0
(MSIDR0)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1C20
Shared message signaled interrupt vector/priority register 1
(MSIVPR1)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1C30
Shared message signaled interrupt destination register 1
(MSIDR1)
Mixed
0x0000_0001
10.3.6.5/10-36
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Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0x5_1C40
Shared message signaled interrupt vector/priority register 2
(MSIVPR2)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1C50
Shared message signaled interrupt destination register 2
(MSIDR2)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1C60
Shared message signaled interrupt vector/priority register 3
(MSIVPR3)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1C70
Shared message signaled interrupt destination register 3
(MSIDR3)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1C80
Shared message signaled interrupt vector/priority register 4
(MSIVPR4)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1C90
Shared message signaled interrupt destination register 4
(MSIDR4)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1CA0
Shared message signaled interrupt vector/priority register 5
(MSIVPR5)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1CB0
Shared message signaled interrupt destination register 5
(MSIDR5)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1CC0
Shared message signaled interrupt vector/priority register 6
(MSIVPR6)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1CD0
Shared message signaled interrupt destination register 6
(MSIDR6)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1CE0
Shared message signaled interrupt vector/priority register 7
(MSIVPR7)
Mixed
0x1000_0000
10.3.6.4/10-35
0x5_1CF0
Shared message signaled interrupt destination register 7
(MSIDR7)
Mixed
0x0000_0001
10.3.6.5/10-36
0x5_1D00–
0x5_FFF0
Reserved
—
—
—
PIC Register Address Map—Per-CPU Registers
0x6_0000–
0x6_0030
Reserved
—
—
—
0x6_0040
IPIDR0—P0 IPI 0 dispatch register
W
0x0000_0000
10.3.8.1/10-43
0x6_0050
IPIDR1—P0 IPI 1 dispatch register
0x6_0060
IPIDR2—P0 IPI 2 dispatch register
0x6_0070
IPIDR3—P0 IPI 3 dispatch register
0x6_0080
CTPR—Current task priority register
R/W
0x0000_000F
10.3.8.2/10-44
0x6_0090
WHOAMI—Who am I register
R
0x0000_0000
10.3.8.3/10-45
0x6_00A0
IACK—Interrupt acknowledge register
R
0x0000_0000
10.3.8.4/10-45
0x6_00B0
EOI—End of interrupt register
W
0x0000_0000
10.3.8.5/10-46
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Freescale Semiconductor
2-53
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
RapidIO Registers8
RapidIO Architectural Registers
0xC_0000
Device identity capability register (DIDCAR)
R
0x0012_0002 =
MPC8548E
0x0013_0002 =
MPC8548
0x0014_0002 =
MPC8543E
0x0015_0002 =
MPC8543
0x0018_0002 =
MPC8547E
0x0019_0002 =
MPC8545E
0x001A_0002 =
MPC8545
17.6.1.1/17-11
0xC_0004
Device information capability register (DICAR)
R
0xnnnn_nnnn
17.6.1.2/17-11
0xC_0008
Assembly identity capability register (AIDCAR)
R/W
0xnnnn_nnnn
17.6.1.3/17-12
0xC_000C
Assembly information capability register (AICAR)
R/W
0x0000_0000
17.6.1.4/17-13
0xC_0010
Processing element features capability register (PEFCAR)
R
0xE0F8_00n9
17.6.1.5/17-13
0xC_0018
Source operations capability register (SOCAR)
R
0x0600_FCF0
17.6.1.6/17-14
0xC_001C
Destination operations capability register (DOCAR)
R
0x0000_FCF4
17.6.1.7/17-15
0xC_0040
Mailbox command and status register (MCSR)
R
0x2020_0000
17.6.1.8/17-17
0xC_0044
Port -Write and doorbell command and status register
(PWDCSR)
R
0x2000_0020
17.6.1.9/17-18
0xC_004C
Processing element logical layer control command and status
register (PELLCCSR)
R
0x0000_0001
17.6.1.10/17-19
0xC_005C
Local configuration space base address 1 command and status
register (LCSBA1CSR)
R/W
0x0000_0000
17.6.1.11/17-20
0xC_0060
Base device ID command and status register (BDIDCSR)
R/W
0x00nn_nnnn
17.6.1.12/17-21
0xC_0068
Host base device ID lock command and status register
(HBDIDLCSR)
Special
0x0000_FFFF
17.6.1.13/17-21
0xC_006C
Component tag command and status register (CTCSR)
R/W
0x0000_0000
17.6.1.14/17-22
R
0x0600_0001
17.6.2.1/17-22
Extended Features Space
1x/4x LP-Serial
0xC_0100
Port maintenance block header 0 (PMBH0)
0xC_0120
Port link time-out control command and status register
(PLTOCCSR)
R/W
0xFFFF_FF00
17.6.2.2/17-23
0xC_0124
Port response time-out control command and status register
(PRTOCCSR)
R/W
0xFFFF_FF00
17.6.2.3/17-23
0xC_013C
General control command and status register (GCCSR)
R/W
0xn000_0000
17.6.2.4/17-24
0xC_0140
Link maintenance request command and status register
(LMREQCSR)
R/W
0x0000_0000
17.6.2.5/17-25
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Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
R
0x0000_0000
17.6.2.6/17-25
0xC_0144
Link maintenance response command and status register
(LMRESPCSR)
0xC_0148
Local ackID status command and status register (LASCSR)
Mixed
0x0000_0000
17.6.2.7/17-26
0xC_0158
Error and status command and status register (ESCSR)
Mixed
0x0000_0001
17.6.2.8/17-27
0xC_015C
Control command and status register (CCSR)
R/W
0x5060_0001
17.6.2.9/17-28
R
0x0000_0007
17.6.3.1/17-30
0x0_00160–
0x0_053C
Reserved
Error Reporting, Logical
0xC_0600
Error reporting block header (ERBH)
0xC_0608
Logical/Transport layer error detect command and status
register (LTLEDCSR)
R/W
0x0000_0000
17.6.3.2/17-31
0xC_060C
Logical/Transport layer error enable command and status
register (LTLEECSR)
R/W
0x0000_0000
17.6.3.3/17-33
0xC_0614
Logical/Transport layer address capture command and status
register (LTLACCSR)
R/W
0x0000_0000
17.6.3.4/17-34
0xC_0618
Logical/Transport layer device ID capture command and status
register (LTLDIDCCSR)
R/W
0x0000_0000
17.6.3.5/17-35
0xC_061C
Logical/Transport layer control capture command and status
register (LTLCCCSR)
R/W
0x0000_0000
17.6.3.5/17-35
Error Reporting, Physical
0xC_0640
Error detect command and status register (EDCSR)
R/W
0x0000_0000
17.6.4.1/17-36
0xC_0644
Error rate enable command and status register (ERECSR)
R/W
0x0000_0000
17.6.4.2/17-37
0xC_0648
Error capture attributes command and status register
(ECACSR)
R/W
0x0000_0000
17.6.4.3/17-38
0xC_064C
Packet/control symbol error capture command and status
register 0 (PCSECCSR0)
R/W
0x0000_0000
17.6.4.4/17-39
0xC_0650
Packet error capture command and status register 1
(PECCSR1)
R/W
0x0000_0000
17.6.4.5/17-40
0xC_0654
Packet error capture command and status register 2
(PECCSR2)
R/W
0x0000_0000
17.6.4.6/17-40
0xC_0658
Packet error capture command and status register 3
(PECCSR3)
R/W
0x0000_0000
17.6.4.7/17-41
0xC_0668
Error rate command and status register (ERCSR)
R/W
0x8000_0000
17.6.4.8/17-41
0xC_066C
Error rate threshold command and status register (ERTCSR)
R/W
0xFFFF_0000
17.6.4.9/17-42
0xC_0680–
0xC_0E3C
Reserved
R/W
0x0000_0000
17.6.5.1/17-43
R
0x0000_0000
17.6.5.2/17-44
R/W
0x0000_00FF
17.6.5.3/17-44
Implementation Space
General
0xD_0004
Logical layer configuration register (LLCR)
0xD_0010
Error / port-write interrupt status register (EPWISR)
0xD_0020
Logical retry error threshold configuration register (LRETCR)
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-55
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0xD_0080
Physical retry error threshold configuration register (PRETCR)
R/W
0x0000_00FF
17.6.5.4/17-45
0xD_0100
Alternate device ID command and status register (ADIDCSR)
R/W
0x0000_0000
17.6.5.5/17-45
0xD_0120
Accept-all configuration register (AACR)
R/W
0xn000_000n
17.6.5.6/17-46
0xD_0124
Logical Outbound Packet time-to-live configuration register
(LOPTTLCR)
R/W
0x0000_0000
17.6.5.7/17-46
0xD_0130
Implementation error command and status register (IECSR)
w1c
0x0000_0000
17.6.5.8/17-47
0xD_0140
Physical configuration register (PCR)
R/W
0x0000_8010
17.6.5.9/17-48
0xD_0158
Serial link command and status register (SLCSR)
w1c
0x0000_0000
17.6.5.10/17-48
0xD_0160
Serial link error injection configuration register (SLEICR)
R/W
0x0000_0000
17.6.5.11/17-49
0xD_0180–
0xD_08FC
Reserved
Revision Control Register
0xD_0BF8
IP Block Revision Register 1 (IPBRR1)
R
0x01C0_0000
17.6.6.1/17-50
0xD_0BFC
IP Block Revision Register 2 (IPBRR2)
R
0x0000_0000
17.6.6.2/17-50
ATMU
0xD_0C00
RapidIO outbound window translation address register 0
(ROWTAR0)
R/W
0xFF80_0000
17.6.7.2/17-53
0xD_0C04
RapidIO outbound window translation extended address
register 0 (ROWTEAR0)
R/W
0x0000_003F
17.6.7.3/17-54
0xD_0C08–
0xD_0C0F
Reserved
0xD_0C10
RapidIO outbound window attributes register 0 (ROWAR0)
R/W
0x8004_4023
17.6.7.5/17-55
0xD_0C20
RapidIO outbound window translation address register 1
(ROWTAR1)
R/W
0x0000_0000
17.6.7.2/17-53
0xD_0C24
RapidIO outbound window translation extended address
register 1 (ROWTEAR1)
R/W
0x0000_0000
17.6.7.3/17-54
0xD_0C28
RapidIO outbound window base address register 1
(ROWBAR1)
R/W
0x0000_0000
17.6.7.4/17-55
0xD_0C30
RapidIO outbound window attributes register 1 (ROWAR1)
R/W
0x0004_4023
17.6.7.5/17-55
0xD_0C34
RapidIO outbound window segment 1 register 1 (ROWS1R1)
R/W
0x0044_0000
17.6.7.6/17-57
0xD_0C38
RapidIO outbound window segment 2 register 1 (ROWS2R1)
R/W
0x0044_0000
17.6.7.6/17-57
0xD_0C3C
RapidIO outbound window segment 3 register 1 (ROWS3R1)
R/W
0x0044_0000
17.6.7.6/17-57
0xD_0C40–
0xD_0CFC
RapidIO outbound window 2 through outbound window 7
0xD_0D00
RapidIO outbound window translation address register 8
(ROWTAR8)
R/W
0x0000_0000
17.6.7.2/17-53
0xD_0D04
RapidIO outbound window translation extended address
register 8 (ROWTEAR8)
R/W
0x0000_0000
17.6.7.3/17-54
0xD_0D08
RapidIO outbound window base address register 8
(ROWBAR8)
R/W
0x0000_0000
17.6.7.4/17-55
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Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0xD_0D10
RapidIO outbound window attributes register 8 (ROWAR8)
R/W
0x0004_4023
17.6.7.5/17-55
0xD_0D14
RapidIO outbound window segment 1 register 8 (ROWS1R8)
R/W
0x0044_0000
17.6.7.6/17-57
0xD_0D18
RapidIO outbound window segment 2 register 8 (ROWS2R8)
R/W
0x0044_0000
17.6.7.6/17-57
0xD_0D1C
RapidIO outbound window segment 3 register 8 (ROWS3R8)
R/W
0x0044_0000
17.6.7.6/17-57
0xD_0D60
RapidIO Inbound window translation address register 4
(RIWTAR4)
R/W
0x0000_0000
17.6.7.7/17-58
0xD_0D68
RapidIO Inbound window base address register 4 (RIWBAR4)
R/W
0x0000_0000
17.6.7.8/17-59
0xD_0D70
RapidIO inbound window attributes register 4 (RIWAR4)
R/W
0x0004_4021
17.6.7.9/17-60
0xD_0D80–
0xD_0DBC
RapidIO inbound window 3 through inbound window 2
0xD_0DC0
RapidIO inbound window translation address register 1
(RIWTAR1)
R/W
0x0000_0000
17.6.7.7/17-58
0xD_0DC8
RapidIO inbound window base address register 1 (RIWBAR1)
R/W
0x0000_0000
17.6.7.8/17-59
0xD_0DD0
RapidIO inbound window attributes register 1 (RIWAR1)
R/W
0x0004_4021
17.6.7.9/17-60
0xD_0DE0
RapidIO inbound window translation address register 0
(RIWTAR0)
R/W
0x0000_0000
17.6.7.7/17-58
0xD_0DF0
RapidIO inbound window attributes register 0 (RIWAR0)
Mixed
0x8004_4021
17.6.7.9/17-60
Message Unit
RapidIO Outbound Message Unit 0 Registers
0xD_3000
Outbound message 0 mode register (OM0MR)
R/W
0x0000_0000
17.7.1.1/17-62
0xD_3004
Outbound message 0 status register (OM0SR)
Mixed
0x0000_0000
17.7.1.2/17-64
0xD_3008
Extended outbound message 0 descriptor queue dequeue
pointer address register (EOM0DQDPAR)
R/W
0x0000_0000
17.7.1.3/17-65
0xD_300C
Outbound message 0 descriptor queue dequeue pointer
address register (OM0DQDPAR)
R/W
0x0000_0000
17.7.1.4/17-67
0xD_3010
Extended outbound message 0 source address register
(EOM0SAR)
R/W
0x0000_0000
17.7.1.5/17-68
0xD_3014
Outbound message 0 source address register (OM0SAR)
R/W
0x0000_0000
17.7.1.5/17-68
0xD_3018
Outbound message 0 destination port register (OM0DPR)
R/W
0x0000_0000
17.7.1.6/17-69
0xD_301C
Outbound message 0 destination attributes Register
(OM0DATR)
R/W
0x0000_0000
17.7.1.7/17-70
0xD_3020
Outbound message 0 double-word count register (OM0DCR)
R/W
0x0000_0000
17.7.1.8/17-70
0xD_3024
Extended outbound message 0 descriptor queue enqueue
pointer address register (EOM0DQEPAR)
R/W
0x0000_0000
17.7.1.4/17-67
0xD_3028
Outbound message 0 descriptor queue enqueue pointer
address register (OM0DQEPAR)
R/W
0x0000_0000
17.7.1.4/17-67
0xD_302C
Outbound message 0 retry error threshold configuration
register (OM0RETCR)
R/W
0x0000_0000
17.7.1.9/17-71
0xD_3030
Outbound message 0 multicast group register (OM0MGR)
R/W
0x0000_0000
17.7.1.10/17-72
0xD_3034
Outbound message 0 multicast list register (OM0MLR)
R/W
0x0000_0000
17.7.1.11/17-72
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Freescale Semiconductor
2-57
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
RapidIO Inbound Message Unit 0 Registers
0xD_3060
Inbound message 0 mode register (IM0MR)
R/W
0x0000_0000
17.7.2.1/17-73
0xD_3064
Inbound message 0 status register (IM0SR)
Mixed
0x0000_0002
17.7.2.2/17-75
0xD_3068
Extended inbound message 0 frame queue dequeue pointer
address register (EIM0FQDPAR)
R/W
0x0000_0000
17.7.2.3/17-76
0xD_306C
Inbound message 0 frame queue dequeue pointer address
register (IM0FQDPAR)
R/W
0x0000_0000
17.7.2.3/17-76
0xD_3070
Extended inbound message 0 frame queue enqueue pointer
address register (EIM0FQEPAR)
R/W
0x0000_0000
17.7.2.4/17-77
0xD_3074
Inbound message 0 frame queue enqueue pointer address
register (IM0FQEPAR)
R/W
0x0000_0000
17.7.2.4/17-77
0xD_3078
Inbound message 0 maximum interrupt report interval register
(IM0MIRIR)
R/W
0xFFFF_FF00
17.7.2.5/17-78
RapidIO Outbound Message Unit 1 Registers
0xD _3100
Outbound message 1 mode register (OM1MR)
R/W
0x0000_0000
17.7.1.1/17-62
0xD _3104
Outbound message 1 status register (OM1SR)
Mixed
0x0000_0000
17.7.1.2/17-64
0xD _3108
Extended outbound message 1 descriptor queue dequeue
pointer address register (EOM1DQDPAR)
R/W
0x0000_0000
17.7.1.3/17-65
0xD _310C
Outbound message 1 descriptor queue dequeue pointer
address register (OM1DQDPAR)
R/W
0x0000_0000
17.7.1.4/17-67
0xD _3110
Extended outbound message 1 source address register
(EOM1SAR)
R/W
0x0000_0000
17.7.1.5/17-68
0xD _3114
Outbound message 1 source address register (OM1SAR)
R/W
0x0000_0000
17.7.1.5/17-68
0xD _3118
Outbound message 1 destination port register (OM1DPR)
R/W
0x0000_0000
17.7.1.6/17-69
0xD _311C
Outbound message 1 destination attributes register
(OM1DATR)
R/W
0x0000_0000
17.7.1.7/17-70
0xD _3120
Outbound message 1 double-word count register (OM1DCR)
R/W
0x0000_0000
17.7.1.8/17-70
0xD _3124
Extended outbound message 1 descriptor queue enqueue
pointer address register (EOM1DQEPAR)
R/W
0x0000_0000
17.7.1.4/17-67
0xD _3128
Outbound message 1 descriptor queue enqueue pointer
address register (OM1DQEPAR)
R/W
0x0000_0000
17.7.1.4/17-67
0xD _312C
Outbound message 1 retry error threshold configuration
register (OM1RETCR)
R/W
0x0000_0000
17.7.1.9/17-71
0xD _3130
Outbound message 1 multicast group register (OM1MGR)
R/W
0x0000_0000
17.7.1.10/17-72
0xD _3134
Outbound message 1 multicast list register (OM1MLR)
R/W
0x0000_0000
17.7.1.11/17-72
0xD _3160
Inbound message 1 mode register (IM1MR)
R/W
0x0000_0000
17.7.2.1/17-73
0xD _3164
Inbound message 1 status register (IM1SR)
Mixed
0x0000_0002
17.7.2.2/17-75
0xD _3168
Extended inbound message 1 frame queue dequeue pointer
address register (EIM1FQDPAR)
R/W
0x0000_0000
17.7.2.3/17-76
RapidIO Inbound Message Unit 1 Registers
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-58
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0xD _316C
Inbound message 1 frame queue dequeue pointer address
register (IM1FQDPAR)
R/W
0x0000_0000
17.7.2.3/17-76
0xD _3170
Extended inbound message 1 frame queue enqueue pointer
address register (EIM1FQEPAR)
R/W
0x0000_0000
17.7.2.4/17-77
0xD _3174
Inbound message 1 frame queue enqueue pointer address
register (IM1FQEPAR)
R/W
0x0000_0000
17.7.2.4/17-77
0xD _3178
Inbound message 1 maximum interrupt report interval register
(IM1MIRIR)
R/W
0xFFFF_FF00
17.7.2.5/17-78
RapidIO Doorbell Registers
0xD_3400
Outbound doorbell mode register (ODMR)
R/W
0x0000_0000
17.7.3.1/17-79
0xD_3404
Outbound doorbell status register (ODSR)
Mixed
0x0000_0000
17.7.3.2/17-80
0xD_3408–
0xD_3414
Reserved
0xD_3418
Outbound doorbell destination port register (ODDPR)
R/W
0x0000_0000
17.7.3.3/17-80
0xD_341C
Outbound doorbell destination attributes register (ODDATR)
R/W
0x0000_0000
17.7.3.4/17-81
0xD_3420–
0xD_3428
Reserved
0xD_342C
Outbound doorbell retry error threshold configuration register
(ODRETCR)
R/W
0x0000_0000
17.7.3.5/17-82
0xD_3430–
0xD_345C
Reserved
0xD_3460
Inbound doorbell mode register (IDMR)
R/W
0x0000_0000
17.7.4.1/17-82
0xD_3464
Inbound doorbell status register (IDSR)
Mixed
0x0000_0002
17.7.4.2/17-84
0xD_3468
Extended inbound doorbell queue dequeue pointer address
register (EIDQDPAR)
R/W
0x0000_0000
17.7.4.3/17-85
0xD_346C
Inbound doorbell queue dequeue Pointer address register
(IDQDPAR)
R/W
0x0000_0000
17.7.4.3/17-85
0xD_3470
Extended inbound doorbell queue enqueue pointer address
register (EIDQEPAR)
R/W
0x0000_0000
17.7.4.4/17-86
0xD_3474
Inbound doorbell Queue enqueue pointer address register
(IDQEPAR)
R/W
0x0000_0000
17.7.4.4/17-86
0xD_3478
Inbound doorbell maximum interrupt report interval register
(IDMIRIR)
R/W
0xFFFF_FF00
17.7.4.5/17-87
0xD_347C
Reserved
0xD_34E0
Inbound port-write mode register (IPWMR)
R/W
0x0000_0000
17.7.5.1/17-88
0xD_34E4
Inbound port-write status register (IPWSR)
Mixed
0x0000_0000
17.7.5.2/17-89
0xD_34E8
Extended inbound port-write queue base address register
(EIPWQBAR)
R/W
0x0000_0000
17.7.5.3/17-89
0xD_34EC
Inbound port-write queue base address register (IPWQBAR)
R/W
0x0000_0000
17.7.5.3/17-89
RapidIO Port-Write Registers
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-59
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
Global Utilities Registers
Power-On Reset Configuration Values
0xE_0000
PORPLLSR—POR PLL ratio status register
R
0x00nn_n0nn
20.4.1.1/20-5
0xE_0004
PORBMSR—POR boot mode status register
R
0xnnnn_0000
20.4.1.2/20-6
0xE_0008
PORIMPSCR—POR I/O impedance status and control register
Mixed
0x000n_007F
20.4.1.3/20-7
0xE_000C
PORDEVSR—POR I/O device status register
R
see ref.
20.4.1.4/20-8
0xE_0010
PORDBGMSR—POR debug mode status register
R
see ref.
20.4.1.5/20-10
0xE_0014
PORDEVSR2—POR I/O device status register 2
R
see ref.
20.4.1.6/20-11
0xE_0020
GPPORCR—General-purpose POR configuration register
R
see ref.
20.4.1.7/20-11
Signal Multiplexing and GPIO Controls
0xE_0030
GPIOCR—GPIO control register
R/W
0x0000_0000
20.4.1.8/20-12
0xE_0040
GPOUTDR—General-purpose output data register
R/W
0x0000_0000
20.4.1.9/20-12
0xE_0050
GPINDR—General-purpose input data register
R
0xnnnn_0000
20.4.1.10/20-14
0xE_0060
PMUXCR—Alternate function signal multiplex control
R/W
0x0000_0000
20.4.1.11/20-14
R/W
0x0000_0000
20.4.1.12/20-15
Mixed
0x0000_0000
20.4.1.13/20-17
w1c
0x0000_0000
20.4.1.14/20-19
Mixed
0x0000_0000
20.4.1.15/20-20
Device Disables
0xE_0070
DEVDISR—Device disable control
Power Management Registers
0xE_0080
POWMGTCSR—Power management status and control
register
Interrupt and Reset Status and Control
0xE_0090
MCPSUMR—Machine check summary register
0xE_0094
RSTRSCR—Reset request status and control register
Version Registers
0xE_00A0
PVR—Processor version register
R
e500 processor
version
20.4.1.16/20-20
0xE_00A4
SVR—System version register
R
MPC8548E
system
version
20.4.1.17/20-21
Status Registers
0xE_00B0
RSTCR—Reset control register
R/W
0x0000_0000
20.4.1.18/20-22
0xE_00C0
LBCVSELCR—LBC voltage select control register
R/W
0x0000_0000
20.4.1.19/20-22
0xE_0B20
DDRCSR—DDR calibration status register
R
0x0000_0000
20.4.1.20/20-23
0xE_0B24
DDRCDR—DDR control driver register
R/W
0x0000_0000
20.4.1.21/20-23
0xE_0B28
DDRCLKDR—DDR clock disable register
R/W
0x0000_0000
20.4.1.22/20-25
Debug Control
0xE_0E00
CLKOCR—Clock out control register
R/W
0x0000_0000
20.4.1.23/20-25
0xE_0F04
SRDSCR0—LSerDes control register 0
R/W
0xnn00_nn00
20.4.1.24/20-26
0xE_0F08
SRDSCR1—LSerDes control register 1
R/W
0x0000_0000
20.4.1.25/20-27
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-60
Freescale Semiconductor
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
0xE_0F28
TSEC12IOOVCR—eTSEC 1 & 2 overdrive control register
R/W
See register
20.4.1.26/20-28
0xE_0F2C
TSEC34IOOVCR—eTSEC 3 & 4 overdrive control register
R/W
See register
20.4.1.27/20-29
Performance Monitor Control Registers
0xE_1000
PMGC0—Performance monitor global control register
R/W
0x0000_0000
21.3.2.1/21-5
0xE_1010
PMLCA0—Performance monitor local control register A0
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1014
PMLCB0—Performance monitor local control register B0
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1018
PMC0 (lower)—Performance monitor counter 0 upper
R/W
0x0000_0000
21.3.3.1/21-9
0xE_101C
PMC0 (upper)—Performance monitor counter 0 lower
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1020
PMLCA1—Performance monitor local control register A1
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1024
PMLCB1—Performance monitor local control register B1
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1028
PMC1—Performance monitor counter 1
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1030
PMLCA2—Performance monitor local control register A2
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1034
PMLCB2—Performance monitor local control register B 2
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1038
PMC2—Performance monitor counter 2
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1040
PMLCA3—Performance monitor local control register A3
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1044
PMLCB3—Performance monitor local control register B3
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1048
PMC3—Performance monitor counter 3
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1050
PMLCA4—Performance monitor local control register A4
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1054
PMLCB4—Performance monitor local control register B4
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1058
PMC4—Performance monitor counter 4
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1060
PMLCA5—Performance monitor local control register A5
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1064
PMLCB5—Performance monitor local control register B 5
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1068
PMC5—Performance monitor counter 5
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1070
PMLCA6—Performance monitor local control register A6
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1074
PMLCB6—Performance monitor local control register B6
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1078
PMC6—Performance monitor counter 6
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1080
PMLCA7—Performance monitor local control register A7
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1084
PMLCB7—Performance monitor local control register B7
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1088
PMC7—Performance monitor counter 7
R/W
0x0000_0000
21.3.3.1/21-9
0xE_1090
PMLCA8—Performance monitor local control register A8
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1094
PMLCB8—Performance monitor local control register B8
R/W
0x0000_0000
21.3.2.2/21-5
0xE_1098
PMC8—Performance monitor counter 8
R/W
0x0000_0000
21.3.3.1/21-9
0xE_10A0
PMLCA9—Performance monitor local control register A9
R/W
0x0000_0000
21.3.2.2/21-5
0xE_10A4
PMLCB9—Performance monitor local control register B9
R/W
0x0000_0000
21.3.2.2/21-5
0xE_10A8
PMC9—Performance monitor counter 9
R/W
0x0000_0000
21.3.3.1/21-9
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2-61
Memory Map
Table 2-11. Memory Map (continued)
Offset
Register
Access
Reset
Section/Page
Debug and Watchpoint Monitor Registers
Watchpoint Monitor Registers
0xE_2000
WMCR0—Watchpoint monitor control register 0
R/W
0x0000_0000
22.3.1.1/22-11
0xE_2004
WMCR1—Watchpoint monitor control register 1
R/W
0x0000_0000
22.3.1.1/22-11
0xE_200C
WMAR—Watchpoint monitor address register
R/W
0x0000_0000
22.3.1.2/22-13
0xE_2014
WMAMR—Watchpoint monitor address mask register
R/W
0x0000_0000
22.3.1.3/22-13
0xE_2018
WMTMR—Watchpoint monitor transaction mask register
R/W
0x0000_0000
22.3.1.4/22-13
0xE_201C
WMSR—Watchpoint monitor status register
R/W
0x0000_0000
22.3.1.5/22-15
Trace Buffer Registers
0xE_2040
TBCR0—Trace buffer control register 0
R/W
0x0000_0000
22.3.2.1/22-16
0xE_2044
TBCR1—Trace buffer control register 1
R/W
0x0000_0000
22.3.2.1/22-16
0xE_204C
TBAR—Trace buffer address register
R/W
0x0000_0000
22.3.2.2/22-18
0xE_2054
TBAMR—Trace buffer address mask register
R/W
0x0000_0000
22.3.2.3/22-19
0xE_2058
TBTMR—Trace buffer transaction mask register
R/W
0x0000_0000
22.3.2.4/22-19
0xE_205C
TBSR—Trace buffer status register
R/W
0x0000_0000
22.3.2.5/22-20
0xE_2060
TBACR—Trace buffer access control register
R/W
0x0000_0000
22.3.2.6/22-21
0xE_2064
TBADHR—Trace buffer access data high register
R/W
0x0000_0000
22.3.2.7/22-21
0xE_2068
TBADR—Trace buffer access data register
R/W
0x0000_0000
22.3.2.8/22-22
Context ID Registers
0xE_20A0
PCIDR—Programmed context ID register
R/W
0x0000_0000
22.3.3.1/22-22
0xE_20A4
CCIDR—Current context ID register
R/W
0x0000_0000
22.3.3.2/22-23
R/W
0x0000_0000
22.3.4.1/22-24
Other Registers
0xE_20B0
1
2
3
4
5
6
7
8
TOSR—Trigger output source register
Implementation-dependent reset values are listed in specified section/page.
I2C2 has the same memory-mapped registers that are described for I2C1 from 0x 0x0_3000 to 0x0_3014, except the offsets
are from 0x0_3100 to 0x0_3114.
Port size for BR0 is configured from external signals during reset, hence ‘nn’ is either 0x08, 0x10, or 0x18. See Section 4.4.3.3,
“Boot ROM Location,” for more information.
Cleared on read
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
eTSEC3 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_6000 to 0x2_6FFF.
eTSEC4 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_7000 to 0x2_7FFF.
Serial RapidIO registers: values indicated with n are read from configuration signals at reset; values indicated with X are
implementation dependent.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
2-62
Freescale Semiconductor
Chapter 3
Signal Descriptions
This chapter describes the MPC8548E external signals. It is organized into the following sections:
• Overview of signals and cross-references for signals that serve multiple functions, including two
lists: one by functional block and one alphabetical
• List of reset configuration signals
• List of output signal states at reset
NOTE
A bar over a signal name indicates that the signal is active low, such as
IRQ_OUT (interrupt out). Active-low signals are referred to as asserted
(active) when they are low and negated when they are high. Signals that are
not active low, such as IRQ (interrupt input), are referred to as asserted when
they are high and negated when they are low.
Internal signals are shown throughout this document as lower case and in
italics. For example, sys_logic_clk is an internal signal. These are discussed
only as necessary for understanding the external functionality of the device.
3.1
Signals Overview
The MPC8548E signals are grouped as follows:
• PCI interface signals
• I2C interface signals
• System control, general-purpose output, power management, and debug signals
• Test, JTAG, configuration, and clock signals
• PCI Express/serial RapidIO interface signals
• eTSEC1–4 interface signals
• DDR memory interface signals
• Local bus interface signals
• DMA interface signals
• PIC interface signals
• DUART interface signals
• Configuration signals
Figure 3-1, Figure 3-2, and Figure 3-3 illustrate the external signals of the MPC8548E, showing how the
signals are grouped. Refer to the MPC8548E Integrated Processor Hardware Specifications for a pinout
diagram showing pin numbers and a listing of all the electrical and mechanical specifications. Note that
these figures may show multiplexed signals more than once.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-1
Signal Descriptions
PCI1_AD[63:48]/PCI2_AD[31:16]
PCI1_AD[47:40]/PCI2_AD[15:8]
/GPOUT[8:15]
PCI1_AD[39:32]/PCI2_AD[7:0]
/GPIN[8:15]
PCI1_AD[31:0]
PCI1_C/BE[7:4]/PCI2_C/BE[3:0]
PCI1_C/BE[3:0]
PCI1_PAR
PCI1_PAR64/PCI2_PAR
PCI1_FRAME
PCI1_TRDY
PCI1_IRDY
PCI1_STOP
PCI1/PCI-X
Interface
PCI1_DEVSEL
PCI1_IDSEL
PCI1_REQ64/PCI2_FRAME
/cfg_pci1_width
16
8
8
32
4
16
PCI2_AD[15:8]/PCI1_AD[47:40]
/GPOUT[8:15]
8
8
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
PCI1_ACK64/PCI2_DEVSEL
1
1
1
1
1
1
PCI1_PERR
PCI1_SERR
PCI1_REQ0
1
PCI1_REQ[1:4]
4
PCI1_GNT0
1
PCI1_GNT1/cfg_pci1_impd
PCI2_PAR
1
1
1
PCI2_AD[7:0]/PCI1_AD[39:32]
/GPIN[8:15]
PCI2_C/BE[3:0]
PCI2_FRAME/PCI1_REQ64
/cfg_pci1_width
4
1
PCI2_AD[31:16]/PCI1_AD[63:48]
1
1
1
PCI2_TRDY
PCI2_IRDY
PCI2_STOP
PCI2_DEVSEL/PCI1_ACK64
PCI2
Interface
PCI2_PERR
PCI2_SERR
PCI2_REQ0
PCI2_REQ[1:4]
PCI2_GNT0
PCI2_GNT1/cfg_pci2_impd
PCI2_GNT2/cfg_pci2_arb
PCI2_GNT3/cfg_pci1_clk
PCI2_GNT4/cfg_pci2_clk
PCI2_CLK
1
PCI1_GNT2/cfg_pci1_arb
1
8
PCI1_GNT3/cfg_pci1_debug
1
PCI1_GNT4/cfg_pci1_mode
1
1
1
1
PCI1_CLK
HRESET
System
Control
HRESET_REQ
SRESET
CKSTP_IN
CKSTP_OUT
READY/TRIG_OUT
1
1
1
1
1
1
1
1
1
1
2
1
1
TRIG_OUT/READY
1
1
MSRCID0/cfg_mem_debug
1
1
MSRCID1/cfg_ddr_debug
1
1
MSRCID[2:4]
3
TRIG_IN
Debug
1
MDVAL
1
1
16
16
Power
Management
ASLEEP
1
2
GPOUT[24:31]
Gen. Purpose
SYSCLK
RTC
CLK_OUT
Clock
LSSD_MODE
L1_TSTCLK
L2_TSTCLK
TEST_SEL (MPC8543E only)
/TEST_SEL (MPC8548E, MPC8547E,
MPC8545E)
THERM[0:1]
TCK
TDI
TDO
TMS
TRST
Test
JTAG
SD_TX[7:0], SD_TX[[7:0]
SD_RX[7:0], SD_RX[7:0]
SD_REF_CLK, SD_REF_CLK
SerDes
Interface
Figure 3-1. MPC8548E Signal Groupings (1/3)
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-2
Freescale Semiconductor
Signal Descriptions
Ethernet
EC_GTX_CLK125
EC_MDC/cfg_tsec_1_2_reduce
EC_MDIO
1
1
1
3
1
3
1
TSEC2_TXD7/GPOUT0
/cfg_tsec2_prtcl1
TSEC2_TXD[6:5]/GPOUT[1:2]
TSEC2_TXD[4:2]/GPOUT[3:5]
/cfg_device_ID[7:5]
TSEC2_TXD1/GPOUT6
/cfg_dram_type0
TSEC2_TXD0//GPOUT7
/cfg_tsec2_prtcl0
TSEC2_TX_EN
eTSEC2
TSEC2_TX_ER/cfg_dram_type1
TSEC2_TX_CLK
TSEC2_GTX_CLK
TSEC2_CRS
TSEC2_COL
TSEC2_RXD[7:0]/GPIN[0:7]
TSEC2_RX_DV
TSEC2_RX_ER
TSEC2_RX_CLK
1
1
1
2
1
1
3
1
1
1
1
1
8
1
1
1
TSEC4_TXD2/TSEC3_TXD6
/FIFO3_TXD6/cfg_srds_en
TSEC4_TXD[1:0]/TSEC3_TXD[5:4]
/FIFO3_TXD[5:4]/cfg_tsec4_prtcl[1:0]
eTSEC4
TSEC4_TX_EN
/TSEC3_TX_ER/FIFO3_TX_ER
TSEC4_GTX_CLK
TSEC4_RXD[3:0]/TSEC3_RXD[7:4]
/FIFO3_RXD[7:4]
1
1
1
1
1
1
8
1
2
1
1
1
2
1
4
2
4
1
1
1
4
1
TSEC4_RX_CLK/TSEC3_COL
/FIFO3_TX_FC
1
PIC
Interface
1
1
1
1
1
1
1
1
9
1
1
1
I2C
IICn_SCL
TSEC1_TXD0/cfg_tsec1_prtcl0
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
eTSEC1
TSEC1_CRS
TSEC1_COL
TSEC1_RXD[7:0]
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RX_CLK
TSEC3_TXD7/TSEC4_TXD3
/FIFO3_TXD7
TSEC3_TXD6/TSEC4_TXD2
/FIFO3_TXD6
TSEC3_TXD[5:4]/TSEC4_TXD[1:0]
/FIFO3_TXD[5:4]/cfg_tsec4_prtcl[1:0]
TSEC3_TXD3/FIFO3_TXD3
TSEC3_TXD2/FIFO3_TXD2
/cfg_tsec_3_reduce
TSEC3_RXD[7:4]/TSEC4_RXD[3:0]
/FIFO3_RXD[7:4]
TSEC3_RXD[3:0]/FIFO3_RXD[3:0]
eTSEC3
TSEC3_TX_EN/FIFO3_TX_EN
TSEC3_TX_ER/TSEC4_TX_EN
/FIFO3_TX_ER
TSEC3_TX_CLK/FIFO3_TX_CLK
TSEC3_GTX_CLK
TSEC3_CRS/TSEC4_RX_DV
/FIFO3_RX_FC
TSEC3_COL/TSEC4_RX_CLK
/FIFO3_TX_FC
TSEC3_RX_DV/FIFO3_RX_DV
TSEC3_RX_ER/FIFO3_RX_ER
TSEC3_RX_CLK/FIFO3_RX_CLK
1
1
1
2
2
IICn_SDA
TSEC1_TXD[3:1]/cfg_io_ports[0:2]
TSEC3_TXD[1:0]//FIFO3_TXD[1:0]
/cfg_tsec3_prtcl[1:0]
1
TSEC4_RX_DV/TSEC3_CRS
/FIFO3_RX_FC
MCP
UDE
IRQ[0:8]
IRQ9/DMA_DREQ3
IRQ10/DMA_DACK3
IRQ11/DMA_DDONE3
IRQ_OUT
TSEC1_TXD[6:4]/cfg_rom_loc[0:2]
1
1
TSEC4_TXD3/TSEC3_TXD7
/FIFO3_TXD7
TSEC1_TXD7/cfg_tsec1_prtcl1
2
2
2
2
UART_SIN[0:1]
UART_SOUT[0:1]
UART_CTS[0:1]
UART_RTS[0:1]
Dual UART
Interface
Figure 3-2. MPC8548E Signal Groupings (2/3) (Continued)
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-3
Signal Descriptions
Memory
Interface
MDQ[0:63]
MECC[0:7]
MDM[0:8]
MDQS[0:8]
MDQS[0:8]
MBA[2:0]
MA[15:0]
MWE
MRAS
MCAS
MCS[0:3]
MCKE[0:3]
MCK[0:5], MCK[0:5]
MODT[0:3]
MDIC[0:1]
MSRCID0/cfg_mem_debug
MSRCID1/cfg_ddr_debug
MSRCID[2:4]
DMA_DREQ[0:1]
DMA_DACK[0:1]
DMA_DDONE[0:1]
DMA_DREQ2/LCS5
DMA
Interface
DMA_DACK2/LCS6
DMA_DDONE2/LCS7
DMA_DREQ3/IRQ9
DMA_DACK3/IRQ10
DMA_DDONE3/IRQ11
64
32
8
9
1
9
4
9
1
3
16
3
1
1
1
1
1
1
4
1
4
1
12
4
2
1
1
3
1
1
1
1
1
3
3
2
1
2
2
1
1
1
1
1
2
1
1
1
1
Local
Bus
Interface
LBCTL/cfg_core_pll0
LALE/cfg_core_pll1
LGPL0/LSDA10/cfg_rio_sys_size
LGPL1/LSDWE/cfg_pci2_speed
LGPL2/LOE/LSDRAS/cfg_core_pll2
LGPL3/LSDCAS/cfg_boot_seq0
LGPL4/LGTA/LUPWAIT/LPBSE
LGPL5/cfg_boot_seq1
LCKE
LCLK[0:2]
LSYNC_IN, LSYNC_OUT
32
1
1
1
4
1
cfg_mem_debug/MSRCID0
cfg_ddr_debug/MSRCID1
cfg_tsec1_prtcl1/TSEC1_TXD7
cfg_rom_loc[0:2]/TSEC1_TXD[6:4]
cfg_io_ports[0:2]/TSEC1_TXD[3:1]
cfg_tsec1_prtcl0/TSEC1_TXD0
cfg_tsec_3_reduce
/TSEC3_TXD2/FIFO3_TXD2
cfg_tsec3_prtcl[1:0]/TSEC3_TXD[1:0]
/FIFO3_TXD[1:0]
cfg_pci1_width/PCI2_FRAME/
PCI1_REQ64
cfg_pci2_impd/PCI2_GNT1
Configuration
cfg_pci2_arb/PCI2_GNT2
cfg_pci1_clk/PCI2_GNT3
cfg_pci2_clk/PCI2_GNT4
cfg_pci1_impd/PCI1_GNT1
cfg_pci1_arb/PCI1_GNT2
1
cfg_pci1_debug/PCI1_GNT3
1
1
cfg_pci1_speed/LWE0/LSDDQM0/LBS0
cfg_host_agt[0:2]/LWE[1:3]/
LSDDQM[1:3]/LBS[1:3]
cfg_core_pll0/LBCTL
cfg_core_pll1/LALE
cfg_rio_sys_size/LGPL0/LSDA10
cfg_pci2_speed/LGPL1/LSDWE
cfg_core_pll2/LGPL2/LOE/LSDRAS
cfg_boot_seq0/LGPL3/LSDCAS
cfg_boot_seq1/LGPL5
cfg_pci1_width/PCI1_REQ64/
PCI2_FRAME
4
5
cfg_cpu_boot/LA27
cfg_sys_pll[0:3]/LA[28:31]
1
1
LAD[0:31]/cfg_gpinput[0:31]
LDP[0:3]
LA27/cfg_cpu_boot
LA[28:31]/cfg_sys_pll[0:3]
LCS[0:4]
LCS5/DMA_DREQ2
LCS6/DMA_DACK2
LCS7/DMA_DDONE2
LWE0/LSDDQM0/LBS0/cfg_pci1_speed
LWE[1:3]//LSDDQM[]/
LBS[1:3]/cfg_host_agt[0:2]
cfg_gpinput[0:31]/LAD[0:31]
1
cfg_pci1_mode/PCI1_GNT4
1
1
1
1
MSRCID1/cfg_ddr_debug
3
1
1
1
1
1
1
3
1
1
1
1
1
1
1
3
1
2
2
cfg_tsec_1_2_reduce/EC_MDC
cfg_tsec2_prtcl1/TSEC2_TXD7
/GPOUT0
cfg_device_ID[7:5]/TSEC2_TXD[4:2]
/GPOUT[3:5]
cfg_dram_type0/TSEC2_TXD1
/GPOUT6
cfg_tsec2_prtcl0/TSEC2_TXD0
/GPOUT7
cfg_dram_type1/TSEC2_TX_ER
cfg_tsec4_prtcl[1:0]/TSEC4_TXD[1:0]
/TSEC3_TXD[5:4]/FIFO3_TXD[5:4]
Figure 3-3. MPC8548E Signal Groupings (3/3) (Continued)
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-4
Freescale Semiconductor
Signal Descriptions
Note that individual chapters of this document provide details for each signal, describing each signal’s
behavior when the signal is asserted or negated and when the signal is an input or an output.
The following tables provide summaries of signal functions. Table 3-1 provides a summary of the signals
grouped by function, and Table 3-2 provides the summary list of the signals grouped alphabetically. These
tables detail the signal name, interface, alternate functions, number of signals, and whether the signal is an
input, output, or bidirectional. The direction of the multiplexed signals applies for the primary signal
function listed in the left-most column of the table for that row (and does not apply for the state of the reset
configuration signals). Finally, the table provides a pointer to the table where the signal function is
described.
NOTE
If the MPC8548E is configured to use serial RapidIO, only the PCI1/X
interface is available. In this case PCI1/X may still be 64 bits wide.
Table 3-1. MPC8548E Signal Reference by Functional Block
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
MDQ[0:63]
DDR data
DDR memory
—
64
I/O
9-3/9-6
MECC[0:7]
DDR error correcting code
DDR memory
—
8
I/O
9-3/9-6
MDM[0:7]
DDR data mask
DDR memory
—
8
O
9-3/9-6
DDR ECC data mask
DDR memory
—
1
O
9-3/9-6
DDR data strobe
DDR memory
—
8
I/O
9-3/9-6
MDQS8
DDR ECC data strobe
DDR memory
—
1
I/O
9-3/9-6
MDQS[0:8]
DDR ECC data strobe
(complement)
DDR memory
—
9
I/O
9-3/9-6
MBA[1:0]
DDR bank select
DDR memory
—
2
O
9-3/9-6
MBA2
DDR bank select
DDR memory
—
1
0
9-3/9-6
MA[14:0]
DDR address
DDR memory
—
15
O
9-3/9-6
MA15
DDR address
DDR memory
—
1
O
9-3/9-6
MWE
DDR write enable
DDR memory
—
1
O
9-3/9-6
MRAS
DDR row address strobe
DDR memory
—
1
O
9-3/9-6
MCAS
DDR column address strobe
DDR memory
—
1
O
9-3/9-6
DDR chip select (2/DIMM)
DDR memory
—
4
O
9-3/9-6
MCKE[0:3]
DDR clock enable
DDR memory
—
4
O
9-4/9-9
MCK[0:5],
MCK[0:5]
DDR differential clocks (3
pairs/DIMM)
DDR memory
—
12
O
9-4/9-9
MODT[0:3]
DRAM On-Die Termination
DDR memory
—
4
O
—
Memory debug source ID
Debug/
DDR memory
—
5
O
22-3/22-7
Driver impedance calibration
DDR memory
—
2
I/O
PCI/X
PCI2_AD[31:16]
16
I/O
MDM8
MDQS[0:7]
MCS[0:3]
MSRCID[0:4]
MDIC[0:1]
PCI1_AD[63:48]
PCI address/data
16-2/16-8
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-5
Signal Descriptions
Table 3-1. MPC8548E Signal Reference by Functional Block (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
PCI1_AD[47:40]
PCI address/data
PCI/X
PCI2_AD[15:8]
GPOUT[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI1_AD[39:32]
PCI address/data
PCI/X
PCI2_AD[7:0]
GPIN[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI1_AD[31:0]
PCI address/data
PCI/X
—
32
I/O
16-2/16-8
PCI1_C/BE[7:4]
PCI command/byte enable
PCI/X
PCI2_C/BE[3:0]
4
I/O
16-2/16-8
PCI1_C/BE[3:0]
PCI command/byte enable
PCI/X
—
4
I/O
16-2/16-8
PCI parity
PCI/X
—
1
I/O
16-2/16-8
PCI1_PAR64
PCI parity 64
PCI/X
PCI2_PAR
1
I/O
16-2/16-8
PCI1_FRAME
PCI frame
PCI/X
—
1
I/O
16-2/16-8
PCI1_TRDY
PCI target ready
PCI/X
—
1
I/O
16-2/16-8
PCI1_IRDY
PCI initiator ready
PCI/X
—
1
I/O
16-2/16-8
PCI1_STOP
PCI stop
PCI/X
—
1
I/O
16-2/16-8
PCI device select
PCI/X
—
1
I/O
16-2/16-8
PCI1_IDSEL
PCI initial device select
PCI/X
—
1
I
16-2/16-8
PCI1_REQ64
PCI request 64
PCI/X
PCI2_FRAME
cfg_pci1_width
1
I/O
16-2/16-8
PCI1_ACK64
PCI acknowledge 64
PCI/X
PCI2_DEVSEL
1
I/O
16-2/16-8
PCI1_PERR
PCI parity error
PCI/X
—
1
I/O
16-2/16-8
PCI1_SERR
PCI system error
PCI/X
—
1
I/O
16-2/16-8
PCI1_REQ0
PCI request 0
PCI/X
—
1
I/O
16-2/16-8
PCI request 4–1
PCI/X
—
4
I
16-2/16-8
PCI1_GNT0
PCI grant 0
PCI/X
—
1
I/O
16-2/16-8
PCI1_GNT1
PCI grant 1
PCI/X
cfg_pci1_impd
1
I/O
16-2/16-8
PCI1_GNT2
PCI grant 2
PCI/X
cfg_pci1_arb
1
I/O
16-2/16-8
PCI1_GNT3
PCI grant 3
PCI/X
cfg_pci1_debug
1
I/O
16-2/16-8
PCI1_GNT4
PCI grant 4
PCI/X
cfg_pci1_mode
1
I/O
16-2/16-8
PCI clock
PCI/X
—
1
I
16-2/16-8
PCI2_AD[31:16]
PCI address/data
PCI/X
PCI1_AD[63:48]
16
I/O
16-2/16-8
PCI2_AD[15:8]
PCI address/data
PCI/X
PCI1_AD[47:40]
GPOUT[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI2_AD[7:0]
PCI address/data
PCI/X
PCI1_AD[39:32]
GPIN[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI command/byte enable
PCI/X
PCI1_C/BE[7:4]
4
I/O
16-2/16-8
PCI parity 64
PCI/X
PCI1_PAR64
1
I/O
16-2/16-8
PC1I_PAR
PCI1_DEVSEL
PCI1_REQ[4:1]
PCI1_CLK
PCI2_C/BE[3:0]
PCI2_PAR
PCI2_TRDY
PCI target ready
PCI
—
1
I/O
16-2/16-8
PCI2_IRDY
PCI initiator ready
PCI
—
1
I/O
16-2/16-8
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-6
Freescale Semiconductor
Signal Descriptions
Table 3-1. MPC8548E Signal Reference by Functional Block (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
PCI2_FRAME
PCI request 64
PCI
PCI1_REQ64
cfg_pci1_width
1
I/O
16-2/16-8
PCI2_DEVSEL
PCI acknowledge 64
PCI
PCI1_ACK64
1
I/O
16-2/16-8
PCI2_STOP
PCI stop
PCI
—
1
I/O
16-2/16-8
PCI2_PERR
PCI parity error
PCI
—
1
I/O
16-2/16-8
PCI2_SERR
PCI system error
PCI
—
1
I/O
16-2/16-8
PCI2_REQ0
PCI request 0
PCI
—
1
I/O
16-2/16-8
PCI request 4–1
PCI
—
4
I
16-2/16-8
PCI2_GNT0
PCI grant 0
PCI
—
1
I/O
16-2/16-8
PCI2_GNT1
PCI grant 4–1
PCI
cfg_pci2_impd
1
I/O
16-2/16-8
PCI2_GNT2
PCI grant 4–1
PCI
cfg_pci2_arb
1
I/O
16-2/16-8
PCI2_GNT3
PCI grant 4–1
PCI
cfg_pci1_clk
1
I/O
16-2/16-8
PCI2_GNT4
PCI grant 4–1
PCI
cfg_pci2_clk
1
I/O
16-2/16-8
PCI clock
PCI
—
1
I
16-2/16-8
Gigabit reference clock
Gigabit clock
—
1
I
14-2/14-8
EC_MDC
Ethernet management data
clock
Ethernet
management
cfg_tsec_1_2_reduce
1
O
14-2/14-8
EC_MDIO
Ethernet management data
in/out
Ethernet
management
—
1
I/O
14-2/14-8
TSEC1 transmit data 7
TSEC1
cfg_tsec1_prtcl[1]
1
O
14-2/14-8
TSEC1_TXD[6:4]
TSEC1 transmit data 6–4
TSEC1
cfg_rom_loc[0:2]
3
O
14-2/14-8
TSEC1_TXD[3:1]
TSEC1 transmit data 3–1
TSEC1
cfg_io_ports[0:2]
3
O
14-2/14-8
TSEC1_TXD0
TSEC1 transmit data 0
TSEC1
cfg_tsec1_prtcl[0]
1
O
14-2/14-8
TSEC1_TX_EN
TSEC1 transmit enable
TSEC1
—
1
O
14-2/14-8
TSEC1_TX_ER
TSEC1 transmit error
TSEC1
—
1
O
14-2/14-8
TSEC1_TX_CLK
TSEC1 transmit clock in
TSEC1
—
1
I
14-2/14-8
TSEC1
—
1
O
14-2/14-8
PCI2_REQ[4:1]
PCI2_CLK
EC_GTX_CLK125
TSEC1_TXD7
TSEC1_GTX_CLK TSEC1 transmit clock out
TSEC1_CRS
TSEC1 carrier sense
TSEC1
—
1
I
14-2/14-8
TSEC1_COL
TSEC1 collision detect
TSEC1
—
1
I
14-2/14-8
TSEC1 receive data
TSEC1
—
8
I
14-2/14-8
TSEC1_RX_DV
TSEC1 receive data valid
TSEC1
—
1
I
14-2/14-8
TSEC1_RX_ER
TSEC1 receiver error
TSEC1
—
1
I
14-2/14-8
TSEC1_RX_CLK
TSEC1 receive clock
TSEC1
—
1
I
14-2/14-8
TSEC2 transmit data 7
TSEC2
cfg_tsec2_prtcl[1]
GPOUT0
1
O
14-2/14-8
TSEC2 transmit data 6–5
TSEC2
GPOUT[1:2]
2
O
14-2/14-8
TSEC1_RXD[7:0]
TSEC2_TXD7
TSEC2_TXD[6:5]
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-7
Signal Descriptions
Table 3-1. MPC8548E Signal Reference by Functional Block (continued)
Name
Description
TSEC2_TXD[4:2]
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
TSEC2 transmit data 4–2
TSEC2
cfg_device_ID[7:5]
GPOUT[3:5]
3
O
14-2/14-8
TSEC2_TXD1
TSEC2 transmit data 1
TSEC2
cfg_dram_type0
GPOUT6
1
O
14-2/14-8
TSEC2_TXD0
TSEC2 transmit data 0
TSEC2
cfg_tsec2_prtcl[0]
GPOUT7
1
O
14-2/14-8
TSEC2_TX_EN
TSEC2 transmit enable
TSEC2
—
1
O
14-2/14-8
TSEC2_TX_ER
TSEC2 transmit error
TSEC2
cfg_dram_type1
1
O
14-2/14-8
TSEC2_TX_CLK
TSEC2 transmit clock in
TSEC2
—
1
I
14-2/14-8
TSEC2
—
1
O
14-2/14-8
TSEC2_GTX_CLK TSEC2 transmit clock out
TSEC2_CRS
TSEC2 carrier sense
TSEC2
—
1
I
14-2/14-8
TSEC2_COL
TSEC2 collision detect
TSEC2
—
1
I
14-2/14-8
TSEC2 receive data
TSEC2
GPIN[0:7]
8
I
14-2/14-8
TSEC2_RX_DV
TSEC2 receive data valid
TSEC2
—
1
I
14-2/14-8
TSEC2_RX_ER
TSEC2 receive error
TSEC2
—
1
I
14-2/14-8
TSEC2_RX_CLK
TSEC2 receive clock
TSEC2
—
1
I
14-2/14-8
TSEC3_TXD3
TSEC3 transmit data 3
TSEC3
FIFO3_TXD3
1
O
14-2/14-8
TSEC3_TXD2
TSEC3 transmit data 2
TSEC3
FIFO3_TXD2
cfg_tsec_3_reduce
1
O
14-2/14-8
TSEC3 transmit data 1–0
TSEC3
FIFO3_TXD[1:0]
cfg_tsec3_prtcl[1:0]
2
O
14-2/14-8
TSEC3_TX_EN
TSEC3 transmit enable
TSEC3
FIFO3_TX_EN
1
O
14-2/14-8
TSEC3_TX_CLK
TSEC3 transmit clock in
TSEC3
FIFO3_TX_CLK
1
I
14-2/14-8
TSEC3_GTX_CLK TSEC3 transmit clock out
TSEC3
—
1
O
14-2/14-8
TSEC3_RXD[3:0]
TSEC3 receive data 3–0
TSEC3
FIFO3_RXD[3:0]
4
I
14-2/14-8
TSEC3_RX_DV
TSEC3 receive data valid
TSEC3
FIFO3_RX_DV
1
I
14-2/14-8
TSEC3_RX_ER
TSEC3 receive error
TSEC3
FIFO3_RX_ER
1
I
14-2/14-8
TSEC3_RX_CLK
TSEC3 receive clock
TSEC3
FIFO3_RXCLK
1
I
14-2/14-8
TSEC4_TXD[3]/
TSEC3_TXD[7]
TSEC4 transmit data 3/
TSEC3 transmit data 7
TSEC4
FIFO3_TXD7
1
O
14-2/14-8
TSEC4_TXD[2]/
TSEC3_TXD[6]
TSEC4 transmit data 2/
TSEC3 transmit data 6
TSEC4
FIFO3_TXD6
cfg_srds_en
1
O
14-2/14-8
TSEC4 transmit data 1–0/
TSEC3 transmit data 5–4
TSEC4
FIFO3_TXD[5:4]
cfg_tsec3_prtcl[1:0]
2
O
14-2/14-8
TSEC4 transmit enable/
TSEC3 transmit error
TSEC4
—
1
O
14-2/14-8
TSEC4
—
1
O
14-2/14-8
TSEC2_RXD[7:0]
TSEC3_TXD[1:0]
TSEC4_TXD[1:0]/
TSEC3_TXD[5:4]
TSEC4_TX_EN/
TSEC3_TX_ER
TSEC4_GTX_CLK TSEC4 transmit clock out
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-8
Freescale Semiconductor
Signal Descriptions
Table 3-1. MPC8548E Signal Reference by Functional Block (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
TSEC4_RXD[3:0]/
TSEC3_RXD[7:4]
TSEC4 receive data 3–0/
TSEC3 receive data 7–4
TSEC4
FIFO3_RXD[7:4]
4
I
14-2/14-8
TSEC4_RX_DV/
TSEC3_CRS
TSEC4 receive data valid/
TSEC3 carrier sense
TSEC4
FIFO3_RX_FC
1
I
14-2/14-8
TSEC4_RX_CLK/
TSEC3_COL
TSEC4 receive clock/
TSEC3 collision detect
TSEC4
FIFO3_TX_FC
1
I
14-2/14-8
LAD[0:31]
Local bus address/data
LBC
cfg_gpinput[0:31]
32
I/O
13-2/13-5
LDP[0:3]
Local bus data parity
LBC
—
4
I/O
13-2/13-5
LA27
Local bus burst address
LBC
cfg_cpu_boot
1
O
13-2/13-5
LA[28:31]
Local bus port address
LBC
cfg_sys_pll[0:3]
4
O
13-2/13-5
LCS[0:4]
Local bus chip select 0–4
LBC
—
5
O
13-2/13-5
LCS5
Local bus chip select 5
LBC
DMA_DREQ2
1
O
13-2/13-5
LCS6
Local bus chip select 6
LBC
DMA_DACK2
1
O
13-2/13-5
LCS7
Local bus chip select 7
LBC
DMA_DDONE2
1
O
13-2/13-5
LWE0/LSDDQM0/
LBS0
Local bus write enable/data
mask/byte select 0
LBC
cfg_pci1_speed
1
O
13-2/13-5
LWE[1:3]/
LSDDQM[1:3]/
LBS[1:3]
Local bus write enable/data
mask/byte select 1–3
LBC
cfg_host_agt[0:2]
3
O
13-2/13-5
LBCTL
Local bus data buffer control
LBC
cfg_core_pll0
1
O
13-2/13-5
Local bus address latch enable
LBC
cfg_core_pll1
1
O
13-2/13-5
LGPL0/LSDA10
Local bus UPM general
purpose line 0/SDRAM
address bit 10
LBC
cfg_rio_sys_size
1
O
13-2/13-5
LGPL1/LSDWE
Local bus GP line 1/SDRAM
write enable
LBC
cfg_pci2_speed
1
O
13-2/13-5
Local bus GP line 2/output
enable/SDRAM RAS
LBC
cfg_core_pll2
1
O
13-2/13-5
LGPL3/LSDCAS
Local bus GP line 3/SDRAM
CAS
LBC
cfg_boot_seq0
1
O
13-2/13-5
LGPL4/LGTA/
LUPWAIT/LPBSE
Local bus GP line 4/GPCM
terminate access/UPM
wait/parity byte select
LBC
—
1
I/O
13-2/13-5
LGPL5
Local bus GP line 5 address
LBC
cfg_boot_seq1
1
O
13-2/13-5
LCKE
Local bus clock enable
LBC
—
1
O
13-2/13-5
LCLK[0:2]
Local bus clock
LBC
—
3
O
13-2/13-5
LSYNC_IN
Local bus PLL synchronization
LBC
—
1
I
13-2/13-5
LSYNC_OUT
Local bus PLL synchronization
LBC
—
1
O
13-2/13-5
DMA request 0–1
DMA
—
2
I
15-3/15-6
LALE
LGPL2/LOE/
LSDRAS
DMA_DREQ[0:1]
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-9
Signal Descriptions
Table 3-1. MPC8548E Signal Reference by Functional Block (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
DMA_DREQ2
DMA request 2
DMA
LCS5
1
I
15-3/15-6
DMA_DREQ3
DMA request 3
DMA
IRQ9
1
I
15-3/15-6
DMA acknowledge 0–1
DMA
—
2
O
15-3/15-6
DMA_DACK2
DMA acknowledge 2
DMA
LCS6
1
O
15-3/15-6
DMA_DACK3
DMA acknowledge 3
DMA
IRQ10
1
O
15-3/15-6
DMA
—
2
O
15-3/15-6
DMA_DACK[0:1]
DMA_DDONE[0:1] DMA done 0–1
DMA_DDONE2
DMA done 2
DMA
LCS7
1
O
15-3/15-6
DMA_DDONE3
DMA done 3
DMA
IRQ11
1
O
15-3/15-6
MCP
Machine check processor
PIC
—
1
I
10-5/10-6
UDE
Unconditional debug event
PIC
—
1
I
10-5/10-6
External interrupt 0–8
PIC
—
9
I
10-5/10-6
IRQ9
External interrupt 9
PIC
DMA_DREQ3
1
I
10-5/10-6
IRQ10
External interrupt 10
PIC
DMA_DACK3
1
I
10-5/10-6
IRQ11
External interrupt 11
PIC
DMA_DDONE3
1
I
10-5/10-6
Interrupt output
PIC
—
1
O
10-5/10-6
DUART serial data in
Dual UART
—
2
I
12-2/12-3
UART_SOUT[0:1]
DUART serial data out
Dual UART
—
2
O
12-2/12-3
UART_CTS[0:1]
DUART clear to send
Dual UART
—
2
I
12-2/12-3
UART_RTS[0:1]
DUART ready to send
Dual UART
—
2
O
12-2/12-3
serial data
I2C
—
1
I/O
11-2/11-4
serial clock
I2C
—
1
I/O
11-2/11-4
serial data
I2C
—
1
I/O
11-2/11-4
I2C
—
1
I/O
11-2/11-4
IRQ[0:8]
IRQ_OUT
UART_SIN[0:1]
IIC1_SDA
I2C
IIC1_SCL
I
2C
IIC2_SDA
I
2C
IIC2_SCL
I2C serial clock
SD_RX[7:0]
Receive data
PCI Express
Multiplexed with Serial
RapidIO
8
I
18-2/18-5
SD_RX[7:0]
Receive data (complement)
PCI Express
Multiplexed with Serial
RapidIO
8
I
18-2/18-5
SD_TX[7:0]
Transmit data
PCI Express
Multiplexed with Serial
RapidIO
8
O
18-2/18-5
SD_TX[7:0]
Transmit data (complement)
PCI Express
Multiplexed with Serial
RapidIO
8
O
18-2/18-5
SD_TX[7:4]
Transmit data
SRIO
Multiplexed with
PCI Express
4
O
17.4/17-3
SD_TX[7:4]
Transmit data (complement)
SRIO
Multiplexed with
PCI Express
4
O
17.4/17-3
SD_RX[7:4]
Receive data
SRIO
Multiplexed with
PCI Express
4
I
17.4/17-3
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-10
Freescale Semiconductor
Signal Descriptions
Table 3-1. MPC8548E Signal Reference by Functional Block (continued)
Name
SD_RX[7:4]
HRESET
HRESET_REQ
SRESET
CKSTP_IN
CKSTP_OUT
GPOUT[24:31]
Description
Receive data (complement)
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
SRIO
Multiplexed with
PCI Express
4
I
17.4/17-3
Hard reset
System control
—
1
I
4-2/4-2
Hard reset request
System control
—
1
O
4-2/4-2
Soft reset
System control
—
1
I
4-2/4-2
Checkstop in
System control
—
1
I
20-2/20-2
Checkstop out
System control
—
1
O
20-2/20-2
Generalpurpose outputs
—
8
O
20-2/20-2
20.4.1.9/20-12
System control
TRIG_OUT
1
O
4-2/4-2
Power mgmt
—
1
O
20-2/20-2
General-purpose output
READY
Device ready
ASLEEP
Asleep
TRIG_IN
Watchpoint trigger in
Debug
—
1
I
22-4/22-8
TRIG_OUT
Watchpoint trigger out
Debug
READY
1
O
22-4/22-8
MSRCID0
Memory debug source port
ID 0
Debug
cfg_mem_debug
1
O
22-3/22-7
MSRCID1
Memory debug source port
ID 1
Debug
cfg_ddr_debug
1
O
22-3/22-7
MSRCID[2:4]
Memory debug source port
ID 2–4
Debug
—
3
O
22-3/22-7
Memory debug data valid
Debug
—
1
O
22-3/22-7
MDVAL
LSSD_MODE
LSSD mode
Test
—
1
I
22-5/22-8
L1_TSTCLK
L1 test clock
Test
—
1
I
22-5/22-8
L2_TSTCLK
L2 test clock
Test
—
1
I
22-5/22-8
TEST_SEL
(MPC8548E,
MPC8547E,
MPC8545E)
Test select
Test
—
1
I
22-5/22-8
Thermal resistor access
Test
—
2
I
22-5/22-8
TCK
Test clock
JTAG
—
1
I
22-5/22-8
TDI
Test data in
JTAG
—
1
I
22-5/22-8
TDO
Test data out
JTAG
—
1
O
22-5/22-8
TMS
Test mode select
JTAG
—
1
I
22-5/22-8
TRST
Test reset
JTAG
—
1
I
22-5/22-8
System clock/PCI clock
Clock
—
1
I
4-3/4-3
Real time clock
Clock
—
1
I
4-3/4-3
Clock out
Clock
—
1
O
20-2/20-2
TEST_SEL
(MPC8543E)
THERM[0:1]
SYSCLK
RTC
CLK_OUT
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-11
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference
Functional
Block
Alternate Function(s)
Power mgmt
—
1
O
20-2/20-2
Checkstop in
System control
—
1
I
20-2/20-2
Checkstop out
System control
—
1
O
20-2/20-2
Clock out
Clock
—
1
O
20-2/20-2
DMA acknowledge 0–1
DMA
—
2
O
15-3/15-6
DMA_DACK2
DMA acknowledge 2
DMA
LCS6
1
O
15-3/15-6
DMA_DACK3
DMA acknowledge 3
DMA
IRQ10
1
O
15-3/15-6
DMA
—
2
O
15-3/15-6
Name
ASLEEP
CKSTP_IN
CKSTP_OUT
CLK_OUT
DMA_DACK[0:1]
Description
Asleep
DMA_DDONE[0:1] DMA done 0–1
No. of
I/O
Signals
Table/
Page
DMA_DDONE2
DMA done 2
DMA
LCS7
1
O
15-3/15-6
DMA_DDONE3
DMA done 3
DMA
IRQ11
1
O
15-3/15-6
DMA request 0–1
DMA
—
2
I
15-3/15-6
DMA_DREQ2
DMA request 2
DMA
LCS5
1
I
15-3/15-6
DMA_DREQ3
DMA request 3
DMA
IRQ9
1
I
15-3/15-6
Gigabit reference clock
Gigabit clock
—
1
I
14-2/14-8
EC_MDC
Ethernet management data
clock
Ethernet
management
cfg_tsec_1_2_reduce
1
O
14-2/14-8
EC_MDIO
Ethernet management data
in/out
Ethernet
management
—
1
I/O
14-2/14-8
General-purpose output
Generalpurpose outputs
—
8
O
20-2/20-2
20.4.1.9/20-12
Hard reset
System control
—
1
I
4-2/4-2
Hard reset request
System control
—
1
O
4-2/4-2
serial clock
I2C
—
1
I/O
11-2/11-4
serial data
I2C
—
1
I/O
11-2/11-4
serial clock
I2C
—
1
I/O
11-2/11-4
serial data
I2C
—
1
I/O
11-2/11-4
External interrupt 0–8
PIC
—
9
I
10-5/10-6
Interrupt output
PIC
—
1
O
10-5/10-6
IRQ10
External interrupt 10
PIC
DMA_DACK3
1
I
10-5/10-6
IRQ11
External interrupt 11
PIC
DMA_DDONE3
1
I
10-5/10-6
IRQ9
External interrupt 9
PIC
DMA_DREQ3
1
I
10-5/10-6
L1_TSTCLK
L1 test clock
Test
—
1
I
22-5/22-8
L2_TSTCLK
L2 test clock
Test
—
1
I
22-5/22-8
LA[28:31]
Local bus port address
LBC
cfg_sys_pll[0:3]
4
O
13-2/13-5
LA27
Local bus burst address
LBC
cfg_cpu_boot
1
O
13-2/13-5
LAD[0:31]
Local bus address/data
LBC
cfg_gpinput[0:31]
32
I/O
13-2/13-5
DMA_DREQ[0:1]
EC_GTX_CLK125
GPOUT[24:31]
HRESET
HRESET_REQ
IIC1_SCL
I2C
IIC1_SDA
2C
IIC2_SCL
IIC2_SDA
IRQ[0:8]
IRQ_OUT
I
2C
I
2C
I
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-12
Freescale Semiconductor
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference (continued)
Name
Description
Functional
Block
Alternate Function(s)
LALE
Local bus address latch enable
LBC
cfg_core_pll1
1
O
13-2/13-5
LBCTL
Local bus data buffer control
LBC
cfg_core_pll0
1
O
13-2/13-5
LCKE
Local bus clock enable
LBC
—
1
O
13-2/13-5
LCLK[0:2]
Local bus clock
LBC
—
3
O
13-2/13-5
LCS[0:4]
Local bus chip select 0–4
LBC
—
5
O
13-2/13-5
LCS5
Local bus chip select 5
LBC
DMA_DREQ2
1
O
13-2/13-5
LCS6
Local bus chip select 6
LBC
DMA_DACK2
1
O
13-2/13-5
LCS7
Local bus chip select 7
LBC
DMA_DDONE2
1
O
13-2/13-5
Local bus data parity
LBC
—
4
I/O
13-2/13-5
LGPL0/LSDA10
Local bus UPM general purpose
line 0/SDRAM address bit 10
LBC
cfg_rio_sys_size
1
O
13-2/13-5
LGPL1/LSDWE
Local bus GP line 1/SDRAM
write enable
LBC
cfg_pci2_speed
1
O
13-2/13-5
Local bus GP line 2/output
enable/SDRAM RAS
LBC
cfg_core_pll2
1
O
13-2/13-5
LGPL3/LSDCAS
Local bus GP line
3/SDRAM CAS
LBC
cfg_boot_seq0
1
O
13-2/13-5
LGPL4/LGTA/
LUPWAIT/LPBSE
Local bus GP line 4/GPCM
terminate access/UPM
wait/parity byte select
LBC
—
1
I/O
13-2/13-5
LGPL5
Local bus GP line 5 address
LBC
cfg_boot_seq1
1
O
13-2/13-5
LSSD mode
Test
—
1
I
22-5/22-8
LSYNC_IN
Local bus PLL synchronization
LBC
—
1
I
13-2/13-5
LSYNC_OUT
Local bus PLL synchronization
LBC
—
1
O
13-2/13-5
LWE[1:3]/
LSDDQM[1:3]/
LBS[1:3]
Local bus write enable/data
mask/byte select 1–3
LBC
cfg_host_agt[0:2]
3
O
13-2/13-5
LWE0/LSDDQM0/
LBS0
Local bus write enable/data
mask/byte select 0
LBC
cfg_pci1_speed
1
O
13-2/13-5
LDP[0:3]
LGPL2/LOE/
LSDRAS
LSSD_MODE
No. of
I/O
Signals
Table/
Page
MA[14:0]
DDR address
DDR memory
—
15
O
9-3/9-6
MA15
DDR address
DDR memory
—
1
O
9-3/9-6
MBA[1:0]
DDR bank select
DDR memory
—
2
O
9-3/9-6
MBA2
DDR bank select
DDR memory
—
1
0
9-3/9-6
MCAS
DDR column address strobe
DDR memory
—
1
O
9-3/9-6
MCK[0:5],
MCK[0:5]
DDR differential clocks
(3 pairs/DIMM)
DDR memory
—
12
O
9-4/9-9
MCKE[0:3]
DDR clock enable
DDR memory
—
4
O
9-4/9-9
PIC
—
1
I
10-5/10-6
MCP
Machine check processor
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-13
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
MCS[0:3]
DDR chip select (2/DIMM)
DDR memory
—
4
O
MDIC[0:1]
Driver impedance calibration
DDR memory
—
2
I/O
MDM[0:7]
DDR data mask
DDR memory
—
8
O
9-3/9-6
DDR ECC data mask
DDR memory
—
1
O
9-3/9-6
MDQ[0:63]
DDR data
DDR memory
—
64
I/O
9-3/9-6
MDQS[0:7]
DDR data strobe
DDR memory
—
8
I/O
9-3/9-6
MDQS[0:8]
DDR ECC data strobe
(complement)
DDR memory
—
9
I/O
9-3/9-6
MDQS8
DDR ECC data strobe
DDR memory
—
1
I/O
9-3/9-6
MDVAL
Memory debug data valid
Debug
—
1
O
22-3/22-7
MECC[0:7]
DDR error correcting code
DDR memory
—
8
I/O
9-3/9-6
MODT[0:3]
DRAM On-Die Termination
DDR memory
—
4
O
—
MRAS
DDR row address strobe
DDR memory
—
1
O
9-3/9-6
MSRCID[0:4]
Memory debug source ID
Debug/
DDR memory
—
5
O
22-3/22-7
MSRCID[2:4]
Memory debug source port
ID 2–4
Debug
—
3
O
22-3/22-7
MSRCID0
Memory debug source port ID 0
Debug
cfg_mem_debug
1
O
22-3/22-7
MSRCID1
Memory debug source port ID 1
Debug
cfg_ddr_debug
1
O
22-3/22-7
DDR memory
—
1
O
9-3/9-6
PCI parity
PCI/X
—
1
I/O
16-2/16-8
PCI acknowledge 64
PCI/X
PCI2_DEVSEL
1
I/O
16-2/16-8
PCI1_AD[31:0]
PCI address/data
PCI/X
—
32
I/O
16-2/16-8
PCI1_AD[39:32]
PCI address/data
PCI/X
PCI2_AD[7:0]
GPIN[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI1_AD[47:40]
PCI address/data
PCI/X
PCI2_AD[15:8]
GPOUT[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI1_AD[63:48]
PCI address/data
PCI/X
PCI2_AD[31:16]
16
I/O
16-2/16-8
PCI1_C/BE[3:0]
PCI command/byte enable
PCI/X
—
4
I/O
16-2/16-8
PCI1_C/BE[7:4]
PCI command/byte enable
PCI/X
PCI2_C/BE[3:0]
4
I/O
16-2/16-8
PCI clock
PCI/X
—
1
I
16-2/16-8
PCI1_DEVSEL
PCI device select
PCI/X
—
1
I/O
16-2/16-8
PCI1_FRAME
PCI frame
PCI/X
—
1
I/O
16-2/16-8
PCI1_GNT0
PCI grant 0
PCI/X
—
1
I/O
16-2/16-8
PCI1_GNT1
PCI grant 1
PCI/X
cfg_pci1_impd
1
I/O
16-2/16-8
PCI1_GNT2
PCI grant 2
PCI/X
cfg_pci1_arb
1
I/O
16-2/16-8
PCI1_GNT3
PCI grant 3
PCI/X
cfg_pci1_debug
1
I/O
16-2/16-8
MDM8
MWE
PC1I_PAR
PCI1_ACK64
PCI1_CLK
DDR write enable
9-3/9-6
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-14
Freescale Semiconductor
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
PCI1_GNT4
PCI grant 4
PCI/X
cfg_pci1_mode
1
I/O
16-2/16-8
PCI1_IDSEL
PCI initial device select
PCI/X
—
1
I
16-2/16-8
PCI initiator ready
PCI/X
—
1
I/O
16-2/16-8
PCI1_PAR64
PCI parity 64
PCI/X
PCI2_PAR
1
I/O
16-2/16-8
PCI1_PERR
PCI parity error
PCI/X
—
1
I/O
16-2/16-8
PCI1_REQ[4:1]
PCI request 4–1
PCI/X
—
4
I
16-2/16-8
PCI1_REQ0
PCI request 0
PCI/X
—
1
I/O
16-2/16-8
PCI1_REQ64
PCI request 64
PCI/X
PCI2_FRAME
cfg_pci1_width
1
I/O
16-2/16-8
PCI1_SERR
PCI system error
PCI/X
—
1
I/O
16-2/16-8
PCI1_STOP
PCI stop
PCI/X
—
1
I/O
16-2/16-8
PCI1_TRDY
PCI target ready
PCI/X
—
1
I/O
16-2/16-8
PCI2_AD[15:8]
PCI address/data
PCI/X
PCI1_AD[47:40]
GPOUT[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI2_AD[31:16]
PCI address/data
PCI/X
PCI1_AD[63:48]
16
I/O
16-2/16-8
PCI2_AD[7:0]
PCI address/data
PCI/X
PCI1_AD[39:32]
GPIN[8:15]
8
I/O
16-2/16-8
20.4.1.10/20-14
PCI command/byte enable
PCI/X
PCI1_C/BE[7:4]
4
I/O
16-2/16-8
PCI
—
1
I
16-2/16-8
PCI1_IRDY
PCI2_C/BE[3:0]
PCI2_CLK
PCI clock
PCI2_DEVSEL
PCI acknowledge 64
PCI/X
PCI1_ACK64
1
I/O
16-2/16-8
PCI2_FRAME
PCI request 64
PCI/X
PCI1_REQ64
cfg_pci1_width
1
I/O
16-2/16-8
PCI2_GNT0
PCI grant 0
PCI
—
1
I/O
16-2/16-8
PCI2_GNT1
PCI grant 4–1
PCI
cfg_pci2_impd
1
I/O
16-2/16-8
PCI2_GNT2
PCI grant 4–1
PCI
cfg_pci2_arb
1
I/O
16-2/16-8
PCI2_GNT3
PCI grant 4–1
PCI
cfg_pci1_clk
1
I/O
16-2/16-8
PCI2_GNT4
PCI grant 4–1
PCI
cfg_pci2_clk
1
I/O
16-2/16-8
PCI2_IRDY
PCI initiator ready
PCI
—
1
I/O
16-2/16-8
PCI2_PAR
PCI parity 64
PCI/X
PCI1_PAR64
1
I/O
16-2/16-8
PCI2_PERR
PCI parity error
PCI
—
1
I/O
16-2/16-8
PCI2_REQ[4:1]
PCI request 4–1
PCI
—
4
I
16-2/16-8
PCI2_REQ0
PCI request 0
PCI
—
1
I/O
16-2/16-8
PCI2_SERR
PCI system error
PCI
—
1
I/O
16-2/16-8
PCI2_STOP
PCI stop
PCI
—
1
I/O
16-2/16-8
PCI2_TRDY
PCI target ready
PCI
—
1
I/O
16-2/16-8
System control
TRIG_OUT
1
O
4-2/4-2
READY
Device ready
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-15
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference (continued)
Name
RTC
Description
Real time clock
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
Clock
—
1
I
4-3/4-3
SD_RX[7:0]
Receive data
PCI Express
Multiplexed with Serial
RapidIO
8
I
18-2/18-5
SD_RX[7:0]
Receive data (complement)
PCI Express
Multiplexed with Serial
RapidIO
8
I
18-2/18-5
SD_RX[7:4]
Receive data
SRIO
Multiplexed with
PCI Express
4
I
17.4/17-3
SD_RX[7:4]
Receive data (complement)
SRIO
Multiplexed with
PCI Express
4
I
17.4/17-3
SD_TX[7:0]
Transmit data
PCI Express
Multiplexed with Serial
RapidIO
8
O
18-2/18-5
SD_TX[7:0]
Transmit data (complement)
PCI Express
Multiplexed with Serial
RapidIO
8
O
18-2/18-5
SD_TX[7:4]
Transmit data
SRIO
Multiplexed with
PCI Express
4
O
17.4/17-3
SD_TX[7:4]
Transmit data (complement)
SRIO
Multiplexed with
PCI Express
4
O
17.4/17-3
System control
—
1
I
4-2/4-2
SRESET
Soft reset
SYSCLK
System clock/PCI clock
Clock
—
1
I
4-3/4-3
TCK
Test clock
JTAG
—
1
I
22-5/22-8
TDI
Test data in
JTAG
—
1
I
22-5/22-8
TDO
Test data out
JTAG
—
1
O
22-5/22-8
Test select
Test
—
1
I
22-5/22-8
Thermal resistor access
Test
—
2
I
22-5/22-8
Test mode select
JTAG
—
1
I
22-5/22-8
Watchpoint trigger in
Debug
—
1
I
22-4/22-8
Watchpoint trigger out
Debug
READY
1
O
22-4/22-8
Test reset
JTAG
—
1
I
22-5/22-8
TEST_SEL
(MPC8548E,
MPC8547E,
MPC8545E)
TEST_SEL
(MPC8543E)
THERM[0:1]
TMS
TRIG_IN
TRIG_OUT
TRST
TSEC1_COL
TSEC1 collision detect
TSEC1
—
1
I
14-2/14-8
TSEC1_CRS
TSEC1 carrier sense
TSEC1
—
1
I
14-2/14-8
TSEC1
—
1
O
14-2/14-8
TSEC1 receive clock
TSEC1
—
1
I
14-2/14-8
TSEC1_RX_DV
TSEC1 receive data valid
TSEC1
—
1
I
14-2/14-8
TSEC1_RX_ER
TSEC1 receiver error
TSEC1
—
1
I
14-2/14-8
TSEC1_GTX_CLK TSEC1 transmit clock out
TSEC1_RX_CLK
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
TSEC1_RXD[7:0]
TSEC1 receive data
TSEC1
—
8
I
14-2/14-8
TSEC1_TX_CLK
TSEC1 transmit clock in
TSEC1
—
1
I
14-2/14-8
TSEC1_TX_EN
TSEC1 transmit enable
TSEC1
—
1
O
14-2/14-8
TSEC1_TX_ER
TSEC1 transmit error
TSEC1
—
1
O
14-2/14-8
TSEC1_TXD[3:1]
TSEC1 transmit data 3–1
TSEC1
cfg_io_ports[0:2]
3
O
14-2/14-8
TSEC1_TXD[6:4]
TSEC1 transmit data 6–4
TSEC1
cfg_rom_loc[0:2]
3
O
14-2/14-8
TSEC1_TXD0
TSEC1 transmit data 0
TSEC1
cfg_tsec1_prtcl[0]
1
O
14-2/14-8
TSEC1_TXD7
TSEC1 transmit data 7
TSEC1
cfg_tsec1_prtcl[1]
1
O
14-2/14-8
TSEC2_COL
TSEC2 collision detect
TSEC2
—
1
I
14-2/14-8
TSEC2_CRS
TSEC2 carrier sense
TSEC2
—
1
I
14-2/14-8
TSEC2
—
1
O
14-2/14-8
TSEC2 receive clock
TSEC2
—
1
I
14-2/14-8
TSEC2_RX_DV
TSEC2 receive data valid
TSEC2
—
1
I
14-2/14-8
TSEC2_RX_ER
TSEC2 receive error
TSEC2
—
1
I
14-2/14-8
TSEC2_RXD[7:0]
TSEC2 receive data
TSEC2
GPIN[0:7]
8
I
14-2/14-8
TSEC2_TX_CLK
TSEC2 transmit clock in
TSEC2
—
1
I
14-2/14-8
TSEC2_TX_EN
TSEC2 transmit enable
TSEC2
—
1
O
14-2/14-8
TSEC2_TX_ER
TSEC2 transmit error
TSEC2
cfg_dram_type1
1
O
14-2/14-8
TSEC2_TXD[4:2]
TSEC2 transmit data 4–2
TSEC2
cfg_device_ID[7:5]
GPOUT[3:5]
3
O
14-2/14-8
TSEC2_TXD[6:5]
TSEC2 transmit data 6–5
TSEC2
GPOUT[1:2]
2
O
14-2/14-8
TSEC2_TXD0
TSEC2 transmit data 0
TSEC2
cfg_tsec2_prtcl[0]
GPOUT7
1
O
14-2/14-8
TSEC2_TXD1
TSEC2 transmit data 1
TSEC2
cfg_dram_type0
GPOUT6
1
O
14-2/14-8
TSEC2_TXD7
TSEC2 transmit data 7
TSEC2
cfg_tsec2_prtcl[1]
GPOUT0
1
O
14-2/14-8
TSEC3
—
1
O
14-2/14-8
TSEC3 receive clock
TSEC3
FIFO3_RXCLK
1
I
14-2/14-8
TSEC3_RX_DV
TSEC3 receive data valid
TSEC3
FIFO3_RX_DV
1
I
14-2/14-8
TSEC3_RX_ER
TSEC3 receive error
TSEC3
FIFO3_RX_ER
1
I
14-2/14-8
TSEC3_RXD[3:0]
TSEC3 receive data 3–0
TSEC3
FIFO3_RXD[3:0]
4
I
14-2/14-8
TSEC3_TX_CLK
TSEC3 transmit clock in
TSEC3
FIFO3_TX_CLK
1
I
14-2/14-8
TSEC3_TX_EN
TSEC3 transmit enable
TSEC3
FIFO3_TX_EN
1
O
14-2/14-8
TSEC3 transmit data 1–0
TSEC3
FIFO3_TXD[1:0]
cfg_tsec3_prtcl[1:0]
2
O
14-2/14-8
TSEC2_GTX_CLK TSEC2 transmit clock out
TSEC2_RX_CLK
TSEC3_GTX_CLK TSEC3 transmit clock out
TSEC3_RX_CLK
TSEC3_TXD[1:0]
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-17
Signal Descriptions
Table 3-2. MPC8548E Alphabetical Signal Reference (continued)
Name
Description
Functional
Block
Alternate Function(s)
No. of
I/O
Signals
Table/
Page
TSEC3_TXD2
TSEC3 transmit data 2
TSEC3
FIFO3_TXD2
cfg_tsec_3_reduce
1
O
14-2/14-8
TSEC3_TXD3
TSEC3 transmit data 3
TSEC3
FIFO3_TXD3
1
O
14-2/14-8
TSEC4_GTX_CLK TSEC4 transmit clock out
TSEC4
—
1
O
14-2/14-8
TSEC4_RX_CLK/
TSEC3_COL
TSEC4 receive clock/
TSEC3 collision detect
TSEC4
FIFO3_TX_FC
1
I
14-2/14-8
TSEC4_RX_DV/
TSEC3_CRS
TSEC4 receive data valid/
TSEC3 carrier sense
TSEC4
FIFO3_RX_FC
1
I
14-2/14-8
TSEC4_RXD[3:0]/
TSEC3_RXD[7:4]
TSEC4 receive data 3–0/
TSEC3 receive data 7–4
TSEC4
FIFO3_RXD[7:4]
4
I
14-2/14-8
TSEC4_TX_EN/
TSEC3_TX_ER
TSEC4 transmit enable/
TSEC3 transmit error
TSEC4
—
1
O
14-2/14-8
TSEC4 transmit data 1–0/
TSEC3 transmit data 5–4
TSEC4
FIFO3_TXD[5:4]
cfg_tsec3_prtcl[1:0]
2
O
14-2/14-8
TSEC4_TXD[2]/
TSEC3_TXD[6]
TSEC4 transmit data 2/
TSEC3 transmit data 6
TSEC4
FIFO3_TXD6
cfg_srds_en
1
O
14-2/14-8
TSEC4_TXD[3]/
TSEC3_TXD[7]
TSEC4 transmit data 3/
TSEC3 transmit data 7
TSEC4
FIFO3_TXD7
1
O
14-2/14-8
UART_CTS[0:1]
DUART clear to send
Dual UART
—
2
I
12-2/12-3
UART_RTS[0:1]
DUART ready to send
Dual UART
—
2
O
12-2/12-3
UART_SIN[0:1]
DUART serial data in
Dual UART
—
2
I
12-2/12-3
DUART serial data out
Dual UART
—
2
O
12-2/12-3
PIC
—
1
I
10-5/10-6
TSEC4_TXD[1:0]/
TSEC3_TXD[5:4]
UART_SOUT[0:1]
UDE
3.2
Unconditional debug event
Configuration Signals Sampled at Reset
The signals that serve alternate functions as configuration input signals during system reset are
summarized in Table 3-3. The detailed interpretation of their voltage levels during reset is described in
Chapter 4, “Reset, Clocking, and Initialization.”
Note that throughout this document, the reset configuration signals are described as being sampled at the
negation of HRESET. However, there is a setup and hold time for these signals relative to the rising edge
of HRESET, as described in the MPC8548E Integrated Processor Hardware Specifications. Note that the
PLL configuration signals have different setup and hold time requirements than the other reset
configuration signals.
The reset configuration signals are multiplexed with other functional signals. The values on these signals
during reset are interpreted to be logic one or zero, regardless of whether the functional signal name is
defined as active-low. Most of the reset configuration signals have internal pull-up resistors so that if the
signals are not driven, the default value is high (a one), as shown in the table. Some signals do not have
pull-up resistors and must be driven high or low during the reset period. For details about all the signals
that require external pull-up resistors, see the MPC8548E Integrated Processor Hardware Specifications.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-18
Freescale Semiconductor
Signal Descriptions
Note that the multiplexing of various signals on the MPC8548E is controlled by the PMUXCR register
described in Chapter 20, “Global Utilities.”
Table 3-3. MPC8548E Reset Configuration Signals
Functional Interface
PCI
Ethernet Management
TSEC1
TSEC2
TSEC3
TSEC4
Reset Configuration
Name
Default
PCI1_REQ64/PCI2_FRAME
cfg_pci1_width
1
PCI1_GNT4
cfg_pci1_mode
1
PCI1_GNT3
cfg_pci1_debug
1
PCI1_GNT2
cfg_pci1_arb
1
PCI1_GNT1
cfg_pci1_impd
1
PCI2_GNT4
cfg_pci2_clk
1
PCI2_GNT3
cfg_pci1_clk
1
PCI2_GNT2
cfg_pci2_arb
1
PCI2_GNT1
cfg_pci2_impd
1
cfg_tsec_1_2_reduce
1
TSEC1_TXD7
cfg_tsec1_prtcl[1]
1
TSEC1_TXD0
cfg_tsec1_prtcl[0]
1
TSEC1_TXD[6:4]
cfg_rom_loc[0:2]
111
TSEC1_TXD[3:1]
cfg_io_ports[0:2]
111
TSEC2_TXD7
cfg_tsec2_prtcl[1]
1
TSEC2_TXD0
cfg_tsec2_prtcl[0]
TSEC2_TXD[4:2]
cfg_device_ID[7:5]
111
TSEC2_TXD1
cfg_dram_type[0]
1
TSEC2_TX_ER
cfg_dram_type[1]
1
TSEC3_TXD2
cfg_tsec_3_reduce
1
TSEC3_TXD[1:0]
cfg_tsec3_prtcl[1:0]
11
TSEC4_TXD[1:0]
cfg_tsec4_prtcl[1:0]
11
cfg_srds_en
1
Functional Signal Name
EC_MDC
TSEC4_TXD2
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-19
Signal Descriptions
Table 3-3. MPC8548E Reset Configuration Signals (continued)
Functional Interface
LBC
Functional Signal Name
Reset Configuration
Name
LAD[0:31]
cfg_gpinput[0:31]
Indeterminate if not
driven (no default)
cfg_cpu_boot
1
cfg_sys_pll[0:3]
Must be driven
cfg_host_agt[0:2]
111
LBCTL
cfg_core_pll0
Must be driven
LALE
cfg_core_pll1
Must be driven
LGPL2/LOE/LSDRAS
cfg_core_pll2
Must be driven
LGPL0/LSDA10
cfg_rio_sys_size
1
LWE0/LSDDQM0/LBS0
cfg_pci1_speed
1
LGPL1/LSDWE
cfg_pci2_speed
1
LGPL3/LSDCAS
cfg_boot_seq0
1
LGPL5
cfg_boot_seq1
1
MSRCID0
cfg_mem_debug
1
MSRCID1
cfg_ddr_debug
1
LA27
LA[28:31]
LWE[1:3]/LSDDQM[1:3]/LBS[1:3]
Debug
3.3
Default
Output Signal States During Reset
When a system reset is recognized (HRESET is asserted), the MPC8548E aborts all current internal and
external transactions and releases all bidirectional I/O signals to a high-impedance state. See Chapter 4,
“Reset, Clocking, and Initialization,” for a complete description of the reset functionality.
During reset, the MPC8548E ignores most input signals (except for the reset configuration signals) and
drives most of the output-only signals to an inactive state. Table 3-4 shows the states of the output-only
signals (that is, the signals that are not multiplexed with other inputs, or are not used as reset configuration
signals during system reset).
Table 3-4. Output Signal States During System Reset
Interface
Signal
State During Reset
DDR Memory
MBA[2:0]
High-Z
DDR Memory
MA[15:0]
High-Z
DDR Memory
MWE
High-Z
DDR Memory
MRAS
High-Z
DDR Memory
MCAS
High-Z
DDR Memory
MCS[0:3]
High-Z
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-20
Freescale Semiconductor
Signal Descriptions
Table 3-4. Output Signal States During System Reset (continued)
Interface
Signal
State During Reset
Driven1
DDR Memory
MCKE[0:3]
DDR Memory
MCK[0:5], MCK[0:5]
DDR Memory
MODT[0:3]
PCI Express/
Serial RapidIO
SD_TX[7:0], SD_TX[7:0]
High-Z
PCI Express/
Serial RapidIO
SD_PLL_TPD
High-Z
Analog
SD_PLL_TPA
Driven
TSEC1
TSEC1_TX_EN
Driven Low
TSEC1
TSEC1_TX_ER
High-Z
TSEC1
TSEC1_GTX_CLK
High-Z
TSEC2
TSEC2_TX_EN
TSEC2
TSEC2_TXD[5:6]
Input—reset config (test only)2
TSEC2
TSEC2_GTX_CLK
High-Z
TSEC3
TSEC3_TX_EN
TSEC3
TSEC3_GTX_CLK
TSEC3
TSEC3_TXD[3]
TSEC3/TSEC4
TSEC3_TXD[6:7]
/TSEC4_TXD[2:3]
TSEC3/TSEC4
TSEC3_TX_ER
/TSEC4_TX_EN
TSEC4
Driven Toggling
Driven Low
Driven Low
Driven Low
High-Z
Input—reset config (test only)2
Input—reset config
Driven Low
TSEC4_GTX_CLK
High-Z
LBC
LCLK[0:2]
High-Z
LBC
LCKE
High-Z
LBC
LCS[0:4]
High-Z
LBC
DMA_DACK2/LCS6
DMA_DDONE2/LCS7
High-Z
DMA
DMA_DACK[0:1]
DMA
DMA_DACK2/LCS6
DMA_DDONE2/LCS7
High-Z
DMA
DMA_DDONE[0:1]
High-Z
PIC
IRQ8
PIC
IRQ_OUT
High-Z
Dual UART
UART_SOUT[0:1]
High-Z
Dual UART
UART_RTS[0:1]
High-Z
Input—reset config (test only)3
Driven (test only)2
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
3-21
Signal Descriptions
Table 3-4. Output Signal States During System Reset (continued)
Interface
Signal
System Control
HRESET_REQ
System Control
CKSTP_OUT
State During Reset
Input—reset config (test only)2
High-Z
Debug
TRIG_OUT/READY
Input—reset config (test only)2
Debug
MSRCID[2:4]
Input—reset config (test only)2
Debug
MDVAL
Power Mgmt
Clock
GPOUT
JTAG
ASLEEP
CLK_OUT
High-Z
Input—reset config (test only)2
Driven Toggling
GPOUT[24:31]
High-Z
TDO
Driven
1
Driven according to DRAM type. See Section 4.4.3.8, “DDR SDRAM Type,” on page 4-16
for specific voltage levels.
2 Test-mode input during reset; must not be pulled low.
3 Test-mode input during reset; see the MPC8548E Integrated Processor Hardware
Specifications for details.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
3-22
Freescale Semiconductor
Chapter 4
Reset, Clocking, and Initialization
This chapter describes the reset, clocking, and some overall initialization of the MPC8548E, including a
definition of the reset configuration signals and the options they select. Additionally, the configuration,
control, and status registers are described. Note that other chapters in this book may describe specific
aspects of initialization for individual blocks.
4.1
Overview
The reset, clocking, and control signals provide many options for the operation of the MPC8548E.
Additionally, many modes are selected with reset configuration signals during a hard reset (assertion of
HRESET).
4.2
External Signal Descriptions
Table 4-1 summarizes the external signals described in this chapter. Table 4-2 and Table 4-3 have detailed
signal descriptions, but Table 4-1 contains references to additional sections that contain more information.
Table 4-1. Signal Summary
Description
References
(Section/Page)
Signal
I/O
HRESET
I
Hard reset input. Causes a power-on reset (POR) sequence.
HRESET_REQ
O
Hard reset request output. An internal block requests that HRESET be asserted.
SRESET
I
Soft reset input. Causes mcp assertion to the core
READY
O
The MPC8548E has completed the reset operation and is not in a power-down (nap,
doze or sleep) or debug state.
SYSCLK
I
Primary clock input to the MPC8548E
4.4.4.1/4-25
RTC
I
Real time clock input
4.4.4.4/4-27
SD_REF_CLK/
SD_REF_CLK
I
SERDES high-speed interface reference clock
4.4.4.2/4-26
4.4.1.2/4-8
—
4.4.1.1/4-8
4.4.2/4-9
The following sections describe the reset and clock signals in detail.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
4-1
Reset, Clocking, and Initialization
4.2.1
System Control Signals
Table 4-2 describes some of the system control signals of the MPC8548E. Section 4.4.3, “Power-On Reset
Configuration,” describes the signals that also function as reset configuration signals. Note that the
CKSTP_IN and CKSTP_OUT signals are described in Chapter 20, “Global Utilities.”
Table 4-2. System Control Signals—Detailed Signal Descriptions
Signal
I/O
Description
HRESET
I
Hard reset. Causes the MPC8548E to abort all current internal and external transactions and set all
registers to their default values. HRESET may be asserted completely asynchronously with respect to
all other signals.
State Asserted/Negated—See Chapter 3, “Signal Descriptions,” and Section 4.4.3, “Power-On
Meaning
Reset Configuration,” for more information on the interpretation of the other MPC8548E
signals during reset.
Timing Assertion/Negation—The MPC8548E Integrated Processor Hardware Specifications gives
specific timing information for this signal and the reset configuration signals.
HRESET_REQ
O
Hard reset request. Indicates to the board (system in which the MPC8548E is embedded) that a
condition requiring the assertion of HRESET has been detected.
State Asserted—A watchdog timer, a RapidIO command, a boot sequencer failure (see
Meaning
Section 11.4.5, “Boot Sequencer Mode”), or has triggered a request for hard reset.
Negated—Indicates no reset request.
Timing Assertion/Negation—May occur any time, synchronous to the core complex bus clock. Once
asserted, HRESET_REQ does not negate until HRESET is asserted.
SRESET
I
Soft reset. Causes a machine check interrupt to the e500 core. Note that if the e500 core is not
configured to process machine check interrupts, the assertion of SRESET causes a core checkstop.
SRESET need not be asserted during a hard reset.
State Asserted—Asserting SRESET causes a machine check interrupt (edge sensitive) to the
Meaning
e500 core. SRESET has no effect while HRESET is asserted. However, the POR
sequence is paused if SRESET is asserted during POR.
Timing Assertion—May occur at any time, asynchronous to any clock.
Negation—Must be asserted for at least two CCB_clk cycles.
READY
O
Ready. Multiplexed with TRIG_OUT and QUIESCE. See Chapter 22, “Debug Features and Watchpoint
Facility,” for more information on TOSR and TRIG_OUT.
State Asserted—Indicates that the MPC8548E has completed the reset operation and is not in a
Meaning
power-down state (nap, doze, or sleep) when TOSR[SEL] equals 0b000. See
Section 4.4.2, “Power-On Reset Sequence,” for more information.
Timing Assertion/Negation—Initial assertion of READY after reset is synchronous with SYSCLK.
Subsequent assertion/negation due to power down modes occurs asynchronously.
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4.2.2
Clock Signals
Table 4-3 describes the overall clock signals of the MPC8548E. Note that some clock signals are specific
to blocks within the MPC8548E, and although some of their functionality is described in Section 4.4.4,
“Clocking,” they are defined in detail in their respective chapters.
Note that there is also a CLK_OUT signal in the MPC8548E; the signal driven on the CLK_OUT pin is
selectable and described in Section 20.4.1.23, “Clock Out Control Register (CLKOCR).”
Table 4-3. Clock Signals—Detailed Signal Descriptions
Signal
I/O
Description
SYSCLK
I
System clock/PCI clock (SYSCLK/PCI_CLK). SYSCLK is the primary clock input to the MPC8548E. It is the
clock source for the e500 core and for all devices and interfaces that operate synchronously with the core. It is
multiplied up with a phased-lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform
clock), which is used by virtually all of the synchronous system logic, including the L2 cache, the DDR SDRAM
and local bus memory controllers, and other internal blocks such as the DMA and interrupt controllers. The CCB
clock, in turn, feeds the PLL in the e500 core and the PLL that creates the local bus memory clocks.
When the PCI1/PCI-X interface is used, SYSCLK also functions as the PCI_CLK signal. Note that this is true
whether the MPC8548E is in agent or host mode. The MPC8548E does not provide a separate PCI_CLK output
in host mode.
Timing Assertion/Negation—See the MPC8548E Integrated Processor Hardware Specifications for specific
timing information for this signal.
RTC
I
Real time clock. May be used (optionally) to clock the time base of the e500 core. The RTC timing specifications
are given in the MPC8548E Integrated Processor Hardware Specifications, but the maximum frequency should
be less than one-quarter of the CCB frequency. See Section 4.4.4.4, “Real Time Clock.” This signal can also be
used (optionally) to clock the global timers in the programmable interrupt controller (PIC).
Timing Assertion/Negation—See the MPC8548E Integrated Processor Hardware Specifications for specific
timing information for this signal.
4.3
Memory Map/Register Definition
This section describes the configuration and control registers that control access to the configuration space
and to the boot code as well as guidelines for accessing these regions. It also contains a brief description
of the boot sequencer which may be used to initialize configuration registers or memory before the CPU
is released to boot.
4.3.1
Local Configuration Control
Table 4-4 shows the memory map for local configuration control registers.
In this table and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
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•
•
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Table 4-4. Local Configuration Control Register Map
Local Memory
Offset (Hex)
Register
Access
Reset
Section/Page
0x0_0000
CCSRBAR—Configuration, control, and status registers base
address register
R/W
0x000F_F700
4.3.1.1.2/4-5
0x0_0008
ALTCBAR—Alternate configuration base address register
R/W
0x0000_0000
4.3.1.2.1/4-6
0x0_0010
ALTCAR—Alternate configuration attribute register
R/W
0x0000_0000
4.3.1.2.1/4-6
0x0_0020
BPTR—Boot page translation register
R/W
0x0000_0000
4.3.1.3.1/4-7
4.3.1.1
Accessing Configuration, Control, and Status Registers
The configuration, control, and status registers are memory mapped. The set of configuration, control, and
status registers occupies a 1-Mbyte region of memory. Their location is programmable using the CCSR base
address register (CCSRBAR). The default base address for the configuration, control, and status registers
is 0xFF70_0000 (CCSRBAR = 0x000F_F700). CCSRBAR itself is part of the local access block of CCSR
memory, which begins at offset 0x0 from CCSRBAR. Because CCSRBAR is at offset 0x0 from the
beginning of the local access registers, CCSRBAR always points to itself. The contents of CCSRBAR are
broadcast internally in the MPC8548E to all functional units that need to be able to identify or create
configuration transactions.
4.3.1.1.1
Updating CCSRBAR
Updates to CCSRBAR that relocate the entire 1-Mbyte region of configuration, control, and status
registers require special treatment. The effect of the update must be guaranteed to be visible by the
mapping logic before an access to the new location is seen. To make sure this happens, these guidelines
should be followed:
• CCSRBAR should be updated during initial configuration of the device when only one host or
controller has access to the device.
– If the boot sequencer is being used to initialize, it is recommended that the boot sequencer
set CCSRBAR to its desired final location.
– If an external host on PCI or RapidIO is configuring the device, it should set CCSRBAR to
the desired final location before the e500 core is released to boot.
– If the e500 core is initializing the device, it should set CCSRBAR to the desired final
location before enabling other I/O devices to access the device.
• When the e500 core is writing to CCSRBAR, it should use the following sequence:
– Read the current value of CCSRBAR using a load word instruction followed by an isync.
This forces all accesses to configuration space to complete.
– Write the new value to CCSRBAR.
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– Perform a load of an address that does not access configuration space or the on-chip SRAM,
but has an address mapping already in effect (for example, boot ROM). Follow this load
with an isync.
– Read the contents of CCSRBAR from its new location, followed by another isync.
4.3.1.1.2
Configuration, Control, and Status Base Address Register (CCSRBAR)
Figure 4-1 shows the fields of CCSRBAR.
Offset 0x0_0000
Access: Read/Write
0
7
R
8
23 24
—
W
Reset 0
0
0
0
0
31
BASE_ADDR
0
0
0
0
0
0
0
1
1
1
1
1
1
—
1
1
0
1
1
1
0
0
0
0
0
0
0
0
Figure 4-1. Configuration, Control, and Status Register Base Address Register (CCSRBAR)
Table 4-5 defines the bit fields of CCSRBAR.
Table 4-5. CCSRBAR Bit Settings
Bits
Name
0–7
—
8–23
24–31
4.3.1.2
Description
Write reserved, read = 0.
BASE_ADDR Identifies the16 most-significant address bits of the window used for configuration accesses. The base
address is aligned on a 1-Mbyte boundary.
—
Write reserved, read = 0
Accessing Alternate Configuration Space
An alternate configuration space can be accessed by configuring the ALTCBAR and ALTCAR registers.
These are intended to be used with the boot sequencer to allow the boot sequencer to access an alternate
1-Mbyte region of configuration space. By loading the proper boot sequencer command in the serial ROM,
the base address in the ALTCBAR can be combined with the 20 bits of address offset supplied from the
serial ROM to generate a 36-bit address that is mapped to the target specified in ALTCAR. Thus, by
configuring these registers, the boot sequencer has access to the entire memory map, one 1-Mbyte block
at a time. See Section 11.4.5, “Boot Sequencer Mode,” for more information.
NOTE
The enable bit in the ALTCAR register should be cleared either by the boot
sequencer or by the boot code that executes after the boot sequencer has
completed its configuration operations. This prevents problems with
incorrect mappings if subsequent configuration of the local access windows
uses a different target mapping for the address specified in ALTCBAR.
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4.3.1.2.1
Alternate Configuration Base Address Register (ALTCBAR)
Figure 4-2 shows the fields of ALTCBAR.
Offset 0x0_0008
Access: Read/Write
0
7
R
8
23 24
—
W
31
BASE_ADDR
Reset
—
All zeros
Figure 4-2. Alternate Configuration Base Address Register (ALTCBAR)
Table 4-6 defines the bit fields of ALTCBAR.
Table 4-6. ALTCBAR Bit Settings
Bits
Name
0–7
—
8–23
Description
Write reserved, read = 0
BASE_ADDR Identifies the16 most significant address bits of an alternate window used for configuration accesses.
24–31
—
4.3.1.2.2
Write reserved, read = 0
Alternate Configuration Attribute Register (ALTCAR)
Figure 4-3 shows the fields of ALTCAR.
Offset 0x0_0010
0
R
W
Access: Read/Write
1
EN
7
8
—
Reset
11 12
31
TRGT_ID
—
All zeros
Figure 4-3. Alternate Configuration Attribute Register (ALTCAR)
Table 4-7 defines ALTCAR fields.
Table 4-7. ALTCAR Bit Settings
Bits
Name
0
EN
Enable for a second configuration window. Like CCSRBAR, it has a fixed size of 1 Mbyte.
0 Second configuration window is disabled.
1 Second configuration window is enabled.
1–7
—
Write reserved, read = 0
8–11
12–31
Description
TRGT_I Identifies the device ID to target when a transaction hits in the 1-Mbyte address range defined by the second
D
configuration window.
1001–1010Reserved
0000 PCI1/PCI-X interface
1011 Security
0001 PCI2
1100 RapidIO
0010 PCI Express
1101 Reserved
0011 Reserved
1110 Reserved
0100 Local bus controller
1111 Local memory —DDR SDRAM and on-chip
0101–1011 Reserved
SRAM
1000 Configuration, control, status registers
—
Write reserved, read = 0
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4.3.1.3
Boot Page Translation
When the e500 core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. The
core begins execution with the instruction at effective address 0x0_FFFF_FFFC. To get this instruction,
the core’s first instruction fetch is a burst read of boot code from effective address 0x0_FFFF_FFE0. For
systems in which the boot code resides at a different address, the MPC8548E provides boot page
translation capability. Boot page translation is controlled by the boot page translation register (BPTR).
The boot sequencer can enable boot page translation, or the boot page translation can be set up by an
external host when the MPC8548E is configured to be in boot holdoff mode. If translation is to be
performed to a page outside the default boot ROM address range defined in the MPC8548E (8 Mbytes at
0x0_FF80_0000 to 0x0_FFFF_FFFF as defined in Section 4.4.3.3, “Boot ROM Location”), the external
host or boot sequencer must then also set up a local access window to define the routing of the boot code
fetch to the target interface that contains the boot code, because the BPTR defines only the address
translation, not the target interface. See Section 2.1, “Local Memory Map Overview and Example,” and
Section 11.4.5, “Boot Sequencer Mode,” for more information.
4.3.1.3.1
Boot Page Translation Register (BPTR)
Figure 4-4 shows the fields of BPTR.
Offset 0x0_0020
0
R
W
Access: Read/Write
1
7
EN
8
31
—
BOOT_PAGE
Reset
All zeros
Figure 4-4. Boot Page Translation Register (BPTR)
Table 4-8 describes BPTR bit settings.
Table 4-8. BPTR Bit Settings
Bits
Name
0
EN
Boot page translation enable
0 Boot page is not translated.
1 Boot page is translated as defined in the BPTR[BOOT_PAGE] parameter.
1–7
—
Write reserved, read = 0
8–31
4.3.2
Description
BOOT_PAGE Translation for boot page. If enabled, the high order 24 bits of accesses to 0x0_FFFF_Fnnn are
replaced with this value.
Boot Sequencer
The boot sequencer is a DMA engine that accesses a serial ROM on the I2C interface and writes data to
CCSR memory or the memory space pointed to by the alternate configuration base address register
(ALTCBAR). See Section 4.3.1.2, “Accessing Alternate Configuration Space.” The boot sequencer is
enabled by reset configuration pins as described in Section 4.4.3.7, “Boot Sequencer Configuration.” If the
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boot sequencer is enabled, the e500 core is held in reset until the boot sequencer has completed its
operation. For more details, see Section 11.4.5, “Boot Sequencer Mode,” in the I2C chapter.
4.4
Functional Description
This section describes the various ways to reset the MPC8548E device, the POR configurations, and the
clocking on the device.
4.4.1
Reset Operations
The MPC8548E has reset input signals for hard and soft reset operation.
4.4.1.1
Soft Reset
Assertion of SRESET causes a machine check interrupt to the e500 core. When this occurs, the soft reset
flag is recorded in the machine check summary register (MCPSUMR) in the global utilities block so that
software can identify the machine check as a soft reset condition. See the PowerPC™ e500 Core Family
Reference Manual for more information on the machine check interrupt and Section 20.4.1.14, “Machine
Check Summary Register (MCPSUMR),” for more information on the setting of the soft reset flag. Note
that if SRESET is asserted before the e500 core is configured to handle a machine check interrupt, a core
checkstop condition occurs, which causes CKSTP_OUT to assert.
4.4.1.2
Hard Reset
The MPC8548E can be completely reset by the assertion of the HRESET input. The assertion of this signal
by external logic is the equivalent of a POR and causes the sequence of events described in Section 4.4.2,
“Power-On Reset Sequence.”
Refer to the MPC8548E Integrated Processor Hardware Specifications for the timing requirements for
HRESET assertion and negation.
The hard reset request output signal (HRESET_REQ) indicates to external logic that a hard reset is being
requested by hardware or software or a RapidIO device. Hardware causes this signal to assert for a boot
sequencer failure (see Section 11.4.5, “Boot Sequencer Mode,” and Section 11.4.5.2, “EEPROM Data
Format”) or when the e500 watchdog timer is configured to cause a reset request when it expires. Software
may request a hard reset by setting a bit in a global utilities register; see Section 20.4.1.18, “Reset Control
Register (RSTCR).” A RapidIO device causes this signal to assert if it sends four consecutive RapidIO link
maintenance reset commands without any other intervening packets or control symbols, except idle control
symbols.
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4.4.2
Power-On Reset Sequence
The POR sequence for the MPC8548E is as follows:
1. Power is applied to meet the specifications in the MPC8548 Integrated Processor Hardware
Specifications.
2. The system asserts HRESET and TRST, causing all registers to be initialized to their default states
and most I/O drivers to be three-stated (some clock, clock enabled, and system control signals are
active).
3. The system applies a stable SYSCLK signal and stable PLL configuration inputs, and the device
PLL begins locking to SYSCLK.
4. System negates HRESET after its required hold time and after POR configuration inputs have been
valid for at least 4 SYSCLK cycles.
NOTE:
If the JTAG signals are not used, refer to the MPC8548E Integrated
Processor Hardware Specifications for proper connection
recommendations.
There is no need to assert the SRESET signal when HRESET is asserted. If
SRESET is asserted on negation of HRESET, the POR sequence will be
paused after the e500 core PLL is locked and before the e500 reset is
negated. The POR sequence will be resumed when SRESET is negated.
5. MPC8548E enables I/O drivers.
6. The MPC8548E PCI1/PCI-X interface can assert DEVSEL in response to configuration cycles.
7. The e500 PLL configuration inputs are applied, allowing the e500 PLL to begin locking to the
device clock (the CCB clock).
8. The CCB clock is cycled for approximately 50 μs to lock the e500 PLL.
9. The internal hard reset to the e500 core is negated and soft resets are negated to the PLLs and other
remaining I/O blocks. The PLLs begin to lock.
10. When PLL locking is completed, the boot sequencer is released, causing it to load configuration
data from serial ROMs, if enabled, as described in Section 4.4.3.7, “Boot Sequencer
Configuration.”
11. When the boot sequencer completes, the RapidIO interface begins training, the PCI interface is
released to accept external requests, and the boot vector fetch by the e500 core is allowed to
proceed unless processor booting is further held off by POR configuration inputs as described in
Section 4.4.3.6, “CPU Boot Configuration.” The MPC8548E is now in its ready state.
12. The ASLEEP signal negates synchronized to a rising edge of SYSCLK, indicating the ready state.
The ready state is also indicated by the assertion of READY/TRIG_OUT if TOSR[SEL] = 000. In
this case, READY is asserted with the same rising edge of SYSCLK, to indicate that the device has
reached its ready state. See Section 22.3.4.1, “Trigger Out Source Register (TOSR),” for more
information on this register.
Asserting READY allows external system monitors to know basic device status, for example,
exactly when it emerges from reset, or if the device is in a low-power mode. For more information
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on the debug functions of TRIG_OUT, see Section 22.3.4, “Trigger Out Function.” For more
information about power management states, see Section 20.4.1, “Register Descriptions.”
Figure 4-5 shows a timing diagram of the POR sequence.
HRESET
(high impedance)
HRESET_REQ
SYSCLK
TRST
SRESET
PLL Configs
POR Configs
(High Impedance)
ASLEEP
(High Impedance)
READY1
1
Multiplexed with TRIG_OUT.
Figure 4-5. Power-On Reset Sequence
4.4.3
Power-On Reset Configuration
Various device functions are initialized by sampling certain signals during the assertion of HRESET. The
values of all these signals are sampled into registers while HRESET is asserted. These inputs are to be
pulled high or low by external resistors. During HRESET, all other signal drivers connected to these
signals must be in the high-impedance state.
Most POR configuration signals have internal pull-up resistors so that if the desired setting is high, there
is no need for a pull-up resistor on the board. Other POR configuration signals do not use pull-ups and
therefore must be pulled high or low. Refer to the MPC8548E Integrated Processor Hardware
Specifications for proper resistor values to be used for pulling POR configuration signals high or low.
This section describes the functions and modes configured by POR configuration signals. Note that many
reset configuration settings are accessible to software through the following read-only memory-mapped
registers described in Chapter 20, “Global Utilities”:
• POR PLL status register (PORPLLSR)
• POR boot mode status register (PORBMSR)
• POR I/O impedance status and control register (PORIMPSCR)
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•
•
•
POR device status register (PORDEVSR)
POR debug mode status register (PORDBGMSR)
General-purpose POR configuration register (GPPORCR)—Reports the value on LAD[0:31]
during POR (can be used to external system configuration)
NOTE
In the following tables, the binary value 0b0 represents a signal pulled down
to GND and a value of 0b1 represents a signal pulled up to VDD, regardless
of the sense of the functional signal name on the signal.
4.4.3.1
System PLL Ratio
The system PLL inputs, shown in Table 4-9, establish the clock ratio between the SYSCLK input and the
platform clock used by the MPC8548E. The platform clock, also called the CCB clock, drives the L2
cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB). There is no default value for
this PLL ratio; these signals must be pulled to the desired values. See Section 4.4.4.2.1, “Minimum
Frequency Requirements,” for optimal selection of this ratio with regard to available high-speed interface
widths and frequencies. Note that the values latched on these signals during POR are accessible in the
PORPLLSR (POR PLL status register), as described in Section 20.4.1.1, “POR PLL Status Register
(PORPLLSR).”
Table 4-9. CCB Clock PLL Ratio
Functional Signals
Reset Configuration
Name
Value
(Binary)
CCB Clock : SYSCLK Ratio
LA[28:31]
cfg_sys_pll[0:3]
0000
16 : 1
0001
Reserved
0010
2:1
0011
3:1
0100
4:1
0101
5:1
0110
6:1
0111
Reserved
1000
8:1
1001
9:1
1010
10 : 1
1011
Reserved
1100
12 : 1
1101
20: 1
1110
Reserved
1111
Reserved
No Default
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4.4.3.2
e500 Core PLL Ratio
Table 4-10 describes the e500 core clock PLL inputs that program the core PLL and establish the ratio
between the e500 core clock and the e500 core complex bus (CCB) clock. There is no default value for
this PLL ratio; these signals must be pulled to the desired values. Note that the values latched on these
signals during POR are accessible through the memory-mapped PORPLLSR, as described in
Section 20.4.1.1, “POR PLL Status Register (PORPLLSR),” and also in the e500 core HID1 register, as
described in Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”
Table 4-10. e500 Core Clock PLL Ratios
Functional Signals
Reset Configuration Name Value (Binary)
LBCTL, LALE, LGPL2/LOE/LSDRAS
cfg_core_pll[0:2]
No Default
4.4.3.3
e500 Core: CCB ClockRatio
000
4:1
001
9 : 2 (4.5:1)
010
1:1
011
3 : 2 (1.5 : 1)
100
2:1
101
5 : 2 (2.5:1)
110
3:1
111
7 : 2 (3.5 : 1)
Boot ROM Location
The MPC8548E defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000
to 0x0_FFFF_FFFF. However, which peripheral interface handles these boot ROM accesses can be
selected at power on.
The boot ROM location inputs, shown in Table 4-11, select the physical location of boot ROM. Accesses
to the boot vector and the default boot ROM region of the local address map are directed to the interface
specified by these inputs.
Table 4-11. Boot ROM Location
Functional Signals
Reset Configuration Name
Value
(Binary)
TSEC1_TXD[6:4]
cfg_rom_loc[0:2]
000
PCI1/PCI-X
001
DDR SDRAM
010
PCI2
0111
Serial RapidIO
100
PCI Express
101
Local bus GPCM—8-bit ROM
110
Local bus GPCM—16-bit ROM
111
Local Bus GPCM—32-bit ROM (default)
Default (111)
1
Meaning
When booting from serial RapidIO, outbound ATMU window 0 must be used. See Section 17.6.7, “RapidIO
Implementation Space—ATMU Registers,” for information on configuring this window.
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Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in Section 20.4.1.2, “POR Boot Mode Status
Register (PORBMSR).”
See Section 2.1, “Local Memory Map Overview and Example,” for an example memory map that relies
on the default boot ROM values. Also, see Section 4.3.1.3.1, “Boot Page Translation Register (BPTR),”
for information on translation of the boot page.
4.4.3.4
Host/Agent Configuration
The host/agent reset configuration inputs, shown in Table 4-12, configure the MPC8548E to act as a host
or as an agent of a master on another interface. In host mode, the MPC8548E is immediately enabled to
master transactions to the RapidIO and PCI/X interfaces. If the MPC8548E is an agent on the PCI/X, PCI
Express, or RapidIO interfaces, then the MPC8548E is disabled from mastering transactions on that
interface until the external host enables it to do so. The external host does this by setting the control
registers of the MPC8548E’s interfaces appropriately. See details in the PCI, PCI Express, and RapidIO
programming models described in Chapter 16, “PCI/PCI-X Bus Interface,” Chapter 18, “PCI Express
Interface Controller,” and Chapter 17, “Serial RapidIO Interface,” respectively.
Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in Section 20.4.1.2, “POR Boot Mode Status
Register (PORBMSR).”
Table 4-12. Host/Agent Configuration
Functional Signals
Reset Configuration
Name
Value
(Binary)
LWE[1:3]/LBS[1:3]
cfg_host_agt[0:2]
000
MPC8548E acts as an agent (endpoint) of both a PCI Express and a
serial RapidIO device. It acts as host for PCI1/PCI-X.
x01
MPC8548E acts as an agent of a serial RapidIO host. It acts as host
for PCI Express and PCI1/PCI-X.
010
MPC8548E acts as an endpoint of a PCI Express host. It acts as host
for serial RapidIO and PCI1/PCI-X.
011
Reserved
100
MPC8548E acts as an agent of both a PCI1/PCI-X and a serial
RapidIO device. It acts as the host processor/root complex for PCI
Express.
110
MPC8548E acts as an agent of a PCI1/PCI-X host. It acts as the host
processor/root complex for PCI Express and as host for serial
RapidIO.
111
MPC8548E acts as the host processor/root complex (default).
Default (111)
Meaning
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Reset, Clocking, and Initialization
4.4.3.5
I/O Port Selection
The MPC8548E can be configured with different I/O ports active. Table 4-13 shows the configuration of
I/O ports and bit rates (and required reference clocks) that are possible for the Serial RapidIO and PCI
Express interfaces.
NOTE
In addition to the combinations shown below, it is important to note that the
PCI2 interface is unavailable and powered down whenever Serial RapidIO
is in use.
Table 4-13. I/O Port Selection
Functional
Signal
Reset Configuration
Name
Value
(Binary)
TSEC1_TXD[3:1]
cfg_IO_ports[0:2]
000
Reserved
001
Reserved
010
Reserved
011
Serial RapidIO x4 (2.5 Gbps); PCI Express x4 (2.5 Gbps)
(PCI2 is automatically disabled)
100-MHz reference clock
Serial RapidIO:
RX lane[0:3] → SD_RX[4:7]
TX lane[0:3] → SD_TX[4:7]
PCI Express:
RX lane[0:3] → SD_RX[0:3]
TX lane[0:3] → SD_TX[0:3]
100
Serial RapidIO x4 (1.25 Gbps); PCI Express x4 (2.5 Gbps)
(PCI2 is automatically disabled)
100-MHz reference clock
Serial RapidIO:
RX lane[0:3] → SD_RX[4:7]
TX lane[0:3] → SD_TX[4:7]
PCI Express:
RX lane[0:3] → SD_RX[0:3]
TX lane[0:3] → SD_TX[0:3]
101
Serial RapidIO x4 (3.125 Gbps)
(PCI2 is automatically disabled)
125-MHz reference clock
RX lane[0:3] → SD_RX[4:7]
TX lane[0:3] → SD_TX[4:7]
110
Serial RapidIO x4 (1.25 Gbps)
(PCI2 is automatically disabled)
100-MHz reference clock
RX lane[0:3] → SD_RX[4:7]
TX lane[0:3] → SD_TX[4:7]
111
PCI Express x8 (2.5 Gbps)
100-MHz reference clock
RX lane[0:7] → SD_RX[0:7]
TX lane[0:7] → SD_TX[0:7]
Default (111)
Meaning
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Reset, Clocking, and Initialization
4.4.3.6
CPU Boot Configuration
The CPU boot configuration input, shown in Table 4-14, specifies the boot configuration mode. If LA27
is sampled low at reset, the e500 core is prevented from fetching boot code until configuration by an
external master is complete. The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in
the ECM CCB port configuration register (EEBPCR). See Section 8.2.1.2, “ECM CCB Port Configuration
Register (EEBPCR),” for more information.
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in Section 20.4.1.2, “POR Boot Mode Status
Register (PORBMSR).”
Note also that the value latched on this signal during POR affects the PCI agent lock mode (See
Section 16.3.2.19, “PCI Bus Function Register (PBFR).”) and the PCI Express Configuration Ready
Register (See Section 18.3.10.18, “Configuration Ready Register—0x4B0.”)
Table 4-14. CPU Boot Configuration
Functional
Signal
Reset Configuration
Name
Value
(Binary)
LA27
cfg_cpu_boot
0
CPU boot holdoff mode. The e500 core is prevented from booting until
configured by an external master.
1
The e500 core is allowed to boot without waiting for configuration by an
external master (default).
Default (1)
4.4.3.7
Meaning
Boot Sequencer Configuration
The boot sequencer configuration options, shown in Table 4-15, allow the boot sequencer to load
configuration data from the serial ROM located on the I2C1 port before the host tries to configure the
MPC8548E. These options also specify normal or extended I2C addressing modes. See Section 11.4.5,
“Boot Sequencer Mode,” for more information on the boot sequencer.
Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in Section 20.4.1.2, “POR Boot Mode Status
Register (PORBMSR).”
Table 4-15. Boot Sequencer Configuration
Functional
Signal
LGPL3/LSDCAS,
LGPL5
Reset Configuration Value
Name
(Binary)
cfg_boot_seq[0:1]
Meaning
00
Reserved
01
Normal I2C addressing mode is used. Boot sequencer is enabled and
loads configuration information from a ROM on the I2C interface. A valid
ROM must be present.
10
Extended I2C addressing mode is used. Boot sequencer is enabled and
loads configuration information from a ROM on the I2C1 interface. A valid
ROM must be present.
11
Boot sequencer is disabled. No I2C ROM is accessed (default).
Default (11)
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Reset, Clocking, and Initialization
NOTE
When the boot sequencer is enabled, the processor core will be held in reset
and thus prevented from fetching boot code until the boot sequencer has
completed its task, regardless of the state of the CPU boot configuration
signal described in Section 4.4.3.6, “CPU Boot Configuration.”
4.4.3.8
DDR SDRAM Type
DDR1 requires a different voltage level from DDR2. Table 4-16 describes the configuration of the DDR
SDRAM type.
Table 4-16. DDR DRAM Type
Functional
Signal
Reset Configuration
Value
Name
(Binary)
TSEC2_TXD1,
TSEC2_TX_ER
cfg_dram_type[0:1]
00
Reserved
01
DDR1
2.5V, CKE low at reset
10
Reserved
11
DDR2
1.8V, CKE low at reset (default)
Default (11)
4.4.3.9
Meaning
eTSEC1 and eTSEC2 Width
The eTSEC width input, shown in Table 4-17, selects standard versus reduced width for three-speed
Ethernet controller interfaces 1 and 2. Note that the value latched on this signal during POR is accessible
through the memory-mapped PORDEVSR (POR device status register) described in Section 20.4.1.4,
“POR Device Status Register (PORDEVSR).”
This input does not affect the width of the FIFO interface for eTSEC2, which is always an 8-bit FIFO
interface. For eTSEC1, however, this bit controls whether the interface is operating as a 16-bit FIFO or an
8-bit FIFO. Note that since the full-width FIFO interface (16-bits) requires the pins from both eTSEC1 and
eTSEC2 controllers, eTSEC2 is unavailable if eTSEC1 is in 16-bit FIFO mode.
Table 4-17. eTSEC1/eTSEC2 Width Configuration
Functional Reset Configuration
Value
Signal
Name
(Binary)
EC_MDC
Default (1)
cfg_tsec_1_2_reduce
Meaning
0
eTSEC1 and eTSEC2 Ethernet interfaces operate in reduced pin mode, either
RTBI, RGMII, RMII, or in 8-bit FIFO mode.
1
eTSEC1 and eTSEC2 Ethernet interfaces operate in their standard width TBI,
GMII, MII. Or, if eTSEC1 is in FIFO mode, it operates as a 16-bit FIFO. eTSEC2
FIFO width is 8 bits regardless of this configuration setting.
(default)
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Reset, Clocking, and Initialization
NOTE
While the width of both interfaces eTSEC1 and eTSEC2 is controlled by
this one configuration input, the protocol (TBI, GMII, or FIFO) used by
each is separately controlled with other configuration inputs described in
Section 4.4.3.11, “eTSEC1 Protocol,” and Section 4.4.3.12, “eTSEC2
Protocol.”
4.4.3.10
eTSEC3 and eTSEC4 Width
The eTSEC3 width input, shown in Table 4-18, selects standard versus reduced width for three-speed
Ethernet controller interfaces 3 and 4. Note that the value latched on this signal during POR is accessible
through the memory-mapped PORDEVSR (POR device status register) described in Section 20.4.1.4,
“POR Device Status Register (PORDEVSR).”
The value of this configuration setting does not affect the width of the FIFO interface on eTSEC3, which
is always 8 bits.
Because eTSEC3 and eTSEC4 share pins, eTSEC3 must operate in reduced-pin-width mode in order for
eTSEC4 to be accessible. If eTSEC3 is not in reduced-pin-width mode, eTSEC4 is powered down.
Table 4-18. eTSEC3/eTSEC4 Width Configuration
Functional
Signal
Reset Configuration Value
Name
(Binary)
TSEC3_TXD[2] cfg_tsec_3_reduce
Default (1)
Meaning
0
eTSEC3 and eTSEC4 Ethernet interfaces operate in reduced mode, either
RTBI, RGMII or RMII.
1
eTSEC3 Ethernet interface operates in standard TBI, GMII, MII, or 8-bit FIFO
mode. eTSEC 4 is unavailable.
(default).
NOTE
While the width of both interfaces eTSEC3 and eTSEC4 is controlled by
this one configuration input, the protocol (TBI, GMII, or FIFO) used by
each is separately controlled with other configuration inputs described in
Section 4.4.3.13, “eTSEC3 Protocol,” and Section 4.4.3.14, “eTSEC4
Protocol.”
4.4.3.11
eTSEC1 Protocol
The eTSEC1 protocol inputs, shown in Table 4-19, select the protocol (FIFO, MII, GMII or TBI) used by
the eTSEC1 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in Section 20.4.1.4, “POR Device
Status Register (PORDEVSR).”
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Reset, Clocking, and Initialization
Table 4-19. eTSEC1 Protocol Configuration
Functional
Signal
Reset Configuration Value
Name
(Binary)
TSEC1_TXD[0],
TSEC1_TXD[7]
cfg_tsec1_prtcl[0:1]
Default (11)
4.4.3.12
Meaning
00
The eTSEC1 controller operates using 16-bit FIFO protocol (or 8-bit FIFO
protocol if configured in reduced mode as described in Section 4.4.3.9,
“eTSEC1 and eTSEC2 Width”).
01
The eTSEC1 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in Section 4.4.3.9, “eTSEC1 and
eTSEC2 Width”).
10
The eTSEC1 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in Section 4.4.3.9, “eTSEC1 and
eTSEC2 Width”).
11
The eTSEC1 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in Section 4.4.3.9, “eTSEC1 and
eTSEC2 Width”) (default).
eTSEC2 Protocol
The eTSEC2 protocol inputs, shown in Table 4-20, select the protocol (FIFO, MII, GMII or TBI) used by
the eTSEC2 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in Section 20.4.1.4, “POR Device
Status Register (PORDEVSR).”
Table 4-20. eTSEC2 Protocol Configuration
Functional Signal
TSEC2_TXD[0],
TSEC2_TXD[7]
Reset Configuration Value
Name
(Binary)
cfg_tsec2_prtcl[0:1]
00
The eTSEC2 controller operates using 8-bit FIFO protocol.
01
The eTSEC2 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in Section 4.4.3.9, “eTSEC1
and eTSEC2 Width”)
10
The eTSEC2 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in Section 4.4.3.9, “eTSEC1
and eTSEC2 Width”).
11
The eTSEC2 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in Section 4.4.3.9, “eTSEC1
and eTSEC2 Width”) (default).
Default (11)
4.4.3.13
Meaning
eTSEC3 Protocol
The eTSEC3 protocol inputs, shown in Table 4-21, select the protocol (FIFO, MII, GMII or TBI) used by
the eTSEC3 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in Section 20.4.1.4, “POR Device
Status Register (PORDEVSR).”
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Reset, Clocking, and Initialization
Table 4-21. eTSEC3 Protocol Configuration
Functional Signal
TSEC3_TXD[0],
TSEC3_TXD[1]
Reset Configuration Value
Name
(Binary)
cfg_tsec3_prtcl[0:1]
00
The eTSEC3 controller operates using 8-bit FIFO protocol.
01
The eTSEC3 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in Section 4.4.3.10, “eTSEC3
and eTSEC4 Width”)
10
The eTSEC3 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in Section 4.4.3.10, “eTSEC3
and eTSEC4 Width”).
11
The eTSEC3 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in Section 4.4.3.10, “eTSEC3
and eTSEC4 Width”) (default).
Default (11)
4.4.3.14
Meaning
eTSEC4 Protocol
The eTSEC4 protocol input, shown in Table 4-22, selects the protocol (RMII, RGMII or RTBI) used by
the eTSEC4 controller. Note that the value latched on this signal during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in Section 20.4.1.4, “POR Device
Status Register (PORDEVSR).”
Table 4-22. eTSEC4 Protocol Configuration
Functional Signal
TSEC4_TXD[0],
TSEC4_TXD[1]
Reset Configuration
Name
Value
(Binary)
cfg_tsec4_prtcl[0:1]
00
Reserved
01
The eTSEC4 controller operates using the RMII protocol.
10
The eTSEC4 controller operates using the RGMII protocol.
11
The eTSEC4 controller operates using the RTBI protocol (default).
Default (11)
4.4.3.15
Meaning
RapidIO Device ID
The RapidIO device ID inputs, shown in Table 4-23, specify the 3 lower-order bits of the device ID of the
MPC8548E as used by RapidIO hosts. Note that the 5 high-order RapidIO device ID bits cannot be set via
POR configuration inputs. They may be initialized via the boot sequencer or by the processor from boot
ROM or by the RapidIO discovery process.
Table 4-23. RapidIO Device ID
Functional Signals
Reset Configuration Name
Meaning
TSEC2_TXD2
cfg_device_ID5
Device ID used for RapidIO hosts
TSEC2_TXD3
cfg_device_ID6
Device ID used for RapidIO hosts
TSEC2_TXD4
cfg_device_ID7
Device ID used for RapidIO hosts
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Reset, Clocking, and Initialization
If configured as a RapidIO host, the upper-order device ID bits default to zeros. If configured as a RapidIO
agent, the upper-order device ID bits default to ones. Unconnected cfg_device_IDn inputs default to 1s
regardless of the host/agent mode configuration.
Note that the value latched on this signal at POR is accessible through the memory-mapped PORDEVSR
described in Section 20.4.1.4, “POR Device Status Register (PORDEVSR),” as well as the
memory-mapped BDIDCSR described in Section 17.6.1.12, “Base Device ID Command and Status
Register (BDIDCSR).”
4.4.3.16
RapidIO System Size
The RapidIO common transport specification defines two system sizes. The large size uses 16-bit source
and destination IDs allowing for 65,536 devices, while the small size uses 8-bit source and destination IDs,
supporting 256 devices.
The RapidIO system size configuration shown in Table 4-24 specifies which system size is to be used by
the RapidIO controller on the MPC8548E.
Note that the system size setting determined by this signal at POR is accessible through the
memory-mapped PORDEVSR described in Section 20.4.1.4, “POR Device Status Register
(PORDEVSR),” as well as the memory-mapped PEFCAR described in Section 17.6.1.5, “Processing
Element Features Capability Register (PEFCAR).”
Table 4-24. RapidIO System Size
Functional Signals
Reset Configuration Name
Value
(Binary)
LGPL0
cfg_rio_sys_size
0
Large system size (up to 65,536 devices)
1
Small system size (up to 256 devices) (default)
Default (1)
4.4.3.17
Meaning
PCI Clock Selection
The PCI clock source inputs, shown in Table 4-25 and Table 4-26 specify the clock mode (synchronous or
asynchronous) for the PCI1/PCI-X and PCI2 interfaces. See Section 4.4.4.1, “System Clock/PCI Clock,”
for more information. Note that the value latched on this signal during POR is accessible through the
memory-mapped PORPLLSR (POR PLL status register) described in Section 20.4.1.1, “POR PLL Status
Register (PORPLLSR).”
NOTE
When in synchronous mode, the maximum PCI-X frequency is 110 MHz.
Table 4-25. PCI1/PCI-X Clock Select
Functional
Signal
PCI2_GNT[3]
Default (1)
Reset Configuration Value
Name
(Binary)
cfg_pci1_clk
Meaning
0
Asynchronous mode. PCI1_CLK is used as the clock for the PCI1/PCI-X
interface
1
Synchronous mode. SYSCLK is used as the clock for the PCI1/PCI-X interface.
(default)
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Reset, Clocking, and Initialization
Table 4-26. PCI2 Clock Select
Functional
Signal
Reset Configuration Value
Name
(Binary)
cfg_pci2_clk
PCI2_GNT[4]
Default (1)
4.4.3.18
Meaning
0
Asynchronous mode. PCI2_CLK is used as the clock for the PCI2 interface
1
Synchronous mode. SYSCLK is used as the clock for the PCI2 interface.
(default).
PCI Speed Configuration
The PCI speed configuration inputs, shown in Table 4-27 and Table 4-28, configure internal logic for
proper operation with the PCI clock frequencies in use. The default setting is appropriate for PCI operating
above 33 MHz or for PCI-X operating above 66 MHz. For low speed operation (PCI at or below 33 MHZ
or PCI-X at 66 MHz) this POR configuration input should be low during HRESET. If this configuration is
not set properly, behavior of the PCI interface may be unreliable. Note that the value latched on this signal
during POR is accessible through the memory-mapped PORDEVSR, described in Section 20.4.1.4, “POR
Device Status Register (PORDEVSR).”
Table 4-27. PCI1 Speed Configuration
Functional Signal
Reset Configuration
Name
Value
(Binary)
LWE0
cfg_pci1_speed
0
PCI frequency at or below 33 MHz or PCI-X frequency at 66 MHz
1
PCI frequency above 33 MHz or PCI-X frequency above 66 MHz
(default)
Default (1)
Meaning
Table 4-28. PCI2 Speed Configuration
Functional Signal
Reset Configuration
Name
Value
(Binary)
LGPL1
cfg_pci2_speed
0
PCI frequency at or below 33 MHz
1
PCI frequency above 33 MHz (default)
Default (1)
4.4.3.19
Meaning
PCI Bus Width
The PCI width configuration input, shown in Table 4-29, configures the PCI1/PCI-X interface to 32- or
64-bit extended mode of operation. Note that the value latched on this signal during POR is accessible
through the PORDEVSR, described in Section 20.4.1.4, “POR Device Status Register (PORDEVSR).”
Table 4-29. PCI-32 Configuration
Functional Signal
Reset Configuration
Name
Value
(Binary)
PCI1_REQ64
cfg_pci1_width
0
The PCI1/PCI-X interface operates as a 64-bit interface.
1
The PCI1/PCI-X interface operates as a 32-bit interface (default).
Default (1)
Meaning
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Reset, Clocking, and Initialization
NOTE
The PCI1_REQ64 signal is shared with PCI2_FRAME.
4.4.3.20
PCI I/O Impedance
The PCI I/O impedance configuration inputs, shown in Table 4-30 and Table 4-31 select the impedance of
the PCI I/O drivers for the respective interfaces. Note that the values latched on these signals during POR
are accessible through PORIMPSCR, described in Section 20.4.1.3, “POR I/O Impedance Status and
Control Register (PORIMPSCR).”
Table 4-30. PCI1/PCI-X I/O Impedance
Functional Signal
Reset Configuration
Name
Value
(Binary)
PCI1_GNT1
cfg_pci1_impd
0
25-Ω I/O drivers are used on the PCI1/PCI-X interface.
1
42-Ω I/O drivers are used on the PCI1/PCI-X interface (default).
Default (1)
Meaning
Table 4-31. PCI2 I/O Impedance
Functional Signal
Reset Configuration
Name
Value
(Binary)
PCI2_GNT1
cfg_pci2_impd
0
25 Ω I/O drivers are used on the PCI2 interface.
1
42 Ω I/O drivers are used on the PCI2 interface (default).
Default (1)
4.4.3.21
Meaning
PCI Arbiter Configuration
The PCI arbiter configuration inputs, shown in Table 4-32 and Table 4-33, enable the on-chip PCI1/PCI-X
arbiter. Note that the value latched on these signals during POR are accessible through the PORDEVSR
described in Section 20.4.1.4, “POR Device Status Register (PORDEVSR).”
Table 4-32. PCI1/PCI-X Arbiter Configuration
Functional
Signal
PCI1_GNT2
Reset Configuration Value
Name
(Binary)
cfg_pci1_arb
Default (1)
Meaning
0
The on-chip PCI1/PCI-X arbiter is disabled. External arbitration is required.
1
The on-chip PCI1/PCI-X arbiter is enabled (default).
Table 4-33. PCI2 Arbiter Configuration
Functional
Signal
PCI2_GNT2
Default (1)
Reset Configuration Value
Name
(Binary)
cfg_pci2_arb
Meaning
0
The on-chip PCI2 arbiter is disabled. External arbitration is required.
1
The on-chip PCI2 arbiter is enabled (default).
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Reset, Clocking, and Initialization
4.4.3.22
PCI Debug Configuration
The PCI debug configuration input, shown in Table 4-34, enables PCI debug mode for the PCI1/PCI-X
interface only. In this mode, source ID information is driven onto the address/data signals PCI_AD[62:58]
during the bus command phase (PCI) or attribute phase (PCI-X). Note that this debug functionality is only
available on the PCI1/PCI-X interface and only when the controller is in 64-bit mode. Note that the value
latched on this signal during POR is accessible through the PORDBGMSR described in Section 20.4.1.5,
“POR Debug Mode Status Register (PORDBGMSR).”
Table 4-34. PCI Debug Configuration
Functional
Signal
Reset Configuration
Name
Value
(Binary)
PCI1_GNT3
cfg_pci1_debug
0
PCI debug is enabled. Source ID information is driven onto the highest order
address bits, PCI_AD[62:58], during the bus command phase (PCI) or
attribute phase (PCI-X).
1
PCI operates in normal mode (default).
Default (1)
4.4.3.23
Meaning
PCI-X Configuration
The PCI-X configuration input, shown in Table 4-35, configures PCI or PCI-X mode on the PCI1/PCI-X
port. Note that this input does not support the three states of the PCIXCAP input defined in the PCI-X
specification. It is sampled as either a 1 or a 0 during reset only. Note that the value latched on this signal
during POR is accessible through the memory-mapped PORDEVSR, described in Section 20.4.1.4, “POR
Device Status Register (PORDEVSR).”
Table 4-35. PCI1/PCI-X Configuration
Functional Signal
Reset Configuration Name
Value
(Binary)
PCI1_GNT4
cfg_pci1_mode
0
PCI-X mode
1
PCI mode (default)
Default (1)
4.4.3.24
Meaning
Memory Debug Configuration
The memory debug configuration input, shown in Table 4-36, selects which debug outputs (DDR or LBC
memory controller) are driven onto the MSRCID and MDVAL debug signals. Note that the value latched
on this signal during POR is accessible through the memory-mapped PORDBGMSR (POR debug mode
register) described in Section 20.4.1.5, “POR Debug Mode Status Register (PORDBGMSR).”
Table 4-36. Memory Debug Configuration
Functional
Signal
Reset Configuration
Name
Value
(Binary)
MSRCID0
cfg_mem_debug
0
Debug information from the local bus controller (LBC) is driven on the
MSRCID and MDVAL signals
1
Debug information from the DDR SDRAM controller is driven on the
MSRCID and MDVAL signals (default).
Default (1)
Meaning
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Reset, Clocking, and Initialization
4.4.3.25
DDR Debug Configuration
The DDR debug configuration input, shown in Table 4-37, enables a DDR memory controller debug mode
in which the DDR SDRAM source ID field and data valid strobe are driven onto the ECC pins. ECC
checking and generation are disabled in this case. ECC signals driven from the SDRAMs must be
electrically disconnected from the ECC I/O pins of the MPC8548E in this mode.
Table 4-37. DDR Debug Configuration
Functional Reset Configuration Value
Signal
Name
(Binary)
MSRCID1
cfg_ddr_debug
Meaning
0
Debug information is driven on the ECC pins instead of normal ECC I/O. ECC
signals from memory devices must be disconnected.
1
Debug information is not driven on ECC pins. ECC pins function in their normal
mode (default).
Default (1)
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORDBGMSR (POR debug mode register) described in Section 20.4.1.5, “POR Debug Mode Status
Register (PORDBGMSR).”
4.4.3.26
General-Purpose POR Configuration
The LBC address/data bus inputs, shown in Table 4-38, configure the value of the general-purpose POR
configuration register defined in Section 20.4.1.7, “General-Purpose POR Configuration Register
(GPPORCR).” This register is intended to facilitate POR configuration of user systems. A value placed on
LAD[0:31] during POR is captured and stored (read only) in the GPPORCR. Software can then use this
value to inform the operating system about initial system configuration. Typical interpretations include
circuit board type, board ID number, or a list of available peripherals.
Table 4-38. General-Purpose POR Configuration
Functional
Signals
LAD[0:31]
No default
4.4.3.27
Reset Configuration
Value
Name
(Binary)
cfg_gpinput[0:31]
—
Meaning
General-purpose POR configuration vector to be placed in GPPORCR
SerDes Enable
The SerDes high speed interface may be disabled during power-on reset by pulling low the POR
configuration signal cfg_srds_en, which exists on the external signal TSEC4_TXD[2], and is described in
Table 4-39. By default, this signal is sampled high (SerDes enabled) unless pulled low externally
(disabling SerDes). Pulling this signal low during POR is logically equivalent to setting DEVDISR
bitfields, PCIE and SRIO. Note that the value latched on this signal during POR is accessible through the
PORDEVSR2, described in Section 20.4.1.6, “POR Device Status Register 2 (PORDEVSR2).”
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Reset, Clocking, and Initialization
Table 4-39. SerDes Enable POR Configuration
Functional
Signals
TSEC4_TXD2
Reset Configuration
Value
Name
(Binary)
cfg_srds_en
Default (1)
4.4.4
Meaning
0
SerDes interface is disabled.
1
SerDes interface is enabled. (default)
Clocking
The following paragraphs describe the clocking within the MPC8548E device.
4.4.4.1
System Clock/PCI Clock
The MPC8548E takes a single input clock, SYSCLK, as its primary clock source for the e500 core and all
of the devices and interfaces that operate synchronously with the core. As shown in Figure 4-6, the
SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus
(CCB) clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous
system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller.
The CCB clock also feeds the PLL in the e500 core and the PLL that create clocks for the local bus memory
controller. Note that the divide-by-two CCB clock divider and the divide-by-n CCB clock divider, shown
in Figure 4-6, are located in the DDR and local bus blocks, respectively.
The PCI interfaces may use SYSCLK as the PCI clocks and thus have PCI operation be synchronous with
the platform. Alternately, separate, independent clocks may be used for the PCI interfaces, in which case PCI
operation is asynchronous with respect to SYSCLK and the platform clock.
NOTE
If PCI/PCI-X is to be operated synchronously, the clock ratio between the
CCB clock and the SYSCLK input must be an even multiple (for example
6:1). If an uneven ratio such as 5:1 is needed, the PCI interface must be
operated asynchronously.
When in synchronous mode, the maximum PCI-X frequency is 110 MHz.
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MPC8548E
e500 Core
cfg_core_pll[0:2]
cfg_sys_pll[0:3]
3
4
Core PLL
Device PLL
CCB_clk
÷2
core_clk
6
DDR
6
MCK[0:5]
MCK[0:5]
DDR
Controller
SYSCLK
LSYNC_IN
÷n
PCI1_CLK
LSYNC_OUT
PLL
PCI1
LCLK0
LCLK1
LCLK2
LBC
CCB_clk to Rest
of the Device
PCI2_CLK
PCI2
Figure 4-6. Clock Subsystem Block Diagram
4.4.4.2
RapidIO and PCI Express Clocks
Clocks for these high speed interfaces on the MPC8548E are derived from a PLL in the SerDes block. This
PLL is driven by a reference clock (SD_REF_CLK/SD_REF_CLK) whose input frequency is a function
of the protocol and bit rate being used as shown in Table 4-40.
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Reset, Clocking, and Initialization
Table 4-40. High Speed Interface Clocking
4.4.4.2.1
Interfaces
Bit Rate
(Gbps)
Reference Clock Frequency
(MHz)
PCI Express
2.5
100
Serial RapidIO
3.125
125
2.5
100
1.25
100
Serial RapidIO
PCI Express
2.5
2.5
100
Serial RapidIO
PCI Express
2.5
1.25
100
Minimum Frequency Requirements
Section 4.4.3.5, “I/O Port Selection,” describes various high-speed interface configuration options. Note
that the CCB clock frequency must be considered for proper operation of such interfaces as described
below.
For proper PCI Express operation, the CCB clock frequency must be greater than:
500 MHz × ( PCI Express link width )
---------------------------------------------------------------------------------------------8
See Section 18.1.3.2, “Link Width,” for PCI Express interface width details.
For proper serial RapidIO operation, the CCB clock frequency must be greater than:
2 × ( 0.80 ) × ( serial RapidIO interface frequency ) × ( serial RapidIO link width )
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------64
See Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency
details.
Note that the minimum CCB:SYSCLK ratio for PCI/PCI-X in synchronous mode is 6:1. See
Section 4.4.3.1, “System PLL Ratio,” for details of selecting this ratio. See Section 4.4.4.1, “System
Clock/PCI Clock,” for selecting synchronous/asynchronous PCI/PCI-X
4.4.4.3
Ethernet Clocks
The Ethernet blocks operate asynchronously with respect to the rest of the device. These blocks use receive
and transmit clocks supplied by their respective PHY chips, plus a 125-MHz clock input for gigabit
protocols. Data transfers are synchronized to the CCB clock internally.
4.4.4.4
Real Time Clock
As shown in Figure 4-7, the real time clock (RTC) input can optionally be used to clock the e500 core timer
facilities. RTC can also be used (optionally) by the MPC8548E programmable interrupt controller (PIC)
global timer facilities. The RTC is separate from the e500 core clock and is intended to support relatively
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Reset, Clocking, and Initialization
low frequency timing applications. The RTC frequency range is specified in the MPC8548E Integrated
Processor Hardware Specifications, but the maximum value should not exceed one-quarter of the CCB
Frequency.
Before being distributed to the core time base, RTC is sampled and synchronized with the CCB clock.
The clock source for the core time base is specified by two fields in HID0: time base enable (TBEN), and
select time base clock (SEL_TBCLK). If the time base is enabled, (HID0[TBEN] is set), the clock source
is determined as follows:
• HID0[SEL_TBCLK] = 0, the time base is updated every 8 CCB clocks
• HID0[SEL_TBCLK] = 1, the time base is updated on the rising edge of RTC
The default source of the time base is the CCB clock divided by eight. For more details, see the
PowerPC™ e500 Core Family Reference Manual.
Section 10.3.2.6, “Timer Control Register (TCR),” provides additional information on the use of the RTC
signal to clock the global timers in the PIC unit.
e500 Core
HID0
TBEN
SEL_TBCLK
Core Time Base (Incrementer)
TBU
32
TBL
63
RTC
32
Watchdog timer events based on one of the
64 TB bits selected by the EIS-defined
TCR[WPEXT] concatenated with the
Book E–defined TCR[WP] (WPEXT||WP).
Fixed-interval timer events based on one of the
64 TB bits selected by the EIS-defined
TCR[FPEXT] concatenated with the
Book E–defined TCR[FP] (FP||FPEXT).
(Sampled and
Synchronized)
63
÷8
•
•
•
Core Timer
Facilities Clock
CCB
Clock
•
•
•
(Decrementer)
DEC
Decrementer Event
(0 ⇒ 1 Detect)
Auto-Reload
DECAR
32
63
Note: The logic circuits shown depict functional relationships only; they do not represent physical implementation details.
Figure 4-7. RTC and Core Timer Facilities Clocking Options
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Part II
e500 Core Complex and L2 Cache
This part describes the many features of the MPC8548E core processor at an overview level and the
interaction between the core complex and the L2 cache. The following chapters are included:
• Chapter 5, “Core Complex Overview,” provides an overview of the e500 core processor and the
L1 caches and MMU that, together with the core, comprise the core complex.
• Chapter 6, “Core Register Summary,” provides a listing of the e500 registers in reference form.
• Chapter 7, “L2 Look-Aside Cache/SRAM,” describes the L2 cache of the MPC8548E. Note that
the L2 cache can also be addressed directly as memory-mapped SRAM.
The e500 processor core is a low-power implementation of the family of reduced instruction set computing
(RISC) embedded processors that implement the embedded category of the Power Architecture
technology. This part provides additional information about the Book E architecture as it relates
specifically to the e500 core complex and specific details on how its registers are accessed.
The e500 core complex interacts with the L2 cache through the core complex bus (CCB).
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Chapter 5
Core Complex Overview
This chapter provides an overview of the e500 microprocessor core as it is implemented on the
MPC8548E.
References to e500 are true for both the e500v1 and e500v2.
This chapter includes the following:
• An overview of architecture features as implemented in this core and a summary of the core feature
set
• A summary of the instruction pipeline and flow
• An overview of the programming model
• An overview of interrupts and exception handling
• A description of the memory management architecture
• High-level details of the e500 core memory and coherency model
• A brief description of the core complex bus (CCB)
• A summary of the Power Architecture embedded category compatibility and migration from the
original version of the PowerPC architecture as it is defined by Apple, IBM, and Motorola (referred
to as the AIM version of the PowerPC architecture)
Specific details about the e500 are provided in the PowerPC™ e500 Core Family Reference Manual
(Freescale Document ID No. E500CORERM). The e500 core provides features that the integrated device
may not implement or may implement in a more specific way.
5.1
Overview
The e500 processor core is a low-power implementation of the family of reduced instruction set computing
(RISC) embedded processors that implement the embedded category features of the Power Architecture
technology. The e500 is a 32-bit implementation using the lower words in the 64-bit general-purpose
registers (GPRs).
Figure 5-1 is a block diagram of the processor core complex that shows how the functional units operate
independently and in parallel. Note that this conceptual diagram does not attempt to show how these
features are physically implemented.
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5-1
5-2
Maximum
Two Instructions
Retire per Cycle
BTB
512 Entry
Completion Bus
Simple Unit 2
(32 bit)
Simple Unit 1
(32/64 bit)
Rename
Buffers (14)
GPR File
32-/
64-Bit
e500v1 (3 entry)
e500v2 (5 entry)
GPR
Operand Bus
Multiple Unit
(64/32 bit)
Reservation
Station
Reservation
Station
Data Line
Fill Buffer Data Write
Buffer
L1 Store Load Miss
Queue
Queue
64-Entry
I-L1TLB4K
256/512-Entry
TLB Array
(TLB0)
64-Entry
D-L1TLB4K
e500v2 (9 entry)
Instruction Line
Fill Buffer
e500v1 (4 entry)
Tags
32-Kbyte D Cache
4-Entry
D-L1VSP
L1 Data MMU
16-Entry
TLB Array
(TLB1)
L2 MMUs
Unified
4-Entry
I-L1VSP
L1 Instruction MMU
32-Kbyte I Cache
Tags
Memory Unit
Core Complex Bus
Core Interface Unit
MAS
Registers
128-Bit
(4 Instructions)
Load/Store Unit
(64/32 bit)
Each execution unit can accept one
instruction per cycle.
General Issue
Queue (GIQ)
Instruction Queue
(12 instructions)
Two instruction issue to GIQ per clock
Two Instruction Dispatch
(1 BIQ, 2 GIQ)
Reservation
Station
Branch Issue
Queue (BIQ)
Reservation
Station
CRF Bus
Condition
Register
CR Field
Rename
Buffers (14)
Completion Queue (14 Entry)
Branch
Unit
Reservation
Station
One instruction issue to BIQ per clock
CTR
LR
Branch Prediction Unit
Fetch Stages
Instruction Unit
Program order is maintained by passing instructions
from the IQ to the CQ at dispatch.
Additional Features
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Power Management
• Performance Monitor
Core Complex Overview
Figure 5-1. e500 Core Complex Block Diagram
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Core Complex Overview
The Power Architecture technology defines categories that extend the architecture that can perform
computational or system management functions. One of these on the e500 is the signal processing engine
(SPE), which includes a suite of vector instructions that use the upper and lower halves of the GPRs as a
single two-element operand. Some extensions are defined by Freescale’s embedded category
implementation standards (EIS).
5.1.1
Upward Compatibility
The e500 provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits, as defined by the
architecture. It also provides two-element, 64-bit data types for the SPE and embedded vector
floating-point instructions, which include instructions that operate on operands comprised of two 32-bit
elements. It also provides a 64-bit scalar data type for use with the embedded double-precision
floating-point APU.
The embedded single-precision scalar floating-point instructions use 32-bit single-precision instructions.
NOTE
The SPE (which includes embedded floating-point functionality) is
implemented in all PowerQUICC III devices. However, these instructions
will not be supported in devices subsequent to PowerQUICC III. Freescale
Semiconductor strongly recommends that use of these instructions be
confined to libraries and device drivers. Customer software that uses SPE or
embedded floating-point instructions at the assembly level or that uses SPE
intrinsics will require rewriting for upward compatibility with
next-generation PowerQUICC devices.
Freescale Semiconductor offers a libcfsl_e500 library that uses SPE
instructions. Freescale will also provide libraries to support next-generation
PowerQUICC devices.
5.1.2
Core Complex Summary
The core complex is a superscalar processor that can issue two instructions and complete two instructions
per clock cycle. Instructions complete in order, but can execute out of order. Execution results are available
to subsequent instructions through the rename buffers, but those results are recorded into architected
registers in program order, maintaining a precise exception model. All arithmetic instructions that execute
in the core operate on data in the GPRs. Although the GPRs are 64 bits wide, only SPE, DPFP (e500v2
only), and embedded vector floating-point instructions operate on the upper word of the GPRs; the upper
32 bits are not affected by other 32-bit instructions.
The processor core integrates two simple instruction units (SU1, SU2), a multiple-cycle instruction unit
(MU), a branch unit (BU), and a load/store unit (LSU).
The LSU and SU2 support 64- and 32-bit instructions.
The ability to execute five instructions in parallel and the use of simple instructions with short execution
times yield high efficiency and throughput. Most integer instructions execute in 1 clock cycle. A series of
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Core Complex Overview
independent vector floating-point add instructions can be issued and completed with a throughput of one
instruction per cycle.
The core complex includes independent on-chip, 32-Kbyte, eight-way set-associative, physically
addressed caches for instructions and data. It also includes on-chip first-level instruction and data memory
management units (MMUs) and an on-chip second-level unified MMU.
• The first-level MMUs contain two four-entry, fully-associative instruction and data translation
lookaside buffer (TLB) arrays that provide support for demand-paged virtual memory address
translation and variable-sized pages. They also contain two 64-entry, 4-way set-associative
instruction and data TLB arrays that support 4-Kbyte pages. These arrays are maintained entirely
by the hardware with a true least-recently-used (LRU) algorithm.
• The second-level MMU contains a 16-entry, fully-associative unified (instruction and data) TLB
array that provides support for variable-sized pages. It also contains a unified TLB for 4-Kbyte
page size support, as follows:
— a 256-entry, 2-way set-associative unified TLB for the e500v1
— a 512-entry, 4-way set-associative unified TLB for the e500v2
These second-level TLBs are maintained completely by the software.
The core complex allows cache-line-based user-mode locks on the contents in either the instruction or data
cache. This provides embedded applications with the capability for locking interrupt routines or other
important (time-sensitive) instruction sequences into the instruction cache. It also allows data to be locked
into the data cache, which supports deterministic execution time.
The core complex supports a high-speed on-chip internal bus with data tagging called the core complex
bus (CCB). The CCB has two general-purpose read data buses, one write data bus, data parity bits, data
tag bits, an address bus, and address attribute bits. The processor core complex supports out-of-order reads,
in-order writes, and one level of pipelining for addresses with address-retry responses. It can also support
single-beat and burst data transfers for memory accesses and memory-mapped I/O operations.
5.2
e500 Processor and System Version Numbers
Table 5-1lists the revision codes in the processor version register (PVR) and the system version register
(SVR). These registers can be accessed as SPRs through the e500 core (see Section 6.5.3, “Processor
Version Register (PVR),” and Section 6.5.4, “System Version Register (SVR)”) or as memory-mapped
registers defined by the integrated device (see “Section 20.4.1.16, “Processor Version Register (PVR),”
and Section 20.4.1.17, “System Version Register (SVR)”).
Table 5-1. Device Revision Level Cross-Reference
MPC8548E Revision
Core
Revision
Processor Version
Register (PVR)
1.0
1.0
0x8021_0010
System Version
Register (SVR)
0x8039_0010 for MPC8548E with security
0x8031_0010 for MPC8548 without security
0x803A_0010 for MPC8543E with security
0x8032_0010 for MPC8543 without security
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Core Complex Overview
Table 5-1. Device Revision Level Cross-Reference (continued)
5.3
MPC8548E Revision
Core
Revision
Processor Version
Register (PVR)
1.1, 1.1.1
1.0
0x8021_0010
1.2
1.0
0x8021_0010
2.0
2.0
0x8021_0020
System Version
Register (SVR)
0x8039_0011 for MPC8548E with security
0x8031_0011 for MPC8548 without security
0x803A_0011 for MPC8543E with security
0x8032_0011 for MPC8543 without security
0x8039_0020 for MPC8548E with security
0x8031_0020 for MPC8548 without security
0x8039_0120 for MPC8547E with security
0x8039_0220 for MPC8545E with security
0x8031_0220 for MPC8545 without security
0x803A_0020 for MPC8543E with security
0x8032_0020 for MPC8543 without security
Features
Key features of the e500 are summarized as follows:
• 32-bit architecture
• Additional categories (formerly referred to as APUs)
Branch target buffer (BTB) locking is specific to the e500. BTB locking gives the user the ability
to lock, unlock, and invalidate BTB entries; further information is provided in Table 5-5. The EIS
(see EREF: a Reference for Freescale Book E and the e500 Core) defines the following:
— Integer select. This instruction is now part of the Power Architecture technology base category.
— Performance monitor. The performance monitor facility provides the ability to monitor and
count predefined events such as processor clocks, misses in the instruction cache or data cache,
types of instructions decoded, or mispredicted branches. The count of such events can be used
to trigger the performance monitor exception. Additional performance monitor registers
(PMRs) similar to SPRs are used to configure and track performance monitor operations. These
registers are accessed with the Move to PMR and Move from PMR instructions (mtpmr and
mfpmr). See Section 5.12, “Performance Monitoring.”
— Cache locking. Allows instructions and data to be locked into their respective caches on a cache
block basis. Locking is performed by a set of touch and lock set instructions. This functionality
can be enabled for user mode by setting MSR[UCLE]. The feature also provides resources for
detecting and handling overlocking conditions.
— Machine check. The machine check interrupt is treated as a separate level of interrupt. It uses
its own save and restore registers (MCSRR0 and MCSRR1) and Return from Machine Check
Interrupt (rfmci) instruction. See Section 5.8, “Interrupts and Exception Handling.”
— Single-precision embedded scalar and vector floating-point instructions, listed in Table 5-4.
— Signal processing engine (SPE). Note that the SPE is not a separate unit; SPE computational and
logical instructions are executed in the simple and multiple-cycle units used by all other
computational and logical instructions, and 64-bit loads and stores are executed in the common
LSU. Figure 5-1 shows how execution logic for SU1, the MU, and the LSU is replicated to
support operations on the upper halves of the GPRs.
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Core Complex Overview
NOTE
The SPE APU and the two single-precision floating-point APUs were
combined in the original implementation of the e500 v1, as shown in
Figure 5-2.
Vector and Floating-Point APUs
Original SPE
Definition
e500 v1 e500 v2
SPE vector instructions ev…
√
√
Vector single-precision floating-point evfs…
√
√
Scalar single-precision floating-point efs…
√
√
Scalar double-precision floating-point efd…
√
Figure 5-2. Vector and Floating-Point APUs
•
•
The e500 register set is modified as follows:
– GPRs are widened to 64 bits to support 64-bit load, store, and merge operations. Note that
the upper 32 bits are affected only by 64-bit instructions.
– A 64-bit accumulator (ACC) has been added.
– The signal processing and embedded floating-point status and control register (SPEFSCR)
provides interrupt control and status for SPE and embedded floating-point instructions.
These registers are shown in Figure 5-7. SPE instructions are grouped as follows:
– Single-cycle integer add and subtract with the same latencies for SPE operations as for the
32-bit equivalent
– Single-cycle logical operations
– Single-cycle shift and rotates
– Four-cycle integer pipelined multiplies
– 4-, 11-, 19-, and 35-cycle integer divides
– If rA or rB is zero, a floating-point divide takes 4 cycles; all other cases take 29 cycles.
– Four-cycle SIMD pipelined multiply-accumulate (MAC)
– 64-bit accumulator for no-stall MAC operations
– 64-bit loads and stores
– 64-bit merge instructions
Cache structure—Separate 32-Kbyte, 32-byte line, 8-way set-associative level 1 instruction and
data caches
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU (PLRU) replacement algorithm
— Copy-back data cache that can function as a write-through cache on a page-by-page basis
— Supports all embedded category memory coherency modes
— Supports EIS-defined cache-locking instructions, as listed in Table 5-3
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Core Complex Overview
•
•
•
•
•
•
•
Dual-issue superscalar control
— Two-instructions-per-clock peak issue rate
— Precise exception handling
Decode unit
— 12-entry instruction queue (IQ)
— Full hardware detection of interlocks
— Decodes as many as two instructions per cycle
— Decode serialization control
— Register dependency resolution and renaming
Branch prediction unit (BPU)
— Dynamic branch prediction using a 512-entry, 4-way set-associative branch target buffer
(BTB) supported by the e500 BTB instructions listed in Table 5-5.
— Branch prediction is handled in the fetch stages.
Completion unit
— As many as 14 instructions allowed in 14-entry completion queue (CQ)
— In-order retirement of as many as two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts, mispredicted branches, and
context-synchronizing instructions
Issue queues
— Two-entry branch instruction issue queue (BIQ)
— Four-entry general instruction issue queue (GIQ)
Branch unit—The branch unit (BU) is an execution unit and is distinct from the BPU. It executes
(resolves) all branch and CR logical instructions.
Two simple units (SU1 and SU2)
— Add and subtract
— Shift and rotate
— Logical operations
— Support for 64-bit SPE instructions in SU1
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Core Complex Overview
•
Multiple-cycle unit (MU)—The MU is shown in Figure 5-3.
From GIQ0 or GIQ1
Reservation
Station
Upper
Lower
MU-1
Divide Bypass Path
MU-2
Divide
Postdivide
MU-3
MU-4
Figure 5-3. Four-Stage MU Pipeline, Showing Divide Bypass
The MU has the following features:
— Four-cycle latency for all multiplication, including SPE integer and fractional multiply
instructions and embedded scalar and vector floating-point multiply instructions
— Variable-latency divide: 4, 11, 19, and 35 cycles for all integer divide instructions. If rA or rB
is zero, floating-point divide instructions take 4 cycles; all others take 29. Note that although
most divide instructions take more than 4 cycles to execute, the MU allows subsequent
multiply instructions to execute through all four MU stages in parallel with the divide.
— 4-cycle floating-point add and subtract
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•
The load/store unit (LSU) is shown in Figure 5-4.
Reservation
Station
To completion queue
Load/Store Unit
(64-/32-Bit)
Three-Stage Pipeline
To GPR operand bus
To GPRs
Queues and Buffers
Load
L1 Store
Queue
Miss
Queue
e500v1 (4 entry)
Data Line
Fill Buffer
e500v1 (3 entry)
e500v2 (5 entry)
To data cache
e500v2 (9 entry)
Data Write
Buffer
To core interface unit
Figure 5-4. Three-Stage Load/Store Unit
•
•
The LSU has the following features:
— Three-cycle load latency
— Fully pipelined
— Load miss queue allows up to four load misses before stalling (up to nine load misses in the
e500v2).
— Load hits can continue to be serviced when the load miss queue is full.
— The seven-entry L1 store queue allows full pipelining of stores.
— The three-entry data line fill buffer (five-entry on the e500v2) is used for loads and cacheable
stores. Stores are allocated here so loads can access data from the store immediately.
— The data write buffer contains three entries: one dedicated for snoop pushes, one dedicated for
castouts, and one that can be used for snoop pushes or cast outs.
Cache coherency
— Supports four-state cache coherency: modified-exclusive, exclusive, shared, and invalid
(MESI). Note, however that shared state may not be accessible in some implementations.
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)—internal bus
— High-speed, on-chip local bus with data tagging
— 32-bit address bus
— Address protocol with address pipelining and retry/copyback derived from bus used by
previous generations of processors (referred to as the 60x bus)
— Two general-purpose read data buses and one write data bus
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Core Complex Overview
•
•
•
Extended exception handling
— Supports embedded category interrupt model
– Less than 10-cycle interrupt latency
– Interrupt vector prefix register (IVPR)
– Interrupt vector offset registers (IVORs) 0–15 and 32–35
– Exception syndrome register (ESR)
– Preempting critical interrupt, including critical interrupt status registers (CSRR0 and
CSRR1) and an rfci instruction
– A separate set of resources for machine-check interrupts
– SPE unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
Memory management unit (MMU)
— 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual address)
for the e500v1core and 36-bit real addressing for the e500v2 core
— TLB entries for variable- (4-Kbyte–256-Mbyte pages for the e500v1 and 4-Kbyte–4-Gbyte
pages for the e500v2) and fixed-size (4-Kbyte) pages
— Data L1 MMU
– 4-entry, fully-associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages
— Instruction L1 MMU
– 4-entry, fully-associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages
— Unified L2 MMU
– 16-entry, fully-associative TLB array for variable-sized pages
– e500v1—A 256-entry, 2-way set-associative unified (for instruction and data accesses) L2
TLB array (TLB0) supports only 4-Kbyte pages
– e500v2—A 512-entry, 4-way set-associative unified (for instruction and data accesses) L2
TLB array (TLB0) supports only 4-Kbyte pages
— Software reload for TLBs
— Virtual memory support for as much as 4 Gbytes (232) of effective address space
— Real memory support for as much as 4 Gbytes (232) of physical memory on the e500v1 and 64
Gbytes (236) on the e500v2
— Support for big-endian and true little-endian memory on a per-page basis
Power management
— Low-power design
— Power-saving modes: core-halted and core-stopped
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•
5.3.1
— Internal clock multipliers ranging from 1 to 8 times the bus clock, including integer and
half-mode multipliers.The MPC8548E supports multipliers of 2, 2.5, 3, and 3.5
— Dynamic power management of execution units, caches, and MMUs
— NAP, DOZE, and SLEEP bits in HID0 can be used to assert nap, doze, and sleep output signals
to initiate power-saving modes at the integrated device level.
Testability
— LSSD scan design
— JTAG interface
— ESP support
Reliability and serviceability
— Parity checking on caches
— Parity checking on e500 local bus
e500v2 Differences
The e500v2 provides the following additional features not supported by the e500v1:
• The e500v2 uses 36-bit physical addressing, which is supported by the following:
— MMU assist register 7 (MAS7)
— HID0[EN_MAS7_UPDATE]
— Programmable jumper options to specify the upper bits of the reset vector.
• The e500v2 has a 512-entry, 4-way set-associative unified TLB for TLB1.
• The maximum variable page size is extended to 4 Gbytes.
• Embedded double-precision floating-point APU has been added. These instructions use the 64-bit
GPRs as single, 64-bit double-precision operands. This APU is enabled through MSR[SPE].
• Slightly different functionality of HID1[RFXE] bit.
• The data line fill buffer in the LSU is expanded from three to five entries.
• The load miss queue in the LSU is expanded from four to nine entries.
• TBSEL and TBEE bits have been added to the performance monitor global control register 0
(PMGC0) to support monitoring of time base events.
• Minor modifications to the SPE APU.
• Data cache flush assist capability, supported through HID0[DCFA]. When DCFA is set, the cache
miss replacement algorithm ignores invalid entries and follows the replacement sequence defined
by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions required
to flush the cache.
Detailed descriptions of these differences are provided in their respective chapters.
NOTE
Unless otherwise indicated, references to e500 apply to both e500v1 and
e500v2.
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Core Complex Overview
5.4
Instruction Set
The e500 implements the following instructions:
• The embedded category instruction set for 32-bit implementations. This is composed primarily of
the user-level instructions defined by the Power Architecture user instruction set architecture
(UISA). The e500 does not include floating-point instructions that require floating-point registers
(FPRs), load string, or store string instructions.
• The e500 supports the following instructions:
— Integer select. Now part of the base category. Consists of the Integer Select instruction (isel),
which functions as an if-then-else statement that selects between two source registers by
comparison to a CR bit. This instruction eliminates conditional branches, decreases latency,
and reduces the code footprint.
— Performance monitor. Table 5-2 lists performance monitor instructions.
Table 5-2. Performance Monitor Instructions
Name
Mnemonic
Syntax
Move from Performance Monitor Register
mfpmr
rD,PMRN
Move to Performance Monitor Register
mtpmr
PMRN,rS
— Cache locking. Consists of the instructions described in Table 5-3.
Table 5-3. Cache Locking Instructions
Name
Mnemonic
Syntax
dcblc
CT, rA, rB
Data Cache Block Lock Clear
Data Cache Block Touch and Lock Set
dcbtls
CT, rA, rB
dcbtstls
CT, rA, rB
Instruction Cache Block Lock Clear
icblc
CT, rA, rB
Instruction Cache Block Touch and Lock Set
icbtls
CT, rA, rB
Data Cache Block Touch for Store and Lock Set
— Machine check. Defines the Return from Machine Check Interrupt instruction (rfmci).
— SPE vector instructions. Vector instructions are defined that view the 64-bit GPRs as composed
of a vector of two 32-bit elements (some instructions also read or write 16-bit elements). Some
scalar instructions produce a 64-bit scalar result.
— The embedded floating-point categories provide scalar and vector floating-point instructions.
Scalar single-precision floating-point instructions use only the lower 32 bits of the GPRs;
double-precision operands (e500v2 only) use all 64 bits. Table 5-4 lists embedded
floating-point instructions.
Table 5-4. Scalar and Vector Embedded Floating-Point APU Instructions
Mnemonic
Instruction
Syntax
Scalar SP
Scalar DP
Vector
Convert Floating-Point Single- from Double-Precision
—
efscfd
—
rD,rB
Convert Floating-Point Double- from Single-Precision
—
efdcfs
—
rD,rB
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Table 5-4. Scalar and Vector Embedded Floating-Point APU Instructions (continued)
Mnemonic
Instruction
Syntax
Scalar SP
Scalar DP
Vector
Convert Floating-Point from Signed Fraction
efscfsf
efdcfsf
evfscfsf
rD,rB
Convert Floating-Point from Signed Fraction
efscfsf
efdcfsf
evfscfsf
rD,rB
Convert Floating-Point from Signed Integer
efscfsi
efdcfsi
evfscfsi
rD,rB
Convert Floating-Point from Unsigned Fraction
efscfuf
efdcfuf
evfscfuf
rD,rB
Convert Floating-Point from Unsigned Integer
efscfui
efdcfui
evfscfui
rD,rB
Convert Floating-Point to Signed Fraction
efsctsf
efdctsf
evfsctsf
rD,rB
Convert Floating-Point to Signed Integer
efsctsi
efdctsi
evfsctsi
rD,rB
Convert Floating-Point to Signed Integer with Round toward Zero
efsctsiz
efdctsiz
evfsctsiz
rD,rB
Convert Floating-Point to Unsigned Fraction
efsctuf
efdctuf
evfsctuf
rD,rB
Convert Floating-Point to Unsigned Integer
efsctui
efdctui
evfsctui
rD,rB
Convert Floating-Point to Unsigned Integer with Round toward Zero
efsctuiz
efdctuiz
evfsctuiz
rD,rB
Floating-Point Absolute Value
efsabs
efdabs
evfsabs
rD,rA
Floating-Point Add
efsadd
efdadd
evfsadd
rD,rA,rB
Floating-Point Compare Equal
efscmpeq efdcmpeq
evfscmpeq
crD,rA,rB
Floating-Point Compare Greater Than
efscmpgt
efdcmpgt
evfscmpgt
crD,rA,rB
Floating-Point Compare Less Than
efscmplt
efdcmplt
evfscmplt
crD,rA,rB
Floating-Point Divide
efsdiv
efddiv
evfsdiv
rD,rA,rB
Floating-Point Multiply
efsmul
efdmul
evfsmul
rD,rA,rB
Floating-Point Negate
efsneg
efdneg
evfsneg
rD,rA
Floating-Point Negative Absolute Value
efsnabs
efdnabs
evfsnabs
rD,rA
Floating-Point Subtract
efssub
efdsub
evfssub
rD,rA,rB
Floating-Point Test Equal
efststeq
efdtsteq
evfststeq
crD,rA,rB
Floating-Point Test Greater Than
efststgt
efdtstgt
evfststgt
crD,rA,rB
Floating-Point Test Less Than
efststlt
efdtstlt
evfststlt
crD,rA,rB
— BTB locking instructions. The core complex provides a 512-entry BTB for efficient processing
of branch instructions. The BTB is a branch target address cache, organized as 128 rows with
4-way set associativity, that holds the address and target instruction of the 512 most-recently
taken branches. Table 5-5 lists BTB instructions.
Table 5-5. BTB Locking Instructions
Name
Mnemonic
Syntax
Branch Buffer Load Entry and Lock Set
bblels
—
Branch Buffer Entry Lock Reset
bbelr
—
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Core Complex Overview
5.5
Instruction Flow
The e500 core is a pipelined, superscalar processor with parallel execution units that allow instructions to
execute out of order but record their results in order. Pipelining breaks instruction processing into discrete
stages, so multiple instructions in an instruction sequence can occupy the successive stages: as an
instruction completes one stage, it passes to the next, leaving the previous stage available to a subsequent
instruction. So, even though it may take multiple cycles for an instruction to pass through all of the pipeline
stages, once a pipeline is full, instruction throughput is much shorter than the latency.
A superscalar processor is one that issues multiple independent instructions into separate execution units,
allowing parallel execution. The e500 core has five execution units, one each for branch (BU), load/store
(LSU), and multiple-cycle operations (MU), and two for simple arithmetic operations (SU1 and SU2). The
MU and SU1 arithmetic execution units also execute 64-bit SPE vector instructions, using both the lower
and upper halves of the 64-bit GPRs.
The parallel execution units allow multiple instructions to execute in parallel and out of order. For
example, a low-latency addition instruction that is issued to an SU after an integer divide is issued to the
MU should finish executing before the higher latency divide instruction. The add instruction can make its
results available to a subsequent instruction, but it cannot update the architected GPR specified as its target
operand ahead of the multiple-cycle divide instruction.
5.5.1
Initial Instruction Fetch
The e500 core begins execution at fixed virtual address 0xFFFF_FFFC. The MMU has a default page
translation which maps this to the identical physical address. So, the instruction at physical address
0xFFFF_FFFC must be a branch to another address within the 4-Kbyte boot page.
5.5.2
Branch Detection and Prediction
To improve branch performance, the e500 provides implementation-specific dynamic branch prediction
using the BTB to resolve branch instructions and improve the accuracy of branch predictions. Each of the
512 entries in the 4-way set associative address cache of branch target addresses includes a 2-bit saturating
branch history counter, whose value is incremented or decremented depending on whether the branch was
taken. These bits can take on four values indicating strongly taken, weakly taken, weakly not taken, and
strongly not taken. The BTB is used not only to predict branches, but to detect branches during the fetch
stage, offering an efficient way to access instruction streams for branches predicted as taken.
In the e500, all branch instructions are assigned positions in the completion queue at dispatch. Speculative
instructions in branch target streams are allowed to execute and proceed through the completion queue,
although they can complete only after the branch prediction is resolved as correct and after the branch
instruction itself completes.
If a branch resolves as correct, instructions in the target stream are marked nonspeculative and are allowed
to complete. If the branch history bits in the BTB indicated weakly taken or weakly not taken, the
prediction is upgraded to strongly taken or strongly not taken.
If a branch resolves as incorrect, instructions in the target stream are flushed from the execution pipeline, the
branch history bits are updated in the BTB entry, and nonspeculative fetching begins from the correct path.
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5.5.3
e500 Execution Pipeline
The seven stages of the e500 execution pipeline—fetch1, fetch2/predecode, decode/dispatch, issue,
execute, complete, and write back—are highlighted in grey in Figure 5-5.
Fetch Stage 1
Indicates stages
Instruction Cache
Fetch Stage 2
At dispatch, instructions are deallocated from the
IQ and assigned sequential positions in the CQ.
Maximum four-instruction
fetch per clock cycle
Decode Stage
Maximum two-instruction per cycle dispatch
to the issue queues. BIQ can accept one
per cycle; GIQ can accept at most two.
Issue Stage
General Issue Queue (GIQ)
Branch Issue Queue (BIQ)
Execute Stage
MU Stage 1
BU
Execute
BU
Finish
Divide Bypass
LSU Stage 1
Stage 2
Divide
Stage 2
Stage 3
Postdivide
Stage 3
Stage 4
SU1
SU2
Completion Stage Maximum two-instruction
completion per clock cycle
Write-Back Stage
Figure 5-5. Instruction Pipeline Flow
The common pipeline stages are as follows:
• Instruction fetch—Includes the clock cycles necessary to request an instruction and the time the
memory system takes to respond to the request. Instructions retrieved are latched into the instruction
queue (IQ) for subsequent consideration by the dispatcher.
Instruction fetch timing depends on many variables, such as whether an instruction is in the on-chip
instruction cache or an L2 cache (if implemented). Those factors increase when it is necessary to
fetch instructions from system memory and include the processor-to-bus clock ratio, the amount of
bus traffic, and whether any cache coherency operations are required.
Because there are so many variables, unless otherwise specified, the instruction timing examples
in this chapter assume optimal performance and show the portion of the fetch stage in which the
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Core Complex Overview
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•
instruction is in the instruction queue. The fetch1 and fetch2 stages are primarily involved in
retrieving instructions.
The decode/dispatch stage fully decodes each instruction; most instructions are dispatched to the
issue queues (however, isync, rfi, sc, nops, and some other instructions do not go to issue queues).
The two issue queues, BIQ and GIQ, can accept as many as one and two instructions, respectively,
in a cycle. The behavior of instruction dispatch is covered in significant detail in the e500 Software
Optimization Guide. The following simplification covers most cases:
— Instructions dispatch only from the two lowest IQ entries—IQ0 and IQ1.
— A total of two instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to decode and dispatch (this includes
instructions that are assigned a space in the CQ but not in an issue queue).
Dispatch is treated as an event at the end of the decode stage. The issue stage reads source operands
from rename registers and register files and determines when instructions are latched into the
execution unit reservation stations. Note that the e500 has 14 rename registers, one for each
completion queue entry, so instructions cannot stall because of a shortage of rename registers.
The general behavior of the two issue queues is described as follows:
— The GIQ accepts as many as two instructions from the dispatch unit per cycle. SU1, SU2, MU,
and all LSU instructions (including 64-bit loads and stores) are dispatched to the GIQ, shown
in Figure 5-6.
From IQ0/IQ1
GIQ3
GIQ2
GIQ1
To SU2, MU, or LSU
GIQ0
To SU1, MU, or LSU
Figure 5-6. GPR Issue Queue (GIQ)
•
Instructions can be issued out-of-order from the bottom two GIQ entries (GIQ1–GIQ0). GIQ0
can issue to SU1, MU, and LSU. GIQ1 can issue to SU2, MU, and LSU.
Note that SU2 executes a subset of the instructions that can be executed in SU1. The ability to
identify and dispatch instructions to SU2 increases the availability of SU1 to execute more
computational-intensive instructions.
An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU instruction in
GIQ0 that is stalled behind a long-latency divide.
The execute stage accepts instructions from its issue queue when the appropriate reservation
stations are not busy. In this stage, the operands assigned to the execution stage from the issue stage
are latched.
The execution unit executes the instruction (perhaps over multiple cycles), writes results on its
result bus, and notifies the CQ when the instruction finishes. The execution unit reports any
exceptions to the completion stage. Instruction-generated exceptions are not taken until the
excepting instruction is next to retire.
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Most integer instructions have a 1-cycle latency, so results of these instructions are available
1 clock cycle after an instruction enters the execution unit. The MU and LSU are pipelined, as
shown in Figure 5-5.
Branches resolve in execute stage. If a branch is mispredicted, it takes 5 cycles for the next
instruction to reach the execute stage.
The complete and write-back stages maintain the correct architectural machine state and commit
results to the architecture-defined registers in the proper order. If completion logic detects an
instruction containing an exception status or a mispredicted branch, all following instructions are
cancelled, their execution results in rename registers are discarded, and the correct instruction
stream is fetched.
The complete stage ends when the instruction is retired. Two instructions can be retired per clock
cycle. If no dependencies exist, as many as two instructions are retired in program order.
The write-back stage occurs in the clock cycle after the instruction is retired.
The e500 core also provides new instructions that perform single-instruction, multiple-data (SIMD)
operations. These signal processing instructions consist of parallel operations on both the upper and lower
32 bits of two 64-bit GPR values and produce two 32-bit results written to a 64-bit GPR.
As shown in Figure 5-5, the LSU, MU, and SU1 replicate logic to support 64-bit operations. Although a
vector instruction generates separate, discrete results in the upper and lower halves of the target GPR,
latency and throughput for vector instructions are the same as those for their scalar equivalents.
5.6
Programming Model
The following section describes the e500 core registers. Figure 5-7 shows the e500 register set.
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Core Complex Overview
User-Level Registers
General-Purpose Registers
0
31 32
Instruction-Accessible Registers
63
0
31 32
(upper) GPR0 (lower)
CR
GPR1
Generalpurpose
registers
GPR2
GPR31
Performance Monitor PMRs (Read-Only)
pmr 384 UPMGC0
pmr 0–3
1
UPMCs 1
CTR
spr 8
LR
1
spr 515
spr 516
L1CFG11
spr 512 SPEFSCR 1
Integer exception
register
SPE FP status/control
register
Accumulator
3
spr 513
BBEAR
spr 514
BBTAR 3
SPRG3
spr 260
SPRG4
spr 263
User SPR
general 0
SPR general
registers 3–7
SPRG7
Time-Base Registers (Read-Only)
Branch buffer entry
address register
Branch buffer target
address register
L1 cache
configuration registers
0–1
spr 259
• • •
Miscellaneous Registers
Local control registers
a0–a3, b0–b3
L1 Cache (Read-Only)
L1CFG01
Link register
XER
63
USPRG0
General SPRs (Read-Only)
Count register
ACC 1
Counter
registers 0–3
pmr 128–131 UPMLCas 1
pmr 256–259 UPMLCbs
Global control register
32
spr 256
Condition register
spr 9
spr 1
User General SPR (Read/Write)
63
spr 268
TBL
spr 269
TBU
spr 526
ATBL 1, 2
spr 527
ATBU 1, 2
Time base
lower/upper
Alternate time base
lower/upper
Supervisor-Level Registers
Interrupt Registers
32
spr 63
IVPR
spr 26
SRR0
spr 27
SRR1
spr 58
CSRR0
spr 59
CSRR1
spr 570 MCSRR0 1
spr 571 MCSRR1 1
spr 62
ESR
spr 572
MCSR 1
spr 573
MCAR
spr 569
MCARU 2
spr 61
DEAR
32
Interrupt vector
prefix
spr 308
DBCR0
spr 309
DBCR1
spr 310
DBCR2
spr 304
DBSR
spr 312
IAC1
spr 313
IAC2
spr 317
DAC1
DAC2
IVOR0
spr 401
IVOR1
Critical SRR 0/1
spr 415
IVOR15
spr 528
IVOR32 1
spr 529
spr 530
Machine check
SRR 0/1
spr 531
2
3
IVOR33 1
Interrupt vector offset
registers 32–35
IVOR34 1
IVOR35
32
Interrupt vector offset
registers 0–15
• • •
Machine check
syndrome register
Machine check
address register
spr 1012 MMUCSR0
Data exception
address register
spr 624
MAS0
1
spr 625
MAS1
1
spr 626
MAS2
1
spr 627
MAS3
1
spr 628
MAS4
1
spr 630
MAS6
1
spr 944
Debug control
registers 0–2
Debug status register
Instruction address
compare
registers 1 and 2
Data address
compare
registers 1 and 2
MAS7
spr 48
PID0
PID1 1
spr 634
PID2 1
spr 1023
SVR
System version
spr 286
PIR
Processor ID
spr 287
PVR
Processor version
Timer/Decrementer Registers
1
MMU assist
registers
spr 688 TLB0CFG 1
spr 689 TLB1CFG 1
L1CSR1 1
DECAR
spr 284
TBL
spr 285
TBU
Time base
lower/upper
spr 340
TCR
Timer control
spr 336
TSR
Timer status
spr 1008
HID0 1
spr 1009
HID1 1
spr 1013
BUCSR3
spr 272–279
SPRG0–7
Process ID
registers 0–2
TLB configuration 0/1
Hardware
implementation
dependent 0–1
Branch control and
status register
General SPRs 0–7
Performance Monitor Registers
MMU configuration
L1 Cache (Read/Write)
L1CSR0 1
Decrementer
Decrementer
auto-reload
Miscellaneous Registers
MMU Control and Status (Read Only)
spr 1015 MMUCFG 1
DEC
spr 54
MMU control and status
register 0
1. 2
spr 633
Machine state
spr 22
MMU Control and Status (Read/Write)
Machine check
address register upper
63
MSR
1
Exception syndrome
register
spr 1010
spr 1011
1
63
spr 400
Save/restore
registers 0/1
Debug Registers
spr 316
Configuration Registers
63
pmr 400
PMGC0 1
pmr 16–19
PMC0–3 1
Global control register
Counter registers 0–3
1
Local control a0–a3
pmr 272–275 PMLCb0–3 1
Local control b0–b3
pmr 144–147 PMLCa0–3
L1 Cache
Control/Status 0/1
These registers are defined by the EIS
e500v2 only
These registers are e500-specific
Figure 5-7. e500 Core Programming Model
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5.7
On-Chip Cache Implementation
The core complex contains separate 32-Kbyte, eight-way set-associative, level 1 (L1) instruction and data
caches to give rapid access to instructions and data.
The data cache supports four-state MESI memory coherency protocol. The core complex broadcasts all
cache management functions based on the setting of the address broadcast enable bit, HID1[ABE],
allowing management of other caches in the system.
On the MPC8548E the ABE bit must be set to ensure that cache and TLB management instructions operate
properly on the L2 cache.
The caches implement a pseudo-least-recently-used (PLRU) replacement algorithm.
Parity generation and checking may be enabled for both caches, and each cache can be independently
invalidated through L1CSR1 and L1CSR0. Additionally, instructions are provided to perform cache
locking and unlocking on both data and instruction caches on a cache-block granularity. These are listed
in Section 5.10.3, “Cache Control Instructions.”
Individual instruction cache blocks and data cache blocks can be invalidated using the icbi and dcbi
instructions, respectively. The entire data cache can be invalidated by setting L1CSR0[CFI]; the entire
instruction cache can be invalidated by setting L1CSR1[ICFI].
5.8
Interrupts and Exception Handling
The e500 core supports an extended exception handling model, with nested interrupt capability and
extensive interrupt vector programmability. The following sections define the exception model, including
an overview of exception handling as implemented on the e500 core, a brief description of the exception
classes, and an overview of the registers involved in the processes.
5.8.1
Exception Handling
In general, interrupt processing begins with an exception that occurs due to external conditions, errors, or
program execution problems. When the exception occurs, the processor checks to verify interrupt
processing is enabled for that particular exception. If enabled, the interrupt causes the state of the processor
to be saved in the appropriate registers and prepares to begin execution of the handler located at the
associated vector address for that particular exception.
Once the handler is executing, the implementation may need to check one or more bits in the exception
syndrome register (ESR) or the SPEFSCR, depending on the exception, to verify the specific cause of the
exception and take appropriate action.
The core complex provides the interrupts described in Section 5.8.5, “Interrupt Registers.”
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5.8.2
Interrupt Classes
All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.
• Asynchronous interrupts (such as machine check, critical input, and external interrupts) are caused
by events that are independent of instruction execution. For asynchronous interrupts, the address
reported in a save/restore register is the address of the instruction that would have executed next
had the asynchronous interrupt not occurred.
• Synchronous interrupts are those that are caused directly by the execution or attempted execution
of instructions. Synchronous inputs may be either precise or imprecise, which are described as
follows:
— Synchronous precise interrupts are those that precisely indicate the address of the instruction
causing the exception that generated the interrupt or, in some cases, the address of the
immediately following instruction. The interrupt type and status bits indicate which instruction
is addressed in the appropriate save/restore register.
— Synchronous imprecise interrupts are those that may indicate the address of the instruction
causing the exception that generated the interrupt or some instruction after the instruction
causing the interrupt. If the interrupt was caused by either the context synchronizing mechanism
or the execution synchronizing mechanism, the address in the appropriate save/restore register
is the address of the interrupt forcing instruction. If the interrupt was not caused by either of
those mechanisms, the address in the save/restore register is the last instruction to start execution
and may not have completed. No instruction following the instruction in the save/restore register
has executed.
5.8.3
Interrupt Types
The e500 core processes all interrupts as either machine check, critical, or noncritical types. Separate
control and status register sets are provided for each interrupt type. The core handles interrupts from these
three types in the following priority order:
1. Machine check interrupt (highest priority)—The e500 defines a separate set of resources for the
machine check interrupt. They use the machine check save and restore registers
(MCSRR0/MCSRR1) to save state when they are taken, and they use the rfmci instruction to
restore state. These interrupts can be masked by the machine check enable bit, MSR[ME].
2. Noncritical interrupts—First-level interrupts that allow the processor to change program flow to
handle conditions generated by external signals, errors, or unusual conditions arising from program
execution or from programmable timer-related events. These interrupts are largely identical to
those previously defined by the OEA portion of the architecture. They use save and restore
registers (SRR0/SRR1) to save state when they are taken and they use the rfi instruction to restore
state. Asynchronous noncritical interrupts can be masked by the external interrupt enable bit,
MSR[EE].
3. Critical interrupts—Critical interrupts can be taken during a noncritical interrupt or during regular
program flow. They use the critical save and restore registers (CSRR0/CSRR1) to save state when
they are taken and they use the rfci instruction to restore state. These interrupts can be masked by
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the critical enable bit, MSR[CE]. The embedded category defines the critical input, watchdog
timer, and machine check interrupts as critical interrupts, but the e500 implements a third set of
resources for the machine check interrupt, as described in Table 5-6.
All interrupts except machine check are ordered within the two categories of noncritical and critical, such
that only one interrupt of each category is reported, and when it is processed (taken), no program state is
lost. Because save/restore register pairs are serially reusable, program state may be lost when an unordered
interrupt is taken.
5.8.4
Upper Bound on Interrupt Latencies
Core complex interrupt latency is defined as the number of core clocks between the sampling of the
interrupt signal as asserted and the initiation of the IVOR fetch (that is, the fetch of the first instruction in
the handler). Core complex interrupt latency is determinate unless a guarded load or a cache-inhibited
stwcx. is being executed, in which case the latency is indeterminate. The minimum latency is 3 core clocks
and the maximum is 8, not including the 2 bus clock cycles required to synchronize the interrupt signal
from the pad.
When an interrupt is taken, all instructions in the IQ are thrown away unless the oldest instruction is a
load/store instruction. That is, if an asynchronous interrupt is being serviced and the oldest instruction is
not a load/store instruction, the core complex goes straight from sampling the interrupt to ensuring a
recoverable state and issuing an exception. If a load/store instruction is oldest, the core complex waits
4 clocks before ensuring a recoverable state. During this time, any instruction finished by the LSU is
deallocated.
5.8.5
Interrupt Registers
The registers associated with interrupt and exception handling are described in Table 5-6.
Table 5-6. Interrupt Registers
Register
Description
Noncritical Interrupt Registers
SRR0
Save/restore register 0—Holds the address of the instruction causing the exception or the address of the instruction
that will execute after the rfi instruction.
SRR1
Save/restore register 1—Holds machine state on noncritical interrupts and restores machine state after an rfi
instruction is executed.
Critical Interrupt Registers
CSRR0
Critical save/restore register 0—On critical interrupts, holds either the address of the instruction causing the
exception or the address of the instruction that will execute after the rfci instruction.
CSRR1
Critical save/restore register 1—Holds machine state on critical interrupts and restores machine state after an rfci
instruction is executed.
Machine Check Interrupt Registers
MCSRR0 Machine check save/restore register 0—Used to store the address of the instruction that will execute after an rfmci
instruction is executed.
MCSRR1 Machine check save/restore register 1—Holds machine state on machine check interrupts and restores machine
state (if recoverable) after an rfmci instruction is executed.
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Table 5-6. Interrupt Registers (continued)
Register
MCAR
Description
Machine check address register—Holds the address of the data or instruction that caused the machine check
interrupt. MCAR contents are not meaningful if a signal triggered the machine check interrupt.
Syndrome Registers
MCSR
ESR
Machine check syndrome register—Holds machine state information on machine check interrupts and restores
machine state after an rfmci instruction is executed.
Exception syndrome register—Provides a syndrome to differentiate between the different kinds of exceptions that
generate the same interrupt type. Upon generation of a specific exception type, the associated bit is set and all
other bits are cleared.
SPE Interrupt Registers
SPEFSCR Signal processing and embedded floating-point status and control register—Provides interrupt control and status
as well as various condition bits associated with the operations performed by the SPE.
Other Interrupt Registers
DEAR
Data exception address register—Holds the address that was referenced by a load, store, or cache management
instruction that caused an alignment, data TLB miss, or data storage interrupt.
IVPR
IVORs
Together, IVPR[32–47] || IVORn [48–59] || 0b0000 define the address of an interrupt-processing routine. See
Table 5-7 and the EREF for more information.
Each interrupt has an associated interrupt vector address, obtained by concatenating the IVPR value with
the address index in the associated IVOR (that is, IVPR[32–47] || IVORn[48–59] || 0b0000). The resulting
address is that of the instruction to be executed when that interrupt occurs. IVPR and IVOR values are
indeterminate on reset, and must be initialized by the system software using mtspr. Table 5-7 lists IVOR
registers implemented on the e500 and the associated interrupts.
Table 5-7. Interrupt Vector Registers and Exception Conditions
Register
Interrupt
Embedded Category–Defined IVORs
IVOR0
Critical input
IVOR1
Machine check interrupt offset
IVOR2
Data storage interrupt offset
IVOR3
Instruction storage interrupt offset
IVOR4
External input interrupt offset
IVOR5
Alignment interrupt offset
IVOR6
Program interrupt offset
IVOR7
Floating-point unavailable interrupt offset
IVOR8
System call interrupt offset
IVOR9
Auxiliary processor unavailable interrupt offset
IVOR10
Decrementer interrupt offset
IVOR11
Fixed-interval timer interrupt offset
IVOR12
Watchdog timer interrupt offset
IVOR13
Data TLB error interrupt offset
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Table 5-7. Interrupt Vector Registers and Exception Conditions (continued)
Register
Interrupt
IVOR14
Instruction TLB error interrupt offset
IVOR15
Debug interrupt offset
e500-Specific IVORs
5.9
IVOR32
SPE unavailable interrupt offset
IVOR33
SPE floating-point data exception interrupt offset
IVOR34
SPE floating-point round exception interrupt offset
IVOR35
Performance monitor
Memory Management
The e500 core complex supports demand-paged virtual memory as well other memory management
schemes that depend on precise control of effective-to-physical address translation and flexible memory
protection as defined by the architecture. The mapping mechanism consists of software-managed TLBs
that support variable-sized pages with per-page properties and permissions. The following properties can
be configured for each TLB:
• User-mode page execute access
• User-mode page read access
• User-mode page write access
• Supervisor-mode page execute access
• Supervisor-mode page read access
• Supervisor-mode page write access
• Write-through required (W)
• Caching inhibited (I)
• Memory coherency required (M) (ignored on the MPC8548E)
• Guarded (G)
• Endianness (E)
• User-definable (U0–U3), a 4-bit implementation-specific field
The core complex employs a two-level memory management unit (MMU) architecture. There are separate
instruction and data level-1 (L1) MMUs backed up by a unified level-2 (L2) MMU.
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Core Complex Overview
This two-level structure is shown in Figure 5-8.
Memory Unit
To instruction unit
Instruction Line
FIll Buffer
32-Kbyte I-Cache
Tags
L1 Instruction MMU
4-Entry
I-L1VSP
MAS
Registers
64-Entry
I-L1TLB4K
L2 MMUs
Unified
16-Entry
TLB Array
(TLB1)
256/512-Entry
TLB Array
(TLB0)
L1 Data MMU
4-Entry
D-L1VSP
64-Entry
D-L1TLB4K
Data Line
FIll Buffer
To load/store unit
Tags
32-Kbyte D-Cache
Core Interface
Figure 5-8. MMU Structure
Level-1 MMUs have the following features:
• Four-entry, fully associative TLB array that supports all nine page sizes
• 64-entry, 4-way set-associative TLB 4-Kbyte array that supports 4-Kbyte pages only
• Hardware partially managed by L2 MMU
• Supports snooping of TLBs by both internal and external tlbivax instructions
The level-2 MMU has the following features:
• A 16-entry, fully associative L2 TLB array (TLB1) that supports all nine variable page sizes
• TLB array (TLB0) that supports only 4-Kbyte pages, as follows:
— e500v1—256-entry, 2-way set-associative TLB array
— e500v2—512-entry, 4-way set-associative TLB array
• Hardware assist for TLB miss exceptions
• Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions
• Supports snooping of TLB by both internal and external tlbivax instructions
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5.9.1
Address Translation
The core complex fetch and load/store units generate 32-bit effective addresses. The MMU translates these
addresses to real addresses (32-bit real addresses for the e500v1 core, 36-bit for the e500v2) (which are
used for memory bus accesses) using an interim 41-bit virtual address.
Figure 5-9 shows the translation flow for the e500v1 core.
•••
IS DS •••
MSR
Instruction Access
Data Access
8 Bits
AS
PID0
32-Bit Effective Address (EA)
4–20 Bits*
12–28 Bits*
Effective Page Number
Byte Address
PID1
PID2
Three 41-Bit Virtual Addresses (VAs)
L1 MMUs
L2 MMU (Unified)
16-Entry Fully-Assoc. VSP Array (TLB1)
Instruction L1 MMU
2 TLBs
Data L1 MMU
2 TLBs
256-Entry 2-Way Set-Assoc. Array (TLB0)
4–20 Bits*
32-Bit Real Address
Real Page Number
12–28 Bits*
Byte Address
* Number of bits depends on page size (4 Kbytes–256 Mbytes).
Figure 5-9. Effective-to-Real Address Translation Flow
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Figure 5-10 shows the same translation flow for the e500v2 core.
•••
IS DS •••
MSR
Instruction Access
Data Access
8 bits
AS
PID0
32-bit Effective Address (EA)
0–20 bits*
12–32 bits*
Effective Page Number
Byte Address
PID1
PID2
Three 41-bit Virtual Addresses (VAs)
L1 MMUs
L2 MMU (unified)
16-Entry Fully-Assoc. VSP Array (TLB1)
Instruction L1 MMU
2 TLBs
Data L1 MMU
2 TLBs
512-Entry 4-Way Set Assoc. Array (TLB0)
4–24 bits*
36-bit Real Address
12–32 bits*
Real Page Number
Byte Address
* Number of bits depends on page size
(4 Kbytes–4 Gbytes)
Figure 5-10. Effective-to-Real Address Translation Flow (e500v2)
The appropriate L1 MMU (instruction or data) is checked for a matching address translation. The
instruction L1 MMU and data L1 MMU operate independently and can be accessed in parallel, so that hits
for instruction accesses and data accesses can occur in the same clock. If an L1 MMU misses, the request
for translation is forwarded to the unified (instruction and data) L2 MMU. If found, the contents of the
TLB entry are concatenated with the byte address to obtain the physical address of the requested access.
On misses, the L1 TLB entries are replaced from their L2 TLB counterparts using a true LRU algorithm.
5.9.2
MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)
MMU assist registers are used to hold values either read from or to be written to the TLBs and information
required to identify the TLB to be accessed. MAS3 implements the real page number (RPN), the user
attribute bits (U0–U3), and permission bits (UX, SX, UW, SW, UR, SR) that specify user and supervisor
read, write, and execute permissions.
The e500 does not implement MAS5.
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MAS registers are affected by the following instructions (see the EREF for more detailed information):
• MAS registers are accessed with the mtspr and mfspr instructions.
• The TLB Read Entry instruction (tlbre) causes the contents of a single TLB entry from the L2
MMU to be placed in defined locations in MAS0–MAS3 (and optionally MAS7 on the e500v2).
The TLB entry to be extracted is determined by information written to MAS0 and MAS2 before
the tlbre instruction is executed.
• The TLB Write Entry instruction (tlbwe) causes the information stored in certain locations of
MAS0–MAS3 (and MAS7 on the e500v2) to be written to the TLB specified in MAS0.
• The TLB Search Indexed instruction (tlbsx) updates MAS registers conditionally, based on success
or failure of a lookup in the L2 MMU. The lookup is specified by the instruction encoding and
specific search fields in MAS6. The values placed in the MAS registers may differ, depending on
a successful or unsuccessful search.
For TLB miss and certain MMU-related DSI/ISI exceptions, MAS4 provides default values for updating
MAS0–MAS2.
5.9.3
Process ID Registers (PID0–PID2)
The e500 core complex also implements three process ID (PID) registers that hold the values used to
construct the three virtual addresses for each access. These process IDs provide an extended page sharing
capability. Which of these three virtual addresses is used is controlled by the TID field of a matching TLB
entry, and when TID = 0x00 (identifying a page as globally shared), the PID values are ignored.
A hit to multiple TLB entries in the L1 MMU (even if they are in separate arrays) or a hit to multiple entries
in the L2 MMU is considered to be a programming error.
5.9.4
TLB Coherency
The core complex provides the ability to invalidate a TLB entry, as defined by the architecture. The tlbivax
instruction invalidates a matching local TLB entry. Execution of this instruction is also broadcast on the
core complex bus (CCB) if HID1[ABE] is set. The core complex also snoops TLB invalidate transactions
on the CCB from other bus masters.
On the MPC8548E the ABE bit must be set to ensure that cache and TLB management instructions operate
properly on the L2 cache.
5.10
Memory Coherency
The core complex supports four-state memory coherency. Memory coherency is hardware-supported on
the system bus through bus snooping and the retry/copyback bus protocol, and through broadcasting of
cache management instructions. Translation coherency is also hardware-supported through broadcasting
and bus snooping of TLB invalidate transactions. The four-state MESI protocol supports efficient
large-scale real-time data sharing between multiple caching bus masters.
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5.10.1
Atomic Update Memory References
The e500 core supports atomic update memory references for both aligned word forms of data using the
load and reserve and store conditional instruction pair, lwarx and stwcx. Typically, a load and reserve
instruction establishes a reservation and is paired with a store conditional instruction to achieve the atomic
operation. However, there are restrictions and requirements for this functionality. The processor revokes
reservations during a context switch, so the programmer must reacquire the reservation after a context
switch occurs.
5.10.2
Memory Access Ordering
The core complex supports weakly ordered references to memory. Thus the e500 manages the order and
synchronization of instructions to ensure proper execution when memory is shared between multiple
processes or programs. The cache and data memory control attributes, along with msync and mbar,
provide the required access control.
5.10.3
Cache Control Instructions
The core complex supports instructions for performing a full range of cache control functions, including
cache locking by line. The core complex supports broadcasting and snooping of these cache control
instructions on the CCB. The e500 core also supports the following e500-specific cache locking
instructions:
• Data Cache Block Lock Clear (dcblc)
• Data Cache Block Touch and Lock Set (dcbtls)
• Data Cache Block Touch for Store and Lock Set (dcbtstls)
• Instruction Cache Block Lock Clear (icblc)
• Instruction Cache Block Touch and Lock Set (icbtls)
5.10.4
Programmable Page Characteristics
Cache and memory attributes are programmable on a per-page basis. In addition to the write-through,
caching-inhibited, memory coherency enforced, and guarded characteristics defined by the WIMG bits,
the endianness bit, E, allows selection of big- or little-endian byte ordering on a per-page basis.
In addition to the WIMGE bits, the MMU model defines user-definable page attribute bits U0–U3.
5.11
Core Complex Bus (CCB)
The core complex defines a versatile local bus interface that allows a wide range of system performance
and system-complexity trade-offs. The interface defines the following buses:
• An address-out bus for mastering bus transactions
• An address-in bus for snooping internal resources
• Three tagged data buses
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Two of the data buses are general-purpose data-in buses for reads, and the third is a data-out bus for writes.
The two data-in buses feature support for out-of-order read transactions from two different sources
simultaneously, and all three data buses may be operated concurrently. The address-in bus supports
snooping for external management of the L1 caches and TLBs by other bus masters. The core complex
broadcasts and snoops the cache and TLB management instructions accordingly. It is envisioned that a
wide range of system implementations can be constructed from the defined interface.
5.12
Performance Monitoring
The e500 core provides a performance monitoring capability that allows counting of events such as
processor clocks, instruction cache misses, data cache misses, mispredicted branches, and others. The
count of these events may be configured to trigger a performance monitor exception following the e500
interrupt model. This interrupt is assigned to vector offset register IVOR35.
The register set associated with the performance monitoring function consists of counter registers, a global
control register, and local control registers. These registers are read/write from supervisor mode, and each
register is reflected to a corresponding read-only register for user mode. Two instructions, mtpmr and
mfpmr, are provided for moving data to and from these registers. An overview of the performance
monitoring registers is provided in the following sections.
5.12.1
Global Control Register
The PMGC0 register provides global control of the performance monitoring facility from supervisor
mode. From this register all counters may be frozen, unfrozen, or configured to freeze on an enabled
condition or event. Additionally, the performance monitoring facility may be disabled or enabled from this
register. The contents of PMGC0 are reflected to UPMGC0, which may be read from user mode using the
mfpmr instruction.
5.12.2
Performance Monitor Counter Registers
There are four counter registers (PCM0–PCM3) provided in the performance monitoring facility. These
32-bit registers hold the current count for software-selectable events and can be programmed to generate
an exception on overflow. These registers may be written or read from supervisor mode using the mtpmr
and mfpmr instructions. The contents of these registers are reflected to UPCM0–UPCM3, which can be
read from user mode with mfpmr.
Performance monitor exceptions occur only if all of the following conditions are met:
• A counter is in the overflow state.
• The counter's overflow signaling is enabled.
• Overflow exception generation is enabled in PMGC0.
• MSR[EE] is set.
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5.12.3
Local Control Registers
For each of the counter registers, there are two corresponding local control registers. These two registers
specify which of the 128 available events is to be counted, what specific action is to be taken on overflow,
and various options for freezing a counter value under given modes or conditions.
• PMLCa0–PMLCa3 provide fields that allow freezing of the corresponding counter in user mode,
supervisor mode, or under software control. Additionally, the overflow condition may be enabled
or disabled from this register. The contents of these registers are reflected to
UPMLCa0–UPMLCa3, which can be read from user mode with mfpmr.
• PMLCb0–PMLCb3 provide count scaling for each counter register using configurable threshold
and multiplier values. The threshold is a 6-bit value and the multiplier is a 3-bit encoded value,
allowing eight multiplier values in the range of 1 to 128. Any counter may be configured to
increment only when an event occurs more than [threshold × multiplier] times. The contents of
these registers are reflected to UPMLCb0–UPMLCb3, which can be read from user mode with
mfpmr.
5.13
Legacy Support of Power Architecture Technology
This section provides an overview of the architectural differences and compatibilities of the e500 core
compared with the AIM Power Architecture technology. The two levels of the e500 programming
environment are as follows:
• User level—This defines the base user-level instruction set, user-level registers, data types,
memory conventions, and the memory and programming models seen by application
programmers.
• Supervisor level—This defines supervisor-level resources typically required by an operating
system, the memory management model, supervisor level registers, and the exception model.
Like all devices that implement the Power Architecture technology, in general, the e500 core supports the
user-level architecture. The following sections are intended to highlight the main differences. For specific
implementation details refer to the relevant chapter.
5.13.1
Instruction Set Compatibility
The following sections generally describe the user and supervisor instruction sets.
5.13.1.1
User Instruction Set
The e500 core executes legacy user-mode binaries and object files except for the following:
• The e500 supports vector and scalar single-precision floating-point operations as part of the SPE.
The e500v2 supports scalar double-precision floating-point instructions. These instructions have
different encoding than the AIM definition of the architecture. Additionally, the e500 core uses
GPRs for floating-point operations, rather than the FPRs defined by the UISA. Most porting of
floating-point operations can be handled by recompiling.
• String instructions are not implemented on the e500; therefore, trap emulation must be provided to
ensure backward compatibility.
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5.13.1.2
Supervisor Instruction Set
The supervisor mode instruction set defined by the PowerPC architecture is compatible with the e500 with
the following exceptions:
• The MMU architecture is different, so some TLB manipulation instructions have different
semantics.
• Instructions that support the BATs and segment registers are not implemented.
5.13.2
Memory Subsystem
The architecture provides separate instruction and data memory resources. The e500 provides additional
cache control features, including cache locking.
5.13.3
Exception Handling
Exception handling is generally the same as that defined in the AIM version of the architecture for the
e500, with the following differences:
• The critical interrupt provides an extra level of interrupt nesting. The critical interrupt includes
external critical and watchdog timer time-out inputs.
• The machine check exception uses the Return from Machine Check Interrupt instruction, rfmci,
and two machine check save/restore registers, MCSRR0 and MCSRR1.
• IVPR and IVORs set interrupt vectors individually, but they can be set to the address offsets
defined in the OEA to provide compatibility.
• The embedded category does not define a reset vector; execution begins at a fixed virtual address,
0xFFFF_FFFC.
• Timer services are generally compatible, although the embedded category defines a new
decrementer auto reload feature, the fixed-interval timer critical interrupt, and the watchdog timer
interrupt, which are implemented in the e500 core.
An overview of the interrupt and exception handling capabilities of the e500 core can be found in
Section 5.8, “Interrupts and Exception Handling.”
5.13.4
Memory Management
The embedded category defines resources for fixed 4-Kbyte pages and multiple, variable page sizes that
can be configured in a single implementation. TLB management is provided with new instructions and
SPRs.
5.13.5
Reset
Embedded category–compliant cores do not share a common reset vector with the AIM version of the
architecture. Instead, at reset fetching begins at address 0xFFFF_FFFC. In addition, the Freescale MMU
category defines specific aspects of the MMU page translation and protection mechanisms. Unlike the
AIM version of the core, as soon as instruction fetching begins, the e500 core is in virtual mode with a
hardware-initialized TLB entry.
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MMU operations are described in the EREF.
5.13.6
Little-Endian Mode
Unlike the AIM version of the architecture, where little-endian mode is controlled on a system basis, the
embedded category allows control of byte ordering on a memory page basis. In addition, the little-endian
byte ordering used is true little endian.
5.14
PowerQUICC III Implementation Details
Table 5-8 summarizes e500 core functionality that is not implemented by PowerQUICC III devices.
Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core Implementation
Feature
PowerQUICC III Implementation
Cache protocol
The L2 cache does not support MESI cache protocol.
Multiprocessor
functionality
Because PowerQUICC III is designed for a uniprocessor environment, the following e500 functionality is not
implemented:
• The memory coherence bit, M, which is controlled through MAS2[M] and MAS4[MD] has no effect.
• HID1[ABE] has meaning only in that it must be set to ensure that cache and TLB management instructions
operate properly with respect to the L2 cache.
• Dynamic snooping does not occur in power-stopped state (see the note below in the entry for dynamic bus
snooping).
Nexus support
Nexus is not supported. The Nexus processor ID register (NPIDR) and the Nexus bus enable bit
(HID1[NEXEN]) are not supported.
R1 and R2 data R1 and R2 data bus parity are disabled on PowerQUICC III devices. HID1[R1DPE,R2DPE] are reserved.
bus parity
Dynamic bus
snooping
The PowerQUICC III devices do not perform dynamic bus snooping as described here. That is, when the e500
core is in core-stopped state (which is the state of the core when the PowerQUICC III device is in either the
nap or sleep state), the core is not awakened to perform snoops on global transactions. Therefore, before
entering nap or sleep modes, L1 caches should be flushed if coherency is required during these power-down
modes. For more information, see Section 20.5.1.9, “Snooping in Power-Down Modes.”
Supported
TCR[WRC]
PowerQUICC III devices define values for 01, 10, and 11, as follows:
00 No watchdog timer reset can occur.
01 Force processor checkstop on second timeout of watchdog timer
10 Assert processor reset output (core_hreset_req) on second timeout of watchdog timer
11 Reserved
SPE and
floating-point
categories
The SPE and the vector and scalar floating-point instructions will not be implemented in the next generation
of PowerQUICC devices. Freescale Semiconductor strongly recommends that use of these instructions be
confined to libraries and device drivers. Customer software that uses these instructions at the assembly level
or that uses SPE or floating-point intrinsics will require rewriting for upward compatibility with next generation
PowerQUICC devices.
The e500v2 core implements the double-precision floating-point APU.
Freescale Semiconductor offers a libcfsl_e500 library that uses SPE instructions. Freescale Semiconductor
will also provide future libraries to support next generation PowerQUICC devices.
HID0
implementation
SEL_TBCLK bit. Selects time base clock. If this bit is set and the time base is enabled, the time base is based
on the TBCLK input, which on the PowerQUICC III devices is RTC.
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Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core Implementation (continued)
Feature
PowerQUICC III Implementation
HID1
Implementation
PLL_MODE. Set to 01
PLL_CFG. PowerQUICC III devices support the following:
0001_00Ratio of 2:1
0001_01Ratio of 5:2 (2.5:1)
0001_10Ratio of 3:1
0001_11Ratio of 7:2 (3.5:1)
NEXEN, R1DPE, R2DPE, MPXTT, MSHARS, SSHAR, ATS, and MID are not implemented
On PowerQUICC III devices, ABE must be set to ensure that cache and TLB management instructions operate
properly on the L2 cache.
Please refer to the description of HID1[RFXE] in Section 6.10.2, “Hardware Implementation-Dependent
Register 1 (HID1).”
If RFXE is 0, conditions that cause the assertion of core_fault_in cannot directly cause the e500 to generate
a machine check; however, PowerQUICC III devices must be configured to detect and enable such conditions.
The following describes how error bits should be configured:
• ECM mapping errors: EEER[LAEE] must be set. See Section 8.2.1.6, “ECM Error Enable Register (EEER).”
• L2 multiple-bit ECC errors: L2ERRDIS[MBECCDIS] must be cleared to ensure that error can be detected.
L2ERRINTEN[MBECCINTEN] must be set. See Section 7.3.1.4, “L2 Error Registers.”
• DDR multiple-bit ECC errors. ERR_DISABLE[MBED] and ERR_INT_EN[MBEE] must be zero and
DDR_SDRAM_CFG[ECC_EN] must be one to ensure that an interrupt is generated. See Section 9.4.1,
“Register Descriptions.”
• PCI. The appropriate parity detect and master-abort bits in ERR_DR must be cleared and the
corresponding enable bits in ERR_EN must be set to ensure that an interrupt is generated.
Local bus controller parity errors. LTEDR[PARD] must be cleared and LTEIR[PARI] must be set to ensure that
an parity errors can generate an interrupt. See Section 13.3.1.11, “Transfer Error Check Disable Register
(LTEDR),” and Section 13.3.1.12, “Transfer Error Interrupt Enable Register (LTEIR).”
PIR value
The PIR value is all zeros on PowerQUICC III devices.
PVR value
The PVR reset value is 0x80nn_nnnn. See Table 5-1 for specific values.
PVR[VERSION] = 0x80nn
PVR[REVISION] = 0xnnnn
SVR value
The SVR reset value is 0x80nn_nnnn. See Table 5-1 for specific values.
Alternate time
base
The alternate time base defines a time base counter similar to the time base defined in architecture. It is
intended to be used for measuring time in implementation defined intervals. It differs from the defined Time
Base in that it is not writable and always counts up, wrapping when the 64-bit count overflows. It defines two
SPRs, ATBL (SPR 526) and ATBL (SPR 527).
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Core Complex Overview
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Chapter 6
Core Register Summary
This chapter describes the e500 register model and indicates whether each register is defined by the Power
Architecture technology, by the Freescale embedded category implementation standards (EIS), or by the
implementation. For the programmer, drawing this distinction indicates the degree to which code is
portable among Freescale processors.
This chapter provides reference material—figures for each register and complete descriptions of register
fields, including how the registers are accessed, reset values, and whether they can be accessed by userand supervisor-level software. Detailed discussions of how these registers are used are provided in EREF:
A Reference for Freescale Book E and the e500 Core and the PowerPC™ e500 Core Family Reference
Manual.
Note that all registers described here are implemented in the hardware as part of the e500 core.
6.1
Overview
As shown in Figure 6-1, most of the registers implemented are defined by the architecture, and most of
those were defined by the AIM definition of the architecture and have changed very little. Additional
registers and fields within registers are defined by the EIS and by the implementation.
The Power Architecture technology defines some register fields in a very general way, leaving some
details as implementation specific. In some cases, this more specific functionality is defined by the EIS;
in others it is left up to the processor. This chapter identifies the level at which each features is defined.
References to e500 are true for both the e500v1 and e500v2.
6.1.1
Register Set
Table 6-1 shows the e500 register set, grouped by whether they can be accessed by user- or
supervisor-level software. Unless otherwise indicated, these registers are defined by the base or embedded
category.
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6-1
Core Register Summary
User-Level Registers
General-Purpose Registers
0
31 32
63
(upper) GPR02 (lower)
GPR1
GPR2
0
Generalpurpose
registers
Performance Monitor Registers
(read-only PMRs)
pmr 384 UPMGC03
Global control register
UPMCs 3
Counter
registers 0–3
Local control registers
a0–a3
Local control registers
b0–b3
pmr 128–131 UPMLCa0–33
pmr 256–259 UPMLCb0–33
31 32
User General SPR (read/write)
63
CR
GPR31
pmr 0–3
Instruction-Accessible Registers
Condition register
spr 9
CTR
spr 8
LR
Link register
spr 1
XER
Integer exception
register
SPE FP status/control
register
Accumulator
Count register
spr 512 SPEFSCR3
ACC3
Miscellaneous Registers
3
spr 513
BBEAR
spr 514
BBTAR3
Branch buffer entry
address register
Branch buffer target
address register
spr 256
32
63
USPRG0
User SPR
general 01
General SPRs (read only)
spr 259
spr 260
SPRG3
SPRG4
SPR general
registers 3–7
• • •
spr 263
SPRG7
Time-Base Registers (read only)
TBL
spr 268
spr 269
Time base
lower/upper
TBU
L1 Cache (read only)
spr 515
spr 516
L1CFG03
L1 cache
configuration registers
0–1
L1CFG13
Supervisor-Level Registers
Interrupt Registers
32
spr 63
63
IVPR
spr 26
spr 27
SRR0
SRR1
spr 58
spr 59
CSRR0
CSRR1
spr 570 MCSRR03
spr 571 MCSRR13
spr 62
ESR
spr 572
MCSR3
spr 573
MCAR
spr 569
MCARU 4
spr 61
DEAR
Interrupt vector
prefix
Save/restore
registers 0/1
DBCR0
DBCR1
spr 310
DBCR2
spr 304
DBSR
spr 312
IAC1
spr 313
IAC2
spr 316
spr 317
DAC1
DAC2
63
spr 400
IVOR0
spr 401
IVOR1
• • •
32
Interrupt vector offset
registers 0–15
spr 1023
63
MSR
Machine state
SVR
System version
spr 415
IVOR15
spr 286
PIR
Processor ID
Critical SRR 0/1
spr 528
spr 287
PVR
Processor version
Machine check
SRR 0/1
spr 529
spr 530
spr 531
IVOR323
IVOR333
IVOR343
IVOR353
Interrupt vector offset
registers 32–35
MMU Control and Status (read/write)
Machine check
syndrome register
Machine check
address register
Machine check
address register upper
Data exception
address register
spr 1012 MMUCSR0 3
Debug control
registers 0–2
Debug status register
Instruction address
compare
registers 1–4
Data address
compare
registers 1 and 2
spr 624
spr 625
MAS0 3
MAS1 3
spr 626
spr 627
spr 628
MAS2 3
spr 630
spr 944
MAS3 3
MAS4 3
MMU control and status
register 0
MMU assist
registers
0–4 and 6
MAS7 4
spr 48
PID0
PID13
PID23
TLB0CFG3
spr 688
spr 689 TLB1CFG3
Decrementer
spr 54
DECAR
Decrementer
auto-reload
spr 284
spr 285
TBL
TBU
Time base
lower/upper
spr 340
TCR
Timer control
spr 336
TSR
Timer status
spr 1009
HID03
HID13
spr 1013
BUCSR5
spr 272–279
SPRG0–7
spr 1008
Process ID
registers 0–2
MMU Control and Status (read only)
spr 1015 MMUCFG3
DEC
Miscellaneous Registers
MAS6 3
spr 633
spr 634
Timer/Decrementer Registers
spr 22
Exception syndrome
register
Debug Registers
spr 308
spr 309
Configuration Registers
32
MMU configuration
TLB configuration 0/1
Hardware
implementation
dependent 0–1
Branch control and
status register
General SPRs 0–7
Performance Monitor Registers
pmr 400
PMGC03
pmr 16–19
3
PMC0–3
Global control
Counter registers 0–3
3
L1 Cache (read/write)
spr 1010
spr 1011
1
2
3
4
5
L1CSR03
L1CSR13
pmr 144–147 PMLCa0–3
pmr 272–275 PMLCb0–33
Local control a0–a3
Local control b0–b3
L1 Cache
Control/Status 0/1
USPRG0 is a separate physical register from SPRG0.
The 64-bit GPR registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word.
These registers are defined by the EIS and are not part of the Book E architecture.
e500v2 only
These registers are e500-specific
Figure 6-1. Core Register Model
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Core Register Summary
6.2
Register Model for 32-Bit Implementations
Embedded 32-bit processors implement the following types of software-accessible registers:
• Architecture-defined registers that are accessed as part of instruction execution. These include the
following:
— Registers used for computation. These include the following:
– General-purpose registers (GPRs)—The 32 GPRs hold source and destination operands for
load, store, arithmetic, and computational instructions, and to read and write to other
registers. The e500 implements these as 64-bit registers for use with 64-bit load, store, and
merge instructions, as described in Section 6.3.1, “General-Purpose Registers (GPRs).”
– Integer exception register (XER)—Bits in this register are set based on the operation of an
instruction considered as a whole, not on intermediate results. (For example, the Subtract
from Carrying instruction (subfc), the result of which is specified as the sum of three values,
sets bits in the XER based on the entire operation, not on an intermediate sum.)
These registers are described in Section 6.3, “Registers for Computational Operations.”
— Condition register (CR)—Used to record conditions such as overflows and carries that occur
as a result of executing arithmetic instructions (including those implemented by the SPE). The
CR is described in Section 6.4, “Registers for Branch Operations.”
— Machine state register (MSR)—Used by the operating system to configure parameters such as
user/supervisor mode, address space, and enabling of asynchronous interrupts. This register is
described in Section 6.5.1, “Machine State Register (MSR),” grouped with processor control
SPRs.
• Special-purpose registers (SPRs) are accessed explicitly using mtspr and mfspr instructions.
These registers are listed in Table 6-1 in Section 6.2.1, “Special-Purpose Registers (SPRs).”
• Freescale EIS– and e500-defined SPRs that are accessed explicitly using mtspr and mfspr are
listed in Table 6-2 in Section 6.2.1, “Special-Purpose Registers (SPRs).”
• Freescale EIS–defined performance monitor registers (PMRs). These registers are similar to SPRs,
but are accessed with Freescale EIS–defined move to and move from PMR instructions (mtpmr
and mfpmr).
In this chapter, SPRs are grouped by function as follows:
• Section 6.4, “Registers for Branch Operations,” describes the count register (CTR) and the link
register (LR).
• Section 6.5, “Processor Control Registers”
• Section 6.6, “Timer Registers”
• Section 6.7, “Interrupt Registers”
• Section 6.8, “Software-Use SPRs (SPRG0–SPRG7 and USPRG0),” describes SPRs defined for
software use.
• Section 6.9, “Branch Target Buffer (BTB) Registers,” describes e500-specific registers defined to
support the e500 tabs.
• Section 6.10, “Hardware Implementation-Dependent Registers,” describes HID0 and HID1.
• Section 6.11, “L1 Cache Configuration Registers”
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Core Register Summary
•
•
•
Section 6.12, “MMU Registers”
Section 6.13, “Debug Registers”
Section 6.14, “Signal Processing and Embedded Floating-Point Status and Control Register
(SPEFSCR)”
The e500 core implements 64-bit GPRs, the upper 32 bits of which are used only with 64-bit load, store,
and merge instructions.
6.2.1
Special-Purpose Registers (SPRs)
Table 6-1 summarizes SPRs. The SPR numbers are used in the instruction mnemonics. Bit 5 in an SPR
number indicates whether an SPR is accessible from user- or supervisor-level software. An mtspr or
mfspr instruction that specifies an unsupported SPR number is considered an invalid instruction.
In Table 6-1 and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
• Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
NOTE
Writing to the following registers requires synchronization, as described in
the “Synchronization Requirements” section in the “Register Model”
chapter of the PowerPC™ e500 Core Family Reference Manual.
•
•
•
•
•
•
BTB locking registers—BBEAR, BBTAR, and BUCSR
DBCRn
HIDn
L1CSRn
MMU registers—MASn, MMUCSR0, PIDn
SPEFSCR
Table 6-1. Base and Embedded Category Special-Purpose Registers (by SPR Abbreviation)
Defined SPR Number
SPR
Abbreviation
Name
Decimal
Binary
Access
Supervisor
Only
Section/
Page
CSRR0
Critical save/restore register 0
58
00001 11010
Read/Write
Yes
6.7.1.1/6-17
CSRR1
Critical save/restore register 1
59
00001 11011
Read/Write
Yes
6.7.1.2/6-17
Count register
9
00000 01001
Read/Write
No
6.4.3/6-11
CTR
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Core Register Summary
Table 6-1. Base and Embedded Category Special-Purpose Registers (by SPR Abbreviation) (continued)
Defined SPR Number
SPR
Abbreviation
Name
Decimal
Binary
Access
Supervisor
Only
Section/
Page
Read/Write
Yes
6.13.4/6-45
6.13.1/6-39
DAC1
Data address compare 1
316
01001 11100
DAC2
Data address compare 2
317
01001 11101
DBCR0
Debug control register 0 1
308
01001 10100
Read/Write
Yes
DBCR1
Debug control register 1
1
309
01001 10101
Read/Write
Yes
DBCR2
Debug control register 2 1
310
01001 10110
Read/Write
Yes
Yes
6.13.2/6-43
DBSR
Debug status register
304
01001 10000
w1c2
DEAR
Data exception address register
61
00001 11101
Read/Write
Yes
6.7.1.5/6-18
Decrementer
22
00000 10110
Read/Write
Yes
6.6.4/6-16
Decrementer auto-reload
54
00001 10110
Write only
ESR
Exception syndrome register
62
00001 11110
Read/Write
Yes
6.7.1.8/6-19
IAC1
Instruction address compare 1
312
01001 11000
Read/Write
Yes
6.13.3/6-45
IAC2
Instruction address compare 2
313
01001 11001
IVOR0
Critical input
400
01100 10000
Read/Write
Yes
6.7.1.7/6-18
IVOR1
Machine check interrupt offset
401
01100 10001
IVOR2
Data storage interrupt offset
402
01100 10010
IVOR3
Instruction storage interrupt offset
403
01100 10011
IVOR4
External input interrupt offset
404
01100 10100
IVOR5
Alignment interrupt offset
405
01100 10101
IVOR6
Program interrupt offset
406
01100 10110
IVOR8
System call interrupt offset
408
01100 11000
IVOR10
Decrementer interrupt offset
410
01100 11010
IVOR11
Fixed-interval timer interrupt offset
411
01100 11011
IVOR12
Watchdog timer interrupt offset
412
01100 11100
IVOR13
Data TLB error interrupt offset
413
01100 11101
IVOR14
Instruction TLB error interrupt offset
414
01100 11110
IVOR15
Debug interrupt offset
415
01100 11111
Interrupt vector
63
00001 11111
Read/Write
Yes
6.7.1.6/6-18
LR
Link register
8
00000 01000
Read/Write
No
6.4.2/6-11
PID
Process ID register 3
48
00001 10000
Read/Write
Yes
6.12.1/6-32
PIR
Processor ID register
286
01000 11110
Read only
Yes
6.5.2/6-13
PVR
Processor version register
287
01000 11111
Read only
Yes
6.5.3/6-13
DEC
DECAR
IVPR
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Core Register Summary
Table 6-1. Base and Embedded Category Special-Purpose Registers (by SPR Abbreviation) (continued)
Defined SPR Number
SPR
Abbreviation
Read/Write
Yes
SPRG1
SPR general 1
273
01000 10001
Read/Write
Yes
SPRG2
SPR general 2
274
01000 10010
Read/Write
Yes
SPRG3
SPR general 3
259
01000 00011
Read only
No4
275
01000 10011
Read/Write
Yes
260
01000 00100
Read only
No
276
01000 10100
Read/Write
Yes
261
01000 00101
Read only
No
277
01000 10101
Read/Write
Yes
262
01000 00110
Read only
No
278
01000 10110
Read/Write
Yes
263
01000 00111
Read only
No
279
01000 10111
Read/Write
Yes
SPR general 5
SPR general 6
SPR general 7
6.8/6-22
Save/restore register 0
26
00000 11010
Read/Write
Yes
6.7.1.1/6-17
SRR1
Save/restore register 1
27
00000 11011
Read/Write
Yes
6.7.1.2/6-17
Time base lower
268
01000 01100
Read only
No
6.6.3/6-16
284
01000 11100
Write only
Yes
269
01000 01101
Read only
No
285
01000 11101
Write only
Yes
TBU
Time base upper
TCR
Timer control register
340
01010 10100
Read/Write
Yes
6.6.1/6-14
TSR
Timer status register
336
01010 10000
w1c5
Yes
6.6.2/6-15
06
256
01000 00000
Read/Write
No
6.8/6-22
1
00000 00001
Read/Write
No
6.3.2/6-8
USPRG0
XER
6
SPR general 4
SRR0
TBL
5
6.8/6-22
01000 10000
SPRG7
4
Section/
Page
272
SPRG6
3
Binary
Supervisor
Only
SPR general 0
SPRG5
2
Decimal
Access
SPRG0
SPRG4
1
Name
User SPR general
Integer exception register
Accesses to this register requires synchronization, as described in the “Synchronization Requirements” section of the
“Register Model” chapter of the PowerPC™ e500 Core Family Reference Manual
The DBSR is read using mfspr. It cannot be directly written to. Instead, DBSR bits corresponding to 1 bits in the GPR can be
cleared using mtspr.
Implementations may support more than one PID. For implementations with multiple PIDs, the PID defined by the embedded
category is PID0.
User-mode read access to SPRG3 is implementation dependent.
The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be
cleared using mtspr.
USPRG0 is a separate physical register from SPRG0.
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Core Register Summary
Table 6-2 describes the implementation-specific SPRs and SPRs defined by categories other than the base
and embedded categories. Compilers should recognize the mnemonic names given in Table 6-2 when
parsing instructions.
Table 6-2. Additional SPRs (by SPR Abbreviation)
SPR
Abbreviation
Name
BBEAR
Branch buffer entry address register 1
BBTAR
Branch buffer target address register 1
BUCSR
Branch unit control and status register
1
SPR Number
Access
Supervisor
Only
Section/
Page
513
Read/Write
No
6.9.1/6-23
514
Read/Write
No
6.9.2/6-23
1013
Read/Write
Yes
6.9.3/6-24
HID0
Hardware implementation dependent reg 0 1
1008
Read/Write
Yes
6.10.1/6-25
HID1
1
1009
Read/Write
Yes
6.10.2/6-26
6.7.1.7/6-18
Hardware implementation dependent reg 1
IVOR32
SPE unavailable interrupt offset
528
Read/Write
Yes
IVOR33
Floating-point data exception interrupt offset
529
Read/Write
Yes
IVOR34
Floating-point round exception interrupt offset
530
Read/Write
Yes
IVOR35
Performance monitor
531
Read/Write
Yes
L1CFG0
L1 cache configuration register 0
515
Read only
No
6.11.3/6-30
L1CFG1
L1 cache configuration register 1
516
Read only
No
6.11.4/6-31
L1CSR0
L1 cache control and status register 0 1
1010
Read/Write
Yes
6.11.1/6-28
L1CSR1
1
1011
Read/Write
Yes
6.11.2/6-29
L1 cache control and status register 1
MAS0
MMU assist register 0 1
624
Read/Write
Yes
6.12.5.1/6-35
MAS1
MMU assist register 1
1
625
Read/Write
Yes
6.12.5.2/6-35
MAS2
MMU assist register 2 1
626
Read/Write
Yes
6.12.5.3/6-36
MAS3
MMU assist register 3
1
627
Read/Write
Yes
6.12.5.4/6-37
MAS4
MMU assist register 4 1
628
Read/Write
Yes
6.12.5.5/6-38
MAS6
MMU assist register 6
1
630
Read/Write
Yes
6.12.5.6/6-38
MAS7
MMU assist register 7 1
944
Read/Write
Yes
6.12.5.7/6-39
MCAR
Machine check address register
573
Read only
Yes
6.7.2.3/6-21
Machine check address register upper
569
Read only
Yes
6.7.2.3/6-21
Machine check syndrome register
572
Read/Write
Yes
6.7.2.4/6-21
MCSRR0
Machine check save/restore register 0
570
Read/Write
Yes
6.7.2.1/6-20
MCSRR1
Machine check save/restore register 1
571
Read/Write
Yes
6.7.2.2/6-20
MMUCFG
MMU configuration register
1015
Read only
Yes
6.12.3/6-32
1012
Read/Write
Yes
6.12.2/6-32
MCARU
MCSR
MMUCSR0
MMU control and status register 0
1
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Core Register Summary
Table 6-2. Additional SPRs (by SPR Abbreviation) (continued)
SPR
Abbreviation
SPR Number
Access
Supervisor
Only
Section/
Page
6.12.1/6-32
PID0
Process ID register 0 1
48
Read/Write
Yes
PID1
Process ID register 1 1
633
Read/Write
Yes
PID2
1
634
Read/Write
Yes
Signal processing and embedded floating-point
status and control register 1
512
Read/Write
No
6.14/6-45
System version register
1023
Read only
Yes
6.5.4/6-14
TLB0CFG
TLB configuration register 0
688
Read only
Yes
6.12.4/6-33
TLB1CFG
TLB configuration register 1
689
Read only
Yes
6.12.4.2/6-34
SPEFSCR
SVR
1
Name
Process ID register 2
Accesses to this register requires synchronization, as described in the “Synchronization Requirements” section of the
“Register Model” chapter of the PowerPC™ e500 Core Family Reference Manual.
6.3
Registers for Computational Operations
The following sections describe general-purpose and integer exception registers.
NOTE
Register fields designated as write-one-to-clear are cleared only by writing
ones to them. Writing zeros to them has no effect.
6.3.1
General-Purpose Registers (GPRs)
GPR0–GPR31 support integer operations. The instruction formats provide 5-bit fields for specifying the
GPRs to be used in the execution of the instruction. Each GPR is a 64-bit register, although only 64-bit
load, store, and merge instructions use GPR bits 0–31.
6.3.2
Integer Exception Register (XER)
SPR 1
R
W
Reset
Access: User read/write
32
33
34
SO
OV
CA
35
56 57
—
63
Number of bytes
All zeros
Figure 6-2. Integer Exception Register (XER)
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Core Register Summary
Table 6-3. XER Field Description
Bits
Name
Description
32
SO
Summary overflow. Set when an instruction (except mtspr) sets the overflow bit. Once set, SO remains
set until it is cleared by mtspr[XER] or mcrxr. SO is not altered by compare instructions or by other
instructions (except mtspr[XER] and mcrxr) that cannot overflow. Executing mtspr[XER], supplying the
values 0 for SO and 1 for OV, causes SO to be cleared and OV to be set.
33
OV
Overflow. X-form add, subtract from, and negate instructions having OE = 1 set OV if the carry out of bit
32 is not equal to the carry out of bit 33, and clear OV otherwise to indicate a signed overflow. X-form
multiply low word and divide word instructions having OE = 1 set OV if the result cannot be represented in
32 bits (mullwo, divwo, and divwuo) and clear OV otherwise. OV is not altered by compare instructions
or by other instructions (except mtspr[XER] and mcrxr) that cannot overflow.
34
CA
Carry. Add carrying, subtract from carrying, add extended, and subtract from extended instructions set CA
if there is a carry out of bit 32 and clear it otherwise. CA can be used to indicate unsigned overflow for add
and subtract operations that set CA. Shift right algebraic word instructions set CA if any 1 bits are shifted
out of a negative operand and clear CA otherwise. Compare instructions and instructions that cannot carry
(except Shift Right Algebraic Word, mtspr[XER], and mcrxr) do not affect CA.
35–56
—
Reserved, should be cleared.
57–63
No. of
bytes
6.4
Supports emulation of load and store string instructions. Specifies the number of bytes to be transferred by
a load string indexed or store string indexed instruction.
Registers for Branch Operations
This section describes registers that support branch and CR operations.
6.4.1
Condition Register (CR)
Access: User read/write
32
R
W
35 36
39 40
CR0
CR1
Reset
43 44
CR2
47 48
CR3
51 52
CR4
55 56
CR5
59 60
CR6
63
CR7
All zeros
Figure 6-3. Condition Register (CR)
Table 6-4. BI Operand Settings for CR Fields
CRn Bits
CR Bits
BI
Description
CR0[0]
32
00000
Negative (LT)—Set when the result is negative.
For SPE vector compare and vector test instructions:
Set if the high-order element of rA is equal to the high-order element of rB; cleared otherwise.
CR0[1]
33
00001
Positive (GT)—Set when the result is positive (and not zero).
For SPE vector compare and vector test instructions:
Set if the low-order element of rA is equal to the low-order element of rB; cleared otherwise.
CR0[2]
34
00010
Zero (EQ)—Set when the result is zero. For SPE vector compare and vector test instructions:
Set to the OR of the result of the compare of the high and low elements.
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Core Register Summary
Table 6-4. BI Operand Settings for CR Fields (continued)
CRn Bits
CR Bits
BI
CR0[3]
35
00011
Summary overflow (SO). Copy of XER[SO] at the instruction’s completion.
For SPE vector compare and vector test instructions:
Set to the AND of the result of the compare of the high and low elements.
CR1[0]
36
00100
Negative (LT)
For SPE vector compare and vector test instructions:
Set if the high-order element of rA is equal to the high-order element of rB; cleared otherwise.
CR1[1]
37
00101
Positive (GT)
For SPE vector compare and vector test instructions:
Set if the low-order element of rA is equal to the low-order element of rB; cleared otherwise.
CR1[2]
38
00110
Zero (EQ)
For SPE vector compare and vector test instructions:
Set to the OR of the result of the compare of the high and low elements.
CR1[3]
39
00111
Summary overflow (SO)
For SPE vector compare and vector test instructions:
Set to the AND of the result of the compare of the high and low elements.
CRn[0]
40
44
48
52
56
60
01000
01100
10000
10100
11000
11100
Less than (LT)
For integer compare instructions:
rA < SIMM or rB (signed comparison) or rA < UIMM or rB (unsigned comparison).
For SPE vector compare and vector test instructions:
Set if the high-order element of rA is equal to the high-order element of rB; cleared otherwise.
CRn[1]
41
45
49
53
57
61
01001
01101
10001
10101
11001
11101
Greater than (GT)
For integer compare instructions:
rA > SIMM or rB (signed comparison) or rA > UIMM or rB (unsigned comparison).
For SPE vector compare and vector test instructions:
Set if the low-order element of rA is equal to the low-order element of rB; cleared otherwise.
CRn[2]
42
46
50
54
58
62
01010
01110
10010
10110
11010
11110
Equal (EQ)
For integer compare instructions:
rA = SIMM, UIMM, or rB.
For SPE vector compare and vector test instructions:
Set to the OR of the result of the compare of the high and low elements.
CRn[3]
43
47
51
55
59
63
01011
01111
10011
10111
11011
11111
Summary overflow (SO)
For integer compare instructions, this is a copy of XER[SO] at the completion of the
instruction.
For SPE vector compare and vector test instructions:
Set to the AND of the result of the compare of the high and low elements.
Description
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Core Register Summary
The bits of CR0 are interpreted as described in Table 6-5.
Table 6-5. CR0 Bit Descriptions
CR Bit
Name
32
Negative (LT)
Bit 32 of the result is equal to 1.
33
Positive (GT)
Bit 32 of the result is equal to 0 and at least one bit from 33–63 of the result is non-zero.
34
Zero (EQ)
35
Description
Bits 32–63 of the result are equal to 0.
Summary overflow (SO) This is a copy of the final state of XER[SO] at the completion of the instruction.
6.4.2
Link Register (LR)
SPR 8
Access: User read/write
32
63
R
Link address
W
Reset
All zeros
Figure 6-4. Link Register (LR)
6.4.3
Count Register (CTR)
SPR 9
Access: User read/write
32
63
R
Count value
W
Reset
All zeros
Figure 6-5. Count Register (CTR)
6.5
Processor Control Registers
This section addresses machine state, processor ID, and processor version registers.
6.5.1
Machine State Register (MSR)
Access: Supervisor read/write
32
R
W
36
—
37
38
UCLE SPE
Reset
39
44
—
45
46 47 48
49
50
51 52
53
54 55
WE CE — EE PR — ME — UBLE DE
57 58 59 60
—
61
IS DS — PMM
62 63
—
All zeros
Figure 6-6. Machine State Register (MSR)
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Core Register Summary
Table 6-6. MSR Field Descriptions
Bits
Name
32–36
—
37
38
Description
Reserved, should be cleared.1
UCLE User-mode cache lock enable. Used to restrict user-mode cache-line locking by the operating system
0 Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and sets either
ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the locking/unlocking of cache
lines by user-mode tasks.
1 Cache-locking instructions can be executed in user-mode and they do not take a DSI for cache-locking (they
may still take a DSI for access violations though).
SPE
SPE enable. (e500-specific).
0 If software attempts to execute an instruction that accesses the upper word of a GPR, the SPE unavailable
exception is taken.
1 Software can execute the following instructions:
These instructions include the SPE instructions, embedded double-precision, and single-precision vector
floating-point instructions. (That is, all instructions that access the upper half of the 64-bit GPRs.)
39–44
—
Reserved, should be cleared. 1
45
WE
Wait state enable. Allows the core complex to signal a request for power management, according to the states
of HID0[DOZE], HID0[NAP], and HID0[SLEEP].
0 The processor is not in wait state and continues processing. No power management request is signaled to
external logic.
1 The processor enters wait state by ceasing to execute instructions and entering low-power mode. Details of
how wait state is entered and exited and how the processor behaves in the wait state are
implementation-dependent. On the e500, MSR[WE] gates the DOZE, NAP, and SLEEP outputs from the core
complex; as a result, these outputs negate to the external power management logic on entry to the interrupt
and then return to their previous state on return from the interrupt. WE is cleared on entry to any interrupt and
restored to its previous state upon return.
46
CE
Critical enable
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.
47
—
Reserved, should be cleared. 1
48
EE
External enable
0 External input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled.
1 External input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled.
49
PR
User mode (problem state)
0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for example,
GPRs, SPRs, and the MSR).
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged
resource.
PR also affects memory access control
50
—
Reserved, should be cleared. 1
51
ME
Machine check enable
0 Machine check interrupts are disabled.
1 Machine check interrupts are enabled.
52
—
Reserved, should be cleared. 1
53
UBLE In the e500, it is the user BTB lock enable bit.
0 User-mode execution of the BTB lock instructions is disabled; privileged instruction exception taken instead.
1 User-mode execution of the BTB lock instructions for user mode is enabled.
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Core Register Summary
Table 6-6. MSR Field Descriptions (continued)
Bits
Name
54
DE
Debug interrupt enable. See the description of the DBSR[UDE] in Section 6.13.2, “Debug Status Register
(DBSR).”
0 Debug interrupts are disabled.
1 Debug interrupts are enabled if DBCR0[IDM] = 1.
55–57
—
Reserved, should be cleared. 1
58
IS
Instruction address space
0 The processor directs all instruction fetches to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs all instruction fetches to address space 1 (TS = 1 in the relevant TLB entry).
59
DS
Data address space
0 The processor directs data memory accesses to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs data memory accesses to address space 1 (TS = 1 in the relevant TLB entry).
60
—
Reserved, should be cleared. 1
61
PMM Performance monitor mark bit. System software can set PMM when a marked process is running to enable
statistics to be gathered only during execution of the marked process. MSR[PR] and MSR[PMM] together define
a state that the processor (supervisor or user) and the process (marked or unmarked) may be in at any time. If
this state matches an individual state specified in the PMLCax, the state for which monitoring is enabled,
counting is enabled.
62–63
1
Description
—
Preserved for OEA-defined RI and LE, respectively
An MSR bit that is reserved may be altered by a return from interrupt instruction.
6.5.2
Processor ID Register (PIR)
SPR 286
Access: Supervisor read only
32
63
R
Processor ID
W
Reset
All zeros
Figure 6-7. Processor ID Register (PIR)
6.5.3
Processor Version Register (PVR)
SPR 287
Access: Supervisor read only
32
47 48
R
Version
63
Revision
W
Reset
SoC-dependent value. See Section 5.2, “e500 Processor and System Version Numbers.”
Figure 6-8. Processor Version Register (PVR)
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Core Register Summary
Table 6-7. PVR Field Descriptions
Bits
Name
32–47
Version
48–63
Revision A 16-bit number that distinguishes between implementations of the version. Different revision numbers
indicate minor differences between processors having the same version number, such as clock rate and
engineering change level. (See Section 5.2, “e500 Processor and System Version Numbers,” for specific
values.)
6.5.4
Description
A 16-bit number that identifies the version of the processor. Different version numbers indicate major
differences between processors, such as which optional facilities and instructions are supported. (See
Section 5.2, “e500 Processor and System Version Numbers,” for specific values.)
System Version Register (SVR)
SPR 1023
Access: Supervisor read only
32
63
R
System version
W
Reset
SoC-dependent value. See Section 5.2, “e500 Processor and System Version Numbers.”
Figure 6-9. System Version Register (SVR)
Table 6-8. SVR Field Descriptions
Bits
Name
Description
32–63 System version
6.6
A 16-bit number that identifies the SoC version. See Section 5.2, “e500 Processor and System
Version Numbers,” for specific values.
Timer Registers
6.6.1
Timer Control Register (TCR)
SPR 340
Access: Supervisor read/write
32 33 34 35
R
W
Reset
WP
36
37
WRC WIE DIE
38 39
FP
40
41
42 43
FIE ARE —
46 47
WPEXT
50 51
FPEXT
63
—
All zeros
Figure 6-10. Timer Control Register (TCR)
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Core Register Summary
Table 6-9. TCR Field Descriptions
Bits
Name
Description
32–33
WP
Watchdog timer period. When concatenated with WPEXT, specifies one of 64-bit locations of the time base
used to signal a watchdog timer exception on a transition from 0 to 1.
WPEXT[0–3] || WP[0–1] = 0b00_0000 selects TBU[32] (the msb of the TB)
WPEXT[0–3] || WP[0–1] = 0b11_1111 selects TBL[63] (the lsb of the TB)
34–35
WRC
Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC
may be set by software but cannot be cleared by software, except by a software-induced reset. Once written
to a non-zero value, WRC may no longer be altered by software.
00 No watchdog timer reset will occur.
01 A second timeout is ignored, regardless of the value of MSR[ME].
10 Assert processor reset output (core_hreset_req) on second timeout of watchdog timer
11 Reserved
36
WIE
Watchdog timer interrupt enable
0 Watchdog timer interrupts disabled
1 Watchdog timer interrupts enabled
37
DIE
Decrementer interrupt enable
0 Decrementer interrupts disabled
1 Decrementer interrupts enabled
38–39
FP
Fixed interval timer period. When concatenated with FPEXT, FP specifies one of 64 bit locations of the time
base used to signal a fixed-interval timer exception on a transition from 0 to 1.
FPEXT[0–3] || FP[0–1] = 0b00_0000 selects TBU[32] (the msb of the TB)
FPEXT[0–3] || FP[0–1] = 0b11_1111 selects TBL[63] (the lsb of the TB)
40
FIE
Fixed interval interrupt enable
0 Fixed interval interrupts disabled
1 Fixed interval interrupts enabled
41
ARE
Auto-reload enable. Controls whether the DECAR value is reloaded into the DEC when the DEC value
reaches 0000_0001. See EREF: A Reference for Freescale Book E and the e500 Core.
0 Auto-reload disabled
1 Auto-reload enabled
42
—
Reserved, should be cleared.
43–46
WPEXT Watchdog timer period extension (see the description for WP)
47–50
FPEXT
51–63
—
6.6.2
Fixed-interval timer period extension (see the description for FP)
Reserved, should be cleared.
Timer Status Register (TSR)
Access: Supervisor w1c1
SPR 336
36
37
R ENW
32
WIS
33
34
WRS
DIS
FIS
W w1c
w1c
w1c
w1c
w1c
Reset
35
38
63
—
All zeros
1
Set by hardware. Read with mfspr and cleared with mtspr by writing ones to any TSR bit positions to be cleared and
zeros in all other bit positions.
Figure 6-11. Timer Status Register (TSR)
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Core Register Summary
Table 6-10. TSR Field Descriptions
Bits
Name
Description
32
ENW Enable next watchdog time. Functions as write-one-to-clear.
0 Action on next watchdog timer time-out is to set TSR[ENW]
1 Action on next watchdog timer time-out is governed by TSR[WIS]
When a watchdog timer time-out occurs while WIS = 0 and the next watchdog time-out is enabled
(ENW = 1), a watchdog timer exception is generated and logged by setting WIS. This is referred to as
a watchdog timer first time out. A watchdog timer interrupt occurs if enabled by TCR[WIE] and
MSR[CE]. To avoid another watchdog timer interrupt once MSR[CE] is reenabled, (assuming
TCR[WIE] is not cleared instead), the interrupt handler must reset TSR[WIS].
33
WIS
Watchdog timer interrupt status. Functions as write-one-to-clear.
0 A watchdog timer event has not occurred.
1 A watchdog timer event occurred. When MSR[CE] = 1 and TCR[WIE] = 1, a watchdog timer
interrupt is taken.
See the description of ENW for more information about how WIS is used.
34–35 WRS Watchdog timer reset status. Functions as write-one-to-clear. Defined at reset (value = 00). Set to
TCR[WRC] when a reset is caused by the watchdog timer.
36
DIS
Decrementer interrupt status. Functions as write-one-to-clear.
0 A decrementer event has not occurred.
1 A decrementer event occurred. When MSR[EE] = TCR[DIE] = 1, a decrementer interrupt is taken.
37
FIS
Fixed-interval timer interrupt status. Functions as write-one-to-clear.
0 A fixed-interval timer event has not occurred.
1 A fixed-interval timer event occurred. When MSR[EE] = 1 and TCR[FIE] = 1, a fixed-interval timer
interrupt is taken.
38–63
—
Reserved, should be cleared.
6.6.3
Time Base Registers
SPR TBU: 269 read/285 write
TBL: 268 read/284 write
Access: User read/Supervisor write
32
R
63 32
TBU
W
Reset
63
TBL
All zeros
Figure 6-12. Time Base Upper/Lower Registers (TBU/TBL)
6.6.4
Decrementer Register
SPR 22
Access: Supervisor read/write
32
63
R
W
Reset
Decrementer value
All zeros
Figure 6-13. Decrementer Register (DEC)
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Core Register Summary
6.6.5
Decrementer Auto-Reload Register (DECAR)
SPR 54
Access: Supervisor write only
32
63
R
W
Decrementer auto-reload value
Reset
All zeros
Figure 6-14. Decrementer Auto-Reload Register (DECAR)
6.7
Interrupt Registers
6.7.1
Interrupt Registers Defined by the Embedded and Base Categories
6.7.1.1
Save/Restore Register 0 (SRR0)
SPR 26
Access: Supervisor read/write
32
63
R
Next instruction address
W
Reset
All zeros
Figure 6-15. Save/Restore Register 0 (SRR0)
6.7.1.2
Save/Restore Register 1 (SRR1)
SPR 27
Access: Supervisor read/write
32
63
R
MSR state information
W
Reset
All zeros
Figure 6-16. Save/Restore Register 1 (SRR1)
6.7.1.3
Critical Save/Restore Register 0 (CSRR0)
SPR 58
Access: Supervisor read/write
32
63
R
Next instruction address
W
Reset
All zeros
Figure 6-17. Critical Save/Restore Register 0 (CSRR0)
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Core Register Summary
6.7.1.4
Critical Save/Restore Register 1 (CSRR1)
SPR 59
Access: Supervisor read/write
32
63
R
MSR state information
W
Reset
All zeros
Figure 6-18. Critical Save/Restore Register 1 (CSRR1)
6.7.1.5
Data Exception Address Register (DEAR)
SPR 61
Access: Supervisor read/write
32
63
R
Exception address
W
Reset
All zeros
Figure 6-19. Data Exception Address Register (DEAR)
6.7.1.6
Interrupt Vector Prefix Register (IVPR)
SPR 63
Access: Supervisor read/write
32
47 48
R
63
Interrupt vector prefix
W
Reset
—
All zeros
Figure 6-20. Interrupt Vector Prefix Register (IVPR)
6.7.1.7
Interrupt Vector Offset Registers (IVORn)
SPR (See Table 6-11.)
Access: Supervisor read/write
32
47 48
R
—
W
59 60
Interrupt vector offset
Reset
63
—
All zeros
Figure 6-21. Interrupt Vector Offset Registers (IVORn)
Table 6-11. IVOR Assignments
IVOR Number
SPR
Interrupt Type
IVOR0
400
Critical input
IVOR1
401
Machine check
IVOR2
402
Data storage
IVOR3
403
Instruction storage
IVOR4
404
External input
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Core Register Summary
Table 6-11. IVOR Assignments (continued)
6.7.1.8
IVOR Number
SPR
Interrupt Type
IVOR5
405
Alignment
IVOR6
406
Program
IVOR8
408
System call
IVOR10
410
Decrementer
IVOR11
411
Fixed-interval timer interrupt
IVOR12
412
Watchdog timer interrupt
IVOR13
413
Data TLB error
IVOR14
414
Instruction TLB error
IVOR15
415
Debug
IVOR16–IVOR31
—
IVOR32
528
SPE unavailable
IVOR33
529
Floating-point data exception
IVOR34
530
Floating-point round exception
IVOR35
531
Performance monitor
IVOR36–IVOR63
—
Reserved for future architectural use
Allocated for implementation-dependent use
Exception Syndrome Register (ESR)
SPR 62
Access: Supervisor read/write
32
R
W
35
—
36
37
PIL
PPR
38
39
40
41
PTR — ST —
Reset
42
43
DLK
ILK
44
45
—
46
47
BO
55
—
56
57
SPE
63
—
All zeros
Figure 6-22. Exception Syndrome Register (ESR)
Table 6-12. ESR Field Descriptions
Bits
Name
Syndrome
Interrupt Types
32–35
—
Reserved, should be cleared.
—
36
PIL
Illegal instruction exception
Program
37
PPR
Privileged instruction exception
Program
38
PTR
Trap exception
Program
39
—
Reserved and permanently cleared because the e500 does not implement this FPU. —
Setting it has no effect.
40
ST
Store operation
Alignment, data
storage, data TLB
error
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Core Register Summary
Table 6-12. ESR Field Descriptions (continued)
Bits
Name
41
—
42
Syndrome
Interrupt Types
Reserved, should be cleared.
—
DLK
Cache locking. Settings are implementation-dependent.
0 Default
1 On the e500, DLK is set when a DSI occurs because dcbtls, dcbtstls, or dcblc
is executed in user mode while MSR[UCLE] = 0.
Data storage
43
ILK
Set when a DSI occurs because icbtl or icblc is executed in user mode
(MSR[PR] = 1) and MSR[UCLE] = 0
Data storage
44–45
—
Reserved, should be cleared.
46
BO
Byte-ordering exception
Data storage,
instruction storage
47–55
—
Reserved, should be cleared.
—
56
SPE
SPE exception bit (e500-specific)
0 Default
1 Any exception caused by an SPE or SPFP instruction
SPE unavailable
57–63
—
Reserved, should be cleared.
—
6.7.2
Additional Interrupt Registers
6.7.2.1
Machine Check Save/Restore Register 0 (MCSRR0)
SPR 570
Access: Supervisor read/write
32
R
63
Next instruction address
W
Reset
All zeros
Figure 6-23. Machine Check Save/Restore Register 0 (MCSRR0)
6.7.2.2
Machine Check Save/Restore Register 1 (MCSRR1)
SPR 571
Access: Supervisor read/write
32
R
W
Reset
63
MSR state information
All zeros
Figure 6-24. Machine Check Save/Restore Register 1 (MCSRR1)
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Core Register Summary
6.7.2.3
Machine Check Address Register (MCAR/MCARU)
SPR 573
Access: Supervisor read only
32
63
R
Machine check address 4–35
W
Reset
All zeros
Figure 6-25. Machine Check Address Register (MCAR)
SPR 569
Access: Supervisor read only
32
59 60
R
—
W
63
Machine check address 0–4
Reset
All zeros
Figure 6-26. Machine Check Address Register Upper (MCARU)
6.7.2.4
Machine Check Syndrome Register (MCSR)
SPR 572
R
W
Access: Supervisor read/write
32
33
34
35
MCP
ICPERR
DCP_PERR
DCPERR
Reset
36
39
—
All zeros
40
47
R
—
W
Reset
All zeros
48
55
R
—
W
Reset
All zeros
56
R
W
57
58
59
60
61
62
63
BUS_IAERR BUS_RAERR BUS_WAERR BUS_IBERR BUS_RBERR BUS_WBERR BUS_IPERR BUS_RPERR
Reset
All zeros
Figure 6-27. Machine Check Syndrome Register (MCSR)
Table 6-13. MCSR Field Descriptions
Bits
Name
32
MCP
33
ICPERR
Description
Machine check input pin
Instruction cache parity error
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Core Register Summary
Table 6-13. MCSR Field Descriptions (continued)
Bits
Name
34
DCP_PERR
35
DCPERR
36–55
—
Reserved, should be cleared.
56
BUS_IAERR
Bus instruction address error
57
BUS_RAERR
Bus read address error
58
BUS_WAERR
Bus write address error
59
BUS_IBERR
Bus instruction data bus error
60
BUS_RBERR
Bus read data bus error
61
BUS_WBERR
Bus write bus error
62
BUS_IPERR
Bus instruction parity error
63
BUS_RPERR
Bus read parity error
6.8
Description
Data cache push parity error
Data cache parity error
Software-Use SPRs (SPRG0–SPRG7 and USPRG0)
SPR See Table 6-14.
Access: See Table 6-14.
32
63
R
Software-Determined Information
W
Reset
All zeros
Figure 6-28. Software-Use SPRs (SPRG0–SPRG7 and USPRG0)
Table 6-14. SPR Assignments
Name
SPR
Access
Level
SPRG0
272
Read/Write
Supervisor
SPRG1
273
Read/Write
Supervisor
SPRG2
274
Read/Write
Supervisor
SPRG3
SPRG4
SPRG5
SPRG6
SPRG7
USPRG0
259
Read only
User/Supervisor
275
Read/Write
Supervisor
260
Read only
User/Supervisor
276
Read/Write
Supervisor
261
Read only
User/Supervisor
277
Read/Write
Supervisor
262
Read only
User/Supervisor
278
Read/Write
Supervisor
263
Read only
User/Supervisor
279
Read/Write
Supervisor
256
Read/Write
User/Supervisor
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Core Register Summary
6.9
Branch Target Buffer (BTB) Registers
6.9.1
Branch Buffer Entry Address Register (BBEAR)
SPR 513
Access: User read/write
32
61
R
Branch buffer entry address
W
Reset
62
63
IAB[0–1]
All zeros
Figure 6-29. Branch Buffer Entry Address Register (BBEAR)
Table 6-15. BBEAR Field Descriptions
Bits
Name
32–61
Branch buffer
entry address
62–63
IAB[0–1]
6.9.2
Description
Branch buffer entry effective address bits 0–29
Instruction after branch (with BBTAR[62]). 3-bit pointer that points to the instruction in the cache line
after the branch. See the description in the bblels instruction in the EREF. If the branch is the last
instruction in the cache block, IAB = 000, to indicate the next sequential instruction, which resides in
the zeroth position of the next cache block.
Branch Buffer Target Address Register (BBTAR)
SPR 514
Access: User read/write
32
61
R
Branch buffer target address
W
Reset
62
63
IAB2 BDIRPR
All zeros
Figure 6-30. Branch Buffer Target Address Register (BBTAR)
Table 6-16. BBTAR Field Descriptions
Bits
Name
32–61
Branch buffer
target address
62
IAB2
63
BDIRPR
Description
Branch buffer target effective address bits 0–29
Instruction after branch bit 2 (with BBEAR[62–63]). IAB is a 3-bit pointer that points to the instruction
in the cache line after the branch. See the description for bblels in the EREF. If the branch is the last
instruction in the cache block, IAB = 000, to indicate the next sequential instruction, which resides in
the zeroth position of the next cache block.
Branch direction prediction. The user can pick the direction of the predicted branch.
0 The locked address is always predicted as not taken.
1 The locked address is always predicted as taken.
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Core Register Summary
6.9.3
Branch Unit Control and Status Register (BUCSR)
SPR 1013
Access: Supervisor read/write
32
53
R
—
W
Reset
54
55
56
57
58
BBFI BBLO BBUL BBLFC
62
—
63
BPEN
All zeros
Figure 6-31. Branch Unit Control and Status Register (BUCSR)
Table 6-17. BUCSR Field Descriptions
Bits
Name
32–53
—
54
BBFI
55
BBLO Branch buffer lock overflow status
0 Indicates a lock overflow condition was not encountered in the branch buffer
1 Indicates a lock overflow condition was encountered in the branch buffer
This sticky bit is set by hardware and is cleared by writing 0 to this bit location.
56
BBUL Branch buffer unable to lock
0 Indicates a lock overflow condition in the branch buffer
1 Indicates a lock set instruction failed in the branch buffer, for example, if the BTB is disabled.
This sticky bit is set by hardware and is cleared by writing 0 to this bit location.
57
BBLFC Branch buffer lock bits flash clear. Clearing and then setting BBLFC flash clears the lock bit of all entries in
the branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBLFC is always
read as 0.
58–62
63
—
Description
Reserved, should be cleared.
Branch buffer flash invalidate. Clearing and then setting BBFI flash clears the valid bit of all entries in the
branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBFI is always read as
0.
Reserved, should be cleared.
BPEN Branch prediction enable
0 Branch prediction disabled
1 Branch prediction enabled (enables BTB to predict branches)
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Core Register Summary
6.10
Hardware Implementation-Dependent Registers
6.10.1
Hardware Implementation-Dependent Register 0 (HID0)
SPR 1008
Access: Supervisor read/write
32
R
W
33
39
EMCP
—
42
43
47
NAP SLEEP
—
All zeros
48
W
41
DOZE
Reset
R
40
—
49
50
TBEN SEL_TBCLK
51
55
—
Reset
56
57
EN_MAS7_UPDATE DCFA
58
62
—
63
NOPTI
All zeros
Figure 6-32. Hardware Implementation-Dependent Register 0 (HID0)
Table 6-18. HID0 Field Descriptions
Bits
Name
Description
32
EMCP
Enable machine check pin, MCP. Used to mask out further machine check exceptions caused by
assertion of MCP.
0 MCP is disabled.
1 MCP is enabled. If MSE[ME] = 0, asserting MCP causes checkstop. If MSR[ME] = 1, asserting MCP
causes a machine check exception.
33–39
—
40
DOZE
41
NAP
42
SLEEP
43–48
—
49
TBEN
50
51–55
Reserved, should be cleared.
Doze power management mode. If MSR[WE] is set, this bit controls DOZE mode.
0 Core not in doze mode
1 Core in doze mode
Nap power management mode. If MSR[WE] is set, this bit controls NAP mode.
0 Core not in nap mode
1 Core in nap mode
Configure for sleep power management mode. Controls SLEEP mode if MSR[WE] is set.
0 Core not in sleep mode
1 Core in sleep mode
Reserved, should be cleared.
Time base enable
0 Time base disabled (no counting)
1 Time base enabled
• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8 bus clocks
• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is updated on the rising edge of
core_tbclk (sampled at bus rate). The maximum supported frequency can be found in the electrical
specifications, but this value is approximately 25% of the bus clock frequency.
SEL_TBCLK Select time base clock. If the time base is enabled, this field functions as follows:
0 Time base is based on the processor clock
1 Time base is based on the TBCLK (RTC) input
—
Reserved, should be cleared.
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Core Register Summary
Table 6-18. HID0 Field Descriptions (continued)
Bits
56
Name
Description
EN_MAS7_ Enable MAS7 update (e500v2 only). Enables updating MAS7 by tlbre and tlbsx.
UPDATE 0 MAS7 is not updated by a tlbre or tlbsx.
1 MAS7 is updated by a tlbre or tlbsx.
57
DCFA
58–62
—
63
NOPTI
6.10.2
Data cache flush assist (e500v2 only). Force data cache to ignore invalid sets on miss replacement
selection.
0 The data cache flush assist facility is disabled
1 The miss replacement algorithm ignores invalid entries and follows the replacement sequence
defined by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions to
eight per set. The bit should be set just before beginning a cache flush routine and should be cleared
when the series of instructions is complete.
Reserved, should be cleared.
No-op the data and instruction cache touch instructions.
0 dcbt, dcbtst, and icbt are enabled. On the e500, if CT = 0, icbt is always a no-op, regardless of the
value of NOPTI. If CT = 1, icbt does a touch load to an L2 cache, if one is present.
1 dcbt, dcbtst, and icbt are treated as no-ops; dcblc and dcbtls are not.
Hardware Implementation-Dependent Register 1 (HID1)
SPR 1009
Access: Supervisor read/write
32
R
33
34
39
PLL_MODE
40
45
PLL_CFG
—
W
Reset
W
47
RFXE
—
All zeros
48
R
46
49
—
50
51
52
63
ASTME ABE
—
Reset
All zeros
Figure 6-33. Hardware Implementation-Dependent Register 1 (HID1)
Table 6-19. HID1 Field Descriptions
Bits
32–33
34–39
Name
Description
PLL_MODE Read-only for integrated devices.
01 Fixed value for MPC8548E
PLL_CFG
Reflected directly from configuration input pins (read-only). PLL_CFG[0–4] corresponds to the integer
divide ratio and PLL_CFG5 is the half-mode bit. The following values are supported:
0001_00 Ratio of 2:1
0001_01 Ratio of 5:2 (2.5:1)
0001_10 Ratio of 3:1
0001_11 Ratio of 7:2 (3.5:1)
Note that this value is also reflected to PORPLLSR[e500_Ratio]. See Section 20.4.1.1, “POR PLL
Status Register (PORPLLSR).”
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Core Register Summary
Table 6-19. HID1 Field Descriptions (continued)
Bits
Name
Description
40–45
—
46
RFXE
47–49
—
50
ASTME
Reserved, should be cleared.
Read fault exception enable. Enables the core to internally generate a machine check interrupt when
core_fault_in is asserted. Depending on the value of MSR[ME], this results in either a machine check
interrupt or a checkstop.
0 Assertion of core_fault_in cannot cause a machine check. The core does not execute any instructions
from a faulty instruction fetch and does not execute any load instructions that get their data from a
faulty data fetch.
On the e500v2, if these instructions are eventually required by the sequential programming model
(that is, they are not in a speculative execution path), the e500v2 stalls until an asynchronous interrupt
is taken. The e500v1 does not stall when faulty instructions or data are received, as described in the
following note.
Note: The e500v1 does not stall when faulty instructions or data are received. Instead, it continues
processing with faulty instructions or data. The only reliable way to prevent such behavior is to set RFXE,
which causes a machine check before the faulty instructions or data are used. To avoid the use of faulty
instructions or data and to have good error determination, software must set RFXE and program the PIC
to interrupt the processor when errors occur. As a result, software must deal with multiple interrupts for
the same fundamental problem.
1 Assertion of core_fault_in causes a machine check if MSR[ME] = 1 or a checkstop if MSR[ME] = 0.
The core_fault_in signal is asserted to the core when logic outside of the core has a problem
delivering good data to the core. For example, the front-side L2 cache asserts core_fault_in when an
ECC error occurs and ECC is enabled. As a second example, it is asserted when there is a master
abort on a PCI transaction. See “Proper Reporting of Bus Faults” in the core complex bus chapter of
the PowerPC™ e500 Core Family Reference Manual.
The RFXE bit provides flexibility in error recovery. Typically, devices outside the core have some way
other than the assertion of core_fault_in to signal the core that an error occurred. Usually, this is done
by channeling interrupt requests through a programmable interrupt controller (PIC) to the core. In these
cases, the assertion of core_fault_in is used only to prevent the core from using bad data before
receiving an interrupt from the PIC (for example, an external or critical input interrupt). Possible
combinations of RFXE and PIC configuration are as follows:
• RFXE = 0 and the PIC is configured to interrupt the processor. In this configuration, the assertion of
core_fault_in does not trigger a machine check interrupt. The core does not use the faulty instructions
or data and may stall. The PIC interrupts the core so that error recovery can begin. This configuration
allows the core to query the PIC and the rest of the system for more information about the cause of
the interrupt, and generally provides the best error recovery capabilities.
• RFXE = 1 and the PIC is not configured to interrupt the processor. This configuration provides quick
error detection without the overhead of configuring the PIC. When the PIC is not configured, setting
RFXE avoids stalling the core when core_fault_in is asserted. Determination of the root cause of the
problem may be somewhat more difficult than it would be if the PIC were enabled.
• RFXE = 1 and the PIC is configured to interrupt the processor. In this configuration, the core may
receive two interrupts for the same fundamental error. The two interrupts may occur in any order,
which may complicate error handling. Therefore, this is usually not an interesting configuration for a
single-core device. This may, however, be an interesting configuration for multi-core devices in which
the PIC may steer interrupts to a processor other than the one that attempted to fetch the faulty data.
• RFXE = 0 and the PIC is not configured to interrupt the processor. This is not a recommended
configuration. The processor may stall indefinitely due to an unreported error.
Reserved, should be cleared.
Address bus streaming mode enable. This bit, along with the ECM stream control bits in the EEBACR,
enables address bus streaming on the CCB. See Section 8.2.1.1, “ECM CCB Address Configuration
Register (EEBACR).”
0 Address bus streaming mode disabled
1 Address bus streaming mode enabled
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Core Register Summary
Table 6-19. HID1 Field Descriptions (continued)
Bits
Name
Description
51
ABE
Address broadcast enable. The e500 broadcasts cache management instructions (dcbst, dcblc
(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) based on ABE. ABE must be set to
allow management of external L2 caches.
0 Address broadcasting disabled
1 Address broadcasting enabled
52–63
—
6.11
Reserved, should be cleared.
L1 Cache Configuration Registers
6.11.1
L1 Cache Control and Status Register 0 (L1CSR0)
SPR 1010
Access: Supervisor read/write
Line Locking Bits
32
46
R
—
W
47
48
CPE CPI
Reset
49
51
—
52
53
54
55
56
CSLC CUL CLO CLFR
61
—
62
63
CFI CE
All zeros
Figure 6-34. L1 Cache Control and Status Register 0 (L1CSR0)
Table 6-20. L1CSR0 Field Descriptions
Bits
Name
32–46
—
47
CPE
(Data) Cache parity enable
0 Parity checking of the cache disabled
1 Parity checking of the cache enabled
48
CPI
(Data) Parity error injection enable
0 Parity error injection disabled
1 Parity error injection enabled. Cache parity must also be enabled (CPE = 1) when this bit is set.
49–51
—
52
Description
Reserved, should be cleared.
Reserved, should be cleared.
CSLC (Data) Cache snoop lock clear. Sticky bit set by hardware if a dcbi snoop (either internally or externally
generated) invalidated a locked cache line. Note that the lock bit for that line is cleared whenever the line is
invalidated. This bit can be cleared only by software.
0 The cache has not encountered a dcbi snoop that invalidated a locked line.
1 The cache has encountered a dcbi snoop that invalidated a locked line.
53
CUL
(Data) Cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock set instruction was effective in the cache
1 Indicates a lock set instruction was not effective in the cache
54
CLO
(Data) Cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock overflow condition was not encountered in the cache
1 Indicates a lock overflow condition was encountered in the cache
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Core Register Summary
Table 6-20. L1CSR0 Field Descriptions (continued)
Bits
Name
55
Description
CLFR (Data) Cache lock bits flash reset. Writing a 1 during a flash clear operation causes an undefined operation.
Writing a 0 during a flash clear operation is ignored. Clearing occurs regardless of the enable (CE) value.
0 Default.
1 Hardware initiates a cache lock bits flash clear operation. This bit is cleared when the operation is
complete.
56–61
—
Reserved, should be cleared.
62
CFI
(Data) Cache flash invalidate.
0 No cache invalidate. Writing a 0 to CFI during an invalidation operation is ignored.
1 Cache invalidation operation. A cache invalidation operation is initiated by hardware. Once complete, this
bit is cleared. Writing a 1 during an invalidation operation causes an undefined operation.
Invalidation occurs regardless of the enable (CE) value.
63
CE
(Data) Cache enable
0 The cache is neither accessed or updated.
1 Enables cache operation
6.11.2
L1 Cache Control and Status Register 1 (L1CSR1)
SPR 1011
Access: Supervisor read/write
Line Locking Bits
32
46
R
—
W
47
48
ICPE ICPI
Reset
49
51
—
52
53
54
55
56
ICSLC ICUL ICLO ICLFR
61
—
62
63
ICFI ICE
All zeros
Figure 6-35. L1 Cache Control and Status Register 1 (L1CSR1)
Table 6-21. L1CSR1 Field Descriptions
Bits
Name
32–46
—
47
ICPE
Instruction cache parity enable
0 Parity checking of the instruction cache disabled
1 Parity checking of the instruction cache enabled
48
ICPI
Instruction parity error injection enable
0 Parity error injection disabled
1 Parity error injection enabled. Note that instruction cache parity must also be enabled (ICPE = 1) when this
bit is set.
49–51
—
52
Description
Reserved, should be cleared.
Reserved, should be cleared.
ICSLC Instruction cache snoop lock clear. Sticky bit set by hardware if an icbi snoop (either internally or externally
generated) invalidated a locked line in the instruction cache. Note that the lock bit for that line is cleared
whenever the line is invalidated. This bit can only be cleared by software.
0 The instruction cache has not encountered an icbi snoop that invalidated a locked line.
1 The instruction cache has encountered an icbi snoop that invalidated a locked line.
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Core Register Summary
Table 6-21. L1CSR1 Field Descriptions (continued)
Bits
Name
Description
53
ICUL
Instruction cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock set instruction was effective in the instruction cache
1 Indicates a lock set instruction was not effective in the instruction cache
54
ICLO
Instruction cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock overflow condition was not encountered in the instruction cache
1 Indicates a lock overflow condition was encountered in the instruction cache
55
ICLFR Instruction cache lock bits flash reset. Writing 0 and then 1 flash clears the lock bit of all entries in the
instruction cache; clearing occurs independently from the value of the enable bit (ICE). ICLFR is always read
as 0.
56–61
—
62
ICFI
Instruction cache flash invalidate. Written to 0 and then 1 to flash clear the valid bit of all entries in the
instruction cache; operates independently from the value of the enable bit (ICE). ICFI is always read as 0.
63
ICE
Instruction cache enable
0 The instruction cache is neither accessed or updated.
1 Enables instruction cache operation
6.11.3
Reserved, should be cleared.
L1 Cache Configuration Register 0 (L1CFG0)
SPR 515
32
Access: User read only
33
34
R CARCH
38
—
39
40
41
42
43
44
CBSIZE CREPL CLA CPA
45
49 50 51 52 53
—
CNWAY
55 56
—
63
CSIZE
W
Reset 0
0
0 0 0 0 0
0
0
0
1
1
1
0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0
Figure 6-36. L1 Cache Configuration Register 0 (L1CFG0)
Table 6-22. L1CFG0 Field Descriptions
Bits
Name
Description
32–33
CARCH
34–38
—
39–40
CBSIZE
Cache line size
0 32 bytes
1 64 bytes
41–42
CREPL
Cache replacement policy
0 True LRU
1 Pseudo LRU
43
CLA
Cache architecture
00 Harvard
01 Unified
Reserved, should be cleared.
Cache locking available
0 Unavailable
1 Available
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Core Register Summary
Table 6-22. L1CFG0 Field Descriptions (continued)
Bits
Name
44
CPA
45–49
—
50–52
CNWAY
53–55
—
56–63
CSIZE
6.11.4
Description
Cache parity available
0 Unavailable
1 Available
Reserved, should be cleared.
Cache number of ways
111 Indicates 8 ways
Reserved, should be cleared.
Cache size
0x20 indicates 32 Kbytes
L1 Cache Configuration Register 1 (L1CFG1)
SPR 516
Access: User read only
32
38
R
—
39
40
41
42
43
44
ICBSIZE ICREPL ICLA ICPA
45
52 53
ICNWAY
63
ICSIZE
W
Reset 0 0 0 0 0 0 0
0
0
0
1
1
1
0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0
Figure 6-37. L1 Cache Configuration Register 1 (L1CFG1)
Table 6-23. L1CFG1 Field Descriptions
Bits
Name
Description
32–38
—
39–40
ICBSIZ
Instruction cache block size
00 Indicates block size of 32 bytes
41–42
ICREPL
Instruction cache replacement policy
01 Indicates pseudo-LRU policy
43
ICLA
Instruction cache locking available
1 Indicates available
44
ICPA
Instruction cache parity available
1 Indicates available
45–52
ICNWAY
Instruction cache number of ways
111 Indicates 8 ways
53–63
ICSIZE
Reserved, should be cleared.
Instruction cache size
0x20 indicates 32 Kbytes
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Core Register Summary
6.12
MMU Registers
6.12.1
Process ID Registers (PID0–PID2)
Access: Supervisor read/write
SPR 48 (PID0)
SPR 633 (PID1)
SPR 634 (PID2)
32
55 56
R
63
—
W
Process ID
Reset
All zeros
Figure 6-38. Process ID Registers (PID0–PID2)
6.12.2
MMU Control and Status Register 0 (MMUCSR0)
SPR 1012
Access: Supervisor read/write
32
60
R
—
W
61
62
63
L2TLB0_FI L2TLB1_FI —
Reset
All zeros
Figure 6-39. MMU Control and Status Register 0 (MMUCSR0)
Table 6-24. MMUCSR0 Field Descriptions
Bits
Name
32–60
—
Description
Reserved, should be cleared.
61
L2TLB0_FI TLB0 flash invalidate (write to 1 to invalidate)
62
L2TLB1_FI TLB1 flash invalidate (write 1 to invalidate)
0 No flash invalidate. Writing a 0 to this bit during an invalidation operation is ignored.
1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation operation. When this operation is
complete, this bit is cleared. Writing a 1 during an invalidation operation causes an undefined
operation.
63
—
6.12.3
Reserved, should be cleared.
MMU Configuration Register (MMUCFG)
SPR 1015
Access: Supervisor read only
32
48 49
R
—
52 53
NPIDS
57 58 59
PIDSIZE
—
60
61
62
63
NTLBS
MAVN
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
1
0
Figure 6-40. MMU Configuration Register (MMUCFG)
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Core Register Summary
Table 6-25. MMUCFG Field Descriptions
Bits
Name
Description
32–48
—
49–52
NPIDS
Number of PID registers, a 4-bit field that indicates the number of PID registers provided by the processor.
The e500 implements three PIDs.
53–57
PIDSIZE
PID register size. The 5-bit value of PIDSIZE is one less than the number of bits in each of the PID
registers implemented by the processor. The processor implements only the least significant PIDSIZE+1
bits in the PID registers.
00111 indicates 8-bit registers. This is the value presented by the e500.
58–59
—
60–61
NTLBS
Number of TLBs. The value of NTLBS is one less than the number of software-accessible TLB structures
that are implemented by the processor. NTLBS is set to one less than the number of TLB structures so
that its value matches the maximum value of MAS0[TLBSEL].
00 1 TLB
01 2 TLBs. This is the value presented by the e500.
10 3 TLBs
11 4 TLBs
62–63
MAVN
MMU architecture version number. Indicates the version number of the architecture of the MMU
implemented by the processor. 0b00 indicates version 1.0.
Reserved, should be cleared.
Reserved, should be cleared.
TLB Configuration Registers (TLBnCFG)
6.12.4
6.12.4.1
TLB0 Configuration Register 0 (TLB0CFG)
SPR 688
Access: Supervisor read only
32
R
39 40
ASSOC
43 44
MINSIZE
47
MAXSIZE
48
49
50 51 52
IPROT AVAIL
—
63
NENTRY
W
Reset 0 0 0 0 0 1 0 0
0
0
0
1
0
0
0
1
0
0
0 0 0 0 1 0 0 0 0 0 0 0 0
0
Figure 6-41. TLB Configuration Register 0 (TLB0CFG)
Table 6-26. TLB0CFG Field Descriptions
Bits
Name
Description
32–39
ASSOC
Associativity of TLB0
0x02 indicates associativity is 2-way set associative
40–43
MINSIZE
Minimum page size of TLB0
0x1 indicates smallest page size is 4K
44–47
MAXSIZE Maximum page size of TLB0
0x1 indicates maximum page size is 4K
48
IPROT
Invalidate protect capability of TLB0
0 Indicates invalidate protection capability not supported
49
AVAIL
Page size availability of TLB0
0 No variable-sized pages available (MINSIZE = MAXSIZE)
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Core Register Summary
Table 6-26. TLB0CFG Field Descriptions (continued)
Bits
Name
50–51
—
52–63
NENTRY
6.12.4.2
Description
Reserved, should be cleared.
Number of entries in TLB0
0x100 LB0 contains 256 entries
0x200TLB0 contains 512 entries (e500v2 only)
TLB1 Configuration Register 1 (TLB1CFG)
SPR 689
Access: Supervisor read only
32
39 40
R
ASSOC
43 44
MINSIZE
47
MAXSIZE
48
49
IPROT AVAIL
50 51 52
63
—
NENTRY
W
Reset 0
0 0 1
0 0
0 0
0 0 0
1 1
0 1 1
1
1
0 0 0
0 0
0 0
0 0 1
0 0
0 0
Figure 6-42. TLB Configuration Register 1 (TLB1CFG)
Table 6-27. TLB1CFG Field Descriptions
Bits
Name
Description
32–39
ASSOC
Associativity of TLB1
0x10 indicates associativity is 16
40–43
MINSIZE
Minimum page size of TLB1
0x1 indicates smallest page size is 4K
44–47
MAXSIZE
Maximum page size of TLB1
0x9 Indicates maximum page size is 256 Mbyte
0xB Indicates maximum page size is 4 Gbytes (e500v2 only)
48
IPROT
Invalidate protect capability of TLB1
1 Indicates that TLB1 supports invalidate protection capability
49
AVAIL
Page size availability of TLB1
1 Indicates all page sizes between MINSIZE and MAXSIZE supported
50–51
—
52–63
NENTRY
Reserved, should be cleared.
Number of entries in TLB1
0x010: TLB1 contains 16 entries
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Core Register Summary
6.12.5
MMU Assist Registers
6.12.5.1
MAS Register 0 (MAS0)
SPR 624
Access: Supervisor read/write
32
R
34
—
W
35
36
TLBSEL
43 44
—
47 48
62
ESEL
Reset
—
63
NV
All zeros
Figure 6-43. MAS Register 0 (MAS0)
Table 6-28. MAS0 Field Descriptions—MMU Read/Write and Replacement Control
Bits
Name
32–34
—
35
TLBSEL
36–43
—
44–47
ESEL
48–62
—
Reserved, should be cleared.
63
NV
Next victim. Next victim bit value to be written to TLB0[NV] on execution of tlbwe. This field is also updated
on TLB error exceptions (misses), tlbsx hit and miss cases and on execution of tlbre.
This field is updated based on the calculated next victim bit for TLB0 (based on the round-robin
replacement algorithm.)
Note that this field is not defined for operations that specify TLB1 (when TLBSEL = 01).
6.12.5.2
Descriptions
Reserved, should be cleared.
Selects TLB for access
0 TLB0
1 TLB1
Reserved, should be cleared.
Entry select. Number of entry in selected array to be used for tlbwe. This field is also updated on TLB
error exceptions (misses), and tlbsx hit and miss cases. Only certain bits are valid, depending on the array
selected in TLBSEL. Other bits should be 0.
For the e500, ESEL serves as the way select for the corresponding TLB as follows:
When TLBSEL = 00 (TLB0 selected), bits 46–47 are used (and bits 44–45 should be cleared). This field
selects between way 0, 1, 2, or 3 of TLB0. EA bits 45–51 from MAS2[EPN] are used to index into the TLB
to further select the entry for the operation. Note that for the e500v1, bit 47 selects either way 0 or way 1,
and bit 46 should remain cleared.
When TLBSEL = 01 (TLB1 selected), all four bits are used to select one of 16 entries in the array.
MAS Register 1 (MAS1)
SPR 625
32
R
W
Access: Supervisor read/write
33
34
V IPROT
39 40
—
Reset
47 48
TID
50
—
51
52
TS
55 56
TSIZE
63
—
All zeros
Figure 6-44. MAS Register 1 (MAS1)
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Core Register Summary
Table 6-29. MAS1 Field Descriptions—Descriptor Context and Configuration Control
Bits
Name
32
V
33
Descriptions
TLB valid bit
0 This TLB entry is invalid.
1 This TLB entry is valid.
IPROT Invalidate protect. Set to protect this TLB entry from invalidate operations due the execution of tlbiva[x] (TLB1
only). Note that not all TLB arrays are necessarily protected from invalidation with IPROT. Arrays that support
invalidate protection are denoted as such in the TLB configuration registers.
0 Entry is not protected from invalidation
1 Entry is protected from invalidation.
34–39
—
Reserved, should be cleared.
40–47
TID
Translation identity. An 8-bit field that defines the process ID for this TLB entry. TID is compared with the
current process IDs of the three virtual address to be translated. A TID value of 0 defines an entry as global
and matches with all process IDs.
48–50
—
Reserved, should be cleared.
51
TS
Translation space. This bit is compared with the IS or DS fields of the MSR (depending on the type of access)
to determine if this TLB entry may be used for translation.
52–55
TSIZE Translation size. Defines the TLB entry page size. For arrays that contain fixed-size TLB entries, TSIZE is
ignored. For variable page size arrays, the page size is 4TSIZE Kbytes. The e500 supports the following sizes:
0001
0010
0011
0100
0101
0110
56–63
—
6.12.5.3
0111
1000
1001
1010
1011
4 Kbytes
16 Kbytes
64 Kbytes
256 Kbytes
1 Mbyte
4 Mbytes
16 Mbytes
64 Mbytes
256 Mbytes
1 Gbyte (e500v2 only)
4 Gbytes (e500v2 only)
Reserved, should be cleared.
MAS Register 2 (MAS2)
SPR 626
Access: Supervisor read/write
32
51 52
R
EPN
W
Reset
56
—
57
58
59 60 61 62 63
X0 X1 W
I
M G E
All zeros
Figure 6-45. MAS Register 2 (MAS2)
Table 6-30. MAS2 Field Descriptions—EPN and Page Attributes
Bits
Name
Description
32–51
EPN
Effective page number. Depending on page size, only the bits associated with a page boundary are valid.
Bits that represent offsets within a page are ignored and should be cleared.
52–56
—
Reserved for implementation-specific use
57
X0
Implementation-dependent page attribute
58
X1
Implementation-dependent page attribute
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Core Register Summary
Table 6-30. MAS2 Field Descriptions—EPN and Page Attributes (continued)
Bits
Name
59
W
60
I
Caching-inhibited
0 Accesses to this page are considered cacheable.
1 The page is considered caching-inhibited. All loads and stores to the page bypass the caches and are
performed directly to main memory.
61
M
Memory coherency required
0 Memory coherency is not required.
1 Memory coherency is required. This allows loads and stores to this page to be coherent with loads and
stores from other processors (and devices) in the system, assuming all such devices are participating in
the coherency protocol.
62
G
Guarded
0 Accesses to this page are not guarded and can be performed before it is known if they are required by
the sequential execution model.
1 All loads and stores to this page that miss in the L1 cache are performed without speculation (that is, they
are known to be required). Speculative loads can be performed if they hit in the L1 cache. In addition,
accesses to caching-inhibited pages are performed using only the memory element that is explicitly
specified.
63
E
Endianness. Determines endianness for the corresponding page. Little-endian operation is true little endian,
which differs from the modified little-endian byte-ordering model optionally available in previous devices that
implement the original PowerPC architecture. See the PowerPC™ e500 Core Family Reference Manual for
more information.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
6.12.5.4
Description
Write-through
0 This page is considered write-back with respect to the caches in the system.
1 All stores performed to this page are written through the caches to main memory.
MAS Register 3 (MAS3)
SPR 627
Access: Supervisor read/write
32
51 52 53 54
R
RPN
W
Reset
—
57
U0–U3
58
59
60
61
62
63
UX SX UW SW UR SR
All zeros
Figure 6-46. MAS Register 3 (MAS3)
Table 6-31. MAS3 Field Descriptions–RPN and Access Control
Bits
Name
Description
32–51
RPN
Real page number. Depending on page size, only the bits associated with a page boundary are valid. Bits
that represent offsets within a page are ignored and should be cleared. For the e500v2, the 4 high-order bits
of RPN are stored in MAS7[RPN].
52–53
—
54–57
U0–U3
58–63
Reserved, should be cleared.
User attribute bits. Associated with a TLB entry and can be used by system software. For example, they can
hold information useful to a page-scanning algorithm or mark more abstract page attributes.
PERMIS Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write, and execute permission bits.
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Core Register Summary
6.12.5.5
MAS Register 4 (MAS4)
SPR 628
Access: Supervisor read/write
32
R
34
—
W
35
36
45
TLBSELD
—
46
47
48
TIDSELD
Reset
50 51 52
—
55 56
57
58
59
60
61
62
63
TSIZED — X0D X1D WD ID MD GD ED
All zeros
Figure 6-47. MAS Register 4 (MAS4)
Table 6-32. MAS4 Field Descriptions—Hardware Replacement Assist Configuration
Bits
Name
32–34
—
35
Description
Reserved, should be cleared.
TLBSELD TLBSEL default value. The default value to be loaded in MAS0[TLBSEL] on a TLB miss exception.
0 TLB0
1 TLB1
36–45
—
46–47
Reserved, should be cleared.
TIDSELD TID default selection value. A 2-bit field that specifies which of the current PID registers should be used
to load the MAS1[TID] field on a TLB miss exception.
The e500 implementation defines this field as follows:
00 PID0
01 PID1
10 PID2
11 TIDZ (0x00) (all zeros)
48–51
—
52–55
TSIZED
56
—
57
X0D
Default X0 value. Specifies the default value to be loaded into MAS2[X0] on a TLB miss exception.
58
X1D
Default X1 value. Specifies the default value to be loaded into MAS2[X1] on a TLB miss exception.
59
WD
Default W value. Specifies the default value to be loaded into MAS2[W] on a TLB miss exception.
60
ID
Default I value. Specifies the default value to be loaded into MAS2[I] on a TLB miss exception.
61
MD
Default M value. Specifies the default value to be loaded into MAS2[M] on a TLB miss exception.
62
GD
Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception.
63
ED
Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception.
6.12.5.6
Reserved, should be cleared.
Default TSIZE value. Specifies the default value to be loaded into MAS1[TSIZE] on a TLB miss exception.
Reserved, should be cleared.
MAS Register 6 (MAS6)
SPR 630
Access: Supervisor read/write
32
R
W
Reset
39 40
—
47 48
SPID0
62
—
63
SAS
All zeros
Figure 6-48. MAS Register 6 (MAS6)
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Core Register Summary
Table 6-33. MAS6—TLB Search Context Register 0
Bits
Name
32–39
—
40–47
Comments, or Function when Set
Reserved, should be cleared.
SPID0 Specifies the PID value (recent value of PID0) used when searching the TLB during execution of tlbsx.
48–62
—
63
SAS
6.12.5.7
Reserved, should be cleared.
Address space (AS) value for searches. Specifies the value of AS used when searching the TLB (during
execution of tlbsx).
MAS Register 7 (MAS7)
SPR 944
Access: Supervisor read/write
32
59 60
R
—
W
Reset
63
RPN
All zeros
Figure 6-49. MAS Register 7 (MAS7)
Table 6-34. MAS 7 Field Descriptions—High Order RPN
6.13
Bits
Name
32–63
RPN
Description
Real page number. Four high-order bits of the RPN. The
20 low-order bits of RPN are in MAS3.
Debug Registers
6.13.1
Debug Control Registers (DBCR0–DBCR2)
6.13.1.1
Debug Control Register 0 (DBCR0)
SPR 308
32
R
W
Access: Supervisor read/write
33
34 35
36
37
38
39
40
41
— IDM RST ICMP BRT IRPT TRAP IAC1 IAC2
Reset
42 43 44 45 46 47
—
48
49
DAC1 DAC2 RET
62 63
—
FT
All zeros
Figure 6-50. Debug Control Register 0 (DBCR0)
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Core Register Summary
Table 6-35. DBCR0 Field Descriptions
Bits
Name
Description
32
—
33
IDM
Internal debug mode
0 Debug interrupts are disabled. No debug interrupts are taken and debug events are not logged.
1 If MSR[DE] = 1, the occurrence of a debug event or the recording of an earlier debug event in the DBSR
when MSR[DE] = 0 or DBCR0[IDM] = 0 causes a debug interrupt.
Programming note: Software must clear debug event status in the DBSR in the debug interrupt handler
when a debug interrupt is taken before re-enabling interrupts through MSR[DE]. Otherwise, redundant debug
interrupts are taken for the same debug event.
34–35
RST
Reset. The e500 implements these bits as follows:
0x Default (No action)
1x Causes a hard reset if MSR[DE] and DBCR0[IDM] are set. Always cleared on subsequent cycle. This
causes a hard reset to the core only.
36
ICMP
Instruction completion debug event enable
0 ICMP debug events are disabled
1 ICMP debug events are enabled
Note: Instruction completion does not cause an ICMP debug event if MSR[DE] = 0.
37
BRT
Branch taken debug event enable
0 BRT debug events are disabled
1 BRT debug events are enabled
Note: Taken branches do not cause a BRT debug event if MSR[DE] = 0.
38
IRPT
Interrupt taken debug event enable. This bit affects only noncritical interrupts.
0 IRPT debug events are disabled
1 IRPT debug events are enabled
39
TRAP
Trap debug event enable
0 TRAP debug events cannot occur
1 TRAP debug events can occur
40
IAC1
Instruction address compare 1 debug event enable
0 IAC1 debug events cannot occur
1 IAC1 debug events can occur
41
IAC2
Instruction address compare 2 debug event enable
0 IAC2 debug events cannot occur
1 IAC2 debug events can occur
42–43
—
44–45
DAC1
Data address compare 1 debug event enable
00 DAC1 debug events cannot occur
01 DAC1 debug events can occur only if a store-type data storage access
10 DAC1 debug events can occur only if a load-type data storage access
11 DAC1 debug events can occur on any data storage access
46–47
DAC2
Data address compare 2 debug event enable
00 DAC2 debug events cannot occur
01 DAC2 debug events can occur only if a store-type data storage access
10 DAC2 debug events can occur only if a load-type data storage access
11 DAC2 debug events can occur on any data storage access
Reserved, should be cleared.
Reserved, should be cleared.
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Core Register Summary
Table 6-35. DBCR0 Field Descriptions (continued)
Bits
Name
48
RET
49–62
—
Reserved, should be cleared.
63
FT
Freeze timers on debug event
0 Enable clocking of timers
1 Disable clocking of timers if any DBSR bit is set (except MRR)
6.13.1.2
Description
Return debug event enable
0 RET debug events cannot occur
1 RET debug events can occur
Note: An rfci does not cause an RET debug event if MSR[DE] = 0 at the time that rfci executes.
Debug Control Register 1 (DBCR1)
SPR 309
32
R
W
Access: Supervisor read/write
33
34
35
36
37
38
39
40
41
42
63
IAC1US IAC1ER IAC2US IAC2ER IAC12M
Reset
—
All zeros
Figure 6-51. Debug Control Register 1 (DBCR1)
Table 6-36. DBCR1 Field Descriptions
Bits
Name
Description
32–33
IAC1US Instruction address compare 1 user/supervisor mode
00 IAC1 debug events can occur
01 Reserved
10 IAC1 debug events can occur only if MSR[PR] = 0
11 IAC1 debug events can occur only if MSR[PR] = 1
34–35
IAC1ER Instruction address compare 1 effective/real mode
00 IAC1 debug events are based on effective addresses
01 Reserved on the e500
10 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 0
11 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 1
36–37
IAC2US Instruction address compare 2 user/supervisor mode
00 IAC2 debug events can occur
01 Reserved
10 IAC2 debug events can occur only if MSR[PR] = 0
11 IAC2 debug events can occur only if MSR[PR] = 1
38–39
IAC2ER Instruction address compare 2 effective/real mode
00 IAC2 debug events are based on effective addresses
01 Reserved on the e500
10 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 0
11 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 1
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Core Register Summary
Table 6-36. DBCR1 Field Descriptions (continued)
Bits
40–41
Name
Description
IAC12M Instruction address compare 1/2 mode
00 Exact address compare. IAC1 debug events can occur only if the address of the instruction fetch is
equal to the value specified in IAC1. IAC2 debug events can occur only if the address of the instruction
fetch is equal to the value specified in IAC2.
01 Address bit match. IAC1 and IAC2 debug events can occur only if the address of the instruction fetch,
ANDed with the contents of IAC2 are equal to the contents of IAC1, plus ANDed with the contents of
IAC2.
If IAC1US ≠ IAC2US or IAC1ER ≠ IAC2ER, results are boundedly undefined.
10 Inclusive address range compare. IAC1 and IAC2 debug events occur only if the address of the
instruction fetch is greater than or equal to the value specified in IAC1 and less than the value specified
in IAC2.
If IAC1US ≠ IAC2US or IAC1ER ≠ IAC2ER, results are boundedly undefined.
11 Exclusive address range compare. IAC1 and IAC2 debug events occur only if the address of the
instruction fetch is less than the value specified in IAC1 or is greater than or equal to the value specified
in IAC2.
If IAC1US ≠ IAC2US or IAC1ER ≠ IAC2ER, results are boundedly undefined.
42–63
—
6.13.1.3
Reserved, should be cleared.
Debug Control Register 2 (DBCR2)
SPR 310
32
R
W
Access: Supervisor read/write
33
34
35
36
37
38
39
40
41 42
63
DAC1US DAC1ER DAC2US DAC2ER DAC12M
Reset
—
All zeros
Figure 6-52. Debug Control Register 2 (DBCR2)
Table 6-37. DBCR2 Field Descriptions
Bits
Name
Description
32–33
DAC1US Data address compare 1 user/supervisor mode
00 DAC1 debug events can occur
01 Reserved
10 DAC1 debug events can occur only if MSR[PR] = 0.
11 DAC1 debug events can occur only if MSR[PR] = 1.
34–35
DAC1ER Data address compare 1 effective/real mode
00 DAC1 debug events are based on effective addresses.
01 Reserved on the e500
10 DAC1 debug events are based on effective addresses and can occur only if MSR[DS] = 0.
11 DAC1 debug events are based on effective addresses and can occur only if MSR[DS] = 1.
36–37
DAC2US Data address compare 2 user/supervisor mode
00 DAC2 debug events can occur.
01 Reserved
10 DAC2 debug events can occur only if MSR[PR] = 0.
11 DAC2 debug events can occur only if MSR[PR] = 1.
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Core Register Summary
Table 6-37. DBCR2 Field Descriptions (continued)
Bits
Name
Description
38–39
DAC2ER Data address compare 2 effective/real mode
00 DAC2 debug events are based on effective addresses.
01 Reserved on the e500
10 DAC2 debug events are based on effective addresses and can occur only if MSR[DS] = 0.
11 DAC2 debug events are based on effective addresses and can occur only if MSR[DS] = 1.
40–41
DAC12M Data address compare 1/2 mode
00 Exact address compare. DAC1 debug events can occur only if the address of the data storage access
is equal to the value specified in DAC1. DAC2 debug events can occur only if the address of the data
storage access is equal to the value specified in DAC2.
01 Address bit match. DAC1 and DAC2 debug events can occur only if the address of the data storage
access, ANDed with the contents of DAC2 are equal to the contents of DAC1, also ANDed with the
contents of DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.
10 Inclusive address range compare. DAC1 and DAC2 debug events can occur only if the address of the
data storage access is greater than or equal to the value specified in DAC1 and less than the value
specified in DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.
11 Exclusive address range compare. DAC1 and DAC2 debug events can occur only if the address of the
data storage access is less than the value specified in DAC1 or is greater than or equal to the value
specified in DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.
42–63
—
6.13.2
Reserved, should be cleared.
Debug Status Register (DBSR)
SPR: 304
Access: Supervisor w1c
32
33
IDE
UDE
MRR
IRPT TRAP IAC1
IAC2
W w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
undefined
0
0
0
0
0
0
48
49
R
Reset
34
35
36
37
ICMP BRT
38
39
40
41
42
43
45
46
47
DAC1R DAC1W DAC2R DAC2W
—
0
44
0
w1c
w1c
w1c
w1c
0
0
0
0
63
R RET
—
W w1c
Reset
All zeros
Figure 6-53. Debug Status Register (DBSR)
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Core Register Summary
Table 6-38. DBSR Field Descriptions
Bits
Name
Description
32
IDE
Imprecise debug event. Set if MSR[DE] = 0 and a debug event causes its respective DBSR bit to be set.
Functions as write-one-to-clear.
33
UDE
Unconditional debug event. Set if an unconditional debug event occurred. Functions as
write-one-to-clear. If UDE (level sensitive, active low) is asserted, DBSR[UDE] is affected as follows:
MSR[DE]DBCR0[IDM]Action
X 0 No action.
0 1 UDE is set.
1 1 UDE is set and a debug interrupt is taken.
34–35
MRR
Most recent reset. Functions as write-one-to-clear. Undefined at power-on. The e500 implements
HRESET as follows:
0x No hard reset occurred since this bit was last cleared by software.
1x The previous reset was a hard reset.
36
ICMP
Instruction complete debug event. Set if an instruction completion debug event occurred and
DBCR0[ICMP] = 1. Functions as write-one-to-clear.
37
BRT
Branch taken debug event. Set if a branch taken debug event occurred (DBCR0[BRT] = 1). Functions as
write-one-to-clear.
38
IRPT
Interrupt taken debug event. Set if an interrupt taken debug event occurred (DBCR0[IRPT] = 1).
Functions as write-one-to-clear.
39
TRAP
Trap instruction debug event. Set if a trap Instruction debug event occurred (DBCR0[TRAP] = 1).
Functions as write-one-to-clear.
40
IAC1
Instruction address compare 1 debug event. Set if an IAC1 debug event occurred (DBCR0[IAC1] = 1).
Functions as write-one-to-clear.
41
IAC2
Instruction address compare 2 debug event. Set if an IAC2 debug event occurred (DBCR0[IAC2] = 1).
Functions as write-one-to-clear.
42–43
—
44
DAC1R
Data address compare 1 read debug event. Set if a read-type DAC1 debug event occurred
(DBCR0[DAC1] = 10 or 11). Functions as write-one-to-clear.
45
DAC1W
Data address compare 1 write debug event. Set if a write-type DAC1 debug event occurred
(DBCR0[DAC1] = 01 or 11). Functions as write-one-to-clear.
46
DAC2R
Data address compare 2 read debug event.Set if a read-type DAC2 debug event occurred
(DBCR0[DAC2] = 10 or 11). Functions as write-one-to-clear.
47
DAC2W
Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurred
(DBCR0[DAC2] = 01 or 11). Functions as write-one-to-clear.
48
RET
Return debug event. Set if a return debug event occurred (DBCR0[RET] = 1). Functions as
write-one-to-clear.
49–63
—
Reserved, should be cleared
Reserved, should be cleared.
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Core Register Summary
6.13.3
Instruction Address Compare Registers (IAC1–IAC2)
SPR 312 (IAC1); SPR 313 (IAC2)
Access: Supervisor read/write
32
61 62 63
R
Instruction address
W
Reset
—
All zeros
Figure 6-54. Instruction Address Compare Registers (IAC1–IAC2)
6.13.4
Data Address Compare Registers (DAC1–DAC2)
SPR 316 (DAC1); SPR 317 (DAC2)
Access: Supervisor read/write
32
63
R
Data address
W
Reset
All zeros
Figure 6-55. Data Address Compare Registers (DAC1–DAC2)
Signal Processing and Embedded Floating-Point Status
and Control Register (SPEFSCR)
6.14
SPR: 512
Access: User mixed
High-Word Error Bits
32
R
W
33
34
35
36
37
Status Bits
38
39
40
SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH
Reset
41
—
42
43
44
45
46
FINXS FINVS FDBZS FUNFS FOVFS
47
MODE
All zeros
Enable Bits
R
W
48
49
50
51
52
53
54
SOV
OV
FG
FX
FINV
FDBZ
FUNF
Reset
55
56
57
58
59
60
61
FOVF — FINXE FINVE FDBZE FUNFE FOVFE
62
63
FRMC
All zeros
Figure 6-56. Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)
Table 6-39. SPEFSCR Field Descriptions
Bits
Name
Function
32
SOVH
Summary integer overflow high. Set whenever an instruction (except mtspr) sets OVH. SOVH remains set
until it is cleared by an mtspr[SPEFSCR].
33
OVH
Integer overflow high. An overflow occurred in the upper half of the register while executing a SPE integer
instruction
34
FGH
Embedded floating-point guard bit high. Floating-point guard bit from the upper half. The value is undefined
if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point
underflow.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
6-45
Core Register Summary
Table 6-39. SPEFSCR Field Descriptions (continued)
Bits
Name
Function
35
FXH
36
FINVH
37
FDBZH Embedded floating-point divide by zero error high. Set if the dividend is non-zero and the divisor is zero.
38
FUNFH Embedded floating-point underflow error high
39
FOVFH Embedded floating-point overflow error high
Embedded floating-point sticky bit high. Floating bit from the upper half. The value is undefined if the
processor takes a floating-point exception due to input error, floating-point overflow, or floating-point
underflow.
Embedded floating-point invalid operation error high. Set when an input value on the high side is a NaN, Inf,
or Denorm. Also set on a divide if both the dividend and divisor are zero.
40–41
—
Reserved, should be cleared.
42
FINXS
Embedded floating-point inexact sticky. FINXS = FINXS | FGH | FXH | FG | FX
43
FINVS
Embedded floating-point invalid operation sticky. Location for software to use when implementing true IEEE
floating point.
44
FDBZS Embedded floating-point divide by zero sticky. FDBZS = FDBZS | FDBZH | FDBZ
45
FUNFS Embedded floating-point underflow sticky. Storage location for software to use when implementing true
IEEE floating point.
46
FOVFS
Embedded floating-point overflow sticky. Storage location for software to use when implementing true IEEE
floating point.
47
MODE
Embedded floating-point mode (read only on e500)
48
SOV
49
OV
Integer overflow. An overflow occurred in the lower half of the register while a SPE integer instruction is
being executed.
50
FG
Embedded floating-point guard bit. Floating-point guard bit from the lower half. The value is undefined if the
processor takes a floating-point exception due to input error, floating-point overflow, or floating-point
underflow.
51
FX
Embedded floating-point sticky bit. Floating bit from the lower half. The value is undefined if the processor
takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow.
52
FINV
Embedded floating-point invalid operation error. Set when an input value on the high side is a NaN, Inf, or
Denorm. Also set on a divide if both the dividend and divisor are zero.
53
FDBZ
Embedded floating-point divide by zero error. Set of the dividend is non-zero and the divisor is zero.
54
FUNF
Embedded floating-point underflow error
55
FOVF
Embedded floating-point overflow error
56
—
57
FINXE
Embedded floating-point inexact enable
58
FINVE
Embedded floating-point invalid operation/input error exception enable
0 Exception disabled
1 Exception enabled
If the exception is enabled, a floating-point data exception is taken if FINV or FINVH is set by a floating-point
instruction.
Integer summary overflow. Set whenever an SPE instruction (except mtspr) sets OV. SOV remains set until
it is cleared by mtspr[SPEFSCR].
Reserved, should be cleared.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
6-46
Freescale Semiconductor
Core Register Summary
Table 6-39. SPEFSCR Field Descriptions (continued)
Bits
Name
Function
59
FDBZE Embedded floating-point divide-by-zero exception enable
0 Exception disabled
1 Exception enabled
If the exception is enabled, a floating-point data exception is taken if FDBZ or FDBZH is set by a
floating-point instruction.
60
FUNFE Embedded floating-point underflow exception enable
0 Exception disabled
1 Exception enabled
If the exception is enabled, a floating-point data exception is taken if FUNF or FUNFH is set by a
floating-point instruction.
61
FOVFE
Embedded floating-point overflow exception enable
0 Exception disabled
1 Exception enabled
If the exception is enabled, a floating-point data exception is taken if FOVF or FOVFH is set by a
floating-point instruction.
62–63
FRMC
Embedded floating-point rounding mode control
00 Round to nearest
01 Round toward zero
10 Round toward +infinity
11 Round toward –infinity
6.14.1
Accumulator (ACC)
Access: User read/write
0
31 32
R
63
Upper word
W
Reset
Lower word
All zeros
Figure 6-57. Accumulator (ACC)
Table 6-40. ACC FIeld Descriptions
Bits
Name
Function
0–31
Upper word
Holds the upper-word accumulate value for SPE multiply with accumulate instructions
32–63
Lower word
Holds the lower-word accumulate value for SPE multiply with accumulate instructions
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
6-47
Core Register Summary
6.15
Performance Monitor Registers (PMRs)
Table 6-41. Supervisor-Level PMRs (PMR[5] = 1)
Abbreviation
Register Name
PMR Number
pmr[0–4]
pmr[5–9]
Section/Page
6.15.4/6-52
PMC0
Performance monitor counter 0
16
00000
10000
PMC1
Performance monitor counter 1
17
00000
10001
PMC2
Performance monitor counter 2
18
00000
10010
PMC3
Performance monitor counter 3
19
00000
10011
PMGC0
Performance monitor global control register 0
400
01100
10000
6.15.1/6-49
PMLCa0
Performance monitor local control a0
144
00100
10000
6.15.2/6-50
PMLCa1
Performance monitor local control a1
145
00100
10001
PMLCa2
Performance monitor local control a2
146
00100
10010
PMLCa3
Performance monitor local control a3
147
00100
10011
PMLCb0
Performance monitor local control b0
272
01000
10000
PMLCb1
Performance monitor local control b1
273
01000
10001
PMLCb2
Performance monitor local control b2
274
01000
10010
PMLCb3
Performance monitor local control b3
275
01000
10011
6.15.3/6-51
Table 6-42. User-Level PMRs (PMR[5] = 0) (Read Only)
Abbreviation
Register Name
PMR Number
pmr[0–4]
pmr[5–9]
Section/Page
6.15.4/6-52
UPMC0
User performance monitor counter 0
0
00000
00000
UPMC1
User performance monitor counter 1
1
00000
00001
UPMC2
User performance monitor counter 2
2
00000
00010
UPMC3
User performance monitor counter 3
3
00000
00011
UPMLCa0
User performance monitor local control a0
128
00100
00000
UPMLCa1
User performance monitor local control a1
129
00100
00001
UPMLCa2
User performance monitor local control a2
130
00100
00010
UPMLCa3
User performance monitor local control a3
131
00100
00011
UPMLCb0
User performance monitor local control b0
256
01000
00000
UPMLCb1
User performance monitor local control b1
257
01000
00001
UPMLCb2
User performance monitor local control b2
258
01000
00010
UPMLCb3
User performance monitor local control b3
259
01000
00011
UPMGC0
User performance monitor global control register 0
384
01100
00000
6.15.3/6-51
6.15.3/6-51
6.15.2/6-50
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
6-48
Freescale Semiconductor
Core Register Summary
6.15.1
Global Control Register 0 (PMGC0, UPMGC0)
PMGC0 (PMR400)
UPMGC0 (PMR384)
32
R
W
33
34
Access: PMGC0: Supervisor- read/write
UPMGC0: Supervisor/user read only
35
50
FAC PMIE FCECE
52
TBSEL1
—
Reset
51
53 54
55
—
TBEE1
56
63
—
All zeros
1
e500v2 only
Figure 6-58. Performance Monitor Global Control Register 0 (PMGC0),
User Performance Monitor Global Control Register 0 (UPMGC0)
Table 6-43. PMGC0 Field Descriptions
Bits
Name
Description
32
FAC
Freeze all counters. When FAC is set by hardware or software, PMLCx[FC] maintains its current value until
it is changed by software.
0 The PMCs are incremented (if permitted by other PM control bits).
1 The PMCs are not incremented.
33
PMIE
Performance monitor interrupt enable
0 Performance monitor interrupts are disabled.
1 Performance monitor interrupts are enabled and occur when an enabled condition or event occurs.
34
FCECE Freeze counters on enabled condition or event
0 The PMCs can be incremented (if permitted by other PM control bits).
1 The PMCs can be incremented (if permitted by other PM control bits) only until an enabled condition or
event occurs. When an enabled condition or event occurs, PMGC0[FAC] is set. It is up to software to
clear FAC.
35–50
—
51–52
TBSEL
53–54
—
Reserved, should be cleared.
Time base selector. Selects the time base bit that can cause a time base transition event (the event occurs
when the selected bit changes from 0 to 1).
00 TB[63] (TBL[31])
01 TB[55] (TBL[23])
10 TB[51] (TBL[19])
11 TB[47] (TBL[15])
Time base transition events can be used to periodically collect information about processor activity. In
multiprocessor systems in which TB registers are synchronized among processors, time base transition
events can be used to correlate the performance monitor data obtained by the several processors. For this
use, software must specify the same TBSEL value for all processors in the system. Because the time-base
frequency is implementation-dependent, software should invoke a system service program to obtain the
frequency before choosing a value for TBSEL.
Reserved, should be cleared.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
6-49
Core Register Summary
Table 6-43. PMGC0 Field Descriptions (continued)
Bits
Name
Description
55
TBEE
Time base transition event exception enable.
0 Exceptions from time base transition events are disabled.
1 Exceptions from time base transition events are enabled. A timebase transition is signaled to the
performance monitor if the TB bit specified in PMGC0[TBSEL] changes from 0 to 1. Timebase transition
events can be used to freeze the counters (PMGC0[FCECE]) or signal an exception (PMGC0[PMIE]).
Changing PMGC0[TBSEL] while PMGC0[TBEE] is enabled may cause a false 0 to 1 transition that
signals the specified action (freeze, exception) to occur immediately. Although the interrupt signal
condition may occur with MSR[EE] = 0, the interrupt cannot be taken until MSR[EE] = 1.
56–63
—
6.15.2
Reserved, should be cleared.
Local Control A Registers
(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3)
UPMLCa0
UPMLCa1
UPMLCa2
UPMLCa3
PMLCa0 (PMR144)
PMLCa1 (PMR145)
PMLCa2 (PMR146)
PMLCa3 (PMR147)
32
R
W
33
34
35
36
37 38
FC FCS FCU FCM1 FCM0 CE
Reset
Access: PMLCa0–PMLCa3: Supervisor read/write
UPMLCa0–UPMLCa3: Supervisor/user read only
(PMR128)
(PMR129)
(PMR130)
(PMR131)
40 41
—
47 48
EVENT
63
—
All zeros
Figure 6-59. Local Control A Registers (PMLCa0–PMLCa3), User Local Control A Registers
(UPMLCa0–UPMLCa3)
Table 6-44. PMLCa0–PMLCa3 Field Descriptions
Bits
Name
Description
32
FC
Freeze counter
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented.
33
FCS
Freeze counter in supervisor state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 0.
34
FCU
Freeze counter in user state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 1.
35
FCM1 Freeze counter while mark = 1
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 1.
36
FCM0 Freeze counter while mark = 0
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 0.
MPC8548E PowerQUICC III Integrated Processor Family Reference Manual, Rev. 2
6-50
Freescale Semiconductor
Core Register Summary
Table 6-44. PMLCa0–PMLCa3 Field Descriptions (continued)
Bits
Name
Description
37
CE
Condition enable
0 PMC x overflow conditions cannot occur (PMCx cannot cause interrupts, cannot freeze counters)
1 Overflow conditions occur when the most-significant bit of PMC x is equal to 1.
It is recommended that CE be cleared when counter PMC x is selected for chaining.
38–40
—
Reserved, should be cleared.
41–47 EVENT Event selector. Up to 128 events selectable. These events are described in the PowerPC™ e500 Core Family
Reference Manual.
48–63
—
Reserved, should be cleared.
6.15.3
Local Control B Registers (PMLCb0–PMLCb3,
UPMLCb0–UPMLCb3)
PMLCb0
PMLCb1
PMLCb2
PMLCb3
(PMR272)
(PMR273)
(PMR274)
(PMR275)
Access: PMLCb0–PMLCb3: Supervisor read/write
UPMLCb0–UPMLCb3: Supervisor/user read only
UPMLCb0 (PMR256)
UPMLCb1 (PMR257)
UPMLCb2 (PMR258)
UPMLCb3 (PMR259)
32
52
R
—
W
53
55
56 57 58
THRESHMUL
Reset
—
63
THRESHOLD
All zeros
Figure 6-60. Local Control B Registers (PMLCb0–PMLCb3)/User Local Control B Registers
(UPMLCb0–UPMLCb3)
Table 6-45. PMLCb0–PMLCb3 Field Descriptions
Bits
Name
32–52
—
53–55
THRESHMUL
Description
Reserved, should be cleared.
56–57
—
58–63
THRESHOLD
Threshold multiple
000 Threshold field is
001 Threshold field is
010 Threshold field is
011 Threshold field is
100 Threshold field is
101 Threshold field is
110 Threshold field is
111 Threshold field is
multiplied by 1 (PMLCbn[THRESHOLD] × 1)
multiplied by 2 (PMLCbn[THRESHOLD] × 2)
multiplied by 4 (PMLCbn[THRESHOLD] × 4)
multiplied by 8 (PMLCbn[THRESHOLD] × 8)
multiplied by 16 (PMLCb