NXP VF5xx Arm® Cortex®-A5 based Microprocessors Reference Manual

NXP VF5xx Arm® Cortex®-A5 based Microprocessors Reference Manual
VFxxx Controller Reference Manual
F-Series and R-Series
Document Number: VFXXXRM
Rev. 0, 10/2016
VFxxx Controller Reference Manual, Rev. 0, 10/2016
2
NXP Semiconductors
Contents
Section number
Title
Page
Chapter 1
About This Document
1.1
1.2
Overview.........................................................................................................................................................................135
1.1.1
Purpose.............................................................................................................................................................135
1.1.2
Audience.......................................................................................................................................................... 135
1.1.3
Reference Manual Overview........................................................................................................................... 135
1.1.4
Related Resources............................................................................................................................................ 136
Conventions.................................................................................................................................................................... 136
1.2.1
Numbering systems..........................................................................................................................................136
1.2.2
Typographic notation....................................................................................................................................... 137
1.2.3
Special terms.................................................................................................................................................... 137
Chapter 2
Introduction
2.1
VFxxx Controller Platform............................................................................................................................................. 139
2.2
Feature Set...................................................................................................................................................................... 140
2.3
Detailed Block Diagram................................................................................................................................................. 142
2.4
VFxxx Controller Device Configuration........................................................................................................................ 143
2.5
Modules on the device.................................................................................................................................................... 145
2.5.1
Clocks...............................................................................................................................................................145
2.5.2
Platform Modules.............................................................................................................................................146
2.5.3
System Modules............................................................................................................................................... 149
2.5.4
Memories and Memory Interfaces................................................................................................................... 150
2.5.5
Audio modules................................................................................................................................................. 152
2.5.6
Timer modules................................................................................................................................................. 153
2.5.7
Communication interfaces............................................................................................................................... 154
2.5.8
Graphics Modules............................................................................................................................................ 156
2.5.9
Analog modules............................................................................................................................................... 157
Chapter 3
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Section number
Title
Page
Chip Configuration
3.1
Introduction.....................................................................................................................................................................159
3.2
Core modules.................................................................................................................................................................. 159
3.3
3.2.1
Cortex-M4 Processor Core...............................................................................................................................159
3.2.2
Cortex-M4 Instruction Fetches on the System Bus......................................................................................... 161
3.2.3
Cortex-A5 Processor Core............................................................................................................................... 162
3.2.4
Interrupt Assignments...................................................................................................................................... 164
DMAMUX Request Sources.......................................................................................................................................... 171
3.3.1
3.4
Wakeup Unit (WKPU)....................................................................................................................................................176
3.4.1
3.5
WKPU configuration....................................................................................................................................... 176
CMU Chip Signals..........................................................................................................................................................177
3.5.1
3.6
DMAMUX Request Sources........................................................................................................................... 171
CMU Chip Signals........................................................................................................................................... 177
Cyclic Redundancy Check (CRC).................................................................................................................................. 178
3.6.1
CRC Reverse Logic Functions.........................................................................................................................178
3.7
External Watchdog Monitor........................................................................................................................................... 178
3.8
Timers............................................................................................................................................................................. 179
3.8.1
3.8.2
3.8.3
FlexTimer.........................................................................................................................................................179
3.8.1.1
Instantiation Information..............................................................................................................179
3.8.1.2
FTM Clock Input......................................................................................................................... 179
3.8.1.3
FTM Hardware Triggers.............................................................................................................. 179
3.8.1.4
FTM output triggers for other modules........................................................................................182
3.8.1.5
FTM Global Time Base............................................................................................................... 182
3.8.1.6
FTM Fault Detection Inputs.........................................................................................................183
Programmable Interrupt Timer(PIT)................................................................................................................183
3.8.2.1
PIT Instantiations......................................................................................................................... 183
3.8.2.2
PIT/DMA Periodic Trigger Assignments ................................................................................... 183
Programmable Delay Block (PDB)..................................................................................................................184
3.8.3.1
PDB Instantiation......................................................................................................................... 184
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Section number
3.8.4
Page
3.8.3.1.1
PDB Output Triggers............................................................................................ 184
3.8.3.1.2
PDB Input Trigger Connections........................................................................... 184
3.8.3.2
PDB Module Interconnections.....................................................................................................185
3.8.3.3
DMA support on PDB .................................................................................................................185
3.8.3.4
PDB in Low-Power modes.......................................................................................................... 185
3.8.3.5
PDB implementation with ADC.................................................................................................. 186
Low-Power Timer (LPTMR)........................................................................................................................... 187
3.8.4.1
3.9
Title
LPTMR prescaler/glitch filter clocking options.......................................................................... 187
External memory interfaces............................................................................................................................................ 187
3.9.1
3.9.2
Quad SPI.......................................................................................................................................................... 187
3.9.1.1
QuadSPI Instances....................................................................................................................... 187
3.9.1.2
QuadSPI Memory Interface......................................................................................................... 188
3.9.1.3
QuadSPI Buffer............................................................................................................................188
3.9.1.4
QuadSPI Clocking........................................................................................................................189
3.9.1.5
Booting from QuadSPI.................................................................................................................189
DRAM Controller............................................................................................................................................ 189
3.9.2.1
3.9.3
Nand Flash Controller...................................................................................................................................... 190
3.9.3.1
3.9.4
DDR maximum address space..................................................................................................... 189
Instantiation..................................................................................................................................190
FlexBus Controller........................................................................................................................................... 190
3.9.4.1
FlexBus signal multiplexing........................................................................................................ 190
3.9.4.2
VFxxx Controller restrictions...................................................................................................... 192
3.9.4.3
FlexBus Signal Multiplexing....................................................................................................... 192
3.9.4.4
FlexBus External Signal...............................................................................................................193
3.9.4.5
FlexBus Security.......................................................................................................................... 193
3.9.4.6
Instantiation Information..............................................................................................................193
3.9.4.7
FlexBus Chip Select Control Register (CSCR0) Reset Value..................................................... 195
3.9.4.8
Bus Timeout................................................................................................................................. 195
3.10 Communication interfaces.............................................................................................................................................. 195
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Section number
3.10.1
3.10.2
3.10.3
Title
10/100 Ethernet Subsystem..............................................................................................................................195
3.10.1.1
Instantiation Information..............................................................................................................195
3.10.1.2
MII and RMII configuration........................................................................................................ 196
3.10.1.3
IEEE 1588 Timers........................................................................................................................197
3.10.1.4
Ethernet Operation in Low Power Modes....................................................................................197
3.10.1.5
Ethernet Subsystem Interrupts..................................................................................................... 199
3.10.1.6
Ethernet switch register reset values............................................................................................ 200
USB 2.0 HS/FS/LS Dual Role (Host / Device) Controller.............................................................................. 200
3.10.2.1
USB Configuration and Options.................................................................................................. 200
3.10.2.2
USB Host initialization and bring up........................................................................................... 200
3.10.2.3
SOF for USB Audio..................................................................................................................... 203
3.10.2.4
OverCurrent and VBUS Connection............................................................................................204
Secure Digital Host Controller (SDHC).......................................................................................................... 205
3.10.3.1
SD bus pullup/pulldown constraints............................................................................................ 205
3.10.3.2
SDHC Wakeup.............................................................................................................................206
3.10.3.2.1
3.10.3.3
3.10.4
3.10.5
3.10.8
SDHC Software Guidelines......................................................................................................... 206
3.10.4.1
UART configuration information................................................................................................ 207
3.10.4.2
UART wakeup............................................................................................................................. 207
3.10.4.3
UART interrupts.......................................................................................................................... 207
FlexCAN.......................................................................................................................................................... 208
Instantiation..................................................................................................................................208
MediaLB Device Module (MLB50)................................................................................................................ 209
3.10.6.1
3.10.7
Setting Wake Up Events....................................................................................... 206
UART...............................................................................................................................................................207
3.10.5.1
3.10.6
Page
Instantiation..................................................................................................................................209
SPI.................................................................................................................................................................... 209
3.10.7.1
SPI Instantiation........................................................................................................................... 209
3.10.7.2
Number of PCS............................................................................................................................ 210
Inter-Integrated Circuit (I2C)...........................................................................................................................211
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Section number
3.10.8.1
Title
Page
Instantiation Information..............................................................................................................211
3.11 Analog.............................................................................................................................................................................211
3.11.1
3.11.2
12-bit Analog to Digital Converter (ADC)...................................................................................................... 211
3.11.1.1
ADC Instantiation ....................................................................................................................... 211
3.11.1.2
Voltage reference selection (REFSEL settings)...........................................................................212
3.11.1.3
DMA Support on ADC................................................................................................................ 212
3.11.1.4
ADC Channel Assignments......................................................................................................... 212
3.11.1.5
ADC interconnections..................................................................................................................213
3.11.1.6
ADC Calibration.......................................................................................................................... 213
3.11.1.7
Temperature Sensor..................................................................................................................... 214
12-Bit Digital-to-Analog Converter (DAC).....................................................................................................214
3.11.2.1
12-bit DAC Instantiation..............................................................................................................214
3.11.2.2
12-bit DAC External Reference................................................................................................... 214
3.11.2.3
DMA support on DAC................................................................................................................. 215
3.11.2.4
DAC interconnections..................................................................................................................215
3.12 Display/Video interfaces.................................................................................................................................................215
3.12.1
Display Control Unit........................................................................................................................................ 215
3.12.1.1
3.12.2
Timing Controller (TCON).............................................................................................................................. 215
3.12.2.1
3.12.3
3.12.5
Instantiation..................................................................................................................................215
RLE Decoder (RLE)........................................................................................................................................ 216
3.12.3.1
3.12.4
Instantiation..................................................................................................................................215
Instantiation..................................................................................................................................216
Segmented LCD Controller............................................................................................................................. 216
3.12.4.1
Instantiation..................................................................................................................................216
3.12.4.2
Number of Front and Back Planes............................................................................................... 216
3.12.4.3
LCD clock selection.....................................................................................................................216
3.12.4.4
Settings during STANDBY mode................................................................................................217
3.12.4.5
Segment LCD configuration........................................................................................................ 217
Video Interface Unit(VIU)...............................................................................................................................218
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Section number
3.12.5.1
3.12.6
Title
Page
Instantiation..................................................................................................................................218
Video ADC(VADC)........................................................................................................................................ 218
3.12.6.1
Instantiation..................................................................................................................................218
3.13 Audio Subsystem............................................................................................................................................................ 219
3.13.1
Audio Subsystem Modules.............................................................................................................................. 219
3.13.1.1
Audio Subsystem Overview.........................................................................................................219
3.13.1.2
Synchronous Audio Interface (SAI)............................................................................................ 220
3.13.1.2.1
SAI3 register details..............................................................................................220
3.13.1.2.2
Simultaneous SAI DMA requests.........................................................................221
3.13.1.2.3
SAI transmitter and receiver options for MCLK selection...................................221
3.13.1.2.4
SAI in Stop mode..................................................................................................221
3.13.1.3
Enhanced Serial Audio Interface (ESAI).....................................................................................221
3.13.1.4
ESAI Bus Interface and FIFO (ESAI_BIFIFO)...........................................................................222
3.14 Miscellaneous................................................................................................................................................................. 222
3.14.1
GPIO................................................................................................................................................................ 222
3.14.1.1
GPIO Mapping............................................................................................................................. 222
3.14.1.2
Configuring a pin as GPIO...........................................................................................................226
3.14.1.3
Port 4 Register Differences.......................................................................................................... 226
Chapter 4
Memory Map
4.1
System memory map.......................................................................................................................................................229
4.2
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................................... 231
4.3
Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................................... 234
4.4
Private Peripheral Bus (PPB) memory map....................................................................................................................238
Chapter 5
Chip IO and Pinmux
5.1
Pinouts............................................................................................................................................................................ 239
5.2
Input/Output Multiplexer Controller (IOMUXC)...........................................................................................................239
5.2.1
Overview.......................................................................................................................................................... 239
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Section number
Title
Page
5.2.2
Functional Description..................................................................................................................................... 240
5.2.3
Daisy chain - multi pads driving same module input pin................................................................................ 244
5.2.4
IOMUXC register groups.................................................................................................................................245
5.2.5
Memory map and register definition................................................................................................................245
5.2.5.1
Software MUX Pad Control Register 0 (IOMUXC_PTA6)........................................................ 256
5.2.5.2
Software MUX Pad Control Register 1 (IOMUXC_PTA8)........................................................ 257
5.2.5.3
Software MUX Pad Control Register 2 (IOMUXC_PTA9)........................................................ 259
5.2.5.4
Software MUX Pad Control Register 3 (IOMUXC_PTA10)...................................................... 261
5.2.5.5
Software MUX Pad Control Register 4 (IOMUXC_PTA11)...................................................... 263
5.2.5.6
Software MUX Pad Control Register 5 (IOMUXC_PTA12)...................................................... 264
5.2.5.7
Software MUX Pad Control Register 6 (IOMUXC_PTA16)...................................................... 266
5.2.5.8
Software MUX Pad Control Register 7 (IOMUXC_PTA17)...................................................... 268
5.2.5.9
Software MUX Pad Control Register 8 (IOMUXC_PTA18)...................................................... 270
5.2.5.10
Software MUX Pad Control Register 9 (IOMUXC_PTA19)...................................................... 271
5.2.5.11
Software MUX Pad Control Register 10 (IOMUXC_PTA20).................................................... 273
5.2.5.12
Software MUX Pad Control Register 11 (IOMUXC_PTA21).................................................... 275
5.2.5.13
Software MUX Pad Control Register 12 (IOMUXC_PTA22).................................................... 277
5.2.5.14
Software MUX Pad Control Register 13 (IOMUXC_PTA23).................................................... 278
5.2.5.15
Software MUX Pad Control Register 14 (IOMUXC_PTA24).................................................... 280
5.2.5.16
Software MUX Pad Control Register 15 (IOMUXC_PTA25).................................................... 282
5.2.5.17
Software MUX Pad Control Register 16 (IOMUXC_PTA26).................................................... 283
5.2.5.18
Software MUX Pad Control Register 17 (IOMUXC_PTA27).................................................... 285
5.2.5.19
Software MUX Pad Control Register 18 (IOMUXC_PTA28).................................................... 287
5.2.5.20
Software MUX Pad Control Register 19 (IOMUXC_PTA29).................................................... 288
5.2.5.21
Software MUX Pad Control Register 20 (IOMUXC_PTA30).................................................... 290
5.2.5.22
Software MUX Pad Control Register 21 (IOMUXC_PTA31).................................................... 292
5.2.5.23
Software MUX Pad Control Register 22 (IOMUXC_PTB0)...................................................... 294
5.2.5.24
Software MUX Pad Control Register 23 (IOMUXC_PTB1)...................................................... 295
5.2.5.25
Software MUX Pad Control Register 24 (IOMUXC_PTB2)...................................................... 297
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Section number
Title
Page
5.2.5.26
Software MUX Pad Control Register 25 (IOMUXC_PTB3)...................................................... 299
5.2.5.27
Software MUX Pad Control Register 26 (IOMUXC_PTB4)...................................................... 301
5.2.5.28
Software MUX Pad Control Register 27 (IOMUXC_PTB5)...................................................... 302
5.2.5.29
Software MUX Pad Control Register 28 (IOMUXC_PTB6)...................................................... 304
5.2.5.30
Software MUX Pad Control Register 29 (IOMUXC_PTB7)...................................................... 306
5.2.5.31
Software MUX Pad Control Register 30 (IOMUXC_PTB8)...................................................... 308
5.2.5.32
Software MUX Pad Control Register 31 (IOMUXC_PTB9)...................................................... 309
5.2.5.33
Software MUX Pad Control Register 32 (IOMUXC_PTB10).................................................... 311
5.2.5.34
Software MUX Pad Control Register 33 (IOMUXC_PTB11).................................................... 313
5.2.5.35
Software MUX Pad Control Register 34 (IOMUXC_PTB12).................................................... 315
5.2.5.36
Software MUX Pad Control Register 35 (IOMUXC_PTB13).................................................... 316
5.2.5.37
Software MUX Pad Control Register 36 (IOMUXC_PTB14).................................................... 318
5.2.5.38
Software MUX Pad Control Register 37 (IOMUXC_PTB15).................................................... 320
5.2.5.39
Software MUX Pad Control Register 38 (IOMUXC_PTB16).................................................... 321
5.2.5.40
Software MUX Pad Control Register 39 (IOMUXC_PTB17).................................................... 323
5.2.5.41
Software MUX Pad Control Register 40 (IOMUXC_PTB18).................................................... 325
5.2.5.42
Software MUX Pad Control Register 41 (IOMUXC_PTB19).................................................... 326
5.2.5.43
Software MUX Pad Control Register 42 (IOMUXC_PTB20).................................................... 328
5.2.5.44
Software MUX Pad Control Register 43 (IOMUXC_PTB21).................................................... 330
5.2.5.45
Software MUX Pad Control Register 44 (IOMUXC_PTB22).................................................... 331
5.2.5.46
Software MUX Pad Control Register 45 (IOMUXC_PTC0)...................................................... 333
5.2.5.47
Software MUX Pad Control Register 46 (IOMUXC_PTC1)...................................................... 335
5.2.5.48
Software MUX Pad Control Register 47 (IOMUXC_PTC2)...................................................... 337
5.2.5.49
Software MUX Pad Control Register 48 (IOMUXC_PTC3)...................................................... 338
5.2.5.50
Software MUX Pad Control Register 49 (IOMUXC_PTC4)...................................................... 340
5.2.5.51
Software MUX Pad Control Register 50 (IOMUXC_PTC5)...................................................... 342
5.2.5.52
Software MUX Pad Control Register 51 (IOMUXC_PTC6)...................................................... 344
5.2.5.53
Software MUX Pad Control Register 52 (IOMUXC_PTC7)...................................................... 345
5.2.5.54
Software MUX Pad Control Register 53 (IOMUXC_PTC8)...................................................... 347
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Section number
Title
Page
5.2.5.55
Software MUX Pad Control Register 54 (IOMUXC_PTC9)...................................................... 349
5.2.5.56
Software MUX Pad Control Register 55 (IOMUXC_PTC10).................................................... 351
5.2.5.57
Software MUX Pad Control Register 56 (IOMUXC_PTC11).................................................... 352
5.2.5.58
Software MUX Pad Control Register 57 (IOMUXC_PTC12).................................................... 354
5.2.5.59
Software MUX Pad Control Register 58 (IOMUXC_PTC13).................................................... 356
5.2.5.60
Software MUX Pad Control Register 59 (IOMUXC_PTC14).................................................... 358
5.2.5.61
Software MUX Pad Control Register 60 (IOMUXC_PTC15).................................................... 359
5.2.5.62
Software MUX Pad Control Register 61 (IOMUXC_PTC16).................................................... 361
5.2.5.63
Software MUX Pad Control Register 62 (IOMUXC_PTC17).................................................... 363
5.2.5.64
Software MUX Pad Control Register 63 (IOMUXC_PTD31).................................................... 365
5.2.5.65
Software MUX Pad Control Register 64 (IOMUXC_PTD30).................................................... 366
5.2.5.66
Software MUX Pad Control Register 65 (IOMUXC_PTD29).................................................... 368
5.2.5.67
Software MUX Pad Control Register 66 (IOMUXC_PTD28).................................................... 370
5.2.5.68
Software MUX Pad Control Register 67 (IOMUXC_PTD27).................................................... 371
5.2.5.69
Software MUX Pad Control Register 68 (IOMUXC_PTD26).................................................... 373
5.2.5.70
Software MUX Pad Control Register 69 (IOMUXC_PTD25).................................................... 375
5.2.5.71
Software MUX Pad Control Register 70 (IOMUXC_PTD24).................................................... 376
5.2.5.72
Software MUX Pad Control Register 71 (IOMUXC_PTD23).................................................... 378
5.2.5.73
Software MUX Pad Control Register 72 (IOMUXC_PTD22).................................................... 380
5.2.5.74
Software MUX Pad Control Register 73 (IOMUXC_PTD21).................................................... 382
5.2.5.75
Software MUX Pad Control Register 74 (IOMUXC_PTD20).................................................... 383
5.2.5.76
Software MUX Pad Control Register 75 (IOMUXC_PTD19).................................................... 385
5.2.5.77
Software MUX Pad Control Register 76 (IOMUXC_PTD18).................................................... 387
5.2.5.78
Software MUX Pad Control Register 77 (IOMUXC_PTD17).................................................... 389
5.2.5.79
Software MUX Pad Control Register 78 (IOMUXC_PTD16).................................................... 390
5.2.5.80
Software MUX Pad Control Register 79 (IOMUXC_PTD0)...................................................... 392
5.2.5.81
Software MUX Pad Control Register 80 (IOMUXC_PTD1)...................................................... 394
5.2.5.82
Software MUX Pad Control Register 81 (IOMUXC_PTD2)...................................................... 396
5.2.5.83
Software MUX Pad Control Register 82 (IOMUXC_PTD3)...................................................... 397
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Section number
Title
Page
5.2.5.84
Software MUX Pad Control Register 83 (IOMUXC_PTD4)...................................................... 399
5.2.5.85
Software MUX Pad Control Register 84 (IOMUXC_PTD5)...................................................... 401
5.2.5.86
Software MUX Pad Control Register 85 (IOMUXC_PTD6)...................................................... 403
5.2.5.87
Software MUX Pad Control Register 86 (IOMUXC_PTD7)...................................................... 404
5.2.5.88
Software MUX Pad Control Register 87 (IOMUXC_PTD8)...................................................... 406
5.2.5.89
Software MUX Pad Control Register 88 (IOMUXC_PTD9)...................................................... 408
5.2.5.90
Software MUX Pad Control Register 89 (IOMUXC_PTD10).................................................... 410
5.2.5.91
Software MUX Pad Control Register 90 (IOMUXC_PTD11).................................................... 411
5.2.5.92
Software MUX Pad Control Register 91 (IOMUXC_PTD12).................................................... 413
5.2.5.93
Software MUX Pad Control Register 92 (IOMUXC_PTD13).................................................... 415
5.2.5.94
Software MUX Pad Control Register 93 (IOMUXC_PTB23).................................................... 416
5.2.5.95
Software MUX Pad Control Register 94 (IOMUXC_PTB24).................................................... 418
5.2.5.96
Software MUX Pad Control Register 95 (IOMUXC_PTB25).................................................... 420
5.2.5.97
Software MUX Pad Control Register 96 (IOMUXC_PTB26).................................................... 422
5.2.5.98
Software MUX Pad Control Register 97 (IOMUXC_PTB27).................................................... 423
5.2.5.99
Software MUX Pad Control Register 98 (IOMUXC_PTB28).................................................... 425
5.2.5.100
Software MUX Pad Control Register 99 (IOMUXC_PTC26).................................................... 427
5.2.5.101
Software MUX Pad Control Register 100 (IOMUXC_PTC27).................................................. 428
5.2.5.102
Software MUX Pad Control Register 101 (IOMUXC_PTC28).................................................. 430
5.2.5.103
Software MUX Pad Control Register 102 (IOMUXC_PTC29).................................................. 432
5.2.5.104
Software MUX Pad Control Register 103 (IOMUXC_PTC30).................................................. 434
5.2.5.105
Software MUX Pad Control Register 104 (IOMUXC_PTC31).................................................. 435
5.2.5.106
Software MUX Pad Control Register 105 (IOMUXC_PTE0).................................................... 437
5.2.5.107
Software MUX Pad Control Register 106 (IOMUXC_PTE1).................................................... 439
5.2.5.108
Software MUX Pad Control Register 107 (IOMUXC_PTE2).................................................... 440
5.2.5.109
Software MUX Pad Control Register 108 (IOMUXC_PTE3).................................................... 442
5.2.5.110
Software MUX Pad Control Register 109 (IOMUXC_PTE4).................................................... 444
5.2.5.111
Software MUX Pad Control Register 110 (IOMUXC_PTE5).................................................... 445
5.2.5.112
Software MUX Pad Control Register 111 (IOMUXC_PTE6).................................................... 447
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Section number
Title
Page
5.2.5.113
Software MUX Pad Control Register 112 (IOMUXC_PTE7).................................................... 449
5.2.5.114
Software MUX Pad Control Register 113 (IOMUXC_PTE8).................................................... 450
5.2.5.115
Software MUX Pad Control Register 114 (IOMUXC_PTE9).................................................... 452
5.2.5.116
Software MUX Pad Control Register 115 (IOMUXC_PTE10).................................................. 454
5.2.5.117
Software MUX Pad Control Register 116 (IOMUXC_PTE11).................................................. 455
5.2.5.118
Software MUX Pad Control Register 117 (IOMUXC_PTE12).................................................. 457
5.2.5.119
Software MUX Pad Control Register 118 (IOMUXC_PTE13).................................................. 459
5.2.5.120
Software MUX Pad Control Register 119 (IOMUXC_PTE14).................................................. 460
5.2.5.121
Software MUX Pad Control Register 120 (IOMUXC_PTE15).................................................. 462
5.2.5.122
Software MUX Pad Control Register 121 (IOMUXC_PTE16).................................................. 464
5.2.5.123
Software MUX Pad Control Register 122 (IOMUXC_PTE17).................................................. 465
5.2.5.124
Software MUX Pad Control Register 123 (IOMUXC_PTE18).................................................. 467
5.2.5.125
Software MUX Pad Control Register 124 (IOMUXC_PTE19).................................................. 469
5.2.5.126
Software MUX Pad Control Register 125 (IOMUXC_PTE20).................................................. 470
5.2.5.127
Software MUX Pad Control Register 126 (IOMUXC_PTE21).................................................. 472
5.2.5.128
Software MUX Pad Control Register 127 (IOMUXC_PTE22).................................................. 474
5.2.5.129
Software MUX Pad Control Register 128 (IOMUXC_PTE23).................................................. 475
5.2.5.130
Software MUX Pad Control Register 129 (IOMUXC_PTE24).................................................. 477
5.2.5.131
Software MUX Pad Control Register 130 (IOMUXC_PTE25).................................................. 479
5.2.5.132
Software MUX Pad Control Register 131 (IOMUXC_PTE26).................................................. 480
5.2.5.133
Software MUX Pad Control Register 132 (IOMUXC_PTE27).................................................. 482
5.2.5.134
Software MUX Pad Control Register 133 (IOMUXC_PTE28).................................................. 484
5.2.5.135
Software MUX Pad Control Register 134 (IOMUXC_PTA7).................................................... 486
5.2.5.136
Software MUX DDR RESET Pad Configuration Register (IOMUXC_DDR_RESETB).......... 488
5.2.5.137
Software MUX DDR A15 Pad Control Register (IOMUXC_DDR_A_15)................................489
5.2.5.138
Software MUX DDR A14 Pad Control Register (IOMUXC_DDR_A_14)................................491
5.2.5.139
Software MUX DDR A13 Pad Control Register (IOMUXC_DDR_A_13)................................492
5.2.5.140
Software MUX DDR A12 Pad Control Register (IOMUXC_DDR_A_12)................................494
5.2.5.141
Software MUX DDR A11 Pad Control Register (IOMUXC_DDR_A_11)................................495
VFxxx Controller Reference Manual, Rev. 0, 10/2016
NXP Semiconductors
13
Section number
Title
Page
5.2.5.142
Software MUX DDR A10 Pad Control Register (IOMUXC_DDR_A_10)................................497
5.2.5.143
Software MUX DDR A9 Pad Control Register (IOMUXC_DDR_A_9)....................................498
5.2.5.144
Software MUX DDR A8 Pad Control Register (IOMUXC_DDR_A_8)....................................500
5.2.5.145
Software MUX DDR A7 Pad Control Register (IOMUXC_DDR_A_7)....................................501
5.2.5.146
Software MUX DDR A6 Pad Control Register (IOMUXC_DDR_A_6)....................................503
5.2.5.147
Software MUX DDR A5 Pad Control Register (IOMUXC_DDR_A_5)....................................504
5.2.5.148
Software MUX DDR A4 Pad Control Register (IOMUXC_DDR_A_4)....................................506
5.2.5.149
Software MUX DDR Pad A3 Control Register (IOMUXC_DDR_A_3)....................................507
5.2.5.150
Software MUX DDR A2 Pad Control Register (IOMUXC_DDR_A_2)....................................509
5.2.5.151
Software MUX DDR A1 Pad Control Register (IOMUXC_DDR_A_1)....................................510
5.2.5.152
Software MUX DDR A0 Pad Control Register (IOMUXC_DDR_A_0)....................................512
5.2.5.153
Software MUX DDR BA2 Pad Control Register (IOMUXC_DDR_BA_2).............................. 513
5.2.5.154
Software MUX DDR BA1 Pad Control Register (IOMUXC_DDR_BA_1).............................. 515
5.2.5.155
Software MUX DDR BA0 Pad Control Register (IOMUXC_DDR_BA_0).............................. 516
5.2.5.156
Software MUX DDR CAS Pad Control Register (IOMUXC_DDR_CAS_B)........................... 518
5.2.5.157
Software MUX DDR CKE0 Pad Control Register (IOMUXC_DDR_CKE_0)..........................519
5.2.5.158
Software MUX DDR CLK0 Pad Control Register (IOMUXC_DDR_CLK_0)..........................521
5.2.5.159
Software MUX DDR CS B0 Pad Control Register (IOMUXC_DDR_CS_B_0)....................... 522
5.2.5.160
Software MUX DDR CS D15 Pad Control Register (IOMUXC_DDR_CS_D_15)................... 524
5.2.5.161
Software MUX DDR CS D14 Pad Control Register (IOMUXC_DDR_CS_D_14)................... 525
5.2.5.162
Software MUX DDR CS D13 Pad Control Register (IOMUXC_DDR_CS_D_13)................... 527
5.2.5.163
Software MUX DDR CS D12 Pad Control Register (IOMUXC_DDR_CS_D_12)................... 528
5.2.5.164
Software MUX DDR CS D11 Pad Control Register (IOMUXC_DDR_CS_D_11)................... 530
5.2.5.165
Software MUX DDR CS D10 Pad Control Register (IOMUXC_DDR_CS_D_10)................... 531
5.2.5.166
Software MUX DDR CS D9 Pad Control Register (IOMUXC_DDR_CS_D_9)....................... 533
5.2.5.167
Software MUX DDR CS D8 Pad Control Register (IOMUXC_DDR_CS_D_8)....................... 534
5.2.5.168
Software MUX DDR CS D7 Pad Control Register (IOMUXC_DDR_CS_D_7)....................... 536
5.2.5.169
Software MUX DDR CS D6 Pad Control Register (IOMUXC_DDR_CS_D_6)....................... 537
5.2.5.170
Software MUX DDR CS D5 Pad Control Register (IOMUXC_DDR_CS_D_5)....................... 539
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14
NXP Semiconductors
Section number
Title
Page
5.2.5.171
Software MUX DDR CS D4 Pad Control Register (IOMUXC_DDR_CS_D_4)....................... 540
5.2.5.172
Software MUX DDR CS D3 Pad Control Register (IOMUXC_DDR_CS_D_3)....................... 542
5.2.5.173
Software MUX DDR CS D2 Pad Control Register (IOMUXC_DDR_CS_D_2)....................... 543
5.2.5.174
Software MUX DDR CS D1 Pad Control Register (IOMUXC_DDR_CS_D_1)....................... 545
5.2.5.175
Software MUX DDR CS D0 Pad Control Register (IOMUXC_DDR_CS_D_0)....................... 546
5.2.5.176
Software MUX DDR DQM1 Pad Control Register (IOMUXC_DDR_DQM_1)....................... 548
5.2.5.177
Software MUX DDR DQM0 Pad Control Register 0 (IOMUXC_DDR_DQM_0).................... 549
5.2.5.178
Software MUX DDR DQS1 Pad Control Register 1 (IOMUXC_DDR_DQS_1).......................551
5.2.5.179
Software MUX DDR DQS0 Pad Control Register 0 (IOMUXC_DDR_DQS_0).......................552
5.2.5.180
Software MUX DDR RAS Pad Control Register (IOMUXC_DDR_RAS_B)........................... 554
5.2.5.181
Software MUX DDR WE Pad Control Register (IOMUXC_DDR_WE_B).............................. 555
5.2.5.182
Software MUX DDR ODT0 Pad Control Register (IOMUXC_DDR_ODT_0)......................... 557
5.2.5.183
Software MUX DDR ODT1 Pad Control Register (IOMUXC_DDR_ODT_1)......................... 558
5.2.5.184
Software MUX Dummy DDRBYTE1 Pad Control Register
(IOMUXC_DUMMY_DDRBYTE1).......................................................................................... 560
5.2.5.185
Software MUX Dummy DDRBYTE2 Pad Control Register
(IOMUXC_DUMMY_DDRBYTE2).......................................................................................... 561
5.2.5.186
CCM Audio External Clock Input Select Register
(IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT)........................................................... 563
5.2.5.187
CCM Ethernet External Clock Input Select Register
(IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT)......................................................... 563
5.2.5.188
CCM Ethernet TS Clock Input Select Register
(IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT).............................................................564
5.2.5.189
DSPI1 SCK Input Select Register (IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT)...... 565
5.2.5.190
DSPI1 SIN Input Select Register (IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT).........566
5.2.5.191
DSPI1 SS Input Select Register (IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT)........ 567
5.2.5.192
Ethernet MAC0 TIMER0 Input Select Register
(IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT)...................... 568
5.2.5.193
Ethernet MAC0 TIMER1 Input Select Register
(IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT)...................... 569
5.2.5.194
ESAI FST Input Select Register (IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT)........... 570
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NXP Semiconductors
15
Section number
Title
Page
5.2.5.195
ESAI SCKT Input Select Register (IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT).....571
5.2.5.196
ESAI SDO0 Input Select Register (IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT)..... 572
5.2.5.197
ESAI SDO1 Input Select Register (IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT)..... 573
5.2.5.198
ESAI SDO2 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT).................................................. 574
5.2.5.199
ESAI SDO3 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT).................................................. 575
5.2.5.200
ESAI SDO4 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT).................................................. 576
5.2.5.201
ESAI SDO5 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT).................................................. 577
5.2.5.202
FlexTimer1 CH0 Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT)................................... 578
5.2.5.203
FlexTimer1 CH1 Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT)................................... 579
5.2.5.204
FlexTimer1 PHA Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT).....................................580
5.2.5.205
FlexTimer1 PHB Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT)..................................... 581
5.2.5.206
I2C0 SCL Input Select Register (IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT)............ 581
5.2.5.207
I2C0 SDA Input Select Register (IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT)........... 582
5.2.5.208
I2C1 SCL Input Select Register (IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT)............ 583
5.2.5.209
I2C1 SDA Input Select Register (IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT)........... 583
5.2.5.210
I2C2 SCL Input Select Register (IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT)............ 584
5.2.5.211
I2C2 SDA Input Select Register (IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT)........... 585
5.2.5.212
MediaLB Clock Input Select Register
(IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT)....................................................... 586
5.2.5.213
MediaLB Data Input Select Register
(IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT)....................................................... 587
5.2.5.214
MediaLB Signal Input Select Register
(IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT).........................................................588
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16
NXP Semiconductors
Section number
5.2.5.215
Title
Page
SAI1 TXSYNC Input Select Register
(IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT)...............................................589
5.2.5.216
SAI2 RXBCLK Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT).............................................. 589
5.2.5.217
SAI2 RXDATA0 Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT).......................................... 590
5.2.5.218
SAI2 RXSYNC Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT).............................................. 591
5.2.5.219
SAI2 TXBLCK Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT)...............................................591
5.2.5.220
SAI2 TXSYNC Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT)...............................................592
5.2.5.221
UART FLX1 CTS Input Select Register
(IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT)..................................................593
5.2.5.222
UART FLX1 RX Input Select Register
(IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT)................................................ 593
5.2.5.223
UART FLX1 TX Input Select Register
(IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT)................................................ 594
5.2.5.224
UART FLX2 CTS Input Select Register
(IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT)..................................................595
5.2.5.225
UART FLX2 RX Input Select Register
(IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT)................................................ 595
5.2.5.226
UART FLX2 TX Input Select Register
(IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT)................................................ 596
5.2.5.227
UART FLX3 RX Input Select Register
(IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT)................................................ 597
5.2.5.228
UART FLX3 TX Input Select Register
(IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT)................................................ 598
5.2.5.229
Video Decoder Input Select Register
(IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT)..................................................... 598
5.2.5.230
Video IN0 Input Select Register (IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT)599
5.2.5.231
Video PIXCLK Input Select Register
(IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT).......................................... 600
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NXP Semiconductors
17
Section number
5.2.6
5.3
Title
Page
Special Pad Settings......................................................................................................................................... 600
5.2.6.1
DUMMY PADS (DDR/QuadSPI)............................................................................................... 601
5.2.6.2
SDHC........................................................................................................................................... 601
5.2.6.3
I2C................................................................................................................................................601
5.2.6.4
FlexBus........................................................................................................................................ 601
5.2.6.5
LCD/ADC.................................................................................................................................... 601
5.2.6.6
SCI............................................................................................................................................... 602
5.2.6.7
Reset Pin Configuration............................................................................................................... 602
5.2.6.8
Typical IOMUX Configuration................................................................................................... 602
Port Control and Interrupts (PORT)............................................................................................................................... 613
5.3.1
.......................................................................................................................................................................... 0
5.3.2
Features............................................................................................................................................................ 613
5.3.3
Modes of operation.......................................................................................................................................... 614
5.3.4
5.3.3.1
Run mode..................................................................................................................................... 614
5.3.3.2
Wait mode.................................................................................................................................... 614
5.3.3.3
Stop mode.................................................................................................................................... 614
5.3.3.4
Debug mode................................................................................................................................. 614
.......................................................................................................................................................................... 0
5.3.4.1
...................................................................................................................................................... 0
5.3.4.2
...................................................................................................................................................... 0
5.3.4.2.1
............................................................................................................................... 0
5.3.4.2.2
............................................................................................................................... 0
5.3.4.2.3
............................................................................................................................... 0
5.3.4.2.4
............................................................................................................................... 0
5.3.5
.......................................................................................................................................................................... 0
5.3.6
.......................................................................................................................................................................... 0
5.3.7
Pin Control Register n (PORTx_PCRn)...........................................................................................................620
5.3.8
Interrupt Status Flag Register (PORTx_ISFR)................................................................................................ 621
5.3.9
Digital Filter Enable Register (PORTx_DFER)...............................................................................................622
VFxxx Controller Reference Manual, Rev. 0, 10/2016
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NXP Semiconductors
Section number
Page
5.3.10
Digital Filter Clock Register (PORTx_DFCR)................................................................................................ 622
5.3.11
Digital Filter Width Register (PORTx_DFWR).............................................................................................. 623
5.3.37
.......................................................................................................................................................................... 0
5.3.37.1
5.4
Title
...................................................................................................................................................... 0
5.3.38
External interrupts............................................................................................................................................623
5.3.39
Digital filter......................................................................................................................................................624
5.3.40
.......................................................................................................................................................................... 0
5.3.40.1
...................................................................................................................................................... 0
5.3.40.2
...................................................................................................................................................... 0
General-Purpose Input/Output (GPIO)........................................................................................................................... 625
5.4.1
Features............................................................................................................................................................ 625
5.4.2
Modes of operation.......................................................................................................................................... 625
5.4.3
GPIO signal descriptions................................................................................................................................. 625
5.4.3.1
5.4.4
Detailed signal description...........................................................................................................626
.......................................................................................................................................................................... 0
5.4.4.1
...................................................................................................................................................... 0
5.4.4.2
...................................................................................................................................................... 0
5.4.4.3
...................................................................................................................................................... 0
5.4.4.3.1
............................................................................................................................... 0
5.4.5
Port Data Output Register (GPIOx_PDOR).....................................................................................................628
5.4.6
Port Set Output Register (GPIOx_PSOR)........................................................................................................629
5.4.7
Port Clear Output Register (GPIOx_PCOR)....................................................................................................629
5.4.8
Port Toggle Output Register (GPIOx_PTOR)................................................................................................. 630
5.4.9
Port Data Input Register (GPIOx_PDIR).........................................................................................................630
5.4.35
.......................................................................................................................................................................... 0
5.4.35.1
...................................................................................................................................................... 0
5.4.36
General-purpose input......................................................................................................................................631
5.4.37
.......................................................................................................................................................................... 0
5.4.37.1
...................................................................................................................................................... 0
VFxxx Controller Reference Manual, Rev. 0, 10/2016
NXP Semiconductors
19
Section number
Title
Page
Chapter 6
Clocks and Power Management
6.1
Clocking Overview......................................................................................................................................................... 633
6.1.1
Introduction...................................................................................................................................................... 633
6.1.2
High Level Clocking Diagram......................................................................................................................... 633
6.1.3
Clock Sources.................................................................................................................................................. 635
6.1.4
CMU Block Diagram....................................................................................................................................... 636
6.1.5
PLL Summary.................................................................................................................................................. 637
6.1.6
6.1.7
6.1.5.1
PLL Block Diagram..................................................................................................................... 637
6.1.5.2
Spread Spectrum (SSC)............................................................................................................... 638
6.1.5.3
PLL Summary.............................................................................................................................. 639
PLL Features.................................................................................................................................................... 641
6.1.6.1
528 MHz Phase Locked Loop......................................................................................................641
6.1.6.2
High Frequency PLL ...................................................................................................................641
6.1.6.3
Ethernet PLL ............................................................................................................................... 642
PLL/PFD Configuration...................................................................................................................................643
6.1.7.1
PLL Configuration....................................................................................................................... 643
6.1.7.1.1
6.1.7.2
Typical PLL Configuration...................................................................................643
PFD Configuration....................................................................................................................... 644
6.1.7.2.1
Typical PFD Configuration...................................................................................644
6.1.8
Clock Configuration.........................................................................................................................................645
6.1.9
Clock Modes.................................................................................................................................................... 646
6.1.9.1
Synchronous Mode...................................................................................................................... 646
6.1.9.1.1
6.1.9.2
Asynchronous Mode.................................................................................................................... 647
6.1.9.2.1
6.1.10
Asynchronous DDR mode.................................................................................... 647
Clock Gating.................................................................................................................................................... 647
6.1.10.1
6.1.11
Synchronous Mode............................................................................................... 646
Clock Gating................................................................................................................................ 647
Peripheral Clocks............................................................................................................................................. 648
VFxxx Controller Reference Manual, Rev. 0, 10/2016
20
NXP Semiconductors
Section number
6.2
Title
Page
6.1.11.1
Module clocks.............................................................................................................................. 648
6.1.11.2
FlexCAN Clocking...................................................................................................................... 648
6.1.11.3
FTM clocking...............................................................................................................................649
6.1.11.4
NFC clocking............................................................................................................................... 649
6.1.11.5
QuadSPI Clocking........................................................................................................................650
6.1.11.6
Ethernet RMII/MII Clocking....................................................................................................... 650
6.1.11.7
Ethernet Timer Clocking..............................................................................................................650
6.1.11.8
eSDHC Clocking..........................................................................................................................651
6.1.11.9
DCU clocking.............................................................................................................................. 651
6.1.11.10
ESAI clocking.............................................................................................................................. 652
6.1.11.11
SPDIF Clocking........................................................................................................................... 652
6.1.11.12
SAI clocking................................................................................................................................ 652
6.1.11.13
Video ADC clock.........................................................................................................................653
6.1.11.14
GPU clocking............................................................................................................................... 653
6.1.11.15
SWO Clocking............................................................................................................................. 654
6.1.11.16
Trace clocking..............................................................................................................................654
6.1.12
Appendix.......................................................................................................................................................... 655
6.1.13
Maximum Frequencies Supported................................................................................................................... 655
Clock Controller Module (CCM)....................................................................................................................................656
6.2.1
6.2.2
Introduction...................................................................................................................................................... 656
6.2.1.1
Overview...................................................................................................................................... 656
6.2.1.2
Features........................................................................................................................................ 657
6.2.1.3
CCM Block Diagram................................................................................................................... 657
Memory Map and Registers............................................................................................................................. 659
6.2.2.1
CCM Control Register (CCM_CCR)...........................................................................................661
6.2.2.2
CCM Status Register (CCM_CSR)..............................................................................................663
6.2.2.3
CCM Clock Switcher Register (CCM_CCSR)............................................................................ 664
6.2.2.4
CCM ARM Clock Root Register (CCM_CACRR)..................................................................... 666
6.2.2.5
CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1).................................................... 669
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NXP Semiconductors
21
Section number
6.3
6.4
Title
Page
6.2.2.6
CCM Serial Clock Divider Register 1 (CCM_CSCDR1)............................................................671
6.2.2.7
CCM Serial Clock Divider Register 2 (CCM_CSCDR2)............................................................674
6.2.2.8
CCM Serial Clock Divider Register 3 (CCM_CSCDR3)............................................................676
6.2.2.9
CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2).................................................... 678
6.2.2.10
CCM Testing Observability Register (CCM_CTOR)................................................................. 681
6.2.2.11
CCM Low Power Control Register (CCM_CLPCR).................................................................. 683
6.2.2.12
CCM Interrupt Status Register (CCM_CISR)............................................................................. 687
6.2.2.13
CCM Interrupt Mask Register (CCM_CIMR).............................................................................689
6.2.2.14
CCM Clock Output Source Register (CCM_CCOSR)................................................................ 690
6.2.2.15
CCM General Purpose Register (CCM_CGPR).......................................................................... 695
6.2.2.16
CCM Clock Gating Register (CCM_CCGRn).............................................................................696
6.2.2.17
CCM Module Enable Override Register (CCM_CMEORn)....................................................... 702
6.2.2.18
CCM PLL PFD Disable Status Register (CCM_CPPDSR).........................................................705
6.2.2.19
CCM CORE Wakeup Register (CCM_CCOWR)....................................................................... 707
6.2.2.20
CCM Platform Clock Gating Register (CCM_CCPGRn)........................................................... 708
6.2.3
Sync Signals..................................................................................................................................................... 711
6.2.4
Accessory clocks..............................................................................................................................................711
6.2.5
CKIL Synchronizing to ipg_clk....................................................................................................................... 711
6.2.6
Low Power Clock Gating module (LPCG)......................................................................................................711
6.2.7
Power modes.................................................................................................................................................... 714
Slow Clock Source Controller Module (SCSC)............................................................................................................. 714
6.3.1
Introduction...................................................................................................................................................... 714
6.3.2
Memory Map and Registers............................................................................................................................. 715
6.3.2.1
SIRC Control Register (SCSC_SIRC_CTR)............................................................................... 715
6.3.2.2
SOSC Control (SCSC_SOSC_CTR)........................................................................................... 716
Clock Monitor Unit (CMU)............................................................................................................................................ 717
6.4.1
Introduction...................................................................................................................................................... 717
6.4.1.1
6.4.2
Main features................................................................................................................................718
Block diagram.................................................................................................................................................. 718
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NXP Semiconductors
Section number
Signals.............................................................................................................................................................. 718
6.4.4
Register description and memory map.............................................................................................................719
6.4.4.1
CMU Control Status Register (CMU_CSR)................................................................................ 720
6.4.4.2
CMU Frequency Display Register (CMU_FDR)........................................................................ 721
6.4.4.3
CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)...................................722
6.4.4.4
CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR).................................... 722
6.4.4.5
CMU Interrupt Status Register (CMU_ISR)............................................................................... 723
6.4.4.6
CMU Measurement Duration Register (CMU_MDR)................................................................ 725
Functional description......................................................................................................................................725
6.4.5.1
Frequency meter...........................................................................................................................725
6.4.5.2
CLKMN0_RMT supervisor......................................................................................................... 726
6.4.5.3
CLKMN1 supervisor....................................................................................................................726
Power Management........................................................................................................................................................ 727
6.5.1
Introduction...................................................................................................................................................... 727
6.5.2
Power domains................................................................................................................................................. 728
6.5.3
Low-power modes............................................................................................................................................729
6.5.3.1
Run mode..................................................................................................................................... 730
6.5.3.2
LPRun mode................................................................................................................................ 730
6.5.3.3
ULPRun mode..............................................................................................................................730
6.5.3.4
Wait mode.................................................................................................................................... 730
6.5.3.5
Stop mode.................................................................................................................................... 731
6.5.3.6
6.5.3.7
6.6
Page
6.4.3
6.4.5
6.5
Title
6.5.3.5.1
Stop mode entry sequence (clock-gating mode)...................................................731
6.5.3.5.2
Optional stop mode entry sequence...................................................................... 731
LPStopn modes............................................................................................................................ 732
6.5.3.6.1
LPStopn mode entry sequence (power-gating mode)...........................................732
6.5.3.6.2
Optional LPStopn mode entry sequence...............................................................733
Interrupt connectivity................................................................................................................... 733
Global Power Controller (GPC)......................................................................................................................................734
6.6.1
Introduction...................................................................................................................................................... 734
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23
Section number
Title
6.6.2
Features............................................................................................................................................................ 734
6.6.3
GPC Memory/Register Map............................................................................................................................ 734
6.6.4
6.6.3.1
Power Gating Control Register (GPC_PGCR)............................................................................ 735
6.6.3.2
Power Gating Status Register (GPC_PGSR)............................................................................... 737
6.6.3.3
Low Power Mode Register (GPC_LPMR).................................................................................. 737
6.6.3.4
Interrupt Mask Register 1 (GPC_IMR1)..................................................................................... 739
6.6.3.5
Interrupt Mask Register 2 (GPC_IMR2)..................................................................................... 741
6.6.3.6
Interrupt Mask Register 3 (GPC_IMR3)..................................................................................... 744
6.6.3.7
Interrupt Mask Register (GPC_IMR4)........................................................................................ 747
6.6.3.8
Interrupt Status Register 1 (GPC_ISR1)...................................................................................... 748
6.6.3.9
Interrupt Status Register 2 (GPC_ISR2)...................................................................................... 750
6.6.3.10
Interrupt Status Register 3 (GPC_ISR3)...................................................................................... 752
6.6.3.11
Interrupt Status Register 4 (GPC_ISR4)...................................................................................... 755
Functional Description..................................................................................................................................... 756
6.6.4.1
Power Shutdown Controller.........................................................................................................756
6.6.4.2
Power Gating Controller.............................................................................................................. 757
6.6.4.2.1
6.7
Page
Functional Mode................................................................................................... 757
6.6.4.2.1.1
LPSTOP Entry Sequence (PG Entry Sequence)........................ 757
6.6.4.2.1.2
LPStop Mode Exit Sequence......................................................758
6.6.4.2.1.3
Stop Mode Entry Sequence........................................................ 759
6.6.4.2.1.4
Stop Mode Exit Sequence.......................................................... 759
6.6.4.2.1.5
Well Bias Stop mode entry sequence......................................... 759
6.6.4.2.1.6
Well Bias Stop mode exit sequence........................................... 760
6.6.4.2.1.7
Inhibit Stop and FIRC Control................................................... 760
Voltage Regulators..........................................................................................................................................................761
6.7.1
6.7.2
Overview.......................................................................................................................................................... 761
6.7.1.1
Signal Description........................................................................................................................762
6.7.1.2
Digital Interface Block Diagram..................................................................................................763
Memory Map and Registers............................................................................................................................. 763
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NXP Semiconductors
Section number
6.7.3
6.8
Title
Page
6.7.2.1
Control Register (VREG_CTRL)................................................................................................ 763
6.7.2.2
Status register (VREG_STAT).................................................................................................... 765
Functional Description..................................................................................................................................... 766
6.7.3.1
High Power or Main Regulator (HPREG)................................................................................... 766
6.7.3.2
Low Power Regulator (LPREG).................................................................................................. 766
6.7.3.3
Ultra Low Power Regulator (ULPREG)...................................................................................... 766
6.7.3.4
LVDs and POR............................................................................................................................ 767
6.7.3.5
Power Up Sequencing.................................................................................................................. 767
6.7.3.6
STOP Mode..................................................................................................................................768
6.7.3.7
Low Power Stop Mode (LPSTOP) ............................................................................................. 768
6.7.3.8
Well Bias STOP Mode.................................................................................................................768
Analog Components Control Digital Interface (ANADIG)............................................................................................769
6.8.1
Overview.......................................................................................................................................................... 769
6.8.2
Memory Map and Registers............................................................................................................................. 769
6.8.2.1
Anadig Registers.......................................................................................................................... 769
6.8.2.1.1
PLL3 Control register (ANADIG_PLL3_CTRL)................................................ 771
6.8.2.1.2
PLL7 Control register (ANADIG_PLL7_CTRL)................................................ 773
6.8.2.1.3
PLL2 Control register (ANADIG_PLL2_CTRL)................................................ 775
6.8.2.1.4
PLL2 Spread Spectrum definition register (ANADIG_PLL2_SS)...................... 777
6.8.2.1.5
PLL2 Numerator definition register (ANADIG_PLL2_NUM)............................778
6.8.2.1.6
PLL2 Denominator definition register (ANADIG_PLL2_DENOM)...................778
6.8.2.1.7
PLL4 Control register (ANADIG_PLL4_CTRL)................................................ 779
6.8.2.1.8
PLL4 Numerator register (ANADIG_PLL4_NUM)............................................ 780
6.8.2.1.9
PLL4 Denominator register (ANADIG_PLL4_DENOM)................................... 781
6.8.2.1.10
PLL6 Control register (ANADIG_PLL6_CTRL)................................................ 782
6.8.2.1.11
PLL6 Numerator register (ANADIG_PLL6_NUM)............................................ 783
6.8.2.1.12
PLL6 Denominator register (ANADIG_PLL6_DENOM)................................... 784
6.8.2.1.13
PLL5 Control register (ANADIG_PLL5_CTRL)................................................ 785
6.8.2.1.14
ANADIG PLL3 PFD definition register (ANADIG_PLL3_PFD).......................786
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25
Section number
Title
Page
6.8.2.1.15
ANADIG PLL2 PFD definition register (ANADIG_PLL2_PFD).......................789
6.8.2.1.16
ANADIG Regulator 1P1 definition register (ANADIG_REG_1P1)....................792
6.8.2.1.17
ANADIG Regulator 3P0 definition register (ANADIG_REG_3P0)....................793
6.8.2.1.18
ANADIG Regulator 2P5 definition register (ANADIG_REG_2P5)....................796
6.8.2.1.19
ANADIG Analog Miscellaneous definition register (ANADIG_ANA_MISC0) 798
6.8.2.1.20
ANADIG Analog Miscellaneous definition register (ANADIG_ANA_MISC1) 800
6.8.2.1.21
PLL1 Control register (ANADIG_PLL1_CTRL)................................................ 802
6.8.2.1.22
PLL1 Spread Spectrum register (ANADIG_PLL1_SS)....................................... 804
6.8.2.1.23
PLL1 Numerator register (ANADIG_PLL1_NUM)............................................ 805
6.8.2.1.24
PLL1 Denominator register (ANADIG_PLL1_DENOM)................................... 805
6.8.2.1.25
ANADIG PLL1_PFD definition register (ANADIG_PLL1_PFD)......................806
6.8.2.1.26
ANADIG PLL Lock register (ANADIG_PLL_LOCK)....................................... 808
Chapter 7
SNVS, Reset, eFuse, and Boot
7.1
Secure Non-Volatile Storage (SNVS)............................................................................................................................ 809
7.1.1
7.1.2
7.1.3
SNVS overview................................................................................................................................................809
7.1.1.1
SNVS features..............................................................................................................................810
7.1.1.2
Modes of operation...................................................................................................................... 811
SNVS structure................................................................................................................................................ 811
7.1.2.1
SNVS_HP (high-power domain)................................................................................................. 812
7.1.2.2
Non-secure real-time counter.......................................................................................................813
7.1.2.2.1
Calibrating the time counter..................................................................................813
7.1.2.2.2
Time counter alarm............................................................................................... 813
7.1.2.2.3
Periodic interrupt.................................................................................................. 814
SNVS_LP (low-power domain).......................................................................................................................814
7.1.3.1
Behavior during system power down...........................................................................................815
7.1.3.2
Monotonic Counter (MC)............................................................................................................ 815
7.1.4
SNVS reset and system powerup..................................................................................................................... 816
7.1.5
SNVS interrupts and alarms.............................................................................................................................816
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26
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Section number
7.1.6
7.1.7
7.2
7.3
Title
Page
Programming guidelines.................................................................................................................................. 816
7.1.6.1
RTC control bits setting............................................................................................................... 816
7.1.6.2
RTC value read............................................................................................................................ 817
7.1.6.3
General initialization guidelines.................................................................................................. 818
SNVS memory map/register definition............................................................................................................818
7.1.7.1
SNVS_HP Lock register (SNVS_HPLR).................................................................................... 820
7.1.7.2
SNVS_HP Command register (SNVS_HPCOMR)..................................................................... 823
7.1.7.3
SNVS_HP Control register (SNVS_HPCR)................................................................................825
7.1.7.4
SNVS_HP Status register (SNVS_HPSR)...................................................................................827
7.1.7.5
SNVS_HP Real-Time Counter MSB Register (SNVS_HPRTCMR)..........................................828
7.1.7.6
SNVS_HP Real-Time Counter LSB Register (SNVS_HPRTCLR)............................................829
7.1.7.7
SNVS_HP Time Alarm MSB Register (SNVS_HPTAMR)....................................................... 829
7.1.7.8
SNVS_HP Time Alarm LSB Register (SNVS_HPTALR)..........................................................830
7.1.7.9
SNVS_LP Lock Register (SNVS_LPLR)....................................................................................831
7.1.7.10
SNVS_LP Control Register (SNVS_LPCR)............................................................................... 833
7.1.7.11
SNVS_LP Status Register (SNVS_LPSR).................................................................................. 834
7.1.7.12
SNVS_LP Secure Monotonic Counter MSB Register (SNVS_LPSMCMR)............................. 836
7.1.7.13
SNVS_LP Secure Monotonic Counter LSB Register (SNVS_LPSMCLR)................................836
7.1.7.14
SNVS_LP General-Purpose Register (SNVS_LPGPR).............................................................. 837
7.1.7.15
SNVS_HP Version ID Register 1 (SNVS_HPVIDR1)............................................................... 837
7.1.7.16
SNVS_HP Version ID Register 2 (SNVS_HPVIDR2)............................................................... 838
Reset................................................................................................................................................................................839
7.2.1
Introduction...................................................................................................................................................... 839
7.2.2
Reset Sources................................................................................................................................................... 839
7.2.3
Reset Functions................................................................................................................................................ 839
7.2.4
Clock Monitor.................................................................................................................................................. 840
System Reset Controller (SRC)...................................................................................................................................... 841
7.3.1
Introduction...................................................................................................................................................... 841
7.3.2
SRC Overview................................................................................................................................................. 841
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27
Section number
7.3.2.1
7.3.3
7.3.4
7.4
Title
Page
Features........................................................................................................................................ 842
Memory Map and Register Definition............................................................................................................. 842
7.3.3.1
Register Descriptions................................................................................................................... 842
7.3.3.2
SRC Control Register (SRC_SCR)..............................................................................................844
7.3.3.3
SRC Boot Mode Register 1 (SRC_SBMR1)............................................................................... 845
7.3.3.4
SRC Status Register (SRC_SRSR).............................................................................................. 845
7.3.3.5
SRC_SECR.................................................................................................................................. 849
7.3.3.6
SRC Reset Interrupt Configuration Register (SRC_SICR)......................................................... 850
7.3.3.7
SRC Interrupt Masking Register (SRC_SIMR)...........................................................................852
7.3.3.8
SRC Boot Mode Register 2 (SRC_SBMR2)............................................................................... 854
7.3.3.9
General Purpose Register (SRC_GPRn)......................................................................................855
7.3.3.10
MISC0 (SRC_MISC0)................................................................................................................. 855
7.3.3.11
MISC1 (SRC_MISC1)................................................................................................................. 857
7.3.3.12
MISC2 (SRC_MISC2)................................................................................................................. 859
7.3.3.13
MISC3 (SRC_MISC3)................................................................................................................. 860
Functional Description..................................................................................................................................... 861
7.3.4.1
Reset Sources............................................................................................................................... 861
7.3.4.2
Destructive reset sequence........................................................................................................... 862
7.3.4.3
Functional reset sequence............................................................................................................ 863
7.3.4.4
External reset sequence................................................................................................................ 864
7.3.4.5
Standby reset sequence................................................................................................................ 865
7.3.4.6
Memory Repair............................................................................................................................ 867
7.3.4.7
BOOTMOD Pin Latching............................................................................................................ 868
On-Chip One Time Programmable Controller (OCOTP)...............................................................................................870
7.4.1
Introduction...................................................................................................................................................... 870
7.4.2
Overview of On-Chip OTP (OCOTP) controller.............................................................................................870
7.4.3
Top-level symbol and functional overview..................................................................................................... 870
7.4.3.1
Operation......................................................................................................................................871
7.4.3.1.1
Fuse shadow memory footprint............................................................................ 871
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Section number
Title
7.4.3.1.1.1
7.4.4
Page
Fuse map address table...............................................................872
7.4.3.1.2
Fuse values............................................................................................................873
7.4.3.1.3
Fuse protection and overrides............................................................................... 873
7.4.3.1.4
Fuse blowing.........................................................................................................873
7.4.3.1.5
Fuse and shadow register read.............................................................................. 874
7.4.3.1.6
Fuse and Shadow Register Writes........................................................................ 874
7.4.3.1.7
Write postamble.................................................................................................... 876
7.4.3.2
OTP read/write timing parameters............................................................................................... 876
7.4.3.3
Behavior During Reset.................................................................................................................877
7.4.3.4
Secure JTAG control....................................................................................................................877
OCOTP memory map/register definition.........................................................................................................878
7.4.4.1
OTP Controller Control Register (OCOTP_CTRLn).................................................................. 881
7.4.4.2
OTP Controller Timing Register (OCOTP_TIMING)................................................................ 883
7.4.4.3
OTP Controller Write Data Register (OCOTP_DATA)..............................................................883
7.4.4.4
OTP Controller Read Control Register (OCOTP_READ_CTRL).............................................. 884
7.4.4.5
OTP Controller Read Data Register (OCOTP_READ_FUSE_DATA)...................................... 885
7.4.4.6
Software Controllable Set Register (OCOTP_SCSn).................................................................. 885
7.4.4.7
OTP Controller CRC address (OCOTP_CRC_ADDR)...............................................................886
7.4.4.8
OTP Controller CRC Value Register (OCOTP_CRC_VALUE)................................................ 887
7.4.4.9
OTP Controller Version Register (OCOTP_VERSION).............................................................887
7.4.4.10
Value of OTP Bank0 Word0 (Lock controls) (OCOTP_LOCK)................................................ 887
7.4.4.11
Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) (OCOTP_CFG0).........890
7.4.4.12
Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) (OCOTP_CFG1).........891
7.4.4.13
Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) (OCOTP_CFG4).........891
7.4.4.14
Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) (OCOTP_CFG5).........895
7.4.4.15
Value of Bank1 Word6 (Temperature Sensor calibration OCOTP_ANA_TEMPSENSE)
(OCOTP_TEMPSENSE)............................................................................................................. 897
7.4.4.16
Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) (OCOTP_ANA2)..... 898
7.4.4.17
Value of OTP Bank4 Word0 (Secure JTAG Response Field) (OCOTP_RESP0)...................... 898
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Section number
7.5
Title
Page
7.4.4.18
Value of OTP Bank4 Word1 (Secure JTAG Response Field) (OCOTP_HSJC_RESP1)........... 899
7.4.4.19
Value of OTP Bank4 Word2 (MAC Address) (OCOTP_MAC0)............................................... 899
7.4.4.20
Value of OTP Bank4 Word3 (MAC Address) (OCOTP_MAC1)............................................... 900
7.4.4.21
Value of OTP Bank4 Word4 (MAC Address) (OCOTP_MAC2)............................................... 900
7.4.4.22
Value of OTP Bank4 Word5 (MAC Address) (OCOTP_MAC3)............................................... 901
7.4.4.23
Value of OTP Bank4 Word6 (HW Capabilities) (OCOTP_GP1)............................................... 901
7.4.4.24
Value of OTP Bank4 Word7 (HW Capabilities) (OCOTP_GP2)............................................... 902
7.4.4.25
Value of OTP Bank7 Word5 (Memory Related Info.) (OCOTP_RNG)..................................... 902
7.4.4.26
Value of OTP Bank7 Word7 (Memory Related Info.) (OCOTP_VTMON)............................... 903
7.4.4.27
Value of OTP Bank15 Word0 (OCOTP_CRC0)......................................................................... 904
7.4.4.28
Value of OTP Bank15 Word1 (OCOTP_CRC1)......................................................................... 904
7.4.4.29
Value of OTP Bank15 Word2 (OCOTP_CRC2)......................................................................... 905
7.4.4.30
Value of OTP Bank15 Word3 (OCOTP_CRC3)......................................................................... 905
7.4.4.31
Value of OTP Bank15 Word4 (OCOTP_CRC4)......................................................................... 906
7.4.4.32
Value of OTP Bank15 Word5 (OCOTP_CRC5)......................................................................... 906
7.4.4.33
Value of OTP Bank15 Word6 (OCOTP_CRC6)......................................................................... 907
7.4.4.34
Value of OTP Bank15 Word7 (OCOTP_CRC7)......................................................................... 907
System Boot.................................................................................................................................................................... 908
7.5.1
Introduction...................................................................................................................................................... 908
7.5.2
Boot Modes...................................................................................................................................................... 909
7.5.3
7.5.2.1
Boot Mode Pin Settings............................................................................................................... 910
7.5.2.2
High Level Boot Sequence.......................................................................................................... 910
7.5.2.3
Boot From Fuses Mode (BOOT_MODE [1:0] = 0b00).............................................................. 912
7.5.2.4
Mode: Serial Downloader Mode (BOOT_MODE [1:0] = 0b01)................................................ 912
7.5.2.5
Boot from RCON (BOOT_MODE [1:0] = 0b10)........................................................................913
Device Configuration....................................................................................................................................... 914
7.5.3.1
Boot eFUSE Descriptions............................................................................................................ 914
7.5.3.2
GPIO Boot Overrides...................................................................................................................916
7.5.3.3
Device Configuration Data.......................................................................................................... 917
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30
NXP Semiconductors
Section number
7.5.4
7.5.5
Title
Page
Device Initialization......................................................................................................................................... 917
7.5.4.1
Internal ROM / RAM Memory Map............................................................................................918
7.5.4.2
Boot Block Activation................................................................................................................. 918
7.5.4.3
Clocks at Boot Time.................................................................................................................... 919
7.5.4.4
Enabling MMU and Caches......................................................................................................... 923
7.5.4.5
WDOG_ENABLE eFUSE........................................................................................................... 924
7.5.4.6
Watchdog Reset Boot Mode........................................................................................................ 925
7.5.4.7
Exception Handling......................................................................................................................925
7.5.4.8
Interrupt Handling during Boot....................................................................................................925
7.5.4.9
Persistent Bits...............................................................................................................................926
Boot Devices (Internal Boot)........................................................................................................................... 926
7.5.5.1
7.5.5.2
7.5.5.3
QuadSPI Serial Flash Memory Boot............................................................................................927
7.5.5.1.1
QuadSPI eFUSE Configuration............................................................................ 927
7.5.5.1.2
QuadSPI Serial Flash BOOT Operation............................................................... 927
7.5.5.1.3
IOMUX Configuration for QuadSPI.................................................................... 928
7.5.5.1.4
CCM Settings in various modes .......................................................................... 929
7.5.5.1.5
QuadSPI Configuration Parameters......................................................................929
7.5.5.1.6
QuadSPI boot flow chart.......................................................................................932
7.5.5.1.7
QuadSPI register boot ROM reset values............................................................. 934
NOR Flash Boot using FlexBus Interface....................................................................................934
7.5.5.2.1
NOR Flash eFUSE Configuration........................................................................ 935
7.5.5.2.2
NOR Flash Boot Operation...................................................................................935
7.5.5.2.3
NOR Flash Configuration Block.......................................................................... 936
7.5.5.2.4
CCM Settings in various modes .......................................................................... 938
7.5.5.2.5
IOMUX Configuration for FlexBus......................................................................938
Serial ROM Boot using SPI/I2C Interface...................................................................................939
7.5.5.3.1
Serial ROM eFUSE Configuration....................................................................... 939
7.5.5.3.2
SPI Boot................................................................................................................ 940
7.5.5.3.3
IOMUX Configuration for SPI............................................................................. 942
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NXP Semiconductors
31
Section number
7.5.5.4
7.5.5.5
7.5.5.6
7.5.6
Title
Page
7.5.5.3.4
I2C Boot................................................................................................................943
7.5.5.3.5
IOMUX Configuration for I2C.............................................................................944
FlexCAN Boot............................................................................................................................. 945
7.5.5.4.1
FlexCAN eFUSE Configuration........................................................................... 945
7.5.5.4.2
FlexCAN Configuration Parameters.....................................................................945
7.5.5.4.3
FlexCAN Boot Operation..................................................................................... 946
7.5.5.4.4
IOMUX Configuration for FlexCAN................................................................... 949
SD/MMC Boot............................................................................................................................. 950
7.5.5.5.1
SD/MMC eFUSE Configuration.......................................................................... 950
7.5.5.5.2
MMC and eMMC Boot.........................................................................................952
7.5.5.5.3
SD, eSD Boot........................................................................................................959
7.5.5.5.4
IOMUX Configuration for SD/MMC...................................................................960
7.5.5.5.5
CCM Settings in various modes........................................................................... 960
7.5.5.5.6
Redundant Boot Support for Expansion Device...................................................961
NAND Flash Boot using NFC Interface...................................................................................... 962
7.5.5.6.1
NAND Flash eFUSE Configuration..................................................................... 962
7.5.5.6.2
NAND Flash Boot Flow and BOOT Control Blocks (BCB)................................963
7.5.5.6.3
Firmware Configuration Block (FCB)..................................................................965
7.5.5.6.4
Discovered Bad Block Table (DBBT)..................................................................967
7.5.5.6.5
Typical NAND Page Organization....................................................................... 967
7.5.5.6.6
Bad Block Handling in the ROM..........................................................................968
7.5.5.6.7
Setup DMA for DDR Transfers............................................................................970
7.5.5.6.8
IOMUX Configuration for NFC........................................................................... 970
7.5.5.6.9
CCM Settings in various modes........................................................................... 970
Program Image................................................................................................................................................. 971
7.5.6.1
7.5.6.2
Image Vector Table and Boot Data..............................................................................................971
7.5.6.1.1
Image Vector Table Structure...............................................................................972
7.5.6.1.2
Boot Data Structure...............................................................................................973
Device Configuration Data (DCD).............................................................................................. 973
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32
NXP Semiconductors
Section number
Title
7.5.6.2.1
Write Data Command........................................................................................... 974
7.5.6.2.2
Check Data Command.......................................................................................... 976
7.5.6.2.3
NOP Command.....................................................................................................977
7.5.7
Plugin Image.................................................................................................................................................... 978
7.5.8
Serial Downloader (BOOT_MODE [1:0] = 0b01).......................................................................................... 979
7.5.8.1
7.5.8.2
7.5.8.3
USB Boot Flow............................................................................................................................ 980
7.5.8.1.1
USB Configuration Details................................................................................... 980
7.5.8.1.2
IOMUX Configuration for USB........................................................................... 981
UART Boot Flow.........................................................................................................................981
7.5.8.2.1
UART eFUSE Configuration................................................................................981
7.5.8.2.2
IOMUX Configuration for UART........................................................................ 982
Serial Download protocol............................................................................................................ 982
7.5.8.3.1
7.6
Page
SDP Command..................................................................................................... 983
7.5.8.3.1.1
READ REGISTER..................................................................... 983
7.5.8.3.1.2
WRITE REGISTER................................................................... 984
7.5.8.3.1.3
WRITE_FILE............................................................................. 985
7.5.8.3.1.4
ERROR_STATUS......................................................................986
7.5.8.3.1.5
DCD WRITE.............................................................................. 987
7.5.8.3.1.6
JUMP ADDRESS.......................................................................988
7.5.9
Recovery Devices............................................................................................................................................ 989
7.5.10
HAB Re-Authentication at Low Power Standby Exit..................................................................................... 989
7.5.11
Running Secondary Core................................................................................................................................. 990
7.5.12
Appendix.......................................................................................................................................................... 990
7.5.12.1
IOMUX and GPIO Pad Settings for BOOT Interfaces................................................................990
7.5.12.2
Fuse RCON Mapping...................................................................................................................990
7.5.12.3
PLL Configuration after BOOT................................................................................................... 991
7.5.12.4
Basic CCM Settings..................................................................................................................... 991
Fusemap.......................................................................................................................................................................... 992
7.6.1
Boot Fusemap.................................................................................................................................................. 992
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Section number
Title
Page
7.6.2
Fusemap Descriptions Table............................................................................................................................ 992
7.6.3
Lock Fusemap.................................................................................................................................................. 999
Chapter 8
Analog and Misc Control
8.1
12-bit Digital-to-Analog Converter (DAC).................................................................................................................... 1001
8.1.1
Introduction...................................................................................................................................................... 1001
8.1.2
Features............................................................................................................................................................ 1001
8.1.3
Block diagram.................................................................................................................................................. 1002
8.1.4
Memory map/register definition...................................................................................................................... 1003
8.1.5
8.1.4.1
DAC Data Register (DACx_DATn)............................................................................................ 1004
8.1.4.2
DAC Status and Control Register (DACx_STATCTRL)............................................................ 1005
Functional description......................................................................................................................................1007
8.1.5.1
8.2
DAC data buffer operation...........................................................................................................1007
8.1.5.1.1
DAC data buffer interrupts................................................................................... 1008
8.1.5.1.2
Modes of DAC data buffer operation................................................................... 1008
8.1.5.2
DMA operation............................................................................................................................ 1009
8.1.5.3
Resets........................................................................................................................................... 1009
8.1.5.4
Low-Power mode operation.........................................................................................................1009
Analog-to-Digital Converter (ADC)...............................................................................................................................1009
8.2.1
Overview.......................................................................................................................................................... 1009
8.2.1.1
Features........................................................................................................................................ 1010
8.2.1.2
ADC I/F block diagram................................................................................................................1010
8.2.1.3
ADC block diagram..................................................................................................................... 1011
8.2.1.4
ADC module interface................................................................................................................. 1012
8.2.1.5
Modes of Operation..................................................................................................................... 1013
8.2.2
External Signals............................................................................................................................................... 1013
8.2.3
Functional Description..................................................................................................................................... 1013
8.2.3.1
Clock Select and Divide Control................................................................................................. 1014
8.2.3.2
Voltage Reference Selection ....................................................................................................... 1015
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Section number
8.2.3.3
Title
Conversion Control...................................................................................................................... 1015
8.2.3.3.1
Initiating Conversions...........................................................................................1016
8.2.3.3.2
Completing Conversions.......................................................................................1016
8.2.3.3.3
Aborting Conversions........................................................................................... 1017
8.2.3.3.4
Power Control....................................................................................................... 1017
8.2.3.3.5
Sample Time and Total Conversion Time............................................................ 1018
8.2.3.3.6
Conversion Time Examples..................................................................................1020
8.2.3.3.7
8.2.4
8.2.3.3.6.1
Typical conversion time configuration.......................................1020
8.2.3.3.6.2
Long conversion time configuration.......................................... 1020
8.2.3.3.6.3
Short conversion time configuration.......................................... 1021
Hardware Average Function................................................................................. 1022
8.2.3.4
Automatic Compare Function...................................................................................................... 1022
8.2.3.5
Calibration Function.................................................................................................................... 1023
8.2.3.6
User Defined Offset Function ..................................................................................................... 1024
8.2.3.7
Temperature Sensor..................................................................................................................... 1025
8.2.3.8
MCU Wait Mode Operation........................................................................................................ 1025
8.2.3.9
MCU Stop Mode Operation......................................................................................................... 1026
8.2.3.9.1
Stop Mode With ADACK Disabled..................................................................... 1026
8.2.3.9.2
Stop Mode With ADACK Enabled.......................................................................1026
Initialization Information................................................................................................................................. 1027
8.2.4.1
8.2.5
Page
ADC Module Initialization Example........................................................................................... 1027
8.2.4.1.1
Initialization Sequence..........................................................................................1027
8.2.4.1.2
Pseudo-Code Example.......................................................................................... 1027
Application Information...................................................................................................................................1029
8.2.5.1
Sources of Error........................................................................................................................... 1029
8.2.5.1.1
Sampling Error......................................................................................................1029
8.2.5.1.2
Pin Leakage Error................................................................................................. 1030
8.2.5.1.3
Noise-Induced Errors............................................................................................ 1030
8.2.5.1.4
Code Width and Quantization Error..................................................................... 1031
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Section number
8.2.6
8.3
Title
8.2.5.1.5
Linearity Errors.....................................................................................................1031
8.2.5.1.6
Code Jitter, Non-Monotonicity, and Missing Codes............................................ 1032
Memory map and register definition................................................................................................................1033
8.2.6.1
Control register (ADCx_HC0)..................................................................................................... 1034
8.2.6.2
Status register (ADCx_HS).......................................................................................................... 1036
8.2.6.3
Data result register (ADCx_R0)...................................................................................................1037
8.2.6.4
Configuration register (ADCx_CFG)...........................................................................................1038
8.2.6.5
General control register (ADCx_GC).......................................................................................... 1040
8.2.6.6
General status register (ADCx_GS)............................................................................................. 1042
8.2.6.7
Compare value register (ADCx_CV)........................................................................................... 1043
8.2.6.8
Offset correction value register (ADCx_OFS).............................................................................1044
8.2.6.9
Calibration value register (ADCx_CAL)..................................................................................... 1045
8.2.6.10
Pin control register (ADCx_PCTL)............................................................................................. 1045
Miscellaneous Control Module (MCM)......................................................................................................................... 1049
8.3.1
Introduction...................................................................................................................................................... 1049
8.3.1.1
8.3.2
8.3.3
Features........................................................................................................................................ 1049
Memory map/register descriptions...................................................................................................................1049
8.3.2.1
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................1050
8.3.2.2
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................ 1050
8.3.2.3
Control Register (MCM_CR)...................................................................................................... 1051
8.3.2.4
Interrupt Status and Control Register (MCM_ISCR).................................................................. 1052
8.3.2.5
Fault address register (MCM_FADR)......................................................................................... 1055
8.3.2.6
Fault attributes register (MCM_FATR)....................................................................................... 1056
8.3.2.7
Fault data register (MCM_FDR)..................................................................................................1058
Functional description......................................................................................................................................1059
8.3.3.1
Interrupts...................................................................................................................................... 1059
8.3.3.1.1
8.4
Page
Determining source of the interrupt......................................................................1059
Miscellaneous System Control Module (MSCM).......................................................................................................... 1059
8.4.1
Overview.......................................................................................................................................................... 1059
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Section number
Title
Page
8.4.2
Chip Configuration and Boot........................................................................................................................... 1060
8.4.3
MSCM Memory Map/Register Definition.......................................................................................................1061
8.4.3.1
CPU Configuration Memory Map and Registers.........................................................................1061
8.4.3.2
MSCM Interrupt Router Memory Map and Register Descriptions............................................. 1061
8.4.3.3
MSCM Access Control and TrustZone Security (ACTZS) Memory Map and Registers........... 1062
8.4.3.4
Processor X Type Register (MSCM_CPxTYPE)........................................................................ 1072
8.4.3.5
Processor X Number Register (MSCM_CPxNUM).................................................................... 1073
8.4.3.6
Processor X Master Register (MSCM_CPxMASTER)............................................................... 1073
8.4.3.7
Processor X Count Register (MSCM_CPxCOUNT)...................................................................1075
8.4.3.8
Processor X Configuration 0 Register (MSCM_CPxCFG0)....................................................... 1076
8.4.3.9
Processor X Configuration 1 Register (MSCM_CPxCFG1)....................................................... 1077
8.4.3.10
Processor X Configuration 2 Register (MSCM_CPxCFG2)....................................................... 1078
8.4.3.11
Processor X Configuration 3 Register (MSCM_CPxCFG3)....................................................... 1080
8.4.3.12
Processor 0 Type Register (MSCM_CP0TYPE)......................................................................... 1083
8.4.3.13
Processor 0 Number Register (MSCM_CP0NUM).....................................................................1084
8.4.3.14
Processor 0 Master Register (MSCM_CP0MASTER)................................................................ 1085
8.4.3.15
Processor 0 Count Register (MSCM_CP0COUNT)....................................................................1086
8.4.3.16
Processor 0 Configuration 0 Register (MSCM_CP0CFG).......................................................... 1087
8.4.3.17
Processor 0 Configuration 1 Register (MSCM_CP0CFG1)........................................................ 1088
8.4.3.18
Processor 0 Configuration 2 Register (MSCM_CP0CFG2)........................................................ 1089
8.4.3.19
Processor 0 Configuration 3 Register (MSCM_CP0CFG3)........................................................ 1091
8.4.3.20
Processor 1 Type Register (MSCM_CP1TYPE)......................................................................... 1094
8.4.3.21
Processor 1 Number Register (MSCM_CP1NUM).....................................................................1095
8.4.3.22
Processor 1 Master Register (MSCM_CP1MASTER)................................................................ 1096
8.4.3.23
Processor 1 Count Register (MSCM_CP1COUNT)....................................................................1097
8.4.3.24
Processor 1 Configuration 0 Register (MSCM_CP1CFG).......................................................... 1098
8.4.3.25
Processor 1 Configuration 1 Register (MSCM_CP1CFG1)........................................................ 1099
8.4.3.26
Processor 1 Configuration 2 Register (MSCM_CP1CFG2)........................................................ 1100
8.4.3.27
Processor 1 Configuration 3 Register (MSCM_CP1CFG3)........................................................ 1102
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Section number
Title
Page
8.4.3.28
Interrupt Router CP0 Interrupt Register (MSCM_IRCP0IR)...................................................... 1105
8.4.3.29
Interrupt Router CP1 Interrupt Register (MSCM_IRCP1IR)...................................................... 1107
8.4.3.30
Interrupt Router CPU Generate Interrupt Register (MSCM_IRCPGIR).....................................1109
8.4.3.31
Interrupt Router Shared Peripheral Routing Control Register n (MSCM_IRSPRCn)................ 1110
8.4.3.32
ACTZS TrustZone Enable Register (MSCM_TZENR).............................................................. 1111
8.4.3.33
ACTZS TrustZone Interrupt Register (MSCM_TZIR)............................................................... 1114
8.4.3.34
ACTZS CSLn Interrupt Enable Register (MSCM_CSLIER)......................................................1116
8.4.3.35
ACTZS CSLn Interrupt Register (MSCM_CSLIR).................................................................... 1119
8.4.3.36
ACTZS CSLn Interrupt Overrun Register (MSCM_CSOVR).................................................... 1121
8.4.3.37
ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)..................................... 1124
8.4.3.38
ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)................................................. 1126
8.4.3.39
ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn).............................................. 1127
Chapter 9
ARM Platform and Debug
9.1
Peripheral Bridge (AIPS-Lite)........................................................................................................................................ 1129
9.1.1
Introduction...................................................................................................................................................... 1129
9.1.1.1
Features........................................................................................................................................ 1129
9.1.1.2
General operation......................................................................................................................... 1129
9.1.2
Memory map/register definition...................................................................................................................... 1130
9.1.3
Functional description......................................................................................................................................1130
9.1.3.1
9.2
Access support............................................................................................................................. 1130
Semaphores (SEMA4).................................................................................................................................................... 1131
9.2.1
Introduction ..................................................................................................................................................... 1131
9.2.1.1
Multi-Core Programming 101: Software Gates........................................................................... 1131
9.2.1.2
Overview...................................................................................................................................... 1133
9.2.1.3
Features........................................................................................................................................ 1134
9.2.1.4
Modes of Operation..................................................................................................................... 1135
9.2.2
External Signal Description............................................................................................................................. 1135
9.2.3
Memory map and register definition................................................................................................................1135
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NXP Semiconductors
Section number
9.2.4
9.3
Title
Page
9.2.3.1
Semaphores Gate 3 Register (SEMA4_Gate03).......................................................................... 1137
9.2.3.2
Semaphores Gate 2 Register (SEMA4_Gate02).......................................................................... 1138
9.2.3.3
Semaphores Gate 1 Register (SEMA4_Gate01).......................................................................... 1139
9.2.3.4
Semaphores Gate 0 Register (SEMA4_Gate00).......................................................................... 1140
9.2.3.5
Semaphores Gate 7 Register (SEMA4_Gate07).......................................................................... 1141
9.2.3.6
Semaphores Gate 6 Register (SEMA4_Gate06).......................................................................... 1142
9.2.3.7
Semaphores Gate 5 Register (SEMA4_Gate05).......................................................................... 1143
9.2.3.8
Semaphores Gate 4 Register (SEMA4_Gate04).......................................................................... 1144
9.2.3.9
Semaphores Gate 11 Register (SEMA4_Gate11)........................................................................ 1145
9.2.3.10
Semaphores Gate 10 Register (SEMA4_Gate10)........................................................................ 1146
9.2.3.11
Semaphores Gate 9 Register (SEMA4_Gate09).......................................................................... 1147
9.2.3.12
Semaphores Gate 8 Register (SEMA4_Gate08).......................................................................... 1148
9.2.3.13
Semaphores Gate 15 Register (SEMA4_Gate15)........................................................................ 1149
9.2.3.14
Semaphores Gate 14 Register (SEMA4_Gate14)........................................................................ 1150
9.2.3.15
Semaphores Gate 13 Register (SEMA4_Gate13)........................................................................ 1151
9.2.3.16
Semaphores Gate 12 Register (SEMA4_Gate12)........................................................................ 1152
9.2.3.17
Semaphores Processor n IRQ Notification Enable (SEMA4_CPnINE)...................................... 1153
9.2.3.18
Semaphores Processor n IRQ Notification (SEMA4_CPnNTF)................................................. 1155
9.2.3.19
Semaphores (Secure) Reset Gate n (SEMA4_RSTGT)...............................................................1156
9.2.3.20
Semaphores (Secure) Reset IRQ Notification (SEMA4_RSTNTF)............................................1158
Functional Description..................................................................................................................................... 1159
9.2.4.1
SEMA4_GATEn Operation......................................................................................................... 1159
9.2.4.2
SEMA4_CPnNTF Operation....................................................................................................... 1161
9.2.5
Initialization Information................................................................................................................................. 1164
9.2.6
Application Information...................................................................................................................................1164
On-Chip Memory Controller (OCMEM)........................................................................................................................1166
9.3.1
Overview.......................................................................................................................................................... 1166
9.3.2
Functional Description..................................................................................................................................... 1166
9.3.2.1
OCRAM Error Correcting Code (ECC).......................................................................................1167
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Section number
9.3.2.2
Title
9.3.2.1.1
ECC Checkbit / Syndrome Coding....................................................................... 1169
9.3.2.1.2
ECC and System Performance Implications.........................................................1173
OCRAM_gfx Pixel Conversion................................................................................................... 1173
9.3.2.2.1
9.3.2.3
9.3.3
9.4
Page
OCRAM_gfx Pixel Converter Functional Description.........................................1174
9.3.2.2.1.1
RGB565......................................................................................1174
9.3.2.2.1.2
ARGB1555................................................................................. 1175
9.3.2.2.1.3
ARGB4444................................................................................. 1175
9.3.2.2.1.4
ARGB8888 Conversions to 16-bit Pixel Data............................1175
Pixel Conversion and System Performance Implications............................................................ 1177
OCMEM Memory Map/Register Definition....................................................................................................1177
9.3.3.1
On-Chip Memory Descriptor Register (OCMEM_OCMDRn)................................................... 1178
9.3.3.2
On-Chip Memory ECC Control Register (OCMEM_OCMECR)............................................... 1182
9.3.3.3
On-Chip Memory ECC Interrupt Register (OCMEM_OCMEIR).............................................. 1184
9.3.3.4
On-Chip Memory ECC Error Generation Register (OCMEM_OCMEGR)................................1186
9.3.3.5
On-Chip Memory ECC Fault Address Register (OCMEM_OCMFAR).....................................1189
9.3.3.6
On-Chip Memory ECC Fault Attribute Register (OCMEM_OCMFTR).................................... 1190
9.3.3.7
On-Chip Memory ECC Fault Data Register (OCMEM_OCMFDR).......................................... 1191
Local Memory Controller (LMEM)................................................................................................................................1192
9.4.1
9.4.2
Introduction...................................................................................................................................................... 1192
9.4.1.1
Block Diagram............................................................................................................................. 1192
9.4.1.2
Cache features.............................................................................................................................. 1194
Memory Map and Registers............................................................................................................................. 1196
9.4.2.1
Cache control register (LMEM_PCCCR)....................................................................................1196
9.4.2.2
Cache line control register (LMEM_PCCLCR).......................................................................... 1198
9.4.2.3
Cache search address register (LMEM_PCCSAR)..................................................................... 1200
9.4.2.4
Cache read/write value register (LMEM_PCCCVR).................................................................. 1201
9.4.2.5
Cache control register (LMEM_PSCCR).................................................................................... 1202
9.4.2.6
Cache line control register (LMEM_PSCLCR)...........................................................................1203
9.4.2.7
Cache search address register (LMEM_PSCSAR)...................................................................... 1206
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NXP Semiconductors
Section number
9.4.2.8
9.4.3
9.4.3.2
9.6
Page
Cache read/write value register (LMEM_PSCCVR)...................................................................1207
Functional Description..................................................................................................................................... 1207
9.4.3.1
9.5
Title
LMEM Function.......................................................................................................................... 1207
9.4.3.1.1
Processor Code accesses....................................................................................... 1208
9.4.3.1.2
Processor System accesses....................................................................................1208
9.4.3.1.3
Backdoor port accesses......................................................................................... 1208
SRAM Function........................................................................................................................... 1208
9.4.3.2.1
SRAM Configuration............................................................................................1208
9.4.3.2.2
SRAM Arrays....................................................................................................... 1209
9.4.3.2.3
SRAM Accesses....................................................................................................1209
9.4.3.3
Cache Function............................................................................................................................ 1210
9.4.3.4
Cache Control.............................................................................................................................. 1211
9.4.3.4.1
Cache set commands.............................................................................................1211
9.4.3.4.2
Cache line commands........................................................................................... 1212
9.4.3.4.2.1
Executing a series of line commands using cache addresses..... 1213
9.4.3.4.2.2
Executing a series of line commands using physical addresses. 1213
9.4.3.4.2.3
Line command results.................................................................1214
System Bus Interconnect.................................................................................................................................................1215
9.5.1
Overview.......................................................................................................................................................... 1215
9.5.2
Features............................................................................................................................................................ 1217
9.5.3
NIC301 Physical Structure and Programming Model..................................................................................... 1218
9.5.3.1
NIC301 Physical Structure...........................................................................................................1218
9.5.3.2
NIC301 Programming Model...................................................................................................... 1221
9.5.3.3
NIC301 Bus Arbitration...............................................................................................................1225
AHB-TrustZone Address Space Controller (AHBTZASC)........................................................................................... 1226
9.6.1
Overview.......................................................................................................................................................... 1226
9.6.2
AHB-TZASC Programming Model Differences vs. (AXI) TZASC............................................................... 1226
9.6.3
AHB-TZASC Memory Map/Register Definition............................................................................................ 1227
9.6.3.1
Configuration Register (AHB-TZASC_CONFIG)...................................................................... 1229
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Section number
9.7
Title
Page
9.6.3.2
Action Register (AHB-TZASC_ACTION)................................................................................. 1230
9.6.3.3
Lockdown Range Register (AHB-TZASC_LOCKDOWN_RANGE)........................................1230
9.6.3.4
Lockdown Select Register (AHB-TZASC_LOCKDOWN_SELECT)....................................... 1231
9.6.3.5
Interrupt Status Register (AHB-TZASC_INT_STATUS)...........................................................1231
9.6.3.6
Interrupt Clear Register (AHB-TZASC_INT_CLEAR)..............................................................1232
9.6.3.7
Fail Address Low Register (AHB-TZASC_FAIL_ADDRESS_LOW)...................................... 1232
9.6.3.8
Fail Address High Register (AHB-TZASC_FAIL_ADDRESS_HIGH).....................................1233
9.6.3.9
Fail Control Register (AHB-TZASC_FAIL_CONTROL).......................................................... 1233
9.6.3.10
Fail ID Register (AHB-TZASC_FAIL_ID).................................................................................1234
9.6.3.11
Speculation Control Register (AHB-TZASC_SPECULATION_CONTROL)........................... 1234
9.6.3.12
Security Inversion Enable Register (AHB-TZASC_SECURITY_INVERSION_EN)............... 1235
9.6.3.13
Region Setup Low n Register (AHB-TZASC_REGION_SETUP_LOW_n)..............................1235
9.6.3.14
Region Setup High n Register (AHB-TZASC_REGION_SETUP_HIGH_n)............................ 1236
9.6.3.15
Region Attributes n Register (AHB-TZASC_REGION_ATTRIBUTES_n).............................. 1236
Watchdog Timer (WDOG)............................................................................................................................................. 1237
9.7.1
Overview.......................................................................................................................................................... 1237
9.7.1.1
Features........................................................................................................................................ 1238
9.7.2
External signals................................................................................................................................................ 1239
9.7.3
Clocks...............................................................................................................................................................1239
9.7.4
Watchdog mechanism and system integration.................................................................................................1239
9.7.5
Functional description......................................................................................................................................1240
9.7.5.1
Timeout event.............................................................................................................................. 1240
9.7.5.1.1
Servicing WDOG to reload the counter................................................................1241
9.7.5.2
Interrupt event ............................................................................................................................. 1241
9.7.5.3
Power-down counter event...........................................................................................................1241
9.7.5.4
Low power modes........................................................................................................................ 1242
9.7.5.5
9.7.5.4.1
STOP and DOZE mode........................................................................................ 1242
9.7.5.4.2
WAIT mode.......................................................................................................... 1242
Debug mode................................................................................................................................. 1242
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Section number
9.7.5.6
9.8
Title
Page
Operations.................................................................................................................................... 1243
9.7.5.6.1
Watchdog reset generation....................................................................................1243
9.7.5.6.2
WDOG_B generation............................................................................................1243
9.7.5.7
Reset.............................................................................................................................................1245
9.7.5.8
Interrupt........................................................................................................................................1246
9.7.5.9
Flow Diagrams............................................................................................................................. 1246
9.7.6
Initialization..................................................................................................................................................... 1248
9.7.7
WDOG Memory Map/Register Definition...................................................................................................... 1249
9.7.7.1
Watchdog Control Register (WDOG_WCR).............................................................................. 1249
9.7.7.2
Watchdog Service Register (WDOG_WSR)............................................................................... 1251
9.7.7.3
Watchdog Reset Status Register (WDOG_WRSR).....................................................................1252
9.7.7.4
Watchdog Interrupt Control Register (WDOG_WICR).............................................................. 1253
9.7.7.5
Watchdog Miscellaneous Control Register (WDOG_WMCR)...................................................1254
External Watchdog Monitor (EWM).............................................................................................................................. 1254
9.8.1
Introduction...................................................................................................................................................... 1254
9.8.1.1
Features........................................................................................................................................ 1255
9.8.1.2
Modes of Operation..................................................................................................................... 1255
9.8.1.3
9.8.1.2.1
Stop Mode.............................................................................................................1255
9.8.1.2.2
Wait Mode............................................................................................................ 1256
9.8.1.2.3
Debug Mode..........................................................................................................1256
Block Diagram............................................................................................................................. 1256
9.8.2
EWM Signal Descriptions............................................................................................................................... 1257
9.8.3
Memory Map/Register Definition....................................................................................................................1258
9.8.3.1
Control Register (EWM_CTRL)................................................................................................. 1258
9.8.3.2
Service Register (EWM_SERV)..................................................................................................1259
9.8.3.3
Compare Low Register (EWM_CMPL)...................................................................................... 1259
9.8.3.4
Compare High Register (EWM_CMPH)..................................................................................... 1260
9.8.3.5
Clock Control Register (EWM_CLKCTRL)............................................................................... 1260
9.8.3.6
Clock Prescaler Register (EWM_CLKPRESCALER)................................................................ 1261
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Section number
9.8.4
9.9
Title
Page
Functional Description..................................................................................................................................... 1262
9.8.4.1
The EWM_out Signal.................................................................................................................. 1262
9.8.4.2
The EWM_in Signal.................................................................................................................... 1263
9.8.4.3
EWM Counter.............................................................................................................................. 1263
9.8.4.4
EWM Compare Registers............................................................................................................ 1263
9.8.4.5
EWM Refresh Mechanism...........................................................................................................1264
9.8.4.6
EWM Interrupt............................................................................................................................. 1264
9.8.4.7
Selecting the EWM counter clock............................................................................................... 1264
9.8.4.8
Counter clock prescaler................................................................................................................1265
Watchdog Configuration (WCON).................................................................................................................................1265
9.9.1
Watchdog Scheme............................................................................................................................................1265
9.9.2
Watchdog Connectivity....................................................................................................................................1266
9.9.3
WDOG clocking options..................................................................................................................................1267
9.9.4
WDOG Debug requirement............................................................................................................................. 1268
9.10 Wakeup Unit (WKPU)....................................................................................................................................................1268
9.10.1
Introduction...................................................................................................................................................... 1268
9.10.2
Features............................................................................................................................................................ 1269
9.10.3
External signal description...............................................................................................................................1270
9.10.4
WKPU memory map and register definition................................................................................................... 1270
9.10.5
9.10.4.1
NMI Status Flag Register (WKPU_NSR)................................................................................... 1271
9.10.4.2
NMI Configuration Register (WKPU_NCR).............................................................................. 1272
9.10.4.3
Wakeup/Interrupt Status Flag Register (WKPU_WISR).............................................................1274
9.10.4.4
Interrupt Request Enable Register (WKPU_IRER).....................................................................1275
9.10.4.5
Wakeup Request Enable Register (WKPU_WRER)................................................................... 1275
9.10.4.6
Wakeup/Interrupt Rising-Edge Event Enable Register (WKPU_WIREER)...............................1276
9.10.4.7
Wakeup/Interrupt Falling-Edge Event Enable Register (WKPU_WIFEER).............................. 1276
9.10.4.8
Wakeup/Interrupt Filter Enable Register (WKPU_WIFER)....................................................... 1277
9.10.4.9
Wakeup/Interrupt Pullup Enable Register (WKPU_WIPUER)...................................................1277
Functional description......................................................................................................................................1278
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Section number
9.10.5.1
Title
Non-maskable interrupts.............................................................................................................. 1278
9.10.5.1.1
9.10.5.2
External interrupt management.............................................................................1281
On-chip wakeups..........................................................................................................................1282
9.10.5.3.1
9.10.6
NMI management................................................................................................. 1279
External wakeups/interrupts.........................................................................................................1280
9.10.5.2.1
9.10.5.3
Page
On-chip wakeup management...............................................................................1282
Initialization Information................................................................................................................................. 1282
9.10.6.1
Glitch Filter and Pad Configuration.............................................................................................1282
9.10.6.2
Non-Maskable Interrupts............................................................................................................. 1282
9.10.6.3
Reset Request............................................................................................................................... 1283
9.11 System Debug................................................................................................................................................................. 1284
9.11.1
Overview.......................................................................................................................................................... 1284
9.11.2
System Level Debug Architecture................................................................................................................... 1285
9.11.3
Test and Debug Access Port Connectivity.......................................................................................................1287
9.11.4
JTAG to SWD cJTAG switching sequence..................................................................................................... 1288
9.11.4.1
JTAG-to-SWD change sequence................................................................................................. 1288
9.11.4.2
JTAG-to-cJTAG change sequence...............................................................................................1288
9.11.4.3
System JTAG Controller (JTAGC)..............................................................................................1289
9.11.4.4
Debug Access Port (DAP) TAP...................................................................................................1290
9.11.4.4.1
ROM Table........................................................................................................... 1291
9.11.4.4.1.1
CM4 ROM table......................................................................... 1292
9.11.4.4.1.2
CA5 ROM table..........................................................................1292
9.11.4.4.1.3
DAP ROM table......................................................................... 1293
9.11.5
Debug Port Pin Descriptions............................................................................................................................1294
9.11.6
Secure JTAG Controller (SJC)........................................................................................................................ 1295
9.11.6.1
9.11.7
Challenge Response Access Sequence........................................................................................ 1295
Debug Status and Control Registers................................................................................................................ 1296
9.11.7.1
Miscellaneous Debug Module (MDM) AP Control Register...................................................... 1296
9.11.7.2
Miscellaneous Debug Module (MDM) AP Status Register.........................................................1298
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Section number
Title
Page
9.11.8
Debug Resets....................................................................................................................................................1299
9.11.9
Trace Architecture............................................................................................................................................1299
9.11.9.1
Data Watchpoint and Trace (DWT).............................................................................................1301
9.11.9.2
Flash Patch and Breakpoints (FPB) (CM4 only)......................................................................... 1302
9.11.9.3
Instrumentation Trace Macrocell (ITM)...................................................................................... 1302
9.11.9.4
Embedded Trace Macrocell (ETM)............................................................................................. 1303
9.11.9.5
CoreSight Embedded Trace Buffer (ETB)...................................................................................1303
9.11.9.6
Trace Port Interface Unit (TPIU)................................................................................................. 1304
9.11.9.7
Serial Wire Output....................................................................................................................... 1304
9.11.9.8
Performance Monitoring Unit (for CA5 Only)............................................................................ 1305
9.11.9.9
Embedded Cross Trigger............................................................................................................. 1305
9.11.9.9.1
CM4 CTI Triggers................................................................................................ 1306
9.11.9.9.2
CA5 CTI Triggers................................................................................................. 1307
9.11.10 Low Power Debug........................................................................................................................................... 1308
9.11.11 Secured JTAG.................................................................................................................................................. 1309
9.11.11.1
Additional Authentication Interface.............................................................................................1309
9.11.12 Configuration sequence....................................................................................................................................1310
9.11.12.1
Halt mode..................................................................................................................................... 1310
9.11.12.2
Monitor mode...............................................................................................................................1311
9.12 System JTAG Controller (SJC)...................................................................................................................................... 1311
9.12.1
Introduction...................................................................................................................................................... 1311
9.12.2
External signal description...............................................................................................................................1311
9.12.3
9.12.4
9.12.2.1
External signal overview..............................................................................................................1311
9.12.2.2
TAP controller..............................................................................................................................1312
9.12.2.3
Accessing ExtraDebug register.................................................................................................... 1314
JTAG Instruction Register (SJIR)....................................................................................................................1315
9.12.3.1
BYPASS instruction.................................................................................................................... 1316
9.12.3.2
ENABLE_ExtraDebug instruction.............................................................................................. 1316
Security............................................................................................................................................................ 1317
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Section number
9.12.4.1
Title
JTAG Security Modes..................................................................................................................1317
9.12.4.1.1
Mode 1: no debug—maximum security............................................................... 1317
9.12.4.1.2
Mode 2: secure JTAG–high security.................................................................... 1318
9.12.4.1.2.1
9.12.4.1.3
9.12.4.2
9.12.5
Page
Challenge/response mechanism..................................................1318
Mode 3: JTAG enabled—low security................................................................. 1319
Software enabled JTAG............................................................................................................... 1319
Programmable registers....................................................................................................................................1320
9.12.5.1
Security Status Register (SJC_SSR)............................................................................................ 1321
Chapter 10
External Memory and Mass Storage
10.1 LPDDR2/DDR3 SDRAM Memory Controller (DDRMC)............................................................................................ 1323
10.1.1
Introduction...................................................................................................................................................... 1323
10.1.2
Block diagram.................................................................................................................................................. 1324
10.1.3
Modes of Operation......................................................................................................................................... 1324
10.1.3.1
10.1.4
Signal Description............................................................................................................................................1325
10.1.4.1
10.1.5
Low Power Modes....................................................................................................................... 1324
Detailed Signal Descriptions........................................................................................................1325
Memory map and register description............................................................................................................. 1332
10.1.5.1
Control Register 0 (DDRMC_CR00).......................................................................................... 1341
10.1.5.2
Control Register 1 (DDRMC_CR01).......................................................................................... 1342
10.1.5.3
Control Register 2 (DDRMC_CR02).......................................................................................... 1343
10.1.5.4
Control Register 3 (DDRMC_CR03).......................................................................................... 1344
10.1.5.5
Control Register 4 (DDRMC_CR04).......................................................................................... 1344
10.1.5.6
Control Register 5 (DDRMC_CR05).......................................................................................... 1345
10.1.5.7
Control Register 6 (DDRMC_CR06).......................................................................................... 1345
10.1.5.8
Control Register 7 (DDRMC_CR07).......................................................................................... 1346
10.1.5.9
Control Register 8 (DDRMC_CR08).......................................................................................... 1346
10.1.5.10
Control Register 9 (DDRMC_CR09).......................................................................................... 1347
10.1.5.11
Control Register 10 (DDRMC_CR10)........................................................................................ 1347
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Section number
Title
Page
10.1.5.12
Control Register 11 (DDRMC_CR11)........................................................................................ 1348
10.1.5.13
Control Register 12 (DDRMC_CR12)........................................................................................ 1348
10.1.5.14
Control Register 13 (DDRMC_CR13)........................................................................................ 1350
10.1.5.15
Control Register 14 (DDRMC_CR14)........................................................................................ 1351
10.1.5.16
Control Register 15 (DDRMC_CR15)........................................................................................ 1352
10.1.5.17
Control Register 16 (DDRMC_CR16)........................................................................................ 1353
10.1.5.18
Control Register 17 (DDRMC_CR17)........................................................................................ 1353
10.1.5.19
Control Register 18 (DDRMC_CR18)........................................................................................ 1354
10.1.5.20
Control Register 19 (DDRMC_CR19)........................................................................................ 1355
10.1.5.21
Control Register 20 (DDRMC_CR20)........................................................................................ 1356
10.1.5.22
Control Register 21 (DDRMC_CR21)........................................................................................ 1357
10.1.5.23
Control Register 22 (DDRMC_CR22)........................................................................................ 1358
10.1.5.24
Control Register 23 (DDRMC_CR23)........................................................................................ 1359
10.1.5.25
Control Register 24 (DDRMC_CR24)........................................................................................ 1360
10.1.5.26
Control Register 25 (DDRMC_CR25)........................................................................................ 1362
10.1.5.27
Control Register 26 (DDRMC_CR26)........................................................................................ 1363
10.1.5.28
Control Register 27 (DDRMC_CR27)........................................................................................ 1364
10.1.5.29
Control Register 28 (DDRMC_CR28)........................................................................................ 1364
10.1.5.30
Control Register 29 (DDRMC_CR29)........................................................................................ 1365
10.1.5.31
Control Register 30 (DDRMC_CR30)........................................................................................ 1366
10.1.5.32
Control Register 31 (DDRMC_CR31)........................................................................................ 1366
10.1.5.33
Control Register 32 (DDRMC_CR32)........................................................................................ 1367
10.1.5.34
Control Register 33 (DDRMC_CR33)........................................................................................ 1368
10.1.5.35
Control Register 34 (DDRMC_CR34)........................................................................................ 1369
10.1.5.36
Control Register 35 (DDRMC_CR35)........................................................................................ 1370
10.1.5.37
Control Register 36 (DDRMC_CR36)........................................................................................ 1373
10.1.5.38
Control Register 37 (DDRMC_CR37)........................................................................................ 1375
10.1.5.39
Control Register 38 (DDRMC_CR38)........................................................................................ 1376
10.1.5.40
Control Register 39 (DDRMC_CR39)........................................................................................ 1377
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Section number
Title
Page
10.1.5.41
Control Register 40 (DDRMC_CR40)........................................................................................ 1378
10.1.5.42
Control Register 41 (DDRMC_CR41)........................................................................................ 1378
10.1.5.43
Control Register 42 (DDRMC_CR42)........................................................................................ 1379
10.1.5.44
Control Register 43 (DDRMC_CR43)........................................................................................ 1379
10.1.5.45
Control Register 44 (DDRMC_CR44)........................................................................................ 1380
10.1.5.46
Control Register 45 (DDRMC_CR45)........................................................................................ 1380
10.1.5.47
Control Register 46 (DDRMC_CR46)........................................................................................ 1381
10.1.5.48
Control Register 47 (DDRMC_CR47)........................................................................................ 1382
10.1.5.49
Control Register 48 (DDRMC_CR48)........................................................................................ 1383
10.1.5.50
Control Register 49 (DDRMC_CR49)........................................................................................ 1384
10.1.5.51
Control Register 50 (DDRMC_CR50)........................................................................................ 1384
10.1.5.52
Control Register 51 (DDRMC_CR51)........................................................................................ 1385
10.1.5.53
Control Register 52 (DDRMC_CR52)........................................................................................ 1385
10.1.5.54
Control Register 53 (DDRMC_CR53)........................................................................................ 1386
10.1.5.55
Control Register 54 (DDRMC_CR54)........................................................................................ 1387
10.1.5.56
Control Register 55 (DDRMC_CR55)........................................................................................ 1387
10.1.5.57
Control Register 56 (DDRMC_CR56)........................................................................................ 1388
10.1.5.58
Control Register 57 (DDRMC_CR57)........................................................................................ 1388
10.1.5.59
Control Register 58 (DDRMC_CR58)........................................................................................ 1389
10.1.5.60
Control Register 59 (DDRMC_CR59)........................................................................................ 1390
10.1.5.61
Control Register 60 (DDRMC_CR60)........................................................................................ 1391
10.1.5.62
Control Register 61 (DDRMC_CR61)........................................................................................ 1391
10.1.5.63
Control Register 62 (DDRMC_CR62)........................................................................................ 1392
10.1.5.64
Control Register 63 (DDRMC_CR63)........................................................................................ 1392
10.1.5.65
Control Register 64 (DDRMC_CR64)........................................................................................ 1393
10.1.5.66
Control Register 65 (DDRMC_CR65)........................................................................................ 1393
10.1.5.67
Control Register 66 (DDRMC_CR66)........................................................................................ 1394
10.1.5.68
Control Register 67 (DDRMC_CR67)........................................................................................ 1394
10.1.5.69
Control Register 68 (DDRMC_CR68)........................................................................................ 1395
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Section number
Title
Page
10.1.5.70
Control Register 69 (DDRMC_CR69)........................................................................................ 1395
10.1.5.71
Control Register 70 (DDRMC_CR70)........................................................................................ 1396
10.1.5.72
Control Register 71 (DDRMC_CR71)........................................................................................ 1397
10.1.5.73
Control Register 72 (DDRMC_CR72)........................................................................................ 1398
10.1.5.74
Control Register 73 (DDRMC_CR73)........................................................................................ 1399
10.1.5.75
Control Register 74 (DDRMC_CR74)........................................................................................ 1400
10.1.5.76
Control Register 75 (DDRMC_CR75)........................................................................................ 1402
10.1.5.77
Control Register 76 (DDRMC_CR76)........................................................................................ 1403
10.1.5.78
Control Register 77 (DDRMC_CR77)........................................................................................ 1405
10.1.5.79
Control Register 78 (DDRMC_CR78)........................................................................................ 1407
10.1.5.80
Control Register 79 (DDRMC_CR79)........................................................................................ 1409
10.1.5.81
Control Register 80 (DDRMC_CR80)........................................................................................ 1410
10.1.5.82
Control Register 81 (DDRMC_CR81)........................................................................................ 1412
10.1.5.83
Control Register 82 (DDRMC_CR82)........................................................................................ 1412
10.1.5.84
Control Register 83 (DDRMC_CR83)........................................................................................ 1413
10.1.5.85
Control Register 84 (DDRMC_CR84)........................................................................................ 1413
10.1.5.86
Control Register 85 (DDRMC_CR85)........................................................................................ 1414
10.1.5.87
Control Register 86 (DDRMC_CR86)........................................................................................ 1414
10.1.5.88
Control Register 87 (DDRMC_CR87)........................................................................................ 1415
10.1.5.89
Control Register 88 (DDRMC_CR88)........................................................................................ 1416
10.1.5.90
Control Register 89 (DDRMC_CR89)........................................................................................ 1416
10.1.5.91
Control Register 90 (DDRMC_CR90)........................................................................................ 1417
10.1.5.92
Control Register 91 (DDRMC_CR91)........................................................................................ 1417
10.1.5.93
Control Register 92 (DDRMC_CR92)........................................................................................ 1418
10.1.5.94
Control Register 93 (DDRMC_CR93)........................................................................................ 1420
10.1.5.95
Control Register 94 (DDRMC_CR94)........................................................................................ 1422
10.1.5.96
Control Register 95 (DDRMC_CR95)........................................................................................ 1424
10.1.5.97
Control Register 96 (DDRMC_CR96)........................................................................................ 1426
10.1.5.98
Control Register 97 (DDRMC_CR97)........................................................................................ 1428
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Section number
10.1.5.99
Title
Page
Control Register 98 (DDRMC_CR98)........................................................................................ 1429
10.1.5.100 Control Register 99 (DDRMC_CR99)........................................................................................ 1430
10.1.5.101 Control Register 100 (DDRMC_CR100).................................................................................... 1430
10.1.5.102 Control Register 101 (DDRMC_CR101).................................................................................... 1431
10.1.5.103 Control Register 102 (DDRMC_CR102).................................................................................... 1433
10.1.5.104 Control Register 103 (DDRMC_CR103).................................................................................... 1434
10.1.5.105 Control Register 104 (DDRMC_CR104).................................................................................... 1435
10.1.5.106 Control Register 105 (DDRMC_CR105).................................................................................... 1436
10.1.5.107 Control Register 106 (DDRMC_CR106).................................................................................... 1437
10.1.5.108 Control Register 107 (DDRMC_CR107).................................................................................... 1437
10.1.5.109 Control Register 108 (DDRMC_CR108).................................................................................... 1438
10.1.5.110 Control Register 109 (DDRMC_CR109).................................................................................... 1439
10.1.5.111 Control Register 110 (DDRMC_CR110).................................................................................... 1440
10.1.5.112 Control Register 111 (DDRMC_CR111).................................................................................... 1440
10.1.5.113 Control Register 112 (DDRMC_CR112).................................................................................... 1441
10.1.5.114 Control Register 113 (DDRMC_CR113).................................................................................... 1441
10.1.5.115 Control Register 114 (DDRMC_CR114).................................................................................... 1441
10.1.5.116 Control Register 115 (DDRMC_CR115).................................................................................... 1442
10.1.5.117 Control Register 116 (DDRMC_CR116).................................................................................... 1442
10.1.5.118 Control Register 117 (DDRMC_CR117).................................................................................... 1443
10.1.5.119 Control Register 118 (DDRMC_CR118).................................................................................... 1444
10.1.5.120 Control Register 119 (DDRMC_CR119).................................................................................... 1445
10.1.5.121 Control Register 120 (DDRMC_CR120).................................................................................... 1447
10.1.5.122 Control Register 121 (DDRMC_CR121).................................................................................... 1449
10.1.5.123 Control Register 122 (DDRMC_CR122).................................................................................... 1450
10.1.5.124 Control Register 123 (DDRMC_CR123).................................................................................... 1451
10.1.5.125 Control Register 124 (DDRMC_CR124).................................................................................... 1453
10.1.5.126 Control Register 125 (DDRMC_CR125).................................................................................... 1454
10.1.5.127 Control Register 126 (DDRMC_CR126).................................................................................... 1455
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Title
Page
10.1.5.128 Control Register 127 (DDRMC_CR127).................................................................................... 1457
10.1.5.129 Control Register 128 (DDRMC_CR128).................................................................................... 1457
10.1.5.130 Control Register 129 (DDRMC_CR129).................................................................................... 1458
10.1.5.131 Control Register 130 (DDRMC_CR130).................................................................................... 1458
10.1.5.132 Control Register 131 (DDRMC_CR131).................................................................................... 1458
10.1.5.133 Control Register 132 (DDRMC_CR132).................................................................................... 1459
10.1.5.134 Control Register 133 (DDRMC_CR133).................................................................................... 1460
10.1.5.135 Control Register 134 (DDRMC_CR134).................................................................................... 1460
10.1.5.136 Control Register 135 (DDRMC_CR135).................................................................................... 1460
10.1.5.137 Control Register 136 (DDRMC_CR136).................................................................................... 1461
10.1.5.138 Control Register 137 (DDRMC_CR137).................................................................................... 1461
10.1.5.139 Control Register 138 (DDRMC_CR138).................................................................................... 1462
10.1.5.140 Control Register 139 (DDRMC_CR139).................................................................................... 1463
10.1.5.141 Control Register 140 (DDRMC_CR140).................................................................................... 1464
10.1.5.142 Control Register 141 (DDRMC_CR141).................................................................................... 1465
10.1.5.143 Control Register 142 (DDRMC_CR142).................................................................................... 1465
10.1.5.144 Control Register 143 (DDRMC_CR143).................................................................................... 1466
10.1.5.145 Control Register 144 (DDRMC_CR144).................................................................................... 1467
10.1.5.146 Control Register 145 (DDRMC_CR145).................................................................................... 1468
10.1.5.147 Control Register 146 (DDRMC_CR146).................................................................................... 1469
10.1.5.148 Control Register 147 (DDRMC_CR147).................................................................................... 1469
10.1.5.149 Control Register 148 (DDRMC_CR148).................................................................................... 1470
10.1.5.150 Control Register 149 (DDRMC_CR149).................................................................................... 1471
10.1.5.151 Control Register 150 (DDRMC_CR150).................................................................................... 1472
10.1.5.152 Control Register 151 (DDRMC_CR151).................................................................................... 1473
10.1.5.153 Control Register 152 (DDRMC_CR152).................................................................................... 1474
10.1.5.154 Control Register 153 (DDRMC_CR153).................................................................................... 1475
10.1.5.155 Control Register 154 (DDRMC_CR154).................................................................................... 1476
10.1.5.156 Control Register 155 (DDRMC_CR155).................................................................................... 1478
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Section number
Title
Page
10.1.5.157 Control Register 156 (DDRMC_CR156).................................................................................... 1480
10.1.5.158 Control Register 157 (DDRMC_CR157).................................................................................... 1482
10.1.5.159 Control Register 158 (DDRMC_CR158).................................................................................... 1483
10.1.5.160 Control Register 159 (DDRMC_CR159).................................................................................... 1484
10.1.5.161 Control Register 160 (DDRMC_CR160).................................................................................... 1484
10.1.5.162 Control Register 161 (DDRMC_CR161).................................................................................... 1485
10.1.5.163 PHY Register 00 (DDRMC_PHY00).......................................................................................... 1486
10.1.5.164 PHY Register 01 (DDRMC_PHY01).......................................................................................... 1487
10.1.5.165 PHY Register 02 (DDRMC_PHY02).......................................................................................... 1488
10.1.5.166 PHY Register 03 (DDRMC_PHY03).......................................................................................... 1491
10.1.5.167 PHY Register 04 (DDRMC_PHY04).......................................................................................... 1493
10.1.5.168 PHY Register 10 (DDRMC_PHY10).......................................................................................... 1494
10.1.5.169 PHY Register 11 (DDRMC_PHY11).......................................................................................... 1496
10.1.5.170 PHY Register 12 (DDRMC_PHY12).......................................................................................... 1497
10.1.5.171 PHY Register 13 (DDRMC_PHY13).......................................................................................... 1498
10.1.5.172 PHY Register 16 (DDRMC_PHY16).......................................................................................... 1498
10.1.5.173 PHY Register 17 (DDRMC_PHY17).......................................................................................... 1499
10.1.5.174 PHY Register 18 (DDRMC_PHY18).......................................................................................... 1501
10.1.5.175 PHY Register 19 (DDRMC_PHY19).......................................................................................... 1503
10.1.5.176 PHY Register 20 (DDRMC_PHY20).......................................................................................... 1505
10.1.5.177 PHY Register 26 (DDRMC_PHY26).......................................................................................... 1507
10.1.5.178 PHY Register 27 (DDRMC_PHY27).......................................................................................... 1509
10.1.5.179 PHY Register 28 (DDRMC_PHY28).......................................................................................... 1510
10.1.5.180 PHY Register 29 (DDRMC_PHY29).......................................................................................... 1511
10.1.5.181 PHY Register 32 (DDRMC_PHY32).......................................................................................... 1511
10.1.5.182 PHY Register 33 (DDRMC_PHY33).......................................................................................... 1512
10.1.5.183 PHY Register 34 (DDRMC_PHY34).......................................................................................... 1513
10.1.5.184 PHY Register 35 (DDRMC_PHY35).......................................................................................... 1515
10.1.5.185 PHY Register 36 (DDRMC_PHY36).......................................................................................... 1517
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Section number
Title
Page
10.1.5.186 PHY Register 42 (DDRMC_PHY42).......................................................................................... 1518
10.1.5.187 PHY Register 43 (DDRMC_PHY43).......................................................................................... 1520
10.1.5.188 PHY Register 44 (DDRMC_PHY44).......................................................................................... 1521
10.1.5.189 PHY Register 45 (DDRMC_PHY45).......................................................................................... 1522
10.1.5.190 PHY Register 49 (DDRMC_PHY49).......................................................................................... 1522
10.1.5.191 PHY Register 50 (DDRMC_PHY50).......................................................................................... 1523
10.1.5.192 PHY Register 52 (DDRMC_PHY52).......................................................................................... 1524
10.1.6
Functional Description..................................................................................................................................... 1526
10.1.6.1
10.1.6.2
Address Mapping......................................................................................................................... 1526
10.1.6.1.1
DDR SDRAM Address Mapping Options............................................................1526
10.1.6.1.2
Maximum Address Space..................................................................................... 1527
10.1.6.1.3
Memory Mapping to Address Space.....................................................................1527
AXI Interface............................................................................................................................... 1527
10.1.6.2.1
Architecture Overview..........................................................................................1527
10.1.6.2.2
AXI Interfaces.......................................................................................................1528
10.1.6.2.3
Restrictions on the AXI Bus................................................................................. 1529
10.1.6.2.4
Internal Command Handling.................................................................................1529
10.1.6.2.5
Controller configuration........................................................................................1531
10.1.6.2.6
Port Clocking........................................................................................................ 1532
10.1.6.2.7
AXI Port FIFOs.....................................................................................................1533
10.1.6.2.8
Command FIFO.................................................................................................... 1534
10.1.6.2.8.1
10.1.6.3
In-Port Arbitration...................................................................... 1534
10.1.6.2.9
Read FIFO.............................................................................................................1536
10.1.6.2.10
Write FIFO............................................................................................................1537
10.1.6.2.11
Response Interface................................................................................................ 1537
10.1.6.2.12
Bufferable, Coherent Bufferable and Non-Bufferable Response Types.............. 1538
10.1.6.2.13
Exclusive Access Option...................................................................................... 1538
Multi-Port Arbiter........................................................................................................................ 1539
10.1.6.3.1
Arbitration Overview............................................................................................ 1539
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Section number
10.1.6.4
Title
10.1.6.3.2
Understanding Round-Robin Operation............................................................... 1539
10.1.6.3.3
Understanding Port Priority.................................................................................. 1540
10.1.6.3.4
Understanding Relative Priority........................................................................... 1541
10.1.6.3.5
Understanding Port Ordering................................................................................1542
10.1.6.3.6
Weighted Round-Robin Arbitration Summary.....................................................1543
10.1.6.3.7
Priority Relaxing...................................................................................................1545
10.1.6.3.8
Port Pairing........................................................................................................... 1548
10.1.6.3.9
Error Conditions................................................................................................... 1549
10.1.6.3.10
Programmable Options for Weighted Round Robin Arbitration..........................1550
Core Command Queue with Placement Logic.............................................................................1551
10.1.6.4.1
Rules of the Placement Algorithm........................................................................1551
10.1.6.4.1.1
Source ID Collision...............................................................................................1552
10.1.6.4.3
Priority.................................................................................................................. 1552
10.1.6.4.4
Bank Splitting....................................................................................................... 1553
10.1.6.4.5
Write-to-Read Splitting.........................................................................................1553
10.1.6.4.6
Read/Write Grouping............................................................................................1553
10.1.6.4.8
10.1.6.4.6.1
Bank Conflicts and Read/Write Grouping................................. 1553
10.1.6.4.6.2
Chip Select Grouping with Read/Write Grouping..................... 1555
10.1.6.4.6.3
Page Grouping with Read/Write Grouping................................ 1555
Command Execution Order After Placement....................................................... 1555
10.1.6.4.7.1
Command Selection Logic......................................................... 1556
10.1.6.4.7.2
High-Priority Command Swapping............................................1556
10.1.6.4.7.3
Command Aging........................................................................ 1557
ACT Request Control........................................................................................... 1558
ECC Options................................................................................................................................ 1558
10.1.6.5.1
10.1.6.6
Address Collision/Data Coherency Violation............................ 1551
10.1.6.4.2
10.1.6.4.7
10.1.6.5
Page
Initialization of memory when using ECC........................................................... 1560
Low Power Operation.................................................................................................................. 1560
10.1.6.6.1
Automatic Interface.............................................................................................. 1563
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Section number
Title
Page
10.1.6.6.1.1
Automatic Entry......................................................................... 1564
10.1.6.6.1.2
Automatic Exit............................................................................1564
10.1.6.6.2
Refresh Masking................................................................................................... 1565
10.1.6.6.3
LPDDR2 SDRAM Memories............................................................................... 1565
10.1.6.6.3.1
Enabling Mobile Usage.............................................................. 1565
10.1.6.6.3.2
Partial Array Self-Refresh.......................................................... 1566
10.1.6.7
Out-of-Range Address Checking................................................................................................. 1566
10.1.6.8
Command to Command Timing.................................................................................................. 1568
10.1.6.9
Writing Mode Registers............................................................................................................... 1569
10.1.6.9.1
WRMD (write mode register) bit fields................................................................1569
10.1.6.9.2
MRW Module and Arbiter....................................................................................1570
10.1.6.9.3
Programming Errors..............................................................................................1571
10.1.6.9.4
Mode Register Storage in the Memory Controller............................................... 1572
10.1.6.10
Refresh Per Command Timing.................................................................................................... 1572
10.1.6.11
LPDDR2 Memories DQS............................................................................................................ 1573
10.1.6.12
DRAM Refresh............................................................................................................................ 1573
10.1.6.12.1
Programming of the TREF field........................................................................... 1574
10.1.6.12.2
Programming of the tref_INT bits........................................................................ 1574
10.1.6.13
Half Data path option................................................................................................................... 1575
10.1.6.14
ZQ pad calibration....................................................................................................................... 1575
10.1.6.15
DDR PHY.................................................................................................................................... 1576
10.1.6.15.1
High Level Block Diagram...................................................................................1576
10.1.6.15.2
DFI........................................................................................................................ 1577
10.1.6.15.3
Command and Address Timing for DDR3........................................................... 1577
10.1.6.15.4
Command and Address Timing for LPDDR2...................................................... 1579
10.1.6.15.5
Data Slice Overview............................................................................................. 1579
10.1.6.15.6
Read Data Capture................................................................................................ 1580
10.1.6.15.7
Synchronize Read Data From delayed_dqs To PHY_CLK domain.....................1581
10.1.6.15.8
Write Data Path.....................................................................................................1583
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Section number
Title
10.1.6.15.9
Page
Digital DLL and the Delay-Line...........................................................................1585
10.1.6.15.10 Configure the "output enable" of I/O Control.......................................................1587
10.1.6.15.11 Low Frequency Options........................................................................................1588
10.1.6.15.11.1 Operating between 150 MHz and 300 MHz...............................1589
10.1.6.15.11.2 Operating below 150 MHz......................................................... 1589
10.1.6.16
Levelling Operations through Software....................................................................................... 1590
10.1.6.16.1
Detailed Software Leveling Procedure ................................................................ 1591
10.1.6.16.2
Software Write Leveling.......................................................................................1593
10.1.6.16.3
10.1.6.16.4
10.1.7
10.1.6.16.2.1
Software Write Leveling in MC Evaluation Mode.................... 1593
10.1.6.16.2.2
Software Write Leveling Software Considerations....................1596
Software Gate Training.........................................................................................1596
10.1.6.16.3.1
Software Gate Training in MC Evaluation Mode...................... 1597
10.1.6.16.3.2
Software Gate Training Software Considerations......................1599
Software Read Leveling........................................................................................1599
10.1.6.16.4.1
Software Read Leveling in MC Evaluation Mode..................... 1600
10.1.6.16.4.2
Software Read Leveling Software Considerations.....................1602
Initialization and Application Information...................................................................................................... 1602
10.2 Quad Serial Peripheral Interface (QuadSPI)...................................................................................................................1603
10.2.1
10.2.2
Introduction...................................................................................................................................................... 1603
10.2.1.1
Features........................................................................................................................................ 1603
10.2.1.2
Block Diagram............................................................................................................................. 1604
10.2.1.3
QuadSPI Modes of Operation...................................................................................................... 1605
10.2.1.3.1
Normal Mode........................................................................................................ 1605
10.2.1.3.2
Module Disable Mode...........................................................................................1606
10.2.1.3.3
Stop Mode.............................................................................................................1606
10.2.1.4
Acronyms and Abbreviations.......................................................................................................1606
10.2.1.5
Glossary for QuadSPI module..................................................................................................... 1606
External Signal Description............................................................................................................................. 1608
10.2.2.1
Driving External Signals.............................................................................................................. 1609
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Section number
10.2.3
Title
Page
Memory Map and Register Definition............................................................................................................. 1611
10.2.3.1
Register Write Access.................................................................................................................. 1611
10.2.3.2
Peripheral Bus Register Descriptions.......................................................................................... 1612
10.2.3.2.1
Module Configuration Register (QuadSPIx_MCR)..............................................1624
10.2.3.2.2
IP Configuration Register (QuadSPIx_IPCR)...................................................... 1626
10.2.3.2.3
Flash Configuration Register (QuadSPIx_FLSHCR)........................................... 1627
10.2.3.2.4
Buffer0 Configuration Register (QuadSPIx_BUF0CR)....................................... 1627
10.2.3.2.5
Buffer1 Configuration Register (QuadSPIx_BUF1CR)....................................... 1628
10.2.3.2.6
Buffer2 Configuration Register (QuadSPIx_BUF2CR)....................................... 1629
10.2.3.2.7
Buffer3 Configuration Register (QuadSPIx_BUF3CR)....................................... 1630
10.2.3.2.8
Buffer Generic Configuration Register (QuadSPIx_BFGENCR)........................ 1631
10.2.3.2.9
SOC Configuration Register (QuadSPIx_SOCCR).............................................. 1632
10.2.3.2.10
Buffer0 Top Index Register (QuadSPIx_BUF0IND)........................................... 1632
10.2.3.2.11
Buffer1 Top Index Register (QuadSPIx_BUF1IND)........................................... 1633
10.2.3.2.12
Buffer2 Top Index Register (QuadSPIx_BUF2IND)........................................... 1634
10.2.3.2.13
Serial Flash Address Register (QuadSPIx_SFAR)............................................... 1634
10.2.3.2.14
Sampling Register (QuadSPIx_SMPR)................................................................ 1635
10.2.3.2.15
RX Buffer Status Register (QuadSPIx_RBSR).................................................... 1636
10.2.3.2.16
RX Buffer Control Register (QuadSPIx_RBCT)..................................................1637
10.2.3.2.17
TX Buffer Status Register (QuadSPIx_TBSR).....................................................1638
10.2.3.2.18
TX Buffer Data Register (QuadSPIx_TBDR)...................................................... 1638
10.2.3.2.19
Status Register (QuadSPIx_SR)............................................................................1640
10.2.3.2.20
Flag Register (QuadSPIx_FR).............................................................................. 1643
10.2.3.2.21
Interrupt and DMA Request Select and Enable Register (QuadSPIx_RSER)......1645
10.2.3.2.22
Sequence Suspend Status Register (QuadSPIx_SPNDST)...................................1649
10.2.3.2.23
Sequence Pointer Clear Register (QuadSPIx_SPTRCLR)................................... 1651
10.2.3.2.24
Serial Flash A1 Top Address (QuadSPIx_SFA1AD)........................................... 1652
10.2.3.2.25
Serial Flash A2 Top Address (QuadSPIx_SFA2AD)........................................... 1652
10.2.3.2.26
Serial Flash B1Top Address (QuadSPIx_SFB1AD).............................................1653
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Section number
Title
Page
10.2.3.2.27
Serial Flash B2Top Address (QuadSPIx_SFB2AD).............................................1653
10.2.3.2.28
RX Buffer Data Register (QuadSPIx_RBDRn)....................................................1654
10.2.3.2.29
LUT Key Register (QuadSPIx_LUTKEY)...........................................................1654
10.2.3.2.30
LUT Lock Configuration Register (QuadSPIx_LCKCR).....................................1655
10.2.3.2.31
Look-up Table register (QuadSPIx_LUTn).......................................................... 1656
10.2.3.3
Serial Flash Address Assignment................................................................................................ 1657
10.2.3.4
AMBA Bus Register Memory Map............................................................................................. 1658
10.2.3.5
AHB Bus Register Memory Map Descriptions........................................................................... 1659
10.2.3.5.1
AHB Bus Access Considerations..........................................................................1659
10.2.3.5.2
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A............1660
10.2.3.5.3
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B............ 1660
10.2.3.5.4
Parallel Flash Mode.............................................................................................. 1661
10.2.3.5.5
AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)................................. 1662
10.2.3.5.5.1
AHB RX Data Buffer register (ARDBn)................................... 1663
10.2.4
Interrupt Signals............................................................................................................................................... 1665
10.2.5
Functional Description..................................................................................................................................... 1666
10.2.5.1
Serial Flash Access Schemes....................................................................................................... 1666
10.2.5.2
Modes of Operation..................................................................................................................... 1667
10.2.5.3
Normal Mode............................................................................................................................... 1667
10.2.5.3.1
Programmable Sequence Engine.......................................................................... 1667
10.2.5.3.2
Flexible AHB buffers............................................................................................1669
10.2.5.3.3
Suspend-Abort Mechanism...................................................................................1671
10.2.5.3.4
Look-up Table.......................................................................................................1672
10.2.5.3.5
Issuing SFM Commands.......................................................................................1673
10.2.5.3.6
Flash Programming...............................................................................................1674
10.2.5.3.7
Flash Read.............................................................................................................1675
10.2.5.3.8
Byte Ordering of Serial Flash Read Data............................................................. 1679
10.2.5.3.9
Normal Mode Interrupt and DMA Requests........................................................ 1682
10.2.5.3.10
TX Buffer Operation.............................................................................................1684
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Section number
Title
10.2.5.3.11
10.2.6
Address scheme.................................................................................................... 1685
Initialization/Application Information............................................................................................................. 1685
10.2.6.1
Power Up and Reset..................................................................................................................... 1686
10.2.6.2
Available Status/Flag Information............................................................................................... 1686
10.2.6.3
10.2.6.2.1
IP Commands........................................................................................................1686
10.2.6.2.2
AHB Commands...................................................................................................1686
10.2.6.2.3
Overview of Error Flags....................................................................................... 1687
10.2.6.2.4
IP Bus and AHB Access Command Collisions.................................................... 1688
Exclusive Access to Serial Flash for AHB Commands............................................................... 1688
10.2.6.3.1
RX Buffer Read via QSPI_ARDB Registers........................................................1689
10.2.6.3.2
RX Buffer Read via QSPI_RBDR Registers........................................................ 1689
10.2.6.4
Command Arbitration ................................................................................................................. 1690
10.2.6.5
Flash Device Selection.................................................................................................................1690
10.2.6.6
DMA Usage................................................................................................................................. 1691
10.2.6.6.1
DMA Usage in Normal Mode...............................................................................1691
10.2.6.6.1.1
10.2.6.7
10.2.7
Page
Bandwidth considerations.......................................................... 1691
Parallel mode................................................................................................................................1693
Serial Flash Devices.........................................................................................................................................1696
10.2.7.1
Example Sequences......................................................................................................................1696
10.2.7.1.1
Fast Read Sequence (Macronix/Numonyx/Spansion/Winbond).......................... 1696
10.2.7.1.2
Fast Dual I/O DT Read Sequence (Macronix)......................................................1696
10.2.7.1.3
Fast Read Quad Output (Winbond)...................................................................... 1697
10.2.7.1.4
4 x I/O Read Enhance Performance Mode (XIP) (Macronix).............................. 1697
10.2.7.1.5
Dual Command Page Program (Numonyx)..........................................................1698
10.2.7.1.6
Sector Erase (Macronix/Spansion/Numonyx)...................................................... 1698
10.2.7.1.7
Read Status Register (Macronix/Spansion/Numonyx/Winbond)......................... 1698
10.2.7.2
Dual Die Flashes.......................................................................................................................... 1698
10.2.7.3
Boot initialization sequence......................................................................................................... 1699
10.2.7.4
Serial Flash Clock Frequency Limitations...................................................................................1700
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Section number
10.2.8
Title
Page
Sampling of Serial Flash Input Data................................................................................................................ 1700
10.2.8.1
Basic Description......................................................................................................................... 1701
10.2.8.2
SDR mode.................................................................................................................................... 1702
10.2.8.3
10.2.8.4
10.2.8.2.1
Internal sampling.................................................................................................. 1702
10.2.8.2.2
DQS sampling method..........................................................................................1703
DDR Mode................................................................................................................................... 1703
10.2.8.3.1
Internal sampling (4x sampling method).............................................................. 1704
10.2.8.3.2
DQS sampling method..........................................................................................1704
Data Strobe (DQS) sampling method.......................................................................................... 1705
10.2.8.4.1
Basic Description.................................................................................................. 1705
10.3 NAND Flash Controller (NFC)...................................................................................................................................... 1706
10.3.1
Introduction...................................................................................................................................................... 1706
10.3.1.1
Block Diagram............................................................................................................................. 1707
10.3.1.2
Features........................................................................................................................................ 1708
10.3.2
External Signal Description............................................................................................................................. 1709
10.3.3
Memory Map/Register Definition....................................................................................................................1709
10.3.3.1
Flash command 1 (NFC_CMD1).................................................................................................1710
10.3.3.2
Flash command 2 (NFC_CMD2).................................................................................................1711
10.3.3.3
Column address (NFC_CAR)...................................................................................................... 1712
10.3.3.4
Row address (NFC_RAR)........................................................................................................... 1713
10.3.3.5
Flash command repeat (NFC_RPT).............................................................................................1714
10.3.3.6
Row address increment (NFC_RAI)............................................................................................1714
10.3.3.7
Flash status 1 (NFC_SR1)............................................................................................................1715
10.3.3.8
Flash status 2 (NFC_SR2)............................................................................................................1715
10.3.3.9
DMA channel 1 address (NFC_DMA_CH1)...............................................................................1716
10.3.3.10
DMA configuration (NFC_DMACFG)....................................................................................... 1716
10.3.3.11
Cach swap (NFC_SWAP)............................................................................................................1717
10.3.3.12
Sector size (NFC_SECSZ)...........................................................................................................1718
10.3.3.13
Flash configuration (NFC_CFG)................................................................................................. 1719
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Section number
10.3.4
Title
Page
10.3.3.14
DMA channel 2 address (NFC_DMA_CH2)...............................................................................1721
10.3.3.15
Interrupt status (NFC_ISR).......................................................................................................... 1721
Functional Description..................................................................................................................................... 1723
10.3.4.1
NFC Buffer Memory Space......................................................................................................... 1724
10.3.4.2
Error Corrector Status.................................................................................................................. 1725
10.3.4.3
NFC Basic Commands.................................................................................................................1726
10.3.4.3.1
Page Read..............................................................................................................1726
10.3.4.3.2
Page Program........................................................................................................ 1728
10.3.4.3.3
Block Erase........................................................................................................... 1730
10.3.4.3.4
Read ID................................................................................................................. 1731
10.3.4.3.5
Reset......................................................................................................................1732
10.3.4.4
NAND Flash Boot........................................................................................................................1732
10.3.4.5
Fast Flash Configuration for EDO............................................................................................... 1735
10.3.4.6
Organization of the Data in the NAND Flash..............................................................................1736
10.3.4.7
Flash Command Code Description.............................................................................................. 1739
10.3.4.8
Interrupts...................................................................................................................................... 1740
10.4 Secured Digital Host Controller (SDHC)....................................................................................................................... 1741
10.4.1
Introduction...................................................................................................................................................... 1741
10.4.2
Overview.......................................................................................................................................................... 1741
10.4.2.1
Supported types of cards.............................................................................................................. 1741
10.4.2.2
SDHC block diagram................................................................................................................... 1742
10.4.2.3
Features........................................................................................................................................ 1743
10.4.2.4
Modes and operations.................................................................................................................. 1744
10.4.3
SDHC signal descriptions................................................................................................................................ 1745
10.4.4
Memory map and register definition................................................................................................................1746
10.4.4.1
DMA System Address register (SDHCx_DSADDR).................................................................. 1748
10.4.4.2
Block Attributes register (SDHCx_BLKATTR)..........................................................................1749
10.4.4.3
Command Argument register (SDHCx_CMDARG)................................................................... 1750
10.4.4.4
Transfer Type register (SDHCx_XFERTYP).............................................................................. 1750
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Section number
10.4.5
Title
Page
10.4.4.5
Command Response 0 (SDHCx_CMDRSP0)............................................................................. 1755
10.4.4.6
Command Response 1 (SDHCx_CMDRSP1)............................................................................. 1755
10.4.4.7
Command Response 2 (SDHCx_CMDRSP2)............................................................................. 1755
10.4.4.8
Command Response 3 (SDHCx_CMDRSP3)............................................................................. 1756
10.4.4.9
Buffer Data Port register (SDHCx_DATPORT)......................................................................... 1757
10.4.4.10
Present State register (SDHCx_PRSSTAT).................................................................................1757
10.4.4.11
Protocol Control register (SDHCx_PROCTL)............................................................................ 1763
10.4.4.12
System Control register (SDHCx_SYSCTL)...............................................................................1766
10.4.4.13
Interrupt Status register (SDHCx_IRQSTAT)............................................................................. 1770
10.4.4.14
Interrupt Status Enable register (SDHCx_IRQSTATEN)........................................................... 1775
10.4.4.15
Interrupt Signal Enable register (SDHCx_IRQSIGEN)...............................................................1778
10.4.4.16
Auto CMD12 Error Status Register (SDHCx_AC12ERR)..........................................................1780
10.4.4.17
Host Controller Capabilities (SDHCx_HTCAPBLT)..................................................................1783
10.4.4.18
Watermark Level Register (SDHCx_WML)............................................................................... 1785
10.4.4.19
Force Event register (SDHCx_FEVT)......................................................................................... 1786
10.4.4.20
DLL (Delay Line) Control register (SDHCx_DLLCTRL).......................................................... 1788
10.4.4.21
DLL Status Register (SDHCx_DLLSTS).................................................................................... 1790
10.4.4.22
Vendor Specific register (SDHCx_VENDOR)............................................................................1791
10.4.4.23
MMC Boot register (SDHCx_MMCBOOT)............................................................................... 1792
10.4.4.24
Host Controller Version (SDHCx_HOSTVER).......................................................................... 1793
Functional description......................................................................................................................................1794
10.4.5.1
10.4.5.2
Data buffer................................................................................................................................... 1794
10.4.5.1.1
Write operation sequence......................................................................................1796
10.4.5.1.2
Read operation sequence.......................................................................................1797
10.4.5.1.3
Data buffer and block size.................................................................................... 1798
10.4.5.1.4
Dividing large data transfer.................................................................................. 1798
10.4.5.1.5
External DMA request.......................................................................................... 1799
DMA crossbar switch interface....................................................................................................1800
10.4.5.2.1
Internal DMA request........................................................................................... 1801
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Section number
10.4.5.3
Title
10.4.5.2.2
DMA burst length................................................................................................. 1801
10.4.5.2.3
Crossbar switch master interface.......................................................................... 1802
SD protocol unit........................................................................................................................... 1802
10.4.5.3.1
SD transceiver.......................................................................................................1803
10.4.5.3.2
SD clock & monitor.............................................................................................. 1803
10.4.5.3.3
Command agent.................................................................................................... 1803
10.4.5.3.4
Data agent............................................................................................................. 1804
10.4.5.4
Clock and reset manager.............................................................................................................. 1804
10.4.5.5
Clock generator............................................................................................................................ 1804
10.4.5.6
SDIO card interrupt......................................................................................................................1805
10.4.5.6.1
Interrupts in 1-bit mode........................................................................................ 1805
10.4.5.6.2
Interrupt in 4-bit mode.......................................................................................... 1805
10.4.5.6.3
Card interrupt handling......................................................................................... 1806
10.4.5.7
Card insertion and removal detection.......................................................................................... 1807
10.4.5.8
Power management and wakeup events.......................................................................................1807
10.4.5.8.1
10.4.5.9
10.4.6
Page
Setting wakeup events...........................................................................................1808
MMC fast boot............................................................................................................................. 1809
10.4.5.9.1
Boot operation.......................................................................................................1809
10.4.5.9.2
Alternative boot operation.................................................................................... 1810
Initialization/application of SDHC.................................................................................................................. 1811
10.4.6.1
Command send and response receive basic operation................................................................. 1811
10.4.6.2
Card Identification mode............................................................................................................. 1812
10.4.6.3
10.4.6.2.1
Card detect............................................................................................................ 1812
10.4.6.2.2
Reset......................................................................................................................1813
10.4.6.2.3
Voltage validation.................................................................................................1814
10.4.6.2.4
Card registry..........................................................................................................1815
Card access...................................................................................................................................1816
10.4.6.3.1
Block write............................................................................................................1817
10.4.6.3.1.1
Normal write...............................................................................1817
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Section number
Title
10.4.6.3.2
10.4.6.3.3
10.4.6.3.4
10.4.6.3.5
10.4.6.4
10.4.6.5
10.4.6.6
10.4.6.7
10.4.7
Page
10.4.6.3.1.2
DDR write.................................................................................. 1818
10.4.6.3.1.3
Write with pause.........................................................................1819
Block read............................................................................................................. 1820
10.4.6.3.2.1
Normal read................................................................................ 1820
10.4.6.3.2.2
DDR read....................................................................................1821
10.4.6.3.2.3
Read with pause..........................................................................1822
10.4.6.3.2.4
DLL (delay line) in read path..................................................... 1823
Suspend resume.................................................................................................... 1824
10.4.6.3.3.1
Suspend.......................................................................................1825
10.4.6.3.3.2
Resume....................................................................................... 1825
Transfer error........................................................................................................ 1826
10.4.6.3.4.1
CRC error................................................................................... 1826
10.4.6.3.4.2
Internal DMA error.....................................................................1826
10.4.6.3.4.3
Auto CMD12 error..................................................................... 1827
Card interrupt........................................................................................................ 1827
Switch function............................................................................................................................ 1827
10.4.6.4.1
Query, enabl,e and disable SDIO high-speed mode............................................. 1828
10.4.6.4.2
Query, enable, and disable SD high-speed mode................................................. 1828
10.4.6.4.3
Query, enable, and disable MMC high-speed mode.............................................1829
10.4.6.4.4
Set MMC bus width.............................................................................................. 1829
ADMA operation......................................................................................................................... 1829
10.4.6.5.1
ADMA1 operation................................................................................................ 1830
10.4.6.5.2
ADMA2 operation................................................................................................ 1830
Fast boot operation.......................................................................................................................1830
10.4.6.6.1
Normal fast boot flow........................................................................................... 1831
10.4.6.6.2
Alternative fast boot flow..................................................................................... 1832
10.4.6.6.3
Fast boot application case in DMA mode.............................................................1833
Commands for MMC/SD/SDIO.................................................................................................. 1835
Software restrictions........................................................................................................................................ 1840
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10.4.7.1
Initialization active.......................................................................................................................1840
10.4.7.2
Software polling procedure.......................................................................................................... 1841
10.4.7.3
Suspend operation........................................................................................................................ 1841
10.4.7.4
DMA address setting....................................................................................................................1841
10.4.7.5
Data port access........................................................................................................................... 1841
10.4.7.6
Change clock frequency...............................................................................................................1842
10.4.7.7
Multi-block read...........................................................................................................................1842
10.5 External Bus Interface (FlexBus)....................................................................................................................................1842
10.5.1
Introduction...................................................................................................................................................... 1842
10.5.1.1
Definition..................................................................................................................................... 1842
10.5.1.2
Features........................................................................................................................................ 1843
10.5.2
Signal descriptions........................................................................................................................................... 1843
10.5.3
Memory Map/Register Definition....................................................................................................................1845
10.5.4
10.5.3.1
Chip Select Address Register (FB_CSARn)................................................................................1847
10.5.3.2
Chip Select Mask Register (FB_CSMRn)................................................................................... 1847
10.5.3.3
Chip Select Control Register (FB_CSCRn).................................................................................1848
10.5.3.4
Chip Select port Multiplexing Control Register (FB_CSPMCR)................................................1852
Functional description......................................................................................................................................1853
10.5.4.1
Use cases...................................................................................................................................... 1853
10.5.4.2
Address comparison..................................................................................................................... 1854
10.5.4.3
Address driven on address bus.....................................................................................................1854
10.5.4.4
Connecting address/data lines...................................................................................................... 1854
10.5.4.5
Bit ordering.................................................................................................................................. 1854
10.5.4.6
Data transfer signals.....................................................................................................................1855
10.5.4.7
Signal transitions..........................................................................................................................1855
10.5.4.8
Data-byte alignment and physical connections............................................................................1855
10.5.4.9
Address/data bus multiplexing.....................................................................................................1857
10.5.4.9.1
FlexBus multiplexed operating modes for CSCRn[BLS]=0................................ 1857
10.5.4.9.2
FlexBus multiplexed operating modes for CSCRn[BLS]=1................................ 1857
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Page
10.5.4.10
Data transfer states....................................................................................................................... 1857
10.5.4.11
FlexBus Timing Examples...........................................................................................................1858
10.5.4.11.1
Basic Read Bus Cycle...........................................................................................1859
10.5.4.11.2
Basic Write Bus Cycle.......................................................................................... 1861
10.5.4.11.3
Bus Cycle Sizing...................................................................................................1862
10.5.4.11.3.1
Bus Cycle Sizing—Byte Transfer, 8-bit Device, No Wait
States...........................................................................................1862
10.5.4.11.3.2
Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait
States...........................................................................................1864
10.5.4.11.3.3
Bus Cycle Sizing—Longword Transfer, 32-bit Device, No
Wait States..................................................................................1866
10.5.4.11.4
10.5.4.12
Timing Variations................................................................................................. 1868
10.5.4.11.4.1
Wait States..................................................................................1868
10.5.4.11.4.2
Address Setup and Hold............................................................. 1872
Burst cycles.................................................................................................................................. 1877
10.5.4.12.1
Enabling and inhibiting burst................................................................................1877
10.5.4.12.2
Transfer size and port size translation.................................................................. 1878
10.5.4.12.3
32-bit-Read burst from 8-Bit port 2-1-1-1 (no wait states)...................................1878
10.5.4.12.4
32-bit-Write burst to 8-Bit port 3-1-1-1 (no wait states)...................................... 1879
10.5.4.12.5
32-bit-read burst-inhibited from 8-bit port (no wait states).................................. 1880
10.5.4.12.6
32-bit-write burst-inhibited to 8-bit port (no wait states)..................................... 1881
10.5.4.12.7
32-bit-read burst from 8-bit port 3-2-2-2 (one wait state).................................... 1882
10.5.4.12.8
32-bit-write burst to 8-bit port 3-2-2-2 (one wait state)........................................1883
10.5.4.12.9
32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold)...................... 1884
10.5.4.12.10 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and hold)......................... 1885
10.5.5
10.5.4.13
Extended Transfer Start/Address Latch Enable........................................................................... 1886
10.5.4.14
Bus errors..................................................................................................................................... 1887
Initialization/Application Information............................................................................................................. 1888
10.5.5.1
Initializing a chip-select............................................................................................................... 1888
10.5.5.2
Reconfiguring a chip-select......................................................................................................... 1888
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Page
10.6 Cyclic Redundancy Check (CRC).................................................................................................................................. 1889
10.6.1
10.6.2
10.6.3
Introduction...................................................................................................................................................... 1889
10.6.1.1
Features........................................................................................................................................ 1889
10.6.1.2
Block diagram.............................................................................................................................. 1889
10.6.1.3
Modes of operation...................................................................................................................... 1890
10.6.1.3.1
Run mode.............................................................................................................. 1890
10.6.1.3.2
Low-power modes (Wait or Stop)........................................................................ 1890
Memory map and register descriptions............................................................................................................ 1890
10.6.2.1
CRC Data register (CRC_DATA)............................................................................................... 1891
10.6.2.2
CRC Polynomial register (CRC_GPOLY).................................................................................. 1892
10.6.2.3
CRC Control register (CRC_CTRL)............................................................................................1893
10.6.2.1
CRC Data register: High 1 (CRC_DH1)......................................................................................1894
10.6.2.2
CRC Data register: High 0 (CRC_DH0)......................................................................................1895
10.6.2.3
CRC Data register: Low 1 (CRC_DL1).......................................................................................1895
10.6.2.4
CRC Data register: Low 0 (CRC_DL0).......................................................................................1896
10.6.2.5
CRC Polynomial Register: High 1 (CRC_PH1).......................................................................... 1897
10.6.2.6
CRC Polynomial Register: High 0 (CRC_PH0).......................................................................... 1897
10.6.2.7
CRC Polynomial Register: Low 1 (CRC_PL1)........................................................................... 1898
10.6.2.8
CRC Polynomial Register: Low 0 (CRC_PL0)........................................................................... 1898
10.6.2.9
CRC Control register (CRC_CTRL)............................................................................................1899
Functional description......................................................................................................................................1908
10.6.3.1
CRC initialization/reinitialization................................................................................................ 1908
10.6.3.2
CRC calculations..........................................................................................................................1909
10.6.3.3
10.6.3.2.1
16-bit CRC............................................................................................................ 1909
10.6.3.2.2
32-bit CRC............................................................................................................ 1909
CRC result complement............................................................................................................... 1910
Chapter 11
Connectivity
11.1 Universal Serial Bus Controller(USB)............................................................................................................................1911
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Title
Page
11.1.1
Overview.......................................................................................................................................................... 1911
11.1.2
Features............................................................................................................................................................ 1912
11.1.2.1
11.1.3
11.1.4
Ports............................................................................................................................................. 1913
11.1.2.1.1
Modes of Operation.............................................................................................. 1913
11.1.2.1.2
Normal Mode........................................................................................................ 1913
11.1.2.1.3
Low Power Mode..................................................................................................1914
Non-core Registers...........................................................................................................................................1914
11.1.3.1
USB Control Register (USBCx_CTRL)...................................................................................... 1916
11.1.3.2
UTMI PHY Control Register (USBCx_PHY)............................................................................. 1919
Core Registers.................................................................................................................................................. 1920
11.1.4.1
Identification register (USBx_ID)................................................................................................1924
11.1.4.2
Hardware General (USBx_HWGENERAL)................................................................................1925
11.1.4.3
Host Hardware Parameters (USBx_HWHOST).......................................................................... 1926
11.1.4.4
Device Hardware Parameters (USBx_HWDEVICE).................................................................. 1927
11.1.4.5
TX Buffer Hardware Parameters (USBx_HWTXBUF).............................................................. 1927
11.1.4.6
RX Buffer Hardware Parameters (USBx_HWRXBUF).............................................................. 1928
11.1.4.7
General Purpose Timer #0 Load (USBx_GPTIMER0LD).......................................................... 1928
11.1.4.8
General Purpose Timer #0 Controller (USBx_GPTIMER0CTRL)............................................. 1929
11.1.4.9
General Purpose Timer #1 Load (USBx_GPTIMER1LD).......................................................... 1930
11.1.4.10
General Purpose Timer #1 Controller (USBx_GPTIMER1CTRL)............................................. 1931
11.1.4.11
System Bus Config (USBx_SBUSCFG)......................................................................................1932
11.1.4.12
Capability Register Length (USBx_CAPLENGTH)................................................................... 1933
11.1.4.13
Host Controller Interface Version (USBx_HCIVERSION)........................................................ 1933
11.1.4.14
Host Controller Structural Parameters (USBx_HCSPARAMS)..................................................1934
11.1.4.15
Host Controller Capability Parameters (USBx_HCCPARAMS)................................................ 1935
11.1.4.16
Device Controller Interface Version (USBx_DCIVERSION).....................................................1936
11.1.4.17
Device Controller Capability Parameters (USBx_DCCPARAMS).............................................1937
11.1.4.18
USB Command Register (USBx_USBCMD)..............................................................................1937
11.1.4.19
USB Status Register (USBx_USBSTS)....................................................................................... 1942
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11.1.5
Title
Page
11.1.4.20
Interrupt Enable Register (USBx_USBINTR)............................................................................. 1946
11.1.4.21
USB Frame Index (USBx_FRINDEX)........................................................................................ 1948
11.1.4.22
Frame List Base Address (USBx_PERIODICLISTBASE)......................................................... 1949
11.1.4.23
Device Address (USBx_DEVICEADDR)................................................................................... 1950
11.1.4.24
Next Asynch. Address (USBx_ASYNCLISTADDR)................................................................. 1951
11.1.4.25
Endpoint List Address (USBx_ENDPTLISTADDR)..................................................................1951
11.1.4.26
Programmable Burst Size (USBx_BURSTSIZE)........................................................................ 1952
11.1.4.27
TX FIFO Fill Tuning (USBx_TXFILLTUNING)....................................................................... 1952
11.1.4.28
Endpoint NAK (USBx_ENDPTNAK).........................................................................................1954
11.1.4.29
Endpoint NAK Enable (USBx_ENDPTNAKEN)....................................................................... 1954
11.1.4.30
Port Status & Control (USBx_PORTSC1)...................................................................................1955
11.1.4.31
On-The-Go Status & control (USBx_OTGSC)........................................................................... 1961
11.1.4.32
USB Device Mode (USBx_USBMODE).................................................................................... 1964
11.1.4.33
Endpoint Setup Status (USBx_ENDPTSETUPSTAT)................................................................1965
11.1.4.34
Endpoint Initialization (USBx_ENDPTPRIME)......................................................................... 1966
11.1.4.35
Endpoint De-Initialize (USBx_ENDPTFLUSH)......................................................................... 1967
11.1.4.36
Endpoint Status (USBx_ENDPTSTAT)...................................................................................... 1967
11.1.4.37
Endpoint Complete (USBx_ENDPTCOMPLETE)..................................................................... 1968
11.1.4.38
Endpoint Control0 (USBx_ENDPTCTRL0)............................................................................... 1969
11.1.4.39
Endpoint Controln (USBx_ENDPTCTRLn)............................................................................... 1970
Functional description......................................................................................................................................1973
11.1.5.1
11.1.5.2
USB dual role device/host controller........................................................................................... 1973
11.1.5.1.1
Host mode............................................................................................................. 1973
11.1.5.1.2
Peripheral (Device) Mode.....................................................................................1973
USB Power Control Block........................................................................................................... 1974
11.1.5.2.1
Entering Low Power Suspend mode.....................................................................1974
11.1.5.2.2
Wake-up events.....................................................................................................1974
11.1.5.2.2.1
Host mode events....................................................................... 1974
11.1.5.2.2.2
Device mode events....................................................................1975
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11.1.5.3
11.1.6
Title
Page
Interrupts...................................................................................................................................... 1976
11.1.5.3.1
USB core interrupts...............................................................................................1976
11.1.5.3.2
USB wake-up interrupts........................................................................................1976
USB operation model.......................................................................................................................................1977
11.1.6.1
11.1.6.2
Register interface......................................................................................................................... 1977
11.1.6.1.1
Configuration, Control and Status Register Set....................................................1978
11.1.6.1.2
Identification registers.......................................................................................... 1979
Host data structures...................................................................................................................... 1979
11.1.6.2.1
Periodic Frame List...............................................................................................1980
11.1.6.2.2
Asynchronous List Queue Head Pointer...............................................................1982
11.1.6.2.3
Isochronous (High-Speed) Transfer Descriptor (iTD)..........................................1983
11.1.6.2.4
11.1.6.2.5
11.1.6.2.6
11.1.6.2.3.1
Next Link Pointer-Host Data Structures.....................................1984
11.1.6.2.3.2
iTD Transaction Status and Control List....................................1984
11.1.6.2.3.3
iTD Buffer Page Pointer List (Plus)........................................... 1986
Split Transaction Isochronous Transfer Descriptor (siTD).................................. 1987
11.1.6.2.4.1
Next Link Pointer....................................................................... 1988
11.1.6.2.4.2
siTD Endpoint Capabilities/Characteristics............................... 1988
11.1.6.2.4.3
siTD Transfer State.....................................................................1989
11.1.6.2.4.4
siTD Buffer Pointer List (plus)...................................................1990
11.1.6.2.4.5
siTD Back Link Pointer..............................................................1991
Queue Element Transfer Descriptor (qTD).......................................................... 1991
11.1.6.2.5.1
Next qTD Pointer....................................................................... 1992
11.1.6.2.5.2
Alternate Next qTD Pointer........................................................1993
11.1.6.2.5.3
qTD Token..................................................................................1993
11.1.6.2.5.4
qTD Buffer Page Pointer List.....................................................1996
Queue Head...........................................................................................................1996
11.1.6.2.6.1
Queue Head Horizontal Link Pointer......................................... 1997
11.1.6.2.6.2
Queue Head Endpoint Capabilities/Characteristics....................1998
11.1.6.2.6.3
Transfer Overlay-Queue Head................................................... 2000
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11.1.6.2.7
11.1.6.3
Page
Periodic Frame Span Traversal Node (FSTN) .....................................................2001
11.1.6.2.7.1
FSTN Normal Path Pointer ....................................................... 2002
11.1.6.2.7.2
FSTN Back Path Link Pointer ...................................................2002
Host Operational Model ..............................................................................................................2003
11.1.6.3.1
Host Controller Initialization ............................................................................... 2003
11.1.6.3.2
Port Routing and Control ..................................................................................... 2004
11.1.6.3.2.1
Port Routing Control through EHCI Configured (CF) Bit ........2006
11.1.6.3.2.2
Port Routing Control through PortOwner and Disconnect
Event ..........................................................................................2007
11.1.6.3.3
11.1.6.3.2.3
Example Port Routing State Machine ....................................... 2009
11.1.6.3.2.4
Port Power ................................................................................. 2010
11.1.6.3.2.5
Port Reporting Over-Current .....................................................2011
Suspend/Resume-Host Operational Model ..........................................................2012
11.1.6.3.3.1
11.1.6.3.4
Port Suspend/Resume ................................................................2012
Schedule Traversal Rules .....................................................................................2014
11.1.6.3.4.1
Example - Preserving Micro-Frame Integrity ........................... 2016
11.1.6.3.5
Periodic Schedule Frame Boundaries vs Bus Frame Boundaries ........................2019
11.1.6.3.6
Periodic Schedule .................................................................................................2022
11.1.6.3.7
Managing Isochronous Transfers Using iTDs ..................................................... 2023
11.1.6.3.8
11.1.6.3.9
11.1.6.3.7.1
Host Controller Operational Model for iTDs ............................ 2023
11.1.6.3.7.2
Software Operational Model for iTDs .......................................2025
Asynchronous Schedule .......................................................................................2028
11.1.6.3.8.1
Adding Queue Heads to Asynchronous Schedule......................2030
11.1.6.3.8.2
Removing Queue Heads from Asynchronous Schedule ........... 2030
11.1.6.3.8.3
Empty Asynchronous Schedule Detection ................................ 2033
11.1.6.3.8.4
Restarting Asynchronous Schedule Before EOF ...................... 2033
11.1.6.3.8.5
Asynchronous Schedule Traversal: Start Event......................... 2036
11.1.6.3.8.6
Reclamation Status Bit (USBSTS Register) ..............................2037
Operational Model for Nak Counter..................................................................... 2037
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11.1.6.3.9.1
11.1.6.3.10
11.1.6.4
Page
Nak Count Reload Control ........................................................ 2039
Managing Control/Bulk/Interrupt Transfers through Queue Heads..................... 2040
11.1.6.3.10.1
Fetch Queue Head ..................................................................... 2043
11.1.6.3.10.2
Advance Queue ......................................................................... 2043
11.1.6.3.10.3
Execute Transaction .................................................................. 2044
11.1.6.3.10.4
Write Back qTD ........................................................................ 2050
11.1.6.3.10.5
Follow Queue Head Horizontal Pointer .................................... 2051
11.1.6.3.10.6
Buffer Pointer List Use for Data Streaming with qTDs ............ 2051
11.1.6.3.10.7
Adding Interrupt Queue Heads to the Periodic Schedule ..........2054
11.1.6.3.10.8
Managing Transfer Complete Interrupts from Queue Heads .... 2054
11.1.6.3.11
Ping Control ......................................................................................................... 2055
11.1.6.3.12
Split Transactions .................................................................................................2056
11.1.6.3.12.1
Split Transactions for Asynchronous Transfers ........................ 2056
11.1.6.3.12.2
Split Transaction Interrupt .........................................................2059
11.1.6.3.12.3
Split Transaction Isochronous ................................................... 2074
11.1.6.3.13
Host Controller Pause .......................................................................................... 2090
11.1.6.3.14
Port Test Modes -Host Operational Model...........................................................2091
11.1.6.3.15
Interrupts-Host Operational Model.......................................................................2091
11.1.6.3.15.1
Transfer/Transaction Based Interrupts ...................................... 2093
11.1.6.3.15.2
Host Controller Event Interrupts ............................................... 2095
EHCI Deviation............................................................................................................................2097
11.1.6.4.1
Embedded Transaction Translator Function.........................................................2098
11.1.6.4.1.1
Capability Registers....................................................................2098
11.1.6.4.1.2
Operational Registers................................................................. 2098
11.1.6.4.1.3
Discovery-EHCI Deviation........................................................ 2099
11.1.6.4.1.4
Data Structures........................................................................... 2099
11.1.6.4.1.5
Operational Model......................................................................2100
11.1.6.4.2
Device Operation.................................................................................................. 2102
11.1.6.4.3
USB.USBMODE Register....................................................................................2102
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11.1.6.4.4
11.1.6.4.3.1
Non-Zero Fields the Register File.............................................. 2103
11.1.6.4.3.2
SOF Interrupt..............................................................................2103
Embedded Design Interface..................................................................................2103
11.1.6.4.4.1
11.1.6.4.5
11.1.6.5
Frame Adjust Register................................................................2103
Miscellaneous variations from EHCI....................................................................2103
11.1.6.4.5.1
Programmable Physical Interface Behaviour............................. 2104
11.1.6.4.5.2
Discovery....................................................................................2104
11.1.6.4.5.3
Port Test Mode........................................................................... 2105
Device Data Structures.................................................................................................................2105
11.1.6.5.1
11.1.6.5.2
11.1.6.6
Page
Endpoint Queue Head (dQH)................................................................................2106
11.1.6.5.1.1
Endpoint Capabilities/Characteristics........................................ 2107
11.1.6.5.1.2
Transfer Overlay-Endpoint Queue Head....................................2108
11.1.6.5.1.3
Current dTD Pointer................................................................... 2108
11.1.6.5.1.4
Set-up Buffer.............................................................................. 2109
Endpoint Transfer Descriptor (dTD).................................................................... 2109
Device Operational Model........................................................................................................... 2111
11.1.6.6.1
Device Controller Initialization............................................................................ 2111
11.1.6.6.2
Port State and Control...........................................................................................2112
11.1.6.6.3
11.1.6.6.4
11.1.6.6.2.1
Bus Reset.................................................................................... 2114
11.1.6.6.2.2
Suspend/Resume.........................................................................2115
11.1.6.6.2.3
Managing Endpoints...................................................................2116
11.1.6.6.2.4
Endpoint Initialization................................................................ 2117
11.1.6.6.2.5
Stalling........................................................................................2117
11.1.6.6.2.6
Data Toggle ............................................................................... 2118
Operational Model For Packet Transfers..............................................................2120
11.1.6.6.3.1
Interrupt/Bulk Endpoint Operational Model.............................. 2120
11.1.6.6.3.2
Control Endpoint Operation Model............................................2123
11.1.6.6.3.3
Isochronous Endpoint Operational Model..................................2126
Managing Queue Heads........................................................................................2128
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Section number
Title
11.1.6.6.5
11.1.6.6.6
11.1.7
Page
11.1.6.6.4.1
Queue Head Initialization...........................................................2129
11.1.6.6.4.2
Operational Model For Setup Transfers..................................... 2130
Managing Transfers with Transfer Descriptors.................................................... 2131
11.1.6.6.5.1
Software Link Pointers............................................................... 2131
11.1.6.6.5.2
Building a Transfer Descriptor...................................................2131
11.1.6.6.5.3
Executing A Transfer Descriptor................................................2132
11.1.6.6.5.4
Transfer Completion...................................................................2133
11.1.6.6.5.5
Flushing/De-priming an Endpoint..............................................2133
11.1.6.6.5.6
Device Error Matrix................................................................... 2134
Servicing Interrupts...............................................................................................2134
11.1.6.6.6.1
High-Frequency Interrupts......................................................... 2135
11.1.6.6.6.2
Low-Frequency Interrupts.......................................................... 2135
11.1.6.6.6.3
Error Interrupts........................................................................... 2135
Glossary of Terms and Abbreviations............................................................................................................. 2136
11.2 Universal Serial Bus 2.0 Integrated PHY (USBPHY)....................................................................................................2142
11.2.1
USB PHY Overview........................................................................................................................................ 2142
11.2.2
USB PHY Memory Map/Register Definition ................................................................................................. 2143
11.2.3
11.2.2.1
USB PHY Power-Down Register (USBPHYx_PWDn).............................................................. 2147
11.2.2.2
USB PHY Transmitter Control Register (USBPHYx_TXn)....................................................... 2148
11.2.2.3
USB PHY Receiver Control Register (USBPHYx_RXn)........................................................... 2150
11.2.2.4
USB PHY General Control Register (USBPHYx_CTRLn)........................................................ 2152
11.2.2.5
USB PHY Status Register (USBPHYx_STATUS)..................................................................... 2155
11.2.2.6
USB PHY Debug Register (USBPHYx_DEBUGn).................................................................... 2157
11.2.2.7
UTMI Debug Status Register 0 (USBPHYx_DEBUG0_STATUS)............................................2159
11.2.2.8
UTMI Debug Status Register 1 (USBPHYx_DEBUG1n)...........................................................2160
11.2.2.9
UTMI RTL Version (USBPHYx_VERSION).............................................................................2160
11.2.2.10
USB PHY IP Block Register (USBPHYx_IPn)...........................................................................2161
USB Analog Memory Map/Register Definition ............................................................................................. 2162
11.2.3.1
USB0 VBUS Detect control register (USB_ANALOG_USB0_VBUS_DETECTn)................... 2164
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Section number
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Page
11.2.3.2
USB0 Charger Detect control register (USB_ANALOG_USB0_CHRG_DETECTn)...............2167
11.2.3.3
USB0 VBUS Detect Status definition register
(USB_ANALOG_USB0_VBUS_DETECT_STATUS)............................................................. 2169
11.2.3.4
USB0 Charger Detect Status definition register
(USB_ANALOG_USB0_CHRG_DETECT_STATUS)............................................................. 2171
11.2.3.5
USB0 Loopback register (USB_ANALOG_USB0_LOOPBACKn).......................................... 2173
11.2.3.6
USB0 Miscellaneous definition register (USB_ANALOG_USB0_MISCn).............................. 2175
11.2.3.7
USB1 VBUS Detect control register (USB_ANALOG_USB1_VBUS_DETECTn)................... 2176
11.2.3.8
USB1 Charger Detect control register (USB_ANALOG_USB1_CHRG_DETECTn)...............2179
11.2.3.9
USB1 VBUS Detect STS definition register
(USB_ANALOG_USB1_VBUS_DETECT_STATUS)............................................................. 2181
11.2.3.10
USB1 Charger Detect Status definition register
(USB_ANALOG_USB1_CHRG_DETECT_STATUS)............................................................. 2183
11.2.4
11.2.3.11
USB1 Loopback register (USB_ANALOG_USB1_LOOPBACKn).......................................... 2185
11.2.3.12
USB1 Miscellaneous definition register (USB_ANALOG_USB1_MISCn).............................. 2187
Operation..........................................................................................................................................................2188
11.2.4.1
UTMI........................................................................................................................................... 2188
11.2.4.2
Digital Transmitter....................................................................................................................... 2188
11.2.4.3
Digital Receiver........................................................................................................................... 2189
11.2.4.4
Analog Receiver...........................................................................................................................2189
11.2.4.5
11.2.4.4.1
HS Differential Receiver.......................................................................................2190
11.2.4.4.2
Squelch Detector...................................................................................................2191
11.2.4.4.3
LS/FS Differential Receiver................................................................................. 2191
11.2.4.4.4
HS Disconnect Detector........................................................................................2191
11.2.4.4.5
USB Plugged-In Detector..................................................................................... 2191
11.2.4.4.6
Single-Ended USB_DP Receiver..........................................................................2192
11.2.4.4.7
Single-Ended USB_DM Receiver........................................................................ 2192
11.2.4.4.8
9X Oversample Module........................................................................................2192
Analog Transmitter...................................................................................................................... 2192
11.2.4.5.1
Switchable High-Speed 45Ω Termination Resistors.............................................2192
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Section number
11.2.4.6
Title
Page
11.2.4.5.2
Low-Speed/Full-Speed Differential Driver.......................................................... 2192
11.2.4.5.3
High-Speed Differential Driver............................................................................ 2193
11.2.4.5.4
Switchable 1.5KΩ USB_DP Pullup Resistor........................................................2193
11.2.4.5.5
Switchable 15KΩ USB_DP Pulldown Resistor....................................................2193
Recommended Register Configuration for USB Certification.................................................... 2195
11.3 MediaLB (MLB) (R-Series only)................................................................................................................................... 2196
11.3.1
11.3.2
Introduction ..................................................................................................................................................... 2196
11.3.1.1
Overview...................................................................................................................................... 2196
11.3.1.2
Features........................................................................................................................................ 2197
11.3.1.3
Logic Blocks................................................................................................................................ 2198
11.3.1.4
Modes of Operation..................................................................................................................... 2199
External Signal Description............................................................................................................................. 2199
11.3.2.1
11.3.3
Detailed Signal Descriptions .......................................................................................................2199
Memory Map and Register Definition............................................................................................................. 2200
11.3.3.1
Device Control Configuration Register (MLB_DCCR).............................................................. 2205
11.3.3.2
System Status Configuration Register (MLB_SSCR)................................................................. 2207
11.3.3.3
System Data Configuration Register (MLB_SDCR)...................................................................2209
11.3.3.4
System Mask Configuration Register (MLB_SMCR).................................................................2209
11.3.3.5
Version Control Configuration Register (MLB_VCCR).............................................................2211
11.3.3.6
Synchronous Base Address Configuration Register (MLB_SBCR)............................................2211
11.3.3.7
Asynchronous Base Address Configuration Register (MLB_ABCR).........................................2212
11.3.3.8
Control Base Address Configuration Register (MLB_CBCR)....................................................2212
11.3.3.9
Isochronous Base Address Configuration Register (MLB_IBCR)..............................................2213
11.3.3.10
Channel Interrupt Configuration Register (MLB_CICR)............................................................ 2213
11.3.3.11
Channel Entry Configuration Register (MLB_CECRn).............................................................. 2214
11.3.3.12
Channel Status Configuration Register (MLB_CSCRn)............................................................. 2217
11.3.3.13
Channel Current Buffer Configuration Register (MLB_CCBCRn)............................................ 2221
11.3.3.14
Channel Next Buffer Configuration Register (MLB_CNBCRn)................................................ 2222
11.3.3.15
Local Channel Buffer Configuration Register (MLB_LCBCRn)................................................2222
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Section number
11.3.4
Title
Page
Functional Description..................................................................................................................................... 2224
11.3.4.1
Local Channel Buffer RAM.........................................................................................................2224
11.3.4.1.1
Local Buffer Start Address................................................................................... 2225
11.3.4.1.2
Local Channel Buffer Depth.................................................................................2225
11.3.4.2
Streaming Channel Frame Synchronization................................................................................ 2226
11.3.4.3
Loop-Back Test Mode................................................................................................................. 2227
11.4 10/100-Mbps Ethernet MAC (ENET)............................................................................................................................ 2228
11.4.1
Introduction...................................................................................................................................................... 2228
11.4.2
Overview.......................................................................................................................................................... 2229
11.4.2.1
11.4.2.2
Features........................................................................................................................................ 2229
11.4.2.1.1
Ethernet MAC features......................................................................................... 2229
11.4.2.1.2
IP protocol performance optimization features.....................................................2231
11.4.2.1.3
IEEE 1588 features............................................................................................... 2231
Block diagram.............................................................................................................................. 2232
11.4.3
External signal description...............................................................................................................................2233
11.4.4
Memory map/register definition...................................................................................................................... 2235
11.4.4.1
Interrupt Event Register (ENETx_EIR)....................................................................................... 2244
11.4.4.2
Interrupt Mask Register (ENETx_EIMR)....................................................................................2247
11.4.4.3
Receive Descriptor Active Register (ENETx_RDAR)................................................................ 2250
11.4.4.4
Transmit Descriptor Active Register (ENETx_TDAR)...............................................................2251
11.4.4.5
Ethernet Control Register (ENETx_ECR)................................................................................... 2252
11.4.4.6
MII Management Frame Register (ENETx_MMFR).................................................................. 2253
11.4.4.7
MII Speed Control Register (ENETx_MSCR)............................................................................ 2254
11.4.4.8
MIB Control Register (ENETx_MIBC).......................................................................................2256
11.4.4.9
Receive Control Register (ENETx_RCR)....................................................................................2258
11.4.4.10
Transmit Control Register (ENETx_TCR).................................................................................. 2261
11.4.4.11
Physical Address Lower Register (ENETx_PALR).................................................................... 2263
11.4.4.12
Physical Address Upper Register (ENETx_PAUR).................................................................... 2263
11.4.4.13
Opcode/Pause Duration Register (ENETx_OPD)........................................................................2264
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Section number
Title
Page
11.4.4.14
Descriptor Individual Upper Address Register (ENETx_IAUR).................................................2264
11.4.4.15
Descriptor Individual Lower Address Register (ENETx_IALR).................................................2265
11.4.4.16
Descriptor Group Upper Address Register (ENETx_GAUR)..................................................... 2265
11.4.4.17
Descriptor Group Lower Address Register (ENETx_GALR)..................................................... 2266
11.4.4.18
Transmit FIFO Watermark Register (ENETx_TFWR)............................................................... 2266
11.4.4.19
Receive Descriptor Ring Start Register (ENETx_RDSR)........................................................... 2267
11.4.4.20
Transmit Buffer Descriptor Ring Start Register (ENETx_TDSR).............................................. 2268
11.4.4.21
Maximum Receive Buffer Size Register (ENETx_MRBR)........................................................ 2269
11.4.4.22
Receive FIFO Section Full Threshold (ENETx_RSFL).............................................................. 2270
11.4.4.23
Receive FIFO Section Empty Threshold (ENETx_RSEM).........................................................2270
11.4.4.24
Receive FIFO Almost Empty Threshold (ENETx_RAEM)........................................................ 2271
11.4.4.25
Receive FIFO Almost Full Threshold (ENETx_RAFL)..............................................................2271
11.4.4.26
Transmit FIFO Section Empty Threshold (ENETx_TSEM)....................................................... 2272
11.4.4.27
Transmit FIFO Almost Empty Threshold (ENETx_TAEM)....................................................... 2272
11.4.4.28
Transmit FIFO Almost Full Threshold (ENETx_TAFL)............................................................ 2273
11.4.4.29
Transmit Inter-Packet Gap (ENETx_TIPG)................................................................................ 2273
11.4.4.30
Frame Truncation Length (ENETx_FTRL)................................................................................. 2274
11.4.4.31
Transmit Accelerator Function Configuration (ENETx_TACC).................................................2274
11.4.4.32
Receive Accelerator Function Configuration (ENETx_RACC).................................................. 2275
11.4.4.33
Reserved Statistic Register (ENETx_RMON_T_DROP)............................................................2276
11.4.4.34
Tx Packet Count Statistic Register (ENETx_RMON_T_PACKETS).........................................2277
11.4.4.35
Tx Broadcast Packets Statistic Register (ENETx_RMON_T_BC_PKT)....................................2277
11.4.4.36
Tx Multicast Packets Statistic Register (ENETx_RMON_T_MC_PKT)....................................2278
11.4.4.37
Tx Packets with CRC/Align Error Statistic Register (ENETx_RMON_T_CRC_ALIGN)........ 2278
11.4.4.38
Tx Packets Less Than Bytes and Good CRC Statistic Register
(ENETx_RMON_T_UNDERSIZE)............................................................................................ 2278
11.4.4.39
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
(ENETx_RMON_T_OVERSIZE)............................................................................................... 2279
11.4.4.40
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENETx_RMON_T_FRAG). 2279
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Section number
11.4.4.41
Title
Page
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
(ENETx_RMON_T_JAB)........................................................................................................... 2280
11.4.4.42
Tx Collision Count Statistic Register (ENETx_RMON_T_COL).............................................. 2280
11.4.4.43
Tx 64-Byte Packets Statistic Register (ENETx_RMON_T_P64)................................................2281
11.4.4.44
Tx 65- to 127-byte Packets Statistic Register (ENETx_RMON_T_P65TO127)........................ 2281
11.4.4.45
Tx 128- to 255-byte Packets Statistic Register (ENETx_RMON_T_P128TO255).................... 2282
11.4.4.46
Tx 256- to 511-byte Packets Statistic Register (ENETx_RMON_T_P256TO511).................... 2282
11.4.4.47
Tx 512- to 1023-byte Packets Statistic Register (ENETx_RMON_T_P512TO1023)................ 2283
11.4.4.48
Tx 1024- to 2047-byte Packets Statistic Register (ENETx_RMON_T_P1024TO2047)............ 2283
11.4.4.49
Tx Packets Greater Than 2048 Bytes Statistic Register (ENETx_RMON_T_P_GTE2048)...... 2284
11.4.4.50
Tx Octets Statistic Register (ENETx_RMON_T_OCTETS).......................................................2284
11.4.4.51
Reserved Statistic Register (ENETx_IEEE_T_DROP)............................................................... 2284
11.4.4.52
Frames Transmitted OK Statistic Register (ENETx_IEEE_T_FRAME_OK)............................ 2285
11.4.4.53
Frames Transmitted with Single Collision Statistic Register (ENETx_IEEE_T_1COL)............2285
11.4.4.54
Frames Transmitted with Multiple Collisions Statistic Register (ENETx_IEEE_T_MCOL)..... 2286
11.4.4.55
Frames Transmitted after Deferral Delay Statistic Register (ENETx_IEEE_T_DEF)................2286
11.4.4.56
Frames Transmitted with Late Collision Statistic Register (ENETx_IEEE_T_LCOL).............. 2286
11.4.4.57
Frames Transmitted with Excessive Collisions Statistic Register (ENETx_IEEE_T_EXCOL). 2287
11.4.4.58
Frames Transmitted with Tx FIFO Underrun Statistic Register (ENETx_IEEE_T_MACERR) 2287
11.4.4.59
Frames Transmitted with Carrier Sense Error Statistic Register (ENETx_IEEE_T_CSERR)....2288
11.4.4.60
Reserved Statistic Register (ENETx_IEEE_T_SQE).................................................................. 2288
11.4.4.61
Flow Control Pause Frames Transmitted Statistic Register (ENETx_IEEE_T_FDXFC)........... 2288
11.4.4.62
Octet Count for Frames Transmitted w/o Error Statistic Register
(ENETx_IEEE_T_OCTETS_OK)............................................................................................... 2289
11.4.4.63
Rx Packet Count Statistic Register (ENETx_RMON_R_PACKETS)........................................ 2289
11.4.4.64
Rx Broadcast Packets Statistic Register (ENETx_RMON_R_BC_PKT)................................... 2290
11.4.4.65
Rx Multicast Packets Statistic Register (ENETx_RMON_R_MC_PKT)................................... 2290
11.4.4.66
Rx Packets with CRC/Align Error Statistic Register (ENETx_RMON_R_CRC_ALIGN)........ 2290
11.4.4.67
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENETx_RMON_R_UNDERSIZE)............................................................................................ 2291
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Section number
11.4.4.68
Title
Page
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
(ENETx_RMON_R_OVERSIZE)............................................................................................... 2291
11.4.4.69
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENETx_RMON_R_FRAG).2292
11.4.4.70
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
(ENETx_RMON_R_JAB)........................................................................................................... 2292
11.4.4.71
Reserved Statistic Register (ENETx_RMON_R_RESVD_0)..................................................... 2292
11.4.4.72
Rx 64-Byte Packets Statistic Register (ENETx_RMON_R_P64)............................................... 2293
11.4.4.73
Rx 65- to 127-Byte Packets Statistic Register (ENETx_RMON_R_P65TO127)....................... 2293
11.4.4.74
Rx 128- to 255-Byte Packets Statistic Register (ENETx_RMON_R_P128TO255)................... 2294
11.4.4.75
Rx 256- to 511-Byte Packets Statistic Register (ENETx_RMON_R_P256TO511)................... 2294
11.4.4.76
Rx 512- to 1023-Byte Packets Statistic Register (ENETx_RMON_R_P512TO1023)............... 2294
11.4.4.77
Rx 1024- to 2047-Byte Packets Statistic Register (ENETx_RMON_R_P1024TO2047)........... 2295
11.4.4.78
Rx Packets Greater than 2048 Bytes Statistic Register (ENETx_RMON_R_P_GTE2048)....... 2295
11.4.4.79
Rx Octets Statistic Register (ENETx_RMON_R_OCTETS)...................................................... 2296
11.4.4.80
Frames not Counted Correctly Statistic Register (ENETx_IEEE_R_DROP)............................. 2296
11.4.4.81
Frames Received OK Statistic Register (ENETx_IEEE_R_FRAME_OK)................................ 2296
11.4.4.82
Frames Received with CRC Error Statistic Register (ENETx_IEEE_R_CRC).......................... 2297
11.4.4.83
Frames Received with Alignment Error Statistic Register (ENETx_IEEE_R_ALIGN).............2297
11.4.4.84
Receive FIFO Overflow Count Statistic Register (ENETx_IEEE_R_MACERR)...................... 2298
11.4.4.85
Flow Control Pause Frames Received Statistic Register (ENETx_IEEE_R_FDXFC)............... 2298
11.4.4.86
Octet Count for Frames Received without Error Statistic Register
(ENETx_IEEE_R_OCTETS_OK)...............................................................................................2298
11.4.4.87
Adjustable Timer Control Register (ENETx_ATCR)..................................................................2299
11.4.4.88
Timer Value Register (ENETx_ATVR)...................................................................................... 2301
11.4.4.89
Timer Offset Register (ENETx_ATOFF).................................................................................... 2301
11.4.4.90
Timer Period Register (ENETx_ATPER)....................................................................................2302
11.4.4.91
Timer Correction Register (ENETx_ATCOR)............................................................................ 2302
11.4.4.92
Time-Stamping Clock Period Register (ENETx_ATINC).......................................................... 2303
11.4.4.93
Timestamp of Last Transmitted Frame (ENETx_ATSTMP)...................................................... 2303
11.4.4.94
Timer Global Status Register (ENETx_TGSR)........................................................................... 2304
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Section number
11.4.5
Title
Page
11.4.4.95
Timer Control Status Register (ENETx_TCSRn)........................................................................ 2305
11.4.4.96
Timer Compare Capture Register (ENETx_TCCRn).................................................................. 2306
Functional description......................................................................................................................................2307
11.4.5.1
11.4.5.2
11.4.5.3
Ethernet MAC frame formats...................................................................................................... 2307
11.4.5.1.1
Pause Frames........................................................................................................ 2308
11.4.5.1.2
Magic packets....................................................................................................... 2309
IP and higher layers frame format................................................................................................2309
11.4.5.2.1
Ethernet types........................................................................................................2310
11.4.5.2.2
IPv4 datagram format........................................................................................... 2310
11.4.5.2.3
IPv6 datagram format........................................................................................... 2311
11.4.5.2.4
Internet Control Message Protocol (ICMP) datagram format.............................. 2312
11.4.5.2.5
User Datagram Protocol (UDP) datagram format................................................ 2312
11.4.5.2.6
TCP datagram format............................................................................................2313
IEEE 1588 message formats........................................................................................................ 2314
11.4.5.3.1
11.4.5.3.2
11.4.5.4
Transport encapsulation........................................................................................ 2314
11.4.5.3.1.1
UDP/IP....................................................................................... 2314
11.4.5.3.1.2
Native Ethernet (PTPv2)............................................................ 2315
PTP header............................................................................................................ 2315
11.4.5.3.2.1
PTPv1 header..............................................................................2315
11.4.5.3.2.2
PTPv2 header..............................................................................2316
MAC receive................................................................................................................................ 2317
11.4.5.4.1
Collision detection in half-duplex mode...............................................................2318
11.4.5.4.2
Preamble processing............................................................................................. 2318
11.4.5.4.3
MAC address check.............................................................................................. 2319
11.4.5.4.4
11.4.5.4.3.1
Unicast address check.................................................................2319
11.4.5.4.3.2
Multicast and unicast address resolution....................................2319
11.4.5.4.3.3
Broadcast address reject............................................................. 2320
11.4.5.4.3.4
Miss-bit implementation.............................................................2320
Frame length/type verification: payload length check..........................................2321
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Section number
11.4.5.5
11.4.5.6
11.4.5.7
11.4.5.8
Title
Page
11.4.5.4.5
Frame length/type verification: frame length check............................................. 2321
11.4.5.4.6
VLAN frames processing..................................................................................... 2321
11.4.5.4.7
Pause frame termination....................................................................................... 2322
11.4.5.4.8
CRC check............................................................................................................ 2322
11.4.5.4.9
Frame padding removal........................................................................................ 2322
MAC transmit.............................................................................................................................. 2323
11.4.5.5.1
Frame payload padding.........................................................................................2324
11.4.5.5.2
MAC address insertion......................................................................................... 2324
11.4.5.5.3
CRC-32 generation............................................................................................... 2324
11.4.5.5.4
Inter-packet gap (IPG).......................................................................................... 2325
11.4.5.5.5
Collision detection and handling — half-duplex operation only..........................2325
Full-duplex flow control operation.............................................................................................. 2327
11.4.5.6.1
Remote device congestion.................................................................................... 2327
11.4.5.6.2
Local device/FIFO congestion..............................................................................2327
Magic packet detection................................................................................................................ 2328
11.4.5.7.1
Sleep mode............................................................................................................2329
11.4.5.7.2
Magic packet detection......................................................................................... 2329
11.4.5.7.3
Wakeup................................................................................................................. 2329
IP accelerator functions................................................................................................................2329
11.4.5.8.1
Checksum calculation........................................................................................... 2330
11.4.5.8.2
Additional padding processing............................................................................. 2331
11.4.5.8.3
32-bit Ethernet payload alignment........................................................................2331
11.4.5.8.3.1
Receive processing..................................................................... 2331
11.4.5.8.3.2
Transmit processing....................................................................2332
11.4.5.8.4
Received frame discard.........................................................................................2332
11.4.5.8.5
IPv4 fragments...................................................................................................... 2332
11.4.5.8.6
IPv6 support.......................................................................................................... 2333
11.4.5.8.6.1
Receive processing..................................................................... 2333
11.4.5.8.6.2
Transmit processing....................................................................2334
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Section number
11.4.5.9
11.4.5.10
Title
Resets and stop controls............................................................................................................... 2334
11.4.5.9.1
Hardware reset...................................................................................................... 2334
11.4.5.9.2
Soft reset............................................................................................................... 2334
11.4.5.9.3
Hardware freeze.................................................................................................... 2334
11.4.5.9.4
Graceful stop.........................................................................................................2335
11.4.5.9.4.1
Graceful transmit stop (GTS)..................................................... 2335
11.4.5.9.4.2
Graceful receive stop (GRS)...................................................... 2336
11.4.5.9.4.3
Graceful stop interrupt (GRA)....................................................2337
IEEE 1588 functions.................................................................................................................... 2337
11.4.5.10.1
Adjustable timer module.......................................................................................2337
11.4.5.10.1.1
11.4.5.11
Page
Adjustable timer implementation............................................... 2338
11.4.5.10.2
Transmit timestamping......................................................................................... 2339
11.4.5.10.3
Receive timestamping...........................................................................................2339
11.4.5.10.4
Time synchronization............................................................................................2340
11.4.5.10.5
Input Capture and Output Compare......................................................................2340
11.4.5.10.5.1
Input capture...............................................................................2340
11.4.5.10.5.2
Output compare.......................................................................... 2340
11.4.5.10.5.3
DMA requests.............................................................................2341
FIFO thresholds............................................................................................................................2341
11.4.5.11.1
Receive FIFO........................................................................................................ 2341
11.4.5.11.2
Transmit FIFO...................................................................................................... 2342
11.4.5.12
Loopback options......................................................................................................................... 2343
11.4.5.13
Legacy buffer descriptors.............................................................................................................2344
11.4.5.14
11.4.5.15
11.4.5.13.1
Legacy receive buffer descriptor.......................................................................... 2344
11.4.5.13.2
Legacy transmit buffer descriptor.........................................................................2345
Enhanced buffer descriptors.........................................................................................................2345
11.4.5.14.1
Enhanced receive buffer descriptor...................................................................... 2345
11.4.5.14.2
Enhanced transmit buffer descriptor.....................................................................2349
Client FIFO application interface................................................................................................ 2351
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Section number
11.4.5.16
Title
Page
11.4.5.15.1
Data structure description..................................................................................... 2352
11.4.5.15.2
Data structure examples........................................................................................2353
11.4.5.15.3
Frame status.......................................................................................................... 2354
FIFO protection............................................................................................................................2354
11.4.5.16.1
Transmit FIFO underflow..................................................................................... 2355
11.4.5.16.2
Transmit FIFO overflow....................................................................................... 2355
11.4.5.16.3
Receive FIFO overflow.........................................................................................2356
11.4.5.17
Reference clock............................................................................................................................2356
11.4.5.18
PHY management interface......................................................................................................... 2357
11.4.5.19
11.4.5.18.1
MDIO clause 22 frame format..............................................................................2357
11.4.5.18.2
MDIO clause 45 frame format..............................................................................2358
11.4.5.18.3
MDIO clock generation........................................................................................ 2359
11.4.5.18.4
MDIO operation....................................................................................................2359
Ethernet interfaces........................................................................................................................2360
11.4.5.19.1
RMII interface.......................................................................................................2360
11.4.5.19.2
MII Interface — transmit...................................................................................... 2361
11.4.5.19.2.1
11.4.5.19.3
Transmit with collision — half-duplex...................................... 2362
MII interface — receive........................................................................................2363
11.5 Ethernet Switch (ESW) (F-Series only)..........................................................................................................................2364
11.5.1
11.5.2
11.5.3
Introduction...................................................................................................................................................... 2364
11.5.1.1
Block Diagram............................................................................................................................. 2365
11.5.1.2
Features........................................................................................................................................ 2366
Modes of Operation......................................................................................................................................... 2367
11.5.2.1
Passthrough mode........................................................................................................................ 2367
11.5.2.2
Switch Mode................................................................................................................................ 2368
11.5.2.2.1
Port 0 Input Buffer................................................................................................ 2369
11.5.2.2.2
Port 0 Input Backpressure/Congestion Indication................................................ 2369
ESW memory map and registers......................................................................................................................2370
11.5.3.1
Revision (ESW_REV)................................................................................................................. 2376
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11.5.3.2
Scratch register (ESW_SCR)....................................................................................................... 2376
11.5.3.3
Port enable register (ESW_PER)................................................................................................. 2377
11.5.3.4
VLAN verify (ESW_VLANV).................................................................................................... 2378
11.5.3.5
Default broadcast resolution (ESW_DBCR)............................................................................... 2379
11.5.3.6
Default multicast resolution (ESW_DMCR)............................................................................... 2380
11.5.3.7
Blocking and learning enable (ESW_BKLR).............................................................................. 2380
11.5.3.8
Bridge management port configuration (ESW_BMPC).............................................................. 2382
11.5.3.9
Mode configuration (ESW_MODE)............................................................................................ 2383
11.5.3.10
VLAN input manipulation select (ESW_VIMSEL).................................................................... 2384
11.5.3.11
VLAN output manipulation select (ESW_VOMSEL).................................................................2385
11.5.3.12
VLAN input manipulation enable (ESW_VIMEN).....................................................................2386
11.5.3.13
VLAN tag ID (ESW_VID).......................................................................................................... 2386
11.5.3.14
Mirror control register (ESW_MCR)...........................................................................................2387
11.5.3.15
Egress port definitions (ESW_EGMAP)..................................................................................... 2388
11.5.3.16
Ingress port definitions (ESW_INGMAP)...................................................................................2389
11.5.3.17
Ingress source MAC address low (ESW_INGSAL)....................................................................2389
11.5.3.18
Ingress source MAC address high (ESW_INGSAH).................................................................. 2390
11.5.3.19
Ingress destination MAC address low (ESW_INGDAL)............................................................ 2390
11.5.3.20
Ingress destination MAC address high (ESW_INGDAH).......................................................... 2390
11.5.3.21
Egress source MAC address low (ESW_EGSAL)...................................................................... 2391
11.5.3.22
Egress source MAC address high (ESW_EGSAH)..................................................................... 2391
11.5.3.23
Egress destination MAC address low (ESW_EGDAL)...............................................................2391
11.5.3.24
Egress destination MAC address high (ESW_EGDAH)............................................................. 2392
11.5.3.25
Mirror count value (ESW_MCVAL)........................................................................................... 2392
11.5.3.26
Memory manager status (ESW_MMSR)..................................................................................... 2393
11.5.3.27
Low memory threshold (ESW_LMT)..........................................................................................2394
11.5.3.28
Lowest number of free cells (ESW_LFC)................................................................................... 2395
11.5.3.29
Port congestion status (ESW_PCSR)...........................................................................................2395
11.5.3.30
Switch input and output interface status (ESW_IOSR)............................................................... 2396
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Page
11.5.3.31
Queue weights (ESW_QWT).......................................................................................................2397
11.5.3.32
Port 0 Backpressure Congestion Threshold (ESW_P0BCT)....................................................... 2398
11.5.3.33
Port 0 forced forwarding enable (ESW_FFEN)...........................................................................2399
11.5.3.34
Port snooping registers (ESW_PSNP1)....................................................................................... 2400
11.5.3.35
Port snooping registers (ESW_PSNP2)....................................................................................... 2401
11.5.3.36
Port snooping registers (ESW_PSNP3)....................................................................................... 2402
11.5.3.37
Port snooping registers (ESW_PSNP4)....................................................................................... 2403
11.5.3.38
Port snooping registers (ESW_PSNP5)....................................................................................... 2404
11.5.3.39
Port snooping registers (ESW_PSNP6)....................................................................................... 2405
11.5.3.40
Port snooping registers (ESW_PSNP7)....................................................................................... 2406
11.5.3.41
Port snooping registers (ESW_PSNP8)....................................................................................... 2407
11.5.3.42
IP snooping registers (ESW_IPSNP1)......................................................................................... 2408
11.5.3.43
IP snooping registers (ESW_IPSNP2)......................................................................................... 2409
11.5.3.44
IP snooping registers (ESW_IPSNP3)......................................................................................... 2410
11.5.3.45
IP snooping registers (ESW_IPSNP4)......................................................................................... 2411
11.5.3.46
IP snooping registers (ESW_IPSNP5)......................................................................................... 2412
11.5.3.47
IP snooping registers (ESW_IPSNP6)......................................................................................... 2413
11.5.3.48
IP snooping registers (ESW_IPSNP7)......................................................................................... 2414
11.5.3.49
IP snooping registers (ESW_IPSNP8)......................................................................................... 2415
11.5.3.50
Port 0 VLAN priority resolution map (ESW_P0VRES)............................................................. 2416
11.5.3.51
Port 1 VLAN priority resolution map (ESW_P1VRES)............................................................. 2417
11.5.3.52
Port 2 VLAN priority resolution map (ESW_P2VRES)............................................................. 2418
11.5.3.53
IPv4/v6 priority resolution table (ESW_IPRES)......................................................................... 2419
11.5.3.54
Port 0 priority resolution configuration (ESW_P0RES)..............................................................2420
11.5.3.55
Port 1 priority resolution configuration (ESW_P1RES)..............................................................2421
11.5.3.56
Port 2 priority resolution configuration (ESW_P2RES)..............................................................2422
11.5.3.57
Port 0 VLAN ID (ESW_P0ID).................................................................................................... 2423
11.5.3.58
Port 1 VLAN ID (ESW_P1ID).................................................................................................... 2423
11.5.3.59
Port 2 VLAN ID (ESW_P2ID).................................................................................................... 2424
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Page
11.5.3.60
VLAN domain resolution entry 0 (ESW_VRES0)...................................................................... 2424
11.5.3.61
VLAN domain resolution entry 1 (ESW_VRES1)...................................................................... 2425
11.5.3.62
VLAN domain resolution entry 2 (ESW_VRES2)...................................................................... 2426
11.5.3.63
VLAN domain resolution entry 4 (ESW_VRES3)...................................................................... 2427
11.5.3.64
VLAN domain resolution entry 4 (ESW_VRES4)...................................................................... 2428
11.5.3.65
VLAN domain resolution entry 5 (ESW_VRES5)...................................................................... 2429
11.5.3.66
VLAN domain resolution entry 6 (ESW_VRES6)...................................................................... 2430
11.5.3.67
VLAN domain resolution entry 7 (ESW_VRES7)...................................................................... 2431
11.5.3.68
VLAN domain resolution entry 8 (ESW_VRES8)...................................................................... 2432
11.5.3.69
VLAN domain resolution entry 9 (ESW_VRES9)...................................................................... 2433
11.5.3.70
VLAN domain resolution entry 10 (ESW_VRES10).................................................................. 2434
11.5.3.71
VLAN domain resolution entry 11 (ESW_VRES11).................................................................. 2435
11.5.3.72
VLAN domain resolution entry 12 (ESW_VRES12).................................................................. 2436
11.5.3.73
VLAN domain resolution entry 13 (ESW_VRES13).................................................................. 2437
11.5.3.74
VLAN domain resolution entry 14 (ESW_VRES14).................................................................. 2438
11.5.3.75
VLAN domain resolution entry 15 (ESW_VRES15).................................................................. 2439
11.5.3.76
VLAN domain resolution entry 16 (ESW_VRES16).................................................................. 2440
11.5.3.77
VLAN domain resolution entry 17 (ESW_VRES17).................................................................. 2441
11.5.3.78
VLAN domain resolution entry 18 (ESW_VRES18).................................................................. 2442
11.5.3.79
VLAN domain resolution entry 19 (ESW_VRES19).................................................................. 2443
11.5.3.80
VLAN domain resolution entry 20 (ESW_VRES20).................................................................. 2444
11.5.3.81
VLAN domain resolution entry 21 (ESW_VRES21).................................................................. 2445
11.5.3.82
VLAN domain resolution entry 22 (ESW_VRES22).................................................................. 2446
11.5.3.83
VLAN domain resolution entry 23 (ESW_VRES23).................................................................. 2447
11.5.3.84
VLAN domain resolution entry 24 (ESW_VRES24).................................................................. 2448
11.5.3.85
VLAN domain resolution entry 25 (ESW_VRES25).................................................................. 2449
11.5.3.86
VLAN domain resolution entry 26 (ESW_VRES26).................................................................. 2450
11.5.3.87
VLAN domain resolution entry 27 (ESW_VRES27).................................................................. 2451
11.5.3.88
VLAN domain resolution entry 28 (ESW_VRES28).................................................................. 2452
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Title
Page
11.5.3.89
VLAN domain resolution entry 29 (ESW_VRES29).................................................................. 2453
11.5.3.90
VLAN domain resolution entry 30 (ESW_VRES30).................................................................. 2454
11.5.3.91
VLAN domain resolution entry 31 (ESW_VRES31).................................................................. 2455
11.5.3.92
Number of discarded frames (ESW_DISCN).............................................................................. 2455
11.5.3.93
Bytes of discarded frames (ESW_DISCB).................................................................................. 2456
11.5.3.94
Number of non-discarded frames (ESW_NDISCN)....................................................................2456
11.5.3.95
Bytes of non-discarded frames (ESW_NDISCB)........................................................................ 2457
11.5.3.96
Port 0 output queue congestion (ESW_P0OQC)......................................................................... 2457
11.5.3.97
Port 0 mismatching VLAN ID (ESW_P0MVID)........................................................................ 2458
11.5.3.98
Port 0 missing VLAN tag (ESW_P0MVTAG)............................................................................2458
11.5.3.99
Port 0 blocked (ESW_P0BL)....................................................................................................... 2459
11.5.3.100 Port 1 output queue congestion (ESW_P1OQC)......................................................................... 2459
11.5.3.101 Port 1 mismatching VLAN ID (ESW_P1MVID)........................................................................ 2460
11.5.3.102 Port 1 missing VLAN tag (ESW_P1MVTAG)............................................................................2460
11.5.3.103 Port 1 blocked (ESW_P1BL)....................................................................................................... 2461
11.5.3.104 Port 2 output queue congestion (ESW_P2OQC)......................................................................... 2461
11.5.3.105 Port 2 mismatching VLAN ID (ESW_P2MVID)........................................................................ 2462
11.5.3.106 Port 2 missing VLAN tag (ESW_P2MVTAG)............................................................................2462
11.5.3.107 Port 2 blocked (ESW_P2BL)....................................................................................................... 2463
11.5.3.108 Interrupt status register (ESW_ISR)............................................................................................ 2463
11.5.3.109 Interrupt mask register (ESW_IMR)............................................................................................2464
11.5.3.110 Receive descriptor ring pointer (ESW_RDSR)........................................................................... 2466
11.5.3.111 Transmit descriptor ring pointer (ESW_TDSR).......................................................................... 2467
11.5.3.112 Maximum receive buffer size (ESW_MRBR).............................................................................2467
11.5.3.113 Receive descriptor active (ESW_RDAR).................................................................................... 2468
11.5.3.114 Transmit descriptor active (ESW_TDAR)...................................................................................2469
11.5.3.115 Learning records A0 & B1 (ESW_LREC0)................................................................................ 2470
11.5.3.116 Learning record B1 (ESW_LREC1)............................................................................................ 2471
11.5.3.117 Learning data available status (ESW_LSR).................................................................................2471
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11.5.4
11.5.5
Title
Page
MAC address lookup table...............................................................................................................................2472
11.5.4.1
MAC Address Lookup Entry Low (MAC_ADDRLn)................................................................ 0
11.5.4.2
MAC Address Lookup Entry High (MAC_ADDRHn)............................................................... 0
Functional Description..................................................................................................................................... 2472
11.5.5.1
VLAN Input Processing Function................................................................................................2472
11.5.5.1.1
Terms and Definitions...........................................................................................2473
11.5.5.1.2
Configuration Information.................................................................................... 2473
11.5.5.1.3
Modes of Operation.............................................................................................. 2474
11.5.5.1.3.1
Frame Processing........................................................................2474
11.5.5.1.3.2
Mode 1 — Single Tagging with Passthrough.............................2474
11.5.5.1.3.3
Mode 2 — Single Tagging with Replace................................... 2474
11.5.5.1.3.4
Mode 3 — Double Tagging with Passthrough........................... 2475
11.5.5.1.3.5
Mode 4 — Double Tagging with Replace..................................2475
11.5.5.2
IP Snooping..................................................................................................................................2475
11.5.5.3
TCP/UDP Port Number Snooping............................................................................................... 2476
11.5.5.4
VLAN Output Processing Function............................................................................................. 2476
11.5.5.4.1
11.5.5.5
Configuration Information.................................................................................... 2476
11.5.5.4.1.1
Mode 0 — Disabled....................................................................2477
11.5.5.4.1.2
Mode 1 — Strip Mode................................................................2477
11.5.5.4.1.3
Mode 2 — Tag Through Mode.................................................. 2477
11.5.5.4.1.4
Mode 3 — Transparent Mode.................................................... 2477
Frame Classification and Priority Resolution.............................................................................. 2477
11.5.5.5.1
VLAN Priority Look-Up.......................................................................................2478
11.5.5.5.2
IPv4 and IPv6 Priority Look Up........................................................................... 2478
11.5.5.5.2.1
Classification Table Programming Model..................................2479
11.5.5.5.3
Priority Resolution................................................................................................ 2480
11.5.5.5.4
Bridge Control Protocol Identification................................................................. 2481
11.5.5.6
Input Port Selection......................................................................................................................2481
11.5.5.7
Layer 2 Look-Up Engine............................................................................................................. 2481
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11.5.5.8
Title
11.5.5.7.1
Hash Code.............................................................................................................2482
11.5.5.7.2
Address Memory...................................................................................................2482
Layer 2 Lookup Tasks Overview.................................................................................................2483
11.5.5.8.1
MAC Address Lookup..........................................................................................2483
11.5.5.8.2
Forced Forwarding................................................................................................2484
11.5.5.8.3
Learning................................................................................................................ 2484
11.5.5.8.3.1
11.5.5.9
Learning Interface...................................................................... 2484
11.5.5.8.4
Migration...............................................................................................................2486
11.5.5.8.5
Aging.....................................................................................................................2486
Frame-Forwarding Tasks............................................................................................................. 2486
11.5.5.9.1
VLAN Domain Verification................................................................................. 2487
11.5.5.9.2
Broadcast/Multicast/VLAN Domain Resolution..................................................2487
11.5.5.9.2.1
VLAN Resolution Table.............................................................2488
11.5.5.9.2.2
VLAN Switching / Resolution Mechanism................................2488
11.5.5.9.3
Port Mirroring....................................................................................................... 2489
11.5.5.9.4
Protocol Snooping.................................................................................................2490
11.5.5.9.5
Bridge Protocol Frame Resolution........................................................................2490
11.5.5.9.6
11.5.5.9.7
11.5.5.10
Page
11.5.5.9.5.1
Input Port Blocking.................................................................... 2491
11.5.5.9.5.2
Input Port Learning Disable....................................................... 2491
11.5.5.9.5.3
Management Port Forwarding....................................................2491
11.5.5.9.5.4
Management Frame Forwarding................................................ 2491
Congestion Resolution.......................................................................................... 2492
11.5.5.9.6.1
Unique Destination (one input to one output)............................ 2492
11.5.5.9.6.2
Multiple Destinations (Flooding)............................................... 2492
Switching.............................................................................................................. 2492
Output Frame Queuing.................................................................................................................2493
11.5.5.10.1
Cell and Queue Concept....................................................................................... 2493
11.5.5.10.2
Write Control Module...........................................................................................2494
11.5.5.10.3
Cell Factory Module............................................................................................. 2494
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Title
11.5.5.10.4
Output Queue Manager.........................................................................................2495
11.5.5.10.4.1
11.5.5.10.5
11.5.5.11
Page
Weighted Fair Queuing Scheduling Algorithm..........................2495
Congestion Management...................................................................................... 2495
Reset and stop functions.............................................................................................................. 2496
11.5.5.11.1
Stop Controls........................................................................................................ 2496
11.5.5.11.2
Port Disable...........................................................................................................2496
11.5.5.11.3
Port 0 Input Protection.......................................................................................... 2496
11.5.5.11.4
Port 1/2 Input Protection.......................................................................................2497
11.5.5.11.5
DMA Bus Error.....................................................................................................2497
Chapter 12
Low Speed Communications and Interconnects
12.1 Flexible Controller Area Network (FlexCAN)............................................................................................................... 2499
12.1.1
12.1.2
12.1.3
Introduction...................................................................................................................................................... 2499
12.1.1.1
Overview...................................................................................................................................... 2500
12.1.1.2
FlexCAN module features........................................................................................................... 2501
12.1.1.3
Modes of operation...................................................................................................................... 2502
FlexCAN signal descriptions........................................................................................................................... 2504
12.1.2.1
CAN Rx .......................................................................................................................................2504
12.1.2.2
CAN Tx .......................................................................................................................................2504
Memory map/register definition...................................................................................................................... 2504
12.1.3.1
FlexCAN memory mapping.........................................................................................................2504
12.1.3.2
Module Configuration Register (CANx_MCR)...........................................................................2515
12.1.3.3
Control 1 register (CANx_CTRL1)............................................................................................. 2519
12.1.3.4
Free Running Timer (CANx_TIMER).........................................................................................2522
12.1.3.5
Rx Mailboxes Global Mask Register (CANx_RXMGMASK)....................................................2523
12.1.3.6
Rx 14 Mask register (CANx_RX14MASK)................................................................................ 2524
12.1.3.7
Rx 15 Mask register (CANx_RX15MASK)................................................................................ 2525
12.1.3.8
Error Counter (CANx_ECR)........................................................................................................2526
12.1.3.9
Error and Status 1 register (CANx_ESR1).................................................................................. 2527
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12.1.4
Title
Page
12.1.3.10
Interrupt Masks 2 register (CANx_IMASK2)............................................................................. 2531
12.1.3.11
Interrupt Masks 1 register (CANx_IMASK1)............................................................................. 2532
12.1.3.12
Interrupt Flags 2 register (CANx_IFLAG2)................................................................................ 2532
12.1.3.13
Interrupt Flags 1 register (CANx_IFLAG1)................................................................................ 2533
12.1.3.14
Control 2 register (CANx_CTRL2)............................................................................................. 2535
12.1.3.15
Error and Status 2 register (CANx_ESR2).................................................................................. 2539
12.1.3.16
CRC Register (CANx_CRCR).....................................................................................................2540
12.1.3.17
Rx FIFO Global Mask register (CANx_RXFGMASK).............................................................. 2541
12.1.3.18
Rx FIFO Information Register (CANx_RXFIR)......................................................................... 2542
12.1.3.19
Rx Individual Mask Registers (CANx_RXIMRn).......................................................................2542
12.1.3.20
Memory Error Control Register (CANx_MECR)........................................................................2543
12.1.3.21
Error Injection Address Register (CANx_ERRIAR)................................................................... 2545
12.1.3.22
Error Injection Data Pattern Register (CANx_ERRIDPR).......................................................... 2546
12.1.3.23
Error Injection Parity Pattern Register (CANx_ERRIPPR).........................................................2547
12.1.3.24
Error Report Address Register (CANx_RERRAR)..................................................................... 2547
12.1.3.25
Error Report Data Register (CANx_RERRDR)...........................................................................2549
12.1.3.26
Error Report Syndrome Register (CANx_RERRSYNR).............................................................2549
12.1.3.27
Error Status Register (CANx_ERRSR)........................................................................................2552
12.1.3.80
Message buffer structure.............................................................................................................. 2553
12.1.3.81
Rx FIFO structure........................................................................................................................ 2559
Functional description......................................................................................................................................2561
12.1.4.1
Transmit process.......................................................................................................................... 2562
12.1.4.2
Arbitration process....................................................................................................................... 2562
12.1.4.2.1
Lowest-number Mailbox first............................................................................... 2563
12.1.4.2.2
Highest-priority Mailbox first...............................................................................2563
12.1.4.2.3
12.1.4.3
12.1.4.2.2.1
Local Priority disabled............................................................... 2564
12.1.4.2.2.2
Local Priority enabled................................................................ 2564
Arbitration process (continued)............................................................................ 2565
Receive process............................................................................................................................2566
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Page
12.1.4.4
Matching process......................................................................................................................... 2568
12.1.4.5
Move process............................................................................................................................... 2573
12.1.4.6
12.1.5
Title
12.1.4.5.1
Move-in.................................................................................................................2573
12.1.4.5.2
Move-out...............................................................................................................2574
Data coherence............................................................................................................................. 2574
12.1.4.6.1
Transmission abort mechanism.............................................................................2574
12.1.4.6.2
Mailbox inactivation............................................................................................. 2576
12.1.4.6.3
Mailbox lock mechanism......................................................................................2576
12.1.4.7
Rx FIFO....................................................................................................................................... 2578
12.1.4.8
CAN protocol related features..................................................................................................... 2579
12.1.4.8.1
Remote frames...................................................................................................... 2579
12.1.4.8.2
Overload frames....................................................................................................2580
12.1.4.8.3
Time stamp............................................................................................................2581
12.1.4.8.4
Protocol timing..................................................................................................... 2581
12.1.4.8.5
Arbitration and matching timing...........................................................................2584
12.1.4.9
Clock domains and restrictions.................................................................................................... 2586
12.1.4.10
Modes of operation details........................................................................................................... 2586
12.1.4.10.1
Freeze mode.......................................................................................................... 2586
12.1.4.10.2
Module Disable mode........................................................................................... 2587
12.1.4.10.3
Stop mode............................................................................................................. 2588
12.1.4.11
Interrupts...................................................................................................................................... 2589
12.1.4.12
Bus interface................................................................................................................................ 2590
12.1.4.13
Detection and Correction of Memory Errors............................................................................... 2591
12.1.4.13.1
Sources of the Memory Access.............................................................................2592
12.1.4.13.2
Error Indication.....................................................................................................2592
12.1.4.13.3
Error Reporting..................................................................................................... 2593
12.1.4.13.4
Response to Errors................................................................................................ 2593
12.1.4.13.5
Error Injection.......................................................................................................2594
Initialization/application information.............................................................................................................. 2594
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12.1.5.1
Title
Page
FlexCAN initialization sequence................................................................................................. 2594
12.2 Inter-Integrated Circuit (I2C)..........................................................................................................................................2596
12.2.1
Overview.......................................................................................................................................................... 2596
12.2.2
Introduction to I2C...........................................................................................................................................2597
12.2.3
12.2.4
12.2.5
12.2.2.1
Definition: I2C module................................................................................................................ 2597
12.2.2.2
Advantages of the I2C bus........................................................................................................... 2597
12.2.2.3
Module block diagram................................................................................................................. 2597
12.2.2.4
Features........................................................................................................................................ 2598
12.2.2.5
Modes of operation...................................................................................................................... 2599
12.2.2.6
Definition: I2C conditions........................................................................................................... 2600
External signal descriptions............................................................................................................................. 2601
12.2.3.1
Signal overview............................................................................................................................2601
12.2.3.2
Detailed external signal descriptions........................................................................................... 2601
Memory map and register definition................................................................................................................2601
12.2.4.1
Register accessibility....................................................................................................................2602
12.2.4.2
Register figure conventions......................................................................................................... 2602
12.2.4.3
I2C Bus Address Register (I2Cx_IBAD).....................................................................................2604
12.2.4.4
I2C Bus Frequency Divider Register (I2Cx_IBFD).................................................................... 2605
12.2.4.5
I2C Bus Control Register (I2Cx_IBCR)...................................................................................... 2605
12.2.4.6
I2C Bus Status Register (I2Cx_IBSR)......................................................................................... 2607
12.2.4.7
I2C Bus Data I/O Register (I2Cx_IBDR).................................................................................... 2608
12.2.4.8
I2C Bus Interrupt Config Register (I2Cx_IBIC)..........................................................................2609
12.2.4.9
I2C Bus Debug Register (I2Cx_IBDBG).....................................................................................2610
Functional description......................................................................................................................................2611
12.2.5.1
Notes about module operation..................................................................................................... 2611
12.2.5.2
Transactions................................................................................................................................. 2611
12.2.5.2.1
Protocol overview................................................................................................. 2612
12.2.5.2.2
Transaction protocol definitions........................................................................... 2612
12.2.5.2.3
I2C calling address requirements..........................................................................2613
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Section number
Page
12.2.5.2.4
High-level protocol steps...................................................................................... 2613
12.2.5.2.5
START condition..................................................................................................2613
12.2.5.2.6
Slave address transmission................................................................................... 2614
12.2.5.2.7
Data transmission..................................................................................................2614
12.2.5.2.8
STOP condition.....................................................................................................2615
12.2.5.2.9
Repeated START condition..................................................................................2615
12.2.5.3
Arbitration procedure................................................................................................................... 2615
12.2.5.4
Clock behavior............................................................................................................................. 2616
12.2.5.5
12.2.6
Title
12.2.5.4.1
Clock synchronization.......................................................................................... 2616
12.2.5.4.2
Clock stretching.................................................................................................... 2617
12.2.5.4.3
Handshaking......................................................................................................... 2617
12.2.5.4.4
Clock rate and IBFD settings................................................................................2617
12.2.5.4.4.1
Timing definitions...................................................................... 2617
12.2.5.4.4.2
Divider and hold values..............................................................2618
Interrupts...................................................................................................................................... 2623
12.2.5.5.1
Interrupt vector......................................................................................................2623
12.2.5.5.2
Interrupt description..............................................................................................2624
12.2.5.6
STOP mode.................................................................................................................................. 2624
12.2.5.7
DEBUG mode.............................................................................................................................. 2625
12.2.5.8
DMA interface............................................................................................................................. 2627
Initialization/application information.............................................................................................................. 2628
12.2.6.1
Recommended interrupt service flow.......................................................................................... 2628
12.2.6.2
General programming guidelines (for both master and slave mode)...........................................2629
12.2.6.3
12.2.6.2.1
Initializing the I2C module................................................................................... 2630
12.2.6.2.2
Software response after a transfer.........................................................................2630
Programming guidelines specific to master mode....................................................................... 2631
12.2.6.3.1
Generating START............................................................................................... 2631
12.2.6.3.2
Transmit/receive sequence....................................................................................2632
12.2.6.3.3
Generating STOP.................................................................................................. 2634
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Section number
Title
Page
12.2.6.3.4
Generating repeated START.................................................................................2634
12.2.6.3.5
Loss of arbitration................................................................................................. 2634
12.2.6.4
Programming guidelines specific to slave mode..........................................................................2635
12.2.6.5
DMA application information......................................................................................................2635
12.2.6.5.1
DMA mode, master transmit.................................................................................2636
12.2.6.5.2
DMA mode, master reception...............................................................................2637
12.2.6.5.3
Exiting DMA mode, system requirement considerations..................................... 2638
12.3 Universal Asynchronous Receiver/Transmitter (UART)............................................................................................... 2642
12.3.1
12.3.2
Introduction...................................................................................................................................................... 2642
12.3.1.1
Features........................................................................................................................................ 2642
12.3.1.2
Modes of operation...................................................................................................................... 2644
Run mode.............................................................................................................. 2644
12.3.1.2.2
Stop mode............................................................................................................. 2644
UART signal descriptions................................................................................................................................ 2644
12.3.2.1
12.3.3
12.3.1.2.1
Detailed signal descriptions......................................................................................................... 2644
Memory map and registers...............................................................................................................................2645
12.3.3.1
UART Baud Rate Registers: High (UARTx_BDH).................................................................... 2653
12.3.3.2
UART Baud Rate Registers: Low (UARTx_BDL)..................................................................... 2654
12.3.3.3
UART Control Register 1 (UARTx_C1)..................................................................................... 2654
12.3.3.4
UART Control Register 2 (UARTx_C2)..................................................................................... 2656
12.3.3.5
UART Status Register 1 (UARTx_S1)........................................................................................ 2658
12.3.3.6
UART Status Register 2 (UARTx_S2)........................................................................................ 2661
12.3.3.7
UART Control Register 3 (UARTx_C3)..................................................................................... 2662
12.3.3.8
UART Data Register (UARTx_D)...............................................................................................2664
12.3.3.9
UART Match Address Registers 1 (UARTx_MA1)....................................................................2665
12.3.3.10
UART Match Address Registers 2 (UARTx_MA2)....................................................................2665
12.3.3.11
UART Control Register 4 (UARTx_C4)..................................................................................... 2666
12.3.3.12
UART Extended Data Register (UARTx_ED)............................................................................ 2666
12.3.3.13
UART Infrared Register (UARTx_IR)........................................................................................ 2667
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Section number
12.3.4
Title
Page
12.3.3.14
UART FIFO Parameters (UARTx_PFIFO)................................................................................. 2668
12.3.3.15
UART FIFO Control Register (UARTx_CFIFO)........................................................................ 2670
12.3.3.16
UART FIFO Status Register (UARTx_SFIFO)...........................................................................2671
12.3.3.17
UART FIFO Transmit Watermark (UARTx_TWFIFO)............................................................. 2672
12.3.3.18
UART FIFO Transmit Count (UARTx_TCFIFO).......................................................................2673
12.3.3.19
UART FIFO Receive Watermark (UARTx_RWFIFO)...............................................................2673
12.3.3.20
UART FIFO Receive Count (UARTx_RCFIFO)........................................................................ 2674
12.3.3.21
UART 7816 Control Register (UARTx_C7816)......................................................................... 2674
12.3.3.22
UART 7816 Interrupt Enable Register (UARTx_IE7816).......................................................... 2676
12.3.3.23
UART 7816 Interrupt Status Register (UARTx_IS7816)............................................................2677
12.3.3.24
UART 7816 Wait Parameter Register (UARTx_WP7816T1).....................................................2678
12.3.3.25
UART 7816 Wait N Register (UARTx_WN7816)......................................................................2679
12.3.3.26
UART 7816 Wait FD Register (UARTx_WF7816).................................................................... 2679
12.3.3.27
UART 7816 Error Threshold Register (UARTx_ET7816)..........................................................2680
12.3.3.28
UART 7816 Transmit Length Register (UARTx_TL7816)........................................................ 2681
Functional description......................................................................................................................................2681
12.3.4.1
12.3.4.2
Transmitter................................................................................................................................... 2681
12.3.4.1.1
Transmitter character length................................................................................. 2682
12.3.4.1.2
Transmission bit order.......................................................................................... 2682
12.3.4.1.3
Character transmission..........................................................................................2683
12.3.4.1.4
Transmitting break characters...............................................................................2684
12.3.4.1.5
Idle characters....................................................................................................... 2684
Receiver....................................................................................................................................... 2685
12.3.4.2.1
Receiver character length......................................................................................2686
12.3.4.2.2
Receiver bit ordering.............................................................................................2686
12.3.4.2.3
Character reception............................................................................................... 2686
12.3.4.2.4
Data sampling....................................................................................................... 2687
12.3.4.2.5
Framing errors.......................................................................................................2692
12.3.4.2.6
Receiving break characters................................................................................... 2692
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Section number
Title
12.3.4.2.7
12.3.4.2.8
12.3.4.2.9
Page
Infrared decoder.................................................................................................... 2693
12.3.4.2.7.1
Start bit detection........................................................................2693
12.3.4.2.7.2
Noise filtering.............................................................................2693
12.3.4.2.7.3
Low-bit detection........................................................................2694
12.3.4.2.7.4
High-bit detection.......................................................................2694
Baud rate tolerance............................................................................................... 2694
12.3.4.2.8.1
Slow data tolerance.....................................................................2694
12.3.4.2.8.2
Fast data tolerance...................................................................... 2695
Receiver wakeup...................................................................................................2696
12.3.4.2.9.1
Idle input line wakeup (C1[WAKE] = 0)................................... 2696
12.3.4.2.9.2
Address mark wakeup (C1[WAKE] = 1)................................... 2697
12.3.4.2.9.3
Match address operation.............................................................2697
12.3.4.3
Baud rate generation.................................................................................................................... 2698
12.3.4.4
Data format (non ISO-7816)........................................................................................................ 2700
12.3.4.4.1
Eight-bit configuration..........................................................................................2700
12.3.4.4.2
Nine-bit configuration...........................................................................................2700
12.3.4.4.3
Timing examples...................................................................................................2701
12.3.4.4.3.1
Eight-bit format with parity disabled......................................... 2702
12.3.4.4.3.2
Eight-bit format with parity enabled.......................................... 2702
12.3.4.4.3.3
Nine-bit format with parity disabled.......................................... 2702
12.3.4.4.3.4
Nine-bit format with parity enabled........................................... 2702
12.3.4.4.3.5
Non-memory mapped tenth bit for parity...................................2703
12.3.4.5
Single-wire operation................................................................................................................... 2703
12.3.4.6
Loop operation............................................................................................................................. 2703
12.3.4.7
ISO-7816/smartcard support........................................................................................................ 2704
12.3.4.7.1
Initial characters....................................................................................................2705
12.3.4.7.2
Protocol T = 0....................................................................................................... 2705
12.3.4.7.3
Protocol T = 1....................................................................................................... 2706
12.3.4.7.4
Wait time and guard time parameters................................................................... 2707
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Section number
12.3.4.8
Title
Page
12.3.4.7.5
Baud rate generation............................................................................................. 2708
12.3.4.7.6
UART restrictions in ISO-7816 operation............................................................2708
Infrared interface..........................................................................................................................2708
12.3.4.8.1
Infrared transmit encoder......................................................................................2709
12.3.4.8.2
Infrared receive decoder....................................................................................... 2709
12.3.5
Reset.................................................................................................................................................................2709
12.3.6
System level interrupt sources......................................................................................................................... 2710
12.3.6.1
RXEDGIF description..................................................................................................................2710
12.3.6.1.1
RxD edge detect sensitivity.................................................................................. 2710
12.3.6.1.2
Clearing RXEDGIF interrupt request................................................................... 2710
12.3.6.1.3
Exit from low-power modes................................................................................. 2710
12.3.7
DMA operation................................................................................................................................................ 2711
12.3.8
Application information................................................................................................................................... 2711
12.3.8.1
Transmit/receive data buffer operation........................................................................................ 2711
12.3.8.2
ISO-7816 initialization sequence................................................................................................. 2712
12.3.8.2.1
Transmission procedure for (C7816[TTYPE] = 0)...............................................2713
12.3.8.2.2
Transmission procedure for (C7816[TTYPE] = 1)...............................................2713
12.3.8.3
Initialization sequence (non ISO-7816)....................................................................................... 2713
12.3.8.4
Overrun (OR) flag implications................................................................................................... 2714
12.3.8.4.1
Overrun operation................................................................................................. 2715
12.3.8.5
Overrun NACK considerations.................................................................................................... 2715
12.3.8.6
Match address registers................................................................................................................ 2716
12.3.8.7
IrDA minimum pulse width......................................................................................................... 2716
12.3.8.8
Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................2716
12.3.8.9
Legacy and reverse compatibility considerations........................................................................ 2717
12.4 Serial Peripheral Interface (SPI)..................................................................................................................................... 2717
12.4.1
Introduction...................................................................................................................................................... 2717
12.4.1.1
Block Diagram............................................................................................................................. 2717
12.4.1.2
Features........................................................................................................................................ 2718
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Section number
12.4.1.3
Title
Interface configurations............................................................................................................... 2720
12.4.1.3.1
12.4.1.4
12.4.2
12.4.3
12.4.4
Page
SPI configuration.................................................................................................. 2720
Modes of Operation..................................................................................................................... 2720
12.4.1.4.1
Master Mode......................................................................................................... 2721
12.4.1.4.2
Slave Mode........................................................................................................... 2721
12.4.1.4.3
Module Disable Mode...........................................................................................2721
12.4.1.4.4
External Stop Mode.............................................................................................. 2721
Module signal descriptions.............................................................................................................................. 2722
12.4.2.1
PCS0/SS—Peripheral Chip Select/Slave Select.......................................................................... 2722
12.4.2.2
PCS1–PCS3—Peripheral Chip Selects 1–3................................................................................. 2722
12.4.2.3
PCS4—Peripheral Chip Select 4..................................................................................................2722
12.4.2.4
PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................2723
12.4.2.5
SCK—Serial Clock...................................................................................................................... 2723
12.4.2.6
SIN—Serial Input........................................................................................................................ 2723
12.4.2.7
SOUT—Serial Output..................................................................................................................2723
Memory Map/Register Definition....................................................................................................................2723
12.4.3.1
Module Configuration Register (SPIx_MCR)............................................................................. 2728
12.4.3.2
Transfer Count Register (SPIx_TCR).......................................................................................... 2731
12.4.3.3
Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)................................ 2732
12.4.3.4
Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)................... 2736
12.4.3.5
Status Register (SPIx_SR)........................................................................................................... 2738
12.4.3.6
DMA/Interrupt Request Select and Enable Register (SPIx_RSER)............................................ 2741
12.4.3.7
PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)........................................................ 2743
12.4.3.8
PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)............................................2745
12.4.3.9
POP RX FIFO Register (SPIx_POPR).........................................................................................2746
12.4.3.10
Transmit FIFO Registers (SPIx_TXFRn).................................................................................... 2746
12.4.3.11
Receive FIFO Registers (SPIx_RXFRn)......................................................................................2747
Functional description......................................................................................................................................2747
12.4.4.1
Start and Stop of module transfers............................................................................................... 2748
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Section number
12.4.4.2
Title
Serial Peripheral Interface (SPI) configuration............................................................................2749
12.4.4.2.1
Master mode..........................................................................................................2749
12.4.4.2.2
Slave mode............................................................................................................2750
12.4.4.2.3
FIFO disable operation......................................................................................... 2750
12.4.4.2.4
Transmit First In First Out (TX FIFO) buffering mechanism.............................. 2750
12.4.4.2.5
12.4.4.3
12.4.4.4
Page
12.4.4.2.4.1
Filling the TX FIFO....................................................................2751
12.4.4.2.4.2
Draining the TX FIFO................................................................ 2751
Receive First In First Out (RX FIFO) buffering mechanism................................2751
12.4.4.2.5.1
Filling the RX FIFO................................................................... 2752
12.4.4.2.5.2
Draining the RX FIFO................................................................2752
Module baud rate and clock delay generation............................................................................. 2752
12.4.4.3.1
Baud rate generator............................................................................................... 2753
12.4.4.3.2
PCS to SCK Delay (tCSC)....................................................................................2753
12.4.4.3.3
After SCK Delay (tASC)...................................................................................... 2753
12.4.4.3.4
Delay after Transfer (tDT).................................................................................... 2754
12.4.4.3.5
Peripheral Chip Select Strobe Enable (PCSS )..................................................... 2754
Transfer formats........................................................................................................................... 2756
12.4.4.4.1
Classic SPI Transfer Format (CPHA = 0)............................................................ 2756
12.4.4.4.2
Classic SPI Transfer Format (CPHA = 1)............................................................ 2757
12.4.4.4.3
Modified SPI Transfer Format (MTFE = 1, CPHA = 0)...................................... 2758
12.4.4.4.4
Modified SPI Transfer Format (MTFE = 1, CPHA = 1)...................................... 2761
12.4.4.4.5
Continuous Selection Format................................................................................2763
12.4.4.4.6
Fast Continuous Selection Format........................................................................ 2765
12.4.4.5
Continuous Serial Communications Clock.................................................................................. 2767
12.4.4.6
Slave Mode Operation Constraints.............................................................................................. 2768
12.4.4.7
Parity Generation and Check....................................................................................................... 2769
12.4.4.7.1
12.4.4.8
Parity for SPI Frames............................................................................................2769
Interrupts/DMA requests..............................................................................................................2770
12.4.4.8.1
End Of Queue interrupt request............................................................................ 2770
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Section number
12.4.4.9
12.4.5
Title
Page
12.4.4.8.2
Transmit FIFO Fill Interrupt or DMA Request.................................................... 2771
12.4.4.8.3
Transfer Complete Interrupt Request....................................................................2771
12.4.4.8.4
Transmit FIFO Underflow Interrupt Request....................................................... 2771
12.4.4.8.5
Receive FIFO Drain Interrupt or DMA Request.................................................. 2771
12.4.4.8.6
Receive FIFO Overflow Interrupt Request...........................................................2772
12.4.4.8.7
SPI Frame Parity Error Interrupt Request.............................................................2772
Power saving features.................................................................................................................. 2772
12.4.4.9.1
Stop mode (External Stop mode)..........................................................................2772
12.4.4.9.2
Module Disable mode........................................................................................... 2773
Initialization/application information.............................................................................................................. 2773
12.4.5.1
How to manage queues................................................................................................................ 2773
12.4.5.2
Switching Master and Slave mode...............................................................................................2774
12.4.5.3
Initializing Module in Master/Slave Modes.................................................................................2774
12.4.5.4
Baud rate settings......................................................................................................................... 2775
12.4.5.5
Delay settings............................................................................................................................... 2775
12.4.5.6
Calculation of FIFO pointer addresses.........................................................................................2776
12.4.5.6.1
Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO.....2777
12.4.5.6.2
Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO.....2777
Chapter 13
Timers
13.1 FlexTimer Module (FTM).............................................................................................................................................. 2779
13.1.1
Introduction...................................................................................................................................................... 2779
13.1.1.1
FlexTimer philosophy.................................................................................................................. 2779
13.1.1.2
Features........................................................................................................................................ 2780
13.1.1.3
Modes of operation...................................................................................................................... 2782
13.1.1.4
Block diagram.............................................................................................................................. 2782
13.1.2
FTM signal descriptions...................................................................................................................................2784
13.1.3
Memory map and register definition................................................................................................................2784
13.1.3.1
Memory map................................................................................................................................ 2784
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Section number
13.1.4
Title
Page
13.1.3.2
Register descriptions.................................................................................................................... 2785
13.1.3.3
Status And Control (FTMx_SC).................................................................................................. 2793
13.1.3.4
Counter (FTMx_CNT)................................................................................................................. 2794
13.1.3.5
Modulo (FTMx_MOD)................................................................................................................ 2795
13.1.3.6
Channel (n) Status And Control (FTMx_CnSC)..........................................................................2796
13.1.3.7
Channel (n) Value (FTMx_CnV)................................................................................................. 2798
13.1.3.8
Counter Initial Value (FTMx_CNTIN)........................................................................................2799
13.1.3.9
Capture And Compare Status (FTMx_STATUS)........................................................................ 2799
13.1.3.10
Features Mode Selection (FTMx_MODE).................................................................................. 2801
13.1.3.11
Synchronization (FTMx_SYNC)................................................................................................. 2803
13.1.3.12
Initial State For Channels Output (FTMx_OUTINIT).................................................................2806
13.1.3.13
Output Mask (FTMx_OUTMASK)............................................................................................. 2807
13.1.3.14
Function For Linked Channels (FTMx_COMBINE)...................................................................2809
13.1.3.15
Deadtime Insertion Control (FTMx_DEADTIME)..................................................................... 2814
13.1.3.16
FTM External Trigger (FTMx_EXTTRIG)................................................................................. 2815
13.1.3.17
Channels Polarity (FTMx_POL).................................................................................................. 2817
13.1.3.18
Fault Mode Status (FTMx_FMS).................................................................................................2819
13.1.3.19
Input Capture Filter Control (FTMx_FILTER)........................................................................... 2821
13.1.3.20
Fault Control (FTMx_FLTCTRL)............................................................................................... 2822
13.1.3.21
Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................2824
13.1.3.22
Configuration (FTMx_CONF)..................................................................................................... 2826
13.1.3.23
FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................2827
13.1.3.24
Synchronization Configuration (FTMx_SYNCONF)..................................................................2829
13.1.3.25
FTM Inverting Control (FTMx_INVCTRL)................................................................................2831
13.1.3.26
FTM Software Output Control (FTMx_SWOCTRL).................................................................. 2832
13.1.3.27
FTM PWM Load (FTMx_PWMLOAD)..................................................................................... 2834
Functional description......................................................................................................................................2835
13.1.4.1
Clock source.................................................................................................................................2836
13.1.4.1.1
Counter clock source.............................................................................................2836
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Section number
Title
Page
13.1.4.2
Prescaler....................................................................................................................................... 2837
13.1.4.3
Counter.........................................................................................................................................2837
13.1.4.4
13.1.4.3.1
Up counting...........................................................................................................2837
13.1.4.3.2
Up-down counting................................................................................................ 2840
13.1.4.3.3
Free running counter............................................................................................. 2841
13.1.4.3.4
Counter reset......................................................................................................... 2842
13.1.4.3.5
When the TOF bit is set........................................................................................ 2842
Input Capture mode......................................................................................................................2843
13.1.4.4.1
Filter for Input Capture mode............................................................................... 2844
13.1.4.5
Output Compare mode................................................................................................................. 2845
13.1.4.6
Edge-Aligned PWM (EPWM) mode........................................................................................... 2847
13.1.4.7
Center-Aligned PWM (CPWM) mode........................................................................................ 2848
13.1.4.8
Combine mode............................................................................................................................. 2850
13.1.4.8.1
Asymmetrical PWM............................................................................................. 2858
13.1.4.9
Complementary mode.................................................................................................................. 2858
13.1.4.10
Registers updated from write buffers...........................................................................................2859
13.1.4.11
13.1.4.10.1
CNTIN register update..........................................................................................2859
13.1.4.10.2
MOD register update.............................................................................................2860
13.1.4.10.3
CnV register update.............................................................................................. 2860
PWM synchronization..................................................................................................................2861
13.1.4.11.1
Hardware trigger................................................................................................... 2861
13.1.4.11.2
Software trigger.................................................................................................... 2862
13.1.4.11.3
Boundary cycle and loading points.......................................................................2862
13.1.4.11.4
MOD register synchronization..............................................................................2863
13.1.4.11.5
CNTIN register synchronization...........................................................................2866
13.1.4.11.6
C(n)V and C(n+1)V register synchronization...................................................... 2867
13.1.4.11.7
OUTMASK register synchronization................................................................... 2867
13.1.4.11.8
INVCTRL register synchronization......................................................................2870
13.1.4.11.9
SWOCTRL register synchronization....................................................................2871
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Title
Page
13.1.4.11.10 FTM counter synchronization...............................................................................2873
13.1.4.12
Inverting....................................................................................................................................... 2875
13.1.4.13
Software output control................................................................................................................2877
13.1.4.14
Deadtime insertion....................................................................................................................... 2879
13.1.4.14.1
Deadtime insertion corner cases........................................................................... 2880
13.1.4.15
Output mask................................................................................................................................. 2882
13.1.4.16
Fault control................................................................................................................................. 2882
13.1.4.16.1
Automatic fault clearing....................................................................................... 2884
13.1.4.16.2
Manual fault clearing............................................................................................ 2885
13.1.4.16.3
Fault inputs polarity control..................................................................................2886
13.1.4.17
Polarity control.............................................................................................................................2886
13.1.4.18
Initialization................................................................................................................................. 2886
13.1.4.19
Features priority........................................................................................................................... 2887
13.1.4.20
Channel trigger output................................................................................................................. 2888
13.1.4.21
Initialization trigger......................................................................................................................2889
13.1.4.22
Capture Test mode....................................................................................................................... 2891
13.1.4.23
DMA............................................................................................................................................ 2892
13.1.4.24
Dual Edge Capture mode............................................................................................................. 2893
13.1.4.25
13.1.4.24.1
One-Shot Capture mode........................................................................................2894
13.1.4.24.2
Continuous Capture mode.....................................................................................2894
13.1.4.24.3
Pulse width measurement..................................................................................... 2895
13.1.4.24.4
Period measurement..............................................................................................2897
13.1.4.24.5
Read coherency mechanism..................................................................................2899
Quadrature Decoder mode........................................................................................................... 2900
13.1.4.25.1
Quadrature Decoder boundary conditions............................................................ 2904
13.1.4.26
BDM mode...................................................................................................................................2905
13.1.4.27
Intermediate load..........................................................................................................................2906
13.1.4.28
Global time base (GTB)............................................................................................................... 2908
13.1.4.28.1
Enabling the global time base (GTB)................................................................... 2909
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Title
Page
13.1.5
Reset overview................................................................................................................................................. 2910
13.1.6
FTM Interrupts................................................................................................................................................. 2911
13.1.7
13.1.6.1
Timer Overflow Interrupt.............................................................................................................2912
13.1.6.2
Channel (n) Interrupt....................................................................................................................2912
13.1.6.3
Fault Interrupt.............................................................................................................................. 2912
Initialization Procedure.................................................................................................................................... 2912
13.2 Periodic Interrupt Timer (PIT)........................................................................................................................................2913
13.2.1
Introduction...................................................................................................................................................... 2913
13.2.1.1
Block diagram.............................................................................................................................. 2914
13.2.1.2
Features........................................................................................................................................ 2914
13.2.2
Signal description.............................................................................................................................................2915
13.2.3
Memory map/register description.................................................................................................................... 2915
13.2.4
13.2.3.1
PIT Module Control Register (PIT_MCR).................................................................................. 2917
13.2.3.2
PIT Upper Lifetime Timer Register (PIT_LTMR64H)............................................................... 2918
13.2.3.3
PIT Lower Lifetime Timer Register (PIT_LTMR64L)............................................................... 2918
13.2.3.4
Timer Load Value Register (PIT_LDVALn)...............................................................................2919
13.2.3.5
Current Timer Value Register (PIT_CVALn)............................................................................. 2919
13.2.3.6
Timer Control Register (PIT_TCTRLn)...................................................................................... 2920
13.2.3.7
Timer Flag Register (PIT_TFLGn)..............................................................................................2921
Functional description......................................................................................................................................2921
13.2.4.1
General operation......................................................................................................................... 2921
13.2.4.1.1
Timers................................................................................................................... 2922
13.2.4.1.2
Debug mode.......................................................................................................... 2923
13.2.4.2
Interrupts...................................................................................................................................... 2923
13.2.4.3
Chained timers............................................................................................................................. 2923
13.2.5
Initialization and application information........................................................................................................2923
13.2.6
Example configuration for chained timers.......................................................................................................2924
13.2.7
Example configuration for the lifetime timer.................................................................................................. 2925
13.3 Low-Power Timer (LPTMR)..........................................................................................................................................2926
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13.3.1
13.3.2
13.3.4
Page
Introduction...................................................................................................................................................... 2926
13.3.1.1
Features........................................................................................................................................ 2926
13.3.1.2
Modes of operation...................................................................................................................... 2926
LPTMR signal descriptions............................................................................................................................. 2927
13.3.2.1
13.3.3
Title
Detailed signal descriptions......................................................................................................... 2927
Memory map and register definition................................................................................................................2927
13.3.3.1
Low Power Timer Control Status Register (LPTMRx_CSR)......................................................2928
13.3.3.2
Low Power Timer Prescale Register (LPTMRx_PSR)................................................................2929
13.3.3.3
Low Power Timer Compare Register (LPTMRx_CMR).............................................................2931
13.3.3.4
Low Power Timer Counter Register (LPTMRx_CNR)............................................................... 2931
Functional description......................................................................................................................................2932
13.3.4.1
LPTMR power and reset.............................................................................................................. 2932
13.3.4.2
LPTMR clocking..........................................................................................................................2932
13.3.4.3
LPTMR prescaler/glitch filter...................................................................................................... 2932
13.3.4.3.1
Prescaler enabled.................................................................................................. 2933
13.3.4.3.2
Prescaler bypassed................................................................................................ 2933
13.3.4.3.3
Glitch filter............................................................................................................2933
13.3.4.3.4
Glitch filter bypassed............................................................................................ 2934
13.3.4.4
LPTMR compare..........................................................................................................................2934
13.3.4.5
LPTMR counter........................................................................................................................... 2934
13.3.4.6
LPTMR hardware trigger.............................................................................................................2935
13.3.4.7
LPTMR interrupt..........................................................................................................................2935
13.4 Programmable Delay Block (PDB)................................................................................................................................ 2935
13.4.1
Introduction...................................................................................................................................................... 2935
13.4.1.1
Features........................................................................................................................................ 2936
13.4.1.2
Implementation............................................................................................................................ 2936
13.4.1.3
Back-to-back acknowledgment connections................................................................................2937
13.4.1.4
Block diagram.............................................................................................................................. 2937
13.4.1.5
Modes of operation...................................................................................................................... 2939
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13.4.2
13.4.3
13.4.4
Title
Page
Memory map and register definition................................................................................................................2939
13.4.2.1
Status and Control register (PDB_SC).........................................................................................2941
13.4.2.2
Modulus register (PDB_MOD)....................................................................................................2944
13.4.2.3
Counter register (PDB_CNT)...................................................................................................... 2944
13.4.2.4
Interrupt Delay register (PDB_IDLY)......................................................................................... 2945
13.4.2.5
Channel n Control register 1 (PDB_CHnC1).............................................................................. 2945
13.4.2.6
Channel n Status register (PDB_CHnS)...................................................................................... 2946
13.4.2.7
Channel n Delay 0 register (PDB_CHnDLY0)............................................................................2947
13.4.2.8
Channel n Delay 1 register (PDB_CHnDLY1)............................................................................2948
13.4.2.9
DAC Interval Trigger n Control register (PDB_DACINTCn).................................................... 2948
13.4.2.10
DAC Interval n register (PDB_DACINTn)................................................................................. 2949
Functional description......................................................................................................................................2949
13.4.3.1
PDB pre-trigger and trigger outputs.............................................................................................2949
13.4.3.2
PDB trigger input source selection.............................................................................................. 2951
13.4.3.3
DAC interval trigger outputs........................................................................................................2952
13.4.3.4
Updating the delay registers.........................................................................................................2953
13.4.3.5
Interrupts...................................................................................................................................... 2954
13.4.3.6
DMA............................................................................................................................................ 2954
Application information................................................................................................................................... 2955
13.4.4.1
Impact of using the prescaler and multiplication factor on timing resolution............................. 2955
Chapter 14
DMA
14.1 Enhanced Direct Memory Access (eDMA)....................................................................................................................2957
14.1.1
Introduction...................................................................................................................................................... 2957
14.1.1.1
eDMA system block diagram...................................................................................................... 2957
14.1.1.2
Block parts................................................................................................................................... 2958
14.1.1.3
Features........................................................................................................................................ 2959
14.1.2
Modes of operation.......................................................................................................................................... 2960
14.1.3
Memory map/register definition...................................................................................................................... 2961
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Page
14.1.3.1
TCD memory............................................................................................................................... 2961
14.1.3.2
TCD initialization........................................................................................................................ 2961
14.1.3.3
TCD structure...............................................................................................................................2961
14.1.3.4
Reserved memory and bit fields...................................................................................................2962
14.1.3.5
Control Register (DMAx_CR)..................................................................................................... 3015
14.1.3.6
Error Status Register (DMAx_ES)...............................................................................................3018
14.1.3.7
Enable Request Register (DMAx_ERQ)......................................................................................3020
14.1.3.8
Enable Error Interrupt Register (DMAx_EEI).............................................................................3024
14.1.3.9
Clear Enable Error Interrupt Register (DMAx_CEEI)................................................................ 3027
14.1.3.10
Set Enable Error Interrupt Register (DMAx_SEEI).................................................................... 3028
14.1.3.11
Clear Enable Request Register (DMAx_CERQ)......................................................................... 3029
14.1.3.12
Set Enable Request Register (DMAx_SERQ)............................................................................. 3030
14.1.3.13
Clear DONE Status Bit Register (DMAx_CDNE)...................................................................... 3031
14.1.3.14
Set START Bit Register (DMAx_SSRT).................................................................................... 3032
14.1.3.15
Clear Error Register (DMAx_CERR).......................................................................................... 3033
14.1.3.16
Clear Interrupt Request Register (DMAx_CINT)........................................................................3034
14.1.3.17
Interrupt Request Register (DMAx_INT).................................................................................... 3034
14.1.3.18
Error Register (DMAx_ERR)...................................................................................................... 3038
14.1.3.19
Hardware Request Status Register (DMAx_HRS)...................................................................... 3042
14.1.3.20
Channel n Priority Register (DMAx_DCHPRIn)........................................................................ 3048
14.1.3.21
TCD Source Address (DMAx_TCDn_SADDR)......................................................................... 3049
14.1.3.22
TCD Signed Source Address Offset (DMAx_TCDn_SOFF)...................................................... 3050
14.1.3.23
TCD Transfer Attributes (DMAx_TCDn_ATTR)....................................................................... 3050
14.1.3.24
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMAx_TCDn_NBYTES_MLNO).............................................................................................3051
14.1.3.25
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMAx_TCDn_NBYTES_MLOFFNO)..................................................................................... 3052
14.1.3.26
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMAx_TCDn_NBYTES_MLOFFYES)................................................................................... 3053
14.1.3.27
TCD Last Source Address Adjustment (DMAx_TCDn_SLAST)............................................... 3054
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Title
Page
14.1.3.28
TCD Destination Address (DMAx_TCDn_DADDR)................................................................. 3055
14.1.3.29
TCD Signed Destination Address Offset (DMAx_TCDn_DOFF).............................................. 3055
14.1.3.30
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMAx_TCDn_CITER_ELINKYES).........................................................................................3056
14.1.3.31
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMAx_TCDn_CITER_ELINKNO)...........................................................................................3057
14.1.3.32
TCD Last Destination Address Adjustment/Scatter Gather Address
(DMAx_TCDn_DLASTSGA)..................................................................................................... 3058
14.1.3.33
TCD Control and Status (DMAx_TCDn_CSR)...........................................................................3059
14.1.3.34
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMAx_TCDn_BITER_ELINKYES).........................................................................................3061
14.1.3.35
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMAx_TCDn_BITER_ELINKNO)...........................................................................................3062
14.1.4
14.1.5
Functional description......................................................................................................................................3063
14.1.4.1
eDMA basic data flow................................................................................................................. 3063
14.1.4.2
Fault reporting and handling........................................................................................................ 3066
14.1.4.3
Channel preemption..................................................................................................................... 3069
14.1.4.4
Performance................................................................................................................................. 3069
14.1.4.4.1
Peak transfer rates................................................................................................. 3069
14.1.4.4.2
Peak request rates..................................................................................................3070
14.1.4.4.3
eDMA performance example................................................................................3072
Initialization/application information.............................................................................................................. 3073
14.1.5.1
eDMA initialization..................................................................................................................... 3073
14.1.5.2
Programming errors..................................................................................................................... 3075
14.1.5.3
Arbitration mode considerations.................................................................................................. 3076
14.1.5.4
14.1.5.3.1
Fixed group arbitration, Fixed channel arbitration............................................... 3076
14.1.5.3.2
Fixed group arbitration, Round-robin channel arbitration....................................3077
Performing DMA transfers.......................................................................................................... 3077
14.1.5.4.1
Single request........................................................................................................3077
14.1.5.4.2
Multiple requests...................................................................................................3079
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Title
14.1.5.4.3
14.1.5.5
Page
Using the modulo feature......................................................................................3081
Monitoring transfer descriptor status........................................................................................... 3081
14.1.5.5.1
Testing for minor loop completion....................................................................... 3081
14.1.5.5.2
Reading the transfer descriptors of active channels..............................................3082
14.1.5.5.3
Checking channel preemption status.................................................................... 3082
14.1.5.6
Channel Linking...........................................................................................................................3083
14.1.5.7
Dynamic programming................................................................................................................ 3084
14.1.5.7.1
Dynamically changing the channel priority..........................................................3084
14.1.5.7.2
Dynamic channel linking...................................................................................... 3084
14.1.5.7.3
Dynamic scatter/gather......................................................................................... 3085
14.1.5.7.3.1
Method 1 (channel not using major loop channel linking).........3086
14.1.5.7.3.2
Method 2 (channel using major loop channel linking)...............3087
14.2 Direct Memory Access Multiplexer (DMAMUX)......................................................................................................... 3088
14.2.1
Introduction...................................................................................................................................................... 3088
14.2.1.1
Overview...................................................................................................................................... 3088
14.2.1.2
Features........................................................................................................................................ 3088
14.2.1.3
Modes of operation...................................................................................................................... 3089
14.2.2
External signal description...............................................................................................................................3089
14.2.3
Memory map/register definition...................................................................................................................... 3090
14.2.3.1
14.2.4
14.2.5
Channel Configuration register (DMAMUXx_CHCFGn).......................................................... 3093
Functional description......................................................................................................................................3094
14.2.4.1
DMA channels with periodic triggering capability......................................................................3094
14.2.4.2
DMA channels with no triggering capability...............................................................................3096
14.2.4.3
Always-enabled DMA sources.................................................................................................... 3096
Initialization/application information.............................................................................................................. 3098
14.2.5.1
Reset.............................................................................................................................................3098
14.2.5.2
Enabling and configuring sources................................................................................................3098
Chapter 15
Audio
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Section number
Title
Page
15.1 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)........................................................................ 3103
15.1.1
Introduction...................................................................................................................................................... 3103
15.1.1.1
Features........................................................................................................................................ 3103
15.1.1.2
Block diagram.............................................................................................................................. 3103
15.1.1.3
Modes of operation...................................................................................................................... 3104
15.1.1.3.1
Run mode.............................................................................................................. 3104
15.1.1.3.2
Stop modes............................................................................................................3104
15.1.1.3.3
Debug mode.......................................................................................................... 3104
15.1.2
External signals................................................................................................................................................ 3105
15.1.3
Memory map and register definition................................................................................................................3105
15.1.4
15.1.3.1
SAI Transmit Control Register (I2Sx_TCSR)............................................................................. 3109
15.1.3.2
SAI Transmit Configuration 1 Register (I2Sx_TCR1)................................................................ 3112
15.1.3.3
SAI Transmit Configuration 2 Register (I2Sx_TCR2)................................................................ 3113
15.1.3.4
SAI Transmit Configuration 3 Register (I2Sx_TCR3)................................................................ 3114
15.1.3.5
SAI Transmit Configuration 4 Register (I2Sx_TCR4)................................................................ 3115
15.1.3.6
SAI Transmit Configuration 5 Register (I2Sx_TCR5)................................................................ 3116
15.1.3.7
SAI Transmit Data Register (I2Sx_TDRn).................................................................................. 3117
15.1.3.8
SAI Transmit FIFO Register (I2Sx_TFRn)................................................................................. 3118
15.1.3.9
SAI Transmit Mask Register (I2Sx_TMR).................................................................................. 3118
15.1.3.10
SAI Receive Control Register (I2Sx_RCSR)...............................................................................3119
15.1.3.11
SAI Receive Configuration 1 Register (I2Sx_RCR1)..................................................................3122
15.1.3.12
SAI Receive Configuration 2 Register (I2Sx_RCR2)..................................................................3123
15.1.3.13
SAI Receive Configuration 3 Register (I2Sx_RCR3)..................................................................3124
15.1.3.14
SAI Receive Configuration 4 Register (I2Sx_RCR4)..................................................................3125
15.1.3.15
SAI Receive Configuration 5 Register (I2Sx_RCR5)..................................................................3127
15.1.3.16
SAI Receive Data Register (I2Sx_RDRn)................................................................................... 3127
15.1.3.17
SAI Receive FIFO Register (I2Sx_RFRn)...................................................................................3128
15.1.3.18
SAI Receive Mask Register (I2Sx_RMR)................................................................................... 3128
Functional description......................................................................................................................................3129
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15.1.4.1
15.1.4.2
15.1.4.3
Title
Page
SAI clocking................................................................................................................................ 3129
15.1.4.1.1
Audio master clock............................................................................................... 3129
15.1.4.1.2
Bit clock................................................................................................................ 3130
15.1.4.1.3
Bus clock...............................................................................................................3130
SAI resets..................................................................................................................................... 3130
15.1.4.2.1
Software reset........................................................................................................3130
15.1.4.2.2
FIFO reset............................................................................................................. 3131
Synchronous modes..................................................................................................................... 3131
15.1.4.3.1
Synchronous mode................................................................................................3131
15.1.4.4
Frame sync configuration.............................................................................................................3132
15.1.4.5
Data FIFO.................................................................................................................................... 3132
15.1.4.5.1
Data alignment...................................................................................................... 3132
15.1.4.5.2
FIFO pointers........................................................................................................ 3133
15.1.4.6
Word mask register...................................................................................................................... 3134
15.1.4.7
Interrupts and DMA requests....................................................................................................... 3134
15.1.4.7.1
FIFO request flag.................................................................................................. 3134
15.1.4.7.2
FIFO warning flag.................................................................................................3135
15.1.4.7.3
FIFO error flag......................................................................................................3135
15.1.4.7.4
Sync error flag.......................................................................................................3136
15.1.4.7.5
Word start flag...................................................................................................... 3136
15.2 Enhanced Serial Audio Interface (ESAI)........................................................................................................................3136
15.2.1
15.2.2
Overview.......................................................................................................................................................... 3136
15.2.1.1
Features........................................................................................................................................ 3138
15.2.1.2
Modes of Operation..................................................................................................................... 3138
15.2.1.2.1
Normal/Network/On-Demand Mode Selection.................................................... 3138
15.2.1.2.2
Synchronous/Asynchronous Operating Modes.....................................................3139
15.2.1.2.3
Frame Sync Selection........................................................................................... 3139
15.2.1.2.4
Shift Direction Selection.......................................................................................3140
External Signals............................................................................................................................................... 3140
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Section number
15.2.3
15.2.4
15.2.5
Title
Page
15.2.2.1
Serial Transmit 0 Data Pin........................................................................................................... 3141
15.2.2.2
Serial Transmit 1 Data Pin........................................................................................................... 3141
15.2.2.3
Serial Transmit 2/Receive 3 Data Pin.......................................................................................... 3141
15.2.2.4
Serial Transmit 3/Receive 2 Data Pin.......................................................................................... 3142
15.2.2.5
Serial Transmit 4/Receive 1 Data Pin.......................................................................................... 3142
15.2.2.6
Serial Transmit 5/Receive 0 Data Pin.......................................................................................... 3143
15.2.2.7
Receiver Serial Clock...................................................................................................................3143
15.2.2.8
Transmitter Serial Clock.............................................................................................................. 3144
15.2.2.9
Frame Sync for Receiver..............................................................................................................3146
15.2.2.10
Frame Sync for Transmitter......................................................................................................... 3146
15.2.2.11
High Frequency Clock for Transmitter........................................................................................ 3146
15.2.2.12
High Frequency Clock for Receiver............................................................................................ 3147
15.2.2.13
Serial I/O Flags............................................................................................................................ 3147
Functional Description..................................................................................................................................... 3148
15.2.3.1
ESAI After Reset......................................................................................................................... 3148
15.2.3.2
ESAI Interrupt Requests.............................................................................................................. 3149
15.2.3.3
ESAI DMA Requests from the FIFOs......................................................................................... 3150
15.2.3.4
ESAI Transmit and Receive Shift Registers................................................................................ 3151
15.2.3.4.1
ESAI Transmit Shift Registers............................................................................. 3151
15.2.3.4.2
ESAI Receive Shift Registers............................................................................... 3154
Initialization Information................................................................................................................................. 3154
15.2.4.1
ESAI Initialization....................................................................................................................... 3154
15.2.4.2
ESAI Initialization Examples.......................................................................................................3155
15.2.4.2.1
Initializing the ESAI using Personal Reset...........................................................3155
15.2.4.2.2
Initializing the ESAI Transmitter Section.............................................................3156
15.2.4.2.3
Initializing the ESAI Receiver Section................................................................. 3156
ESAI Memory Map/Register Definition..........................................................................................................3157
15.2.5.1
ESAI Transmit Data Register (ESAI_ETDR)............................................................................. 3159
15.2.5.2
ESAI Receive Data Register (ESAI_ERDR)...............................................................................3159
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Page
15.2.5.3
ESAI Control Register (ESAI_ECR)........................................................................................... 3160
15.2.5.4
ESAI Status Register (ESAI_ESR)..............................................................................................3161
15.2.5.5
Transmit FIFO Configuration Register (ESAI_TFCR)............................................................... 3163
15.2.5.6
Transmit FIFO Status Register (ESAI_TFSR)............................................................................ 3165
15.2.5.7
Receive FIFO Configuration Register (ESAI_RFCR).................................................................3166
15.2.5.8
Receive FIFO Status Register (ESAI_RFSR)..............................................................................3168
15.2.5.9
Transmit Data Register n (ESAI_TXn)....................................................................................... 3169
15.2.5.10
ESAI Transmit Slot Register (ESAI_TSR)..................................................................................3169
15.2.5.11
Receive Data Register n (ESAI_RXn).........................................................................................3170
15.2.5.12
Serial Audio Interface Status Register (ESAI_SAISR)............................................................... 3171
15.2.5.13
Serial Audio Interface Control Register (ESAI_SAICR)............................................................ 3173
15.2.5.14
Transmit Control Register (ESAI_TCR)..................................................................................... 3176
15.2.5.15
Transmit Clock Control Register (ESAI_TCCR)........................................................................ 3183
15.2.5.16
Receive Control Register (ESAI_RCR).......................................................................................3187
15.2.5.17
Receive Clock Control Register (ESAI_RCCR)......................................................................... 3191
15.2.5.18
Transmit Slot Mask Register A (ESAI_TSMA).......................................................................... 3194
15.2.5.19
Transmit Slot Mask Register B (ESAI_TSMB).......................................................................... 3195
15.2.5.20
Receive Slot Mask Register A (ESAI_RSMA)........................................................................... 3196
15.2.5.21
Receive Slot Mask Register B (ESAI_RSMB)............................................................................3197
15.2.5.22
Port C Direction Register (ESAI_PRRC).................................................................................... 3198
15.2.5.23
Port C Control Register (ESAI_PCRC)....................................................................................... 3198
15.3 Asynchronous Sample Rate Converter (ASRC)............................................................................................................. 3199
15.3.1
Introduction ..................................................................................................................................................... 3199
15.3.1.1
Overview...................................................................................................................................... 3201
15.3.1.2
Features........................................................................................................................................ 3202
15.3.1.3
Modes of Operation..................................................................................................................... 3202
15.3.1.3.1
Data Transfer Schemes......................................................................................... 3202
15.3.1.3.1.1
Data Input Modes....................................................................... 3202
15.3.1.3.1.2
Data Output Modes.....................................................................3204
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Title
15.3.1.3.2
Page
Word Alignment Supported..................................................................................3205
15.3.1.3.2.1
Input Data Alignment Modes..................................................... 3205
15.3.1.3.2.2
Output Data Alignment Modes.................................................. 3205
15.3.2
Interrupts.......................................................................................................................................................... 3206
15.3.3
DMA requests.................................................................................................................................................. 3206
15.3.4
Programmable Registers.................................................................................................................................. 3207
15.3.4.1
ASRC Control Register (ASRC_ASRCTR)................................................................................ 3210
15.3.4.2
ASRC Interrupt Enable Register (ASRC_ASRIER)................................................................... 3212
15.3.4.3
ASRC Channel Number Configuration Register (ASRC_ASRCNCR)...................................... 3214
15.3.4.4
ASRC Filter Configuration Status Register (ASRC_ASRCFG)................................................. 3216
15.3.4.5
ASRC Clock Source Register (ASRC_ASRCSR).......................................................................3218
15.3.4.6
ASRC Clock Divider Register 1 (ASRC_ASRCDR1)................................................................ 3222
15.3.4.7
ASRC Clock Divider Register 2 (ASRC_ASRCDR2)................................................................ 3223
15.3.4.8
ASRC Status Register (ASRC_ASRSTR)................................................................................... 3224
15.3.4.9
ASRC Parameter Register (ASRC_ASRPMn)............................................................................ 3227
15.3.4.10
ASRC ASRC Task Queue FIFO Register 1 (ASRC_ASRTFR1)............................................... 3228
15.3.4.11
ASRC Channel Counter Register (ASRC_ASRCCR).................................................................3229
15.3.4.12
ASRC Data Input Register for Pair x (ASRC_ASRDIn)............................................................. 3230
15.3.4.13
ASRC Data Output Register for Pair x (ASRC_ASRDOn).........................................................3230
15.3.4.14
ASRC Ideal Ratio for Pair A-High Part (ASRC_ASRIDRHA).................................................. 3231
15.3.4.15
ASRC Ideal Ratio for Pair A -Low Part (ASRC_ASRIDRLA).................................................. 3231
15.3.4.16
ASRC Ideal Ratio for Pair B-High Part (ASRC_ASRIDRHB)...................................................3232
15.3.4.17
ASRC Ideal Ratio for Pair B-Low Part (ASRC_ASRIDRLB)....................................................3232
15.3.4.18
ASRC Ideal Ratio for Pair C-High Part (ASRC_ASRIDRHC)...................................................3233
15.3.4.19
ASRC Ideal Ratio for Pair C-Low Part (ASRC_ASRIDRLC)....................................................3233
15.3.4.20
ASRC 76kHz Period in terms of ASRC processing clock (ASRC_ASR76K)............................3234
15.3.4.21
ASRC 56kHz Period in terms of ASRC processing clock (ASRC_ASR56K)............................3234
15.3.4.22
ASRC Misc Control Register for Pair A (ASRC_ASRMCRA).................................................. 3235
15.3.4.23
ASRC FIFO Status Register for Pair A (ASRC_ASRFSTA)......................................................3237
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15.3.5
Title
15.3.4.24
ASRC Misc Control Register for Pair B (ASRC_ASRMCRB).................................................. 3238
15.3.4.25
ASRC FIFO Status Register for Pair B (ASRC_ASRFSTB)...................................................... 3240
15.3.4.26
ASRC Misc Control Register for Pair C (ASRC_ASRMCRC).................................................. 3241
15.3.4.27
ASRC FIFO Status Register for Pair C (ASRC_ASRFSTC)...................................................... 3243
15.3.4.28
ASRC Misc Control Register 1 for Pair x (ASRC_ASRMCR1n)............................................... 3244
Functional Description..................................................................................................................................... 3245
15.3.5.1
Algorithm Description................................................................................................................. 3245
15.3.5.1.1
Signal Processing Flow.........................................................................................3245
15.3.5.1.2
Operation of the Filter...........................................................................................3248
15.3.5.1.2.1
15.3.6
Page
Support of Physical Clocks........................................................ 3249
Startup Procedure............................................................................................................................................. 3251
15.4 Sony/Philips Digital Interface (SPDIF).......................................................................................................................... 3255
15.4.1
Introduction ..................................................................................................................................................... 3255
15.4.1.1
Overview...................................................................................................................................... 3257
15.4.2
External Signal Description............................................................................................................................. 3257
15.4.3
Functional Description..................................................................................................................................... 3257
15.4.3.1
SPDIF Receiver............................................................................................................................3257
15.4.3.1.1
Audio Data Reception...........................................................................................3258
15.4.3.1.1.1
SPDIF receiver data registers - Behavior on overrun, underrun 3258
15.4.3.1.1.2
SPDIF receiver data registers - Automatic resynchronization
of FIFOs......................................................................................3259
15.4.3.1.1.3
15.4.3.1.2
Channel Status Reception..................................................................................... 3261
15.4.3.1.2.1
15.4.3.1.3
Application Note........................................................................ 3259
Channel Status Interrupt............................................................. 3261
User Bit Reception................................................................................................3261
15.4.3.1.3.1
Behavior of U Channel receive interface on incoming CD U
Channel Sub-code in SPDIF receiver.........................................3261
15.4.3.1.3.2
Behavior of U Channel receive interface on incoming non-CD
data............................................................................................. 3263
15.4.3.1.4
Validity Flag Reception........................................................................................ 3263
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Section number
15.4.3.2
15.4.4
Title
Page
15.4.3.1.5
SPDIF Receiver Interrupt Exception Definition...................................................3264
15.4.3.1.6
Standards Compliance.......................................................................................... 3264
15.4.3.1.7
SPDIF PLOCK Detection and Rxclk Output........................................................3265
15.4.3.1.8
Measuring Frequency of SPDIF_RxClk...............................................................3265
SPDIF Transmitter....................................................................................................................... 3266
15.4.3.2.1
Audio Data Transmission..................................................................................... 3266
15.4.3.2.2
Channel Status Transmission................................................................................3267
15.4.3.2.3
Validity Flag Transmission...................................................................................3267
Programmable Registers.................................................................................................................................. 3267
15.4.4.1
SPDIF Configuration Register (SPDIF_SCR)............................................................................. 3269
15.4.4.2
CDText Control Register (SPDIF_SRCD).................................................................................. 3271
15.4.4.3
PhaseConfig Register (SPDIF_SRPC).........................................................................................3272
15.4.4.4
InterruptEn Register (SPDIF_SIE).............................................................................................. 3274
15.4.4.5
InterruptStat Register (SPDIF_SIS).............................................................................................3277
15.4.4.6
InterruptClear Register (SPDIF_SIC).......................................................................................... 3280
15.4.4.7
SPDIFRxLeft Register (SPDIF_SRL)......................................................................................... 3282
15.4.4.8
SPDIFRxRight Register (SPDIF_SRR).......................................................................................3282
15.4.4.9
SPDIFRxCChannel_h Register (SPDIF_SRCSH).......................................................................3283
15.4.4.10
SPDIFRxCChannel_l Register (SPDIF_SRCSL)........................................................................ 3283
15.4.4.11
UchannelRx Register (SPDIF_SRU)........................................................................................... 3284
15.4.4.12
QchannelRx Register (SPDIF_SRQ)........................................................................................... 3284
15.4.4.13
SPDIFTxLeft Register (SPDIF_STL)..........................................................................................3285
15.4.4.14
SPDIFTxRight Register (SPDIF_STR)....................................................................................... 3285
15.4.4.15
SPDIFTxCChannelCons_h Register (SPDIF_STCSCH)............................................................ 3286
15.4.4.16
SPDIFTxCChannelCons_l Register (SPDIF_STCSCL)............................................................. 3286
15.4.4.17
FreqMeas Register (SPDIF_SRFM)............................................................................................ 3287
15.4.4.18
SPDIFTxClk Register (SPDIF_STC).......................................................................................... 3287
Chapter 16
Display
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Section number
Title
Page
16.1 Display Control Unit (DCU)...........................................................................................................................................3289
16.1.1
16.1.2
Introduction...................................................................................................................................................... 3289
16.1.1.1
Overview...................................................................................................................................... 3289
16.1.1.2
Features........................................................................................................................................ 3291
16.1.1.3
Modes of Operation..................................................................................................................... 3292
External Signal Description............................................................................................................................. 3293
16.1.2.1
Overview...................................................................................................................................... 3293
16.1.2.2
Detailed Signal Descriptions........................................................................................................3293
16.1.3
DCU4 Memory Map........................................................................................................................................ 3294
16.1.4
Memory Map and Registers............................................................................................................................. 3294
16.1.4.1
Control Descriptor Cursor 1 Register (DCUx_CTRLDESCCURSOR1).................................... 3352
16.1.4.2
Control Descriptor Cursor 2 Register (DCUx_CTRLDESCCURSOR2).................................... 3352
16.1.4.3
Control Descriptor Cursor 3 Register (DCUx_CTRLDESCCURSOR3).................................... 3353
16.1.4.4
Control Descriptor Cursor 4 Register (DCUx_CTRLDESCCURSOR4).................................... 3354
16.1.4.5
DCU4 Mode Register (DCUx_DCU_MODE)............................................................................ 3355
16.1.4.6
Background Register (DCUx_BGND).........................................................................................3357
16.1.4.7
Display Size Register (DCUx_DISP_SIZE)................................................................................ 3358
16.1.4.8
Horizontal Sync Parameter Register (DCUx_HSYN_PARA).....................................................3358
16.1.4.9
Vertical Sync Parameter Register (DCUx_VSYN_PARA).........................................................3359
16.1.4.10
Synchronize Polarity Register (DCUx_SYNPOL)...................................................................... 3361
16.1.4.11
Threshold Register (DCUx_THRESHOLD)............................................................................... 3362
16.1.4.12
Interrupt Status Register (DCUx_INT_STATUS)....................................................................... 3363
16.1.4.13
Interrupt Mask Register (DCUx_INT_MASK)........................................................................... 3365
16.1.4.14
COLBAR_1 Register (DCUx_COLBAR_1)............................................................................... 3368
16.1.4.15
COLBAR_2 Register (DCUx_COLBAR_2)............................................................................... 3369
16.1.4.16
COLBAR_3 Register (DCUx_COLBAR_3)............................................................................... 3369
16.1.4.17
COLBAR_4 Register (DCUx_COLBAR_4)............................................................................... 3370
16.1.4.18
COLBAR_5 Register (DCUx_COLBAR_5)............................................................................... 3371
16.1.4.19
COLBAR_6 Register (DCUx_COLBAR_6)............................................................................... 3371
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Page
16.1.4.20
COLBAR_7 Register (DCUx_COLBAR_7)............................................................................... 3372
16.1.4.21
COLBAR_8 Register (DCUx_COLBAR_8)............................................................................... 3373
16.1.4.22
Divide Ratio Register (DCUx_DIV_RATIO)..............................................................................3373
16.1.4.23
Sign Calculation 1 Register (DCUx_SIGN_CALC_1)................................................................3374
16.1.4.24
Sign Calculation 2 Register (DCUx_SIGN_CALC_2)................................................................3374
16.1.4.25
CRC Value Register (DCUx_CRC_VAL)...................................................................................3375
16.1.4.26
Parameter Error Status 1 Register (DCUx_PARR_ERR_STATUS1).........................................3375
16.1.4.27
Parameter Error Status 2 Register (DCUx_PARR_ERR_STATUS2).........................................3376
16.1.4.28
Parameter Error Status 3 Register (DCUx_PARR_ERR_STATUS3).........................................3377
16.1.4.29
Mask Parameter Error Status 1 Register (DCUx_MASK_PARR_ERR_STATUS1)................. 3378
16.1.4.30
Mask Parameter Error Status 2 Register (DCUx_MASK_PARR_ERR_STATUS2)................. 3378
16.1.4.31
Mask Parameter Error Status 3 Register (DCUx_MASK_PARR_ERR_STATUS3)................. 3379
16.1.4.32
Threshold Input 1 Register (DCUx_THRESHOLD_INP_BUF_1).............................................3380
16.1.4.33
Threshold Input 2 Register (DCUx_THRESHOLD_INP_BUF_2).............................................3381
16.1.4.34
Threshold Input 3 Register (DCUx_THRESHOLD_INP_BUF_3).............................................3382
16.1.4.35
LUMA Component Register (DCUx_LUMA_COMP)............................................................... 3383
16.1.4.36
Red Chroma Components Register (DCUx_CHROMA_RED).................................................. 3384
16.1.4.37
Green Chroma Components Register (DCUx_CHROMA_GREEN)..........................................3384
16.1.4.38
Blue Chroma Components Register (DCUx_CHROMA_BLUE)...............................................3385
16.1.4.39
CRC Position Register (DCUx_CRC_POS)................................................................................ 3386
16.1.4.40
Layer Interpolation Enable Register (DCUx_LYR_INTPOL_EN).............................................3386
16.1.4.41
Layer Luminance Component Register (DCUx_LYR_LUMA_COMP).................................... 3387
16.1.4.42
Layer Chroma Red Register (DCUx_LYR_CHRM_RED)......................................................... 3388
16.1.4.43
Layer Chroma Green Register (DCUx_LYR_CHRM_GRN)..................................................... 3388
16.1.4.44
Layer Chroma Blue Register (DCUx_LYR_CHRM_BLUE)..................................................... 3389
16.1.4.45
Compression Image Size Register (DCUx_COMP_IMSIZE).....................................................3390
16.1.4.46
Update Mode Register (DCUx_UPDATE_MODE).................................................................... 3390
16.1.4.47
Underrun Register (DCUx_UNDERRUN).................................................................................. 3391
16.1.4.48
Global Protection Register (DCUx_GLBL_PROTECT)............................................................. 3392
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16.1.5
Title
Page
16.1.4.49
Soft Lock Bit Layer 0 Register (DCUx_SFT_LCK_BIT_L0).....................................................3393
16.1.4.50
Soft Lock Bit Layer 1 Register (DCUx_SFT_LCK_BIT_L1).....................................................3395
16.1.4.51
Soft Lock Display Size Register (DCUx_SFT_LCK_DISP_SIZE)............................................ 3397
16.1.4.52
Soft Lock Hsync/Vsync Parameter Register (DCUx_SFT_LCK_HS_VS_PARA).................... 3398
16.1.4.53
Soft Lock POL Register (DCUx_SFT_LCK_POL).....................................................................3399
16.1.4.54
Soft Lock L0 Transparency Register (DCUx_SFT_LCK_L0_TRANSP)...................................3400
16.1.4.55
Soft Lock L1 Transparency Register (DCUx_SFT_LCK_L1_TRANSP)...................................3401
16.1.4.56
Control Descriptor Ln_0 Register (DCUx_CTRLDESCLn_1)................................................... 3402
16.1.4.57
Control Descriptor Ln_1 Register (DCUx_CTRLDESCLn_2)................................................... 3403
16.1.4.58
Control Descriptor Ln_2 Register (DCUx_CTRLDESCLn_3)................................................... 3403
16.1.4.59
Control Descriptor Ln_3 Register (DCUx_CTRLDESCLn_4)................................................... 3404
16.1.4.60
Control Descriptor Ln_4 Register (DCUx_CTRLDESCLn_5)................................................... 3406
16.1.4.61
Control Descriptor Ln_5 Register (DCUx_CTRLDESCLn_6)................................................... 3406
16.1.4.62
Control Descriptor Ln_6 Register (DCUx_CTRLDESCLn_7)................................................... 3407
16.1.4.63
Control Descriptor Ln_7 Register (DCUx_CTRLDESCLn_8)................................................... 3408
16.1.4.64
Control Descriptor Ln_8 Register (DCUx_CTRLDESCLn_9)................................................... 3408
Functional Description..................................................................................................................................... 3409
16.1.5.1
Graphic sources............................................................................................................................3409
16.1.5.2
TFT LCD panel configuration..................................................................................................... 3409
16.1.5.3
DCU4 Mode selection and background color..............................................................................3411
16.1.5.4
Layer configuration and blending................................................................................................ 3412
16.1.5.4.1
Blending priority of layers.................................................................................... 3413
16.1.5.4.2
Transfer of DCU Configuration............................................................................3416
16.1.5.4.3
Control Descriptors...............................................................................................3417
16.1.5.4.4
Layer size and positioning.................................................................................... 3417
16.1.5.4.5
Graphics and data format...................................................................................... 3418
16.1.5.4.6
Alpha and Chroma-key blending.......................................................................... 3422
16.1.5.4.7
Transparency mode and blending......................................................................... 3429
16.1.5.4.8
Luminance mode...................................................................................................3432
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Section number
Title
16.1.5.4.9
16.1.7
16.1.8
Hardware cursor........................................................................................................................... 3434
16.1.5.6
CLUT/Tile RAM..........................................................................................................................3435
16.1.5.7
Gamma correction........................................................................................................................3436
16.1.5.8
Temporal Dithering......................................................................................................................3437
16.1.5.9
Special DDR Mode...................................................................................................................... 3439
16.1.5.10
Run Length Encoding (RLE) Mode.............................................................................................3439
RLE Decoding Scheme.........................................................................................3440
Timing, Error and Interrupt Management........................................................................................................3441
16.1.6.1
Synchronizing to panel frame rate............................................................................................... 3441
16.1.6.2
Managing the DCU4 FIFOs and DMA activity...........................................................................3442
16.1.6.3
Error detection..............................................................................................................................3444
16.1.6.4
Interrupt generation......................................................................................................................3444
Register protection........................................................................................................................................... 3446
16.1.7.1
Operation of scheme.................................................................................................................... 3446
16.1.7.2
List of protected registers.............................................................................................................3446
Safety Mode..................................................................................................................................................... 3447
16.1.8.1
16.1.9
Tile mode.............................................................................................................. 3432
16.1.5.5
16.1.5.10.1
16.1.6
Page
CRC Area Description................................................................................................................. 3449
16.1.8.1.1
Relationship between various input signals..........................................................3449
16.1.8.1.2
Features................................................................................................................. 3450
16.1.8.1.3
Summary of Operation..........................................................................................3451
DCU4 Initialization..........................................................................................................................................3451
16.2 LCD Driver (LCD)......................................................................................................................................................... 3452
16.2.1
16.2.2
Introduction...................................................................................................................................................... 3452
16.2.1.1
Overview...................................................................................................................................... 3452
16.2.1.2
Features........................................................................................................................................ 3453
16.2.1.3
Modes of Operation..................................................................................................................... 3454
External Signal Description............................................................................................................................. 3454
16.2.2.1
Detailed Signal Descriptions........................................................................................................3454
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Section number
16.2.3
16.2.4
Title
Page
Memory Map and Registers............................................................................................................................. 3455
16.2.3.1
LCD Control Register (LCD_LCDCR)....................................................................................... 3456
16.2.3.2
LCD Prescaler Control Register (LCD_LCDPCR)..................................................................... 3458
16.2.3.3
LCD Contrast Control Register (LCD_LCDCCR)...................................................................... 3459
16.2.3.4
LCD Frontplane Enable Register 0 (LCD_ENFPR0)..................................................................3459
16.2.3.5
LCD Frontplane Enable Register 1 (LCD_ENFPR1)..................................................................3460
16.2.3.6
LCDRAM (Location 0) (LCD_LCDRAM0)............................................................................... 3460
16.2.3.7
LCDRAM Location 1 (LCD_LCDRAM1)..................................................................................3461
16.2.3.8
LCDRAM Location 2 (LCD_LCDRAM2)..................................................................................3462
16.2.3.9
LCDRAM Location 3 (LCD_LCDRAM3)..................................................................................3462
16.2.3.10
LCDRAM Location 4 (LCD_LCDRAM4)..................................................................................3463
16.2.3.11
LCDRAM Location 5 (LCD_LCDRAM5)..................................................................................3464
16.2.3.12
LCDRAM Location 6 (LCD_LCDRAM6)..................................................................................3464
16.2.3.13
LCDRAM Location 7 (LCD_LCDRAM7)..................................................................................3465
16.2.3.14
LCDRAM Location 8 (LCD_LCDRAM8)..................................................................................3466
16.2.3.15
LCDRAM Location 9 (LCD_LCDRAM9)..................................................................................3466
Functional Description..................................................................................................................................... 3467
16.2.4.1
Frontplane, Backplane, and LCD System During Reset..............................................................3467
16.2.4.2
LCD Clock and Frame Frequency............................................................................................... 3467
16.2.4.3
Contrast Adjustment.................................................................................................................... 3468
16.2.4.3.1
Adjusting the supply voltage (VDDE)..................................................................3469
16.2.4.3.2
Adding Contrast Adjustment Phases.................................................................... 3469
16.2.4.4
LCD RAM....................................................................................................................................3470
16.2.4.5
LCD Driver System Enable and Frontplane Enable Sequencing................................................ 3470
16.2.4.6
LCD Driver Backplane Remapping............................................................................................. 3470
16.2.4.7
LCD Bias and Modes of Operation..............................................................................................3472
16.2.4.8
Operation in Power Saving Modes.............................................................................................. 3473
16.2.4.8.1
Operation in STOP mode......................................................................................3473
16.2.4.8.2
Operation in LPSTOP Mode.................................................................................3473
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Section number
16.2.4.9
16.2.4.10
Title
Other Power Saving..................................................................................................................... 3474
16.2.4.9.1
LCD Reference Clock Select................................................................................ 3474
16.2.4.9.2
Boost at Switching................................................................................................ 3474
16.2.4.9.3
Standard Drive Selection...................................................................................... 3475
16.2.4.9.4
Usage Recommendation....................................................................................... 3475
Interrupts...................................................................................................................................... 3476
16.2.4.10.1
16.2.5
16.2.6
Page
EOF Interrupt........................................................................................................ 3476
LCD Waveform Examples...............................................................................................................................3477
16.2.5.1
1/1 Duty Multiplexed with 1/1 Bias Mode.................................................................................. 3477
16.2.5.2
1/2 Duty Multiplexed with 1/2 Bias Mode.................................................................................. 3478
16.2.5.3
1/2 Duty Multiplexed with 1/3 Bias Mode.................................................................................. 3479
16.2.5.4
1/3 Duty multiplexed with 1/3 Bias mode................................................................................... 3480
16.2.5.5
1/4 Duty multiplexed with 1/3 Bias mode................................................................................... 3481
16.2.5.6
1/5 Duty multiplexed with 1/3 Bias............................................................................................. 3482
16.2.5.7
1/6 Duty multiplexed with 1/3 Bias mode................................................................................... 3483
Initialization Information................................................................................................................................. 3484
16.3 Timing Controller (TCON).............................................................................................................................................3485
16.3.1
16.3.2
Introduction...................................................................................................................................................... 3485
16.3.1.1
Features........................................................................................................................................ 3485
16.3.1.2
Modes of Operation..................................................................................................................... 3486
Memory map and register definition................................................................................................................3486
16.3.2.1
TCON control1 register (TCONx_CTRL1)................................................................................. 3491
16.3.2.2
Bit map control register (TCONx_BMC).................................................................................... 3493
16.3.2.3
Comparator configure register (TCONx_COMPn)......................................................................3494
16.3.2.4
Comparator compare value mask register (TCONx_COMPn_MSK)......................................... 3495
16.3.2.5
Pulse configure register (TCONx_PULSEn)............................................................................... 3496
16.3.2.6
Pulse compare value mask register (TCONx_PULSEn_MSK)................................................... 3497
16.3.2.7
Function control register (TCONx_SMXn)................................................................................. 3497
16.3.2.8
TCON output mux control low (TCONx_OMUX_LOW).......................................................... 3499
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Section number
16.3.3
Page
16.3.2.9
TCON output mux control high (TCONx_OMUX_HIGH)........................................................ 3500
16.3.2.10
TCON look up table (TCONx_LUTn).........................................................................................3501
16.3.2.11
TCON control2 register (TCONx_CTRL2)................................................................................. 3502
Functional Description..................................................................................................................................... 3502
16.3.3.1
16.3.3.2
16.3.3.3
16.3.3.4
16.3.4
Title
Modes of operation...................................................................................................................... 3502
16.3.3.1.1
TTL mode............................................................................................................. 3502
16.3.3.1.2
Bypass mode......................................................................................................... 3503
Timing signal generator............................................................................................................... 3503
16.3.3.2.1
Comparator........................................................................................................... 3504
16.3.3.2.2
Pulse generator......................................................................................................3504
16.3.3.2.3
Toggle generator................................................................................................... 3505
16.3.3.2.4
Signal Mixer (SMX)............................................................................................. 3506
16.3.3.2.5
Output Crossbar Mux............................................................................................3507
Bit Mapping Control (BMC)........................................................................................................3508
16.3.3.3.1
Bit mapping in TTL mode.................................................................................... 3508
16.3.3.3.2
Bit mapping examples...........................................................................................3509
16.3.3.3.3
Clock mapping in TTL mode................................................................................3509
Clock/Data Skew Adjustment...................................................................................................... 3510
Initialization/Application Information............................................................................................................. 3511
16.3.4.1
TCON Initialization..................................................................................................................... 3511
16.4 Run Length Encoding Decoder (RLE_DEC)................................................................................................................. 3511
16.4.1
16.4.2
Introduction...................................................................................................................................................... 3511
16.4.1.1
Overview...................................................................................................................................... 3512
16.4.1.2
Features........................................................................................................................................ 3513
16.4.1.3
RLE_DEC Modes of Operation................................................................................................... 3513
16.4.1.3.1
Normal Mode........................................................................................................ 3513
16.4.1.3.2
Module Disable Mode...........................................................................................3514
16.4.1.3.3
Stop Mode.............................................................................................................3514
External Signal Description............................................................................................................................. 3514
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Section number
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Page
16.4.3
Interrupt and DMA Request Signals................................................................................................................ 3514
16.4.4
Memory map and register definition................................................................................................................3514
16.4.5
16.4.4.1
Module Configuration Register (RLE_DEC_MCR)................................................................... 3516
16.4.4.2
Image Configuration Register (RLE_DEC_ICR)........................................................................ 3517
16.4.4.3
Compressed Image Size Register (RLE_DEC_CISR).................................................................3518
16.4.4.4
Decompressed Image Co-ordinates register (RLE_DEC_DICR)................................................3518
16.4.4.5
Status Register (RLE_DEC_SR)................................................................................................. 3519
16.4.4.6
Interrupt Request Status Register (RLE_DEC_ISR)................................................................... 3520
16.4.4.7
Interrupt Request Enable Register (RLE_DEC_RIER)............................................................... 3521
16.4.4.8
Start Pixel Co-ordinate Register of Image (RLE_DEC_SPCR).................................................. 3522
16.4.4.9
End Pixel Co-ordinate Register of Image (RLE_DEC_EPCR)................................................... 3522
16.4.4.10
Crossbar Switch Bus Register Memory Map...............................................................................3523
16.4.4.11
Crossbar switch memory map descriptions................................................................................. 3523
16.4.4.11.1
Rx FIFO Address Range.......................................................................................3523
16.4.4.11.2
Tx FIFO Address Range....................................................................................... 3524
16.4.4.11.3
Memory Mapped Rx FIFO................................................................................... 3524
16.4.4.11.4
Memory Mapped Tx FIFO....................................................................................3524
Functional Description..................................................................................................................................... 3525
16.4.5.1
RLE encoding format...................................................................................................................3525
16.4.5.2
RLE decoding process................................................................................................................. 3526
16.4.5.3
Image coordinates' example......................................................................................................... 3527
16.4.5.4
Modes of Operation..................................................................................................................... 3528
16.4.5.5
Normal Mode............................................................................................................................... 3528
16.4.5.6
Power Saving Features.................................................................................................................3528
16.4.5.6.1
Module Disable Mode...........................................................................................3528
16.5 2D Graphics Processing Unit (GPU2D) (R-Series only)................................................................................................3529
16.5.1
Overview.......................................................................................................................................................... 3529
16.5.2
GPU2D Block Diagram................................................................................................................................... 3529
16.5.2.1
V2D GPU..................................................................................................................................... 3529
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Section number
16.5.3
Page
GPU2D Features.............................................................................................................................................. 3530
16.5.3.1
16.5.4
Title
V2D GPU Structure..................................................................................................................... 3530
16.5.3.1.1
Host Interface-V2D...............................................................................................3530
16.5.3.1.2
Memory Controller-V2D...................................................................................... 3531
16.5.3.1.3
Graphics Pipeline Front End-V2D........................................................................3531
16.5.3.1.4
Tessellation Engine...............................................................................................3531
16.5.3.1.5
Vector Graphics Engine........................................................................................3531
16.5.3.1.6
Imaging Engine.....................................................................................................3531
16.5.3.1.7
VG Pixel Engine................................................................................................... 3531
GPU2D OPERATIONS................................................................................................................................... 3531
16.5.4.1
V2D GPU Operations.................................................................................................................. 3531
16.5.4.1.1
OPENVG 1.1-API STANDARD for VECTOR GRAPHICS
ACCELERATION................................................................................................3531
16.5.4.2
16.5.5
16.5.4.1.2
Advantages of Using OpenVG............................................................................. 3532
16.5.4.1.3
OpenVG Target Applications............................................................................... 3532
16.5.4.1.4
OpenVG Features..................................................................................................3532
16.5.4.1.4.1
Core API ....................................................................................3532
16.5.4.1.4.2
The VGU Utility Library ...........................................................3532
16.5.4.1.4.3
OpenVG Rendering Pipeline......................................................3533
V2D GPU Operations.................................................................................................................. 3531
16.5.4.2.1
Memory Master Interfaces....................................................................................3533
16.5.4.2.2
Slave Interface to CPU or controller interface .....................................................3533
16.5.4.3
Debug Support............................................................................................................................. 3533
16.5.4.4
Interrupt........................................................................................................................................3534
GPU2D Memory Map/Register Definition......................................................................................................3534
16.5.5.1
Clock Control Register (GPU2D_AQHiClockControl).............................................................. 3537
16.5.5.2
Idle Status Register (GPU2D_AQHiIdle)....................................................................................3539
16.5.5.3
AXI Configuration Register (GPU2D_AQAxiConfig)............................................................... 3540
16.5.5.4
AXI Status Register (GPU2D_AQAxiStatus)............................................................................. 3541
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Page
16.5.5.5
Interrupt Acknowledge Register (GPU2D_AQIntrAcknowledge)..............................................3541
16.5.5.6
Interrupt Enable Register (GPU2D_AQIntrEnbl)........................................................................3542
16.5.5.7
Identification Register (GPU2D_AQIdent)................................................................................. 3542
16.5.5.8
Features Register (GPU2D_Features)..........................................................................................3544
16.5.5.9
Chip Identification Register (GPU2D_ChipId)........................................................................... 3548
16.5.5.10
Chip Revision Register (GPU2D_ChipRev)................................................................................3549
16.5.5.11
Chip Release Date Register (GPU2D_ChipDate)........................................................................3549
16.5.5.12
Chip Release Time Register (GPU2D_ChipTime)...................................................................... 3550
16.5.5.13
Chip Customer Register (GPU2D_ChipCustomer)..................................................................... 3550
16.5.5.14
Minor Features Register 0 (GPU2D_MinorFeatures0)................................................................3551
16.5.5.15
Cache Control Register (GPU2D_CacheControl)....................................................................... 3555
16.5.5.16
Reset Mem Counters Register (GPU2D_ResetMemCounters)................................................... 3556
16.5.5.17
Read Count Register (GPU2D_TotalReads)................................................................................3556
16.5.5.18
Write Count Register (GPU2D_TotalWrites)..............................................................................3557
16.5.5.19
Chip Specification Register (GPU2D_ChipSpecs)......................................................................3557
16.5.5.20
Write Data Count Register (GPU2D_TotalWriteBursts).............................................................3558
16.5.5.21
Write REQ Count Register (GPU2D_TotalWriteReqs).............................................................. 3559
16.5.5.22
Total WLAST Count Register (GPU2D_TotalWriteLasts).........................................................3559
16.5.5.23
Total Read Data Count Register (GPU2D_TotalReadBursts)..................................................... 3560
16.5.5.24
Total Read REQ Count Register (GPU2D_TotalReadReqs).......................................................3560
16.5.5.25
Total RLAST Count Register (GPU2D_TotalReadLasts)...........................................................3561
16.5.5.26
General Purpose Register 0 (GPU2D_GpOut0).......................................................................... 3561
16.5.5.27
General Purpose Register 1 (GPU2D_GpOut1).......................................................................... 3562
16.5.5.28
General Purpose Register 2 (GPU2D_GpOut2).......................................................................... 3562
16.5.5.29
AXI Control Register (GPU2D_AxiControl).............................................................................. 3562
16.5.5.30
Minor Features Register 1 (GPU2D_MinorFeatures1)................................................................3564
16.5.5.31
Total Cycle Counter Register (GPU2D_TotalCycles).................................................................3566
16.5.5.32
Total Idle Cycle Register (GPU2D_TotalIdleCyles)................................................................... 3566
16.5.5.33
Chip Specification Register (GPU2D_ChipSpecs2)....................................................................3567
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Section number
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16.5.5.34
Power Control Register (GPU2D_ModulePowerControls)......................................................... 3567
16.5.5.35
Power Level Register (GPU2D_ModulePowerModuleControl)................................................. 3569
16.5.5.36
Power Status Register (GPU2D_ModulePowerModuleStatus)................................................... 3571
16.6 Video subsystem............................................................................................................................................................. 3573
16.6.1
Introduction...................................................................................................................................................... 3573
16.6.2
External signal description...............................................................................................................................3574
16.6.3
Analog front end (AFE)................................................................................................................................... 3575
16.6.4
16.6.3.1
AFE features................................................................................................................................ 3575
16.6.3.2
AFE controller preset................................................................................................................... 3575
AFE memory map and registers.......................................................................................................................3576
16.6.4.1
Misc. ID (AFE_MISC_ID).......................................................................................................... 3578
16.6.4.2
Power Down Buffers (AFE_PDBUF)..........................................................................................3578
16.6.4.3
Software Reset (AFE_SWRST)...................................................................................................3579
16.6.4.4
Band Gap (AFE_BGREG)...........................................................................................................3580
16.6.4.5
Accessar ID (AFE_ACCESSAR_ID).......................................................................................... 3581
16.6.4.6
Power Down ADC (AFE_PDADC)............................................................................................ 3581
16.6.4.7
Power Down SAR High (AFE_PDSARH).................................................................................. 3582
16.6.4.8
Power Down SAR Low (AFE_PDSARL)................................................................................... 3583
16.6.4.9
Power Down ADC Ref. High (AFE_PDADCRFH).................................................................... 3583
16.6.4.10
Power Down ADC Ref. Low (AFE_PDADCRFL)..................................................................... 3584
16.6.4.11
ADC Gain (AFE_ADCGN)......................................................................................................... 3584
16.6.4.12
ADC Ref Trim Low (AFE_REFTRIML).................................................................................... 3585
16.6.4.13
ADC Ref Trim High (AFE_REFTRIMH)................................................................................... 3586
16.6.4.14
Delay Loop Calculated Data (AFE_DLYALG).......................................................................... 3586
16.6.4.15
Clamp DAC Trim (AFE_DACAMP).......................................................................................... 3587
16.6.4.16
Clamp DAC Data (AFE_CLMPDAT).........................................................................................3587
16.6.4.17
Clamp DAC Control (AFE_CLMPAMP)....................................................................................3588
16.6.4.18
Clamp Control (AFE_CLAMP)...................................................................................................3589
16.6.4.19
Input Buffer (AFE_INPBUF)...................................................................................................... 3590
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Section number
16.6.5
16.6.6
Title
Page
16.6.4.20
Analog Input Filter (AFE_INPFLT)............................................................................................ 3591
16.6.4.21
ADC Digital Gain (AFE_ADCDGN).......................................................................................... 3593
16.6.4.22
Off-Chip Drive (AFE_OFFDRV)................................................................................................ 3593
16.6.4.23
Acc ID (AFE_ACC_ID).............................................................................................................. 3594
16.6.4.24
ADC Sample Acquisition (AFE_ASAREG)............................................................................... 3595
16.6.4.25
ADC Sample Compensation (AFE_ASCREG)........................................................................... 3596
16.6.4.26
Block Level Control Register (AFE_BLCREG)......................................................................... 3597
16.6.4.27
ADC Operation Controller 0 (AFE_AOCREG0)........................................................................ 3598
Video decoder.................................................................................................................................................. 3598
16.6.5.1
Video decoder features.................................................................................................................3599
16.6.5.2
VDEC controller preset................................................................................................................3599
Video decoder memory map and registers.......................................................................................................3600
16.6.6.1
2D Comb Filter Control 1 (VDEC_CFC1).................................................................................. 3602
16.6.6.2
Burst Gate (VDEC_BRSTGT).....................................................................................................3603
16.6.6.3
Horizontal Position (VDEC_HZPOS)......................................................................................... 3604
16.6.6.4
Vertical Position (VDEC_VRTPOS)...........................................................................................3604
16.6.6.5
Output Conditioning and HV Shift (VDEC_HVSHFT).............................................................. 3605
16.6.6.6
HSync Ignore Start (VDEC_HSIGS)...........................................................................................3606
16.6.6.7
HSync Ignore End (VDEC_HSIGE)............................................................................................3606
16.6.6.8
VSync Control 1 (VDEC_VSCON1).......................................................................................... 3607
16.6.6.9
VSync Control 2 (VDEC_VSCON2).......................................................................................... 3608
16.6.6.10
Y/C Delay and Chroma Debug (VDEC_YCDEL)...................................................................... 3609
16.6.6.11
After Clamp (VDEC_AFTCLP).................................................................................................. 3610
16.6.6.12
DC Offset (VDEC_DCOFF)........................................................................................................3611
16.6.6.13
Chroma Swap, Invert, and Debug (VDEC_CSID)...................................................................... 3612
16.6.6.14
Cb Gain (VDEC_CBGN).............................................................................................................3613
16.6.6.15
Cr Gain (VDEC_CRGN)............................................................................................................. 3613
16.6.6.16
Contrast (VDEC_CNTR)............................................................................................................. 3614
16.6.6.17
Brightness (VDEC_BRT)............................................................................................................ 3614
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16.6.6.18
Hue (VDEC_HUE)...................................................................................................................... 3614
16.6.6.19
Chroma Burst Threshold (VDEC_CHBTH)................................................................................3615
16.6.6.20
Sharpness Improvement (VDEC_SHPIMP)................................................................................ 3615
16.6.6.21
Chroma PLL and Input Mode (VDEC_CHPLLIM).................................................................... 3616
16.6.6.22
Video Mode (VDEC_VIDMOD).................................................................................................3617
16.6.6.23
Video Status (VDEC_VIDSTS)...................................................................................................3619
16.6.6.24
Noise Detector (VDEC_NOISE)................................................................................................. 3620
16.6.6.25
Standards and Debug (VDEC_STDDBG)................................................................................... 3620
16.6.6.26
Manual Override (VDEC_MANOVR)........................................................................................ 3622
16.6.6.27
VSync and Signal Thresholds (VDEC_VSSGTH)...................................................................... 3623
16.6.6.28
Debug Framebuffer (VDEC_DBGFBH)..................................................................................... 3624
16.6.6.29
Debug Framebuffer 2 (VDEC_DBGFBL)...................................................................................3624
16.6.6.30
H Active Start (VDEC_HACTS)................................................................................................. 3625
16.6.6.31
H Active End (VDEC_HACTE)..................................................................................................3625
16.6.6.32
V Active Start (VDEC_VACTS)................................................................................................. 3625
16.6.6.33
V Active End (VDEC_VACTE)..................................................................................................3626
16.6.6.34
HSync Tip (VDEC_HSTIP).........................................................................................................3626
16.6.6.35
Bluescreen Y (VDEC_BLSCRY)................................................................................................ 3627
16.6.6.36
Bluescreen Cr (VDEC_BLSCRCR)............................................................................................ 3627
16.6.6.37
Bluescreen Cb (VDEC_BLSCRCB)............................................................................................3627
16.6.6.38
Luma AGC Control 2 (VDEC_LMAGC2)..................................................................................3628
16.6.6.39
Chroma AGC Control 2 (VDEC_CHAGC2)...............................................................................3628
16.6.6.40
Minimum Threshold (VDEC_MINTH).......................................................................................3629
16.6.6.41
Vertical Lines High (VDEC_VFRQOH)..................................................................................... 3629
16.6.6.42
Vertical Lines Low (VDEC_VFRQOL)...................................................................................... 3630
16.7 Video Interface Unit (VIU).............................................................................................................................................3630
16.7.1
Introduction...................................................................................................................................................... 3630
16.7.2
Features............................................................................................................................................................ 3631
16.7.3
Video Input Signal Mapping............................................................................................................................3632
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Section number
16.7.4
16.7.5
Title
Page
Memory map and register definition................................................................................................................3633
16.7.4.1
Status And Configuration Register (VIU3_SCR)........................................................................ 3635
16.7.4.2
Luminance Coefficients For Red, Green And Blue Matrix (VIU3_LUMA_COMP)................. 3638
16.7.4.3
Chroma Coefficients For Red Matrix (VIU3_CHROMA_RED)................................................ 3639
16.7.4.4
Chroma Coefficients For Green Matrix (VIU3_CHROMA_GREEN)....................................... 3640
16.7.4.5
Chroma Coefficients For Blue Matrix (VIU3_CHROMA_BLUE)............................................ 3640
16.7.4.6
Base Address Of Every Field/Frame Of Picture In Memory (VIU3_DMA_ADDR)................. 3641
16.7.4.7
Horizontal DMA Increment (VIU3_DMA_INC)........................................................................ 3641
16.7.4.8
Input Video Pixel and Line Count (VIU3_INVSZ).....................................................................3642
16.7.4.9
High IPM Request Priority Alarm (VIU3_HPRALRM)............................................................. 3642
16.7.4.10
Programable Alpha Value (VIU3_ALPHA)................................................................................3643
16.7.4.11
Down Scaling Factor In Horizontal Direction (VIU3_HFACTOR)............................................3643
16.7.4.12
Down Scaling Factor In Vertical Direction (VIU3_VFACTOR)................................................ 3643
16.7.4.13
Down Scaling Destination Pixel and Line Count (VIU3_VID_SIZE)........................................ 3644
16.7.4.14
B/C Adjust Look-up-table Current Address (VIU3_LUT_ADDR)............................................ 3644
16.7.4.15
B/C Adjust Look-up-table Data Entry (VIU3_LUT_DATA)......................................................3645
16.7.4.16
Extended Configuration Register (VIU3_EXT_CONFIG)......................................................... 3645
16.7.4.17
Red, Green and Blue Coefficients for Luminance component (VIU3_RGB_Y)........................ 3647
16.7.4.18
Red, Green and Blue Coefficients for Chroma U component (VIU3_RGB_U)..........................3648
16.7.4.19
Red, Green and Blue Coefficients for Chroma V component (VIU3_RGB_V)..........................3648
Functional Description..................................................................................................................................... 3649
16.7.5.1
Input Formats............................................................................................................................... 3649
16.7.5.1.1
ITU656..................................................................................................................3649
16.7.5.1.2
Parallel Input Format............................................................................................ 3651
16.7.5.1.3
Parallel YC Format............................................................................................... 3651
16.7.5.1.4
Serial RGB888 Format......................................................................................... 3651
16.7.5.2
Input Synchronizer....................................................................................................................... 3652
16.7.5.3
Decoder........................................................................................................................................ 3652
16.7.5.4
Scaling..........................................................................................................................................3652
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16.7.6
Title
Page
16.7.5.4.1
Down Scaling........................................................................................................3652
16.7.5.4.2
Up-scaling............................................................................................................. 3653
16.7.5.5
Brightness and Contrast Adjust....................................................................................................3654
16.7.5.6
YUV to RGB Conversion............................................................................................................ 3655
16.7.5.7
Round and Dither......................................................................................................................... 3655
16.7.5.7.1
Round....................................................................................................................3655
16.7.5.7.2
Dither.................................................................................................................... 3655
16.7.5.8
Output Formatter..........................................................................................................................3656
16.7.5.9
High Priority Alarm..................................................................................................................... 3657
16.7.5.10
DMA and De-interlace.................................................................................................................3657
16.7.5.11
Error Case.................................................................................................................................... 3658
Initialization/Application Information............................................................................................................. 3659
16.7.6.1
Initialization Information............................................................................................................. 3659
16.7.6.2
Application Information...............................................................................................................3661
16.7.6.2.1
Register Configuration Timing Window.............................................................. 3661
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Chapter 1
About This Document
1.1 Overview
1.1.1 Purpose
This document describes the features, architecture, and programming model of the NXP
VFxxx Controller microprocessor (MPU).
This document is common for the VFxxx Controller F-Series and R-Series. Note
however that some functions are only available on the F-series parts and others only on
R-series parts. For a detailed feature list, refer to the data sheet for the specific family.
1.1.2 Audience
This document is primarily intended for system architects and software application
developers who are using, or considering using, a VFxxx Controller device in a system.
1.1.3 Reference Manual Overview
This manual is intended to be a reference guide for both the VFxxx Controller F-Series
and R-Series. As such, not all modules and features are available on both devices. For
example, the MediaLB (MLB) and Graphics Processing Unit (GPU) modules are specific
to the R-Series parts, and the Ethernet Switch (ESW) feature is only implemented on FSeries.
A comprehensive fuse map and a block diagram that encompasses all modules available
on both F-Series and R-Series have been included in this manual. For the specific
implementation of modules and features on your device, consult the F-Series and/or RSeries data sheets.
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Conventions
1.1.4 Related Resources
Type
Description
Resource
The Data Sheet includes electrical
characteristics and signal connections.
VYBRIDFSERIESEC for MVF* parts1
Reference Manual
The Reference Manual contains a
comprehensive description of the
structure and function (operation) of the
device.
This document
Chip Errata
The chip mask set Errata provides
additional or corrective information for a
particular device mask set.
VFxxx Controller Chip Errata1
Application Notes
Application Notes are engineering
support documents that assist the user
in evaluating the operation of a device
product line, package type, or general
application topic.
Data Sheet
VYBRIDRSERIESEC for SVF* parts1
• AN4651 1 - TFT Panel Support in
the Vybrid Microcontroller Family
• AN4672 1 - Using the Run-Length
Decoding Features on Vybrid
Devices
• AN4647 1 - Configuring and Using
the 2D-ACE on Vybrid
Microcontrollers
• AN4635 1 - Using the Vybrid
TCON Module
• AN4512 1 - Quad Serial Peripheral
Interface (QuadSPI) Module
Updates
• AN4947 1 - Understanding Vybrid
Architecture
• AN4807 1 - Vybrid Power
Consumption and Options
1. To find the associated resource, go to www.nxp.com and perform a search using this term.
1.2 Conventions
1.2.1 Numbering systems
The following suffixes identify different numbering systems:
This suffix
Identifies a
b
Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are
shown with the prefix 0b.
d
Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general,
decimal numbers are shown without a suffix.
Table continues on the next page...
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Chapter 1 About This Document
This suffix
Identifies a
h
Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases,
hexadecimal numbers are shown with the prefix 0x.
1.2.2 Typographic notation
The following typographic notation is used throughout this document:
Example
Description
placeholder, x
Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.
SR[SCM]
A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0]
Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.2.3 Special terms
The following terms have special meanings:
Term
Meaning
asserted
Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted
Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved
Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the
module or chip behavior is unpredictable.
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Conventions
Term
w1c
Meaning
Write 1 to clear: Refers to a register bitfield that must be
written as 1 to be "cleared."
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Chapter 2
Introduction
2.1 VFxxx Controller Platform
This family of devices is NXP’s latest Dual and Single Core offerings with ARM®
Cortex®-A5 and ARM® Cortex®-M4 based processors for high end industrial and
general purpose applications.
NOTE
Throughout this manual, ARM® Cortex®-A5 is referred to as
Cortex-A5 or CA5. Also, ARM® Cortex®-M4 is referred to as
Cortex-M4 or CM4.
These devices are highly integrated reducing system cost for target applications. The
following features can be found on VFxxx Controller Processors. For part-specific
features, refer to the data sheets.
• Cortex-A5 with TrustZone with 32 KB I-Cache/32 KB D-Cache
• Neon Media Processing Engine (MPE) co-processor and double precision Floating
Point Unit (FPU)
• Cortex-M4 with 16 KB I-Cache/16 KB D-Cache
• 1.5 MB on-chip SRAM of which 512 KB optionally supports ECC
• Support for LPDDR2/DDR3
• Dual TFT display up to SVGA and optional 40x4 and 38x6 Segmented LCD
• Dual 10/100 Ethernet (R-Series)
• Dual 10/100 Ethernet with on-chip L2 Switch (F-Series only)
• Dual USB OTG with on-chip HS PHY and on-chip HS/FS/LS PHY
• OpenVG 1.1 GPU (R-Series only)
• Advanced Security supporting Symmetric with on-chip Tamper detection
• Rich set of communication peripherals and general purpose features
• Advanced digital audio support with multiple audio interfaces and hardware
asynchronous sample-rate converter co-processor.
• Package options for 176 LQFP and 364 BGA
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Feature Set
This family of devices is manufactured utilizing 40nm low-power process.
2.2 Feature Set
The following features can be found on the VFxxx Controller Processors. For partspecific features, refer to the data sheets.
Table 2-1. Feature Set
Operating Characteristics
• Voltage range 3.0 V - 3.6 V
• Temperature range (TJ) -40 to 105 °C
• Flexible modes of operation
ARM Cortex-A5 Core
• Up to 500 MHz (F-Series) or 400 MHz (R-Series) ARM
Cortex-A5
• 32 KB/32 KB I-/D- L1 Cache
• 1.57 DMIPS/MHz based on ARMv7 architecture
• NEON MPE co-processor
• Dual precision FPU
• Optional 512K L2 Cache
ARM Cortex-M4 Core
•
•
•
•
Clocks
• 6 Phase Locked Loops (PLLs)
• 2 external crystal oscillators (XOSC)
• 2 internal RC (IRC) oscillators
System, protection and power management features
• Flexible stop, wait, and run modes to provide lower
power based on application needs.
• Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
• Low voltage warning and detect
• Hardware CRC module to support fast cyclic
redundancy checks (CRC)
• 64-bit unique chip identifier
• Hardware watchdog
• External Watchdog Monitor (EWM)
• Dual DMA controller with 32 channels (with DMAMUX)
Debug
• Standard JTAG
• 16 bit Trace port
Timers
•
•
•
•
Communications
•
•
•
•
Up to 167 MHz ARM Cortex M4
Build-in DSP capability
16KB/16KB I-/D- L1 Cache
1.25 DMIPS/MHz based on ARMv7 architecture
General purpose timer (FTM)
Low Power Timer (LPTMR)
One Periodic Interrupt Timer (PIT) with 8 channels
IEEE® 1588 Timers (part of Ethernet Subsystem)
UART(IrDA, and hardware flow control)
Serial peripheral interface (SPI)
I2C with SMBUS support
Dual USB 2.0 HS OTG Controller (Supports LS/FS/HS)
with integrated PHYs
• 4/8 bit Secure Digital Host controller
• Local Media Bus (MLB50) (R-Series only)
• Dual 10/100 Ethernet (R-Series)
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Table 2-1. Feature Set (continued)
• Dual 10/100 Ethernet with L2 Switch (F-Series only)
• FlexCAN3
Memory Interfaces
• 8/16 bit DRAM Controller with support for LPDDR2/
DDR3 - Up to 800MT/s (400 MHz)
• 8/16-bit NAND Flash controller with ECC
• 8/16/32 bit External bus (Flexbus)
• Dual QuadSPI supporting Execute-In-Place (XIP),
which means two ports can be used simultaneously.
XIP mode on QuadSPI interface works in all modes:
Single (1-bit data), Dual (2-bit data), or Quad (4-bit
data)
Graphics Display and Video
• Dual Display Control Unit (DCU) with support for color
TFT displays up to SVGA
• Segment LCD (3V Glass only) configurable as 40x4,
38x6, and 36x8
• Video Interface Unit (VIU) for camera input
• OpenVG Graphics Processing Unit (GPU) (R-Series
only)
• Run Length Endoded (RLE) Decoder
• Composite Video Decoder supporting PAL and NTSC
Analog
• 12-bit SAR ADC
• 12-bit DAC
Audio
• Synchronous Audio Interfaces (SAI) supporting I2S,
AC97 and Codec/DSP interfaces
• Enhanced Serial Audio Interface (ESAI)
• Sony/Philips Digital Interface (SPDIF), Rx and Tx
• Asynchronous Sample Rate Converter (ASRC)
Human-Machine Interface (HMI)
• GPIO pins with interrupt support, DMA request
capability, digital glitch filter.
• Hysteresis and configurable pull up/down device on all
input pins
• Configurable slew rate and drive strength on all output
pins
On-Chip RAM/ROM
• 512 KB On-Chip SRAM with ECC
• 1 MB On-Chip Graphics SRAM without ECC
• 96KB On-Chip ROM
Power Consumption
• Low power modes (LP/ULPRUN, STOP, LPSTOP1,
LPSTOP2 and LPSTOP3)
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Detailed Block Diagram
AXI
M0
PLLs
M1
64
32
64
32
M2
M17
M3
M4
M7
M5
M10
M12
M6
M11
NFC
AHB
eSDHC-0
32
32
32
AHB
AHB
AHB
AHB
32
eSDHC-1
L2 switch
32
ENET-0 (IEEE1588)
ENET-1 (IEEE1588)
MLB50
AHB
USB-PHY
USB-PHY
64
64
AHB
AHB
USB-OTG-0
TCON
Video ADC
AXI
AXI
AXI
64
64
64
AHB
24MHz / 128KHz
IRC
AHB
L2 Cache Controller
64
64
64
AHB
AXI
AHB
AHB
24MHz / 32KHz
XOSC
VIU3
System
AHB
Code
Clocking
DCU-1
32KB L1 32KB L1
D-Cache I-Cache
GC355
OpenVG GPU
FPU
16KB L1 16KB L1
D-Cache I-Cache
AHB
64KB
TCM
MCSM
DAP
NEON
FPU
32CH DMA-1
I/O Ctrl
Reset Ctrl
32CH DMA-0
ARM
Cortex-A5
TCON
ARM
Cortex-M4
GIC
NVIC
DCU-0
System Modules
USB-OTG-1
2.3 Detailed Block Diagram
32
32
32
M9
M8
M13 M14 M15
NIC301
RGPIO
LVD / HVD
Low Power Ctrl
S3
64
S0
64
AHB
256KB
SRAM (ECC)
AHB
64
AHB
S6
S8
64 AXI
64
S9
AXI
64
Port Splitter
AIPS-0
AIPS-1
S2
S7
64
Port Splitter
256KB
SRAM (ECC)
1MB
GRAM
(no ECC)
AXI
LP-DDR2,
DDR3
DRAM
Controller
16-bit
QuadSPI-0
Power
AXI
QuadSPI-1
Pixel
Convert
Port Splitter
HP/LP/ULP Vreg
S4
64
RLE
Decoder
S5
AXI
64
Boot ROM
S1
AHB
Flexbus
RTC
Clock Monitor
Debug
SJTAG
TPIU
SEMA4
PDB
EWM
CRC
12-bit ADC
ASRC
SPDIF
ESAI
SAI (4)
PIT
LPTIMER
FTM (2)
I2C (2)
SPI (2)
UART (4)
FlexCAN
LCD Segemnt
12-bit DAC
12-bit ADC
FTM (2)
I2C (2)
RNG
SNVS/TAMPERS
SPI (2)
FlexCAN
Security
UART (2)
4K TPB
See Device Configuration
Figure 2-1. Detailed Block Diagram
NOTE
Throughout this manual, ARM® Cortex®-A5 is referred to as
Cortex-A5 or CA5. ARM® Cortex®-M4 is referred to as
Cortex-M4 or CM4.
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Chapter 2 Introduction
2.4 VFxxx Controller Device Configuration
The following table lists the superset configuration for each package within the device.
Table 2-2. VFxxx Controller Device Configuration
Device
VF3XX
VF3XXR
VF5XX
VF5XXR
VF6XX
General
Cortex®-A5 Core
Frequency
266 MHz
266 MHz
Up to 500 MHz
Up to 400 MHz
Up to 500 MHz
Cortex®-M4 Core
Frequency
N/A
167 MHz
N/A
167 MHz
Up to 167 MHz
Package
176 LQFP
176 LQFP
364 BGA
364 BGA
364 BGA
24 x 24
17 x 17
17 x 17
17 x 17
Pitch (0.5 mm)
(Pitch 0.8mm)
(Pitch 0.8mm)
(Pitch 0.8mm)
2 x 32 ch DMA
Controllers
2 x 32 ch DMA
Controllers
2 x 32 ch DMA
Controllers
2 x 32 ch DMA
Controllers
2 x 32 ch DMA
Controllers
4 x 64 to 16 DMA
Muxes
4 x 64 to 16 DMA
Muxes
4 x 64 to 16 DMA
Muxes
4 x 64 to 16 DMA
Muxes
4 x 64 to 16 DMA
Muxes
8 bit Output Trace
8 bit Output Trace
16 bit Output Trace 16 bit Output Trace 16 bit Output Trace
Package
24 x 24
Dimensions (mm2)
Pitch (0.5 mm)
Core, Platform and Debug
DMA (with DMA
Mux)
Trace Port
Security Subsystem
Random number
generator
accelerator (RNG)
1, (NIST SP
800-90)
N/A
1, (NIST SP
800-90)
N/A
1, (NIST SP
800-90)
External Tamper
inputs
2
N/A
6
N/A
6
On-chip RAM
1.5 MB
1.5 MB
1.5 MB SRAM or 1 1.5 MB SRAM or 1 1.5 MB SRAM or 1
MB SRAM + 512
MB SRAM + 512
MB SRAM + 512
KB L2 Cache
KB L2 Cache
KB L2 Cache
ECC on On-chip
RAM (512K)
1
1
1
1
1
On-Chip ROM
96 KB
96 KB
96 KB
96 KB
96 KB
DRAM Controller
(LPDDR2/DDR3)
No
No
16 bit
16 bit
16 bit
8 bit
8 bit
8 bit
NAND Flash
Controller
1 (8 bit)
1 (8 bit)
1 (16 bit)
1 (16 bit)
1 (16 bit)
Quad SPI
2
1
2
1
2
FlexTimer (FTM0)
channel pins
8 Ch
8 Ch
8 Ch
8 Ch
8 Ch
FlexTimer (FTM1)
channel pins
2 Ch
2 Ch
2 Ch
2 Ch
2 Ch
On-Chip Memories
Memory Interfaces
Timers/PWM
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VFxxx Controller Device Configuration
Table 2-2. VFxxx Controller Device Configuration (continued)
Device
VF3XX
VF3XXR
VF5XX
VF5XXR
VF6XX
FlexTimer (FTM2)
channel pins
2 Ch
2 Ch
2 Ch
2 Ch
2 Ch
FlexTimer (FTM3)
channel pins
None
None
8 Ch
8 Ch
8 Ch
IEEE® 1588
Timers
4 Ch
4 Ch
8 Ch
8 Ch
8 Ch
Periodic Interrupt
Timers(PITs)
4 Ch
4 Ch
8 Ch
8 Ch
8 Ch
Low power timer
(LPTMR)
1
1
1
1
1
Communication Interfaces
10/100 ENET with
IEEE®1588
2
1
2
2
2
eSDHC
1 (8 bit)
1 (8 bit)
2 (8 bit and 4 bit)
2 (8 bit and 4 bit)
2 (8 bit and 4 bit)
FlexCAN
2
2
2
2
2
USB 2.0 HS OTG
Controller
1
1
2
2
2
UART (SCI)
4
4
6
6
6
DSPI (16-bit)
3
3
4
4
4
I2C
3
3
4
4
4
MLB50
0
1
0
1
0
TFT Display
1
Control Unit (DCU)
2 (1, if segment
display used)
2
2 (1, if segment
display used)
2
Segmented LCD
(40x4)
1 (0, if 2 TFT
displays used)
0
1 (0, if 2 TFT
displays used)
0
Display and Video
1
Video Interface Unit 1 (digital input only) 1 (digital input only) 1 (digital input only) 1 (digital input only) 1 (with digital or
(VIU)
analog video input)
RLE Decoder
1
1
1
1
1
12 bit SAR ADC
2 (12 Ch)
2 (12 Ch)
2 (16 Ch)
2 (16 Ch)
2 (16 Ch)
Video ADC
(Channels)
0
2
0
4
4
USB HS PHY
(OTG)
1
1
2
2
2
12-bit DAC
2
2
2
2
2
Asynchronous
Sample Rate
converter (ASRC)
1
1
1
1
1
SAI
3
3
4
4
4
ESAI
1
1
1
1
1
SDPIF
1
1
1
1
1
Analog
Audio
Table continues on the next page...
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Table 2-2. VFxxx Controller Device Configuration (continued)
Device
VF3XX
VF3XXR
VF5XX
VF5XXR
VF6XX
Human Machine Interface
Total GPIO pins
(with Interrupt
capability)
Up to 115
Up to 115
Up to 135
Up to 135
Up to 135
2.5 Modules on the device
2.5.1 Clocks
The following clock modules are available on this device.
Table 2-3. Clock modules
Module
Description
Reference links to the related information 1
Clock Controller Module The Clock Controller Module controls the
(CCM)
following functions:
• Uses the available clock sources to
generate clock roots to various parts of the
device
• Uses programmable bits to control
frequencies of the clock roots
• Controls the low power mechanism
• Provides control signals to Low Power
Clock Gating module (LPCG) for gating
clocks
• Provides handshake with System Reset
Controller (SRC) for reset performance
• Provides handshake with Global Power
Controller (GPC) for low power mode
operations
• Clocking Overview to read about the
overall clock distribution on this device. It
provides an overview about the different
clock sources their typical configuration,
and module clocks on this device.
• Clock Controller Module (CCM) to read
about module features, programming
model, Low Power Clock gating, and
auxiliary clocks on this device.
Analog components
control interface
(ANADIG)
ANADIG is collection of digital interfaces and
controllers of analog components, which include
control registers for controlling analog
components like device PLLs, PFDs, and
regulators.
• Clocking Overview.
• ANADIG to read about the registers that
control the PLLs, PFDs, and regulators on
this device.
Slow Clock Source
Controller (SCSC)
Controls the module configures the Slow internal
RC oscillator 128 KHz (SIRC) and Slow external
crystal oscillator 32 KHz (SXOSC) on the device.
• Clocking Overview.
• Introduction Slow Clock Source Controller
(SCSC)
Clock Monitor Unit
(CMU)
Measures the frequency of clock sources
• Clocking Overview.
• Clock Monitor Unit (CMU) to read about
module features, programming model, and
signals.
• CMU Chip Signals section to view the
mapping between CMU module signals
and the chip-level signals.
1. It is recommended to read the information in the order below.
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Modules on the device
2.5.2 Platform Modules
The following table lists all platform modules available on this device.
NOTE
Shaded modules are ARM modules. For the detailed description
about them, refer to the ARM website.
Table 2-4. Platform modules
Module
ARM Cortex-A5
Description
The Cortex-A5 processor is a high-performance,
low-power ARM macrocell with an L1 cache
subsystem that provides full virtual memory
capabilities. It supports:
• ARMv7-A instruction set architecture
including
• Includes Vector Floating-Point v4
(VFPv4) architecture
• NEON Media Processing Engine
(MPE)
• TrustZone security
• 8-stage single issue pipeline
implementation
• 1.57 DMIPS per MHz integer
performance
• 4-stage load/store pipeline
• 5-stage FPU/MPE pipeline
• 64-bit AXI System Bus Interface supporting
multiple outstanding transactions
Reference
For ARM Cortex-A5 processor documentation,
refer to Cortex-A5 MPCore r0p1 Technical
Reference Manual, DDI0434B at http://
www.arm.com
• Processor-local Memories
• 2 way set-associative 32 KB
Instruction Cache with 32 byte line
size
• 4 way set-associative 32 KB Data
Cache with 32 byte line size
• Standard Cortex-A5 Memory
Management Unit 64-bit AXI System
Bus Interface supporting multiple
outstanding transactions
CoreLink™ Level 2
Cache Controller
The addition of an on-chip secondary cache, also For ARM Cache Controller documentation, refer
referred to as a Level 2 or L2 cache, is a
to DDI0246F_l2c310_r3p2_trm at http://
recognized method of improving the performance www.arm.com
of ARM-based systems when significant memory
traffic is generated by the processor. By definition
a secondary cache assumes the presence of a
Level 1 or primary cache, closely coupled or
internal to the processor.
ARM Cortex-M4 Core
The Cortex-M4 processor core brings next
For ARM Cortex-M4 processor documentation,
generation capabilities to its predecessor, the
refer to Cortex-M4 User Guide Reference
Cortex-M3. Its new capabilities provide backward Material, DUI0553A at http://www.arm.com
compatibility with the Cortex-M3, while adding
important features.
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Table 2-4. Platform modules (continued)
Module
Description
Reference
• Supports ARMv7-M instruction set
architecture
• Includes the single precision FPU
• 3-stage single issue pipeline
implementation
• 1.25 DMIPS per MHz integer
performance
• Processor-local Memories
• All local memories operate at core
frequency and provide 0 wait state
response on “hits”
• 64 KB of Tightly-Coupled Memory
split equally between TCM{Lower,
Upper}
• 2 way set-associative 16KB
CodeCache
• 2 way set-associative 16 KB
SystemCache
• Modified Harvard 64-bit AHB System Bus
Interface + 64-bit AHB backdoor port to
TCM
Local Memory
Controller
The Local Memory Controller provides the ARM
Cortex-M4 processor with tightly coupled
processor-local memories and bus paths to all
slave memory spaces.
The local memory controller includes four
memory controllers and their attached memories:
• SRAM lower (SRAM_L) controller via the
PC bus
• SRAM upper (SRAM_U) controller via the
PS bus
• Cache memory controller via the PC bus
• Cache memory controller via the PS bus
CoreLink™ System Bus The CoreLink™ Network Interconnect (NIC301) For NIC301 documentation, refer to
Interconnect (NIC301) is a 2nd generation highly configurable IP
DDI0397H_corelink_network_interconnect_nic30
component that enables the creation of a
1_r2p2_trm.pdf at http://www.arm.com
complete high performance, optimized AMBAcompliant network infrastructure.
• 1-128 AXI or AHB-Lite slave interfaces for
bus master connections
• 1-64 master interfaces that can be AXI,
AHB-Lite, APB2, or APB3 for bus slave
connections
• Single-cycle arbitration
• Full pipelining to prevent master stalls
• Programmable control for FIFO transaction
release
• Multiple switch networks
• AXI or AHB-Lite masters and slaves
• Non-contiguous APB slave address map
for a single master interface
• Independent widths of user-defined
sideband signals for each channel
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Modules on the device
Table 2-4. Platform modules (continued)
Module
Description
Reference
• Global Programmers View (GPV) for the
entire infrastructure, configurable for
customizing the memory mapped visibility
• Highly flexible timing closure options
ARM Generic Interrupt
Controller (GIC)
Generic Interrupt Controller (GIC) is a centralized For ARM GIC documentation, refer to
resource for supporting and managing interrupts IHI0048B_gic_architecture_specification.pdf at
in a system that includes at least one processor. http://www.arm.com
It provides:
• registers for managing interrupt sources,
interrupt behavior, and interrupt routing to
one or more processors
• support for the following:
• the ARM architecture Security
Extensions
• the ARM architecture Virtualization
Extensions
• enabling, disabling, and generating
processor interrupts from hardware
(peripheral) interrupt sources
• Software-generated Interrupts (SGIs)
• interrupt masking and prioritization
• uniprocessor and multiprocessor
environments
• wakeup events in powermanagement environments.
Debug Interfaces
The device debug and trace is based on ARM
CoreSightTM architecture supplemented with the
Secured JTAG controller (SJC) to allow security
features. Debug interfaces supported are:
For ARM debug documentation, refer to ARM
Debug Interface IHI0031A_ARM_debug_interface_v5.pdf at http://
www.arm.com
• IEEE 1149.1 System JTAG Controller
(SJC) that provides the security
authentication for debug access to the
chip.
• IEEE 1149.7 JTAG. Also known as
compact JTAG (cJTAG).
• ARM Serial Wire Debug (SWD)
• Support for Secured and non secured
invasive/ non invasive debug to allow
further granularity in debug accesses.
• Support for field return parts to open
access for debug and test to allow failure
analysis.
• Cross Trigger supported between the two
cores as recommended by ARM.
• Program trace support
• Data trace supported by the Cortex-A5
eDMA
• 32 channels support independent
• 8-, 16-, or 32-bit single value or block
transfers
• Supports variable sized queues and
circular queues
• Source and destination address registers
are independently configured to
postincrement or remain constant
Refer to the Direct Memory Access Controller
(eDMA) chapter of this manual.
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Table 2-4. Platform modules (continued)
Module
Description
Reference
• Each transfer is initiated by a peripheral,
CPU, periodic timer interrupt or eDMA
channel request
• Each DMA channel can optionally send an
interrupt request to the CPU on completion
of a single value or block transfer
• DMA transfers possible between
memories, General Purpose I/Os (GPIOs)
and Slave Peripherals that support DMA
• Programmable DMA Channel Mux allows
assignment of any DMA source to any
available DMA channel with up to a total of
64 potential request sources
Peripheral Bridge
(AIPS-Lite)
Semaphores (SEMA4)
• Supports up to 160 peripherals and two
Refer to the AIPS-lite chapter of this manual.
global external peripheral spaces
• Supports 8-, 16-, and 32-bit width
peripheral slots
• Supports a pair of 32-bit transactions for
selected 64-bit memory accesses
• Each independently configurable peripheral
includes a clock enable, which allows
peripherals to operate at any speed less
than the system clock rate.
The Semaphores module implements hardware- Refer to the IPS_Semaphore chapter of this
enforced semaphores as an IPS-mapped slave
manual.
peripheral device. The feature set includes:
• Support for 16 hardware-enforced gates in
a dual-processor configuration
• Each hardware gate appears as a 3state, 2-bit state machine, with all 16
gates mapped as a byte-size array
• Optional interrupt notification after a
failed lock write provides a
mechanism to indicate when the gate
is unlocked
• Secure reset mechanisms are
supported to clear the contents of
individual gates or notification logic,
as well as a clear_all capability
• Memory-mapped IPS slave peripheral
platform module
• Interface to the IPS bus for
programming-model accesses
• Two outputs (one per processor) for
interrupt notification of failed lock
writes
2.5.3 System Modules
The following system modules are available on this device.
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Modules on the device
Table 2-5. System modules
Module
Description
Power management
controller (PMC)
The PMC provides the user with multiple power
options. Ten different modes are supported that
allow the user to optimize power consumption for
the level of functionality needed. Includes poweron-reset (POR) and integrated low voltage detect
(LVD) with reset (brownout) capability.
Peripheral bridges
The peripheral bridge converts the crossbar
switch interface to an interface to access a
majority of peripherals on the device.
DMA multiplexer
(DMAMUX)
The DMA multiplexer selects from many DMA
requests down to 16 for the DMA controller.
There are 2 DMA multiplexers associated with
each 32-channel DMA.
Direct memory access
(DMA) controller
The DMA controller provides programmable
channels with transfer control descriptors for data
movement via dual-address transfers for 8-, 16-,
32- and 128-bit data values.
External watchdog
monitor (EWM)
The EWM is a redundant mechanism to the
software watchdog module that monitors both
internal and external system operation for fail
conditions.
Software watchdog
(WDOG)
The WDOG monitors internal system operation
and forces a reset in case of failure. It operates
on SXOSC 32 KHz clock with a programmable
refresh window to detect deviations in program
flow or system frequency.
Reference links to the chip related
information
DMAMUX Request Sources
2.5.4 Memories and Memory Interfaces
The following memories and memory interfaces are available on this device.
Table 2-6. Memories and memory interfaces
Module
On-chip memory
Programmable Cyclic
Redundancy Check
(CRC32)
Description
Reference links to chip related information
• The device Includes:
• 512 KB On-Chip SRAM with error
correcting code (ECC)
• 1 MB On-Chip Graphics SRAM
without ECC
• 96 KB On-Chip ROM
The module generates 16/32-bit CRC code for
error detection. The CRC module provides a
programmable polynomial, SEED, and other
parameters required to implement a 16-bit or 32bit CRC standard. The 16/32-bit code is
calculated for 8/16/32-bit data at a time. The data
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Table 2-6. Memories and memory interfaces (continued)
Module
Description
Reference links to chip related information
width and transpose features are selectable by a
parameter.
DRAM Memory
Controller (DDRMC)
DDRMC is a complete embedded memory
DDR maximum address space
controller that interfaces to a PHY.
The features of this Memory Controller include:
• Supports interfacing to LPDDR2 and DDR3
memory types. It supports 8-bit and 16-bit
memory interface.
• Fully pipelined command, read and write
data interfaces to the memory controller.
• Advanced bank look-ahead features for
high memory throughput.
• Front-end interface to 2 standard AXI ports.
A programmable register interface to
control memory parameters and protocols
including auto pre-charge.
• Full initialization of memory on memory
controller reset.
• ECC functionality with single bit and double
bit error reporting and automatic correction
of single bit error events. 10-bit memory
interface is required for ECC (8-bit user
data + 2-bit ECC).
• ECC functionality with single bit and double
bit error reporting and automatic correction
of single bit error events.
• Clock frequencies from 100 MHz to 400
MHz supported.
• Back-end interface to a PHY.
• Integrates support for DDR pad calibration
logic - both software and hardware auto
modes
FlexBus
External bus interface with multiple independent,
user-programmable chip-select signals that can
interface with external SRAM, PROM, EPROM,
EEPROM, flash, and other peripherals via 8-, 16and 32-bit port sizes. Configurations include
multiplexed or non-multiplexed address and data
buses using 8-bit, 16-bit, 32-bit, and 16-byte linesized transfers. Maximum frequency that FlexBus
supports is 57 MHz
NAND flash controller
8-bit and 16-bit NAND flash interface with 32-bit
ECC error correction.
• Supports all NAND Flash products
regardless of density/organization (with
page size of 512 K+16B/2 K+64B/4 K
+128B/4 K+218B/8 K)
• Two Configurable DMA channels
• Maximum serial clock frequency 80 MHz
QuadSPI
Interface for up to two external quad serial flash
memories for code / data storage and code
execution
•
•
•
•
•
FlexBus signal multiplexing
FlexBus external signal
FlexBus security
Instantiation Information
FlexBus Chip Select Control Register
(CSCR0) Reset Value
• Bus Timeout
Instantiation
•
•
•
•
QuadSPI Instances
QuadSPI Memory Interface
QuadSPI Buffer
Booting from QuadSPI
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Modules on the device
Table 2-6. Memories and memory interfaces
Module
Description
Reference links to chip related information
• Supports industry standard single, dual and
quad mode serial flashes
• Supports Double Data Rate (DDR) serial
flash for high performance
• Maximum serial clock frequency 80 MHz
• Dual controller architecture enables
simultaneous access to two external
flashes resulting peak read bandwidth of
160 Mbytes/s
• Flexible buffering scheme, multi-master,
prioritized access
2.5.5 Audio modules
The following audio modules are available on this device:
Table 2-7. Audio modules
Module
Description
Reference links to chip related information
Enhanced Serial Audio
Interface (ESAI)
Provides a full-duplex serial port for serial
communication with a variety of serial devices,
including industry-standard codecs, Sony/Phillips
Digital Interface (SPDIF) transceivers, and other
DSPs. The ESAI consists of independent
transmitter and receiver sections, each section
with its own clock generator.
• Enhanced Serial Audio Interface (ESAI)
• ESAI Bus Interface and FIFO
(ESAI_BIFIFO)
Sony/Philips Digital
Interface (SPDIF)
The SPDIF is composed of two parts:
• SPDIF Receiver: The SPDIF receiver
extracts the audio data from each SPDIF
frame and places the data in the SPDIF Rx
left and right FIFOs. The Channel Status
and User Bits are also extracted from each
frame and placed in the corresponding
registers. The SPDIF receiver also
provides a bypass option for direct transfer
of the SPDIF input signal to the SPDIF
transmitter.
• SPDIF Transmitter. For the SPDIF
transmitter, the audio data is provided by
the processor via the SPDIFTxLeft and
SPDIFTxRight registers. The Channel
Status bits are also provided via the
corresponding registers.
Asynchronous Sample Converts the sampling rate of a signal associated
Rate Converter (ASRC) to an input clock into a signal associated to a
different output clock.The ASRC supports
concurrent sample rate conversion of up to 10
channels of about -120dB THD+N. The ASRC
supports up to 3 sampling rate pairs. The ASRC
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Table 2-7. Audio modules (continued)
Module
Description
Reference links to chip related information
is hard-coded implemented, as a co-processor,
with minimal CPU intervention.
Synchronous Audio
Interface (SAI)
Implements supports full-duplex serial interfaces
with frame synchronization such as I2S, AC97,
and CODEC/ DSP interfaces.
•
•
•
•
Synchronous Audio Interface (SAI)
SAI3 register details
Simultaneous SAI DMA requests
SAI transmitter and receiver options for
MCLK selection
• SAI in Stop mode
2.5.6 Timer modules
The following timer modules are available on this device:
Table 2-8. Timer modules
Module
Description
Reference links to chip related information
Programmable delay
block (PDB)
• 16-bit resolution
• 3-bit prescaler
• Positive transition of trigger event signal
initiates the counter
• Supports two triggered delay output
signals, each with an independentlycontrolled delay from the trigger event
• Outputs can be OR'd together to schedule
two conversions from one input trigger
event and can schedule precise edge
placement for a pulsed output. This feature
is used to generate the control signal for
the CMP windowing feature and output to a
package pin if needed for applications,
such as critical conductive mode power
factor correction.
• Continuous-pulse output or single-shot
mode supported, each output is
independently enabled, with possible
trigger events
• Supports bypass mode
• Supports DMA
•
•
•
•
•
PDB Instantiation
PDB Module Interconnections
DMA support on PDB
PDB in Low-Power modes
PDB implementation with ADC
Flexible timer modules
(FTM)
• Selectable FTM source clock,
programmable prescaler
• 16-bit counter supporting free-running or
initial/final value, and counting is up or updown
• Input capture, output compare, and edgealigned and center-aligned PWM modes
• Operation of FTM channels as pairs with
equal outputs, pairs with complimentary
outputs, or independent channels with
independent outputs
•
•
•
•
•
FTM Instantiation
FTM output triggers for other modules
FTM Global Time Base
FTM Hardware Triggers
FTM Fault Detection Inputs
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Table 2-8. Timer modules (continued)
Module
Description
Reference links to chip related information
• Deadtime insertion is available for each
complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture,
reference compare, overflowed counter, or
detected fault condition
• Quadrature decoder with input filters,
relative position counting, and interrupt on
position count or capture of position count
on external event
• DMA support for FTM events
Periodic interrupt timer
(PIT)
• 8 channels
• Interrupt timers for triggering ADC
conversions
• 32-bit counter resolution
• Clocked at system clock frequency
• 4 channels connected to DMA
• PIT Instantiations
• PIT/DMA Periodic Trigger Assignments
Low-power timer
(LPTimer)
• Selectable clock for prescaler/glitch filter of LPTMR prescaler/glitch filter clocking options
1 kHz (internal LPO), 32.768 kHz (external
crystal), or internal reference clock
• Configurable Glitch Filter or Prescaler with
16-bit counter
• 16-bit time or pulse counter with compare
• Interrupt generated on Timer Compare
• Hardware trigger generated on Timer
Compare
Real-time clock (RTC)
• Independent power supply, POR, and 32
kHz Crystal Oscillator
• 32-bit seconds counter with 32-bit Alarm
• 16-bit Prescaler with compensation that
can correct errors between 0.12 ppm and
3906 ppm
2.5.7 Communication interfaces
The following communication interfaces are available on the VFxxx Controller devices:
Table 2-9. Communication modules
Module
Ethernet MAC with
IEEE 1588 capability
(ENET)
Description
Ethernet Subsystem on VFxxx Controller include
the following blocks:
• Dual 10/100 Ethernet MAC (MAC-NET
From MTIP)
• Hardware support for IEEE Standard
for a Precision Clock Synchronization
Reference links to the chip related
information
•
•
•
•
•
•
Instantiation Information
MII and RMII configuration
IEEE 1588 Timers
Ethernet Operation in Low Power Modes
Ethernet Subsystem Interrupts
Ethernet switch register reset values
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Table 2-9. Communication modules (continued)
Module
Description
Reference links to the chip related
information
Protocol for Networked Measurement
and Control Systems IEEE 1588
• Reduced media independent
interface (RMII) support
• Interfaces with Unified DMA
• Supports wake-up from low power
mode through magic packets
• Multiple clock source options for
time-stamping clock
• Dual Unified DMA
• On-chip transmit and receive FIFOs
• F-Series only: 10/100 L2 Ethernet Switch
(From MTIP)
• 3-Port Switch
• Supports two MAC-NETs
• Supports 64-bit Atlantic/FIFO ports
and IEEE 1588 support
• Fast cut-through mode
• QoS with 8-queues per port and port
mirroring
• Level 3 IP snooping
Universal Serial Bus
Controller (USB)
USB 2.0 compliant module with support for host,
device, and On-The-Go modes. Includes an onchip transceiver for full and low speeds. The
registers and data structures are based on the
Enhanced Host Controller Interface Specification
for Universal Serial Bus (EHCI) from Intel
Corporation.
• USB Configuration and Options
• SOF for USB Audio
• OverCurrent and VBUS Connection
NOTE: OTG controller should be treated as
Dual role controller that allows the
controller to act as either a Host or a
device with no support for HNP/SRP.
Controller Area Network Supports the full implementation of the CAN
(CAN)
Specification Version 2.0, Part B
Serial Peripheral
Interface (SPI)
Synchronous serial bus for communication to an
external device
Inter-Integrated Circuit
(I2C)
Allows communication between a number of
devices. Also supports the System Management
Bus (SMBus) Specification, version 2.
FlexCAN Instantiation
• SPI Instantiation
• Number of PCS
Instantiation Information
Universal asynchronous Asynchronous serial bus communication
receiver/transmitters
interface with programmable 8- or 9-bit data
(UART)
format and support of ISO 7816 smart card
interface
•
•
•
•
Secure Digital host
controller (SDHC)
• SD bus pullup/pulldown constraints
• SDHC Wakeup
• SDHC Software Guidelines
Interface between the host system and the SD,
SDIO, MMC, or CE-ATA cards. The SDHC acts
as a bridge, passing host bus transactions to the
cards by sending commands and performing
data accesses to/from the cards. It handles the
SD, SDIO, MMC, and CE-ATA protocols at the
transmission level.
UART configuration information
UART wakeup
UART interrupts
UART Instances Register Difference
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Modules on the device
Table 2-9. Communication modules (continued)
Module
Description
Reference links to the chip related
information
Media Local Bus (MLB) Implements the Physical Layer and Link Layer of Instantiation
the MediaLB specification, interfacing to an MLB
(R-Series only)
controller. The MLB implements the 3-pin MLB
mode and can run at speeds up to 1024Fs.
2.5.8 Graphics Modules
The following core modules are available on the VFxxx Controller devices. For modules
enabled on a specific part, refer to the data sheets.
Table 2-10. Graphics/Display Modules
Module
Description
Reference links to chip related information
Display Controller Unit
(DCU4)
It is a system master that fetches graphics stored DCU Instantiation
in internal or external memory and displays them
on a TFT LCD panel. It supports:
• Full RGB888 output to TFT LCD panel
• 64 graphics layers, a default background
color layer and a cursor layer with
integrated blinking option
• Blending of each pixel using up to 6 source
layers dependent on size of panel
• Programmable panel size up to XGA
(1008x768)
• Gamma correction with 8-bit resolution on
each color component
• Safety mode for tagging pixels on highest
priority layers
• Dedicated memory blocks to store a cursor
and Color Look Up Tables (CLUTs)
• Temporal Dithering
GPU
Defines a high-performance graphics core
designed for hardware acceleration of OpenVG
vector graphics display on a variety of consumer
devices.
(R-Series only)
RLE
Decodes data that has been compressed using a RLE Instantiation
Run Length Encoding (RLE) scheme. It has input
and output FIFO buffers directly connected to the
crossbar switch and requires the CPU or DMA to
push in the encoded data and then extract the
decoded result. The module configuration is
optimized for decoding data stored in a twodimensional image format but can also be used
to extract data stored as a linear array.
• 32 channels support independent
• 8/16/32-bit single value or block transfers
• Supports variable sized queues and
circular queues
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Table 2-10. Graphics/Display Modules (continued)
Module
Description
Reference links to chip related information
• Source and destination address registers
are independently configured to
postincrement or remain constant
• Each transfer is initiated by a peripheral,
CPU, periodic timer interrupt or eDMA
channel request
• Each DMA channel can optionally send an
interrupt request to the CPU on completion
of a single value or block transfer
• DMA transfers possible between system
memories, General Purpose I/Os (GPIOs)
and Slave Peripherals that support DMA
• Programmable DMA Channel Mux allows
assignment of any DMA source to any
available DMA channel with up to a total of
64 potential request sources
The Timing Controller module (TCON) provides TCON Instantiation
an alternative interface for the DCU that provides
RGB data and timing signals for "raw" TFT
panels which have no embedded TCON.
TCON
• Flexible timing generation unit supporting
12 timing signal channels
• Supports bit mapping of 8-bit or 6-bit color
depth
• Blanking of RGB data during inactive
period (driven to all "0" or all "1")
2.5.9 Analog modules
The following analog modules are available on this device:
Table 2-11. Analog modules
Module
Description
Reference links to chip related information
12-bit analog-to-digital
converter (ADC)
It is a successive approximation ADC designed
for operation within an integrated microcontroller
system-on-chip.
• ADC Instantiation
• Voltage reference selection (REFSEL
settings)
• DMA Support on ADC
• ADC Channel Assignments
• ADC interconnections
Video ADC
The VideoADC module comprises an analog
Instantiation
front end and video decoder block allowing up to
4 composite video sources to be connected. The
Video ADC accepts NTSC and PAL format
composite video, digitises, filters and decode this
video and outputs a digital video stream to the
VIU module for further processing.
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Modules on the device
Table 2-11. Analog modules (continued)
Module
Description
Temperature Voltage
Monitor
It contains the voltage and temperature monitor
circuits. These circuits are put into a separate
power domain. Its features are:
• Low power designs to support the coin
battery
• Trimmable Voltage and Temperature
detector thresholds
Power Management
Unit (PMU)
The PMU of the device includes:
• High power or main regulator (HPREG)
• Voltage reference for HPREG
• Low power regulator (LPREG)
• Ultra low power regulator (ULPREG)
• Voltage reference for LPREG and
ULPREG
• Low voltage detector for 3.3V supply
• Separate Low voltage detectors for
HPREG ,LPREG ,ULPREG output voltages
· Power on Reset(POR)
• Power up sequencing and testing
• N-well bias circuit
Reference links to chip related information
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Chapter 3
Chip Configuration
3.1 Introduction
This chapter provides implementation details of the modules that are described in this
manual. Many modules used on this device are also used on other NXP processors, such
as i.MX and Kinetis. Therefore, the module documentation is generic and may describe
features or ports that are not used or not implemented on this processor. Likewise, there
may be implementation details like interrupts, clock sources, and signal multiplexing that
are specific for each device.
This chapter also provides the following information:
• Specific module-to-module interactions not necessarily discussed in the individual
module chapters
• Number of instances of the module in the device and their features
• Number of instances of the module in the device and the differences in the features
(if any)
• Register differences between the multiple instances of a module
3.2 Core modules
3.2.1 Cortex-M4 Processor Core
Cortex-M4 implements the ARMv7-ME instruction set architecture (ISA): this is the
Thumb2 definition - it provides compatibility with Cortex-M3 and adds significant new
capabilities with DSP and SIMD extensions. The basic multiply-accumulate instructions
support operations up to 32 x 32 + 64. Cortex-M4 also includes a single-precision
floating-point unit (FPU), which includes an extension register file of thirty-two 32-bit
floating-point data registers. Cortex-M4 complex includes the FPU and two 32-bit system
bus interfaces. The device Cortex-M4 implementations include two tightly-coupled local
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Core modules
memories and two cache memories connected to these bus interfaces although the device
implementation connects to the 64-bit system bus interconnect and supports a 32-byte
cache line size.
• L1 2-way set-associative 16kB Instruction cache with 32B line size length
• L1 2-way set-associative 16kB Data cache with 32B line size length
Cortex-M4
core complex
NVIC
FPU
Cortex-M4
CPU
FPB
Cortex-M4
core
DWT
Bus matrix
AP
System bus
ITM
Code bus
RAM
array
TCMU
TCML
RAM
array
Tag/data
arrays
Sys-$
Code-$
Tag/data
arrays
SysBIU
64
AHB system bus
CodeBIU
64
64
AHB code bus
Backdoor port
Figure 3-1. Cortex-M4 Block Diagram
Cortex-M4 core features a single issue, three stage pipeline microarchitecture. A highlevel spatial pipeline block diagram of the CPU is shown below. The stages of the
pipeline include:
• Fe - Instruction fetch stage where data is returned from instruction memory
• De - Instruction decode stage, generation of Load/Store Unit (LSU) address using
forwarded register ports and immediate offset of LR register branch forwarding
• Ex - Instruction execute stage, single pipeline with multi-cycle stalls, LSU address/
data pipelining to AHB interface, multiply/divide and ALU with branch result
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LSU branch result
Fe
De
Ex
Address
generation
unit
Fetch
Data
phase
load/store
and
branch
Address
phase
and
writeback
Instruction
decode
and
register
read
Multiply
and
divide
Shift
WR
ALU
and
branch
Branch
Branch forwarding and speculation
ALU branch not forwarded/speculated
LSU branch result
Figure 3-2. Cortex-M4 Pipeline Block Diagram
3.2.2 Cortex-M4 Instruction Fetches on the System Bus
The Cortex-M4 processors implement multiple 32-bit bus interfaces that support a
Harvard memory architecture. Specifically, the cores provide a modified Harvard
connection with 2-cycle pipelined AMBA-AHB code and system buses. The modified
Harvard memory architecture results since the bus interfaces are activated by address
range and include both instruction fetches and operand data references on a given bus
port. A traditional Harvard architecture separates instruction fetches and operand data
references onto specific bus ports regardless of access address.
The code bus is typically used for instruction fetching and data accesses of PC-relative
data, while the system bus is typically used for operand data references to the on- and offchip memories and peripheral accesses. This bus structure fully supports concurrent
instruction fetch and data accesses, but the Cortex-M4 implementations can generate both
types of references on each bus. Additionally, there is a separate 32-bit Private Peripheral
Bus (PPB) connection to several important modules (for example, the Nested Vectored
Interrupt Controller) accessible to only the core. By placing the various code and data
sections in the appropriate locations within the memory map, overall system performance
can be maximized.
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Core modules
To provide a “clean timing interface” on the core's system bus, instruction and vector
fetch requests to this bus are registered. This increases fetch time by an additional cycle
of latency because instructions fetched from the system bus take a minimum of two
cycles. This also means that back-to-back instruction fetches from the system bus are not
possible.
Instruction fetch requests to the code bus are not registered. It is recommended that
performance critical code be located such that it fetches from the ICode bus interface as
defined by addresses < 0x2000_0000 (the system bus interface includes the addresses > =
0x2000_0000 and < 0xE000_0000 and the Private Peripheral Bus is used for addresses
>= 0xE000_0000).
NOTE
In the device, the memory map includes aliased address spaces
that are mapped into the ICode region for code sections that
reside in the system address space. As a simple example, the
DDR address space is located in the system region of the
memory map, but a subset of this space is aliased so that it
appears in the ICode region that instructions mapped into the
DDR space can be executed as maximum performance.
3.2.3 Cortex-A5 Processor Core
The Cortex-A5 processor is a high-performance, low-power ARM macrocell with an L1
cache subsystem that provides full virtual memory capabilities. The core supports the
ARMv7-A instruction set architecture (supporting 32-bit ARM plus 16- and 32-bit
Thumb{-2} instructions) and the microarchitecture has been optimized for area,
performance/power efficiency, scalability and flexibility. It is architecturally compatible
with the Cortex-A9.
It includes both an FPU and the NEON Media Processing Engine. The Cortex-A5
Floating Point Unit (FPU) is a VFPv4-D16 implementation of the ARM v7 floating-point
architecture. The unit provides floating-point computation functionality that is compliant
with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic
(IEEE 754).
The FPU includes all data processing instructions and data types in the VFPv4
architecture and fully supports single-precision and double-precision add, subtract,
multiply, divide, multiply and accumulate, and square root operations. It also provides
conversions between fixed-point and floating-point data formats, and floating-point
constant instructions. The FPU is tightly integrated to the Cortex-A5 processor pipeline.
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The NEON Media Processing Engine (MPE) extends the capabilities of the FPU with an
implementation of the ARM NEON Advanced SIMD v2 instruction set for further
acceleration of media and signal processing functions. It includes an additional register
set supporting a rich set of SIMD operations over 8, 16, and 32-bit integer and 32-bit
floating-point data types. The Cortex-A5 implements TrustZone® Technology to ensure
reliable implementation of security applications ranging from digital rights management
to electronic payment.
Figure 3-3. Cortex-A5 Processor Core Block Diagram
The processor microarchitecture implements a single issue, 8-stage pipeline design
capable of 1.57 DMIPS per MHz performance. For the device, the configurable L1
caches are defined as 32K I- and 32K D-Caches and the system bus interface is a high
performance 64-bit AXI bus that supports multiple outstanding transactions and has over
3x the memory bandwidth of the ARM1176JZ-S.
• L1 2-way set-associative 32 KB Instruction cache with 32B line size length
• L1 4-way set-associative 32 KB Data cache with 32B line size length
• L2 8-way set associative 512 KB cache with 32B line size length
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Figure 3-4. Cortex-A5 Processor Pipeline Organization
3.2.4 Interrupt Assignments
Cortex-A5 uses the ARM Generic Interrupts Controller (GIC) architecture version 1.0.
Cortex-M4 uses the Nested Vectored Interrupt Controller (NVIC).
All peripheral interrupts on the device will be directed to a specific interrupt controller
(GIC or NVIC) through an Interrupt Router module. In addition to the shared peripheral
interrupts, there are CPU-to-CPU interrupts that will pass through the Interrupt Router.
Finally, a small number of private peripheral interrupts to each core will connect directly
to the NVIC or the GIC. For example, the L2 cache interrupts that are only relevant to the
CortexA5 core. The GIC can support up to 16 Private Peripheral Interrupts (PPIs).
NOTE
This is a combined Reference Manual for both the VFxxx
Controller F-Series and R-Series. Not all features listed in this
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document are available on all parts. For features enabled on a
specific part, refer to the data sheets.
Table 3-1. Interrupt Assignment
Vector
Offset
Address
Cortex-M4
Vector
0x0000_0000
NVIC
Interrupt ID
Name
Cortex-A5
Vector
0
Initial Stack
Pointer
0x0000_0004
1
0x0000_0008
GIC Interrupt
ID
Type
Name
0
h/w
Reset
Initial Program
Counter
1
h/w
Undefined
Instruction
2
NMI
2
h/w
Supervisor
Call
0x0000_000C
3
Hard Fault
3
h/w
Prefetch Abort
0x0000_0010
4
4
h/w
Data Abort
0x0000_0014
5
Bus Fault
5
0x0000_0018
6
Usage Fault
6
IRQ
h/w
IRQ
0x0000_001C
7
7
FIQ
h/w
FIQ
0x0000_0020
8
8
0x0000_0024
9
9
0x0000_0028
10
10
h/w
0x0000_002C
11
SVCall
11
h/w
0x0000_0030
12
Debug
Monitor
12
h/w
0x0000_0034
13
13
h/w
0x0000_0038
14
PendableSrvR
eq
14
h/w
0x0000_003C
15
SysTick
15
h/w
h/w
SMC
h/w
Secure
Monitor Call
h/w
16
0
SGI
Softwaregenerated int
17
1
SGI
Softwaregenerated int
18
2
SGI
Softwaregenerated int
19
3
SGI
Softwaregenerated int
20
4
SGI
Softwaregenerated int
21
5
SGI
Softwaregenerated int
22
6
SGI
Softwaregenerated int
23
7
SGI
Softwaregenerated int
24
8
SGI
Softwaregenerated int
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Table 3-1. Interrupt Assignment (continued)
Vector
Offset
Address
Cortex-M4
Vector
NVIC
Interrupt ID
Name
Cortex-A5
Vector
GIC Interrupt
ID
Type
Name
25
9
SGI
Softwaregenerated int
26
10
SGI
Softwaregenerated int
27
11
SGI
Softwaregenerated int
28
12
SGI
Softwaregenerated int
29
13
SGI
Softwaregenerated int
30
14
SGI
Softwaregenerated int
31
15
SGI
Softwaregenerated int
32
16
PPI
Private
peripheral int
33
17
PPI
Private
peripheral int
34
18
PPI
Private
peripheral int
35
19
PPI
Private
peripheral int
36
20
PPI
Private
peripheral int
37
21
PPI
Private
peripheral int
38
22
PPI
Private
peripheral int
39
23
PPI
Private
peripheral int
40
24
PPI
Private
peripheral int
41
25
PPI
Private
peripheral int
42
26
PPI
Private
peripheral int
43
27
Global Timer
Private
peripheral int
44
28
Legacy nFIQ
Private
peripheral int
45
29
Core Timer
Private
peripheral int
46
30
Core
Watchdog
Private
peripheral int
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-1. Interrupt Assignment (continued)
Vector
Offset
Address
Cortex-M4
Vector
NVIC
Interrupt ID
Name
Cortex-A5
Vector
GIC Interrupt
ID
Type
Name
47
31
Legacy nIRQ
Private
peripheral int
CPU to CPU and Directed Interrupts (CPU to CPU interrupts pass through the Interrupt Router)
0x0000_0040
16
0
CPU to CPU
int0
48
32
Peripheral
Shared
Interrupts
(PSI)
CPU to CPU
int0
0x0000_0044
17
1
CPU to CPU
int1
49
33
PSI
CPU to CPU
int1
0x0000_0048
18
2
CPU to CPU
int2
50
34
PSI
CPU to CPU
int2
0x0000_004C
19
3
CPU to CPU
int3
51
35
PSI
CPU to CPU
int3
0x0000_0050
20
4
Directed
Cortex-M4(=
SEMA4)
52
36
PSI
Directed
Cortex-A5(=
SEMA4)
0x0000_0054
21
5
Directed
Cortex-M4 (=
MCM)
53
37
PSI
Directed
Cortex-A5 (=
DBG)
0x0000_0058
22
6
Directed
Cortex-M4
54
38
PSI
Directed
Cortex-A5(=
L2CC)
0x0000_005C
23
7
Directed
Cortex-M4
55
39
PSI
Directed
Cortex-A5(=
PMU)
DMA0
DMA transfer
complete
CH0-31
SHARED PERIPHERAL INTERRUPTS (Inputs to Interrupt Router)
On-Platform Vectors
0x0000_0060
24
8
56
40
0x0000_0064
25
9
57
41
0x0000_0068
26
10
58
42
0x0000_006C
27
11
59
43
0x0000_0070
28
12
60
44
0x0000_0074
29
13
61
45
0x0000_0078
30
14
62
46
MSCM-ECC0
0x0000_007C
31
15
63
47
MSCM-ECC1
DMA Error
Interrupt
Channels
0-31
DMA1
DMA transfer
complete
CH0-31
DMA Error
Interrupt
Channels
0-31
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Core modules
Table 3-1. Interrupt Assignment (continued)
Vector
Offset
Address
Cortex-M4
Vector
NVIC
Interrupt ID
0x0000_0080
32
0x0000_0084
Name
Cortex-A5
Vector
GIC Interrupt
ID
Type
16
64
48
CSU_Alarm
33
17
65
49
0x0000_0088
34
18
66
50
0x0000_008C
35
19
67
51
MSCM_ACTZ
S
Name
All CSLn +
TZASC
Off-Platform Vectors
0x0000_0090
36
20
68
52
WDOG-A5
0x0000_0094
37
21
69
53
WDOG-M4
0x0000_0098
38
22
70
54
WDOG-SNVS
0x0000_009C
39
23
71
55
CP1 Boot Fail
0x0000_00A0
40
24
72
56
QuadSPI0
0x0000_00A4
41
25
73
57
QuadSPI1
0x0000_00A8
42
26
74
58
DDRMC
0x0000_00AC
43
27
75
59
SDHC0
0x0000_00B0
44
28
76
60
SDHC1
0x0000_00B4
45
29
77
61
Reserved
0x0000_00B8
46
30
78
62
DCU0
0x0000_00BC
47
31
79
63
DCU1
0x0000_00C0
48
32
80
64
VIU
0x0000_00C4
49
33
81
65
Reserved
0x0000_00C8
50
34
82
66
GPU (RSeries)
Reserved (FSeries)
0x0000_00CC
51
35
83
67
RLE
0x0000_00D0
52
36
84
68
SEG LCD
0x0000_00D4
53
37
85
69
Reserved
0x0000_00D8
54
38
86
70
Reserved
0x0000_00DC
55
39
87
71
PIT
0x0000_00E0
56
40
88
72
LPTimer0
0x0000_00E4
57
41
89
73
Reserved
0x0000_00E8
58
42
90
74
FlexTimer0
0x0000_00EC
59
43
91
75
FlexTimer1
0x0000_00F0
60
44
92
76
FlexTimer2
0x0000_00F4
61
45
93
77
FlexTimer3
0x0000_00F8
62
46
94
78
Reserved
0x0000_00FC
63
47
95
79
Reserved
0x0000_0100
64
48
96
80
Reserved
0x0000_0104
65
49
97
81
Reserved
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Table 3-1. Interrupt Assignment (continued)
Vector
Offset
Address
Cortex-M4
Vector
NVIC
Interrupt ID
0x0000_0108
66
0x0000_010C
Name
Cortex-A5
Vector
GIC Interrupt
ID
Type
Name
50
98
82
ANADIG
USBPHY 0
67
51
99
83
ANADIG
USBPHY 1
0x0000_0110
68
52
100
84
Reserved
0x0000_0114
69
53
101
85
ADC0
0x0000_0118
70
54
102
86
ADC1
0x0000_011C
71
55
103
87
DAC0
0x0000_0120
72
56
104
88
DAC1
0x0000_0124
73
57
105
89
Reserved
0x0000_0128
74
58
106
90
FlexCAN0
0x0000_012C
75
59
107
91
FlexCAN1
0x0000_0130
76
60
108
92
MLB (RSeries)
Reserved (FSeries)
0x0000_0134
77
61
109
93
UART0
0x0000_0138
78
62
110
94
UART1
0x0000_013C
79
63
111
95
UART2
0x0000_0140
80
64
112
96
UART3
0x0000_0144
81
65
113
97
UART4
0x0000_0148
82
66
114
98
UART5
0x0000_014C
83
67
115
99
SPI0
0x0000_0150
84
68
116
100
SPI1
0x0000_0154
85
69
117
101
SPI2
0x0000_0158
86
70
118
102
SPI3
0x0000_015C
87
71
119
103
I2C0
0x0000_0160
88
72
120
104
I2C1
0x0000_0164
89
73
121
105
I2C2
0x0000_0168
90
74
122
106
I2C3
0x0000_016C
91
75
123
107
USBC0
0x0000_0170
92
76
124
108
USBC1
0x0000_0174
93
77
125
109
Reserved
0x0000_0178
94
78
126
110
ENET0
0x0000_017C
95
79
127
111
ENET1
0x0000_0180
96
80
128
112
1588 Timer 0
0x0000_0184
97
81
129
113
1588 Timer 1
0x0000_0188
98
82
130
114
ENET Switch
0x0000_018C
99
83
131
115
NFC
0x0000_0190
100
84
132
116
SAI0
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Table 3-1. Interrupt Assignment (continued)
Vector
Offset
Address
Cortex-M4
Vector
NVIC
Interrupt ID
0x0000_0194
101
0x0000_0198
Name
Cortex-A5
Vector
GIC Interrupt
ID
Type
Name
85
133
117
SAI1
102
86
134
118
SAI2
0x0000_019C
103
87
135
119
SAI3
0x0000_01A0
104
88
136
120
ESAI_BIFIFO
0x0000_01A4
105
89
137
121
SPDIF
0x0000_01A8
106
90
138
122
ASRC
0x0000_01AC
107
91
139
123
VREG
0x0000_01B0
108
92
140
124
WKPU0
0x0000_01B4
109
93
141
125
Reserved
0x0000_01B8
110
94
142
126
CCM
FXOSC ready
interrupt
0x0000_01BC
111
95
143
127
CCM
Logical OR of
LRF of PLL1,
PLL2, PLL3
and PLL4
0x0000_01C0
112
96
144
128
SRC
0x0000_01C4
113
97
145
129
PDB
0x0000_01C8
114
98
146
130
EWM
0x0000_01CC
115
99
147
131
Reserved
0x0000_01D0
116
100
148
132
Reserved
Reserved
0x0000_01D4
117
101
149
133
Reserved
Reserved
0x0000_01D8
118
102
150
134
Reserved
0x0000_01DC
119
103
151
135
Reserved
0x0000_01E0
120
104
152
136
Reserved
0x0000_01E4
121
105
153
137
Reserved
0x0000_01E8
122
106
154
138
Reserved
0x0000_01EC
123
107
155
139
GPIO0
Pin
Interrupts /
Wake-ups
0x0000_01F0
124
108
156
140
GPIO1
Pin
Interrupts /
Wake-ups
0x0000_01F4
125
109
157
141
GPIO2
Pin
Interrupts /
Wake-ups
0x0000_01F8
126
110
158
142
GPIO3
Pin
Interrupts /
Wake-ups
0x0000_01FC
127
111
159
143
GPIO4
Pin
Interrupts /
Wake-ups
HVD Interrupt
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The following diagram shows the high level architecture of the device interrupts.
Cortex-M4
Cortex-A5
(NVIC)
Nested vectored
interrupt controller
(GIC)
Generic interrupt controller
4
Private
Cortex-M4
interrupts
– MCM
– debug specific
Peripheral Shared
interrupts (PSIs)
– on platform
– off platform
n
n
4
Interrupt
router
(part of
platform)
PSI
SGI
PPI
n
4
4
4
FIQ
IRQ
Cortex-A5
private peripheral
interrupts (PPIs)
– L2 cache
– debug specific
CPU-to-CPU
interrupts
3.3 DMAMUX Request Sources
3.3.1 DMAMUX Request Sources
This device includes a DMA request mux that allows up to 64 DMA request signals to be
mapped to any of the 16 DMA channels. The first four channels of DMAMUX provide
periodic triggering capability. The trigger is generated by Periodic Interrupt Timer
(PIT[3:0]).
Each DMA includes two DMA request MUXes that allows up to 126 DMA request
signals. As shown in the figure below, requests from MUX0 can be mapped to any of the
first 16 DMA0 channels [15:0] and from MUX1, to any of the upper 16 DMA0 channels
[31:16]. Likewise, MUX2 can be mapped to any of the first 16 DMA1 channels [15:0]
and from MUX3 to any of the upper 16 DMA1 channels [31:16].
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DMAMUX Request Sources
15:0
31:16
15:0
31:16
Figure 3-5. DMA Request MUX/DMA Structure
To allow for flexibility and optimal usage of the available DMA channels some of the
DMA request sources are available on both muxes.
Because of the mux there is not a hard correlation between any of the DMA request
sources and a specific DMA channel.
NOTE
Two duplicate Channel Muxes cannot be enabled
simultaneously for two (same) peripherals.
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Table 3-2. DMA request sources - DMA0 (MUX 0)/DMA1 (MUX3)
Source
number
Source module
Source description
0
—
Channel disabled1
1
Reserved
Not used
2
UART0
Receive
3
UART0
Transmit
4
UART1
Receive
5
UART1
Transmit
6
UART2
Receive
7
UART2
Transmit
8
UART3
Receive
9
UART3
Transmit
10
Reserved
—
11
Reserved
—
12
SPI0
Receive
13
SPI0
Transmit
14
SPI1
Receive
15
SPI1
Transmit
16
SAI0
(I2S0)
Receive
17
SAI0(I2S0)
Transmit
18
SAI1
(I2S1)
Receive
SAI1
(I2S1)
Transmit
20
SAI2
(I2S2)
Receive
21
SAI2 (I2S2)
Transmit
22
PDB
—
23
Reserved
—
24
FTM0
Channel 0
25
FTM0
Channel 1
26
FTM0
Channel 2
27
FTM0
Channel 3
28
FTM0
Channel 4
29
FTM0
Channel 5
30
FTM0
Channel 6
31
FTM0
Channel 7
32
FTM1
Channel 0
33
FTM1
Channel 1
34
ADC0
—
35
Reserved
—
36
QuadSPI0
—
37
Reserved
—
38
Port control module
Port A
19
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DMAMUX Request Sources
Table 3-2. DMA request sources - DMA0 (MUX 0)/DMA1 (MUX3) (continued)
Source
number
Source module
Source description
39
Port control module
Port B
40
Port control module
Port C
41
Port control module
Port D
42
Port control module
Port E
43
Reserved
—
44
Reserved
—
45
RLE-RX
Receive
46
RLE-TX
Transmit
47
SPDIF
Receive
48
SPDIF
Transmit
49
Reserved
50
I2C0
Receive
51
I2C0
Transmit
52
I2C1
Receive
53
I2C1
Transmit
54
DMA MUX
Always enabled
55
DMA MUX
Always enabled
56
DMA MUX
Always enabled
57
DMA MUX
Always enabled
58
DMA MUX
Always enabled
59
DMA MUX
Always enabled
60
DMA MUX
Always enabled
61
DMA MUX
Always enabled
62
DMA MUX
Always enabled
63
DMA MUX
Always enabled
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
Table 3-3. DMA request sources - DMA1 (MUX 2)/DMA0 (MUX1)
Source
number
Source module
Source description
0
—
Channel disabled1
1
Reserved
Not used
2
UART4
Receive
3
UART4
Transmit
4
UART5
Receive
5
UART5
Transmit
6
Reserved
—
7
Reserved
—
Table continues on the next page...
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Table 3-3. DMA request sources - DMA1 (MUX 2)/DMA0 (MUX1) (continued)
Source
number
Source module
Source description
8
SAI3 (I2S3)
Receive
9
(I2S3)
Transmit
SAI3
10
SPI2
Receive
11
SPI2
Transmit
12
SPI3
Receive
13
SPI3
Transmit
14
Reserved
—
15
Reserved
—
16
FTM2
Channel 0
17
FTM2
Channel 1
18
FTM3
Channel 0
19
FTM3
Channel 1
20
FTM3
Channel 2
21
FTM3
Channel 3
22
FTM3
Channel 4
23
FTM3
Channel 5
24
FTM3
Channel 6
25
FTM3
Channel 7
26
ADC1
—
27
QuadSPI1
—
28
Reserved
—
29
Reserved
—
30
Reserved
—
31
Reserved
—
32
DAC0
—
33
DAC1
—
34
ESAI_BIFIFO
Transmit
35
ESAI_BIFIFO
Receive
36
I2C2
Receive
37
I2C2
Transmit
38
I2C3
Receive
39
I2C3
Transmit
40
ASRC
1
41
ASRC
4
42
ASRC
2
43
ASRC
5
44
Reserved
—
45
Reserved
46
Reserved
—
Table continues on the next page...
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Wakeup Unit (WKPU)
Table 3-3. DMA request sources - DMA1 (MUX 2)/DMA0 (MUX1) (continued)
Source
number
Source module
Source description
47
Reserved
48
Reserved
49
Reserved
50
Reserved
51
Reserved
—
52
ASRC
3
53
ASRC
6
54
DMA MUX
Always enabled
55
DMA MUX
Always enabled
56
DMA MUX
Always enabled
57
DMA MUX
Always enabled
58
DMA MUX
Always enabled
59
DMA MUX
Always enabled
60
DMA MUX
Always enabled
61
DMA MUX
Always enabled
62
DMA MUX
Always enabled
63
DMA MUX
Always enabled
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
3.4 Wakeup Unit (WKPU)
3.4.1 WKPU configuration
The WKPU includes the following features.
•
•
•
•
•
•
One NMI source
17 external interrupt sources with glitch filtering
One external interrupt vector
Four on-chip wakeup sources
12-bit address width
00000000b NMI default destination address
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The table below shows the internal and external inputs to the WKUP module supported
by the device. The signals are in the order that they appear in the wakeup unit Enable and
Status registers. The first signal in the table corresponds to bit b0.
Table 3-4. WKUP Pins
Wakeup
Source
NVIC Interrupt ID
NMI
WKPU_P0
PTB0
INT92
No
WKPU_P1
PTB1
INT92
No
WKPU_P2
PTB2
INT92
No
WKPU_P3
PTB3
INT92
No
WKPU_P4
PTB4
INT92
No
WKPU_P5
PTB5
INT92
No
WKPU_P6
PTB6
INT92
No
WKPU_P7
PTB7
INT92
No
WKPU_P8
PTB11
INT92
No
WKPU_P9
PTB12
INT92
Yes
WKPU_P10
PTB14
INT92
No
WKPU_P11
PTB16
INT92
No
WKPU_P12
PTB19
INT92
No
WKPU_P13
PTB20
INT92
No
WKPU_P14
PTB27
INT92
No
WKPU_P15
PTC30
INT92
No
WKPU_P16
PTE20
INT92
No
WKPU_M0IF
LPTIMER
NA
NA
WKPU_M1IF
NA
NA
NA
WKPU_M2IF
ADC0
NA
NA
WKPU_M3IF
ADC1
NA
NA
WKPU_M4IF
-
NA
NA
NOTE
The wakeup unit cannot wake the core from STOP mode as it
needs the IPG-CLK to generate the wakeup interrupt.
3.5 CMU Chip Signals
3.5.1 CMU Chip Signals
This table correlate the chip-level signal name with the signal name used in the module's
chapter.
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Cyclic Redundancy Check (CRC)
Table 3-5. CMU Signals Mapping
Chip Signal Name
Module Signal Name
Bus Clock
CLKMN1f
FXOSC
CLKMN0_RMT
FIRC
CLKMT0_RMN
SIRC
CLKMT1
Tied to 0
CLKMT2
3.6 Cyclic Redundancy Check (CRC)
3.6.1 CRC Reverse Logic Functions
Reverse logic functions are not available in this implementation.
3.7 External Watchdog Monitor
The external watchdog monitor (EWM) has support for 4 clock sources, selectable in the
EWM module's EWM_CLKCTRL register. In this device, only the 32-KHz clock is used
as source and is always selected.
The EWM input is pin PTE20 and the output pin is PTE28. To use these pins for EWM
functionality, they must be configured in the IOMUX.
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3.8 Timers
3.8.1 FlexTimer
3.8.1.1 Instantiation Information
The following table shows how these modules are configured, including the number of
channels supported.
Table 3-6. FTM Instantiations
176 LQFP
364 BGA
Features/Usage
FTM0
8
8
3-phase motor + 2 general
purpose or stepper motor
FTM1
2
2
Quadrature decoder or
general purpose
FTM2
2
2
Quadrature decoder or
general purpose
FTM3
0
8
3-phase motor + 2 general
purpose or stepper motor
The FTM1 and FTM2 configuration differs from the FTM0 and FTM3 configuration by
reduced number of channels and adding Quadrature decoder.
3.8.1.2 FTM Clock Input
The FTM module's external clock input can be sourced from any of the slow oscillators,
the fast oscillator, or the external audio master clock (EXT_AUDIO_MCLK).
For details, see FTM clocking.
3.8.1.3 FTM Hardware Triggers
Following table provides the hardware trigger options for FTMs.
Table 3-7. FTM Hardware Trigger options
Hardware Triggers
Trigger 1
FTM0
ADC0
FTM1
ADC0
FTM2
ADC0
FTM3
ADC0
Table continues on the next page...
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FlexTimer
Table 3-7. FTM Hardware Trigger options (continued)
Hardware Triggers
FTM0
FTM1
FTM2
FTM3
Trigger 2
ADC1
ADC1
ADC1 or USB1 SOF
ADC1 or USB1 SOF
Trigger 3
EXTRIG or USB0 SOF
EXTRIG or USB0 SOF
EXTRIG or USB0 SOF
EXTRIG or USB0 SOF
Each flextimer has 3 trigger inputs (0/1/2) which are configured using SRC_MISC0
register.
The following figures show the flextimer triggers for each instance.
ADC0 Conversion Complete
ADC1 Conversion Complete
USB0SOF
TRIG0
TRIG1
0
TRIG2
EXTRIG
1
SRC_MISC0[26]
FTM0
Figure 3-6. FTM0 Triggers
ADC0 Conversion Complete
ADC1 Conversion Complete
USB0SOF
TRIG0
TRIG1
0
TRIG2
EXTRIG
1
SRC_MISC0[27]
FTM1
Figure 3-7. FTM1 Triggers
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ADC0 Conversion Complete
USB1SOF
ADC1 Conversion
Complete
TRIG0
0
TRIG1
1
SRC_MISC0[28]
USB0SOF
0
TRIG2
EXTRIG
1
SRC_MISC0[29]
FTM2
Figure 3-8. FTM2 Triggers
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FlexTimer
ADC0 Conversion Complete
USB1SOF
ADC1 Conversion
Complete
TRIG0
0
TRIG1
1
SRC_MISC0[30]
USB0SOF
0
TRIG2
EXTRIG
1
SRC_MISC0[31]
FTM3
Figure 3-9. FTM3 Triggers
3.8.1.4 FTM output triggers for other modules
Following are the FTM Output Triggers options
•
•
•
•
ADC0
ADC1
DAC0
DAC1
3.8.1.5 FTM Global Time Base
This chip provides the optional FTM global time base feature (see Global time base
(GTB)).
FTM0 provides the only source for the FTM global time base. The other FTM modules
can share the time base as shown in the following figure:
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FTM1
CONF Register
GTBEOUT = 0
GTBEEN = 1
FTM0
CONF Register
GTBEOUT = 1
GTBEEN = 1
gtb_in
FTM Counter
gtb_in
FTM Counter
gtb_out
FTM2
CONF Register
GTBEOUT = 0
GTBEEN = 1
FTM Counter
gtb_in
FTM3
CONF Register
GTBEOUT = 0
GTBEEN = 1
FTM Counter
gtb_in
Figure 3-10. FTM Global Time Base Configuration
3.8.1.6 FTM Fault Detection Inputs
Fault inputs are useful for motor control. For motor control applications, the inputs come
from a comparator. This device doesn’t have an on-chip comparator; however, this device
can still be used for Motor control. External interrupts (or GPIOs) from a comparator on
the board can be used to indicate Fault inputs from the Motor.
In this case, the SRC would include the four Fault Inputs bits. Whenever a fault is
asserted, software can write the appropriate register in SRC and this value will be driven
internally to FTM.
3.8.2 Programmable Interrupt Timer(PIT)
3.8.2.1 PIT Instantiations
This device contains one PIT module with eight channels.
3.8.2.2 PIT/DMA Periodic Trigger Assignments
The PIT generates periodic trigger events to the DMA Mux as shown in the table below.
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Programmable Delay Block (PDB)
Table 3-8. PIT channel assignments for periodic DMA triggering
DMA Channel Number
PIT Channel
DMA Channel 0
PIT Channel 0
DMA Channel 1
PIT Channel 1
DMA Channel 2
PIT Channel 2
DMA Channel 3
PIT Channel 3
NOTE
When DMA channel is enabled with periodic triggering
capability, and using "always enabled" DMA sources, PIT
trigger is ignored.
NOTE
To implement gating the request from "always enabled" source,
follow the steps below to re-assert the request:
1. Set DREQ bit in DMA_TCDn_CSR register and
DMAMUX_CHCFGn[ENBL] = 0
2. Set DMAMUX_CHCFGn[ENBL] = 1, DMASREQ =
channel in your DMA DONE interrupt service routine so
that "always enabled" source could negate its request.
Then, DMA request could be negated.
3.8.3 Programmable Delay Block (PDB)
3.8.3.1 PDB Instantiation
This device has one instance of PDB.
3.8.3.1.1
PDB Output Triggers
Table 3-9. PDB Output Triggers
PDB Parameter
Value
Number of ADC channels
2
Number of pre-triggers per ADC channel
2
Number of DAC interval triggers
2
PulseOut channels
None
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3.8.3.1.2
PDB Input Trigger Connections
Table 3-10. PDB Input Trigger Options
PDB Trigger
PDB Input
0000
External Trigger at RGPIO[25]
0001
PIT Ch 0 Output
0010
PIT Ch 1 Output
0011
PIT Ch 2 Output
0100
PIT Ch 3 Output
0101
PIT Ch 4 Output
0110
PIT Ch 5 Output
0111
PIT Ch 6 Output
1000
Init and Ext Triggers from FTM0
1001
Init and Ext Triggers from FTM1
1010
Init and Ext Triggers from FTM2
1011
Init and Ext Triggers from FTM3
1101
RTC Alarm
1110
LPT Output
1111
Software Trigger
3.8.3.2 PDB Module Interconnections
PDB trigger outputs
Connection
Channel 0 triggers
ADC0 trigger
Channel 1 triggers
ADC1 trigger
3.8.3.3 DMA support on PDB
The PDB supports the DMA request functionality. One DMA request is supported.
3.8.3.4 PDB in Low-Power modes
PDB is available in the WAIT, LPRUN, UPLRUN, and STOP modes. However, the PDB
is in power-gated domain and is not available in the LPSTOP1, LPSTOP2, and LPSTOP3
Low-Power Stop modes. In Low-Power Stop modes, the ADC is triggered using the
Low-Power Timer (LPTMR).
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Programmable Delay Block (PDB)
3.8.3.5 PDB implementation with ADC
The following figure illustrates the implementation of the PDB interface with ADC.
There is one back-to-back acknowledgement from the ADC0 to channel 0 of the PDB. In
this MCU, PDB back-to-back acknowledgment connection is implemented as follows:
• PDB channel 1 pre-trigger 0 acknowledgement input: ADC0SC1B_COCO
PDB trigger 0
0
Alternate trigger
ADC0
ADC
conversion
complete
1
SRC_MISC1[25]
LPTMR
trigger
2
Channel 0
back-to-back
acknowledgement
(tied to 0)
PDB trigger 1
Alternate trigger
ADC1
0
SRC_MISC1[27:26]
PDB
Channel 1
back-to-back
acknowledgement
1
1'b1
1
ADC0
pre-trigger
0
SRC_MISC1[28]
0
1'b1
External hardware trigger support
ADC0
External hardware trigger support
1
SRC_MISC1[29]
1'b1
1
ADC1
pre-trigger
0
SRC_MISC1[30]
0
1'b1
External hardware trigger support
ADC1
External hardware trigger support
1
SRC_MISC1[31]
Figure 3-11. PDB implementation with ADC
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3.8.4 Low-Power Timer (LPTMR)
3.8.4.1 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four
sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the
chip-specific clock assignments for this bitfield.
NOTE
The chosen clock must remain enabled if the LPTMR is to
continue operating in all required low-power modes.
LPTMR0_PSR[PCS]
Prescaler/glitch filter clock
number
Chip clock
00
0
24MHz FIRC
01
1
1KHz Derived from SIRC
10
2
32KHz SXOSC
11
3
128KHz SIRC
To read about clocking on this device, refer to Clocking Overview.
3.9 External memory interfaces
3.9.1 Quad SPI
3.9.1.1 QuadSPI Instances
There are two instances of the QuadSPI module on this device. QuadSPI0 supports two
serial flash ports, while QuadSPI1 supports a single serial flash port. Each QuadSPI port
implements two chip-selects (CS) enabling two separate serial flashes to be attached to
each individual port. The dual CS arrangement also allows dual-die packaged serial flash
to be connected to a single port of a QuadSPI. The 2-port configuration of QuadSPI0
allows two external flash devices to operate in a parallel read mode with read data from
the flashes being recombined automatically in the QuadSPI module. This effectively
enables an 8-bit flash interface, doubling the read bandwidth and is particularly useful for
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Quad SPI
XiP operation of fast fetch of graphics data from the external flash. Each QuadSPI
implements a flexible 1 KB AHB buffer which can be configured in accordance with
application needs.
Table 3-11. Module Instances
QuadSPI
Serial Flash Ports
# CS per Port
Parallel Mode
AHB Buffer Size
Peak DDR Read
Bandwidth
QuadSPI0
2
2
Yes
1 KB
132 MB
QuadSPI1
1
1
No
1 KB
66 MB
QuadSPI0 and QuadSPI1 are available as multiplexing options on all package variants.
NOTE
Quadspi DQS Loopback mode is not supported on this device.
Any reference to it in this document should be ignored.
3.9.1.2 QuadSPI Memory Interface
Each port of QuadSPI supports the following signals:
•
•
•
•
SCK: Serial Clock
IO[0:3] : Serial I/O for command, address and data
/CS: Chip Select
/CS2: Chip Select 2; used to select second instance of QuadSPI or select a second
flash device sharing SCK and IO[0:3]
• DQS: Data strobe signal for some manufacturers for DDR read timing at 50 MHz
and above
3.9.1.3 QuadSPI Buffer
Each QuadSPI 4 implements a flexible AHB buffer scheme to support multiple data
streams the. The buffer can be partitioned into four separate buffers of different size, each
associated to specific bus masters. In addition, the buffers can be associated with one or
other of the connected serial flashes or both simultaneously. For details on configuration
of the AHB buffers, refer to the QuadSPI chapter in this reference manual.
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3.9.1.4 QuadSPI Clocking
The QuadSPI module's clock configuration is entirely controlled in the CCM module (see
QuadSPI Clocking for details). The SCLKCFG bit field in the QuadSPIx_MCR register
is not used.
3.9.1.5 Booting from QuadSPI
Available frequency in System Boot for booting through QuadsSPI0 with multiple
configuration (SDR, DDR modes):
Table 3-12. Booting from QuadSPI
QuadSPI 0 in DDR Mode
SCK frequency options in MHz
18
QuadSPI 0 in SDR Mode
18, 60, 74
3.9.2 DRAM Controller
3.9.2.1 DDR maximum address space
The maximum address space available for the DDR controller is calculated using the
following formula:
The maximum values available for this device are:
•
•
•
•
Chip selects = 1
Device address = 16 rows + 10 columns = 26
Number of banks = 8
Memory data path width = 2 bytes
As a result, the maximum accessible memory area is 1 GB.
The address map for this configuration is shown below. Address bits 30–31 are not used.
These bits are ignored when generating the address to the DRAM devices.
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Nand Flash Controller
Figure 3-12. Alternate memory map
3.9.3 Nand Flash Controller
3.9.3.1 Instantiation
The NAND Flash Controller(NFC) interfaces standard NAND Flash devices to the IC
and hides the complexities of accessing the NAND Flash. It provides a glueless interface
to both 8-bit and 16-bit NAND Flash parts with page sizes of 512 bytes, 2 KB, 4 KB and
8 KB.
3.9.4 FlexBus Controller
3.9.4.1 FlexBus signal multiplexing
The multiplexing of the FlexBus address and data signals is controlled by the port control
module. However, the multiplexing of some of the FlexBus control signals is controlled
by the port control and FlexBus modules. The port control module registers control
whether the FlexBus or another module signals are available on the external pin, while
the FlexBus's CSPMCR register configures which FlexBus signals are available from the
module. Use the CSPMCR and port control registers to configure which control signal is
available on the external pin.
The control signals are grouped as illustrated:
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CSPMCR
FB_ALE
FB_CS1
FB_TS
Group1
Port Control Module
To other modules
FlexBus
FB_MUXED_ALE
FB_TSIZ0
FB_BE_31_24
Group2
FB_MUXED_TSIZ0
External Pins
Reserved
To other modules
Reserved
Reserved
FB_TSIZ1
FB_BE_23_16
Group3
To other modules
Reserved
FB_MUXED_TSIZ1
FB_TBST
FB_CS2
FB_BE_15_8
Group4
To other modules
Reserved
FB_MUXED_TBST_b
FB_TA
FB_CS3
FB_BE_7_0
Group5
To other modules
Reserved
FB_MUXED_TA_b
Reserved
Figure 3-13. FlexBus control signal multiplexing
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FlexBus Controller
Therefore, use the CSPMCR and port control registers to configure which control signal
is available on the external pin.
3.9.4.2 VFxxx Controller restrictions
VFxxx Controller-specific restrictions to Flexbus Multiplexing:
• Only chip-selects 0-3 are made available on pins.
• Only 32-byte bursts are supported; no 16-byte transfers
• Only Multiplexed Address/Data bus available.
3.9.4.3 FlexBus Signal Multiplexing
The table below shows the FlexBus signal multiplexing on this device.
Table 3-13. FlexBus Multiplexing
Flexbus Signal
CSPMCR bits
Value of
CSPMCR bits
Pad
Connected to
Pin Connected
to
ALT Mode
Signal Name
FB_ALE
[31:28]
0
PAD[93]
PTB23
ALT4
FB_MUXED_AL
E
FB_CS1_b
—
1
—
—
—
—
FB_TS_b
—
2
—
—
—
—
Reserved
—
Rest
—
—
—
—
Reserved
[27:24]
0
PAD[94]
PTB24
ALT4
FB_MUXED_TS
IZ0
FB_SIZE[0]
—
1
—
—
—
—
FE_BE_31_24_
b
—
2
—
—
—
—
Reserved
—
Rest
—
—
—
—
Reserved
[23:20]
0
PAD[102]
PTC29
ALT5
FB_MUXED_TS
IZ1
FB_SIZE[1]
—
1
—
—
—
—
FB_BE_23_16_
b
—
2
—
—
—
—
Reserved
—
Rest
—
—
—
—
FB_TBST_b
[19:16]
0
PAD[97]
PTB27
ALT5
FB_MUXED_TB
ST_b
FB_CS2_b
—
1
—
—
—
—
FB_BE_15_8_b
—
2
—
—
—
—
Reserved
—
Rest
—
—
—
—
FB_TA_b
[15:12]
0
PAD[103]
PTC30
ALT4
FB_MUXED_BE
0_b
FB_CS3_b
—
1
—
—
—
—
FB_BE_7_0_b
—
2
—
—
—
—
Table continues on the next page...
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Table 3-13. FlexBus Multiplexing (continued)
Flexbus Signal
CSPMCR bits
Value of
CSPMCR bits
Pad
Connected to
Pin Connected
to
ALT Mode
Signal Name
Reserved
—
Rest
—
—
—
—
3.9.4.4 FlexBus External Signal
The following sections correlate the chip-level signal with the signal name used in the
module's chapter.
Table 3-14. External Signals
Chip signal name
Module Signal name
FB_BE3_B
FB_BE31_24_B
FB_BE2_B
FB_BE23_16_B
FB_BE1_B
FB_BE15_8_B
FB_BE0_B
FB_BE7_0_B
3.9.4.5 FlexBus Security
FlexBus accesses are moderated by AHB TrustZone that is part of platform.
3.9.4.6 Instantiation Information
The FlexBus module is pinned out with a 32-bit multiplexed address and data bus with
four chip selects. The bus allows for the configurations listed in the table below. In
configurations where the full 32-bit bus is not needed those signals can be used as GPIO
or other multiplexed functions.
NOTE
By default, FlexBus clocks are disabled and have to be
explicitly enabled by software.
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FlexBus Controller
NOTE
Any access to the FlexBus device without clocks initialized
may hang the bus.
Table 3-15. FlexBus Configurations
Number of Address
Lines
Number of Data Lines
Number of External
Signals
CSCR[bit 9] setting
Mode
32
32/16/8
32 (FB_AD[31:0])
1
Multiplexed
FB_AD[31:0] allows for
full 32-bit address with
multiplexed 32-bit, 16bit, or 8-bit data. 8-bit
data comes out on
FB_AD[7:0].
24 or less
16/8
24 or less
(FB_AD[23:0])
1
Multiplexed
FB_AD[23:0] allows for
up to 24 address lines
with multiplexed 16-bit
or 8-bit data. 8-bit data
comes out on
FB_AD[7:0]
24 or less
8
32 or less (FB_AD[23:0]
+ FB_AD[31:24])
0
Non-multiplexed mode.
FB_A[24:0] are
dedicated address
lines. FB_D[7:0]
(FB_AD[31:24]
internally) are used as
dedicated data lines.
16 or less
16
32 or less (FB_AD[15:0]
+ FB_AD[31:16])
0
Non-multiplexed mode.
FB_A[15:0] are
dedicated address
lines. FB_D[15:0]
(FB_AD[31:16]
internally) are used as
dedicated data lines.
0
32/16/8
32, 16, or 8
(FB_AD[31:0],
FB_AD[31:16]/
FB_AD[15:0], or
FB_AD[31:24/
FB_AD[7:0])
0 or 1
Data only mode.
Commonly used for
interfacing to smart
LCD devices. Support
32-bit, 16-bit, or 8-bt
data. Either the upper
or lower half of the data
bus can be used as
selected by CSCR[bit
9].
NOTE
CSCR[bit9] is configured by boot code when Flexbus is
selected as boot device. It is configured by BOOT_CFG1[0].
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3.9.4.7 FlexBus Chip Select Control Register (CSCR0) Reset Value
On this device the Chip Select Control Register (CSCR0) resets to 0x003F_FC00.
Configure this register as needed before performing any FlexBus acccess.
For more information about CSCR0 control bits, see Chip Select Control Register
(FB_CSCRn).
3.9.4.8 Bus Timeout
For scenarios where auto-acknowledge feature is disabled, device can hang if there is no
external FB_TA_b received. To avoid this scenario, a monitor is provided that terminates
a FlexBus transaction as bus error if it does not complete within the specified time. Refer
to SRC_MISC3 register description in System Reset Controller to get details about the
configuration of this counter.
3.10 Communication interfaces
3.10.1 10/100 Ethernet Subsystem
3.10.1.1 Instantiation Information
VFxxx Controller family devices will instantiate Ethernet modules as shown below.
Table 3-16. Ethernet Instantiations
176 LQFP
10/100 Ethernet (MAC-NET
1 (R-Series)
364 BGA
2
2 (F-Series)
L2 Ethernet Switch
None (R-Series)
1
1 (F-Series)
NOTE
MII mode is supported for MAC0 only and when MII mode for
MAC0 is enabled, RMII of MAC1 cannot be used.
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10/100 Ethernet Subsystem
3.10.1.2 MII and RMII configuration
MII is a 4-bit interface, which is clocked at 25 MHz to support 100 Mbits/sec and RMII
is a 2-bit interface clock at 50 MHz to support same data rate. This device has two
Ethernet MACs. MAC0 has been configured to support both RMII and MII, while MAC1
has been configured to support only RMII. Further, if MII interface on MAC0 is enabled,
MAC1 cannot be used for RMII interface. Various pins used in RMII and MII for MAC0
and the pins that can be used are described below.
Table 3-17. MII and RMII configuration for MAC0
Ethernet signal name
Description
Pin configuration in MII
mode
Pin configuration in RMII
mode
Transmitter Signals
TXD0
Transmit data bit 0 (MAC to
PHY)
PTC7-ALT1
PTC7-ALT1
TXD1
Transmit data bit 1 (MAC to
PHY)
PTC6-ALT1
PTC6-ALT1
TXD2
Transmit data bit 2 (MAC to
PHY)
PTD18-ALT6
Not used in RMII mode
TXD3
Transmit data bit 3 (MAC to
PHY)
PTD19-ALT6
Not used in RMII mode
TXEN
Transmit data valid(MAC to
PHY)
PTC8-ALT1
PTC8-ALT1
TXER
Transmit data error(MAC to
PHY)
PTD17-ALT6
Not used in RMII mode
TXCLK
Transmit Clock (PHY to MAC. PTA6-ALT2/ PTA9-ALT3
Can be internal for RMII as
well.)
Both TX and RX clock in RMII
mode are muxed into one
signal. The source can be
either: PTA6-ALT2/ PTA9ALT3/PLL5 main clock/Audio
Ext clock as explained in
Section 9.11.6 Ethernet RMII
Clocking.
RXD0
Receive bit 0 (PHY to MAC)
PTC4-ALT1
PTC4-ALT1
RXD1
Receive bit 1 (PHY to MAC)
PTC3-ALT1
PTC3-ALT1
RXD2
Receive bit 2 (PHY to MAC)
PTD22-ALT0 (It is shared with Not used in RMII mode
RGPIO, so ensure IOMUX
register has obe=0 for this pin
when used for MII.)
RXD3
Receive bit 3 (PHY to MAC)
PTD23-ALT0 (It is shared with Not used in RMII mode
RGPIO, so ensure IOMUX
register has obe=0 for this pin
when used for MII.)
RX_CRS_DV
Receive data valid (PHY to
PTC2-ALT1
MAC) and CRS in RMII mode.
Receiver Signals
PTC2-ALT1
Table continues on the next page...
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Table 3-17. MII and RMII configuration for MAC0 (continued)
Ethernet signal name
Description
Pin configuration in MII
mode
Pin configuration in RMII
mode
RXER
Receive data error (PHY to
MAC)
PTC5-ALT1
PTC5-ALT1
COL
Collision (PHY to MAC)
PTD20-ALT0 (It is shared with Not used in RMII mode
RGPIO, so ensure IOMUX
register has obe=0 for this pin
when used for MII.)
CRS
Carrier Sense (PHY to MAC)
PTD21-ALT0 (It is shared with Not used in RMII mode.
RGPIO, so ensure IOMUX
register has obe=0 for this pin
when used for MII.)
RXCLK
Receive Clock (PHY to MAC.
Can be internal for RMII as
well.)
PTA21-ALT0 (It is shared with It is muxed with TXCLK. See
RGPIO, so ensure IOMUX
above for details.
register has obe=0 for this pin
when used for MII.)
MDIO
Management I/O data
(Bidirectional)
PTC1-ALT1
PTC1-ALT1
MDC
Management Clock (PHY to
PTC0-ALT1
MAX. Can be internal as well.)
PTC0-ALT1
3.10.1.3 IEEE 1588 Timers
The ethernet module includes a four channel timer module for IEEE 1588 timestamping.
The timer supports input capture (rising, falling, or both edges), output compare (toggle
or pulse with programmable polarity). The timer matches on greater than or equal (the
1588 can skip numbers, so the counter might not ever exactly match the compare value).
The counter is able to operate asynchronously to the ethernet bus by using one of four
clock sources. See Clocking Chapter for more details.
NOTE
For best jitter performance, use MII and not RMII for 1588
applications.
3.10.1.4 Ethernet Operation in Low Power Modes
Low Power modes with Ethernet only Operation
The Ethernet module is not fully operational in any low power modes. However, the
module does support magic packet detection that can generate a wakeup in low power
mode if enabled.
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10/100 Ethernet Subsystem
During low power operation:
• The MAC transmit logic is disabled
• The core FIFO receive/transmit functions are disabled
• The MAC receive logic is kept in normal mode, but it ignores all traffic from the line
except magic packets.
The recieve logic needed for magic packet detection is clocked using the externallysupplied RMII clock. This allows for the wakeup functionality in low power modes.
NOTE
Wakeup from Magic Packet is supported on VFxxx Controller
STOP mode but not supported on LPSTOP1/2/3 mode.
Low Power modes with Dual Ethernet and L2 Switch operation (F-Series only)
In low power mode(STOP mode) , the ENET stops immediately and freezes operation,
register values, state machines, and external pins. During this mode, the ENET clocks are
shut down. Coming out of stop mode returns the ENET to operation from the state prior
to stop mode entry.
NOTE
Practically this would not occur as system would not go in Stop
Mode during this mode. CPU enters or executes a stop
instruction for the system to go in Stop mode (low power mode)
when it sees inactivity or when the system is in idle state for a
long period of time. In case there is no activity on the Ethernet
Bus or no packets to forward to the other port, CPU may enter
this mode. In that case, ENET should have the capability to
wake up from stop mode in case of activity on Ethernet bus for
the system to exit this mode (RMII clock would still be ON to
interrupt the processor on looking at any activity on the RMII
bus).
Low Power modes with Dual Ethernet and L2 Switch Bypassed (F-Series only)
In this mode, the ENET stops immediately and freezes operation, register values, state
machines, and external pins. During this mode, the ENET clocks are shut down. Coming
out of low power mode returns the ENET to operation from the state prior to low power
mode entry.
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NOTE
Any activity on the Ethernet Bus (RMII/MII interface) would
wake up the system and would exit from the low power mode.
Similar to the previous case, system would not enter into this
mode practically in case of an ongoing activity on packet
transmission via RMII interface.
Battery mode of operation
The ENET does not support any Standby Mode of operation or a capability to operate on
battery in case the main supply fails. The ENET would be disabled during this Mode.
3.10.1.5 Ethernet Subsystem Interrupts
The Ethernet has multiple sources of interrupt requests. However, some of these sources
are OR'd together to generate an interrupt request. See the following table:
Table 3-18. Ethernet Subsystem Interrupts
Interrupt request
Interrupt source
ENET interrupt
•
•
•
•
•
•
•
•
•
•
•
•
•
Transmit frame interrupt
Transmit buffer interrupt
Receive frame interrupt
Receive buffer interrupt
Wake-up
Payload receive error
Babbling receive error
Babbling transmit error
Graceful stop complete
MII interrupt – Data transfer done
Ethernet bus error
Late collision
Collision retry limit
IEEE 1588 timer interrupt
• Time stamp available
• 1588 timer interrupt
Ethernet Switch interrupt
•
•
•
•
•
•
•
•
Learning Interrupt
Output Discard for port 0 (OD0)
Output Discard for port 1 (OD1)
Output Discard for port 2 (OD2)
Receive Buffer Interrupt
Receive Frame Interrupt
Transmit Buffer Interrupt
Transmit Frame Interrupt
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3.10.1.6 Ethernet switch register reset values
Some of the Ethernet Switch registers have reset values that are specific to this device.
These registers and reset values are listed below and supersede the default reset values
given in the Ethernet Switch chapter.
Table 3-19. Device-specific reset values
Register
Reset value
ESW_REV
0x0001_0130
3.10.2 USB 2.0 HS/FS/LS Dual Role (Host / Device) Controller
3.10.2.1 USB Configuration and Options
USB Subsystem includes the following:• USB 2.0 HS/FS/LS Dual Role (Host / Device) Controller (x2)
• HS 2.0 integrated PHY (x 2)
3.10.2.2 USB Host initialization and bring up
Table 3-20. Steps to start USB in Device mode
Initialization
• Power ON VFxxx Controller.
• With all the regulators activated, they generate OK. Once, all regulators are up and OK will release functional reset.
• The Core works on 24 Mhz IRC. It initializes the registers, configures generic interrupt controller, and initializes interrupt
handlers.
• Enable 24 MHz XTAL.
• Once, XTAL OK is asserted, enables all PLL (mainly SYS PLL).
• Wait for PLL Lock. (Get status from ANADIG PLL registers.)
• After PLL are Locked, disable Clock gating and disable the bypass for PLL.
• Switch the Clocks to PLL Clock.
• Switch to USB specific configuration for running USB and initialize USB specific features with VFxxx Controller.
Initializaing USB specific features
• Disable the on-chip oscillator (XOSC 24M) powerdown in next powerdown.
• In register CCM Low Power control register (CCM_CLPCR) deassert SBYOS bit. CCM_CLPCR[SBYOS]= 0.
• Enable the USB regulator. Set bit# 0 (ENABLE_LINREG) in register ANADIG Regulator 3P0 definition register
(Anadig_REG_3P0). This regulator works on 5V supply. This needs to be driven from outside the chip.
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Table 3-20. Steps to start USB in Device mode (continued)
• Enable USB PLL and enable usb clocks: In ANADIG register–(Anadig_USB1_PLL_CTRL) and
(Anadig_USB2_PLL_CTRL) enable EN_USB_CLKS and disable BYPASS, that is,
• Anadig_USB1_PLL_CTRL[POWER]=1
• Anadig_USB1_PLL_CTRL[EN_USB_CLKS]=1
• Anadig_USB1_PLL_CTRL[BYPASS]=0
• Start the USB PHY –
• Disable Soft reset of USB PHY – USBPHY_CTRLn[SFTRST]=0
• Enable USB Clocks – USBPHY_CTRLn[CLKGATE]=0
• For running the controller in LS mode, user needs to set bit#15 (ENUTMILEVEL3) and bit#14 (ENUTMILEVEL2)
• In USB PHY Power-Down Register (USBPHY_PWD) clear all the bits and set them to zero.
Anadig[USBPHY_PWD]= 0x0000_0000
• Optionally, one can enable the interrupt of USB controller going to the processor ARM Generic Interrupt Controller
(GIC)-Enable Interrupt ID 107 (USB0) and Enable Interrupt ID 108 (USB1).
• The user can set the WIE bit, if the GIC bit is configured. USBC0_CTRL[WIE]=1
• Refer to “Starting USB Controller in HOST Mode”. Once, controller is set to host mode, user can start to next step.
• Setup Memory for the USB controller to start communication:
• Configure the memory as per “Configure the USB controller to read the descriptor from the connected device and
Set Address” for setting up memory for starting communication.
• User can wait for the device to detect, configure and connect for starting communication over USB. Refer to Detection
for port status change, resetting the USB and speed of connected device.
• Once the setup is complete--device connected and configured. One can start communication over usb. Refer to
Starting the communication over the USB from Configured Connected Device.
Starting USB Controller in Host Mode
• By default the USB on VFxxx Controller is defaulted to device controller. For initializing them as a Host user has to do
following steps:
• In USB_OTG1_USBCMD register, set the RST bit
• Keeping polling for de-assertion of this bit.
• In USBMODE register configure CM bit, that is, bit 1 and bit 0
• Keep polling and writing back 2’b11 on CM if bit are not set to 11.
• Once these bits are set to 11, controller is configured to function like a host.
• Refer to “Setting Up device controller” for setup device interrupt and periodic index .
• If Port Power is required then refer to “Enable the port power in device Controller”
Enable the port power in Host controller
• In register Host Controller Structural Parameters (USBx_HCSPARAMS), read if implementation allows controlling the
port power. If it reads back to ‘1’, indicates the port power can be controlled. In that case, we can configure bit number
12 of Port Status & Control (USBx_PORTSC1) register to enable port power.
Setting Up Host controller
• Setting Up interrupt threshold–In USB Command Register (USBx_USBCMD), set ITC bit to zero. Else set ITC bit as
per system needs.
• In USB Frame Index (USBx_FRINDEX), write 1 to the to FRINDEX. This register is used by the host controller to index
the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Moreover, this register
cannot be written unless the Host Controller is in the 'Halted' state as indicated by the HCHalted bit inside USB Status
Register (USBx_USBSTS).
Detection for port status change, resetting the USB and speed of connected device
• Everything is set, now user can wait for connection of any external device to the host controller. To sense the device
attached, user can poll or configure an interrupt waiting for USB_OTG1_USBSTS to check the change in the port
status.
• Once bit2 of PCI bit is found asserted; dessert this bit by writing back 1 to the same location. This is W1C bit.
• Poll for PORTSC0 register, bit #1, Current Status Change (CSC). If set to ‘1’, set port change is detected. Now
clear this bit by writing back ‘1’ into the same location.
• Check the connect status—Bit#0 of register OTG_PORTSC0. If found asserted port is connected. Else
disconnect or under enumeration.
• Check if UTMI clocks are OK in USBNC registers – USBCx_PHY – bit# 31.
• Reset the USB port
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Table 3-20. Steps to start USB in Device mode (continued)
• IN USB Command Register (USBx_USBCMD), set RS bit#0. To start the controller.
• Check bit#12 in USBSTS register – HCH. If set to 1, controller is in halted state.
• Set bit#8 of PORTSC0 register for starting the reset sequence. Once this bit is written with 1, controller will start
reset sequence (CHRIP) for that port.
• Wait for USB_PORTSC[PR] bit to clear.
• Now check for bit#2 of PORTSC register to check if the device is not disconnected due to reset sequence.
If not, move to next step, else restart from “Detection for port change”.
• Now check bit#27:26 of PORTSC register to check the port speed. If PSPD is found to be:
• 00 – Full speed
• 01 – Low speed
• 10 – High speed
If found not connected, restart from “Detection for port change”.
• Configure the host controller to create channel between software running at processor and the device connected.
• The populated data structure for communication between the software and the device is kept in the memory. This
structure needs to be kept at 64 byte aligned boundary address. The base address of this data structure needs to
be loaded inside the controller to operate.
• This address needs to be loaded at USB_OTG1_ASYNCLISTADDR.
Configure the USB controller to read the descriptor from the connected device and Set Address
• Refer the EHCI Documentation for detailed configuration and running the USB. The method shown here is one of the
method for Writing Software for running the USB on VFxxx Controller.
• USB memory need to be initialized to get configured, check features and set address for starting communication over
USB.
• Populate the Asynchronous Queue in Memory.
• Get device feature: Reading control descriptor  Communicate to EP0, ADD0, read Descriptor.
• Assign Address: If readback features are supported, and need not to suspend the USB port then assign
Address.
• Once address assignment is done, populate to new QTHead where further communication to happen with
new address.
• Read feature descriptor allocated to other endpoint of the connected device.
• Once, all the device feature are read, firmware can communicate with device accordingly to access and
control different feature by populating qTD for the feature.
• The user needs to populate “Periodic framelist ” for isochronous and interrupt transfers and “asynchronous list” for
control and bulk transfers.
• For running the controller in FS mode, user needs to set endpoint speed to FS in endpoint control populated in
the memory. For LS mode, user need to set the endpoint to LS in endpoint control populated in the memory.
• User has to dump the periodic framelist baseaddress into Frame List Base Address
(USBx_PERIODICLISTBASE) register .
• For Async transfer, user has to dump async framelist base address into Asynch. Address
(USBx_ASYNCLISTADDR)
• Please refer section " Host Data Structures” for more information on Periodic and Asynchronous Framelist.
• Now, controller waits for any device to connect. Once there is any port status change, controller will generate interrupt
to the processor.
• In register USBSTS, poll for USB Status, bit#0 for completion of command list given through Asynchronous queue.
Starting the communication over the USB from Configured Connected Device
• Refer the EHCI documentation for detailed configuration and running the USB. The method shown here is one of the
method for Writing Software for running the USB on VFxxx Controller.
• Read the “Host Data Structures” VFxxx Controller RM.
• User needs to set following:
• Programming the endpoint capabilities/characteristics in the queue head with the capabilities of the endpoint and
device to communicate. User can program following things in the register: Endpoint number, Endpoint speed,
Endpoint max packet length, and device address .
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Table 3-20. Steps to start USB in Device mode
• Program the page offset in the queue head. Each page carries a packet to be transmitted. User can actually
check the status of the transmission by looking into “Current qTD pointer”, “Next qTD pointer”, and “Alternate qTD
pointer”
• In register USBSTS, poll for USB Status, bit#0 for completion of command list given through Asynchronous
queue.
• After populating the entire structure into the memory, user has to set bit#7 in qTD token status. This bit is set by the
software to enable the execution of transaction by the Host controller. Keep polling the remaining bits [6:0] for different
communication issues.
3.10.2.3 SOF for USB Audio
This is mainly applicable when Dual Role (Host / Device) Controller is working in
Device Mode. For some of the USB Audio use-cases, require some sort of audio clock
recovery capability. One way to do it is to use the Start of Frame (SOF) signal which is
generated at the start of a microframe in the USB 2.0 HS. This is a signal with a rate of
125 microseconds. When operating in Full Speed mode, the SOF signal has a rate of 1
ms.
Pulse that asserts for 64 system clock cycles when the SOF token is detected on the USB
bus when the USB controller is in device mode.
In order to properly support USB Audio Isochronous Asynchronous mode of operation, it
is necessary to measure how many audio sample clock ticks occur between two
consecutive occurrences of the SOF signal. This measurement is used to provide
feedback to the USB audio source in order to speed up or slow down the audio sample
delivery over the USB bus.
This is the method of estimating the ratio between the USB Host clock (SOF
occurrences) and the local audio clock.
Figure below shows the USB SOF connectivity with FlexTimer to enable this scheme.
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Figure 3-14. USB SOF connectivity with Flextimer
1. The two SOF signals (one from each USB port) must be brought to two timers
channels of one FlexTimer. This flexibility is provided in FTM2 and FTM3 as shown
in figure.
2. At least one of the SOF signals should be connected to one channel of a second
FlexTimer. This will allow measuring of two sets of audio clock/SOF signals. To
accomodate this USB0 SOF is connected to all Flextimers.
The audio master clock should also be provided as one of the clock options to FlexTimer.
3.10.2.4 OverCurrent and VBUS Connection
The figure below provides OverCurrent and VBUS Connection.
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Chapter 3 Chip Configuration
USB0_oc
0
1
IOMUX
PAD[7]
IOMUX
PAD[6]
SRC_MISC3[8]
SRC_MISC3[9]
USB_WRAPPER
USB0
USB0_VBUS_EN
usb_interrupt
(Edge detect)
(Status)
USB_CTRL[24]
USB1
Other
interrupt
USB1_VBUS_EN
IOMUX
PAD[14]
usb_interrupt
0
1
IOMUX
PAD[15]
SRC_MISC3[10]
SRC_MISC3[11]
VBUS_EN is routed to PAD as well as an interrupt from USB. Its status is in USB_CTRL[24]
and can be masked using USB_CTRL[25].
Figure 3-15. OverCurrent and VBUS Connection
3.10.3 Secure Digital Host Controller (SDHC)
3.10.3.1 SD bus pullup/pulldown constraints
The SD standard requires the SD bus signals (except the SD clock) to be pulled up during
data transfers. The SDHC also provides a feature of detecting card insertion/removal, by
detecting voltage level changes on DAT[3] of the SD bus. To support this DAT[3] must
be pulled down. To avoid a situation where the SDHC detects voltage changes due to
normal data transfers on the SD bus as card insertion/removal, the interrupt relating to
this event must be disabled after the card has been inserted and detected. It can be reenabled after the card is removed.
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Secure Digital Host Controller (SDHC)
3.10.3.2 SDHC Wakeup
The SDHC controller is taken out of low power mode by some of its interrupts, known as
wakeup interrupts. The SDHC can generate these interrupts even when clocks are not
enabled. The three interrupts which can be used as wakeup events are:
1. Card Removal Interrupt
2. Card Insertion Interrupt
3. Interrupt from SDIO card
To make the interrupt a wakeup event, when all the clocks to the SDHC are disabled or
when the whole system is in low power mode, the corresponding wakeup enabled bit
needs to be set.
3.10.3.2.1
Setting Wake Up Events
For the SDHC to respond to a wakeup event, the software must set the respective wakeup
enable bit before the CPU enters sleep mode. Before the software disables the host clock,
it should ensure that all of the following conditions have been met:
•
•
•
•
No Read or Write Transfer is active
Data and Command lines are not active
No interrupts are pending
Internal data buffer is empty
3.10.3.3 SDHC Software Guidelines
SDHC interrupt does not set under the following circumstances:
1. SDHC configured to generate wakeup on card interrupt. PLL3 is selected as SDHC's
baud rate clock.
2. ESDHC clocks are disabled by SDHC_SYSCTL register. For details about the
register, refer to the respective chapter in this document.
3. PLLs are powered down by software before entering into STOP mode.
4. ESDHC wakeup occurs because of card interrupt.
5. Bus clock restarts but PLL does not start as software directly jumps to SDHC ISR
instead of PLL enabling routine.
6. CPU reads SDHC_IRQSTAT register, but finds no bit set. The bit requires baud rate
clock to get set, which needs PLL3 to get powered up.
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Chapter 3 Chip Configuration
3.10.4 UART
3.10.4.1 UART configuration information
This device contains up to six UART modules. This section describes how each module
is configured on this device.
1. Standard features of all UARTs:
• RS-485 support
• Hardware flow control (RTS/CTS)
• 9-bit UART to support address mark with parity
• MSB/LSB configuration on data
2. All UARTs are clocked on the IPS bus clock. The maximum baud rate is 1/16 of
related source clock frequency.
3. IrDA is available on all UARTs
4. UART0 and UART1 contains the standard features plus ISO7816
5. UART0 and UART1 contains 16-entry transmit and 16-entry receive FIFOs
6. All other UARTs contain a 8-entry transmit and 8-entry receive FIFOs
7. LIN 2.0 supported on all UARTs.
3.10.4.2 UART wakeup
The UART can be configured to generate an interrupt/wakeup on the first active edge that
it receives.
3.10.4.3 UART interrupts
The UART has multiple sources of interrupt requests. However, some of these sources
are OR'd together to generate a single interrupt request. See below for the mapping of the
individual interrupt sources to the interrupt request:
The status interrupt combines the following interrupt sources:
Source
UART 0
UART 1
UART 2
UART 3
UART 4
UART 5
Transmit data
empty
x
x
x
x
x
x
Transmit
complete
x
x
x
x
x
x
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FlexCAN
Source
UART 0
UART 1
UART 2
UART 3
UART 4
UART 5
Idle line
x
x
x
x
x
x
Receive data
full
x
x
x
x
x
x
LIN break
detect
x
x
x
x
x
x
RxD pin active
edge
x
x
x
x
x
x
Initial character
detect
x
x
—
—
—
—
The error interrupt combines the following interrupt sources:
Source
UART 0
UART 1
UART 2
UART 3
UART 4
UART 5
Receiver
overrun
x
x
x
x
x
x
Noise flag
x
x
x
x
x
x
Framing error
x
x
x
x
x
x
Parity error
x
x
x
x
x
x
Transmitter
buffer overflow
x
x
x
x
x
x
Receiver buffer
underflow
x
x
x
x
x
x
Transmit
threshold
x
x
—
—
—
—
Receiver
threshold
x
x
—
—
—
—
Wait timer
x
x
—
—
—
—
Character wait
timer
x
x
—
—
—
—
Block wait timer x
x
—
—
—
—
Guard time
violation
x
—
—
—
—
x
3.10.5 FlexCAN
3.10.5.1 Instantiation
There are two instances of the FlexCAN module on this device: FlexCAN0 and
FlexCAN1.
Each FlexCAN is implemented with 64 message buffers each.
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Chapter 3 Chip Configuration
3.10.6 MediaLB Device Module (MLB50)
3.10.6.1 Instantiation
There is one instance of the MLB50 module on R-Series devices.
The MLB50 module is only available on the BGA version of this device.
The module interfaces to Intelligent Network Interface Controller (INIC50) via 3 external
signals:
• MLBCLK(I)
• MLBDAT(I/O)
• MLBSIG(I/O)
MLB50 supports 3.3 V I/O
The MLB interface operates at up to 50 MB/s. Thus, the minimum continuous bandwidth
to be supported over the NIC to the system memory is 50 MB/s. Typical data bandwidths
are much less, however the maximum continuous bandwidth must be provided to
guarantee meeting the full specification.
The MediaLB module is to be interfaced to this device via the peripheral bus and the high
speed NIC. The peripheral bus is used to interface to the MediaLB control/status registers
via the peripheral bus interface (PBI). The PBI is a slave on the peripheral bus. The MLB
module registers are memory mapped by the AIPS(0). Data is transferred between the
MLB module and the system memory via the high speed NIC. The interface to the NIC is
AHB.
3.10.7 SPI
3.10.7.1 SPI Instantiation
This device contains up to 4 SPI modules.
Table 3-21. SPI Instances
SPI
176 LQFP
364 BGA
No. of SPI
3
4
SPI0 CTAR
4
4
SPI1 CTAR
2
2
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SPI
Table 3-21. SPI Instances (continued)
SPI
176 LQFP
364 BGA
SPI2 CTAR
2
2
SPI3 CTAR
N/A
2
SPI0 Chip Selects
6
6
SPI1 Chip Selects
4
4
SPI2 Chip Selects
2
2
SPI3 Chip Selects
N/A
2
TX FIFO SPI0
4
4
RX FIFO SPI0
4
4
TX FIFO SPI1
4
4
RX FIFO SPI1
4
4
TX FIFO SPI2
4
4
RX FIFO SPI2
4
4
TX FIFO SPI3
N/A
4
RX FIFO SPI3
N/A
4
NOTE
The SPI's de-serial interface (DSI) and timed serial bus (TSB)
features are not supported on any SPI instance
The SPI module is clocked by the internal bus clock. The module has an internal divider,
with a minimum divide of two. Thus, the SPI can run at a maximum frequency of bus
clock/2.
3.10.7.2 Number of PCS
Depending on the number of DSPI instances, the number of PCS varies from 2 to 6.
For :
• DSPI0 - 6
• DSPI1 - 4
• DSPI2 - 2
• DSPI3 - 2
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3.10.8 Inter-Integrated Circuit (I2C)
3.10.8.1 Instantiation Information
This device contains up to four I2C modules, I2C0, I2C1, I2C2, and I2C3.
3.11 Analog
3.11.1 12-bit Analog to Digital Converter (ADC)
3.11.1.1 ADC Instantiation
This device contains a total of 16 ADC pin inputs. The ADC signals are distributed
around the chip in order to optimize the flexibility in layout and feature trade off for the
user.
The ADC conversion channel is selected by setting the Pin Mux control bit.
The 364 BGA offers dedicated ADC channels on pads apart from ADC channels muxed
with GPIO.
Table 3-22. ADC instantiation
Features
176 LQFP
364 BGA
No of ADC modules
2
2
No of Differential Channels
Not Supported
Not Supported
No of Single Ended Channels(muxed
with GPIO)
6+6
8+8
No of dedicated single Ended Channels
None
2+2
VREFH/VREFL
Yes
Yes
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12-bit Analog to Digital Converter (ADC)
3.11.1.2 Voltage reference selection (REFSEL settings)
The bit field definition for ADCx_CFG[REFSEL] is as follows for this chip:
Table 3-23. ADCx_CFG[REFSEL]
settings
Bit value
Definition
00
Selects VREFH/VREFL as reference voltage. VREFH/VREFL are connected to VREFH_ADC
and VREFL_ADC pads.
01
Selects VALTH/VALTL as reference voltage. VALTH/VALTL are connected to ADC reference
voltage (1.2V) from Voltage Regulator.
10
Selects VBGH/VBGL as reference voltage. VBGH/VBGL are connected to ADC reference
voltage (1.2V) from Voltage Regulator. (Same as 01 above).
11
Reserved
3.11.1.3 DMA Support on ADC
Applications may require continuous sampling of ADC (4K samples/sec at minimum)
that may have considerable load on CPU. Though using PDB to trigger ADC may reduce
some CPU load, ADC need to support DMA for higher performance where ADC is
sampled at very high rate or cases were PDB is bypassed. ADC should trigger on-chip
DMA (via DMA req) on conversion completion.
3.11.1.4 ADC Channel Assignments
Table 3-24. ADC Channel Assignments
ADC Channel
ADC0
ADC1
Type
0
PAD[8]
PAD[6]
External
1
PAD[9]
PAD[7]
External
2
PAD[22]
PAD[24]
External
3
PAD[23]
PAD[25]
External
4
PAD[26]
PAD[27]
External
5
PAD[103]
PAD[104]
External
6
PAD[59]
PAD[61]
External
7
PAD[60]
PAD[62]
External
8
Dedicated PAD - ADC0SE8
Dedicated PAD - ADC1SE8
External
9
Dedicated PAD - ADC0SE9
Dedicated PAD - ADC1SE9
External
10
DAC0 - external output
DAC1 - external output
Internal
11
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
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Table 3-24. ADC Channel Assignments (continued)
ADC Channel
ADC0
ADC1
Type
12
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
13
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
14
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
15
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
16
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
17
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
18
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
19
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
20
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
21
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
22
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
23
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
24
VSS33_IO_ADC_DAC
VSS33_IO_ADC_DAC
NA
25
VREF from dedicated pad or VREF from dedicated pad or
PMU (select one based on
PMU (select one based on
register programming of ADC) register programming of ADC)
Internal
26
Temperature Sensor
Temperature Sensor
Internal
27
VREF from PMU
VREF from PMU
Internal
28
HI-Z
HI-Z
NA
29
HI-Z
HI-Z
NA
30
HI-Z
HI-Z
NA
31
HI-Z
HI-Z
NA
3.11.1.5 ADC interconnections
Table 3-25. ADC interconnections
Trigger Module
Trigger
Trigger
ADC
ADC0
ADC0
PDB
Trig0
Trig1
LPTIMER
LPTIMER-Trig
LPTIMER-Trig
3.11.1.6 ADC Calibration
The device fuse map (Bank7-Word5 ) has been assigned to store the 16-bit calibrated
value for ADC0 and ADC1. This calibrated value is derived at room temperature, with
nominal voltage and with max averaging. This calibrated value can be copied from Fuses
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12-Bit Digital-to-Analog Converter (DAC)
to ADC register to avoid running calibration sequence at reset. Alternatively, the
calibration sequence can be run after each and every reset. Refer to Calibration Function
for details.
3.11.1.7 Temperature Sensor
The on-chip temperature sensor is connected to Channel 26 of both ADC0 or ADC1 so
either ADC can be used to read the sensor data.
The current temperature is obtained by the simplified formula: Current temperature = 25
+ (tempsensor_count – 866) * -0.437870
A more accurate temperature is obtained by using the calibration data that is stored in the
e-fuses. Fuse map Bank1 Word6 holds calibration data for the temperature sensor. This
calibration data is obtained during the device's test procedure before it leaves the factory.
See the TEMPSENSE register in OCOTP for details.
3.11.2 12-Bit Digital-to-Analog Converter (DAC)
3.11.2.1 12-bit DAC Instantiation
Table 3-26. 12-bit DAC Instantiation
176 LQFP
Number of 12-bit DACs
2
364 BGA
2
3.11.2.2 12-bit DAC External Reference
For this device, external voltage supplied to VREFH_ADC pin is the only reference
voltage for DAC reference. You need to set up DACx_STATCTRL[DACRFS]=1 to
select the valid VREFH_ADC reference. When DACx_STATCTRL[DACRFS]=0, the
DAC reference is connected to an internal ground node and is not a valid voltage
reference. Be aware that if the DAC and ADC use the VREFH_ADC reference
simultaneously, some degradation of ADC accuracy is to be expected due to DAC
switching.
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3.11.2.3 DMA support on DAC
Applications may require continuous sampling of DAC (4K samples/sec at minimum)
that may have considerable load on CPU. The DAC supports DMA for higher
performance where the DAC is sampled at a very high rate. To trigger a DMA request,
the DAC uses the watermark and buffer bottom and up flags. The DAC must trigger onchip DMA (via DMA request) on conversion completion.
3.11.2.4 DAC interconnections
Table 3-27. DAC interconnections
DAC trigger from PDB
Connection
DAC0
DAC refresh trigger 0
DAC1
DAC refresh trigger 1
3.12 Display/Video interfaces
3.12.1 Display Control Unit
3.12.1.1 Instantiation
The DCU4 modules connect to the NIC301 as bus masters.
Each DCU4 interface is a 64-bit AXI
Each DCU features an APB interface for control.
HSYNC/VSYNC, DE and Pixel Clock connect to I/O as well as to inputs of a TCON
module for generation of additional timing signals
3.12.2 Timing Controller (TCON)
3.12.2.1 Instantiation
Number of TCON instances: 2 (one for each DCU)
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RLE Decoder (RLE)
Number of timing channels: 12
3.12.3 RLE Decoder (RLE)
3.12.3.1 Instantiation
Number of RLE_DEC instances: 1
Module is disabled by default.
3.12.4 Segmented LCD Controller
3.12.4.1 Instantiation
There is one instance of the LCD module on this device that is connected to the AIPS
peripheral bridge.
3.12.4.2 Number of Front and Back Planes
Table 3-28. Number of Front and Back Planes
Parameter
Number of front
Value
planes1
36 or 38 or 40
Number of back planes2
4 or 6 or 8
1. Software-configurable. Default assignment is 40 FP and 4 BP. BP0-3 are located on pads LCD40-43. FP0-39 are located
at pads LCD0-39.
2. Software-configurable. See LCD Driver Backplane Remapping for different configurations.
3.12.4.3 LCD clock selection
The LCD module can be optionally clocked by the system bus clock, the internal 128
KHz IRC or the external 32 KHz crystal clock.
Mode
Description
Normal Run Mode
In normal run modes the LCD is clocked by the system clock.
Low Power Mode
In low power modes of operation to conserve power the LCD
module is optionally clocked by the internal 128 KHz IRC or
the 32 KHz external crystal oscillator. These two clock
sources are available in the low power domains.
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Chapter 3 Chip Configuration
The following table shows the clocks selected by the LCDCR[LCDOCS] bit.
Table 3-29. LCD Clock Selection Based on
LCDCR[LCDOCS]
Value of LCDCR[LCDOCS]
Clock selected
1
32 kHz OSC
0
128 kHz OSC
3.12.4.4 Settings during STANDBY mode
To keep the LCD driver shut down in STANDBY mode, the following settings are
needed:
• LCDCR[LCDRST] = 0
• LCDCR[LCDRCS] = 0
To keep the LCD driver on (functioning) in STANDBY mode, the following settings are
needed:
• LCDCR[LCDRST] = 1
• LCDCR[LCDRCS] = 1
• LCDCR[LCDOCS] = 0 or 1
• If this field is 0, the LCD driver will operate from SIRC.
• If this field is 1, the LCD driver will operate from SXOSC.
3.12.4.5 Segment LCD configuration
In this device the LCD module will be part of the Low Power Domain to enable LCD
display content to be maintained. For the display to be updated the MPU must wake up
from Low Power mode.
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Video Interface Unit(VIU)
NOTE
The device does not support 5V I/O, therefore the LCD module
will interface only to 3.6V glass.
Table 3-30. Number of Front and Back Planes
Parameter
Value
Number of Front Planes
40 or 38 or 36
Number of Back Planes
4 or 6 or 8
NOTE
There are only ten LCDRAM registers (LCDRAM0LCDRAM9) implemented on this device. The other registers
(LCDRAM10-LCDRAM15) that are described in the LCD
chapter are not available on this device.
3.12.5 Video Interface Unit(VIU)
3.12.5.1 Instantiation
Number of VIU3 instances: 1
3.12.6 Video ADC(VADC)
3.12.6.1 Instantiation
This device features one instance of the VideoADC
The VideoADC accepts up to 4 single-ended analog inputs.
The VideoADC digital output interfaces directly to the VIU module as shown below.
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Chapter 3 Chip Configuration
NOTE
This mux is controlled by the MISC2 register in the SRC
module.
3.13 Audio Subsystem
3.13.1 Audio Subsystem Modules
3.13.1.1 Audio Subsystem Overview
The modules that belong to the audio subsystem are the SAI0, SAI1, SAI2, SAI3, ESAI,
ESAI_BIFIFO, SPDIF and ASRC. In addition, the IOMUX must be appropriately
configured to get signals in and out of the chip.
SAI0-3 are synchronous audio interfaces used to transfer audio data. SAI0-3 are on the
peripheral bus.
The ESAI (Enhanced Serial Audio Interface) provides a full-duplex serial port for serial
communication with a variety of serial devices, including industry-standard codecs,
SPDIF transceivers, and other processors. The ESAI consists of independent transmitter
and receiver sections, each section with its own clock generator. The ESAI is connected
to the IOMUX and to the ESAI_BIFIFO module.
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Audio Subsystem Modules
The ESAI_BIFIFO (ESAI Bus Interface and FIFO) is the interface between the ESAI
module and the shared peripheral bus. It contains the FIFOs used to buffer data to/from
the ESAI, as well as providing the data word alignment and padding necessary to match
the 24-bit data bus of the ESAI to the 32-bit data bus of the shared peripheral bus.
The SPDIF (Sony/Philips Digital Interface) audio module is a stereo transceiver that
allows the processor to receive and transmit digital audio over it. The SPDIF receiver
section includes a frequency measurement block that allows the precise measurement of
an incoming sampling frequency. A recovered clock is provided by the SPDIF receiver
section and may be used to drive both internal and external components in the system.
The SPDIF is connected to the shared peripheral bus.
The ASRC is a hardware audio sample rate converter supporting up to 10 channels split
into 3 sampling rate pairs.
3.13.1.2 Synchronous Audio Interface (SAI)
The Synchronous Audio Interface (SAI) implements supports full-duplex serial interfaces
with frame synchronization such as I2S, AC97, and codec/DSP interfaces.
This device implements four SAI modules. SAI0-2 are required for connected radio
applications with Radio Tuner devices. SAI3 is added to support future expansion.
The following table shows the configuration of the SAIs:
Table 3-31. SAI Configurations
SAI Instance
Tx Data Lines
Rx Data Lines
Tx FIFO Depth
Rx FIFO Depth
SAI0
1
1
32
32
SAI1
1
1
32
32
SAI2
1
1
32
32
SAI3
1
1
64
64
3.13.1.2.1
SAI3 register details
The dedicated SAI chapter documents the identically instantiated SAI0, SAI1, and SAI2.
The following table summarizes SAI3 register details that differ from the other module
instances.
Table 3-32. SAI3 register differences from other SAI instances
Instance
SAI3
TCR1[TFW] and RCR1[RFW]
Each field is 6 bits wide
TFR[WFP], TFR[RFP], RFR[WFP], and RFR[RFP]
Each field is 7 bits wide
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3.13.1.2.2
Simultaneous SAI DMA requests
If all four instances of the SAI module issue DMA requests simultaneously, DMA must
be configured in round robin arbitration mode.
3.13.1.2.3
SAI transmitter and receiver options for MCLK selection
For an internally generated bit clock of the transmitter or receiver, all SAI instances have
the same options for selecting an audio master clock (MCLK) source. TCR2[MSEL] and
RCR2[MSEL] independently select the MCLK source for the transmitter and receiver,
respectively. The following table shows the MSEL settings and the corresponding
available MCLK sources on this device.
Table 3-33. SAIn transmitter and receiver options for MCLK selection
TCR2[MSEL] or RCR2[MSEL]
MCLK source for internally generated bit clock of
transmitter or receiver
00
Bus Clock
01
Clock selected by CCM_CSCMR1[SAIn_CLK_SEL]
10
Not supported
11
Not supported
3.13.1.2.4 SAI in Stop mode
MCU wakeup from an SAI module is not supported because the SAI clock is gated in
Stop mode. Before the MCU enters Stop mode, you must disable operation of the SAI
transmitter and receiver in Stop mode. More specifically:
1. In the SAI, program TCSR[STOPE] and RCSR[STOPE] to 0.
2. Execute the MCU’s entry to Stop mode.
3.13.1.3 Enhanced Serial Audio Interface (ESAI)
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial
communication with a variety of serial devices, including industry-standard codecs,
SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each section with its
own clock generator. All serial transfers are synchronized to a clock. Additional
synchronization signals are used to delineate the word frames. The normal mode of
operation is used to transfer data at a periodic rate, one word per period. The network
mode is also intended for periodic transfers; however, it supports up to 32 words (time
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Miscellaneous
slots) per period. This mode can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for non-periodic transfers of data
and to transfer data serially at high speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection to external devices. The ESAI is
internally connected to the ESAI_BIFIFO, and does not connect directly to the shared
peripheral bus. The ESAI interface is designed for a 24-bit data bus, while the shared
peripheral data bus is 32-bit wide. Also, the ESAI data paths are only double buffered,
not allowing efficient DMA service in the applications processor environment. The
ESAI_BIFIFO allows increasing the data buffering and data width matching to the shared
peripheral bus.
3.13.1.4 ESAI Bus Interface and FIFO (ESAI_BIFIFO)
The ESAI_BIFIFO (ESAI Bus Interface and FIFO) is the interface between the ESAI
module and the shared peripheral bus. It contains the FIFOs used to buffer data to/from
the ESAI, as well as providing the data word alignment and padding necessary to match
the 24-bit data bus of the ESAI to the 32-bit data bus of the shared peripheral bus..
There are two independent 128-word FIFOs, one servicing the ESAI transmit section,
shared by the 6 ESAI transmitters, while the other 128-word FIFO services the ESAI
receive section, shared by the 4 ESAI receivers. Each FIFO has a programmable
watermark level where it can trigger a DMA service request.
The ESAI 24-bit data words are aligned and formatted according to the Transmit Word
Alignment and Receive Word Alignment controls.
3.14 Miscellaneous
3.14.1 GPIO
3.14.1.1 GPIO Mapping
Table 3-34. RGPIO versus Pins
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[0]
PORT0[0]
PTA6
IOMUXC_PTA6
40048000
RGPIO[1]
PORT0[1]
PTA8
IOMUXC_PTA8
40048004
RGPIO[2]
PORT0[2]
PTA9
IOMUXC_PTA9
40048008
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-34. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[3]
PORT0[3]
PTA10
IOMUXC_PTA10
4004800C
RGPIO[4]
PORT0[4]
PTA11
IOMUXC_PTA11
40048010
RGPIO[5]
PORT0[5]
PTA12
IOMUXC_PTA12
40048014
RGPIO[6]
PORT0[6]
PTA16
IOMUXC_PTA16
40048018
RGPIO[7]
PORT0[7]
PTA17
IOMUXC_PTA17
4004801C
RGPIO[8]
PORT0[8]
PTA18
IOMUXC_PTA18
40048020
RGPIO[9]
PORT0[9]
PTA19
IOMUXC_PTA19
40048024
RGPIO[10]
PORT0[10]
PTA20
IOMUXC_PTA20
40048028
RGPIO[11]
PORT0[11]
PTA21
IOMUXC_PTA21
4004802C
RGPIO[12]
PORT0[12]
PTA22
IOMUXC_PTA22
40048030
RGPIO[13]
PORT0[13]
PTA23
IOMUXC_PTA23
40048034
RGPIO[14]
PORT0[14]
PTA24
IOMUXC_PTA24
40048038
RGPIO[15]
PORT0[15]
PTA25
IOMUXC_PTA25
4004803C
RGPIO[16]
PORT0[16]
PTA26
IOMUXC_PTA26
40048040
RGPIO[17]
PORT0[17]
PTA27
IOMUXC_PTA27
40048044
RGPIO[18]
PORT0[18]
PTA28
IOMUXC_PTA28
40048048
RGPIO[19]
PORT0[19]
PTA29
IOMUXC_PTA29
4004804C
RGPIO[20]
PORT0[20]
PTA30
IOMUXC_PTA30
40048050
RGPIO[21]
PORT0[21]
PTA31
IOMUXC_PTA31
40048054
RGPIO[22]
PORT0[22]
PTB0
IOMUXC_PTB0
40048058
RGPIO[23]
PORT0[23]
PTB1
IOMUXC_PTB1
4004805C
RGPIO[24]
PORT0[24]
PTB2
IOMUXC_PTB2
40048060
RGPIO[25]
PORT0[25]
PTB3
IOMUXC_PTB3
40048064
RGPIO[26]
PORT0[26]
PTB4
IOMUXC_PTB4
40048068
RGPIO[27]
PORT0[27]
PTB5
IOMUXC_PTB5
4004806C
RGPIO[28]
PORT0[28]
PTB6
IOMUXC_PTB6
40048070
RGPIO[29]
PORT0[29]
PTB7
IOMUXC_PTB7
40048074
RGPIO[30]
PORT0[30]
PTB8
IOMUXC_PTB8
40048078
RGPIO[31]
PORT0[31]
PTB9
IOMUXC_PTB9
4004807C
RGPIO[32]
PORT1[0]
PTB10
IOMUXC_PTB10
40048080
RGPIO[33]
PORT1[1]
PTB11
IOMUXC_PTB11
40048084
RGPIO[34]
PORT1[2]
PTB12
IOMUXC_PTB12
40048088
RGPIO[35]
PORT1[3]
PTB13
IOMUXC_PTB13
4004808C
RGPIO[36]
PORT1[4]
PTB14
IOMUXC_PTB14
40048090
RGPIO[37]
PORT1[5]
PTB15
IOMUXC_PTB15
40048094
RGPIO[38]
PORT1[6]
PTB16
IOMUXC_PTB16
40048098
RGPIO[39]
PORT1[7]
PTB17
IOMUXC_PTB17
4004809C
RGPIO[40]
PORT1[8]
PTB18
IOMUXC_PTB18
400480A0
RGPIO[41]
PORT1[9]
PTB19
IOMUXC_PTB19
400480A4
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GPIO
Table 3-34. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[42]
PORT1[10]
PTB20
IOMUXC_PTB20
400480A8
RGPIO[43]
PORT1[11]
PTB21
IOMUXC_PTB21
400480AC
RGPIO[44]
PORT1[12]
PTB22
IOMUXC_PTB22
400480B0
RGPIO[45]
PORT1[13]
PTC0
IOMUXC_PTC0
400480B4
RGPIO[46]
PORT1[14]
PTC1
IOMUXC_PTC1
400480B8
RGPIO[47]
PORT1[15]
PTC2
IOMUXC_PTC2
400480BC
RGPIO[48]
PORT1[16]
PTC3
IOMUXC_PTC3
400480C0
RGPIO[49]
PORT1[17]
PTC4
IOMUXC_PTC4
400480C4
RGPIO[50]
PORT1[18]
PTC5
IOMUXC_PTC5
400480C8
RGPIO[51]
PORT1[19]
PTC6
IOMUXC_PTC6
400480CC
RGPIO[52]
PORT1[20]
PTC7
IOMUXC_PTC7
400480D0
RGPIO[53]
PORT1[21]
PTC8
IOMUXC_PTC8
400480D4
RGPIO[54]
PORT1[22]
PTC9
IOMUXC_PTC9
400480D8
RGPIO[55]
PORT1[23]
PTC10
IOMUXC_PTC10
400480DC
RGPIO[56]
PORT1[24]
PTC11
IOMUXC_PTC11
400480E0
RGPIO[57]
PORT1[25]
PTC12
IOMUXC_PTC12
400480E4
RGPIO[58]
PORT1[26]
PTC13
IOMUXC_PTC13
400480E8
RGPIO[59]
PORT1[27]
PTC14
IOMUXC_PTC14
400480EC
RGPIO[60]
PORT1[28]
PTC15
IOMUXC_PTC15
400480F0
RGPIO[61]
PORT1[29]
PTC16
IOMUXC_PTC16
400480F4
RGPIO[62]
PORT1[30]
PTC17
IOMUXC_PTC17
400480F8
RGPIO[63]
PORT1[31]
PTD31
IOMUXC_PTD31
400480FC
RGPIO[64]
PORT2[0]
PTD30
IOMUXC_PTD30
40048100
RGPIO[65]
PORT2[1]
PTD29
IOMUXC_PTD29
40048104
RGPIO[66]
PORT2[2]
PTD28
IOMUXC_PTD28
40048108
RGPIO[67]
PORT2[3]
PTD27
IOMUXC_PTD27
4004810C
RGPIO[68]
PORT2[4]
PTD26
IOMUXC_PTD26
40048110
RGPIO[69]
PORT2[5]
PTD25
IOMUXC_PTD25
40048114
RGPIO[70]
PORT2[6]
PTD24
IOMUXC_PTD24
40048118
RGPIO[71]
PORT2[7]
PTD23
IOMUXC_PTD23
4004811C
RGPIO[72]
PORT2[8]
PTD22
IOMUXC_PTD22
40048120
RGPIO[73]
PORT2[9]
PTD21
IOMUXC_PTD21
40048124
RGPIO[74]
PORT2[10]
PTD20
IOMUXC_PTD20
40048128
RGPIO[75]
PORT2[11]
PTD19
IOMUXC_PTD19
4004812C
RGPIO[76]
PORT2[12]
PTD18
IOMUXC_PTD18
40048130
RGPIO[77]
PORT2[13]
PTD17
IOMUXC_PTD17
40048134
RGPIO[78]
PORT2[14]
PTD16
IOMUXC_PTD16
40048138
RGPIO[79]
PORT2[15]
PTD0
IOMUXC_PTD0
4004813C
RGPIO[80]
PORT2[16]
PTD1
IOMUXC_PTD1
40048140
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Table 3-34. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[81]
PORT2[17]
PTD2
IOMUXC_PTD2
40048144
RGPIO[82]
PORT2[18]
PTD3
IOMUXC_PTD3
40048148
RGPIO[83]
PORT2[19]
PTD4
IOMUXC_PTD4
4004814C
RGPIO[84]
PORT2[20]
PTD5
IOMUXC_PTD5
40048150
RGPIO[85]
PORT2[21]
PTD6
IOMUXC_PTD6
40048154
RGPIO[86]
PORT2[22]
PTD7
IOMUXC_PTD7
40048158
RGPIO[87]
PORT2[23]
PTD8
IOMUXC_PTD8
4004815C
RGPIO[88]
PORT2[24]
PTD9
IOMUXC_PTD9
40048160
RGPIO[89]
PORT2[25]
PTD10
IOMUXC_PTD10
40048164
RGPIO[90]
PORT2[26]
PTD11
IOMUXC_PTD11
40048168
RGPIO[91]
PORT2[27]
PTD12
IOMUXC_PTD12
4004816C
RGPIO[92]
PORT2[28]
PTD13
IOMUXC_PTD13
40048170
RGPIO[93]
PORT2[29]
PTB23
IOMUXC_PTB23
40048174
RGPIO[94]
PORT2[30]
PTB24
IOMUXC_PTB24
40048178
RGPIO[95]
PORT2[31]
PTB25
IOMUXC_PTB25
4004817C
RGPIO[96]
PORT3[0]
PTB26
IOMUXC_PTB26
40048180
RGPIO[97]
PORT3[1]
PTB27
IOMUXC_PTB27
40048184
RGPIO[98]
PORT3[2]
PTB28
IOMUXC_PTB28
40048188
RGPIO[99]
PORT3[3]
PTC26
IOMUXC_PTC26
4004818C
RGPIO[100]
PORT3[4]
PTC27
IOMUXC_PTC27
40048190
RGPIO[101]
PORT3[5]
PTC28
IOMUXC_PTC28
40048194
RGPIO[102]
PORT3[6]
PTC29
IOMUXC_PTC29
40048198
RGPIO[103]
PORT3[7]
PTC30
IOMUXC_PTC30
4004819C
RGPIO[104]
PORT3[8]
PTC31
IOMUXC_PTC31
400481A0
RGPIO[105]
PORT3[9]
PTE0
IOMUXC_PTE0
400481A4
RGPIO[106]
PORT3[10]
PTE1
IOMUXC_PTE1
400481A8
RGPIO[107]
PORT3[11]
PTE2
IOMUXC_PTE2
400481AC
RGPIO[108]
PORT3[12]
PTE3
IOMUXC_PTE3
400481B0
RGPIO[109]
PORT3[13]
PTE4
IOMUXC_PTE4
400481B4
RGPIO[110]
PORT3[14]
PTE5
IOMUXC_PTE5
400481B8
RGPIO[111]
PORT3[15]
PTE6
IOMUXC_PTE6
400481BC
RGPIO[112]
PORT3[16]
PTE7
IOMUXC_PTE7
400481C0
RGPIO[113]
PORT3[17]
PTE8
IOMUXC_PTE8
400481C4
RGPIO[114]
PORT3[18]
PTE9
IOMUXC_PTE9
400481C8
RGPIO[115]
PORT3[19]
PTE10
IOMUXC_PTE10
400481CC
RGPIO[116]
PORT3[20]
PTE11
IOMUXC_PTE11
400481D0
RGPIO[117]
PORT3[21]
PTE12
IOMUXC_PTE12
400481D4
RGPIO[118]
PORT3[22]
PTE13
IOMUXC_PTE13
400481D8
RGPIO[119]
PORT3[23]
PTE14
IOMUXC_PTE14
400481DC
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GPIO
Table 3-34. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[120]
PORT3[24]
PTE15
IOMUXC_PTE15
400481E0
RGPIO[121]
PORT3[25]
PTE16
IOMUXC_PTE16
400481E4
RGPIO[122]
PORT3[26]
PTE17
IOMUXC_PTE17
400481E8
RGPIO[123]
PORT3[27]
PTE18
IOMUXC_PTE18
400481EC
RGPIO[124]
PORT3[28]
PTE19
IOMUXC_PTE19
400481F0
RGPIO[125]
PORT3[29]
PTE20
IOMUXC_PTE20
400481F4
RGPIO[126]
PORT3[30]
PTE21
IOMUXC_PTE21
400481F8
RGPIO[127]
PORT3[31]
PTE22
IOMUXC_PTE22
400481FC
RGPIO[128]
PORT4[0]
PTE23
IOMUXC_PTE23
40048200
RGPIO[129]
PORT4[1]
PTE24
IOMUXC_PTE24
40048204
RGPIO[130]
PORT4[2]
PTE25
IOMUXC_PTE25
40048208
RGPIO[131]
PORT4[3]
PTE26
IOMUXC_PTE26
4004820C
RGPIO[132]
PORT4[4]
PTE27
IOMUXC_PTE27
40048210
RGPIO[133]
PORT4[5]
PTE28
IOMUXC_PTE28
40048214
RGPIO[134]
PORT4[6]
PTA7
IOMUXC_PTA7
40048218
3.14.1.2 Configuring a pin as GPIO
To program a pin as GPIO:
1. Program the corresponding register in IOMUX. For example, to configure PORT0pin16 (PTA16), program IOMUXC_PTA16.
2. Program proper ALT mode in this register and program IBE (for Input) and OBE (for
Output).
3. Program the GPIO registers (PDOR, PSOR, PCOR, PTOR, PDIR) you can set/reset
this pin or read from this pin.
NOTE
For details about IOMUX and GPIO registers, see the
respective chapters of this document.
3.14.1.3 Port 4 Register Differences
In this device, 135 PADs are implemented across 5 RGPIO port instances as 4 x 32 + 7.
The last instance has only 7 PAD control registers. The dedicated RGPIO chapter
documents the identically instantiated Port 0, 1, 2, and 3. The following table summarizes
Port E register details that differ from the other module instances.
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Table 3-35. Port 4 register differences from other Port instances
Instance
Port 4
Port Data Output Register
(GPIO_PDOR)
PDO[6:0] field is 7 bits wide
Port Data Input Register (GPIO_PDIR)
PDI [6:0] field is 7 bits wide
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Chapter 4
Memory Map
4.1 System memory map
The following table shows the high-level device memory map.
Table 4-1. Device Memory Map
CM4 Address Range
Size
[Start Addr - End Addr]
[MB]
CM4 Alias
System Address (A5)
[Start Addr - End Addr]
Region
Description
0x0000_0000 -0x007f_ffff
8
0x0000_0000
0x0000_0000-0x007f_ffff
Boot ROM
0x0080_0000-0x0fff_ffff
248
0x8080_0000
Reserved
CM4 DDR code
alias
0x1000_0000-0x17ff_ffff
128
0x2000_0000
Reserved
CM4 QuadSPI0
code alias
0x1800_0000-0x1eff_ffff
112
0x3000_0000
Reserved
CM4 FlexBus
code alias
0x1f00_0000-0x1f7f_ffff
8
0x3f00_0000
Reserved
CM4 OCRAM
code alias
0x1f80_0000-0x1fff_ffff
8
N/A
0x1f80_0000-0x1fff_ffff
CM4 TCML
(code)
0x2000_0000-0x2fff_ffff
256
0x2000_0000
0x2000_0000-0x2fff_ffff
QuadSPI0
Memory
0x3000_0000-0x3eff_ffff
240
0x3000_0000
0x3000_0000-0x3eff_ffff
FlexBus
0x3f00_0000- 0x3F03_FFFF
0.25
0x3f00_0000
0x3f00_0000-0x3F03_FFFF
OCRAM SysRAM0
0x3F04_0000 - 0x3F07_FFFF
0.25
0x3F04_0000
0x3F04_0000 - 0x3F07_FFFF
OCRAM sysRAM1
0x3F08_0000 - 0x3F3F_FFFF
3.50
N/A
Reserved
Reserved
0x3f40_0000-0x3f47_ffff
.5
0x3f40_0000
0x3f40_0000-0x3f47_ffff
OCRAM gfxRAM0
0x3f48_0000-0x3f4f_ffff
.5
0x3f48_0000
0x3f48_0000-0x3f4f_ffff
OCRAM –
gfxRAM1 / L2
cache
0x3f50_0000-3f7f_ffff
3
N/A
Reserved
Reserved
0x3f80_0000-0x3fff_ffff
8
N/A
0x3f80_0000-0x3fff_ffff
CM4 TCMU
(data)
Table continues on the next page...
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System memory map
Table 4-1. Device Memory Map (continued)
CM4 Address Range
Size
[Start Addr - End Addr]
[MB]
CM4 Alias
System Address (A5)
[Start Addr - End Addr]
Region
Description
0x4000_0000-0x4006_ffff
0.448
0x4000_0000
0x4000_0000-0x4006_ffff
IPS0
0x4007_C000-0x4007_ffff
0.016
0x4007_C000
0x4007_C000-0x4007_ffff
Reserved
0x4008_0000-0x400f_efff
0.5
0x4008_0000
0x4008_0000-0x400f_efff
IPS1
0x4010_0000-0x4fff_ffff
255
N/A
Reserved
Reserved
0x5000_0000-0x5fff_ffff
256
0x5000_0000-0x5fff_ffff
QuadSPI1
Memory
0x6000_0000 0x6fff_ffff
256
N/A
Reserved
Reserved
0x7000_0000 0x77ff_ffff
128
N/A
Reserved
Reserved
0x7800_0000 0x79ff_ffff
32
0x7800_0000
0x7800_0000 - 0x79ff_ffff
RLE
0x7a00_0000 0x7bff_ffff
32
0x7a00_0000
0x7a00_0000 - 0x7bff_ffff
QuadSPI1 Rx
buffer
0x7c00_0000 0x7dff_ffff
32
0x7c00_0000
0x7c00_0000 - 0x7dff_ffff
QuadSPI0 Rx
buffer
0x7e00_0000 0x7e7f_ffff
8
0x7e00_0000
0x7e00_0000 - 0x7e7f_ffff
gfxRAMRGB565 view
0x7e80_0000 0x7eff_ffff
8
0x7e80_0000
0x7e80_0000 - 0x7eff_ffff
gfxRAMARGB1555 view
0x7f00_0000 0x7f7f_ffff
8
0x7f00_0000
0x7f00_0000 - 0x7f7f_ffff
gfxRAMARGB4444 view
0x7f80_0000 0x7fff_ffff
8
N/A
Reserved
Reserved
0x8000_0000-0xdfff_ffff
1536
0x8000_0000-0xdfff_ffff
DDR
0xe000_0000-0xffff_ffff
512
N/A
Reserved
CM4 Private
Peripheral Bus
(PPB)
512
N/A
0xe000_0000-0xffff_ffff
DDR (A5 only)
NOTE
64 KB/16 KB SRAM, which is retained in LPSTOP modes
occupies the lower part of OCRAM-SysRAM0
NOTE
For OCRAM-gfxRAM region (0x3f40_0000-0x3f4f_ffff), if
there is no L2 cache on the device, the entire 1 MB space based
at 0x3f40_0000 is allocated to gfxRAM. If the device has L2
cache, the first 512 KB (0x3f40_0000 - 0x3f47_ffff) is
allocated to gfxRAM and the upper 512 KB is allocated to the
L2 Cache data array.
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Chapter 4 Memory Map
NOTE
If there is an access to reserved/illegal memory space, then the
system may hang, requiring a reset to recover. There is no timeout mechanism to recover from this scenario.
4.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
NOTE
Not all features are available on each device. For the features
enabled on a specific part, refer to the data sheets.
Table 4-2. Peripheral bridge 0 slot assignments
System 32-bit base address
Slot
number
Module
On-platform
0x4000_0000
0
0x4000_1000
1
MSCM (CPU Configuration, INTR, OCRAM)
0x4000_2000
2
CA5-SCU+GIC CPU Interface registers1
0x4000_3000
3
CA5-INTD GIC Distributor registers1
0x4000_4000
4
0x4000_5000
5
0x4000_6000
6
0x4000_7000
7
0x4000_8000
8
NIC0 (Network Interconnect)
0x4000_9000
9
NIC1
0x4000_A000
10
NIC2
CA5-L2C (CA5 L2 Cache Controller)
0x4000_B000
11
NIC3
0x4000_C000
12
NIC4
0x4000_D000
13
NIC5
0x4000_E000
14
NIC6
0x4000_F000
15
NIC7
0x4001_0000
16
0x4001_1000
17
0x4001_2000
18
0x4001_3000
19
0x4001_4000
20
0x4001_5000
21
0x4001_6000
22
0x4001_7000
23
0x4001_8000
24
DMA0
0x4001_9000
25
DMA0_TCD
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Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4001_A000
26
0x4001_B000
27
0x4001_C000
28
0x4001_D000
29
SEMA4
0x4001_E000
30
FlexBus
0x4001_F000
31
Off-platform
0x4002_0000
32
FlexCAN0
0x4002_1000
33
FlexCAN0
0x4002_2000
34
FlexCAN0
0x4002_3000
35
FlexCAN0
0x4002_4000
36
DMA channel Mux0
0x4002_5000
37
DMA channel Mux1
0x4002_6000
38
0x4002_7000
39
UART0
0x4002_8000
40
UART1
0x4002_9000
41
UART2
0x4002_A000
42
UART3
0x4002_B000
43
0x4002_C000
44
SPI 0
0x4002_D000
45
SPI 1
0x4002_E000
46
0x4002_F000
47
SAI0
0x4003_0000
48
SAI1
0x4003_1000
49
SAI2
0x4003_2000
50
SAI3
0x4003_3000
51
CRC
0x4003_4000
52
USBC0
0x4003_5000
53
0x4003_6000
54
Programmable delay block (PDB)
0x4003_7000
55
Periodic interrupt timers (PIT)
0x4003_8000
56
FlexTimer (FTM) 0
0x4003_9000
57
FlexTimer (FTM) 1
0x4003_A000
58
—
0x4003_B000
59
Analog-to-digital converter (ADC) 0
0x4003_C000
60
0x4003_D000
61
TCON0
0x4003_E000
62
WDOG-A5
0x4003_F000
63
WDOG-M4
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Chapter 4 Memory Map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4004_0000
64
0x4004_1000
65
0x4004_2000
66
RLE
0x4004_3000
67
MLB (R-Series only)
0x4004_4000
68
QuadSPI0
0x4004_5000
69
0x4004_6000
70
0x4004_7000
71
0x4004_8000
72
IO MUX Controller
0x4004_9000
73
Port A multiplexing control
0x4004_A000
74
Port B multiplexing control
0x4004_B000
75
Port C multiplexing control
0x4004_C000
76
Port D multiplexing control
0x4004_D000
77
Port E multiplexing control
0x4004_E000
78
0x4004_F000
79
0x4005_0000
80
0x4005_1000
81
0x4005_2000
82
0x4005_3000
83
0x4005_4000
84
0x4005_5000
85
0x4005_6000
86
0x4005_7000
87
0x4005_8000
88
DCU0
0x4005_9000
89
DCU0
0x4005_A000
90
DCU0
0x4005_B000
91
DCU0
0x4005_C000
92
DCU0
0x4005_D000
93
DCU0
0x4005_E000
94
DCU0
0x4005_F000
95
DCU0
0x4006_0000
96
ASRC
0x4006_1000
97
SPDIF
0x4006_2000
98
ESAI
0x4006_3000
99
0x4006_4000
100
0x4006_5000
101
External watchdog (EWM)
0x4006_6000
102
I2C 0
Low-power timer (LPTMR)
ANADIG
Slow Clock Source Controller Module (SCSC)
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Peripheral Bridge 1 (AIPS-Lite 1) Memory Map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4006_7000
103
0x4006_8000
104
0x4006_9000
105
0x4006_A000
106
Wake up Unit (WKUP)
0x4006_B000
107
Clock Control Module (CCM)
0x4006_C000
108
Global Power Controller (GPC)
0x4006_D000
109
Voltage Regulator-Digital (VREG)
0x4006_E000
110
System Reset Controller (SRC)
0x4006_F000
111
Clock Monitor Unit (CMU)
I2C 1
1. Refer to ARM GIC documentation for details of these registers.
4.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map
NOTE
Not all features are available on each device. For the features
enabled on a specific part, refer to the data sheets.
Table 4-3. Peripheral bridge 1 slot assignments
System 32-bit base address
Slot
number
Module
On-platform
0x4008_0000
0
0x4008_1000
1
0x4008_2000
2
0x4008_3000
3
0x4008_4000
4
0x4008_5000
5
0x4008_6000
6
0x4008_7000
7
Debug Access Port (DAP)-RomTable
0x4008_8000
8
CA5-DBG (CA5 Debug)
0x4008_9000
9
CA5-PMU (CA5 Performance Monitoring Unit)
0x4008_A000
10
CA5-ETM
0x4008_B000
11
0x4008_C000
12
0x4008_D000
13
0x4008_E000
14
0x4008_F000
15
CA5-RomTable
CA5-CTI
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Chapter 4 Memory Map
Table 4-3. Peripheral bridge 1 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4009_0000
16
CA5-Instrumentation Trace Macrocell (ITM)
0x4009_1000
17
CA5-Embedded Trace Macrocell (ETB)
0x4009_2000
18
CA5-Funnel
0x4009_3000
19
Pltf-TCTL
0x4009_4000
20
Pltf-Trace Port Interface Unit (TPIU)
0x4009_5000
21
Pltf-Funnel
0x4009_6000
22
Pltf-Serial Wire Output (SWO)
0x4009_7000
23
0x4009_8000
24
DMA1
0x4009_9000
25
DMA1_TCD
0x4009_A000
26
0x4009_B000
27
0x4009_C000
28
0x4009_D000
29
0x4009_E000
30
0x4009_F000
31
Off-platform
0x400A_0000
32
0x400A_1000
33
DMA Channel Mux2
0x400A_2000
34
DMA Channel Mux3
0x400A_3000
35
0x400A_4000
36
0x400A_5000
37
0x400A_6000
38
0x400A_7000
39
0x400A_8000
40
0x400A_9000
41
UART4
0x400A_A000
42
UART5
OTP CTRL
0x400A_B000
43
0x400A_C000
44
SPI 2
0x400A_D000
45
SPI 3
0x400A_E000
46
DDRMC
0x400A_F000
47
0x400B_0000
48
0x400B_1000
49
SDHC0
0x400B_2000
50
SDHC1
0x400B_3000
51
0x400B_4000
52
0x400B_5000
53
USBC1
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Peripheral Bridge 1 (AIPS-Lite 1) Memory Map
Table 4-3. Peripheral bridge 1 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x400B_6000
54
0x400B_7000
55
0x400B_8000
56
FlexTimer (FTM) 2
0x400B_9000
57
FlexTimer (FTM) 3
0x400B_A000
58
0x400B_B000
59
0x400B_C000
60
0x400B_D000
61
TCON1
0x400B_E000
62
Segment LCD
0x400B_F000
63
0x400C_0000
64
0x400C_1000
65
0x400C_2000
66
0x400C_3000
67
0x400C_4000
68
0x400C_5000
69
0x400C_6000
70
0x400C_7000
71
Video ADC
0x400C_8000
72
Video Decoder
0x400C_9000
73
VIU3
0x400C_A000
74
0x400C_B000
75
0x400C_C000
76
12-bit digital-to-analog converter (DAC) 0
0x400C_D000
77
12-bit digital-to-analog converter (DAC) 1
0x400C_E000
78
0x400C_F000
79
Open VG GPU (R-Series only)
0x400D_0000
80
Ethernet MAC0 and IEEE 1588 timers
0x400D_1000
81
Ethernet MAC1 and IEEE 1588 timers
0x400D_2000
82
0x400D_3000
83
0x400D_4000
84
FlexCAN1
0x400D_5000
85
FlexCAN1
0x400D_6000
86
FlexCAN1
0x400D_7000
87
FlexCAN1
0x400D_8000
88
DCU1
0x400D_9000
89
DCU1
0x400D_A000
90
DCU1
0x400D_B000
91
DCU1
0x400D_C000
92
DCU1
Analog-to-digital converter (ADC) 1
QuadSPI1
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Chapter 4 Memory Map
Table 4-3. Peripheral bridge 1 slot assignments (continued)
System 32-bit base address
Slot
number
0x400D_D000
93
DCU1
0x400D_E000
94
DCU1
0x400D_F000
95
DCU1
0x400E_0000
96
Nand Flash Controller (NFC)
0x400E_1000
97
Nand Flash Controller (NFC)
0x400E_2000
98
Nand Flash Controller (NFC)
0x400E_3000
99
Nand Flash Controller (NFC)
0x400E_4000
100
0x400E_5000
101
0x400E_6000
102
I2C2
0x400E_7000
103
I2C3
0x400E_8000
104
Ethernet L2 Switch (F-Series only)
0x400E_9000
105
Ethernet L2 Switch (F-Series only)
0x400E_A000
106
Ethernet L2 Switch (F-Series only)
0x400E_B000
107
Ethernet L2 Switch (F-Series only)
0x400E_C000
108
Ethernet L2 Switch Look-up table (F-Series only)
0x400E_D000
109
Ethernet L2 Switch Look-up table (F-Series only)
0x400E_E000
110
Ethernet L2 Switch Look-up table (F-Series only)
0x400E_F000
111
Ethernet L2 Switch Look-up table (F-Series only)
0x400F_0000
112
0x400F_1000
113
0x400F_2000
114
0x400F_3000
115
0x400F_4000
116
0x400F_5000
117
0x400F_6000
118
0x400F_7000
119
0x400F_8000
120
0x400F_9000
121
0x400F_A000
122
0x400F_B000
123
0x400F_C000
124
0x400F_D000
125
0x400F_E000
126
0x400F_F000
Module
Not an AIPS-Lite slot. The 32-bit general purpose input/output module that shares the
crossbar switch slave port with the AIPS-Lite is accessed at this address.
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Private Peripheral Bus (PPB) memory map
NOTE
Access to non-implemented registers in the following modules
may result in unwanted behavior:
• UART
• MLB
• NFC
• IOMUX
• ASRC
• SPDIF
• VIU
• TCON
• USB
• OCOTP
• ANADIG
• SDHC
4.4 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 4-4. PPB memory map
System 32-bit Address Range
Resource
0xE000_0000–0xE000_0FFF
Instrumentation Trace Macrocell (ITM)
0xE000_1000–0xE000_1FFF
Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF
Flash Patch and Breakpoint (FPB)
0xE000_3000–0xE000_DFFF
Reserved
0xE000_E000–0xE000_EFFF
System Control Space (SCS) (for NVIC and FPU)
0xE000_F000–0xE004_0FFF
Reserved
0xE004_1000–0xE004_1FFF
Embedded Trace Macrocell (ETM)
0xE004_2000–0xE004_2FFF
Embedded Trace Buffer (ETB)
0xE004_3000–0xE004_3FFF
Embedded Trace Funnel
0xE004_4000–0xE004_4FFF
Cross Trigger Interface (CTI)
0xE005_0000–0xE007_4FFF
Reserved
0xE008_0000–0xE008_0FFF
Miscellaneous Control Module (MCM)
0xE008_1000–0xE008_1FFF
Reserved
0xE008_2000–0xE008_2FFF
Cache Controller
0xE008_3000–0xE00F_EFFF
Reserved
0xE00F_F000–0xE00F_FFFF
ROM Table - allows auto-detection of debug components
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Chapter 5
Chip IO and Pinmux
5.1 Pinouts
For part number and package-specific pinout details, refer to the data sheets.
A Quick Reference Guide to the pinouts can also be found at the end of this document.
5.2 Input/Output Multiplexer Controller (IOMUXC)
5.2.1 Overview
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the device to
share one pad to several functional blocks. The sharing is done by multiplexing the pad
input/output signals.
Every module requires a specific pad setting (such as pull up, keeper, and so on). The pad
settings parameters are controlled by the IOMUXC.
The IOMUX consists only of combinatorial logic combined from several basic iomux
cells. Each basic iomux cell handles only one pad signal's muxing.
NOTE
IOMUX registers control the PAD settings. To see the PAD
mapping on this device with the PORT pins, refer to GPIO
Mapping
NOTE
For TCON[x] signals, like tcon0 refer to DCU0_TCONx signal
and tcon1 refer to DCU1_TCONx signal in the Pinouts table.
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Input/Output Multiplexer Controller (IOMUXC)
5.2.2 Functional Description
IOMUX module is used to configure the Pad settings through the IOMUX registers and
multiplex multiple modules on to a single PAD and drive input to a module from multiple
PADs. Muxing is done only on obe, ibe, ind and do and rest of the pad settings are
through IOMUX registers. DDR pads are dedicated pads for DDR and there is no muxing
on them.
IOMUX register – IOMUXC_PTD30
Pad controls:
DSE, PUE, PKE, etc.
MUX_SEL (ALT modes)
ALT0
ALT1
IO PAD
PTD30
(PADRING)
PAD_64
8x1
IOMUX
RGPIO[64]
RGPIO
PORTC[0]
•
•
•
•
•
ALT17
Figure 5-1. Path from the pint PTD30 to RGPIO
The figure below shows the GPIO Pad .
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Chapter 5 Chip IO and Pinmux
obe
dse0, dse1, dse2
Output
driver
do
Pad
sre
fsel0
fsel1
Driver
config
logic
pue
pus0
pus1
ode
PU/PD/Keeper
logic
pke
ibe
PU/PD
devices
Keeper
device
ind
Input
receiver
hys
Figure 5-2. GPIO PAD
Table 5-1. Signal Description
Signal Name
Description
Description
Pad
Input/Output
I/O to external world
do
Input
Data coming from the core into the pad
obe
Input
Output enable
ode
Input
Select open drain or CMOS output
dse
Input
Drive Strength select
sre
Input
Slew rate of output buffer
fsel1, fsel0
Input
Slew rate control (SPEED setting)
pke
Input
Enable pull up, pull down and keeper
capability
pue
Input
Enable pull-up/down or keeper
pus
Input
Pull-up/down select
ibe
Input
Input enable
ind
Output
Data coming out of the pad into the core
hys
Input
Select Schmitt trigger or CMOS input
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Input/Output Multiplexer Controller (IOMUXC)
NOTE
For DDR pads, there are additional control signals as explained
in IOMUX register map to control DDR functionality.
Table 5-2. Truth Table
ode
obe
pke
pue
pus
do
dse
pad
Output Buffer Mode (functional)
0
1
0
X
X
do
001, 010, 011,
100, 101, 110,
111
do
0
1
0
X
X
do
0
Z
0
0
0
X
X
X
X
Z
X
X
pad (keep
previous
state)
Output Buffer Mode + Keeper
0
0
1
0
X
Output Buffer Mode + pull-up/pull-down resistors
0
0
1
1
0
X
X
weak0 (pulldown 100
KOhm)
0
0
1
1
1
X
X
weak1 (pullup 47 KOhm)
0
0
1
1
10
X
X
weak1 (pullup 100
KOhm)
0
0
1
1
11
X
X
weak1 (pullup 22 KOhm)
1
1
0
X
X
do
001, 010, 011,
100, 101, 110,
111
do
0
1
0
X
X
do
0
Z
1
0
0
X
X
X
X
Z
1
1
1
0
X
0
X
0 (open drain
+ keeper)
1
1
1
0
X
1
X
weak0
(keeper)
1
1
1
1
0
1
X
0 (open drain
+ pull-down)
Open Drain Mode
Open Drain Mode + Keeper/Pull-down
Open Drain Mode + Pull-up
1
1
1
1
1
0
X
0 (open drain
+ pull-up 47
KOhm)
1
1
1
1
10
0
X
0 (open drain
+ pull-up 100
KOhm)
Table continues on the next page...
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Chapter 5 Chip IO and Pinmux
Table 5-2. Truth Table (continued)
ode
obe
pke
pue
pus
do
dse
pad
1
1
1
1
11
0
X
0 (open drain
+ pull-up 22
KOhm)
1
1
1
1
1
1
X
weak1 (open
drain +pull-up
47 KOhm)
1
1
1
1
10
1
X
weak1 (open
drain +pull-up
100 KOhm)
1
1
1
1
11
1
X
weak1 (open
drain +pull-up
22 KOhm)
1
0
0
X
X
X
X
Z
1
0
1
0
X
X
X
pad (keep
previous
state)
Table 5-3. Truth Table - Pad to Core
ibe
pad
ind (keep previous state)
0
X
ind
1
pad
pad
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Input/Output Multiplexer Controller (IOMUXC)
5.2.3 Daisy chain - multi pads driving same module input pin
In some cases, more than one pad may drive a single module input pin. Such cases
require the addition of one more level of IOMUXing; all of these input signals are
muxed, and a dedicated software controlled register controls the mux in order to select
the required input path.
A module port involved in "daisy chain" requires two software configuration commands,
one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers).
This means that a module port involved in "daisy chain" requires two software
configuration commands, one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers). The daisy chain is illustrated in the figure below.
IOMUX
IOMUX Cells
IORING
To module D
To module F
A
To module X
ALT x select
To module G
To module X
Module X
B
To module H
ALT x select
Daisy Chain
select
To module X
To module M
To module N
C
ALT x select
Figure 5-3. Daisy chain illustration
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Chapter 5 Chip IO and Pinmux
5.2.4 IOMUXC register groups
The main groups of the IOMUXC registers are:
• The General Purpose Registers IOMUXC_GPR[13:0] are used to select operating
modes for general features in the SoC, usually not related to the IOMUX itself.
• The Software MUX Control Registers are used to configure the IOMUX muxing,
and "connect" the pad to a given port in a module.
• The PAD Settings Registers are used to control the pad settings configuration. For
some pads (in order to save chip route) the pad settings are grouped in one register;
changing the group register will affect the settings for all pads in the group.
IOMUXC shows the IOMUXC register summary.
5.2.5 Memory map and register definition
IOMUXC memory map
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_8000
Software MUX Pad Control Register 0 (IOMUXC_PTA6)
32
R/W
0000_0060h
5.2.5.1/256
4004_8004
Software MUX Pad Control Register 1 (IOMUXC_PTA8)
32
R/W
0010_006Dh
5.2.5.2/257
4004_8008
Software MUX Pad Control Register 2 (IOMUXC_PTA9)
32
R/W
0010_006Dh
5.2.5.3/259
4004_800C
Software MUX Pad Control Register 3 (IOMUXC_PTA10)
32
R/W
0010_3060h
5.2.5.4/261
4004_8010
Software MUX Pad Control Register 4 (IOMUXC_PTA11)
32
R/W
0010_006Dh
5.2.5.5/263
4004_8014
Software MUX Pad Control Register 5 (IOMUXC_PTA12)
32
R/W
0000_0060h
5.2.5.6/264
4004_8018
Software MUX Pad Control Register 6 (IOMUXC_PTA16)
32
R/W
0000_0060h
5.2.5.7/266
4004_801C
Software MUX Pad Control Register 7 (IOMUXC_PTA17)
32
R/W
0000_0060h
5.2.5.8/268
4004_8020
Software MUX Pad Control Register 8 (IOMUXC_PTA18)
32
R/W
0000_0060h
5.2.5.9/270
4004_8024
Software MUX Pad Control Register 9 (IOMUXC_PTA19)
32
R/W
0000_0060h
5.2.5.10/
271
4004_8028
Software MUX Pad Control Register 10 (IOMUXC_PTA20)
32
R/W
0000_0060h
5.2.5.11/
273
4004_802C
Software MUX Pad Control Register 11 (IOMUXC_PTA21)
32
R/W
0000_0060h
5.2.5.12/
275
4004_8030
Software MUX Pad Control Register 12 (IOMUXC_PTA22)
32
R/W
0000_0060h
5.2.5.13/
277
4004_8034
Software MUX Pad Control Register 13 (IOMUXC_PTA23)
32
R/W
0000_0060h
5.2.5.14/
278
4004_8038
Software MUX Pad Control Register 14 (IOMUXC_PTA24)
32
R/W
0000_0060h
5.2.5.15/
280
Table continues on the next page...
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Input/Output Multiplexer Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_803C
Software MUX Pad Control Register 15 (IOMUXC_PTA25)
32
R/W
0000_0060h
5.2.5.16/
282
4004_8040
Software MUX Pad Control Register 16 (IOMUXC_PTA26)
32
R/W
0000_0060h
5.2.5.17/
283
4004_8044
Software MUX Pad Control Register 17 (IOMUXC_PTA27)
32
R/W
0000_0060h
5.2.5.18/
285
4004_8048
Software MUX Pad Control Register 18 (IOMUXC_PTA28)
32
R/W
0000_0060h
5.2.5.19/
287
4004_804C
Software MUX Pad Control Register 19 (IOMUXC_PTA29)
32
R/W
0000_0060h
5.2.5.20/
288
4004_8050
Software MUX Pad Control Register 20 (IOMUXC_PTA30)
32
R/W
0000_0060h
5.2.5.21/
290
4004_8054
Software MUX Pad Control Register 21 (IOMUXC_PTA31)
32
R/W
0000_0060h
5.2.5.22/
292
4004_8058
Software MUX Pad Control Register 22 (IOMUXC_PTB0)
32
R/W
0000_0060h
5.2.5.23/
294
4004_805C
Software MUX Pad Control Register 23 (IOMUXC_PTB1)
32
R/W
0030_0060h
5.2.5.24/
295
4004_8060
Software MUX Pad Control Register 24 (IOMUXC_PTB2)
32
R/W
0030_0060h
5.2.5.25/
297
4004_8064
Software MUX Pad Control Register 25 (IOMUXC_PTB3)
32
R/W
0000_0060h
5.2.5.26/
299
4004_8068
Software MUX Pad Control Register 26 (IOMUXC_PTB4)
32
R/W
0000_0060h
5.2.5.27/
301
4004_806C
Software MUX Pad Control Register 27 (IOMUXC_PTB5)
32
R/W
0000_0060h
5.2.5.28/
302
4004_8070
Software MUX Pad Control Register 28 (IOMUXC_PTB6)
32
R/W
0000_0060h
5.2.5.29/
304
4004_8074
Software MUX Pad Control Register 29 (IOMUXC_PTB7)
32
R/W
0000_0060h
5.2.5.30/
306
4004_8078
Software MUX Pad Control Register 30 (IOMUXC_PTB8)
32
R/W
0000_0060h
5.2.5.31/
308
4004_807C
Software MUX Pad Control Register 31 (IOMUXC_PTB9)
32
R/W
0000_0060h
5.2.5.32/
309
4004_8080
Software MUX Pad Control Register 32 (IOMUXC_PTB10)
32
R/W
0000_0060h
5.2.5.33/
311
4004_8084
Software MUX Pad Control Register 33 (IOMUXC_PTB11)
32
R/W
0000_0060h
5.2.5.34/
313
4004_8088
Software MUX Pad Control Register 34 (IOMUXC_PTB12)
32
R/W
0000_0060h
5.2.5.35/
315
4004_808C
Software MUX Pad Control Register 35 (IOMUXC_PTB13)
32
R/W
0000_0060h
5.2.5.36/
316
4004_8090
Software MUX Pad Control Register 36 (IOMUXC_PTB14)
32
R/W
0000_0060h
5.2.5.37/
318
Table continues on the next page...
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Chapter 5 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_8094
Software MUX Pad Control Register 37 (IOMUXC_PTB15)
32
R/W
0000_0060h
5.2.5.38/
320
4004_8098
Software MUX Pad Control Register 38 (IOMUXC_PTB16)
32
R/W
0000_0060h
5.2.5.39/
321
4004_809C
Software MUX Pad Control Register 39 (IOMUXC_PTB17)
32
R/W
0000_0060h
5.2.5.40/
323
4004_80A0
Software MUX Pad Control Register 40 (IOMUXC_PTB18)
32
R/W
0000_0061h
5.2.5.41/
325
4004_80A4
Software MUX Pad Control Register 41 (IOMUXC_PTB19)
32
R/W
0000_0061h
5.2.5.42/
326
4004_80A8
Software MUX Pad Control Register 42 (IOMUXC_PTB20)
32
R/W
0000_0060h
5.2.5.43/
328
4004_80AC Software MUX Pad Control Register 43 (IOMUXC_PTB21)
32
R/W
0000_0060h
5.2.5.44/
330
4004_80B0
Software MUX Pad Control Register 44 (IOMUXC_PTB22)
32
R/W
0000_0061h
5.2.5.45/
331
4004_80B4
Software MUX Pad Control Register 45 (IOMUXC_PTC0)
32
R/W
0070_0061h
5.2.5.46/
333
4004_80B8
Software MUX Pad Control Register 46 (IOMUXC_PTC1)
32
R/W
0070_0061h
5.2.5.47/
335
4004_80BC Software MUX Pad Control Register 47 (IOMUXC_PTC2)
32
R/W
0070_0061h
5.2.5.48/
337
4004_80C0
Software MUX Pad Control Register 48 (IOMUXC_PTC3)
32
R/W
0000_0060h
5.2.5.49/
338
4004_80C4
Software MUX Pad Control Register 49 (IOMUXC_PTC4)
32
R/W
0000_0060h
5.2.5.50/
340
4004_80C8
Software MUX Pad Control Register 50 (IOMUXC_PTC5)
32
R/W
0000_0060h
5.2.5.51/
342
4004_80CC Software MUX Pad Control Register 51 (IOMUXC_PTC6)
32
R/W
0000_0060h
5.2.5.52/
344
4004_80D0
Software MUX Pad Control Register 52 (IOMUXC_PTC7)
32
R/W
0000_0060h
5.2.5.53/
345
4004_80D4
Software MUX Pad Control Register 53 (IOMUXC_PTC8)
32
R/W
0000_0060h
5.2.5.54/
347
4004_80D8
Software MUX Pad Control Register 54 (IOMUXC_PTC9)
32
R/W
0000_0060h
5.2.5.55/
349
4004_80DC Software MUX Pad Control Register 55 (IOMUXC_PTC10)
32
R/W
0000_0060h
5.2.5.56/
351
4004_80E0
Software MUX Pad Control Register 56 (IOMUXC_PTC11)
32
R/W
0000_0060h
5.2.5.57/
352
4004_80E4
Software MUX Pad Control Register 57 (IOMUXC_PTC12)
32
R/W
0000_0060h
5.2.5.58/
354
4004_80E8
Software MUX Pad Control Register 58 (IOMUXC_PTC13)
32
R/W
0000_0060h
5.2.5.59/
356
Table continues on the next page...
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Input/Output Multiplexer Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_80EC Software MUX Pad Control Register 59 (IOMUXC_PTC14)
32
R/W
0000_0060h
5.2.5.60/
358
4004_80F0
Software MUX Pad Control Register 60 (IOMUXC_PTC15)
32
R/W
0000_0060h
5.2.5.61/
359
4004_80F4
Software MUX Pad Control Register 61 (IOMUXC_PTC16)
32
R/W
0000_0060h
5.2.5.62/
361
4004_80F8
Software MUX Pad Control Register 62 (IOMUXC_PTC17)
32
R/W
0000_0060h
5.2.5.63/
363
4004_80FC Software MUX Pad Control Register 63 (IOMUXC_PTD31)
32
R/W
0000_0060h
5.2.5.64/
365
4004_8100
Software MUX Pad Control Register 64 (IOMUXC_PTD30)
32
R/W
0000_0060h
5.2.5.65/
366
4004_8104
Software MUX Pad Control Register 65 (IOMUXC_PTD29)
32
R/W
0000_0060h
5.2.5.66/
368
4004_8108
Software MUX Pad Control Register 66 (IOMUXC_PTD28)
32
R/W
0000_0060h
5.2.5.67/
370
4004_810C
Software MUX Pad Control Register 67 (IOMUXC_PTD27)
32
R/W
0000_0060h
5.2.5.68/
371
4004_8110
Software MUX Pad Control Register 68 (IOMUXC_PTD26)
32
R/W
0000_0060h
5.2.5.69/
373
4004_8114
Software MUX Pad Control Register 69 (IOMUXC_PTD25)
32
R/W
0000_0060h
5.2.5.70/
375
4004_8118
Software MUX Pad Control Register 70 (IOMUXC_PTD24)
32
R/W
0000_0060h
5.2.5.71/
376
4004_811C
Software MUX Pad Control Register 71 (IOMUXC_PTD23)
32
R/W
0000_0060h
5.2.5.72/
378
4004_8120
Software MUX Pad Control Register 72 (IOMUXC_PTD22)
32
R/W
0000_0060h
5.2.5.73/
380
4004_8124
Software MUX Pad Control Register 73 (IOMUXC_PTD21)
32
R/W
0000_0060h
5.2.5.74/
382
4004_8128
Software MUX Pad Control Register 74 (IOMUXC_PTD20)
32
R/W
0000_0060h
5.2.5.75/
383
4004_812C
Software MUX Pad Control Register 75 (IOMUXC_PTD19)
32
R/W
0000_0060h
5.2.5.76/
385
4004_8130
Software MUX Pad Control Register 76 (IOMUXC_PTD18)
32
R/W
0000_0060h
5.2.5.77/
387
4004_8134
Software MUX Pad Control Register 77 (IOMUXC_PTD17)
32
R/W
0000_0060h
5.2.5.78/
389
4004_8138
Software MUX Pad Control Register 78 (IOMUXC_PTD16)
32
R/W
0000_0060h
5.2.5.79/
390
4004_813C
Software MUX Pad Control Register 79 (IOMUXC_PTD0)
32
R/W
0000_0060h
5.2.5.80/
392
4004_8140
Software MUX Pad Control Register 80 (IOMUXC_PTD1)
32
R/W
0000_0060h
5.2.5.81/
394
Table continues on the next page...
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Chapter 5 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_8144
Software MUX Pad Control Register 81 (IOMUXC_PTD2)
32
R/W
0000_0060h
5.2.5.82/
396
4004_8148
Software MUX Pad Control Register 82 (IOMUXC_PTD3)
32
R/W
0000_0060h
5.2.5.83/
397
4004_814C
Software MUX Pad Control Register 83 (IOMUXC_PTD4)
32
R/W
0000_0060h
5.2.5.84/
399
4004_8150
Software MUX Pad Control Register 84 (IOMUXC_PTD5)
32
R/W
0000_0060h
5.2.5.85/
401
4004_8154
Software MUX Pad Control Register 85 (IOMUXC_PTD6)
32
R/W
0000_0060h
5.2.5.86/
403
4004_8158
Software MUX Pad Control Register 86 (IOMUXC_PTD7)
32
R/W
0000_0060h
5.2.5.87/
404
4004_815C
Software MUX Pad Control Register 87 (IOMUXC_PTD8)
32
R/W
0000_0060h
5.2.5.88/
406
4004_8160
Software MUX Pad Control Register 88 (IOMUXC_PTD9)
32
R/W
0000_0060h
5.2.5.89/
408
4004_8164
Software MUX Pad Control Register 89 (IOMUXC_PTD10)
32
R/W
0000_0060h
5.2.5.90/
410
4004_8168
Software MUX Pad Control Register 90 (IOMUXC_PTD11)
32
R/W
0000_0060h
5.2.5.91/
411
4004_816C
Software MUX Pad Control Register 91 (IOMUXC_PTD12)
32
R/W
0000_0060h
5.2.5.92/
413
4004_8170
Software MUX Pad Control Register 92 (IOMUXC_PTD13)
32
R/W
0000_0060h
5.2.5.93/
415
4004_8174
Software MUX Pad Control Register 93 (IOMUXC_PTB23)
32
R/W
0030_0061h
5.2.5.94/
416
4004_8178
Software MUX Pad Control Register 94 (IOMUXC_PTB24)
32
R/W
0030_0061h
5.2.5.95/
418
4004_817C
Software MUX Pad Control Register 95 (IOMUXC_PTB25)
32
R/W
0030_0061h
5.2.5.96/
420
4004_8180
Software MUX Pad Control Register 96 (IOMUXC_PTB26)
32
R/W
0030_0061h
5.2.5.97/
422
4004_8184
Software MUX Pad Control Register 97 (IOMUXC_PTB27)
32
R/W
0030_0061h
5.2.5.98/
423
4004_8188
Software MUX Pad Control Register 98 (IOMUXC_PTB28)
32
R/W
0030_0061h
5.2.5.99/
425
4004_818C
Software MUX Pad Control Register 99 (IOMUXC_PTC26)
32
R/W
0030_0061h
5.2.5.100/
427
4004_8190
Software MUX Pad Control Register 100 (IOMUXC_PTC27)
32
R/W
0030_0061h
5.2.5.101/
428
4004_8194
Software MUX Pad Control Register 101 (IOMUXC_PTC28)
32
R/W
0030_0061h
5.2.5.102/
430
4004_8198
Software MUX Pad Control Register 102 (IOMUXC_PTC29)
32
R/W
0030_0061h
5.2.5.103/
432
Table continues on the next page...
VFxxx Controller Reference Manual, Rev. 0, 10/2016
NXP Semiconductors
249
Input/Output Multiplexer Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
4004_819C
Software MUX Pad Control Register 103 (IOMUXC_PTC30)
32
4004_81A0
Software MUX Pad Control Register 104 (IOMUXC_PTC31)
4004_81A4
4004_81A8
Reset value
Section/
page
R/W
0030_0061h
5.2.5.104/
434
32
R/W
0030_0061h
5.2.5.105/
435
Software MUX Pad Control Register 105 (IOMUXC_PTE0)
32
R/W
0020_0044h
5.2.5.106/
437
Software MUX Pad Control Register 106 (IOMUXC_PTE1)
32
R/W
0020_0044h
5.2.5.107/
439
4004_81AC Software MUX Pad Control Register 107 (IOMUXC_PTE2)
32
R/W
0000_0060h
5.2.5.108/
440
4004_81B0
Software MUX Pad Control Register 108 (IOMUXC_PTE3)
32
R/W
0000_0060h
5.2.5.109/
442
4004_81B4
Software MUX Pad Control Register 109 (IOMUXC_PTE4)
32
R/W
0000_0060h
5.2.5.110/
444
4004_81B8
Software MUX Pad Control Register 110 (IOMUXC_PTE5)
32
R/W
0000_0060h
5.2.5.111/
445
4004_81BC Software MUX Pad Control Register 111 (IOMUXC_PTE6)
32
R/W
0000_0060h
5.2.5.112/
447
4004_81C0
Software MUX Pad Control Register 112 (IOMUXC_PTE7)
32
R/W
0030_0060h
5.2.5.113/
449
4004_81C4
Software MUX Pad Control Register 113 (IOMUXC_PTE8)
32
R/W
0030_0060h
5.2.5.114/
450
4004_81C8
Software MUX Pad Control Register 114 (IOMUXC_PTE9)
32
R/W
0030_0060h
5.2.5.115/
452
4004_81CC Software MUX Pad Control Register 115 (IOMUXC_PTE10)
32
R/W
0030_0060h
5.2.5.116/
454
4004_81D0
Software MUX Pad Control Register 116 (IOMUXC_PTE11)
32
R/W
0030_0060h
5.2.5.117/
455
4004_81D4
Software MUX Pad Control Register 117 (IOMUXC_PTE12)
32
R/W
0030_0060h
5.2.5.118/
457
4004_81D8
Software MUX Pad Control Register 118 (IOMUXC_PTE13)
32
R/W
0000_0060h
5.2.5.119/
459
4004_81DC Software MUX Pad Control Register 119 (IOMUXC_PTE14)
32
R/W
0000_0060h
5.2.5.120/
460
4004_81E0
Software MUX Pad Control Register 120 (IOMUXC_PTE15)
32
R/W
0030_0060h
5.2.5.121/
462
4004_81E4
Software MUX Pad Control Register 121 (IOMUXC_PTE16)
32
R/W
0030_0060h
5.2.5.122/
464
4004_81E8
Software MUX Pad Control Register 122 (IOMUXC_PTE17)
32
R/W
0030_0060h
5.2.5.123/
465
4004_81EC Software MUX Pad Control Register 123 (IOMUXC_PTE18)
32
R/W
0030_0060h
5.2.5.124/
467
4004_81F0
32
R/W
0030_0060h
5.2.5.125/
469
Software MUX Pad Control Register 124 (IOMUXC_PTE19)
Width
Access
(in bits)
Table continues on the next page...
VFxxx Controller Reference Manual, Rev. 0, 10/2016
250
NXP Semiconductors
Chapter 5 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
4004_81F4
Software MUX Pad Control Register 125 (IOMUXC_PTE20)
32
4004_81F8
Software MUX Pad Control Register 126 (IOMUXC_PTE21)
Width
Access
(in bits)
Reset value
Section/
page
R/W
0030_0060h
5.2.5.126/
470
32
R/W
0000_0060h
5.2.5.127/
472
4004_81FC Software MUX Pad Control Register 127 (IOMUXC_PTE22)
32
R/W
0000_0060h
5.2.5.128/
474
4004_8200
Software MUX Pad Control Register 128 (IOMUXC_PTE23)
32
R/W
0030_0060h
5.2.5.129/
475
4004_8204
Software MUX Pad Control Register 129 (IOMUXC_PTE24)
32
R/W
0030_0060h
5.2.5.130/
477
4004_8208
Software MUX Pad Control Register 130 (IOMUXC_PTE25)
32
R/W
0030_0060h
5.2.5.131/
479
4004_820C
Software MUX Pad Control Register 131 (IOMUXC_PTE26)
32
R/W
0030_0060h
5.2.5.132/
480
4004_8210
Software MUX Pad Control Register 132 (IOMUXC_PTE27)
32
R/W
0030_0060h
5.2.5.133/
482
4004_8214
Software MUX Pad Control Register 133 (IOMUXC_PTE28)
32
R/W
0030_0060h
5.2.5.134/
484
4004_8218
Software MUX Pad Control Register 134 (IOMUXC_PTA7)
32
R/W
0000_0060h
5.2.5.135/
486
4004_821C
Software MUX DDR RESET Pad Configuration Register
(IOMUXC_DDR_RESETB)
32
R/W
0001_0060h
5.2.5.136/
488
4004_8220
Software MUX DDR A15 Pad Control Register
(IOMUXC_DDR_A_15)
32
R/W
0001_0060h
5.2.5.137/
489
4004_8224
Software MUX DDR A14 Pad Control Register
(IOMUXC_DDR_A_14)
32
R/W
0001_0060h
5.2.5.138/
491
4004_8228
Software MUX DDR A13 Pad Control Register
(IOMUXC_DDR_A_13)
32
R/W
0001_0060h
5.2.5.139/
492
4004_822C
Software MUX DDR A12 Pad Control Register
(IOMUXC_DDR_A_12)
32
R/W
0001_0060h
5.2.5.140/
494
4004_8230
Software MUX DDR A11 Pad Control Register
(IOMUXC_DDR_A_11)
32
R/W
0001_0060h
5.2.5.141/
495
4004_8234
Software MUX DDR A10 Pad Control Register
(IOMUXC_DDR_A_10)
32
R/W
0001_0060h
5.2.5.142/
497
4004_8238
Software MUX DDR A9 Pad Control Register
(IOMUXC_DDR_A_9)
32
R/W
0001_0060h
5.2.5.143/
498
4004_823C
Software MUX DDR A8 Pad Control Register
(IOMUXC_DDR_A_8)
32
R/W
0001_0060h
5.2.5.144/
500
4004_8240
Software MUX DDR A7 Pad Control Register
(IOMUXC_DDR_A_7)
32
R/W
0001_0060h
5.2.5.145/
501
4004_8244
Software MUX DDR A6 Pad Control Register
(IOMUXC_DDR_A_6)
32
R/W
0001_0060h
5.2.5.146/
503
4004_8248
Software MUX DDR A5 Pad Control Register
(IOMUXC_DDR_A_5)
32
R/W
0001_0060h
5.2.5.147/
504
Table continues on the next page...
VFxxx Controller Reference Manual, Rev. 0, 10/2016
NXP Semiconductors
251
Input/Output Multiplexer Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_824C
Software MUX DDR A4 Pad Control Register
(IOMUXC_DDR_A_4)
32
R/W
0001_0060h
5.2.5.148/
506
4004_8250
Software MUX DDR Pad A3 Control Register
(IOMUXC_DDR_A_3)
32
R/W
0001_0060h
5.2.5.149/
507
4004_8254
Software MUX DDR A2 Pad Control Register
(IOMUXC_DDR_A_2)
32
R/W
0001_0060h
5.2.5.150/
509
4004_8258
Software MUX DDR A1 Pad Control Register
(IOMUXC_DDR_A_1)
32
R/W
0001_0060h
5.2.5.151/
510
4004_825C
Software MUX DDR A0 Pad Control Register
(IOMUXC_DDR_A_0)
32
R/W
0001_0060h
5.2.5.152/
512
4004_8260
Software MUX DDR BA2 Pad Control Register
(IOMUXC_DDR_BA_2)
32
R/W
0001_0060h
5.2.5.153/
513
4004_8264
Software MUX DDR BA1 Pad Control Register
(IOMUXC_DDR_BA_1)
32
R/W
0001_0060h
5.2.5.154/
515
4004_8268
Software MUX DDR BA0 Pad Control Register
(IOMUXC_DDR_BA_0)
32
R/W
0001_0060h
5.2.5.155/
516
4004_826C
Software MUX DDR CAS Pad Control Register
(IOMUXC_DDR_CAS_B)
32
R/W
0001_0060h
5.2.5.156/
518
4004_8270
Software MUX DDR CKE0 Pad Control Register
(IOMUXC_DDR_CKE_0)
32
R/W
0001_0068h
5.2.5.157/
519
4004_8274
Software MUX DDR CLK0 Pad Control Register
(IOMUXC_DDR_CLK_0)
32
R/W
0001_0060h
5.2.5.158/
521
4004_8278
Software MUX DDR CS B0 Pad Control Register
(IOMUXC_DDR_CS_B_0)
32
R/W
0001_0060h
5.2.5.159/
522
4004_827C
Software MUX DDR CS D15 Pad Control Register
(IOMUXC_DDR_CS_D_15)
32
R/W
0001_0060h
5.2.5.160/
524
4004_8280
Software MUX DDR CS D14 Pad Control Register
(IOMUXC_DDR_CS_D_14)
32
R/W
0001_0060h
5.2.5.161/
525
4004_8284
Software MUX DDR CS D13 Pad Control Register
(IOMUXC_DDR_CS_D_13)
32
R/W
0001_0060h
5.2.5.162/
527
4004_8288
Software MUX DDR CS D12 Pad Control Register
(IOMUXC_DDR_CS_D_12)
32
R/W
0001_0060h
5.2.5.163/
528
4004_828C
Software MUX DDR CS D11 Pad Control Register
(IOMUXC_DDR_CS_D_11)
32
R/W
0001_0060h
5.2.5.164/
530
4004_8290
Software MUX DDR CS D10 Pad Control Register
(IOMUXC_DDR_CS_D_10)
32
R/W
0001_0060h
5.2.5.165/
531
4004_8294
Software MUX DDR CS D9 Pad Control Register
(IOMUXC_DDR_CS_D_9)
32
R/W
0001_0060h
5.2.5.166/
533
4004_8298
Software MUX DDR CS D8 Pad Control Register
(IOMUXC_DDR_CS_D_8)
32
R/W
0001_0060h
5.2.5.167/
534
4004_829C
Software MUX DDR CS D7 Pad Control Register
(IOMUXC_DDR_CS_D_7)
32
R/W
0001_0060h
5.2.5.168/
536
4004_82A0
Software MUX DDR CS D6 Pad Control Register
(IOMUXC_DDR_CS_D_6)
32
R/W
0001_0060h
5.2.5.169/
537
Table continues on the next page...
VFxxx Controller Reference Manual, Rev. 0, 10/2016
252
NXP Semiconductors
Chapter 5 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_82A4
Software MUX DDR CS D5 Pad Control Register
(IOMUXC_DDR_CS_D_5)
32
R/W
0001_0060h
5.2.5.170/
539
4004_82A8
Software MUX DDR CS D4 Pad Control Register
(IOMUXC_DDR_CS_D_4)
32
R/W
0001_0060h
5.2.5.171/
540
4004_82AC
Software MUX DDR CS D3 Pad Control Register
(IOMUXC_DDR_CS_D_3)
32
R/W
0001_0060h
5.2.5.172/
542
4004_82B0
Software MUX DDR CS D2 Pad Control Register
(IOMUXC_DDR_CS_D_2)
32
R/W
0001_0060h
5.2.5.173/
543
4004_82B4
Software MUX DDR CS D1 Pad Control Register
(IOMUXC_DDR_CS_D_1)
32
R/W
0001_0060h
5.2.5.174/
545
4004_82B8
Software MUX DDR CS D0 Pad Control Register
(IOMUXC_DDR_CS_D_0)
32
R/W
0001_0060h
5.2.5.175/
546
4004_82BC
Software MUX DDR DQM1 Pad Control Register
(IOMUXC_DDR_DQM_1)
32
R/W
0001_0060h
5.2.5.176/
548
4004_82C0
Software MUX DDR DQM0 Pad Control Register 0
(IOMUXC_DDR_DQM_0)
32
R/W
0001_0060h
5.2.5.177/
549
4004_82C4
Software MUX DDR DQS1 Pad Control Register 1
(IOMUXC_DDR_DQS_1)
32
R/W
0001_0060h
5.2.5.178/
551
4004_82C8
Software MUX DDR DQS0 Pad Control Register 0
(IOMUXC_DDR_DQS_0)
32
R/W
0001_0060h
5.2.5.179/
552
4004_82CC
Software MUX DDR RAS Pad Control Register
(IOMUXC_DDR_RAS_B)
32
R/W
0001_0060h
5.2.5.180/
554
4004_82D0
Software MUX DDR WE Pad Control Register
(IOMUXC_DDR_WE_B)
32
R/W
0001_0060h
5.2.5.181/
555
4004_82D4
Software MUX DDR ODT0 Pad Control Register
(IOMUXC_DDR_ODT_0)
32
R/W
0001_0060h
5.2.5.182/
557
4004_82D8
Software MUX DDR ODT1 Pad Control Register
(IOMUXC_DDR_ODT_1)
32
R/W
0001_0060h
5.2.5.183/
558
4004_82DC
Software MUX Dummy DDRBYTE1 Pad Control Register
(IOMUXC_DUMMY_DDRBYTE1)
32
R/W
0001_0060h
5.2.5.184/
560
4004_82E0
Software MUX Dummy DDRBYTE2 Pad Control Register
(IOMUXC_DUMMY_DDRBYTE2)
32
R/W
0001_0060h
5.2.5.185/
561
4004_82EC
CCM Audio External Clock Input Select Register
(IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.186/
563
4004_82F0
CCM Ethernet External Clock Input Select Register
(IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.187/
563
4004_82F4
CCM Ethernet TS Clock Input Select Register
(IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.188/
564
4004_82F8
DSPI1 SCK Input Select Register
(IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.189/
565
4004_82FC
DSPI1 SIN Input Select Register
(IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.190/
566
4004_8300
DSPI1 SS Input Select Register
(IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.191/
567
Table continues on the next page...
VFxxx Controller Reference Manual, Rev. 0, 10/2016
NXP Semiconductors
253
Input/Output Multiplexer Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
4004_8304
Ethernet MAC0 TIMER0 Input Select Register
(IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SE
LECT_INPUT)
32
4004_8308
Ethernet MAC0 TIMER1 Input Select Register
(IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SE
LECT_INPUT)
4004_830C
Width
Access
(in bits)
Reset value
Section/
page
R/W
0000_0000h
5.2.5.192/
568
32
R/W
0000_0000h
5.2.5.193/
569
ESAI FST Input Select Register
(IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.194/
570
4004_8310
ESAI SCKT Input Select Register
(IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.195/
571
4004_8314
ESAI SDO0 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.196/
572
4004_8318
ESAI SDO1 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.197/
573
4004_831C
ESAI SDO2 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.198/
574
4004_8320
ESAI SDO3 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.199/
575
4004_8324
ESAI SDO4 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.200/
576
4004_8328
ESAI SDO5 Input Select Register
(IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.201/
577
4004_832C
FlexTimer1 CH0 Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_I
NPUT)
32
R/W
0000_0000h
5.2.5.202/
578
4004_8330
FlexTimer1 CH1 Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_I
NPUT)
32
R/W
0000_0000h
5.2.5.203/
579
4004_8334
FlexTimer1 PHA Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_IN
PUT)
32
R/W
0000_0000h
5.2.5.204/
580
4004_8338
FlexTimer1 PHB Input Select Register
(IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_IN
PUT)
32
R/W
0000_0000h
5.2.5.205/
581
4004_833C
I2C0 SCL Input Select Register
(IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.206/
581
4004_8340
I2C0 SDA Input Select Register
(IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.207/
582
4004_8344
I2C1 SCL Input Select Register
(IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.208/
583
4004_8348
I2C1 SDA Input Select Register
(IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.209/
583
4004_834C
I2C2 SCL Input Select Register
(IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.210/
584
Table continues on the next page...
VFxxx Controller Reference Manual, Rev. 0, 10/2016
254
NXP Semiconductors
Chapter 5 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_8350
I2C2 SDA Input Select Register
(IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.211/
585
4004_8354
MediaLB Clock Input Select Register
(IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.212/
586
4004_8358
MediaLB Data Input Select Register
(IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.213/
587
4004_835C
MediaLB Signal Input Select Register
(IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.214/
588
4004_8360
SAI1 TXSYNC Input Select Register
(IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.215/
589
4004_8364
SAI2 RXBCLK Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.216/
589
4004_8368
SAI2 RXDATA0 Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPU
T)
32
R/W
0000_0000h
5.2.5.217/
590
4004_836C
SAI2 RXSYNC Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.218/
591
4004_8370
SAI2 TXBLCK Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.219/
591
4004_8374
SAI2 TXSYNC Input Select Register
(IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.220/
592
4004_8378
UART FLX1 CTS Input Select Register
(IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.221/
593
4004_837C
UART FLX1 RX Input Select Register
(IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.222/
593
4004_8380
UART FLX1 TX Input Select Register
(IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.223/
594
4004_8384
UART FLX2 CTS Input Select Register
(IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.224/
595
4004_8388
UART FLX2 RX Input Select Register
(IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.225/
595
4004_838C
UART FLX2 TX Input Select Register
(IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.226/
596
4004_8390
UART FLX3 RX Input Select Register
(IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.227/
597
4004_8394
UART FLX3 TX Input Select Register
(IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.228/
598
4004_83A4
Video Decoder Input Select Register
(IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.229/
598
4004_83A8
Video IN0 Input Select Register
(IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT)
32
R/W
0000_0000h
5.2.5.230/
599
32
R/W
0000_0000h
5.2.5.231/
600
Video PIXCLK Input Select Register
4004_83AC (IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPU
T)
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5.2.5.1 Software MUX Pad Control Register 0 (IOMUXC_PTA6)
Address: 4004_8000h base + 0h offset = 4004_8000h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTA6 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA6.
NOTE: Pad PTA6 is involved in Daisy Chain.
• Config CCM_ENET_EXT_CLK_SELECT_INPUT for mode ALT2.
000
001
010
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[0] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII_CLKOUT of instance: ccm.
Select mux mode: ALT2 mux port: RMII_CLKIN of instance: ccm. Used as MAC0-TXCLK when
MAC0-MII is enabled.
Select mux mode: ALT4 mux port: TCON[11] of instance: tcon1.
Select mux mode: ALT7 mux port: DATA_OUT[20] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA6.
00
01
10
11
Low (50 MHz)
medium (100MHz)
medium (100MHz)
high (200MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA6.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA6.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA6.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA6.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
Table continues on the next page...
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IOMUXC_PTA6 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA6.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA6.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA6.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA6.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA6.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.2 Software MUX Pad Control Register 1 (IOMUXC_PTA8)
Address: 4004_8000h base + 4h offset = 4004_8004h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
1
1
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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IOMUXC_PTA8 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 4 IOMUX modes to be used for pad: PTA8.
NOTE: Pad PTA8 is involved in Daisy Chain.
• Config Register IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT for mode ALT7.
000
001
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[1] of instance: rgpioc.
Select mux mode: ALT1 mux port: TCLK of instance: debug.
Select mux mode: ALT4 mux port: DATA_OUT[18] of instance: tcon0.
Select mux mode: ALT7 mux port: MLBCLK of instance: mlb_top.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA8.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA8.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA8.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA8.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA8.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA8.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA8.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Table continues on the next page...
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IOMUXC_PTA8 field descriptions (continued)
Field
Description
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA8.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA8.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA8.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.3 Software MUX Pad Control Register 2 (IOMUXC_PTA9)
Address: 4004_8000h base + 8h offset = 4004_8008h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
1
1
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA9 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTA9.
NOTE: Pad PTA9 is involved in Daisy Chain.
• Config Register IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT for mode ALT3.
000
001
010
011
100
110
19–14
Reserved
Select mux mode: ALT0 mux port: GPIO[2] of instance: rgpioc.
Select mux mode: ALT1 mux port: TDI of instance: debug.
Select mux mode: ALT2 mux port: RMII_CLKOUT of instance: ccm.
Select mux mode: ALT3 mux port: RMII_CLKIN of instance: ccm. Used as MAC0-TXCLK when
MAC0-MII is enabled.
Select mux mode: ALT4 mux port: DATA_OUT[19] of instance: tcon0.
Select mux mode: ALT6 mux port: IPP_WDOG_CA5_CM4_B of instance: wdog_glue.
This field is reserved.
Table continues on the next page...
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IOMUXC_PTA9 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTA9.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA9.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA9.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA9.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA9.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA9.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA9.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA9.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA9.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA9.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Table continues on the next page...
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IOMUXC_PTA9 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.4 Software MUX Pad Control Register 3 (IOMUXC_PTA10)
Address: 4004_8000h base + Ch offset = 4004_800Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
1
0
1
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA10 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTA10.
NOTE: Pad PTA10 is involved in Daisy Chain.
• Config Register IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT for mode ALT6.
• Config Register IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT for mode ALT7.
000
001
010
100
110
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[3] of instance: rgpioc.
Select mux mode: ALT1 mux port: TDO of instance: debug.
Select mux mode: ALT2 mux port: EXT_AUDIO_MCLK of instance: ccm.
Select mux mode: ALT4 mux port: DATA_OUT[10] of instance: tcon0.
Select mux mode: ALT6 mux port: ENET_TS_CLKIN of instance: ccm.
Select mux mode: ALT7 mux port: MLBSIGNAL of instance: mlb_top.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA10.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTA10.
0
1
Slow Slew Rate
Fast Slew Rate
Table continues on the next page...
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IOMUXC_PTA10 field descriptions (continued)
Field
Description
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA10.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA10.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA10.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA10.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA10.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA10.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA10.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA10.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.5 Software MUX Pad Control Register 4 (IOMUXC_PTA11)
Address: 4004_8000h base + 10h offset = 4004_8010h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
1
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
1
1
0
1
IOMUXC_PTA11 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 4 IOMUX modes to be used for pad: PTA11.
NOTE: Pad PTA11 is involved in Daisy Chain.
• Config Register IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT for mode ALT7.
000
001
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[4] of instance: rgpioc.
Select mux mode: ALT1 mux port: TMS of instance: debug.
Select mux mode: ALT4 mux port: DATA_OUT[11] of instance: tcon0.
Select mux mode: ALT7 mux port: MLBDATA of instance: mlb_top.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA11.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA11.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA11.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA11.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA11.
0
1
0
1
0
1
000
001
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
Table continues on the next page...
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IOMUXC_PTA11 field descriptions (continued)
Field
Description
010
011
100
101
110
111
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA11.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA11.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA11.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA11.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA11.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.6 Software MUX Pad Control Register 5 (IOMUXC_PTA12)
Address: 4004_8000h base + 14h offset = 4004_8014h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTA12 field descriptions
Field
31–23
Reserved
Description
This field is reserved.
Table continues on the next page...
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IOMUXC_PTA12 field descriptions (continued)
Field
22–20
MUX_MODE
Description
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA12.
NOTE: Pad PTA12 is involved in Daisy Chain.
• Config Register IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT for mode ALT7.
000
001
010
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[5] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACECK of instance: platform.
Select mux mode: ALT2 mux port: EXT_AUDIO_MCLK of instance: ccm.
Select mux mode: ALT6 mux port: DATA[13] of instance: video_in0.
Select mux mode: ALT7 mux port: SCL of instance: i2c0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA12.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA12.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA12.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA12.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA12.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA12.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA12.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTA12 field descriptions (continued)
Field
Description
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA12.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA12.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA12.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.7 Software MUX Pad Control Register 6 (IOMUXC_PTA16)
Address: 4004_8000h base + 18h offset = 4004_8018h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA16 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTA16.
NOTE: Pad PTA16 is involved in Daisy Chain.
• Config Register IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT for mode ALT7.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT for mode ALT5.
000
001
010
011
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[6] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[0] of instance: platform.
Select mux mode: ALT2 mux port: VBUS_EN_OTG of instance: usb.
Select mux mode: ALT3 mux port: ADC1SE0 of instance: adc1_da.
Select mux mode: ALT4 mux port: LCD29 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: TX_BCLK of instance: sai2.
Select mux mode: ALT6 mux port: DATA[14] of instance: video_in0.
Select mux mode: ALT7 mux port: SDA of instance: i2c0.
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IOMUXC_PTA16 field descriptions (continued)
Field
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
Speed Field. Select one of the following values for pad: PTA16.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA16.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA16.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA16.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA16.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA16.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA16.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA16.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA16.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTA16 field descriptions (continued)
Field
Description
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA16.
0
1
Disabled
Enabled
5.2.5.8 Software MUX Pad Control Register 7 (IOMUXC_PTA17)
Address: 4004_8000h base + 1Ch offset = 4004_801Ch
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
21
20
19
MUX_MODE
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
0
0
7
6
5
DSE
0
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTA17 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTA17.
NOTE: Pad PTA17 is involved in Daisy Chain.
• Config Register IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT for mode ALT7.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[7] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[1] of instance: platform.
Select mux mode: ALT2 mux port: VBUS_OC_OTG of instance: usb.
Select mux mode: ALT3 mux port: ADC1SE1 of instance: adc1_da.
Select mux mode: ALT4 mux port: LCD30 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: USB0_SOF_PULSE of instance: usb.
Select mux mode: ALT6 mux port: DATA[15] of instance: video_in0.
Select mux mode: ALT7 mux port: SCL of instance: i2c1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA17.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTA17.
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IOMUXC_PTA17 field descriptions (continued)
Field
Description
0
1
Slow Slew Rate
Fast Slew Rate
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA17.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA17.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA17.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA17.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA17.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA17.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA17.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA17.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.9 Software MUX Pad Control Register 8 (IOMUXC_PTA18)
Address: 4004_8000h base + 20h offset = 4004_8020h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTA18 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTA18.
NOTE: Pad PTA18 is involved in Daisy Chain.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT for mode ALT7.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[8] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[2] of instance: platform.
Select mux mode: ALT2 mux port: ADC0SE0 of instance: adc0_da.
Select mux mode: ALT3 mux port: QD_PHA of instance: flextimer1.
Select mux mode: ALT4 mux port: LCD31 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: TX_DATA of instance: sai2.
Select mux mode: ALT6 mux port: DATA[16] of instance: video_in0.
Select mux mode: ALT7 mux port: SDA of instance: i2c1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA18.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA18.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA18.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA18.
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
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IOMUXC_PTA18 field descriptions (continued)
Field
Description
0
1
CMOS input
Schmitt trigger input
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA18.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA18.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA18.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA18.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA18.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA18.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.10 Software MUX Pad Control Register 9 (IOMUXC_PTA19)
Address: 4004_8000h base + 24h offset = 4004_8024h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTA19 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTA19.
NOTE: Pad PTA19 is involved in Daisy Chain.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT for mode ALT5.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[9] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[3] of instance: platform.
Select mux mode: ALT2 mux port: ADC0SE1 of instance: adc0_da.
Select mux mode: ALT3 mux port: QD_PHB of instance: flextimer1.
Select mux mode: ALT4 mux port: LCD32 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: TX_SYNC of instance: sai2.
Select mux mode: ALT6 mux port: DATA[17] of instance: video_in0.
Select mux mode: ALT7 mux port: QSCK_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA19.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA19.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA19.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA19.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA19.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA19.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
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IOMUXC_PTA19 field descriptions (continued)
Field
Description
01
10
11
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA19.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA19.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA19.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA19.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.11 Software MUX Pad Control Register 10 (IOMUXC_PTA20)
Address: 4004_8000h base + 28h offset = 4004_8028h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA20 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA20.
NOTE: Pad PTA20 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT6.
000
001
100
Select mux mode: ALT0 mux port: GPIO[10] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[4] of instance: platform.
Select mux mode: ALT4 mux port: LCD33 of instance: lcd_64f6b.
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IOMUXC_PTA20 field descriptions (continued)
Field
Description
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT6 mux port: TX of instance: sci_flx3.
Select mux mode: ALT7 mux port: TCON[1] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA20.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA20.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA20.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA20.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA20.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA20.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA20.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA20.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA20.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
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IOMUXC_PTA20 field descriptions (continued)
Field
Description
0
1
0
IBE
Disabled
Enabled
Input Buffer Enable Field. Select one of the following values for pad: PTA20.
0
1
Disabled
Enabled
5.2.5.12 Software MUX Pad Control Register 11 (IOMUXC_PTA21)
Address: 4004_8000h base + 2Ch offset = 4004_802Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA21 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA21.
NOTE: Pad PTA21 is involved in Daisy Chain.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT for mode ALT5.
• Config Register IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT6.
000
001
101
110
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[11] of instance: rgpioc. Also, RXCLK for MAC0 is enabled
in this mux mode so ensure obe is disabled if this pin is used for MAC0-MII instead of GPIO.
Select mux mode: ALT1 mux port: TRACED[5] of instance: platform.
Select mux mode: ALT5 mux port: RX_BCLK of instance: sai2.
Select mux mode: ALT6 mux port: RX of instance: sci_flx3.
Select mux mode: ALT7 mux port: TCON[2] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA21.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTA21.
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IOMUXC_PTA21 field descriptions (continued)
Field
Description
0
1
Slow Slew Rate
Fast Slew Rate
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA21.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA21.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA21.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA21.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA21.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA21.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA21.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA21.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.13 Software MUX Pad Control Register 12 (IOMUXC_PTA22)
Address: 4004_8000h base + 30h offset = 4004_8030h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTA22 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA22.
NOTE: Pad PTA22 is involved in Daisy Chain.
• Config Register IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT for mode ALT6.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT for mode ALT5.
000
001
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[12] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[6] of instance: platform.
Select mux mode: ALT5 mux port: RX_DATA of instance: sai2.
Select mux mode: ALT6 mux port: SCL of instance: i2c2.
Select mux mode: ALT7 mux port: TCON[0] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA22.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA22.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA22.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA22.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA22.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTA22 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA22.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA22.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA22.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA22.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA22.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.14 Software MUX Pad Control Register 13 (IOMUXC_PTA23)
Address: 4004_8000h base + 34h offset = 4004_8034h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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IOMUXC_PTA23 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA23.
NOTE: Pad PTA23 is involved in Daisy Chain.
• Config Register IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT for mode ALT6.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT for mode ALT5.
000
001
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[13] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[7] of instance: platform.
Select mux mode: ALT5 mux port: RX_SYNC of instance: sai2.
Select mux mode: ALT6 mux port: SDA of instance: i2c2.
Select mux mode: ALT7 mux port: TCON[3] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA23.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA23.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA23.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA23.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA23.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA23.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTA23 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA23.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA23.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA23.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA23.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.15 Software MUX Pad Control Register 14 (IOMUXC_PTA24)
Address: 4004_8000h base + 38h offset = 4004_8038h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTA24 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTA24.
000
001
010
101
110
111
Select mux mode: ALT0 mux port: GPIO[14] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[8] of instance: platform.
Select mux mode: ALT2 mux port: VBUS_EN of instance: usb.
Select mux mode: ALT5 mux port: CLK of instance: esdhc1.
Select mux mode: ALT6 mux port: TCON[4] of instance: tcon1.
Select mux mode: ALT7 mux port: PAD_CTRL of instance: ddr_test_logic.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA24.
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IOMUXC_PTA24 field descriptions (continued)
Field
Description
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA24.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA24.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA24.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA24.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA24.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA24.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA24.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA24.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA24.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.16 Software MUX Pad Control Register 15 (IOMUXC_PTA25)
Address: 4004_8000h base + 3Ch offset = 4004_803Ch
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTA25 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA25.
000
001
010
101
110
Select mux mode: ALT0 mux port: GPIO[15] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[9] of instance: platform.
Select mux mode: ALT2 mux port: VBUS_OC of instance: usb.
Select mux mode: ALT5 mux port: CMD of instance: esdhc1.
Select mux mode: ALT6 mux port: TCON[5] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA25.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA25.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA25.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA25.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA25.
0
1
0
1
0
1
000
001
010
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
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IOMUXC_PTA25 field descriptions (continued)
Field
Description
011
100
101
110
111
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA25.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA25.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA25.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA25.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA25.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.17 Software MUX Pad Control Register 16 (IOMUXC_PTA26)
Address: 4004_8000h base + 40h offset = 4004_8040h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA26 field descriptions
Field
31–23
Reserved
Description
This field is reserved.
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IOMUXC_PTA26 field descriptions (continued)
Field
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA26.
000
001
010
101
110
Select mux mode: ALT0 mux port: GPIO[16] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[10] of instance: platform.
Select mux mode: ALT2 mux port: TX_BCLK of instance: sai3.
Select mux mode: ALT5 mux port: DAT0 of instance: esdhc1.
Select mux mode: ALT6 mux port: TCON[6] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA26.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA26.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA26.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA26.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA26.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA26.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA26.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
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IOMUXC_PTA26 field descriptions (continued)
Field
Description
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA26.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA26.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA26.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.18 Software MUX Pad Control Register 17 (IOMUXC_PTA27)
Address: 4004_8000h base + 44h offset = 4004_8044h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTA27 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTA27.
000
001
010
101
110
Select mux mode: ALT0 mux port: GPIO[17] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[11] of instance: platform.
Select mux mode: ALT2 mux port: RX_BCLK of instance: sai3.
Select mux mode: ALT5 mux port: DAT1 of instance: esdhc1.
Select mux mode: ALT6 mux port: TCON[7] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA27.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
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IOMUXC_PTA27 field descriptions (continued)
Field
Description
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA27.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA27.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA27.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA27.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA27.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA27.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA27.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA27.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA27.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.19 Software MUX Pad Control Register 18 (IOMUXC_PTA28)
Address: 4004_8000h base + 48h offset = 4004_8048h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTA28 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTA28.
000
001
010
011
100
101
110
Select mux mode: ALT0 mux port: GPIO[18] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[12] of instance: platform.
Select mux mode: ALT2 mux port: RX_DATA of instance: sai3.
Select mux mode: ALT3 mux port: MAC1_TMR0 of instance: enet_swiahb.
Select mux mode: ALT4 mux port: TX of instance: sci_flx4.
Select mux mode: ALT5 mux port: DAT2 of instance: esdhc1.
Select mux mode: ALT6 mux port: TCON[8] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA28.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA28.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA28.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA28.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA28.
0
1
0
1
0
1
000
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
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IOMUXC_PTA28 field descriptions (continued)
Field
Description
001
010
011
100
101
110
111
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA28.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA28.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA28.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA28.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA28.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.20 Software MUX Pad Control Register 19 (IOMUXC_PTA29)
Address: 4004_8000h base + 4Ch offset = 4004_804Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTA29 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTA29.
000
001
010
011
100
101
110
Select mux mode: ALT0 mux port: GPIO[19] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[13] of instance: platform.
Select mux mode: ALT2 mux port: TX_DATA of instance: sai3.
Select mux mode: ALT3 mux port: MAC1_TMR1 of instance: enet_swiahb.
Select mux mode: ALT4 mux port: RX of instance: sci_flx4.
Select mux mode: ALT5 mux port: DAT3 of instance: esdhc1.
Select mux mode: ALT6 mux port: TCON[9] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA29.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA29.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA29.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA29.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA29.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA29.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTA29 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA29.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA29.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA29.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA29.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.21 Software MUX Pad Control Register 20 (IOMUXC_PTA30)
Address: 4004_8000h base + 50h offset = 4004_8050h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTA30 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTA30.
NOTE: Pad PTA30 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT7.
000
001
010
011
100
101
111
Select mux mode: ALT0 mux port: GPIO[20] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[14] of instance: platform.
Select mux mode: ALT2 mux port: RX_SYNC of instance: sai3.
Select mux mode: ALT3 mux port: MAC1_TMR2 of instance: enet_swiahb.
Select mux mode: ALT4 mux port: RTS of instance: sci_flx4.
Select mux mode: ALT5 mux port: SCL of instance: i2c3.
Select mux mode: ALT7 mux port: TX of instance: sci_flx3.
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IOMUXC_PTA30 field descriptions (continued)
Field
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
Speed Field. Select one of the following values for pad: PTA30.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTA30.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA30.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA30.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA30.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA30.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA30.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA30.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA30.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTA30 field descriptions (continued)
Field
Description
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA30.
0
1
Disabled
Enabled
5.2.5.22 Software MUX Pad Control Register 21 (IOMUXC_PTA31)
Address: 4004_8000h base + 54h offset = 4004_8054h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTA31 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTA31.
NOTE: Pad PTA31 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT7.
000
001
010
100
101
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[21] of instance: rgpioc.
Select mux mode: ALT1 mux port: TRACED[15] of instance: platform.
Select mux mode: ALT2 mux port: TX_SYNC of instance: sai3.
Select mux mode: ALT4 mux port: CTS of instance: sci_flx4.
Select mux mode: ALT5 mux port: SDA of instance: i2c3.
Select mux mode: ALT7 mux port: RX of instance: sci_flx3.
This field is reserved.
Speed Field. Select one of the following values for pad: PTA31.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTA31.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTA31 field descriptions (continued)
Field
Description
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTA31.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTA31.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTA31.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTA31.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTA31.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTA31.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTA31.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTA31.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.23 Software MUX Pad Control Register 22 (IOMUXC_PTB0)
Address: 4004_8000h base + 58h offset = 4004_8058h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
1
0
4
PUS
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTB0 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB0.
NOTE: Pad PTB0 is involved in Daisy Chain.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT for mode ALT5.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[22] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[0] of instance: flextimer0.
Select mux mode: ALT2 mux port: ADC0SE2 of instance: adc0_da.
Select mux mode: ALT3 mux port: TRACECTL of instance: platform.
Select mux mode: ALT4 mux port: LCD34 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: RX_BCLK of instance: sai2.
Select mux mode: ALT6 mux port: DATA[18] of instance: video_in0.
Select mux mode: ALT7 mux port: QPCS0_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB0.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB0.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB0.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB0.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTB0 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB0.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB0.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB0.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB0.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB0.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB0.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.24 Software MUX Pad Control Register 23 (IOMUXC_PTB1)
Address: 4004_8000h base + 5Ch offset = 4004_805Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTB1 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB1.
NOTE: Pad PTB1 is involved in Daisy Chain.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT for mode ALT5.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[23] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[1] of instance: flextimer0.
Select mux mode: ALT2 mux port: ADC0SE3 of instance: adc0_da.
Select mux mode: ALT3 mux port: RCON30 of instance: src.
Select mux mode: ALT4 mux port: LCD35 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: RX_DATA of instance: sai2.
Select mux mode: ALT6 mux port: DATA[19] of instance: video_in0.
Select mux mode: ALT7 mux port: QSPI_IO3_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB1.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB1.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB1.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB1.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB1.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB1.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
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IOMUXC_PTB1 field descriptions (continued)
Field
Description
10
11
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB1.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB1.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB1.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB1.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.25 Software MUX Pad Control Register 24 (IOMUXC_PTB2)
Address: 4004_8000h base + 60h offset = 4004_8060h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB2 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB2.
NOTE: Pad PTB2 is involved in Daisy Chain.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT for mode ALT5.
000
001
010
011
100
Select mux mode: ALT0 mux port: GPIO[24] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[2] of instance: flextimer0.
Select mux mode: ALT2 mux port: ADC1SE2 of instance: adc1_da.
Select mux mode: ALT3 mux port: RCON31 of instance: src.
Select mux mode: ALT4 mux port: LCD36 of instance: lcd_64f6b.
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IOMUXC_PTB2 field descriptions (continued)
Field
Description
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT5 mux port: RX_SYNC of instance: sai2.
Select mux mode: ALT6 mux port: DATA[20] of instance: video_in0.
Select mux mode: ALT7 mux port: QSPI_IO2_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB2.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB2.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB2.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB2.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB2.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB2.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB2.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB2.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
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IOMUXC_PTB2 field descriptions (continued)
Field
Description
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB2.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB2.
0
1
0
1
Disabled
Enabled
Disabled
Enabled
5.2.5.26 Software MUX Pad Control Register 25 (IOMUXC_PTB3)
Address: 4004_8000h base + 64h offset = 4004_8064h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB3 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
11
SRE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTB3.
000
001
010
011
100
110
111
Select mux mode: ALT0 mux port: GPIO[25] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[3] of instance: flextimer0.
Select mux mode: ALT2 mux port: ADC1SE3 of instance: adc1_da.
Select mux mode: ALT3 mux port: EXTRIG of instance: pdb.
Select mux mode: ALT4 mux port: LCD37 of instance: lcd_64f6b.
Select mux mode: ALT6 mux port: DATA[21] of instance: video_in0.
Select mux mode: ALT7 mux port: QSPI_IO1_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB3.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTB3.
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IOMUXC_PTB3 field descriptions (continued)
Field
Description
0
1
Slow Slew Rate
Fast Slew Rate
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB3.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB3.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB3.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB3.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB3.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB3.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB3.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB3.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.27 Software MUX Pad Control Register 26 (IOMUXC_PTB4)
Address: 4004_8000h base + 68h offset = 4004_8068h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
1
0
4
PUS
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTB4 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB4.
NOTE: Pad PTB4 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT for mode ALT5.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[26] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[4] of instance: flextimer0.
Select mux mode: ALT2 mux port: TX of instance: sci_flx1.
Select mux mode: ALT3 mux port: ADC0SE4 of instance: adc0_da.
Select mux mode: ALT4 mux port: LCD38 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: FID of instance: video_in0.
Select mux mode: ALT6 mux port: DATA[22] of instance: video_in0.
Select mux mode: ALT7 mux port: QSPI_IO0_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB4.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB4.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB4.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB4.
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
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IOMUXC_PTB4 field descriptions (continued)
Field
Description
0
1
CMOS input
Schmitt trigger input
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB4.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB4.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB4.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB4.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB4.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB4.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.28 Software MUX Pad Control Register 27 (IOMUXC_PTB5)
Address: 4004_8000h base + 6Ch offset = 4004_806Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTB5 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB5.
NOTE: Pad PTB5 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT for mode ALT5.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[27] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[5] of instance: flextimer0.
Select mux mode: ALT2 mux port: RX of instance: sci_flx1.
Select mux mode: ALT3 mux port: ADC1SE4 of instance: adc1_da.
Select mux mode: ALT4 mux port: LCD39 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: DE of instance: video_in0.
Select mux mode: ALT6 mux port: DATA[23] of instance: video_in0
Select mux mode: ALT7 mux port: DQS_A of instance: quadspi1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB5.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB5.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB5.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB5.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB5.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB5.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
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IOMUXC_PTB5 field descriptions (continued)
Field
Description
01
10
11
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB5.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB5.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB5.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB5.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.29 Software MUX Pad Control Register 28 (IOMUXC_PTB6)
Address: 4004_8000h base + 70h offset = 4004_8070h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB6 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB6.
NOTE: Pad PTB6 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT7.
000
001
010
011
Select mux mode: ALT0 mux port: GPIO[28] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[6] of instance: flextimer0.
Select mux mode: ALT2 mux port: RTS of instance: sci_flx1.
Select mux mode: ALT3 mux port: QPCS1_A of instance: quadspi0.
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IOMUXC_PTB6 field descriptions (continued)
Field
Description
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT4 mux port: LCD40 of instance: lcd_64f6b.
Select mux mode: ALT5 mux port: FB_CLKOUT of instance: lpcg0.
Select mux mode: ALT6 mux port: HSYNC of instance: video_in0.
Select mux mode: ALT7 mux port: TX of instance: sci_flx2.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB6.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB6.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB6.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB6.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB6.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB6.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB6.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB6.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
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IOMUXC_PTB6 field descriptions (continued)
Field
Description
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB6.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB6.
0
1
0
1
Disabled
Enabled
Disabled
Enabled
5.2.5.30 Software MUX Pad Control Register 29 (IOMUXC_PTB7)
Address: 4004_8000h base + 74h offset = 4004_8074h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB7 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTB7.
NOTE: Pad PTB7 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT7.
000
001
010
011
100
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[29] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[7] of instance: flextimer0.
Select mux mode: ALT2 mux port: CTS of instance: sci_flx1.
Select mux mode: ALT3 mux port: QPCS1_B of instance: quadspi0.
Select mux mode: ALT4 mux port: LCD41 of instance: lcd_64f6b.
Select mux mode: ALT6 mux port: VSYNC of instance: video_in0.
Select mux mode: ALT7 mux port: RX of instance: sci_flx2.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB7.
00
01
Low (50 MHz)
Medium (100 MHz)
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IOMUXC_PTB7 field descriptions (continued)
Field
Description
10
11
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB7.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB7.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB7.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB7.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB7.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB7.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB7.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB7.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB7.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.31 Software MUX Pad Control Register 30 (IOMUXC_PTB8)
Address: 4004_8000h base + 78h offset = 4004_8078h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
1
0
4
PUS
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTB8 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB8.
NOTE: Pad PTB8 is involved in Daisy Chain.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT for mode ALT1.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT for mode ALT5.
000
001
011
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[30] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[0] of instance: flextimer1.
Select mux mode: ALT3 mux port: QD_PHA of instance: flextimer1.
Select mux mode: ALT5 mux port: DE of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[24] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB8.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB8.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB8.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB8.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTB8 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB8.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB8.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB8.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB8.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB8.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB8.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.32 Software MUX Pad Control Register 31 (IOMUXC_PTB9)
Address: 4004_8000h base + 7Ch offset = 4004_807Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTB9 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 4 IOMUX modes to be used for pad: PTB9.
NOTE: Pad PTB9 is involved in Daisy Chain.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT for mode ALT1.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT for mode ALT3.
000
001
011
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[31] of instance: rgpioc.
Select mux mode: ALT1 mux port: CH[1] of instance: flextimer1.
Select mux mode: ALT3 mux port: QD_PHB of instance: flextimer1.
Select mux mode: ALT7 mux port: DATA_OUT[25] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB9.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB9.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB9.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB9.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB9.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB9.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTB9 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB9.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB9.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB9.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB9.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.33 Software MUX Pad Control Register 32 (IOMUXC_PTB10)
Address: 4004_8000h base + 80h offset = 4004_8080h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTB10 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTB10.
NOTE: Pad PTB10 is involved in Daisy Chain.
• Config Register IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT for mode ALT7.
• Config Register IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT for mode ALT5.
000
001
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[32] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX of instance: sci_flx0.
Select mux mode: ALT4 mux port: TCON[4] of instance: tcon0.
Select mux mode: ALT5 mux port: DE of instance: video_in0.
CKO1
Select mux mode: ALT7 mux port: ENET_TS_CLKIN of instance: ccm.
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IOMUXC_PTB10 field descriptions (continued)
Field
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
Speed Field. Select one of the following values for pad: PTB10.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB10.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB10.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB10.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB10.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB10.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB10.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB10.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB10.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTB10 field descriptions (continued)
Field
Description
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB10.
0
1
Disabled
Enabled
5.2.5.34 Software MUX Pad Control Register 33 (IOMUXC_PTB11)
Address: 4004_8000h base + 84h offset = 4004_8084h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTB11 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTB11.
NOTE: Pad PTB11 is involved in Daisy Chain.
• Config Register IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT for mode
ALT7.
000
001
100
101
110
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[33] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX of instance: sci_flx0.
Select mux mode: ALT4 mux port: TCON[5] of instance: tcon0.
Select mux mode: ALT5 mux port: SNVS_ALARM_OUT_B of instance: snvs_lp_wrapper.
CKO2
Select mux mode: ALT7 mux port: MAC0_TMR0 of instance: enet_swiahb.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB11.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTB11.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTB11 field descriptions (continued)
Field
Description
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB11.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB11.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB11.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB11.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB11.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB11.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB11.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB11.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.35 Software MUX Pad Control Register 34 (IOMUXC_PTB12)
Address: 4004_8000h base + 88h offset = 4004_8088h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTB12 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTB12.
NOTE: Pad PTB12 is involved in Daisy Chain.
• Config Register IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT for mode
ALT7.
000
001
011
100
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[34] of instance: rgpioc.
Select mux mode: ALT1 mux port: RTS of instance: sci_flx0.
Select mux mode: ALT3 mux port: CS5 of instance: dspi0.
Select mux mode: ALT4 mux port: TCON[6] of instance: tcon0.
Select mux mode: ALT5 mux port: FB_AD[1] of instance: platform.
Select mux mode: ALT7 mux port: MAC0_TMR1 of instance: enet_swiahb.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB12.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB12.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB12.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB12.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTB12 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB12.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB12.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB12.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB12.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB12.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB12.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.36 Software MUX Pad Control Register 35 (IOMUXC_PTB13)
Address: 4004_8000h base + 8Ch offset = 4004_808Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTB13 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTB13.
000
001
011
100
101
110
Select mux mode: ALT0 mux port: GPIO[35] of instance: rgpioc.
Select mux mode: ALT1 mux port: CTS of instance: sci_flx0.
Select mux mode: ALT3 mux port: CS4 of instance: dspi0.
Select mux mode: ALT4 mux port: TCON[7] of instance: tcon0.
Select mux mode: ALT5 mux port: FB_AD[0] of instance: platform.
Select mux mode: ALT6 mux port: TRACECTL of instance: platform.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB13.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB13.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB13.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB13.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB13.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB13.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB13.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Table continues on the next page...
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IOMUXC_PTB13 field descriptions (continued)
Field
Description
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB13.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB13.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB13.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.37 Software MUX Pad Control Register 36 (IOMUXC_PTB14)
Address: 4004_8000h base + 90h offset = 4004_8090h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB14 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB14.
NOTE: Pad PTB14 is involved in Daisy Chain.
• Config Register IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT for mode ALT2.
000
001
010
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[36] of instance: rgpioc.
Select mux mode: ALT1 mux port: RXD of instance: can0.
Select mux mode: ALT2 mux port: SCL of instance: i2c0.
Select mux mode: ALT4 mux port: TCON[8] of instance: tcon0.
Select mux mode: ALT7 mux port: DATA_OUT[1] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB14.
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IOMUXC_PTB14 field descriptions (continued)
Field
Description
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB14.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB14.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB14.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB14.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB14.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB14.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB14.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB14.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB14.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.38 Software MUX Pad Control Register 37 (IOMUXC_PTB15)
Address: 4004_8000h base + 94h offset = 4004_8094h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTB15 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB15.
NOTE: Pad PTB15 is involved in Daisy Chain.
• Config Register IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT for mode ALT7.
000
001
010
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[37] of instance: rgpioc.
Select mux mode: ALT1 mux port: TXD of instance: can0.
Select mux mode: ALT2 mux port: SDA of instance: i2c0.
Select mux mode: ALT4 mux port: TCON[9] of instance: tcon0.
Select mux mode: ALT7 mux port: PIX_CLK of instance: video_in0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB15.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB15.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB15.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB15.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB15.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTB15 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB15.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB15.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB15.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB15.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB15.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.39 Software MUX Pad Control Register 38 (IOMUXC_PTB16)
Address: 4004_8000h base + 98h offset = 4004_8098h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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IOMUXC_PTB16 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 4 IOMUX modes to be used for pad: PTB16.
NOTE: Pad PTB16 is involved in Daisy Chain.
• Config Register IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT for mode ALT2.
000
001
010
100
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[38] of instance: rgpioc.
Select mux mode: ALT1 mux port: RXD of instance: can1.
Select mux mode: ALT2 mux port: SCL of instance: i2c1.
Select mux mode: ALT4 mux port: TCON[10] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB16.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB16.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB16.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB16.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB16.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB16.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB16.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTB16 field descriptions (continued)
Field
Description
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB16.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB16.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB16.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.40 Software MUX Pad Control Register 39 (IOMUXC_PTB17)
Address: 4004_8000h base + 9Ch offset = 4004_809Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB17 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 4 IOMUX modes to be used for pad: PTB17.
NOTE: Pad PTB17 is involved in Daisy Chain.
• Config Register IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT for mode ALT2.
000
001
010
100
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[39] of instance: rgpioc.
Select mux mode: ALT1 mux port: TXD of instance: can1.
Select mux mode: ALT2 mux port: SDA of instance: i2c1.
Select mux mode: ALT4 mux port: TCON[11] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB17.
00
Low (50 MHz)
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IOMUXC_PTB17 field descriptions (continued)
Field
Description
01
10
11
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB17.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB17.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB17.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB17.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB17.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB17.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB17.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB17.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB17.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.41 Software MUX Pad Control Register 40 (IOMUXC_PTB18)
Address: 4004_8000h base + A0h offset = 4004_80A0h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
1
0
IOMUXC_PTB18 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB18.
NOTE: Pad PTB18 is involved in Daisy Chain.
• Config Register IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT for mode ALT2.
000
001
010
100
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[40] of instance: rgpioc.
Select mux mode: ALT1 mux port: CS1 of instance: dspi0.
Select mux mode: ALT2 mux port: EXT_AUDIO_MCLK of instance: ccm.
CKO1
Select mux mode: ALT6 mux port: DATA[9] of instance: video_in0.
Reserved
This field is reserved.
Speed Field. Select one of the following values for pad: PTB18.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB18.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB18.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB18.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB18.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTB18 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB18.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB18.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB18.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB18.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB18.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.42 Software MUX Pad Control Register 41 (IOMUXC_PTB19)
Address: 4004_8000h base + A4h offset = 4004_80A4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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IOMUXC_PTB19 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 4 IOMUX modes to be used for pad: PTB19.
000
001
110
111
Select mux mode: ALT0 mux port: GPIO[41] of instance: rgpioc.
Select mux mode: ALT1 mux port: CS0 of instance: dspi0.
Select mux mode: ALT6 mux port: DATA[10] of instance: video_in0.
Reserved
This field is reserved.
Speed Field. Select one of the following values for pad: PTB19.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB19.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB19.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB19.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB19.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB19.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB19.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Table continues on the next page...
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IOMUXC_PTB19 field descriptions (continued)
Field
Description
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB19.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB19.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB19.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.43 Software MUX Pad Control Register 42 (IOMUXC_PTB20)
Address: 4004_8000h base + A8h offset = 4004_80A8h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB20 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB20.
000
001
100
110
111
Select mux mode: ALT0 mux port: GPIO[42] of instance: rgpioc.
Select mux mode: ALT1 mux port: SIN of instance: dspi0.
Select mux mode: ALT4 mux port: LCD42 of instance: lcd_64f6b.
Select mux mode: ALT6 mux port: DATA[11] of instance: video_in0.
Reserved
This field is reserved.
Speed Field. Select one of the following values for pad: PTB20.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
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IOMUXC_PTB20 field descriptions (continued)
Field
Description
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB20.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB20.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB20.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB20.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB20.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB20.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB20.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB20.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB20.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.44 Software MUX Pad Control Register 43 (IOMUXC_PTB21)
Address: 4004_8000h base + ACh offset = 4004_80ACh
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTB21 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB21.
000
001
100
110
111
Select mux mode: ALT0 mux port: GPIO[43] of instance: rgpioc.
Select mux mode: ALT1 mux port: SOUT of instance: dspi0.
Select mux mode: ALT4 mux port: LCD43 of instance: lcd_64f6b.
Select mux mode: ALT6 mux port: DATA[12] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[1] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB21.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB21.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB21.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB21.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB21.
0
1
0
1
0
1
000
001
010
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
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IOMUXC_PTB21 field descriptions (continued)
Field
Description
011
100
101
110
111
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB21.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB21.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB21.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB21.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB21.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.45 Software MUX Pad Control Register 44 (IOMUXC_PTB22)
Address: 4004_8000h base + B0h offset = 4004_80B0h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB22 field descriptions
Field
31–23
Reserved
Description
This field is reserved.
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IOMUXC_PTB22 field descriptions (continued)
Field
22–20
MUX_MODE
Description
MUX Mode Select Field. Select 1 of 3 IOMUX modes to be used for pad: PTB22.
NOTE: Pad PTB22 is involved in Daisy Chain.
• Config Register IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT for mode ALT5.
000
001
101
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[44] of instance: rgpioc.
Select mux mode: ALT1 mux port: SCK of instance: dspi0.
Select mux mode: ALT5 mux port: FID of instance: video_in0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB22.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB22.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB22.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB22.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB22.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB22.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB22.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
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IOMUXC_PTB22 field descriptions (continued)
Field
Description
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB22.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB22.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB22.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.46 Software MUX Pad Control Register 45 (IOMUXC_PTC0)
Address: 4004_8000h base + B4h offset = 4004_80B4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC0 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC0.
NOTE: Pad PTC0 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT for mode ALT4.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_SRC_IPP_BOOT_CFG_18_SELECT_INPUT for mode ALT7.
000
001
010
011
100
101
110
111
19–14
Reserved
Select mux mode: ALT0 mux port: GPIO[45] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_MDC/MII0_MDC of instance: enet_swiahb.
Select mux mode: ALT2 mux port: CH[0] of instance: flextimer1.
Select mux mode: ALT3 mux port: CS3 of instance: dspi0.
Select mux mode: ALT4 mux port: SCKT of instance: esai.
Select mux mode: ALT5 mux port: CLK of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[0] of instance: video_in0.
Select mux mode: ALT7 mux port: RCON18 of instance: src.
This field is reserved.
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IOMUXC_PTC0 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTC0.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC0.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC0.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC0.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC0.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC0.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC0.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC0.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC0.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC0.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTC0 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.47 Software MUX Pad Control Register 46 (IOMUXC_PTC1)
Address: 4004_8000h base + B8h offset = 4004_80B8h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC1 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC1.
NOTE: Pad PTC1 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT for mode ALT4.
• Config Register IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_SRC_IPP_BOOT_CFG_19_SELECT_INPUT for mode ALT7.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[46] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_MDIO/MII0_MDIO of instance: enet_swiahb.
Select mux mode: ALT2 mux port: CH[1] of instance: flextimer1.
Select mux mode: ALT3 mux port: CS2 of instance: dspi0.
Select mux mode: ALT4 mux port: FST of instance: esai.
Select mux mode: ALT5 mux port: CMD of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[1] of instance: video_in0.
Select mux mode: ALT7 mux port: RCON19 of instance: src.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC1.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTC1.
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IOMUXC_PTC1 field descriptions (continued)
Field
Description
0
1
Slow Slew Rate
Fast Slew Rate
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC1.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC1.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC1.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC1.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC1.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC1.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC1.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC1.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.48 Software MUX Pad Control Register 47 (IOMUXC_PTC2)
Address: 4004_8000h base + BCh offset = 4004_80BCh
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
1
1
7
6
5
DSE
0
0
1
1
0
4
PUS
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
1
0
IOMUXC_PTC2 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC2.
NOTE: Pad PTC2 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT for mode ALT4.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT2.
• Config Register IOMUXC_SRC_IPP_BOOT_CFG_20_SELECT_INPUT for mode ALT7.
000
001
010
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[47] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_RX_EN of instance: enet_swiahb.
Select mux mode: ALT2 mux port: TX of instance: sci_flx1.
Select mux mode: ALT4 mux port: SDO0 of instance: esai.
Select mux mode: ALT5 mux port: DAT0 of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[2] of instance: video_in0.
Select mux mode: ALT7 mux port: RCON20 of instance: src.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC2.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC2.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC2.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC2.
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
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IOMUXC_PTC2 field descriptions (continued)
Field
Description
0
1
CMOS input
Schmitt trigger input
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC2.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC2.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC2.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC2.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC2.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC2.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.49 Software MUX Pad Control Register 48 (IOMUXC_PTC3)
Address: 4004_8000h base + C0h offset = 4004_80C0h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTC3 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC3.
NOTE: Pad PTC3 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT for mode ALT4.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT2.
000
001
010
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[48] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_RXD[1]//MII0_RXD[1] of instance: enet_swiahb.
Select mux mode: ALT2 mux port: RX of instance: sci_flx1.
Select mux mode: ALT4 mux port: SDO1 of instance: esai.
Select mux mode: ALT5 mux port: DAT1 of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[3] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[18] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC3.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC3.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC3.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC3.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC3.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC3.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
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IOMUXC_PTC3 field descriptions (continued)
Field
Description
10
11
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC3.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC3.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC3.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC3.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.50 Software MUX Pad Control Register 49 (IOMUXC_PTC4)
Address: 4004_8000h base + C4h offset = 4004_80C4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC4 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC4.
NOTE: Pad PTC4 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT for mode ALT4.
000
001
010
011
100
Select mux mode: ALT0 mux port: GPIO[49] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_RXD[0]/MII0_RXD[0] of instance: enet_swiahb.
Select mux mode: ALT2 mux port: RTS of instance: sci_flx1.
Select mux mode: ALT3 mux port: CS1 of instance: dspi1.
Select mux mode: ALT4 mux port: SDO2 of instance: esai.
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IOMUXC_PTC4 field descriptions (continued)
Field
Description
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT5 mux port: DAT2 of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[4] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[19] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC4.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC4.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC4.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC4.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC4.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC4.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC4.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC4.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
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IOMUXC_PTC4 field descriptions (continued)
Field
Description
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC4.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC4.
0
1
0
1
Disabled
Enabled
Disabled
Enabled
5.2.5.51 Software MUX Pad Control Register 50 (IOMUXC_PTC5)
Address: 4004_8000h base + C8h offset = 4004_80C8h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC5 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC5.
NOTE: Pad PTC5 is involved in Daisy Chain.
• Config Register IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT for mode ALT4.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT for mode ALT2.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[50] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_RXER/MII0_RXER of instance: enet_swiahb.
Select mux mode: ALT2 mux port: CTS of instance: sci_flx1.
Select mux mode: ALT3 mux port: CS0 of instance: dspi1.
Select mux mode: ALT4 mux port: SDO3 of instance: esai.
Select mux mode: ALT5 mux port: DAT3 of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[5] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[10] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC5.
00
01
Low (50 MHz)
Medium (100 MHz)
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IOMUXC_PTC5 field descriptions (continued)
Field
Description
10
11
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC5.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC5.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC5.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC5.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC5.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC5.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC5.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC5.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC5.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.52 Software MUX Pad Control Register 51 (IOMUXC_PTC6)
Address: 4004_8000h base + CCh offset = 4004_80CCh
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
1
0
4
PUS
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTC6 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC6.
NOTE: Pad PTC6 is involved in Daisy Chain.
• Config Register IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT for mode ALT4.
000
001
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[51] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_TXD[1]/MII0_TXD[1] of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SIN of instance: dspi1.
Select mux mode: ALT4 mux port: SDI0 of instance: esai.
Select mux mode: ALT5 mux port: WP of instance: esdhc0.
Select mux mode: ALT6 mux port: DATA[6] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[11] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC6.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC6.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC6.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC6.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTC6 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC6.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC6.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC6.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC6.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC6.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC6.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.53 Software MUX Pad Control Register 52 (IOMUXC_PTC7)
Address: 4004_8000h base + D0h offset = 4004_80D0h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTC7 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTC7.
NOTE: Pad PTC7 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT for mode ALT4.
000
001
011
100
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[52] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_TXD[0]/MII0_TXD[0] of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SOUT of instance: dspi1.
Select mux mode: ALT4 mux port: SDI1 of instance: esai.
Select mux mode: ALT6 mux port: DATA[7] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[2] of instance: tcon0.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC7.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC7.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC7.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC7.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC7.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC7.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTC7 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC7.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC7.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC7.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC7.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.54 Software MUX Pad Control Register 53 (IOMUXC_PTC8)
Address: 4004_8000h base + D4h offset = 4004_80D4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTC8 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC8.
NOTE: Pad PTC8 is involved in Daisy Chain.
• Config Register IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT for mode ALT3.
000
001
011
110
111
19–14
Reserved
Select mux mode: ALT0 mux port: GPIO[53] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII0_TXEN/MII0_TXEN of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SCK of instance: dspi1.
Select mux mode: ALT6 mux port: DATA[8] of instance: video_in0.
Select mux mode: ALT7 mux port: DATA_OUT[3] of instance: tcon0.
This field is reserved.
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IOMUXC_PTC8 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTC8.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC8.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC8.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC8.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC8.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC8.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC8.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC8.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC8.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC8.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTC8 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.55 Software MUX Pad Control Register 54 (IOMUXC_PTC9)
Address: 4004_8000h base + D8h offset = 4004_80D8h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC9 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC9.
NOTE: Pad PTC9 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT for mode ALT6.
000
001
011
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[54] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_MDC of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SCKT of instance: esai.
Select mux mode: ALT6 mux port: MLBCLK of instance: mlb_top.
Select mux mode: ALT7 mux port: debug_out[0] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC9.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC9.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC9.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTC9 field descriptions (continued)
Field
Description
0
1
Output is CMOS
Output is open drain
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC9.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC9.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC9.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC9.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC9.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC9.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC9.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.56 Software MUX Pad Control Register 55 (IOMUXC_PTC10)
Address: 4004_8000h base + DCh offset = 4004_80DCh
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTC10 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC10.
NOTE: Pad PTC10 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT for mode ALT6.
000
001
011
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[55] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_MDIO of instance: enet_swiahb.
Select mux mode: ALT3 mux port: FST of instance: esai.
Select mux mode: ALT6 mux port: MLBSIGNAL of instance: mlb_top.
Select mux mode: ALT7 mux port: debug_out[1] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC10.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC10.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC10.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC10.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC10.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTC10 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC10.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC10.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC10.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC10.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC10.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.57 Software MUX Pad Control Register 56 (IOMUXC_PTC11)
Address: 4004_8000h base + E0h offset = 4004_80E0h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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IOMUXC_PTC11 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC11.
NOTE: Pad PTC11 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT for mode ALT6.
000
001
011
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[56] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_CRS_DV of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SDO0 of instance: esai.
Select mux mode: ALT6 mux port: MLBDATA of instance: mlb_top.
Select mux mode: ALT7 mux port: debug_out[2] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC11.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC11.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC11.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC11.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC11.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC11.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTC11 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC11.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC11.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC11.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC11.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.58 Software MUX Pad Control Register 57 (IOMUXC_PTC12)
Address: 4004_8000h base + E4h offset = 4004_80E4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTC12 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC12.
NOTE: Pad PTC12 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT for mode ALT5.
000
001
011
101
111
19–14
Reserved
Select mux mode: ALT0 mux port: GPIO[57] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_RXD[1] of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SDO1 of instance: esai.
Select mux mode: ALT5 mux port: TX_BCLK of instance: sai2.
Select mux mode: ALT7 mux port: debug_out[3] of instance: viu_mux.
This field is reserved.
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IOMUXC_PTC12 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTC12.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC12.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC12.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC12.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC12.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC12.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC12.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC12.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC12.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC12.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Table continues on the next page...
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IOMUXC_PTC12 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.59 Software MUX Pad Control Register 58 (IOMUXC_PTC13)
Address: 4004_8000h base + E8h offset = 4004_80E8h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC13 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC13.
NOTE: Pad PTC13 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT for mode ALT5.
000
001
011
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[58] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_RXD[0] of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SDO2 of instance: esai.
Select mux mode: ALT5 mux port: RX_BCLK of instance: sai2.
Select mux mode: ALT7 mux port: debug_out[4] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC13.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC13.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC13.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTC13 field descriptions (continued)
Field
Description
0
1
Output is CMOS
Output is open drain
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC13.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC13.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC13.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC13.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC13.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC13.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC13.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.60 Software MUX Pad Control Register 59 (IOMUXC_PTC14)
Address: 4004_8000h base + ECh offset = 4004_80ECh
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTC14 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC14.
NOTE: Pad PTC14 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT for mode ALT5.
000
001
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[59] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_RXER of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SDO3 of instance: esai.
Select mux mode: ALT4 mux port: TX of instance: sci_flx5.
Select mux mode: ALT5 mux port: RX_DATA of instance: sai2.
Select mux mode: ALT6 mux port: ADC0SE6 of instance: adc0_da.
Select mux mode: ALT7 mux port: debug_out[5] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC14.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC14.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC14.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC14.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
Table continues on the next page...
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IOMUXC_PTC14 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC14.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC14.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC14.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC14.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC14.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC14.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.61 Software MUX Pad Control Register 60 (IOMUXC_PTC15)
Address: 4004_8000h base + F0h offset = 4004_80F0h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTC15 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC15.
NOTE: Pad PTC15 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT for mode ALT3.
000
001
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[60] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_TXD[1] of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SDI0 of instance: esai.
Select mux mode: ALT4 mux port: RX of instance: sci_flx5.
Select mux mode: ALT5 mux port: TX_DATA of instance: sai2.
Select mux mode: ALT6 mux port: ADC0SE7 of instance: adc0_da.
Select mux mode: ALT7 mux port: debug_out[6] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC15.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC15.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC15.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC15.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC15.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC15.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
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IOMUXC_PTC15 field descriptions (continued)
Field
Description
10
11
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC15.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC15.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC15.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC15.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.62 Software MUX Pad Control Register 61 (IOMUXC_PTC16)
Address: 4004_8000h base + F4h offset = 4004_80F4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC16 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC16.
NOTE: Pad PTC16 is involved in Daisy Chain.
• Config Register IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT for mode ALT3.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT for mode ALT5.
000
001
011
100
101
Select mux mode: ALT0 mux port: GPIO[61] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_TXD[0] of instance: enet_swiahb.
Select mux mode: ALT3 mux port: SDI1 of instance: esai.
Select mux mode: ALT4 mux port: RTS of instance: sci_flx5.
Select mux mode: ALT5 mux port: RX_SYNC of instance: sai2.
Table continues on the next page...
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IOMUXC_PTC16 field descriptions (continued)
Field
Description
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT6 mux port: ADC1SE6 of instance: adc1_da.
Select mux mode: ALT7 mux port: debug_out[7] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC16.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC16.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC16.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC16.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC16.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC16.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC16.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC16.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC16.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
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IOMUXC_PTC16 field descriptions (continued)
Field
Description
0
1
0
IBE
Disabled
Enabled
Input Buffer Enable Field. Select one of the following values for pad: PTC16.
0
1
Disabled
Enabled
5.2.5.63 Software MUX Pad Control Register 62 (IOMUXC_PTC17)
Address: 4004_8000h base + F8h offset = 4004_80F8h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC17 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC17.
NOTE: Pad PTC17 is involved in Daisy Chain.
• Config Register IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT for mode ALT5.
000
001
011
100
101
110
111
19–14
Reserved
13–12
SPEED
11
SRE
Select mux mode: ALT0 mux port: GPIO[62] of instance: rgpioc.
Select mux mode: ALT1 mux port: RMII1_TXEN of instance: enet_swiahb.
Select mux mode: ALT3 mux port: ADC1SE7 of instance: adc1_da.
Select mux mode: ALT4 mux port: CTS of instance: sci_flx5.
Select mux mode: ALT5 mux port: TX_SYNC of instance: sai2.
Select mux mode: ALT6 mux port: USB1_SOF_PULSE of instance: usb.
Select mux mode: ALT7 mux port: debug_out[8] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC17.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
Slew Rate Field. Select one of the following values for pad: PTC17.
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IOMUXC_PTC17 field descriptions (continued)
Field
Description
0
1
Slow Slew Rate
Fast Slew Rate
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC17.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC17.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC17.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC17.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC17.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC17.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC17.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC17.
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.64 Software MUX Pad Control Register 63 (IOMUXC_PTD31)
Address: 4004_8000h base + FCh offset = 4004_80FCh
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTD31 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD31.
000
001
010
100
101
111
Select mux mode: ALT0 mux port: GPIO[63] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[31] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[15] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: CH[0] of instance: flextimer3.
Select mux mode: ALT5 mux port: CS1 of instance: dspi2.
Select mux mode: ALT7 mux port: debug_out[9] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD31.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD31.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD31.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD31.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD31.
0
1
0
1
0
1
000
001
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
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IOMUXC_PTD31 field descriptions (continued)
Field
Description
010
011
100
101
110
111
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD31.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD31.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD31.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD31.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD31.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.65 Software MUX Pad Control Register 64 (IOMUXC_PTD30)
Address: 4004_8000h base + 100h offset = 4004_8100h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTD30 field descriptions
Field
31–23
Reserved
Description
This field is reserved.
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IOMUXC_PTD30 field descriptions (continued)
Field
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD30.
000
001
010
100
101
111
Select mux mode: ALT0 mux port: GPIO[64] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[30] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[14] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: CH[1] of instance: flextimer3.
Select mux mode: ALT5 mux port: CS0 of instance: dspi2.
Select mux mode: ALT7 mux port: debug_out[10] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD30.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD30.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD30.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD30.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD30.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD30.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD30.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
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IOMUXC_PTD30 field descriptions (continued)
Field
Description
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD30.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD30.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD30.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.66 Software MUX Pad Control Register 65 (IOMUXC_PTD29)
Address: 4004_8000h base + 104h offset = 4004_8104h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD29 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD29.
000
001
010
100
101
111
Select mux mode: ALT0 mux port: GPIO[65] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[29] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[13] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: CH[2] of instance: flextimer3.
Select mux mode: ALT5 mux port: SIN of instance: dspi2.
Select mux mode: ALT7 mux port: debug_out[11] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD29.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
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IOMUXC_PTD29 field descriptions (continued)
Field
Description
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD29.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD29.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD29.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD29.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD29.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD29.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD29.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD29.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD29.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.67 Software MUX Pad Control Register 66 (IOMUXC_PTD28)
Address: 4004_8000h base + 108h offset = 4004_8108h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTD28 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD28.
NOTE: Pad PTD28 is involved in Daisy Chain.
• Config Register IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT for mode ALT3.
000
001
010
011
100
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[66] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[28] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[12] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: SCL of instance: i2c2.
Select mux mode: ALT4 mux port: CH[3] of instance: flextimer3.
Select mux mode: ALT5 mux port: SOUT of instance: dspi2.
Select mux mode: ALT7 mux port: debug_out[12] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD28.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD28.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD28.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD28.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTD28 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD28.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD28.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD28.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD28.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD28.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD28.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.68 Software MUX Pad Control Register 67 (IOMUXC_PTD27)
Address: 4004_8000h base + 10Ch offset = 4004_810Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTD27 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD27.
NOTE: Pad PTD27 is involved in Daisy Chain.
• Config Register IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT for mode ALT3.
000
001
010
011
100
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[67] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[27] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[11] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: SDA of instance: i2c2.
Select mux mode: ALT4 mux port: CH[4] of instance: flextimer3.
Select mux mode: ALT5 mux port: SCK of instance: dspi2.
Select mux mode: ALT7 mux port: debug_out[13] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD27.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD27.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD27.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD27.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD27.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD27.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
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IOMUXC_PTD27 field descriptions (continued)
Field
Description
10
11
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD27.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD27.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD27.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD27.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.69 Software MUX Pad Control Register 68 (IOMUXC_PTD26)
Address: 4004_8000h base + 110h offset = 4004_8110h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD26 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD26.
000
001
010
100
101
111
Select mux mode: ALT0 mux port: GPIO[68] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[26] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[10] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: CH[5] of instance: flextimer3.
Select mux mode: ALT5 mux port: WP of instance: esdhc1.
Select mux mode: ALT7 mux port: debug_out[14] of instance: viu_mux.
This field is reserved.
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IOMUXC_PTD26 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTD26.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD26.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD26.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD26.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD26.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD26.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD26.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD26.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD26.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD26.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTD26 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.70 Software MUX Pad Control Register 69 (IOMUXC_PTD25)
Address: 4004_8000h base + 114h offset = 4004_8114h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD25 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD25.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[69] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[25] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[9] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: CH[6] of instance: flextimer3.
Select mux mode: ALT7 mux port: debug_out[15] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD25.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD25.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD25.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD25.
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
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IOMUXC_PTD25 field descriptions (continued)
Field
Description
0
1
CMOS input
Schmitt trigger input
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD25.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD25.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD25.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD25.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD25.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD25.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.71 Software MUX Pad Control Register 70 (IOMUXC_PTD24)
Address: 4004_8000h base + 118h offset = 4004_8118h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTD24 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD24.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[70] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[24] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[8] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: CH[7] of instance: flextimer3.
Select mux mode: ALT7 mux port: debug_out[16] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD24.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD24.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD24.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD24.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD24.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD24.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD24.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTD24 field descriptions (continued)
Field
Description
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD24.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD24.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD24.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.72 Software MUX Pad Control Register 71 (IOMUXC_PTD23)
Address: 4004_8000h base + 11Ch offset = 4004_811Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD23 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTD23.
NOTE: Pad PTD23 is involved in Daisy Chain.
• Config Register IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT for mode
ALT4.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT6.
000
001
010
011
100
101
Select mux mode: ALT0 mux port: GPIO[71] of instance: rgpioc. Also, RXDATA[3] for MAC0 is
enabled in this mux mode so ensure obe is disabled if this pin is used for MAC0-MII instead of
GPIO.
Select mux mode: ALT1 mux port: FB_AD[23] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[7] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: CH[0] of instance: flextimer2.
Select mux mode: ALT4 mux port: MAC0_TMR0 of instance: enet_swiahb.
Select mux mode: ALT5 mux port: DAT4 of instance: esdhc0.
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IOMUXC_PTD23 field descriptions (continued)
Field
Description
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT6 mux port: TX of instance: sci_flx2.
Select mux mode: ALT7 mux port: DATA_OUT[21] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD23.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD23.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD23.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD23.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD23.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD23.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD23.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD23.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD23.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
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IOMUXC_PTD23 field descriptions (continued)
Field
Description
0
1
0
IBE
Disabled
Enabled
Input Buffer Enable Field. Select one of the following values for pad: PTD23.
0
1
Disabled
Enabled
5.2.5.73 Software MUX Pad Control Register 72 (IOMUXC_PTD22)
Address: 4004_8000h base + 120h offset = 4004_8120h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD22 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTD22.
NOTE: Pad PTD22 is involved in Daisy Chain.
• Config Register IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT for mode
ALT4.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT6.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[72] of instance: rgpioc. Also, RXDATA[2] for MAC0 is
enabled in this mux mode so ensure obe is disabled if this pin is used for MAC0-MII instead of
GPIO.
Select mux mode: ALT1 mux port: FB_AD[22] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[6] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: CH[1] of instance: flextimer2.
Select mux mode: ALT4 mux port: MAC0_TMR1 of instance: enet_swiahb.
Select mux mode: ALT5 mux port: DAT5 of instance: esdhc0.
Select mux mode: ALT6 mux port: RX of instance: sci_flx2.
Select mux mode: ALT7 mux port: DATA_OUT[22] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD22.
00
01
Low (50 MHz)
Medium (100 MHz)
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IOMUXC_PTD22 field descriptions (continued)
Field
Description
10
11
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD22.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD22.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD22.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD22.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD22.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD22.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD22.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD22.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD22.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.74 Software MUX Pad Control Register 73 (IOMUXC_PTD21)
Address: 4004_8000h base + 124h offset = 4004_8124h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTD21 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD21.
000
001
010
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[73] of instance: rgpioc. Also, CRS for MAC0 is enabled in
this mux mode so ensure obe is disabled if this pin is used for MAC0-MII instead of GPIO.
Select mux mode: ALT1 mux port: FB_AD[21] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[5] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: MAC0_TMR2 of instance: enet_swiahb.
Select mux mode: ALT5 mux port: DAT6 of instance: esdhc0.
Select mux mode: ALT6 mux port: RTS of instance: sci_flx2.
Select mux mode: ALT7 mux port: DATA_OUT[23] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD21.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD21.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD21.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD21.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD21.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
Table continues on the next page...
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IOMUXC_PTD21 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD21.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD21.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD21.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD21.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD21.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.75 Software MUX Pad Control Register 74 (IOMUXC_PTD20)
Address: 4004_8000h base + 128h offset = 4004_8128h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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IOMUXC_PTD20 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD20.
NOTE: Pad PTD20 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT for mode ALT6.
000
001
010
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[74] of instance: rgpioc. Also, COL for MAC0 is enabled in
this mux mode so ensure obe is disabled if this pin is used for MAC0-MII instead of GPIO.
Select mux mode: ALT1 mux port: FB_AD[20] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[4] of instance: nfc_mlc.
Select mux mode: ALT4 mux port: MAC0_TMR3 of instance: enet_swiahb.
Select mux mode: ALT5 mux port: DAT7 of instance: esdhc0.
Select mux mode: ALT6 mux port: CTS of instance: sci_flx2.
Select mux mode: ALT7 mux port: DATA_OUT[18] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD20.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD20.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD20.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD20.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD20.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD20.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
Table continues on the next page...
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IOMUXC_PTD20 field descriptions (continued)
Field
Description
10
11
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD20.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD20.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD20.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD20.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.76 Software MUX Pad Control Register 75 (IOMUXC_PTD19)
Address: 4004_8000h base + 12Ch offset = 4004_812Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD19 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD19.
NOTE: Pad PTD19 is involved in Daisy Chain.
• Config Register IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT for mode ALT4.
000
001
010
011
100
Select mux mode: ALT0 mux port: GPIO[75] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[19] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[3] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: SCKR of instance: esai.
Select mux mode: ALT4 mux port: SCL of instance: i2c0.
Table continues on the next page...
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IOMUXC_PTD19 field descriptions (continued)
Field
Description
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT5 mux port: QD_PHA of instance: flextimer2.
Select mux mode: ALT6 mux port: TXDATA[3] for MAC0-MII
Select mux mode: ALT7 mux port: DATA_OUT[19] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD19.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD19.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD19.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD19.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD19.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD19.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD19.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD19.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Table continues on the next page...
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IOMUXC_PTD19 field descriptions (continued)
Field
Description
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD19.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD19.
0
1
0
1
Disabled
Enabled
Disabled
Enabled
5.2.5.77 Software MUX Pad Control Register 76 (IOMUXC_PTD18)
Address: 4004_8000h base + 130h offset = 4004_8130h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD18 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD18.
NOTE: Pad PTD18 is involved in Daisy Chain.
• Config Register IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT for mode ALT4.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[76] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[18] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[2] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: FSR of instance: esai.
Select mux mode: ALT4 mux port: SDA of instance: i2c0.
Select mux mode: ALT5 mux port: QD_PHB of instance: flextimer2.
Select mux mode: ALT6 mux port: txdata[2] for MAC0-MII
Select mux mode: ALT7 mux port: DATA_OUT[10] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD18.
00
01
Low (50 MHz)
Medium (100 MHz)
Table continues on the next page...
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IOMUXC_PTD18 field descriptions (continued)
Field
Description
10
11
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD18.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD18.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD18.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD18.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD18.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD18.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD18.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD18.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD18.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.78 Software MUX Pad Control Register 77 (IOMUXC_PTD17)
Address: 4004_8000h base + 134h offset = 4004_8134h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTD17 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD17.
NOTE: Pad PTD17 is involved in Daisy Chain.
• Config Register IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT for mode ALT4.
000
001
010
011
100
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[77] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[17] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[1] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: HCKR of instance: esai.
Select mux mode: ALT4 mux port: SCL of instance: i2c1.
Select mux mode: ALT6 mux port: TXERR of MAC0-MII
Select mux mode: ALT7 mux port: DATA_OUT[11] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD17.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD17.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD17.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD17.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
Table continues on the next page...
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IOMUXC_PTD17 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD17.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD17.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD17.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD17.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD17.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD17.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.79 Software MUX Pad Control Register 78 (IOMUXC_PTD16)
Address: 4004_8000h base + 138h offset = 4004_8138h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTD16 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD16.
NOTE: Pad PTD16 is involved in Daisy Chain.
• Config Register IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT for mode ALT4.
000
001
010
011
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[78] of instance: rgpioc.
Select mux mode: ALT1 mux port: FB_AD[16] of instance: platform.
Select mux mode: ALT2 mux port: NF_IO[0] of instance: nfc_mlc.
Select mux mode: ALT3 mux port: HCKT of instance: esai.
Select mux mode: ALT4 mux port: SDA of instance: i2c1.
Select mux mode: ALT7 mux port: DATA_OUT[12] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD16.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD16.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD16.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD16.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD16.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD16.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTD16 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD16.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD16.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD16.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD16.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.80 Software MUX Pad Control Register 79 (IOMUXC_PTD0)
Address: 4004_8000h base + 13Ch offset = 4004_813Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTD0 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD0.
NOTE: Pad PTD0 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT2.
000
001
010
100
101
111
19–14
Reserved
Select mux mode: ALT0 mux port: GPIO[79] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSCK_A of instance: quadspi0.
Select mux mode: ALT2 mux port: TX of instance: sci_flx2.
Select mux mode: ALT4 mux port: FB_AD[15] of instance: platform.
Select mux mode: ALT5 mux port: EXTCLK of instance: spdif.
Select mux mode: ALT7 mux port: debug_out[17] of instance: viu_mux.
This field is reserved.
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IOMUXC_PTD0 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTD0.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD0.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD0.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD0.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD0.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD0.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD0.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD0.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD0.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD0.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTD0 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.81 Software MUX Pad Control Register 80 (IOMUXC_PTD1)
Address: 4004_8000h base + 140h offset = 4004_8140h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD1 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD1.
NOTE: Pad PTD1 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT2.
000
001
010
100
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[80] of instance: rgpioc.
Select mux mode: ALT1 mux port: QPCS0_A of instance: quadspi0.
Select mux mode: ALT2 mux port: RX of instance: sci_flx2.
Select mux mode: ALT4 mux port: FB_AD[14] of instance: platform.
Select mux mode: ALT5 mux port: IN1 of instance: spdif.
Select mux mode: ALT7 mux port: debug_out[18] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD1.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD1.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD1.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTD1 field descriptions (continued)
Field
Description
0
1
Output is CMOS
Output is open drain
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD1.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD1.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD1.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD1.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD1.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD1.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD1.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.82 Software MUX Pad Control Register 81 (IOMUXC_PTD2)
Address: 4004_8000h base + 144h offset = 4004_8144h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTD2 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD2.
000
001
010
011
100
101
111
Select mux mode: ALT0 mux port: GPIO[81] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO3_A of instance: quadspi0.
Select mux mode: ALT2 mux port: RTS of instance: sci_flx2.
Select mux mode: ALT3 mux port: CS3 of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[13] of instance: platform.
Select mux mode: ALT5 mux port: OUT1 of instance: spdif.
Select mux mode: ALT7 mux port: debug_out[19] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD2.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD2.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD2.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD2.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD2.
0
1
0
1
0
1
000
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
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IOMUXC_PTD2 field descriptions (continued)
Field
Description
001
010
011
100
101
110
111
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD2.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD2.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD2.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD2.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD2.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.83 Software MUX Pad Control Register 82 (IOMUXC_PTD3)
Address: 4004_8000h base + 148h offset = 4004_8148h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTD3 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTD3.
NOTE: Pad PTD3 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT for mode ALT2.
000
001
010
011
100
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[82] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO2_A of instance: quadspi0.
Select mux mode: ALT2 mux port: CTS of instance: sci_flx2.
Select mux mode: ALT3 mux port: CS2 of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[12] of instance: platform.
Select mux mode: ALT5 mux port: PLOCK of instance: spdif.
Select mux mode: ALT7 mux port: debug_out[20] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD3.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD3.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD3.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD3.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD3.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD3.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
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IOMUXC_PTD3 field descriptions (continued)
Field
Description
10
11
100 kOhm Pull Up
22 kOhm Pull Up
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD3.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD3.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD3.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD3.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.84 Software MUX Pad Control Register 83 (IOMUXC_PTD4)
Address: 4004_8000h base + 14Ch offset = 4004_814Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD4 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD4.
000
001
011
100
101
111
Select mux mode: ALT0 mux port: GPIO[83] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO1_A of instance: quadspi0.
Select mux mode: ALT3 mux port: CS1 of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[11] of instance: platform.
Select mux mode: ALT5 mux port: SRCLK of instance: spdif.
Select mux mode: ALT7 mux port: debug_out[21] of instance: viu_mux.
This field is reserved.
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IOMUXC_PTD4 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTD4.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD4.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD4.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD4.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD4.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD4.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD4.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD4.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD4.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD4.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTD4 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.85 Software MUX Pad Control Register 84 (IOMUXC_PTD5)
Address: 4004_8000h base + 150h offset = 4004_8150h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD5 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD5.
NOTE: Pad PTD5 is involved in Daisy Chain.
• Config Register IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT for mode ALT3.
000
001
011
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[84] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO0_A of instance: quadspi0.
Select mux mode: ALT3 mux port: CS0 of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[10] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[22] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD5.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD5.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD5.
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
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IOMUXC_PTD5 field descriptions (continued)
Field
Description
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD5.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD5.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD5.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD5.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD5.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD5.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD5.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.86 Software MUX Pad Control Register 85 (IOMUXC_PTD6)
Address: 4004_8000h base + 154h offset = 4004_8154h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
0
IOMUXC_PTD6 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD6.
NOTE: Pad PTD6 is involved in Daisy Chain.
• Config Register IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT for mode ALT3.
000
001
011
100
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[85] of instance: rgpioc.
Select mux mode: ALT1 mux port: DQS_A of instance: quadspi0.
Select mux mode: ALT3 mux port: SIN of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[9] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[23] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD6.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD6.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD6.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD6.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD6.
0
1
0
1
0
1
000
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
Table continues on the next page...
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IOMUXC_PTD6 field descriptions (continued)
Field
Description
001
010
011
100
101
110
111
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD6.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD6.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD6.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD6.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD6.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.87 Software MUX Pad Control Register 86 (IOMUXC_PTD7)
Address: 4004_8000h base + 158h offset = 4004_8158h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTD7 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD7.
000
001
011
100
111
Select mux mode: ALT0 mux port: GPIO[86] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSCK_B of instance: quadspi0.
Select mux mode: ALT3 mux port: SOUT of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[8] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[24] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD7.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD7.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD7.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD7.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD7.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD7.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD7.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Table continues on the next page...
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IOMUXC_PTD7 field descriptions (continued)
Field
Description
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD7.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD7.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD7.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.88 Software MUX Pad Control Register 87 (IOMUXC_PTD8)
Address: 4004_8000h base + 15Ch offset = 4004_815Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD8 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD8.
NOTE: Pad PTD8 is involved in Daisy Chain.
• Config Register IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT for mode ALT3.
000
001
010
011
100
111
19–14
Reserved
Select mux mode: ALT0 mux port: GPIO[87] of instance: rgpioc.
Select mux mode: ALT1 mux port: QPCS0_B of instance: quadspi0.
Select mux mode: ALT2 mux port: FB_CLKOUT of instance: lpcg0.
Select mux mode: ALT3 mux port: SCK of instance: dspi1.
Select mux mode: ALT4 mux port: FB_AD[7] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[25] of instance: viu_mux.
This field is reserved.
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IOMUXC_PTD8 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTD8.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD8.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD8.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD8.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD8.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD8.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD8.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD8.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD8.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD8.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Table continues on the next page...
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IOMUXC_PTD8 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.89 Software MUX Pad Control Register 88 (IOMUXC_PTD9)
Address: 4004_8000h base + 160h offset = 4004_8160h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD9 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 6 IOMUX modes to be used for pad: PTD9.
NOTE: Pad PTD9 is involved in Daisy Chain.
• Config Register IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT for mode ALT6.
000
001
010
100
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[88] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO3_B of instance: quadspi0.
Select mux mode: ALT2 mux port: CS1 of instance: dspi3.
Select mux mode: ALT4 mux port: FB_AD[6] of instance: platform.
Select mux mode: ALT6 mux port: TX_SYNC of instance: sai1.
Select mux mode: ALT7 mux port: DATA_OUT[2] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD9.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD9.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD9.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTD9 field descriptions (continued)
Field
Description
0
1
Output is CMOS
Output is open drain
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD9.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD9.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD9.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD9.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD9.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD9.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD9.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.90 Software MUX Pad Control Register 89 (IOMUXC_PTD10)
Address: 4004_8000h base + 164h offset = 4004_8164h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTD10 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD10.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[89] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO2_B of instance: quadspi0.
Select mux mode: ALT2 mux port: CS0 of instance: dspi3.
Select mux mode: ALT4 mux port: FB_AD[5] of instance: platform.
Select mux mode: ALT7 mux port: DATA_OUT[3] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD10.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD10.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD10.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD10.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD10.
0
1
0
1
0
1
000
001
010
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
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IOMUXC_PTD10 field descriptions (continued)
Field
Description
011
100
101
110
111
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD10.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD10.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD10.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD10.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD10.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.91 Software MUX Pad Control Register 90 (IOMUXC_PTD11)
Address: 4004_8000h base + 168h offset = 4004_8168h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD11 field descriptions
Field
31–23
Reserved
Description
This field is reserved.
Table continues on the next page...
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IOMUXC_PTD11 field descriptions (continued)
Field
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD11.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[90] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO1_B of instance: quadspi0.
Select mux mode: ALT2 mux port: SIN of instance: dspi3.
Select mux mode: ALT4 mux port: FB_AD[4] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[26] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD11.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD11.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD11.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD11.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD11.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD11.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD11.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Table continues on the next page...
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IOMUXC_PTD11 field descriptions (continued)
Field
Description
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD11.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD11.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD11.
0
1
0
1
0
1
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.92 Software MUX Pad Control Register 91 (IOMUXC_PTD12)
Address: 4004_8000h base + 16Ch offset = 4004_816Ch
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTD12 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD12.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[91] of instance: rgpioc.
Select mux mode: ALT1 mux port: QSPI_IO0_B of instance: quadspi0.
Select mux mode: ALT2 mux port: SOUT of instance: dspi3.
Select mux mode: ALT4 mux port: FB_AD[3] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[27] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD12.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
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IOMUXC_PTD12 field descriptions (continued)
Field
Description
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD12.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD12.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD12.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD12.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD12.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD12.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD12.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD12.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD12.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.93 Software MUX Pad Control Register 92 (IOMUXC_PTD13)
Address: 4004_8000h base + 170h offset = 4004_8170h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
0
7
6
5
DSE
0
0
0
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
0
IOMUXC_PTD13 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTD13.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[92] of instance: rgpioc.
Select mux mode: ALT1 mux port: DQS_B of instance: quadspi0.
Select mux mode: ALT2 mux port: SCK of instance: dspi3.
Select mux mode: ALT4 mux port: FB_AD[2] of instance: platform.
Select mux mode: ALT7 mux port: debug_out[28] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTD13.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTD13.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTD13.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTD13.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTD13.
0
1
0
1
0
1
000
001
010
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
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IOMUXC_PTD13 field descriptions (continued)
Field
Description
011
100
101
110
111
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTD13.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTD13.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTD13.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTD13.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTD13.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.94 Software MUX Pad Control Register 93 (IOMUXC_PTB23)
Address: 4004_8000h base + 174h offset = 4004_8174h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTB23 field descriptions
Field
31–23
Reserved
Description
This field is reserved.
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IOMUXC_PTB23 field descriptions (continued)
Field
22–20
MUX_MODE
Description
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB23.
NOTE: Pad PTB23 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT for mode ALT2.
000
001
010
011
100
101
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[93] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX_BCLK of instance: sai0.
Select mux mode: ALT2 mux port: TX of instance: sci_flx1.
Select mux mode: ALT3 reserved
Select mux mode: ALT4 mux port: FB_MUXED_ALE of instance: platform.
Select mux mode: ALT5 mux port: FB_TS_b of instance: platform.
Select mux mode: ALT6 mux port: RTS of instance: sci_flx3.
Select mux mode: ALT7 mux port: DATA_OUT[13] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB23.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB23.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB23.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB23.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB23.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB23.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTB23 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB23.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB23.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB23.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB23.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.95 Software MUX Pad Control Register 94 (IOMUXC_PTB24)
Address: 4004_8000h base + 178h offset = 4004_8178h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTB24 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTB24.
NOTE: Pad PTB24 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT for mode ALT2.
000
001
010
011
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[94] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX_BCLK of instance: sai0.
Select mux mode: ALT2 mux port: RX of instance: sci_flx1.
Select mux mode: ALT3 reserved
Select mux mode: ALT4 mux port: FB_MUXED_TSIZ0 of instance: platform.
Select mux mode: ALT5 mux port: NF_WE_b of instance: nfc_mlc.
Select mux mode: ALT6 mux port: CTS of instance: sci_flx3.
Select mux mode: ALT7 mux port: DATA_OUT[14] of instance: tcon1.
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IOMUXC_PTB24 field descriptions (continued)
Field
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
Speed Field. Select one of the following values for pad: PTB24.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB24.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB24.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB24.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB24.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB24.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB24.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB24.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB24.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
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IOMUXC_PTB24 field descriptions (continued)
Field
Description
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB24.
0
1
Disabled
Enabled
5.2.5.96 Software MUX Pad Control Register 95 (IOMUXC_PTB25)
Address: 4004_8000h base + 17Ch offset = 4004_817Ch
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
1
7
6
5
DSE
0
0
1
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
1
IOMUXC_PTB25 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTB25.
000
001
010
011
100
101
111
Select mux mode: ALT0 mux port: GPIO[95] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX_DATA of instance: sai0.
Select mux mode: ALT2 mux port: RTS of instance: sci_flx1.
Select mux mode: ALT3 reserved
Select mux mode: ALT4 mux port: FB_CS1_b of instance: platform.
Select mux mode: ALT5 mux port: NF_CE0_b of instance: nfc_mlc.
Select mux mode: ALT7 mux port: DATA_OUT[15] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB25.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB25.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB25.
0
1
Slow Slew Rate
Fast Slew Rate
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IOMUXC_PTB25 field descriptions (continued)
Field
Description
0
1
Output is CMOS
Output is open drain
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB25.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB25.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB25.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB25.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB25.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB25.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB25.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.97 Software MUX Pad Control Register 96 (IOMUXC_PTB26)
Address: 4004_8000h base + 180h offset = 4004_8180h
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
1
7
6
5
DSE
0
0
1
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
1
IOMUXC_PTB26 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTB26.
NOTE: Pad PTB26 is involved in Daisy Chain.
• Config Register IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT for mode ALT2.
000
001
010
011
100
101
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[96] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX_DATA of instance: sai0.
Select mux mode: ALT2 mux port: CTS of instance: sci_flx1.
Select mux mode: ALT3 mux port: RCON21 of instance: src.
Select mux mode: ALT4 mux port: FB_CS0_b of instance: platform.
Select mux mode: ALT5 mux port: NF_CE1_b of instance: nfc_mlc.
Select mux mode: ALT7 mux port: DATA_OUT[16] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB26.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB26.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB26.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB26.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
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IOMUXC_PTB26 field descriptions (continued)
Field
Description
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB26.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB26.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB26.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB26.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB26.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB26.
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.98 Software MUX Pad Control Register 97 (IOMUXC_PTB27)
Address: 4004_8000h base + 184h offset = 4004_8184h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTB27 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTB27.
000
001
011
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[97] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX_SYNC of instance: sai0.
Select mux mode: ALT3 mux port: RCON22 of instance: src.
Select mux mode: ALT4 mux port: FB_OE_b of instance: platform.
Select mux mode: ALT5 mux port: FB_MUXED_TBST_b of instance: platform.
Select mux mode: ALT6 mux port: NF_RE_b of instance: nfc_mlc.
Select mux mode: ALT7 mux port: DATA_OUT[17] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB27.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB27.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB27.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB27.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB27.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB27.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTB27 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB27.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB27.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB27.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB27.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.99 Software MUX Pad Control Register 98 (IOMUXC_PTB28)
Address: 4004_8000h base + 188h offset = 4004_8188h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTB28 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTB28.
000
001
011
100
111
Select mux mode: ALT0 mux port: GPIO[98] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX_SYNC of instance: sai0.
Select mux mode: ALT3 mux port: RCON23 of instance: src.
Select mux mode: ALT4 mux port: FB_RW_b of instance: platform.
Select mux mode: ALT7 mux port: DATA_OUT[8] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTB28.
00
Low (50 MHz)
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IOMUXC_PTB28 field descriptions (continued)
Field
Description
01
10
11
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTB28.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTB28.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTB28.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTB28.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTB28.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTB28.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTB28.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTB28.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTB28.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.100 Software MUX Pad Control Register 99 (IOMUXC_PTC26)
Address: 4004_8000h base + 18Ch offset = 4004_818Ch
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
1
7
6
5
DSE
0
0
1
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
1
IOMUXC_PTC26 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC26.
000
001
010
011
100
101
111
Select mux mode: ALT0 mux port: GPIO[99] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX_BCLK of instance: sai1.
Select mux mode: ALT2 mux port: CS5 of instance: dspi0.
Select mux mode: ALT3 mux port: RCON24 of instance: src.
Select mux mode: ALT4 mux port: FB_TA_b of instance: platform.
Select mux mode: ALT5 mux port: NF_RB_b of instance: nfc_mlc.
Select mux mode: ALT7 mux port: DATA_OUT[9] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC26.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC26.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC26.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC26.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC26.
0
1
0
1
0
1
000
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
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IOMUXC_PTC26 field descriptions (continued)
Field
Description
001
010
011
100
101
110
111
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC26.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC26.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC26.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC26.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC26.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.101 Software MUX Pad Control Register 100 (IOMUXC_PTC27)
Address: 4004_8000h base + 190h offset = 4004_8190h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
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IOMUXC_PTC27 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC27.
000
001
010
011
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[100] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX_BCLK of instance: sai1.
Select mux mode: ALT2 mux port: CS4 of instance: dspi0.
Select mux mode: ALT3 mux port: RCON25 of instance: src.
Select mux mode: ALT4 mux port: FB_BE3_b of instance: platform.
Select mux mode: ALT5 mux port: FB_CS3_b of instance: platform.
Select mux mode: ALT6 mux port: NF_ALE of instance: nfc_mlc.
Select mux mode: ALT7 mux port: DATA_OUT[4] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC27.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC27.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC27.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC27.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC27.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC27.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
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IOMUXC_PTC27 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC27.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC27.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC27.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC27.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.102 Software MUX Pad Control Register 101 (IOMUXC_PTC28)
Address: 4004_8000h base + 194h offset = 4004_8194h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
IOMUXC_PTC28 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC28.
000
001
010
011
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[101] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX_DATA of instance: sai1.
Select mux mode: ALT2 mux port: CS3 of instance: dspi0.
Select mux mode: ALT3 mux port: RCON26 of instance: src.
Select mux mode: ALT4 mux port: FB_BE2_b of instance: platform.
Select mux mode: ALT5 mux port: FB_CS2_b of instance: platform.
Select mux mode: ALT6 mux port: NF_CLE of instance: nfc_mlc.
Select mux mode: ALT7 mux port: DATA_OUT[5] of instance: tcon1.
This field is reserved.
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IOMUXC_PTC28 field descriptions (continued)
Field
13–12
SPEED
Description
Speed Field. Select one of the following values for pad: PTC28.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC28.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC28.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC28.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC28.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC28.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC28.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC28.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC28.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC28.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Table continues on the next page...
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IOMUXC_PTC28 field descriptions (continued)
Field
Description
0
1
Disabled
Enabled
5.2.5.103 Software MUX Pad Control Register 102 (IOMUXC_PTC29)
Address: 4004_8000h base + 198h offset = 4004_8198h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
1
17
16
Reserved
PUS
1
18
0
IOMUXC_PTC29 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 7 IOMUX modes to be used for pad: PTC29.
000
001
010
011
100
101
111
Select mux mode: ALT0 mux port: GPIO[102] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX_DATA of instance: sai1.
Select mux mode: ALT2 mux port: CS2 of instance: dspi0.
Select mux mode: ALT3 mux port: RCON27 of instance: src.
Select mux mode: ALT4 mux port: FB_BE1_b of instance: platform.
Select mux mode: ALT5 mux port: FB_MUXED_TSIZ1 of instance: platform.
Select mux mode: ALT7 mux port: DATA_OUT[6] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC29.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC29.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC29.
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
Table continues on the next page...
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IOMUXC_PTC29 field descriptions (continued)
Field
Description
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC29.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC29.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC29.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC29.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC29.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC29.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC29.
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
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5.2.5.104 Software MUX Pad Control Register 103 (IOMUXC_PTC30)
Address: 4004_8000h base + 19Ch offset = 4004_819Ch
Bit
R
W
31
Reset
0
0
0
0
15
14
13
12
Bit
R
W
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
0
0
0
8
11
10
9
SRE
ODE
HYS
0
0
0
0
21
20
19
MUX_MODE
0
0
1
7
6
5
DSE
0
0
1
4
PUS
1
1
18
17
16
Reserved
0
0
0
0
0
3
2
1
0
PKE
PUE
OBE
IBE
0
0
0
1
IOMUXC_PTC30 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 8 IOMUX modes to be used for pad: PTC30.
000
001
010
011
100
101
110
111
Select mux mode: ALT0 mux port: GPIO[103] of instance: rgpioc.
Select mux mode: ALT1 mux port: RX_SYNC of instance: sai1.
Select mux mode: ALT2 mux port: CS2 of instance: dspi1.
Select mux mode: ALT3 mux port: RCON28 of instance: src.
Select mux mode: ALT4 mux port: FB_MUXED_BE0_b of instance: platform.
Select mux mode: ALT5 mux port: FB_TSIZ0 of instance: platform.
Select mux mode: ALT6 mux port: ADC0SE5 of instance: adc0_da.
Select mux mode: ALT7 mux port: DATA_OUT[7] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC30.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC30.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC30.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC30.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC30.
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
Table continues on the next page...
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Chapter 5 Chip IO and Pinmux
IOMUXC_PTC30 field descriptions (continued)
Field
Description
000
001
010
011
100
101
110
111
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC30.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC30.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC30.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC30.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC30.
00
01
10
11
0
1
0
1
0
1
0
1
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.105 Software MUX Pad Control Register 104 (IOMUXC_PTC31)
Address: 4004_8000h base + 1A0h offset = 4004_81A0h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
0
0
1
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
1
18
17
16
Reserved
0
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Input/Output Multiplexer Controller (IOMUXC)
IOMUXC_PTC31 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTC31.
NOTE: Pad PTC31 is involved in Daisy Chain.
• Config Register IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT for mode ALT1.
000
001
011
110
111
19–14
Reserved
13–12
SPEED
Select mux mode: ALT0 mux port: GPIO[104] of instance: rgpioc.
Select mux mode: ALT1 mux port: TX_SYNC of instance: sai1.
Select mux mode: ALT3 mux port: RCON29 of instance: src.
Select mux mode: ALT6 mux port: ADC1SE5 of instance: adc1_da.
Select mux mode: ALT7 mux port: DATA_OUT[8] of instance: tcon1.
This field is reserved.
Speed Field. Select one of the following values for pad: PTC31.
00
01
10
11
Low (50 MHz)
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTC31.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTC31.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTC31.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTC31.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTC31.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (48 Ohm if pad is DDR)
25 Ohm (40 Ohm if pad is DDR)
20 Ohm (34 Ohm if pad is DDR)
100 kOhm Pull Down
47 kOhm Pull Up
100 kOhm Pull Up
22 kOhm Pull Up
Table continues on the next page...
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Chapter 5 Chip IO and Pinmux
IOMUXC_PTC31 field descriptions (continued)
Field
Description
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTC31.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTC31.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTC31.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTC31.
0
1
0
1
0
1
0
1
Pull/Keeper Disabled
Pull/Keeper Enabled
Keeper enable
Pull enable
Disabled
Enabled
Disabled
Enabled
5.2.5.106 Software MUX Pad Control Register 105 (IOMUXC_PTE0)
Address: 4004_8000h base + 1A4h offset = 4004_81A4h
Bit
R
W
31
Reset
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Bit
R
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRE
ODE
HYS
PKE
PUE
OBE
IBE
0
0
0
0
1
0
0
Reset
30
29
28
27
26
25
24
23
22
Reserved
Reserved
SPEED
0
0
0
0
21
20
19
MUX_MODE
DSE
0
0
PUS
1
0
18
17
16
Reserved
0
IOMUXC_PTE0 field descriptions
Field
31–23
Reserved
22–20
MUX_MODE
19–14
Reserved
13–12
SPEED
Description
This field is reserved.
MUX Mode Select Field. Select 1 of 5 IOMUX modes to be used for pad: PTE0.
000
001
010
100
111
Select mux mode: ALT0 mux port: GPIO[105] of instance: rgpioc.
Select mux mode: ALT1 mux port: TCON[1] of instance: tcon0.
Select mux mode: ALT2 mux port: BOOTMODE[1] of instance: src.
Select mux mode: ALT4 mux port: LCD0 of instance: lcd_64f6b.
Select mux mode: ALT7 mux port: debug_out[29] of instance: viu_mux.
This field is reserved.
Speed Field. Select one of the following values for pad: PTE0.
00
Low (50 MHz)
Table continues on the next page...
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Input/Output Multiplexer Controller (IOMUXC)
IOMUXC_PTE0 field descriptions (continued)
Field
Description
01
10
11
Medium (100 MHz)
Medium (100 MHz)
High (200 MHz)
11
SRE
Slew Rate Field. Select one of the following values for pad: PTE0.
10
ODE
Open Drain Enable Field. Select one of the following values for pad: PTE0.
9
HYS
Hysteresis Enable Field. Select one of the following values for pad: PTE0.
8–6
DSE
Drive Strength Field. Select one of the following values for pad: PTE0.
5–4
PUS
Pull Up / Down Config Field. Select one of the following values for pad: PTE0.
3
PKE
Pull / Keep Enable Field. Select one of the following values for pad: PTE0.
2
PUE
Pull / Keep Select Field. Select one of the following values for pad: PTE0.
1
OBE
Output Buffer Enable Field. Select one of the following values for pad: PTE0.
0
IBE
Input Buffer Enable Field. Select one of the following values for pad: PTE0.
0
1
0
1
0
1
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0
1
Slow Slew Rate
Fast Slew Rate
Output is CMOS
Output is open drain
CMOS input
Schmitt trigger input
output driver disabled;
150 Ohm (240 Ohm if pad is DDR)
75 Ohm (120 Ohm if pad is DDR)
50 Ohm (80 Ohm if pad is DDR)
37 Ohm (60 Ohm if pad is DDR)
30 Ohm (4