NXP PCA85233UG Automotive 80 x 4 LCD driver Data Sheet

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PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Rev. 5 — 12 November 2018 Product data sheet

The PCA85233 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD) 1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCA85233 is compatible with most microcontrollers and communicates via the two-line bidirectional I 2 C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes).

For a selection of NXP LCD segment drivers, see Table 28 on page 46 .

2. Features and benefits

 AEC-Q100 compliant for automotive applications

 Single-chip LCD controller and driver

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 Selectable display bias configuration: static, 1 ⁄

2

, or

 Selectable frame frequency: 150 Hz or 220 Hz

1 ⁄

3

 Internal LCD bias generation with voltage-follower buffers

 80 segment drives:

 Up to 40 7-segment alphanumeric characters

 Up to 20 14-segment alphanumeric characters

 Any graphics of up to 320 segments/elements

 80

4 bit RAM for display data storage

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Independent supplies possible for LCD and logic voltages

 Wide power supply range: from 1.8 V to 5.5 V

 Wide LCD supply range:

 From 2.5 V for low-threshold LCDs

 Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs

 Low power consumption

 400 kHz I 2 C-bus interface

 Extended temperature range up to 105

C

 Backside laser marking

 May be cascaded for large LCD applications (up to 2560 segments possible)

1.

The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20 .

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

 No external components needed

 Compatible with Chip-On-Glass (COG) technology

Table 1.

Ordering information

Type number Package

PCA85233UG

Name bare die

Description

110 bumps

3.1 Ordering options

Table 2.

Ordering options

Product type number Orderable part number Sales item

(12NC)

Delivery form

PCA85233UG/2DA/Q1 PCA85233UG/2DA/Q1Z 935302508033

chip with hard bumps in tray [1]

[1] Bump hardness see

Table 25

.

4. Marking

Table 3.

Marking codes

Type number

PCA85233UG/2DA/Q1

[1] The rear side marking has the following meaning:

XXXXXX.XX — Production and lot information

WW — wafer number

Marking code on the rear side of the die

Line A: PCA85233UG

Line B: XXXXXX.XX WW [1]

SLQRULHQWDWLRQ

LQGLFDWRU

Version

PCA85233

IC revision

1

DDD

Fig 1.

Rear side laser marking

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

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PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

6.1 Pinning

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Viewed from active side. For mechanical details, see

Figure 27 .

Fig 3.

Pin configuration for PCA85233

6.2 Pin description

Table 4.

Pin description overview

Input or input/output pins must always be at a defined level (V

SS

or V

DD

) unless otherwise specified.

Symbol

SDAACK

Pin

1 to 3

Description

I 2 C-bus acknowledge output

SDA

SCL

4 to 6

7 to 9

I 2 C-bus serial data input

I 2 C-bus serial clock input

CLK

V

DD

SYNC

10

11 to 13

14 clock input and output supply voltage cascade synchronization input or output; if not used it must be left open

OSC

FF

15

16 oscillator select frame frequency select

A0, A1 17, 18 subaddress input

T1 19 dedicated testing pin; to be tied to V

SS

in application mode

I 2 C-bus slave address input SA0

V

SS

[1]

20

21 to 23 ground supply voltage

V

LCD

24 to 26 LCD supply voltage

BP2, BP0, BP3, and BP1 27, 28, 109 and 110 LCD backplane output

S0 to S79 29 to 108 LCD segment output

D1 to D9 dummy pins

[1] The substrate (rear side of the die) is at V

SS

potential and should be electrically isolated.

PCA85233

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.1 Commands of PCA85233

The command decoder identifies command bytes that arrive on the I 2 C-bus. The commands available to the PCA85233 are defined in

Table 5

.

Table 5.

Definition of commands

Command

Bit

Operation code

7 6 5 mode-set load-data-pointer device-select

1

0

1

1

P[6:0]

1

0

1 bank-select blink-select

1

1

1

1

1

1

0

1

1

4

0

0

1

0

3

E

2

B

0

0

AB

1

M[1:0]

0

A[1:0]

I

BF[1:0]

O

Reference

Table 6

Table 7

Table 8

Table 9

Table 10

Table 6.

Mode-set command bit description

Bit Symbol Value Description

7 to 4

3

2

1 to 0

-

E

B

M[1:0]

1100

0

1

0

1 fixed value display status

[1]

disabled (blank)

[2]

enabled

LCD bias configuration

[3]

1 ⁄

3

bias

1 ⁄

2

bias

LCD drive mode selection

01

10

11

00 static; 1 backplane

1:2 multiplex; 2 backplanes

1:3 multiplex; 3 backplanes

1:4 multiplex; 4 backplanes

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] The display is disabled by setting all backplane and segment outputs to V

LCD

.

[3] Not applicable for static drive mode.

Table 7.

Load-data-pointer command bit description

See

Section 7.3.1

.

Bit

7

6 to 0

-

Symbol

P[6:0]

Value

0

Description fixed value

0000000 to

1001111 data pointer

7-bit binary value of 0 to 79, transferred to the data pointer to define one of 80 display RAM addresses

PCA85233

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 8.

Device-select command bit description

See

Section 7.3.2

.

Bit

7 to 2

1 to 0

-

Symbol

A[1:0]

Value

111000

00 to 11

Description fixed value device selection

2-bit binary value of 0 to 3, transferred to the subaddress counter to define one of 4 hardware subaddresses

Table 9.

Bank-select command bit description [1]

See

Section 7.3.5

and Section 7.3.6

.

Bit Symbol Value Description

7 to 2

1

-

I

111110

0

1

Static fixed value

1:2 multiplex input bank selection : storage of arriving display data

RAM row 0 RAM rows 0 and 1

0 O

0

1

RAM row 2 RAM rows 2 and 3 output bank selection : retrieval of LCD display data

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.

Table 10.

Blink-select command bit description

See

Section 7.2.3

.

Bit

7 to 3

2

1 to 0

-

Symbol

AB

BF[1:0]

Value

11110

0

1

Description fixed value

blink mode selection [1]

normal blinking blinking by alternating display RAM banks blink frequency selection

[2]

00

01

10

11 off

1

2

3

[1] Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4.

[2]

For the blink frequencies, see Table 12 .

7.2 Clock and frame frequency

7.2.1 Oscillator

The internal logic and the LCD drive signals of the PCA85233 are timed by a frequency f clk

which either is derived from the built-in oscillator frequency f osc

: f clk

= f

--------

64

(1)

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates or equals an external clock frequency f clk(ext)

: f clk

= f clk ext

(2)

7.2.1.1

Internal clock

The internal oscillator is enabled by connecting pin OSC to V

SS

. In this case the output from pin CLK provides the clock signal for any cascaded PCA85233 in the system.

7.2.1.2

External clock

Connecting pin OSC to V

DD

enables an external clock source. Pin CLK then becomes the external clock input.

Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.2.2 Frame frequency

The clock frequency f clk

determines the LCD frame frequency f fr

and is calculated as follows: f fr

= f

--------

24

(3)

The internal clock frequency f clk

can be selected using pin FF. As a result 2 frame frequencies are available: 150 Hz or 220 Hz (typical), see

Table 11

.

Table 11.

LCD frame frequencies

Pin FF tied to [1]

Typical clock frequency (Hz) LCD frame frequency (Hz)

V

DD

V

SS

3600

5280

150

220

[1] FF has no effect when an external clock is used but must not be left floating.

The timing of the PCA85233 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCA85233 in the system.

7.2.3 Blinking

The display blink capabilities of the PCA85233 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see

Table 10

). The blink frequencies are derived from the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode selected (see Table 12

).

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 12.

Blink frequencies

Blink mode Operating mode ratio Blink frequency with respect to f clk

(typical) off f clk

= 3.600 kHz blinking off f clk

= 5.280 kHz blinking off

1 4.7

6.9

f

---------

768

2 2.3

3.4

f

------------

1536

3 1.2

1.7

f

------------

3072

Unit

Hz

Hz

Hz

Hz

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at fixed time intervals.

If the entire display can blink at a frequency other then the typical blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see

Table 6

).

7.3 Display RAM

The display RAM is a static 80

4 bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD segments/elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state.

The display RAM bit map,

Figure 4 , shows rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0,

BP1, BP2, and BP3 respectively.

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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8 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

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The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs.

Fig 4.

Display RAM bitmap

When display data is transmitted to the PCA85233, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and depending on the current multiplex drive mode the bits are stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment

display showing all drive modes is given in Figure 5

; the RAM filling organization depicted applies equally to other LCD types.

The following applies to

Figure 5 :

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as four successive 2-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.3.3

).

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit RAM words.

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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Fig 5.

Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I 2 C-bus

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.3.1 Data pointer

The addressing mechanism for the display RAM is realized using a data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see

Table 7

). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in

Figure 5 . After each byte is stored, the content of the data pointer

is automatically incremented by a value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I 2 C-bus data access is terminated early then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.3.2 Subaddress counter

The storage of display data is determined by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0 and A1. The subaddress counter value is defined by the device-select command (see

Table 8

). If the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA85233 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed whilst the device is being accessed on the I 2 C-bus interface.

7.3.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 13

(see

Figure 5 as

well).

2

3

0

1

Table 13.

Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the display.

Display RAM bits (rows)/ backplane outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

0 1 2 3 4 5 6 7 8 9 :

a7 a6 a5

a4 a3 a2 -

a1 a0

b7 b6 b5

b4 b3 b2 -

b1 b0

c7 c6 c5

c4 c3 c2 -

c1 c0

d7 d6 d5 :

:

:

:

PCA85233

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 14 .

1

2

3

Table 14.

Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.

Display RAM addresses (columns)/segment outputs (Sn) Display RAM bits (rows)/ backplane outputs (BPn)

0 1 2 3 4 5 6 7 8 9 :

0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :

a6 a5

a3 a2

a0/b6 b3 b5

b2

b0/c6 c3 c5

c2

c0/d6 d3 d5

d2

d0/e6 e3 e5

e2 :

:

:

In the case described in

Table 14 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to segments/elements on the display. This can be achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written.

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6.

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6.

Depending on the method of writing to the RAM (standard or entire filling by rewriting), some segments/elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design.

7.3.4 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to fill the RAM over the RAM address boundary. If the PCA85233 is part of a cascade the additional bits fall into the next device that also generates the acknowledge signal. If the

PCA85233 is a single device or the last device in a cascade the additional bits will be discarded and no acknowledge signal will be generated.

7.3.5 Output bank selector

The output bank selector (see Table 9 ) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the selected LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The PCA85233 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex

PCA85233

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.

7.3.6 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 9

). The input bank selector functions independently to the output bank selector.

7.4 Initialization

At power-on the status of the I 2 C-bus and the registers of the PCA85233 is undefined.

Therefore the PCA85233 should be initialized as quickly as possible after power-on to ensure a proper bus communication and to avoid display artifacts. The following instructions should be accomplished for initialization:

7.4.1 Device initialization

At power-on the status of the I 2 C-bus communication interface is undefined since this device doesn’t have POR which was removed to improve the ESD performance. A START and STOP condition with dummy byte in-between must be sent after every power reset to set up the I 2 C-bus communication interface.

• I 2 C-bus (see

Section 8

) initialization

– generating a START condition

– sending 0h (1 byte) and ignoring the acknowledge – Note, this is not the device address but just a dummy byte of all zeros

– generating a STOP condition

7.4.2 Device setup

At power-on the status of the display and configuration registers are undefined and need to be set up to properly display information on the LCD display. After the I 2 C-bus interface

is initialized as discussed in Section 7.4.1

set up the device using these register settings

• Mode-set command (see

Table 6

), setting

– bit E = 0

– bit B to the required LCD bias configuration

– bits M[1:0] to the required LCD drive mode

Load-data-pointer command (see Table 7 ), setting

– bits P[4:0] to 0h (or any other required address)

Device-select command (see Table 8 ), setting

– bits A[1:0] to the required hardware subaddress (for example, 0h)

• Bank-select command (see

Table 9 ), setting

– bit I to 0

– bit O to 0

• Blink-select command (see

Table 10 ), setting

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

– bit AB to 0 or 1

– bits BF[1:0] to 00 (or to a desired blinking mode)

• writing meaningful information (for example, a logo) into the display RAM

• After the initialization, the display can be switched on by setting bit E = 1 with the mode-set command or left off (blank) with bit E = 0.

7.5 Possible display configurations

The PCA85233 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 6

). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to

80 segments.

The display configurations possible with the PCA85233 depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 15 .

All of the display configurations given in

Table 15

can be implemented in a typical system

as shown in Figure 7

.

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PCA85233

Product data sheet

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Fig 6.

Example of displays suitable for PCA85233

4

3

2

1

Table 15.

Selection of possible display configurations

Number of

Backplanes Icons

320

240

160

80

Digits/Characters

7-segment [1]

40

30

20

10

14-segment [2]

20

15

10

5

Dot matrix: segments/ elements

320 (4

80)

240 (3

80)

160 (2

80)

80 (1

80)

[1] 7 segment display has 8 segments/elements including the decimal point.

[2] 14 segment display has 16 segments/elements including decimal point and accent dot.

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

PCA85233

Product data sheet

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Fig 7.

Typical system configuration

DDD

The host microcontroller maintains the 2-line I 2 C-bus communication channel with the

PCA85233. The internal oscillator is enabled by connecting pin OSC to pin V

SS

. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are the power supplies (V

DD

,

V

SS

, and V

LCD

) and the LCD panel chosen for the application.

7.6 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three impedances connected between pins V

LCD

and V

SS

. The center impedance is bypassed by switch if the 1 ⁄

2 bias voltage level for the 1:2 multiplex drive mode configuration is selected.

7.7 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of

V

LCD

and the resulting discrimination ratios (D) are given in

Table 16

.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast.

Table 16.

Biasing characteristics

LCD drive mode

Number of:

Backplanes Levels

LCD bias configuration static 1

1:2 multiplex 2

1:2 multiplex 2

1:3 multiplex 3

1:4 multiplex 4

4

4

2

3

4 static

1 ⁄

2

1 ⁄

3

1 ⁄

3

1 ⁄

3

V

-------------------------

V

LCD

0

0.354

0.333

0.333

0.333

V

------------------------

V

LCD

D =

V

-------------------------

V on

RMS

 off

RMS

1

0.791

2.236

0.745

0.638

0.577

2.236

1.915

1.732

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

PCA85233

Product data sheet

A practical value for V

LCD

is determined by equating V off(RMS)

with a defined LCD threshold voltage (V th(off)

), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is V

LCD

> 3V th(off)

.

Multiplex drive modes of 1:3 and 1:4 with 1 ⁄

2

bias are possible but the discrimination and hence the contrast ratios are smaller.

Bias is calculated by

1 + a

, where the values for a are a = 1 for 1 ⁄

2

bias a = 2 for 1 ⁄

3

bias

The RMS on-state voltage (V on(RMS)

) for the LCD is calculated with

Equation 4 :

V

=

V

LCD

2 + 2a + n n

 

1 + a

 2 where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V off(RMS)

) for the LCD is calculated with

Equation 5

:

(4)

V off RMS

=

V

LCD

2 – 2a + n n

 

1 + a

 2

Discrimination is the ratio of V on(RMS)

to V off(RMS)

and is determined from Equation 6 :

(5)

D =

V

-----------------------

V

=

2

+ 2a + n a

2

– 2a + n

(6)

Using Equation 6 , the discrimination for an LCD drive mode of 1:3 multiplex with

1 ⁄

2 bias is 3 = 1.732

and the discrimination for an LCD drive mode of 1:4 multiplex with

1 ⁄

2 bias is

21

1.528

3

= .

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V

LCD as follows:

• 1:3 multiplex ( 1 ⁄

2

bias): V

LCD

=

• 1:4 multiplex ( 1 ⁄

2

bias): V

LCD

=

6

V off

RMS

= 2.449V

off

RMS

 

3

3

= 2.309V

off

RMS

These compare with V

LCD

= 3V off

RMS

when 1 ⁄

3

bias is used.

V

LCD

is sometimes referred as the LCD operating voltage.

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.7.1 Electro-optical performance

Suitable values for V on(RMS)

and V off(RMS)

are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at V th(off)

) and the other at 90 % relative transmission (at V th(on)

), see

Figure 8 . For a good contrast performance, the following rules should be followed:

V

V

V off RMS

V th off

(7)

(8)

V on(RMS)

and V off(RMS)

are properties of the display driver and are affected by the selection of a, n (see

Equation 4 to Equation 6

) and the V

LCD

voltage.

V th(off)

and V th(on)

are properties of the LCD liquid and can be provided by the module manufacturer. V th(off)

is sometimes named V th

. V th(on)

is sometimes named saturation voltage V sat

.

It is important to match the module properties to those of the driver in order to achieve optimum performance.

2))

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Electro-optical characteristic: relative transmission curve of the liquid

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.8 LCD drive mode waveforms

7.8.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in

Figure 9

.

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V state1

(t) = V

Sn

(t)

V

BP0

(t).

V on(RMS)

= V

LCD

.

V state2

(t) = V

(Sn + 1)

(t)

V

BP0

(t).

V off(RMS)

= 0 V.

Fig 9.

Static drive mode waveforms

DDD

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.8.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCA85233 allows the use of 1 ⁄

2

bias or 1 ⁄

3

bias in this mode as shown in

Figure 10

and

Figure 11 .

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V state1

(t) = V

Sn

(t)

V

BP0

(t).

V on(RMS)

= 0.791V

LCD

.

V state2

(t) = V

Sn

(t)

V

BP1

(t).

V off(RMS)

= 0.354V

LCD

.

Fig 10. Waveforms for the 1:2 multiplex drive mode with 1 ⁄

2

bias

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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19 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7

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V state1

(t) = V

Sn

(t)

V

BP0

(t).

V on(RMS)

= 0.745V

LCD

.

V state2

(t) = V

Sn

(t)

V

BP1

(t).

V off(RMS)

= 0.333V

LCD

.

Fig 11. Waveforms for the 1:2 multiplex drive mode with 1 ⁄

3

bias

DDD

PCA85233

Product data sheet

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PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.8.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 12

.

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66

9

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V state1

(t) = V

Sn

(t)

V

BP0

(t).

V on(RMS)

= 0.638V

LCD

.

V state2

(t) = V

Sn

(t)

V

BP1

(t).

V off(RMS)

= 0.333V

LCD

.

Fig 12. Waveforms for the 1:3 multiplex drive mode with 1 ⁄

3

bias

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DDD

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

7.8.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 13

.

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9

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66

9

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66

9

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9

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9

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V state1

(t) = V

Sn

(t)

V

BP0

(t).

V on(RMS)

= 0.577V

LCD

.

V state2

(t) = V

Sn

(t)

V

BP1

(t).

V off(RMS)

= 0.333V

LCD

.

Fig 13. Waveforms for the 1:4 multiplex drive mode with 1 ⁄

3

bias

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DDD

PCA85233

Product data sheet

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Automotive 80 × 4 LCD driver for low multiplex rates

7.9 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated in accordance with the selected LCD drive mode.

• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1; therefore, these two adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, respectively, BP1 and BP3 carry the same signals and can also be paired to increase the drive capabilities.

• In static drive mode: The same signal is carried by all four backplane outputs; and they can be connected in parallel for very high drive requirements.

7.10 Segment outputs

The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. When less than 80 segment outputs are required the unused segment outputs must be left open-circuit.

PCA85233

Product data sheet

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PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

8. Characteristics of the I

2

C-bus

The I 2 C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

By connecting pin SDAACK to pin SDA on the PCA85233, the SDA line becomes fully

I 2 C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a consequence it may be possible that the acknowledge generated by the PCA85233 can’t be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle is required, it is therefore necessary to minimize the track resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level.

By separating the acknowledge output from the serial data line (having the SDAACK open circuit) design efforts to generate a valid acknowledge level can be avoided. However, in that case the I 2 C-bus master has to be set up in such a way that it ignores the acknowledge cycle.

2

The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see

Figure 14

).

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Fig 14. Bit transfer

8.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P).

2.

For further information, please consider the NXP application note: Ref. 1 “AN10170”

.

PCA85233

Product data sheet

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Automotive 80 × 4 LCD driver for low multiplex rates

The START and STOP conditions are shown in Figure 15 .

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Fig 15. Definition of START and STOP conditions

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8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 16 .

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Fig 16. System configuration

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).

• A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

Acknowledgement on the I 2

C-bus is shown in Figure 17

.

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

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8.5 I 2 C-bus controller

The PCA85233 acts as an I 2 C-bus slave receiver. It does not initiate I 2 C-bus transfers or transmit data to an I 2 C-bus master receiver. The only data output from the PCA85233 are the acknowledge signals from the selected devices. Device selection depends on the

I 2 C-bus slave address, on the transferred command data, and on the hardware subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally tied to V

SS

which defines the hardware subaddress 0. In multiple device applications A0 and A1 are tied to V

SS or V

DD

using a binary coding scheme, so that no two devices with a common I 2 C-bus slave address have the same hardware subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.

8.7 I 2 C-bus protocol

Two I 2 C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA85233. The entire I 2

C-bus slave address byte is shown in Table 17 .

Table 17.

I 2 C slave address byte

Slave address

Bit 6 5 7

MSB

0 1 1

4 3 2 1 0

LSB

R/W 1 0 0 SA0

The PCA85233 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCA85233 will respond to, is defined by the level tied to its SA0 input (V

SS

for logic 0 and V

DD

for logic 1).

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Automotive 80 × 4 LCD driver for low multiplex rates

Having two reserved slave addresses allows the following on the same I 2 C-bus:

• Up to 8 PCA85233 on the same I 2 C-bus for very large LCD applications

• The use of two types of LCD multiplex drive modes on the same I 2 C-bus

The I 2

C-bus protocol is shown in Figure 18

. The sequence is initiated with a START condition (S) from the I 2 C-bus master which is followed by one of the available PCA85233 slave addresses. All PCA85233 with the same SA0 level acknowledge in parallel to the slave address. All PCA85233 with the alternative SA0 level ignore the whole I 2 C-bus transfer.

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Fig 18. I 2 C-bus protocol

After acknowledgement, the control byte is sent, defining if the next byte is a RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data (see

Figure 19

and Table 18

). In this way it is possible to configure the device and then fill the display RAM with little overhead.

06% /6%

&2 56 QRWUHOHYDQW

PJO

Fig 19. Control byte format

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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27 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 18.

Control byte description

Bit

7

Symbol

CO

Value Description continue bit

6

5 to 0 -

RS

0

1

0

1 last control byte control bytes continue register selection command register data register not relevant

The command bytes and control bytes are also acknowledged by all addressed

PCA85233 connected to the bus.

The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated.

The acknowledgement after each byte is made only by the (A0 and A1) addressed

PCA85233. After the last display byte, the I 2 C-bus master issues a STOP condition (P).

Alternatively a START may be asserted to RESTART an I 2 C-bus access.

6$&/.6<1&26&

))$$7

9

/&'

%3%3%3

%36WR6

Fig 20. Device protection diagram

9

66

9

''

9

66

9

''

9

66

6&/6'$6'$$&.

9

66

9

/&'

9

66

DDD

PCA85233

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

28 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

10. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20

, IEC/ST 61340-5 , JESD625-A or equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V

LCD

) is on while the IC supply voltage (V

DD

) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, V

LCD

and V

DD

must be applied or removed together.

CAUTION

Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. The IC must be protected against light. The protection must be applied to all sides of the IC.

PCA85233

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

29 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

11. Limiting values

Table 19.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

I

I

I

O

I

DD

I

SS

V

DD

V

LCD

V i(n)

V o(n)

I

DD(LCD)

P tot

P/out

V

ESD

Parameter supply voltage

LCD supply voltage voltage on any input voltage on any output input current output current supply current ground supply current

LCD supply current total power dissipation power dissipation per output electrostatic discharge voltage

Conditions

V

V

DD

related inputs

LCD

HBM

related outputs

MM

I lu

T stg

T amb latch-up current storage temperature ambient temperature operating device

[2]

-

[3]

-

[4]

[5]

-

65

40

-

-

0.5

0.5

0.5

0.5

10

10

50

50

50

Min

+6.5

+9.0

+6.5

+9.0

+10

+10

+50

+50

+50

400

100

4000

Max

V

250

100

+150

+105

V mA

C

C

[1] Stresses above these values listed may cause permanent damage to the device.

[2]

Pass level; Human Body Model (HBM) according to Ref. 8 “JESD22-A114” .

[3] Pass level; Machine Model (MM), according to

Ref. 9 “JESD22-A115”

.

[4] Pass level; latch-up testing, according to

Ref. 10 “JESD78” at maximum ambient temperature (T

amb(max)

).

[5] According to the store and transport requirements (see

Ref. 13 “UM10569” ) the devices have to be stored at a temperature of +8

C to

+45

C and a humidity of 25 % to 75 %.

V mA mA mA

V

V

Unit

V mA mA mW mW

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

12. Static characteristics

Table 20.

Static characteristics

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 8.0 V; T amb

=

40

C to +105

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

Supplies

V

DD

V

LCD

I

DD

I

DD(LCD) supply voltage

LCD supply voltage supply current

LCD supply current

V

LCD

6.5 V

V

LCD

> 6.5 V

V

DD

< 2.5 V

V

DD

2.5 V f clk(ext)

= 1536 Hz;

V

DD

= 5.5 V; see

Figure 21

f clk(ext)

= 1536 Hz;

V

DD

= 5.5 V;V

LCD

= 8.0 V; see

Figure 21

2.5

[1]

-

2.5

[1]

-

1.8

2.5

-

-

-

-

3

22

5.5

5.5

6.5

8.0

6

45

Logic

V

I

V

IH

V

IL input voltage

HIGH-level input voltage

LOW-level input voltage on pins CLK, SYNC, OSC,

A0, A1, T1, SA0, FF on pins CLK, SYNC, OSC,

A0, A1, T1, SA0, FF

V

SS

0.5

-

0.7V

DD

-

V

SS

0.3V

DD

Unit

V

DD

+ 0.5

V

V

DD

V

V

V

V

V

A

A

V

V

OH

V

OL

I

OH

HIGH-level output voltage

-

0.8V

DD

1 -

-

-

-

0.2V

DD

V

V mA

I

OL

I

L

C

I

I 2

C-bus [2]

LOW-level output voltage

HIGH-level output current output source current; on pin CLK;

V

OH

= 4.6 V; V

DD

= 5 V

LOW-level output current output sink current; on pin CLK, SYNC;

V

OL

= 0.4 V; V

DD

= 5 V leakage current on pins OSC, CLK, SCL,

SDA, A0, A1, T1, SA0, FF;

V

I

= V

DD

or V

SS input capacitance

[3]

-

1

1

-

-

-

+1

7 mA

A pF

Input on pins SDA and SCL

V

I

V

IH

V

IL

C

I

I

OL(SDA) input voltage

HIGH-level input voltage

LOW-level input voltage input capacitance

LOW-level output current on pin SDA output sink current;

V

OL

= 0.4 V; V

DD

= 5 V

V

SS

0.5

-

0.7V

DD

-

[3]

-

V

SS

-

-

3 -

5.5

-

5.5

0.3V

DD

7

V

V

V pF mA

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

31 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 20.

Static characteristics …continued

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 8.0 V; T amb

=

40

C to +105

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

LCD outputs

V

O output voltage variation

100 +100

R

O output resistance on pins BP0 to BP3; C bpl

=

35 nF on pins S0 to S79; C sgm

= 5 nF

V

LCD

= 5 V on pins BP0 to BP3 on pins S0 to S79

[4]

-

[4]

-

100 -

1.5

6.0

+100

10

13.5

[1] LCD outputs are open-circuit; inputs at V

SS

or V

DD

; external clock with 50 % duty factor; I

2

C-bus inactive.

[2] The I

2

C-bus interface of PCA85233 is 5 V tolerant.

[3] Not tested, design specification only.

[4] Outputs measured individually and sequentially.

, ,

DDD

, ,

Unit mV mV k

 k

I

FONH[W

N+]

Conditions: V

DD

= 5.5 V; V

LCD

= 8 V; T amb

= 27

C; all RAM filled with 0.

(1) I

DD(LCD)

.

(2) I

DD

.

Fig 21. Current consumption with respect to external clock frequency

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

13. Dynamic characteristics

Table 21.

Dynamic characteristics

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 8.0 V; T amb

=

40

C to +105

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

Clock

Internal: output pin CLK f f clk fr clock frequency frame frequency

FF = V

DD

FF = V

SS

FF = V

DD

FF = V

SS

 f fr frame frequency variation FF = V

DD

; see

Figure 22

FF = V

SS

; see

Figure 22

External: input pin CLK t f clk(ext) t clk(H) external clock frequency

HIGH-level clock time t clk(L)

LOW-level clock time

Synchronization: input pin SYNC t t

PD(SYNC_N)

SYNC propagation delay

SYNC_NL

SYNC LOW time

Outputs: pins BP0 to BP3 and S0 to S79

V

LCD

= 5 V t

PD(drv) driver propagation delay

I 2 C-bus: timing

[3]

Pin SCL f

SCL t

HIGH

LOW

SCL clock frequency

HIGH period of the SCL clock

LOW period of the SCL clock

Pin SDA t

SU;DAT t

HD;DAT data set-up time data hold time

[1][2]

2630

[1][2]

3855

-

-

110

161

[2]

800

90

90

-

-

1

-

0.6

1.3

100

0

-

-

-

-

-

-

-

-

-

3600

5280

150

220

150

220

-

30

-

-

-

-

-

-

-

7000

30

-

400

4680

-

6865

-

195

286

Unit kHz

 s

 s ns ns ns

 s

 s

Hz

 s

 s

Hz

Hz

Hz

Hz

Hz

Hz

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

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33 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 21.

Dynamic characteristics …continued

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 8.0 V; T amb

=

40

C to +105

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max t t

Pins SCL and SDA t

BUF bus free time between a

STOP and START condition t

SU;STO

HD;STA set-up time for STOP condition hold time (repeated)

START condition t

SU;STA r set-up time for a repeated

START condition rise time of both SDA and

SCL signals t f

C b t w(spike) fall time of both SDA and

SCL signals capacitive load for each bus line spike pulse width f

SCL

= 400 kHz f

SCL

< 125 kHz on bus -

-

-

-

-

1.3

0.6

0.6

0.6

-

-

-

-

-

-

-

-

-

-

-

-

-

0.3

1.0

0.3

400

50

Unit

 s

 s

 s

 s

 s

 s

 s pF ns

[1] Typical output duty cycle of 50 %.

[2] The corresponding frame frequency is f fr

= f

--------

24

.

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V

IL

and V

IH

with an input voltage swing of V

SS

to V

DD

. For I 2 C-bus timings see

Figure 24

.

DDD

I I

PCA85233

Product data sheet

(1) V

DD

= 5.5 V; FF = V

SS

.

(2) V

DD

= 5.5 V; FF = V

DD

.

(3) V

DD

= 1.8 V; FF = V

SS

.

(4) V

DD

= 1.8 V; FF = V

DD

.

Fig 22. Frame frequency with respect to temperature

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Rev. 5 — 12 November 2018

7

DPE

ž&

© NXP B.V. 2018. All rights reserved.

34 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

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&/.

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9

''

9

''

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''

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3'GUY

Fig 23. Driver timing waveforms

W

6<1&B1/

9

9

''

9

9

DDJ

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W

/2:

W

I

6&/

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W

U

W

+''$7 W

+,*+

W

68'$7

6'$

W

6867$

W

68672

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Fig 24. I 2 C-bus timing waveforms

14. Application information

14.1 Cascaded operation

In large display configurations up to 8 PCA85233 can be recognized on the same I 2 C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable I 2 C-bus slave address (SA0).

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

35 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 22.

Addressing cascaded PCA85233

Cluster

1

Bit SA0

0

Pin A1

0

2 1

1

0

0

1

0

1

1

1

0

1

0

1

1

0

Pin A0

0

5

6

3

4

7

1

2

Device

0

When cascaded PCA85233 are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCA85233 of the cascade contribute additional segment outputs. The backplanes can either be connected together to enhance the drive capability or some can be left open-circuit (such as the ones from the slave in

Figure 25

) or just some of the master and some of the slave will be taken to facilitate the layout of the display.

PCA85233

Product data sheet

6'$$&.

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26&

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(1) Is master (OSC connected to V

SS

).

(2) Is slave (OSC connected to V

DD

).

Fig 25. Cascaded PCA85233 configuration

$ $ 7 6$ 9

66

EDFNSODQHV

%3WR%3

DDD

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

For display sizes that are not multiple of 320 segments/elements, a mixed cascaded system can be considered containing only devices like PCA85233 and PCA85132.

Depending on the application, one must take care of the software command and pin connection compatibility.

Only one master but multiple slaves are allowed in a cascade. All devices in the cascade have to use the same clock whether it is supplied externally or provided by the master.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85233. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by the definition of a multiplex drive mode when PCA85233 with different SA0 levels are cascaded).

SYNC is organized as an input/output pin; The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCA85233 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCA85233 to assert

SYNC. The timing relationships between the backplane waveforms and the SYNC signal

for the various drive modes of the PCA85233 are shown in Figure 26 .

7

IU

I

IU

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PCA85233

Product data sheet

%3

ELDV

6<1&

FPXOWLSOH[GULYHPRGH

%3

ELDV

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Fig 26. Synchronization of the cascade for the various PCA85233 drive modes

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Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

37 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, then the device will not be able to synchronize properly. This is particularly applicable to COG applications.

15. Test information

15.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications.

PCA85233

Product data sheet

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Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

38 of 54

NXP Semiconductors

16. Bare die outline

%DUHGLHEXPSV

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

3&$

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H

E

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'

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Fig 27. Bare die outline of PCA85233UG

PCA85233

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 November 2018

(XURSHDQ

SURMHFWLRQ

SFDBGR

,VVXHGDWH

© NXP B.V. 2018. All rights reserved.

39 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

PCA85233

Product data sheet

Table 23.

Dimensions of PCA85233UG

Original dimensions are in mm.

Unit (mm) max nom min

-

-

A

0.40

A

1

0.018

-

A

2

0.015

0.012

-

0.38

-

b

0.03

-

D

-

4.16

-

-

E

1.07

-

e

0.054

-

e

1

0.203

-

-

L

0.09

Table 24.

Bump locations of PCA85233UG

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see

Figure 27 .

Symbol Bump X (

 m)

SDAACK 1

Y (

 m)

1022.67

436.5

SDAACK

SDAACK

2

3

968.67

436.5

914.67

436.5

SDA

SDA

SDA

SCL

4

5

6

7

712.17

436.5

658.17

436.5

604.17

436.5

433.17

436.5

SCL

SCL

CLK

V

V

V

DD

DD

DD

SYNC

OSC

FF

A0

8

9

10

11

12

13

14

15

16

17

379.17

436.5

325.17

436.5

173.52

436.5

61.47

436.5

7.47

46.53

436.5

436.5

149.58

262.08

345.78

429.48

436.5

436.5

436.5

436.5

A1

T1

SA0

V

V

V

V

V

V

SS

SS

SS

LCD

LCD

LCD

BP2

BP0

S0

S1

S2

S3

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

513.18

596.88

680.58

765.63

436.5

436.5

436.5

436.5

819.63

873.63

436.5

436.5

979.83

436.5

1033.83

436.5

1087.83

436.5

1176.03

436.5

1230.03

436.5

1284.03

436.5

1338.03

436.5

1392.03

436.5

1446.03

436.5

[1]

[1]

I

I

I

I

Description

2

2

2 clock input/output supply voltage cascade synchronization input/output oscillator select frame frequency select subaddress input test pin

2

C-bus acknowledge output

C-bus serial data input

C-bus serial clock input

C-bus slave address input; bit 0 ground supply voltage

LCD supply voltage

LCD backplane output

LCD segment output

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40 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

S35

S36

S37

S38

S39

S40

S27

S28

S29

S30

S31

S32

S33

S34

64

65

66

67

68

69

60

61

62

63

56

57

58

59

S19

S20

S21

S22

S23

S24

S25

S26

Table 24.

Bump locations of PCA85233UG

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 27 .

Symbol Bump X (

 m)

S4 33

Y (

 m)

1500.03

436.5

S5

S6

S7

S8

34

35

36

37

1554.03

436.5

1608.03

436.5

1662.03

436.5

1716.03

436.5

S9

S10

S11

38

39

40

1770.03

436.5

1824.03

436.5

1878.03

436.5

Description

LCD segment output

S12 41 1423.53

436.5

S13

S14

42

43

1369.53

1315.53

436.5

436.5

S15

S16

S17

S18

44

45

46

47

1261.53

1207.53

1153.53

1099.53

436.5

436.5

436.5

436.5

48

49

50

51

52

53

54

55

1045.53

436.5

991.53

436.5

937.53

883.53

829.53

714.06

660.06

606.06

436.5

436.5

436.5

436.5

436.5

436.5

552.06

498.06

444.06

390.06

336.06

282.06

228.06

112.59

436.5

436.5

436.5

436.5

436.5

436.5

436.5

436.5

58.59

436.5

4.59

436.5

49.41

436.5

103.41

436.5

157.41

436.5

211.41

436.5

PCA85233

Product data sheet

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NXP Semiconductors

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Automotive 80 × 4 LCD driver for low multiplex rates

PCA85233

Product data sheet

Table 24.

Bump locations of PCA85233UG

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 27 .

Symbol Bump X (

 m)

S41 70

Y (

 m)

265.41

436.5

S42

S43

S44

S45

71

72

73

74

319.41

436.5

373.41

436.5

427.41

436.5

481.41

436.5

S46

S47

S48

S49

S50

S51

S52

S53

75

76

77

78

79

80

81

82

596.88

436.5

650.88

436.5

704.88

436.5

758.88

436.5

812.88

436.5

866.88

436.5

920.88

436.5

974.88

436.5

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S75

S76

S77

S78

S79

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

1028.88 436.5

1082.88 436.5

1136.88

436.5

1252.35 436.5

1306.35 436.5

1360.35 436.5

1414.35 436.5

1468.35 436.5

1522.35 436.5

1576.35 436.5

1630.35 436.5

1684.35 436.5

1738.35 436.5

1792.35 436.5

1876.05

436.5

1822.05

436.5

1768.05

436.5

1714.05

436.5

1660.05

436.5

1606.05

436.5

1552.05

436.5

1498.05

436.5

1444.05

436.5

1390.05

436.5

1336.05

436.5

1282.05

436.5

Description

LCD segment output

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

D4

D5

D6

D7

Table 24.

Bump locations of PCA85233UG

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 27 .

Symbol Bump X (

 m)

BP3 109

Y (

 m)

1228.05

436.5

BP1

D1 -

110

1174.05

436.5

1932.03

436.5

[2]

Description

LCD backplane output dummy pad

D2

D3

-

-

1909.53

1801.53

436.5

436.5

D8

D9

-

-

-

-

-

-

1693.53

436.5

1585.53

436.5

1477.53

436.5

1846.35 436.5

1953 436.5

1930.05

436.5

[1]

For most applications SDA and SDAACK are shorted together; see Section 8

.

[2] The dummy pads are connected to V

SS

but are not tested.

Table 25.

Gold bump hardness

Type number

PCA85233UG/2DA/Q1

Min

60

[1] Pressure of diamond head: 10 g to 50 g.

Max

120

Unit

HV

[1]

PCA85233

Product data sheet

5()

6

5()

&

DDK

The approximate positions of the alignment marks are shown in

Figure 27

.

Fig 28. Alignment marks of PCA85233

Table 26.

Alignment mark locations

All x/y coordinates represent the position of the REF point (see Figure 28

) with respect to the center

(x/y = 0) of the chip; see

Figure 27 .

Symbol

S1

C1

Size (

81

81

81

81 m) X (

 m)

1916.1

1855.8

Y (

 m)

45

45

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Automotive 80 × 4 LCD driver for low multiplex rates

17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A , IEC 61340-5 or equivalent standards.

18. Packing information

18.1 Packing information on the tray

$

+

$

%

$

[

;

GLH

.

) (

GHWDLO;

'

\

\

[

*

)

(

& 2

/

0

6(&7,21$$

<

1

GHWDLO<

'LPHQVLRQVLQPP DDD

Schematic drawing, not drawn to scale. Top side view. For dimensions, see

Table 27

. Tray has pockets on both, top side and bottom side. The IC is stored with the active side up. To get the active side down, turn the tray.

Fig 29. Tray details of PCA85233UG

PCA85233

Product data sheet

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NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Table 27.

Specification of 3 inch tray details

Tray details are shown in Figure 29

. Nominal values without production tolerances.

Tray details

Dimensions

A

6.0

B

2.5

C

4.26

Number of pockets

D

1.17

E

76.0

F

68.0

G

60.0

H

6.75

J

8.0

K L

62.5

4.2

x direction

11 y direction

26

M

2.6

N

3.2

O Unit

0.48

mm

SLQ

DDD

The orientation of the IC in a pocket with active side up is indicated by the position of pin 1 with respect to the chamfer on the upper left corner of the tray.

Fig 30. Die alignment in the tray

PCA85233

Product data sheet

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

19. Appendix

19.1 LCD segment driver selection

Table 28.

Selection of LCD segment drivers

Type name Number of elements at MUX

1:1 1:2 1:3 1:4 1:6 1:8 1:9

PCA8553DTT 40 80 120 160 -

PCA8546ATT -

PCA8546BTT -

-

-

-

-

176 -

176 -

PCA8547AHT 44 88 -

PCA8547BHT 44 88 -

176 -

176 -

PCF85134HL 60 120 180 240 -

PCA85134H 60 120 180 240 -

PCA8543AHL 60 120 -

PCF8545ATT -

PCF8545BTT -

PCF8536AT -

-

-

-

PCF8536BT

PCA8536AT

PCA8536BT

PCF8537AH

PCF8537BH

PCA8537AH

PCA8537BH

PCA9620H

PCA9620U

PCF8576DU

PCF8576EUG 40 80 120 160 -

PCA8576FUG 40 80 120 160 -

PCF85133U

PCA85133U

-

-

-

44

44

44

44

60

60 120 -

80

80

-

-

-

88

88

88

88

-

-

-

-

-

-

-

120 -

-

-

-

-

-

-

-

240 -

176 252 320 -

176 252 320 -

176 252 320 -

176 252 320 -

176 252 320 -

176 252 320 -

176 276 352 -

160 240 320 -

160 240 320 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

176 276 352 -

176 276 352 -

176 276 352 -

240 320 480 -

240 320 480 -

40 80 120 160 -

V

DD

(V) V

LCD

(V) f fr

(Hz)

1.8 to 5.5

1.8 to 5.5

32 to 256 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 6.5

82

1.8 to 5.5

2.5 to 8 82

2.5 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 5.5

60 to 300 [1]

1.8 to 5.5

2.5 to 5.5

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 9

60 to 300 [1]

2.5 to 5.5

2.5 to 9

60 to 300 [1]

2.5 to 5.5

2.5 to 9

60 to 300 [1]

1.8 to 5.5

2.5 to 6.5

77

1.8 to 5.5

2.5 to 6.5

77

1.8 to 5.5

2.5 to 8 200

1.8 to 5.5

2.5 to 6.5

82, 110 [2]

1.8 to 5.5

2.5 to 8

82, 110 [2]

V

LCD

(V) charge pump

N

N

N

Y

Y

N

N

Y

N

N

N

N

N

N

Y

Y

Y

Y

Y

Y

N

N

N

N

N

V

LCD

(V) temperature compensat.

T amb

(

C) Interface Package AEC-

Q100

N

N

N

Y

Y

N

N

Y

N

N

N

N

N

N

Y

Y

Y

Y

Y

Y

N

N

N

N

N

40 to 105 I 2 C / SPI TSSOP56 Y

40 to 95 I 2 C

40 to 95 SPI

TSSOP56

TSSOP56

Y

Y

40 to 95 I 2 C

40 to 95 SPI

40 to 85 I 2 C

40 to 95 I 2 C

TQFP64

TQFP64

LQFP80

LQFP80

Y

Y

N

Y

40 to 105 I 2 C

40 to 85 I 2 C

40 to 85 SPI

40 to 85 I 2 C

40 to 85 SPI

40 to 95 I 2 C

40 to 95 SPI

40 to 85 I 2 C

LQFP80

TSSOP56

TSSOP56

TSSOP56

TSSOP56

TSSOP56

TSSOP56

TQFP64

Y

N

N

N

N

Y

Y

N

40 to 85 SPI

40 to 95 I 2 C

40 to 95 SPI

40 to 105 I 2 C

40 to 105 I 2 C

40 to 85 I 2 C

40 to 85 I 2 C

40 to 105 I 2 C

40 to 85 I 2 C

40 to 95 I 2 C

TQFP64

TQFP64

TQFP64

LQFP80

Bare die

Bare die

Bare die

Bare die

Bare die

Bare die

N

Y

Y

Y

Y

N

N

Y

N

Y

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 28.

Selection of LCD segment drivers …continued

Type name Number of elements at MUX

1:1 1:2 1:3 1:4 1:6 1:8 1:9

V

DD

(V) V

LCD

(V) f fr

(Hz) V

LCD

(V) charge pump

V

LCD

(V) temperature compensat.

T amb

(

C) Interface Package AEC-

Q100

PCA85233UG 80 160 240 320 -

PCF85132U

PCA85132U

PCA85232U

PCF8538UG

PCA8538UG

160 320 480 640 -

PCA8530DUG 102 204 -

160 320 480 640 -

160 320 480 640 -

102 204 -

102 204 -

408 -

-

-

-

-

-

-

-

-

-

1.8 to 5.5

2.5 to 8 150, 220

[2]

1.8 to 5.5

1.8 to 8 60 to 90

[1]

2.5 to 5.5

4 to 12

408 612 816 918 2.5 to 5.5

4 to 12

408 612 816 918 2.5 to 5.5

4 to 12

45 to 300 [1]

1.8 to 5.5

1.8 to 8 60 to 90

[1]

1.8 to 5.5

1.8 to 8

117 to 176 [1]

45 to 300 [1]

45 to 300 [1]

N

N

Y

N

N

Y

Y

N

N

Y

N

N

Y

Y

40 to 105 I 2 C Bare die Y

40 to 85 I 2 C Bare die N

40 to 105 I 2 C / SPI Bare die Y

40 to 95 I 2 C

40 to 95 I 2 C

Bare die

Bare die

Y

Y

40 to 85 I 2 C / SPI Bare die N

40 to 105 I 2 C / SPI Bare die Y

[1] Software programmable.

[2] Hardware selectable.

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

20. Abbreviations

Table 29.

Abbreviations

Acronym Description

CMOS

COG

DC

HBM

I 2 C

IC

ITO

LCD

MM

RAM

RC

RMS

Complementary Metal-Oxide Semiconductor

Chip-On-Glass

Direct Current

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

Indium Tin Oxide

Liquid Crystal Display

Machine Model

Random Access Memory

Resistance-Capacitance

Root Mean Square

21. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers

[2] AN10706 — Handling bare die

[3] AN10853 — ESD and EMC sensitivity of IC

[4] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[5] AN11494 — Cascading NXP LCD segment drivers

[6] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices

[7] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[8] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[9] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[10] JESD78 — IC Latch-Up Test

[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[12] UM10204 — I 2 C-bus specification and user manual

[13] UM10569 — Store and transport requirements

PCA85233

Product data sheet

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Automotive 80 × 4 LCD driver for low multiplex rates

22. Revision history

Table 30.

Revision history

Document ID Release date

PCA85233 v.5

Modifications:

PCA85233 v.4

Modifications:

PCA85233 v.3

PCA85233 v.2

PCA85233 v.1

20181112

Updated

20150506

Product data sheet

Section 7.4 “Initialization”

Product data sheet

Added rear side laser marking

20140926

20140327

20130917

Data sheet status

Product data sheet

Product data sheet

Product data sheet

-

-

-

-

Change notice

201811011I

Supersedes

PCA85233 v.4

-

PCA85233 v.3

PCA85233 v.2

PCA85233 v.1

PCA85233

Product data sheet

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Automotive 80 × 4 LCD driver for low multiplex rates

23. Legal information

Document status

[1][2]

Product status

[3]

Objective [short] data sheet Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

23.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

23.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

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Product data sheet

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Automotive 80 × 4 LCD driver for low multiplex rates

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers.

24. Contact information

NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.

All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I

2

C-bus — logo is a trademark of NXP B.V.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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NXP Semiconductors

25. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description overview . . . . . . . . . . . . . . . . . .4

Table 5. Definition of commands . . . . . . . . . . . . . . . . . . .5

Table 6. Mode-set command bit description . . . . . . . . . .5

Table 7. Load-data-pointer command bit description . . .5

Table 8. Device-select command bit description . . . . . . .6

Table 9. Bank-select command bit description [1]

. . . . . . .6

Table 10. Blink-select command bit description . . . . . . . .6

Table 11. LCD frame frequencies . . . . . . . . . . . . . . . . . . .7

Table 12. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . . .8

Table 13. Standard RAM filling in 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 14. Entire RAM filling by rewriting in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 15. Selection of possible display configurations . . .14

Table 16. Biasing characteristics . . . . . . . . . . . . . . . . . . .15

Table 17. I 2

C slave address byte . . . . . . . . . . . . . . . . . . .26

Table 18. Control byte description . . . . . . . . . . . . . . . . . .28

Table 19. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 20. Static characteristics . . . . . . . . . . . . . . . . . . . .31

Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . . .33

Table 22. Addressing cascaded PCA85233 . . . . . . . . . .36

Table 23. Dimensions of PCA85233UG . . . . . . . . . . . . .40

Table 24. Bump locations of PCA85233UG . . . . . . . . . . .40

Table 25. Gold bump hardness . . . . . . . . . . . . . . . . . . . .43

Table 26. Alignment mark locations . . . . . . . . . . . . . . . .43

Table 27. Specification of 3 inch tray details. . . . . . . . . . .45

Table 28. Selection of LCD segment drivers . . . . . . . . . .46

Table 29. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 30. Revision history . . . . . . . . . . . . . . . . . . . . . . . .49

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

PCA85233

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

52 of 54

NXP Semiconductors

26. Figures

Fig 1. Rear side laser marking . . . . . . . . . . . . . . . . . . . . .2

Fig 2. Block diagram of PCA85233 . . . . . . . . . . . . . . . . .3

Fig 3. Pin configuration for PCA85233 . . . . . . . . . . . . . .4

Fig 4. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . .9

Fig 5. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I

2 C-bus . . . . . . . . . . . . . . . .10

Fig 6. Example of displays suitable for PCA85233 . . . .14

Fig 7. Typical system configuration . . . . . . . . . . . . . . . .15

Fig 8. Electro-optical characteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .17

Fig 9. Static drive mode waveforms . . . . . . . . . . . . . . . .18

Fig 10. Waveforms for the 1:2 multiplex drive mode with 1

2

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 11. Waveforms for the 1:2 multiplex drive mode with 1

3

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 12. Waveforms for the 1:3 multiplex drive mode with 1

3

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 13. Waveforms for the 1:4 multiplex drive mode with 1

3

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 14. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 15. Definition of START and STOP conditions. . . . . .25

Fig 16. System configuration . . . . . . . . . . . . . . . . . . . . . .25

Fig 17. Acknowledgement on the I 2

C-bus . . . . . . . . . . . .26

Fig 18. I

2 C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 19. Control byte format . . . . . . . . . . . . . . . . . . . . . . .27

Fig 20. Device protection diagram . . . . . . . . . . . . . . . . . .28

Fig 21. Current consumption with respect to external clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . .32

Fig 22. Frame frequency with respect to temperature . . .34

Fig 23. Driver timing waveforms . . . . . . . . . . . . . . . . . . .35

Fig 24. I

2 C-bus timing waveforms . . . . . . . . . . . . . . . . . .35

Fig 25. Cascaded PCA85233 configuration. . . . . . . . . . .36

Fig 26. Synchronization of the cascade for the various

PCA85233 drive modes . . . . . . . . . . . . . . . . . . . .37

Fig 27. Bare die outline of PCA85233UG . . . . . . . . . . . .39

Fig 28. Alignment marks of PCA85233 . . . . . . . . . . . . . .43

Fig 29. Tray details of PCA85233UG. . . . . . . . . . . . . . . .44

Fig 30. Die alignment in the tray . . . . . . . . . . . . . . . . . . .45

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

PCA85233

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 November 2018

© NXP B.V. 2018. All rights reserved.

53 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

27. Contents

1

2

3

3.1

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5

6

6.1

6.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.5

7.6

7.7

7.7.1

7.8

7.8.1

7.8.2

7.8.3

7.8.4

7.9

7.10

7.1

7.2

7.2.1

Commands of PCA85233 . . . . . . . . . . . . . . . . . 5

Clock and frame frequency. . . . . . . . . . . . . . . . 6

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.1.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.1.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.2

7.2.3

Frame frequency . . . . . . . . . . . . . . . . . . . . . . . 7

Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.4

Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Subaddress counter . . . . . . . . . . . . . . . . . . . . 11

RAM writing in 1:3 multiplex drive mode. . . . . 11

Writing over the RAM address boundary . . . . 12

Output bank selector . . . . . . . . . . . . . . . . . . . 12

Input bank selector . . . . . . . . . . . . . . . . . . . . . 13

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8

Possible display configurations . . . . . . . . . . . 14

LCD bias generator . . . . . . . . . . . . . . . . . . . . 15

LCD voltage selector . . . . . . . . . . . . . . . . . . . 15

Electro-optical performance . . . . . . . . . . . . . . 17

LCD drive mode waveforms . . . . . . . . . . . . . . 18

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 18

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 19

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 21

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 22

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 23

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 23

Characteristics of the I

2 C-bus . . . . . . . . . . . . 24

8.1

8.2

8.3

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

START and STOP conditions . . . . . . . . . . . . . 24

System configuration . . . . . . . . . . . . . . . . . . . 25

8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.5 I 2

C-bus controller . . . . . . . . . . . . . . . . . . . . . . 26

8.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.7 I 2

C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26

9

10

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28

Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

24

25

26

27

19

19.1

20

21

22

23

23.1

23.2

23.3

23.4

11

12

13

14

14.1

15

15.1

16

17

18

18.1

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 30

Static characteristics . . . . . . . . . . . . . . . . . . . 31

Dynamic characteristics. . . . . . . . . . . . . . . . . 33

Application information . . . . . . . . . . . . . . . . . 35

Cascaded operation. . . . . . . . . . . . . . . . . . . . 35

Test information . . . . . . . . . . . . . . . . . . . . . . . 38

Quality information . . . . . . . . . . . . . . . . . . . . . 38

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 39

Handling information . . . . . . . . . . . . . . . . . . . 44

Packing information . . . . . . . . . . . . . . . . . . . . 44

Packing information on the tray . . . . . . . . . . . 44

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

LCD segment driver selection . . . . . . . . . . . . 46

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Contact information . . . . . . . . . . . . . . . . . . . . 51

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2018.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 12 November 2018

Document identifier: PCA85233

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