NXP TEA19161T Resonant power supply control IC Data Sheet

NXP TEA19161T Resonant power supply control IC Data Sheet
TEA19161T/2
Digital controller for high-efficiency resonant power supply
Rev. 2 — 30 August 2019
1
Product data sheet
General description
The TEA19161T is a fully digital controller for high-efficiency resonant power supplies.
Together with the TEA19162T PFC controller and the TEA1995T dual SR controller, a
complete resonant power supply can be built which is easy to design and has a very low
component count. This power supply meets the efficiency regulations of Energy Star,
the Department of Energy (DoE), the Eco-design directive of the European Union, the
European Code of Conduct, and other guidelines. So, any auxiliary low-power supply can
be omitted.
In contrast to traditional resonant topologies, the TEA19161T (LLC) shows a high
efficiency at low loads due to the newly introduced low-power mode. This mode operates
in the power region between continuous switching (also called high-power mode) and
burst mode.
Because the TEA19161T is regulated via the primary capacitor voltage, it has accurate
information about the power delivered to the output. The measured output power
defines the mode of operation (burst mode, low-power mode or high-power mode). A
configuration pin can easily set the transition levels of the operating modes.
The TEA19161T contains a low-voltage die with a fully digital controller for output power
control, start-up, initializations, and protections. These protections include OverCurrent
Protection (OCP), OverVoltage Protection (OVP), Open-Loop Protection (OLP), and
Capacitive Mode Regulation (CMR). It also contains a high-voltage Silicon-On-Insulator
(SOI) controller for high-voltage start-up, integrated drivers, level shifter, protections, and
circuitry assuring zero-voltage switching.
The TEA19161T is designed to cooperate with the TEA19162T Power Factor Control
(PFC) controller. For communications about start-up and protections, the TEA19161T
contains a digital control interface. The digital control enables a fast latch reset
mechanism. It maximizes the overall system efficiency at low output power levels by
setting the TEA19162T to operate in burst mode.
The TEA19161T/TEA19162T/TEA1995T combination gives an easy to design, highly
efficient and reliable power supply, providing 90 W to 500 W, with a minimum of external
components. The system provides a very low no-load input power (< 75 mW; total
system including the TEA19161T/TEA19162T/TEA1995T combination) and high
efficiency from minimum to maximum load. So, any additional low-power supply can be
omitted, ensuring a significant system cost saving and highly simplified power supply
design.
TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
2
Features and benefits
2.1 Distinctive features
•
•
•
•
•
•
•
•
•
Complete functionality as a combination with TEA19162T
Integrated high-voltage start-up
Integrated high-voltage Level Shifter (LS)
Extremely fast start-up (< 500 ms at Vmains = 100 V (AC))
Continuously VSUPIC regulation via the SUPHV pin during start-up and protection,
allowing minimum SUPIC capacitor values
Operating frequencies are outside the audible area at all operating modes
Integrated soft start
Power good function
Maximum 500 kHz half-bridge switching frequency
2.2 Green features
• Extremely high efficiency from low load to high load
• Compliant with Energy using Product directive (EuP) lot 6
• Excellent no-load input power (< 75 mW for TEA19161T/TEA19162T/TEA1995T
combination)
• Regulated low optocurrent, enabling low no-load power consumption
• Very low supply current during non-switching state in burst mode
• Transition between different operation modes (high-power/low-power/burst mode)
occur at integrated, externally adjustable power levels
• Adaptive non-overlap time
2.3 Protection features
•
•
•
•
•
•
•
•
•
•
3
Supply UnderVoltage Protection (UVP)
OverPower Protection (OPP)
Integrated adjustable overpower time-out
Adjustable latch or restart function for OverPower Protection
On-chip OverTemperature Protection (OTP)
Capacitive Mode Regulation (CMR)
Accurate OverVoltage Protection (OVP)
Maximum on-time protection for low-side and high-side driver output
OverCurrent Protection (OCP)
Disable input
Applications
•
•
•
•
TEA19161T
Product data sheet
Desktop and all-in-one PCs
LCD television
Notebook adapter
Printers
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TEA19161T/2
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Digital controller for high-efficiency resonant power supply
4
Ordering information
Table 1. Ordering information
Type number
Package
TEA19161T/2
5
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Marking
Table 2. Marking codes
6
Type number
Marking code
TEA19161T/2
TEA19161T
Block diagram
SUPHV
I
SUPIC
SUPREG
11 V
SETTINGS
CONTROL
SNSOUT
CONTROL
SUPPLY
supic_charge
internal supplies
setting
UVPSUPREG
SNSSET
I
setting
SNSOUT
UVPSUPIC
I
SUPHS
CONTROL
LOGIC
SOFT START
PFC CONTROL
DRIVERS
A/D
IC
GateHS
setting
PFC burst
POWER
CONTROL
SNSBOOST
PFC protection
start-up
GATEHS
SUPREG
GateLS
Vhs(SNSCAP)
Vls(SNSCAP)
V
LS
GATELS
SWITCHING CONTROL
GateHS
I
GateLS
FEEDBACK CONTROL
OPERATION MODE
1:1
A/D
2.5 V + VT
12 kΩ
1.02 V
1.27 V
2.4 V
SWITCHING
STATE
MACHINE
low-power
mode
P
Plowpwr
s
r
q
#BURSTCYCLES
burst-on
I
Ibias(SNSCAP)
OTP
SNSFB
SNSCAP
VALLEY/
PEAK
DETECT
OCP
/
CMR
/
HB
= 1.5 V
= 0.1 V
SNSCUR
60 kΩ
2.5 V
aaa-017285
Figure 1. Block diagram
TEA19161T
Product data sheet
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TEA19161T/2
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Digital controller for high-efficiency resonant power supply
7
Pinning information
7.1 Pinning
SUPIC
1
16 SNSBOOST
SNSFB
2
15 SNSCAP
SNSOUT
3
14 SNSCUR
GND
4
SUPREG
5
GATELS
6
11 HB
n.c.
7
10 SUPHS
SUPHV
8
IC
13 SNSSET
12 n.c.
9
GATEHS
aaa-017286
Figure 2. TEA19161T pin configuration (SOT109-1)
7.2 Pin description
Table 3. Pin description
TEA19161T
Product data sheet
Symbol
Pin Description
SUPIC
1
input supply voltage and output of internal HV start-up source; externally
connected to an auxiliary winding of the LLC via a diode or to an external DC
supply
SNSFB
2
output voltage regulation feedback sense input; externally connected to an
optocoupler
SNSOUT
3
sense input for setting the burst frequency and monitoring the LLC output
voltage; externally via a resistive divider and a diode connected to the
auxiliary winding
GND
4
ground
SUPREG
5
regulated SUPREG IC supply; internal regulator output; input for drivers;
externally connected to SUPREG buffer capacitor
GATELS
6
LLC low-side MOSFET gate driver output
n.c.
7
not connected
SUPHV
8
internal HV start-up source high-voltage supply input; externally connected to
(PFC) boost voltage
GATEHS
9
LLC high-side MOSFET gate driver output
SUPHS
10
high-side driver supply input; externally connected to bootstrap capacitor
(CSUPHS)
HB
11
low-level reference for high-side driver and input for half-bridge slope
detection; externally connected to half-bridge node HB between the LLC
MOSFETs
n.c.
12
not connected
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Digital controller for high-efficiency resonant power supply
8
Symbol
Pin Description
SNSSET
13
settings for transition levels high/low power mode and low-power/burst mode,
overpower level,overpower time-out, and restart or latched. Output of the
power good signal.
SNSCUR
14
LLC current sense input; externally connected to the resonant current sense
resistor
SNSCAP
15
LLC capacitor voltage sense input; externally connected to divider across
LLC capacitor
SNSBOOST
16
sense input for boost voltage; output for PFC burst control; externally
connected to resistive divided boost voltage
Functional description
8.1 Supply voltages
The TEA19161T includes:
•
•
•
•
A high-voltage supply pin for start-up (SUPHV)
A general supply to be connected to an external auxiliary winding (SUPIC pin)
An accurate regulated voltage (SUPREG pin)
A floating supply for the high-side driver (SUPHS pin)
8.1.1 Start-up and supply voltage
Initially, the capacitors on the SUPIC and SUPREG pins are charged via the SUPHV
pin. The SUPHV pin is connected to the output voltage of a PFC via an external resistor.
Internally, a high-voltage series switch is located between the SUPHV and SUPIC pins.
From the SUPIC pin, the SUPREG pin is supplied using a linear regulator (see Figure 3).
Vboost
RSUPHV
SUPHV
current
limiter
Vrst(SUPIC)
supic_charge
SUPIC
CSUPIC
Vintregd(SUPREG)
SUPREG
IC
CSUPREG
aaa-017751
Figure 3. HV start-up
TEA19161T
Product data sheet
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Digital controller for high-efficiency resonant power supply
Initially, when the voltage on the SUPIC pin is below the reset level VrstSUPIC) (3.5 V),
the SUPIC charge current is internally limited to Ilim(SUPHV) (0.75 mA). In this way, the
dissipation is limited when SUPIC is shorted to ground. When the voltage on the SUPIC
pin exceeds Vrst(SUPIC), the internal switch is closed.
To limit the IC power dissipation, an external resistor (RSUPHV) is required to reduce the
voltage drop between the SUPHV and SUPIC pins when charging the SUPIC capacitor.
RSUPHV must be dimensioned such that the maximum current is limited to below limiting
value ISUPHV (20 mA) and it can handle the required power dissipation. The maximum
power dissipation of the external resistor can be reduced by using several resistors in
series.
When the SUPIC reaches the Vstart(SUPIC) level (19.1 V), it is continuously regulated
to this start level with a hysteresis (Vstart(hys)SUPIC; −0.7 V). It activates the switch
between the SUPHV and SUPIC pins when the SUPIC voltage drops to below
Vstart(SUPIC) + Vstart(hys)SUPIC. It deactivates the switch when it exceeds Vstart(SUPIC). When
start-up is complete and the LLC controller is operating, the LLC transformer auxiliary
winding supplies the SUPIC pin. In this operational state, the HV start-up source is
disabled (see Figure 4).
When the system enters the protection mode, the SUPIC pin is also regulated to the
start level. During the non-switching period of the burst mode, the system also activates
the switch between the SUPHV and SUPIC pins when the SUPIC voltage drops below
Vlow(SUPIC). It regulates the voltage with a hysteresis of Vlow(hys)SUPIC. In this way, the
system avoids that the SUPIC undervoltage protection (Vuvp(SUPIC)) is triggered because
of a long non-switching period in burst mode.
TEA19161T
Product data sheet
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Digital controller for high-efficiency resonant power supply
on
supic_charge
lSUPIC
off
< 20 mA
llim(SUPHV)
Vstart(SUPIC)
Vstart(hys)SUPIC
VSUPIC
Vrst(SUPIC)
on
pulldown_snsboost
off
Vstart(SNSBOOST)
ISNSFB > Ireg(SNSFB)
SNSBOOST
Vout
mode of operation
no supply
readout settings
PFC start-up
LLC start-up
operating
aaa-017753
Figure 4. Start-up sequence and normal operation
8.1.2 Regulated supply (SUPREG pin)
The voltage range on the SUPIC pin exceeds that of the maximum external MOSFETs
gate-source voltage. So, the TEA19161T incorporates an integrated series stabilizer.
The series stabilizer creates an accurate regulated voltage (Vintregd(SUPREG) = 11 V) at the
buffer capacitor CSUPREG. The stabilized voltage is used to:
• Supply the internal low-side LLC driver
• Supply the internal high-side driver using external components
• As a reference voltage for optional external circuits
To ensure that the external MOSFETs receive sufficient gate drive, the voltage on the
SUPREG pin must reach Vuvp(SUPREG) before the system starts switching. If the SUPREG
voltage drops to below this undervoltage protection level, the system restarts.
TEA19161T
Product data sheet
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NXP Semiconductors
Digital controller for high-efficiency resonant power supply
8.1.3 High-side driver floating supply (SUPHS pin)
External bootstrap buffer capacitor CSUPHS supplies the high-side driver. The bootstrap
capacitor is connected between the high-side driver supply, the SUPHS pin, and the
half-bridge node, HB. CSUPHS is charged from the SUPREG pin using an external diode
DSUPHS (see Figure 27).
Careful selection of the appropriate diode minimizes the voltage drop between the
SUPREG and SUPHS pins, especially when large MOSFETs and high switching
frequencies are used. A large voltage drop across the diode reduces the gate drive of the
high-side MOSFET.
8.2 System start-up
Figure 5 shows the flow diagram corresponding with Figure 4.
VSUPIC < Vuvp(SUPIC) or
VSUPREG < Vuvp(SUPREG)
NO SUPPLY
VSUPIC > Vstart(SUPIC) and
VSUPREG > Vuvp(SUPREG)
PFC disabled
via SNSBOOST
READOUT
SETTINGS
all settings defined
SUPIC regulated
via SUPHV
PFC START-UP
VSNSBOOST > Vstart(SNSBOOST)
LLC START-UP
ISNSFB > Ireg(SNSFB)
OPERATING
aaa-017754
Figure 5. LLC controller flow diagram
When the SUPIC or SUPREG pins drop to below their stop levels, the TEA19161T enters
the no supply state. It recharges the SUPIC and SUPREG pins to their start levels via the
SUPHV pin. When the start levels are reached, measuring the external resistances on
the SNSSET, SNSOUT, and GATELS pins initializes the settings.
During the no supply and readout settings states, the SNSBOOST pin is pulled low,
disabling the TEA19162T PFC. When the settings have been defined, the SNSBOOST
pin is released and the PFC starts up. When the SNSBOOST reaches the minimum level
Vstart(SNSBOOST), the LLC starts switching.
TEA19161T
Product data sheet
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TEA19161T/2
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Digital controller for high-efficiency resonant power supply
When a small optocurrent is detected (ISNSFB < Ireg(SNSFB)), the output voltage is close
to its regulation level. As the SUPIC pin must then be supplied via the primary auxiliary
winding, charging via the SUPHV is disabled.
8.3 LLC system regulation
A typical resonant controller regulates the output power by adapting the operating
frequency.
Vboost
trafo model
GATEHS
LS
D2
Vout
Ls
Lm
FREQUENCY CONTROL
GATELS
frequency
D1
fmax
Cr
fmin
SUPREG
VSNSFB
SNSFB
SNSBURST
3.5 V
aaa-017755
Figure 6. Resonant frequency controller
If the power drops and so the voltage of the LLC converter exceeds the targeted
regulation level (12 V or 19.5 V typical), the optocurrent increases and the voltage at the
SNSFB decreases (see Figure 6). The resonant controller then increases the frequency
according to its internal frequency control curve. Because of the higher frequency,
the power to the output is reduced and the output voltage drops. If the output voltage
becomes too low, the controller lowers the system frequency, increasing the output
power. In this way, the system regulates the output power to the required level.
As a small change in frequency gives a significant change in output power, frequency
control has a high gain of the control loop. To increase the efficiency at low loads, most
converters switch to burst mode as soon as the output power is below a minimum level.
The burst mode level is mostly derived from the voltage on the SNSFB pin. For a
frequency controlled resonant converter, it implies that the burst mode is entered
at a certain frequency instead of at a certain load. A small variation of the resonant
components then results in a significant variation in power level at which the burst mode
is activated.
In the TEA19161T, the control mechanism is different. The advantage is a constant
gain of the control loop and a burst mode which is derived from the output power. The
TEA19161T does not regulate the output power by adjusting the frequency but by the
voltage across the primary capacitor.
TEA19161T
Product data sheet
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Digital controller for high-efficiency resonant power supply
The input power (related to the output power) of a resonant converter can be calculated
with Equation 1:
(1)
Equation 1 shows that the input power has a linear relationship with the capacitor voltage
difference ΔVCr.
Figure 7 shows an alternative explanation of the linear relationship between the input
power and the energy stored in the resonant capacitor.
Vboost
Vout
GATEHS
HB
Ls
Lm
GATELS
Cr
aaa-017289
Figure 7. Linear relationship between input power and energy stored in Cr
When the high-side switch is on, a primary current is flowing through the transformer
and resonant capacitor Cr as indicated by the red line. Half the energy the input delivers
is transferred to the output. The other half charges resonant capacitor Cr. The voltage
across the resonant capacitor increases.
When the high-side switch is off and the low-side switch is on, the energy which is stored
in resonant capacitor Cr is transferred to the output and its voltage decreases. In this
way, the linear relationship between the increase of the resonant capacitor voltage and
the output power can be seen.
Although the TEA19161T uses the primary capacitor voltage as a regulation parameter,
all application values, like the resonant inductances, resonant capacitor, and primary
MOSFETs remain unchanged compared to a frequency controlled LLC converter. A
secondary TL431 circuitry in combination with an optocoupler connected to the primary
SNSFB pin continuously regulates the output voltage.
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
8.3.1 Output power regulation loop
Figure 8 shows the output power regulation loop of Vcap control as used by the
TEA19161T. Figure 9 shows a corresponding timing diagram.
Vboost
IC
GATEHS
LS
trafo model
D2
Vout
Ls
Lm
Vcap CONTROL
VSNSCAP
burst
GATELS
D1
Vhs(SNSCAP)
Vls(SNSCAP)
Iburst
q
s
qn r
ISNSFB
Vhs(SNSCAP)
SNSCAP
Vls(SNSCAP)
ISNSFB
Cr
SNSFB
2.5 V
aaa-017290
Figure 8. Regulation loop Vcap control
Iload
Ireg(SNSFB) (85 µA)
ISNSFB
Vhs(SNSCAP)
VSNSCAP
Vls(SNSCAP)
t
GATEHS
GATELS
t1
t2
aaa-017291
Figure 9. Timing diagram of the regulation loop
When the divided resonant capacitor voltage (VSNSCAP) exceeds the capacitor voltage
high level (Vhs(SNSCAP)), the high-side MOSFET is switched off (see Figure 9 (t1). After a
short delay, the low-side MOSFET is switched on. Because of the resonant current, the
resonant capacitor voltage initially increases further but eventually drops.
TEA19161T
Product data sheet
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Digital controller for high-efficiency resonant power supply
When the divided capacitor voltage (VSNSCAP) drops to below the capacitor voltage
low level (Vls(SNSCAP)), the low-side MOSFET is switched off (see Figure 9 (t2)). After a
short delay, the high-side MOSFET is switched on. Figure 9 shows that the switching
frequency is a result of this switching behavior. In a frequency controlled system, the
frequency is a control parameter and the output power is a result. The TEA19161T
regulates the power and the frequency is a result.
The difference between the high and low capacitor voltage level is a measure of the
delivered output power. The value of the primary optocurrent, defined by the secondary
TL431 circuitry, determines the difference between the high and low capacitor voltages.
Figure 9 also shows the behavior at a transient. If the output load increases, the current
pulled out of the SNSFB pin decreases. The result is that the TEA19161T increases the
high-level capacitor voltage and lowers the low-level capacitor voltage. According to
Equation 1 in Section 8.3, the output power increases and eventually the output voltage
increases to its regulation level.
To minimize no-load input power of the system, the primary current into the optocoupler
is continuously regulated to 85 μA (see Section 8.5).
8.3.2 Output voltage start-up
The system controls the output power by regulating the primary VCr (see Section 8.3).
When the system is in regulation and the output voltage is stabilized, a small change in
ΔVCr corresponds to a small change in the output current (see Equation 2).
(2)
However, before start-up, when the output voltage is around zero, a small capacitor
voltage increase (ΔVCr) corresponds to a substantial output current increase. So, at startup, the divided ΔVCr voltage (ΔVSNSCAP) is slowly increased from a minimum value to the
regulation level. As a result, the system starts up at a higher frequency. The GATELS
resistor sets the starting value of the ΔVSNSCAP.
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
8.4 Modes of operation
Figure 10 shows the control curve between the output power and the voltage difference
between the high and low capacitor voltage levels.
VSNSCAP CONTROL
VSNSCAP
Vhs(SNSCAP)
VSNSCAP
Vls(SNSCAP)
burst
mode
low-power
mode
high-power
mode
Pout(max)
Pt(lp)
low-power period
1/flp(min)
tlp
2.25/fr
Pout
Pout(max)
aaa-017757
Figure 10. TEA19161T control curve
When the output power (Pout) is at its maximum, the low capacitor voltage level
(Vls(SNSCAP)) is at its minimum and the high capacitor voltage (Vhs(SNSCAP))
is at its maximum level. According to Equation 1, the maximum ΔVSNSCAP
(Vhs(SNSCAP) − Vls(SNSCAP)), which is the divided ΔVCr voltage, corresponds to the
maximum output power.
When the output load decreases, the ΔVSNSCAP voltage decreases. As a result, the
output power decreases and the output voltage is regulated. This mode is called highpower mode.
When the output power drops to below the transition level (Pt(lp)), the system enters the
low-power mode. External components can set the applied Pt(lp) level (see Section 8.7.3).
To compensate for the hold period, ΔVSNSCAP is initially increased at entering the
low-power mode (see Section 8.4.2). In low-power mode, the output power is initially
regulated by adapting ΔVSNSCAP, until it reaches a minimum. Then, the output power is
regulated by lowering the duty cycle of the low-power mode with a fixed ΔVSNSCAP until
the period time of a low-power cycle reaches a maximum (1 / flp(min)). The system enters
the burst mode (see Section 8.4.3).
TEA19161T
Product data sheet
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Digital controller for high-efficiency resonant power supply
8.4.1 High-power mode
In high-power mode, the system operates as described in Section 8.3.1. Figure 11 shows
a flow diagram of the high-power mode.
System off
GATELS = on/GATEHS = off
t > ton(min)
VSNSCAP < Vls(SNSCAP)
lprim < -locp
lprim > -lreg(capm)
t > ton(max)
GATELS = off/GATEHS = off
t > tno(min)
lprim ≤ 0
End of HB slope
t > tno(max)
GATELS = off/GATEHS = on
t > ton(min)
VSNSCAP > Vhs(SNSCAP)
lprim > locp
lprim < lreg(capm)
t > ton(max)
GATELS = off/GATEHS = off
t > tno(min)
lprim ≤ 0
End of HB slope
t > tno(max)
explanation flow diagram
settings
exit condition 1
exit condition 2a
exit condition 2b
exit condition 2c
exit condition 2d
settings: actions taken when the system is in this state
exit condition: exit condition 1 has to be fulfilled and one of
the exit conditions 2x
aaa-017758
Figure 11. High-power mode flow diagram
TEA19161T
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Digital controller for high-efficiency resonant power supply
When the system is off, GATELS is on and GATEHS is off. The external bootstrap
buffer capacitor (CSUPHS) is charged via the SUPREG pin and an external diode. The
system remains in this state for at least the minimum on-time (ton(min)) of GATELS. Before
entering the next state, one of the following conditions must be fulfilled:
•
•
•
•
The VSNSCAP voltage drops to below the minimum VSNSCAP voltage (Vls(SNSCAP))
The measured current exceeds the OCP level (see Section 8.6.6)
The system is close to capacitive mode (see Section 8.6.5)
The maximum on-time (ton(max)), a protection that maximizes the time the high-side or
low-side MOSFET is kept on, is exceeded.
In the next state, to avoid false detection of the HB peak voltage, the system waits until
the minimum non-overlap time (tno(min)) is exceeded. When it is exceeded, the system
starts to detect the end (= peak voltage) of the HB node. When it detects the peak of
the HB node and the measured resonant current is negative (or zero), it enters the next
state.
If the system does not detect a peak at the HB node, it also enters the next state when
the maximum non-overlap time (tno(max)) is exceeded under the condition of a negative
(or zero) resonant current.
Finally, the third and fourth states (see Figure 11) describe the GATEHS and GATEHS to
GATELS transition criteria which are the inverse of the first two states.
8.4.2 Low-power mode
At low loads, the operating frequency of a resonant converter increases. As a result,
the magnetization and switching losses increase. For this reason, the efficiency of a
resonant converter drops at low loads. A newly introduced low-power mode ensures high
efficiency at lower loads as well.
When the output power drops to below the Pt(lp) level, the system enters the low-power
mode (see Figure 10 and Figure 12). It continues switching for 3 half-cycles (low-side,
high-side, low-side) with a fixed duty cycle of 67 %. To ensure a constant output power
level, it increases the energy per cycle (Vhs(SNSCAP) − Vls(SNSCAP)) at the same time. So
1/3 of the time the converter is in a "hold" period. The result is a 33 % magnetization and
switching losses reduction.
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Digital controller for high-efficiency resonant power supply
Iload
high-power mode
low-power mode
Vhs(SNSCAP)
VSNSCAP
VSNSCAP
Vls(SNSCAP)
3 half-cycles
hold
period
tlp
ID1
ID2
aaa-017765
Figure 12. Timing diagram transition high-power to low-power mode
As the system continuously tracks the primary capacitor voltage, it knows exactly when
to enter the "hold" period. It can also continue again at exactly the correct voltage and
current levels of the resonant converter. In this way, a "hold" period can be introduced
which reduces the magnetization and switching losses without any additional losses. The
currents ID1 and ID2 (see Figure 12) are the secondary currents through diodes D1 and
D2 (see Figure 27).
When in the low-power mode the output power is further reduced, the amount of energy
per cycle (= ΔVSNSCAP) is reduced and the duty cycle remains the same (see Figure 13).
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Digital controller for high-efficiency resonant power supply
Iload
Vhs(SNSCAP)
VSNSCAP
Vls(SNSCAP)
ID1
ID2
aaa-017766
Figure 13. Low-power mode: Lowering the energy-per-cycle (ΔVSNCAP)
When, in low-power mode, the minimum energy per cycle is reached, the duty cycle
regulates the output power (see Figure 14). Increasing the "hold" period lowers the duty
cycle.
Iload
Vhs(SNSCAP)
VSNSCAP
Vls(SNSCAP)
ID1
ID2
aaa-017767
Figure 14. Low-power mode: lowering the duty cycle
To avoid audible noise, the system reduces the duty cycle until the frequency reaches
flp(min) (23 kHz). If the output power is lowered further, the system enters the burst mode.
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8.4.3 Burst mode
In burst mode, the system alternates between operating in low-power mode and an
extended hold state (see Figure 15). Because of this additional extended hold period, the
magnetization and switching losses are further reduced. So, the efficiency of the system
is increased.
Figure 15 shows that all operating frequencies are outside the audible area. The
minimum low-power frequency is 23 kHz. Within a low-power period, the system is
switching at the resonant frequency of the converter, which is typically between 50 kHz
and 200 kHz.
low-power
hold
low-power
hold
hold
ISNSFB
106 µA
burst-on
Isec
tlp
Tburst
aaa-017768
Figure 15. Burst mode
The burst frequency (1 / tburst) is continuously regulated to a predefined value, which can
be set externally to 200 Hz, 400 Hz, 800 Hz or 1600 Hz. Isec is the secondary current
flowing through either diode D1 or D2 (see Figure 27).
When the primary optocurrent (ISNSFB) drops to below 106 μA, a new burst-on period is
started. The end of the burst-on period depends on the calculated number of low-power
cycles. The number of low-power cycles within a burst-on is continuously adjusted so that
the burst period is at least the period defined by the setting (see Figure 16).
Iload
ISNSFB
106 µA
burst-on
Isec
Tburst
<<Tburst
t1
<Tburst
t2
Tburst
t3
t4
aaa-017769
Figure 16. Burst mode: Regulating the number of low-power cycles
The system continuously measures the burst period from the start of the previous burston period to a new burst-on period. At t1, the measured burst period (tburst) equals the
required Tburst. So, the next number of low-power cycles equals the number of previous
low-power cycles. At a constant output power, the system expects that when the next
burst-on period has the same number of low-power cycles as the previous burst-on
period, the burst period (tburst) remains constant.
At a positive transient (t2), a new low-power cycle is started immediately to minimize the
drop in output voltage. The measured time period, at time t2, is below the targeted burst
period. The system increases the number of burst cycles. At t3, it measures the burst
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period again. In this example, the burst period is still below the targeted burst period.
So, the system increases the number of low-power cycles again and again until the
measured burst period equals the target burst period, which occurs at t4.
8.5 Optobias regulation
In a typical application, the output voltage is sensed using a TL431 and connected to
the SNSFB pin of the TEA19161T via an optocoupler (see Figure 27). Because of the
behavior of the TL431, the current through the optocoupler is at the maximum level
when the output power is at the minimum level. It is therefore one of the most critical
parameters to achieve the required no-load input power. To achieve maximum efficiency
at low load/no-load, the TEA19161T continuously regulates the optocurrent to a low level
that is independent of the output load.
A very low optocurrent reduces the transient response of the system, because of the
parasitic capacitance at the optocoupler collector. So, the TEA19161T applies a fixed
voltage at the SNSFB pin. It measures the current through the optocoupler which defines
the required output power. Via an additional internal circuitry, which adds an offset to the
required output power, the optocurrent is continuously (slowly) regulated to the Ireg(SNSFB)
level (= 85 μA). This level is independent of the output power.
At a positive load transient, the optocurrent initially decreases (see Figure 9; ISNSFB).
The TEA19161T immediately increases the ΔVSNSCAP which again increases the output
power.
FEEDBACK CONTROL
A/D
25 V + VT
12 kΩ
P
VSNSCAP
1.02 V
SNSFB
aaa-017770
Figure 17. Optobias regulation
Figure 17 shows that when the optocurrent decreases, the internal voltage across
the 12 kΩ resistor drops to below the targeted level of 1020 mV (= 85 μA × 12 kΩ).
The TEA19161T then slowly increases an additional offset at the power level (ΔP). It
continues to increase the additional offset until the optocurrent reaches the target of
85 μA. At a negative transient, the additional offset to the power level is decreased. As a
result, the output voltage increases which again increases the optocurrent. In this way,
the optocurrent is continuously regulated to the Ireg(SNSFB) level (see Figure 9).
The behavior of the internal circuitry connected to the SNSFB pin is the same as
the behavior of the traditional circuitry. The fixed voltage at the SNSFB pin and the
continuous regulation of the optocurrent level does not influence the regulation level. The
advantage, however, is a reduction in no-load input power and an optimization of the
transient response.
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Digital controller for high-efficiency resonant power supply
When the system operates in low-power mode at the minimum energy per cycle and
at minimum duty cycle, it can no longer reduce the optocurrent level to the Ireg(SNSFB)
target (» 85 μA). If the output power decreases further and the optocurrent increases
to above the level of Istart(burst) (» 106 μA), the burst mode is triggered. When the output
power drops to below this level again, a new burst cycle is started (see Figure 15 and
Figure 16).
8.6 Protections
Table 4 gives an overview of the available protections.
Table 4. Protections overview
Protection
Description
Action
PFC
UVP SUPIC/
SUPREG
undervoltage protection SUPIC/
SUPREG pins
LLC = off; recharge via SUPHV;
restart when VSUPIC > Vstart(SUPIC)
and VSUPREG > Vstart(SUPREG)
off
UVP SUPHS
undervoltage protection SUPHS
pin
GATEHS = off
UVP SNSBOOST undervoltage protection boost
LLC = off; restart when
VSNSBOOST > Vstart(SNSBOOST)
OVP output
overvoltage protection output
latched after 5 consecutive cycles
CMR
capacitive mode regulation
system ensures that mode of
operation is inductive
OCP
overcurrent protection
switch off cycle-by-cycle; After 5
consecutive cycles, it follows the
[2]
OPP setting.
OTP
overtemperature protection
latched
off
Latched implies that the system only
restarts after a mains disconnection.
OPP
overpower protection
latched
off
Latched implies that the system only
restarts after a mains disconnection.
[3]
/safe restart
[1]
[2]
[3]
[2]
[1]
off
off
Can be longer due to the sharing of the internal ADC converter.
Latched implies that the system only restarts after a mains disconnection.
Can be set by external components.
When the system is in a latched or safe restart protection, the SUPIC voltage is regulated
to its start level via the SUPHV pin.
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8.6.1 Undervoltage protection SUPIC/SUPREG
When the voltage on the SUPIC pin or the SUPREG pin is below its undervoltage
level Vuvp(SUPIC) / Vuvp(SUPREG), the LLC converter stops switching. The capacitors at
the SUPIC and SUPREG pins are recharged via the SUPHV pin (see Figure 5). The
SNSBOOST pin is pulled low, disabling the PFC. When the supply voltages exceed their
start levels, the system restarts.
8.6.2 Undervoltage protection SUPHS
To ensure a minimum drive voltage at the high-side driver output (GATEHS), this driver is
kept off when its voltage is below the minimum level (VSUPHS < Vrst(SUPHS)).
8.6.3 Undervoltage protection boost
The PFC output voltage is measured via a resistive divider connected to the
SNSBOOST pin. The voltage at the SNSBOOST pin must exceed the start level
(VSNSBOOST > Vstart(SNSBOOST)) before the system is allowed to start switching.
When the system is operating and the voltage at the SNSBOOST pin drops to below the
minimum level (VSNSBOOST < Vuvp(SNSBOOST)), the LLC converter stops switching. When it
exceeds the start level, it restarts.
8.6.4 Overvoltage protection
When the voltage at the SNSOUT pin exceeds the Vovp(SNSOUT) level for at least 5
consecutive switching cycles, the OVP protection is triggered. The voltage at the
SNSOUT pin is internally measured via an ADC converter. As the same ADC converter
toggles between measuring the SNSOUT and SNSBOOST pins (see Figure 1), there is
an additional delay before the OVP is triggered. OVP is a latched protection. The PFC is
disabled via the SNSBOOST pin.
8.6.5 Capacitive Mode Regulation (CMR)
The TEA19161T has a Capacitive Mode Regulation (CMR) which ensures that the
system is always operating in inductive mode and avoids operation in capacitive mode.
At lower input voltage or higher output power and depending on the resonant design, the
resonant current can already approach zero before the capacitor voltage reaches the
regulation level.
When the resonant current has changed polarity before the switches are turned off and
the other switch is turned on, hard switching occurs. This event is called capacitive mode.
To avoid that the system operates in capacitive mode, the system also switches off the
high-side/low-side switch when the resonant current approaches zero.
Figure 18 shows the signals that occur when a resonant converter is switching in
CMR mode. At t1 (and also at t3), the low-side switch is on while the resonant current
approaches zero before VSNSCAP reaches Vls(SNSCAP). At t2, the resonant current is also
close to changing polarity while the divided capacitor voltage (VSNSCAP) has not reached
the Vhs(SNSCAP) level yet. To avoid a turn-off of the high-side switch at a negative current
or the low-side at a positive current, the system also turns off the high-side/low-side
switch when the primary current approaches zero. So at t2, the high-side switch is turned
off because the primary current is close to zero. At t3 (and also at t1), the low-side switch
is turned off, although VSNSCAP did not reach the regulation level (Vls(SNSCAP)) yet. The
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primary current is measured via an external sense resistor connected to the SNSCUR
pin. The capacitive mode protection levels are Vreg(capm) (−100 mV and +100 mV,
respectively).
In this mode, the amount of output power is reduced and the output voltage decreases.
The TEA19161T does not enter a so-called "capacitive mode protection", but avoids this
mode of operation.
GATEHS
GATELS
HB
Vhs(SNSCAP)
VSNSCAP
Vls(SNSCAP)
Iprim
Vreg(capm)
0
Vreg(capm)
t0
t1
t2
t3
aaa-017772
Figure 18. Near capacitive mode switching
8.6.6 Overcurrent protection
The system measures the primary current continuously via a sense resistor connected
to the SNSCUR pin. If the measured voltage exceeds the overcurrent level (Vocp), the
corresponding switch (GATELS/GATEHS) is turned off, but the system continuous
switching. In this way, the primary current is limited to the OCP level. If the OCP level
is exceeded for 5 consecutive cycles (GATELS and/or GATEHS), the system stops
switching and enters the latched OCP protection mode. The PFC is disabled via the
SNSBOOST pin.
8.6.7 Overtemperature protection
When the internal junction temperature exceeds the Totp level, the overtemperature
protection is triggered. OTP is a latched protection which also disables the PFC.
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8.6.8 Overpower protection
VSNSCAP CONTROL
Vhs(SNSCAP)
VSNSCAP
Vopp(SNSCAP)
Vth(max)SNSCAP
burst mode
Vls(SNSCAP)
low-power mode
starting internal
counter 50/200 ms
Pt(lp)
125 %/175 %
150 %/200 %
Pout
aaa-017773
Figure 19. TEA19161T overpower
The external capacitive/resistive divider connected to the SNSCAP pin must be chosen
such that:
• The voltage difference between Vhs(SNSCAP) and Vls(SNSCAP) equals ΔVopp(SNSCAP)
• The voltage difference between Vhs(SNSCAP) and Vls(SNSCAP) occurs at 125 % of the
maximum output power or at 175 %, depending on the settings
When the ΔVSNSCAP (Vhs(SNSCAP) − Vls(SNSCAP)) exceeds the ΔVopp(SNSCAP)
voltage difference, an internal counter is started. When this counter exceeds td(opp)
(50 ms/200 ms), the system enters a latched/safe restart protection as defined by the
external settings.
The voltage difference between Vhs(SNSCAP) and Vls(SNSCAP) is also limited to
ΔVth(max)SNSCAP, which then corresponds to an output power of 150 % or 200 %,
depending on the settings (see Figure 19). If the output of the LLC converter requires
additional power, the output voltage drops as the power delivered by the LLC converter is
limited to 150 % or 200 %.
An additional option is to disable the overpower counter, using the external settings. In
this way, the overpower rating can be used as an extension of the typical power level.
8.7 External settings
Before the system starts switching, it reads the external settings. Using specific resistor
values at the GATELS, SNSSET, and SNSOUT pins, several internal settings can be
defined.
8.7.1 Burst period
Figure 20 shows how the internal regulated burst frequency can be set using the external
resistor connected to the SNSOUT pin.
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Digital controller for high-efficiency resonant power supply
SNSOUT
RSNSOUT2
RSNSOUT1
aaa-017774
Figure 20. External setting of the burst frequency
Table 5. External setting of the burst frequency
RSNSOUT1
Burst frequency
22 kΩ
200 Hz
15 kΩ
400 Hz
10 kΩ
800 Hz
6.8 kΩ
1600 Hz
The absolute value of the resistor connected between the SNSOUT pin and ground
(RSNSOUT1) defines the burst frequency. An accurate resistor of 1 % according to Table 5
is required. The OVP level can be set using resistor RSNSOUT2.
A low burst frequency is best for minimum audible noise. However, a high burst
frequency minimizes the output voltage ripple.
8.7.2 General settings
Variables on the OPP function can be set using resistor RSNSSET1 connected to the
SNSSET pin (see Figure 21).
IC
SNSSET
RSNSSET2
RSNSSET1
CSNSSET
aaa-017775
Figure 21. External setting of the SNSSET pin
Table 6. General settings
RSNSSET1 (kΩ)
Power capability
level (%)
< 10
OPP timer level
(%)
200
infinite
53.6
200
175
Product data sheet
OPP timer (ms)
Protection
190
200
1 s restart
no start-up
46.4
TEA19161T
End of power
good timer (ms)
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Digital controller for high-efficiency resonant power supply
RSNSSET1 (kΩ)
Power capability
level (%)
OPP timer level
(%)
End of power
good timer (ms)
OPP timer (ms)
Protection
61.9
200
175
45
50
1 s restart
71.5
150
125
190
200
1 s restart
82.5
150
125
45
50
1 s restart
95.3
200
175
190
200
latched
110
200
175
45
50
latched
127
150
125
190
200
latched
147
150
125
45
50
latched
When the measured value of RSNSSET1 < 10 kΩ, the system assumes a shorted pin to
ground and the start-up is inhibited. At a value of 46.4 kΩ, the system can of continuously
delivering the maximum power of 200 %.
The output power level at which the overpower timer is started can be set to 125 % or
175 %. Two corresponding timer values can be selected, 50 ms or 200 ms. Finally, the
value of RSNSSET1 (see Table 6) can set the behavior of the overpower function (either
a 1 s restart or latched). During this protection period, the SUPIC is regulated at its
Vstart(SUPIC) level.
8.7.3 Low-power mode/burst mode transition levels
To ensure the best efficiency, the system must enter the low-power mode and the burst
mode at high power levels. However, to ensure the best output ripple, these modes must
be entered at low-power levels. To choose the optimum level for a specific application,
the power transition levels at which the system enters the low-power mode and the burst
mode can be set externally.
Resistor RSNSSET2 defines the power levels at which the system enters the low-power
mode and the burst mode. Table 7 gives an overview.
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Digital controller for high-efficiency resonant power supply
Table 7. External setting of the high-power/low-power and low-power/burst transition levels
[1]
RSNSSET2
(kΩ)
High-power => low-power
[1]
(%)
Burst mode
200 Hz (%)
400 Hz (%) 800 Hz (%)
1600 Hz (%)
1
25
9
9
9
9
6.8
25
12
12
12
12
15
37.5
9
9
9
10
27
37.5
12
12
12
13
47
50
9
10
11
12
82
50
12
13
15
17
180
62.5
9
10
12
14
open
62.5
12
15
17.5
20
[1]
The values in this table are including the additional shift due to the internal (tPD(SNSCAP)) delay and a typical external delay
of 150 ns and 300 ns, respectively. When an external R + C network compensates these delays, the levels in Table 7 can
be lowered.
The power level at which the system enters the burst mode also depends on the defined
burst period. In this way, the optimum between efficiency and output voltage ripple can
be chosen.
8.8 Power good function
The TEA19161T provides a power good function via the SNSSET pin. At initialization,
the TEA19161T measures the resistors connected to the SNSSET pin to set internal
variables. After that, the pin is used for the power good function.
SUPREG
D2
Vout
SNSSET
IC
powergood
D1
aaa-017785
a. Primary side
aaa-017786
b. Secondary side
Figure 22. Power good function
After the system has read the external settings (see Figure 5), the SNSSET output is
active high, enabling an external MOSFET. A secondary power good signal can be pulled
low using an external optocoupler.
When the system enters the operating state (see Figure 5), the SNSSET output is pulled
low and the external power good signal becomes active high. Any required delay can be
achieved via an external R/C network.
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At low power good, the SNSSET output becomes active high when:
• The voltage on the SNSBOOST pin drops to below Vdet(SNSBOOST) (1.95 V)
• The OPP counter is at a value indicated in Table 6.
In this way, the secondary power good signal is pulled low at 5 ms or 10 ms before the
output is disabled.
When the system enters protection mode (OVP, OCP, UVP or OTP), it pulls low the
SNSSET pin and stops switching immediately.
8.9 PFC/LLC communication protocol
The TEA19161T is designed to cooperate with the TEA19162T (PFC) in one system. The
TEA19161T and TEA19162T can be seen as a combination, split up into two packages.
All required functionality between the two controllers is arranged via the combined SUPIC
and SNSBOOST pins.
8.9.1 Start-up
To ensure that at start-up the TEA19161T and TEA19162T are enabled at the same
time, the TEA19161T (LLC) pulls down the SNSBOOST pin to below the SNSBOOST
short protection level of the PFC. The TEA19161T disables the TEA19162T (PFC)
(see Figure 23) until the system enters the PFC start-up phase (see Figure 5 and
Figure 23).
The SUPIC start levels and stop levels of the TEA19162T (PFC) are below the SUPIC
start levels and stop levels of the TEA19161T (LLC). When the SUPIC exceeds the start
level of the TEA19161T, both controllers are enabled.
In this way, both controllers are enabled/disabled at the same SUPIC start and stop
levels.
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Digital controller for high-efficiency resonant power supply
SUPIC
PFC
LLC
Vstart(SUPIC) = 19.1 V
Vstart(hys)SUPIC = -0.7 V
Vuvp(SUPIC) = 13.2 V
Vstart(SUPIC) = 13.0 V
Vuvp(SUPIC) = 9 V
Vrst(SUPIC) = 3.5 V
t1
t2
t3
t6
Vboost
Vreg(SNSBOOST) = 2.5 V
Vstart(SNSBOOST) = 2.3 V
SNSBOOST
Vshort(SNSBOOST) = 0.4 V
td(start)
UVLO
off
t5
PFC
wait
on
t4
UVLO
LLC
SUPIC regulation
on
Vout
aaa-017789
Figure 23. Start-up of the PFC and LLC
When the LLC reaches a minimum supply voltage level (Vrst(SUPIC); t1), the LLC pulls
down the SNSBOOST pin to disable the PFC.
At t2, the SUPIC reaches the start level of the PFC converter. However, as the LLC
pulls low the SNSBOOST voltage to < the PFC short protection level, the PFC is still
off. When at t3 the SUPIC reaches the start level of the LLC, after the LLC has read
out the external settings, the SNSBOOST voltage is released. It increases because of
the connected resistive divider which is connected to the PFC boost voltage. To ensure
that the SNSBOOST voltage is a representative of the Vboost voltage before the system
actually starts to switch, an additional delay (until t4) is built into the PFC controller before
it starts.
When at t5 the SNSBOOST voltage reaches the start level of the LLC, the LLC converter
starts to switch. At t6, the SUPIC is supplied via the primary auxiliary winding.
8.9.2 Protection
When a protection is triggered in either the PFC or LLC, it may also disable the other
converter. For example, if an OVP is detected at the LLC, both converters are latched.
Also, at initial start-up, the PFC disables the LLC converter until the mains voltage
detects the brownin level.
The PFC can disable the LLC converter by pulling down the SNSBOOST pin to below
the Vuvp(SNSBOOST) level of the LLC converter. The LLC can disable the PFC converter by
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pulling down the SNSBOOST pin to below the short protection level of the PFC converter
SNSBOOST pin.
Table 4 in Section 8.6 gives an overview of protections in the LLC converter. It shows
which protections also disable the PFC.
SUPIC
PFC
LLC
Vstart(SUPIC) = 19.1 V
Vstart(hys)SUPIC = -0.7 V
Vuvp(SUPIC) = 13.2 V
Vstart(SUPIC) = 13.0 V
Vuvp(SUPIC) = 9 V
Vrst(SUPIC) = 3.5 V
t1
t2
t3
t7
mains
brownin
Vreg(SNSBOOST) = 2.5 V
Vstart(SNSBOOST) = 2.3 V
SNSBOOST
t4
Vshort(SNSBOOST) = 0.4 V
td(start)
UVP
brownout
t6
t5
UVP
PFC
on
wait
off
LLC
on
SUPIC regulation
OVP
Vout
t9
t8
SNSOUT
> 5 cycles
Vovp(SNSOUT) = 3.5 V
aaa-017791
Figure 24. System protection
The start-up period up to t3 is identical in Figure 23 and Figure 24. At t3, the LLC
converter releases the pull-down of the SNSBOOST pin. However, as the mains voltage
is below the brownin level, the PFC converter pulls low the SNSBOOST pin. When
the mains voltage exceeds the brownin level (t4), the SNSBOOST pin is released and
increases because of the resistive divider connected between the PFC boost voltage and
the SNSBOOST pin. To allow some external capacitance on the SNSBOOST pin, the
PFC converter waits until the SNSBOOST voltage is stabilized.
At t5, the PFC converter starts to switch. At t6, the LLC converter also starts to switch, as
the SNSBOOST voltage reaches the Vstart(SNSBOOST) of the LLC converter.
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
At t7, the primary auxiliary winding takes over the supply of the SUPIC pin.
At t8, the LLC detects an OVP at the SNSOUT pin. After at least 5 consecutive OVP
cycles (t9), the LLC stops switching and pulls down the SNSBOOST pin. As a result, the
PFC also stops switching.
When either the PFC or LLC is in protection, the SUPIC pin is regulated to the
Vstart(SUPIC) via the SUPHV pin as soon as it drops below the Vstart(SUPIC) level.
8.9.3 Fast latch reset
The SUPIC pin is regulated to the Vstart(SUPIC) level when a (latched) protection is
triggered. So, it can remain in this protection mode until the capacitor at the PFC output,
which the SUPHV is connected to, is discharged. Hence, it may remain in protection
mode for a long time after the mains is disconnected.
When protection modes are tested at mass-production, a long reset time is not
acceptable in most cases. So, a fast latch reset function is built into the PFC and the
LLC. When the mains is initially disconnected and then reconnected, all protections the
PFC or the LLC initiated are released again.
SUPIC
PFC
LLC
Vstart(SUPIC) = 19.1 V
Vstart(hys)SUPIC = -0.7 V
td(mains)bo
mains
brownin
brownout
t2
Vreg(SNSBOOST) = 2.5 V
Vstart(SNSBOOST) = 2.3 V
Vpu(rst)SNSBOOST = 2.0 V
Vuvp(SNSBOOST) = 1.6 V
VSNSBOOST
Vscp(stop) = 0.4 V
t1
PFC
off
td(start)
wait
brownout
on
t3
LLC
UVPSNSBOOST
protection
Vout
on
t4
aaa-017798
Figure 25. Fast latch reset
Before t1, the LLC is in a (latched) protection and pulls down the SNSBOOST pin, which
also disables the PFC.
When the mains voltage drops to below the brownout level for a minimum period of
td(mains)bo, the PFC enters the brownout protection mode. When the mains voltage
increases again to > the brownin level (t2) in the brownout protection mode, the PFC
pulls up the SNSBOOST voltage until it reaches the Vuvp(SNSBOOST) level of the LLC
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
converter. The LLC converter then releases all protection modes and waits until the
SNSBOOST pin exceeds its start level (Vstart(SNSBOOST)). After a waiting time, the PFC
converter starts (t3), followed by a start-up of the LLC converter (t4).
8.9.4 PFC burst mode
When the LLC operates in burst mode and the duty cycle of the burst is below 50 % for
at least 8 consecutive burst periods, the TEA19161T (LLC) sets the TEA19162T (PFC) in
burst mode as well. The corresponding output power level is then 50 % of the power level
at which the LLC enters the burst mode (see Table 7).
When the output power exceeds 75 % of the power level at which the LLC enters the
burst mode (see Table 7), the PFC burst is disabled again.
When the PFC burst is enabled, an additional current out of the SNSBOOST pin stops
the PFC from switching via a soft stop, so the audible noise is minimized (see Figure 26).
PFC
LLC
Ioff(burst) = 6.4 µA
GM AMPLIFIER
Ion(stop)soft = 32 µA
PFC burst mode
VSNSBOOST > 2.37 V
q s
3.23 V
soft stop
SNSBOOST
r
Voff(burst)
PFCCOMP
MAX.
VALUE
100 kΩ
2.8 V
3.8 V
RESET
100 µs
DELAY
OVP
2.63 V
aaa-021168
a. Block diagram
PFC
LLC
ON
OFF
ON
OFF
VSNSBOOST
Vdet(H)SNSBOOST = 3.23 V
Ioff(burst)
t4
Voff(burst) = -75 mV
Vdet(L)SNSBOOST = 2.8 V
Vovp(stop) = 2.63 V
Vreg(SNSBOOST) = 2.5 V
Von(burst)max = 2.37 V
t1
Vclamp(PFCCOMP) = 3.80 V
t5
t2
Vtonzero(PFCCOMP) = 3.5 V
t3
t6
VGATEPFC
aaa-021167
b. Timing diagram
Figure 26. PFC burst mode
At t1, the current out of the LLC SNSBOOST pin (Ioff(burst)) is activated and the voltage on
the SNSBOOST pin increases. When an external 100 kΩ resistor (RSNSBOOST) is used
between the SNSBOOST pin and GND pin (see Figure 27), the SNSBOOST voltage
increase is approximately 640 mV (= Ioff(burst) * RSNSBOOST). Because of this increase,
the SNSBOOST voltage is between the Vdet(L)SNSBOOST and Vdet(H)SNSBOOST levels of the
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
PFC (t2), so the soft stop of the PFC converter is started. At the end of the soft stop, the
PFC enters the energy safe state and stops switching (t3). Because of the continuous
operation of the LLC converter, even when the PFC is stopped, the PFC output capacitor
is discharged.
When the PFC boost capacitor is discharged so much that the voltage on the
SNSBOOST pin has dropped 75 mV (ΔVoff(burst); t4), the internal current source in the
LLC converter is switched off. Because of the negative voltage drop at the SNSBOOST
pin, the PFC starts switching again. When VSNSBOOST exceeds the LLC Von(burst)max level
(2.37 V) again, the internal current source is reactivated and the PFC stops switching
again (t1).
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
9
Limiting values
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VSUPHV
voltage on pin SUPHV
maximum during mains surge;not −0.4
repetitive
+700
V
VSUPHS
voltage on pin SUPHS
VHB
VHB + 14
V
VHB
voltage on pin HB
maximum during mains surge;
not repetitive
−3
+700
V
t < 1 μs
−14
-
V
Voltages
VSUPIC
voltage on pin SUPIC
−0.4
+36
V
VSUPREG
voltage on pin SUPREG
−0.4
+12
V
VGATEHS
voltage on pin GATEHS
VHB − 0.4
VSUPHS + 0.4
V
VGATELS
voltage on pin GATELS
−0.4
VSUPREG + 0.4
V
VSNSFB
voltage on pin SNSFB
−0.4
+12
V
VSNSOUT
voltage on pin SNSOUT
−0.4
+12
V
VSNSSET
voltage on pin SNSSET
−0.4
+12
V
VSNSCUR
voltage on pin SNSCUR
−0.4
+12
V
VSNSCAP
voltage on pin SNSCAP
−0.4
+12
V
VSNSBOOST
voltage on pin SNSBOOST
−0.4
+12
V
current on pin SUPHV
-
20
mA
-
0.7
W
Currents
ISUPHV
General
Ptot
total power dissipation
Tamb < 75 °C
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−40
+150
°C
−100
+100
mA
pins SUPHV, SUPHS,
GATEHS, and HB
−1000
+1000
V
other pins
−2000
+2000
V
−500
+500
V
Latch-up
Ilu
latch-up current
all pins; according to JEDEC:
Standard 78D
ElectroStatic Discharge (ESD)
VESD
electrostatic discharge voltage
human body model
charged device model; all pins
TEA19161T
Product data sheet
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Digital controller for high-efficiency resonant power supply
10 Thermal characteristics
Table 9. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
In free air; JEDEC test board
107
K/W
Rth(j-c)
thermal resistance from junction to case
In free air; JEDEC test board
60
K/W
11 Characteristics
Table 10. Characteristics
Tamb = 25 °C; VSUPIC = 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the
IC;unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ilim(SUPHV)
current limit on pin SUPHV
VSUPIC < Vrst(SUPIC)
0.5
0.75
1.0
mA
Ioff(SUPHV)
off-state current on pin SUPHV
VSUPIC = 15 V
-
0.5
0.9
μA
ΔVI(SUPHV-SUPIC)
input voltage difference
between pin SUPHV and pin
SUPIC
ISUPHV = 20 mA
-
7
-
V
SUPHV pin
SUPIC pin
Vstart(SUPIC)
start voltage on pin SUPIC
18.3
19.1
19.8
V
Vstart(hys)SUPIC
start voltage hysteresis on pin
SUPIC
-
−0.7
-
V
Vlow(hys)SUPIC
low voltage hysteresis on pin
SUPIC
-
0.9
-
V
Vlow(SUPIC)
low voltage on pin SUPIC
-
14.0
-
V
Vuvp(SUPIC)
undervoltage protection voltage
on pin SUPIC
12.7
13.2
13.7
V
Vrst(SUPIC)
reset voltage on pin SUPIC
-
3.5
-
V
ICC(SUPIC)
supply current on pin SUPIC
operating mode; fHB = 100 kHz; GATEHS/GATELS open;
ISNSFB = −85 μA;
ISNSCAP = −100 μA
5.6
-
mA
latched protection;
ISNSFB = 0 μA;
ISNSCAP = −100 μA
2.3
3.0
3.7
mA
burst mode; ISNSFB = −106 μA;
ISNSCAP = −100 μA
-
0.7
-
mA
Vuvp(SUPIC) = 13.3 V;
tracks with Vuvp(SUPIC)
SUPREG pin
Vintregd(SUPREG)
internal regulated voltage on
pin SUPREG
VSUPIC > 13.8 V;
ISUPREG = 50 mA
10.6
11.0
11.4
V
Vreg(acc)SUPREG
regulator voltage accuracy on
pin SUPREG
VSUPIC > 13.8 V;
10 μA < ISUPREG < 20 mA
−150
−100
−50
mV
Ilim(SUPREG)
current limit on pin SUPREG
VSUPIC = 19.5 V
−44
−37
−30
mA
TEA19161T
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vuvp(SUPREG)
undervoltage protection voltage
on pin SUPREG
8.6
9.0
9.4
V
-
2.50
-
V
−245
−210
−175
μA
Vhs(SNSCAP) − Vls(SNSCAP);
Pout = 200 %;
VSNSBOOST = 2.5 V
-
1.92
-
V
Vhs(SNSCAP) − Vls(SNSCAP);
Pout = 200 %;
VSNSBOOST < 2.0 V
2.85
3.00
3.15
V
Vhs(SNSCAP) − Vls(SNSCAP);
Pout = 150 %;
VSNSBOOST = 2.5 V
-
1.44
-
V
Vhs(SNSCAP) − Vls(SNSCAP);
Pout = 150 %;
VSNSBOOST = 2.1 V
-
2.24
-
V
from crossing
Vls(SNSCAP)/Vhs(SNSCAP) level to
GATELS/GATEHS switch-off
-
150
-
ns
40
50
60
ms
160
170
180
ms
restart delay time
0.8
1.0
1.2
s
Vbias(SNSCUR)
bias voltage on pin SNSCUR
2.4
2.5
2.6
V
RO(SNSCUR)
output resistance on pin
SNSCUR
-
60
-
kΩ
Vocp
overcurrent protection voltage
positive level;
VSNSCUR − Vbias(SNSCUR)
1.35
1.50
1.65
V
negative level;
VSNSCUR − Vbias(SNSCUR)
−1.65
−1.50
−1.35
V
positive level;
VSNSCUR − Vbias(SNSCUR)
85
100
115
mV
negative level;
VSNSCUR − Vbias(SNSCUR)
−115
−100
−85
mV
detected as ≥ 0
-
−13
-
mV
detected as ≤ 0
-
13
-
mV
SNSCAP pin
VAV(regd)SNSCAP
regulated average voltage on
pin SNSCAP
Ibias(max)SNSCAP
maximum bias current on pin
SNSCAP
ΔVth(max)SNSCAP
maximum threshold voltage
difference on pin SNSCAP
regulated average of
Vhs(SNSCAP) and Vls(SNSCAP)
Overpower protection
ΔVopp(SNSCAP)
overpower protection voltage
difference on pin SNSCAP
tPD(SNSCAP)
propagation delay on pin
SNSCAP
td(opp)
overpower protection delay time See Table 6 for related
RSNSSET1
See Table 6 for related
RSNSSET1
td(restart)
SNSCUR pin
Vreg(capm)
Vdet(zero)
TEA19161T
Product data sheet
capacitive mode regulation
voltage
zero detection voltage
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SNSBOOST pin
Vstart(SNSBOOST)
start voltage on pin
SNSBOOST
2.2
2.3
2.4
V
Vuvp(SNSBOOST)
undervoltage protection voltage
on pin SNSBOOST
1.5
1.6
1.7
V
Vdet(SNSBOOST)
detection voltage on pin
SNSBOOST
when below power good = LOW 1.8
1.95
2.1
V
%
PFC burst mode controller
δen(burst)
burst mode enable duty cycle
enable of PFC burst mode; duty cycle of LLC burst mode
50
-
Ncy(en)burst
burst mode enable number of
cycles
enable of PFC burst mode;
cycles of LLC burst mode
-
8
-
δdis(burst)
burst mode disable duty cycle
disable of PFC burst mode;
duty cycle of LLC burst mode
-
75
-
%
Vpu(SNSBOOST)
pull-up voltage on pin
SNSBOOST
to enter PFC burst mode offstate
-
2.95
-
V
Ioff(burst)
burst mode off-state current
during PFC burst mode offstate
−7.1
−6.4
−5.7
μA
ΔVoff(burst)
burst mode off-state voltage
difference
during PFC burst mode offstate; between peak voltage
and end of off-state
-
−75
-
mV
Von(burst)max
maximum burst mode on-state
voltage
during PFC burst mode onstate
2.29
2.37
2.45
V
tto(det)on(burst)
burst mode on-state detection
time-out time
during PFC burst mode onstate
3.7
4.0
4.3
ms
PFC protection controller
Rpd(SNSBOOST)
pull-down resistance on pin
SNSBOOST
at protection activation
-
550
-
Ω
Ipd(SNSBOOST)
pull-down current on pin
SNSBOOST
during active protection
94
110
127
μA
Iprot(SNSBOOST)
protection current on pin
SNSBOOST
-
60
-
nA
Vovp(SNSOUT)
overvoltage protection voltage
on pin SNSOUT
3.36
3.50
3.64
V
Iprot(SNSOUT)
protection current on pin
SNSOUT
for open pin
-
−60
-
nA
bias voltage on pin SNSFB
ISNSFB = −85 μA
2.2
2.5
2.8
V
Ireg(SNSFB)
regulation current on pin
SNSFB
Istart(burst) = 106 μA;
tracks with Istart(burst)
-
−85
-
μA
Ireg(max)SNSFB
maximum regulation current on
pin SNSFB
Istart(burst) = 106 μA;
tracks with Istart(burst)
-
−310
-
μA
SNSOUT pin
SNSFB pin
Vbias(SNSFB)
Optobias regulator
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ireg(min)SNSFB
minimum regulation current on
pin SNSFB
Istart(burst) = 106 μA;
tracks with Istart(burst)
-
−63
-
μA
Istart(burst)
burst mode start current
LLC burst mode
−123
−106
−89
μA
Istop(burst)
burst mode stop current
LLC burst mode
-
−200
-
μA
Burst mode regulator
GATELS and GATEHS pins
Isource(GATEHS)
source current on pin GATEHS
VGATEHS − VHB = 4 V
-
−340
-
mA
Isource(GATELS)
source current on pin GATELS
VGATELS − VGND = 4 V
-
−340
-
mA
Isink(GATEHS)
sink current on pin GATEHS
VGATEHS − VHB = 2 V
-
580
-
mA
VGATEHS − VHB = 11 V
-
2
-
A
VGATELS − VGND = 2 V
-
580
-
mA
VGATELS − VGND = 11 V
-
2
-
A
6.4
7
7.6
V
-
0.6
-
V
Isink(GATELS)
sink current on pin GATELS
Vrst(SUPHS)
reset voltage on pin SUPHS
Vrst(hys)SUPHS
hysteresis of reset voltage on
pin SUPHS
ton(min)
minimum on-time
-
0.83
-
μs
ton(max)
maximum on-time
14.8
17.4
20.0
μs
tsweep
sweep time
1
12
14
ms
20
23
26
kHz
RSNSOUT1 = 22 kΩ
170
200
230
Hz
RSNSOUT1 = 15 kΩ
340
400
460
Hz
RSNSOUT1 = 10 kΩ
680
800
920
Hz
RSNSOUT1 = 6.8 kΩ
1360
1600
1840
Hz
> Vrst(SUPHS)
frequency; at start-up
Low-power mode regulator
flp(min)
minimum low-power mode
frequency
Burst mode regulator
fburst(max)
maximum burst mode
frequency
Power good characteristics (pin SNSSET)
VOH(SNSSET)
HIGH-level output voltage on
pin SNSSET
ISNSSET = −100 μA;
power good = LOW
-
4
-
V
IOH(SNSSET)
HIGH-level output current on
pin SNSSET
VSNSSET = 3 V;
power good = LOW
−11
−8
−5
mA
IOL(SNSSET)
LOW-level output current on pin VSNSSET = 0.5 V;
SNSSET
power good = HIGH
8
11
14
mA
td(H)SNSSET
HIGH-level delay time on pin
SNSSET
See Table 6 for related
RSNSSET1
35
45
55
ms
See Table 6 for related
RSNSSET1
150
190
230
ms
Settings sensor (SNSOUT, SNSSET, and GATELS pins)
IO(SNSOUT)
output current on pin SNSOUT
during RSNSOUT1 measurement
-
−171
-
μA
IO(SNSSET)
output current on pin SNSSET
during RSNSSET measurement
-
−26.8
-
μA
TEA19161T
Product data sheet
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Rev. 2 — 30 August 2019
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ΔVO(GATELS-SUPREG)
output voltage difference
between pin GATELS and pin
SUPREG
during RGATELS measurement
-
1.25
-
V
HB pin
(dV/dt)tno(min)
minimum non-overlap time rate
of change of voltage
-
-
120
V/μs
tno(min)
minimum non-overlap time
-
200
-
ns
tno(max)
maximum non-overlap time
-
1.1
-
μs
130
140
150
°C
Overtemperature protection
Totp
overtemperature protection trip
12 Application information
Vboost
DSUPHS
RSUPHV
CSUPREG
CSUPHS
SUPREG
SUPHS
SUPHV
GATEHS
S2
D2
Vout
Ls
HB
power good
Lm
SNSBOOST
GATELS
S1
D1
SNSCAP
IC
SUPREG
SNSCUR
Cr
SUPIC
SNSSET
CSUPIC
SNSOUT
GND
SNSFB
aaa-017821
Figure 27. TEA19161T application diagram
TEA19161T
Product data sheet
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TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
13 Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
w M
bp
0
2.5
detail X
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.05
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
0.244
0.041
0.228
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Figure 28. Package outline SOT109-1 (SO16)
TEA19161T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 30 August 2019
© NXP B.V. 2019. All rights reserved.
39 / 43
TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
14 Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TEA19161T v.2
20190830
Product data sheet
-
TEA19161T v.1
Modifications:
• Changes have been made throughout the data sheet.
TEA19161T v.1
20160310
TEA19161T
Product data sheet
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 30 August 2019
-
© NXP B.V. 2019. All rights reserved.
40 / 43
TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
15 Legal information
15.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
TEA19161T
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 30 August 2019
© NXP B.V. 2019. All rights reserved.
41 / 43
TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Security — While NXP Semiconductors has implemented advanced
security features, all products may be subject to unidentified vulnerabilities.
Customers are responsible for the design and operation of their applications
and products to reduce the effect of these vulnerabilities on customer’s
applications and products, and NXP Semiconductors accepts no liability for
any vulnerability that is discovered. Customers should implement appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
TEA19161T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 30 August 2019
© NXP B.V. 2019. All rights reserved.
42 / 43
TEA19161T/2
NXP Semiconductors
Digital controller for high-efficiency resonant power supply
Contents
1
2
2.1
2.2
2.3
3
4
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.2
8.1.3
8.2
8.3
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.4.3
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.7
8.7.1
8.7.2
8.7.3
8.8
8.9
8.9.1
8.9.2
8.9.3
8.9.4
9
10
11
12
13
14
15
General description ............................................ 1
Features and benefits .........................................2
Distinctive features ............................................ 2
Green features ...................................................2
Protection features .............................................2
Applications .........................................................2
Ordering information .......................................... 3
Marking .................................................................3
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 4
Functional description ........................................5
Supply voltages ................................................. 5
Start-up and supply voltage ...............................5
Regulated supply (SUPREG pin) .......................7
High-side driver floating supply (SUPHS pin) .... 8
System start-up ................................................. 8
LLC system regulation .......................................9
Output power regulation loop .......................... 11
Output voltage start-up .................................... 12
Modes of operation ..........................................13
High-power mode ............................................ 14
Low-power mode ............................................. 15
Burst mode ...................................................... 18
Optobias regulation ..........................................19
Protections ....................................................... 20
Undervoltage protection SUPIC/SUPREG .......21
Undervoltage protection SUPHS ..................... 21
Undervoltage protection boost .........................21
Overvoltage protection .....................................21
Capacitive Mode Regulation (CMR) ................ 21
Overcurrent protection ..................................... 22
Overtemperature protection ............................. 22
Overpower protection ...................................... 23
External settings .............................................. 23
Burst period ..................................................... 23
General settings .............................................. 24
Low-power mode/burst mode transition
levels ................................................................25
Power good function ........................................26
PFC/LLC communication protocol ................... 27
Start-up ............................................................ 27
Protection .........................................................28
Fast latch reset ................................................30
PFC burst mode .............................................. 31
Limiting values .................................................. 33
Thermal characteristics ....................................34
Characteristics .................................................. 34
Application information .................................... 38
Package outline .................................................39
Revision history ................................................ 40
Legal information .............................................. 41
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 August 2019
Document identifier: TEA19161T
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