NXP TEA1999TS GreenChip synchronous rectifier controller User Guide

NXP TEA1999TS GreenChip synchronous rectifier controller User Guide

UM11119

TEA1999DB1546 synchronous rectifier controller demo board Rev. 1 — 12 September 2018 User manual

Document information Information Content

Keywords TEA1999DB1546,TEA1999TS flyback converter, Synchronous Rectifier (SR) driver, TSOP6, high efficiency, power supply, demo board Abstract This user manual describes the TEA1999DB1546 demo board. The TEA1999DB1546 demo board can be connected to a flyback converter.

The TEA1999DB1546 demo board contains a TEA1999TS SR controller in a TSOP6 package.

Additionally, the TEA1999DB1546 demo board contains two possible options to place power MOSFETs. It replaces the secondary rectification part of the flyback converter.

NXP Semiconductors Revision history Rev Date

v.1

20180912

Description

first issue

UM11119 TEA1999DB1546 synchronous rectifier controller demo board

UM11119

User manual

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Rev. 1 — 12 September 2018

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NXP Semiconductors UM11119 TEA1999DB1546 synchronous rectifier controller demo board

1 Introduction

Warning The non-insulated high voltages that are present when operating this product, constitute a risk of electric shock, personal injury, death and/or ignition of fire.

This product is intended for evaluation purposes only. It shall be operated in a designated test area by personnel qualified according to local requirements and labor laws to work with non-insulated mains voltages and high-voltage circuits. This product shall never be operated unattended.

This document describes the TEA1999DB1546 demo board. A functional description is provided, including instructions about how to connect the board, for the best results and performance. The TEA1999DB1546 demo board contains the secondary part of a single output flyback converter, excluding the output capacitors and the feedback control hardware. To use the TEA1999DB1546 demo board correctly, a flyback converter board in which the demo board can replace the secondary rectifier part is required.

2 Safety warning

The board application is AC mains voltage powered. Avoid touching the board while it is connected to the mains voltage and when it is in operation. An isolated housing is obligatory when used in uncontrolled, non-laboratory environments. Galvanic isolation from the mains phase using a fixed or variable transformer is always recommended.

Figure 1 shows the symbols on how to recognize these devices.

019aab173

a. Isolated

Figure 1. Isolation symbols

b. Not isolated

3 Specifications

Table 1. TEA1999DB1546 specifications Symbol Parameter

V XV voltage on pin XV V DRAIN voltage on pin DRAIN

Value

−0.4 V to +12 V −0.4 V to +26 V −0.8 V to +60 V −0.8 V to +120 V V SOURCE P i(noload) voltage on pin SOURCE no-load input power 1 mW to 1.5 mW

019aab174

Conditions

MOSFET = 60 V MOSFET = 100 V MOSFET = 60 V MOSFET = 100 V −0.4 V to +0.4 V V XV = 5 V UM11119

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4 TEA1999TS SR controller

The TEA1999TS is a dedicated controller IC for synchronous rectification on the secondary side of flyback converters. It incorporates the sensing stage and driver stages for driving the SR MOSFET. The SR MOSFET rectifies the output of the secondary transformer winding.

The TEA1999TS can generate its own supply voltage for battery charging applications with low output voltage or for applications with high-side rectification.

• • •

The TEA1999TS can be used in all power supplies that require a high efficiency, like: Chargers Adapters Flyback power supplies with very low and/or variable output voltages

4.1 Features • • • • • • •

Operates in an output voltage range between 26 V and 0 V Drain sense pin capable of handling input voltages up to 120 V Self-supply function Operates with standard and logic level SR MOSFETs Supports USB BC, QuickCharge, and smart charging applications Adaptive gate drive for fast turn-off at the end of conduction Under Voltage Lockout (UVLO) with active gate pull-down

4.2 Pinning

CAP 1 GND 2

IC

6 DRAIN 5 SOURCE XV 3

aaa-021171

Figure 2. TEA1999TS pin configuration (SOT457)

4 GATE UM11119

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5 Board photographs

UM11119 TEA1999DB1546 synchronous rectifier controller demo board

a. Front view

Figure 3. TEA1999DB1546 demo board photographs

b. Back view Keep the board clean after soldering. For no_clean fluxes, keep the board under pollution degree 1 board conditions (IEC 60065).

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6 Board connections

6.1 Connections for low-side SR

Connect SOURCE demoboard to SOURCE motherboard Connect XV to Vout motherboard WWW.NXP.COM

SOURCE Remove JP2 VCC JP1 SECONDARY CONTROLLER OPTO XV DRAIN GATE SOURCE

TEA1999

CAP GND GND C3 DRAIN C1 C2 D1 TEA1999 DB1546 Connect DRAIN demoboard to DRAIN motherboard Remove JP1

aaa-030794 aaa-030795

a. TEA1999TS default application

Figure 4. Connections for low-side SR

b. TEA1999DB1546 demo board application

Figure 4 (a) shows the default TEA1999TS application for low-side SR. The drain, gate,

and source connection of the TEA1999TS can be coupled directly to the corresponding pins of the MOSFET. Put small, 0 Ω resistors in the drain and gate tracks. To reduce high gate current spikes, the resistor in the gate track can be modified (maximum: 10 Ω). The resistor in the drain track can protect this track from being damaged during

pin short conditions. Normally, a snubber provision, like R3/C3 in Figure 4

(b), is also recommended.

Figure 4 (b) shows how to connect the TEA1999DB1546 demo board to an existing

application. First, remove the original rectifier circuit in the existing application. The original rectifier circuit consists of either a diode or the combination of an SR controller and a MOSFET. Then, connect the DRAIN, SOURCE, and XV pins of the demo board to the drain, source, and V out connections of the main application with short wires. Also, remove the JP1 and JP2 jumpers. This way, the SR controller functions in a correct way for output voltages up to 12 V and the circuit can be evaluated. For output voltages higher than 12 V (up to 26 V), replace MOSFET Q1 (60 V version) on the demo board with a more robust MOSFET (100 V version).

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NXP Semiconductors UM11119 TEA1999DB1546 synchronous rectifier controller demo board 6.2 Connections for high-side SR with self-supply

Connect SOURCE demoboard to SOURCE motherboard WWW.NXP.COM

SOURCE XV DRAIN GATE SOURCE

TEA1999

CAP JP1 GND XV SECONDARY CONTROLLER GND OPTO C3 DRAIN C1 C2 D1 TEA1999 DB1546 Connect DRAIN demoboard to DRAIN motherboard Remove JP1

aaa-030796

a. TEA1999TS default application

Figure 5. Connections for high-side SR with self-supply

b. TEA1999DB1546 demo board application Mount JP2

aaa-030797

Figure 5 (a) shows the default TEA1999TS application for high-side SR. The drain, gate,

and source connection of the TEA1999TS can be coupled directly to the corresponding pins of the MOSFET. Put small, 0 Ω resistors in the drain and gate tracks. To reduce high gate current spikes, the resistor in the gate track can be modified (maximum: 10 Ω). The resistor in the drain track can protect this track from being damaged during

pin short conditions. Normally, a snubber provision, like R3/C3 in Figure 5

(b), is also recommended.

Figure 5 (b) shows how to connect the TEA1999DB1546 demo board to an existing

application. First, remove the original rectifier circuit in the existing application. The original rectifier circuit consists of either a diode or the combination of an SR controller and a MOSFET. Then, connect The DRAIN and SOURCE pins of the demo board to the drain and source connections of the main application with short wires. Remove jumper JP1 and mount jumper JP2. This way, the XV pin is connected to the GND pin and the CAP voltage is charged to a level of approximately 9.8 V. The SR controller functions in a correct way for output voltages up to 12 V and the circuit can be evaluated. For output voltages higher than 12 V (up to 26 V), replace MOSFET Q1 (60 V version) on the demo board with a more robust MOSFET (100 V version).

UM11119

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Rev. 1 — 12 September 2018

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NXP Semiconductors UM11119 TEA1999DB1546 synchronous rectifier controller demo board

7 Schematic

C3 10 nF 50 V n.m.

R3 10 Ω n.m.

DRAIN SOURCE E2 AWG12 DRAIN Q2 PSMN4R3-100PS n.m.

Q1 BUK9Y4R8-60E R1 0 Ω DRAIN U1 6 SOURCE 5

TEA1999TS

GATE 4 1 2 3 CAP GND XV R2 0 Ω n.m.

C1 100 pF 50 V CAP XV C2 100 nF 50 V E4 AWG18 SE connect wire to SR supply for high side mode D1 BAS316 E1 AWG18 XV connect wire to VOUT for low side mode JP1 22-28-4020 MCL1 CAB 9 GS jumper; black; 2.54 mm with handle CAB 9 GS JP2 22-28-4020 MCL2 CAB 9 GS jumper; black; 2.54 mm with handle CAB 9 GS E3 AWG12 SOURCE

Figure 6. TEA1999DB1546 schematic diagram

aaa-030798

• •

Figure 6 shows the schematic diagram of the TEA1999DB1546 demo board. The board

incorporates the TEA1999TS controller and a 60 V logic-level power MOSFET. To facilitate easy connection for low-side, high-side, or self-supply applications, some adjustments have been made to the board: By default, a 60 V logic level MOSFET is mounted. For applications with an output voltage > 12 V, use a MOSFET type with a higher V approximately 5 * V out ) ds capability (use a rating of By default, jumpers JP1 and JP2 are not mounted (only to be used for high-side applications) By default, the LFPAK MOSFET Q1 is mounted with a 0 Ω gate resistor (R1). It is also possible to mount a TO220 MOSFET Q2 with gate resistor R2. Capacitors C1 and C2 are decoupling capacitors for the V CC of the TEA1999TS. Connect these capacitors close to the IC.

To ensure sufficient charge power to drive the external MOSFET during the secondary stroke, a value of 100 nF is used for capacitor C2. When a MOSFET with a higher value, which requires much more gate charge, is used, it can be necessary to increase this value for stable operation. To prevent unwanted oscillation of the V CC supply, capacitor C1 is added.

A provision is made for snubber R3/C3. The components are not mounted. However, if high-voltage spikes occur on the drain-source connections of the MOSFETs, they can be added.

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NXP Semiconductors UM11119 TEA1999DB1546 synchronous rectifier controller demo board

8 Bill Of Materials (BOM)

Q1 Q2 R1 R2 R3 U1

Table 2. TEA1999DB1546 demo board bill of materials Reference Description and values

C1 capacitor; 100 pF; 10 %; 50 V; C0G; 0805 C2 C3 capacitor; 100 nF; 10 %; 50 V; X7R; 0805 capacitor; not mounted; 10 nF; 10 %; 100 V; X7R; 0805 D1 E1; E4 E2; E3 JP1; JP2 diode; 100 V; 250 mA wire hole; AWG18; 1 mm wire hole; AWG12; 2 mm header; straight; 1 x 2-way; 2.54 mm MCL1; MCL2 jumper; P = 2.54 mm; without handle synchronous rectifier controller; TEA1999TS -

Part number

BAS316 22-28-4020 CAB 9 GS MOSFET-N; 60 V; 100 A MOSFET-N; not mounted; 100 V; 120 A resistor; 0 Ω; jumper; 63 mW; 0603 resistor; not mounted; 0 Ω; jumper; 63 mW; 0603 resistor; not mounted; 10 Ω; 1 %; 100 mW; 0805 BUK9Y4R8-60E PSMN4R3-100PS TEA1999TS -

Manufacturer

NXP Semiconductors Molex FISCHER NXP Semiconductors NXP Semiconductors NXP Semiconductors UM11119

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9 Layout

UM11119 TEA1999DB1546 synchronous rectifier controller demo board

a. Front view

Figure 7. TEA1999DB1546 demo board layout

b. Back view

• • • • •

Some important guidelines for a good layout: Keep the trace from the DRAIN pin to the MOSFET drain as short as possible.

Keep the trace from the SOURCE pin to the MOSFET source as short as possible.

Keep the area of the loop from the DRAIN pin to the MOSFET drain, to the MOSFET source, and to the SOURCE pin as small as possible. Ensure that the overlap of this loop over the power drain track or the power source track is as small as possible. Take care that the two loops do not cross each other.

Keep the track from the GATE pin to the gate of the MOSFET as short as possible.

Use separate clean tracks for the XV and the GND pins. If possible, use a small ground plane underneath the IC, which improves the heat dispersion.

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10 Abbreviations

Table 3. Abbreviations Acronym Description

CCM continuous conduction mode MOSFET SR UVLO metal-oxide-semiconductor field-effect transistor synchronous rectifier undervoltage lockout IC USB BC integrated circuit universal serial bus battery charging UM11119

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11 Legal information

11.1 Definitions Draft

— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

11.2 Disclaimers Limited warranty and liability

— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes

to the publication hereof.

— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior

Suitability for use

— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications

— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Export control

— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Evaluation products

— This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose.

Translations

— A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

Security

— While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities.

Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.

11.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

GreenChip

— is a trademark of NXP B.V.

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7

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1 2 3

4

4.1

4.2

5

6

6.1

6.2

Contents

Introduction ......................................................... 3 Safety warning .................................................... 3 Specifications ......................................................3

TEA1999TS SR controller ...................................4

Features .............................................................4

Pinning ...............................................................4

Board photographs .............................................5

Board connections ..............................................6

Connections for low-side SR ............................. 6

Connections for high-side SR with self supply .................................................................7

Schematic ............................................................ 8

Bill Of Materials (BOM) .......................................9

Layout .................................................................10

Abbreviations .................................................... 11

Legal information ..............................................12

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.

© NXP B.V. 2018.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 12 September 2018 Document identifier: UM11119

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